diff --git a/.github/lockdown.yml b/.github/lockdown.yml deleted file mode 100644 index e0ef8504c11714fce9e0aee9bf577097853acae9..0000000000000000000000000000000000000000 --- a/.github/lockdown.yml +++ /dev/null @@ -1,8 +0,0 @@ -# Configuration for Repo Lockdown - https://github.com/dessant/repo-lockdown - -skipCreatedBefore: "2020-03-21" - -pulls: - comment: > - This repository does not accept pull requests. - Please follow http://llvm.org/docs/Contributing.html#how-to-submit-a-patch for contribution to LLVM. diff --git a/.github/workflows/repo-lockdown.yml b/.github/workflows/repo-lockdown.yml new file mode 100644 index 0000000000000000000000000000000000000000..af2e635930d40fc83a73aee19900e85783ee4eb7 --- /dev/null +++ b/.github/workflows/repo-lockdown.yml @@ -0,0 +1,18 @@ +name: 'Repo Lockdown' +on: + pull_request_target: + types: opened + +permissions: + pull-requests: write + +jobs: + action: + runs-on: ubuntu-latest + steps: + - uses: dessant/repo-lockdown@v2 + with: + process-only: 'prs' + pr-comment: > + This repository does not accept pull requests. + Please follow http://llvm.org/docs/Contributing.html#how-to-submit-a-patch for contribution to LLVM. diff --git a/clang/docs/Block-ABI-Apple.rst b/clang/docs/Block-ABI-Apple.rst index 4f98b3ba65386b2b3a6e5e7b470e589b6e78a5aa..9983f26a62403ae03d0558aaa197545beb27f82f 100644 --- a/clang/docs/Block-ABI-Apple.rst +++ b/clang/docs/Block-ABI-Apple.rst @@ -765,7 +765,7 @@ The compiler would synthesize: printf("%d\n", _block->foo.value()); } - void __block_literal_10(struct __block_literal_10 *dst, struct __block_literal_10 *src) { + void __block_copy_10(struct __block_literal_10 *dst, struct __block_literal_10 *src) { FOO_ctor(&dst->foo, &src->foo); } diff --git a/clang/docs/tools/clang-formatted-files.txt b/clang/docs/tools/clang-formatted-files.txt index 1b09cc64dae5d6ed206c8be55228ae320f297fa9..45451c9090b50d02cbb0201c0718d911be5335da 100644 --- a/clang/docs/tools/clang-formatted-files.txt +++ b/clang/docs/tools/clang-formatted-files.txt @@ -4745,7 +4745,6 @@ llvm/include/llvm/IR/ReplaceConstant.h llvm/include/llvm/IR/StructuralHash.h llvm/include/llvm/IR/TrackingMDRef.h llvm/include/llvm/IR/UseListOrder.h -llvm/include/llvm/LTO/Caching.h llvm/include/llvm/LTO/SummaryBasedOptimizations.h llvm/include/llvm/MC/MCAsmInfoCOFF.h llvm/include/llvm/MC/MCAsmInfoDarwin.h @@ -4852,6 +4851,7 @@ llvm/include/llvm/Support/BinaryStreamRef.h llvm/include/llvm/Support/BinaryStreamWriter.h llvm/include/llvm/Support/BuryPointer.h llvm/include/llvm/Support/CachePruning.h +llvm/include/llvm/Support/Caching.h llvm/include/llvm/Support/CFGDiff.h llvm/include/llvm/Support/CFGUpdate.h llvm/include/llvm/Support/CodeGenCoverage.h diff --git a/clang/include/clang/Basic/CodeGenOptions.def b/clang/include/clang/Basic/CodeGenOptions.def index 520487325d6e09a487d9b6f42d7831a15e04ff37..61012326017557d7f9af4444ba1694cb1e7beab4 100644 --- a/clang/include/clang/Basic/CodeGenOptions.def +++ b/clang/include/clang/Basic/CodeGenOptions.def @@ -64,7 +64,7 @@ CODEGENOPT(DisableLifetimeMarkers, 1, 0) ///< Don't emit any lifetime markers CODEGENOPT(DisableO0ImplyOptNone , 1, 0) ///< Don't annonate function with optnone at O0 CODEGENOPT(ExperimentalStrictFloatingPoint, 1, 0) ///< Enables the new, experimental ///< strict floating point. -CODEGENOPT(DisableNoundefAttrs, 1, 0) ///< Disable emitting `noundef` attributes on IR call arguments and return values +CODEGENOPT(EnableNoundefAttrs, 1, 0) ///< Enable emitting `noundef` attributes on IR call arguments and return values CODEGENOPT(LegacyPassManager, 1, 0) ///< Use the legacy pass manager. CODEGENOPT(DebugPassManager, 1, 0) ///< Prints debug information for the new ///< pass manager. diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 2c5aa94e101f630817b925174f5de05143042057..9ff4867e6c29c2d8f693346a92c475f231ed73db 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -5319,9 +5319,9 @@ def disable_free : Flag<["-"], "disable-free">, def clear_ast_before_backend : Flag<["-"], "clear-ast-before-backend">, HelpText<"Clear the Clang AST before running backend code generation">, MarshallingInfoFlag>; -def disable_noundef_analysis : Flag<["-"], "disable-noundef-analysis">, Group, - HelpText<"Disable analyzing function argument and return types for mandatory definedness">, - MarshallingInfoFlag>; +def enable_noundef_analysis : Flag<["-"], "enable-noundef-analysis">, Group, + HelpText<"Enable analyzing function argument and return types for mandatory definedness">, + MarshallingInfoFlag>; def discard_value_names : Flag<["-"], "discard-value-names">, HelpText<"Discard value names in LLVM IR">, MarshallingInfoFlag>; diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp index 986c9e8104e9dcb85dc7d10b942c20bb27efd620..ff76ef1d9dd882226eba622eaebc7b1ba2f8797e 100644 --- a/clang/lib/CodeGen/BackendUtil.cpp +++ b/clang/lib/CodeGen/BackendUtil.cpp @@ -1561,7 +1561,7 @@ static void runThinLTOBackend( return; auto AddStream = [&](size_t Task) { - return std::make_unique(std::move(OS)); + return std::make_unique(std::move(OS)); }; lto::Config Conf; if (CGOpts.SaveTempsFilePrefix != "") { diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index c3b87398c49719addd41b63b78264fdbeafd52ae..daea09be3e70b7e5918fd0d4db02b5ba6f113d7e 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -2255,7 +2255,7 @@ void CodeGenModule::ConstructAttributeList( getLangOpts().Sanitize.has(SanitizerKind::Return); // Determine if the return type could be partially undef - if (!CodeGenOpts.DisableNoundefAttrs && HasStrictReturn) { + if (CodeGenOpts.EnableNoundefAttrs && HasStrictReturn) { if (!RetTy->isVoidType() && RetAI.getKind() != ABIArgInfo::Indirect && DetermineNoUndef(RetTy, getTypes(), DL, RetAI)) RetAttrs.addAttribute(llvm::Attribute::NoUndef); @@ -2390,7 +2390,7 @@ void CodeGenModule::ConstructAttributeList( // Decide whether the argument we're handling could be partially undef bool ArgNoUndef = DetermineNoUndef(ParamType, getTypes(), DL, AI); - if (!CodeGenOpts.DisableNoundefAttrs && ArgNoUndef) + if (CodeGenOpts.EnableNoundefAttrs && ArgNoUndef) Attrs.addAttribute(llvm::Attribute::NoUndef); // 'restrict' -> 'noalias' is done in EmitFunctionProlog when we diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp index fc299e1ee913ebf9b652ef22ba0ee2919cfbd70a..b4401548ce54568dd1f9ef7f1c330f8c06d26731 100644 --- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp +++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp @@ -41,7 +41,8 @@ static bool getArchFeatures(const Driver &D, StringRef Arch, return false; } - (*ISAInfo)->toFeatures(Args, Features); + (*ISAInfo)->toFeatures( + Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); }); return true; } diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index b5a557e458223b2179931bcffe2b4002037a2372..c5f35ae089f6c29e580179178577e2acd67810ca 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -4696,6 +4696,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, // cleanup. if (!C.isForDiagnostics()) CmdArgs.push_back("-disable-free"); + CmdArgs.push_back("-clear-ast-before-backend"); #ifdef NDEBUG const bool IsAssertBuild = false; @@ -5133,9 +5134,9 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, } // Enable -mconstructor-aliases except on darwin, where we have to work around - // a linker bug (see ), and CUDA/AMDGPU device code, - // where aliases aren't supported. - if (!RawTriple.isOSDarwin() && !RawTriple.isNVPTX() && !RawTriple.isAMDGPU()) + // a linker bug (see ), and CUDA device code, where + // aliases aren't supported. + if (!RawTriple.isOSDarwin() && !RawTriple.isNVPTX()) CmdArgs.push_back("-mconstructor-aliases"); // Darwin's kernel doesn't support guard variables; just die if we diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index 54fbc6e4bac050660dbbf6ceb2462326745e4e22..ef1743b8645691229bd34494d05e3b0558d83512 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -454,6 +454,8 @@ static bool FixupInvocation(CompilerInvocation &Invocation, CodeGenOpts.XRayAlwaysEmitTypedEvents = LangOpts.XRayAlwaysEmitTypedEvents; CodeGenOpts.DisableFree = FrontendOpts.DisableFree; FrontendOpts.GenerateGlobalModuleIndex = FrontendOpts.UseGlobalModuleIndex; + if (FrontendOpts.ShowStats) + CodeGenOpts.ClearASTBeforeBackend = false; LangOpts.SanitizeCoverage = CodeGenOpts.hasSanitizeCoverage(); LangOpts.ForceEmitVTables = CodeGenOpts.ForceEmitVTables; LangOpts.SpeculativeLoadHardening = CodeGenOpts.SpeculativeLoadHardening; diff --git a/clang/lib/Interpreter/Interpreter.cpp b/clang/lib/Interpreter/Interpreter.cpp index 02b3025297b6718215a5d2ce8cbc0e524e5753ea..d14940d2e1321cff0cf6ba3cb9787884cbc05483 100644 --- a/clang/lib/Interpreter/Interpreter.cpp +++ b/clang/lib/Interpreter/Interpreter.cpp @@ -113,6 +113,10 @@ CreateCI(const llvm::opt::ArgStringList &Argv) { Clang->getTarget().adjust(Clang->getDiagnostics(), Clang->getLangOpts()); + // Don't clear the AST before backend codegen since we do codegen multiple + // times, reusing the same AST. + Clang->getCodeGenOpts().ClearASTBeforeBackend = false; + return std::move(Clang); } diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index 6b091364c911f3e63ca07752a32a33943a9f4f4c..0f3f50c8f6c6f8dd77f5df655efa0ed81b74dbf1 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -1967,10 +1967,10 @@ Sema::BuildCXXNew(SourceRange Range, bool UseGlobal, if (Deduced && isa(Deduced)) { if (ArraySize) return ExprError( - Diag(ArraySize ? (*ArraySize)->getExprLoc() : TypeRange.getBegin(), + Diag(*ArraySize ? (*ArraySize)->getExprLoc() : TypeRange.getBegin(), diag::err_deduced_class_template_compound_type) << /*array*/ 2 - << (ArraySize ? (*ArraySize)->getSourceRange() : TypeRange)); + << (*ArraySize ? (*ArraySize)->getSourceRange() : TypeRange)); InitializedEntity Entity = InitializedEntity::InitializeNew(StartLoc, AllocType); diff --git a/clang/lib/Sema/SemaSYCL.cpp b/clang/lib/Sema/SemaSYCL.cpp index 481725eb0924eb0c6c8a4d3bf26ead06e14345b6..815463307ecc7003a70b5ab8a2f059b00653080c 100644 --- a/clang/lib/Sema/SemaSYCL.cpp +++ b/clang/lib/Sema/SemaSYCL.cpp @@ -38,7 +38,7 @@ bool Sema::checkSYCLDeviceFunction(SourceLocation Loc, FunctionDecl *Callee) { "Should only be called during SYCL compilation"); assert(Callee && "Callee may not be null."); - // Errors in unevaluated context don't need to be generated, + // Errors in an unevaluated context don't need to be generated, // so we can safely skip them. if (isUnevaluatedContext() || isConstantEvaluated()) return true; diff --git a/clang/test/CXX/except/except.spec/p14-ir.cpp b/clang/test/CXX/except/except.spec/p14-ir.cpp index d3edbf24f65b9b6c3515bba448ca73b08eea47c6..f2dc0b81915ce15492e5ac017645e2095c52f315 100644 --- a/clang/test/CXX/except/except.spec/p14-ir.cpp +++ b/clang/test/CXX/except/except.spec/p14-ir.cpp @@ -26,12 +26,12 @@ struct X4 { struct X5 : X0, X4 { }; void test(X2 x2, X3 x3, X5 x5) { - // CHECK: define linkonce_odr void @_ZN2X2C1ERKS_(%struct.X2* {{[^,]*}} %this, %struct.X2* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr + // CHECK: define linkonce_odr void @_ZN2X2C1ERKS_(%struct.X2* {{[^,]*}} %this, %struct.X2* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr // CHECK: call void @_ZN2X2C2ERKS_({{.*}}) [[NUW:#[0-9]+]] // CHECK-NEXT: ret void // CHECK-NEXT: } X2 x2a(x2); - // CHECK: define linkonce_odr void @_ZN2X3C1ERKS_(%struct.X3* {{[^,]*}} %this, %struct.X3* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr + // CHECK: define linkonce_odr void @_ZN2X3C1ERKS_(%struct.X3* {{[^,]*}} %this, %struct.X3* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr // CHECK: call void @_ZN2X3C2ERKS_({{.*}}) [[NUW]] // CHECK-NEXT: ret void // CHECK-NEXT: } diff --git a/clang/test/CXX/expr/expr.prim/expr.prim.lambda/blocks-irgen.mm b/clang/test/CXX/expr/expr.prim/expr.prim.lambda/blocks-irgen.mm index e4f9b13600bf4b4037bae123839808c7d0dac47a..2b4c998724628b1069685f2179d9c5b89030552a 100644 --- a/clang/test/CXX/expr/expr.prim/expr.prim.lambda/blocks-irgen.mm +++ b/clang/test/CXX/expr/expr.prim/expr.prim.lambda/blocks-irgen.mm @@ -13,8 +13,8 @@ namespace PR12746 { return outer(); } - // CHECK: define internal noundef zeroext i1 @___ZN7PR127462f1EPi_block_invoke - // CHECK: call noundef zeroext i1 @"_ZZZN7PR127462f1EPiEUb_ENK3$_0clEv" + // CHECK: define internal zeroext i1 @___ZN7PR127462f1EPi_block_invoke + // CHECK: call zeroext i1 @"_ZZZN7PR127462f1EPiEUb_ENK3$_0clEv" bool f2(int *x) { auto outer = [&]() -> bool { diff --git a/clang/test/CodeGen/2005-01-02-ConstantInits.c b/clang/test/CodeGen/2005-01-02-ConstantInits.c index b3091a25f56bb62c6ecc9e75ba148fdeaf27a7f6..ec29185fae2992d92f6d91e08a969a497528b346 100644 --- a/clang/test/CodeGen/2005-01-02-ConstantInits.c +++ b/clang/test/CodeGen/2005-01-02-ConstantInits.c @@ -29,21 +29,21 @@ int i = (int) &( ((struct X *)0) -> a[1]); int Arr[100]; // CHECK-LABEL: define {{[^@]+}}@foo -// CHECK-SAME: (i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-SAME: (i32 [[I:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 -// CHECK-NEXT: [[CALL:%.*]] = call i32 (i32*, ...) bitcast (i32 (...)* @bar to i32 (i32*, ...)*)(i32* noundef getelementptr inbounds ([100 x i32], [100 x i32]* @Arr, i64 0, i64 49)) +// CHECK-NEXT: [[CALL:%.*]] = call i32 (i32*, ...) bitcast (i32 (...)* @bar to i32 (i32*, ...)*)(i32* getelementptr inbounds ([100 x i32], [100 x i32]* @Arr, i64 0, i64 49)) // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[I_ADDR]], align 4 // CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP0]] to i64 // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @Arr, i64 0, i64 [[IDXPROM]] -// CHECK-NEXT: [[CALL1:%.*]] = call i32 (i32*, ...) bitcast (i32 (...)* @bar to i32 (i32*, ...)*)(i32* noundef [[ARRAYIDX]]) +// CHECK-NEXT: [[CALL1:%.*]] = call i32 (i32*, ...) bitcast (i32 (...)* @bar to i32 (i32*, ...)*)(i32* [[ARRAYIDX]]) // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] // CHECK-NEXT: ret i32 [[ADD]] // int foo(int i) { return bar(&Arr[49])+bar(&Arr[i]); } // CHECK-LABEL: define {{[^@]+}}@foo2 -// CHECK-SAME: (i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-SAME: (i32 [[I:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[P:%.*]] = alloca i32*, align 8 @@ -55,7 +55,7 @@ int foo(int i) { return bar(&Arr[49])+bar(&Arr[i]); } // CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[I_ADDR]], align 4 // CHECK-NEXT: [[IDX_EXT:%.*]] = sext i32 [[TMP1]] to i64 // CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @Arr, i64 0, i64 0), i64 [[IDX_EXT]] -// CHECK-NEXT: [[CALL:%.*]] = call i32 (i32*, ...) bitcast (i32 (...)* @bar to i32 (i32*, ...)*)(i32* noundef [[ADD_PTR]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32 (i32*, ...) bitcast (i32 (...)* @bar to i32 (i32*, ...)*)(i32* [[ADD_PTR]]) // CHECK-NEXT: ret i32 [[CALL]] // int foo2(int i) { diff --git a/clang/test/CodeGen/2006-05-19-SingleEltReturn.c b/clang/test/CodeGen/2006-05-19-SingleEltReturn.c index 79e84020ca4703584ea79045f7eadf8844a2efe5..0895041908024058d500a00b21bd18f198e370d6 100644 --- a/clang/test/CodeGen/2006-05-19-SingleEltReturn.c +++ b/clang/test/CodeGen/2006-05-19-SingleEltReturn.c @@ -23,7 +23,7 @@ struct Y bar() { } -// X86_32: define{{.*}} void @foo(%struct.Y* noundef %P) +// X86_32: define{{.*}} void @foo(%struct.Y* %P) // X86_32: call void @bar(%struct.Y* sret(%struct.Y) align 4 %{{[^),]*}}) // X86_32: define{{.*}} void @bar(%struct.Y* noalias sret(%struct.Y) align 4 %{{[^,)]*}}) diff --git a/clang/test/CodeGen/2007-06-18-SextAttrAggregate.c b/clang/test/CodeGen/2007-06-18-SextAttrAggregate.c index b8e32497102debf16bfeb6d785a7651e8a177e60..4bac5c61bc58c042392042bc46bceba460896b41 100644 --- a/clang/test/CodeGen/2007-06-18-SextAttrAggregate.c +++ b/clang/test/CodeGen/2007-06-18-SextAttrAggregate.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -disable-noundef-analysis %s -o - -emit-llvm | FileCheck %s +// RUN: %clang_cc1 %s -o - -emit-llvm | FileCheck %s // XFAIL: aarch64, arm64, x86_64-pc-windows-msvc, x86_64-w64-windows-gnu, x86_64-pc-windows-gnu // PR1513 diff --git a/clang/test/CodeGen/2009-02-13-zerosize-union-field.c b/clang/test/CodeGen/2009-02-13-zerosize-union-field.c index b4752503855af48cee620d5d49c36b9c1b020b97..e6f024770855adbb89ee9a7f35571916d3c9b191 100644 --- a/clang/test/CodeGen/2009-02-13-zerosize-union-field.c +++ b/clang/test/CodeGen/2009-02-13-zerosize-union-field.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -disable-noundef-analysis -triple i686-apple-darwin -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 %s -triple i686-apple-darwin -emit-llvm -o - | FileCheck %s // Every printf has 'i32 0' for the GEP of the string; no point counting those. typedef unsigned int Foo __attribute__((aligned(32))); typedef union{Foo:0;}a; diff --git a/clang/test/CodeGen/2009-05-04-EnumInreg.c b/clang/test/CodeGen/2009-05-04-EnumInreg.c index 895849022d3fe3ca4286f13a3a9237061c04b2e3..2abc747caf27affa891813ef8d9d6f133ac36905 100644 --- a/clang/test/CodeGen/2009-05-04-EnumInreg.c +++ b/clang/test/CodeGen/2009-05-04-EnumInreg.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -emit-llvm -triple i686-apple-darwin -mregparm 3 %s -o - | FileCheck %s +// RUN: %clang_cc1 -emit-llvm -triple i686-apple-darwin -mregparm 3 %s -o - | FileCheck %s // PR3967 enum kobject_action { diff --git a/clang/test/CodeGen/64bit-swiftcall.c b/clang/test/CodeGen/64bit-swiftcall.c index fe3cb51f1ce67f62ecc7a279c4f66cc402055ba2..dd9abc957bd0eb746e0d6cdd299a55987a879d78 100644 --- a/clang/test/CodeGen/64bit-swiftcall.c +++ b/clang/test/CodeGen/64bit-swiftcall.c @@ -1,7 +1,7 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s --check-prefix=X86-64 -// RUN: %clang_cc1 -disable-noundef-analysis -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s --check-prefix=ARM64 +// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s --check-prefix=X86-64 +// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s --check-prefix=ARM64 // REQUIRES: aarch64-registered-target,x86-registered-target diff --git a/clang/test/CodeGen/RISCV/riscv-inline-asm.c b/clang/test/CodeGen/RISCV/riscv-inline-asm.c index 2eb152943ffe421939b9d0a517e9abd5d474c0a2..2303293876920772998318579cfc64c2995d2689 100644 --- a/clang/test/CodeGen/RISCV/riscv-inline-asm.c +++ b/clang/test/CodeGen/RISCV/riscv-inline-asm.c @@ -40,7 +40,7 @@ void test_f() { } void test_A(int *p) { -// CHECK-LABEL: define{{.*}} void @test_A(i32* noundef %p) +// CHECK-LABEL: define{{.*}} void @test_A(i32* %p) // CHECK: call void asm sideeffect "", "*A"(i32* %p) asm volatile("" :: "A"(*p)); } diff --git a/clang/test/CodeGen/RISCV/riscv32-ilp32-abi.c b/clang/test/CodeGen/RISCV/riscv32-ilp32-abi.c index ad6e5f139a492ff42836f0b06f576a2e57237d88..26c42d4ac8c3a6806ca6c768f675581046beeb34 100644 --- a/clang/test/CodeGen/RISCV/riscv32-ilp32-abi.c +++ b/clang/test/CodeGen/RISCV/riscv32-ilp32-abi.c @@ -25,7 +25,7 @@ struct large { // Scalars passed on the stack should not have signext/zeroext attributes // (they are anyext). -// CHECK-LABEL: define{{.*}} i32 @f_scalar_stack_1(i32 noundef %a, i64 noundef %b, float noundef %c, double noundef %d, fp128 noundef %e, i8 noundef zeroext %f, i8 noundef %g, i8 noundef %h) +// CHECK-LABEL: define{{.*}} i32 @f_scalar_stack_1(i32 %a, i64 %b, float %c, double %d, fp128 %e, i8 zeroext %f, i8 %g, i8 %h) int f_scalar_stack_1(int32_t a, int64_t b, float c, double d, long double e, uint8_t f, int8_t g, uint8_t h) { return g + h; @@ -35,7 +35,7 @@ int f_scalar_stack_1(int32_t a, int64_t b, float c, double d, long double e, // the presence of large return values that consume a register due to the need // to pass a pointer. -// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 4 %agg.result, float noundef %a, i64 noundef %b, double noundef %c, fp128 noundef %d, i8 noundef zeroext %e, i8 noundef %f, i8 noundef %g) +// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 4 %agg.result, float %a, i64 %b, double %c, fp128 %d, i8 zeroext %e, i8 %f, i8 %g) struct large f_scalar_stack_2(float a, int64_t b, double c, long double d, uint8_t e, int8_t f, uint8_t g) { return (struct large){a, e, f, g}; @@ -44,10 +44,10 @@ struct large f_scalar_stack_2(float a, int64_t b, double c, long double d, // Aggregates and >=XLen scalars passed on the stack should be lowered just as // they would be if passed via registers. -// CHECK-LABEL: define{{.*}} void @f_scalar_stack_3(double noundef %a, i64 noundef %b, double noundef %c, i64 noundef %d, i32 noundef %e, i64 noundef %f, float noundef %g, double noundef %h, fp128 noundef %i) +// CHECK-LABEL: define{{.*}} void @f_scalar_stack_3(double %a, i64 %b, double %c, i64 %d, i32 %e, i64 %f, float %g, double %h, fp128 %i) void f_scalar_stack_3(double a, int64_t b, double c, int64_t d, int e, int64_t f, float g, double h, long double i) {} -// CHECK-LABEL: define{{.*}} void @f_agg_stack(double noundef %a, i64 noundef %b, double noundef %c, i64 noundef %d, i32 %e.coerce, [2 x i32] %f.coerce, i64 %g.coerce, %struct.large* noundef %h) +// CHECK-LABEL: define{{.*}} void @f_agg_stack(double %a, i64 %b, double %c, i64 %d, i32 %e.coerce, [2 x i32] %f.coerce, i64 %g.coerce, %struct.large* %h) void f_agg_stack(double a, int64_t b, double c, int64_t d, struct tiny e, struct small f, struct small_aligned g, struct large h) {} diff --git a/clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-abi.c b/clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-abi.c index 7223c09311233be2b1521749a882db427d5cb6a2..0b3b3b6be90dc90f13566f0d161a8bf905382416 100644 --- a/clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-abi.c +++ b/clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-abi.c @@ -27,7 +27,7 @@ struct large { // Scalars passed on the stack should not have signext/zeroext attributes // (they are anyext). -// CHECK-LABEL: define{{.*}} i32 @f_scalar_stack_1(i32 noundef %a, i64 noundef %b, i32 noundef %c, double noundef %d, fp128 noundef %e, i8 noundef zeroext %f, i8 noundef %g, i8 noundef %h) +// CHECK-LABEL: define{{.*}} i32 @f_scalar_stack_1(i32 %a, i64 %b, i32 %c, double %d, fp128 %e, i8 zeroext %f, i8 %g, i8 %h) int f_scalar_stack_1(int32_t a, int64_t b, int32_t c, double d, long double e, uint8_t f, int8_t g, uint8_t h) { return g + h; @@ -37,7 +37,7 @@ int f_scalar_stack_1(int32_t a, int64_t b, int32_t c, double d, long double e, // the presence of large return values that consume a register due to the need // to pass a pointer. -// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 4 %agg.result, i32 noundef %a, i64 noundef %b, double noundef %c, fp128 noundef %d, i8 noundef zeroext %e, i8 noundef %f, i8 noundef %g) +// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 4 %agg.result, i32 %a, i64 %b, double %c, fp128 %d, i8 zeroext %e, i8 %f, i8 %g) struct large f_scalar_stack_2(int32_t a, int64_t b, double c, long double d, uint8_t e, int8_t f, uint8_t g) { return (struct large){a, e, f, g}; @@ -46,10 +46,10 @@ struct large f_scalar_stack_2(int32_t a, int64_t b, double c, long double d, // Aggregates and >=XLen scalars passed on the stack should be lowered just as // they would be if passed via registers. -// CHECK-LABEL: define{{.*}} void @f_scalar_stack_3(double noundef %a, i64 noundef %b, double noundef %c, i64 noundef %d, i32 noundef %e, i64 noundef %f, i32 noundef %g, double noundef %h, fp128 noundef %i) +// CHECK-LABEL: define{{.*}} void @f_scalar_stack_3(double %a, i64 %b, double %c, i64 %d, i32 %e, i64 %f, i32 %g, double %h, fp128 %i) void f_scalar_stack_3(double a, int64_t b, double c, int64_t d, int e, int64_t f, int32_t g, double h, long double i) {} -// CHECK-LABEL: define{{.*}} void @f_agg_stack(double noundef %a, i64 noundef %b, double noundef %c, i64 noundef %d, i32 %e.coerce, [2 x i32] %f.coerce, i64 %g.coerce, %struct.large* noundef %h) +// CHECK-LABEL: define{{.*}} void @f_agg_stack(double %a, i64 %b, double %c, i64 %d, i32 %e.coerce, [2 x i32] %f.coerce, i64 %g.coerce, %struct.large* %h) void f_agg_stack(double a, int64_t b, double c, int64_t d, struct tiny e, struct small f, struct small_aligned g, struct large h) {} diff --git a/clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c b/clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c index 9cf0849e8bc5048f93f776c2ae13fb36570cffc8..da0be1dd0c0dcbc5ebab04a2047a30b4abfe96c4 100644 --- a/clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c +++ b/clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c @@ -17,37 +17,37 @@ void f_void(void) {} // Scalar arguments and return values smaller than the word size are extended // according to the sign of their type, up to 32 bits -// CHECK-LABEL: define{{.*}} zeroext i1 @f_scalar_0(i1 noundef zeroext %x) +// CHECK-LABEL: define{{.*}} zeroext i1 @f_scalar_0(i1 zeroext %x) _Bool f_scalar_0(_Bool x) { return x; } -// CHECK-LABEL: define{{.*}} signext i8 @f_scalar_1(i8 noundef signext %x) +// CHECK-LABEL: define{{.*}} signext i8 @f_scalar_1(i8 signext %x) int8_t f_scalar_1(int8_t x) { return x; } -// CHECK-LABEL: define{{.*}} zeroext i8 @f_scalar_2(i8 noundef zeroext %x) +// CHECK-LABEL: define{{.*}} zeroext i8 @f_scalar_2(i8 zeroext %x) uint8_t f_scalar_2(uint8_t x) { return x; } -// CHECK-LABEL: define{{.*}} i32 @f_scalar_3(i32 noundef %x) +// CHECK-LABEL: define{{.*}} i32 @f_scalar_3(i32 %x) int32_t f_scalar_3(int32_t x) { return x; } -// CHECK-LABEL: define{{.*}} i64 @f_scalar_4(i64 noundef %x) +// CHECK-LABEL: define{{.*}} i64 @f_scalar_4(i64 %x) int64_t f_scalar_4(int64_t x) { return x; } #ifdef __SIZEOF_INT128__ -// CHECK-FORCEINT128-LABEL: define{{.*}} i128 @f_scalar_5(i128 noundef %x) +// CHECK-FORCEINT128-LABEL: define{{.*}} i128 @f_scalar_5(i128 %x) __int128_t f_scalar_5(__int128_t x) { return x; } #endif -// CHECK-LABEL: define{{.*}} float @f_fp_scalar_1(float noundef %x) +// CHECK-LABEL: define{{.*}} float @f_fp_scalar_1(float %x) float f_fp_scalar_1(float x) { return x; } -// CHECK-LABEL: define{{.*}} double @f_fp_scalar_2(double noundef %x) +// CHECK-LABEL: define{{.*}} double @f_fp_scalar_2(double %x) double f_fp_scalar_2(double x) { return x; } // Scalars larger than 2*xlen are passed/returned indirect. However, the // RISC-V LLVM backend can handle this fine, so the function doesn't need to // be modified. -// CHECK-LABEL: define{{.*}} fp128 @f_fp_scalar_3(fp128 noundef %x) +// CHECK-LABEL: define{{.*}} fp128 @f_fp_scalar_3(fp128 %x) long double f_fp_scalar_3(long double x) { return x; } // Empty structs or unions are ignored. @@ -87,7 +87,7 @@ struct tiny f_agg_tiny_ret() { typedef uint8_t v4i8 __attribute__((vector_size(4))); typedef int32_t v1i32 __attribute__((vector_size(4))); -// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v4i8(i32 noundef %x.coerce) +// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v4i8(i32 %x.coerce) void f_vec_tiny_v4i8(v4i8 x) { x[0] = x[1]; x[2] = x[3]; @@ -98,7 +98,7 @@ v4i8 f_vec_tiny_v4i8_ret() { return (v4i8){1, 2, 3, 4}; } -// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v1i32(i32 noundef %x.coerce) +// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v1i32(i32 %x.coerce) void f_vec_tiny_v1i32(v1i32 x) { x[0] = 114; } @@ -126,7 +126,7 @@ struct small f_agg_small_ret() { typedef uint8_t v8i8 __attribute__((vector_size(8))); typedef int64_t v1i64 __attribute__((vector_size(8))); -// CHECK-LABEL: define{{.*}} void @f_vec_small_v8i8(i64 noundef %x.coerce) +// CHECK-LABEL: define{{.*}} void @f_vec_small_v8i8(i64 %x.coerce) void f_vec_small_v8i8(v8i8 x) { x[0] = x[7]; } @@ -136,7 +136,7 @@ v8i8 f_vec_small_v8i8_ret() { return (v8i8){1, 2, 3, 4, 5, 6, 7, 8}; } -// CHECK-LABEL: define{{.*}} void @f_vec_small_v1i64(i64 noundef %x.coerce) +// CHECK-LABEL: define{{.*}} void @f_vec_small_v1i64(i64 %x.coerce) void f_vec_small_v1i64(v1i64 x) { x[0] = 114; } @@ -169,21 +169,21 @@ struct large { int32_t a, b, c, d; }; -// CHECK-LABEL: define{{.*}} void @f_agg_large(%struct.large* noundef %x) +// CHECK-LABEL: define{{.*}} void @f_agg_large(%struct.large* %x) void f_agg_large(struct large x) { x.a = x.b + x.c + x.d; } // The address where the struct should be written to will be the first // argument -// CHECK-LABEL: define{{.*}} void @f_agg_large_ret(%struct.large* noalias sret(%struct.large) align 4 %agg.result, i32 noundef %i, i8 noundef signext %j) +// CHECK-LABEL: define{{.*}} void @f_agg_large_ret(%struct.large* noalias sret(%struct.large) align 4 %agg.result, i32 %i, i8 signext %j) struct large f_agg_large_ret(int32_t i, int8_t j) { return (struct large){1, 2, 3, 4}; } typedef unsigned char v16i8 __attribute__((vector_size(16))); -// CHECK-LABEL: define{{.*}} void @f_vec_large_v16i8(<16 x i8>* noundef %0) +// CHECK-LABEL: define{{.*}} void @f_vec_large_v16i8(<16 x i8>* %0) void f_vec_large_v16i8(v16i8 x) { x[0] = x[7]; } @@ -196,7 +196,7 @@ v16i8 f_vec_large_v16i8_ret() { // Scalars passed on the stack should not have signext/zeroext attributes // (they are anyext). -// CHECK-LABEL: define{{.*}} i32 @f_scalar_stack_1(i32 %a.coerce, [2 x i32] %b.coerce, i64 %c.coerce, %struct.large* noundef %d, i8 noundef zeroext %e, i8 noundef signext %f, i8 noundef %g, i8 noundef %h) +// CHECK-LABEL: define{{.*}} i32 @f_scalar_stack_1(i32 %a.coerce, [2 x i32] %b.coerce, i64 %c.coerce, %struct.large* %d, i8 zeroext %e, i8 signext %f, i8 %g, i8 %h) int f_scalar_stack_1(struct tiny a, struct small b, struct small_aligned c, struct large d, uint8_t e, int8_t f, uint8_t g, int8_t h) { return g + h; @@ -206,13 +206,13 @@ int f_scalar_stack_1(struct tiny a, struct small b, struct small_aligned c, // the presence of large return values that consume a register due to the need // to pass a pointer. -// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 4 %agg.result, i32 noundef %a, i64 noundef %b, i64 noundef %c, fp128 noundef %d, i8 noundef zeroext %e, i8 noundef %f, i8 noundef %g) +// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 4 %agg.result, i32 %a, i64 %b, i64 %c, fp128 %d, i8 zeroext %e, i8 %f, i8 %g) struct large f_scalar_stack_2(int32_t a, int64_t b, int64_t c, long double d, uint8_t e, int8_t f, uint8_t g) { return (struct large){a, e, f, g}; } -// CHECK-LABEL: define{{.*}} fp128 @f_scalar_stack_4(i32 noundef %a, i64 noundef %b, i64 noundef %c, fp128 noundef %d, i8 noundef zeroext %e, i8 noundef %f, i8 noundef %g) +// CHECK-LABEL: define{{.*}} fp128 @f_scalar_stack_4(i32 %a, i64 %b, i64 %c, fp128 %d, i8 zeroext %e, i8 %f, i8 %g) long double f_scalar_stack_4(int32_t a, int64_t b, int64_t c, long double d, uint8_t e, int8_t f, uint8_t g) { return d; @@ -221,11 +221,11 @@ long double f_scalar_stack_4(int32_t a, int64_t b, int64_t c, long double d, // Aggregates and >=XLen scalars passed on the stack should be lowered just as // they would be if passed via registers. -// CHECK-LABEL: define{{.*}} void @f_scalar_stack_5(double noundef %a, i64 noundef %b, double noundef %c, i64 noundef %d, i32 noundef %e, i64 noundef %f, float noundef %g, double noundef %h, fp128 noundef %i) +// CHECK-LABEL: define{{.*}} void @f_scalar_stack_5(double %a, i64 %b, double %c, i64 %d, i32 %e, i64 %f, float %g, double %h, fp128 %i) void f_scalar_stack_5(double a, int64_t b, double c, int64_t d, int e, int64_t f, float g, double h, long double i) {} -// CHECK-LABEL: define{{.*}} void @f_agg_stack(double noundef %a, i64 noundef %b, double noundef %c, i64 noundef %d, i32 %e.coerce, [2 x i32] %f.coerce, i64 %g.coerce, %struct.large* noundef %h) +// CHECK-LABEL: define{{.*}} void @f_agg_stack(double %a, i64 %b, double %c, i64 %d, i32 %e.coerce, [2 x i32] %f.coerce, i64 %g.coerce, %struct.large* %h) void f_agg_stack(double a, int64_t b, double c, int64_t d, struct tiny e, struct small f, struct small_aligned g, struct large h) {} @@ -236,14 +236,14 @@ void f_agg_stack(double a, int64_t b, double c, int64_t d, struct tiny e, int f_va_callee(int, ...); // CHECK-LABEL: define{{.*}} void @f_va_caller() -// CHECK: call i32 (i32, ...) @f_va_callee(i32 noundef 1, i32 noundef 2, i64 noundef 3, double noundef 4.000000e+00, double noundef 5.000000e+00, i32 {{%.*}}, [2 x i32] {{%.*}}, i64 {{%.*}}, %struct.large* noundef {{%.*}}) +// CHECK: call i32 (i32, ...) @f_va_callee(i32 1, i32 2, i64 3, double 4.000000e+00, double 5.000000e+00, i32 {{%.*}}, [2 x i32] {{%.*}}, i64 {{%.*}}, %struct.large* {{%.*}}) void f_va_caller() { f_va_callee(1, 2, 3LL, 4.0f, 5.0, (struct tiny){6, 7, 8, 9}, (struct small){10, NULL}, (struct small_aligned){11}, (struct large){12, 13, 14, 15}); } -// CHECK-LABEL: define{{.*}} i32 @f_va_1(i8* noundef %fmt, ...) {{.*}} { +// CHECK-LABEL: define{{.*}} i32 @f_va_1(i8* %fmt, ...) {{.*}} { // CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 4 // CHECK: [[VA:%.*]] = alloca i8*, align 4 // CHECK: [[V:%.*]] = alloca i32, align 4 @@ -361,7 +361,7 @@ double f_va_3(char *fmt, ...) { return v + x; } -// CHECK-LABEL: define{{.*}} i32 @f_va_4(i8* noundef %fmt, ...) {{.*}} { +// CHECK-LABEL: define{{.*}} i32 @f_va_4(i8* %fmt, ...) {{.*}} { // CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 4 // CHECK-NEXT: [[VA:%.*]] = alloca i8*, align 4 // CHECK-NEXT: [[V:%.*]] = alloca i32, align 4 diff --git a/clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c b/clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c index a6c8c762056cf0853e25333b0f321a2d6f28e09c..39a210a89ae79b536bfa3e76a74b7039870f40f9 100644 --- a/clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c +++ b/clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c @@ -9,7 +9,7 @@ // Doubles are passed in FPRs, so argument 'i' will be passed zero-extended // because it will be passed in a GPR. -// CHECK: define{{.*}} void @f_fpr_tracking(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, i8 noundef zeroext %i) +// CHECK: define{{.*}} void @f_fpr_tracking(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, i8 zeroext %i) void f_fpr_tracking(double a, double b, double c, double d, double e, double f, double g, double h, uint8_t i) {} @@ -77,7 +77,7 @@ struct double_float_s f_ret_double_float_s() { return (struct double_float_s){1.0, 2.0}; } -// CHECK: define{{.*}} void @f_double_double_s_arg_insufficient_fprs(float noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, %struct.double_double_s* noundef %h) +// CHECK: define{{.*}} void @f_double_double_s_arg_insufficient_fprs(float %a, double %b, double %c, double %d, double %e, double %f, double %g, %struct.double_double_s* %h) void f_double_double_s_arg_insufficient_fprs(float a, double b, double c, double d, double e, double f, double g, struct double_double_s h) {} @@ -116,7 +116,7 @@ struct double_int32_s f_ret_double_int32_s() { return (struct double_int32_s){1.0, 2}; } -// CHECK: define{{.*}} void @f_double_int64_s_arg(%struct.double_int64_s* noundef %a) +// CHECK: define{{.*}} void @f_double_int64_s_arg(%struct.double_int64_s* %a) void f_double_int64_s_arg(struct double_int64_s a) {} // CHECK: define{{.*}} void @f_ret_double_int64_s(%struct.double_int64_s* noalias sret(%struct.double_int64_s) align 8 %agg.result) @@ -143,18 +143,18 @@ struct double_int8_zbf_s f_ret_double_int8_zbf_s() { return (struct double_int8_zbf_s){1.0, 2}; } -// CHECK: define{{.*}} void @f_double_int8_s_arg_insufficient_gprs(i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, i32 noundef %h, %struct.double_int8_s* noundef %i) +// CHECK: define{{.*}} void @f_double_int8_s_arg_insufficient_gprs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, %struct.double_int8_s* %i) void f_double_int8_s_arg_insufficient_gprs(int a, int b, int c, int d, int e, int f, int g, int h, struct double_int8_s i) {} -// CHECK: define{{.*}} void @f_struct_double_int8_insufficient_fprs(float noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, %struct.double_int8_s* noundef %i) +// CHECK: define{{.*}} void @f_struct_double_int8_insufficient_fprs(float %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, %struct.double_int8_s* %i) void f_struct_double_int8_insufficient_fprs(float a, double b, double c, double d, double e, double f, double g, double h, struct double_int8_s i) {} // Complex floating-point values or structs containing a single complex // floating-point value should be passed as if it were an fp+fp struct. -// CHECK: define{{.*}} void @f_doublecomplex(double noundef %a.coerce0, double noundef %a.coerce1) +// CHECK: define{{.*}} void @f_doublecomplex(double %a.coerce0, double %a.coerce1) void f_doublecomplex(double __complex__ a) {} // CHECK: define{{.*}} { double, double } @f_ret_doublecomplex() @@ -240,7 +240,7 @@ struct doublearr2_tricky4_s f_ret_doublearr2_tricky4_s() { struct int_double_int_s { int a; double b; int c; }; -// CHECK: define{{.*}} void @f_int_double_int_s_arg(%struct.int_double_int_s* noundef %a) +// CHECK: define{{.*}} void @f_int_double_int_s_arg(%struct.int_double_int_s* %a) void f_int_double_int_s_arg(struct int_double_int_s a) {} // CHECK: define{{.*}} void @f_ret_int_double_int_s(%struct.int_double_int_s* noalias sret(%struct.int_double_int_s) align 8 %agg.result) @@ -250,7 +250,7 @@ struct int_double_int_s f_ret_int_double_int_s() { struct int64_double_s { int64_t a; double b; }; -// CHECK: define{{.*}} void @f_int64_double_s_arg(%struct.int64_double_s* noundef %a) +// CHECK: define{{.*}} void @f_int64_double_s_arg(%struct.int64_double_s* %a) void f_int64_double_s_arg(struct int64_double_s a) {} // CHECK: define{{.*}} void @f_ret_int64_double_s(%struct.int64_double_s* noalias sret(%struct.int64_double_s) align 8 %agg.result) @@ -260,7 +260,7 @@ struct int64_double_s f_ret_int64_double_s() { struct char_char_double_s { char a; char b; double c; }; -// CHECK-LABEL: define{{.*}} void @f_char_char_double_s_arg(%struct.char_char_double_s* noundef %a) +// CHECK-LABEL: define{{.*}} void @f_char_char_double_s_arg(%struct.char_char_double_s* %a) void f_char_char_double_s_arg(struct char_char_double_s a) {} // CHECK: define{{.*}} void @f_ret_char_char_double_s(%struct.char_char_double_s* noalias sret(%struct.char_char_double_s) align 8 %agg.result) @@ -287,19 +287,19 @@ union double_u f_ret_double_u() { // returned in registers). This includes complex doubles, which are treated as // double+double structs by the ABI. -// CHECK: define{{.*}} { double, i32 } @f_ret_double_int32_s_double_int32_s_just_sufficient_gprs(i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, double %0, i32 %1) +// CHECK: define{{.*}} { double, i32 } @f_ret_double_int32_s_double_int32_s_just_sufficient_gprs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, double %0, i32 %1) struct double_int32_s f_ret_double_int32_s_double_int32_s_just_sufficient_gprs( int a, int b, int c, int d, int e, int f, int g, struct double_int32_s h) { return (struct double_int32_s){1.0, 2}; } -// CHECK: define{{.*}} { double, double } @f_ret_double_double_s_double_int32_s_just_sufficient_gprs(i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, double %0, i32 %1) +// CHECK: define{{.*}} { double, double } @f_ret_double_double_s_double_int32_s_just_sufficient_gprs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, double %0, i32 %1) struct double_double_s f_ret_double_double_s_double_int32_s_just_sufficient_gprs( int a, int b, int c, int d, int e, int f, int g, struct double_int32_s h) { return (struct double_double_s){1.0, 2.0}; } -// CHECK: define{{.*}} { double, double } @f_ret_doublecomplex_double_int32_s_just_sufficient_gprs(i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, double %0, i32 %1) +// CHECK: define{{.*}} { double, double } @f_ret_doublecomplex_double_int32_s_just_sufficient_gprs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, double %0, i32 %1) double __complex__ f_ret_doublecomplex_double_int32_s_just_sufficient_gprs( int a, int b, int c, int d, int e, int f, int g, struct double_int32_s h) { return 1.0; diff --git a/clang/test/CodeGen/RISCV/riscv32-ilp32f-abi.c b/clang/test/CodeGen/RISCV/riscv32-ilp32f-abi.c index 1963267e6ca8805748178a066ae59f26b4fd09e8..e48ceccee4d9477859ecdc268c433c0d73839ce3 100644 --- a/clang/test/CodeGen/RISCV/riscv32-ilp32f-abi.c +++ b/clang/test/CodeGen/RISCV/riscv32-ilp32f-abi.c @@ -6,7 +6,7 @@ // Doubles are still passed in GPRs, so the 'e' argument will be anyext as // GPRs are exhausted. -// CHECK: define{{.*}} void @f_fpr_tracking(double noundef %a, double noundef %b, double noundef %c, double noundef %d, i8 noundef %e) +// CHECK: define{{.*}} void @f_fpr_tracking(double %a, double %b, double %c, double %d, i8 %e) void f_fpr_tracking(double a, double b, double c, double d, int8_t e) {} // Lowering for doubles is unnmodified, as 64 > FLEN. @@ -23,7 +23,7 @@ struct double_s f_ret_double_s() { struct double_double_s { double d; double e; }; -// CHECK: define{{.*}} void @f_double_double_s_arg(%struct.double_double_s* noundef %a) +// CHECK: define{{.*}} void @f_double_double_s_arg(%struct.double_double_s* %a) void f_double_double_s_arg(struct double_double_s a) {} // CHECK: define{{.*}} void @f_ret_double_double_s(%struct.double_double_s* noalias sret(%struct.double_double_s) align 8 %agg.result) @@ -35,7 +35,7 @@ struct double_int8_s { double d; int64_t i; }; struct int_double_s { int a; double b; }; -// CHECK: define{{.*}} void @f_int_double_s_arg(%struct.int_double_s* noundef %a) +// CHECK: define{{.*}} void @f_int_double_s_arg(%struct.int_double_s* %a) void f_int_double_s_arg(struct int_double_s a) {} // CHECK: define{{.*}} void @f_ret_int_double_s(%struct.int_double_s* noalias sret(%struct.int_double_s) align 8 %agg.result) diff --git a/clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c b/clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c index 3dae826bf774662c90d910e079682a16e17682b4..e887d986f96a38bd152fabd20182a3808feddc3c 100644 --- a/clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c +++ b/clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c @@ -11,7 +11,7 @@ // Floats are passed in FPRs, so argument 'i' will be passed zero-extended // because it will be passed in a GPR. -// CHECK: define{{.*}} void @f_fpr_tracking(float noundef %a, float noundef %b, float noundef %c, float noundef %d, float noundef %e, float noundef %f, float noundef %g, float noundef %h, i8 noundef zeroext %i) +// CHECK: define{{.*}} void @f_fpr_tracking(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, i8 zeroext %i) void f_fpr_tracking(float a, float b, float c, float d, float e, float f, float g, float h, uint8_t i) {} @@ -70,7 +70,7 @@ struct float_float_s f_ret_float_float_s() { return (struct float_float_s){1.0, 2.0}; } -// CHECK: define{{.*}} void @f_float_float_s_arg_insufficient_fprs(float noundef %a, float noundef %b, float noundef %c, float noundef %d, float noundef %e, float noundef %f, float noundef %g, [2 x i32] %h.coerce) +// CHECK: define{{.*}} void @f_float_float_s_arg_insufficient_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, [2 x i32] %h.coerce) void f_float_float_s_arg_insufficient_fprs(float a, float b, float c, float d, float e, float f, float g, struct float_float_s h) {} @@ -109,7 +109,7 @@ struct float_int32_s f_ret_float_int32_s() { return (struct float_int32_s){1.0, 2}; } -// CHECK: define{{.*}} void @f_float_int64_s_arg(%struct.float_int64_s* noundef %a) +// CHECK: define{{.*}} void @f_float_int64_s_arg(%struct.float_int64_s* %a) void f_float_int64_s_arg(struct float_int64_s a) {} // CHECK: define{{.*}} void @f_ret_float_int64_s(%struct.float_int64_s* noalias sret(%struct.float_int64_s) align 8 %agg.result) @@ -136,18 +136,18 @@ struct float_int8_zbf_s f_ret_float_int8_zbf_s() { return (struct float_int8_zbf_s){1.0, 2}; } -// CHECK: define{{.*}} void @f_float_int8_s_arg_insufficient_gprs(i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, i32 noundef %h, [2 x i32] %i.coerce) +// CHECK: define{{.*}} void @f_float_int8_s_arg_insufficient_gprs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, [2 x i32] %i.coerce) void f_float_int8_s_arg_insufficient_gprs(int a, int b, int c, int d, int e, int f, int g, int h, struct float_int8_s i) {} -// CHECK: define{{.*}} void @f_struct_float_int8_insufficient_fprs(float noundef %a, float noundef %b, float noundef %c, float noundef %d, float noundef %e, float noundef %f, float noundef %g, float noundef %h, [2 x i32] %i.coerce) +// CHECK: define{{.*}} void @f_struct_float_int8_insufficient_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, [2 x i32] %i.coerce) void f_struct_float_int8_insufficient_fprs(float a, float b, float c, float d, float e, float f, float g, float h, struct float_int8_s i) {} // Complex floating-point values or structs containing a single complex // floating-point value should be passed as if it were an fp+fp struct. -// CHECK: define{{.*}} void @f_floatcomplex(float noundef %a.coerce0, float noundef %a.coerce1) +// CHECK: define{{.*}} void @f_floatcomplex(float %a.coerce0, float %a.coerce1) void f_floatcomplex(float __complex__ a) {} // CHECK: define{{.*}} { float, float } @f_ret_floatcomplex() @@ -233,7 +233,7 @@ struct floatarr2_tricky4_s f_ret_floatarr2_tricky4_s() { struct int_float_int_s { int a; float b; int c; }; -// CHECK: define{{.*}} void @f_int_float_int_s_arg(%struct.int_float_int_s* noundef %a) +// CHECK: define{{.*}} void @f_int_float_int_s_arg(%struct.int_float_int_s* %a) void f_int_float_int_s_arg(struct int_float_int_s a) {} // CHECK: define{{.*}} void @f_ret_int_float_int_s(%struct.int_float_int_s* noalias sret(%struct.int_float_int_s) align 4 %agg.result) @@ -243,7 +243,7 @@ struct int_float_int_s f_ret_int_float_int_s() { struct int64_float_s { int64_t a; float b; }; -// CHECK: define{{.*}} void @f_int64_float_s_arg(%struct.int64_float_s* noundef %a) +// CHECK: define{{.*}} void @f_int64_float_s_arg(%struct.int64_float_s* %a) void f_int64_float_s_arg(struct int64_float_s a) {} // CHECK: define{{.*}} void @f_ret_int64_float_s(%struct.int64_float_s* noalias sret(%struct.int64_float_s) align 8 %agg.result) diff --git a/clang/test/CodeGen/RISCV/riscv64-lp64-abi.c b/clang/test/CodeGen/RISCV/riscv64-lp64-abi.c index e7561c3f5c1b134ea5f44a978c8d3fec54a1a808..c42277ec46ed3cf93be82cd3b2a8f822be09c6f4 100644 --- a/clang/test/CodeGen/RISCV/riscv64-lp64-abi.c +++ b/clang/test/CodeGen/RISCV/riscv64-lp64-abi.c @@ -15,7 +15,7 @@ typedef unsigned char v32i8 __attribute__((vector_size(32))); // Scalars passed on the stack should not have signext/zeroext attributes // (they are anyext). -// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_1(i32 noundef signext %a, i128 noundef %b, float noundef %c, fp128 noundef %d, <32 x i8>* noundef %0, i8 noundef zeroext %f, i8 noundef %g, i8 noundef %h) +// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_1(i32 signext %a, i128 %b, float %c, fp128 %d, <32 x i8>* %0, i8 zeroext %f, i8 %g, i8 %h) int f_scalar_stack_1(int32_t a, __int128_t b, float c, long double d, v32i8 e, uint8_t f, int8_t g, uint8_t h) { return g + h; @@ -25,7 +25,7 @@ int f_scalar_stack_1(int32_t a, __int128_t b, float c, long double d, v32i8 e, // the presence of large return values that consume a register due to the need // to pass a pointer. -// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 8 %agg.result, double noundef %a, i128 noundef %b, fp128 noundef %c, <32 x i8>* noundef %0, i8 noundef zeroext %e, i8 noundef %f, i8 noundef %g) +// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 8 %agg.result, double %a, i128 %b, fp128 %c, <32 x i8>* %0, i8 zeroext %e, i8 %f, i8 %g) struct large f_scalar_stack_2(double a, __int128_t b, long double c, v32i8 d, uint8_t e, int8_t f, uint8_t g) { return (struct large){a, e, f, g}; @@ -34,7 +34,7 @@ struct large f_scalar_stack_2(double a, __int128_t b, long double c, v32i8 d, // Complex floating-point values or structs containing a single complex // floating-point value should be passed in a GPR. -// CHECK: define{{.*}} void @f_floatcomplex(i64 noundef %a.coerce) +// CHECK: define{{.*}} void @f_floatcomplex(i64 %a.coerce) void f_floatcomplex(float __complex__ a) {} // CHECK: define{{.*}} i64 @f_ret_floatcomplex() diff --git a/clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-abi.c b/clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-abi.c index c4ef7b4bf4321c563be2ba0436fe4b4d08608979..9e2be9a52eb6829497898ffc5f61bc320fe3a5df 100644 --- a/clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-abi.c +++ b/clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-abi.c @@ -17,7 +17,7 @@ typedef unsigned char v32i8 __attribute__((vector_size(32))); // Scalars passed on the stack should not have signext/zeroext attributes // (they are anyext). -// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_1(i32 noundef signext %a, i128 noundef %b, double noundef %c, fp128 noundef %d, <32 x i8>* noundef %0, i8 noundef zeroext %f, i8 noundef %g, i8 noundef %h) +// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_1(i32 signext %a, i128 %b, double %c, fp128 %d, <32 x i8>* %0, i8 zeroext %f, i8 %g, i8 %h) int f_scalar_stack_1(int32_t a, __int128_t b, double c, long double d, v32i8 e, uint8_t f, int8_t g, uint8_t h) { return g + h; @@ -27,7 +27,7 @@ int f_scalar_stack_1(int32_t a, __int128_t b, double c, long double d, v32i8 e, // the presence of large return values that consume a register due to the need // to pass a pointer. -// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 8 %agg.result, double noundef %a, i128 noundef %b, fp128 noundef %c, <32 x i8>* noundef %0, i8 noundef zeroext %e, i8 noundef %f, i8 noundef %g) +// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 8 %agg.result, double %a, i128 %b, fp128 %c, <32 x i8>* %0, i8 zeroext %e, i8 %f, i8 %g) struct large f_scalar_stack_2(double a, __int128_t b, long double c, v32i8 d, uint8_t e, int8_t f, uint8_t g) { return (struct large){a, e, f, g}; diff --git a/clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c b/clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c index f020197e0ea11efef54c1284b5e5955816f38732..ba11475a9c5507d3c039230c0f32fd3e31f42ad4 100644 --- a/clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c +++ b/clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c @@ -16,28 +16,28 @@ void f_void(void) {} // Scalar arguments and return values smaller than the word size are extended // according to the sign of their type, up to 32 bits -// CHECK-LABEL: define{{.*}} zeroext i1 @f_scalar_0(i1 noundef zeroext %x) +// CHECK-LABEL: define{{.*}} zeroext i1 @f_scalar_0(i1 zeroext %x) _Bool f_scalar_0(_Bool x) { return x; } -// CHECK-LABEL: define{{.*}} signext i8 @f_scalar_1(i8 noundef signext %x) +// CHECK-LABEL: define{{.*}} signext i8 @f_scalar_1(i8 signext %x) int8_t f_scalar_1(int8_t x) { return x; } -// CHECK-LABEL: define{{.*}} zeroext i8 @f_scalar_2(i8 noundef zeroext %x) +// CHECK-LABEL: define{{.*}} zeroext i8 @f_scalar_2(i8 zeroext %x) uint8_t f_scalar_2(uint8_t x) { return x; } -// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_3(i32 noundef signext %x) +// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_3(i32 signext %x) uint32_t f_scalar_3(int32_t x) { return x; } -// CHECK-LABEL: define{{.*}} i64 @f_scalar_4(i64 noundef %x) +// CHECK-LABEL: define{{.*}} i64 @f_scalar_4(i64 %x) int64_t f_scalar_4(int64_t x) { return x; } -// CHECK-LABEL: define{{.*}} float @f_fp_scalar_1(float noundef %x) +// CHECK-LABEL: define{{.*}} float @f_fp_scalar_1(float %x) float f_fp_scalar_1(float x) { return x; } -// CHECK-LABEL: define{{.*}} double @f_fp_scalar_2(double noundef %x) +// CHECK-LABEL: define{{.*}} double @f_fp_scalar_2(double %x) double f_fp_scalar_2(double x) { return x; } -// CHECK-LABEL: define{{.*}} fp128 @f_fp_scalar_3(fp128 noundef %x) +// CHECK-LABEL: define{{.*}} fp128 @f_fp_scalar_3(fp128 %x) long double f_fp_scalar_3(long double x) { return x; } // Empty structs or unions are ignored. @@ -77,7 +77,7 @@ struct tiny f_agg_tiny_ret() { typedef uint16_t v4i16 __attribute__((vector_size(8))); typedef int64_t v1i64 __attribute__((vector_size(8))); -// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v4i16(i64 noundef %x.coerce) +// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v4i16(i64 %x.coerce) void f_vec_tiny_v4i16(v4i16 x) { x[0] = x[1]; x[2] = x[3]; @@ -88,7 +88,7 @@ v4i16 f_vec_tiny_v4i16_ret() { return (v4i16){1, 2, 3, 4}; } -// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v1i64(i64 noundef %x.coerce) +// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v1i64(i64 %x.coerce) void f_vec_tiny_v1i64(v1i64 x) { x[0] = 114; } @@ -116,7 +116,7 @@ struct small f_agg_small_ret() { typedef uint16_t v8i16 __attribute__((vector_size(16))); typedef __int128_t v1i128 __attribute__((vector_size(16))); -// CHECK-LABEL: define{{.*}} void @f_vec_small_v8i16(i128 noundef %x.coerce) +// CHECK-LABEL: define{{.*}} void @f_vec_small_v8i16(i128 %x.coerce) void f_vec_small_v8i16(v8i16 x) { x[0] = x[7]; } @@ -126,7 +126,7 @@ v8i16 f_vec_small_v8i16_ret() { return (v8i16){1, 2, 3, 4, 5, 6, 7, 8}; } -// CHECK-LABEL: define{{.*}} void @f_vec_small_v1i128(i128 noundef %x.coerce) +// CHECK-LABEL: define{{.*}} void @f_vec_small_v1i128(i128 %x.coerce) void f_vec_small_v1i128(v1i128 x) { x[0] = 114; } @@ -159,21 +159,21 @@ struct large { int64_t a, b, c, d; }; -// CHECK-LABEL: define{{.*}} void @f_agg_large(%struct.large* noundef %x) +// CHECK-LABEL: define{{.*}} void @f_agg_large(%struct.large* %x) void f_agg_large(struct large x) { x.a = x.b + x.c + x.d; } // The address where the struct should be written to will be the first // argument -// CHECK-LABEL: define{{.*}} void @f_agg_large_ret(%struct.large* noalias sret(%struct.large) align 8 %agg.result, i32 noundef signext %i, i8 noundef signext %j) +// CHECK-LABEL: define{{.*}} void @f_agg_large_ret(%struct.large* noalias sret(%struct.large) align 8 %agg.result, i32 signext %i, i8 signext %j) struct large f_agg_large_ret(int32_t i, int8_t j) { return (struct large){1, 2, 3, 4}; } typedef unsigned char v32i8 __attribute__((vector_size(32))); -// CHECK-LABEL: define{{.*}} void @f_vec_large_v32i8(<32 x i8>* noundef %0) +// CHECK-LABEL: define{{.*}} void @f_vec_large_v32i8(<32 x i8>* %0) void f_vec_large_v32i8(v32i8 x) { x[0] = x[7]; } @@ -186,13 +186,13 @@ v32i8 f_vec_large_v32i8_ret() { // Scalars passed on the stack should not have signext/zeroext attributes // (they are anyext). -// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_1(i64 %a.coerce, [2 x i64] %b.coerce, i128 %c.coerce, %struct.large* noundef %d, i8 noundef zeroext %e, i8 noundef signext %f, i8 noundef %g, i8 noundef %h) +// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_1(i64 %a.coerce, [2 x i64] %b.coerce, i128 %c.coerce, %struct.large* %d, i8 zeroext %e, i8 signext %f, i8 %g, i8 %h) int f_scalar_stack_1(struct tiny a, struct small b, struct small_aligned c, struct large d, uint8_t e, int8_t f, uint8_t g, int8_t h) { return g + h; } -// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_2(i32 noundef signext %a, i128 noundef %b, i64 noundef %c, fp128 noundef %d, <32 x i8>* noundef %0, i8 noundef zeroext %f, i8 noundef %g, i8 noundef %h) +// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_2(i32 signext %a, i128 %b, i64 %c, fp128 %d, <32 x i8>* %0, i8 zeroext %f, i8 %g, i8 %h) int f_scalar_stack_2(int32_t a, __int128_t b, int64_t c, long double d, v32i8 e, uint8_t f, int8_t g, uint8_t h) { return g + h; @@ -202,7 +202,7 @@ int f_scalar_stack_2(int32_t a, __int128_t b, int64_t c, long double d, v32i8 e, // the presence of large return values that consume a register due to the need // to pass a pointer. -// CHECK-LABEL: define{{.*}} void @f_scalar_stack_3(%struct.large* noalias sret(%struct.large) align 8 %agg.result, i32 noundef signext %a, i128 noundef %b, fp128 noundef %c, <32 x i8>* noundef %0, i8 noundef zeroext %e, i8 noundef %f, i8 noundef %g) +// CHECK-LABEL: define{{.*}} void @f_scalar_stack_3(%struct.large* noalias sret(%struct.large) align 8 %agg.result, i32 signext %a, i128 %b, fp128 %c, <32 x i8>* %0, i8 zeroext %e, i8 %f, i8 %g) struct large f_scalar_stack_3(uint32_t a, __int128_t b, long double c, v32i8 d, uint8_t e, int8_t f, uint8_t g) { return (struct large){a, e, f, g}; @@ -217,31 +217,31 @@ int f_va_callee(int, ...); // CHECK-LABEL: define{{.*}} void @f_va_caller() void f_va_caller() { - // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i64 noundef 3, double noundef 4.000000e+00, double noundef 5.000000e+00, i64 {{%.*}}, [2 x i64] {{%.*}}, i128 {{%.*}}, %struct.large* noundef {{%.*}}) + // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i64 3, double 4.000000e+00, double 5.000000e+00, i64 {{%.*}}, [2 x i64] {{%.*}}, i128 {{%.*}}, %struct.large* {{%.*}}) f_va_callee(1, 2, 3LL, 4.0f, 5.0, (struct tiny){6, 7, 8, 9}, (struct small){10, NULL}, (struct small_aligned){11}, (struct large){12, 13, 14, 15}); - // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, fp128 noundef 0xL00000000000000004001400000000000, i32 noundef signext 6, i32 noundef signext 7, i32 noundef 8, i32 noundef 9) + // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, fp128 0xL00000000000000004001400000000000, i32 signext 6, i32 signext 7, i32 8, i32 9) f_va_callee(1, 2, 3, 4, 5.0L, 6, 7, 8, 9); - // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i128 {{%.*}}, i32 noundef signext 6, i32 noundef signext 7, i32 noundef 8, i32 noundef 9) + // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, i128 {{%.*}}, i32 signext 6, i32 signext 7, i32 8, i32 9) f_va_callee(1, 2, 3, 4, (struct small_aligned){5}, 6, 7, 8, 9); - // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, [2 x i64] {{%.*}}, i32 noundef signext 6, i32 noundef signext 7, i32 noundef 8, i32 noundef 9) + // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, [2 x i64] {{%.*}}, i32 signext 6, i32 signext 7, i32 8, i32 9) f_va_callee(1, 2, 3, 4, (struct small){5, NULL}, 6, 7, 8, 9); - // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, fp128 noundef 0xL00000000000000004001800000000000, i32 noundef 7, i32 noundef 8, i32 noundef 9) + // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, i32 signext 5, fp128 0xL00000000000000004001800000000000, i32 7, i32 8, i32 9) f_va_callee(1, 2, 3, 4, 5, 6.0L, 7, 8, 9); - // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, i128 {{%.*}}, i32 noundef 7, i32 noundef 8, i32 noundef 9) + // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, i32 signext 5, i128 {{%.*}}, i32 7, i32 8, i32 9) f_va_callee(1, 2, 3, 4, 5, (struct small_aligned){6}, 7, 8, 9); - // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, [2 x i64] {{%.*}}, i32 noundef signext 7, i32 noundef 8, i32 noundef 9) + // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, i32 signext 5, [2 x i64] {{%.*}}, i32 signext 7, i32 8, i32 9) f_va_callee(1, 2, 3, 4, 5, (struct small){6, NULL}, 7, 8, 9); - // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, i32 noundef signext 6, fp128 noundef 0xL00000000000000004001C00000000000, i32 noundef 8, i32 noundef 9) + // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, i32 signext 5, i32 signext 6, fp128 0xL00000000000000004001C00000000000, i32 8, i32 9) f_va_callee(1, 2, 3, 4, 5, 6, 7.0L, 8, 9); - // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, i32 noundef signext 6, i128 {{%.*}}, i32 noundef 8, i32 noundef 9) + // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, i32 signext 5, i32 signext 6, i128 {{%.*}}, i32 8, i32 9) f_va_callee(1, 2, 3, 4, 5, 6, (struct small_aligned){7}, 8, 9); - // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, i32 noundef signext 6, [2 x i64] {{.*}}, i32 noundef 8, i32 noundef 9) + // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, i32 signext 5, i32 signext 6, [2 x i64] {{.*}}, i32 8, i32 9) f_va_callee(1, 2, 3, 4, 5, 6, (struct small){7, NULL}, 8, 9); } -// CHECK-LABEL: define{{.*}} signext i32 @f_va_1(i8* noundef %fmt, ...) {{.*}} { +// CHECK-LABEL: define{{.*}} signext i32 @f_va_1(i8* %fmt, ...) {{.*}} { // CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 8 // CHECK: [[VA:%.*]] = alloca i8*, align 8 // CHECK: [[V:%.*]] = alloca i32, align 4 diff --git a/clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c b/clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c index a057cf82bae2f1a7f44d7307cd07c250b6786ea8..a25116f836fd4a7fb45a5db5af75fcdee97e5979 100644 --- a/clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c +++ b/clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c @@ -9,7 +9,7 @@ // Doubles are passed in FPRs, so argument 'i' will be passed zero-extended // because it will be passed in a GPR. -// CHECK: define{{.*}} void @f_fpr_tracking(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, i8 noundef zeroext %i) +// CHECK: define{{.*}} void @f_fpr_tracking(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, i8 zeroext %i) void f_fpr_tracking(double a, double b, double c, double d, double e, double f, double g, double h, uint8_t i) {} @@ -77,7 +77,7 @@ struct double_float_s f_ret_double_float_s() { return (struct double_float_s){1.0, 2.0}; } -// CHECK: define{{.*}} void @f_double_double_s_arg_insufficient_fprs(float noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, [2 x i64] %h.coerce) +// CHECK: define{{.*}} void @f_double_double_s_arg_insufficient_fprs(float %a, double %b, double %c, double %d, double %e, double %f, double %g, [2 x i64] %h.coerce) void f_double_double_s_arg_insufficient_fprs(float a, double b, double c, double d, double e, double f, double g, struct double_double_s h) {} @@ -143,18 +143,18 @@ struct double_int8_zbf_s f_ret_double_int8_zbf_s() { return (struct double_int8_zbf_s){1.0, 2}; } -// CHECK: define{{.*}} void @f_double_int8_s_arg_insufficient_gprs(i32 noundef signext %a, i32 noundef signext %b, i32 noundef signext %c, i32 noundef signext %d, i32 noundef signext %e, i32 noundef signext %f, i32 noundef signext %g, i32 noundef signext %h, [2 x i64] %i.coerce) +// CHECK: define{{.*}} void @f_double_int8_s_arg_insufficient_gprs(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e, i32 signext %f, i32 signext %g, i32 signext %h, [2 x i64] %i.coerce) void f_double_int8_s_arg_insufficient_gprs(int a, int b, int c, int d, int e, int f, int g, int h, struct double_int8_s i) {} -// CHECK: define{{.*}} void @f_struct_double_int8_insufficient_fprs(float noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, [2 x i64] %i.coerce) +// CHECK: define{{.*}} void @f_struct_double_int8_insufficient_fprs(float %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, [2 x i64] %i.coerce) void f_struct_double_int8_insufficient_fprs(float a, double b, double c, double d, double e, double f, double g, double h, struct double_int8_s i) {} // Complex floating-point values or structs containing a single complex // floating-point value should be passed as if it were an fp+fp struct. -// CHECK: define{{.*}} void @f_doublecomplex(double noundef %a.coerce0, double noundef %a.coerce1) +// CHECK: define{{.*}} void @f_doublecomplex(double %a.coerce0, double %a.coerce1) void f_doublecomplex(double __complex__ a) {} // CHECK: define{{.*}} { double, double } @f_ret_doublecomplex() @@ -240,7 +240,7 @@ struct doublearr2_tricky4_s f_ret_doublearr2_tricky4_s() { struct int_double_int_s { int a; double b; int c; }; -// CHECK: define{{.*}} void @f_int_double_int_s_arg(%struct.int_double_int_s* noundef %a) +// CHECK: define{{.*}} void @f_int_double_int_s_arg(%struct.int_double_int_s* %a) void f_int_double_int_s_arg(struct int_double_int_s a) {} // CHECK: define{{.*}} void @f_ret_int_double_int_s(%struct.int_double_int_s* noalias sret(%struct.int_double_int_s) align 8 %agg.result) diff --git a/clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c b/clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c index 7ffacdeae0da67c7480c6cb1f8d922682dfc337d..b3a2645f4b06032cc7ba787f486b365ae9edaeab 100644 --- a/clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c +++ b/clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c @@ -11,7 +11,7 @@ // Floats are passed in FPRs, so argument 'i' will be passed zero-extended // because it will be passed in a GPR. -// CHECK: define{{.*}} void @f_fpr_tracking(float noundef %a, float noundef %b, float noundef %c, float noundef %d, float noundef %e, float noundef %f, float noundef %g, float noundef %h, i8 noundef zeroext %i) +// CHECK: define{{.*}} void @f_fpr_tracking(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, i8 zeroext %i) void f_fpr_tracking(float a, float b, float c, float d, float e, float f, float g, float h, uint8_t i) {} @@ -70,7 +70,7 @@ struct float_float_s f_ret_float_float_s() { return (struct float_float_s){1.0, 2.0}; } -// CHECK: define{{.*}} void @f_float_float_s_arg_insufficient_fprs(float noundef %a, float noundef %b, float noundef %c, float noundef %d, float noundef %e, float noundef %f, float noundef %g, i64 %h.coerce) +// CHECK: define{{.*}} void @f_float_float_s_arg_insufficient_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, i64 %h.coerce) void f_float_float_s_arg_insufficient_fprs(float a, float b, float c, float d, float e, float f, float g, struct float_float_s h) {} @@ -136,18 +136,18 @@ struct float_int8_zbf_s f_ret_float_int8_zbf_s() { return (struct float_int8_zbf_s){1.0, 2}; } -// CHECK: define{{.*}} void @f_float_int8_s_arg_insufficient_gprs(i32 noundef signext %a, i32 noundef signext %b, i32 noundef signext %c, i32 noundef signext %d, i32 noundef signext %e, i32 noundef signext %f, i32 noundef signext %g, i32 noundef signext %h, i64 %i.coerce) +// CHECK: define{{.*}} void @f_float_int8_s_arg_insufficient_gprs(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e, i32 signext %f, i32 signext %g, i32 signext %h, i64 %i.coerce) void f_float_int8_s_arg_insufficient_gprs(int a, int b, int c, int d, int e, int f, int g, int h, struct float_int8_s i) {} -// CHECK: define{{.*}} void @f_struct_float_int8_insufficient_fprs(float noundef %a, float noundef %b, float noundef %c, float noundef %d, float noundef %e, float noundef %f, float noundef %g, float noundef %h, i64 %i.coerce) +// CHECK: define{{.*}} void @f_struct_float_int8_insufficient_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, i64 %i.coerce) void f_struct_float_int8_insufficient_fprs(float a, float b, float c, float d, float e, float f, float g, float h, struct float_int8_s i) {} // Complex floating-point values or structs containing a single complex // floating-point value should be passed as if it were an fp+fp struct. -// CHECK: define{{.*}} void @f_floatcomplex(float noundef %a.coerce0, float noundef %a.coerce1) +// CHECK: define{{.*}} void @f_floatcomplex(float %a.coerce0, float %a.coerce1) void f_floatcomplex(float __complex__ a) {} // CHECK: define{{.*}} { float, float } @f_ret_floatcomplex() @@ -168,7 +168,7 @@ struct floatcomplex_s f_ret_floatcomplex_s() { // Complex floating-point values or structs containing a single complex // floating-point value should be passed in GPRs if no two FPRs is available. -// CHECK: define{{.*}} void @f_floatcomplex_insufficient_fprs1(float noundef %a.coerce0, float noundef %a.coerce1, float noundef %b.coerce0, float noundef %b.coerce1, float noundef %c.coerce0, float noundef %c.coerce1, float noundef %d.coerce0, float noundef %d.coerce1, i64 noundef %e.coerce) +// CHECK: define{{.*}} void @f_floatcomplex_insufficient_fprs1(float %a.coerce0, float %a.coerce1, float %b.coerce0, float %b.coerce1, float %c.coerce0, float %c.coerce1, float %d.coerce0, float %d.coerce1, i64 %e.coerce) void f_floatcomplex_insufficient_fprs1(float __complex__ a, float __complex__ b, float __complex__ c, float __complex__ d, float __complex__ e) {} @@ -181,13 +181,13 @@ void f_floatcomplex_s_arg_insufficient_fprs1(struct floatcomplex_s a, struct floatcomplex_s d, struct floatcomplex_s e) {} -// CHECK: define{{.*}} void @f_floatcomplex_insufficient_fprs2(float noundef %a, float noundef %b.coerce0, float noundef %b.coerce1, float noundef %c.coerce0, float noundef %c.coerce1, float noundef %d.coerce0, float noundef %d.coerce1, i64 noundef %e.coerce) +// CHECK: define{{.*}} void @f_floatcomplex_insufficient_fprs2(float %a, float %b.coerce0, float %b.coerce1, float %c.coerce0, float %c.coerce1, float %d.coerce0, float %d.coerce1, i64 %e.coerce) void f_floatcomplex_insufficient_fprs2(float a, float __complex__ b, float __complex__ c, float __complex__ d, float __complex__ e) {} -// CHECK: define{{.*}} void @f_floatcomplex_s_arg_insufficient_fprs2(float noundef %a, float %0, float %1, float %2, float %3, float %4, float %5, i64 %e.coerce) +// CHECK: define{{.*}} void @f_floatcomplex_s_arg_insufficient_fprs2(float %a, float %0, float %1, float %2, float %3, float %4, float %5, i64 %e.coerce) void f_floatcomplex_s_arg_insufficient_fprs2(float a, struct floatcomplex_s b, struct floatcomplex_s c, diff --git a/clang/test/CodeGen/SystemZ/systemz-abi-vector.c b/clang/test/CodeGen/SystemZ/systemz-abi-vector.c index fa85074981c5d9026cfddec822791a8608e710d4..43027b0a3cbb45f430b3f58739fb8d5b28720a7c 100644 --- a/clang/test/CodeGen/SystemZ/systemz-abi-vector.c +++ b/clang/test/CodeGen/SystemZ/systemz-abi-vector.c @@ -1,20 +1,20 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu \ +// RUN: %clang_cc1 -triple s390x-linux-gnu \ // RUN: -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-feature +vector \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-feature +vector \ // RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu z13 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z13 \ // RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch11 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch11 \ // RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu z14 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z14 \ // RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch12 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch12 \ // RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu z15 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z15 \ // RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch13 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch13 \ // RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch14 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch14 \ // RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s // Vector types diff --git a/clang/test/CodeGen/SystemZ/systemz-abi.c b/clang/test/CodeGen/SystemZ/systemz-abi.c index 1755de3a87e92e263ba71985f665793efba7f3bd..a287fe1d04c8d542f48216fdccb213f5615fbd93 100644 --- a/clang/test/CodeGen/SystemZ/systemz-abi.c +++ b/clang/test/CodeGen/SystemZ/systemz-abi.c @@ -1,25 +1,25 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu \ +// RUN: %clang_cc1 -triple s390x-linux-gnu \ // RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-feature +vector \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-feature +vector \ // RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu z13 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z13 \ // RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch11 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch11 \ // RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu z14 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z14 \ // RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch12 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch12 \ // RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu z15 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z15 \ // RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch13 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch13 \ // RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch13 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch13 \ // RUN: -emit-llvm -o - %s -mfloat-abi soft | FileCheck %s \ // RUN: --check-prefixes=CHECK,SOFT-FLOAT -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch14 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch14 \ // RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT -// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch14 \ +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch14 \ // RUN: -emit-llvm -o - %s -mfloat-abi soft | FileCheck %s \ // RUN: --check-prefixes=CHECK,SOFT-FLOAT diff --git a/clang/test/CodeGen/SystemZ/systemz-inline-asm.c b/clang/test/CodeGen/SystemZ/systemz-inline-asm.c index 2040d318a6ac0c5df461b37066f58e82f3206cdc..0994b11825fe8a3667c78f06e77756729cf5bc4a 100644 --- a/clang/test/CodeGen/SystemZ/systemz-inline-asm.c +++ b/clang/test/CodeGen/SystemZ/systemz-inline-asm.c @@ -5,31 +5,31 @@ unsigned long gl; void test_store_m(unsigned int i) { asm("st %1, %0" : "=m" (gi) : "r" (i)); -// CHECK-LABEL: define{{.*}} void @test_store_m(i32 noundef zeroext %i) +// CHECK-LABEL: define{{.*}} void @test_store_m(i32 zeroext %i) // CHECK: call void asm "st $1, $0", "=*m,r"(i32* nonnull @gi, i32 %i) } void test_store_Q(unsigned int i) { asm("st %1, %0" : "=Q" (gi) : "r" (i)); -// CHECK-LABEL: define{{.*}} void @test_store_Q(i32 noundef zeroext %i) +// CHECK-LABEL: define{{.*}} void @test_store_Q(i32 zeroext %i) // CHECK: call void asm "st $1, $0", "=*Q,r"(i32* nonnull @gi, i32 %i) } void test_store_R(unsigned int i) { asm("st %1, %0" : "=R" (gi) : "r" (i)); -// CHECK-LABEL: define{{.*}} void @test_store_R(i32 noundef zeroext %i) +// CHECK-LABEL: define{{.*}} void @test_store_R(i32 zeroext %i) // CHECK: call void asm "st $1, $0", "=*R,r"(i32* nonnull @gi, i32 %i) } void test_store_S(unsigned int i) { asm("st %1, %0" : "=S" (gi) : "r" (i)); -// CHECK-LABEL: define{{.*}} void @test_store_S(i32 noundef zeroext %i) +// CHECK-LABEL: define{{.*}} void @test_store_S(i32 zeroext %i) // CHECK: call void asm "st $1, $0", "=*S,r"(i32* nonnull @gi, i32 %i) } void test_store_T(unsigned int i) { asm("st %1, %0" : "=T" (gi) : "r" (i)); -// CHECK-LABEL: define{{.*}} void @test_store_T(i32 noundef zeroext %i) +// CHECK-LABEL: define{{.*}} void @test_store_T(i32 zeroext %i) // CHECK: call void asm "st $1, $0", "=*T,r"(i32* nonnull @gi, i32 %i) } @@ -75,28 +75,28 @@ int test_load_T() { void test_mI(unsigned char *c) { asm volatile("cli %0, %1" :: "Q" (*c), "I" (100)); -// CHECK-LABEL: define{{.*}} void @test_mI(i8* noundef %c) +// CHECK-LABEL: define{{.*}} void @test_mI(i8* %c) // CHECK: call void asm sideeffect "cli $0, $1", "*Q,I"(i8* %c, i32 100) } unsigned int test_dJa(unsigned int i, unsigned int j) { asm("sll %0, %2(%3)" : "=d" (i) : "0" (i), "J" (1000), "a" (j)); return i; -// CHECK-LABEL: define{{.*}} zeroext i32 @test_dJa(i32 noundef zeroext %i, i32 noundef zeroext %j) +// CHECK-LABEL: define{{.*}} zeroext i32 @test_dJa(i32 zeroext %i, i32 zeroext %j) // CHECK: call i32 asm "sll $0, $2($3)", "=d,0,J,a"(i32 %i, i32 1000, i32 %j) } unsigned long test_rK(unsigned long i) { asm("aghi %0, %2" : "=r" (i) : "0" (i), "K" (-30000)); return i; -// CHECK-LABEL: define{{.*}} i64 @test_rK(i64 noundef %i) +// CHECK-LABEL: define{{.*}} i64 @test_rK(i64 %i) // CHECK: call i64 asm "aghi $0, $2", "=r,0,K"(i64 %i, i32 -30000) } unsigned long test_rL(unsigned long i) { asm("sllg %0, %1, %2" : "=r" (i) : "r" (i), "L" (500000)); return i; -// CHECK-LABEL: define{{.*}} i64 @test_rL(i64 noundef %i) +// CHECK-LABEL: define{{.*}} i64 @test_rL(i64 %i) // CHECK: call i64 asm "sllg $0, $1, $2", "=r,r,L"(i64 %i, i32 500000) } @@ -109,21 +109,21 @@ void test_M() { float test_f32(float f, float g) { asm("aebr %0, %2" : "=f" (f) : "0" (f), "f" (g)); return f; -// CHECK-LABEL: define{{.*}} float @test_f32(float noundef %f, float noundef %g) +// CHECK-LABEL: define{{.*}} float @test_f32(float %f, float %g) // CHECK: call float asm "aebr $0, $2", "=f,0,f"(float %f, float %g) } double test_f64(double f, double g) { asm("adbr %0, %2" : "=f" (f) : "0" (f), "f" (g)); return f; -// CHECK-LABEL: define{{.*}} double @test_f64(double noundef %f, double noundef %g) +// CHECK-LABEL: define{{.*}} double @test_f64(double %f, double %g) // CHECK: call double asm "adbr $0, $2", "=f,0,f"(double %f, double %g) } long double test_f128(long double f, long double g) { asm("axbr %0, %2" : "=f" (f) : "0" (f), "f" (g)); return f; -// CHECK: define{{.*}} void @test_f128(fp128* noalias nocapture sret(fp128) align 8 [[DEST:%.*]], fp128* nocapture noundef readonly %0, fp128* nocapture noundef readonly %1) +// CHECK: define{{.*}} void @test_f128(fp128* noalias nocapture sret(fp128) align 8 [[DEST:%.*]], fp128* nocapture readonly %0, fp128* nocapture readonly %1) // CHECK: %f = load fp128, fp128* %0 // CHECK: %g = load fp128, fp128* %1 // CHECK: [[RESULT:%.*]] = tail call fp128 asm "axbr $0, $2", "=f,0,f"(fp128 %f, fp128 %g) diff --git a/clang/test/CodeGen/WebAssembly/wasm-arguments.c b/clang/test/CodeGen/WebAssembly/wasm-arguments.c index 04b19749119ddf9583aef1e39fda98f0d1af79ac..13700b50b5bd86b7fbd2c8577b3a2ea908194156 100644 --- a/clang/test/CodeGen/WebAssembly/wasm-arguments.c +++ b/clang/test/CodeGen/WebAssembly/wasm-arguments.c @@ -7,8 +7,8 @@ // Basic argument/attribute and return tests for WebAssembly -// WEBASSEMBLY32: define void @misc_args(i32 noundef %i, i32 noundef %j, i64 noundef %k, double noundef %l, fp128 noundef %m) -// WEBASSEMBLY64: define void @misc_args(i32 noundef %i, i64 noundef %j, i64 noundef %k, double noundef %l, fp128 noundef %m) +// WEBASSEMBLY32: define void @misc_args(i32 %i, i32 %j, i64 %k, double %l, fp128 %m) +// WEBASSEMBLY64: define void @misc_args(i32 %i, i64 %j, i64 %k, double %l, fp128 %m) void misc_args(int i, long j, long long k, double l, long double m) {} typedef struct { @@ -17,8 +17,8 @@ typedef struct { } s1; // Structs should be passed byval and not split up. -// WEBASSEMBLY32: define void @struct_arg(%struct.s1* noundef byval(%struct.s1) align 4 %i) -// WEBASSEMBLY64: define void @struct_arg(%struct.s1* noundef byval(%struct.s1) align 4 %i) +// WEBASSEMBLY32: define void @struct_arg(%struct.s1* byval(%struct.s1) align 4 %i) +// WEBASSEMBLY64: define void @struct_arg(%struct.s1* byval(%struct.s1) align 4 %i) // Except in the experimental multivalue ABI, where structs are passed in args // EXPERIMENTAL-MV: define void @struct_arg(i32 %i.0, i32 %i.1) @@ -58,17 +58,17 @@ s2 single_elem_ret() { return foo; } -// WEBASSEMBLY32: define void @long_long_arg(i64 noundef %i) -// WEBASSEMBLY64: define void @long_long_arg(i64 noundef %i) +// WEBASSEMBLY32: define void @long_long_arg(i64 %i) +// WEBASSEMBLY64: define void @long_long_arg(i64 %i) void long_long_arg(long long i) {} // i8/i16 should be signext, i32 and higher should not. -// WEBASSEMBLY32: define void @char_short_arg(i8 noundef signext %a, i16 noundef signext %b) -// WEBASSEMBLY64: define void @char_short_arg(i8 noundef signext %a, i16 noundef signext %b) +// WEBASSEMBLY32: define void @char_short_arg(i8 signext %a, i16 signext %b) +// WEBASSEMBLY64: define void @char_short_arg(i8 signext %a, i16 signext %b) void char_short_arg(char a, short b) {} -// WEBASSEMBLY32: define void @uchar_ushort_arg(i8 noundef zeroext %a, i16 noundef zeroext %b) -// WEBASSEMBLY64: define void @uchar_ushort_arg(i8 noundef zeroext %a, i16 noundef zeroext %b) +// WEBASSEMBLY32: define void @uchar_ushort_arg(i8 zeroext %a, i16 zeroext %b) +// WEBASSEMBLY64: define void @uchar_ushort_arg(i8 zeroext %a, i16 zeroext %b) void uchar_ushort_arg(unsigned char a, unsigned short b) {} enum my_enum { @@ -78,8 +78,8 @@ enum my_enum { }; // Enums should be treated as the underlying i32. -// WEBASSEMBLY32: define void @enum_arg(i32 noundef %a) -// WEBASSEMBLY64: define void @enum_arg(i32 noundef %a) +// WEBASSEMBLY32: define void @enum_arg(i32 %a) +// WEBASSEMBLY64: define void @enum_arg(i32 %a) void enum_arg(enum my_enum a) {} enum my_big_enum { @@ -87,8 +87,8 @@ enum my_big_enum { }; // Big enums should be treated as the underlying i64. -// WEBASSEMBLY32: define void @big_enum_arg(i64 noundef %a) -// WEBASSEMBLY64: define void @big_enum_arg(i64 noundef %a) +// WEBASSEMBLY32: define void @big_enum_arg(i64 %a) +// WEBASSEMBLY64: define void @big_enum_arg(i64 %a) void big_enum_arg(enum my_big_enum a) {} union simple_union { @@ -97,8 +97,8 @@ union simple_union { }; // Unions should be passed as byval structs. -// WEBASSEMBLY32: define void @union_arg(%union.simple_union* noundef byval(%union.simple_union) align 4 %s) -// WEBASSEMBLY64: define void @union_arg(%union.simple_union* noundef byval(%union.simple_union) align 4 %s) +// WEBASSEMBLY32: define void @union_arg(%union.simple_union* byval(%union.simple_union) align 4 %s) +// WEBASSEMBLY64: define void @union_arg(%union.simple_union* byval(%union.simple_union) align 4 %s) // EXPERIMENTAL-MV: define void @union_arg(i32 %s.0) void union_arg(union simple_union s) {} @@ -123,9 +123,9 @@ typedef struct { } bitfield1; // Bitfields should be passed as byval structs. -// WEBASSEMBLY32: define void @bitfield_arg(%struct.bitfield1* noundef byval(%struct.bitfield1) align 4 %bf1) -// WEBASSEMBLY64: define void @bitfield_arg(%struct.bitfield1* noundef byval(%struct.bitfield1) align 4 %bf1) -// EXPERIMENTAL-MV: define void @bitfield_arg(%struct.bitfield1* noundef byval(%struct.bitfield1) align 4 %bf1) +// WEBASSEMBLY32: define void @bitfield_arg(%struct.bitfield1* byval(%struct.bitfield1) align 4 %bf1) +// WEBASSEMBLY64: define void @bitfield_arg(%struct.bitfield1* byval(%struct.bitfield1) align 4 %bf1) +// EXPERIMENTAL-MV: define void @bitfield_arg(%struct.bitfield1* byval(%struct.bitfield1) align 4 %bf1) void bitfield_arg(bitfield1 bf1) {} // And returned via sret pointers. diff --git a/clang/test/CodeGen/WebAssembly/wasm-main_argc_argv.c b/clang/test/CodeGen/WebAssembly/wasm-main_argc_argv.c index 54b30101ff0f4e28b7586e1b3a7fa8bf089df90d..194afc2fd5af94e284058fef618b27a7a33f1964 100644 --- a/clang/test/CodeGen/WebAssembly/wasm-main_argc_argv.c +++ b/clang/test/CodeGen/WebAssembly/wasm-main_argc_argv.c @@ -6,4 +6,4 @@ int main(int argc, char **argv) { return 0; } -// CHECK-LABEL: define i32 @__main_argc_argv(i32 noundef %argc, i8** noundef %argv) +// CHECK-LABEL: define i32 @__main_argc_argv(i32 %argc, i8** %argv) diff --git a/clang/test/CodeGen/X86/avx-union.c b/clang/test/CodeGen/X86/avx-union.c index 2c4525f4f207480eaf8b5bbd9456546b9fa75b60..43b2ad26ba68782e363c21e0d59cbd110c465445 100644 --- a/clang/test/CodeGen/X86/avx-union.c +++ b/clang/test/CodeGen/X86/avx-union.c @@ -27,10 +27,10 @@ union M256 m1; union M512 m2; // CHECK-LABEL: define{{.*}} void @test() // CHECK: call void @foo1(<4 x double> -// CHECK-LEGACY: call void @foo1(%union.M256* noundef byval(%union.M256) align 32 -// AVX: call void @foo2(%union.M512* noundef byval(%union.M512) align 64 +// CHECK-LEGACY: call void @foo1(%union.M256* byval(%union.M256) align 32 +// AVX: call void @foo2(%union.M512* byval(%union.M512) align 64 // AVX512: call void @foo2(<8 x double> -// AVX512-LEGACY: call void @foo2(%union.M512* noundef byval(%union.M512) align 64 +// AVX512-LEGACY: call void @foo2(%union.M512* byval(%union.M512) align 64 void test() { foo1(m1); foo2(m2); diff --git a/clang/test/CodeGen/X86/avx512fp16-complex-abi.c b/clang/test/CodeGen/X86/avx512fp16-complex-abi.c index bd4d05517a7e4f09c82d2de1d9e3d82c50f261f8..066f8a89b8590f3210b85c1d2d190681c220048e 100644 --- a/clang/test/CodeGen/X86/avx512fp16-complex-abi.c +++ b/clang/test/CodeGen/X86/avx512fp16-complex-abi.c @@ -2,6 +2,6 @@ // Return value should be passed in <2 x half> so the backend will use xmm0 _Complex _Float16 f16(_Complex _Float16 A, _Complex _Float16 B) { - // CHECK-LABEL: define{{.*}}<2 x half> @f16({ half, half }* noundef byval({ half, half }) align 4 %{{.*}}, { half, half }* noundef byval({ half, half }) align 4 %{{.*}}) + // CHECK-LABEL: define{{.*}}<2 x half> @f16({ half, half }* byval({ half, half }) align 4 %{{.*}}, { half, half }* byval({ half, half }) align 4 %{{.*}}) return A + B; } diff --git a/clang/test/CodeGen/X86/avx512fp16-complex.c b/clang/test/CodeGen/X86/avx512fp16-complex.c index 8e66cf8ab9e8d8aea85492e70aba6375a1411fe2..8a6b50eb0056bef3cb708eadc0600d8ba328ba60 100644 --- a/clang/test/CodeGen/X86/avx512fp16-complex.c +++ b/clang/test/CodeGen/X86/avx512fp16-complex.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -O0 -fno-experimental-new-pass-manager -emit-llvm -triple x86_64-unknown-unknown -target-feature +avx512fp16 -o - | FileCheck %s --check-prefix=X86 +// RUN: %clang_cc1 %s -O0 -emit-llvm -triple x86_64-unknown-unknown -target-feature +avx512fp16 -o - | FileCheck %s --check-prefix=X86 _Float16 _Complex add_half_rr(_Float16 a, _Float16 b) { // X86-LABEL: @add_half_rr( diff --git a/clang/test/CodeGen/X86/builtin-movdir.c b/clang/test/CodeGen/X86/builtin-movdir.c index f1f104db87b4afdbe9f95c3eb2e64b3468c63616..d2bc7485ee32b2de19ed476287df51a7d656d79a 100644 --- a/clang/test/CodeGen/X86/builtin-movdir.c +++ b/clang/test/CodeGen/X86/builtin-movdir.c @@ -1,7 +1,5 @@ -// RUN: %clang_cc1 -ffreestanding -Wall -pedantic -fno-experimental-new-pass-manager -triple x86_64-unknown-unknown -target-feature +movdiri -target-feature +movdir64b %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,X86_64 -// RUN: %clang_cc1 -ffreestanding -Wall -pedantic -fno-experimental-new-pass-manager -triple i386-unknown-unknown -target-feature +movdiri -target-feature +movdir64b %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK -// RUN: %clang_cc1 -ffreestanding -Wall -pedantic -fexperimental-new-pass-manager -triple x86_64-unknown-unknown -target-feature +movdiri -target-feature +movdir64b %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,X86_64 -// RUN: %clang_cc1 -ffreestanding -Wall -pedantic -fexperimental-new-pass-manager -triple i386-unknown-unknown -target-feature +movdiri -target-feature +movdir64b %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK +// RUN: %clang_cc1 -ffreestanding -Wall -pedantic -triple x86_64-unknown-unknown -target-feature +movdiri -target-feature +movdir64b %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,X86_64 +// RUN: %clang_cc1 -ffreestanding -Wall -pedantic -triple i386-unknown-unknown -target-feature +movdiri -target-feature +movdir64b %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK #include #include diff --git a/clang/test/CodeGen/X86/ms-x86-intrinsics.c b/clang/test/CodeGen/X86/ms-x86-intrinsics.c index 89bb1c5fc497d0c0427e14a7822ab37350cfa069..0eca455bb5c32347dc7b802319637f04b0b55553 100644 --- a/clang/test/CodeGen/X86/ms-x86-intrinsics.c +++ b/clang/test/CodeGen/X86/ms-x86-intrinsics.c @@ -11,7 +11,7 @@ char test__readfsbyte(unsigned long Offset) { return __readfsbyte(++Offset); } -// CHECK-I386-LABEL: define dso_local signext i8 @test__readfsbyte(i32 noundef %Offset) +// CHECK-I386-LABEL: define dso_local signext i8 @test__readfsbyte(i32 %Offset) // CHECK-I386: %inc = add i32 %Offset, 1 // CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to i8 addrspace(257)* // CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i8, i8 addrspace(257)* [[PTR]], align 1 @@ -20,7 +20,7 @@ char test__readfsbyte(unsigned long Offset) { short test__readfsword(unsigned long Offset) { return __readfsword(++Offset); } -// CHECK-I386-LABEL: define dso_local signext i16 @test__readfsword(i32 noundef %Offset) +// CHECK-I386-LABEL: define dso_local signext i16 @test__readfsword(i32 %Offset) // CHECK-I386: %inc = add i32 %Offset, 1 // CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to i16 addrspace(257)* // CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i16, i16 addrspace(257)* [[PTR]], align 2 @@ -29,7 +29,7 @@ short test__readfsword(unsigned long Offset) { long test__readfsdword(unsigned long Offset) { return __readfsdword(++Offset); } -// CHECK-I386-LABEL: define dso_local i32 @test__readfsdword(i32 noundef %Offset) +// CHECK-I386-LABEL: define dso_local i32 @test__readfsdword(i32 %Offset) // CHECK-I386: %inc = add i32 %Offset, 1 // CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to i32 addrspace(257)* // CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i32, i32 addrspace(257)* [[PTR]], align 4 @@ -38,7 +38,7 @@ long test__readfsdword(unsigned long Offset) { long long test__readfsqword(unsigned long Offset) { return __readfsqword(++Offset); } -// CHECK-I386-LABEL: define dso_local i64 @test__readfsqword(i32 noundef %Offset) +// CHECK-I386-LABEL: define dso_local i64 @test__readfsqword(i32 %Offset) // CHECK-I386: %inc = add i32 %Offset, 1 // CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to i64 addrspace(257)* // CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i64, i64 addrspace(257)* [[PTR]], align 8 @@ -48,7 +48,7 @@ long long test__readfsqword(unsigned long Offset) { __int64 test__emul(int a, int b) { return __emul(a, b); } -// CHECK-LABEL: define dso_local i64 @test__emul(i32 noundef %a, i32 noundef %b) +// CHECK-LABEL: define dso_local i64 @test__emul(i32 %a, i32 %b) // CHECK: [[X:%[0-9]+]] = sext i32 %a to i64 // CHECK: [[Y:%[0-9]+]] = sext i32 %b to i64 // CHECK: [[RES:%[0-9]+]] = mul nsw i64 [[Y]], [[X]] @@ -57,7 +57,7 @@ __int64 test__emul(int a, int b) { unsigned __int64 test__emulu(unsigned int a, unsigned int b) { return __emulu(a, b); } -// CHECK-LABEL: define dso_local i64 @test__emulu(i32 noundef %a, i32 noundef %b) +// CHECK-LABEL: define dso_local i64 @test__emulu(i32 %a, i32 %b) // CHECK: [[X:%[0-9]+]] = zext i32 %a to i64 // CHECK: [[Y:%[0-9]+]] = zext i32 %b to i64 // CHECK: [[RES:%[0-9]+]] = mul nuw i64 [[Y]], [[X]] @@ -68,7 +68,7 @@ unsigned __int64 test__emulu(unsigned int a, unsigned int b) { char test__readgsbyte(unsigned long Offset) { return __readgsbyte(++Offset); } -// CHECK-X64-LABEL: define dso_local i8 @test__readgsbyte(i32 noundef %Offset) +// CHECK-X64-LABEL: define dso_local i8 @test__readgsbyte(i32 %Offset) // CHECK-X64: %inc = add i32 %Offset, 1 // CHECK-X64: [[ZEXT:%[0-9]+]] = zext i32 %inc to i64 // CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to i8 addrspace(256)* @@ -78,7 +78,7 @@ char test__readgsbyte(unsigned long Offset) { short test__readgsword(unsigned long Offset) { return __readgsword(++Offset); } -// CHECK-X64-LABEL: define dso_local i16 @test__readgsword(i32 noundef %Offset) +// CHECK-X64-LABEL: define dso_local i16 @test__readgsword(i32 %Offset) // CHECK-X64: %inc = add i32 %Offset, 1 // CHECK-X64: [[ZEXT:%[0-9]+]] = zext i32 %inc to i64 // CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to i16 addrspace(256)* @@ -88,7 +88,7 @@ short test__readgsword(unsigned long Offset) { long test__readgsdword(unsigned long Offset) { return __readgsdword(++Offset); } -// CHECK-X64-LABEL: define dso_local i32 @test__readgsdword(i32 noundef %Offset) +// CHECK-X64-LABEL: define dso_local i32 @test__readgsdword(i32 %Offset) // CHECK-X64: %inc = add i32 %Offset, 1 // CHECK-X64: [[ZEXT:%[0-9]+]] = zext i32 %inc to i64 // CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to i32 addrspace(256)* @@ -98,7 +98,7 @@ long test__readgsdword(unsigned long Offset) { long long test__readgsqword(unsigned long Offset) { return __readgsqword(++Offset); } -// CHECK-X64-LABEL: define dso_local i64 @test__readgsqword(i32 noundef %Offset) +// CHECK-X64-LABEL: define dso_local i64 @test__readgsqword(i32 %Offset) // CHECK-X64: %inc = add i32 %Offset, 1 // CHECK-X64: [[ZEXT:%[0-9]+]] = zext i32 %inc to i64 // CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to i64 addrspace(256)* @@ -108,13 +108,13 @@ long long test__readgsqword(unsigned long Offset) { __int64 test__mulh(__int64 a, __int64 b) { return __mulh(a, b); } -// CHECK-X64-LABEL: define dso_local i64 @test__mulh(i64 noundef %a, i64 noundef %b) +// CHECK-X64-LABEL: define dso_local i64 @test__mulh(i64 %a, i64 %b) // CHECK-X64: = mul nsw i128 % unsigned __int64 test__umulh(unsigned __int64 a, unsigned __int64 b) { return __umulh(a, b); } -// CHECK-X64-LABEL: define dso_local i64 @test__umulh(i64 noundef %a, i64 noundef %b) +// CHECK-X64-LABEL: define dso_local i64 @test__umulh(i64 %a, i64 %b) // CHECK-X64: = mul nuw i128 % __int64 test_mul128(__int64 Multiplier, @@ -122,7 +122,7 @@ __int64 test_mul128(__int64 Multiplier, __int64 *HighProduct) { return _mul128(Multiplier, Multiplicand, HighProduct); } -// CHECK-X64-LABEL: define dso_local i64 @test_mul128(i64 noundef %Multiplier, i64 noundef %Multiplicand, i64*{{[a-z_ ]*}}%HighProduct) +// CHECK-X64-LABEL: define dso_local i64 @test_mul128(i64 %Multiplier, i64 %Multiplicand, i64*{{[a-z_ ]*}}%HighProduct) // CHECK-X64: = sext i64 %Multiplier to i128 // CHECK-X64: = sext i64 %Multiplicand to i128 // CHECK-X64: = mul nsw i128 % @@ -134,7 +134,7 @@ unsigned __int64 test_umul128(unsigned __int64 Multiplier, unsigned __int64 *HighProduct) { return _umul128(Multiplier, Multiplicand, HighProduct); } -// CHECK-X64-LABEL: define dso_local i64 @test_umul128(i64 noundef %Multiplier, i64 noundef %Multiplicand, i64*{{[a-z_ ]*}}%HighProduct) +// CHECK-X64-LABEL: define dso_local i64 @test_umul128(i64 %Multiplier, i64 %Multiplicand, i64*{{[a-z_ ]*}}%HighProduct) // CHECK-X64: = zext i64 %Multiplier to i128 // CHECK-X64: = zext i64 %Multiplicand to i128 // CHECK-X64: = mul nuw i128 % @@ -145,7 +145,7 @@ unsigned __int64 test__shiftleft128(unsigned __int64 l, unsigned __int64 h, unsigned char d) { return __shiftleft128(l, h, d); } -// CHECK-X64-LABEL: define dso_local i64 @test__shiftleft128(i64 noundef %l, i64 noundef %h, i8 noundef %d) +// CHECK-X64-LABEL: define dso_local i64 @test__shiftleft128(i64 %l, i64 %h, i8 %d) // CHECK-X64: = zext i8 %{{.*}} to i64 // CHECK-X64: = tail call i64 @llvm.fshl.i64(i64 %h, i64 %l, i64 %{{.*}}) // CHECK-X64: ret i64 % @@ -154,7 +154,7 @@ unsigned __int64 test__shiftright128(unsigned __int64 l, unsigned __int64 h, unsigned char d) { return __shiftright128(l, h, d); } -// CHECK-X64-LABEL: define dso_local i64 @test__shiftright128(i64 noundef %l, i64 noundef %h, i8 noundef %d) +// CHECK-X64-LABEL: define dso_local i64 @test__shiftright128(i64 %l, i64 %h, i8 %d) // CHECK-X64: = zext i8 %{{.*}} to i64 // CHECK-X64: = tail call i64 @llvm.fshr.i64(i64 %h, i64 %l, i64 %{{.*}}) // CHECK-X64: ret i64 % diff --git a/clang/test/CodeGen/X86/strictfp_builtins.c b/clang/test/CodeGen/X86/strictfp_builtins.c index ccd2553cdb780611801596a276de7844a03dddc6..c3c94164e04f9bd9f8a3371a59224ad79e688968 100644 --- a/clang/test/CodeGen/X86/strictfp_builtins.c +++ b/clang/test/CodeGen/X86/strictfp_builtins.c @@ -17,7 +17,7 @@ int printf(const char *, ...); // CHECK-NEXT: store i32 [[X:%.*]], i32* [[X_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[STR_ADDR]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[X_ADDR]], align 4 -// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8*, ...) @printf(i8* noundef getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i8* noundef [[TMP0]], i32 noundef [[TMP1]]) [[ATTR4:#.*]] +// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i8* [[TMP0]], i32 [[TMP1]]) [[ATTR4:#.*]] // CHECK-NEXT: ret void // void p(char *str, int x) { @@ -35,7 +35,7 @@ void p(char *str, int x) { // CHECK-NEXT: [[SHL1:%.*]] = shl i80 [[BITCAST]], 1 // CHECK-NEXT: [[CMP:%.*]] = icmp eq i80 [[SHL1]], -18446744073709551616 // CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_long_double_isinf(long double ld) { @@ -53,7 +53,7 @@ void test_long_double_isinf(long double ld) { // CHECK-NEXT: [[SHL1:%.*]] = shl i80 [[BITCAST]], 1 // CHECK-NEXT: [[CMP:%.*]] = icmp ult i80 [[SHL1]], -18446744073709551616 // CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([13 x i8], [13 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_long_double_isfinite(long double ld) { @@ -72,7 +72,7 @@ void test_long_double_isfinite(long double ld) { // CHECK-NEXT: [[TMP1:%.*]] = sub i80 604453686435277732577280, [[ABS]] // CHECK-NEXT: [[ISNAN:%.*]] = lshr i80 [[TMP1]], 79 // CHECK-NEXT: [[RES:%.*]] = trunc i80 [[ISNAN]] to i32 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_long_double_isnan(long double ld) { diff --git a/clang/test/CodeGen/X86/x86-atomic-long_double.c b/clang/test/CodeGen/X86/x86-atomic-long_double.c index eb8de03b634bc14164f19b5b0744bade3e6b35d4..7ad7de8c917e7ea4d7b2cddbbfa50840490b724e 100644 --- a/clang/test/CodeGen/X86/x86-atomic-long_double.c +++ b/clang/test/CodeGen/X86/x86-atomic-long_double.c @@ -39,7 +39,7 @@ long double testinc(_Atomic long double *addr) { // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* - // CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_PTR]], i8* noundef [[TEMP_LD_PTR]], i32 noundef 5) + // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: [[ATOMIC_OP]] @@ -54,7 +54,7 @@ long double testinc(_Atomic long double *addr) { // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* - // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, i8* noundef [[OBJ]], i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 5, i32 noundef 5) + // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: [[ATOMIC_CONT]] @@ -101,7 +101,7 @@ long double testdec(_Atomic long double *addr) { // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* - // CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_PTR]], i8* noundef [[TEMP_LD_PTR]], i32 noundef 5) + // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) // CHECK32: [[ORIG_LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: [[ATOMIC_OP]] @@ -116,7 +116,7 @@ long double testdec(_Atomic long double *addr) { // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* - // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, i8* noundef [[OBJ]], i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 5, i32 noundef 5) + // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) // CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: [[ATOMIC_CONT]] @@ -170,7 +170,7 @@ long double testcompassign(_Atomic long double *addr) { // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* - // CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_PTR]], i8* noundef [[TEMP_LD_PTR]], i32 noundef 5) + // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: [[ATOMIC_OP]] @@ -185,14 +185,14 @@ long double testcompassign(_Atomic long double *addr) { // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* - // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, i8* noundef [[OBJ]], i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 5, i32 noundef 5) + // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) // CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: [[ATOMIC_CONT]] // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 4 // CHECK32: [[VOID_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[VOID_GET_ADDR:%.+]] = bitcast x86_fp80* [[GET_ADDR:%.+]] to i8* - // CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_ADDR]], i8* noundef [[VOID_GET_ADDR]], i32 noundef 5) + // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_ADDR]], i8* [[VOID_GET_ADDR]], i32 5) // CHECK32: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[GET_ADDR]], align 4 // CHECK32: ret x86_fp80 [[RET_VAL]] return *addr; @@ -217,7 +217,7 @@ long double testassign(_Atomic long double *addr) { // CHECK32: store x86_fp80 {{.+}}, x86_fp80* [[STORE_TEMP_PTR]], align 4 // CHECK32: [[ADDR_VOID:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i8* - // CHECK32: call void @__atomic_store(i32 noundef 12, i8* noundef [[ADDR_VOID]], i8* noundef [[STORE_TEMP_VOID_PTR]], i32 noundef 5) + // CHECK32: call void @__atomic_store(i32 12, i8* [[ADDR_VOID]], i8* [[STORE_TEMP_VOID_PTR]], i32 5) *addr = 115; // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 8 // CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* @@ -229,7 +229,7 @@ long double testassign(_Atomic long double *addr) { // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 4 // CHECK32: [[VOID_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[VOID_LD_TEMP:%.+]] = bitcast x86_fp80* [[LD_TEMP:%.+]] to i8* - // CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_ADDR]], i8* noundef [[VOID_LD_TEMP]], i32 noundef 5) + // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_ADDR]], i8* [[VOID_LD_TEMP]], i32 5) // CHECK32: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[LD_TEMP]], align 4 // CHECK32: ret x86_fp80 [[RET_VAL]] @@ -274,7 +274,7 @@ long double test_volatile_inc(volatile _Atomic long double *addr) { // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* - // CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_PTR]], i8* noundef [[TEMP_LD_PTR]], i32 noundef 5) + // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: [[ATOMIC_OP]] @@ -289,7 +289,7 @@ long double test_volatile_inc(volatile _Atomic long double *addr) { // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* - // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, i8* noundef [[OBJ]], i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 5, i32 noundef 5) + // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) // CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: [[ATOMIC_CONT]] @@ -335,7 +335,7 @@ long double test_volatile_dec(volatile _Atomic long double *addr) { // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* - // CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_PTR]], i8* noundef [[TEMP_LD_PTR]], i32 noundef 5) + // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) // CHECK32: [[ORIG_LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: [[ATOMIC_OP]] @@ -350,7 +350,7 @@ long double test_volatile_dec(volatile _Atomic long double *addr) { // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* - // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, i8* noundef [[OBJ]], i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 5, i32 noundef 5) + // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) // CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: [[ATOMIC_CONT]] @@ -402,7 +402,7 @@ long double test_volatile_compassign(volatile _Atomic long double *addr) { // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* - // CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_PTR]], i8* noundef [[TEMP_LD_PTR]], i32 noundef 5) + // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: [[ATOMIC_OP]] @@ -417,14 +417,14 @@ long double test_volatile_compassign(volatile _Atomic long double *addr) { // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* - // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, i8* noundef [[OBJ]], i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 5, i32 noundef 5) + // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) // CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: [[ATOMIC_CONT]] // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 4 // CHECK32: [[VOID_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[VOID_GET_ADDR:%.+]] = bitcast x86_fp80* [[GET_ADDR:%.+]] to i8* - // CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_ADDR]], i8* noundef [[VOID_GET_ADDR]], i32 noundef 5) + // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_ADDR]], i8* [[VOID_GET_ADDR]], i32 5) // CHECK32: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[GET_ADDR]], align 4 // CHECK32: ret x86_fp80 [[RET_VAL]] return *addr; @@ -449,7 +449,7 @@ long double test_volatile_assign(volatile _Atomic long double *addr) { // CHECK32: store x86_fp80 {{.+}}, x86_fp80* [[STORE_TEMP_PTR]], align 4 // CHECK32: [[ADDR_VOID:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i8* - // CHECK32: call void @__atomic_store(i32 noundef 12, i8* noundef [[ADDR_VOID]], i8* noundef [[STORE_TEMP_VOID_PTR]], i32 noundef 5) + // CHECK32: call void @__atomic_store(i32 12, i8* [[ADDR_VOID]], i8* [[STORE_TEMP_VOID_PTR]], i32 5) *addr = 115; // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 8 // CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* @@ -461,7 +461,7 @@ long double test_volatile_assign(volatile _Atomic long double *addr) { // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 4 // CHECK32: [[VOID_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[VOID_LD_TEMP:%.+]] = bitcast x86_fp80* [[LD_TEMP:%.+]] to i8* - // CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_ADDR]], i8* noundef [[VOID_LD_TEMP]], i32 noundef 5) + // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_ADDR]], i8* [[VOID_LD_TEMP]], i32 5) // CHECK32: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[LD_TEMP]], align 4 // CHECK32: ret x86_fp80 [[RET_VAL]] diff --git a/clang/test/CodeGen/X86/x86-inline-asm-min-vector-width.c b/clang/test/CodeGen/X86/x86-inline-asm-min-vector-width.c index 5d93dc98b16333e257c20e0b2508cc4a6ab9d535..e473c46146fb387dd78bf2ed58f3fc469c8d9014 100644 --- a/clang/test/CodeGen/X86/x86-inline-asm-min-vector-width.c +++ b/clang/test/CodeGen/X86/x86-inline-asm-min-vector-width.c @@ -4,38 +4,38 @@ typedef long long __m128i __attribute__ ((vector_size (16))); typedef long long __m256i __attribute__ ((vector_size (32))); typedef long long __m512i __attribute__ ((vector_size (64))); -// CHECK: define{{.*}} <2 x i64> @testXMMout(<2 x i64>* noundef %p) #0 +// CHECK: define{{.*}} <2 x i64> @testXMMout(<2 x i64>* %p) #0 __m128i testXMMout(__m128i *p) { __m128i xmm0; __asm__("vmovdqu %1, %0" :"=v"(xmm0) : "m"(*(__m128i*)p)); return xmm0; } -// CHECK: define{{.*}} <4 x i64> @testYMMout(<4 x i64>* noundef %p) #1 +// CHECK: define{{.*}} <4 x i64> @testYMMout(<4 x i64>* %p) #1 __m256i testYMMout(__m256i *p) { __m256i ymm0; __asm__("vmovdqu %1, %0" :"=v"(ymm0) : "m"(*(__m256i*)p)); return ymm0; } -// CHECK: define{{.*}} <8 x i64> @testZMMout(<8 x i64>* noundef %p) #2 +// CHECK: define{{.*}} <8 x i64> @testZMMout(<8 x i64>* %p) #2 __m512i testZMMout(__m512i *p) { __m512i zmm0; __asm__("vmovdqu64 %1, %0" :"=v"(zmm0) : "m"(*(__m512i*)p)); return zmm0; } -// CHECK: define{{.*}} void @testXMMin(<2 x i64> noundef %xmm0, <2 x i64>* noundef %p) #0 +// CHECK: define{{.*}} void @testXMMin(<2 x i64> %xmm0, <2 x i64>* %p) #0 void testXMMin(__m128i xmm0, __m128i *p) { __asm__("vmovdqu %0, %1" : : "v"(xmm0), "m"(*(__m128i*)p)); } -// CHECK: define{{.*}} void @testYMMin(<4 x i64> noundef %ymm0, <4 x i64>* noundef %p) #1 +// CHECK: define{{.*}} void @testYMMin(<4 x i64> %ymm0, <4 x i64>* %p) #1 void testYMMin(__m256i ymm0, __m256i *p) { __asm__("vmovdqu %0, %1" : : "v"(ymm0), "m"(*(__m256i*)p)); } -// CHECK: define{{.*}} void @testZMMin(<8 x i64> noundef %zmm0, <8 x i64>* noundef %p) #2 +// CHECK: define{{.*}} void @testZMMin(<8 x i64> %zmm0, <8 x i64>* %p) #2 void testZMMin(__m512i zmm0, __m512i *p) { __asm__("vmovdqu64 %0, %1" : : "v"(zmm0), "m"(*(__m512i*)p)); } diff --git a/clang/test/CodeGen/X86/x86-long-double.cpp b/clang/test/CodeGen/X86/x86-long-double.cpp index 89d6256c9e32b0925e655f9f8a11473eeee7e0a1..7b8610d5af0a60b497ca8661846ff23333060703 100644 --- a/clang/test/CodeGen/X86/x86-long-double.cpp +++ b/clang/test/CodeGen/X86/x86-long-double.cpp @@ -51,6 +51,6 @@ int size = sizeof(x); long double foo(long double d) { return d; } -// FP64: double @_Z3fooe(double noundef %d) -// FP80: x86_fp80 @_Z3fooe(x86_fp80 noundef %d) -// FP128: fp128 @_Z3foog(fp128 noundef %d) +// FP64: double @_Z3fooe(double %d) +// FP80: x86_fp80 @_Z3fooe(x86_fp80 %d) +// FP128: fp128 @_Z3foog(fp128 %d) diff --git a/clang/test/CodeGen/X86/x86-soft-float.c b/clang/test/CodeGen/X86/x86-soft-float.c index 283a0cbc71bd8d462519c5641ba9f4924f71f94a..64349fdec6249d890e69b15d3fbe525e89e2d51c 100644 --- a/clang/test/CodeGen/X86/x86-soft-float.c +++ b/clang/test/CodeGen/X86/x86-soft-float.c @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 3 -emit-llvm %s -o - | FileCheck %s -check-prefix=HARD // RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 3 -mfloat-abi soft -emit-llvm %s -o - | FileCheck %s -check-prefix=SOFT -// HARD: define{{.*}} void @f1(float noundef %a) -// SOFT: define{{.*}} void @f1(float inreg noundef %a) +// HARD: define{{.*}} void @f1(float %a) +// SOFT: define{{.*}} void @f1(float inreg %a) void f1(float a) {} diff --git a/clang/test/CodeGen/X86/x86-vec-i128.c b/clang/test/CodeGen/X86/x86-vec-i128.c index 6003fea85e6bf8213231a5d5813dde74501c2499..cd2236980952b920efcade5927e97da4fc794592 100644 --- a/clang/test/CodeGen/X86/x86-vec-i128.c +++ b/clang/test/CodeGen/X86/x86-vec-i128.c @@ -23,8 +23,8 @@ typedef unsigned long long v16u64 __attribute__((vector_size(16))); typedef unsigned __int128 v16u128 __attribute__((vector_size(16))); v16u64 test_v16u128(v16u64 a, v16u128 b) { -// CLANG10ABI128: define{{.*}} <2 x i64> @test_v16u128(<2 x i64> noundef %{{.*}}, <2 x i64> noundef %{{.*}}) -// CLANG9ABI128: define{{.*}} <2 x i64> @test_v16u128(<2 x i64> noundef %{{.*}}, <1 x i128> noundef %{{.*}}) +// CLANG10ABI128: define{{.*}} <2 x i64> @test_v16u128(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}) +// CLANG9ABI128: define{{.*}} <2 x i64> @test_v16u128(<2 x i64> %{{.*}}, <1 x i128> %{{.*}}) return a + (v16u64)b; } @@ -32,10 +32,10 @@ typedef unsigned long long v32u64 __attribute__((vector_size(32))); typedef unsigned __int128 v32u128 __attribute__((vector_size(32))); v32u64 test_v32u128(v32u64 a, v32u128 b) { -// MEM256ALIGN16: define{{.*}} <4 x i64> @test_v32u128(<4 x i64>* noundef byval(<4 x i64>) align 16 %{{.*}}, <2 x i128>* noundef byval(<2 x i128>) align 16 %{{.*}}) -// MEM256ALIGN32: define{{.*}} <4 x i64> @test_v32u128(<4 x i64>* noundef byval(<4 x i64>) align 32 %{{.*}}, <2 x i128>* noundef byval(<2 x i128>) align 32 %{{.*}}) -// CLANG10ABI256: define{{.*}} <4 x i64> @test_v32u128(<4 x i64> noundef %{{.*}}, <2 x i128>* noundef byval(<2 x i128>) align 32 %{{.*}}) -// CLANG9ABI256: define{{.*}} <4 x i64> @test_v32u128(<4 x i64> noundef %{{.*}}, <2 x i128> noundef %{{.*}}) +// MEM256ALIGN16: define{{.*}} <4 x i64> @test_v32u128(<4 x i64>* byval(<4 x i64>) align 16 %{{.*}}, <2 x i128>* byval(<2 x i128>) align 16 %{{.*}}) +// MEM256ALIGN32: define{{.*}} <4 x i64> @test_v32u128(<4 x i64>* byval(<4 x i64>) align 32 %{{.*}}, <2 x i128>* byval(<2 x i128>) align 32 %{{.*}}) +// CLANG10ABI256: define{{.*}} <4 x i64> @test_v32u128(<4 x i64> %{{.*}}, <2 x i128>* byval(<2 x i128>) align 32 %{{.*}}) +// CLANG9ABI256: define{{.*}} <4 x i64> @test_v32u128(<4 x i64> %{{.*}}, <2 x i128> %{{.*}}) return a + (v32u64)b; } @@ -43,10 +43,10 @@ typedef unsigned long long v64u64 __attribute__((vector_size(64))); typedef unsigned __int128 v64u128 __attribute__((vector_size(64))); v64u64 test_v64u128(v64u64 a, v64u128 b) { -// MEM512ALIGN16: define{{.*}} <8 x i64> @test_v64u128(<8 x i64>* noundef byval(<8 x i64>) align 16 %{{.*}}, <4 x i128>* noundef byval(<4 x i128>) align 16 %{{.*}}) -// MEM512ALIGN32: define{{.*}} <8 x i64> @test_v64u128(<8 x i64>* noundef byval(<8 x i64>) align 32 %{{.*}}, <4 x i128>* noundef byval(<4 x i128>) align 32 %{{.*}}) -// MEM512ALIGN64: define{{.*}} <8 x i64> @test_v64u128(<8 x i64>* noundef byval(<8 x i64>) align 64 %{{.*}}, <4 x i128>* noundef byval(<4 x i128>) align 64 %{{.*}}) -// CLANG10ABI512: define{{.*}} <8 x i64> @test_v64u128(<8 x i64> noundef %{{.*}}, <4 x i128>* noundef byval(<4 x i128>) align 64 %{{.*}}) -// CLANG9ABI512: define{{.*}} <8 x i64> @test_v64u128(<8 x i64> noundef %{{.*}}, <4 x i128> noundef %{{.*}}) +// MEM512ALIGN16: define{{.*}} <8 x i64> @test_v64u128(<8 x i64>* byval(<8 x i64>) align 16 %{{.*}}, <4 x i128>* byval(<4 x i128>) align 16 %{{.*}}) +// MEM512ALIGN32: define{{.*}} <8 x i64> @test_v64u128(<8 x i64>* byval(<8 x i64>) align 32 %{{.*}}, <4 x i128>* byval(<4 x i128>) align 32 %{{.*}}) +// MEM512ALIGN64: define{{.*}} <8 x i64> @test_v64u128(<8 x i64>* byval(<8 x i64>) align 64 %{{.*}}, <4 x i128>* byval(<4 x i128>) align 64 %{{.*}}) +// CLANG10ABI512: define{{.*}} <8 x i64> @test_v64u128(<8 x i64> %{{.*}}, <4 x i128>* byval(<4 x i128>) align 64 %{{.*}}) +// CLANG9ABI512: define{{.*}} <8 x i64> @test_v64u128(<8 x i64> %{{.*}}, <4 x i128> %{{.*}}) return a + (v64u64)b; } diff --git a/clang/test/CodeGen/X86/x86_32-arguments-darwin.c b/clang/test/CodeGen/X86/x86_32-arguments-darwin.c index 668bb5eb9aaa50fc1b739e7a6f094648ad5c779a..b8b22bed440bf9dfb8f3a7e931890b0a9196c2bc 100644 --- a/clang/test/CodeGen/X86/x86_32-arguments-darwin.c +++ b/clang/test/CodeGen/X86/x86_32-arguments-darwin.c @@ -30,10 +30,10 @@ long double f5(void) { return 0; } -// CHECK-LABEL: define{{.*}} void @f6(i8 noundef signext %a0, i16 noundef signext %a1, i32 noundef %a2, i64 noundef %a3, i8* noundef %a4) +// CHECK-LABEL: define{{.*}} void @f6(i8 signext %a0, i16 signext %a1, i32 %a2, i64 %a3, i8* %a4) void f6(char a0, short a1, int a2, long long a3, void *a4) {} -// CHECK-LABEL: define{{.*}} void @f7(i32 noundef %a0) +// CHECK-LABEL: define{{.*}} void @f7(i32 %a0) typedef enum { A, B, C } e7; void f7(e7 a0) {} @@ -52,7 +52,7 @@ void f8_2(struct s8 a0) {} // FIXME: llvm-gcc expands this, this may have some value for the // backend in terms of optimization but doesn't change the ABI. -// CHECK-LABEL: define{{.*}} void @f9_2(%struct.s9* noundef byval(%struct.s9) align 4 %a0) +// CHECK-LABEL: define{{.*}} void @f9_2(%struct.s9* byval(%struct.s9) align 4 %a0) struct s9 { int a : 17; int b; @@ -153,7 +153,7 @@ struct s37 { float c[1][1]; } f37(void) { while (1) {} } // CHECK-LABEL: define{{.*}} void @f38(%struct.s38* noalias sret(%struct.s38) align 2 %agg.result) struct s38 { char a[3]; short b; } f38(void) { while (1) {} } -// CHECK-LABEL: define{{.*}} void @f39(%struct.s39* noundef byval(%struct.s39) align 16 %x) +// CHECK-LABEL: define{{.*}} void @f39(%struct.s39* byval(%struct.s39) align 16 %x) typedef int v39 __attribute((vector_size(16))); struct s39 { v39 x; }; void f39(struct s39 x) {} @@ -179,10 +179,10 @@ struct s44 { vvbp f0; } f44(void) { } // CHECK-LABEL: define{{.*}} i64 @f45() struct s45 { vvbp f0; int f1; } f45(void) { } -// CHECK-LABEL: define{{.*}} void @f46(i32 noundef %a0) +// CHECK-LABEL: define{{.*}} void @f46(i32 %a0) void f46(enum e40 a0) { } -// CHECK-LABEL: define{{.*}} void @f47(void ()* noundef %a1) +// CHECK-LABEL: define{{.*}} void @f47(void ()* %a1) void f47(vvbp a1) { } // CHECK-LABEL: define{{.*}} void @f48(i32 %a0.0) @@ -201,13 +201,13 @@ void f50(struct s50 a0) { } struct s51 { vvbp f0; int f1; }; void f51(struct s51 a0) { } -// CHECK-LABEL: define{{.*}} void @f52(%struct.s52* noundef byval(%struct.s52) align 4 %0) +// CHECK-LABEL: define{{.*}} void @f52(%struct.s52* byval(%struct.s52) align 4 %0) struct s52 { long double a; }; void f52(struct s52 x) {} -// CHECK-LABEL: define{{.*}} void @f53(%struct.s53* noundef byval(%struct.s53) align 4 %0) +// CHECK-LABEL: define{{.*}} void @f53(%struct.s53* byval(%struct.s53) align 4 %0) struct __attribute__((aligned(32))) s53 { int x; int y; @@ -216,34 +216,34 @@ void f53(struct s53 x) {} typedef unsigned short v2i16 __attribute__((__vector_size__(4))); -// CHECK-LABEL: define{{.*}} i32 @f54(i32 noundef %arg.coerce) +// CHECK-LABEL: define{{.*}} i32 @f54(i32 %arg.coerce) // rdar://8359483 v2i16 f54(v2i16 arg) { return arg+arg; } typedef int v4i32 __attribute__((__vector_size__(16))); -// CHECK-LABEL: define{{.*}} <2 x i64> @f55(<4 x i32> noundef %arg) +// CHECK-LABEL: define{{.*}} <2 x i64> @f55(<4 x i32> %arg) // PR8029 v4i32 f55(v4i32 arg) { return arg+arg; } // CHECK-LABEL: define{{.*}} void @f56( -// CHECK: i8 noundef signext %a0, %struct.s56_0* noundef byval(%struct.s56_0) align 4 %a1, -// CHECK: i64 noundef %a2.coerce, %struct.s56_1* noundef byval(%struct.s56_1) align 4 %0, -// CHECK: i64 noundef %a4.coerce, %struct.s56_2* noundef byval(%struct.s56_2) align 4 %1, -// CHECK: <4 x i32> noundef %a6, %struct.s56_3* noundef byval(%struct.s56_3) align 16 %a7, -// CHECK: <2 x double> noundef %a8, %struct.s56_4* noundef byval(%struct.s56_4) align 16 %a9, -// CHECK: <8 x i32> noundef %a10, %struct.s56_5* noundef byval(%struct.s56_5) align 4 %2, -// CHECK: <4 x double> noundef %a12, %struct.s56_6* noundef byval(%struct.s56_6) align 4 %3) - -// CHECK: call void (i32, ...) @f56_0(i32 noundef 1, -// CHECK: i32 noundef %{{[^ ]*}}, %struct.s56_0* noundef byval(%struct.s56_0) align 4 %{{[^ ]*}}, -// CHECK: i64 noundef %{{[^ ]*}}, %struct.s56_1* noundef byval(%struct.s56_1) align 4 %{{[^ ]*}}, -// CHECK: i64 noundef %{{[^ ]*}}, %struct.s56_2* noundef byval(%struct.s56_2) align 4 %{{[^ ]*}}, -// CHECK: <4 x i32> noundef %{{[^ ]*}}, %struct.s56_3* noundef byval(%struct.s56_3) align 16 %{{[^ ]*}}, -// CHECK: <2 x double> noundef %{{[^ ]*}}, %struct.s56_4* noundef byval(%struct.s56_4) align 16 %{{[^ ]*}}, -// CHECK: <8 x i32> noundef {{[^ ]*}}, %struct.s56_5* noundef byval(%struct.s56_5) align 4 %{{[^ ]*}}, -// CHECK: <4 x double> noundef {{[^ ]*}}, %struct.s56_6* noundef byval(%struct.s56_6) align 4 %{{[^ ]*}}) +// CHECK: i8 signext %a0, %struct.s56_0* byval(%struct.s56_0) align 4 %a1, +// CHECK: i64 %a2.coerce, %struct.s56_1* byval(%struct.s56_1) align 4 %0, +// CHECK: i64 %a4.coerce, %struct.s56_2* byval(%struct.s56_2) align 4 %1, +// CHECK: <4 x i32> %a6, %struct.s56_3* byval(%struct.s56_3) align 16 %a7, +// CHECK: <2 x double> %a8, %struct.s56_4* byval(%struct.s56_4) align 16 %a9, +// CHECK: <8 x i32> %a10, %struct.s56_5* byval(%struct.s56_5) align 4 %2, +// CHECK: <4 x double> %a12, %struct.s56_6* byval(%struct.s56_6) align 4 %3) + +// CHECK: call void (i32, ...) @f56_0(i32 1, +// CHECK: i32 %{{[^ ]*}}, %struct.s56_0* byval(%struct.s56_0) align 4 %{{[^ ]*}}, +// CHECK: i64 %{{[^ ]*}}, %struct.s56_1* byval(%struct.s56_1) align 4 %{{[^ ]*}}, +// CHECK: i64 %{{[^ ]*}}, %struct.s56_2* byval(%struct.s56_2) align 4 %{{[^ ]*}}, +// CHECK: <4 x i32> %{{[^ ]*}}, %struct.s56_3* byval(%struct.s56_3) align 16 %{{[^ ]*}}, +// CHECK: <2 x double> %{{[^ ]*}}, %struct.s56_4* byval(%struct.s56_4) align 16 %{{[^ ]*}}, +// CHECK: <8 x i32> {{[^ ]*}}, %struct.s56_5* byval(%struct.s56_5) align 4 %{{[^ ]*}}, +// CHECK: <4 x double> {{[^ ]*}}, %struct.s56_6* byval(%struct.s56_6) align 4 %{{[^ ]*}}) // CHECK: } // // [i386] clang misaligns long double in structures @@ -289,16 +289,16 @@ void f58(union u58 x) {} struct s59 { float x __attribute((aligned(8))); }; struct s59 f59() { while (1) {} } -// CHECK-LABEL: define{{.*}} void @f60(%struct.s60* noundef byval(%struct.s60) align 4 %0, i32 noundef %y) +// CHECK-LABEL: define{{.*}} void @f60(%struct.s60* byval(%struct.s60) align 4 %0, i32 %y) struct s60 { int x __attribute((aligned(8))); }; void f60(struct s60 x, int y) {} -// CHECK-LABEL: define{{.*}} void @f61(i32 noundef %x, %struct.s61* noundef byval(%struct.s61) align 16 %y) +// CHECK-LABEL: define{{.*}} void @f61(i32 %x, %struct.s61* byval(%struct.s61) align 16 %y) typedef int T61 __attribute((vector_size(16))); struct s61 { T61 x; int y; }; void f61(int x, struct s61 y) {} -// CHECK-LABEL: define{{.*}} void @f62(i32 noundef %x, %struct.s62* noundef byval(%struct.s62) align 4 %0) +// CHECK-LABEL: define{{.*}} void @f62(i32 %x, %struct.s62* byval(%struct.s62) align 4 %0) typedef int T62 __attribute((vector_size(16))); struct s62 { T62 x; int y; } __attribute((packed, aligned(8))); void f62(int x, struct s62 y) {} @@ -317,7 +317,7 @@ int f63(int i, ...) { return s.y; } -// CHECK-LABEL: define{{.*}} void @f64(%struct.s64* noundef byval(%struct.s64) align 4 %x) +// CHECK-LABEL: define{{.*}} void @f64(%struct.s64* byval(%struct.s64) align 4 %x) struct s64 { signed char a[0]; signed char b[]; }; void f64(struct s64 x) {} @@ -341,4 +341,4 @@ T66 f66(int i, ...) { // PR14453 struct s67 { _Complex unsigned short int a; }; void f67(struct s67 x) {} -// CHECK-LABEL: define{{.*}} void @f67(%struct.s67* noundef byval(%struct.s67) align 4 %x) +// CHECK-LABEL: define{{.*}} void @f67(%struct.s67* byval(%struct.s67) align 4 %x) diff --git a/clang/test/CodeGen/X86/x86_32-arguments-iamcu.c b/clang/test/CodeGen/X86/x86_32-arguments-iamcu.c index 5d54016a60308e3e4a6a727b44d4a91704fa9815..35cf114251901c1dbeb40dd230120f3c6468dddd 100644 --- a/clang/test/CodeGen/X86/x86_32-arguments-iamcu.c +++ b/clang/test/CodeGen/X86/x86_32-arguments-iamcu.c @@ -1,18 +1,18 @@ // RUN: %clang_cc1 -w -triple i386-pc-elfiamcu -mfloat-abi soft -emit-llvm -o - %s | FileCheck %s -// CHECK-LABEL: define{{.*}} void @ints(i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d) +// CHECK-LABEL: define{{.*}} void @ints(i32 %a, i32 %b, i32 %c, i32 %d) void ints(int a, int b, int c, int d) {} -// CHECK-LABEL: define{{.*}} void @floats(float noundef %a, float noundef %b, float noundef %c, float noundef %d) +// CHECK-LABEL: define{{.*}} void @floats(float %a, float %b, float %c, float %d) void floats(float a, float b, float c, float d) {} -// CHECK-LABEL: define{{.*}} void @mixed(i32 noundef %a, float noundef %b, i32 noundef %c, float noundef %d) +// CHECK-LABEL: define{{.*}} void @mixed(i32 %a, float %b, i32 %c, float %d) void mixed(int a, float b, int c, float d) {} -// CHECK-LABEL: define{{.*}} void @doubles(double noundef %d1, double noundef %d2) +// CHECK-LABEL: define{{.*}} void @doubles(double %d1, double %d2) void doubles(double d1, double d2) {} -// CHECK-LABEL: define{{.*}} void @mixedDoubles(i32 noundef %a, double noundef %d1) +// CHECK-LABEL: define{{.*}} void @mixedDoubles(i32 %a, double %d1) void mixedDoubles(int a, double d1) {} typedef struct st3_t { @@ -37,16 +37,16 @@ typedef struct st12_t { // CHECK-LABEL: define{{.*}} void @smallStructs(i32 %st1.coerce, i32 %st2.coerce, i32 %st3.coerce) void smallStructs(st4_t st1, st4_t st2, st4_t st3) {} -// CHECK-LABEL: define{{.*}} void @paddedStruct(i32 noundef %i1, i32 %st.coerce0, i32 %st.coerce1, i32 %st4.0) +// CHECK-LABEL: define{{.*}} void @paddedStruct(i32 %i1, i32 %st.coerce0, i32 %st.coerce1, i32 %st4.0) void paddedStruct(int i1, st5_t st, st4_t st4) {} -// CHECK-LABEL: define{{.*}} void @largeStructBegin(%struct.st12_t* noundef byval(%struct.st12_t) align 4 %st) +// CHECK-LABEL: define{{.*}} void @largeStructBegin(%struct.st12_t* byval(%struct.st12_t) align 4 %st) void largeStructBegin(st12_t st) {} -// CHECK-LABEL: define{{.*}} void @largeStructMiddle(i32 noundef %i1, %struct.st12_t* noundef byval(%struct.st12_t) align 4 %st, i32 noundef %i2, i32 noundef %i3) +// CHECK-LABEL: define{{.*}} void @largeStructMiddle(i32 %i1, %struct.st12_t* byval(%struct.st12_t) align 4 %st, i32 %i2, i32 %i3) void largeStructMiddle(int i1, st12_t st, int i2, int i3) {} -// CHECK-LABEL: define{{.*}} void @largeStructEnd(i32 noundef %i1, i32 noundef %i2, i32 noundef %i3, i32 %st.0, i32 %st.1, i32 %st.2) +// CHECK-LABEL: define{{.*}} void @largeStructEnd(i32 %i1, i32 %i2, i32 %i3, i32 %st.0, i32 %st.1, i32 %st.2) void largeStructEnd(int i1, int i2, int i3, st12_t st) {} // CHECK-LABEL: define{{.*}} i24 @retNonPow2Struct(i32 %r.coerce) @@ -58,12 +58,12 @@ st4_t retSmallStruct(st4_t r) { return r; } // CHECK-LABEL: define{{.*}} i64 @retPaddedStruct(i32 %r.coerce0, i32 %r.coerce1) st5_t retPaddedStruct(st5_t r) { return r; } -// CHECK-LABEL: define{{.*}} void @retLargeStruct(%struct.st12_t* noalias sret(%struct.st12_t) align 4 %agg.result, i32 noundef %i1, %struct.st12_t* noundef byval(%struct.st12_t) align 4 %r) +// CHECK-LABEL: define{{.*}} void @retLargeStruct(%struct.st12_t* noalias sret(%struct.st12_t) align 4 %agg.result, i32 %i1, %struct.st12_t* byval(%struct.st12_t) align 4 %r) st12_t retLargeStruct(int i1, st12_t r) { return r; } -// CHECK-LABEL: define{{.*}} i32 @varArgs(i32 noundef %i1, ...) +// CHECK-LABEL: define{{.*}} i32 @varArgs(i32 %i1, ...) int varArgs(int i1, ...) { return i1; } -// CHECK-LABEL: define{{.*}} double @longDoubleArg(double noundef %ld1) +// CHECK-LABEL: define{{.*}} double @longDoubleArg(double %ld1) long double longDoubleArg(long double ld1) { return ld1; } diff --git a/clang/test/CodeGen/X86/x86_32-arguments-linux.c b/clang/test/CodeGen/X86/x86_32-arguments-linux.c index 4d1a04dda6869ee6acd2613c4c5cf32983d7bfde..580f8bbf79417f2b2b2700dabdd0961fb1676a00 100644 --- a/clang/test/CodeGen/X86/x86_32-arguments-linux.c +++ b/clang/test/CodeGen/X86/x86_32-arguments-linux.c @@ -2,22 +2,22 @@ // RUN: FileCheck < %t %s // CHECK-LABEL: define{{.*}} void @f56( -// CHECK: i8 noundef signext %a0, %struct.s56_0* noundef byval(%struct.s56_0) align 4 %a1, -// CHECK: i64 noundef %a2.coerce, %struct.s56_1* noundef byval(%struct.s56_1) align 4 %0, -// CHECK: <1 x double> noundef %a4, %struct.s56_2* noundef byval(%struct.s56_2) align 4 %1, -// CHECK: <4 x i32> noundef %a6, %struct.s56_3* noundef byval(%struct.s56_3) align 4 %2, -// CHECK: <2 x double> noundef %a8, %struct.s56_4* noundef byval(%struct.s56_4) align 4 %3, -// CHECK: <8 x i32> noundef %a10, %struct.s56_5* noundef byval(%struct.s56_5) align 4 %4, -// CHECK: <4 x double> noundef %a12, %struct.s56_6* noundef byval(%struct.s56_6) align 4 %5) +// CHECK: i8 signext %a0, %struct.s56_0* byval(%struct.s56_0) align 4 %a1, +// CHECK: i64 %a2.coerce, %struct.s56_1* byval(%struct.s56_1) align 4 %0, +// CHECK: <1 x double> %a4, %struct.s56_2* byval(%struct.s56_2) align 4 %1, +// CHECK: <4 x i32> %a6, %struct.s56_3* byval(%struct.s56_3) align 4 %2, +// CHECK: <2 x double> %a8, %struct.s56_4* byval(%struct.s56_4) align 4 %3, +// CHECK: <8 x i32> %a10, %struct.s56_5* byval(%struct.s56_5) align 4 %4, +// CHECK: <4 x double> %a12, %struct.s56_6* byval(%struct.s56_6) align 4 %5) -// CHECK: call void (i32, ...) @f56_0(i32 noundef 1, -// CHECK: i32 noundef %{{.*}}, %struct.s56_0* noundef byval(%struct.s56_0) align 4 %{{[^ ]*}}, -// CHECK: i64 noundef %{{[^ ]*}}, %struct.s56_1* noundef byval(%struct.s56_1) align 4 %{{[^ ]*}}, -// CHECK: <1 x double> noundef %{{[^ ]*}}, %struct.s56_2* noundef byval(%struct.s56_2) align 4 %{{[^ ]*}}, -// CHECK: <4 x i32> noundef %{{[^ ]*}}, %struct.s56_3* noundef byval(%struct.s56_3) align 4 %{{[^ ]*}}, -// CHECK: <2 x double> noundef %{{[^ ]*}}, %struct.s56_4* noundef byval(%struct.s56_4) align 4 %{{[^ ]*}}, -// CHECK: <8 x i32> noundef %{{[^ ]*}}, %struct.s56_5* noundef byval(%struct.s56_5) align 4 %{{[^ ]*}}, -// CHECK: <4 x double> noundef %{{[^ ]*}}, %struct.s56_6* noundef byval(%struct.s56_6) align 4 %{{[^ ]*}}) +// CHECK: call void (i32, ...) @f56_0(i32 1, +// CHECK: i32 %{{.*}}, %struct.s56_0* byval(%struct.s56_0) align 4 %{{[^ ]*}}, +// CHECK: i64 %{{[^ ]*}}, %struct.s56_1* byval(%struct.s56_1) align 4 %{{[^ ]*}}, +// CHECK: <1 x double> %{{[^ ]*}}, %struct.s56_2* byval(%struct.s56_2) align 4 %{{[^ ]*}}, +// CHECK: <4 x i32> %{{[^ ]*}}, %struct.s56_3* byval(%struct.s56_3) align 4 %{{[^ ]*}}, +// CHECK: <2 x double> %{{[^ ]*}}, %struct.s56_4* byval(%struct.s56_4) align 4 %{{[^ ]*}}, +// CHECK: <8 x i32> %{{[^ ]*}}, %struct.s56_5* byval(%struct.s56_5) align 4 %{{[^ ]*}}, +// CHECK: <4 x double> %{{[^ ]*}}, %struct.s56_6* byval(%struct.s56_6) align 4 %{{[^ ]*}}) // CHECK: } // // [i386] clang misaligns long double in structures diff --git a/clang/test/CodeGen/X86/x86_32-arguments-nommx.c b/clang/test/CodeGen/X86/x86_32-arguments-nommx.c index 58f3e7f1e0ff64f68eb38c144af66728b3172391..bc740d0f36556cecc33052c60167227240da6d65 100644 --- a/clang/test/CodeGen/X86/x86_32-arguments-nommx.c +++ b/clang/test/CodeGen/X86/x86_32-arguments-nommx.c @@ -3,9 +3,9 @@ // no-mmx should put mmx into memory typedef int __attribute__((vector_size (8))) i32v2; int a(i32v2 x) { return x[0]; } -// CHECK-LABEL: define{{.*}} i32 @a(i64 noundef %x.coerce) +// CHECK-LABEL: define{{.*}} i32 @a(i64 %x.coerce) // but SSE2 vectors should still go into an SSE2 register typedef int __attribute__((vector_size (16))) i32v4; int b(i32v4 x) { return x[0]; } -// CHECK-LABEL: define{{.*}} i32 @b(<4 x i32> noundef %x) +// CHECK-LABEL: define{{.*}} i32 @b(<4 x i32> %x) diff --git a/clang/test/CodeGen/X86/x86_32-arguments-realign.c b/clang/test/CodeGen/X86/x86_32-arguments-realign.c index 16dc46d82f543071d9450bc82182c9afcdcb4439..dd473777ce1899b9fac8499a9982c1a1d6967360 100644 --- a/clang/test/CodeGen/X86/x86_32-arguments-realign.c +++ b/clang/test/CodeGen/X86/x86_32-arguments-realign.c @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -w -fblocks -triple i386-apple-darwin9 -emit-llvm -o %t %s // RUN: FileCheck < %t %s -// CHECK-LABEL: define{{.*}} void @f0(%struct.s0* noundef byval(%struct.s0) align 4 %0) +// CHECK-LABEL: define{{.*}} void @f0(%struct.s0* byval(%struct.s0) align 4 %0) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 16 %{{.*}}, i8* align 4 %{{.*}}, i32 16, i1 false) // CHECK: } struct s0 { long double a; }; diff --git a/clang/test/CodeGen/X86/x86_32-arguments-win32.c b/clang/test/CodeGen/X86/x86_32-arguments-win32.c index 90d5c3aff3ac5da748d4ddbe4195737f59e44929..33a6216a62bd71d8ce28966ce16d83ebf49535ba 100644 --- a/clang/test/CodeGen/X86/x86_32-arguments-win32.c +++ b/clang/test/CodeGen/X86/x86_32-arguments-win32.c @@ -72,10 +72,10 @@ void receive_vec_512(__m512 x, __m512 y, __m512 z, __m512 w, __m512 q) { void receive_vec_1024(__m1024 x, __m1024 y, __m1024 z, __m1024 w, __m1024 q) { gv1024 = x + y + z + w + q; } -// CHECK-LABEL: define dso_local void @receive_vec_128(<4 x float> inreg noundef %x, <4 x float> inreg noundef %y, <4 x float> inreg noundef %z, <4 x float>* noundef %0, <4 x float>* noundef %1) -// CHECK-LABEL: define dso_local void @receive_vec_256(<8 x float> inreg noundef %x, <8 x float> inreg noundef %y, <8 x float> inreg noundef %z, <8 x float>* noundef %0, <8 x float>* noundef %1) -// CHECK-LABEL: define dso_local void @receive_vec_512(<16 x float> inreg noundef %x, <16 x float> inreg noundef %y, <16 x float> inreg noundef %z, <16 x float>* noundef %0, <16 x float>* noundef %1) -// CHECK-LABEL: define dso_local void @receive_vec_1024(<32 x float>* noundef %0, <32 x float>* noundef %1, <32 x float>* noundef %2, <32 x float>* noundef %3, <32 x float>* noundef %4) +// CHECK-LABEL: define dso_local void @receive_vec_128(<4 x float> inreg %x, <4 x float> inreg %y, <4 x float> inreg %z, <4 x float>* %0, <4 x float>* %1) +// CHECK-LABEL: define dso_local void @receive_vec_256(<8 x float> inreg %x, <8 x float> inreg %y, <8 x float> inreg %z, <8 x float>* %0, <8 x float>* %1) +// CHECK-LABEL: define dso_local void @receive_vec_512(<16 x float> inreg %x, <16 x float> inreg %y, <16 x float> inreg %z, <16 x float>* %0, <16 x float>* %1) +// CHECK-LABEL: define dso_local void @receive_vec_1024(<32 x float>* %0, <32 x float>* %1, <32 x float>* %2, <32 x float>* %3, <32 x float>* %4) void pass_vec_128() { __m128 z = {0}; @@ -83,10 +83,10 @@ void pass_vec_128() { } // CHECK-LABEL: define dso_local void @pass_vec_128() -// CHECK: call void @receive_vec_128(<4 x float> inreg noundef %{{[^,)]*}}, <4 x float> inreg noundef %{{[^,)]*}}, <4 x float> inreg noundef %{{[^,)]*}}, <4 x float>* noundef %{{[^,)]*}}, <4 x float>* noundef %{{[^,)]*}}) +// CHECK: call void @receive_vec_128(<4 x float> inreg %{{[^,)]*}}, <4 x float> inreg %{{[^,)]*}}, <4 x float> inreg %{{[^,)]*}}, <4 x float>* %{{[^,)]*}}, <4 x float>* %{{[^,)]*}}) void __fastcall fastcall_indirect_vec(__m128 x, __m128 y, __m128 z, __m128 w, int edx, __m128 q) { gv128 = x + y + z + w + q; } -// CHECK-LABEL: define dso_local x86_fastcallcc void @"\01@fastcall_indirect_vec@84"(<4 x float> inreg noundef %x, <4 x float> inreg noundef %y, <4 x float> inreg noundef %z, <4 x float>* inreg noundef %0, i32 inreg noundef %edx, <4 x float>* noundef %1) +// CHECK-LABEL: define dso_local x86_fastcallcc void @"\01@fastcall_indirect_vec@84"(<4 x float> inreg %x, <4 x float> inreg %y, <4 x float> inreg %z, <4 x float>* inreg %0, i32 inreg %edx, <4 x float>* %1) diff --git a/clang/test/CodeGen/X86/x86_64-arguments-nacl.c b/clang/test/CodeGen/X86/x86_64-arguments-nacl.c index bed6ca5518503014c93c8d54e4bec4f8971d6a0f..fe481147091c290dc919a0a9a9cac72bdf316137 100644 --- a/clang/test/CodeGen/X86/x86_64-arguments-nacl.c +++ b/clang/test/CodeGen/X86/x86_64-arguments-nacl.c @@ -30,7 +30,7 @@ long double f5(void) { return 0; } -// CHECK-LABEL: define{{.*}} void @f6(i8 noundef signext %a0, i16 noundef signext %a1, i32 noundef %a2, i64 noundef %a3, i8* noundef %a4) +// CHECK-LABEL: define{{.*}} void @f6(i8 signext %a0, i16 signext %a1, i32 %a2, i64 %a3, i8* %a4) void f6(char a0, short a1, int a2, long long a3, void *a4) { } @@ -61,14 +61,14 @@ void f12_1(struct s12 a0) {} // Check that sret parameter is accounted for when checking available integer // registers. -// CHECK: define{{.*}} void @f13(%struct.s13_0* noalias sret(%struct.s13_0) align 8 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, {{.*}}* noundef byval({{.*}}) align 8 %e, i32 noundef %f) +// CHECK: define{{.*}} void @f13(%struct.s13_0* noalias sret(%struct.s13_0) align 8 %agg.result, i32 %a, i32 %b, i32 %c, i32 %d, {{.*}}* byval({{.*}}) align 8 %e, i32 %f) struct s13_0 { long long f0[3]; }; struct s13_1 { long long f0[2]; }; struct s13_0 f13(int a, int b, int c, int d, struct s13_1 e, int f) { while (1) {} } -// CHECK-LABEL: define{{.*}} void @f20(%struct.s20* noundef byval(%struct.s20) align 32 %x) +// CHECK-LABEL: define{{.*}} void @f20(%struct.s20* byval(%struct.s20) align 32 %x) struct __attribute__((aligned(32))) s20 { int x; int y; diff --git a/clang/test/CodeGen/X86/x86_64-arguments-win32.c b/clang/test/CodeGen/X86/x86_64-arguments-win32.c index 69bc2d4e81f49939f711ec0655c243a12bf29d6c..2d2baf0dff673f1c16dce42ca871fa95aceac3cf 100644 --- a/clang/test/CodeGen/X86/x86_64-arguments-win32.c +++ b/clang/test/CodeGen/X86/x86_64-arguments-win32.c @@ -3,25 +3,25 @@ // To be ABI compatible with code generated by MSVC, there shouldn't be any // sign/zero extensions on types smaller than 64bit. -// CHECK-LABEL: define dso_local void @f1(i8 noundef %a) +// CHECK-LABEL: define dso_local void @f1(i8 %a) void f1(char a) {} -// CHECK-LABEL: define dso_local void @f2(i8 noundef %a) +// CHECK-LABEL: define dso_local void @f2(i8 %a) void f2(unsigned char a) {} -// CHECK-LABEL: define dso_local void @f3(i16 noundef %a) +// CHECK-LABEL: define dso_local void @f3(i16 %a) void f3(short a) {} -// CHECK-LABEL: define dso_local void @f4(i16 noundef %a) +// CHECK-LABEL: define dso_local void @f4(i16 %a) void f4(unsigned short a) {} // For ABI compatibility with ICC, _Complex should be passed/returned // as if it were a struct with two elements. -// CHECK-LABEL: define dso_local void @f5(i64 noundef %a.coerce) +// CHECK-LABEL: define dso_local void @f5(i64 %a.coerce) void f5(_Complex float a) {} -// CHECK-LABEL: define dso_local void @f6({ double, double }* noundef %a) +// CHECK-LABEL: define dso_local void @f6({ double, double }* %a) void f6(_Complex double a) {} // CHECK-LABEL: define dso_local i64 @f7() diff --git a/clang/test/CodeGen/X86/x86_64-arguments.c b/clang/test/CodeGen/X86/x86_64-arguments.c index f45ee6db5e4ff5b1bc99046afc788527d416518f..8898feb3e12b4c29877dd8447ee90a279ea722cd 100644 --- a/clang/test/CodeGen/X86/x86_64-arguments.c +++ b/clang/test/CodeGen/X86/x86_64-arguments.c @@ -36,11 +36,11 @@ long double f5(void) { return 0; } -// CHECK-LABEL: define{{.*}} void @f6(i8 noundef signext %a0, i16 noundef signext %a1, i32 noundef %a2, i64 noundef %a3, i8* noundef %a4) +// CHECK-LABEL: define{{.*}} void @f6(i8 signext %a0, i16 signext %a1, i32 %a2, i64 %a3, i8* %a4) void f6(char a0, short a1, int a2, long long a3, void *a4) { } -// CHECK-LABEL: define{{.*}} void @f7(i32 noundef %a0) +// CHECK-LABEL: define{{.*}} void @f7(i32 %a0) typedef enum { A, B, C } e7; void f7(e7 a0) { } @@ -48,7 +48,7 @@ void f7(e7 a0) { // Test merging/passing of upper eightbyte with X87 class. // // CHECK-LABEL: define{{.*}} void @f8_1(%union.u8* noalias sret(%union.u8) align 16 %agg.result) -// CHECK-LABEL: define{{.*}} void @f8_2(%union.u8* noundef byval(%union.u8) align 16 %a0) +// CHECK-LABEL: define{{.*}} void @f8_2(%union.u8* byval(%union.u8) align 16 %a0) union u8 { long double a; int b; @@ -74,43 +74,43 @@ void f12_1(struct s12 a0) {} // Check that sret parameter is accounted for when checking available integer // registers. -// CHECK: define{{.*}} void @f13(%struct.s13_0* noalias sret(%struct.s13_0) align 8 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, {{.*}}* noundef byval({{.*}}) align 8 %e, i32 noundef %f) +// CHECK: define{{.*}} void @f13(%struct.s13_0* noalias sret(%struct.s13_0) align 8 %agg.result, i32 %a, i32 %b, i32 %c, i32 %d, {{.*}}* byval({{.*}}) align 8 %e, i32 %f) struct s13_0 { long long f0[3]; }; struct s13_1 { long long f0[2]; }; struct s13_0 f13(int a, int b, int c, int d, struct s13_1 e, int f) { while (1) {} } -// CHECK: define{{.*}} void @f14({{.*}}, i8 noundef signext %X) +// CHECK: define{{.*}} void @f14({{.*}}, i8 signext %X) void f14(int a, int b, int c, int d, int e, int f, char X) {} -// CHECK: define{{.*}} void @f15({{.*}}, i8* noundef %X) +// CHECK: define{{.*}} void @f15({{.*}}, i8* %X) void f15(int a, int b, int c, int d, int e, int f, void *X) {} -// CHECK: define{{.*}} void @f16({{.*}}, float noundef %X) +// CHECK: define{{.*}} void @f16({{.*}}, float %X) void f16(float a, float b, float c, float d, float e, float f, float g, float h, float X) {} -// CHECK: define{{.*}} void @f17({{.*}}, x86_fp80 noundef %X) +// CHECK: define{{.*}} void @f17({{.*}}, x86_fp80 %X) void f17(float a, float b, float c, float d, float e, float f, float g, float h, long double X) {} // Check for valid coercion. The struct should be passed/returned as i32, not // as i64 for better code quality. // rdar://8135035 -// CHECK-LABEL: define{{.*}} void @f18(i32 noundef %a, i32 %f18_arg1.coerce) +// CHECK-LABEL: define{{.*}} void @f18(i32 %a, i32 %f18_arg1.coerce) struct f18_s0 { int f0; }; void f18(int a, struct f18_s0 f18_arg1) { while (1) {} } // Check byval alignment. -// CHECK-LABEL: define{{.*}} void @f19(%struct.s19* noundef byval(%struct.s19) align 16 %x) +// CHECK-LABEL: define{{.*}} void @f19(%struct.s19* byval(%struct.s19) align 16 %x) struct s19 { long double a; }; void f19(struct s19 x) {} -// CHECK-LABEL: define{{.*}} void @f20(%struct.s20* noundef byval(%struct.s20) align 32 %x) +// CHECK-LABEL: define{{.*}} void @f20(%struct.s20* byval(%struct.s20) align 32 %x) struct __attribute__((aligned(32))) s20 { int x; int y; @@ -144,7 +144,7 @@ struct f23S { void f23(int A, struct f23S B) { - // CHECK-LABEL: define{{.*}} void @f23(i32 noundef %A, i64 %B.coerce0, i32 %B.coerce1) + // CHECK-LABEL: define{{.*}} void @f23(i32 %A, i64 %B.coerce0, i32 %B.coerce1) } struct f24s { long a; int b; }; @@ -152,13 +152,13 @@ struct f24s { long a; int b; }; struct f23S f24(struct f23S *X, struct f24s *P2) { return *X; - // CHECK: define{{.*}} { i64, i32 } @f24(%struct.f23S* noundef %X, %struct.f24s* noundef %P2) + // CHECK: define{{.*}} { i64, i32 } @f24(%struct.f23S* %X, %struct.f24s* %P2) } // rdar://8248065 typedef float v4f32 __attribute__((__vector_size__(16))); v4f32 f25(v4f32 X) { - // CHECK-LABEL: define{{.*}} <4 x float> @f25(<4 x float> noundef %X) + // CHECK-LABEL: define{{.*}} <4 x float> @f25(<4 x float> %X) // CHECK-NOT: alloca // CHECK: alloca <4 x float> // CHECK-NOT: alloca @@ -174,7 +174,7 @@ struct foo26 { }; struct foo26 f26(struct foo26 *P) { - // CHECK: define{{.*}} { i32*, float* } @f26(%struct.foo26* noundef %P) + // CHECK: define{{.*}} { i32*, float* } @f26(%struct.foo26* %P) return *P; } @@ -246,7 +246,7 @@ float f31(struct f31foo X) { _Complex float f32(_Complex float A, _Complex float B) { // rdar://6379669 - // CHECK-LABEL: define{{.*}} <2 x float> @f32(<2 x float> noundef %A.coerce, <2 x float> noundef %B.coerce) + // CHECK-LABEL: define{{.*}} <2 x float> @f32(<2 x float> %A.coerce, <2 x float> %B.coerce) return A+B; } @@ -261,17 +261,17 @@ void f33(va_list X) { typedef unsigned long long v1i64 __attribute__((__vector_size__(8))); // rdar://8359248 -// CHECK-LABEL: define{{.*}} double @f34(double noundef %arg.coerce) +// CHECK-LABEL: define{{.*}} double @f34(double %arg.coerce) v1i64 f34(v1i64 arg) { return arg; } // rdar://8358475 -// CHECK-LABEL: define{{.*}} double @f35(double noundef %arg.coerce) +// CHECK-LABEL: define{{.*}} double @f35(double %arg.coerce) typedef unsigned long v1i64_2 __attribute__((__vector_size__(8))); v1i64_2 f35(v1i64_2 arg) { return arg+arg; } // rdar://9122143 -// CHECK: declare void @func(%struct._str* noundef byval(%struct._str) align 16) +// CHECK: declare void @func(%struct._str* byval(%struct._str) align 16) typedef struct _str { union { long double a; @@ -286,14 +286,14 @@ void f9122143() func(ss); } -// CHECK-LABEL: define{{.*}} double @f36(double noundef %arg.coerce) +// CHECK-LABEL: define{{.*}} double @f36(double %arg.coerce) typedef unsigned v2i32 __attribute((__vector_size__(8))); v2i32 f36(v2i32 arg) { return arg; } // AVX: declare void @f38(<8 x float>) -// AVX: declare void @f37(<8 x float> noundef) -// SSE: declare void @f38(%struct.s256* noundef byval(%struct.s256) align 32) -// SSE: declare void @f37(<8 x float>* noundef byval(<8 x float>) align 32) +// AVX: declare void @f37(<8 x float>) +// SSE: declare void @f38(%struct.s256* byval(%struct.s256) align 32) +// SSE: declare void @f37(<8 x float>* byval(<8 x float>) align 32) typedef float __m256 __attribute__ ((__vector_size__ (32))); typedef struct { __m256 m; @@ -309,7 +309,7 @@ void f39() { f38(x38); f37(x37); } // The two next tests make sure that the struct below is passed // in the same way regardless of avx being used -// CHECK: declare void @func40(%struct.t128* noundef byval(%struct.t128) align 16) +// CHECK: declare void @func40(%struct.t128* byval(%struct.t128) align 16) typedef float __m128 __attribute__ ((__vector_size__ (16))); typedef struct t128 { __m128 m; @@ -321,7 +321,7 @@ void func41(two128 s) { func40(s); } -// CHECK: declare void @func42(%struct.t128_2* noundef byval(%struct.t128_2) align 16) +// CHECK: declare void @func42(%struct.t128_2* byval(%struct.t128_2) align 16) typedef struct xxx { __m128 array[2]; } Atwo128; @@ -350,7 +350,7 @@ int f44(int i, ...) { } // Text that vec3 returns the correct LLVM IR type. -// AVX-LABEL: define{{.*}} i32 @foo(<3 x i64> noundef %X) +// AVX-LABEL: define{{.*}} i32 @foo(<3 x i64> %X) typedef long long3 __attribute((ext_vector_type(3))); int foo(long3 X) { @@ -368,7 +368,7 @@ void test45() { f45(x45); } // Make sure we use byval to pass 64-bit vectors in memory; the LLVM call // lowering can't handle this case correctly because it runs after legalization. // CHECK: @test46 -// CHECK: call void @f46({{.*}}<2 x float>* noundef byval(<2 x float>) align 8 {{.*}}, <2 x float>* noundef byval(<2 x float>) align 8 {{.*}}) +// CHECK: call void @f46({{.*}}<2 x float>* byval(<2 x float>) align 8 {{.*}}, <2 x float>* byval(<2 x float>) align 8 {{.*}}) typedef float v46 __attribute((vector_size(8))); void f46(v46,v46,v46,v46,v46,v46,v46,v46,v46,v46); void test46() { v46 x = {1,2}; f46(x,x,x,x,x,x,x,x,x,x); } @@ -409,7 +409,7 @@ void test49(double d, double e) { // CHECK-LABEL: define{{.*}} void @test49( // CHECK: [[T0:%.*]] = load double, double* // CHECK-NEXT: [[T1:%.*]] = load double, double* -// CHECK-NEXT: call void (double, ...) @test49_helper(double noundef [[T0]], double noundef [[T1]]) +// CHECK-NEXT: call void (double, ...) @test49_helper(double [[T0]], double [[T1]]) void test50_helper(); void test50(double d, double e) { @@ -418,7 +418,7 @@ void test50(double d, double e) { // CHECK-LABEL: define{{.*}} void @test50( // CHECK: [[T0:%.*]] = load double, double* // CHECK-NEXT: [[T1:%.*]] = load double, double* -// CHECK-NEXT: call void (double, double, ...) bitcast (void (...)* @test50_helper to void (double, double, ...)*)(double noundef [[T0]], double noundef [[T1]]) +// CHECK-NEXT: call void (double, double, ...) bitcast (void (...)* @test50_helper to void (double, double, ...)*)(double [[T0]], double [[T1]]) struct test51_s { __uint128_t intval; }; void test51(struct test51_s *s, __builtin_va_list argList) { @@ -444,7 +444,7 @@ __m256 x52; void test52() { test52_helper(0, x52, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0i); } -// AVX: @test52_helper(i32 noundef 0, <8 x float> noundef {{%[a-zA-Z0-9]+}}, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef {{%[a-zA-Z0-9]+}}, double noundef {{%[a-zA-Z0-9]+}}) +// AVX: @test52_helper(i32 0, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}}) void test53(__m256 *m, __builtin_va_list argList) { *m = __builtin_va_arg(argList, __m256); @@ -459,8 +459,8 @@ void test54() { test54_helper(x54, x54, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0i); test54_helper(x54, x54, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0i); } -// AVX: @test54_helper(<8 x float> noundef {{%[a-zA-Z0-9]+}}, <8 x float> noundef {{%[a-zA-Z0-9]+}}, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef {{%[a-zA-Z0-9]+}}, double noundef {{%[a-zA-Z0-9]+}}) -// AVX: @test54_helper(<8 x float> noundef {{%[a-zA-Z0-9]+}}, <8 x float> noundef {{%[a-zA-Z0-9]+}}, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, { double, double }* noundef byval({ double, double }) align 8 {{%[^)]+}}) +// AVX: @test54_helper(<8 x float> {{%[a-zA-Z0-9]+}}, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}}) +// AVX: @test54_helper(<8 x float> {{%[a-zA-Z0-9]+}}, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, { double, double }* byval({ double, double }) align 8 {{%[^)]+}}) typedef float __m512 __attribute__ ((__vector_size__ (64))); typedef struct { @@ -474,20 +474,20 @@ __m512 x56; // as per https://github.com/hjl-tools/x86-psABI/commit/30f9c9 3.2.3p2 Rule 1 // // AVX512: declare void @f55(<16 x float>) -// NO-AVX512: declare void @f55(%struct.s512* noundef byval(%struct.s512) align 64) +// NO-AVX512: declare void @f55(%struct.s512* byval(%struct.s512) align 64) void f55(s512 x); // __m512 has type SSE/SSEUP on AVX512. // -// AVX512: declare void @f56(<16 x float> noundef) -// NO-AVX512: declare void @f56(<16 x float>* noundef byval(<16 x float>) align 64) +// AVX512: declare void @f56(<16 x float>) +// NO-AVX512: declare void @f56(<16 x float>* byval(<16 x float>) align 64) void f56(__m512 x); void f57() { f55(x55); f56(x56); } // Like for __m128 on AVX, check that the struct below is passed // in the same way regardless of AVX512 being used. // -// CHECK: declare void @f58(%struct.t256* noundef byval(%struct.t256) align 32) +// CHECK: declare void @f58(%struct.t256* byval(%struct.t256) align 32) typedef struct t256 { __m256 m; __m256 n; @@ -498,7 +498,7 @@ void f59(two256 s) { f58(s); } -// CHECK: declare void @f60(%struct.sat256* noundef byval(%struct.sat256) align 32) +// CHECK: declare void @f60(%struct.sat256* byval(%struct.sat256) align 32) typedef struct at256 { __m256 array[2]; } Atwo256; @@ -511,7 +511,7 @@ void f61(SAtwo256 s) { f60(s); } -// AVX512: @f62_helper(i32 noundef 0, <16 x float> noundef {{%[a-zA-Z0-9]+}}, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef {{%[a-zA-Z0-9]+}}, double noundef {{%[a-zA-Z0-9]+}}) +// AVX512: @f62_helper(i32 0, <16 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}}) void f62_helper(int, ...); __m512 x62; void f62() { @@ -528,8 +528,8 @@ void f63(__m512 *m, __builtin_va_list argList) { *m = __builtin_va_arg(argList, __m512); } -// AVX512: @f64_helper(<16 x float> noundef {{%[a-zA-Z0-9]+}}, <16 x float> noundef {{%[a-zA-Z0-9]+}}, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef {{%[a-zA-Z0-9]+}}, double noundef {{%[a-zA-Z0-9]+}}) -// AVX512: @f64_helper(<16 x float> noundef {{%[a-zA-Z0-9]+}}, <16 x float> noundef {{%[a-zA-Z0-9]+}}, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, { double, double }* noundef byval({ double, double }) align 8 {{%[^)]+}}) +// AVX512: @f64_helper(<16 x float> {{%[a-zA-Z0-9]+}}, <16 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}}) +// AVX512: @f64_helper(<16 x float> {{%[a-zA-Z0-9]+}}, <16 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, { double, double }* byval({ double, double }) align 8 {{%[^)]+}}) void f64_helper(__m512, ...); __m512 x64; void f64() { @@ -541,7 +541,7 @@ struct t65 { __m256 m; int : 0; }; -// SSE-LABEL: @f65(%struct.t65* noundef byval(%struct.t65) align 32 %{{[^,)]+}}) +// SSE-LABEL: @f65(%struct.t65* byval(%struct.t65) align 32 %{{[^,)]+}}) // AVX: @f65(<8 x float> %{{[^,)]+}}) void f65(struct t65 a0) { } diff --git a/clang/test/CodeGen/X86/x86_64-instrument-functions.c b/clang/test/CodeGen/X86/x86_64-instrument-functions.c index 14e2199b0aeded1d77289eab82d27cb7893a6d77..0d414b4eb0cc762f121a07d3791b513fd976cdfa 100644 --- a/clang/test/CodeGen/X86/x86_64-instrument-functions.c +++ b/clang/test/CodeGen/X86/x86_64-instrument-functions.c @@ -1,8 +1,4 @@ // REQUIRES: x86-registered-target -// RUN: %clang_cc1 -fno-experimental-new-pass-manager -triple x86_64-unknown-unknown -S -finstrument-functions -O0 -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -fno-experimental-new-pass-manager -triple x86_64-unknown-unknown -S -finstrument-functions -O2 -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -fno-experimental-new-pass-manager -triple x86_64-unknown-unknown -S -finstrument-functions-after-inlining -O2 -o - -emit-llvm %s | FileCheck -check-prefix=NOINLINE %s - // RUN: %clang_cc1 -fexperimental-new-pass-manager -triple x86_64-unknown-unknown -S -finstrument-functions -O0 -o - -emit-llvm %s | FileCheck %s // RUN: %clang_cc1 -fexperimental-new-pass-manager -triple x86_64-unknown-unknown -S -finstrument-functions -O2 -o - -emit-llvm %s | FileCheck %s // RUN: %clang_cc1 -fexperimental-new-pass-manager -triple x86_64-unknown-unknown -S -finstrument-functions-after-inlining -O2 -o - -emit-llvm %s | FileCheck -check-prefix=NOINLINE %s diff --git a/clang/test/CodeGen/X86/x86_64-longdouble.c b/clang/test/CodeGen/X86/x86_64-longdouble.c index b01b3ad857b78df8c38eff9385dfe5677d25d187..52bb36cbe85141bfa5bc46eb894de9d73461738d 100644 --- a/clang/test/CodeGen/X86/x86_64-longdouble.c +++ b/clang/test/CodeGen/X86/x86_64-longdouble.c @@ -20,16 +20,16 @@ long double _Complex dataLDC = {1.0L, 1.0L}; long double TestLD(long double x) { return x * x; -// ANDROID: define{{.*}} fp128 @TestLD(fp128 noundef %x) -// GNU: define{{.*}} x86_fp80 @TestLD(x86_fp80 noundef %x) -// NACL: define{{.*}} double @TestLD(double noundef %x) +// ANDROID: define{{.*}} fp128 @TestLD(fp128 %x) +// GNU: define{{.*}} x86_fp80 @TestLD(x86_fp80 %x) +// NACL: define{{.*}} double @TestLD(double %x) } long double _Complex TestLDC(long double _Complex x) { return x * x; // ANDROID: define{{.*}} void @TestLDC({ fp128, fp128 }* {{.*}}, { fp128, fp128 }* {{.*}} %x) // GNU: define{{.*}} { x86_fp80, x86_fp80 } @TestLDC({ x86_fp80, x86_fp80 }* {{.*}} %x) -// NACL: define{{.*}} { double, double } @TestLDC(double noundef %x{{.*}}, double noundef %x{{.*}}) +// NACL: define{{.*}} { double, double } @TestLDC(double %x{{.*}}, double %x{{.*}}) } typedef __builtin_va_list va_list; @@ -94,30 +94,30 @@ void TestVarArg(const char *s, ...); void TestPassVarInt(int x) { TestVarArg("A", x); -// CHECK: define{{.*}} void @TestPassVarInt(i32 noundef %x) -// CHECK: call {{.*}} @TestVarArg(i8* {{.*}}, i32 noundef %x) +// CHECK: define{{.*}} void @TestPassVarInt(i32 %x) +// CHECK: call {{.*}} @TestVarArg(i8* {{.*}}, i32 %x) } void TestPassVarFloat(float x) { TestVarArg("A", x); -// CHECK: define{{.*}} void @TestPassVarFloat(float noundef %x) -// CHECK: call {{.*}} @TestVarArg(i8* {{.*}}, double noundef % +// CHECK: define{{.*}} void @TestPassVarFloat(float %x) +// CHECK: call {{.*}} @TestVarArg(i8* {{.*}}, double % } void TestPassVarDouble(double x) { TestVarArg("A", x); -// CHECK: define{{.*}} void @TestPassVarDouble(double noundef %x) -// CHECK: call {{.*}} @TestVarArg(i8* {{.*}}, double noundef %x +// CHECK: define{{.*}} void @TestPassVarDouble(double %x) +// CHECK: call {{.*}} @TestVarArg(i8* {{.*}}, double %x } void TestPassVarLD(long double x) { TestVarArg("A", x); -// ANDROID: define{{.*}} void @TestPassVarLD(fp128 noundef %x) -// ANDROID: call {{.*}} @TestVarArg(i8* {{.*}}, fp128 noundef %x -// GNU: define{{.*}} void @TestPassVarLD(x86_fp80 noundef %x) -// GNU: call {{.*}} @TestVarArg(i8* {{.*}}, x86_fp80 noundef %x -// NACL: define{{.*}} void @TestPassVarLD(double noundef %x) -// NACL: call {{.*}} @TestVarArg(i8* {{.*}}, double noundef %x +// ANDROID: define{{.*}} void @TestPassVarLD(fp128 %x) +// ANDROID: call {{.*}} @TestVarArg(i8* {{.*}}, fp128 %x +// GNU: define{{.*}} void @TestPassVarLD(x86_fp80 %x) +// GNU: call {{.*}} @TestVarArg(i8* {{.*}}, x86_fp80 %x +// NACL: define{{.*}} void @TestPassVarLD(double %x) +// NACL: call {{.*}} @TestVarArg(i8* {{.*}}, double %x } void TestPassVarLDC(long double _Complex x) { @@ -130,6 +130,6 @@ void TestPassVarLDC(long double _Complex x) { // GNU: store x86_fp80 %{{.*}}, x86_fp80* % // GNU-NEXT: store x86_fp80 %{{.*}}, x86_fp80* % // GNU-NEXT: call {{.*}} @TestVarArg(i8* {{.*}}, { x86_fp80, x86_fp80 }* {{.*}} % -// NACL: define{{.*}} void @TestPassVarLDC(double noundef %x{{.*}}, double noundef %x{{.*}}) -// NACL: call {{.*}} @TestVarArg(i8* {{.*}}, double noundef %x{{.*}}, double noundef %x{{.*}}) +// NACL: define{{.*}} void @TestPassVarLDC(double %x{{.*}}, double %x{{.*}}) +// NACL: call {{.*}} @TestVarArg(i8* {{.*}}, double %x{{.*}}, double %x{{.*}}) } diff --git a/clang/test/CodeGen/aapcs-align.cpp b/clang/test/CodeGen/aapcs-align.cpp index 15a8d86a312792635c2b5ab730b0cd96e59d2d3a..8950908183efc76818d2b99e9443eb75ede3b755 100644 --- a/clang/test/CodeGen/aapcs-align.cpp +++ b/clang/test/CodeGen/aapcs-align.cpp @@ -19,10 +19,10 @@ void g0() { f0m(1, 2, 3, 4, 5, s); } // CHECK: define{{.*}} void @g0 -// CHECK: call void @f0(i32 noundef 1, [2 x i32] [i32 6, i32 7] -// CHECK: call void @f0m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [2 x i32] [i32 6, i32 7] -// CHECK: declare void @f0(i32 noundef, [2 x i32]) -// CHECK: declare void @f0m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [2 x i32]) +// CHECK: call void @f0(i32 1, [2 x i32] [i32 6, i32 7] +// CHECK: call void @f0m(i32 1, i32 2, i32 3, i32 4, i32 5, [2 x i32] [i32 6, i32 7] +// CHECK: declare void @f0(i32, [2 x i32]) +// CHECK: declare void @f0m(i32, i32, i32, i32, i32, [2 x i32]) // Aligned struct, passed according to its natural alignment. struct __attribute__((aligned(8))) S8 { @@ -37,10 +37,10 @@ void g1() { f1m(1, 2, 3, 4, 5, s); } // CHECK: define{{.*}} void @g1 -// CHECK: call void @f1(i32 noundef 1, [2 x i32] [i32 6, i32 7] -// CHECK: call void @f1m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [2 x i32] [i32 6, i32 7] -// CHECK: declare void @f1(i32 noundef, [2 x i32]) -// CHECK: declare void @f1m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [2 x i32]) +// CHECK: call void @f1(i32 1, [2 x i32] [i32 6, i32 7] +// CHECK: call void @f1m(i32 1, i32 2, i32 3, i32 4, i32 5, [2 x i32] [i32 6, i32 7] +// CHECK: declare void @f1(i32, [2 x i32]) +// CHECK: declare void @f1m(i32, i32, i32, i32, i32, [2 x i32]) // Aligned struct, passed according to its natural alignment. struct alignas(16) S16 { @@ -56,10 +56,10 @@ void g2() { f2m(1, 2, 3, 4, 5, s); } // CHECK: define{{.*}} void @g2 -// CHECK: call void @f2(i32 noundef 1, [4 x i32] [i32 6, i32 7 -// CHECK: call void @f2m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [4 x i32] [i32 6, i32 7 -// CHECK: declare void @f2(i32 noundef, [4 x i32]) -// CHECK: declare void @f2m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [4 x i32]) +// CHECK: call void @f2(i32 1, [4 x i32] [i32 6, i32 7 +// CHECK: call void @f2m(i32 1, i32 2, i32 3, i32 4, i32 5, [4 x i32] [i32 6, i32 7 +// CHECK: declare void @f2(i32, [4 x i32]) +// CHECK: declare void @f2m(i32, i32, i32, i32, i32, [4 x i32]) // Increased natural alignment. struct SF8 { @@ -75,10 +75,10 @@ void g3() { f3m(1, 2, 3, 4, 5, s); } // CHECK: define{{.*}} void @g3 -// CHECK: call void @f3(i32 noundef 1, [1 x i64] [i64 30064771078] -// CHECK: call void @f3m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [1 x i64] [i64 30064771078] -// CHECK: declare void @f3(i32 noundef, [1 x i64]) -// CHECK: declare void @f3m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [1 x i64]) +// CHECK: call void @f3(i32 1, [1 x i64] [i64 30064771078] +// CHECK: call void @f3m(i32 1, i32 2, i32 3, i32 4, i32 5, [1 x i64] [i64 30064771078] +// CHECK: declare void @f3(i32, [1 x i64]) +// CHECK: declare void @f3m(i32, i32, i32, i32, i32, [1 x i64]) // Increased natural alignment, capped to 8 though. struct SF16 { @@ -95,10 +95,10 @@ void g4() { f4m(1, 2, 3, 4, 5, s); } // CHECK: define{{.*}} void @g4 -// CHECK: call void @f4(i32 noundef 1, %struct.SF16* noundef nonnull byval(%struct.SF16) align 8 -// CHECK: call void @f4m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, %struct.SF16* noundef nonnull byval(%struct.SF16) align 8 -// CHECK: declare void @f4(i32 noundef, %struct.SF16* noundef byval(%struct.SF16) align 8) -// CHECK: declare void @f4m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, %struct.SF16* noundef byval(%struct.SF16) align 8) +// CHECK: call void @f4(i32 1, %struct.SF16* nonnull byval(%struct.SF16) align 8 +// CHECK: call void @f4m(i32 1, i32 2, i32 3, i32 4, i32 5, %struct.SF16* nonnull byval(%struct.SF16) align 8 +// CHECK: declare void @f4(i32, %struct.SF16* byval(%struct.SF16) align 8) +// CHECK: declare void @f4m(i32, i32, i32, i32, i32, %struct.SF16* byval(%struct.SF16) align 8) // Packed structure. struct __attribute__((packed)) P { @@ -114,10 +114,10 @@ void g5() { f5m(1, 2, 3, 4, 5, s); } // CHECK: define{{.*}} void @g5 -// CHECK: call void @f5(i32 noundef 1, [3 x i32] [i32 6, i32 7, i32 0]) -// CHECK: call void @f5m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [3 x i32] [i32 6, i32 7, i32 0]) -// CHECK: declare void @f5(i32 noundef, [3 x i32]) -// CHECK: declare void @f5m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [3 x i32]) +// CHECK: call void @f5(i32 1, [3 x i32] [i32 6, i32 7, i32 0]) +// CHECK: call void @f5m(i32 1, i32 2, i32 3, i32 4, i32 5, [3 x i32] [i32 6, i32 7, i32 0]) +// CHECK: declare void @f5(i32, [3 x i32]) +// CHECK: declare void @f5m(i32, i32, i32, i32, i32, [3 x i32]) // Packed and aligned, alignement causes padding at the end. @@ -134,8 +134,8 @@ void g6() { f6m(1, 2, 3, 4, 5, s); } // CHECK: define{{.*}} void @g6 -// CHECK: call void @f6(i32 noundef 1, [4 x i32] [i32 6, i32 7, i32 0, i32 0]) -// CHECK: call void @f6m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [4 x i32] [i32 6, i32 7, i32 0, i32 0]) -// CHECK: declare void @f6(i32 noundef, [4 x i32]) -// CHECK: declare void @f6m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [4 x i32]) +// CHECK: call void @f6(i32 1, [4 x i32] [i32 6, i32 7, i32 0, i32 0]) +// CHECK: call void @f6m(i32 1, i32 2, i32 3, i32 4, i32 5, [4 x i32] [i32 6, i32 7, i32 0, i32 0]) +// CHECK: declare void @f6(i32, [4 x i32]) +// CHECK: declare void @f6m(i32, i32, i32, i32, i32, [4 x i32]) } diff --git a/clang/test/CodeGen/aapcs64-align.cpp b/clang/test/CodeGen/aapcs64-align.cpp index 7b673493d6e19090d9db83db195684b48d3d6c2f..02f8b12eb8120e7598c0810012ffc5516acc3296 100644 --- a/clang/test/CodeGen/aapcs64-align.cpp +++ b/clang/test/CodeGen/aapcs64-align.cpp @@ -18,10 +18,10 @@ void g0() { f0m(1, 2, 3, 4, 5, s); } // CHECK: define{{.*}} void @g0 -// CHECK: call void @f0(i64 noundef 1, [2 x i64] [i64 6, i64 7] +// CHECK: call void @f0(i64 1, [2 x i64] [i64 6, i64 7] // CHECK: call void @f0m{{.*}}[2 x i64] [i64 6, i64 7] -// CHECK: declare void @f0(i64 noundef, [2 x i64]) -// CHECK: declare void @f0m(i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, [2 x i64]) +// CHECK: declare void @f0(i64, [2 x i64]) +// CHECK: declare void @f0m(i64, i64, i64, i64, i64, [2 x i64]) // Aligned struct, passed according to its natural alignment. struct __attribute__((aligned(16))) S16 { @@ -38,8 +38,8 @@ void g1() { // CHECK: define{{.*}} void @g1 // CHECK: call void @f1{{.*}}[2 x i64] [i64 6, i64 7] // CHECK: call void @f1m{{.*}}[2 x i64] [i64 6, i64 7] -// CHECK: declare void @f1(i64 noundef, [2 x i64]) -// CHECK: declare void @f1m(i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, [2 x i64]) +// CHECK: declare void @f1(i64, [2 x i64]) +// CHECK: declare void @f1m(i64, i64, i64, i64, i64, [2 x i64]) // Increased natural alignment. struct SF16 { @@ -55,10 +55,10 @@ void g3() { f3m(1, 2, 3, 4, 5, s); } // CHECK: define{{.*}} void @g3 -// CHECK: call void @f3(i64 noundef 1, i128 129127208515966861318) -// CHECK: call void @f3m(i64 noundef 1, i64 noundef 2, i64 noundef 3, i64 noundef 4, i64 noundef 5, i128 129127208515966861318) -// CHECK: declare void @f3(i64 noundef, i128) -// CHECK: declare void @f3m(i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i128) +// CHECK: call void @f3(i64 1, i128 129127208515966861318) +// CHECK: call void @f3m(i64 1, i64 2, i64 3, i64 4, i64 5, i128 129127208515966861318) +// CHECK: declare void @f3(i64, i128) +// CHECK: declare void @f3m(i64, i64, i64, i64, i64, i128) // Packed structure. @@ -75,10 +75,10 @@ void g4() { f4m(1, 2, 3, 4, 5, s); } // CHECK: define{{.*}} void @g4() -// CHECK: call void @f4(i32 noundef 1, [2 x i64] [i64 30064771078, i64 0]) -// CHECK: void @f4m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [2 x i64] [i64 30064771078, i64 0]) -// CHECK: declare void @f4(i32 noundef, [2 x i64]) -// CHECK: declare void @f4m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [2 x i64]) +// CHECK: call void @f4(i32 1, [2 x i64] [i64 30064771078, i64 0]) +// CHECK: void @f4m(i32 1, i32 2, i32 3, i32 4, i32 5, [2 x i64] [i64 30064771078, i64 0]) +// CHECK: declare void @f4(i32, [2 x i64]) +// CHECK: declare void @f4m(i32, i32, i32, i32, i32, [2 x i64]) // Packed structure, overaligned, same as above. @@ -95,9 +95,9 @@ void f5m(int, int, int, int, int, P16); f5m(1, 2, 3, 4, 5, s); } // CHECK: define{{.*}} void @g5() -// CHECK: call void @f5(i32 noundef 1, [2 x i64] [i64 30064771078, i64 0]) -// CHECK: void @f5m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [2 x i64] [i64 30064771078, i64 0]) -// CHECK: declare void @f5(i32 noundef, [2 x i64]) -// CHECK: declare void @f5m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [2 x i64]) +// CHECK: call void @f5(i32 1, [2 x i64] [i64 30064771078, i64 0]) +// CHECK: void @f5m(i32 1, i32 2, i32 3, i32 4, i32 5, [2 x i64] [i64 30064771078, i64 0]) +// CHECK: declare void @f5(i32, [2 x i64]) +// CHECK: declare void @f5m(i32, i32, i32, i32, i32, [2 x i64]) } diff --git a/clang/test/CodeGen/aarch64-args.cpp b/clang/test/CodeGen/aarch64-args.cpp index 2a3363663198aa21c76341d62dccf0caf943a636..c54a8e44e1408f095857847898a8a1e02d6869c2 100644 --- a/clang/test/CodeGen/aarch64-args.cpp +++ b/clang/test/CodeGen/aarch64-args.cpp @@ -15,9 +15,9 @@ struct Empty {}; -// CHECK: define{{.*}} i32 @empty_arg(i32 noundef %a) -// CHECK-GNU-C: define{{.*}} i32 @empty_arg(i32 noundef %a) -// CHECK-GNU-CXX: define{{.*}} i32 @empty_arg(i8 %e.coerce, i32 noundef %a) +// CHECK: define{{.*}} i32 @empty_arg(i32 %a) +// CHECK-GNU-C: define{{.*}} i32 @empty_arg(i32 %a) +// CHECK-GNU-CXX: define{{.*}} i32 @empty_arg(i8 %e.coerce, i32 %a) EXTERNC int empty_arg(struct Empty e, int a) { return a; } @@ -38,9 +38,9 @@ struct SuperEmpty { int arr[0]; }; -// CHECK: define{{.*}} i32 @super_empty_arg(i32 noundef %a) -// CHECK-GNU-C: define{{.*}} i32 @super_empty_arg(i32 noundef %a) -// CHECK-GNU-CXX: define{{.*}} i32 @super_empty_arg(i32 noundef %a) +// CHECK: define{{.*}} i32 @super_empty_arg(i32 %a) +// CHECK-GNU-C: define{{.*}} i32 @super_empty_arg(i32 %a) +// CHECK-GNU-CXX: define{{.*}} i32 @super_empty_arg(i32 %a) EXTERNC int super_empty_arg(struct SuperEmpty e, int a) { return a; } @@ -51,9 +51,9 @@ struct SortOfEmpty { struct SuperEmpty e; }; -// CHECK: define{{.*}} i32 @sort_of_empty_arg(i32 noundef %a) -// CHECK-GNU-C: define{{.*}} i32 @sort_of_empty_arg(i32 noundef %a) -// CHECK-GNU-CXX: define{{.*}} i32 @sort_of_empty_arg(i8 %e.coerce, i32 noundef %a) +// CHECK: define{{.*}} i32 @sort_of_empty_arg(i32 %a) +// CHECK-GNU-C: define{{.*}} i32 @sort_of_empty_arg(i32 %a) +// CHECK-GNU-CXX: define{{.*}} i32 @sort_of_empty_arg(i8 %e.coerce, i32 %a) EXTERNC int sort_of_empty_arg(struct Empty e, int a) { return a; } diff --git a/clang/test/CodeGen/aarch64-byval-temp.c b/clang/test/CodeGen/aarch64-byval-temp.c index f25a6b76dde46c5537fec32b70142505866816c8..b7d6f6894cb51cd3724f3a4111a539d3ae4a125c 100644 --- a/clang/test/CodeGen/aarch64-byval-temp.c +++ b/clang/test/CodeGen/aarch64-byval-temp.c @@ -32,12 +32,12 @@ void example() { // CHECK-O0-NEXT: %[[dst:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[l]] to i8* // CHECK-O0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[src]], i8* align 8 %[[dst]], i64 64, i1 false) // Finally, call using a pointer to the temporary stack space. -// CHECK-O0-NEXT: call void @pass_large(%struct.large* noundef %[[byvaltemp]]) +// CHECK-O0-NEXT: call void @pass_large(%struct.large* %[[byvaltemp]]) // Now, do the same for the second call, using the second temporary alloca. // CHECK-O0-NEXT: %[[src:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[byvaltemp1]] to i8* // CHECK-O0-NEXT: %[[dst:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[l]] to i8* // CHECK-O0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[src]], i8* align 8 %[[dst]], i64 64, i1 false) -// CHECK-O0-NEXT: call void @pass_large(%struct.large* noundef %[[byvaltemp1]]) +// CHECK-O0-NEXT: call void @pass_large(%struct.large* %[[byvaltemp1]]) // CHECK-O0-NEXT: ret void // // At O3, we should have lifetime markers to help the optimizer re-use the temporary allocas. @@ -67,7 +67,7 @@ void example() { // CHECK-O3-NEXT: %[[dst:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[l]] to i8* // CHECK-O3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[src]], i8* align 8 %[[dst]], i64 64, i1 false) // Finally, call using a pointer to the temporary stack space. -// CHECK-O3-NEXT: call void @pass_large(%struct.large* noundef %[[byvaltemp]]) +// CHECK-O3-NEXT: call void @pass_large(%struct.large* %[[byvaltemp]]) // // The lifetime of the temporary used to pass a pointer to the struct ends here. // CHECK-O3-NEXT: %[[bitcastbyvaltemp:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[byvaltemp]] to i8* @@ -79,7 +79,7 @@ void example() { // CHECK-O3-NEXT: %[[src:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[byvaltemp1]] to i8* // CHECK-O3-NEXT: %[[dst:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[l]] to i8* // CHECK-O3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[src]], i8* align 8 %[[dst]], i64 64, i1 false) -// CHECK-O3-NEXT: call void @pass_large(%struct.large* noundef %[[byvaltemp1]]) +// CHECK-O3-NEXT: call void @pass_large(%struct.large* %[[byvaltemp1]]) // CHECK-O3-NEXT: %[[bitcastbyvaltemp:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[byvaltemp1]] to i8* // CHECK-O3-NEXT: call void @llvm.lifetime.end.p0i8(i64 64, i8* %[[bitcastbyvaltemp]]) // diff --git a/clang/test/CodeGen/aarch64-neon-3v.c b/clang/test/CodeGen/aarch64-neon-3v.c index 1ba7e7648e33092dfe98c41fa3ebfe03a753ddb3..1ed90430edfeb977b65d26b815e55862c0123e53 100644 --- a/clang/test/CodeGen/aarch64-neon-3v.c +++ b/clang/test/CodeGen/aarch64-neon-3v.c @@ -4,343 +4,343 @@ #include -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vand_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vand_s8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[AND_I:%.*]] = and <8 x i8> %a, %b // CHECK: ret <8 x i8> [[AND_I]] int8x8_t test_vand_s8(int8x8_t a, int8x8_t b) { return vand_s8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vandq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vandq_s8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[AND_I:%.*]] = and <16 x i8> %a, %b // CHECK: ret <16 x i8> [[AND_I]] int8x16_t test_vandq_s8(int8x16_t a, int8x16_t b) { return vandq_s8(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vand_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vand_s16(<4 x i16> %a, <4 x i16> %b) #0 { // CHECK: [[AND_I:%.*]] = and <4 x i16> %a, %b // CHECK: ret <4 x i16> [[AND_I]] int16x4_t test_vand_s16(int16x4_t a, int16x4_t b) { return vand_s16(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vandq_s16(<8 x i16> %a, <8 x i16> %b) #1 { // CHECK: [[AND_I:%.*]] = and <8 x i16> %a, %b // CHECK: ret <8 x i16> [[AND_I]] int16x8_t test_vandq_s16(int16x8_t a, int16x8_t b) { return vandq_s16(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vand_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vand_s32(<2 x i32> %a, <2 x i32> %b) #0 { // CHECK: [[AND_I:%.*]] = and <2 x i32> %a, %b // CHECK: ret <2 x i32> [[AND_I]] int32x2_t test_vand_s32(int32x2_t a, int32x2_t b) { return vand_s32(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vandq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vandq_s32(<4 x i32> %a, <4 x i32> %b) #1 { // CHECK: [[AND_I:%.*]] = and <4 x i32> %a, %b // CHECK: ret <4 x i32> [[AND_I]] int32x4_t test_vandq_s32(int32x4_t a, int32x4_t b) { return vandq_s32(a, b); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vand_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vand_s64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[AND_I:%.*]] = and <1 x i64> %a, %b // CHECK: ret <1 x i64> [[AND_I]] int64x1_t test_vand_s64(int64x1_t a, int64x1_t b) { return vand_s64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vandq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vandq_s64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[AND_I:%.*]] = and <2 x i64> %a, %b // CHECK: ret <2 x i64> [[AND_I]] int64x2_t test_vandq_s64(int64x2_t a, int64x2_t b) { return vandq_s64(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vand_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vand_u8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[AND_I:%.*]] = and <8 x i8> %a, %b // CHECK: ret <8 x i8> [[AND_I]] uint8x8_t test_vand_u8(uint8x8_t a, uint8x8_t b) { return vand_u8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vandq_u8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[AND_I:%.*]] = and <16 x i8> %a, %b // CHECK: ret <16 x i8> [[AND_I]] uint8x16_t test_vandq_u8(uint8x16_t a, uint8x16_t b) { return vandq_u8(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vand_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vand_u16(<4 x i16> %a, <4 x i16> %b) #0 { // CHECK: [[AND_I:%.*]] = and <4 x i16> %a, %b // CHECK: ret <4 x i16> [[AND_I]] uint16x4_t test_vand_u16(uint16x4_t a, uint16x4_t b) { return vand_u16(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vandq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vandq_u16(<8 x i16> %a, <8 x i16> %b) #1 { // CHECK: [[AND_I:%.*]] = and <8 x i16> %a, %b // CHECK: ret <8 x i16> [[AND_I]] uint16x8_t test_vandq_u16(uint16x8_t a, uint16x8_t b) { return vandq_u16(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vand_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vand_u32(<2 x i32> %a, <2 x i32> %b) #0 { // CHECK: [[AND_I:%.*]] = and <2 x i32> %a, %b // CHECK: ret <2 x i32> [[AND_I]] uint32x2_t test_vand_u32(uint32x2_t a, uint32x2_t b) { return vand_u32(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vandq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vandq_u32(<4 x i32> %a, <4 x i32> %b) #1 { // CHECK: [[AND_I:%.*]] = and <4 x i32> %a, %b // CHECK: ret <4 x i32> [[AND_I]] uint32x4_t test_vandq_u32(uint32x4_t a, uint32x4_t b) { return vandq_u32(a, b); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vand_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vand_u64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[AND_I:%.*]] = and <1 x i64> %a, %b // CHECK: ret <1 x i64> [[AND_I]] uint64x1_t test_vand_u64(uint64x1_t a, uint64x1_t b) { return vand_u64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vandq_u64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vandq_u64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[AND_I:%.*]] = and <2 x i64> %a, %b // CHECK: ret <2 x i64> [[AND_I]] uint64x2_t test_vandq_u64(uint64x2_t a, uint64x2_t b) { return vandq_u64(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorr_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorr_s8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[OR_I:%.*]] = or <8 x i8> %a, %b // CHECK: ret <8 x i8> [[OR_I]] int8x8_t test_vorr_s8(int8x8_t a, int8x8_t b) { return vorr_s8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vorrq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vorrq_s8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[OR_I:%.*]] = or <16 x i8> %a, %b // CHECK: ret <16 x i8> [[OR_I]] int8x16_t test_vorrq_s8(int8x16_t a, int8x16_t b) { return vorrq_s8(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorr_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorr_s16(<4 x i16> %a, <4 x i16> %b) #0 { // CHECK: [[OR_I:%.*]] = or <4 x i16> %a, %b // CHECK: ret <4 x i16> [[OR_I]] int16x4_t test_vorr_s16(int16x4_t a, int16x4_t b) { return vorr_s16(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vorrq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vorrq_s16(<8 x i16> %a, <8 x i16> %b) #1 { // CHECK: [[OR_I:%.*]] = or <8 x i16> %a, %b // CHECK: ret <8 x i16> [[OR_I]] int16x8_t test_vorrq_s16(int16x8_t a, int16x8_t b) { return vorrq_s16(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorr_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorr_s32(<2 x i32> %a, <2 x i32> %b) #0 { // CHECK: [[OR_I:%.*]] = or <2 x i32> %a, %b // CHECK: ret <2 x i32> [[OR_I]] int32x2_t test_vorr_s32(int32x2_t a, int32x2_t b) { return vorr_s32(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vorrq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vorrq_s32(<4 x i32> %a, <4 x i32> %b) #1 { // CHECK: [[OR_I:%.*]] = or <4 x i32> %a, %b // CHECK: ret <4 x i32> [[OR_I]] int32x4_t test_vorrq_s32(int32x4_t a, int32x4_t b) { return vorrq_s32(a, b); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorr_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorr_s64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[OR_I:%.*]] = or <1 x i64> %a, %b // CHECK: ret <1 x i64> [[OR_I]] int64x1_t test_vorr_s64(int64x1_t a, int64x1_t b) { return vorr_s64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vorrq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vorrq_s64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[OR_I:%.*]] = or <2 x i64> %a, %b // CHECK: ret <2 x i64> [[OR_I]] int64x2_t test_vorrq_s64(int64x2_t a, int64x2_t b) { return vorrq_s64(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorr_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorr_u8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[OR_I:%.*]] = or <8 x i8> %a, %b // CHECK: ret <8 x i8> [[OR_I]] uint8x8_t test_vorr_u8(uint8x8_t a, uint8x8_t b) { return vorr_u8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vorrq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vorrq_u8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[OR_I:%.*]] = or <16 x i8> %a, %b // CHECK: ret <16 x i8> [[OR_I]] uint8x16_t test_vorrq_u8(uint8x16_t a, uint8x16_t b) { return vorrq_u8(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorr_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorr_u16(<4 x i16> %a, <4 x i16> %b) #0 { // CHECK: [[OR_I:%.*]] = or <4 x i16> %a, %b // CHECK: ret <4 x i16> [[OR_I]] uint16x4_t test_vorr_u16(uint16x4_t a, uint16x4_t b) { return vorr_u16(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vorrq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vorrq_u16(<8 x i16> %a, <8 x i16> %b) #1 { // CHECK: [[OR_I:%.*]] = or <8 x i16> %a, %b // CHECK: ret <8 x i16> [[OR_I]] uint16x8_t test_vorrq_u16(uint16x8_t a, uint16x8_t b) { return vorrq_u16(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorr_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorr_u32(<2 x i32> %a, <2 x i32> %b) #0 { // CHECK: [[OR_I:%.*]] = or <2 x i32> %a, %b // CHECK: ret <2 x i32> [[OR_I]] uint32x2_t test_vorr_u32(uint32x2_t a, uint32x2_t b) { return vorr_u32(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vorrq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vorrq_u32(<4 x i32> %a, <4 x i32> %b) #1 { // CHECK: [[OR_I:%.*]] = or <4 x i32> %a, %b // CHECK: ret <4 x i32> [[OR_I]] uint32x4_t test_vorrq_u32(uint32x4_t a, uint32x4_t b) { return vorrq_u32(a, b); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorr_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorr_u64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[OR_I:%.*]] = or <1 x i64> %a, %b // CHECK: ret <1 x i64> [[OR_I]] uint64x1_t test_vorr_u64(uint64x1_t a, uint64x1_t b) { return vorr_u64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vorrq_u64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vorrq_u64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[OR_I:%.*]] = or <2 x i64> %a, %b // CHECK: ret <2 x i64> [[OR_I]] uint64x2_t test_vorrq_u64(uint64x2_t a, uint64x2_t b) { return vorrq_u64(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_veor_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_veor_s8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[XOR_I:%.*]] = xor <8 x i8> %a, %b // CHECK: ret <8 x i8> [[XOR_I]] int8x8_t test_veor_s8(int8x8_t a, int8x8_t b) { return veor_s8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_veorq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_veorq_s8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[XOR_I:%.*]] = xor <16 x i8> %a, %b // CHECK: ret <16 x i8> [[XOR_I]] int8x16_t test_veorq_s8(int8x16_t a, int8x16_t b) { return veorq_s8(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_veor_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_veor_s16(<4 x i16> %a, <4 x i16> %b) #0 { // CHECK: [[XOR_I:%.*]] = xor <4 x i16> %a, %b // CHECK: ret <4 x i16> [[XOR_I]] int16x4_t test_veor_s16(int16x4_t a, int16x4_t b) { return veor_s16(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_veorq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_veorq_s16(<8 x i16> %a, <8 x i16> %b) #1 { // CHECK: [[XOR_I:%.*]] = xor <8 x i16> %a, %b // CHECK: ret <8 x i16> [[XOR_I]] int16x8_t test_veorq_s16(int16x8_t a, int16x8_t b) { return veorq_s16(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_veor_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_veor_s32(<2 x i32> %a, <2 x i32> %b) #0 { // CHECK: [[XOR_I:%.*]] = xor <2 x i32> %a, %b // CHECK: ret <2 x i32> [[XOR_I]] int32x2_t test_veor_s32(int32x2_t a, int32x2_t b) { return veor_s32(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_veorq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_veorq_s32(<4 x i32> %a, <4 x i32> %b) #1 { // CHECK: [[XOR_I:%.*]] = xor <4 x i32> %a, %b // CHECK: ret <4 x i32> [[XOR_I]] int32x4_t test_veorq_s32(int32x4_t a, int32x4_t b) { return veorq_s32(a, b); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_veor_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_veor_s64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[XOR_I:%.*]] = xor <1 x i64> %a, %b // CHECK: ret <1 x i64> [[XOR_I]] int64x1_t test_veor_s64(int64x1_t a, int64x1_t b) { return veor_s64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_veorq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_veorq_s64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[XOR_I:%.*]] = xor <2 x i64> %a, %b // CHECK: ret <2 x i64> [[XOR_I]] int64x2_t test_veorq_s64(int64x2_t a, int64x2_t b) { return veorq_s64(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_veor_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_veor_u8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[XOR_I:%.*]] = xor <8 x i8> %a, %b // CHECK: ret <8 x i8> [[XOR_I]] uint8x8_t test_veor_u8(uint8x8_t a, uint8x8_t b) { return veor_u8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_veorq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_veorq_u8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[XOR_I:%.*]] = xor <16 x i8> %a, %b // CHECK: ret <16 x i8> [[XOR_I]] uint8x16_t test_veorq_u8(uint8x16_t a, uint8x16_t b) { return veorq_u8(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_veor_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_veor_u16(<4 x i16> %a, <4 x i16> %b) #0 { // CHECK: [[XOR_I:%.*]] = xor <4 x i16> %a, %b // CHECK: ret <4 x i16> [[XOR_I]] uint16x4_t test_veor_u16(uint16x4_t a, uint16x4_t b) { return veor_u16(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_veorq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_veorq_u16(<8 x i16> %a, <8 x i16> %b) #1 { // CHECK: [[XOR_I:%.*]] = xor <8 x i16> %a, %b // CHECK: ret <8 x i16> [[XOR_I]] uint16x8_t test_veorq_u16(uint16x8_t a, uint16x8_t b) { return veorq_u16(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_veor_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_veor_u32(<2 x i32> %a, <2 x i32> %b) #0 { // CHECK: [[XOR_I:%.*]] = xor <2 x i32> %a, %b // CHECK: ret <2 x i32> [[XOR_I]] uint32x2_t test_veor_u32(uint32x2_t a, uint32x2_t b) { return veor_u32(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_veorq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_veorq_u32(<4 x i32> %a, <4 x i32> %b) #1 { // CHECK: [[XOR_I:%.*]] = xor <4 x i32> %a, %b // CHECK: ret <4 x i32> [[XOR_I]] uint32x4_t test_veorq_u32(uint32x4_t a, uint32x4_t b) { return veorq_u32(a, b); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_veor_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_veor_u64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[XOR_I:%.*]] = xor <1 x i64> %a, %b // CHECK: ret <1 x i64> [[XOR_I]] uint64x1_t test_veor_u64(uint64x1_t a, uint64x1_t b) { return veor_u64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_veorq_u64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_veorq_u64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[XOR_I:%.*]] = xor <2 x i64> %a, %b // CHECK: ret <2 x i64> [[XOR_I]] uint64x2_t test_veorq_u64(uint64x2_t a, uint64x2_t b) { return veorq_u64(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vbic_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vbic_s8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, // CHECK: [[AND_I:%.*]] = and <8 x i8> %a, [[NEG_I]] // CHECK: ret <8 x i8> [[AND_I]] @@ -348,7 +348,7 @@ int8x8_t test_vbic_s8(int8x8_t a, int8x8_t b) { return vbic_s8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vbicq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vbicq_s8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, // CHECK: [[AND_I:%.*]] = and <16 x i8> %a, [[NEG_I]] // CHECK: ret <16 x i8> [[AND_I]] @@ -356,7 +356,7 @@ int8x16_t test_vbicq_s8(int8x16_t a, int8x16_t b) { return vbicq_s8(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vbic_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vbic_s16(<4 x i16> %a, <4 x i16> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, // CHECK: [[AND_I:%.*]] = and <4 x i16> %a, [[NEG_I]] // CHECK: ret <4 x i16> [[AND_I]] @@ -364,7 +364,7 @@ int16x4_t test_vbic_s16(int16x4_t a, int16x4_t b) { return vbic_s16(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vbicq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vbicq_s16(<8 x i16> %a, <8 x i16> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, // CHECK: [[AND_I:%.*]] = and <8 x i16> %a, [[NEG_I]] // CHECK: ret <8 x i16> [[AND_I]] @@ -372,7 +372,7 @@ int16x8_t test_vbicq_s16(int16x8_t a, int16x8_t b) { return vbicq_s16(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vbic_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vbic_s32(<2 x i32> %a, <2 x i32> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, // CHECK: [[AND_I:%.*]] = and <2 x i32> %a, [[NEG_I]] // CHECK: ret <2 x i32> [[AND_I]] @@ -380,7 +380,7 @@ int32x2_t test_vbic_s32(int32x2_t a, int32x2_t b) { return vbic_s32(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vbicq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vbicq_s32(<4 x i32> %a, <4 x i32> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, // CHECK: [[AND_I:%.*]] = and <4 x i32> %a, [[NEG_I]] // CHECK: ret <4 x i32> [[AND_I]] @@ -388,7 +388,7 @@ int32x4_t test_vbicq_s32(int32x4_t a, int32x4_t b) { return vbicq_s32(a, b); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vbic_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vbic_s64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, // CHECK: [[AND_I:%.*]] = and <1 x i64> %a, [[NEG_I]] // CHECK: ret <1 x i64> [[AND_I]] @@ -396,7 +396,7 @@ int64x1_t test_vbic_s64(int64x1_t a, int64x1_t b) { return vbic_s64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vbicq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vbicq_s64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, // CHECK: [[AND_I:%.*]] = and <2 x i64> %a, [[NEG_I]] // CHECK: ret <2 x i64> [[AND_I]] @@ -404,7 +404,7 @@ int64x2_t test_vbicq_s64(int64x2_t a, int64x2_t b) { return vbicq_s64(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vbic_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vbic_u8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, // CHECK: [[AND_I:%.*]] = and <8 x i8> %a, [[NEG_I]] // CHECK: ret <8 x i8> [[AND_I]] @@ -412,7 +412,7 @@ uint8x8_t test_vbic_u8(uint8x8_t a, uint8x8_t b) { return vbic_u8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vbicq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vbicq_u8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, // CHECK: [[AND_I:%.*]] = and <16 x i8> %a, [[NEG_I]] // CHECK: ret <16 x i8> [[AND_I]] @@ -420,7 +420,7 @@ uint8x16_t test_vbicq_u8(uint8x16_t a, uint8x16_t b) { return vbicq_u8(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vbic_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vbic_u16(<4 x i16> %a, <4 x i16> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, // CHECK: [[AND_I:%.*]] = and <4 x i16> %a, [[NEG_I]] // CHECK: ret <4 x i16> [[AND_I]] @@ -428,7 +428,7 @@ uint16x4_t test_vbic_u16(uint16x4_t a, uint16x4_t b) { return vbic_u16(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vbicq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vbicq_u16(<8 x i16> %a, <8 x i16> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, // CHECK: [[AND_I:%.*]] = and <8 x i16> %a, [[NEG_I]] // CHECK: ret <8 x i16> [[AND_I]] @@ -436,7 +436,7 @@ uint16x8_t test_vbicq_u16(uint16x8_t a, uint16x8_t b) { return vbicq_u16(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vbic_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vbic_u32(<2 x i32> %a, <2 x i32> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, // CHECK: [[AND_I:%.*]] = and <2 x i32> %a, [[NEG_I]] // CHECK: ret <2 x i32> [[AND_I]] @@ -444,7 +444,7 @@ uint32x2_t test_vbic_u32(uint32x2_t a, uint32x2_t b) { return vbic_u32(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vbicq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vbicq_u32(<4 x i32> %a, <4 x i32> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, // CHECK: [[AND_I:%.*]] = and <4 x i32> %a, [[NEG_I]] // CHECK: ret <4 x i32> [[AND_I]] @@ -452,7 +452,7 @@ uint32x4_t test_vbicq_u32(uint32x4_t a, uint32x4_t b) { return vbicq_u32(a, b); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vbic_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vbic_u64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, // CHECK: [[AND_I:%.*]] = and <1 x i64> %a, [[NEG_I]] // CHECK: ret <1 x i64> [[AND_I]] @@ -460,7 +460,7 @@ uint64x1_t test_vbic_u64(uint64x1_t a, uint64x1_t b) { return vbic_u64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vbicq_u64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vbicq_u64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, // CHECK: [[AND_I:%.*]] = and <2 x i64> %a, [[NEG_I]] // CHECK: ret <2 x i64> [[AND_I]] @@ -468,7 +468,7 @@ uint64x2_t test_vbicq_u64(uint64x2_t a, uint64x2_t b) { return vbicq_u64(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorn_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorn_s8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, // CHECK: [[OR_I:%.*]] = or <8 x i8> %a, [[NEG_I]] // CHECK: ret <8 x i8> [[OR_I]] @@ -476,7 +476,7 @@ int8x8_t test_vorn_s8(int8x8_t a, int8x8_t b) { return vorn_s8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vornq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vornq_s8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, // CHECK: [[OR_I:%.*]] = or <16 x i8> %a, [[NEG_I]] // CHECK: ret <16 x i8> [[OR_I]] @@ -484,7 +484,7 @@ int8x16_t test_vornq_s8(int8x16_t a, int8x16_t b) { return vornq_s8(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorn_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorn_s16(<4 x i16> %a, <4 x i16> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, // CHECK: [[OR_I:%.*]] = or <4 x i16> %a, [[NEG_I]] // CHECK: ret <4 x i16> [[OR_I]] @@ -492,7 +492,7 @@ int16x4_t test_vorn_s16(int16x4_t a, int16x4_t b) { return vorn_s16(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vornq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vornq_s16(<8 x i16> %a, <8 x i16> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, // CHECK: [[OR_I:%.*]] = or <8 x i16> %a, [[NEG_I]] // CHECK: ret <8 x i16> [[OR_I]] @@ -500,7 +500,7 @@ int16x8_t test_vornq_s16(int16x8_t a, int16x8_t b) { return vornq_s16(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorn_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorn_s32(<2 x i32> %a, <2 x i32> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, // CHECK: [[OR_I:%.*]] = or <2 x i32> %a, [[NEG_I]] // CHECK: ret <2 x i32> [[OR_I]] @@ -508,7 +508,7 @@ int32x2_t test_vorn_s32(int32x2_t a, int32x2_t b) { return vorn_s32(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vornq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vornq_s32(<4 x i32> %a, <4 x i32> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, // CHECK: [[OR_I:%.*]] = or <4 x i32> %a, [[NEG_I]] // CHECK: ret <4 x i32> [[OR_I]] @@ -516,7 +516,7 @@ int32x4_t test_vornq_s32(int32x4_t a, int32x4_t b) { return vornq_s32(a, b); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorn_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorn_s64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, // CHECK: [[OR_I:%.*]] = or <1 x i64> %a, [[NEG_I]] // CHECK: ret <1 x i64> [[OR_I]] @@ -524,7 +524,7 @@ int64x1_t test_vorn_s64(int64x1_t a, int64x1_t b) { return vorn_s64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vornq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vornq_s64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, // CHECK: [[OR_I:%.*]] = or <2 x i64> %a, [[NEG_I]] // CHECK: ret <2 x i64> [[OR_I]] @@ -532,7 +532,7 @@ int64x2_t test_vornq_s64(int64x2_t a, int64x2_t b) { return vornq_s64(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorn_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorn_u8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, // CHECK: [[OR_I:%.*]] = or <8 x i8> %a, [[NEG_I]] // CHECK: ret <8 x i8> [[OR_I]] @@ -540,7 +540,7 @@ uint8x8_t test_vorn_u8(uint8x8_t a, uint8x8_t b) { return vorn_u8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vornq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vornq_u8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, // CHECK: [[OR_I:%.*]] = or <16 x i8> %a, [[NEG_I]] // CHECK: ret <16 x i8> [[OR_I]] @@ -548,7 +548,7 @@ uint8x16_t test_vornq_u8(uint8x16_t a, uint8x16_t b) { return vornq_u8(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorn_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorn_u16(<4 x i16> %a, <4 x i16> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, // CHECK: [[OR_I:%.*]] = or <4 x i16> %a, [[NEG_I]] // CHECK: ret <4 x i16> [[OR_I]] @@ -556,7 +556,7 @@ uint16x4_t test_vorn_u16(uint16x4_t a, uint16x4_t b) { return vorn_u16(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vornq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vornq_u16(<8 x i16> %a, <8 x i16> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, // CHECK: [[OR_I:%.*]] = or <8 x i16> %a, [[NEG_I]] // CHECK: ret <8 x i16> [[OR_I]] @@ -564,7 +564,7 @@ uint16x8_t test_vornq_u16(uint16x8_t a, uint16x8_t b) { return vornq_u16(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorn_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorn_u32(<2 x i32> %a, <2 x i32> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, // CHECK: [[OR_I:%.*]] = or <2 x i32> %a, [[NEG_I]] // CHECK: ret <2 x i32> [[OR_I]] @@ -572,7 +572,7 @@ uint32x2_t test_vorn_u32(uint32x2_t a, uint32x2_t b) { return vorn_u32(a, b); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vornq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vornq_u32(<4 x i32> %a, <4 x i32> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, // CHECK: [[OR_I:%.*]] = or <4 x i32> %a, [[NEG_I]] // CHECK: ret <4 x i32> [[OR_I]] @@ -580,7 +580,7 @@ uint32x4_t test_vornq_u32(uint32x4_t a, uint32x4_t b) { return vornq_u32(a, b); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorn_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorn_u64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, // CHECK: [[OR_I:%.*]] = or <1 x i64> %a, [[NEG_I]] // CHECK: ret <1 x i64> [[OR_I]] @@ -588,7 +588,7 @@ uint64x1_t test_vorn_u64(uint64x1_t a, uint64x1_t b) { return vorn_u64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vornq_u64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vornq_u64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, // CHECK: [[OR_I:%.*]] = or <2 x i64> %a, [[NEG_I]] // CHECK: ret <2 x i64> [[OR_I]] diff --git a/clang/test/CodeGen/aarch64-neon-across.c b/clang/test/CodeGen/aarch64-neon-across.c index 57751fcdeb6a8472783710475fc6326bcacf1b41..5fc29d509be82fbc7908b31e1e572a51bbcb1b86 100644 --- a/clang/test/CodeGen/aarch64-neon-across.c +++ b/clang/test/CodeGen/aarch64-neon-across.c @@ -5,7 +5,7 @@ #include -// CHECK-LABEL: define{{.*}} i16 @test_vaddlv_s8(<8 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vaddlv_s8(<8 x i8> %a) #0 { // CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v8i8(<8 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i16 // CHECK: ret i16 [[TMP0]] @@ -13,14 +13,14 @@ int16_t test_vaddlv_s8(int8x8_t a) { return vaddlv_s8(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vaddlv_s16(<4 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vaddlv_s16(<4 x i16> %a) #0 { // CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16> %a) #3 // CHECK: ret i32 [[VADDLV_I]] int32_t test_vaddlv_s16(int16x4_t a) { return vaddlv_s16(a); } -// CHECK-LABEL: define{{.*}} i16 @test_vaddlv_u8(<8 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vaddlv_u8(<8 x i8> %a) #0 { // CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i16 // CHECK: ret i16 [[TMP0]] @@ -28,14 +28,14 @@ uint16_t test_vaddlv_u8(uint8x8_t a) { return vaddlv_u8(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vaddlv_u16(<4 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vaddlv_u16(<4 x i16> %a) #0 { // CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16> %a) #3 // CHECK: ret i32 [[VADDLV_I]] uint32_t test_vaddlv_u16(uint16x4_t a) { return vaddlv_u16(a); } -// CHECK-LABEL: define{{.*}} i16 @test_vaddlvq_s8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vaddlvq_s8(<16 x i8> %a) #1 { // CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v16i8(<16 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i16 // CHECK: ret i16 [[TMP0]] @@ -43,21 +43,21 @@ int16_t test_vaddlvq_s8(int8x16_t a) { return vaddlvq_s8(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vaddlvq_s16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vaddlvq_s16(<8 x i16> %a) #1 { // CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v8i16(<8 x i16> %a) #3 // CHECK: ret i32 [[VADDLV_I]] int32_t test_vaddlvq_s16(int16x8_t a) { return vaddlvq_s16(a); } -// CHECK-LABEL: define{{.*}} i64 @test_vaddlvq_s32(<4 x i32> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i64 @test_vaddlvq_s32(<4 x i32> %a) #1 { // CHECK: [[VADDLVQ_S32_I:%.*]] = call i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32> %a) #3 // CHECK: ret i64 [[VADDLVQ_S32_I]] int64_t test_vaddlvq_s32(int32x4_t a) { return vaddlvq_s32(a); } -// CHECK-LABEL: define{{.*}} i16 @test_vaddlvq_u8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vaddlvq_u8(<16 x i8> %a) #1 { // CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i16 // CHECK: ret i16 [[TMP0]] @@ -65,21 +65,21 @@ uint16_t test_vaddlvq_u8(uint8x16_t a) { return vaddlvq_u8(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vaddlvq_u16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vaddlvq_u16(<8 x i16> %a) #1 { // CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16> %a) #3 // CHECK: ret i32 [[VADDLV_I]] uint32_t test_vaddlvq_u16(uint16x8_t a) { return vaddlvq_u16(a); } -// CHECK-LABEL: define{{.*}} i64 @test_vaddlvq_u32(<4 x i32> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i64 @test_vaddlvq_u32(<4 x i32> %a) #1 { // CHECK: [[VADDLVQ_U32_I:%.*]] = call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> %a) #3 // CHECK: ret i64 [[VADDLVQ_U32_I]] uint64_t test_vaddlvq_u32(uint32x4_t a) { return vaddlvq_u32(a); } -// CHECK-LABEL: define{{.*}} i8 @test_vmaxv_s8(<8 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i8 @test_vmaxv_s8(<8 x i8> %a) #0 { // CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i8 // CHECK: ret i8 [[TMP0]] @@ -87,7 +87,7 @@ int8_t test_vmaxv_s8(int8x8_t a) { return vmaxv_s8(a); } -// CHECK-LABEL: define{{.*}} i16 @test_vmaxv_s16(<4 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vmaxv_s16(<4 x i16> %a) #0 { // CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a) #3 // CHECK: [[TMP2:%.*]] = trunc i32 [[VMAXV_I]] to i16 // CHECK: ret i16 [[TMP2]] @@ -95,7 +95,7 @@ int16_t test_vmaxv_s16(int16x4_t a) { return vmaxv_s16(a); } -// CHECK-LABEL: define{{.*}} i8 @test_vmaxv_u8(<8 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i8 @test_vmaxv_u8(<8 x i8> %a) #0 { // CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i8 // CHECK: ret i8 [[TMP0]] @@ -103,7 +103,7 @@ uint8_t test_vmaxv_u8(uint8x8_t a) { return vmaxv_u8(a); } -// CHECK-LABEL: define{{.*}} i16 @test_vmaxv_u16(<4 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vmaxv_u16(<4 x i16> %a) #0 { // CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a) #3 // CHECK: [[TMP2:%.*]] = trunc i32 [[VMAXV_I]] to i16 // CHECK: ret i16 [[TMP2]] @@ -111,7 +111,7 @@ uint16_t test_vmaxv_u16(uint16x4_t a) { return vmaxv_u16(a); } -// CHECK-LABEL: define{{.*}} i8 @test_vmaxvq_s8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i8 @test_vmaxvq_s8(<16 x i8> %a) #1 { // CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i8 // CHECK: ret i8 [[TMP0]] @@ -119,7 +119,7 @@ int8_t test_vmaxvq_s8(int8x16_t a) { return vmaxvq_s8(a); } -// CHECK-LABEL: define{{.*}} i16 @test_vmaxvq_s16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vmaxvq_s16(<8 x i16> %a) #1 { // CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a) #3 // CHECK: [[TMP2:%.*]] = trunc i32 [[VMAXV_I]] to i16 // CHECK: ret i16 [[TMP2]] @@ -127,14 +127,14 @@ int16_t test_vmaxvq_s16(int16x8_t a) { return vmaxvq_s16(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vmaxvq_s32(<4 x i32> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vmaxvq_s32(<4 x i32> %a) #1 { // CHECK: [[VMAXVQ_S32_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a) #3 // CHECK: ret i32 [[VMAXVQ_S32_I]] int32_t test_vmaxvq_s32(int32x4_t a) { return vmaxvq_s32(a); } -// CHECK-LABEL: define{{.*}} i8 @test_vmaxvq_u8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i8 @test_vmaxvq_u8(<16 x i8> %a) #1 { // CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i8 // CHECK: ret i8 [[TMP0]] @@ -142,7 +142,7 @@ uint8_t test_vmaxvq_u8(uint8x16_t a) { return vmaxvq_u8(a); } -// CHECK-LABEL: define{{.*}} i16 @test_vmaxvq_u16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vmaxvq_u16(<8 x i16> %a) #1 { // CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a) #3 // CHECK: [[TMP2:%.*]] = trunc i32 [[VMAXV_I]] to i16 // CHECK: ret i16 [[TMP2]] @@ -150,14 +150,14 @@ uint16_t test_vmaxvq_u16(uint16x8_t a) { return vmaxvq_u16(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vmaxvq_u32(<4 x i32> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vmaxvq_u32(<4 x i32> %a) #1 { // CHECK: [[VMAXVQ_U32_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> %a) #3 // CHECK: ret i32 [[VMAXVQ_U32_I]] uint32_t test_vmaxvq_u32(uint32x4_t a) { return vmaxvq_u32(a); } -// CHECK-LABEL: define{{.*}} i8 @test_vminv_s8(<8 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i8 @test_vminv_s8(<8 x i8> %a) #0 { // CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i8 // CHECK: ret i8 [[TMP0]] @@ -165,7 +165,7 @@ int8_t test_vminv_s8(int8x8_t a) { return vminv_s8(a); } -// CHECK-LABEL: define{{.*}} i16 @test_vminv_s16(<4 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vminv_s16(<4 x i16> %a) #0 { // CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a) #3 // CHECK: [[TMP2:%.*]] = trunc i32 [[VMINV_I]] to i16 // CHECK: ret i16 [[TMP2]] @@ -173,7 +173,7 @@ int16_t test_vminv_s16(int16x4_t a) { return vminv_s16(a); } -// CHECK-LABEL: define{{.*}} i8 @test_vminv_u8(<8 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i8 @test_vminv_u8(<8 x i8> %a) #0 { // CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i8 // CHECK: ret i8 [[TMP0]] @@ -181,7 +181,7 @@ uint8_t test_vminv_u8(uint8x8_t a) { return vminv_u8(a); } -// CHECK-LABEL: define{{.*}} i16 @test_vminv_u16(<4 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vminv_u16(<4 x i16> %a) #0 { // CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a) #3 // CHECK: [[TMP2:%.*]] = trunc i32 [[VMINV_I]] to i16 // CHECK: ret i16 [[TMP2]] @@ -189,7 +189,7 @@ uint16_t test_vminv_u16(uint16x4_t a) { return vminv_u16(a); } -// CHECK-LABEL: define{{.*}} i8 @test_vminvq_s8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i8 @test_vminvq_s8(<16 x i8> %a) #1 { // CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i8 // CHECK: ret i8 [[TMP0]] @@ -197,7 +197,7 @@ int8_t test_vminvq_s8(int8x16_t a) { return vminvq_s8(a); } -// CHECK-LABEL: define{{.*}} i16 @test_vminvq_s16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vminvq_s16(<8 x i16> %a) #1 { // CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a) #3 // CHECK: [[TMP2:%.*]] = trunc i32 [[VMINV_I]] to i16 // CHECK: ret i16 [[TMP2]] @@ -205,14 +205,14 @@ int16_t test_vminvq_s16(int16x8_t a) { return vminvq_s16(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vminvq_s32(<4 x i32> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vminvq_s32(<4 x i32> %a) #1 { // CHECK: [[VMINVQ_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a) #3 // CHECK: ret i32 [[VMINVQ_S32_I]] int32_t test_vminvq_s32(int32x4_t a) { return vminvq_s32(a); } -// CHECK-LABEL: define{{.*}} i8 @test_vminvq_u8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i8 @test_vminvq_u8(<16 x i8> %a) #1 { // CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i8 // CHECK: ret i8 [[TMP0]] @@ -220,7 +220,7 @@ uint8_t test_vminvq_u8(uint8x16_t a) { return vminvq_u8(a); } -// CHECK-LABEL: define{{.*}} i16 @test_vminvq_u16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vminvq_u16(<8 x i16> %a) #1 { // CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a) #3 // CHECK: [[TMP2:%.*]] = trunc i32 [[VMINV_I]] to i16 // CHECK: ret i16 [[TMP2]] @@ -228,14 +228,14 @@ uint16_t test_vminvq_u16(uint16x8_t a) { return vminvq_u16(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vminvq_u32(<4 x i32> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vminvq_u32(<4 x i32> %a) #1 { // CHECK: [[VMINVQ_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32> %a) #3 // CHECK: ret i32 [[VMINVQ_U32_I]] uint32_t test_vminvq_u32(uint32x4_t a) { return vminvq_u32(a); } -// CHECK-LABEL: define{{.*}} i8 @test_vaddv_s8(<8 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i8 @test_vaddv_s8(<8 x i8> %a) #0 { // CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i8 // CHECK: ret i8 [[TMP0]] @@ -243,7 +243,7 @@ int8_t test_vaddv_s8(int8x8_t a) { return vaddv_s8(a); } -// CHECK-LABEL: define{{.*}} i16 @test_vaddv_s16(<4 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vaddv_s16(<4 x i16> %a) #0 { // CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a) #3 // CHECK: [[TMP2:%.*]] = trunc i32 [[VADDV_I]] to i16 // CHECK: ret i16 [[TMP2]] @@ -251,7 +251,7 @@ int16_t test_vaddv_s16(int16x4_t a) { return vaddv_s16(a); } -// CHECK-LABEL: define{{.*}} i8 @test_vaddv_u8(<8 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i8 @test_vaddv_u8(<8 x i8> %a) #0 { // CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i8 // CHECK: ret i8 [[TMP0]] @@ -259,7 +259,7 @@ uint8_t test_vaddv_u8(uint8x8_t a) { return vaddv_u8(a); } -// CHECK-LABEL: define{{.*}} i16 @test_vaddv_u16(<4 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vaddv_u16(<4 x i16> %a) #0 { // CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a) #3 // CHECK: [[TMP2:%.*]] = trunc i32 [[VADDV_I]] to i16 // CHECK: ret i16 [[TMP2]] @@ -267,7 +267,7 @@ uint16_t test_vaddv_u16(uint16x4_t a) { return vaddv_u16(a); } -// CHECK-LABEL: define{{.*}} i8 @test_vaddvq_s8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i8 @test_vaddvq_s8(<16 x i8> %a) #1 { // CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i8 // CHECK: ret i8 [[TMP0]] @@ -275,7 +275,7 @@ int8_t test_vaddvq_s8(int8x16_t a) { return vaddvq_s8(a); } -// CHECK-LABEL: define{{.*}} i16 @test_vaddvq_s16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vaddvq_s16(<8 x i16> %a) #1 { // CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a) #3 // CHECK: [[TMP2:%.*]] = trunc i32 [[VADDV_I]] to i16 // CHECK: ret i16 [[TMP2]] @@ -283,14 +283,14 @@ int16_t test_vaddvq_s16(int16x8_t a) { return vaddvq_s16(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vaddvq_s32(<4 x i32> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vaddvq_s32(<4 x i32> %a) #1 { // CHECK: [[VADDVQ_S32_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a) #3 // CHECK: ret i32 [[VADDVQ_S32_I]] int32_t test_vaddvq_s32(int32x4_t a) { return vaddvq_s32(a); } -// CHECK-LABEL: define{{.*}} i8 @test_vaddvq_u8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i8 @test_vaddvq_u8(<16 x i8> %a) #1 { // CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> %a) #3 // CHECK: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i8 // CHECK: ret i8 [[TMP0]] @@ -298,7 +298,7 @@ uint8_t test_vaddvq_u8(uint8x16_t a) { return vaddvq_u8(a); } -// CHECK-LABEL: define{{.*}} i16 @test_vaddvq_u16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vaddvq_u16(<8 x i16> %a) #1 { // CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a) #3 // CHECK: [[TMP2:%.*]] = trunc i32 [[VADDV_I]] to i16 // CHECK: ret i16 [[TMP2]] @@ -306,35 +306,35 @@ uint16_t test_vaddvq_u16(uint16x8_t a) { return vaddvq_u16(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vaddvq_u32(<4 x i32> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vaddvq_u32(<4 x i32> %a) #1 { // CHECK: [[VADDVQ_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a) #3 // CHECK: ret i32 [[VADDVQ_U32_I]] uint32_t test_vaddvq_u32(uint32x4_t a) { return vaddvq_u32(a); } -// CHECK-LABEL: define{{.*}} float @test_vmaxvq_f32(<4 x float> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} float @test_vmaxvq_f32(<4 x float> %a) #1 { // CHECK: [[VMAXVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %a) #3 // CHECK: ret float [[VMAXVQ_F32_I]] float32_t test_vmaxvq_f32(float32x4_t a) { return vmaxvq_f32(a); } -// CHECK-LABEL: define{{.*}} float @test_vminvq_f32(<4 x float> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} float @test_vminvq_f32(<4 x float> %a) #1 { // CHECK: [[VMINVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %a) #3 // CHECK: ret float [[VMINVQ_F32_I]] float32_t test_vminvq_f32(float32x4_t a) { return vminvq_f32(a); } -// CHECK-LABEL: define{{.*}} float @test_vmaxnmvq_f32(<4 x float> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} float @test_vmaxnmvq_f32(<4 x float> %a) #1 { // CHECK: [[VMAXNMVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %a) #3 // CHECK: ret float [[VMAXNMVQ_F32_I]] float32_t test_vmaxnmvq_f32(float32x4_t a) { return vmaxnmvq_f32(a); } -// CHECK-LABEL: define{{.*}} float @test_vminnmvq_f32(<4 x float> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} float @test_vminnmvq_f32(<4 x float> %a) #1 { // CHECK: [[VMINNMVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float> %a) #3 // CHECK: ret float [[VMINNMVQ_F32_I]] float32_t test_vminnmvq_f32(float32x4_t a) { diff --git a/clang/test/CodeGen/aarch64-neon-dot-product.c b/clang/test/CodeGen/aarch64-neon-dot-product.c index bffecad5c56066dc450194fad722be2503cdaa82..1cae3e1bc619b7e64f0bad8b6df70f0ac34cbaa2 100644 --- a/clang/test/CodeGen/aarch64-neon-dot-product.c +++ b/clang/test/CodeGen/aarch64-neon-dot-product.c @@ -8,35 +8,35 @@ #include uint32x2_t test_vdot_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) { -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) // CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) // CHECK: ret <2 x i32> [[RESULT]] return vdot_u32(a, b, c); } uint32x4_t test_vdotq_u32(uint32x4_t a, uint8x16_t b, uint8x16_t c) { -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) // CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) // CHECK: ret <4 x i32> [[RESULT]] return vdotq_u32(a, b, c); } int32x2_t test_vdot_s32(int32x2_t a, int8x8_t b, int8x8_t c) { -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) // CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) // CHECK: ret <2 x i32> [[RESULT]] return vdot_s32(a, b, c); } int32x4_t test_vdotq_s32(int32x4_t a, int8x16_t b, int8x16_t c) { -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) // CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) // CHECK: ret <4 x i32> [[RESULT]] return vdotq_s32(a, b, c); } uint32x2_t test_vdot_lane_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) { -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) // CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32> // CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <2 x i32> // CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> @@ -46,7 +46,7 @@ uint32x2_t test_vdot_lane_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) { } uint32x4_t test_vdotq_lane_u32(uint32x4_t a, uint8x16_t b, uint8x8_t c) { -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_u32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) // CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32> // CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <4 x i32> // CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8> @@ -56,7 +56,7 @@ uint32x4_t test_vdotq_lane_u32(uint32x4_t a, uint8x16_t b, uint8x8_t c) { } uint32x2_t test_vdot_laneq_u32(uint32x2_t a, uint8x8_t b, uint8x16_t c) { -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_laneq_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <16 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_laneq_u32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) // CHECK: [[CAST1:%.*]] = bitcast <16 x i8> %c to <4 x i32> // CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[CAST1]], <4 x i32> poison, <2 x i32> // CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> @@ -66,7 +66,7 @@ uint32x2_t test_vdot_laneq_u32(uint32x2_t a, uint8x8_t b, uint8x16_t c) { } uint32x4_t test_vdotq_laneq_u32(uint32x4_t a, uint8x16_t b, uint8x16_t c) { -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_laneq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_laneq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) // CHECK: [[CAST1:%.*]] = bitcast <16 x i8> %c to <4 x i32> // CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[CAST1]], <4 x i32> poison, <4 x i32> // CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8> @@ -76,7 +76,7 @@ uint32x4_t test_vdotq_laneq_u32(uint32x4_t a, uint8x16_t b, uint8x16_t c) { } int32x2_t test_vdot_lane_s32(int32x2_t a, int8x8_t b, int8x8_t c) { -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) // CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32> // CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <2 x i32> // CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> @@ -86,7 +86,7 @@ int32x2_t test_vdot_lane_s32(int32x2_t a, int8x8_t b, int8x8_t c) { } int32x4_t test_vdotq_lane_s32(int32x4_t a, int8x16_t b, int8x8_t c) { -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_s32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) // CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32> // CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <4 x i32> // CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8> @@ -96,7 +96,7 @@ int32x4_t test_vdotq_lane_s32(int32x4_t a, int8x16_t b, int8x8_t c) { } int32x2_t test_vdot_laneq_s32(int32x2_t a, int8x8_t b, int8x16_t c) { -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_laneq_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <16 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_laneq_s32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) // CHECK: [[CAST1:%.*]] = bitcast <16 x i8> %c to <4 x i32> // CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[CAST1]], <4 x i32> poison, <2 x i32> // CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> @@ -106,7 +106,7 @@ int32x2_t test_vdot_laneq_s32(int32x2_t a, int8x8_t b, int8x16_t c) { } int32x4_t test_vdotq_laneq_s32(int32x4_t a, int8x16_t b, int8x16_t c) { -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_laneq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_laneq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) // CHECK: [[CAST1:%.*]] = bitcast <16 x i8> %c to <4 x i32> // CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[CAST1]], <4 x i32> poison, <4 x i32> // CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8> diff --git a/clang/test/CodeGen/aarch64-neon-extract.c b/clang/test/CodeGen/aarch64-neon-extract.c index 9575f4dbb75f2f7dc410ebadb92830771a766298..e1128879fa8704adfcdd35c089f4ab7a19a20f33 100644 --- a/clang/test/CodeGen/aarch64-neon-extract.c +++ b/clang/test/CodeGen/aarch64-neon-extract.c @@ -6,14 +6,14 @@ #include -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vext_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vext_s8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[VEXT:%.*]] = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> // CHECK: ret <8 x i8> [[VEXT]] int8x8_t test_vext_s8(int8x8_t a, int8x8_t b) { return vext_s8(a, b, 2); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vext_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vext_s16(<4 x i16> %a, <4 x i16> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> @@ -24,7 +24,7 @@ int16x4_t test_vext_s16(int16x4_t a, int16x4_t b) { return vext_s16(a, b, 3); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vext_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vext_s32(<2 x i32> %a, <2 x i32> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> @@ -35,7 +35,7 @@ int32x2_t test_vext_s32(int32x2_t a, int32x2_t b) { return vext_s32(a, b, 1); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vext_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vext_s64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> @@ -46,14 +46,14 @@ int64x1_t test_vext_s64(int64x1_t a, int64x1_t b) { return vext_s64(a, b, 0); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vextq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vextq_s8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[VEXT:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> // CHECK: ret <16 x i8> [[VEXT]] int8x16_t test_vextq_s8(int8x16_t a, int8x16_t b) { return vextq_s8(a, b, 2); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vextq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vextq_s16(<8 x i16> %a, <8 x i16> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i16> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> @@ -64,7 +64,7 @@ int16x8_t test_vextq_s16(int16x8_t a, int16x8_t b) { return vextq_s16(a, b, 3); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vextq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vextq_s32(<4 x i32> %a, <4 x i32> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <4 x i32> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> @@ -75,7 +75,7 @@ int32x4_t test_vextq_s32(int32x4_t a, int32x4_t b) { return vextq_s32(a, b, 1); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vextq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vextq_s64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> @@ -86,14 +86,14 @@ int64x2_t test_vextq_s64(int64x2_t a, int64x2_t b) { return vextq_s64(a, b, 1); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vext_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vext_u8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[VEXT:%.*]] = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> // CHECK: ret <8 x i8> [[VEXT]] uint8x8_t test_vext_u8(uint8x8_t a, uint8x8_t b) { return vext_u8(a, b, 2); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vext_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vext_u16(<4 x i16> %a, <4 x i16> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> @@ -104,7 +104,7 @@ uint16x4_t test_vext_u16(uint16x4_t a, uint16x4_t b) { return vext_u16(a, b, 3); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vext_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vext_u32(<2 x i32> %a, <2 x i32> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> @@ -115,7 +115,7 @@ uint32x2_t test_vext_u32(uint32x2_t a, uint32x2_t b) { return vext_u32(a, b, 1); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vext_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vext_u64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> @@ -126,14 +126,14 @@ uint64x1_t test_vext_u64(uint64x1_t a, uint64x1_t b) { return vext_u64(a, b, 0); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vextq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vextq_u8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[VEXT:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> // CHECK: ret <16 x i8> [[VEXT]] uint8x16_t test_vextq_u8(uint8x16_t a, uint8x16_t b) { return vextq_u8(a, b, 2); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vextq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vextq_u16(<8 x i16> %a, <8 x i16> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i16> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> @@ -144,7 +144,7 @@ uint16x8_t test_vextq_u16(uint16x8_t a, uint16x8_t b) { return vextq_u16(a, b, 3); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vextq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vextq_u32(<4 x i32> %a, <4 x i32> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <4 x i32> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> @@ -155,7 +155,7 @@ uint32x4_t test_vextq_u32(uint32x4_t a, uint32x4_t b) { return vextq_u32(a, b, 1); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vextq_u64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vextq_u64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> @@ -166,7 +166,7 @@ uint64x2_t test_vextq_u64(uint64x2_t a, uint64x2_t b) { return vextq_u64(a, b, 1); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vext_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vext_f32(<2 x float> %a, <2 x float> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> @@ -177,7 +177,7 @@ float32x2_t test_vext_f32(float32x2_t a, float32x2_t b) { return vext_f32(a, b, 1); } -// CHECK-LABEL: define{{.*}} <1 x double> @test_vext_f64(<1 x double> noundef %a, <1 x double> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x double> @test_vext_f64(<1 x double> %a, <1 x double> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x double> @@ -188,7 +188,7 @@ float64x1_t test_vext_f64(float64x1_t a, float64x1_t b) { return vext_f64(a, b, 0); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vextq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vextq_f32(<4 x float> %a, <4 x float> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> @@ -199,7 +199,7 @@ float32x4_t test_vextq_f32(float32x4_t a, float32x4_t b) { return vextq_f32(a, b, 1); } -// CHECK-LABEL: define{{.*}} <2 x double> @test_vextq_f64(<2 x double> noundef %a, <2 x double> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x double> @test_vextq_f64(<2 x double> %a, <2 x double> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x double> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double> @@ -210,14 +210,14 @@ float64x2_t test_vextq_f64(float64x2_t a, float64x2_t b) { return vextq_f64(a, b, 1); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vext_p8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vext_p8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[VEXT:%.*]] = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> // CHECK: ret <8 x i8> [[VEXT]] poly8x8_t test_vext_p8(poly8x8_t a, poly8x8_t b) { return vext_p8(a, b, 2); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vext_p16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vext_p16(<4 x i16> %a, <4 x i16> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> @@ -228,14 +228,14 @@ poly16x4_t test_vext_p16(poly16x4_t a, poly16x4_t b) { return vext_p16(a, b, 3); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vextq_p8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vextq_p8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[VEXT:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> // CHECK: ret <16 x i8> [[VEXT]] poly8x16_t test_vextq_p8(poly8x16_t a, poly8x16_t b) { return vextq_p8(a, b, 2); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vextq_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vextq_p16(<8 x i16> %a, <8 x i16> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i16> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> diff --git a/clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c b/clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c index 221b06f37a65db21a0c3924679404aad1b6b77e9..6cda12bf5beabca23603a380eb70ae7f4fa3e500 100644 --- a/clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c +++ b/clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c @@ -5,147 +5,147 @@ #include -// CHECK-LABEL: define{{.*}} float @test_vcvtxd_f32_f64(double noundef %a) #0 { +// CHECK-LABEL: define{{.*}} float @test_vcvtxd_f32_f64(double %a) #0 { // CHECK: [[VCVTXD_F32_F64_I:%.*]] = call float @llvm.aarch64.sisd.fcvtxn(double %a) #2 // CHECK: ret float [[VCVTXD_F32_F64_I]] float32_t test_vcvtxd_f32_f64(float64_t a) { return (float32_t)vcvtxd_f32_f64(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vcvtas_s32_f32(float noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vcvtas_s32_f32(float %a) #0 { // CHECK: [[VCVTAS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %a) #2 // CHECK: ret i32 [[VCVTAS_S32_F32_I]] int32_t test_vcvtas_s32_f32(float32_t a) { return (int32_t)vcvtas_s32_f32(a); } -// CHECK-LABEL: define{{.*}} i64 @test_test_vcvtad_s64_f64(double noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_test_vcvtad_s64_f64(double %a) #0 { // CHECK: [[VCVTAD_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %a) #2 // CHECK: ret i64 [[VCVTAD_S64_F64_I]] int64_t test_test_vcvtad_s64_f64(float64_t a) { return (int64_t)vcvtad_s64_f64(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vcvtas_u32_f32(float noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vcvtas_u32_f32(float %a) #0 { // CHECK: [[VCVTAS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %a) #2 // CHECK: ret i32 [[VCVTAS_U32_F32_I]] uint32_t test_vcvtas_u32_f32(float32_t a) { return (uint32_t)vcvtas_u32_f32(a); } -// CHECK-LABEL: define{{.*}} i64 @test_vcvtad_u64_f64(double noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vcvtad_u64_f64(double %a) #0 { // CHECK: [[VCVTAD_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double %a) #2 // CHECK: ret i64 [[VCVTAD_U64_F64_I]] uint64_t test_vcvtad_u64_f64(float64_t a) { return (uint64_t)vcvtad_u64_f64(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vcvtms_s32_f32(float noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vcvtms_s32_f32(float %a) #0 { // CHECK: [[VCVTMS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtms.i32.f32(float %a) #2 // CHECK: ret i32 [[VCVTMS_S32_F32_I]] int32_t test_vcvtms_s32_f32(float32_t a) { return (int32_t)vcvtms_s32_f32(a); } -// CHECK-LABEL: define{{.*}} i64 @test_vcvtmd_s64_f64(double noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vcvtmd_s64_f64(double %a) #0 { // CHECK: [[VCVTMD_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtms.i64.f64(double %a) #2 // CHECK: ret i64 [[VCVTMD_S64_F64_I]] int64_t test_vcvtmd_s64_f64(float64_t a) { return (int64_t)vcvtmd_s64_f64(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vcvtms_u32_f32(float noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vcvtms_u32_f32(float %a) #0 { // CHECK: [[VCVTMS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtmu.i32.f32(float %a) #2 // CHECK: ret i32 [[VCVTMS_U32_F32_I]] uint32_t test_vcvtms_u32_f32(float32_t a) { return (uint32_t)vcvtms_u32_f32(a); } -// CHECK-LABEL: define{{.*}} i64 @test_vcvtmd_u64_f64(double noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vcvtmd_u64_f64(double %a) #0 { // CHECK: [[VCVTMD_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtmu.i64.f64(double %a) #2 // CHECK: ret i64 [[VCVTMD_U64_F64_I]] uint64_t test_vcvtmd_u64_f64(float64_t a) { return (uint64_t)vcvtmd_u64_f64(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vcvtns_s32_f32(float noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vcvtns_s32_f32(float %a) #0 { // CHECK: [[VCVTNS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtns.i32.f32(float %a) #2 // CHECK: ret i32 [[VCVTNS_S32_F32_I]] int32_t test_vcvtns_s32_f32(float32_t a) { return (int32_t)vcvtns_s32_f32(a); } -// CHECK-LABEL: define{{.*}} i64 @test_vcvtnd_s64_f64(double noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vcvtnd_s64_f64(double %a) #0 { // CHECK: [[VCVTND_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtns.i64.f64(double %a) #2 // CHECK: ret i64 [[VCVTND_S64_F64_I]] int64_t test_vcvtnd_s64_f64(float64_t a) { return (int64_t)vcvtnd_s64_f64(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vcvtns_u32_f32(float noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vcvtns_u32_f32(float %a) #0 { // CHECK: [[VCVTNS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float %a) #2 // CHECK: ret i32 [[VCVTNS_U32_F32_I]] uint32_t test_vcvtns_u32_f32(float32_t a) { return (uint32_t)vcvtns_u32_f32(a); } -// CHECK-LABEL: define{{.*}} i64 @test_vcvtnd_u64_f64(double noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vcvtnd_u64_f64(double %a) #0 { // CHECK: [[VCVTND_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double %a) #2 // CHECK: ret i64 [[VCVTND_U64_F64_I]] uint64_t test_vcvtnd_u64_f64(float64_t a) { return (uint64_t)vcvtnd_u64_f64(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vcvtps_s32_f32(float noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vcvtps_s32_f32(float %a) #0 { // CHECK: [[VCVTPS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtps.i32.f32(float %a) #2 // CHECK: ret i32 [[VCVTPS_S32_F32_I]] int32_t test_vcvtps_s32_f32(float32_t a) { return (int32_t)vcvtps_s32_f32(a); } -// CHECK-LABEL: define{{.*}} i64 @test_vcvtpd_s64_f64(double noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vcvtpd_s64_f64(double %a) #0 { // CHECK: [[VCVTPD_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtps.i64.f64(double %a) #2 // CHECK: ret i64 [[VCVTPD_S64_F64_I]] int64_t test_vcvtpd_s64_f64(float64_t a) { return (int64_t)vcvtpd_s64_f64(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vcvtps_u32_f32(float noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vcvtps_u32_f32(float %a) #0 { // CHECK: [[VCVTPS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtpu.i32.f32(float %a) #2 // CHECK: ret i32 [[VCVTPS_U32_F32_I]] uint32_t test_vcvtps_u32_f32(float32_t a) { return (uint32_t)vcvtps_u32_f32(a); } -// CHECK-LABEL: define{{.*}} i64 @test_vcvtpd_u64_f64(double noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vcvtpd_u64_f64(double %a) #0 { // CHECK: [[VCVTPD_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtpu.i64.f64(double %a) #2 // CHECK: ret i64 [[VCVTPD_U64_F64_I]] uint64_t test_vcvtpd_u64_f64(float64_t a) { return (uint64_t)vcvtpd_u64_f64(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vcvts_s32_f32(float noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vcvts_s32_f32(float %a) #0 { // CHECK: [[TMP0:%.*]] = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a) // CHECK: ret i32 [[TMP0]] int32_t test_vcvts_s32_f32(float32_t a) { return (int32_t)vcvts_s32_f32(a); } -// CHECK-LABEL: define{{.*}} i64 @test_vcvtd_s64_f64(double noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vcvtd_s64_f64(double %a) #0 { // CHECK: [[TMP0:%.*]] = call i64 @llvm.aarch64.neon.fcvtzs.i64.f64(double %a) // CHECK: ret i64 [[TMP0]] int64_t test_vcvtd_s64_f64(float64_t a) { return (int64_t)vcvtd_s64_f64(a); } -// CHECK-LABEL: define{{.*}} i32 @test_vcvts_u32_f32(float noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vcvts_u32_f32(float %a) #0 { // CHECK: [[TMP0:%.*]] = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %a) // CHECK: ret i32 [[TMP0]] uint32_t test_vcvts_u32_f32(float32_t a) { return (uint32_t)vcvts_u32_f32(a); } -// CHECK-LABEL: define{{.*}} i64 @test_vcvtd_u64_f64(double noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vcvtd_u64_f64(double %a) #0 { // CHECK: [[TMP0:%.*]] = call i64 @llvm.aarch64.neon.fcvtzu.i64.f64(double %a) // CHECK: ret i64 [[TMP0]] uint64_t test_vcvtd_u64_f64(float64_t a) { diff --git a/clang/test/CodeGen/aarch64-neon-fma.c b/clang/test/CodeGen/aarch64-neon-fma.c index d55931eda01be67997e0473eb1e1c22851986260..16d5255463a391c44eca231ae6c23120b649215c 100644 --- a/clang/test/CodeGen/aarch64-neon-fma.c +++ b/clang/test/CodeGen/aarch64-neon-fma.c @@ -4,7 +4,7 @@ #include -// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_n_f32(<2 x float> %a, <2 x float> %b, float %c) #0 { // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %c, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %c, i32 1 // CHECK: [[MUL_I:%.*]] = fmul <2 x float> %b, [[VECINIT1_I]] @@ -14,7 +14,7 @@ float32x2_t test_vmla_n_f32(float32x2_t a, float32x2_t b, float32_t c) { return vmla_n_f32(a, b, c); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_n_f32(<4 x float> %a, <4 x float> %b, float %c) #1 { // CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %c, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %c, i32 1 // CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %c, i32 2 @@ -26,7 +26,7 @@ float32x4_t test_vmlaq_n_f32(float32x4_t a, float32x4_t b, float32_t c) { return vmlaq_n_f32(a, b, c); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_n_f32(<4 x float> %a, <4 x float> %b, float %c) #1 { // CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %c, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %c, i32 1 // CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %c, i32 2 @@ -38,7 +38,7 @@ float32x4_t test_vmlsq_n_f32(float32x4_t a, float32x4_t b, float32_t c) { return vmlsq_n_f32(a, b, c); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_n_f32(<2 x float> %a, <2 x float> %b, float %c) #0 { // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %c, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %c, i32 1 // CHECK: [[MUL_I:%.*]] = fmul <2 x float> %b, [[VECINIT1_I]] @@ -48,7 +48,7 @@ float32x2_t test_vmls_n_f32(float32x2_t a, float32x2_t b, float32_t c) { return vmls_n_f32(a, b, c); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_lane_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_lane_f32_0(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 { // CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> // CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> zeroinitializer @@ -59,7 +59,7 @@ float32x2_t test_vmla_lane_f32_0(float32x2_t a, float32x2_t b, float32x2_t v) { return vmla_lane_f32(a, b, v, 0); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_lane_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_lane_f32_0(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 { // CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> // CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> zeroinitializer @@ -70,7 +70,7 @@ float32x4_t test_vmlaq_lane_f32_0(float32x4_t a, float32x4_t b, float32x2_t v) { return vmlaq_lane_f32(a, b, v, 0); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_laneq_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <4 x float> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_laneq_f32_0(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 { // CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> // CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> zeroinitializer @@ -81,7 +81,7 @@ float32x2_t test_vmla_laneq_f32_0(float32x2_t a, float32x2_t b, float32x4_t v) { return vmla_laneq_f32(a, b, v, 0); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_laneq_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_laneq_f32_0(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 { // CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> // CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> zeroinitializer @@ -92,7 +92,7 @@ float32x4_t test_vmlaq_laneq_f32_0(float32x4_t a, float32x4_t b, float32x4_t v) return vmlaq_laneq_f32(a, b, v, 0); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_lane_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_lane_f32_0(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 { // CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> // CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> zeroinitializer @@ -103,7 +103,7 @@ float32x2_t test_vmls_lane_f32_0(float32x2_t a, float32x2_t b, float32x2_t v) { return vmls_lane_f32(a, b, v, 0); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_lane_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_lane_f32_0(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 { // CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> // CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> zeroinitializer @@ -114,7 +114,7 @@ float32x4_t test_vmlsq_lane_f32_0(float32x4_t a, float32x4_t b, float32x2_t v) { return vmlsq_lane_f32(a, b, v, 0); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_laneq_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <4 x float> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_laneq_f32_0(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 { // CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> // CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> zeroinitializer @@ -125,7 +125,7 @@ float32x2_t test_vmls_laneq_f32_0(float32x2_t a, float32x2_t b, float32x4_t v) { return vmls_laneq_f32(a, b, v, 0); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_laneq_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_laneq_f32_0(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 { // CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> // CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> zeroinitializer @@ -136,7 +136,7 @@ float32x4_t test_vmlsq_laneq_f32_0(float32x4_t a, float32x4_t b, float32x4_t v) return vmlsq_laneq_f32(a, b, v, 0); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_lane_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_lane_f32(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 { // CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> // CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> @@ -147,7 +147,7 @@ float32x2_t test_vmla_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) { return vmla_lane_f32(a, b, v, 1); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_lane_f32(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_lane_f32(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 { // CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> // CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> @@ -158,7 +158,7 @@ float32x4_t test_vmlaq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v) { return vmlaq_lane_f32(a, b, v, 1); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_laneq_f32(<2 x float> noundef %a, <2 x float> noundef %b, <4 x float> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_laneq_f32(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 { // CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> // CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> @@ -169,7 +169,7 @@ float32x2_t test_vmla_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v) { return vmla_laneq_f32(a, b, v, 3); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_laneq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_laneq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 { // CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> // CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> @@ -180,7 +180,7 @@ float32x4_t test_vmlaq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v) { return vmlaq_laneq_f32(a, b, v, 3); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_lane_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_lane_f32(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 { // CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> // CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> @@ -191,7 +191,7 @@ float32x2_t test_vmls_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) { return vmls_lane_f32(a, b, v, 1); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_lane_f32(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_lane_f32(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 { // CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float> // CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> @@ -202,7 +202,7 @@ float32x2_t test_vmls_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) { float32x4_t test_vmlsq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v) { return vmlsq_lane_f32(a, b, v, 1); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_laneq_f32(<2 x float> noundef %a, <2 x float> noundef %b, <4 x float> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_laneq_f32(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 { // CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> // CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> @@ -213,7 +213,7 @@ float32x2_t test_vmls_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v) { return vmls_laneq_f32(a, b, v, 3); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_laneq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_laneq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 { // CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float> // CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> @@ -224,7 +224,7 @@ float32x4_t test_vmlsq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v) { return vmlsq_laneq_f32(a, b, v, 3); } -// CHECK-LABEL: define{{.*}} <2 x double> @test_vfmaq_n_f64(<2 x double> noundef %a, <2 x double> noundef %b, double noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <2 x double> @test_vfmaq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #1 { // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %c, i32 1 // CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> [[VECINIT1_I]], <2 x double> %a) @@ -233,7 +233,7 @@ float64x2_t test_vfmaq_n_f64(float64x2_t a, float64x2_t b, float64_t c) { return vfmaq_n_f64(a, b, c); } -// CHECK-LABEL: define{{.*}} <2 x double> @test_vfmsq_n_f64(<2 x double> noundef %a, <2 x double> noundef %b, double noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <2 x double> @test_vfmsq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #1 { // CHECK: [[SUB_I:%.*]] = fneg <2 x double> %b // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %c, i32 1 diff --git a/clang/test/CodeGen/aarch64-neon-ldst-one.c b/clang/test/CodeGen/aarch64-neon-ldst-one.c index 2f1638b8b1d31031e2f73304c7bcecf3cce87c51..db352fecf221ecafbcc5999ef109d4e7646b8cb2 100644 --- a/clang/test/CodeGen/aarch64-neon-ldst-one.c +++ b/clang/test/CodeGen/aarch64-neon-ldst-one.c @@ -4,7 +4,7 @@ #include -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vld1q_dup_u8(i8* noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vld1q_dup_u8(i8* %a) #0 { // CHECK: [[TMP0:%.*]] = load i8, i8* %a // CHECK: [[TMP1:%.*]] = insertelement <16 x i8> undef, i8 [[TMP0]], i32 0 // CHECK: [[LANE:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> [[TMP1]], <16 x i32> zeroinitializer @@ -13,7 +13,7 @@ uint8x16_t test_vld1q_dup_u8(uint8_t *a) { return vld1q_dup_u8(a); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vld1q_dup_u16(i16* noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vld1q_dup_u16(i16* %a) #0 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16* // CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]] @@ -24,7 +24,7 @@ uint16x8_t test_vld1q_dup_u16(uint16_t *a) { return vld1q_dup_u16(a); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vld1q_dup_u32(i32* noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vld1q_dup_u32(i32* %a) #0 { // CHECK: [[TMP0:%.*]] = bitcast i32* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i32* // CHECK: [[TMP2:%.*]] = load i32, i32* [[TMP1]] @@ -35,7 +35,7 @@ uint32x4_t test_vld1q_dup_u32(uint32_t *a) { return vld1q_dup_u32(a); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_dup_u64(i64* noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_dup_u64(i64* %a) #0 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i64* // CHECK: [[TMP2:%.*]] = load i64, i64* [[TMP1]] @@ -46,7 +46,7 @@ uint64x2_t test_vld1q_dup_u64(uint64_t *a) { return vld1q_dup_u64(a); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vld1q_dup_s8(i8* noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vld1q_dup_s8(i8* %a) #0 { // CHECK: [[TMP0:%.*]] = load i8, i8* %a // CHECK: [[TMP1:%.*]] = insertelement <16 x i8> undef, i8 [[TMP0]], i32 0 // CHECK: [[LANE:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> [[TMP1]], <16 x i32> zeroinitializer @@ -55,7 +55,7 @@ int8x16_t test_vld1q_dup_s8(int8_t *a) { return vld1q_dup_s8(a); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vld1q_dup_s16(i16* noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vld1q_dup_s16(i16* %a) #0 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16* // CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]] @@ -66,7 +66,7 @@ int16x8_t test_vld1q_dup_s16(int16_t *a) { return vld1q_dup_s16(a); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vld1q_dup_s32(i32* noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vld1q_dup_s32(i32* %a) #0 { // CHECK: [[TMP0:%.*]] = bitcast i32* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i32* // CHECK: [[TMP2:%.*]] = load i32, i32* [[TMP1]] @@ -77,7 +77,7 @@ int32x4_t test_vld1q_dup_s32(int32_t *a) { return vld1q_dup_s32(a); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_dup_s64(i64* noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_dup_s64(i64* %a) #0 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i64* // CHECK: [[TMP2:%.*]] = load i64, i64* [[TMP1]] @@ -88,7 +88,7 @@ int64x2_t test_vld1q_dup_s64(int64_t *a) { return vld1q_dup_s64(a); } -// CHECK-LABEL: define{{.*}} <8 x half> @test_vld1q_dup_f16(half* noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <8 x half> @test_vld1q_dup_f16(half* %a) #0 { // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to half* // CHECK: [[TMP2:%.*]] = load half, half* [[TMP1]] @@ -99,7 +99,7 @@ float16x8_t test_vld1q_dup_f16(float16_t *a) { return vld1q_dup_f16(a); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vld1q_dup_f32(float* noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vld1q_dup_f32(float* %a) #0 { // CHECK: [[TMP0:%.*]] = bitcast float* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to float* // CHECK: [[TMP2:%.*]] = load float, float* [[TMP1]] @@ -110,7 +110,7 @@ float32x4_t test_vld1q_dup_f32(float32_t *a) { return vld1q_dup_f32(a); } -// CHECK-LABEL: define{{.*}} <2 x double> @test_vld1q_dup_f64(double* noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x double> @test_vld1q_dup_f64(double* %a) #0 { // CHECK: [[TMP0:%.*]] = bitcast double* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to double* // CHECK: [[TMP2:%.*]] = load double, double* [[TMP1]] @@ -121,7 +121,7 @@ float64x2_t test_vld1q_dup_f64(float64_t *a) { return vld1q_dup_f64(a); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vld1q_dup_p8(i8* noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vld1q_dup_p8(i8* %a) #0 { // CHECK: [[TMP0:%.*]] = load i8, i8* %a // CHECK: [[TMP1:%.*]] = insertelement <16 x i8> undef, i8 [[TMP0]], i32 0 // CHECK: [[LANE:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> [[TMP1]], <16 x i32> zeroinitializer @@ -130,7 +130,7 @@ poly8x16_t test_vld1q_dup_p8(poly8_t *a) { return vld1q_dup_p8(a); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vld1q_dup_p16(i16* noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vld1q_dup_p16(i16* %a) #0 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16* // CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]] @@ -141,7 +141,7 @@ poly16x8_t test_vld1q_dup_p16(poly16_t *a) { return vld1q_dup_p16(a); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_dup_p64(i64* noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_dup_p64(i64* %a) #0 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i64* // CHECK: [[TMP2:%.*]] = load i64, i64* [[TMP1]] @@ -152,7 +152,7 @@ poly64x2_t test_vld1q_dup_p64(poly64_t *a) { return vld1q_dup_p64(a); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vld1_dup_u8(i8* noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vld1_dup_u8(i8* %a) #1 { // CHECK: [[TMP0:%.*]] = load i8, i8* %a // CHECK: [[TMP1:%.*]] = insertelement <8 x i8> undef, i8 [[TMP0]], i32 0 // CHECK: [[LANE:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> [[TMP1]], <8 x i32> zeroinitializer @@ -161,7 +161,7 @@ uint8x8_t test_vld1_dup_u8(uint8_t *a) { return vld1_dup_u8(a); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vld1_dup_u16(i16* noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vld1_dup_u16(i16* %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16* // CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]] @@ -172,7 +172,7 @@ uint16x4_t test_vld1_dup_u16(uint16_t *a) { return vld1_dup_u16(a); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vld1_dup_u32(i32* noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vld1_dup_u32(i32* %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i32* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i32* // CHECK: [[TMP2:%.*]] = load i32, i32* [[TMP1]] @@ -183,7 +183,7 @@ uint32x2_t test_vld1_dup_u32(uint32_t *a) { return vld1_dup_u32(a); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_dup_u64(i64* noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_dup_u64(i64* %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i64* // CHECK: [[TMP2:%.*]] = load i64, i64* [[TMP1]] @@ -194,7 +194,7 @@ uint64x1_t test_vld1_dup_u64(uint64_t *a) { return vld1_dup_u64(a); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vld1_dup_s8(i8* noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vld1_dup_s8(i8* %a) #1 { // CHECK: [[TMP0:%.*]] = load i8, i8* %a // CHECK: [[TMP1:%.*]] = insertelement <8 x i8> undef, i8 [[TMP0]], i32 0 // CHECK: [[LANE:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> [[TMP1]], <8 x i32> zeroinitializer @@ -203,7 +203,7 @@ int8x8_t test_vld1_dup_s8(int8_t *a) { return vld1_dup_s8(a); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vld1_dup_s16(i16* noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vld1_dup_s16(i16* %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16* // CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]] @@ -214,7 +214,7 @@ int16x4_t test_vld1_dup_s16(int16_t *a) { return vld1_dup_s16(a); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vld1_dup_s32(i32* noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vld1_dup_s32(i32* %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i32* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i32* // CHECK: [[TMP2:%.*]] = load i32, i32* [[TMP1]] @@ -225,7 +225,7 @@ int32x2_t test_vld1_dup_s32(int32_t *a) { return vld1_dup_s32(a); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_dup_s64(i64* noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_dup_s64(i64* %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i64* // CHECK: [[TMP2:%.*]] = load i64, i64* [[TMP1]] @@ -236,7 +236,7 @@ int64x1_t test_vld1_dup_s64(int64_t *a) { return vld1_dup_s64(a); } -// CHECK-LABEL: define{{.*}} <4 x half> @test_vld1_dup_f16(half* noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <4 x half> @test_vld1_dup_f16(half* %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to half* // CHECK: [[TMP2:%.*]] = load half, half* [[TMP1]] @@ -247,7 +247,7 @@ float16x4_t test_vld1_dup_f16(float16_t *a) { return vld1_dup_f16(a); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vld1_dup_f32(float* noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vld1_dup_f32(float* %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast float* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to float* // CHECK: [[TMP2:%.*]] = load float, float* [[TMP1]] @@ -258,7 +258,7 @@ float32x2_t test_vld1_dup_f32(float32_t *a) { return vld1_dup_f32(a); } -// CHECK-LABEL: define{{.*}} <1 x double> @test_vld1_dup_f64(double* noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <1 x double> @test_vld1_dup_f64(double* %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast double* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to double* // CHECK: [[TMP2:%.*]] = load double, double* [[TMP1]] @@ -269,7 +269,7 @@ float64x1_t test_vld1_dup_f64(float64_t *a) { return vld1_dup_f64(a); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vld1_dup_p8(i8* noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vld1_dup_p8(i8* %a) #1 { // CHECK: [[TMP0:%.*]] = load i8, i8* %a // CHECK: [[TMP1:%.*]] = insertelement <8 x i8> undef, i8 [[TMP0]], i32 0 // CHECK: [[LANE:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> [[TMP1]], <8 x i32> zeroinitializer @@ -278,7 +278,7 @@ poly8x8_t test_vld1_dup_p8(poly8_t *a) { return vld1_dup_p8(a); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vld1_dup_p16(i16* noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vld1_dup_p16(i16* %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16* // CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]] @@ -289,7 +289,7 @@ poly16x4_t test_vld1_dup_p16(poly16_t *a) { return vld1_dup_p16(a); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_dup_p64(i64* noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_dup_p64(i64* %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i64* // CHECK: [[TMP2:%.*]] = load i64, i64* [[TMP1]] @@ -300,7 +300,7 @@ poly64x1_t test_vld1_dup_p64(poly64_t *a) { return vld1_dup_p64(a); } -// CHECK-LABEL: define{{.*}} %struct.uint64x2x2_t @test_vld2q_dup_u64(i64* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint64x2x2_t @test_vld2q_dup_u64(i64* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint64x2x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x2_t, align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x2x2_t* [[__RET]] to i8* @@ -318,7 +318,7 @@ uint64x2x2_t test_vld2q_dup_u64(uint64_t *a) { return vld2q_dup_u64(a); } -// CHECK-LABEL: define{{.*}} %struct.int64x2x2_t @test_vld2q_dup_s64(i64* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.int64x2x2_t @test_vld2q_dup_s64(i64* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int64x2x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int64x2x2_t, align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x2x2_t* [[__RET]] to i8* @@ -336,7 +336,7 @@ int64x2x2_t test_vld2q_dup_s64(int64_t *a) { return vld2q_dup_s64(a); } -// CHECK-LABEL: define{{.*}} %struct.float64x2x2_t @test_vld2q_dup_f64(double* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.float64x2x2_t @test_vld2q_dup_f64(double* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x2x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float64x2x2_t, align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.float64x2x2_t* [[__RET]] to i8* @@ -354,7 +354,7 @@ float64x2x2_t test_vld2q_dup_f64(float64_t *a) { return vld2q_dup_f64(a); } -// CHECK-LABEL: define{{.*}} %struct.poly64x2x2_t @test_vld2q_dup_p64(i64* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x2x2_t @test_vld2q_dup_p64(i64* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x2x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x2x2_t, align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x2x2_t* [[__RET]] to i8* @@ -372,7 +372,7 @@ poly64x2x2_t test_vld2q_dup_p64(poly64_t *a) { return vld2q_dup_p64(a); } -// CHECK-LABEL: define{{.*}} %struct.float64x1x2_t @test_vld2_dup_f64(double* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.float64x1x2_t @test_vld2_dup_f64(double* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x1x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float64x1x2_t, align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.float64x1x2_t* [[__RET]] to i8* @@ -390,7 +390,7 @@ float64x1x2_t test_vld2_dup_f64(float64_t *a) { return vld2_dup_f64(a); } -// CHECK-LABEL: define{{.*}} %struct.poly64x1x2_t @test_vld2_dup_p64(i64* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x1x2_t @test_vld2_dup_p64(i64* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x1x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x1x2_t, align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x1x2_t* [[__RET]] to i8* @@ -408,7 +408,7 @@ poly64x1x2_t test_vld2_dup_p64(poly64_t *a) { return vld2_dup_p64(a); } -// CHECK-LABEL: define{{.*}} %struct.uint64x2x3_t @test_vld3q_dup_u64(i64* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint64x2x3_t @test_vld3q_dup_u64(i64* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint64x2x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x3_t, align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x2x3_t* [[__RET]] to i8* @@ -427,7 +427,7 @@ uint64x2x3_t test_vld3q_dup_u64(uint64_t *a) { // [{{x[0-9]+|sp}}] } -// CHECK-LABEL: define{{.*}} %struct.int64x2x3_t @test_vld3q_dup_s64(i64* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.int64x2x3_t @test_vld3q_dup_s64(i64* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int64x2x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int64x2x3_t, align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x2x3_t* [[__RET]] to i8* @@ -446,7 +446,7 @@ int64x2x3_t test_vld3q_dup_s64(int64_t *a) { // [{{x[0-9]+|sp}}] } -// CHECK-LABEL: define{{.*}} %struct.float64x2x3_t @test_vld3q_dup_f64(double* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.float64x2x3_t @test_vld3q_dup_f64(double* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x2x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float64x2x3_t, align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.float64x2x3_t* [[__RET]] to i8* @@ -465,7 +465,7 @@ float64x2x3_t test_vld3q_dup_f64(float64_t *a) { // [{{x[0-9]+|sp}}] } -// CHECK-LABEL: define{{.*}} %struct.poly64x2x3_t @test_vld3q_dup_p64(i64* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x2x3_t @test_vld3q_dup_p64(i64* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x2x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x2x3_t, align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x2x3_t* [[__RET]] to i8* @@ -484,7 +484,7 @@ poly64x2x3_t test_vld3q_dup_p64(poly64_t *a) { // [{{x[0-9]+|sp}}] } -// CHECK-LABEL: define{{.*}} %struct.float64x1x3_t @test_vld3_dup_f64(double* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.float64x1x3_t @test_vld3_dup_f64(double* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x1x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float64x1x3_t, align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.float64x1x3_t* [[__RET]] to i8* @@ -503,7 +503,7 @@ float64x1x3_t test_vld3_dup_f64(float64_t *a) { // [{{x[0-9]+|sp}}] } -// CHECK-LABEL: define{{.*}} %struct.poly64x1x3_t @test_vld3_dup_p64(i64* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x1x3_t @test_vld3_dup_p64(i64* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x1x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x1x3_t, align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x1x3_t* [[__RET]] to i8* @@ -522,7 +522,7 @@ poly64x1x3_t test_vld3_dup_p64(poly64_t *a) { // [{{x[0-9]+|sp}}] } -// CHECK-LABEL: define{{.*}} %struct.uint64x2x4_t @test_vld4q_dup_u64(i64* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint64x2x4_t @test_vld4q_dup_u64(i64* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint64x2x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x4_t, align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x2x4_t* [[__RET]] to i8* @@ -540,7 +540,7 @@ uint64x2x4_t test_vld4q_dup_u64(uint64_t *a) { return vld4q_dup_u64(a); } -// CHECK-LABEL: define{{.*}} %struct.int64x2x4_t @test_vld4q_dup_s64(i64* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.int64x2x4_t @test_vld4q_dup_s64(i64* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int64x2x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int64x2x4_t, align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x2x4_t* [[__RET]] to i8* @@ -558,7 +558,7 @@ int64x2x4_t test_vld4q_dup_s64(int64_t *a) { return vld4q_dup_s64(a); } -// CHECK-LABEL: define{{.*}} %struct.float64x2x4_t @test_vld4q_dup_f64(double* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.float64x2x4_t @test_vld4q_dup_f64(double* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x2x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float64x2x4_t, align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.float64x2x4_t* [[__RET]] to i8* @@ -576,7 +576,7 @@ float64x2x4_t test_vld4q_dup_f64(float64_t *a) { return vld4q_dup_f64(a); } -// CHECK-LABEL: define{{.*}} %struct.poly64x2x4_t @test_vld4q_dup_p64(i64* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x2x4_t @test_vld4q_dup_p64(i64* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x2x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x2x4_t, align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x2x4_t* [[__RET]] to i8* @@ -594,7 +594,7 @@ poly64x2x4_t test_vld4q_dup_p64(poly64_t *a) { return vld4q_dup_p64(a); } -// CHECK-LABEL: define{{.*}} %struct.float64x1x4_t @test_vld4_dup_f64(double* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.float64x1x4_t @test_vld4_dup_f64(double* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x1x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float64x1x4_t, align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.float64x1x4_t* [[__RET]] to i8* @@ -612,7 +612,7 @@ float64x1x4_t test_vld4_dup_f64(float64_t *a) { return vld4_dup_f64(a); } -// CHECK-LABEL: define{{.*}} %struct.poly64x1x4_t @test_vld4_dup_p64(i64* noundef %a) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x1x4_t @test_vld4_dup_p64(i64* %a) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x1x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x1x4_t, align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x1x4_t* [[__RET]] to i8* @@ -630,7 +630,7 @@ poly64x1x4_t test_vld4_dup_p64(poly64_t *a) { return vld4_dup_p64(a); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vld1q_lane_u8(i8* noundef %a, <16 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vld1q_lane_u8(i8* %a, <16 x i8> %b) #0 { // CHECK: [[TMP0:%.*]] = load i8, i8* %a // CHECK: [[VLD1_LANE:%.*]] = insertelement <16 x i8> %b, i8 [[TMP0]], i32 15 // CHECK: ret <16 x i8> [[VLD1_LANE]] @@ -638,7 +638,7 @@ uint8x16_t test_vld1q_lane_u8(uint8_t *a, uint8x16_t b) { return vld1q_lane_u8(a, b, 15); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vld1q_lane_u16(i16* noundef %a, <8 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vld1q_lane_u16(i16* %a, <8 x i16> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <8 x i16> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> @@ -650,7 +650,7 @@ uint16x8_t test_vld1q_lane_u16(uint16_t *a, uint16x8_t b) { return vld1q_lane_u16(a, b, 7); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vld1q_lane_u32(i32* noundef %a, <4 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vld1q_lane_u32(i32* %a, <4 x i32> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i32* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x i32> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> @@ -662,7 +662,7 @@ uint32x4_t test_vld1q_lane_u32(uint32_t *a, uint32x4_t b) { return vld1q_lane_u32(a, b, 3); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_lane_u64(i64* noundef %a, <2 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_lane_u64(i64* %a, <2 x i64> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> @@ -674,7 +674,7 @@ uint64x2_t test_vld1q_lane_u64(uint64_t *a, uint64x2_t b) { return vld1q_lane_u64(a, b, 1); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vld1q_lane_s8(i8* noundef %a, <16 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vld1q_lane_s8(i8* %a, <16 x i8> %b) #0 { // CHECK: [[TMP0:%.*]] = load i8, i8* %a // CHECK: [[VLD1_LANE:%.*]] = insertelement <16 x i8> %b, i8 [[TMP0]], i32 15 // CHECK: ret <16 x i8> [[VLD1_LANE]] @@ -682,7 +682,7 @@ int8x16_t test_vld1q_lane_s8(int8_t *a, int8x16_t b) { return vld1q_lane_s8(a, b, 15); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vld1q_lane_s16(i16* noundef %a, <8 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vld1q_lane_s16(i16* %a, <8 x i16> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <8 x i16> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> @@ -694,7 +694,7 @@ int16x8_t test_vld1q_lane_s16(int16_t *a, int16x8_t b) { return vld1q_lane_s16(a, b, 7); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vld1q_lane_s32(i32* noundef %a, <4 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vld1q_lane_s32(i32* %a, <4 x i32> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i32* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x i32> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> @@ -706,7 +706,7 @@ int32x4_t test_vld1q_lane_s32(int32_t *a, int32x4_t b) { return vld1q_lane_s32(a, b, 3); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_lane_s64(i64* noundef %a, <2 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_lane_s64(i64* %a, <2 x i64> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> @@ -718,7 +718,7 @@ int64x2_t test_vld1q_lane_s64(int64_t *a, int64x2_t b) { return vld1q_lane_s64(a, b, 1); } -// CHECK-LABEL: define{{.*}} <8 x half> @test_vld1q_lane_f16(half* noundef %a, <8 x half> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x half> @test_vld1q_lane_f16(half* %a, <8 x half> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half> @@ -730,7 +730,7 @@ float16x8_t test_vld1q_lane_f16(float16_t *a, float16x8_t b) { return vld1q_lane_f16(a, b, 7); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vld1q_lane_f32(float* noundef %a, <4 x float> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vld1q_lane_f32(float* %a, <4 x float> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast float* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> @@ -742,7 +742,7 @@ float32x4_t test_vld1q_lane_f32(float32_t *a, float32x4_t b) { return vld1q_lane_f32(a, b, 3); } -// CHECK-LABEL: define{{.*}} <2 x double> @test_vld1q_lane_f64(double* noundef %a, <2 x double> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x double> @test_vld1q_lane_f64(double* %a, <2 x double> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast double* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <2 x double> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> @@ -754,7 +754,7 @@ float64x2_t test_vld1q_lane_f64(float64_t *a, float64x2_t b) { return vld1q_lane_f64(a, b, 1); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vld1q_lane_p8(i8* noundef %a, <16 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vld1q_lane_p8(i8* %a, <16 x i8> %b) #0 { // CHECK: [[TMP0:%.*]] = load i8, i8* %a // CHECK: [[VLD1_LANE:%.*]] = insertelement <16 x i8> %b, i8 [[TMP0]], i32 15 // CHECK: ret <16 x i8> [[VLD1_LANE]] @@ -762,7 +762,7 @@ poly8x16_t test_vld1q_lane_p8(poly8_t *a, poly8x16_t b) { return vld1q_lane_p8(a, b, 15); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vld1q_lane_p16(i16* noundef %a, <8 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vld1q_lane_p16(i16* %a, <8 x i16> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <8 x i16> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> @@ -774,7 +774,7 @@ poly16x8_t test_vld1q_lane_p16(poly16_t *a, poly16x8_t b) { return vld1q_lane_p16(a, b, 7); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_lane_p64(i64* noundef %a, <2 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_lane_p64(i64* %a, <2 x i64> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> @@ -786,7 +786,7 @@ poly64x2_t test_vld1q_lane_p64(poly64_t *a, poly64x2_t b) { return vld1q_lane_p64(a, b, 1); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vld1_lane_u8(i8* noundef %a, <8 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vld1_lane_u8(i8* %a, <8 x i8> %b) #1 { // CHECK: [[TMP0:%.*]] = load i8, i8* %a // CHECK: [[VLD1_LANE:%.*]] = insertelement <8 x i8> %b, i8 [[TMP0]], i32 7 // CHECK: ret <8 x i8> [[VLD1_LANE]] @@ -794,7 +794,7 @@ uint8x8_t test_vld1_lane_u8(uint8_t *a, uint8x8_t b) { return vld1_lane_u8(a, b, 7); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vld1_lane_u16(i16* noundef %a, <4 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vld1_lane_u16(i16* %a, <4 x i16> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> @@ -806,7 +806,7 @@ uint16x4_t test_vld1_lane_u16(uint16_t *a, uint16x4_t b) { return vld1_lane_u16(a, b, 3); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vld1_lane_u32(i32* noundef %a, <2 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vld1_lane_u32(i32* %a, <2 x i32> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i32* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> @@ -818,7 +818,7 @@ uint32x2_t test_vld1_lane_u32(uint32_t *a, uint32x2_t b) { return vld1_lane_u32(a, b, 1); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_lane_u64(i64* noundef %a, <1 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_lane_u64(i64* %a, <1 x i64> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> @@ -830,7 +830,7 @@ uint64x1_t test_vld1_lane_u64(uint64_t *a, uint64x1_t b) { return vld1_lane_u64(a, b, 0); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vld1_lane_s8(i8* noundef %a, <8 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vld1_lane_s8(i8* %a, <8 x i8> %b) #1 { // CHECK: [[TMP0:%.*]] = load i8, i8* %a // CHECK: [[VLD1_LANE:%.*]] = insertelement <8 x i8> %b, i8 [[TMP0]], i32 7 // CHECK: ret <8 x i8> [[VLD1_LANE]] @@ -838,7 +838,7 @@ int8x8_t test_vld1_lane_s8(int8_t *a, int8x8_t b) { return vld1_lane_s8(a, b, 7); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vld1_lane_s16(i16* noundef %a, <4 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vld1_lane_s16(i16* %a, <4 x i16> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> @@ -850,7 +850,7 @@ int16x4_t test_vld1_lane_s16(int16_t *a, int16x4_t b) { return vld1_lane_s16(a, b, 3); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vld1_lane_s32(i32* noundef %a, <2 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vld1_lane_s32(i32* %a, <2 x i32> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i32* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> @@ -862,7 +862,7 @@ int32x2_t test_vld1_lane_s32(int32_t *a, int32x2_t b) { return vld1_lane_s32(a, b, 1); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_lane_s64(i64* noundef %a, <1 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_lane_s64(i64* %a, <1 x i64> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> @@ -874,7 +874,7 @@ int64x1_t test_vld1_lane_s64(int64_t *a, int64x1_t b) { return vld1_lane_s64(a, b, 0); } -// CHECK-LABEL: define{{.*}} <4 x half> @test_vld1_lane_f16(half* noundef %a, <4 x half> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x half> @test_vld1_lane_f16(half* %a, <4 x half> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half> @@ -886,7 +886,7 @@ float16x4_t test_vld1_lane_f16(float16_t *a, float16x4_t b) { return vld1_lane_f16(a, b, 3); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vld1_lane_f32(float* noundef %a, <2 x float> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vld1_lane_f32(float* %a, <2 x float> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast float* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> @@ -898,7 +898,7 @@ float32x2_t test_vld1_lane_f32(float32_t *a, float32x2_t b) { return vld1_lane_f32(a, b, 1); } -// CHECK-LABEL: define{{.*}} <1 x double> @test_vld1_lane_f64(double* noundef %a, <1 x double> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <1 x double> @test_vld1_lane_f64(double* %a, <1 x double> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast double* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double> @@ -910,7 +910,7 @@ float64x1_t test_vld1_lane_f64(float64_t *a, float64x1_t b) { return vld1_lane_f64(a, b, 0); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vld1_lane_p8(i8* noundef %a, <8 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vld1_lane_p8(i8* %a, <8 x i8> %b) #1 { // CHECK: [[TMP0:%.*]] = load i8, i8* %a // CHECK: [[VLD1_LANE:%.*]] = insertelement <8 x i8> %b, i8 [[TMP0]], i32 7 // CHECK: ret <8 x i8> [[VLD1_LANE]] @@ -918,7 +918,7 @@ poly8x8_t test_vld1_lane_p8(poly8_t *a, poly8x8_t b) { return vld1_lane_p8(a, b, 7); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vld1_lane_p16(i16* noundef %a, <4 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vld1_lane_p16(i16* %a, <4 x i16> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> @@ -930,7 +930,7 @@ poly16x4_t test_vld1_lane_p16(poly16_t *a, poly16x4_t b) { return vld1_lane_p16(a, b, 3); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_lane_p64(i64* noundef %a, <1 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_lane_p64(i64* %a, <1 x i64> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> @@ -942,7 +942,7 @@ poly64x1_t test_vld1_lane_p64(poly64_t *a, poly64x1_t b) { return vld1_lane_p64(a, b, 0); } -// CHECK-LABEL: define{{.*}} %struct.int8x16x2_t @test_vld2q_lane_s8(i8* noundef %ptr, [2 x <16 x i8>] %src.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int8x16x2_t @test_vld2q_lane_s8(i8* %ptr, [2 x <16 x i8>] %src.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int8x16x2_t, align 16 // CHECK: [[SRC:%.*]] = alloca %struct.int8x16x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int8x16x2_t, align 16 @@ -971,7 +971,7 @@ int8x16x2_t test_vld2q_lane_s8(int8_t const * ptr, int8x16x2_t src) { return vld2q_lane_s8(ptr, src, 15); } -// CHECK-LABEL: define{{.*}} %struct.uint8x16x2_t @test_vld2q_lane_u8(i8* noundef %ptr, [2 x <16 x i8>] %src.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint8x16x2_t @test_vld2q_lane_u8(i8* %ptr, [2 x <16 x i8>] %src.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint8x16x2_t, align 16 // CHECK: [[SRC:%.*]] = alloca %struct.uint8x16x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint8x16x2_t, align 16 @@ -1000,7 +1000,7 @@ uint8x16x2_t test_vld2q_lane_u8(uint8_t const * ptr, uint8x16x2_t src) { return vld2q_lane_u8(ptr, src, 15); } -// CHECK-LABEL: define{{.*}} %struct.poly8x16x2_t @test_vld2q_lane_p8(i8* noundef %ptr, [2 x <16 x i8>] %src.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly8x16x2_t @test_vld2q_lane_p8(i8* %ptr, [2 x <16 x i8>] %src.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly8x16x2_t, align 16 // CHECK: [[SRC:%.*]] = alloca %struct.poly8x16x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly8x16x2_t, align 16 @@ -1029,7 +1029,7 @@ poly8x16x2_t test_vld2q_lane_p8(poly8_t const * ptr, poly8x16x2_t src) { return vld2q_lane_p8(ptr, src, 15); } -// CHECK-LABEL: define{{.*}} %struct.int8x16x3_t @test_vld3q_lane_s8(i8* noundef %ptr, [3 x <16 x i8>] %src.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int8x16x3_t @test_vld3q_lane_s8(i8* %ptr, [3 x <16 x i8>] %src.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int8x16x3_t, align 16 // CHECK: [[SRC:%.*]] = alloca %struct.int8x16x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int8x16x3_t, align 16 @@ -1061,7 +1061,7 @@ int8x16x3_t test_vld3q_lane_s8(int8_t const * ptr, int8x16x3_t src) { return vld3q_lane_s8(ptr, src, 15); } -// CHECK-LABEL: define{{.*}} %struct.uint8x16x3_t @test_vld3q_lane_u8(i8* noundef %ptr, [3 x <16 x i8>] %src.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint8x16x3_t @test_vld3q_lane_u8(i8* %ptr, [3 x <16 x i8>] %src.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint8x16x3_t, align 16 // CHECK: [[SRC:%.*]] = alloca %struct.uint8x16x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint8x16x3_t, align 16 @@ -1093,7 +1093,7 @@ uint8x16x3_t test_vld3q_lane_u8(uint8_t const * ptr, uint8x16x3_t src) { return vld3q_lane_u8(ptr, src, 15); } -// CHECK-LABEL: define{{.*}} %struct.uint16x8x2_t @test_vld2q_lane_u16(i16* noundef %a, [2 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint16x8x2_t @test_vld2q_lane_u16(i16* %a, [2 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint16x8x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint16x8x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x2_t, align 16 @@ -1127,7 +1127,7 @@ uint16x8x2_t test_vld2q_lane_u16(uint16_t *a, uint16x8x2_t b) { return vld2q_lane_u16(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.uint32x4x2_t @test_vld2q_lane_u32(i32* noundef %a, [2 x <4 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint32x4x2_t @test_vld2q_lane_u32(i32* %a, [2 x <4 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint32x4x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint32x4x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x2_t, align 16 @@ -1161,7 +1161,7 @@ uint32x4x2_t test_vld2q_lane_u32(uint32_t *a, uint32x4x2_t b) { return vld2q_lane_u32(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.uint64x2x2_t @test_vld2q_lane_u64(i64* noundef %a, [2 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint64x2x2_t @test_vld2q_lane_u64(i64* %a, [2 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint64x2x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint64x2x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint64x2x2_t, align 16 @@ -1195,7 +1195,7 @@ uint64x2x2_t test_vld2q_lane_u64(uint64_t *a, uint64x2x2_t b) { return vld2q_lane_u64(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.int16x8x2_t @test_vld2q_lane_s16(i16* noundef %a, [2 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int16x8x2_t @test_vld2q_lane_s16(i16* %a, [2 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int16x8x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int16x8x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int16x8x2_t, align 16 @@ -1229,7 +1229,7 @@ int16x8x2_t test_vld2q_lane_s16(int16_t *a, int16x8x2_t b) { return vld2q_lane_s16(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.int32x4x2_t @test_vld2q_lane_s32(i32* noundef %a, [2 x <4 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int32x4x2_t @test_vld2q_lane_s32(i32* %a, [2 x <4 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int32x4x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int32x4x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int32x4x2_t, align 16 @@ -1263,7 +1263,7 @@ int32x4x2_t test_vld2q_lane_s32(int32_t *a, int32x4x2_t b) { return vld2q_lane_s32(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.int64x2x2_t @test_vld2q_lane_s64(i64* noundef %a, [2 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int64x2x2_t @test_vld2q_lane_s64(i64* %a, [2 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int64x2x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int64x2x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int64x2x2_t, align 16 @@ -1297,7 +1297,7 @@ int64x2x2_t test_vld2q_lane_s64(int64_t *a, int64x2x2_t b) { return vld2q_lane_s64(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.float16x8x2_t @test_vld2q_lane_f16(half* noundef %a, [2 x <8 x half>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float16x8x2_t @test_vld2q_lane_f16(half* %a, [2 x <8 x half>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float16x8x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float16x8x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float16x8x2_t, align 16 @@ -1331,7 +1331,7 @@ float16x8x2_t test_vld2q_lane_f16(float16_t *a, float16x8x2_t b) { return vld2q_lane_f16(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.float32x4x2_t @test_vld2q_lane_f32(float* noundef %a, [2 x <4 x float>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float32x4x2_t @test_vld2q_lane_f32(float* %a, [2 x <4 x float>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float32x4x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float32x4x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float32x4x2_t, align 16 @@ -1365,7 +1365,7 @@ float32x4x2_t test_vld2q_lane_f32(float32_t *a, float32x4x2_t b) { return vld2q_lane_f32(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.float64x2x2_t @test_vld2q_lane_f64(double* noundef %a, [2 x <2 x double>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float64x2x2_t @test_vld2q_lane_f64(double* %a, [2 x <2 x double>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x2x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float64x2x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float64x2x2_t, align 16 @@ -1399,7 +1399,7 @@ float64x2x2_t test_vld2q_lane_f64(float64_t *a, float64x2x2_t b) { return vld2q_lane_f64(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.poly16x8x2_t @test_vld2q_lane_p16(i16* noundef %a, [2 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly16x8x2_t @test_vld2q_lane_p16(i16* %a, [2 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly16x8x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly16x8x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x2_t, align 16 @@ -1433,7 +1433,7 @@ poly16x8x2_t test_vld2q_lane_p16(poly16_t *a, poly16x8x2_t b) { return vld2q_lane_p16(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.poly64x2x2_t @test_vld2q_lane_p64(i64* noundef %a, [2 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x2x2_t @test_vld2q_lane_p64(i64* %a, [2 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x2x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly64x2x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x2_t, align 16 @@ -1467,7 +1467,7 @@ poly64x2x2_t test_vld2q_lane_p64(poly64_t *a, poly64x2x2_t b) { return vld2q_lane_p64(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.uint8x8x2_t @test_vld2_lane_u8(i8* noundef %a, [2 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint8x8x2_t @test_vld2_lane_u8(i8* %a, [2 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint8x8x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint8x8x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x2_t, align 8 @@ -1496,7 +1496,7 @@ uint8x8x2_t test_vld2_lane_u8(uint8_t *a, uint8x8x2_t b) { return vld2_lane_u8(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.uint16x4x2_t @test_vld2_lane_u16(i16* noundef %a, [2 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint16x4x2_t @test_vld2_lane_u16(i16* %a, [2 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint16x4x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint16x4x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x2_t, align 8 @@ -1530,7 +1530,7 @@ uint16x4x2_t test_vld2_lane_u16(uint16_t *a, uint16x4x2_t b) { return vld2_lane_u16(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.uint32x2x2_t @test_vld2_lane_u32(i32* noundef %a, [2 x <2 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint32x2x2_t @test_vld2_lane_u32(i32* %a, [2 x <2 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint32x2x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint32x2x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x2_t, align 8 @@ -1564,7 +1564,7 @@ uint32x2x2_t test_vld2_lane_u32(uint32_t *a, uint32x2x2_t b) { return vld2_lane_u32(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.uint64x1x2_t @test_vld2_lane_u64(i64* noundef %a, [2 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint64x1x2_t @test_vld2_lane_u64(i64* %a, [2 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint64x1x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint64x1x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint64x1x2_t, align 8 @@ -1598,7 +1598,7 @@ uint64x1x2_t test_vld2_lane_u64(uint64_t *a, uint64x1x2_t b) { return vld2_lane_u64(a, b, 0); } -// CHECK-LABEL: define{{.*}} %struct.int8x8x2_t @test_vld2_lane_s8(i8* noundef %a, [2 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int8x8x2_t @test_vld2_lane_s8(i8* %a, [2 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int8x8x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int8x8x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int8x8x2_t, align 8 @@ -1627,7 +1627,7 @@ int8x8x2_t test_vld2_lane_s8(int8_t *a, int8x8x2_t b) { return vld2_lane_s8(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.int16x4x2_t @test_vld2_lane_s16(i16* noundef %a, [2 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int16x4x2_t @test_vld2_lane_s16(i16* %a, [2 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int16x4x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int16x4x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int16x4x2_t, align 8 @@ -1661,7 +1661,7 @@ int16x4x2_t test_vld2_lane_s16(int16_t *a, int16x4x2_t b) { return vld2_lane_s16(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.int32x2x2_t @test_vld2_lane_s32(i32* noundef %a, [2 x <2 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int32x2x2_t @test_vld2_lane_s32(i32* %a, [2 x <2 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int32x2x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int32x2x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int32x2x2_t, align 8 @@ -1695,7 +1695,7 @@ int32x2x2_t test_vld2_lane_s32(int32_t *a, int32x2x2_t b) { return vld2_lane_s32(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.int64x1x2_t @test_vld2_lane_s64(i64* noundef %a, [2 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int64x1x2_t @test_vld2_lane_s64(i64* %a, [2 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int64x1x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int64x1x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int64x1x2_t, align 8 @@ -1729,7 +1729,7 @@ int64x1x2_t test_vld2_lane_s64(int64_t *a, int64x1x2_t b) { return vld2_lane_s64(a, b, 0); } -// CHECK-LABEL: define{{.*}} %struct.float16x4x2_t @test_vld2_lane_f16(half* noundef %a, [2 x <4 x half>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float16x4x2_t @test_vld2_lane_f16(half* %a, [2 x <4 x half>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float16x4x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float16x4x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float16x4x2_t, align 8 @@ -1763,7 +1763,7 @@ float16x4x2_t test_vld2_lane_f16(float16_t *a, float16x4x2_t b) { return vld2_lane_f16(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.float32x2x2_t @test_vld2_lane_f32(float* noundef %a, [2 x <2 x float>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float32x2x2_t @test_vld2_lane_f32(float* %a, [2 x <2 x float>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float32x2x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float32x2x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float32x2x2_t, align 8 @@ -1797,7 +1797,7 @@ float32x2x2_t test_vld2_lane_f32(float32_t *a, float32x2x2_t b) { return vld2_lane_f32(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.float64x1x2_t @test_vld2_lane_f64(double* noundef %a, [2 x <1 x double>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float64x1x2_t @test_vld2_lane_f64(double* %a, [2 x <1 x double>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x1x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float64x1x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float64x1x2_t, align 8 @@ -1831,7 +1831,7 @@ float64x1x2_t test_vld2_lane_f64(float64_t *a, float64x1x2_t b) { return vld2_lane_f64(a, b, 0); } -// CHECK-LABEL: define{{.*}} %struct.poly8x8x2_t @test_vld2_lane_p8(i8* noundef %a, [2 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly8x8x2_t @test_vld2_lane_p8(i8* %a, [2 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly8x8x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly8x8x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x2_t, align 8 @@ -1860,7 +1860,7 @@ poly8x8x2_t test_vld2_lane_p8(poly8_t *a, poly8x8x2_t b) { return vld2_lane_p8(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.poly16x4x2_t @test_vld2_lane_p16(i16* noundef %a, [2 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly16x4x2_t @test_vld2_lane_p16(i16* %a, [2 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly16x4x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly16x4x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x2_t, align 8 @@ -1894,7 +1894,7 @@ poly16x4x2_t test_vld2_lane_p16(poly16_t *a, poly16x4x2_t b) { return vld2_lane_p16(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.poly64x1x2_t @test_vld2_lane_p64(i64* noundef %a, [2 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x1x2_t @test_vld2_lane_p64(i64* %a, [2 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x1x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly64x1x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x2_t, align 8 @@ -1928,7 +1928,7 @@ poly64x1x2_t test_vld2_lane_p64(poly64_t *a, poly64x1x2_t b) { return vld2_lane_p64(a, b, 0); } -// CHECK-LABEL: define{{.*}} %struct.uint16x8x3_t @test_vld3q_lane_u16(i16* noundef %a, [3 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint16x8x3_t @test_vld3q_lane_u16(i16* %a, [3 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint16x8x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint16x8x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x3_t, align 16 @@ -1967,7 +1967,7 @@ uint16x8x3_t test_vld3q_lane_u16(uint16_t *a, uint16x8x3_t b) { return vld3q_lane_u16(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.uint32x4x3_t @test_vld3q_lane_u32(i32* noundef %a, [3 x <4 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint32x4x3_t @test_vld3q_lane_u32(i32* %a, [3 x <4 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint32x4x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint32x4x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x3_t, align 16 @@ -2006,7 +2006,7 @@ uint32x4x3_t test_vld3q_lane_u32(uint32_t *a, uint32x4x3_t b) { return vld3q_lane_u32(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.uint64x2x3_t @test_vld3q_lane_u64(i64* noundef %a, [3 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint64x2x3_t @test_vld3q_lane_u64(i64* %a, [3 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint64x2x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint64x2x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint64x2x3_t, align 16 @@ -2045,7 +2045,7 @@ uint64x2x3_t test_vld3q_lane_u64(uint64_t *a, uint64x2x3_t b) { return vld3q_lane_u64(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.int16x8x3_t @test_vld3q_lane_s16(i16* noundef %a, [3 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int16x8x3_t @test_vld3q_lane_s16(i16* %a, [3 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int16x8x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int16x8x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int16x8x3_t, align 16 @@ -2084,7 +2084,7 @@ int16x8x3_t test_vld3q_lane_s16(int16_t *a, int16x8x3_t b) { return vld3q_lane_s16(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.int32x4x3_t @test_vld3q_lane_s32(i32* noundef %a, [3 x <4 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int32x4x3_t @test_vld3q_lane_s32(i32* %a, [3 x <4 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int32x4x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int32x4x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int32x4x3_t, align 16 @@ -2123,7 +2123,7 @@ int32x4x3_t test_vld3q_lane_s32(int32_t *a, int32x4x3_t b) { return vld3q_lane_s32(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.int64x2x3_t @test_vld3q_lane_s64(i64* noundef %a, [3 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int64x2x3_t @test_vld3q_lane_s64(i64* %a, [3 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int64x2x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int64x2x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int64x2x3_t, align 16 @@ -2162,7 +2162,7 @@ int64x2x3_t test_vld3q_lane_s64(int64_t *a, int64x2x3_t b) { return vld3q_lane_s64(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.float16x8x3_t @test_vld3q_lane_f16(half* noundef %a, [3 x <8 x half>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float16x8x3_t @test_vld3q_lane_f16(half* %a, [3 x <8 x half>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float16x8x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float16x8x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float16x8x3_t, align 16 @@ -2201,7 +2201,7 @@ float16x8x3_t test_vld3q_lane_f16(float16_t *a, float16x8x3_t b) { return vld3q_lane_f16(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.float32x4x3_t @test_vld3q_lane_f32(float* noundef %a, [3 x <4 x float>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float32x4x3_t @test_vld3q_lane_f32(float* %a, [3 x <4 x float>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float32x4x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float32x4x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float32x4x3_t, align 16 @@ -2240,7 +2240,7 @@ float32x4x3_t test_vld3q_lane_f32(float32_t *a, float32x4x3_t b) { return vld3q_lane_f32(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.float64x2x3_t @test_vld3q_lane_f64(double* noundef %a, [3 x <2 x double>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float64x2x3_t @test_vld3q_lane_f64(double* %a, [3 x <2 x double>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x2x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float64x2x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float64x2x3_t, align 16 @@ -2279,7 +2279,7 @@ float64x2x3_t test_vld3q_lane_f64(float64_t *a, float64x2x3_t b) { return vld3q_lane_f64(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.poly8x16x3_t @test_vld3q_lane_p8(i8* noundef %a, [3 x <16 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly8x16x3_t @test_vld3q_lane_p8(i8* %a, [3 x <16 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly8x16x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly8x16x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly8x16x3_t, align 16 @@ -2311,7 +2311,7 @@ poly8x16x3_t test_vld3q_lane_p8(poly8_t *a, poly8x16x3_t b) { return vld3q_lane_p8(a, b, 15); } -// CHECK-LABEL: define{{.*}} %struct.poly16x8x3_t @test_vld3q_lane_p16(i16* noundef %a, [3 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly16x8x3_t @test_vld3q_lane_p16(i16* %a, [3 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly16x8x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly16x8x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x3_t, align 16 @@ -2350,7 +2350,7 @@ poly16x8x3_t test_vld3q_lane_p16(poly16_t *a, poly16x8x3_t b) { return vld3q_lane_p16(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.poly64x2x3_t @test_vld3q_lane_p64(i64* noundef %a, [3 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x2x3_t @test_vld3q_lane_p64(i64* %a, [3 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x2x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly64x2x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x3_t, align 16 @@ -2389,7 +2389,7 @@ poly64x2x3_t test_vld3q_lane_p64(poly64_t *a, poly64x2x3_t b) { return vld3q_lane_p64(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.uint8x8x3_t @test_vld3_lane_u8(i8* noundef %a, [3 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint8x8x3_t @test_vld3_lane_u8(i8* %a, [3 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint8x8x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint8x8x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x3_t, align 8 @@ -2421,7 +2421,7 @@ uint8x8x3_t test_vld3_lane_u8(uint8_t *a, uint8x8x3_t b) { return vld3_lane_u8(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.uint16x4x3_t @test_vld3_lane_u16(i16* noundef %a, [3 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint16x4x3_t @test_vld3_lane_u16(i16* %a, [3 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint16x4x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint16x4x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x3_t, align 8 @@ -2460,7 +2460,7 @@ uint16x4x3_t test_vld3_lane_u16(uint16_t *a, uint16x4x3_t b) { return vld3_lane_u16(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.uint32x2x3_t @test_vld3_lane_u32(i32* noundef %a, [3 x <2 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint32x2x3_t @test_vld3_lane_u32(i32* %a, [3 x <2 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint32x2x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint32x2x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x3_t, align 8 @@ -2499,7 +2499,7 @@ uint32x2x3_t test_vld3_lane_u32(uint32_t *a, uint32x2x3_t b) { return vld3_lane_u32(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.uint64x1x3_t @test_vld3_lane_u64(i64* noundef %a, [3 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint64x1x3_t @test_vld3_lane_u64(i64* %a, [3 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint64x1x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint64x1x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint64x1x3_t, align 8 @@ -2538,7 +2538,7 @@ uint64x1x3_t test_vld3_lane_u64(uint64_t *a, uint64x1x3_t b) { return vld3_lane_u64(a, b, 0); } -// CHECK-LABEL: define{{.*}} %struct.int8x8x3_t @test_vld3_lane_s8(i8* noundef %a, [3 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int8x8x3_t @test_vld3_lane_s8(i8* %a, [3 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int8x8x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int8x8x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int8x8x3_t, align 8 @@ -2570,7 +2570,7 @@ int8x8x3_t test_vld3_lane_s8(int8_t *a, int8x8x3_t b) { return vld3_lane_s8(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.int16x4x3_t @test_vld3_lane_s16(i16* noundef %a, [3 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int16x4x3_t @test_vld3_lane_s16(i16* %a, [3 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int16x4x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int16x4x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int16x4x3_t, align 8 @@ -2609,7 +2609,7 @@ int16x4x3_t test_vld3_lane_s16(int16_t *a, int16x4x3_t b) { return vld3_lane_s16(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.int32x2x3_t @test_vld3_lane_s32(i32* noundef %a, [3 x <2 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int32x2x3_t @test_vld3_lane_s32(i32* %a, [3 x <2 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int32x2x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int32x2x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int32x2x3_t, align 8 @@ -2648,7 +2648,7 @@ int32x2x3_t test_vld3_lane_s32(int32_t *a, int32x2x3_t b) { return vld3_lane_s32(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.int64x1x3_t @test_vld3_lane_s64(i64* noundef %a, [3 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int64x1x3_t @test_vld3_lane_s64(i64* %a, [3 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int64x1x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int64x1x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int64x1x3_t, align 8 @@ -2687,7 +2687,7 @@ int64x1x3_t test_vld3_lane_s64(int64_t *a, int64x1x3_t b) { return vld3_lane_s64(a, b, 0); } -// CHECK-LABEL: define{{.*}} %struct.float16x4x3_t @test_vld3_lane_f16(half* noundef %a, [3 x <4 x half>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float16x4x3_t @test_vld3_lane_f16(half* %a, [3 x <4 x half>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float16x4x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float16x4x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float16x4x3_t, align 8 @@ -2726,7 +2726,7 @@ float16x4x3_t test_vld3_lane_f16(float16_t *a, float16x4x3_t b) { return vld3_lane_f16(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.float32x2x3_t @test_vld3_lane_f32(float* noundef %a, [3 x <2 x float>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float32x2x3_t @test_vld3_lane_f32(float* %a, [3 x <2 x float>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float32x2x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float32x2x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float32x2x3_t, align 8 @@ -2765,7 +2765,7 @@ float32x2x3_t test_vld3_lane_f32(float32_t *a, float32x2x3_t b) { return vld3_lane_f32(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.float64x1x3_t @test_vld3_lane_f64(double* noundef %a, [3 x <1 x double>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float64x1x3_t @test_vld3_lane_f64(double* %a, [3 x <1 x double>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x1x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float64x1x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float64x1x3_t, align 8 @@ -2804,7 +2804,7 @@ float64x1x3_t test_vld3_lane_f64(float64_t *a, float64x1x3_t b) { return vld3_lane_f64(a, b, 0); } -// CHECK-LABEL: define{{.*}} %struct.poly8x8x3_t @test_vld3_lane_p8(i8* noundef %a, [3 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly8x8x3_t @test_vld3_lane_p8(i8* %a, [3 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly8x8x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly8x8x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x3_t, align 8 @@ -2836,7 +2836,7 @@ poly8x8x3_t test_vld3_lane_p8(poly8_t *a, poly8x8x3_t b) { return vld3_lane_p8(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.poly16x4x3_t @test_vld3_lane_p16(i16* noundef %a, [3 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly16x4x3_t @test_vld3_lane_p16(i16* %a, [3 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly16x4x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly16x4x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x3_t, align 8 @@ -2875,7 +2875,7 @@ poly16x4x3_t test_vld3_lane_p16(poly16_t *a, poly16x4x3_t b) { return vld3_lane_p16(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.poly64x1x3_t @test_vld3_lane_p64(i64* noundef %a, [3 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x1x3_t @test_vld3_lane_p64(i64* %a, [3 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x1x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly64x1x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x3_t, align 8 @@ -2914,7 +2914,7 @@ poly64x1x3_t test_vld3_lane_p64(poly64_t *a, poly64x1x3_t b) { return vld3_lane_p64(a, b, 0); } -// CHECK-LABEL: define{{.*}} %struct.uint8x16x4_t @test_vld4q_lane_u8(i8* noundef %a, [4 x <16 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint8x16x4_t @test_vld4q_lane_u8(i8* %a, [4 x <16 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint8x16x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint8x16x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint8x16x4_t, align 16 @@ -2949,7 +2949,7 @@ uint8x16x4_t test_vld4q_lane_u8(uint8_t *a, uint8x16x4_t b) { return vld4q_lane_u8(a, b, 15); } -// CHECK-LABEL: define{{.*}} %struct.uint16x8x4_t @test_vld4q_lane_u16(i16* noundef %a, [4 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint16x8x4_t @test_vld4q_lane_u16(i16* %a, [4 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint16x8x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint16x8x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x4_t, align 16 @@ -2993,7 +2993,7 @@ uint16x8x4_t test_vld4q_lane_u16(uint16_t *a, uint16x8x4_t b) { return vld4q_lane_u16(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.uint32x4x4_t @test_vld4q_lane_u32(i32* noundef %a, [4 x <4 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint32x4x4_t @test_vld4q_lane_u32(i32* %a, [4 x <4 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint32x4x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint32x4x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x4_t, align 16 @@ -3037,7 +3037,7 @@ uint32x4x4_t test_vld4q_lane_u32(uint32_t *a, uint32x4x4_t b) { return vld4q_lane_u32(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.uint64x2x4_t @test_vld4q_lane_u64(i64* noundef %a, [4 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint64x2x4_t @test_vld4q_lane_u64(i64* %a, [4 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint64x2x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint64x2x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint64x2x4_t, align 16 @@ -3081,7 +3081,7 @@ uint64x2x4_t test_vld4q_lane_u64(uint64_t *a, uint64x2x4_t b) { return vld4q_lane_u64(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.int8x16x4_t @test_vld4q_lane_s8(i8* noundef %a, [4 x <16 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int8x16x4_t @test_vld4q_lane_s8(i8* %a, [4 x <16 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int8x16x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int8x16x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int8x16x4_t, align 16 @@ -3116,7 +3116,7 @@ int8x16x4_t test_vld4q_lane_s8(int8_t *a, int8x16x4_t b) { return vld4q_lane_s8(a, b, 15); } -// CHECK-LABEL: define{{.*}} %struct.int16x8x4_t @test_vld4q_lane_s16(i16* noundef %a, [4 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int16x8x4_t @test_vld4q_lane_s16(i16* %a, [4 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int16x8x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int16x8x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int16x8x4_t, align 16 @@ -3160,7 +3160,7 @@ int16x8x4_t test_vld4q_lane_s16(int16_t *a, int16x8x4_t b) { return vld4q_lane_s16(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.int32x4x4_t @test_vld4q_lane_s32(i32* noundef %a, [4 x <4 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int32x4x4_t @test_vld4q_lane_s32(i32* %a, [4 x <4 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int32x4x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int32x4x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int32x4x4_t, align 16 @@ -3204,7 +3204,7 @@ int32x4x4_t test_vld4q_lane_s32(int32_t *a, int32x4x4_t b) { return vld4q_lane_s32(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.int64x2x4_t @test_vld4q_lane_s64(i64* noundef %a, [4 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int64x2x4_t @test_vld4q_lane_s64(i64* %a, [4 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int64x2x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int64x2x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int64x2x4_t, align 16 @@ -3248,7 +3248,7 @@ int64x2x4_t test_vld4q_lane_s64(int64_t *a, int64x2x4_t b) { return vld4q_lane_s64(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.float16x8x4_t @test_vld4q_lane_f16(half* noundef %a, [4 x <8 x half>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float16x8x4_t @test_vld4q_lane_f16(half* %a, [4 x <8 x half>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float16x8x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float16x8x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float16x8x4_t, align 16 @@ -3292,7 +3292,7 @@ float16x8x4_t test_vld4q_lane_f16(float16_t *a, float16x8x4_t b) { return vld4q_lane_f16(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.float32x4x4_t @test_vld4q_lane_f32(float* noundef %a, [4 x <4 x float>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float32x4x4_t @test_vld4q_lane_f32(float* %a, [4 x <4 x float>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float32x4x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float32x4x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float32x4x4_t, align 16 @@ -3336,7 +3336,7 @@ float32x4x4_t test_vld4q_lane_f32(float32_t *a, float32x4x4_t b) { return vld4q_lane_f32(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.float64x2x4_t @test_vld4q_lane_f64(double* noundef %a, [4 x <2 x double>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float64x2x4_t @test_vld4q_lane_f64(double* %a, [4 x <2 x double>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x2x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float64x2x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float64x2x4_t, align 16 @@ -3380,7 +3380,7 @@ float64x2x4_t test_vld4q_lane_f64(float64_t *a, float64x2x4_t b) { return vld4q_lane_f64(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.poly8x16x4_t @test_vld4q_lane_p8(i8* noundef %a, [4 x <16 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly8x16x4_t @test_vld4q_lane_p8(i8* %a, [4 x <16 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly8x16x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly8x16x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly8x16x4_t, align 16 @@ -3415,7 +3415,7 @@ poly8x16x4_t test_vld4q_lane_p8(poly8_t *a, poly8x16x4_t b) { return vld4q_lane_p8(a, b, 15); } -// CHECK-LABEL: define{{.*}} %struct.poly16x8x4_t @test_vld4q_lane_p16(i16* noundef %a, [4 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly16x8x4_t @test_vld4q_lane_p16(i16* %a, [4 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly16x8x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly16x8x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x4_t, align 16 @@ -3459,7 +3459,7 @@ poly16x8x4_t test_vld4q_lane_p16(poly16_t *a, poly16x8x4_t b) { return vld4q_lane_p16(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.poly64x2x4_t @test_vld4q_lane_p64(i64* noundef %a, [4 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x2x4_t @test_vld4q_lane_p64(i64* %a, [4 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x2x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly64x2x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x4_t, align 16 @@ -3503,7 +3503,7 @@ poly64x2x4_t test_vld4q_lane_p64(poly64_t *a, poly64x2x4_t b) { return vld4q_lane_p64(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.uint8x8x4_t @test_vld4_lane_u8(i8* noundef %a, [4 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint8x8x4_t @test_vld4_lane_u8(i8* %a, [4 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint8x8x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint8x8x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x4_t, align 8 @@ -3538,7 +3538,7 @@ uint8x8x4_t test_vld4_lane_u8(uint8_t *a, uint8x8x4_t b) { return vld4_lane_u8(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.uint16x4x4_t @test_vld4_lane_u16(i16* noundef %a, [4 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint16x4x4_t @test_vld4_lane_u16(i16* %a, [4 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint16x4x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint16x4x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x4_t, align 8 @@ -3582,7 +3582,7 @@ uint16x4x4_t test_vld4_lane_u16(uint16_t *a, uint16x4x4_t b) { return vld4_lane_u16(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.uint32x2x4_t @test_vld4_lane_u32(i32* noundef %a, [4 x <2 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint32x2x4_t @test_vld4_lane_u32(i32* %a, [4 x <2 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint32x2x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint32x2x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x4_t, align 8 @@ -3626,7 +3626,7 @@ uint32x2x4_t test_vld4_lane_u32(uint32_t *a, uint32x2x4_t b) { return vld4_lane_u32(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.uint64x1x4_t @test_vld4_lane_u64(i64* noundef %a, [4 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.uint64x1x4_t @test_vld4_lane_u64(i64* %a, [4 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint64x1x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint64x1x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint64x1x4_t, align 8 @@ -3670,7 +3670,7 @@ uint64x1x4_t test_vld4_lane_u64(uint64_t *a, uint64x1x4_t b) { return vld4_lane_u64(a, b, 0); } -// CHECK-LABEL: define{{.*}} %struct.int8x8x4_t @test_vld4_lane_s8(i8* noundef %a, [4 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int8x8x4_t @test_vld4_lane_s8(i8* %a, [4 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int8x8x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int8x8x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int8x8x4_t, align 8 @@ -3705,7 +3705,7 @@ int8x8x4_t test_vld4_lane_s8(int8_t *a, int8x8x4_t b) { return vld4_lane_s8(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.int16x4x4_t @test_vld4_lane_s16(i16* noundef %a, [4 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int16x4x4_t @test_vld4_lane_s16(i16* %a, [4 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int16x4x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int16x4x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int16x4x4_t, align 8 @@ -3749,7 +3749,7 @@ int16x4x4_t test_vld4_lane_s16(int16_t *a, int16x4x4_t b) { return vld4_lane_s16(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.int32x2x4_t @test_vld4_lane_s32(i32* noundef %a, [4 x <2 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int32x2x4_t @test_vld4_lane_s32(i32* %a, [4 x <2 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int32x2x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int32x2x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int32x2x4_t, align 8 @@ -3793,7 +3793,7 @@ int32x2x4_t test_vld4_lane_s32(int32_t *a, int32x2x4_t b) { return vld4_lane_s32(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.int64x1x4_t @test_vld4_lane_s64(i64* noundef %a, [4 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.int64x1x4_t @test_vld4_lane_s64(i64* %a, [4 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int64x1x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int64x1x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int64x1x4_t, align 8 @@ -3837,7 +3837,7 @@ int64x1x4_t test_vld4_lane_s64(int64_t *a, int64x1x4_t b) { return vld4_lane_s64(a, b, 0); } -// CHECK-LABEL: define{{.*}} %struct.float16x4x4_t @test_vld4_lane_f16(half* noundef %a, [4 x <4 x half>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float16x4x4_t @test_vld4_lane_f16(half* %a, [4 x <4 x half>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float16x4x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float16x4x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float16x4x4_t, align 8 @@ -3881,7 +3881,7 @@ float16x4x4_t test_vld4_lane_f16(float16_t *a, float16x4x4_t b) { return vld4_lane_f16(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.float32x2x4_t @test_vld4_lane_f32(float* noundef %a, [4 x <2 x float>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float32x2x4_t @test_vld4_lane_f32(float* %a, [4 x <2 x float>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float32x2x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float32x2x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float32x2x4_t, align 8 @@ -3925,7 +3925,7 @@ float32x2x4_t test_vld4_lane_f32(float32_t *a, float32x2x4_t b) { return vld4_lane_f32(a, b, 1); } -// CHECK-LABEL: define{{.*}} %struct.float64x1x4_t @test_vld4_lane_f64(double* noundef %a, [4 x <1 x double>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.float64x1x4_t @test_vld4_lane_f64(double* %a, [4 x <1 x double>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x1x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float64x1x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float64x1x4_t, align 8 @@ -3969,7 +3969,7 @@ float64x1x4_t test_vld4_lane_f64(float64_t *a, float64x1x4_t b) { return vld4_lane_f64(a, b, 0); } -// CHECK-LABEL: define{{.*}} %struct.poly8x8x4_t @test_vld4_lane_p8(i8* noundef %a, [4 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly8x8x4_t @test_vld4_lane_p8(i8* %a, [4 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly8x8x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly8x8x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x4_t, align 8 @@ -4004,7 +4004,7 @@ poly8x8x4_t test_vld4_lane_p8(poly8_t *a, poly8x8x4_t b) { return vld4_lane_p8(a, b, 7); } -// CHECK-LABEL: define{{.*}} %struct.poly16x4x4_t @test_vld4_lane_p16(i16* noundef %a, [4 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly16x4x4_t @test_vld4_lane_p16(i16* %a, [4 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly16x4x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly16x4x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x4_t, align 8 @@ -4048,7 +4048,7 @@ poly16x4x4_t test_vld4_lane_p16(poly16_t *a, poly16x4x4_t b) { return vld4_lane_p16(a, b, 3); } -// CHECK-LABEL: define{{.*}} %struct.poly64x1x4_t @test_vld4_lane_p64(i64* noundef %a, [4 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x1x4_t @test_vld4_lane_p64(i64* %a, [4 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x1x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly64x1x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x4_t, align 8 @@ -4092,7 +4092,7 @@ poly64x1x4_t test_vld4_lane_p64(poly64_t *a, poly64x1x4_t b) { return vld4_lane_p64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_u8(i8* noundef %a, <16 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_u8(i8* %a, <16 x i8> %b) #0 { // CHECK: [[TMP0:%.*]] = extractelement <16 x i8> %b, i32 15 // CHECK: store i8 [[TMP0]], i8* %a // CHECK: ret void @@ -4100,7 +4100,7 @@ void test_vst1q_lane_u8(uint8_t *a, uint8x16_t b) { vst1q_lane_u8(a, b, 15); } -// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_u16(i16* noundef %a, <8 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_u16(i16* %a, <8 x i16> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <8 x i16> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> @@ -4112,7 +4112,7 @@ void test_vst1q_lane_u16(uint16_t *a, uint16x8_t b) { vst1q_lane_u16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_u32(i32* noundef %a, <4 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_u32(i32* %a, <4 x i32> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i32* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x i32> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> @@ -4124,7 +4124,7 @@ void test_vst1q_lane_u32(uint32_t *a, uint32x4_t b) { vst1q_lane_u32(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_u64(i64* noundef %a, <2 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_u64(i64* %a, <2 x i64> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> @@ -4136,7 +4136,7 @@ void test_vst1q_lane_u64(uint64_t *a, uint64x2_t b) { vst1q_lane_u64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_s8(i8* noundef %a, <16 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_s8(i8* %a, <16 x i8> %b) #0 { // CHECK: [[TMP0:%.*]] = extractelement <16 x i8> %b, i32 15 // CHECK: store i8 [[TMP0]], i8* %a // CHECK: ret void @@ -4144,7 +4144,7 @@ void test_vst1q_lane_s8(int8_t *a, int8x16_t b) { vst1q_lane_s8(a, b, 15); } -// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_s16(i16* noundef %a, <8 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_s16(i16* %a, <8 x i16> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <8 x i16> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> @@ -4156,7 +4156,7 @@ void test_vst1q_lane_s16(int16_t *a, int16x8_t b) { vst1q_lane_s16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_s32(i32* noundef %a, <4 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_s32(i32* %a, <4 x i32> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i32* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x i32> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> @@ -4168,7 +4168,7 @@ void test_vst1q_lane_s32(int32_t *a, int32x4_t b) { vst1q_lane_s32(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_s64(i64* noundef %a, <2 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_s64(i64* %a, <2 x i64> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> @@ -4180,7 +4180,7 @@ void test_vst1q_lane_s64(int64_t *a, int64x2_t b) { vst1q_lane_s64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_f16(half* noundef %a, <8 x half> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_f16(half* %a, <8 x half> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half> @@ -4192,7 +4192,7 @@ void test_vst1q_lane_f16(float16_t *a, float16x8_t b) { vst1q_lane_f16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_f32(float* noundef %a, <4 x float> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_f32(float* %a, <4 x float> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast float* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> @@ -4204,7 +4204,7 @@ void test_vst1q_lane_f32(float32_t *a, float32x4_t b) { vst1q_lane_f32(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_f64(double* noundef %a, <2 x double> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_f64(double* %a, <2 x double> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast double* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <2 x double> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> @@ -4216,7 +4216,7 @@ void test_vst1q_lane_f64(float64_t *a, float64x2_t b) { vst1q_lane_f64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_p8(i8* noundef %a, <16 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_p8(i8* %a, <16 x i8> %b) #0 { // CHECK: [[TMP0:%.*]] = extractelement <16 x i8> %b, i32 15 // CHECK: store i8 [[TMP0]], i8* %a // CHECK: ret void @@ -4224,7 +4224,7 @@ void test_vst1q_lane_p8(poly8_t *a, poly8x16_t b) { vst1q_lane_p8(a, b, 15); } -// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_p16(i16* noundef %a, <8 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_p16(i16* %a, <8 x i16> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <8 x i16> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> @@ -4236,7 +4236,7 @@ void test_vst1q_lane_p16(poly16_t *a, poly16x8_t b) { vst1q_lane_p16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_p64(i64* noundef %a, <2 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} void @test_vst1q_lane_p64(i64* %a, <2 x i64> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> @@ -4248,7 +4248,7 @@ void test_vst1q_lane_p64(poly64_t *a, poly64x2_t b) { vst1q_lane_p64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst1_lane_u8(i8* noundef %a, <8 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} void @test_vst1_lane_u8(i8* %a, <8 x i8> %b) #1 { // CHECK: [[TMP0:%.*]] = extractelement <8 x i8> %b, i32 7 // CHECK: store i8 [[TMP0]], i8* %a // CHECK: ret void @@ -4256,7 +4256,7 @@ void test_vst1_lane_u8(uint8_t *a, uint8x8_t b) { vst1_lane_u8(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst1_lane_u16(i16* noundef %a, <4 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} void @test_vst1_lane_u16(i16* %a, <4 x i16> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> @@ -4268,7 +4268,7 @@ void test_vst1_lane_u16(uint16_t *a, uint16x4_t b) { vst1_lane_u16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst1_lane_u32(i32* noundef %a, <2 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} void @test_vst1_lane_u32(i32* %a, <2 x i32> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i32* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> @@ -4280,7 +4280,7 @@ void test_vst1_lane_u32(uint32_t *a, uint32x2_t b) { vst1_lane_u32(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst1_lane_u64(i64* noundef %a, <1 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} void @test_vst1_lane_u64(i64* %a, <1 x i64> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> @@ -4292,7 +4292,7 @@ void test_vst1_lane_u64(uint64_t *a, uint64x1_t b) { vst1_lane_u64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst1_lane_s8(i8* noundef %a, <8 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} void @test_vst1_lane_s8(i8* %a, <8 x i8> %b) #1 { // CHECK: [[TMP0:%.*]] = extractelement <8 x i8> %b, i32 7 // CHECK: store i8 [[TMP0]], i8* %a // CHECK: ret void @@ -4300,7 +4300,7 @@ void test_vst1_lane_s8(int8_t *a, int8x8_t b) { vst1_lane_s8(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst1_lane_s16(i16* noundef %a, <4 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} void @test_vst1_lane_s16(i16* %a, <4 x i16> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> @@ -4312,7 +4312,7 @@ void test_vst1_lane_s16(int16_t *a, int16x4_t b) { vst1_lane_s16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst1_lane_s32(i32* noundef %a, <2 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} void @test_vst1_lane_s32(i32* %a, <2 x i32> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i32* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> @@ -4324,7 +4324,7 @@ void test_vst1_lane_s32(int32_t *a, int32x2_t b) { vst1_lane_s32(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst1_lane_s64(i64* noundef %a, <1 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} void @test_vst1_lane_s64(i64* %a, <1 x i64> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> @@ -4336,7 +4336,7 @@ void test_vst1_lane_s64(int64_t *a, int64x1_t b) { vst1_lane_s64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst1_lane_f16(half* noundef %a, <4 x half> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} void @test_vst1_lane_f16(half* %a, <4 x half> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half> @@ -4348,7 +4348,7 @@ void test_vst1_lane_f16(float16_t *a, float16x4_t b) { vst1_lane_f16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst1_lane_f32(float* noundef %a, <2 x float> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} void @test_vst1_lane_f32(float* %a, <2 x float> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast float* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> @@ -4360,7 +4360,7 @@ void test_vst1_lane_f32(float32_t *a, float32x2_t b) { vst1_lane_f32(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst1_lane_f64(double* noundef %a, <1 x double> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} void @test_vst1_lane_f64(double* %a, <1 x double> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast double* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double> @@ -4372,7 +4372,7 @@ void test_vst1_lane_f64(float64_t *a, float64x1_t b) { vst1_lane_f64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst1_lane_p8(i8* noundef %a, <8 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} void @test_vst1_lane_p8(i8* %a, <8 x i8> %b) #1 { // CHECK: [[TMP0:%.*]] = extractelement <8 x i8> %b, i32 7 // CHECK: store i8 [[TMP0]], i8* %a // CHECK: ret void @@ -4380,7 +4380,7 @@ void test_vst1_lane_p8(poly8_t *a, poly8x8_t b) { vst1_lane_p8(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst1_lane_p16(i16* noundef %a, <4 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} void @test_vst1_lane_p16(i16* %a, <4 x i16> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> @@ -4392,7 +4392,7 @@ void test_vst1_lane_p16(poly16_t *a, poly16x4_t b) { vst1_lane_p16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst1_lane_p64(i64* noundef %a, <1 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} void @test_vst1_lane_p64(i64* %a, <1 x i64> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8* // CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> @@ -4404,7 +4404,7 @@ void test_vst1_lane_p64(poly64_t *a, poly64x1_t b) { vst1_lane_p64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_u8(i8* noundef %a, [2 x <16 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_u8(i8* %a, [2 x <16 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint8x16x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x2_t, %struct.uint8x16x2_t* [[B]], i32 0, i32 0 @@ -4424,7 +4424,7 @@ void test_vst2q_lane_u8(uint8_t *a, uint8x16x2_t b) { vst2q_lane_u8(a, b, 15); } -// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_u16(i16* noundef %a, [2 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_u16(i16* %a, [2 x <8 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint16x8x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x8x2_t, %struct.uint16x8x2_t* [[B]], i32 0, i32 0 @@ -4449,7 +4449,7 @@ void test_vst2q_lane_u16(uint16_t *a, uint16x8x2_t b) { vst2q_lane_u16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_u32(i32* noundef %a, [2 x <4 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_u32(i32* %a, [2 x <4 x i32>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint32x4x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x4x2_t, %struct.uint32x4x2_t* [[B]], i32 0, i32 0 @@ -4474,7 +4474,7 @@ void test_vst2q_lane_u32(uint32_t *a, uint32x4x2_t b) { vst2q_lane_u32(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_u64(i64* noundef %a, [2 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_u64(i64* %a, [2 x <2 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint64x2x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint64x2x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint64x2x2_t, %struct.uint64x2x2_t* [[B]], i32 0, i32 0 @@ -4499,7 +4499,7 @@ void test_vst2q_lane_u64(uint64_t *a, uint64x2x2_t b) { vst2q_lane_u64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_s8(i8* noundef %a, [2 x <16 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_s8(i8* %a, [2 x <16 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int8x16x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x2_t, %struct.int8x16x2_t* [[B]], i32 0, i32 0 @@ -4519,7 +4519,7 @@ void test_vst2q_lane_s8(int8_t *a, int8x16x2_t b) { vst2q_lane_s8(a, b, 15); } -// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_s16(i16* noundef %a, [2 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_s16(i16* %a, [2 x <8 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int16x8x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int16x8x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x8x2_t, %struct.int16x8x2_t* [[B]], i32 0, i32 0 @@ -4544,7 +4544,7 @@ void test_vst2q_lane_s16(int16_t *a, int16x8x2_t b) { vst2q_lane_s16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_s32(i32* noundef %a, [2 x <4 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_s32(i32* %a, [2 x <4 x i32>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int32x4x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int32x4x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x4x2_t, %struct.int32x4x2_t* [[B]], i32 0, i32 0 @@ -4569,7 +4569,7 @@ void test_vst2q_lane_s32(int32_t *a, int32x4x2_t b) { vst2q_lane_s32(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_s64(i64* noundef %a, [2 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_s64(i64* %a, [2 x <2 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int64x2x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int64x2x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int64x2x2_t, %struct.int64x2x2_t* [[B]], i32 0, i32 0 @@ -4594,7 +4594,7 @@ void test_vst2q_lane_s64(int64_t *a, int64x2x2_t b) { vst2q_lane_s64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_f16(half* noundef %a, [2 x <8 x half>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_f16(half* %a, [2 x <8 x half>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float16x8x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float16x8x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x8x2_t, %struct.float16x8x2_t* [[B]], i32 0, i32 0 @@ -4619,7 +4619,7 @@ void test_vst2q_lane_f16(float16_t *a, float16x8x2_t b) { vst2q_lane_f16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_f32(float* noundef %a, [2 x <4 x float>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_f32(float* %a, [2 x <4 x float>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float32x4x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float32x4x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x4x2_t, %struct.float32x4x2_t* [[B]], i32 0, i32 0 @@ -4644,7 +4644,7 @@ void test_vst2q_lane_f32(float32_t *a, float32x4x2_t b) { vst2q_lane_f32(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_f64(double* noundef %a, [2 x <2 x double>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_f64(double* %a, [2 x <2 x double>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float64x2x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float64x2x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float64x2x2_t, %struct.float64x2x2_t* [[B]], i32 0, i32 0 @@ -4669,7 +4669,7 @@ void test_vst2q_lane_f64(float64_t *a, float64x2x2_t b) { vst2q_lane_f64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_p8(i8* noundef %a, [2 x <16 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_p8(i8* %a, [2 x <16 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly8x16x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x2_t, %struct.poly8x16x2_t* [[B]], i32 0, i32 0 @@ -4689,7 +4689,7 @@ void test_vst2q_lane_p8(poly8_t *a, poly8x16x2_t b) { vst2q_lane_p8(a, b, 15); } -// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_p16(i16* noundef %a, [2 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_p16(i16* %a, [2 x <8 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly16x8x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x8x2_t, %struct.poly16x8x2_t* [[B]], i32 0, i32 0 @@ -4714,7 +4714,7 @@ void test_vst2q_lane_p16(poly16_t *a, poly16x8x2_t b) { vst2q_lane_p16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_p64(i64* noundef %a, [2 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2q_lane_p64(i64* %a, [2 x <2 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly64x2x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x2x2_t, %struct.poly64x2x2_t* [[B]], i32 0, i32 0 @@ -4739,7 +4739,7 @@ void test_vst2q_lane_p64(poly64_t *a, poly64x2x2_t b) { vst2q_lane_p64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst2_lane_u8(i8* noundef %a, [2 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2_lane_u8(i8* %a, [2 x <8 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint8x8x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x2_t, %struct.uint8x8x2_t* [[B]], i32 0, i32 0 @@ -4759,7 +4759,7 @@ void test_vst2_lane_u8(uint8_t *a, uint8x8x2_t b) { vst2_lane_u8(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst2_lane_u16(i16* noundef %a, [2 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2_lane_u16(i16* %a, [2 x <4 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint16x4x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x4x2_t, %struct.uint16x4x2_t* [[B]], i32 0, i32 0 @@ -4784,7 +4784,7 @@ void test_vst2_lane_u16(uint16_t *a, uint16x4x2_t b) { vst2_lane_u16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst2_lane_u32(i32* noundef %a, [2 x <2 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2_lane_u32(i32* %a, [2 x <2 x i32>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint32x2x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x2x2_t, %struct.uint32x2x2_t* [[B]], i32 0, i32 0 @@ -4809,7 +4809,7 @@ void test_vst2_lane_u32(uint32_t *a, uint32x2x2_t b) { vst2_lane_u32(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst2_lane_u64(i64* noundef %a, [2 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2_lane_u64(i64* %a, [2 x <1 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint64x1x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint64x1x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint64x1x2_t, %struct.uint64x1x2_t* [[B]], i32 0, i32 0 @@ -4834,7 +4834,7 @@ void test_vst2_lane_u64(uint64_t *a, uint64x1x2_t b) { vst2_lane_u64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst2_lane_s8(i8* noundef %a, [2 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2_lane_s8(i8* %a, [2 x <8 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int8x8x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int8x8x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x2_t, %struct.int8x8x2_t* [[B]], i32 0, i32 0 @@ -4854,7 +4854,7 @@ void test_vst2_lane_s8(int8_t *a, int8x8x2_t b) { vst2_lane_s8(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst2_lane_s16(i16* noundef %a, [2 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2_lane_s16(i16* %a, [2 x <4 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int16x4x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int16x4x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x4x2_t, %struct.int16x4x2_t* [[B]], i32 0, i32 0 @@ -4879,7 +4879,7 @@ void test_vst2_lane_s16(int16_t *a, int16x4x2_t b) { vst2_lane_s16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst2_lane_s32(i32* noundef %a, [2 x <2 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2_lane_s32(i32* %a, [2 x <2 x i32>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int32x2x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int32x2x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x2x2_t, %struct.int32x2x2_t* [[B]], i32 0, i32 0 @@ -4904,7 +4904,7 @@ void test_vst2_lane_s32(int32_t *a, int32x2x2_t b) { vst2_lane_s32(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst2_lane_s64(i64* noundef %a, [2 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2_lane_s64(i64* %a, [2 x <1 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int64x1x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int64x1x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int64x1x2_t, %struct.int64x1x2_t* [[B]], i32 0, i32 0 @@ -4929,7 +4929,7 @@ void test_vst2_lane_s64(int64_t *a, int64x1x2_t b) { vst2_lane_s64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst2_lane_f16(half* noundef %a, [2 x <4 x half>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2_lane_f16(half* %a, [2 x <4 x half>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float16x4x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float16x4x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x4x2_t, %struct.float16x4x2_t* [[B]], i32 0, i32 0 @@ -4954,7 +4954,7 @@ void test_vst2_lane_f16(float16_t *a, float16x4x2_t b) { vst2_lane_f16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst2_lane_f32(float* noundef %a, [2 x <2 x float>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2_lane_f32(float* %a, [2 x <2 x float>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float32x2x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float32x2x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x2x2_t, %struct.float32x2x2_t* [[B]], i32 0, i32 0 @@ -4979,7 +4979,7 @@ void test_vst2_lane_f32(float32_t *a, float32x2x2_t b) { vst2_lane_f32(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst2_lane_f64(double* noundef %a, [2 x <1 x double>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2_lane_f64(double* %a, [2 x <1 x double>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float64x1x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float64x1x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float64x1x2_t, %struct.float64x1x2_t* [[B]], i32 0, i32 0 @@ -5004,7 +5004,7 @@ void test_vst2_lane_f64(float64_t *a, float64x1x2_t b) { vst2_lane_f64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst2_lane_p8(i8* noundef %a, [2 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2_lane_p8(i8* %a, [2 x <8 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly8x8x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x2_t, %struct.poly8x8x2_t* [[B]], i32 0, i32 0 @@ -5024,7 +5024,7 @@ void test_vst2_lane_p8(poly8_t *a, poly8x8x2_t b) { vst2_lane_p8(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst2_lane_p16(i16* noundef %a, [2 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2_lane_p16(i16* %a, [2 x <4 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly16x4x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x4x2_t, %struct.poly16x4x2_t* [[B]], i32 0, i32 0 @@ -5049,7 +5049,7 @@ void test_vst2_lane_p16(poly16_t *a, poly16x4x2_t b) { vst2_lane_p16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst2_lane_p64(i64* noundef %a, [2 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2_lane_p64(i64* %a, [2 x <1 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly64x1x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x1x2_t, %struct.poly64x1x2_t* [[B]], i32 0, i32 0 @@ -5074,7 +5074,7 @@ void test_vst2_lane_p64(poly64_t *a, poly64x1x2_t b) { vst2_lane_p64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_u8(i8* noundef %a, [3 x <16 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_u8(i8* %a, [3 x <16 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint8x16x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x3_t, %struct.uint8x16x3_t* [[B]], i32 0, i32 0 @@ -5097,7 +5097,7 @@ void test_vst3q_lane_u8(uint8_t *a, uint8x16x3_t b) { vst3q_lane_u8(a, b, 15); } -// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_u16(i16* noundef %a, [3 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_u16(i16* %a, [3 x <8 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint16x8x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x8x3_t, %struct.uint16x8x3_t* [[B]], i32 0, i32 0 @@ -5127,7 +5127,7 @@ void test_vst3q_lane_u16(uint16_t *a, uint16x8x3_t b) { vst3q_lane_u16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_u32(i32* noundef %a, [3 x <4 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_u32(i32* %a, [3 x <4 x i32>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint32x4x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x4x3_t, %struct.uint32x4x3_t* [[B]], i32 0, i32 0 @@ -5157,7 +5157,7 @@ void test_vst3q_lane_u32(uint32_t *a, uint32x4x3_t b) { vst3q_lane_u32(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_u64(i64* noundef %a, [3 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_u64(i64* %a, [3 x <2 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint64x2x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint64x2x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint64x2x3_t, %struct.uint64x2x3_t* [[B]], i32 0, i32 0 @@ -5187,7 +5187,7 @@ void test_vst3q_lane_u64(uint64_t *a, uint64x2x3_t b) { vst3q_lane_u64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_s8(i8* noundef %a, [3 x <16 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_s8(i8* %a, [3 x <16 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int8x16x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x3_t, %struct.int8x16x3_t* [[B]], i32 0, i32 0 @@ -5210,7 +5210,7 @@ void test_vst3q_lane_s8(int8_t *a, int8x16x3_t b) { vst3q_lane_s8(a, b, 15); } -// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_s16(i16* noundef %a, [3 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_s16(i16* %a, [3 x <8 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int16x8x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int16x8x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x8x3_t, %struct.int16x8x3_t* [[B]], i32 0, i32 0 @@ -5240,7 +5240,7 @@ void test_vst3q_lane_s16(int16_t *a, int16x8x3_t b) { vst3q_lane_s16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_s32(i32* noundef %a, [3 x <4 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_s32(i32* %a, [3 x <4 x i32>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int32x4x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int32x4x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x4x3_t, %struct.int32x4x3_t* [[B]], i32 0, i32 0 @@ -5270,7 +5270,7 @@ void test_vst3q_lane_s32(int32_t *a, int32x4x3_t b) { vst3q_lane_s32(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_s64(i64* noundef %a, [3 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_s64(i64* %a, [3 x <2 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int64x2x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int64x2x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int64x2x3_t, %struct.int64x2x3_t* [[B]], i32 0, i32 0 @@ -5300,7 +5300,7 @@ void test_vst3q_lane_s64(int64_t *a, int64x2x3_t b) { vst3q_lane_s64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_f16(half* noundef %a, [3 x <8 x half>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_f16(half* %a, [3 x <8 x half>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float16x8x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float16x8x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x8x3_t, %struct.float16x8x3_t* [[B]], i32 0, i32 0 @@ -5330,7 +5330,7 @@ void test_vst3q_lane_f16(float16_t *a, float16x8x3_t b) { vst3q_lane_f16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_f32(float* noundef %a, [3 x <4 x float>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_f32(float* %a, [3 x <4 x float>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float32x4x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float32x4x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x4x3_t, %struct.float32x4x3_t* [[B]], i32 0, i32 0 @@ -5360,7 +5360,7 @@ void test_vst3q_lane_f32(float32_t *a, float32x4x3_t b) { vst3q_lane_f32(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_f64(double* noundef %a, [3 x <2 x double>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_f64(double* %a, [3 x <2 x double>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float64x2x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float64x2x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float64x2x3_t, %struct.float64x2x3_t* [[B]], i32 0, i32 0 @@ -5390,7 +5390,7 @@ void test_vst3q_lane_f64(float64_t *a, float64x2x3_t b) { vst3q_lane_f64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_p8(i8* noundef %a, [3 x <16 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_p8(i8* %a, [3 x <16 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly8x16x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x3_t, %struct.poly8x16x3_t* [[B]], i32 0, i32 0 @@ -5413,7 +5413,7 @@ void test_vst3q_lane_p8(poly8_t *a, poly8x16x3_t b) { vst3q_lane_p8(a, b, 15); } -// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_p16(i16* noundef %a, [3 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_p16(i16* %a, [3 x <8 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly16x8x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x8x3_t, %struct.poly16x8x3_t* [[B]], i32 0, i32 0 @@ -5443,7 +5443,7 @@ void test_vst3q_lane_p16(poly16_t *a, poly16x8x3_t b) { vst3q_lane_p16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_p64(i64* noundef %a, [3 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3q_lane_p64(i64* %a, [3 x <2 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly64x2x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x2x3_t, %struct.poly64x2x3_t* [[B]], i32 0, i32 0 @@ -5473,7 +5473,7 @@ void test_vst3q_lane_p64(poly64_t *a, poly64x2x3_t b) { vst3q_lane_p64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst3_lane_u8(i8* noundef %a, [3 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3_lane_u8(i8* %a, [3 x <8 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint8x8x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x3_t, %struct.uint8x8x3_t* [[B]], i32 0, i32 0 @@ -5496,7 +5496,7 @@ void test_vst3_lane_u8(uint8_t *a, uint8x8x3_t b) { vst3_lane_u8(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst3_lane_u16(i16* noundef %a, [3 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3_lane_u16(i16* %a, [3 x <4 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint16x4x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x4x3_t, %struct.uint16x4x3_t* [[B]], i32 0, i32 0 @@ -5526,7 +5526,7 @@ void test_vst3_lane_u16(uint16_t *a, uint16x4x3_t b) { vst3_lane_u16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst3_lane_u32(i32* noundef %a, [3 x <2 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3_lane_u32(i32* %a, [3 x <2 x i32>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint32x2x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x2x3_t, %struct.uint32x2x3_t* [[B]], i32 0, i32 0 @@ -5556,7 +5556,7 @@ void test_vst3_lane_u32(uint32_t *a, uint32x2x3_t b) { vst3_lane_u32(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst3_lane_u64(i64* noundef %a, [3 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3_lane_u64(i64* %a, [3 x <1 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint64x1x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint64x1x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint64x1x3_t, %struct.uint64x1x3_t* [[B]], i32 0, i32 0 @@ -5586,7 +5586,7 @@ void test_vst3_lane_u64(uint64_t *a, uint64x1x3_t b) { vst3_lane_u64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst3_lane_s8(i8* noundef %a, [3 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3_lane_s8(i8* %a, [3 x <8 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int8x8x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int8x8x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x3_t, %struct.int8x8x3_t* [[B]], i32 0, i32 0 @@ -5609,7 +5609,7 @@ void test_vst3_lane_s8(int8_t *a, int8x8x3_t b) { vst3_lane_s8(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst3_lane_s16(i16* noundef %a, [3 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3_lane_s16(i16* %a, [3 x <4 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int16x4x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int16x4x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x4x3_t, %struct.int16x4x3_t* [[B]], i32 0, i32 0 @@ -5639,7 +5639,7 @@ void test_vst3_lane_s16(int16_t *a, int16x4x3_t b) { vst3_lane_s16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst3_lane_s32(i32* noundef %a, [3 x <2 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3_lane_s32(i32* %a, [3 x <2 x i32>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int32x2x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int32x2x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x2x3_t, %struct.int32x2x3_t* [[B]], i32 0, i32 0 @@ -5669,7 +5669,7 @@ void test_vst3_lane_s32(int32_t *a, int32x2x3_t b) { vst3_lane_s32(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst3_lane_s64(i64* noundef %a, [3 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3_lane_s64(i64* %a, [3 x <1 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int64x1x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int64x1x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int64x1x3_t, %struct.int64x1x3_t* [[B]], i32 0, i32 0 @@ -5699,7 +5699,7 @@ void test_vst3_lane_s64(int64_t *a, int64x1x3_t b) { vst3_lane_s64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst3_lane_f16(half* noundef %a, [3 x <4 x half>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3_lane_f16(half* %a, [3 x <4 x half>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float16x4x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float16x4x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x4x3_t, %struct.float16x4x3_t* [[B]], i32 0, i32 0 @@ -5729,7 +5729,7 @@ void test_vst3_lane_f16(float16_t *a, float16x4x3_t b) { vst3_lane_f16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst3_lane_f32(float* noundef %a, [3 x <2 x float>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3_lane_f32(float* %a, [3 x <2 x float>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float32x2x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float32x2x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x2x3_t, %struct.float32x2x3_t* [[B]], i32 0, i32 0 @@ -5759,7 +5759,7 @@ void test_vst3_lane_f32(float32_t *a, float32x2x3_t b) { vst3_lane_f32(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst3_lane_f64(double* noundef %a, [3 x <1 x double>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3_lane_f64(double* %a, [3 x <1 x double>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float64x1x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float64x1x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float64x1x3_t, %struct.float64x1x3_t* [[B]], i32 0, i32 0 @@ -5789,7 +5789,7 @@ void test_vst3_lane_f64(float64_t *a, float64x1x3_t b) { vst3_lane_f64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst3_lane_p8(i8* noundef %a, [3 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3_lane_p8(i8* %a, [3 x <8 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly8x8x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x3_t, %struct.poly8x8x3_t* [[B]], i32 0, i32 0 @@ -5812,7 +5812,7 @@ void test_vst3_lane_p8(poly8_t *a, poly8x8x3_t b) { vst3_lane_p8(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst3_lane_p16(i16* noundef %a, [3 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3_lane_p16(i16* %a, [3 x <4 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly16x4x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x4x3_t, %struct.poly16x4x3_t* [[B]], i32 0, i32 0 @@ -5842,7 +5842,7 @@ void test_vst3_lane_p16(poly16_t *a, poly16x4x3_t b) { vst3_lane_p16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst3_lane_p64(i64* noundef %a, [3 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3_lane_p64(i64* %a, [3 x <1 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly64x1x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x1x3_t, %struct.poly64x1x3_t* [[B]], i32 0, i32 0 @@ -5872,7 +5872,7 @@ void test_vst3_lane_p64(poly64_t *a, poly64x1x3_t b) { vst3_lane_p64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_u8(i8* noundef %a, [4 x <16 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_u8(i8* %a, [4 x <16 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint8x16x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x4_t, %struct.uint8x16x4_t* [[B]], i32 0, i32 0 @@ -5898,7 +5898,7 @@ void test_vst4q_lane_u8(uint8_t *a, uint8x16x4_t b) { vst4q_lane_u8(a, b, 15); } -// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_u16(i16* noundef %a, [4 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_u16(i16* %a, [4 x <8 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint16x8x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x8x4_t, %struct.uint16x8x4_t* [[B]], i32 0, i32 0 @@ -5933,7 +5933,7 @@ void test_vst4q_lane_u16(uint16_t *a, uint16x8x4_t b) { vst4q_lane_u16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_u32(i32* noundef %a, [4 x <4 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_u32(i32* %a, [4 x <4 x i32>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint32x4x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x4x4_t, %struct.uint32x4x4_t* [[B]], i32 0, i32 0 @@ -5968,7 +5968,7 @@ void test_vst4q_lane_u32(uint32_t *a, uint32x4x4_t b) { vst4q_lane_u32(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_u64(i64* noundef %a, [4 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_u64(i64* %a, [4 x <2 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint64x2x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.uint64x2x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint64x2x4_t, %struct.uint64x2x4_t* [[B]], i32 0, i32 0 @@ -6003,7 +6003,7 @@ void test_vst4q_lane_u64(uint64_t *a, uint64x2x4_t b) { vst4q_lane_u64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_s8(i8* noundef %a, [4 x <16 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_s8(i8* %a, [4 x <16 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int8x16x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x4_t, %struct.int8x16x4_t* [[B]], i32 0, i32 0 @@ -6029,7 +6029,7 @@ void test_vst4q_lane_s8(int8_t *a, int8x16x4_t b) { vst4q_lane_s8(a, b, 15); } -// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_s16(i16* noundef %a, [4 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_s16(i16* %a, [4 x <8 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int16x8x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int16x8x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x8x4_t, %struct.int16x8x4_t* [[B]], i32 0, i32 0 @@ -6064,7 +6064,7 @@ void test_vst4q_lane_s16(int16_t *a, int16x8x4_t b) { vst4q_lane_s16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_s32(i32* noundef %a, [4 x <4 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_s32(i32* %a, [4 x <4 x i32>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int32x4x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int32x4x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x4x4_t, %struct.int32x4x4_t* [[B]], i32 0, i32 0 @@ -6099,7 +6099,7 @@ void test_vst4q_lane_s32(int32_t *a, int32x4x4_t b) { vst4q_lane_s32(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_s64(i64* noundef %a, [4 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_s64(i64* %a, [4 x <2 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int64x2x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.int64x2x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int64x2x4_t, %struct.int64x2x4_t* [[B]], i32 0, i32 0 @@ -6134,7 +6134,7 @@ void test_vst4q_lane_s64(int64_t *a, int64x2x4_t b) { vst4q_lane_s64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_f16(half* noundef %a, [4 x <8 x half>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_f16(half* %a, [4 x <8 x half>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float16x8x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float16x8x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x8x4_t, %struct.float16x8x4_t* [[B]], i32 0, i32 0 @@ -6169,7 +6169,7 @@ void test_vst4q_lane_f16(float16_t *a, float16x8x4_t b) { vst4q_lane_f16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_f32(float* noundef %a, [4 x <4 x float>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_f32(float* %a, [4 x <4 x float>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float32x4x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float32x4x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x4x4_t, %struct.float32x4x4_t* [[B]], i32 0, i32 0 @@ -6204,7 +6204,7 @@ void test_vst4q_lane_f32(float32_t *a, float32x4x4_t b) { vst4q_lane_f32(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_f64(double* noundef %a, [4 x <2 x double>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_f64(double* %a, [4 x <2 x double>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float64x2x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.float64x2x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float64x2x4_t, %struct.float64x2x4_t* [[B]], i32 0, i32 0 @@ -6239,7 +6239,7 @@ void test_vst4q_lane_f64(float64_t *a, float64x2x4_t b) { vst4q_lane_f64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_p8(i8* noundef %a, [4 x <16 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_p8(i8* %a, [4 x <16 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly8x16x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x4_t, %struct.poly8x16x4_t* [[B]], i32 0, i32 0 @@ -6265,7 +6265,7 @@ void test_vst4q_lane_p8(poly8_t *a, poly8x16x4_t b) { vst4q_lane_p8(a, b, 15); } -// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_p16(i16* noundef %a, [4 x <8 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_p16(i16* %a, [4 x <8 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly16x8x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x8x4_t, %struct.poly16x8x4_t* [[B]], i32 0, i32 0 @@ -6300,7 +6300,7 @@ void test_vst4q_lane_p16(poly16_t *a, poly16x8x4_t b) { vst4q_lane_p16(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_p64(i64* noundef %a, [4 x <2 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4q_lane_p64(i64* %a, [4 x <2 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly64x2x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x2x4_t, %struct.poly64x2x4_t* [[B]], i32 0, i32 0 @@ -6335,7 +6335,7 @@ void test_vst4q_lane_p64(poly64_t *a, poly64x2x4_t b) { vst4q_lane_p64(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst4_lane_u8(i8* noundef %a, [4 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4_lane_u8(i8* %a, [4 x <8 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint8x8x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x4_t, %struct.uint8x8x4_t* [[B]], i32 0, i32 0 @@ -6361,7 +6361,7 @@ void test_vst4_lane_u8(uint8_t *a, uint8x8x4_t b) { vst4_lane_u8(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst4_lane_u16(i16* noundef %a, [4 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4_lane_u16(i16* %a, [4 x <4 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint16x4x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x4x4_t, %struct.uint16x4x4_t* [[B]], i32 0, i32 0 @@ -6396,7 +6396,7 @@ void test_vst4_lane_u16(uint16_t *a, uint16x4x4_t b) { vst4_lane_u16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst4_lane_u32(i32* noundef %a, [4 x <2 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4_lane_u32(i32* %a, [4 x <2 x i32>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint32x2x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x2x4_t, %struct.uint32x2x4_t* [[B]], i32 0, i32 0 @@ -6431,7 +6431,7 @@ void test_vst4_lane_u32(uint32_t *a, uint32x2x4_t b) { vst4_lane_u32(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst4_lane_u64(i64* noundef %a, [4 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4_lane_u64(i64* %a, [4 x <1 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.uint64x1x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.uint64x1x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint64x1x4_t, %struct.uint64x1x4_t* [[B]], i32 0, i32 0 @@ -6466,7 +6466,7 @@ void test_vst4_lane_u64(uint64_t *a, uint64x1x4_t b) { vst4_lane_u64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst4_lane_s8(i8* noundef %a, [4 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4_lane_s8(i8* %a, [4 x <8 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int8x8x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int8x8x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x4_t, %struct.int8x8x4_t* [[B]], i32 0, i32 0 @@ -6492,7 +6492,7 @@ void test_vst4_lane_s8(int8_t *a, int8x8x4_t b) { vst4_lane_s8(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst4_lane_s16(i16* noundef %a, [4 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4_lane_s16(i16* %a, [4 x <4 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int16x4x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int16x4x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x4x4_t, %struct.int16x4x4_t* [[B]], i32 0, i32 0 @@ -6527,7 +6527,7 @@ void test_vst4_lane_s16(int16_t *a, int16x4x4_t b) { vst4_lane_s16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst4_lane_s32(i32* noundef %a, [4 x <2 x i32>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4_lane_s32(i32* %a, [4 x <2 x i32>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int32x2x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int32x2x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x2x4_t, %struct.int32x2x4_t* [[B]], i32 0, i32 0 @@ -6562,7 +6562,7 @@ void test_vst4_lane_s32(int32_t *a, int32x2x4_t b) { vst4_lane_s32(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst4_lane_s64(i64* noundef %a, [4 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4_lane_s64(i64* %a, [4 x <1 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.int64x1x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.int64x1x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int64x1x4_t, %struct.int64x1x4_t* [[B]], i32 0, i32 0 @@ -6597,7 +6597,7 @@ void test_vst4_lane_s64(int64_t *a, int64x1x4_t b) { vst4_lane_s64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst4_lane_f16(half* noundef %a, [4 x <4 x half>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4_lane_f16(half* %a, [4 x <4 x half>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float16x4x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float16x4x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x4x4_t, %struct.float16x4x4_t* [[B]], i32 0, i32 0 @@ -6632,7 +6632,7 @@ void test_vst4_lane_f16(float16_t *a, float16x4x4_t b) { vst4_lane_f16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst4_lane_f32(float* noundef %a, [4 x <2 x float>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4_lane_f32(float* %a, [4 x <2 x float>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float32x2x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float32x2x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x2x4_t, %struct.float32x2x4_t* [[B]], i32 0, i32 0 @@ -6667,7 +6667,7 @@ void test_vst4_lane_f32(float32_t *a, float32x2x4_t b) { vst4_lane_f32(a, b, 1); } -// CHECK-LABEL: define{{.*}} void @test_vst4_lane_f64(double* noundef %a, [4 x <1 x double>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4_lane_f64(double* %a, [4 x <1 x double>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.float64x1x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.float64x1x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float64x1x4_t, %struct.float64x1x4_t* [[B]], i32 0, i32 0 @@ -6702,7 +6702,7 @@ void test_vst4_lane_f64(float64_t *a, float64x1x4_t b) { vst4_lane_f64(a, b, 0); } -// CHECK-LABEL: define{{.*}} void @test_vst4_lane_p8(i8* noundef %a, [4 x <8 x i8>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4_lane_p8(i8* %a, [4 x <8 x i8>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly8x8x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x4_t, %struct.poly8x8x4_t* [[B]], i32 0, i32 0 @@ -6728,7 +6728,7 @@ void test_vst4_lane_p8(poly8_t *a, poly8x8x4_t b) { vst4_lane_p8(a, b, 7); } -// CHECK-LABEL: define{{.*}} void @test_vst4_lane_p16(i16* noundef %a, [4 x <4 x i16>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4_lane_p16(i16* %a, [4 x <4 x i16>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly16x4x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x4x4_t, %struct.poly16x4x4_t* [[B]], i32 0, i32 0 @@ -6763,7 +6763,7 @@ void test_vst4_lane_p16(poly16_t *a, poly16x4x4_t b) { vst4_lane_p16(a, b, 3); } -// CHECK-LABEL: define{{.*}} void @test_vst4_lane_p64(i64* noundef %a, [4 x <1 x i64>] %b.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4_lane_p64(i64* %a, [4 x <1 x i64>] %b.coerce) #2 { // CHECK: [[B:%.*]] = alloca %struct.poly64x1x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x1x4_t, %struct.poly64x1x4_t* [[B]], i32 0, i32 0 diff --git a/clang/test/CodeGen/aarch64-neon-scalar-copy.c b/clang/test/CodeGen/aarch64-neon-scalar-copy.c index 71a8259ba0e4f0ac6280b30ba365e37aa5f449c1..2d74cace185ced3a8b65b668572a5620dfaffa20 100644 --- a/clang/test/CodeGen/aarch64-neon-scalar-copy.c +++ b/clang/test/CodeGen/aarch64-neon-scalar-copy.c @@ -3,7 +3,7 @@ #include -// CHECK-LABEL: define{{.*}} float @test_vdups_lane_f32(<2 x float> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} float @test_vdups_lane_f32(<2 x float> %a) #0 { // CHECK: [[VDUPS_LANE:%.*]] = extractelement <2 x float> %a, i32 1 // CHECK: ret float [[VDUPS_LANE]] float32_t test_vdups_lane_f32(float32x2_t a) { @@ -11,7 +11,7 @@ float32_t test_vdups_lane_f32(float32x2_t a) { } -// CHECK-LABEL: define{{.*}} double @test_vdupd_lane_f64(<1 x double> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} double @test_vdupd_lane_f64(<1 x double> %a) #0 { // CHECK: [[VDUPD_LANE:%.*]] = extractelement <1 x double> %a, i32 0 // CHECK: ret double [[VDUPD_LANE]] float64_t test_vdupd_lane_f64(float64x1_t a) { @@ -19,7 +19,7 @@ float64_t test_vdupd_lane_f64(float64x1_t a) { } -// CHECK-LABEL: define{{.*}} float @test_vdups_laneq_f32(<4 x float> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} float @test_vdups_laneq_f32(<4 x float> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x float> %a, i32 3 // CHECK: ret float [[VGETQ_LANE]] float32_t test_vdups_laneq_f32(float32x4_t a) { @@ -27,7 +27,7 @@ float32_t test_vdups_laneq_f32(float32x4_t a) { } -// CHECK-LABEL: define{{.*}} double @test_vdupd_laneq_f64(<2 x double> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} double @test_vdupd_laneq_f64(<2 x double> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x double> %a, i32 1 // CHECK: ret double [[VGETQ_LANE]] float64_t test_vdupd_laneq_f64(float64x2_t a) { @@ -35,7 +35,7 @@ float64_t test_vdupd_laneq_f64(float64x2_t a) { } -// CHECK-LABEL: define{{.*}} i8 @test_vdupb_lane_s8(<8 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i8 @test_vdupb_lane_s8(<8 x i8> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7 // CHECK: ret i8 [[VGET_LANE]] int8_t test_vdupb_lane_s8(int8x8_t a) { @@ -43,7 +43,7 @@ int8_t test_vdupb_lane_s8(int8x8_t a) { } -// CHECK-LABEL: define{{.*}} i16 @test_vduph_lane_s16(<4 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vduph_lane_s16(<4 x i16> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3 // CHECK: ret i16 [[VGET_LANE]] int16_t test_vduph_lane_s16(int16x4_t a) { @@ -51,7 +51,7 @@ int16_t test_vduph_lane_s16(int16x4_t a) { } -// CHECK-LABEL: define{{.*}} i32 @test_vdups_lane_s32(<2 x i32> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vdups_lane_s32(<2 x i32> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %a, i32 1 // CHECK: ret i32 [[VGET_LANE]] int32_t test_vdups_lane_s32(int32x2_t a) { @@ -59,7 +59,7 @@ int32_t test_vdups_lane_s32(int32x2_t a) { } -// CHECK-LABEL: define{{.*}} i64 @test_vdupd_lane_s64(<1 x i64> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vdupd_lane_s64(<1 x i64> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %a, i32 0 // CHECK: ret i64 [[VGET_LANE]] int64_t test_vdupd_lane_s64(int64x1_t a) { @@ -67,7 +67,7 @@ int64_t test_vdupd_lane_s64(int64x1_t a) { } -// CHECK-LABEL: define{{.*}} i8 @test_vdupb_lane_u8(<8 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i8 @test_vdupb_lane_u8(<8 x i8> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7 // CHECK: ret i8 [[VGET_LANE]] uint8_t test_vdupb_lane_u8(uint8x8_t a) { @@ -75,7 +75,7 @@ uint8_t test_vdupb_lane_u8(uint8x8_t a) { } -// CHECK-LABEL: define{{.*}} i16 @test_vduph_lane_u16(<4 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vduph_lane_u16(<4 x i16> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3 // CHECK: ret i16 [[VGET_LANE]] uint16_t test_vduph_lane_u16(uint16x4_t a) { @@ -83,7 +83,7 @@ uint16_t test_vduph_lane_u16(uint16x4_t a) { } -// CHECK-LABEL: define{{.*}} i32 @test_vdups_lane_u32(<2 x i32> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vdups_lane_u32(<2 x i32> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %a, i32 1 // CHECK: ret i32 [[VGET_LANE]] uint32_t test_vdups_lane_u32(uint32x2_t a) { @@ -91,14 +91,14 @@ uint32_t test_vdups_lane_u32(uint32x2_t a) { } -// CHECK-LABEL: define{{.*}} i64 @test_vdupd_lane_u64(<1 x i64> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vdupd_lane_u64(<1 x i64> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %a, i32 0 // CHECK: ret i64 [[VGET_LANE]] uint64_t test_vdupd_lane_u64(uint64x1_t a) { return vdupd_lane_u64(a, 0); } -// CHECK-LABEL: define{{.*}} i8 @test_vdupb_laneq_s8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i8 @test_vdupb_laneq_s8(<16 x i8> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15 // CHECK: ret i8 [[VGETQ_LANE]] int8_t test_vdupb_laneq_s8(int8x16_t a) { @@ -106,7 +106,7 @@ int8_t test_vdupb_laneq_s8(int8x16_t a) { } -// CHECK-LABEL: define{{.*}} i16 @test_vduph_laneq_s16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vduph_laneq_s16(<8 x i16> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7 // CHECK: ret i16 [[VGETQ_LANE]] int16_t test_vduph_laneq_s16(int16x8_t a) { @@ -114,7 +114,7 @@ int16_t test_vduph_laneq_s16(int16x8_t a) { } -// CHECK-LABEL: define{{.*}} i32 @test_vdups_laneq_s32(<4 x i32> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vdups_laneq_s32(<4 x i32> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a, i32 3 // CHECK: ret i32 [[VGETQ_LANE]] int32_t test_vdups_laneq_s32(int32x4_t a) { @@ -122,7 +122,7 @@ int32_t test_vdups_laneq_s32(int32x4_t a) { } -// CHECK-LABEL: define{{.*}} i64 @test_vdupd_laneq_s64(<2 x i64> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i64 @test_vdupd_laneq_s64(<2 x i64> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a, i32 1 // CHECK: ret i64 [[VGETQ_LANE]] int64_t test_vdupd_laneq_s64(int64x2_t a) { @@ -130,7 +130,7 @@ int64_t test_vdupd_laneq_s64(int64x2_t a) { } -// CHECK-LABEL: define{{.*}} i8 @test_vdupb_laneq_u8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i8 @test_vdupb_laneq_u8(<16 x i8> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15 // CHECK: ret i8 [[VGETQ_LANE]] uint8_t test_vdupb_laneq_u8(uint8x16_t a) { @@ -138,7 +138,7 @@ uint8_t test_vdupb_laneq_u8(uint8x16_t a) { } -// CHECK-LABEL: define{{.*}} i16 @test_vduph_laneq_u16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vduph_laneq_u16(<8 x i16> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7 // CHECK: ret i16 [[VGETQ_LANE]] uint16_t test_vduph_laneq_u16(uint16x8_t a) { @@ -146,7 +146,7 @@ uint16_t test_vduph_laneq_u16(uint16x8_t a) { } -// CHECK-LABEL: define{{.*}} i32 @test_vdups_laneq_u32(<4 x i32> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vdups_laneq_u32(<4 x i32> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a, i32 3 // CHECK: ret i32 [[VGETQ_LANE]] uint32_t test_vdups_laneq_u32(uint32x4_t a) { @@ -154,35 +154,35 @@ uint32_t test_vdups_laneq_u32(uint32x4_t a) { } -// CHECK-LABEL: define{{.*}} i64 @test_vdupd_laneq_u64(<2 x i64> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i64 @test_vdupd_laneq_u64(<2 x i64> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a, i32 1 // CHECK: ret i64 [[VGETQ_LANE]] uint64_t test_vdupd_laneq_u64(uint64x2_t a) { return vdupd_laneq_u64(a, 1); } -// CHECK-LABEL: define{{.*}} i8 @test_vdupb_lane_p8(<8 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i8 @test_vdupb_lane_p8(<8 x i8> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7 // CHECK: ret i8 [[VGET_LANE]] poly8_t test_vdupb_lane_p8(poly8x8_t a) { return vdupb_lane_p8(a, 7); } -// CHECK-LABEL: define{{.*}} i16 @test_vduph_lane_p16(<4 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vduph_lane_p16(<4 x i16> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3 // CHECK: ret i16 [[VGET_LANE]] poly16_t test_vduph_lane_p16(poly16x4_t a) { return vduph_lane_p16(a, 3); } -// CHECK-LABEL: define{{.*}} i8 @test_vdupb_laneq_p8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i8 @test_vdupb_laneq_p8(<16 x i8> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15 // CHECK: ret i8 [[VGETQ_LANE]] poly8_t test_vdupb_laneq_p8(poly8x16_t a) { return vdupb_laneq_p8(a, 15); } -// CHECK-LABEL: define{{.*}} i16 @test_vduph_laneq_p16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vduph_laneq_p16(<8 x i16> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7 // CHECK: ret i16 [[VGETQ_LANE]] poly16_t test_vduph_laneq_p16(poly16x8_t a) { diff --git a/clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c b/clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c index fd6ad5ba96c12c9ce905f23236f90434620ecfae..367978d84af41c91a94eaf44cd0c8bed7ee5a77c 100644 --- a/clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c +++ b/clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c @@ -6,7 +6,7 @@ #include -// CHECK-LABEL: define{{.*}} float @test_vmuls_lane_f32(float noundef %a, <2 x float> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} float @test_vmuls_lane_f32(float %a, <2 x float> %b) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <2 x float> %b, i32 1 // CHECK: [[MUL:%.*]] = fmul float %a, [[VGET_LANE]] // CHECK: ret float [[MUL]] @@ -14,7 +14,7 @@ float32_t test_vmuls_lane_f32(float32_t a, float32x2_t b) { return vmuls_lane_f32(a, b, 1); } -// CHECK-LABEL: define{{.*}} double @test_vmuld_lane_f64(double noundef %a, <1 x double> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} double @test_vmuld_lane_f64(double %a, <1 x double> %b) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <1 x double> %b, i32 0 // CHECK: [[MUL:%.*]] = fmul double %a, [[VGET_LANE]] // CHECK: ret double [[MUL]] @@ -22,7 +22,7 @@ float64_t test_vmuld_lane_f64(float64_t a, float64x1_t b) { return vmuld_lane_f64(a, b, 0); } -// CHECK-LABEL: define{{.*}} float @test_vmuls_laneq_f32(float noundef %a, <4 x float> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} float @test_vmuls_laneq_f32(float %a, <4 x float> %b) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x float> %b, i32 3 // CHECK: [[MUL:%.*]] = fmul float %a, [[VGETQ_LANE]] // CHECK: ret float [[MUL]] @@ -30,7 +30,7 @@ float32_t test_vmuls_laneq_f32(float32_t a, float32x4_t b) { return vmuls_laneq_f32(a, b, 3); } -// CHECK-LABEL: define{{.*}} double @test_vmuld_laneq_f64(double noundef %a, <2 x double> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} double @test_vmuld_laneq_f64(double %a, <2 x double> %b) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x double> %b, i32 1 // CHECK: [[MUL:%.*]] = fmul double %a, [[VGETQ_LANE]] // CHECK: ret double [[MUL]] @@ -38,7 +38,7 @@ float64_t test_vmuld_laneq_f64(float64_t a, float64x2_t b) { return vmuld_laneq_f64(a, b, 1); } -// CHECK-LABEL: define{{.*}} <1 x double> @test_vmul_n_f64(<1 x double> noundef %a, double noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x double> @test_vmul_n_f64(<1 x double> %a, double %b) #0 { // CHECK: [[TMP2:%.*]] = bitcast <1 x double> %a to double // CHECK: [[TMP3:%.*]] = fmul double [[TMP2]], %b // CHECK: [[TMP4:%.*]] = bitcast double [[TMP3]] to <1 x double> @@ -47,7 +47,7 @@ float64x1_t test_vmul_n_f64(float64x1_t a, float64_t b) { return vmul_n_f64(a, b); } -// CHECK-LABEL: define{{.*}} float @test_vmulxs_lane_f32(float noundef %a, <2 x float> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} float @test_vmulxs_lane_f32(float %a, <2 x float> %b) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <2 x float> %b, i32 1 // CHECK: [[VMULXS_F32_I:%.*]] = call float @llvm.aarch64.neon.fmulx.f32(float %a, float [[VGET_LANE]]) // CHECK: ret float [[VMULXS_F32_I]] @@ -55,7 +55,7 @@ float32_t test_vmulxs_lane_f32(float32_t a, float32x2_t b) { return vmulxs_lane_f32(a, b, 1); } -// CHECK-LABEL: define{{.*}} float @test_vmulxs_laneq_f32(float noundef %a, <4 x float> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} float @test_vmulxs_laneq_f32(float %a, <4 x float> %b) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x float> %b, i32 3 // CHECK: [[VMULXS_F32_I:%.*]] = call float @llvm.aarch64.neon.fmulx.f32(float %a, float [[VGETQ_LANE]]) // CHECK: ret float [[VMULXS_F32_I]] @@ -63,7 +63,7 @@ float32_t test_vmulxs_laneq_f32(float32_t a, float32x4_t b) { return vmulxs_laneq_f32(a, b, 3); } -// CHECK-LABEL: define{{.*}} double @test_vmulxd_lane_f64(double noundef %a, <1 x double> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} double @test_vmulxd_lane_f64(double %a, <1 x double> %b) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <1 x double> %b, i32 0 // CHECK: [[VMULXD_F64_I:%.*]] = call double @llvm.aarch64.neon.fmulx.f64(double %a, double [[VGET_LANE]]) // CHECK: ret double [[VMULXD_F64_I]] @@ -71,7 +71,7 @@ float64_t test_vmulxd_lane_f64(float64_t a, float64x1_t b) { return vmulxd_lane_f64(a, b, 0); } -// CHECK-LABEL: define{{.*}} double @test_vmulxd_laneq_f64(double noundef %a, <2 x double> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} double @test_vmulxd_laneq_f64(double %a, <2 x double> %b) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x double> %b, i32 1 // CHECK: [[VMULXD_F64_I:%.*]] = call double @llvm.aarch64.neon.fmulx.f64(double %a, double [[VGETQ_LANE]]) // CHECK: ret double [[VMULXD_F64_I]] @@ -79,7 +79,7 @@ float64_t test_vmulxd_laneq_f64(float64_t a, float64x2_t b) { return vmulxd_laneq_f64(a, b, 1); } -// CHECK-LABEL: define{{.*}} <1 x double> @test_vmulx_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x double> @test_vmulx_lane_f64(<1 x double> %a, <1 x double> %b) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <1 x double> %a, i32 0 // CHECK: [[VGET_LANE6:%.*]] = extractelement <1 x double> %b, i32 0 // CHECK: [[VMULXD_F64_I:%.*]] = call double @llvm.aarch64.neon.fmulx.f64(double [[VGET_LANE]], double [[VGET_LANE6]]) @@ -90,7 +90,7 @@ float64x1_t test_vmulx_lane_f64(float64x1_t a, float64x1_t b) { } -// CHECK-LABEL: define{{.*}} <1 x double> @test_vmulx_laneq_f64_0(<1 x double> noundef %a, <2 x double> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <1 x double> @test_vmulx_laneq_f64_0(<1 x double> %a, <2 x double> %b) #1 { // CHECK: [[VGET_LANE:%.*]] = extractelement <1 x double> %a, i32 0 // CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x double> %b, i32 0 // CHECK: [[VMULXD_F64_I:%.*]] = call double @llvm.aarch64.neon.fmulx.f64(double [[VGET_LANE]], double [[VGETQ_LANE]]) @@ -100,7 +100,7 @@ float64x1_t test_vmulx_laneq_f64_0(float64x1_t a, float64x2_t b) { return vmulx_laneq_f64(a, b, 0); } -// CHECK-LABEL: define{{.*}} <1 x double> @test_vmulx_laneq_f64_1(<1 x double> noundef %a, <2 x double> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <1 x double> @test_vmulx_laneq_f64_1(<1 x double> %a, <2 x double> %b) #1 { // CHECK: [[VGET_LANE:%.*]] = extractelement <1 x double> %a, i32 0 // CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x double> %b, i32 1 // CHECK: [[VMULXD_F64_I:%.*]] = call double @llvm.aarch64.neon.fmulx.f64(double [[VGET_LANE]], double [[VGETQ_LANE]]) @@ -111,7 +111,7 @@ float64x1_t test_vmulx_laneq_f64_1(float64x1_t a, float64x2_t b) { } -// CHECK-LABEL: define{{.*}} float @test_vfmas_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} float @test_vfmas_lane_f32(float %a, float %b, <2 x float> %c) #0 { // CHECK: [[EXTRACT:%.*]] = extractelement <2 x float> %c, i32 1 // CHECK: [[TMP2:%.*]] = call float @llvm.fma.f32(float %b, float [[EXTRACT]], float %a) // CHECK: ret float [[TMP2]] @@ -119,7 +119,7 @@ float32_t test_vfmas_lane_f32(float32_t a, float32_t b, float32x2_t c) { return vfmas_lane_f32(a, b, c, 1); } -// CHECK-LABEL: define{{.*}} double @test_vfmad_lane_f64(double noundef %a, double noundef %b, <1 x double> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} double @test_vfmad_lane_f64(double %a, double %b, <1 x double> %c) #0 { // CHECK: [[EXTRACT:%.*]] = extractelement <1 x double> %c, i32 0 // CHECK: [[TMP2:%.*]] = call double @llvm.fma.f64(double %b, double [[EXTRACT]], double %a) // CHECK: ret double [[TMP2]] @@ -127,7 +127,7 @@ float64_t test_vfmad_lane_f64(float64_t a, float64_t b, float64x1_t c) { return vfmad_lane_f64(a, b, c, 0); } -// CHECK-LABEL: define{{.*}} double @test_vfmad_laneq_f64(double noundef %a, double noundef %b, <2 x double> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} double @test_vfmad_laneq_f64(double %a, double %b, <2 x double> %c) #1 { // CHECK: [[EXTRACT:%.*]] = extractelement <2 x double> %c, i32 1 // CHECK: [[TMP2:%.*]] = call double @llvm.fma.f64(double %b, double [[EXTRACT]], double %a) // CHECK: ret double [[TMP2]] @@ -135,7 +135,7 @@ float64_t test_vfmad_laneq_f64(float64_t a, float64_t b, float64x2_t c) { return vfmad_laneq_f64(a, b, c, 1); } -// CHECK-LABEL: define{{.*}} float @test_vfmss_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} float @test_vfmss_lane_f32(float %a, float %b, <2 x float> %c) #0 { // CHECK: [[SUB:%.*]] = fneg float %b // CHECK: [[EXTRACT:%.*]] = extractelement <2 x float> %c, i32 1 // CHECK: [[TMP2:%.*]] = call float @llvm.fma.f32(float [[SUB]], float [[EXTRACT]], float %a) @@ -144,7 +144,7 @@ float32_t test_vfmss_lane_f32(float32_t a, float32_t b, float32x2_t c) { return vfmss_lane_f32(a, b, c, 1); } -// CHECK-LABEL: define{{.*}} <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 { +// CHECK-LABEL: define{{.*}} <1 x double> @test_vfma_lane_f64(<1 x double> %a, <1 x double> %b, <1 x double> %v) #0 { // CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <1 x double> %v to <8 x i8> @@ -158,7 +158,7 @@ float64x1_t test_vfma_lane_f64(float64x1_t a, float64x1_t b, float64x1_t v) { return vfma_lane_f64(a, b, v, 0); } -// CHECK-LABEL: define{{.*}} <1 x double> @test_vfms_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 { +// CHECK-LABEL: define{{.*}} <1 x double> @test_vfms_lane_f64(<1 x double> %a, <1 x double> %b, <1 x double> %v) #0 { // CHECK: [[SUB:%.*]] = fneg <1 x double> %b // CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <1 x double> [[SUB]] to <8 x i8> @@ -173,7 +173,7 @@ float64x1_t test_vfms_lane_f64(float64x1_t a, float64x1_t b, float64x1_t v) { return vfms_lane_f64(a, b, v, 0); } -// CHECK-LABEL: define{{.*}} <1 x double> @test_vfma_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} <1 x double> @test_vfma_laneq_f64(<1 x double> %a, <1 x double> %b, <2 x double> %v) #1 { // CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <2 x double> %v to <16 x i8> @@ -188,7 +188,7 @@ float64x1_t test_vfma_laneq_f64(float64x1_t a, float64x1_t b, float64x2_t v) { return vfma_laneq_f64(a, b, v, 0); } -// CHECK-LABEL: define{{.*}} <1 x double> @test_vfms_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} <1 x double> @test_vfms_laneq_f64(<1 x double> %a, <1 x double> %b, <2 x double> %v) #1 { // CHECK: [[SUB:%.*]] = fneg <1 x double> %b // CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <1 x double> [[SUB]] to <8 x i8> @@ -204,7 +204,7 @@ float64x1_t test_vfms_laneq_f64(float64x1_t a, float64x1_t b, float64x2_t v) { return vfms_laneq_f64(a, b, v, 0); } -// CHECK-LABEL: define{{.*}} i32 @test_vqdmullh_lane_s16(i16 noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vqdmullh_lane_s16(i16 %a, <4 x i16> %b) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %b, i32 3 // CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %a, i64 0 // CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[VGET_LANE]], i64 0 @@ -215,7 +215,7 @@ int32_t test_vqdmullh_lane_s16(int16_t a, int16x4_t b) { return vqdmullh_lane_s16(a, b, 3); } -// CHECK-LABEL: define{{.*}} i64 @test_vqdmulls_lane_s32(i32 noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vqdmulls_lane_s32(i32 %a, <2 x i32> %b) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %b, i32 1 // CHECK: [[VQDMULLS_S32_I:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %a, i32 [[VGET_LANE]]) // CHECK: ret i64 [[VQDMULLS_S32_I]] @@ -223,7 +223,7 @@ int64_t test_vqdmulls_lane_s32(int32_t a, int32x2_t b) { return vqdmulls_lane_s32(a, b, 1); } -// CHECK-LABEL: define{{.*}} i32 @test_vqdmullh_laneq_s16(i16 noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vqdmullh_laneq_s16(i16 %a, <8 x i16> %b) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %b, i32 7 // CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %a, i64 0 // CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[VGETQ_LANE]], i64 0 @@ -234,7 +234,7 @@ int32_t test_vqdmullh_laneq_s16(int16_t a, int16x8_t b) { return vqdmullh_laneq_s16(a, b, 7); } -// CHECK-LABEL: define{{.*}} i64 @test_vqdmulls_laneq_s32(i32 noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} i64 @test_vqdmulls_laneq_s32(i32 %a, <4 x i32> %b) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %b, i32 3 // CHECK: [[VQDMULLS_S32_I:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %a, i32 [[VGETQ_LANE]]) // CHECK: ret i64 [[VQDMULLS_S32_I]] @@ -242,7 +242,7 @@ int64_t test_vqdmulls_laneq_s32(int32_t a, int32x4_t b) { return vqdmulls_laneq_s32(a, b, 3); } -// CHECK-LABEL: define{{.*}} i16 @test_vqdmulhh_lane_s16(i16 noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vqdmulhh_lane_s16(i16 %a, <4 x i16> %b) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %b, i32 3 // CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %a, i64 0 // CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[VGET_LANE]], i64 0 @@ -253,7 +253,7 @@ int16_t test_vqdmulhh_lane_s16(int16_t a, int16x4_t b) { return vqdmulhh_lane_s16(a, b, 3); } -// CHECK-LABEL: define{{.*}} i32 @test_vqdmulhs_lane_s32(i32 noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vqdmulhs_lane_s32(i32 %a, <2 x i32> %b) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %b, i32 1 // CHECK: [[VQDMULHS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sqdmulh.i32(i32 %a, i32 [[VGET_LANE]]) // CHECK: ret i32 [[VQDMULHS_S32_I]] @@ -262,7 +262,7 @@ int32_t test_vqdmulhs_lane_s32(int32_t a, int32x2_t b) { } -// CHECK-LABEL: define{{.*}} i16 @test_vqdmulhh_laneq_s16(i16 noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vqdmulhh_laneq_s16(i16 %a, <8 x i16> %b) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %b, i32 7 // CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %a, i64 0 // CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[VGETQ_LANE]], i64 0 @@ -274,7 +274,7 @@ int16_t test_vqdmulhh_laneq_s16(int16_t a, int16x8_t b) { } -// CHECK-LABEL: define{{.*}} i32 @test_vqdmulhs_laneq_s32(i32 noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vqdmulhs_laneq_s32(i32 %a, <4 x i32> %b) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %b, i32 3 // CHECK: [[VQDMULHS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sqdmulh.i32(i32 %a, i32 [[VGETQ_LANE]]) // CHECK: ret i32 [[VQDMULHS_S32_I]] @@ -282,7 +282,7 @@ int32_t test_vqdmulhs_laneq_s32(int32_t a, int32x4_t b) { return vqdmulhs_laneq_s32(a, b, 3); } -// CHECK-LABEL: define{{.*}} i16 @test_vqrdmulhh_lane_s16(i16 noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vqrdmulhh_lane_s16(i16 %a, <4 x i16> %b) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %b, i32 3 // CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %a, i64 0 // CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[VGET_LANE]], i64 0 @@ -293,7 +293,7 @@ int16_t test_vqrdmulhh_lane_s16(int16_t a, int16x4_t b) { return vqrdmulhh_lane_s16(a, b, 3); } -// CHECK-LABEL: define{{.*}} i32 @test_vqrdmulhs_lane_s32(i32 noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vqrdmulhs_lane_s32(i32 %a, <2 x i32> %b) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %b, i32 1 // CHECK: [[VQRDMULHS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %a, i32 [[VGET_LANE]]) // CHECK: ret i32 [[VQRDMULHS_S32_I]] @@ -302,7 +302,7 @@ int32_t test_vqrdmulhs_lane_s32(int32_t a, int32x2_t b) { } -// CHECK-LABEL: define{{.*}} i16 @test_vqrdmulhh_laneq_s16(i16 noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vqrdmulhh_laneq_s16(i16 %a, <8 x i16> %b) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %b, i32 7 // CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %a, i64 0 // CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[VGETQ_LANE]], i64 0 @@ -314,7 +314,7 @@ int16_t test_vqrdmulhh_laneq_s16(int16_t a, int16x8_t b) { } -// CHECK-LABEL: define{{.*}} i32 @test_vqrdmulhs_laneq_s32(i32 noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vqrdmulhs_laneq_s32(i32 %a, <4 x i32> %b) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %b, i32 3 // CHECK: [[VQRDMULHS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %a, i32 [[VGETQ_LANE]]) // CHECK: ret i32 [[VQRDMULHS_S32_I]] @@ -322,7 +322,7 @@ int32_t test_vqrdmulhs_laneq_s32(int32_t a, int32x4_t b) { return vqrdmulhs_laneq_s32(a, b, 3); } -// CHECK-LABEL: define{{.*}} i32 @test_vqdmlalh_lane_s16(i32 noundef %a, i16 noundef %b, <4 x i16> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vqdmlalh_lane_s16(i32 %a, i16 %b, <4 x i16> %c) #0 { // CHECK: [[LANE:%.*]] = extractelement <4 x i16> %c, i32 3 // CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %b, i64 0 // CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[LANE]], i64 0 @@ -334,7 +334,7 @@ int32_t test_vqdmlalh_lane_s16(int32_t a, int16_t b, int16x4_t c) { return vqdmlalh_lane_s16(a, b, c, 3); } -// CHECK-LABEL: define{{.*}} i64 @test_vqdmlals_lane_s32(i64 noundef %a, i32 noundef %b, <2 x i32> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vqdmlals_lane_s32(i64 %a, i32 %b, <2 x i32> %c) #0 { // CHECK: [[LANE:%.*]] = extractelement <2 x i32> %c, i32 1 // CHECK: [[VQDMLXL:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %b, i32 [[LANE]]) // CHECK: [[VQDMLXL1:%.*]] = call i64 @llvm.aarch64.neon.sqadd.i64(i64 %a, i64 [[VQDMLXL]]) @@ -343,7 +343,7 @@ int64_t test_vqdmlals_lane_s32(int64_t a, int32_t b, int32x2_t c) { return vqdmlals_lane_s32(a, b, c, 1); } -// CHECK-LABEL: define{{.*}} i32 @test_vqdmlalh_laneq_s16(i32 noundef %a, i16 noundef %b, <8 x i16> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vqdmlalh_laneq_s16(i32 %a, i16 %b, <8 x i16> %c) #1 { // CHECK: [[LANE:%.*]] = extractelement <8 x i16> %c, i32 7 // CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %b, i64 0 // CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[LANE]], i64 0 @@ -355,7 +355,7 @@ int32_t test_vqdmlalh_laneq_s16(int32_t a, int16_t b, int16x8_t c) { return vqdmlalh_laneq_s16(a, b, c, 7); } -// CHECK-LABEL: define{{.*}} i64 @test_vqdmlals_laneq_s32(i64 noundef %a, i32 noundef %b, <4 x i32> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} i64 @test_vqdmlals_laneq_s32(i64 %a, i32 %b, <4 x i32> %c) #1 { // CHECK: [[LANE:%.*]] = extractelement <4 x i32> %c, i32 3 // CHECK: [[VQDMLXL:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %b, i32 [[LANE]]) // CHECK: [[VQDMLXL1:%.*]] = call i64 @llvm.aarch64.neon.sqadd.i64(i64 %a, i64 [[VQDMLXL]]) @@ -364,7 +364,7 @@ int64_t test_vqdmlals_laneq_s32(int64_t a, int32_t b, int32x4_t c) { return vqdmlals_laneq_s32(a, b, c, 3); } -// CHECK-LABEL: define{{.*}} i32 @test_vqdmlslh_lane_s16(i32 noundef %a, i16 noundef %b, <4 x i16> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vqdmlslh_lane_s16(i32 %a, i16 %b, <4 x i16> %c) #0 { // CHECK: [[LANE:%.*]] = extractelement <4 x i16> %c, i32 3 // CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %b, i64 0 // CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[LANE]], i64 0 @@ -376,7 +376,7 @@ int32_t test_vqdmlslh_lane_s16(int32_t a, int16_t b, int16x4_t c) { return vqdmlslh_lane_s16(a, b, c, 3); } -// CHECK-LABEL: define{{.*}} i64 @test_vqdmlsls_lane_s32(i64 noundef %a, i32 noundef %b, <2 x i32> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vqdmlsls_lane_s32(i64 %a, i32 %b, <2 x i32> %c) #0 { // CHECK: [[LANE:%.*]] = extractelement <2 x i32> %c, i32 1 // CHECK: [[VQDMLXL:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %b, i32 [[LANE]]) // CHECK: [[VQDMLXL1:%.*]] = call i64 @llvm.aarch64.neon.sqsub.i64(i64 %a, i64 [[VQDMLXL]]) @@ -385,7 +385,7 @@ int64_t test_vqdmlsls_lane_s32(int64_t a, int32_t b, int32x2_t c) { return vqdmlsls_lane_s32(a, b, c, 1); } -// CHECK-LABEL: define{{.*}} i32 @test_vqdmlslh_laneq_s16(i32 noundef %a, i16 noundef %b, <8 x i16> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vqdmlslh_laneq_s16(i32 %a, i16 %b, <8 x i16> %c) #1 { // CHECK: [[LANE:%.*]] = extractelement <8 x i16> %c, i32 7 // CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %b, i64 0 // CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[LANE]], i64 0 @@ -397,7 +397,7 @@ int32_t test_vqdmlslh_laneq_s16(int32_t a, int16_t b, int16x8_t c) { return vqdmlslh_laneq_s16(a, b, c, 7); } -// CHECK-LABEL: define{{.*}} i64 @test_vqdmlsls_laneq_s32(i64 noundef %a, i32 noundef %b, <4 x i32> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} i64 @test_vqdmlsls_laneq_s32(i64 %a, i32 %b, <4 x i32> %c) #1 { // CHECK: [[LANE:%.*]] = extractelement <4 x i32> %c, i32 3 // CHECK: [[VQDMLXL:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %b, i32 [[LANE]]) // CHECK: [[VQDMLXL1:%.*]] = call i64 @llvm.aarch64.neon.sqsub.i64(i64 %a, i64 [[VQDMLXL]]) diff --git a/clang/test/CodeGen/aarch64-neon-tbl.c b/clang/test/CodeGen/aarch64-neon-tbl.c index 938b1967d378bc35455ea8670687d3753339af4f..c9626c1f5fe03846ddbc01bc6f68ea592a5d016d 100644 --- a/clang/test/CodeGen/aarch64-neon-tbl.c +++ b/clang/test/CodeGen/aarch64-neon-tbl.c @@ -5,7 +5,7 @@ #include -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl1_s8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[VTBL1_I:%.*]] = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <16 x i32> // CHECK: [[VTBL11_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VTBL1_I]], <8 x i8> %b) #3 // CHECK: ret <8 x i8> [[VTBL11_I]] @@ -13,14 +13,14 @@ int8x8_t test_vtbl1_s8(int8x8_t a, int8x8_t b) { return vtbl1_s8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl1_s8(<16 x i8> noundef %a, <8 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl1_s8(<16 x i8> %a, <8 x i8> %b) #1 { // CHECK: [[VTBL1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %a, <8 x i8> %b) #3 // CHECK: ret <8 x i8> [[VTBL1_I]] int8x8_t test_vqtbl1_s8(int8x16_t a, uint8x8_t b) { return vqtbl1_s8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl2_s8([2 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl2_s8([2 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.int8x8x2_t, align 8 // CHECK: [[A:%.*]] = alloca %struct.int8x8x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x2_t, %struct.int8x8x2_t* [[A]], i32 0, i32 0 @@ -42,7 +42,7 @@ int8x8_t test_vtbl2_s8(int8x8x2_t a, int8x8_t b) { return vtbl2_s8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl2_s8([2 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl2_s8([2 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.int8x16x2_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.int8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x2_t, %struct.int8x16x2_t* [[A]], i32 0, i32 0 @@ -63,7 +63,7 @@ int8x8_t test_vqtbl2_s8(int8x16x2_t a, uint8x8_t b) { return vqtbl2_s8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl3_s8([3 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl3_s8([3 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.int8x8x3_t, align 8 // CHECK: [[A:%.*]] = alloca %struct.int8x8x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x3_t, %struct.int8x8x3_t* [[A]], i32 0, i32 0 @@ -89,7 +89,7 @@ int8x8_t test_vtbl3_s8(int8x8x3_t a, int8x8_t b) { return vtbl3_s8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl3_s8([3 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl3_s8([3 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.int8x16x3_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.int8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x3_t, %struct.int8x16x3_t* [[A]], i32 0, i32 0 @@ -113,7 +113,7 @@ int8x8_t test_vqtbl3_s8(int8x16x3_t a, uint8x8_t b) { return vqtbl3_s8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl4_s8([4 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl4_s8([4 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.int8x8x4_t, align 8 // CHECK: [[A:%.*]] = alloca %struct.int8x8x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x4_t, %struct.int8x8x4_t* [[A]], i32 0, i32 0 @@ -142,7 +142,7 @@ int8x8_t test_vtbl4_s8(int8x8x4_t a, int8x8_t b) { return vtbl4_s8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl4_s8([4 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl4_s8([4 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.int8x16x4_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.int8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x4_t, %struct.int8x16x4_t* [[A]], i32 0, i32 0 @@ -169,14 +169,14 @@ int8x8_t test_vqtbl4_s8(int8x16x4_t a, uint8x8_t b) { return vqtbl4_s8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl1q_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl1q_s8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[VTBL1_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> %a, <16 x i8> %b) #3 // CHECK: ret <16 x i8> [[VTBL1_I]] int8x16_t test_vqtbl1q_s8(int8x16_t a, int8x16_t b) { return vqtbl1q_s8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl2q_s8([2 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl2q_s8([2 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 { // CHECK: [[__P0_I:%.*]] = alloca %struct.int8x16x2_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.int8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x2_t, %struct.int8x16x2_t* [[A]], i32 0, i32 0 @@ -197,7 +197,7 @@ int8x16_t test_vqtbl2q_s8(int8x16x2_t a, int8x16_t b) { return vqtbl2q_s8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl3q_s8([3 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl3q_s8([3 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 { // CHECK: [[__P0_I:%.*]] = alloca %struct.int8x16x3_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.int8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x3_t, %struct.int8x16x3_t* [[A]], i32 0, i32 0 @@ -221,7 +221,7 @@ int8x16_t test_vqtbl3q_s8(int8x16x3_t a, int8x16_t b) { return vqtbl3q_s8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl4q_s8([4 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl4q_s8([4 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 { // CHECK: [[__P0_I:%.*]] = alloca %struct.int8x16x4_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.int8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x4_t, %struct.int8x16x4_t* [[A]], i32 0, i32 0 @@ -248,7 +248,7 @@ int8x16_t test_vqtbl4q_s8(int8x16x4_t a, int8x16_t b) { return vqtbl4q_s8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx1_s8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) #0 { // CHECK: [[VTBL1_I:%.*]] = shufflevector <8 x i8> %b, <8 x i8> zeroinitializer, <16 x i32> // CHECK: [[VTBL11_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VTBL1_I]], <8 x i8> %c) #3 // CHECK: [[TMP0:%.*]] = icmp uge <8 x i8> %c, @@ -262,7 +262,7 @@ int8x8_t test_vtbx1_s8(int8x8_t a, int8x8_t b, int8x8_t c) { return vtbx1_s8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx2_s8(<8 x i8> noundef %a, [2 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx2_s8(<8 x i8> %a, [2 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.int8x8x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int8x8x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x2_t, %struct.int8x8x2_t* [[B]], i32 0, i32 0 @@ -284,7 +284,7 @@ int8x8_t test_vtbx2_s8(int8x8_t a, int8x8x2_t b, int8x8_t c) { return vtbx2_s8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx3_s8(<8 x i8> noundef %a, [3 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx3_s8(<8 x i8> %a, [3 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.int8x8x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int8x8x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x3_t, %struct.int8x8x3_t* [[B]], i32 0, i32 0 @@ -316,7 +316,7 @@ int8x8_t test_vtbx3_s8(int8x8_t a, int8x8x3_t b, int8x8_t c) { return vtbx3_s8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx4_s8(<8 x i8> noundef %a, [4 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx4_s8(<8 x i8> %a, [4 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.int8x8x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int8x8x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x4_t, %struct.int8x8x4_t* [[B]], i32 0, i32 0 @@ -345,14 +345,14 @@ int8x8_t test_vtbx4_s8(int8x8_t a, int8x8x4_t b, int8x8_t c) { return vtbx4_s8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx1_s8(<8 x i8> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx1_s8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) #1 { // CHECK: [[VTBX1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbx1.v8i8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) #3 // CHECK: ret <8 x i8> [[VTBX1_I]] int8x8_t test_vqtbx1_s8(int8x8_t a, int8x16_t b, uint8x8_t c) { return vqtbx1_s8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx2_s8(<8 x i8> noundef %a, [2 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx2_s8(<8 x i8> %a, [2 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.int8x16x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x2_t, %struct.int8x16x2_t* [[B]], i32 0, i32 0 @@ -373,7 +373,7 @@ int8x8_t test_vqtbx2_s8(int8x8_t a, int8x16x2_t b, uint8x8_t c) { return vqtbx2_s8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx3_s8(<8 x i8> noundef %a, [3 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx3_s8(<8 x i8> %a, [3 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.int8x16x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x3_t, %struct.int8x16x3_t* [[B]], i32 0, i32 0 @@ -397,7 +397,7 @@ int8x8_t test_vqtbx3_s8(int8x8_t a, int8x16x3_t b, uint8x8_t c) { return vqtbx3_s8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx4_s8(<8 x i8> noundef %a, [4 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx4_s8(<8 x i8> %a, [4 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.int8x16x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x4_t, %struct.int8x16x4_t* [[B]], i32 0, i32 0 @@ -424,14 +424,14 @@ int8x8_t test_vqtbx4_s8(int8x8_t a, int8x16x4_t b, uint8x8_t c) { return vqtbx4_s8(a, b, c); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx1q_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx1q_s8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #1 { // CHECK: [[VTBX1_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.tbx1.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #3 // CHECK: ret <16 x i8> [[VTBX1_I]] int8x16_t test_vqtbx1q_s8(int8x16_t a, int8x16_t b, uint8x16_t c) { return vqtbx1q_s8(a, b, c); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx2q_s8(<16 x i8> noundef %a, [2 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx2q_s8(<16 x i8> %a, [2 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 { // CHECK: [[__P1_I:%.*]] = alloca %struct.int8x16x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x2_t, %struct.int8x16x2_t* [[B]], i32 0, i32 0 @@ -452,7 +452,7 @@ int8x16_t test_vqtbx2q_s8(int8x16_t a, int8x16x2_t b, int8x16_t c) { return vqtbx2q_s8(a, b, c); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx3q_s8(<16 x i8> noundef %a, [3 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx3q_s8(<16 x i8> %a, [3 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 { // CHECK: [[__P1_I:%.*]] = alloca %struct.int8x16x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x3_t, %struct.int8x16x3_t* [[B]], i32 0, i32 0 @@ -476,7 +476,7 @@ int8x16_t test_vqtbx3q_s8(int8x16_t a, int8x16x3_t b, int8x16_t c) { return vqtbx3q_s8(a, b, c); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx4q_s8(<16 x i8> noundef %a, [4 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx4q_s8(<16 x i8> %a, [4 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 { // CHECK: [[__P1_I:%.*]] = alloca %struct.int8x16x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x4_t, %struct.int8x16x4_t* [[B]], i32 0, i32 0 @@ -503,7 +503,7 @@ int8x16_t test_vqtbx4q_s8(int8x16_t a, int8x16x4_t b, int8x16_t c) { return vqtbx4q_s8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl1_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl1_u8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[VTBL1_I:%.*]] = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <16 x i32> // CHECK: [[VTBL11_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VTBL1_I]], <8 x i8> %b) #3 // CHECK: ret <8 x i8> [[VTBL11_I]] @@ -511,14 +511,14 @@ uint8x8_t test_vtbl1_u8(uint8x8_t a, uint8x8_t b) { return vtbl1_u8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl1_u8(<16 x i8> noundef %a, <8 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl1_u8(<16 x i8> %a, <8 x i8> %b) #1 { // CHECK: [[VTBL1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %a, <8 x i8> %b) #3 // CHECK: ret <8 x i8> [[VTBL1_I]] uint8x8_t test_vqtbl1_u8(uint8x16_t a, uint8x8_t b) { return vqtbl1_u8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl2_u8([2 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl2_u8([2 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x8x2_t, align 8 // CHECK: [[A:%.*]] = alloca %struct.uint8x8x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x2_t, %struct.uint8x8x2_t* [[A]], i32 0, i32 0 @@ -540,7 +540,7 @@ uint8x8_t test_vtbl2_u8(uint8x8x2_t a, uint8x8_t b) { return vtbl2_u8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl2_u8([2 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl2_u8([2 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x16x2_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.uint8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x2_t, %struct.uint8x16x2_t* [[A]], i32 0, i32 0 @@ -561,7 +561,7 @@ uint8x8_t test_vqtbl2_u8(uint8x16x2_t a, uint8x8_t b) { return vqtbl2_u8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl3_u8([3 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl3_u8([3 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x8x3_t, align 8 // CHECK: [[A:%.*]] = alloca %struct.uint8x8x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x3_t, %struct.uint8x8x3_t* [[A]], i32 0, i32 0 @@ -587,7 +587,7 @@ uint8x8_t test_vtbl3_u8(uint8x8x3_t a, uint8x8_t b) { return vtbl3_u8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl3_u8([3 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl3_u8([3 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x16x3_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.uint8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x3_t, %struct.uint8x16x3_t* [[A]], i32 0, i32 0 @@ -611,7 +611,7 @@ uint8x8_t test_vqtbl3_u8(uint8x16x3_t a, uint8x8_t b) { return vqtbl3_u8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl4_u8([4 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl4_u8([4 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x8x4_t, align 8 // CHECK: [[A:%.*]] = alloca %struct.uint8x8x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x4_t, %struct.uint8x8x4_t* [[A]], i32 0, i32 0 @@ -640,7 +640,7 @@ uint8x8_t test_vtbl4_u8(uint8x8x4_t a, uint8x8_t b) { return vtbl4_u8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl4_u8([4 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl4_u8([4 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x16x4_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.uint8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x4_t, %struct.uint8x16x4_t* [[A]], i32 0, i32 0 @@ -667,14 +667,14 @@ uint8x8_t test_vqtbl4_u8(uint8x16x4_t a, uint8x8_t b) { return vqtbl4_u8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl1q_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl1q_u8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[VTBL1_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> %a, <16 x i8> %b) #3 // CHECK: ret <16 x i8> [[VTBL1_I]] uint8x16_t test_vqtbl1q_u8(uint8x16_t a, uint8x16_t b) { return vqtbl1q_u8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl2q_u8([2 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl2q_u8([2 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 { // CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x16x2_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.uint8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x2_t, %struct.uint8x16x2_t* [[A]], i32 0, i32 0 @@ -695,7 +695,7 @@ uint8x16_t test_vqtbl2q_u8(uint8x16x2_t a, uint8x16_t b) { return vqtbl2q_u8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl3q_u8([3 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl3q_u8([3 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 { // CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x16x3_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.uint8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x3_t, %struct.uint8x16x3_t* [[A]], i32 0, i32 0 @@ -719,7 +719,7 @@ uint8x16_t test_vqtbl3q_u8(uint8x16x3_t a, uint8x16_t b) { return vqtbl3q_u8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl4q_u8([4 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl4q_u8([4 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 { // CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x16x4_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.uint8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x4_t, %struct.uint8x16x4_t* [[A]], i32 0, i32 0 @@ -746,7 +746,7 @@ uint8x16_t test_vqtbl4q_u8(uint8x16x4_t a, uint8x16_t b) { return vqtbl4q_u8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx1_u8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx1_u8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) #0 { // CHECK: [[VTBL1_I:%.*]] = shufflevector <8 x i8> %b, <8 x i8> zeroinitializer, <16 x i32> // CHECK: [[VTBL11_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VTBL1_I]], <8 x i8> %c) #3 // CHECK: [[TMP0:%.*]] = icmp uge <8 x i8> %c, @@ -760,7 +760,7 @@ uint8x8_t test_vtbx1_u8(uint8x8_t a, uint8x8_t b, uint8x8_t c) { return vtbx1_u8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx2_u8(<8 x i8> noundef %a, [2 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx2_u8(<8 x i8> %a, [2 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x8x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint8x8x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x2_t, %struct.uint8x8x2_t* [[B]], i32 0, i32 0 @@ -782,7 +782,7 @@ uint8x8_t test_vtbx2_u8(uint8x8_t a, uint8x8x2_t b, uint8x8_t c) { return vtbx2_u8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx3_u8(<8 x i8> noundef %a, [3 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx3_u8(<8 x i8> %a, [3 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x8x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint8x8x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x3_t, %struct.uint8x8x3_t* [[B]], i32 0, i32 0 @@ -814,7 +814,7 @@ uint8x8_t test_vtbx3_u8(uint8x8_t a, uint8x8x3_t b, uint8x8_t c) { return vtbx3_u8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx4_u8(<8 x i8> noundef %a, [4 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx4_u8(<8 x i8> %a, [4 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x8x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint8x8x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x4_t, %struct.uint8x8x4_t* [[B]], i32 0, i32 0 @@ -843,14 +843,14 @@ uint8x8_t test_vtbx4_u8(uint8x8_t a, uint8x8x4_t b, uint8x8_t c) { return vtbx4_u8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx1_u8(<8 x i8> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx1_u8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) #1 { // CHECK: [[VTBX1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbx1.v8i8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) #3 // CHECK: ret <8 x i8> [[VTBX1_I]] uint8x8_t test_vqtbx1_u8(uint8x8_t a, uint8x16_t b, uint8x8_t c) { return vqtbx1_u8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx2_u8(<8 x i8> noundef %a, [2 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx2_u8(<8 x i8> %a, [2 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x16x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x2_t, %struct.uint8x16x2_t* [[B]], i32 0, i32 0 @@ -871,7 +871,7 @@ uint8x8_t test_vqtbx2_u8(uint8x8_t a, uint8x16x2_t b, uint8x8_t c) { return vqtbx2_u8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx3_u8(<8 x i8> noundef %a, [3 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx3_u8(<8 x i8> %a, [3 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x16x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x3_t, %struct.uint8x16x3_t* [[B]], i32 0, i32 0 @@ -895,7 +895,7 @@ uint8x8_t test_vqtbx3_u8(uint8x8_t a, uint8x16x3_t b, uint8x8_t c) { return vqtbx3_u8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx4_u8(<8 x i8> noundef %a, [4 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx4_u8(<8 x i8> %a, [4 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x16x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x4_t, %struct.uint8x16x4_t* [[B]], i32 0, i32 0 @@ -922,14 +922,14 @@ uint8x8_t test_vqtbx4_u8(uint8x8_t a, uint8x16x4_t b, uint8x8_t c) { return vqtbx4_u8(a, b, c); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx1q_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx1q_u8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #1 { // CHECK: [[VTBX1_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.tbx1.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #3 // CHECK: ret <16 x i8> [[VTBX1_I]] uint8x16_t test_vqtbx1q_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c) { return vqtbx1q_u8(a, b, c); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx2q_u8(<16 x i8> noundef %a, [2 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx2q_u8(<16 x i8> %a, [2 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 { // CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x16x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x2_t, %struct.uint8x16x2_t* [[B]], i32 0, i32 0 @@ -950,7 +950,7 @@ uint8x16_t test_vqtbx2q_u8(uint8x16_t a, uint8x16x2_t b, uint8x16_t c) { return vqtbx2q_u8(a, b, c); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx3q_u8(<16 x i8> noundef %a, [3 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx3q_u8(<16 x i8> %a, [3 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 { // CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x16x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x3_t, %struct.uint8x16x3_t* [[B]], i32 0, i32 0 @@ -974,7 +974,7 @@ uint8x16_t test_vqtbx3q_u8(uint8x16_t a, uint8x16x3_t b, uint8x16_t c) { return vqtbx3q_u8(a, b, c); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx4q_u8(<16 x i8> noundef %a, [4 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx4q_u8(<16 x i8> %a, [4 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 { // CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x16x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x4_t, %struct.uint8x16x4_t* [[B]], i32 0, i32 0 @@ -1001,7 +1001,7 @@ uint8x16_t test_vqtbx4q_u8(uint8x16_t a, uint8x16x4_t b, uint8x16_t c) { return vqtbx4q_u8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl1_p8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl1_p8(<8 x i8> %a, <8 x i8> %b) #0 { // CHECK: [[VTBL1_I:%.*]] = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <16 x i32> // CHECK: [[VTBL11_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VTBL1_I]], <8 x i8> %b) #3 // CHECK: ret <8 x i8> [[VTBL11_I]] @@ -1009,14 +1009,14 @@ poly8x8_t test_vtbl1_p8(poly8x8_t a, uint8x8_t b) { return vtbl1_p8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl1_p8(<16 x i8> noundef %a, <8 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl1_p8(<16 x i8> %a, <8 x i8> %b) #1 { // CHECK: [[VTBL1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %a, <8 x i8> %b) #3 // CHECK: ret <8 x i8> [[VTBL1_I]] poly8x8_t test_vqtbl1_p8(poly8x16_t a, uint8x8_t b) { return vqtbl1_p8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl2_p8([2 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl2_p8([2 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x8x2_t, align 8 // CHECK: [[A:%.*]] = alloca %struct.poly8x8x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x2_t, %struct.poly8x8x2_t* [[A]], i32 0, i32 0 @@ -1038,7 +1038,7 @@ poly8x8_t test_vtbl2_p8(poly8x8x2_t a, uint8x8_t b) { return vtbl2_p8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl2_p8([2 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl2_p8([2 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x16x2_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.poly8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x2_t, %struct.poly8x16x2_t* [[A]], i32 0, i32 0 @@ -1059,7 +1059,7 @@ poly8x8_t test_vqtbl2_p8(poly8x16x2_t a, uint8x8_t b) { return vqtbl2_p8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl3_p8([3 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl3_p8([3 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x8x3_t, align 8 // CHECK: [[A:%.*]] = alloca %struct.poly8x8x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x3_t, %struct.poly8x8x3_t* [[A]], i32 0, i32 0 @@ -1085,7 +1085,7 @@ poly8x8_t test_vtbl3_p8(poly8x8x3_t a, uint8x8_t b) { return vtbl3_p8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl3_p8([3 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl3_p8([3 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x16x3_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.poly8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x3_t, %struct.poly8x16x3_t* [[A]], i32 0, i32 0 @@ -1109,7 +1109,7 @@ poly8x8_t test_vqtbl3_p8(poly8x16x3_t a, uint8x8_t b) { return vqtbl3_p8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl4_p8([4 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl4_p8([4 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x8x4_t, align 8 // CHECK: [[A:%.*]] = alloca %struct.poly8x8x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x4_t, %struct.poly8x8x4_t* [[A]], i32 0, i32 0 @@ -1138,7 +1138,7 @@ poly8x8_t test_vtbl4_p8(poly8x8x4_t a, uint8x8_t b) { return vtbl4_p8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl4_p8([4 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl4_p8([4 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 { // CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x16x4_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.poly8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x4_t, %struct.poly8x16x4_t* [[A]], i32 0, i32 0 @@ -1165,14 +1165,14 @@ poly8x8_t test_vqtbl4_p8(poly8x16x4_t a, uint8x8_t b) { return vqtbl4_p8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl1q_p8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl1q_p8(<16 x i8> %a, <16 x i8> %b) #1 { // CHECK: [[VTBL1_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> %a, <16 x i8> %b) #3 // CHECK: ret <16 x i8> [[VTBL1_I]] poly8x16_t test_vqtbl1q_p8(poly8x16_t a, uint8x16_t b) { return vqtbl1q_p8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl2q_p8([2 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl2q_p8([2 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 { // CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x16x2_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.poly8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x2_t, %struct.poly8x16x2_t* [[A]], i32 0, i32 0 @@ -1193,7 +1193,7 @@ poly8x16_t test_vqtbl2q_p8(poly8x16x2_t a, uint8x16_t b) { return vqtbl2q_p8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl3q_p8([3 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl3q_p8([3 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 { // CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x16x3_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.poly8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x3_t, %struct.poly8x16x3_t* [[A]], i32 0, i32 0 @@ -1217,7 +1217,7 @@ poly8x16_t test_vqtbl3q_p8(poly8x16x3_t a, uint8x16_t b) { return vqtbl3q_p8(a, b); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl4q_p8([4 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl4q_p8([4 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 { // CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x16x4_t, align 16 // CHECK: [[A:%.*]] = alloca %struct.poly8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x4_t, %struct.poly8x16x4_t* [[A]], i32 0, i32 0 @@ -1244,7 +1244,7 @@ poly8x16_t test_vqtbl4q_p8(poly8x16x4_t a, uint8x16_t b) { return vqtbl4q_p8(a, b); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx1_p8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx1_p8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) #0 { // CHECK: [[VTBL1_I:%.*]] = shufflevector <8 x i8> %b, <8 x i8> zeroinitializer, <16 x i32> // CHECK: [[VTBL11_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VTBL1_I]], <8 x i8> %c) #3 // CHECK: [[TMP0:%.*]] = icmp uge <8 x i8> %c, @@ -1258,7 +1258,7 @@ poly8x8_t test_vtbx1_p8(poly8x8_t a, poly8x8_t b, uint8x8_t c) { return vtbx1_p8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx2_p8(<8 x i8> noundef %a, [2 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx2_p8(<8 x i8> %a, [2 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x8x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly8x8x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x2_t, %struct.poly8x8x2_t* [[B]], i32 0, i32 0 @@ -1280,7 +1280,7 @@ poly8x8_t test_vtbx2_p8(poly8x8_t a, poly8x8x2_t b, uint8x8_t c) { return vtbx2_p8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx3_p8(<8 x i8> noundef %a, [3 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx3_p8(<8 x i8> %a, [3 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x8x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly8x8x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x3_t, %struct.poly8x8x3_t* [[B]], i32 0, i32 0 @@ -1312,7 +1312,7 @@ poly8x8_t test_vtbx3_p8(poly8x8_t a, poly8x8x3_t b, uint8x8_t c) { return vtbx3_p8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx4_p8(<8 x i8> noundef %a, [4 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx4_p8(<8 x i8> %a, [4 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x8x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly8x8x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x4_t, %struct.poly8x8x4_t* [[B]], i32 0, i32 0 @@ -1341,14 +1341,14 @@ poly8x8_t test_vtbx4_p8(poly8x8_t a, poly8x8x4_t b, uint8x8_t c) { return vtbx4_p8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx1_p8(<8 x i8> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx1_p8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) #1 { // CHECK: [[VTBX1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbx1.v8i8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) #3 // CHECK: ret <8 x i8> [[VTBX1_I]] poly8x8_t test_vqtbx1_p8(poly8x8_t a, uint8x16_t b, uint8x8_t c) { return vqtbx1_p8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx2_p8(<8 x i8> noundef %a, [2 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx2_p8(<8 x i8> %a, [2 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x16x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x2_t, %struct.poly8x16x2_t* [[B]], i32 0, i32 0 @@ -1369,7 +1369,7 @@ poly8x8_t test_vqtbx2_p8(poly8x8_t a, poly8x16x2_t b, uint8x8_t c) { return vqtbx2_p8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx3_p8(<8 x i8> noundef %a, [3 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx3_p8(<8 x i8> %a, [3 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x16x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x3_t, %struct.poly8x16x3_t* [[B]], i32 0, i32 0 @@ -1393,7 +1393,7 @@ poly8x8_t test_vqtbx3_p8(poly8x8_t a, poly8x16x3_t b, uint8x8_t c) { return vqtbx3_p8(a, b, c); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx4_p8(<8 x i8> noundef %a, [4 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx4_p8(<8 x i8> %a, [4 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 { // CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x16x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x4_t, %struct.poly8x16x4_t* [[B]], i32 0, i32 0 @@ -1420,14 +1420,14 @@ poly8x8_t test_vqtbx4_p8(poly8x8_t a, poly8x16x4_t b, uint8x8_t c) { return vqtbx4_p8(a, b, c); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx1q_p8(<16 x i8> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx1q_p8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #1 { // CHECK: [[VTBX1_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.tbx1.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #3 // CHECK: ret <16 x i8> [[VTBX1_I]] poly8x16_t test_vqtbx1q_p8(poly8x16_t a, uint8x16_t b, uint8x16_t c) { return vqtbx1q_p8(a, b, c); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx2q_p8(<16 x i8> noundef %a, [2 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx2q_p8(<16 x i8> %a, [2 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 { // CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x16x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x2_t, %struct.poly8x16x2_t* [[B]], i32 0, i32 0 @@ -1448,7 +1448,7 @@ poly8x16_t test_vqtbx2q_p8(poly8x16_t a, poly8x16x2_t b, uint8x16_t c) { return vqtbx2q_p8(a, b, c); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx3q_p8(<16 x i8> noundef %a, [3 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx3q_p8(<16 x i8> %a, [3 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 { // CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x16x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x3_t, %struct.poly8x16x3_t* [[B]], i32 0, i32 0 @@ -1472,7 +1472,7 @@ poly8x16_t test_vqtbx3q_p8(poly8x16_t a, poly8x16x3_t b, uint8x16_t c) { return vqtbx3q_p8(a, b, c); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx4q_p8(<16 x i8> noundef %a, [4 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx4q_p8(<16 x i8> %a, [4 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 { // CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x16x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x4_t, %struct.poly8x16x4_t* [[B]], i32 0, i32 0 diff --git a/clang/test/CodeGen/aarch64-neon-vcombine.c b/clang/test/CodeGen/aarch64-neon-vcombine.c index 72afd18eefbbf7ffd949f5c63c54a042d03ea472..71f5ddfb627704cc54d54f5c78b60edaabb4ca32 100644 --- a/clang/test/CodeGen/aarch64-neon-vcombine.c +++ b/clang/test/CodeGen/aarch64-neon-vcombine.c @@ -4,98 +4,98 @@ #include -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcombine_s8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcombine_s8(<8 x i8> %low, <8 x i8> %high) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> %low, <8 x i8> %high, <16 x i32> // CHECK: ret <16 x i8> [[SHUFFLE_I]] int8x16_t test_vcombine_s8(int8x8_t low, int8x8_t high) { return vcombine_s8(low, high); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcombine_s16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcombine_s16(<4 x i16> %low, <4 x i16> %high) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> %low, <4 x i16> %high, <8 x i32> // CHECK: ret <8 x i16> [[SHUFFLE_I]] int16x8_t test_vcombine_s16(int16x4_t low, int16x4_t high) { return vcombine_s16(low, high); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcombine_s32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcombine_s32(<2 x i32> %low, <2 x i32> %high) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> %low, <2 x i32> %high, <4 x i32> // CHECK: ret <4 x i32> [[SHUFFLE_I]] int32x4_t test_vcombine_s32(int32x2_t low, int32x2_t high) { return vcombine_s32(low, high); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_s64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_s64(<1 x i64> %low, <1 x i64> %high) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <1 x i64> %low, <1 x i64> %high, <2 x i32> // CHECK: ret <2 x i64> [[SHUFFLE_I]] int64x2_t test_vcombine_s64(int64x1_t low, int64x1_t high) { return vcombine_s64(low, high); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcombine_u8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcombine_u8(<8 x i8> %low, <8 x i8> %high) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> %low, <8 x i8> %high, <16 x i32> // CHECK: ret <16 x i8> [[SHUFFLE_I]] uint8x16_t test_vcombine_u8(uint8x8_t low, uint8x8_t high) { return vcombine_u8(low, high); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcombine_u16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcombine_u16(<4 x i16> %low, <4 x i16> %high) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> %low, <4 x i16> %high, <8 x i32> // CHECK: ret <8 x i16> [[SHUFFLE_I]] uint16x8_t test_vcombine_u16(uint16x4_t low, uint16x4_t high) { return vcombine_u16(low, high); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcombine_u32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcombine_u32(<2 x i32> %low, <2 x i32> %high) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> %low, <2 x i32> %high, <4 x i32> // CHECK: ret <4 x i32> [[SHUFFLE_I]] uint32x4_t test_vcombine_u32(uint32x2_t low, uint32x2_t high) { return vcombine_u32(low, high); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_u64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_u64(<1 x i64> %low, <1 x i64> %high) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <1 x i64> %low, <1 x i64> %high, <2 x i32> // CHECK: ret <2 x i64> [[SHUFFLE_I]] uint64x2_t test_vcombine_u64(uint64x1_t low, uint64x1_t high) { return vcombine_u64(low, high); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_p64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_p64(<1 x i64> %low, <1 x i64> %high) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <1 x i64> %low, <1 x i64> %high, <2 x i32> // CHECK: ret <2 x i64> [[SHUFFLE_I]] poly64x2_t test_vcombine_p64(poly64x1_t low, poly64x1_t high) { return vcombine_p64(low, high); } -// CHECK-LABEL: define{{.*}} <8 x half> @test_vcombine_f16(<4 x half> noundef %low, <4 x half> noundef %high) #0 { +// CHECK-LABEL: define{{.*}} <8 x half> @test_vcombine_f16(<4 x half> %low, <4 x half> %high) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x half> %low, <4 x half> %high, <8 x i32> // CHECK: ret <8 x half> [[SHUFFLE_I]] float16x8_t test_vcombine_f16(float16x4_t low, float16x4_t high) { return vcombine_f16(low, high); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vcombine_f32(<2 x float> noundef %low, <2 x float> noundef %high) #0 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vcombine_f32(<2 x float> %low, <2 x float> %high) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x float> %low, <2 x float> %high, <4 x i32> // CHECK: ret <4 x float> [[SHUFFLE_I]] float32x4_t test_vcombine_f32(float32x2_t low, float32x2_t high) { return vcombine_f32(low, high); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcombine_p8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcombine_p8(<8 x i8> %low, <8 x i8> %high) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> %low, <8 x i8> %high, <16 x i32> // CHECK: ret <16 x i8> [[SHUFFLE_I]] poly8x16_t test_vcombine_p8(poly8x8_t low, poly8x8_t high) { return vcombine_p8(low, high); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcombine_p16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcombine_p16(<4 x i16> %low, <4 x i16> %high) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> %low, <4 x i16> %high, <8 x i32> // CHECK: ret <8 x i16> [[SHUFFLE_I]] poly16x8_t test_vcombine_p16(poly16x4_t low, poly16x4_t high) { return vcombine_p16(low, high); } -// CHECK-LABEL: define{{.*}} <2 x double> @test_vcombine_f64(<1 x double> noundef %low, <1 x double> noundef %high) #0 { +// CHECK-LABEL: define{{.*}} <2 x double> @test_vcombine_f64(<1 x double> %low, <1 x double> %high) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <1 x double> %low, <1 x double> %high, <2 x i32> // CHECK: ret <2 x double> [[SHUFFLE_I]] float64x2_t test_vcombine_f64(float64x1_t low, float64x1_t high) { diff --git a/clang/test/CodeGen/aarch64-neon-vget-hilo.c b/clang/test/CodeGen/aarch64-neon-vget-hilo.c index 4ab18b08b1623e2320304091374b31aad1eaaaab..71b344bf20dfd5f76d1b3ba203ec1b28b33b5780 100644 --- a/clang/test/CodeGen/aarch64-neon-vget-hilo.c +++ b/clang/test/CodeGen/aarch64-neon-vget-hilo.c @@ -5,196 +5,196 @@ #include -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_high_s8(<16 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_high_s8(<16 x i8> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> // CHECK: ret <8 x i8> [[SHUFFLE_I]] int8x8_t test_vget_high_s8(int8x16_t a) { return vget_high_s8(a); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_high_s16(<8 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_high_s16(<8 x i16> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> // CHECK: ret <4 x i16> [[SHUFFLE_I]] int16x4_t test_vget_high_s16(int16x8_t a) { return vget_high_s16(a); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_high_s32(<4 x i32> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_high_s32(<4 x i32> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> // CHECK: ret <2 x i32> [[SHUFFLE_I]] int32x2_t test_vget_high_s32(int32x4_t a) { return vget_high_s32(a); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_high_s64(<2 x i64> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_high_s64(<2 x i64> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> // CHECK: ret <1 x i64> [[SHUFFLE_I]] int64x1_t test_vget_high_s64(int64x2_t a) { return vget_high_s64(a); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_high_u8(<16 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_high_u8(<16 x i8> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> // CHECK: ret <8 x i8> [[SHUFFLE_I]] uint8x8_t test_vget_high_u8(uint8x16_t a) { return vget_high_u8(a); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_high_u16(<8 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_high_u16(<8 x i16> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> // CHECK: ret <4 x i16> [[SHUFFLE_I]] uint16x4_t test_vget_high_u16(uint16x8_t a) { return vget_high_u16(a); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_high_u32(<4 x i32> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_high_u32(<4 x i32> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> // CHECK: ret <2 x i32> [[SHUFFLE_I]] uint32x2_t test_vget_high_u32(uint32x4_t a) { return vget_high_u32(a); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_high_u64(<2 x i64> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_high_u64(<2 x i64> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> // CHECK: ret <1 x i64> [[SHUFFLE_I]] uint64x1_t test_vget_high_u64(uint64x2_t a) { return vget_high_u64(a); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_high_p64(<2 x i64> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_high_p64(<2 x i64> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> // CHECK: ret <1 x i64> [[SHUFFLE_I]] poly64x1_t test_vget_high_p64(poly64x2_t a) { return vget_high_p64(a); } -// CHECK-LABEL: define{{.*}} <4 x half> @test_vget_high_f16(<8 x half> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <4 x half> @test_vget_high_f16(<8 x half> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 x i32> // CHECK: ret <4 x half> [[SHUFFLE_I]] float16x4_t test_vget_high_f16(float16x8_t a) { return vget_high_f16(a); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vget_high_f32(<4 x float> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vget_high_f32(<4 x float> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> // CHECK: ret <2 x float> [[SHUFFLE_I]] float32x2_t test_vget_high_f32(float32x4_t a) { return vget_high_f32(a); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_high_p8(<16 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_high_p8(<16 x i8> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> // CHECK: ret <8 x i8> [[SHUFFLE_I]] poly8x8_t test_vget_high_p8(poly8x16_t a) { return vget_high_p8(a); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_high_p16(<8 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_high_p16(<8 x i16> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> // CHECK: ret <4 x i16> [[SHUFFLE_I]] poly16x4_t test_vget_high_p16(poly16x8_t a) { return vget_high_p16(a); } -// CHECK-LABEL: define{{.*}} <1 x double> @test_vget_high_f64(<2 x double> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <1 x double> @test_vget_high_f64(<2 x double> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x double> %a, <2 x double> %a, <1 x i32> // CHECK: ret <1 x double> [[SHUFFLE_I]] float64x1_t test_vget_high_f64(float64x2_t a) { return vget_high_f64(a); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_low_s8(<16 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_low_s8(<16 x i8> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> // CHECK: ret <8 x i8> [[SHUFFLE_I]] int8x8_t test_vget_low_s8(int8x16_t a) { return vget_low_s8(a); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_low_s16(<8 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_low_s16(<8 x i16> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> // CHECK: ret <4 x i16> [[SHUFFLE_I]] int16x4_t test_vget_low_s16(int16x8_t a) { return vget_low_s16(a); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_low_s32(<4 x i32> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_low_s32(<4 x i32> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> // CHECK: ret <2 x i32> [[SHUFFLE_I]] int32x2_t test_vget_low_s32(int32x4_t a) { return vget_low_s32(a); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_low_s64(<2 x i64> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_low_s64(<2 x i64> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> zeroinitializer // CHECK: ret <1 x i64> [[SHUFFLE_I]] int64x1_t test_vget_low_s64(int64x2_t a) { return vget_low_s64(a); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_low_u8(<16 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_low_u8(<16 x i8> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> // CHECK: ret <8 x i8> [[SHUFFLE_I]] uint8x8_t test_vget_low_u8(uint8x16_t a) { return vget_low_u8(a); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_low_u16(<8 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_low_u16(<8 x i16> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> // CHECK: ret <4 x i16> [[SHUFFLE_I]] uint16x4_t test_vget_low_u16(uint16x8_t a) { return vget_low_u16(a); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_low_u32(<4 x i32> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_low_u32(<4 x i32> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> // CHECK: ret <2 x i32> [[SHUFFLE_I]] uint32x2_t test_vget_low_u32(uint32x4_t a) { return vget_low_u32(a); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_low_u64(<2 x i64> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_low_u64(<2 x i64> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> zeroinitializer // CHECK: ret <1 x i64> [[SHUFFLE_I]] uint64x1_t test_vget_low_u64(uint64x2_t a) { return vget_low_u64(a); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_low_p64(<2 x i64> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_low_p64(<2 x i64> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> zeroinitializer // CHECK: ret <1 x i64> [[SHUFFLE_I]] poly64x1_t test_vget_low_p64(poly64x2_t a) { return vget_low_p64(a); } -// CHECK-LABEL: define{{.*}} <4 x half> @test_vget_low_f16(<8 x half> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <4 x half> @test_vget_low_f16(<8 x half> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 x i32> // CHECK: ret <4 x half> [[SHUFFLE_I]] float16x4_t test_vget_low_f16(float16x8_t a) { return vget_low_f16(a); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vget_low_f32(<4 x float> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vget_low_f32(<4 x float> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> // CHECK: ret <2 x float> [[SHUFFLE_I]] float32x2_t test_vget_low_f32(float32x4_t a) { return vget_low_f32(a); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_low_p8(<16 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_low_p8(<16 x i8> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> // CHECK: ret <8 x i8> [[SHUFFLE_I]] poly8x8_t test_vget_low_p8(poly8x16_t a) { return vget_low_p8(a); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_low_p16(<8 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_low_p16(<8 x i16> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> // CHECK: ret <4 x i16> [[SHUFFLE_I]] poly16x4_t test_vget_low_p16(poly16x8_t a) { return vget_low_p16(a); } -// CHECK-LABEL: define{{.*}} <1 x double> @test_vget_low_f64(<2 x double> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <1 x double> @test_vget_low_f64(<2 x double> %a) #0 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x double> %a, <2 x double> %a, <1 x i32> zeroinitializer // CHECK: ret <1 x double> [[SHUFFLE_I]] float64x1_t test_vget_low_f64(float64x2_t a) { diff --git a/clang/test/CodeGen/aarch64-neon-vget.c b/clang/test/CodeGen/aarch64-neon-vget.c index 92ebd45848ed9f58967ce2a9cbb8acd137f505c3..9f88acc17cb121f6e963399851446d9906e70ff2 100644 --- a/clang/test/CodeGen/aarch64-neon-vget.c +++ b/clang/test/CodeGen/aarch64-neon-vget.c @@ -4,70 +4,70 @@ #include -// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_u8(<8 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_u8(<8 x i8> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7 // CHECK: ret i8 [[VGET_LANE]] uint8_t test_vget_lane_u8(uint8x8_t a) { return vget_lane_u8(a, 7); } -// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_u16(<4 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_u16(<4 x i16> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3 // CHECK: ret i16 [[VGET_LANE]] uint16_t test_vget_lane_u16(uint16x4_t a) { return vget_lane_u16(a, 3); } -// CHECK-LABEL: define{{.*}} i32 @test_vget_lane_u32(<2 x i32> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vget_lane_u32(<2 x i32> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %a, i32 1 // CHECK: ret i32 [[VGET_LANE]] uint32_t test_vget_lane_u32(uint32x2_t a) { return vget_lane_u32(a, 1); } -// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_s8(<8 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_s8(<8 x i8> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7 // CHECK: ret i8 [[VGET_LANE]] int8_t test_vget_lane_s8(int8x8_t a) { return vget_lane_s8(a, 7); } -// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_s16(<4 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_s16(<4 x i16> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3 // CHECK: ret i16 [[VGET_LANE]] int16_t test_vget_lane_s16(int16x4_t a) { return vget_lane_s16(a, 3); } -// CHECK-LABEL: define{{.*}} i32 @test_vget_lane_s32(<2 x i32> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i32 @test_vget_lane_s32(<2 x i32> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %a, i32 1 // CHECK: ret i32 [[VGET_LANE]] int32_t test_vget_lane_s32(int32x2_t a) { return vget_lane_s32(a, 1); } -// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_p8(<8 x i8> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_p8(<8 x i8> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7 // CHECK: ret i8 [[VGET_LANE]] poly8_t test_vget_lane_p8(poly8x8_t a) { return vget_lane_p8(a, 7); } -// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_p16(<4 x i16> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_p16(<4 x i16> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3 // CHECK: ret i16 [[VGET_LANE]] poly16_t test_vget_lane_p16(poly16x4_t a) { return vget_lane_p16(a, 3); } -// CHECK-LABEL: define{{.*}} float @test_vget_lane_f32(<2 x float> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} float @test_vget_lane_f32(<2 x float> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <2 x float> %a, i32 1 // CHECK: ret float [[VGET_LANE]] float32_t test_vget_lane_f32(float32x2_t a) { return vget_lane_f32(a, 1); } -// CHECK-LABEL: define{{.*}} float @test_vget_lane_f16(<4 x half> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} float @test_vget_lane_f16(<4 x half> %a) #0 { // CHECK: [[__REINT_242:%.*]] = alloca <4 x half>, align 8 // CHECK: [[__REINT1_242:%.*]] = alloca i16, align 2 // CHECK: store <4 x half> %a, <4 x half>* [[__REINT_242]], align 8 @@ -83,70 +83,70 @@ float32_t test_vget_lane_f16(float16x4_t a) { return vget_lane_f16(a, 1); } -// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_u8(<16 x i8> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15 // CHECK: ret i8 [[VGETQ_LANE]] uint8_t test_vgetq_lane_u8(uint8x16_t a) { return vgetq_lane_u8(a, 15); } -// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_u16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_u16(<8 x i16> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7 // CHECK: ret i16 [[VGETQ_LANE]] uint16_t test_vgetq_lane_u16(uint16x8_t a) { return vgetq_lane_u16(a, 7); } -// CHECK-LABEL: define{{.*}} i32 @test_vgetq_lane_u32(<4 x i32> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vgetq_lane_u32(<4 x i32> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a, i32 3 // CHECK: ret i32 [[VGETQ_LANE]] uint32_t test_vgetq_lane_u32(uint32x4_t a) { return vgetq_lane_u32(a, 3); } -// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_s8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_s8(<16 x i8> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15 // CHECK: ret i8 [[VGETQ_LANE]] int8_t test_vgetq_lane_s8(int8x16_t a) { return vgetq_lane_s8(a, 15); } -// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_s16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_s16(<8 x i16> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7 // CHECK: ret i16 [[VGETQ_LANE]] int16_t test_vgetq_lane_s16(int16x8_t a) { return vgetq_lane_s16(a, 7); } -// CHECK-LABEL: define{{.*}} i32 @test_vgetq_lane_s32(<4 x i32> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i32 @test_vgetq_lane_s32(<4 x i32> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a, i32 3 // CHECK: ret i32 [[VGETQ_LANE]] int32_t test_vgetq_lane_s32(int32x4_t a) { return vgetq_lane_s32(a, 3); } -// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_p8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_p8(<16 x i8> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15 // CHECK: ret i8 [[VGETQ_LANE]] poly8_t test_vgetq_lane_p8(poly8x16_t a) { return vgetq_lane_p8(a, 15); } -// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_p16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_p16(<8 x i16> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7 // CHECK: ret i16 [[VGETQ_LANE]] poly16_t test_vgetq_lane_p16(poly16x8_t a) { return vgetq_lane_p16(a, 7); } -// CHECK-LABEL: define{{.*}} float @test_vgetq_lane_f32(<4 x float> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} float @test_vgetq_lane_f32(<4 x float> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x float> %a, i32 3 // CHECK: ret float [[VGETQ_LANE]] float32_t test_vgetq_lane_f32(float32x4_t a) { return vgetq_lane_f32(a, 3); } -// CHECK-LABEL: define{{.*}} float @test_vgetq_lane_f16(<8 x half> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} float @test_vgetq_lane_f16(<8 x half> %a) #1 { // CHECK: [[__REINT_244:%.*]] = alloca <8 x half>, align 16 // CHECK: [[__REINT1_244:%.*]] = alloca i16, align 2 // CHECK: store <8 x half> %a, <8 x half>* [[__REINT_244]], align 16 @@ -162,28 +162,28 @@ float32_t test_vgetq_lane_f16(float16x8_t a) { return vgetq_lane_f16(a, 3); } -// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_s64(<1 x i64> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_s64(<1 x i64> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %a, i32 0 // CHECK: ret i64 [[VGET_LANE]] int64_t test_vget_lane_s64(int64x1_t a) { return vget_lane_s64(a, 0); } -// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_u64(<1 x i64> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_u64(<1 x i64> %a) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %a, i32 0 // CHECK: ret i64 [[VGET_LANE]] uint64_t test_vget_lane_u64(uint64x1_t a) { return vget_lane_u64(a, 0); } -// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_s64(<2 x i64> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_s64(<2 x i64> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a, i32 1 // CHECK: ret i64 [[VGETQ_LANE]] int64_t test_vgetq_lane_s64(int64x2_t a) { return vgetq_lane_s64(a, 1); } -// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_u64(<2 x i64> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_u64(<2 x i64> %a) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a, i32 1 // CHECK: ret i64 [[VGETQ_LANE]] uint64_t test_vgetq_lane_u64(uint64x2_t a) { @@ -191,70 +191,70 @@ uint64_t test_vgetq_lane_u64(uint64x2_t a) { } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_u8(i8 noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_u8(i8 %a, <8 x i8> %b) #0 { // CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7 // CHECK: ret <8 x i8> [[VSET_LANE]] uint8x8_t test_vset_lane_u8(uint8_t a, uint8x8_t b) { return vset_lane_u8(a, b, 7); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_u16(i16 noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_u16(i16 %a, <4 x i16> %b) #0 { // CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> %b, i16 %a, i32 3 // CHECK: ret <4 x i16> [[VSET_LANE]] uint16x4_t test_vset_lane_u16(uint16_t a, uint16x4_t b) { return vset_lane_u16(a, b, 3); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vset_lane_u32(i32 noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vset_lane_u32(i32 %a, <2 x i32> %b) #0 { // CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i32> %b, i32 %a, i32 1 // CHECK: ret <2 x i32> [[VSET_LANE]] uint32x2_t test_vset_lane_u32(uint32_t a, uint32x2_t b) { return vset_lane_u32(a, b, 1); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_s8(i8 noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_s8(i8 %a, <8 x i8> %b) #0 { // CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7 // CHECK: ret <8 x i8> [[VSET_LANE]] int8x8_t test_vset_lane_s8(int8_t a, int8x8_t b) { return vset_lane_s8(a, b, 7); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_s16(i16 noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_s16(i16 %a, <4 x i16> %b) #0 { // CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> %b, i16 %a, i32 3 // CHECK: ret <4 x i16> [[VSET_LANE]] int16x4_t test_vset_lane_s16(int16_t a, int16x4_t b) { return vset_lane_s16(a, b, 3); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vset_lane_s32(i32 noundef %a, <2 x i32> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vset_lane_s32(i32 %a, <2 x i32> %b) #0 { // CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i32> %b, i32 %a, i32 1 // CHECK: ret <2 x i32> [[VSET_LANE]] int32x2_t test_vset_lane_s32(int32_t a, int32x2_t b) { return vset_lane_s32(a, b, 1); } -// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_p8(i8 noundef %a, <8 x i8> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_p8(i8 %a, <8 x i8> %b) #0 { // CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7 // CHECK: ret <8 x i8> [[VSET_LANE]] poly8x8_t test_vset_lane_p8(poly8_t a, poly8x8_t b) { return vset_lane_p8(a, b, 7); } -// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_p16(i16 noundef %a, <4 x i16> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_p16(i16 %a, <4 x i16> %b) #0 { // CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> %b, i16 %a, i32 3 // CHECK: ret <4 x i16> [[VSET_LANE]] poly16x4_t test_vset_lane_p16(poly16_t a, poly16x4_t b) { return vset_lane_p16(a, b, 3); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vset_lane_f32(float noundef %a, <2 x float> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vset_lane_f32(float %a, <2 x float> %b) #0 { // CHECK: [[VSET_LANE:%.*]] = insertelement <2 x float> %b, float %a, i32 1 // CHECK: ret <2 x float> [[VSET_LANE]] float32x2_t test_vset_lane_f32(float32_t a, float32x2_t b) { return vset_lane_f32(a, b, 1); } -// CHECK-LABEL: define{{.*}} <4 x half> @test_vset_lane_f16(half* noundef %a, <4 x half> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <4 x half> @test_vset_lane_f16(half* %a, <4 x half> %b) #0 { // CHECK: [[__REINT_246:%.*]] = alloca half, align 2 // CHECK: [[__REINT1_246:%.*]] = alloca <4 x half>, align 8 // CHECK: [[__REINT2_246:%.*]] = alloca <4 x i16>, align 8 @@ -274,70 +274,70 @@ float16x4_t test_vset_lane_f16(float16_t *a, float16x4_t b) { return vset_lane_f16(*a, b, 3); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_u8(i8 noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_u8(i8 %a, <16 x i8> %b) #1 { // CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %b, i8 %a, i32 15 // CHECK: ret <16 x i8> [[VSET_LANE]] uint8x16_t test_vsetq_lane_u8(uint8_t a, uint8x16_t b) { return vsetq_lane_u8(a, b, 15); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_u16(i16 noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_u16(i16 %a, <8 x i16> %b) #1 { // CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> %b, i16 %a, i32 7 // CHECK: ret <8 x i16> [[VSET_LANE]] uint16x8_t test_vsetq_lane_u16(uint16_t a, uint16x8_t b) { return vsetq_lane_u16(a, b, 7); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vsetq_lane_u32(i32 noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vsetq_lane_u32(i32 %a, <4 x i32> %b) #1 { // CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i32> %b, i32 %a, i32 3 // CHECK: ret <4 x i32> [[VSET_LANE]] uint32x4_t test_vsetq_lane_u32(uint32_t a, uint32x4_t b) { return vsetq_lane_u32(a, b, 3); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_s8(i8 noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_s8(i8 %a, <16 x i8> %b) #1 { // CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %b, i8 %a, i32 15 // CHECK: ret <16 x i8> [[VSET_LANE]] int8x16_t test_vsetq_lane_s8(int8_t a, int8x16_t b) { return vsetq_lane_s8(a, b, 15); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_s16(i16 noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_s16(i16 %a, <8 x i16> %b) #1 { // CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> %b, i16 %a, i32 7 // CHECK: ret <8 x i16> [[VSET_LANE]] int16x8_t test_vsetq_lane_s16(int16_t a, int16x8_t b) { return vsetq_lane_s16(a, b, 7); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vsetq_lane_s32(i32 noundef %a, <4 x i32> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vsetq_lane_s32(i32 %a, <4 x i32> %b) #1 { // CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i32> %b, i32 %a, i32 3 // CHECK: ret <4 x i32> [[VSET_LANE]] int32x4_t test_vsetq_lane_s32(int32_t a, int32x4_t b) { return vsetq_lane_s32(a, b, 3); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_p8(i8 noundef %a, <16 x i8> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_p8(i8 %a, <16 x i8> %b) #1 { // CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %b, i8 %a, i32 15 // CHECK: ret <16 x i8> [[VSET_LANE]] poly8x16_t test_vsetq_lane_p8(poly8_t a, poly8x16_t b) { return vsetq_lane_p8(a, b, 15); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_p16(i16 noundef %a, <8 x i16> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_p16(i16 %a, <8 x i16> %b) #1 { // CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> %b, i16 %a, i32 7 // CHECK: ret <8 x i16> [[VSET_LANE]] poly16x8_t test_vsetq_lane_p16(poly16_t a, poly16x8_t b) { return vsetq_lane_p16(a, b, 7); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vsetq_lane_f32(float noundef %a, <4 x float> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vsetq_lane_f32(float %a, <4 x float> %b) #1 { // CHECK: [[VSET_LANE:%.*]] = insertelement <4 x float> %b, float %a, i32 3 // CHECK: ret <4 x float> [[VSET_LANE]] float32x4_t test_vsetq_lane_f32(float32_t a, float32x4_t b) { return vsetq_lane_f32(a, b, 3); } -// CHECK-LABEL: define{{.*}} <8 x half> @test_vsetq_lane_f16(half* noundef %a, <8 x half> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <8 x half> @test_vsetq_lane_f16(half* %a, <8 x half> %b) #1 { // CHECK: [[__REINT_248:%.*]] = alloca half, align 2 // CHECK: [[__REINT1_248:%.*]] = alloca <8 x half>, align 16 // CHECK: [[__REINT2_248:%.*]] = alloca <8 x i16>, align 16 @@ -357,28 +357,28 @@ float16x8_t test_vsetq_lane_f16(float16_t *a, float16x8_t b) { return vsetq_lane_f16(*a, b, 7); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_s64(i64 noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_s64(i64 %a, <1 x i64> %b) #0 { // CHECK: [[VSET_LANE:%.*]] = insertelement <1 x i64> %b, i64 %a, i32 0 // CHECK: ret <1 x i64> [[VSET_LANE]] int64x1_t test_vset_lane_s64(int64_t a, int64x1_t b) { return vset_lane_s64(a, b, 0); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_u64(i64 noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_u64(i64 %a, <1 x i64> %b) #0 { // CHECK: [[VSET_LANE:%.*]] = insertelement <1 x i64> %b, i64 %a, i32 0 // CHECK: ret <1 x i64> [[VSET_LANE]] uint64x1_t test_vset_lane_u64(uint64_t a, uint64x1_t b) { return vset_lane_u64(a, b, 0); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_s64(i64 noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_s64(i64 %a, <2 x i64> %b) #1 { // CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %b, i64 %a, i32 1 // CHECK: ret <2 x i64> [[VSET_LANE]] int64x2_t test_vsetq_lane_s64(int64_t a, int64x2_t b) { return vsetq_lane_s64(a, b, 1); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_u64(i64 noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_u64(i64 %a, <2 x i64> %b) #1 { // CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %b, i64 %a, i32 1 // CHECK: ret <2 x i64> [[VSET_LANE]] uint64x2_t test_vsetq_lane_u64(uint64_t a, uint64x2_t b) { diff --git a/clang/test/CodeGen/aarch64-poly128.c b/clang/test/CodeGen/aarch64-poly128.c index 6535d4b69bb8eb20c506b23378efe7dd5b7a0dd9..113160f9d64b685f2d00f18d0d8e25985a9eee54 100644 --- a/clang/test/CodeGen/aarch64-poly128.c +++ b/clang/test/CodeGen/aarch64-poly128.c @@ -12,7 +12,7 @@ #include -// CHECK-LABEL: define{{.*}} void @test_vstrq_p128(i128* noundef %ptr, i128 noundef %val) #0 { +// CHECK-LABEL: define{{.*}} void @test_vstrq_p128(i128* %ptr, i128 %val) #0 { // CHECK: [[TMP0:%.*]] = bitcast i128* %ptr to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i128* // CHECK: store i128 %val, i128* [[TMP1]] @@ -22,7 +22,7 @@ void test_vstrq_p128(poly128_t * ptr, poly128_t val) { } -// CHECK-LABEL: define{{.*}} i128 @test_vldrq_p128(i128* noundef %ptr) #0 { +// CHECK-LABEL: define{{.*}} i128 @test_vldrq_p128(i128* %ptr) #0 { // CHECK: [[TMP0:%.*]] = bitcast i128* %ptr to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i128* // CHECK: [[TMP2:%.*]] = load i128, i128* [[TMP1]] @@ -32,7 +32,7 @@ poly128_t test_vldrq_p128(poly128_t * ptr) { } -// CHECK-LABEL: define{{.*}} void @test_ld_st_p128(i128* noundef %ptr) #0 { +// CHECK-LABEL: define{{.*}} void @test_ld_st_p128(i128* %ptr) #0 { // CHECK: [[TMP0:%.*]] = bitcast i128* %ptr to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i128* // CHECK: [[TMP2:%.*]] = load i128, i128* [[TMP1]] @@ -46,7 +46,7 @@ void test_ld_st_p128(poly128_t * ptr) { } -// CHECK-LABEL: define{{.*}} i128 @test_vmull_p64(i64 noundef %a, i64 noundef %b) #0 { +// CHECK-LABEL: define{{.*}} i128 @test_vmull_p64(i64 %a, i64 %b) #0 { // CHECK: [[VMULL_P64_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %a, i64 %b) #3 // CHECK: [[VMULL_P641_I:%.*]] = bitcast <16 x i8> [[VMULL_P64_I]] to i128 // CHECK: ret i128 [[VMULL_P641_I]] @@ -54,7 +54,7 @@ poly128_t test_vmull_p64(poly64_t a, poly64_t b) { return vmull_p64(a, b); } -// CHECK-LABEL: define{{.*}} i128 @test_vmull_high_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} i128 @test_vmull_high_p64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> // CHECK: [[TMP0:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to i64 // CHECK: [[SHUFFLE_I7_I:%.*]] = shufflevector <2 x i64> %b, <2 x i64> %b, <1 x i32> @@ -66,182 +66,182 @@ poly128_t test_vmull_high_p64(poly64x2_t a, poly64x2_t b) { return vmull_high_p64(a, b); } -// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s8(<16 x i8> %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast <16 x i8> %a to i128 // CHECK: ret i128 [[TMP0]] poly128_t test_vreinterpretq_p128_s8(int8x16_t a) { return vreinterpretq_p128_s8(a); } -// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s16(<8 x i16> %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to i128 // CHECK: ret i128 [[TMP0]] poly128_t test_vreinterpretq_p128_s16(int16x8_t a) { return vreinterpretq_p128_s16(a); } -// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s32(<4 x i32> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s32(<4 x i32> %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to i128 // CHECK: ret i128 [[TMP0]] poly128_t test_vreinterpretq_p128_s32(int32x4_t a) { return vreinterpretq_p128_s32(a); } -// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s64(<2 x i64> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s64(<2 x i64> %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to i128 // CHECK: ret i128 [[TMP0]] poly128_t test_vreinterpretq_p128_s64(int64x2_t a) { return vreinterpretq_p128_s64(a); } -// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u8(<16 x i8> %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast <16 x i8> %a to i128 // CHECK: ret i128 [[TMP0]] poly128_t test_vreinterpretq_p128_u8(uint8x16_t a) { return vreinterpretq_p128_u8(a); } -// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u16(<8 x i16> %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to i128 // CHECK: ret i128 [[TMP0]] poly128_t test_vreinterpretq_p128_u16(uint16x8_t a) { return vreinterpretq_p128_u16(a); } -// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u32(<4 x i32> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u32(<4 x i32> %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to i128 // CHECK: ret i128 [[TMP0]] poly128_t test_vreinterpretq_p128_u32(uint32x4_t a) { return vreinterpretq_p128_u32(a); } -// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u64(<2 x i64> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u64(<2 x i64> %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to i128 // CHECK: ret i128 [[TMP0]] poly128_t test_vreinterpretq_p128_u64(uint64x2_t a) { return vreinterpretq_p128_u64(a); } -// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_f32(<4 x float> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_f32(<4 x float> %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to i128 // CHECK: ret i128 [[TMP0]] poly128_t test_vreinterpretq_p128_f32(float32x4_t a) { return vreinterpretq_p128_f32(a); } -// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_f64(<2 x double> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_f64(<2 x double> %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to i128 // CHECK: ret i128 [[TMP0]] poly128_t test_vreinterpretq_p128_f64(float64x2_t a) { return vreinterpretq_p128_f64(a); } -// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_p8(<16 x i8> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_p8(<16 x i8> %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast <16 x i8> %a to i128 // CHECK: ret i128 [[TMP0]] poly128_t test_vreinterpretq_p128_p8(poly8x16_t a) { return vreinterpretq_p128_p8(a); } -// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_p16(<8 x i16> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_p16(<8 x i16> %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to i128 // CHECK: ret i128 [[TMP0]] poly128_t test_vreinterpretq_p128_p16(poly16x8_t a) { return vreinterpretq_p128_p16(a); } -// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_p64(<2 x i64> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_p64(<2 x i64> %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to i128 // CHECK: ret i128 [[TMP0]] poly128_t test_vreinterpretq_p128_p64(poly64x2_t a) { return vreinterpretq_p128_p64(a); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vreinterpretq_s8_p128(i128 noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vreinterpretq_s8_p128(i128 %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i128 %a to <16 x i8> // CHECK: ret <16 x i8> [[TMP0]] int8x16_t test_vreinterpretq_s8_p128(poly128_t a) { return vreinterpretq_s8_p128(a); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vreinterpretq_s16_p128(i128 noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vreinterpretq_s16_p128(i128 %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i128 %a to <8 x i16> // CHECK: ret <8 x i16> [[TMP0]] int16x8_t test_vreinterpretq_s16_p128(poly128_t a) { return vreinterpretq_s16_p128(a); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vreinterpretq_s32_p128(i128 noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vreinterpretq_s32_p128(i128 %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i128 %a to <4 x i32> // CHECK: ret <4 x i32> [[TMP0]] int32x4_t test_vreinterpretq_s32_p128(poly128_t a) { return vreinterpretq_s32_p128(a); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vreinterpretq_s64_p128(i128 noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vreinterpretq_s64_p128(i128 %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i128 %a to <2 x i64> // CHECK: ret <2 x i64> [[TMP0]] int64x2_t test_vreinterpretq_s64_p128(poly128_t a) { return vreinterpretq_s64_p128(a); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vreinterpretq_u8_p128(i128 noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vreinterpretq_u8_p128(i128 %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i128 %a to <16 x i8> // CHECK: ret <16 x i8> [[TMP0]] uint8x16_t test_vreinterpretq_u8_p128(poly128_t a) { return vreinterpretq_u8_p128(a); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vreinterpretq_u16_p128(i128 noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vreinterpretq_u16_p128(i128 %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i128 %a to <8 x i16> // CHECK: ret <8 x i16> [[TMP0]] uint16x8_t test_vreinterpretq_u16_p128(poly128_t a) { return vreinterpretq_u16_p128(a); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vreinterpretq_u32_p128(i128 noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vreinterpretq_u32_p128(i128 %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i128 %a to <4 x i32> // CHECK: ret <4 x i32> [[TMP0]] uint32x4_t test_vreinterpretq_u32_p128(poly128_t a) { return vreinterpretq_u32_p128(a); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vreinterpretq_u64_p128(i128 noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vreinterpretq_u64_p128(i128 %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i128 %a to <2 x i64> // CHECK: ret <2 x i64> [[TMP0]] uint64x2_t test_vreinterpretq_u64_p128(poly128_t a) { return vreinterpretq_u64_p128(a); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vreinterpretq_f32_p128(i128 noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vreinterpretq_f32_p128(i128 %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i128 %a to <4 x float> // CHECK: ret <4 x float> [[TMP0]] float32x4_t test_vreinterpretq_f32_p128(poly128_t a) { return vreinterpretq_f32_p128(a); } -// CHECK-LABEL: define{{.*}} <2 x double> @test_vreinterpretq_f64_p128(i128 noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <2 x double> @test_vreinterpretq_f64_p128(i128 %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i128 %a to <2 x double> // CHECK: ret <2 x double> [[TMP0]] float64x2_t test_vreinterpretq_f64_p128(poly128_t a) { return vreinterpretq_f64_p128(a); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vreinterpretq_p8_p128(i128 noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vreinterpretq_p8_p128(i128 %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i128 %a to <16 x i8> // CHECK: ret <16 x i8> [[TMP0]] poly8x16_t test_vreinterpretq_p8_p128(poly128_t a) { return vreinterpretq_p8_p128(a); } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vreinterpretq_p16_p128(i128 noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vreinterpretq_p16_p128(i128 %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i128 %a to <8 x i16> // CHECK: ret <8 x i16> [[TMP0]] poly16x8_t test_vreinterpretq_p16_p128(poly128_t a) { return vreinterpretq_p16_p128(a); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vreinterpretq_p64_p128(i128 noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vreinterpretq_p64_p128(i128 %a) #1 { // CHECK: [[TMP0:%.*]] = bitcast i128 %a to <2 x i64> // CHECK: ret <2 x i64> [[TMP0]] poly64x2_t test_vreinterpretq_p64_p128(poly128_t a) { diff --git a/clang/test/CodeGen/aarch64-poly64.c b/clang/test/CodeGen/aarch64-poly64.c index 4fbb384c3b5f6815296f3052fb972045dcc0a6e0..ebc58b5840faf3e00221ce82b558006d5e9739d2 100644 --- a/clang/test/CodeGen/aarch64-poly64.c +++ b/clang/test/CodeGen/aarch64-poly64.c @@ -6,7 +6,7 @@ #include -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vceq_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vceq_p64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[CMP_I:%.*]] = icmp eq <1 x i64> %a, %b // CHECK: [[SEXT_I:%.*]] = sext <1 x i1> [[CMP_I]] to <1 x i64> // CHECK: ret <1 x i64> [[SEXT_I]] @@ -14,7 +14,7 @@ uint64x1_t test_vceq_p64(poly64x1_t a, poly64x1_t b) { return vceq_p64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vceqq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vceqq_p64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[CMP_I:%.*]] = icmp eq <2 x i64> %a, %b // CHECK: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i64> // CHECK: ret <2 x i64> [[SEXT_I]] @@ -22,7 +22,7 @@ uint64x2_t test_vceqq_p64(poly64x2_t a, poly64x2_t b) { return vceqq_p64(a, b); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vtst_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vtst_p64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[TMP4:%.*]] = and <1 x i64> %a, %b // CHECK: [[TMP5:%.*]] = icmp ne <1 x i64> [[TMP4]], zeroinitializer // CHECK: [[VTST_I:%.*]] = sext <1 x i1> [[TMP5]] to <1 x i64> @@ -31,7 +31,7 @@ uint64x1_t test_vtst_p64(poly64x1_t a, poly64x1_t b) { return vtst_p64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vtstq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vtstq_p64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[TMP4:%.*]] = and <2 x i64> %a, %b // CHECK: [[TMP5:%.*]] = icmp ne <2 x i64> [[TMP4]], zeroinitializer // CHECK: [[VTST_I:%.*]] = sext <2 x i1> [[TMP5]] to <2 x i64> @@ -40,7 +40,7 @@ uint64x2_t test_vtstq_p64(poly64x2_t a, poly64x2_t b) { return vtstq_p64(a, b); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vbsl_p64(<1 x i64> noundef %a, <1 x i64> noundef %b, <1 x i64> noundef %c) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vbsl_p64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) #0 { // CHECK: [[VBSL3_I:%.*]] = and <1 x i64> %a, %b // CHECK: [[TMP3:%.*]] = xor <1 x i64> %a, // CHECK: [[VBSL4_I:%.*]] = and <1 x i64> [[TMP3]], %c @@ -50,7 +50,7 @@ poly64x1_t test_vbsl_p64(poly64x1_t a, poly64x1_t b, poly64x1_t c) { return vbsl_p64(a, b, c); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vbslq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b, <2 x i64> noundef %c) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vbslq_p64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) #1 { // CHECK: [[VBSL3_I:%.*]] = and <2 x i64> %a, %b // CHECK: [[TMP3:%.*]] = xor <2 x i64> %a, // CHECK: [[VBSL4_I:%.*]] = and <2 x i64> [[TMP3]], %c @@ -60,35 +60,35 @@ poly64x2_t test_vbslq_p64(poly64x2_t a, poly64x2_t b, poly64x2_t c) { return vbslq_p64(a, b, c); } -// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_p64(<1 x i64> noundef %v) #0 { +// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_p64(<1 x i64> %v) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %v, i32 0 // CHECK: ret i64 [[VGET_LANE]] poly64_t test_vget_lane_p64(poly64x1_t v) { return vget_lane_p64(v, 0); } -// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_p64(<2 x i64> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_p64(<2 x i64> %v) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %v, i32 1 // CHECK: ret i64 [[VGETQ_LANE]] poly64_t test_vgetq_lane_p64(poly64x2_t v) { return vgetq_lane_p64(v, 1); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_p64(i64 noundef %a, <1 x i64> noundef %v) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_p64(i64 %a, <1 x i64> %v) #0 { // CHECK: [[VSET_LANE:%.*]] = insertelement <1 x i64> %v, i64 %a, i32 0 // CHECK: ret <1 x i64> [[VSET_LANE]] poly64x1_t test_vset_lane_p64(poly64_t a, poly64x1_t v) { return vset_lane_p64(a, v, 0); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_p64(i64 noundef %a, <2 x i64> noundef %v) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_p64(i64 %a, <2 x i64> %v) #1 { // CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %v, i64 %a, i32 1 // CHECK: ret <2 x i64> [[VSET_LANE]] poly64x2_t test_vsetq_lane_p64(poly64_t a, poly64x2_t v) { return vsetq_lane_p64(a, v, 1); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vcopy_lane_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vcopy_lane_p64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %b, i32 0 // CHECK: [[VSET_LANE:%.*]] = insertelement <1 x i64> %a, i64 [[VGET_LANE]], i32 0 // CHECK: ret <1 x i64> [[VSET_LANE]] @@ -97,7 +97,7 @@ poly64x1_t test_vcopy_lane_p64(poly64x1_t a, poly64x1_t b) { } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcopyq_lane_p64(<2 x i64> noundef %a, <1 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcopyq_lane_p64(<2 x i64> %a, <1 x i64> %b) #1 { // CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %b, i32 0 // CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %a, i64 [[VGET_LANE]], i32 1 // CHECK: ret <2 x i64> [[VSET_LANE]] @@ -105,7 +105,7 @@ poly64x2_t test_vcopyq_lane_p64(poly64x2_t a, poly64x1_t b) { return vcopyq_lane_p64(a, 1, b, 0); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcopyq_laneq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcopyq_laneq_p64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %b, i32 1 // CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %a, i64 [[VGETQ_LANE]], i32 1 // CHECK: ret <2 x i64> [[VSET_LANE]] @@ -113,20 +113,20 @@ poly64x2_t test_vcopyq_laneq_p64(poly64x2_t a, poly64x2_t b) { return vcopyq_laneq_p64(a, 1, b, 1); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vcreate_p64(i64 noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vcreate_p64(i64 %a) #0 { // CHECK: [[TMP0:%.*]] = bitcast i64 %a to <1 x i64> // CHECK: ret <1 x i64> [[TMP0]] poly64x1_t test_vcreate_p64(uint64_t a) { return vcreate_p64(a); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vdup_n_p64(i64 noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vdup_n_p64(i64 %a) #0 { // CHECK: [[VECINIT_I:%.*]] = insertelement <1 x i64> undef, i64 %a, i32 0 // CHECK: ret <1 x i64> [[VECINIT_I]] poly64x1_t test_vdup_n_p64(poly64_t a) { return vdup_n_p64(a); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vdupq_n_p64(i64 noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vdupq_n_p64(i64 %a) #1 { // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i64> undef, i64 %a, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 %a, i32 1 // CHECK: ret <2 x i64> [[VECINIT1_I]] @@ -134,14 +134,14 @@ poly64x2_t test_vdupq_n_p64(poly64_t a) { return vdupq_n_p64(a); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vmov_n_p64(i64 noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vmov_n_p64(i64 %a) #0 { // CHECK: [[VECINIT_I:%.*]] = insertelement <1 x i64> undef, i64 %a, i32 0 // CHECK: ret <1 x i64> [[VECINIT_I]] poly64x1_t test_vmov_n_p64(poly64_t a) { return vmov_n_p64(a); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vmovq_n_p64(i64 noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vmovq_n_p64(i64 %a) #1 { // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i64> undef, i64 %a, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 %a, i32 1 // CHECK: ret <2 x i64> [[VECINIT1_I]] @@ -149,7 +149,7 @@ poly64x2_t test_vmovq_n_p64(poly64_t a) { return vmovq_n_p64(a); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vdup_lane_p64(<1 x i64> noundef %vec) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vdup_lane_p64(<1 x i64> %vec) #0 { // CHECK: [[TMP0:%.*]] = bitcast <1 x i64> [[VEC:%.*]] to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> // CHECK: [[LANE:%.*]] = shufflevector <1 x i64> [[TMP1]], <1 x i64> [[TMP1]], <1 x i32> zeroinitializer @@ -158,7 +158,7 @@ poly64x1_t test_vdup_lane_p64(poly64x1_t vec) { return vdup_lane_p64(vec, 0); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vdupq_lane_p64(<1 x i64> noundef %vec) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vdupq_lane_p64(<1 x i64> %vec) #1 { // CHECK: [[TMP0:%.*]] = bitcast <1 x i64> [[VEC:%.*]] to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> // CHECK: [[LANE:%.*]] = shufflevector <1 x i64> [[TMP1]], <1 x i64> [[TMP1]], <2 x i32> zeroinitializer @@ -167,7 +167,7 @@ poly64x2_t test_vdupq_lane_p64(poly64x1_t vec) { return vdupq_lane_p64(vec, 0); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vdupq_laneq_p64(<2 x i64> noundef %vec) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vdupq_laneq_p64(<2 x i64> %vec) #1 { // CHECK: [[TMP0:%.*]] = bitcast <2 x i64> [[VEC:%.*]] to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> // CHECK: [[LANE:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP1]], <2 x i32> @@ -176,14 +176,14 @@ poly64x2_t test_vdupq_laneq_p64(poly64x2_t vec) { return vdupq_laneq_p64(vec, 1); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_p64(<1 x i64> noundef %low, <1 x i64> noundef %high) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_p64(<1 x i64> %low, <1 x i64> %high) #1 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <1 x i64> %low, <1 x i64> %high, <2 x i32> // CHECK: ret <2 x i64> [[SHUFFLE_I]] poly64x2_t test_vcombine_p64(poly64x1_t low, poly64x1_t high) { return vcombine_p64(low, high); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_p64(i64* noundef %ptr) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_p64(i64* %ptr) #0 { // CHECK: [[TMP0:%.*]] = bitcast i64* %ptr to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <1 x i64>* // CHECK: [[TMP2:%.*]] = load <1 x i64>, <1 x i64>* [[TMP1]] @@ -192,7 +192,7 @@ poly64x1_t test_vld1_p64(poly64_t const * ptr) { return vld1_p64(ptr); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_p64(i64* noundef %ptr) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_p64(i64* %ptr) #1 { // CHECK: [[TMP0:%.*]] = bitcast i64* %ptr to i8* // CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>* // CHECK: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]] @@ -201,7 +201,7 @@ poly64x2_t test_vld1q_p64(poly64_t const * ptr) { return vld1q_p64(ptr); } -// CHECK-LABEL: define{{.*}} void @test_vst1_p64(i64* noundef %ptr, <1 x i64> noundef %val) #0 { +// CHECK-LABEL: define{{.*}} void @test_vst1_p64(i64* %ptr, <1 x i64> %val) #0 { // CHECK: [[TMP0:%.*]] = bitcast i64* %ptr to i8* // CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %val to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP0]] to <1 x i64>* @@ -212,7 +212,7 @@ void test_vst1_p64(poly64_t * ptr, poly64x1_t val) { return vst1_p64(ptr, val); } -// CHECK-LABEL: define{{.*}} void @test_vst1q_p64(i64* noundef %ptr, <2 x i64> noundef %val) #1 { +// CHECK-LABEL: define{{.*}} void @test_vst1q_p64(i64* %ptr, <2 x i64> %val) #1 { // CHECK: [[TMP0:%.*]] = bitcast i64* %ptr to i8* // CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %val to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>* @@ -223,7 +223,7 @@ void test_vst1q_p64(poly64_t * ptr, poly64x2_t val) { return vst1q_p64(ptr, val); } -// CHECK-LABEL: define{{.*}} %struct.poly64x1x2_t @test_vld2_p64(i64* noundef %ptr) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x1x2_t @test_vld2_p64(i64* %ptr) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x1x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x1x2_t, align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x1x2_t* [[__RET]] to i8* @@ -241,7 +241,7 @@ poly64x1x2_t test_vld2_p64(poly64_t const * ptr) { return vld2_p64(ptr); } -// CHECK-LABEL: define{{.*}} %struct.poly64x2x2_t @test_vld2q_p64(i64* noundef %ptr) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x2x2_t @test_vld2q_p64(i64* %ptr) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x2x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x2x2_t, align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x2x2_t* [[__RET]] to i8* @@ -259,7 +259,7 @@ poly64x2x2_t test_vld2q_p64(poly64_t const * ptr) { return vld2q_p64(ptr); } -// CHECK-LABEL: define{{.*}} %struct.poly64x1x3_t @test_vld3_p64(i64* noundef %ptr) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x1x3_t @test_vld3_p64(i64* %ptr) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x1x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x1x3_t, align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x1x3_t* [[__RET]] to i8* @@ -277,7 +277,7 @@ poly64x1x3_t test_vld3_p64(poly64_t const * ptr) { return vld3_p64(ptr); } -// CHECK-LABEL: define{{.*}} %struct.poly64x2x3_t @test_vld3q_p64(i64* noundef %ptr) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x2x3_t @test_vld3q_p64(i64* %ptr) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x2x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x2x3_t, align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x2x3_t* [[__RET]] to i8* @@ -295,7 +295,7 @@ poly64x2x3_t test_vld3q_p64(poly64_t const * ptr) { return vld3q_p64(ptr); } -// CHECK-LABEL: define{{.*}} %struct.poly64x1x4_t @test_vld4_p64(i64* noundef %ptr) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x1x4_t @test_vld4_p64(i64* %ptr) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x1x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x1x4_t, align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x1x4_t* [[__RET]] to i8* @@ -313,7 +313,7 @@ poly64x1x4_t test_vld4_p64(poly64_t const * ptr) { return vld4_p64(ptr); } -// CHECK-LABEL: define{{.*}} %struct.poly64x2x4_t @test_vld4q_p64(i64* noundef %ptr) #2 { +// CHECK-LABEL: define{{.*}} %struct.poly64x2x4_t @test_vld4q_p64(i64* %ptr) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x2x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x2x4_t, align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x2x4_t* [[__RET]] to i8* @@ -331,7 +331,7 @@ poly64x2x4_t test_vld4q_p64(poly64_t const * ptr) { return vld4q_p64(ptr); } -// CHECK-LABEL: define{{.*}} void @test_vst2_p64(i64* noundef %ptr, [2 x <1 x i64>] %val.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2_p64(i64* %ptr, [2 x <1 x i64>] %val.coerce) #2 { // CHECK: [[VAL:%.*]] = alloca %struct.poly64x1x2_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x1x2_t, %struct.poly64x1x2_t* [[VAL]], i32 0, i32 0 @@ -356,7 +356,7 @@ void test_vst2_p64(poly64_t * ptr, poly64x1x2_t val) { return vst2_p64(ptr, val); } -// CHECK-LABEL: define{{.*}} void @test_vst2q_p64(i64* noundef %ptr, [2 x <2 x i64>] %val.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst2q_p64(i64* %ptr, [2 x <2 x i64>] %val.coerce) #2 { // CHECK: [[VAL:%.*]] = alloca %struct.poly64x2x2_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x2x2_t, %struct.poly64x2x2_t* [[VAL]], i32 0, i32 0 @@ -381,7 +381,7 @@ void test_vst2q_p64(poly64_t * ptr, poly64x2x2_t val) { return vst2q_p64(ptr, val); } -// CHECK-LABEL: define{{.*}} void @test_vst3_p64(i64* noundef %ptr, [3 x <1 x i64>] %val.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3_p64(i64* %ptr, [3 x <1 x i64>] %val.coerce) #2 { // CHECK: [[VAL:%.*]] = alloca %struct.poly64x1x3_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x1x3_t, %struct.poly64x1x3_t* [[VAL]], i32 0, i32 0 @@ -411,7 +411,7 @@ void test_vst3_p64(poly64_t * ptr, poly64x1x3_t val) { return vst3_p64(ptr, val); } -// CHECK-LABEL: define{{.*}} void @test_vst3q_p64(i64* noundef %ptr, [3 x <2 x i64>] %val.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst3q_p64(i64* %ptr, [3 x <2 x i64>] %val.coerce) #2 { // CHECK: [[VAL:%.*]] = alloca %struct.poly64x2x3_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x2x3_t, %struct.poly64x2x3_t* [[VAL]], i32 0, i32 0 @@ -441,7 +441,7 @@ void test_vst3q_p64(poly64_t * ptr, poly64x2x3_t val) { return vst3q_p64(ptr, val); } -// CHECK-LABEL: define{{.*}} void @test_vst4_p64(i64* noundef %ptr, [4 x <1 x i64>] %val.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4_p64(i64* %ptr, [4 x <1 x i64>] %val.coerce) #2 { // CHECK: [[VAL:%.*]] = alloca %struct.poly64x1x4_t, align 8 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x1x4_t, %struct.poly64x1x4_t* [[VAL]], i32 0, i32 0 @@ -476,7 +476,7 @@ void test_vst4_p64(poly64_t * ptr, poly64x1x4_t val) { return vst4_p64(ptr, val); } -// CHECK-LABEL: define{{.*}} void @test_vst4q_p64(i64* noundef %ptr, [4 x <2 x i64>] %val.coerce) #2 { +// CHECK-LABEL: define{{.*}} void @test_vst4q_p64(i64* %ptr, [4 x <2 x i64>] %val.coerce) #2 { // CHECK: [[VAL:%.*]] = alloca %struct.poly64x2x4_t, align 16 // CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x2x4_t, %struct.poly64x2x4_t* [[VAL]], i32 0, i32 0 @@ -511,7 +511,7 @@ void test_vst4q_p64(poly64_t * ptr, poly64x2x4_t val) { return vst4q_p64(ptr, val); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vext_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vext_p64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> @@ -523,7 +523,7 @@ poly64x1_t test_vext_p64(poly64x1_t a, poly64x1_t b) { } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vextq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vextq_p64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> @@ -534,49 +534,49 @@ poly64x2_t test_vextq_p64(poly64x2_t a, poly64x2_t b) { return vextq_p64(a, b, 1); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vzip1q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vzip1q_p64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> // CHECK: ret <2 x i64> [[SHUFFLE_I]] poly64x2_t test_vzip1q_p64(poly64x2_t a, poly64x2_t b) { return vzip1q_p64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vzip2q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vzip2q_p64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> // CHECK: ret <2 x i64> [[SHUFFLE_I]] poly64x2_t test_vzip2q_p64(poly64x2_t a, poly64x2_t b) { return vzip2q_u64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vuzp1q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vuzp1q_p64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> // CHECK: ret <2 x i64> [[SHUFFLE_I]] poly64x2_t test_vuzp1q_p64(poly64x2_t a, poly64x2_t b) { return vuzp1q_p64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vuzp2q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vuzp2q_p64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> // CHECK: ret <2 x i64> [[SHUFFLE_I]] poly64x2_t test_vuzp2q_p64(poly64x2_t a, poly64x2_t b) { return vuzp2q_u64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vtrn1q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vtrn1q_p64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> // CHECK: ret <2 x i64> [[SHUFFLE_I]] poly64x2_t test_vtrn1q_p64(poly64x2_t a, poly64x2_t b) { return vtrn1q_p64(a, b); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vtrn2q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vtrn2q_p64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> // CHECK: ret <2 x i64> [[SHUFFLE_I]] poly64x2_t test_vtrn2q_p64(poly64x2_t a, poly64x2_t b) { return vtrn2q_u64(a, b); } -// CHECK-LABEL: define{{.*}} <1 x i64> @test_vsri_n_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <1 x i64> @test_vsri_n_p64(<1 x i64> %a, <1 x i64> %b) #0 { // CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8> // CHECK: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> @@ -587,7 +587,7 @@ poly64x1_t test_vsri_n_p64(poly64x1_t a, poly64x1_t b) { return vsri_n_p64(a, b, 33); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsriq_n_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsriq_n_p64(<2 x i64> %a, <2 x i64> %b) #1 { // CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8> // CHECK: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> diff --git a/clang/test/CodeGen/aarch64-strictfp-builtins.c b/clang/test/CodeGen/aarch64-strictfp-builtins.c index 73f6ba3053c400f317b7a1051af58449b4418c3a..3b2a4e547f4a6369962ab185b95ff5e443548454 100644 --- a/clang/test/CodeGen/aarch64-strictfp-builtins.c +++ b/clang/test/CodeGen/aarch64-strictfp-builtins.c @@ -15,7 +15,7 @@ int printf(const char *, ...); // CHECK-NEXT: store i32 [[X:%.*]], i32* [[X_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[STR_ADDR]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[X_ADDR]], align 4 -// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8*, ...) @printf(i8* noundef getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i8* noundef [[TMP0]], i32 noundef [[TMP1]]) [[ATTR4:#.*]] +// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i8* [[TMP0]], i32 [[TMP1]]) [[ATTR4:#.*]] // CHECK-NEXT: ret void // void p(char *str, int x) { @@ -33,7 +33,7 @@ void p(char *str, int x) { // CHECK-NEXT: [[SHL1:%.*]] = shl i128 [[BITCAST]], 1 // CHECK-NEXT: [[CMP:%.*]] = icmp eq i128 [[SHL1]], -10384593717069655257060992658440192 // CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_long_double_isinf(long double ld) { @@ -51,7 +51,7 @@ void test_long_double_isinf(long double ld) { // CHECK-NEXT: [[SHL1:%.*]] = shl i128 [[BITCAST]], 1 // CHECK-NEXT: [[CMP:%.*]] = icmp ult i128 [[SHL1]], -10384593717069655257060992658440192 // CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([13 x i8], [13 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_long_double_isfinite(long double ld) { @@ -70,7 +70,7 @@ void test_long_double_isfinite(long double ld) { // CHECK-NEXT: [[TMP1:%.*]] = sub i128 170135991163610696904058773219554885632, [[ABS]] // CHECK-NEXT: [[ISNAN:%.*]] = lshr i128 [[TMP1]], 127 // CHECK-NEXT: [[RES:%.*]] = trunc i128 [[ISNAN]] to i32 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[RES]]) +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) // CHECK-NEXT: ret void // void test_long_double_isnan(long double ld) { diff --git a/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c index a1eba9023b49f957a9a940814e6e520d16fa9107..9d3206a75f0ea718486c34ac7fba5aac06a481c3 100644 --- a/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c +++ b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c @@ -49,7 +49,7 @@ vec2048 x2048 = {0, 1, 2, 3, 3 , 2 , 1, 0, 0, 1, 2, 3, 3 , 2 , 1, 0, #if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS #define N __ARM_FEATURE_SVE_BITS typedef int8_t vec_int8 __attribute__((vector_size(N / 8))); -// CHECK128-LABEL: define{{.*}} <16 x i8> @f2(<16 x i8> noundef %x) +// CHECK128-LABEL: define{{.*}} <16 x i8> @f2(<16 x i8> %x) // CHECK128-NEXT: entry: // CHECK128-NEXT: [[TMP0:%.*]] = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) // CHECK128-NEXT: [[CASTSCALABLESVE:%.*]] = call @llvm.experimental.vector.insert.nxv16i8.v16i8( undef, <16 x i8> [[X:%.*]], i64 0) @@ -58,7 +58,7 @@ typedef int8_t vec_int8 __attribute__((vector_size(N / 8))); // CHECK128-NEXT: ret <16 x i8> [[CASTFIXEDSVE]] // CHECK-LABEL: define{{.*}} void @f2( -// CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noalias nocapture sret(<[[#div(VBITS,8)]] x i8>) align 16 %agg.result, <[[#div(VBITS,8)]] x i8>* nocapture noundef readonly %0) +// CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noalias nocapture sret(<[[#div(VBITS,8)]] x i8>) align 16 %agg.result, <[[#div(VBITS,8)]] x i8>* nocapture readonly %0) // CHECK-NEXT: entry: // CHECK-NEXT: [[X:%.*]] = load <[[#div(VBITS,8)]] x i8>, <[[#div(VBITS,8)]] x i8>* [[TMP0:%.*]], align 16, [[TBAA6:!tbaa !.*]] // CHECK-NEXT: [[TMP1:%.*]] = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) @@ -77,23 +77,23 @@ typedef int8_t vec1 __attribute__((vector_size(N / 8))); void f3(vec1); typedef svint8_t vec2 __attribute__((arm_sve_vector_bits(N))); -// CHECK128-LABEL: define{{.*}} void @g( noundef %x.coerce) +// CHECK128-LABEL: define{{.*}} void @g( %x.coerce) // CHECK128-NEXT: entry: // CHECK128-NEXT: [[X:%.*]] = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8( [[X_COERCE:%.*]], i64 0) -// CHECK128-NEXT: call void @f3(<16 x i8> noundef [[X]]) [[ATTR5:#.*]] +// CHECK128-NEXT: call void @f3(<16 x i8> [[X]]) [[ATTR5:#.*]] // CHECK128-NEXT: ret void -// CHECK-LABEL: define{{.*}} void @g( noundef %x.coerce) +// CHECK-LABEL: define{{.*}} void @g( %x.coerce) // CHECK-NEXT: entry: // CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca <[[#div(VBITS,8)]] x i8>, align 16 // CHECK-NEXT: [[X:%.*]] = call <[[#div(VBITS,8)]] x i8> @llvm.experimental.vector.extract.v[[#div(VBITS,8)]]i8.nxv16i8( [[X_COERCE:%.*]], i64 0) // CHECK-NEXT: store <[[#div(VBITS,8)]] x i8> [[X]], <[[#div(VBITS,8)]] x i8>* [[INDIRECT_ARG_TEMP]], align 16, [[TBAA6]] -// CHECK-NEXT: call void @f3(<[[#div(VBITS,8)]] x i8>* noundef nonnull [[INDIRECT_ARG_TEMP]]) [[ATTR5:#.*]] +// CHECK-NEXT: call void @f3(<[[#div(VBITS,8)]] x i8>* nonnull [[INDIRECT_ARG_TEMP]]) [[ATTR5:#.*]] // CHECK-NEXT: ret void -// CHECK128-LABEL: declare void @f3(<16 x i8> noundef) +// CHECK128-LABEL: declare void @f3(<16 x i8>) // CHECK-LABEL: declare void @f3( -// CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noundef) +// CHECK-SAME: <[[#div(VBITS,8)]] x i8>*) void g(vec2 x) { f3(x); } // OK #endif diff --git a/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp index 935eb8c61be730c60c1c8efabc40ec93464694f7..a808d50884ea2a141b49d17951691982cf9d0853 100644 --- a/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp +++ b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp @@ -46,7 +46,7 @@ void test02() { #define N __ARM_FEATURE_SVE_BITS // CHECK-LABEL: define{{.*}} @_Z1f9__SVE_VLSIu11__SVInt32_tLj // CHECK-SAME: [[#VBITS]] -// CHECK-SAME: EES_( noundef %x.coerce, noundef %y.coerce) +// CHECK-SAME: EES_( %x.coerce, %y.coerce) // CHECK-NEXT: entry: // CHECK-NEXT: [[X:%.*]] = call <[[#div(VBITS, 32)]] x i32> @llvm.experimental.vector.extract.v[[#div(VBITS, 32)]]i32.nxv4i32( [[X_COERCE:%.*]], i64 0) // CHECK-NEXT: [[Y:%.*]] = call <[[#div(VBITS, 32)]] x i32> @llvm.experimental.vector.extract.v[[#div(VBITS, 32)]]i32.nxv4i32( [[X_COERCE1:%.*]], i64 0) @@ -65,15 +65,15 @@ void f(vec1); typedef svint16_t vec2 __attribute__((arm_sve_vector_bits(N))); // CHECK-LABEL: define{{.*}} void @_Z1g9__SVE_VLSIu11__SVInt16_tLj // CHECK-SAME: [[#VBITS]] -// CHECK-SAME: EE( noundef %x.coerce) +// CHECK-SAME: EE( %x.coerce) // CHECK-NEXT: entry: // CHECK128-NEXT: [[X:%.*]] = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16( [[X_COERCE:%.*]], i64 0) -// CHECK128-NEXT: call void @_Z1fDv8_s(<8 x i16> noundef [[X]]) [[ATTR5:#.*]] +// CHECK128-NEXT: call void @_Z1fDv8_s(<8 x i16> [[X]]) [[ATTR5:#.*]] // CHECK128-NEXT: ret void // CHECKWIDE-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca <[[#div(VBITS, 16)]] x i16>, align 16 // CHECKWIDE-NEXT: [[X:%.*]] = call <[[#div(VBITS, 16)]] x i16> @llvm.experimental.vector.extract.v[[#div(VBITS, 16)]]i16.nxv8i16( [[X_COERCE:%.*]], i64 0) // CHECKWIDE-NEXT: store <[[#div(VBITS, 16)]] x i16> [[X]], <[[#div(VBITS, 16)]] x i16>* [[INDIRECT_ARG_TEMP]], align 16, [[TBAA6:!tbaa !.*]] -// CHECKWIDE-NEXT: call void @_Z1fDv[[#div(VBITS, 16)]]_s(<[[#div(VBITS, 16)]] x i16>* noundef nonnull [[INDIRECT_ARG_TEMP]]) [[ATTR5:#.*]] +// CHECKWIDE-NEXT: call void @_Z1fDv[[#div(VBITS, 16)]]_s(<[[#div(VBITS, 16)]] x i16>* nonnull [[INDIRECT_ARG_TEMP]]) [[ATTR5:#.*]] // CHECKWIDE-NEXT: ret void void g(vec2 x) { f(x); } // OK #endif diff --git a/clang/test/CodeGen/aarch64-varargs.c b/clang/test/CodeGen/aarch64-varargs.c index a0903432c8fed26a8c303679c3e3ee7910651115..397d61616b916fef0e12e5bebf2df4fc8b2b4867 100644 --- a/clang/test/CodeGen/aarch64-varargs.c +++ b/clang/test/CodeGen/aarch64-varargs.c @@ -885,7 +885,7 @@ overaligned_int128_struct_member overaligned_int128_struct_member_test() { } void check_start(int n, ...) { -// CHECK-LABEL: define{{.*}} void @check_start(i32 noundef %n, ...) +// CHECK-LABEL: define{{.*}} void @check_start(i32 %n, ...) va_list the_list; va_start(the_list, n); diff --git a/clang/test/CodeGen/address-space-field1.c b/clang/test/CodeGen/address-space-field1.c index 920cd75fc75599598b76bf022a85b89c5f19a281..fa3c5e095edcd6e04c0a5592d05a993e9cd4907e 100644 --- a/clang/test/CodeGen/address-space-field1.c +++ b/clang/test/CodeGen/address-space-field1.c @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -emit-llvm -triple x86_64-apple-darwin10 < %s -o - | FileCheck %s // CHECK:%struct.S = type { i32, i32 } -// CHECK:define{{.*}} void @test_addrspace(%struct.S addrspace(1)* noundef %p1, %struct.S addrspace(2)* noundef %p2) [[NUW:#[0-9]+]] +// CHECK:define{{.*}} void @test_addrspace(%struct.S addrspace(1)* %p1, %struct.S addrspace(2)* %p2) [[NUW:#[0-9]+]] // CHECK: [[p1addr:%.*]] = alloca %struct.S addrspace(1)* // CHECK: [[p2addr:%.*]] = alloca %struct.S addrspace(2)* // CHECK: store %struct.S addrspace(1)* %p1, %struct.S addrspace(1)** [[p1addr]] diff --git a/clang/test/CodeGen/address-space.c b/clang/test/CodeGen/address-space.c index f510a6d8449dc80ecad9b0925c592f61b7abaeef..0d894ad5885e149e8575a730398cfa109454fa37 100644 --- a/clang/test/CodeGen/address-space.c +++ b/clang/test/CodeGen/address-space.c @@ -14,7 +14,7 @@ int a __attribute__((address_space(0))); // CHECK: load i32, i32 addrspace(1)* @foo int test1() { return foo; } -// CHECK-LABEL: define{{.*}} i32 @test2(i32 noundef %i) +// CHECK-LABEL: define{{.*}} i32 @test2(i32 %i) // CHECK: load i32, i32 addrspace(1)* // CHECK-NEXT: ret i32 int test2(int i) { return ban[i]; } diff --git a/clang/test/CodeGen/aggregate-assign-call.c b/clang/test/CodeGen/aggregate-assign-call.c index d3736fc944999169a0b4b9b553b8f66d25357fe9..5aeaca19379a4b2022b6c5f6cf49539c53d3883e 100644 --- a/clang/test/CodeGen/aggregate-assign-call.c +++ b/clang/test/CodeGen/aggregate-assign-call.c @@ -1,7 +1,5 @@ -// RUN: %clang_cc1 -fexperimental-new-pass-manager -triple x86_64-unknown-linux-gnu -O1 -S -emit-llvm -o - %s | FileCheck %s --check-prefixes=O1 -// RUN: %clang_cc1 -fno-experimental-new-pass-manager -triple x86_64-unknown-linux-gnu -O1 -S -emit-llvm -o - %s | FileCheck %s --check-prefixes=O1 -// RUN: %clang_cc1 -fexperimental-new-pass-manager -triple x86_64-unknown-linux-gnu -O0 -S -emit-llvm -o - %s | FileCheck %s --check-prefix=O0 -// RUN: %clang_cc1 -fno-experimental-new-pass-manager -triple x86_64-unknown-linux-gnu -O0 -S -emit-llvm -o - %s | FileCheck %s --check-prefix=O0 +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -O1 -S -emit-llvm -o - %s | FileCheck %s --check-prefixes=O1 +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -O0 -S -emit-llvm -o - %s | FileCheck %s --check-prefix=O0 // // Ensure that we place appropriate lifetime markers around indirectly returned // temporaries, and that the lifetime.ends appear in a timely manner. diff --git a/clang/test/CodeGen/aix-alignment.c b/clang/test/CodeGen/aix-alignment.c index 27814d87a64958ca5ea0e5b08131d70c2a84b518..c8b14832a0b2941583746ded06e3406d9c3f38e3 100644 --- a/clang/test/CodeGen/aix-alignment.c +++ b/clang/test/CodeGen/aix-alignment.c @@ -15,22 +15,22 @@ typedef struct { // AIX: @d1 = global %struct.StructDouble zeroinitializer, align 8 StructDouble d1; -// AIX: double @retDouble(double noundef %x) +// AIX: double @retDouble(double %x) // AIX: %x.addr = alloca double, align 8 // AIX: store double %x, double* %x.addr, align 8 // AIX: load double, double* %x.addr, align 8 // AIX: ret double %0 double retDouble(double x) { return x; } -// AIX32: define void @bar(%struct.StructDouble* noalias sret(%struct.StructDouble) align 4 %agg.result, %struct.StructDouble* noundef byval(%struct.StructDouble) align 4 %x) -// AIX64: define void @bar(%struct.StructDouble* noalias sret(%struct.StructDouble) align 4 %agg.result, %struct.StructDouble* noundef byval(%struct.StructDouble) align 8 %x) +// AIX32: define void @bar(%struct.StructDouble* noalias sret(%struct.StructDouble) align 4 %agg.result, %struct.StructDouble* byval(%struct.StructDouble) align 4 %x) +// AIX64: define void @bar(%struct.StructDouble* noalias sret(%struct.StructDouble) align 4 %agg.result, %struct.StructDouble* byval(%struct.StructDouble) align 8 %x) // AIX: %0 = bitcast %struct.StructDouble* %agg.result to i8* // AIX: %1 = bitcast %struct.StructDouble* %x to i8* // AIX32: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 %1, i32 16, i1 false) // AIX64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %0, i8* align 8 %1, i64 16, i1 false) StructDouble bar(StructDouble x) { return x; } -// AIX: define void @foo(double* noundef %out, double* noundef %in) +// AIX: define void @foo(double* %out, double* %in) // AIX32: %0 = load double*, double** %in.addr, align 4 // AIX64: %0 = load double*, double** %in.addr, align 8 // AIX: %1 = load double, double* %0, align 4 diff --git a/clang/test/CodeGen/aix-altivec.c b/clang/test/CodeGen/aix-altivec.c index 9a2b2a543e1fb8e123359c44dfeb5bd53b28b381..011aa47b631776481dba838402cbc411f4ccc013 100644 --- a/clang/test/CodeGen/aix-altivec.c +++ b/clang/test/CodeGen/aix-altivec.c @@ -2,7 +2,7 @@ // RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-feature +altivec -target-cpu pwr8 -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -triple powerpc-unknown-aix -target-feature +altivec -target-cpu pwr8 -emit-llvm %s -o - | FileCheck %s vector float foo1(vector float x) { return x; } -// CHECK: define <4 x float> @foo1(<4 x float> noundef %x) [[ATTR:#[0-9]+]] { +// CHECK: define <4 x float> @foo1(<4 x float> %x) [[ATTR:#[0-9]+]] { // CHECK: entry: // CHECK: %x.addr = alloca <4 x float>, align 16 // CHECK: store <4 x float> %x, <4 x float>* %x.addr, align 16 @@ -10,7 +10,7 @@ vector float foo1(vector float x) { return x; } // CHECK: ret <4 x float> %0 // CHECK: } vector double foo2(vector double x) { return x; } -// CHECK: define <2 x double> @foo2(<2 x double> noundef %x) [[ATTR]] { +// CHECK: define <2 x double> @foo2(<2 x double> %x) [[ATTR]] { // CHECK: entry: // CHECK: %x.addr = alloca <2 x double>, align 16 // CHECK: store <2 x double> %x, <2 x double>* %x.addr, align 16 @@ -18,7 +18,7 @@ vector double foo2(vector double x) { return x; } // CHECK: ret <2 x double> %0 // CHECK: } vector int foo3(vector int x) { return x; } -// CHECK: define <4 x i32> @foo3(<4 x i32> noundef %x) [[ATTR]] { +// CHECK: define <4 x i32> @foo3(<4 x i32> %x) [[ATTR]] { // CHECK: entry: // CHECK: %x.addr = alloca <4 x i32>, align 16 // CHECK: store <4 x i32> %x, <4 x i32>* %x.addr, align 16 @@ -26,7 +26,7 @@ vector int foo3(vector int x) { return x; } // CHECK: ret <4 x i32> %0 // CHECK: } vector short int foo4(vector short int x) { return x; } -// CHECK: define <8 x i16> @foo4(<8 x i16> noundef %x) [[ATTR]] { +// CHECK: define <8 x i16> @foo4(<8 x i16> %x) [[ATTR]] { // CHECK: entry: // CHECK: %x.addr = alloca <8 x i16>, align 16 // CHECK: store <8 x i16> %x, <8 x i16>* %x.addr, align 16 @@ -34,7 +34,7 @@ vector short int foo4(vector short int x) { return x; } // CHECK: ret <8 x i16> %0 // CHECK: } vector char foo5(vector char x) { return x; } -// CHECK: define <16 x i8> @foo5(<16 x i8> noundef %x) [[ATTR]] { +// CHECK: define <16 x i8> @foo5(<16 x i8> %x) [[ATTR]] { // CHECK: entry: // CHECK: %x.addr = alloca <16 x i8>, align 16 // CHECK: store <16 x i8> %x, <16 x i8>* %x.addr, align 16 diff --git a/clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp b/clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp index 77783a534018314fa4fdd8b9226668a69191e80b..721a3df1e0e7aebc9e28f1770c375b97a01f4d67 100644 --- a/clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp +++ b/clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp @@ -56,18 +56,18 @@ void prambar() {} // VISIBILITY-IR: @b = protected global i32 0 // VISIBILITY-IR: @pramb = hidden global i32 0 -// VISIBILITY-IR: define hidden void @_Z5foo_hPi(i32* noundef %p) +// VISIBILITY-IR: define hidden void @_Z5foo_hPi(i32* %p) // VISIBILITY-IR: declare hidden void @_Z12zoo_extern_hv() // VISIBILITY-IR: define protected void @_Z3barv() -// VISIBILITY-IR: define linkonce_odr hidden noundef i32 @_ZNK9TestClass5valueEv(%class.TestClass* {{[^,]*}} %this) -// VISIBILITY-IR: define weak_odr protected noundef i32 @_ZN5basicIiE7getdataEv(%class.basic* {{[^,]*}} %this) +// VISIBILITY-IR: define linkonce_odr hidden i32 @_ZNK9TestClass5valueEv(%class.TestClass* {{[^,]*}} %this) +// VISIBILITY-IR: define weak_odr protected i32 @_ZN5basicIiE7getdataEv(%class.basic* {{[^,]*}} %this) // VISIBILITY-IR: define hidden void @_Z7prambarv() // NOVISIBILITY-IR: @b = global i32 0 // NOVISIBILITY-IR: @pramb = global i32 0 -// NOVISIBILITY-IR: define void @_Z5foo_hPi(i32* noundef %p) +// NOVISIBILITY-IR: define void @_Z5foo_hPi(i32* %p) // NOVISIBILITY-IR: declare void @_Z12zoo_extern_hv() // NOVISIBILITY-IR: define void @_Z3barv() -// NOVISIBILITY-IR: define linkonce_odr noundef i32 @_ZNK9TestClass5valueEv(%class.TestClass* {{[^,]*}} %this) -// NOVISIBILITY-IR: define weak_odr noundef i32 @_ZN5basicIiE7getdataEv(%class.basic* {{[^,]*}} %this) +// NOVISIBILITY-IR: define linkonce_odr i32 @_ZNK9TestClass5valueEv(%class.TestClass* {{[^,]*}} %this) +// NOVISIBILITY-IR: define weak_odr i32 @_ZN5basicIiE7getdataEv(%class.basic* {{[^,]*}} %this) // NOVISIBILITY-IR: define void @_Z7prambarv() diff --git a/clang/test/CodeGen/aix-return.c b/clang/test/CodeGen/aix-return.c index 20c03cd94dcf1f57b9870707d7c23bf8837052e7..87a2b85d4e94a129caa01ec6ffc9681c1d673c7e 100644 --- a/clang/test/CodeGen/aix-return.c +++ b/clang/test/CodeGen/aix-return.c @@ -7,27 +7,27 @@ // AIX-LABEL: define void @retVoid() void retVoid(void) {} -// AIX-LABEL: define signext i8 @retChar(i8 noundef signext %x) +// AIX-LABEL: define signext i8 @retChar(i8 signext %x) char retChar(char x) { return x; } -// AIX-LABEL: define signext i16 @retShort(i16 noundef signext %x) +// AIX-LABEL: define signext i16 @retShort(i16 signext %x) short retShort(short x) { return x; } -// AIX32-LABEL: define i32 @retInt(i32 noundef %x) -// AIX64-LABEL: define signext i32 @retInt(i32 noundef signext %x) +// AIX32-LABEL: define i32 @retInt(i32 %x) +// AIX64-LABEL: define signext i32 @retInt(i32 signext %x) int retInt(int x) { return 1; } -// AIX-LABEL: define i64 @retLongLong(i64 noundef %x) +// AIX-LABEL: define i64 @retLongLong(i64 %x) long long retLongLong(long long x) { return x; } -// AIX-LABEL: define signext i8 @retEnumChar(i8 noundef signext %x) +// AIX-LABEL: define signext i8 @retEnumChar(i8 signext %x) enum EnumChar : char { IsChar }; enum EnumChar retEnumChar(enum EnumChar x) { return x; } -// AIX32-LABEL: define i32 @retEnumInt(i32 noundef %x) -// AIX64-LABEL: define signext i32 @retEnumInt(i32 noundef signext %x) +// AIX32-LABEL: define i32 @retEnumInt(i32 %x) +// AIX64-LABEL: define signext i32 @retEnumInt(i32 signext %x) enum EnumInt : int { IsInt }; enum EnumInt retEnumInt(enum EnumInt x) { return x; diff --git a/clang/test/CodeGen/aix-struct-arg.c b/clang/test/CodeGen/aix-struct-arg.c index 3e375fa2e815ffeb0eafe6ffb7f3b2c69ff524ac..9524bef9eaa1ff67f435fc4115ba7deaeaa54c0d 100644 --- a/clang/test/CodeGen/aix-struct-arg.c +++ b/clang/test/CodeGen/aix-struct-arg.c @@ -38,52 +38,52 @@ typedef struct { vector signed int vsi; } StructVector; -// AIX32-LABEL: define void @arg0(%struct.Zero* noundef byval(%struct.Zero) align 4 %x) -// AIX64-LABEL: define void @arg0(%struct.Zero* noundef byval(%struct.Zero) align 8 %x) +// AIX32-LABEL: define void @arg0(%struct.Zero* byval(%struct.Zero) align 4 %x) +// AIX64-LABEL: define void @arg0(%struct.Zero* byval(%struct.Zero) align 8 %x) void arg0(Zero x) {} -// AIX32-LABEL: define void @arg1(%struct.One* noundef byval(%struct.One) align 4 %x) -// AIX64-LABEL: define void @arg1(%struct.One* noundef byval(%struct.One) align 8 %x) +// AIX32-LABEL: define void @arg1(%struct.One* byval(%struct.One) align 4 %x) +// AIX64-LABEL: define void @arg1(%struct.One* byval(%struct.One) align 8 %x) void arg1(One x) {} -// AIX32-LABEL: define void @arg2(%struct.Two* noundef byval(%struct.Two) align 4 %x) -// AIX64-LABEL: define void @arg2(%struct.Two* noundef byval(%struct.Two) align 8 %x) +// AIX32-LABEL: define void @arg2(%struct.Two* byval(%struct.Two) align 4 %x) +// AIX64-LABEL: define void @arg2(%struct.Two* byval(%struct.Two) align 8 %x) void arg2(Two x) {} -// AIX32-LABEL: define void @arg3(%struct.Three* noundef byval(%struct.Three) align 4 %x) -// AIX64-LABEL: define void @arg3(%struct.Three* noundef byval(%struct.Three) align 8 %x) +// AIX32-LABEL: define void @arg3(%struct.Three* byval(%struct.Three) align 4 %x) +// AIX64-LABEL: define void @arg3(%struct.Three* byval(%struct.Three) align 8 %x) void arg3(Three x) {} -// AIX32-LABEL: define void @arg4(%struct.Four* noundef byval(%struct.Four) align 4 %x) -// AIX64-LABEL: define void @arg4(%struct.Four* noundef byval(%struct.Four) align 8 %x) +// AIX32-LABEL: define void @arg4(%struct.Four* byval(%struct.Four) align 4 %x) +// AIX64-LABEL: define void @arg4(%struct.Four* byval(%struct.Four) align 8 %x) void arg4(Four x) {} -// AIX32-LABEL: define void @arg5(%struct.Five* noundef byval(%struct.Five) align 4 %x) -// AIX64-LABEL: define void @arg5(%struct.Five* noundef byval(%struct.Five) align 8 %x) +// AIX32-LABEL: define void @arg5(%struct.Five* byval(%struct.Five) align 4 %x) +// AIX64-LABEL: define void @arg5(%struct.Five* byval(%struct.Five) align 8 %x) void arg5(Five x) {} -// AIX32-LABEL: define void @arg6(%struct.Six* noundef byval(%struct.Six) align 4 %x) -// AIX64-LABEL: define void @arg6(%struct.Six* noundef byval(%struct.Six) align 8 %x) +// AIX32-LABEL: define void @arg6(%struct.Six* byval(%struct.Six) align 4 %x) +// AIX64-LABEL: define void @arg6(%struct.Six* byval(%struct.Six) align 8 %x) void arg6(Six x) {} -// AIX32-LABEL: define void @arg7(%struct.Seven* noundef byval(%struct.Seven) align 4 %x) -// AIX64-LABEL: define void @arg7(%struct.Seven* noundef byval(%struct.Seven) align 8 %x) +// AIX32-LABEL: define void @arg7(%struct.Seven* byval(%struct.Seven) align 4 %x) +// AIX64-LABEL: define void @arg7(%struct.Seven* byval(%struct.Seven) align 8 %x) void arg7(Seven x) {} -// AIX32-LABEL: define void @arg8(%struct.Eight* noundef byval(%struct.Eight) align 4 %0) +// AIX32-LABEL: define void @arg8(%struct.Eight* byval(%struct.Eight) align 4 %0) // AIX32: %x = alloca %struct.Eight, align 8 // AIX32: call void @llvm.memcpy.p0i8.p0i8.i32 -// AIX64-LABEL: define void @arg8(%struct.Eight* noundef byval(%struct.Eight) align 8 %x) +// AIX64-LABEL: define void @arg8(%struct.Eight* byval(%struct.Eight) align 8 %x) void arg8(Eight x) {} -// AIX32-LABEL: define void @arg9(%struct.OverAligned* noundef byval(%struct.OverAligned) align 4 %0) +// AIX32-LABEL: define void @arg9(%struct.OverAligned* byval(%struct.OverAligned) align 4 %0) // AIX32: %x = alloca %struct.OverAligned, align 32 // AIX32: call void @llvm.memcpy.p0i8.p0i8.i32 -// AIX64-LABEL: define void @arg9(%struct.OverAligned* noundef byval(%struct.OverAligned) align 8 %0) +// AIX64-LABEL: define void @arg9(%struct.OverAligned* byval(%struct.OverAligned) align 8 %0) // AIX64: %x = alloca %struct.OverAligned, align 32 // AIX64: call void @llvm.memcpy.p0i8.p0i8.i64 void arg9(OverAligned x) {} -// AIX32-LABEL: define void @arg10(%struct.StructVector* noundef byval(%struct.StructVector) align 16 %x) -// AIX64-LABEL: define void @arg10(%struct.StructVector* noundef byval(%struct.StructVector) align 16 %x) +// AIX32-LABEL: define void @arg10(%struct.StructVector* byval(%struct.StructVector) align 16 %x) +// AIX64-LABEL: define void @arg10(%struct.StructVector* byval(%struct.StructVector) align 16 %x) void arg10(StructVector x) {} diff --git a/clang/test/CodeGen/aix-vaargs.c b/clang/test/CodeGen/aix-vaargs.c index 4816954c4d01a89795f4e94ec4648276903107e8..23e7a9d65e2cff0b511d47546d1be1082ed57e28 100644 --- a/clang/test/CodeGen/aix-vaargs.c +++ b/clang/test/CodeGen/aix-vaargs.c @@ -19,8 +19,8 @@ void testva (int n, ...) { __builtin_va_end(ap); } -// AIX32: define void @testva(i32 noundef %n, ...) -// AIX64: define void @testva(i32 noundef signext %n, ...) +// AIX32: define void @testva(i32 %n, ...) +// AIX64: define void @testva(i32 signext %n, ...) // CHECK-NEXT: entry: // CHECK-NEXT: %n.addr = alloca i32, align 4 diff --git a/clang/test/CodeGen/alias.c b/clang/test/CodeGen/alias.c index 0f2ca306012ef2da12147ab01b9a27edbcb7026a..62161aebdbd328c78b84651ce1ca3175672e61e7 100644 --- a/clang/test/CodeGen/alias.c +++ b/clang/test/CodeGen/alias.c @@ -72,16 +72,16 @@ static int inner_weak(int a) { return 0; } extern __typeof(inner) inner_a __attribute__((alias("inner"))); static __typeof(inner_weak) inner_weak_a __attribute__((weakref, alias("inner_weak"))); // CHECKCC: @inner_a ={{.*}} alias i32 (i32), i32 (i32)* @inner -// CHECKCC: define internal arm_aapcs_vfpcc i32 @inner(i32 noundef %a) [[NUW:#[0-9]+]] { +// CHECKCC: define internal arm_aapcs_vfpcc i32 @inner(i32 %a) [[NUW:#[0-9]+]] { int outer(int a) { return inner(a); } -// CHECKCC: define{{.*}} arm_aapcs_vfpcc i32 @outer(i32 noundef %a) [[NUW]] { -// CHECKCC: call arm_aapcs_vfpcc i32 @inner(i32 noundef %{{.*}}) +// CHECKCC: define{{.*}} arm_aapcs_vfpcc i32 @outer(i32 %a) [[NUW]] { +// CHECKCC: call arm_aapcs_vfpcc i32 @inner(i32 %{{.*}}) int outer_weak(int a) { return inner_weak_a(a); } -// CHECKCC: define{{.*}} arm_aapcs_vfpcc i32 @outer_weak(i32 noundef %a) [[NUW]] { -// CHECKCC: call arm_aapcs_vfpcc i32 @inner_weak(i32 noundef %{{.*}}) -// CHECKCC: define internal arm_aapcs_vfpcc i32 @inner_weak(i32 noundef %a) [[NUW]] { +// CHECKCC: define{{.*}} arm_aapcs_vfpcc i32 @outer_weak(i32 %a) [[NUW]] { +// CHECKCC: call arm_aapcs_vfpcc i32 @inner_weak(i32 %{{.*}}) +// CHECKCC: define internal arm_aapcs_vfpcc i32 @inner_weak(i32 %a) [[NUW]] { // CHECKBASIC: attributes [[NUW]] = { noinline nounwind{{.*}} } diff --git a/clang/test/CodeGen/align_value.cpp b/clang/test/CodeGen/align_value.cpp index 4565b849530fea2a9376d89fca988bbcccf09c21..a18cb651fe4c0cdd7601978b625dbac49c3295e4 100644 --- a/clang/test/CodeGen/align_value.cpp +++ b/clang/test/CodeGen/align_value.cpp @@ -3,14 +3,15 @@ typedef double * __attribute__((align_value(64))) aligned_double; -// CHECK-LABEL: @_Z3fooPdS_Rd( +// CHECK-LABEL: define {{[^@]+}}@_Z3fooPdS_Rd +// CHECK-SAME: (double* align 64 [[X:%.*]], double* align 32 [[Y:%.*]], double* nonnull align 128 dereferenceable(8) [[Z:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[X_ADDR:%.*]] = alloca double*, align 8 // CHECK-NEXT: [[Y_ADDR:%.*]] = alloca double*, align 8 // CHECK-NEXT: [[Z_ADDR:%.*]] = alloca double*, align 8 -// CHECK-NEXT: store double* [[X:%.*]], double** [[X_ADDR]], align 8 -// CHECK-NEXT: store double* [[Y:%.*]], double** [[Y_ADDR]], align 8 -// CHECK-NEXT: store double* [[Z:%.*]], double** [[Z_ADDR]], align 8 +// CHECK-NEXT: store double* [[X]], double** [[X_ADDR]], align 8 +// CHECK-NEXT: store double* [[Y]], double** [[Y_ADDR]], align 8 +// CHECK-NEXT: store double* [[Z]], double** [[Z_ADDR]], align 8 // CHECK-NEXT: ret void // void foo(aligned_double x, double * y __attribute__((align_value(32))), @@ -20,10 +21,11 @@ struct ad_struct { aligned_double a; }; -// CHECK-LABEL: @_Z3fooR9ad_struct( +// CHECK-LABEL: define {{[^@]+}}@_Z3fooR9ad_struct +// CHECK-SAME: (%struct.ad_struct* nonnull align 8 dereferenceable(8) [[X:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[X_ADDR:%.*]] = alloca %struct.ad_struct*, align 8 -// CHECK-NEXT: store %struct.ad_struct* [[X:%.*]], %struct.ad_struct** [[X_ADDR]], align 8 +// CHECK-NEXT: store %struct.ad_struct* [[X]], %struct.ad_struct** [[X_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load %struct.ad_struct*, %struct.ad_struct** [[X_ADDR]], align 8 // CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_AD_STRUCT:%.*]], %struct.ad_struct* [[TMP0]], i32 0, i32 0 // CHECK-NEXT: [[TMP1:%.*]] = load double*, double** [[A]], align 8 @@ -35,10 +37,11 @@ double *foo(ad_struct& x) { return x.a; } -// CHECK-LABEL: @_Z3gooP9ad_struct( +// CHECK-LABEL: define {{[^@]+}}@_Z3gooP9ad_struct +// CHECK-SAME: (%struct.ad_struct* [[X:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[X_ADDR:%.*]] = alloca %struct.ad_struct*, align 8 -// CHECK-NEXT: store %struct.ad_struct* [[X:%.*]], %struct.ad_struct** [[X_ADDR]], align 8 +// CHECK-NEXT: store %struct.ad_struct* [[X]], %struct.ad_struct** [[X_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load %struct.ad_struct*, %struct.ad_struct** [[X_ADDR]], align 8 // CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_AD_STRUCT:%.*]], %struct.ad_struct* [[TMP0]], i32 0, i32 0 // CHECK-NEXT: [[TMP1:%.*]] = load double*, double** [[A]], align 8 @@ -50,10 +53,11 @@ double *goo(ad_struct *x) { return x->a; } -// CHECK-LABEL: @_Z3barPPd( +// CHECK-LABEL: define {{[^@]+}}@_Z3barPPd +// CHECK-SAME: (double** [[X:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[X_ADDR:%.*]] = alloca double**, align 8 -// CHECK-NEXT: store double** [[X:%.*]], double*** [[X_ADDR]], align 8 +// CHECK-NEXT: store double** [[X]], double*** [[X_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load double**, double*** [[X_ADDR]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = load double*, double** [[TMP0]], align 8 // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[TMP1]], i64 64) ] @@ -64,10 +68,11 @@ double *bar(aligned_double *x) { return *x; } -// CHECK-LABEL: @_Z3carRPd( +// CHECK-LABEL: define {{[^@]+}}@_Z3carRPd +// CHECK-SAME: (double** nonnull align 8 dereferenceable(8) [[X:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[X_ADDR:%.*]] = alloca double**, align 8 -// CHECK-NEXT: store double** [[X:%.*]], double*** [[X_ADDR]], align 8 +// CHECK-NEXT: store double** [[X]], double*** [[X_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load double**, double*** [[X_ADDR]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = load double*, double** [[TMP0]], align 8 // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[TMP1]], i64 64) ] @@ -78,10 +83,11 @@ double *car(aligned_double &x) { return x; } -// CHECK-LABEL: @_Z3darPPd( +// CHECK-LABEL: define {{[^@]+}}@_Z3darPPd +// CHECK-SAME: (double** [[X:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[X_ADDR:%.*]] = alloca double**, align 8 -// CHECK-NEXT: store double** [[X:%.*]], double*** [[X_ADDR]], align 8 +// CHECK-NEXT: store double** [[X]], double*** [[X_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load double**, double*** [[X_ADDR]], align 8 // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double*, double** [[TMP0]], i64 5 // CHECK-NEXT: [[TMP1:%.*]] = load double*, double** [[ARRAYIDX]], align 8 @@ -94,9 +100,9 @@ double *dar(aligned_double *x) { } aligned_double eep(); -// CHECK-LABEL: @_Z3retv( +// CHECK-LABEL: define {{[^@]+}}@_Z3retv() #0 // CHECK-NEXT: entry: -// CHECK-NEXT: [[CALL:%.*]] = call noundef double* @_Z3eepv() +// CHECK-NEXT: [[CALL:%.*]] = call double* @_Z3eepv() // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[CALL]], i64 64) ] // CHECK-NEXT: ret double* [[CALL]] // @@ -105,10 +111,11 @@ double *ret() { return eep(); } -// CHECK-LABEL: @_Z3no1PPd( +// CHECK-LABEL: define {{[^@]+}}@_Z3no1PPd +// CHECK-SAME: (double** [[X:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[X_ADDR:%.*]] = alloca double**, align 8 -// CHECK-NEXT: store double** [[X:%.*]], double*** [[X_ADDR]], align 8 +// CHECK-NEXT: store double** [[X]], double*** [[X_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load double**, double*** [[X_ADDR]], align 8 // CHECK-NEXT: ret double** [[TMP0]] // @@ -116,10 +123,11 @@ double **no1(aligned_double *x) { return x; } -// CHECK-LABEL: @_Z3no2RPd( +// CHECK-LABEL: define {{[^@]+}}@_Z3no2RPd +// CHECK-SAME: (double** nonnull align 8 dereferenceable(8) [[X:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[X_ADDR:%.*]] = alloca double**, align 8 -// CHECK-NEXT: store double** [[X:%.*]], double*** [[X_ADDR]], align 8 +// CHECK-NEXT: store double** [[X]], double*** [[X_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load double**, double*** [[X_ADDR]], align 8 // CHECK-NEXT: ret double** [[TMP0]] // @@ -127,10 +135,11 @@ double *&no2(aligned_double &x) { return x; } -// CHECK-LABEL: @_Z3no3RPd( +// CHECK-LABEL: define {{[^@]+}}@_Z3no3RPd +// CHECK-SAME: (double** nonnull align 8 dereferenceable(8) [[X:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[X_ADDR:%.*]] = alloca double**, align 8 -// CHECK-NEXT: store double** [[X:%.*]], double*** [[X_ADDR]], align 8 +// CHECK-NEXT: store double** [[X]], double*** [[X_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load double**, double*** [[X_ADDR]], align 8 // CHECK-NEXT: ret double** [[TMP0]] // @@ -138,10 +147,11 @@ double **no3(aligned_double &x) { return &x; } -// CHECK-LABEL: @_Z3no3Pd( +// CHECK-LABEL: define {{[^@]+}}@_Z3no3Pd +// CHECK-SAME: (double* align 64 [[X:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[X_ADDR:%.*]] = alloca double*, align 8 -// CHECK-NEXT: store double* [[X:%.*]], double** [[X_ADDR]], align 8 +// CHECK-NEXT: store double* [[X]], double** [[X_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load double*, double** [[X_ADDR]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[TMP0]], align 8 // CHECK-NEXT: ret double [[TMP1]] @@ -150,10 +160,11 @@ double no3(aligned_double x) { return *x; } -// CHECK-LABEL: @_Z3no4Pd( +// CHECK-LABEL: define {{[^@]+}}@_Z3no4Pd +// CHECK-SAME: (double* align 64 [[X:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[X_ADDR:%.*]] = alloca double*, align 8 -// CHECK-NEXT: store double* [[X:%.*]], double** [[X_ADDR]], align 8 +// CHECK-NEXT: store double* [[X]], double** [[X_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load double*, double** [[X_ADDR]], align 8 // CHECK-NEXT: ret double* [[TMP0]] // diff --git a/clang/test/CodeGen/alloc-align-attr.c b/clang/test/CodeGen/alloc-align-attr.c index f769f5e57b60eb73b8e4250fa713941df3228128..44a57291b47c859e054999a0a6efcd511ccec164 100644 --- a/clang/test/CodeGen/alloc-align-attr.c +++ b/clang/test/CodeGen/alloc-align-attr.c @@ -4,12 +4,13 @@ __INT32_TYPE__*m1(__INT32_TYPE__ i) __attribute__((alloc_align(1))); // Condition where parameter to m1 is not size_t. -// CHECK-LABEL: @test1( +// CHECK-LABEL: define {{[^@]+}}@test1 +// CHECK-SAME: (i32 [[A:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK-NEXT: [[CALL:%.*]] = call i32* @m1(i32 noundef [[TMP0]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32* @m1(i32 [[TMP0]]) // CHECK-NEXT: [[CASTED_ALIGN:%.*]] = zext i32 [[TMP0]] to i64 // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[CALL]], i64 [[CASTED_ALIGN]]) ] // CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[CALL]], align 4 @@ -19,13 +20,14 @@ __INT32_TYPE__ test1(__INT32_TYPE__ a) { return *m1(a); } // Condition where test2 param needs casting. -// CHECK-LABEL: @test2( +// CHECK-LABEL: define {{[^@]+}}@test2 +// CHECK-SAME: (i64 [[A:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 +// CHECK-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 // CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK-NEXT: [[CALL:%.*]] = call i32* @m1(i32 noundef [[CONV]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32* @m1(i32 [[CONV]]) // CHECK-NEXT: [[CASTED_ALIGN:%.*]] = zext i32 [[CONV]] to i64 // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[CALL]], i64 [[CASTED_ALIGN]]) ] // CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[CALL]], align 4 @@ -37,13 +39,14 @@ __INT32_TYPE__ test2(__SIZE_TYPE__ a) { __INT32_TYPE__ *m2(__SIZE_TYPE__ i) __attribute__((alloc_align(1))); // test3 param needs casting, but 'm2' is correct. -// CHECK-LABEL: @test3( +// CHECK-LABEL: define {{[^@]+}}@test3 +// CHECK-SAME: (i32 [[A:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64 -// CHECK-NEXT: [[CALL:%.*]] = call i32* @m2(i64 noundef [[CONV]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32* @m2(i64 [[CONV]]) // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[CALL]], i64 [[CONV]]) ] // CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[CALL]], align 4 // CHECK-NEXT: ret i32 [[TMP1]] @@ -53,12 +56,13 @@ __INT32_TYPE__ test3(__INT32_TYPE__ a) { } // Every type matches, canonical example. -// CHECK-LABEL: @test4( +// CHECK-LABEL: define {{[^@]+}}@test4 +// CHECK-SAME: (i64 [[A:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 +// CHECK-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK-NEXT: [[CALL:%.*]] = call i32* @m2(i64 noundef [[TMP0]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32* @m2(i64 [[TMP0]]) // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[CALL]], i64 [[TMP0]]) ] // CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[CALL]], align 4 // CHECK-NEXT: ret i32 [[TMP1]] @@ -73,7 +77,8 @@ struct MultiArgs { __INT64_TYPE__ a, b;}; // Struct parameter doesn't take up an IR parameter, 'i' takes up 2. // Truncation to i64 is permissible, since alignments of greater than 2^64 are insane. __INT32_TYPE__ *m3(struct Empty s, __int128_t i) __attribute__((alloc_align(2))); -// CHECK-LABEL: @test5( +// CHECK-LABEL: define {{[^@]+}}@test5 +// CHECK-SAME: (i64 [[A_COERCE0:%.*]], i64 [[A_COERCE1:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[A:%.*]] = alloca i128, align 16 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i128, align 16 @@ -81,9 +86,9 @@ __INT32_TYPE__ *m3(struct Empty s, __int128_t i) __attribute__((alloc_align(2))) // CHECK-NEXT: [[COERCE:%.*]] = alloca i128, align 16 // CHECK-NEXT: [[TMP0:%.*]] = bitcast i128* [[A]] to { i64, i64 }* // CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* [[TMP0]], i32 0, i32 0 -// CHECK-NEXT: store i64 [[A_COERCE0:%.*]], i64* [[TMP1]], align 16 +// CHECK-NEXT: store i64 [[A_COERCE0]], i64* [[TMP1]], align 16 // CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* [[TMP0]], i32 0, i32 1 -// CHECK-NEXT: store i64 [[A_COERCE1:%.*]], i64* [[TMP2]], align 8 +// CHECK-NEXT: store i64 [[A_COERCE1]], i64* [[TMP2]], align 8 // CHECK-NEXT: [[A1:%.*]] = load i128, i128* [[A]], align 16 // CHECK-NEXT: store i128 [[A1]], i128* [[A_ADDR]], align 16 // CHECK-NEXT: [[TMP3:%.*]] = load i128, i128* [[A_ADDR]], align 16 @@ -93,7 +98,7 @@ __INT32_TYPE__ *m3(struct Empty s, __int128_t i) __attribute__((alloc_align(2))) // CHECK-NEXT: [[TMP6:%.*]] = load i64, i64* [[TMP5]], align 16 // CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* [[TMP4]], i32 0, i32 1 // CHECK-NEXT: [[TMP8:%.*]] = load i64, i64* [[TMP7]], align 8 -// CHECK-NEXT: [[CALL:%.*]] = call i32* @m3(i64 noundef [[TMP6]], i64 noundef [[TMP8]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32* @m3(i64 [[TMP6]], i64 [[TMP8]]) // CHECK-NEXT: [[CASTED_ALIGN:%.*]] = trunc i128 [[TMP3]] to i64 // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[CALL]], i64 [[CASTED_ALIGN]]) ] // CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[CALL]], align 4 @@ -105,7 +110,8 @@ __INT32_TYPE__ test5(__int128_t a) { } // Struct parameter takes up 2 parameters, 'i' takes up 2. __INT32_TYPE__ *m4(struct MultiArgs s, __int128_t i) __attribute__((alloc_align(2))); -// CHECK-LABEL: @test6( +// CHECK-LABEL: define {{[^@]+}}@test6 +// CHECK-SAME: (i64 [[A_COERCE0:%.*]], i64 [[A_COERCE1:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[A:%.*]] = alloca i128, align 16 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i128, align 16 @@ -113,9 +119,9 @@ __INT32_TYPE__ *m4(struct MultiArgs s, __int128_t i) __attribute__((alloc_align( // CHECK-NEXT: [[COERCE:%.*]] = alloca i128, align 16 // CHECK-NEXT: [[TMP0:%.*]] = bitcast i128* [[A]] to { i64, i64 }* // CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* [[TMP0]], i32 0, i32 0 -// CHECK-NEXT: store i64 [[A_COERCE0:%.*]], i64* [[TMP1]], align 16 +// CHECK-NEXT: store i64 [[A_COERCE0]], i64* [[TMP1]], align 16 // CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* [[TMP0]], i32 0, i32 1 -// CHECK-NEXT: store i64 [[A_COERCE1:%.*]], i64* [[TMP2]], align 8 +// CHECK-NEXT: store i64 [[A_COERCE1]], i64* [[TMP2]], align 8 // CHECK-NEXT: [[A1:%.*]] = load i128, i128* [[A]], align 16 // CHECK-NEXT: store i128 [[A1]], i128* [[A_ADDR]], align 16 // CHECK-NEXT: [[TMP3:%.*]] = load i128, i128* [[A_ADDR]], align 16 @@ -130,7 +136,7 @@ __INT32_TYPE__ *m4(struct MultiArgs s, __int128_t i) __attribute__((alloc_align( // CHECK-NEXT: [[TMP11:%.*]] = load i64, i64* [[TMP10]], align 16 // CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* [[TMP9]], i32 0, i32 1 // CHECK-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8 -// CHECK-NEXT: [[CALL:%.*]] = call i32* @m4(i64 [[TMP6]], i64 [[TMP8]], i64 noundef [[TMP11]], i64 noundef [[TMP13]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32* @m4(i64 [[TMP6]], i64 [[TMP8]], i64 [[TMP11]], i64 [[TMP13]]) // CHECK-NEXT: [[CASTED_ALIGN:%.*]] = trunc i128 [[TMP3]] to i64 // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[CALL]], i64 [[CASTED_ALIGN]]) ] // CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[CALL]], align 4 diff --git a/clang/test/CodeGen/alloc-fns-alignment.c b/clang/test/CodeGen/alloc-fns-alignment.c index 8ab0610accf03bb2db5d233e5ed35e7ef542119d..b19cf867f74c856fff0ec67217cca5563d31c167 100644 --- a/clang/test/CodeGen/alloc-fns-alignment.c +++ b/clang/test/CodeGen/alloc-fns-alignment.c @@ -48,7 +48,7 @@ void *aligned_alloc_large_constant_test(size_t n) { // ALIGN16: align 16 i8* @realloc // CHECK-LABEL: @aligned_alloc_variable_test -// ALIGN16: %[[ALLOCATED:.*]] = call align 16 i8* @aligned_alloc({{i32|i64}} noundef %[[ALIGN:.*]], {{i32|i64}} noundef %[[NBYTES:.*]]) +// ALIGN16: %[[ALLOCATED:.*]] = call align 16 i8* @aligned_alloc({{i32|i64}} %[[ALIGN:.*]], {{i32|i64}} %[[NBYTES:.*]]) // ALIGN16-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* %[[ALLOCATED]], {{i32|i64}} %[[ALIGN]]) ] // CHECK-LABEL: @aligned_alloc_constant_test diff --git a/clang/test/CodeGen/alloc-size-fnptr.c b/clang/test/CodeGen/alloc-size-fnptr.c index 495dc67b37b11ce65ec18b2983eefed17d0ea578..ff410c053f9f5ed2133443879f6b040ca32b73c0 100644 --- a/clang/test/CodeGen/alloc-size-fnptr.c +++ b/clang/test/CodeGen/alloc-size-fnptr.c @@ -14,9 +14,9 @@ extern void *my_calloc(int, int) __attribute__((alloc_size(1, 2))); // CHECK-LABEL: @call_direct void call_direct(void) { my_malloc(50); - // CHECK: call i8* @my_malloc(i32 noundef 50) [[DIRECT_MALLOC_ATTR:#[0-9]+]] + // CHECK: call i8* @my_malloc(i32 50) [[DIRECT_MALLOC_ATTR:#[0-9]+]] my_calloc(1, 16); - // CHECK: call i8* @my_calloc(i32 noundef 1, i32 noundef 16) [[DIRECT_CALLOC_ATTR:#[0-9]+]] + // CHECK: call i8* @my_calloc(i32 1, i32 16) [[DIRECT_CALLOC_ATTR:#[0-9]+]] } extern void *(*malloc_function_pointer)(void *, int)__attribute__((alloc_size(2))); @@ -26,10 +26,10 @@ extern void *(*calloc_function_pointer)(void *, int, int)__attribute__((alloc_si void call_function_pointer(void) { malloc_function_pointer(NULL, 100); // CHECK: [[MALLOC_FN_PTR:%.+]] = load i8* (i8*, i32)*, i8* (i8*, i32)** @malloc_function_pointer, align 8 - // CHECK: call i8* [[MALLOC_FN_PTR]](i8* noundef null, i32 noundef 100) [[INDIRECT_MALLOC_ATTR:#[0-9]+]] + // CHECK: call i8* [[MALLOC_FN_PTR]](i8* null, i32 100) [[INDIRECT_MALLOC_ATTR:#[0-9]+]] calloc_function_pointer(NULL, 2, 4); // CHECK: [[CALLOC_FN_PTR:%.+]] = load i8* (i8*, i32, i32)*, i8* (i8*, i32, i32)** @calloc_function_pointer, align 8 - // CHECK: call i8* [[CALLOC_FN_PTR]](i8* noundef null, i32 noundef 2, i32 noundef 4) [[INDIRECT_CALLOC_ATTR:#[0-9]+]] + // CHECK: call i8* [[CALLOC_FN_PTR]](i8* null, i32 2, i32 4) [[INDIRECT_CALLOC_ATTR:#[0-9]+]] } typedef void *(__attribute__((alloc_size(3))) * my_malloc_fn_pointer_type)(void *, void *, int); @@ -41,10 +41,10 @@ extern my_calloc_fn_pointer_type calloc_function_pointer_with_typedef; void call_function_pointer_typedef(void) { malloc_function_pointer_with_typedef(NULL, NULL, 200); // CHECK: [[INDIRECT_TYPEDEF_MALLOC_FN_PTR:%.+]] = load i8* (i8*, i8*, i32)*, i8* (i8*, i8*, i32)** @malloc_function_pointer_with_typedef, align 8 - // CHECK: call i8* [[INDIRECT_TYPEDEF_MALLOC_FN_PTR]](i8* noundef null, i8* noundef null, i32 noundef 200) [[INDIRECT_TYPEDEF_MALLOC_ATTR:#[0-9]+]] + // CHECK: call i8* [[INDIRECT_TYPEDEF_MALLOC_FN_PTR]](i8* null, i8* null, i32 200) [[INDIRECT_TYPEDEF_MALLOC_ATTR:#[0-9]+]] calloc_function_pointer_with_typedef(NULL, NULL, 8, 4); // CHECK: [[INDIRECT_TYPEDEF_CALLOC_FN_PTR:%.+]] = load i8* (i8*, i8*, i32, i32)*, i8* (i8*, i8*, i32, i32)** @calloc_function_pointer_with_typedef, align 8 - // CHECK: call i8* [[INDIRECT_TYPEDEF_CALLOC_FN_PTR]](i8* noundef null, i8* noundef null, i32 noundef 8, i32 noundef 4) [[INDIRECT_TYPEDEF_CALLOC_ATTR:#[0-9]+]] + // CHECK: call i8* [[INDIRECT_TYPEDEF_CALLOC_FN_PTR]](i8* null, i8* null, i32 8, i32 4) [[INDIRECT_TYPEDEF_CALLOC_ATTR:#[0-9]+]] } // CHECK: attributes [[DIRECT_MALLOC_ATTR]] = { allocsize(0) } diff --git a/clang/test/CodeGen/arc/arguments.c b/clang/test/CodeGen/arc/arguments.c index 9564f96d083be6e764383e554021c78f12104a8d..6a6250c624b017ccd763bfd9672ffd26642eb5d9 100644 --- a/clang/test/CodeGen/arc/arguments.c +++ b/clang/test/CodeGen/arc/arguments.c @@ -3,7 +3,7 @@ // Basic argument tests for ARC. -// CHECK: define{{.*}} void @f0(i32 inreg noundef %i, i32 inreg noundef %j, i64 inreg noundef %k) +// CHECK: define{{.*}} void @f0(i32 inreg %i, i32 inreg %j, i64 inreg %k) void f0(int i, long j, long long k) {} typedef struct { @@ -38,13 +38,13 @@ s3 f3() { return foo; } -// CHECK: define{{.*}} void @f4(i64 inreg noundef %i) +// CHECK: define{{.*}} void @f4(i64 inreg %i) void f4(long long i) {} -// CHECK: define{{.*}} void @f5(i8 inreg noundef signext %a, i16 inreg noundef signext %b) +// CHECK: define{{.*}} void @f5(i8 inreg signext %a, i16 inreg signext %b) void f5(signed char a, short b) {} -// CHECK: define{{.*}} void @f6(i8 inreg noundef zeroext %a, i16 inreg noundef zeroext %b) +// CHECK: define{{.*}} void @f6(i8 inreg zeroext %a, i16 inreg zeroext %b) void f6(unsigned char a, unsigned short b) {} enum my_enum { @@ -53,14 +53,14 @@ enum my_enum { ENUM3, }; // Enums should be treated as the underlying i32. -// CHECK: define{{.*}} void @f7(i32 inreg noundef %a) +// CHECK: define{{.*}} void @f7(i32 inreg %a) void f7(enum my_enum a) {} enum my_big_enum { ENUM4 = 0xFFFFFFFFFFFFFFFF, }; // Big enums should be treated as the underlying i64. -// CHECK: define{{.*}} void @f8(i64 inreg noundef %a) +// CHECK: define{{.*}} void @f8(i64 inreg %a) void f8(enum my_big_enum a) {} union simple_union { @@ -80,32 +80,32 @@ typedef struct { // CHECK: define{{.*}} void @f10(i32 inreg %bf1.coerce) void f10(bitfield1 bf1) {} -// CHECK: define{{.*}} inreg { float, float } @cplx1(float inreg noundef %r) +// CHECK: define{{.*}} inreg { float, float } @cplx1(float inreg %r) _Complex float cplx1(float r) { return r + 2.0fi; } -// CHECK: define{{.*}} inreg { double, double } @cplx2(double inreg noundef %r) +// CHECK: define{{.*}} inreg { double, double } @cplx2(double inreg %r) _Complex double cplx2(double r) { return r + 2.0i; } -// CHECK: define{{.*}} inreg { i32, i32 } @cplx3(i32 inreg noundef %r) +// CHECK: define{{.*}} inreg { i32, i32 } @cplx3(i32 inreg %r) _Complex int cplx3(int r) { return r + 2i; } -// CHECK: define{{.*}} inreg { i64, i64 } @cplx4(i64 inreg noundef %r) +// CHECK: define{{.*}} inreg { i64, i64 } @cplx4(i64 inreg %r) _Complex long long cplx4(long long r) { return r + 2i; } -// CHECK: define{{.*}} inreg { i8, i8 } @cplx6(i8 inreg noundef signext %r) +// CHECK: define{{.*}} inreg { i8, i8 } @cplx6(i8 inreg signext %r) _Complex signed char cplx6(signed char r) { return r + 2i; } -// CHECK: define{{.*}} inreg { i16, i16 } @cplx7(i16 inreg noundef signext %r) +// CHECK: define{{.*}} inreg { i16, i16 } @cplx7(i16 inreg signext %r) _Complex short cplx7(short r) { return r + 2i; } @@ -128,7 +128,7 @@ void st3(s16 a, s16 b, s16 c) {} // 1 sret + 1 i32 + 2*(i32 coerce) + 4*(i32 coerce) + 1 byval s16 st4(int x, s8 a, s16 b, s16 c) { return b; } -// CHECK: define{{.*}} void @st4(%struct.s16* noalias sret(%struct.s16) align 4 %agg.result, i32 inreg noundef %x, i32 inreg %a.coerce0, i32 inreg %a.coerce1, i32 inreg %b.coerce0, i32 inreg %b.coerce1, i32 inreg %b.coerce2, i32 inreg %b.coerce3, { i32, i32, i32, i32 } %c.coerce) +// CHECK: define{{.*}} void @st4(%struct.s16* noalias sret(%struct.s16) align 4 %agg.result, i32 inreg %x, i32 inreg %a.coerce0, i32 inreg %a.coerce1, i32 inreg %b.coerce0, i32 inreg %b.coerce1, i32 inreg %b.coerce2, i32 inreg %b.coerce3, { i32, i32, i32, i32 } %c.coerce) // 1 sret + 2*(i32 coerce) + 4*(i32 coerce) + 4*(i32 coerce) s16 st5(s8 a, s16 b, s16 c) { return b; } diff --git a/clang/test/CodeGen/arithmetic-fence-builtin.c b/clang/test/CodeGen/arithmetic-fence-builtin.c index 61d0b65277424267378fb31f9477ec5c304a29f7..6b5b5b4b9cefa8aa0e9a359d876358fdea57ba92 100644 --- a/clang/test/CodeGen/arithmetic-fence-builtin.c +++ b/clang/test/CodeGen/arithmetic-fence-builtin.c @@ -14,7 +14,7 @@ // int v; int addit(float a, float b) { - // CHECK: define {{.*}}@addit(float noundef %a, float noundef %b) #0 { + // CHECK: define {{.*}}@addit(float %a, float %b) #0 { _Complex double cd, cd1; cd = __arithmetic_fence(cd1); // CHECKFAST: call{{.*}} double @llvm.arithmetic.fence.f64({{.*}}real) @@ -57,18 +57,18 @@ int addit(float a, float b) { // CHECK-NEXT ret i32 0 } int addit1(int a, int b) { - // CHECK: define {{.*}}@addit1(i32 noundef %a, i32 noundef %b{{.*}} + // CHECK: define {{.*}}@addit1(i32 %a, i32 %b{{.*}} v = (a + b); - // CHECK-NOT: call{{.*}} float @llvm.arithmetic.fence.int(float noundef %add) + // CHECK-NOT: call{{.*}} float @llvm.arithmetic.fence.int(float %add) return 0; } #ifdef FAST #pragma float_control(precise, on) int subit(float a, float b, float *fp) { - // CHECKFAST: define {{.*}}@subit(float noundef %a, float noundef %b{{.*}} + // CHECKFAST: define {{.*}}@subit(float %a, float %b{{.*}} *fp = __arithmetic_fence(a - b); *fp = (a + b); - // CHECK-NOT: call{{.*}} float @llvm.arithmetic.fence.f32(float noundef %add) + // CHECK-NOT: call{{.*}} float @llvm.arithmetic.fence.f32(float %add) return 0; } #endif diff --git a/clang/test/CodeGen/arm-aapcs-vfp.c b/clang/test/CodeGen/arm-aapcs-vfp.c index b58f428e86db2ed6e4a2ea428dd8e53d22e3548e..1d10c7c36363f98395c555c3f8d2024fd3c0c73d 100644 --- a/clang/test/CodeGen/arm-aapcs-vfp.c +++ b/clang/test/CodeGen/arm-aapcs-vfp.c @@ -47,15 +47,15 @@ void test_array(struct nested_array arg) { } extern void complex_callee(__complex__ double); -// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_complex({ double, double } noundef %{{.*}}) -// CHECK64: define{{.*}} void @test_complex([2 x double] noundef %cd.coerce) +// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_complex({ double, double } %{{.*}}) +// CHECK64: define{{.*}} void @test_complex([2 x double] %cd.coerce) void test_complex(__complex__ double cd) { complex_callee(cd); } // Long double is the same as double on AAPCS, it should be homogeneous. extern void complex_long_callee(__complex__ long double); -// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_complex_long({ double, double } noundef %{{.*}}) +// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_complex_long({ double, double } %{{.*}}) void test_complex_long(__complex__ long double cd) { complex_callee(cd); } @@ -70,7 +70,7 @@ struct big_struct { float f4; }; // CHECK: define{{.*}} arm_aapcs_vfpcc void @test_big([5 x i32] %{{.*}}) -// CHECK64: define{{.*}} void @test_big(%struct.big_struct* noundef %{{.*}}) +// CHECK64: define{{.*}} void @test_big(%struct.big_struct* %{{.*}}) // CHECK64: call void @llvm.memcpy // CHECK64: call void @big_callee(%struct.big_struct* extern void big_callee(struct big_struct); @@ -114,36 +114,36 @@ void test_neon(struct neon_struct arg) { neon_callee(arg); } -// CHECK-LABEL: define{{.*}} arm_aapcs_vfpcc void @f33(%struct.s33* noundef byval(%struct.s33) align 4 %s) +// CHECK-LABEL: define{{.*}} arm_aapcs_vfpcc void @f33(%struct.s33* byval(%struct.s33) align 4 %s) struct s33 { char buf[32*32]; }; void f33(struct s33 s) { } typedef struct { long long x; int y; } struct_long_long_int; -// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_1(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, i32 noundef %j, i64 noundef %k, i32 noundef %l) +// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_1(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, i64 %k, i32 %l) void test_vfp_stack_gpr_split_1(double a, double b, double c, double d, double e, double f, double g, double h, double i, int j, long long k, int l) {} -// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_2(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, i32 noundef %j, [2 x i64] %k.coerce) +// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_2(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, [2 x i64] %k.coerce) void test_vfp_stack_gpr_split_2(double a, double b, double c, double d, double e, double f, double g, double h, double i, int j, struct_long_long_int k) {} -// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_3(%struct.struct_long_long_int* noalias sret(%struct.struct_long_long_int) align 8 %agg.result, double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, [2 x i64] %k.coerce) +// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_3(%struct.struct_long_long_int* noalias sret(%struct.struct_long_long_int) align 8 %agg.result, double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, [2 x i64] %k.coerce) struct_long_long_int test_vfp_stack_gpr_split_3(double a, double b, double c, double d, double e, double f, double g, double h, double i, struct_long_long_int k) {} typedef struct { int a; int b:4; int c; } struct_int_bitfield_int; -// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_test_vfp_stack_gpr_split_bitfield(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, i32 noundef %j, i32 noundef %k, [3 x i32] %l.coerce) +// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_test_vfp_stack_gpr_split_bitfield(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, i32 %k, [3 x i32] %l.coerce) void test_test_vfp_stack_gpr_split_bitfield(double a, double b, double c, double d, double e, double f, double g, double h, double i, int j, int k, struct_int_bitfield_int l) {} // Note: this struct requires internal padding typedef struct { int x; long long y; } struct_int_long_long; -// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_4(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, i32 noundef %j, [2 x i64] %k.coerce) +// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_4(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, [2 x i64] %k.coerce) void test_vfp_stack_gpr_split_4(double a, double b, double c, double d, double e, double f, double g, double h, double i, int j, struct_int_long_long k) {} // This very large struct (passed byval) uses up the GPRs, so no padding is needed typedef struct { int x[17]; } struct_seventeen_ints; typedef struct { int x[4]; } struct_four_ints; -// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_5(%struct.struct_seventeen_ints* noundef byval(%struct.struct_seventeen_ints) align 4 %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, double noundef %j, [4 x i32] %k.coerce) +// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_5(%struct.struct_seventeen_ints* byval(%struct.struct_seventeen_ints) align 4 %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, double %j, [4 x i32] %k.coerce) void test_vfp_stack_gpr_split_5(struct_seventeen_ints a, double b, double c, double d, double e, double f, double g, double h, double i, double j, struct_four_ints k) {} // Here, parameter k would need padding to prevent it from being split, but it // is passed ByVal (due to being > 64 bytes), so the backend handles this instead. void test_vfp_stack_gpr_split_6(double a, double b, double c, double d, double e, double f, double g, double h, double i, int j, struct_seventeen_ints k) {} -// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_6(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, i32 noundef %j, %struct.struct_seventeen_ints* noundef byval(%struct.struct_seventeen_ints) align 4 %k) +// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_6(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, %struct.struct_seventeen_ints* byval(%struct.struct_seventeen_ints) align 4 %k) diff --git a/clang/test/CodeGen/arm-abi-vector.c b/clang/test/CodeGen/arm-abi-vector.c index b01823edd35a47dcabc74811a92cb78c6acbcf57..8d113d6533e1819c32f3c329eb07c93e4e053a92 100644 --- a/clang/test/CodeGen/arm-abi-vector.c +++ b/clang/test/CodeGen/arm-abi-vector.c @@ -48,11 +48,11 @@ double varargs_vec_2i(int fixed, ...) { double test_2i(__int2 *in) { // CHECK: test_2i -// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_2i(i32 noundef 3, <2 x i32> noundef {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_2i(i32 3, <2 x i32> {{%.*}}) // APCS-GNU: test_2i -// APCS-GNU: call double (i32, ...) @varargs_vec_2i(i32 noundef 3, <2 x i32> noundef {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_vec_2i(i32 3, <2 x i32> {{%.*}}) // ANDROID: test_2i -// ANDROID: call double (i32, ...) @varargs_vec_2i(i32 noundef 3, <2 x i32> noundef {{%.*}}) +// ANDROID: call double (i32, ...) @varargs_vec_2i(i32 3, <2 x i32> {{%.*}}) return varargs_vec_2i(3, *in); } @@ -80,11 +80,11 @@ double varargs_vec_3c(int fixed, ...) { double test_3c(__char3 *in) { // CHECK: test_3c -// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_3c(i32 noundef 3, i32 {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_3c(i32 3, i32 {{%.*}}) // APCS-GNU: test_3c -// APCS-GNU: call double (i32, ...) @varargs_vec_3c(i32 noundef 3, i32 {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_vec_3c(i32 3, i32 {{%.*}}) // ANDROID: test_3c -// ANDROID: call double (i32, ...) @varargs_vec_3c(i32 noundef 3, <3 x i8> noundef {{%.*}}) +// ANDROID: call double (i32, ...) @varargs_vec_3c(i32 3, <3 x i8> {{%.*}}) return varargs_vec_3c(3, *in); } @@ -123,11 +123,11 @@ double varargs_vec_5c(int fixed, ...) { double test_5c(__char5 *in) { // CHECK: test_5c -// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_5c(i32 noundef 5, <2 x i32> {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_5c(i32 5, <2 x i32> {{%.*}}) // APCS-GNU: test_5c -// APCS-GNU: call double (i32, ...) @varargs_vec_5c(i32 noundef 5, <2 x i32> {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_vec_5c(i32 5, <2 x i32> {{%.*}}) // ANDROID: test_5c -// ANDROID: call double (i32, ...) @varargs_vec_5c(i32 noundef 5, <2 x i32> {{%.*}}) +// ANDROID: call double (i32, ...) @varargs_vec_5c(i32 5, <2 x i32> {{%.*}}) return varargs_vec_5c(5, *in); } @@ -166,11 +166,11 @@ double varargs_vec_9c(int fixed, ...) { double test_9c(__char9 *in) { // CHECK: test_9c -// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_9c(i32 noundef 9, <4 x i32> {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_9c(i32 9, <4 x i32> {{%.*}}) // APCS-GNU: test_9c -// APCS-GNU: call double (i32, ...) @varargs_vec_9c(i32 noundef 9, <4 x i32> {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_vec_9c(i32 9, <4 x i32> {{%.*}}) // ANDROID: test_9c -// ANDROID: call double (i32, ...) @varargs_vec_9c(i32 noundef 9, <4 x i32> {{%.*}}) +// ANDROID: call double (i32, ...) @varargs_vec_9c(i32 9, <4 x i32> {{%.*}}) return varargs_vec_9c(9, *in); } @@ -198,11 +198,11 @@ double varargs_vec_19c(int fixed, ...) { double test_19c(__char19 *in) { // CHECK: test_19c -// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_19c(i32 noundef 19, <19 x i8>* noundef {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_19c(i32 19, <19 x i8>* {{%.*}}) // APCS-GNU: test_19c -// APCS-GNU: call double (i32, ...) @varargs_vec_19c(i32 noundef 19, <19 x i8>* noundef {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_vec_19c(i32 19, <19 x i8>* {{%.*}}) // ANDROID: test_19c -// ANDROID: call double (i32, ...) @varargs_vec_19c(i32 noundef 19, <19 x i8>* noundef {{%.*}}) +// ANDROID: call double (i32, ...) @varargs_vec_19c(i32 19, <19 x i8>* {{%.*}}) return varargs_vec_19c(19, *in); } @@ -236,11 +236,11 @@ double varargs_vec_3s(int fixed, ...) { double test_3s(__short3 *in) { // CHECK: test_3s -// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_3s(i32 noundef 3, <2 x i32> {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_3s(i32 3, <2 x i32> {{%.*}}) // APCS-GNU: test_3s -// APCS-GNU: call double (i32, ...) @varargs_vec_3s(i32 noundef 3, <2 x i32> {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_vec_3s(i32 3, <2 x i32> {{%.*}}) // ANDROID: test_3s -// ANDROID: call double (i32, ...) @varargs_vec_3s(i32 noundef 3, <3 x i16> noundef {{%.*}}) +// ANDROID: call double (i32, ...) @varargs_vec_3s(i32 3, <3 x i16> {{%.*}}) return varargs_vec_3s(3, *in); } @@ -278,11 +278,11 @@ double varargs_vec_5s(int fixed, ...) { double test_5s(__short5 *in) { // CHECK: test_5s -// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_5s(i32 noundef 5, <4 x i32> {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_5s(i32 5, <4 x i32> {{%.*}}) // APCS-GNU: test_5s -// APCS-GNU: call double (i32, ...) @varargs_vec_5s(i32 noundef 5, <4 x i32> {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_vec_5s(i32 5, <4 x i32> {{%.*}}) // ANDROID: test_5s -// ANDROID: call double (i32, ...) @varargs_vec_5s(i32 noundef 5, <4 x i32> {{%.*}}) +// ANDROID: call double (i32, ...) @varargs_vec_5s(i32 5, <4 x i32> {{%.*}}) return varargs_vec_5s(5, *in); } @@ -320,10 +320,10 @@ double varargs_struct(int fixed, ...) { double test_struct(StructWithVec* d) { // CHECK: test_struct -// CHECK: call arm_aapcscc double (i32, ...) @varargs_struct(i32 noundef 3, [2 x i64] {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_struct(i32 3, [2 x i64] {{%.*}}) // APCS-GNU: test_struct -// APCS-GNU: call double (i32, ...) @varargs_struct(i32 noundef 3, [2 x i64] {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_struct(i32 3, [2 x i64] {{%.*}}) // ANDROID: test_struct -// ANDROID: call double (i32, ...) @varargs_struct(i32 noundef 3, [2 x i64] {{%.*}}) +// ANDROID: call double (i32, ...) @varargs_struct(i32 3, [2 x i64] {{%.*}}) return varargs_struct(3, *d); } diff --git a/clang/test/CodeGen/arm-arguments.c b/clang/test/CodeGen/arm-arguments.c index b9822b63d51dec78375dd48bf9c9127b45a2f108..ad1b89431ee25fe147b41bcc6f3dc498a1fab5ae 100644 --- a/clang/test/CodeGen/arm-arguments.c +++ b/clang/test/CodeGen/arm-arguments.c @@ -176,14 +176,14 @@ void f32(struct s32 s) { } // PR13350 struct s33 { char buf[32*32]; }; void f33(struct s33 s) { } -// APCS-GNU-LABEL: define{{.*}} void @f33(%struct.s33* noundef byval(%struct.s33) align 4 %s) -// AAPCS-LABEL: define{{.*}} arm_aapcscc void @f33(%struct.s33* noundef byval(%struct.s33) align 4 %s) +// APCS-GNU-LABEL: define{{.*}} void @f33(%struct.s33* byval(%struct.s33) align 4 %s) +// AAPCS-LABEL: define{{.*}} arm_aapcscc void @f33(%struct.s33* byval(%struct.s33) align 4 %s) // PR14048 struct s34 { char c; }; void f34(struct s34 s); void g34(struct s34 *s) { f34(*s); } -// AAPCS: @g34(%struct.s34* noundef %s) +// AAPCS: @g34(%struct.s34* %s) // AAPCS: %[[a:.*]] = alloca [1 x i32] // AAPCS: load [1 x i32], [1 x i32]* %[[a]] @@ -204,7 +204,7 @@ float32x4_t f35(int i, s35_with_align s1, s35_with_align s2) { *(float32x4_t *)&s2); return v; } -// APCS-GNU-LABEL: define{{.*}} <4 x float> @f35(i32 noundef %i, %struct.s35* noundef byval(%struct.s35) align 4 %0, %struct.s35* noundef byval(%struct.s35) align 4 %1) +// APCS-GNU-LABEL: define{{.*}} <4 x float> @f35(i32 %i, %struct.s35* byval(%struct.s35) align 4 %0, %struct.s35* byval(%struct.s35) align 4 %1) // APCS-GNU: %[[a:.*]] = alloca %struct.s35, align 16 // APCS-GNU: %[[b:.*]] = bitcast %struct.s35* %[[a]] to i8* // APCS-GNU: %[[c:.*]] = bitcast %struct.s35* %0 to i8* @@ -212,7 +212,7 @@ float32x4_t f35(int i, s35_with_align s1, s35_with_align s2) { // APCS-GNU: %[[d:.*]] = bitcast %struct.s35* %[[a]] to <4 x float>* // APCS-GNU: load <4 x float>, <4 x float>* %[[d]], align 16 -// AAPCS-LABEL: define{{.*}} arm_aapcscc <4 x float> @f35(i32 noundef %i, %struct.s35* noundef byval(%struct.s35) align 4 %s1, %struct.s35* noundef byval(%struct.s35) align 4 %s2) +// AAPCS-LABEL: define{{.*}} arm_aapcscc <4 x float> @f35(i32 %i, %struct.s35* byval(%struct.s35) align 4 %s1, %struct.s35* byval(%struct.s35) align 4 %s2) // AAPCS: %[[a_addr:.*]] = alloca <4 x float>, align 16 // AAPCS: %[[b_addr:.*]] = alloca <4 x float>, align 16 // AAPCS: %[[p1:.*]] = bitcast %struct.s35* %s1 to <4 x float>* diff --git a/clang/test/CodeGen/arm-bf16-params-returns.c b/clang/test/CodeGen/arm-bf16-params-returns.c index d67d3e5e0d65b2bb20d5d30188e72e36ec5d711c..650ae0adb612738bf1915ceafee8dc182bdcf897 100644 --- a/clang/test/CodeGen/arm-bf16-params-returns.c +++ b/clang/test/CodeGen/arm-bf16-params-returns.c @@ -8,19 +8,19 @@ __bf16 test_ret_bf16(__bf16 v) { return v; } -// CHECK32-HARD: define{{.*}} arm_aapcs_vfpcc bfloat @test_ret_bf16(bfloat noundef returned %v) {{.*}} { +// CHECK32-HARD: define{{.*}} arm_aapcs_vfpcc bfloat @test_ret_bf16(bfloat returned %v) {{.*}} { // CHECK32-HARD: ret bfloat %v -// CHECK32-SOFTFP: define{{.*}} bfloat @test_ret_bf16(bfloat noundef returned %v) {{.*}} { +// CHECK32-SOFTFP: define{{.*}} bfloat @test_ret_bf16(bfloat returned %v) {{.*}} { // CHECK32-SOFTFP: ret bfloat %v -// CHECK64: define{{.*}} bfloat @test_ret_bf16(bfloat noundef returned %v) {{.*}} { +// CHECK64: define{{.*}} bfloat @test_ret_bf16(bfloat returned %v) {{.*}} { // CHECK64: ret bfloat %v bfloat16x4_t test_ret_bf16x4_t(bfloat16x4_t v) { return v; } -// CHECK32-HARD: define{{.*}} arm_aapcs_vfpcc <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> noundef returned %v) {{.*}} { +// CHECK32-HARD: define{{.*}} arm_aapcs_vfpcc <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> returned %v) {{.*}} { // CHECK32-HARD: ret <4 x bfloat> %v // CHECK32-SOFTFP: define{{.*}} <2 x i32> @test_ret_bf16x4_t(<2 x i32> [[V0:.*]]) {{.*}} { // CHECK32-SOFTFP: ret <2 x i32> %v -// CHECK64: define{{.*}} <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> noundef returned %v) {{.*}} { +// CHECK64: define{{.*}} <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> returned %v) {{.*}} { // CHECK64: ret <4 x bfloat> %v diff --git a/clang/test/CodeGen/arm-byval-align.c b/clang/test/CodeGen/arm-byval-align.c index 4a8b1d27a0e4406b7bc918e42c5d16b44aad8577..c3e887773fb04f3a73451678b0518e13a5cbf907 100644 --- a/clang/test/CodeGen/arm-byval-align.c +++ b/clang/test/CodeGen/arm-byval-align.c @@ -7,7 +7,7 @@ struct foo { int d[16]; }; -// CHECK: %struct.foo* noundef byval(%struct.foo) align 8 %z +// CHECK: %struct.foo* byval(%struct.foo) align 8 %z long long bar(int a, int b, int c, int d, int e, struct foo z) { return z.a; diff --git a/clang/test/CodeGen/arm-cmse-attr.c b/clang/test/CodeGen/arm-cmse-attr.c index f19bbde767704d5ef847e200583d3eaa18205c9f..5cfadfd3828a133a7b83f536f8e6627238b8ab8d 100644 --- a/clang/test/CodeGen/arm-cmse-attr.c +++ b/clang/test/CodeGen/arm-cmse-attr.c @@ -29,9 +29,9 @@ void f4() __attribute__((cmse_nonsecure_entry)) { } -// CHECK: define{{.*}} void @f1(void ()* nocapture noundef %fptr) {{[^#]*}}#0 { +// CHECK: define{{.*}} void @f1(void ()* nocapture %fptr) {{[^#]*}}#0 { // CHECK: call void %fptr() #2 -// CHECK: define{{.*}} void @f2(void ()* nocapture noundef %fptr) {{[^#]*}}#0 { +// CHECK: define{{.*}} void @f2(void ()* nocapture %fptr) {{[^#]*}}#0 { // CHECK: call void %fptr() #2 // CHECK: define{{.*}} void @f3() {{[^#]*}}#1 { // CHECK: define{{.*}} void @f4() {{[^#]*}}#1 { diff --git a/clang/test/CodeGen/arm-cmse-call.c b/clang/test/CodeGen/arm-cmse-call.c index 5041789d5300b5011509e78392cacbe477aee7c8..8bbab23d9ea6082d7e8721a545caef96b0de2e5b 100644 --- a/clang/test/CodeGen/arm-cmse-call.c +++ b/clang/test/CodeGen/arm-cmse-call.c @@ -40,7 +40,7 @@ void f(int i) { p2(i); // CHECK: %[[#P2:]] = load {{.*}} @p2 -// CHECK: call void %[[#P2]](i32 noundef %i) #[[#A2]] +// CHECK: call void %[[#P2]](i32 %i) #[[#A2]] a0[i](); // CHECK: %[[EP0:.*]] = getelementptr {{.*}} @a0 @@ -70,7 +70,7 @@ void f(int i) { b[i](i); // CHECK: %[[EP5:.*]] = getelementptr {{.*}} @b // CHECK: %[[#E5:]] = load {{.*}} %[[EP5]] -// CHECK: call void %[[#E5]](i32 noundef %i) #[[#A2]] +// CHECK: call void %[[#E5]](i32 %i) #[[#A2]] } // CHECK: attributes #[[#A1]] = { nounwind } diff --git a/clang/test/CodeGen/arm-float-helpers.c b/clang/test/CodeGen/arm-float-helpers.c index 05a309cd9fcef906837cbea58fb4e21a34f827ef..bb3fbbc3336e620d5c4ddc7e8010603dbc4b67ca 100644 --- a/clang/test/CodeGen/arm-float-helpers.c +++ b/clang/test/CodeGen/arm-float-helpers.c @@ -32,192 +32,192 @@ // other runtime functions such as the _Complex helper routines are not covered. float fadd(float a, float b) { return a + b; } -// CHECK-LABEL: define{{.*}} float @fadd(float noundef %a, float noundef %b) +// CHECK-LABEL: define{{.*}} float @fadd(float %a, float %b) // CHECK-NOT: __aeabi_fadd // CHECK: %add = fadd float {{.*}}, {{.*}} float fdiv(float a, float b) { return a / b; } -// CHECK-LABEL: define{{.*}} float @fdiv(float noundef %a, float noundef %b) +// CHECK-LABEL: define{{.*}} float @fdiv(float %a, float %b) // CHECK-NOT: __aeabi_fdiv // CHECK: %div = fdiv float {{.*}}, {{.*}} float fmul(float a, float b) { return a * b; } -// CHECK-LABEL: define{{.*}} float @fmul(float noundef %a, float noundef %b) +// CHECK-LABEL: define{{.*}} float @fmul(float %a, float %b) // CHECK-NOT: __aeabi_fmul // CHECK: %mul = fmul float {{.*}}, {{.*}} float fsub(float a, float b) { return a - b; } -// CHECK-LABEL: define{{.*}} float @fsub(float noundef %a, float noundef %b) +// CHECK-LABEL: define{{.*}} float @fsub(float %a, float %b) // CHECK-NOT: __aeabi_fsub // CHECK: %sub = fsub float {{.*}}, {{.*}} int fcmpeq(float a, float b) { return a == b; } -// CHECK-LABEL: define{{.*}} i32 @fcmpeq(float noundef %a, float noundef %b) +// CHECK-LABEL: define{{.*}} i32 @fcmpeq(float %a, float %b) // CHECK-NOT: __aeabi_fcmpeq // CHECK: %cmp = fcmp oeq float {{.*}}, {{.*}} int fcmplt(float a, float b) { return a < b; } -// CHECK-LABEL: define{{.*}} i32 @fcmplt(float noundef %a, float noundef %b) +// CHECK-LABEL: define{{.*}} i32 @fcmplt(float %a, float %b) // CHECK-NOT: __aeabi_fcmplt // CHECK: %cmp = fcmp olt float {{.*}}, {{.*}} int fcmple(float a, float b) { return a <= b; } -// CHECK-LABEL: define{{.*}} i32 @fcmple(float noundef %a, float noundef %b) +// CHECK-LABEL: define{{.*}} i32 @fcmple(float %a, float %b) // CHECK-NOT: __aeabi_fcmple // CHECK: %cmp = fcmp ole float {{.*}}, {{.*}} int fcmpge(float a, float b) { return a >= b; } -// CHECK-LABEL: define{{.*}} i32 @fcmpge(float noundef %a, float noundef %b) +// CHECK-LABEL: define{{.*}} i32 @fcmpge(float %a, float %b) // CHECK-NOT: __aeabi_fcmpge // CHECK: %cmp = fcmp oge float {{.*}}, {{.*}} int fcmpgt(float a, float b) { return a > b; } -// CHECK-LABEL: define{{.*}} i32 @fcmpgt(float noundef %a, float noundef %b) +// CHECK-LABEL: define{{.*}} i32 @fcmpgt(float %a, float %b) // CHECK-NOT: __aeabi_fcmpgt // CHECK: %cmp = fcmp ogt float {{.*}}, {{.*}} int fcmpun(float a, float b) { return __builtin_isunordered(a, b); } -// CHECK-LABEL: define{{.*}} i32 @fcmpun(float noundef %a, float noundef %b) +// CHECK-LABEL: define{{.*}} i32 @fcmpun(float %a, float %b) // CHECK-NOT: __aeabi_fcmpun // CHECK: %cmp = fcmp uno float {{.*}}, {{.*}} double dadd(double a, double b) { return a + b; } -// CHECK-LABEL: define{{.*}} double @dadd(double noundef %a, double noundef %b) +// CHECK-LABEL: define{{.*}} double @dadd(double %a, double %b) // CHECK-NOT: __aeabi_dadd // CHECK: %add = fadd double {{.*}}, {{.*}} double ddiv(double a, double b) { return a / b; } -// CHECK-LABEL: define{{.*}} double @ddiv(double noundef %a, double noundef %b) +// CHECK-LABEL: define{{.*}} double @ddiv(double %a, double %b) // CHECK-NOT: __aeabi_ddiv // CHECK: %div = fdiv double {{.*}}, {{.*}} double dmul(double a, double b) { return a * b; } -// CHECK-LABEL: define{{.*}} double @dmul(double noundef %a, double noundef %b) +// CHECK-LABEL: define{{.*}} double @dmul(double %a, double %b) // CHECK-NOT: __aeabi_dmul // CHECK: %mul = fmul double {{.*}}, {{.*}} double dsub(double a, double b) { return a - b; } -// CHECK-LABEL: define{{.*}} double @dsub(double noundef %a, double noundef %b) +// CHECK-LABEL: define{{.*}} double @dsub(double %a, double %b) // CHECK-NOT: __aeabi_dsub // CHECK: %sub = fsub double {{.*}}, {{.*}} int dcmpeq(double a, double b) { return a == b; } -// CHECK-LABEL: define{{.*}} i32 @dcmpeq(double noundef %a, double noundef %b) +// CHECK-LABEL: define{{.*}} i32 @dcmpeq(double %a, double %b) // CHECK-NOT: __aeabi_dcmpeq // CHECK: %cmp = fcmp oeq double {{.*}}, {{.*}} int dcmplt(double a, double b) { return a < b; } -// CHECK-LABEL: define{{.*}} i32 @dcmplt(double noundef %a, double noundef %b) +// CHECK-LABEL: define{{.*}} i32 @dcmplt(double %a, double %b) // CHECK-NOT: __aeabi_dcmplt // CHECK: %cmp = fcmp olt double {{.*}}, {{.*}} int dcmple(double a, double b) { return a <= b; } -// CHECK-LABEL: define{{.*}} i32 @dcmple(double noundef %a, double noundef %b) +// CHECK-LABEL: define{{.*}} i32 @dcmple(double %a, double %b) // CHECK-NOT: __aeabi_dcmple // CHECK: %cmp = fcmp ole double {{.*}}, {{.*}} int dcmpge(double a, double b) { return a >= b; } -// CHECK-LABEL: define{{.*}} i32 @dcmpge(double noundef %a, double noundef %b) +// CHECK-LABEL: define{{.*}} i32 @dcmpge(double %a, double %b) // CHECK-NOT: __aeabi_dcmpge // CHECK: %cmp = fcmp oge double {{.*}}, {{.*}} int dcmpgt(double a, double b) { return a > b; } -// CHECK-LABEL: define{{.*}} i32 @dcmpgt(double noundef %a, double noundef %b) +// CHECK-LABEL: define{{.*}} i32 @dcmpgt(double %a, double %b) // CHECK-NOT: __aeabi_dcmpgt // CHECK: %cmp = fcmp ogt double {{.*}}, {{.*}} int dcmpun(double a, double b) { return __builtin_isunordered(a, b); } -// CHECK-LABEL: define{{.*}} i32 @dcmpun(double noundef %a, double noundef %b) +// CHECK-LABEL: define{{.*}} i32 @dcmpun(double %a, double %b) // CHECK-NOT: __aeabi_dcmpun // CHECK: %cmp = fcmp uno double {{.*}}, {{.*}} int d2iz(double a) { return (int)a; } -// CHECK-LABEL: define{{.*}} i32 @d2iz(double noundef %a) +// CHECK-LABEL: define{{.*}} i32 @d2iz(double %a) // CHECK-NOT: __aeabi_d2iz // CHECK: %conv = fptosi double {{.*}} to i32 unsigned int d2uiz(double a) { return (unsigned int)a; } -// CHECK-LABEL: define{{.*}} i32 @d2uiz(double noundef %a) +// CHECK-LABEL: define{{.*}} i32 @d2uiz(double %a) // CHECK-NOT: __aeabi_d2uiz // CHECK: %conv = fptoui double {{.*}} to i32 long long d2lz(double a) { return (long long)a; } -// CHECK-LABEL: define{{.*}} i64 @d2lz(double noundef %a) +// CHECK-LABEL: define{{.*}} i64 @d2lz(double %a) // CHECK-NOT: __aeabi_d2lz // CHECK: %conv = fptosi double {{.*}} to i64 unsigned long long d2ulz(double a) { return (unsigned long long)a; } -// CHECK-LABEL: define{{.*}} i64 @d2ulz(double noundef %a) +// CHECK-LABEL: define{{.*}} i64 @d2ulz(double %a) // CHECK-NOT: __aeabi_d2ulz // CHECK: %conv = fptoui double {{.*}} to i64 int f2iz(float a) { return (int)a; } -// CHECK-LABEL: define{{.*}} i32 @f2iz(float noundef %a) +// CHECK-LABEL: define{{.*}} i32 @f2iz(float %a) // CHECK-NOT: __aeabi_f2iz // CHECK: %conv = fptosi float {{.*}} to i32 unsigned int f2uiz(float a) { return (unsigned int)a; } -// CHECK-LABEL: define{{.*}} i32 @f2uiz(float noundef %a) +// CHECK-LABEL: define{{.*}} i32 @f2uiz(float %a) // CHECK-NOT: __aeabi_f2uiz // CHECK: %conv = fptoui float {{.*}} to i32 long long f2lz(float a) { return (long long)a; } -// CHECK-LABEL: define{{.*}} i64 @f2lz(float noundef %a) +// CHECK-LABEL: define{{.*}} i64 @f2lz(float %a) // CHECK-NOT: __aeabi_f2lz // CHECK: %conv = fptosi float {{.*}} to i64 unsigned long long f2ulz(float a) { return (unsigned long long)a; } -// CHECK-LABEL: define{{.*}} i64 @f2ulz(float noundef %a) +// CHECK-LABEL: define{{.*}} i64 @f2ulz(float %a) // CHECK-NOT: __aeabi_f2ulz // CHECK: %conv = fptoui float {{.*}} to i64 float d2f(double a) { return (float)a; } -// CHECK-LABEL: define{{.*}} float @d2f(double noundef %a) +// CHECK-LABEL: define{{.*}} float @d2f(double %a) // CHECK-NOT: __aeabi_d2f // CHECK: %conv = fptrunc double {{.*}} to float double f2d(float a) { return (double)a; } -// CHECK-LABEL: define{{.*}} double @f2d(float noundef %a) +// CHECK-LABEL: define{{.*}} double @f2d(float %a) // CHECK-NOT: __aeabi_f2d // CHECK: %conv = fpext float {{.*}} to double double i2d(int a) { return (double)a; } -// CHECK-LABEL: define{{.*}} double @i2d(i32 noundef %a) +// CHECK-LABEL: define{{.*}} double @i2d(i32 %a) // CHECK-NOT: __aeabi_i2d // CHECK: %conv = sitofp i32 {{.*}} to double double ui2d(unsigned int a) { return (double)a; } -// CHECK-LABEL: define{{.*}} double @ui2d(i32 noundef %a) +// CHECK-LABEL: define{{.*}} double @ui2d(i32 %a) // CHECK-NOT: __aeabi_ui2d // CHECK: %conv = uitofp i32 {{.*}} to double double l2d(long long a) { return (double)a; } -// CHECK-LABEL: define{{.*}} double @l2d(i64 noundef %a) +// CHECK-LABEL: define{{.*}} double @l2d(i64 %a) // CHECK-NOT: __aeabi_l2d // CHECK: %conv = sitofp i64 {{.*}} to double double ul2d(unsigned long long a) { return (unsigned long long)a; } -// CHECK-LABEL: define{{.*}} double @ul2d(i64 noundef %a) +// CHECK-LABEL: define{{.*}} double @ul2d(i64 %a) // CHECK-NOT: __aeabi_ul2d // CHECK: %conv = uitofp i64 {{.*}} to double float i2f(int a) { return (int)a; } -// CHECK-LABEL: define{{.*}} float @i2f(i32 noundef %a) +// CHECK-LABEL: define{{.*}} float @i2f(i32 %a) // CHECK-NOT: __aeabi_i2f // CHECK: %conv = sitofp i32 {{.*}} to float float ui2f(unsigned int a) { return (unsigned int)a; } -// CHECK-LABEL: define{{.*}} float @ui2f(i32 noundef %a) +// CHECK-LABEL: define{{.*}} float @ui2f(i32 %a) // CHECK-NOT: __aeabi_ui2f // CHECK: %conv = uitofp i32 {{.*}} to float float l2f(long long a) { return (long long)a; } -// CHECK-LABEL: define{{.*}} float @l2f(i64 noundef %a) +// CHECK-LABEL: define{{.*}} float @l2f(i64 %a) // CHECK-NOT: __aeabi_l2f // CHECK: %conv = sitofp i64 {{.*}} to float float ul2f(unsigned long long a) { return (unsigned long long)a; } -// CHECK-LABEL: define{{.*}} float @ul2f(i64 noundef %a) +// CHECK-LABEL: define{{.*}} float @ul2f(i64 %a) // CHECK-NOT: __aeabi_ul2f // CHECK: %conv = uitofp i64 {{.*}} to float diff --git a/clang/test/CodeGen/arm-fp16-arguments.c b/clang/test/CodeGen/arm-fp16-arguments.c index c511861ece63345c1c36803db57ec5bad5300da6..78afb271decf3c11982e375cce790d5ebf03284e 100644 --- a/clang/test/CodeGen/arm-fp16-arguments.c +++ b/clang/test/CodeGen/arm-fp16-arguments.c @@ -5,9 +5,9 @@ __fp16 g; void t1(__fp16 a) { g = a; } -// SOFT: define{{.*}} void @t1(half noundef [[PARAM:%.*]]) -// HARD: define{{.*}} arm_aapcs_vfpcc void @t1(half noundef [[PARAM:%.*]]) -// NATIVE: define{{.*}} void @t1(half noundef [[PARAM:%.*]]) +// SOFT: define{{.*}} void @t1(half [[PARAM:%.*]]) +// HARD: define{{.*}} arm_aapcs_vfpcc void @t1(half [[PARAM:%.*]]) +// NATIVE: define{{.*}} void @t1(half [[PARAM:%.*]]) // CHECK: store half [[PARAM]], half* @g __fp16 t2() { return g; } @@ -20,9 +20,9 @@ __fp16 t2() { return g; } _Float16 h; void t3(_Float16 a) { h = a; } -// SOFT: define{{.*}} void @t3(half noundef [[PARAM:%.*]]) -// HARD: define{{.*}} arm_aapcs_vfpcc void @t3(half noundef [[PARAM:%.*]]) -// NATIVE: define{{.*}} void @t3(half noundef [[PARAM:%.*]]) +// SOFT: define{{.*}} void @t3(half [[PARAM:%.*]]) +// HARD: define{{.*}} arm_aapcs_vfpcc void @t3(half [[PARAM:%.*]]) +// NATIVE: define{{.*}} void @t3(half [[PARAM:%.*]]) // CHECK: store half [[PARAM]], half* @h _Float16 t4() { return h; } diff --git a/clang/test/CodeGen/arm-homogenous.c b/clang/test/CodeGen/arm-homogenous.c index 88c3ff031cf5d817a1ac2196ebb6cdefc58fc20b..112abedc807fdbd673cb24b821004beb88f0a304 100644 --- a/clang/test/CodeGen/arm-homogenous.c +++ b/clang/test/CodeGen/arm-homogenous.c @@ -95,7 +95,7 @@ void test_array_of_floats(void) { float a[4] = {1.0, 2.0, 3.0, 4.0}; takes_array_of_floats(a); } -// CHECK: declare arm_aapcs_vfpcc void @takes_array_of_floats(float* noundef) +// CHECK: declare arm_aapcs_vfpcc void @takes_array_of_floats(float*) /* Struct-type homogenous aggregate */ typedef struct { diff --git a/clang/test/CodeGen/arm-mangle-bf16.cpp b/clang/test/CodeGen/arm-mangle-bf16.cpp index c5912170a640d5b7ade89b6e25f4e49f2264f471..2d7f5e651459c5c67e2bcf97a629aae42d17273e 100644 --- a/clang/test/CodeGen/arm-mangle-bf16.cpp +++ b/clang/test/CodeGen/arm-mangle-bf16.cpp @@ -2,5 +2,5 @@ // RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi hard -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi softfp -emit-llvm -o - %s | FileCheck %s -// CHECK: define {{.*}}void @_Z3foou6__bf16(bfloat noundef %b) +// CHECK: define {{.*}}void @_Z3foou6__bf16(bfloat %b) void foo(__bf16 b) {} diff --git a/clang/test/CodeGen/arm-neon-directed-rounding.c b/clang/test/CodeGen/arm-neon-directed-rounding.c index 9c99469e31a26d31a50ec99de8e308bf1860e888..c493e3897ab6ab4a8540b1cc4e43a882655e2fbc 100644 --- a/clang/test/CodeGen/arm-neon-directed-rounding.c +++ b/clang/test/CodeGen/arm-neon-directed-rounding.c @@ -7,7 +7,7 @@ #include -// CHECK-LABEL: define{{.*}} <2 x float> @test_vrnda_f32(<2 x float> noundef %a) +// CHECK-LABEL: define{{.*}} <2 x float> @test_vrnda_f32(<2 x float> %a) // CHECK-A32: [[VRNDA_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrinta.v2f32(<2 x float> %a) // CHECK-A64: [[VRNDA_V1_I:%.*]] = call <2 x float> @llvm.round.v2f32(<2 x float> %a) // CHECK: ret <2 x float> [[VRNDA_V1_I]] @@ -15,7 +15,7 @@ float32x2_t test_vrnda_f32(float32x2_t a) { return vrnda_f32(a); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) +// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndaq_f32(<4 x float> %a) // CHECK-A32: [[VRNDAQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrinta.v4f32(<4 x float> %a) // CHECK-A64: [[VRNDAQ_V1_I:%.*]] = call <4 x float> @llvm.round.v4f32(<4 x float> %a) // CHECK: ret <4 x float> [[VRNDAQ_V1_I]] @@ -23,7 +23,7 @@ float32x4_t test_vrndaq_f32(float32x4_t a) { return vrndaq_f32(a); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndm_f32(<2 x float> noundef %a) +// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndm_f32(<2 x float> %a) // CHECK-A32: [[VRNDM_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintm.v2f32(<2 x float> %a) // CHECK-A64: [[VRNDM_V1_I:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> %a) // CHECK: ret <2 x float> [[VRNDM_V1_I]] @@ -31,7 +31,7 @@ float32x2_t test_vrndm_f32(float32x2_t a) { return vrndm_f32(a); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) +// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndmq_f32(<4 x float> %a) // CHECK-A32: [[VRNDMQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintm.v4f32(<4 x float> %a) // CHECK-A64: [[VRNDMQ_V1_I:%.*]] = call <4 x float> @llvm.floor.v4f32(<4 x float> %a) // CHECK: ret <4 x float> [[VRNDMQ_V1_I]] @@ -39,7 +39,7 @@ float32x4_t test_vrndmq_f32(float32x4_t a) { return vrndmq_f32(a); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndn_f32(<2 x float> noundef %a) +// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndn_f32(<2 x float> %a) // CHECK-A32: [[VRNDN_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintn.v2f32(<2 x float> %a) // CHECK-A64: [[VRNDN_V1_I:%.*]] = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %a) // CHECK: ret <2 x float> [[VRNDN_V1_I]] @@ -47,7 +47,7 @@ float32x2_t test_vrndn_f32(float32x2_t a) { return vrndn_f32(a); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) +// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndnq_f32(<4 x float> %a) // CHECK-A32: [[VRNDNQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintn.v4f32(<4 x float> %a) // CHECK-A64: [[VRNDNQ_V1_I:%.*]] = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %a) // CHECK: ret <4 x float> [[VRNDNQ_V1_I]] @@ -55,7 +55,7 @@ float32x4_t test_vrndnq_f32(float32x4_t a) { return vrndnq_f32(a); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndp_f32(<2 x float> noundef %a) +// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndp_f32(<2 x float> %a) // CHECK-A32: [[VRNDP_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintp.v2f32(<2 x float> %a) // CHECK-A64: [[VRNDP_V1_I:%.*]] = call <2 x float> @llvm.ceil.v2f32(<2 x float> %a) // CHECK: ret <2 x float> [[VRNDP_V1_I]] @@ -63,7 +63,7 @@ float32x2_t test_vrndp_f32(float32x2_t a) { return vrndp_f32(a); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) +// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndpq_f32(<4 x float> %a) // CHECK-A32: [[VRNDPQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintp.v4f32(<4 x float> %a) // CHECK-A64: [[VRNDPQ_V1_I:%.*]] = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a) // CHECK: ret <4 x float> [[VRNDPQ_V1_I]] @@ -71,7 +71,7 @@ float32x4_t test_vrndpq_f32(float32x4_t a) { return vrndpq_f32(a); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndx_f32(<2 x float> noundef %a) +// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndx_f32(<2 x float> %a) // CHECK-A32: [[VRNDX_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintx.v2f32(<2 x float> %a) // CHECK-A64: [[VRNDX_V1_I:%.*]] = call <2 x float> @llvm.rint.v2f32(<2 x float> %a) // CHECK: ret <2 x float> [[VRNDX_V1_I]] @@ -79,7 +79,7 @@ float32x2_t test_vrndx_f32(float32x2_t a) { return vrndx_f32(a); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) +// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndxq_f32(<4 x float> %a) // CHECK-A32: [[VRNDXQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintx.v4f32(<4 x float> %a) // CHECK-A64: [[VRNDXQ_V1_I:%.*]] = call <4 x float> @llvm.rint.v4f32(<4 x float> %a) // CHECK: ret <4 x float> [[VRNDXQ_V1_I]] @@ -87,7 +87,7 @@ float32x4_t test_vrndxq_f32(float32x4_t a) { return vrndxq_f32(a); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vrnd_f32(<2 x float> noundef %a) +// CHECK-LABEL: define{{.*}} <2 x float> @test_vrnd_f32(<2 x float> %a) // CHECK-A32: [[VRND_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintz.v2f32(<2 x float> %a) // CHECK-A64: [[VRND_V1_I:%.*]] = call <2 x float> @llvm.trunc.v2f32(<2 x float> %a) // CHECK: ret <2 x float> [[VRND_V1_I]] @@ -95,7 +95,7 @@ float32x2_t test_vrnd_f32(float32x2_t a) { return vrnd_f32(a); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndq_f32(<4 x float> noundef %a) +// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndq_f32(<4 x float> %a) // CHECK-A32: [[VRNDQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintz.v4f32(<4 x float> %a) // CHECK-A64: [[VRNDQ_V1_I:%.*]] = call <4 x float> @llvm.trunc.v4f32(<4 x float> %a) // CHECK: ret <4 x float> [[VRNDQ_V1_I]] @@ -103,7 +103,7 @@ float32x4_t test_vrndq_f32(float32x4_t a) { return vrndq_f32(a); } -// CHECK-LABEL: define{{.*}} float @test_vrndns_f32(float noundef %a) +// CHECK-LABEL: define{{.*}} float @test_vrndns_f32(float %a) // CHECK-A32: [[VRNDN_I:%.*]] = call float @llvm.arm.neon.vrintn.f32(float %a) // CHECK-A64: [[VRNDN_I:%.*]] = call float @llvm.roundeven.f32(float %a) // CHECK: ret float [[VRNDN_I]] @@ -111,7 +111,7 @@ float32_t test_vrndns_f32(float32_t a) { return vrndns_f32(a); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndi_f32(<2 x float> noundef %a) +// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndi_f32(<2 x float> %a) // CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> // CHECK: [[VRNDI1_I:%.*]] = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %a) // CHECK: ret <2 x float> [[VRNDI1_I]] @@ -119,7 +119,7 @@ float32x2_t test_vrndi_f32(float32x2_t a) { return vrndi_f32(a); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndiq_f32(<4 x float> noundef %a) +// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndiq_f32(<4 x float> %a) // CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> // CHECK: [[VRNDI1_I:%.*]] = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %a) // CHECK: ret <4 x float> [[VRNDI1_I]] diff --git a/clang/test/CodeGen/arm-neon-dot-product.c b/clang/test/CodeGen/arm-neon-dot-product.c index 77bd4f4a03ad5f20122471e5270054f3f8b89cea..6eca642db5f2a47de99de0412343e15f84f17429 100644 --- a/clang/test/CodeGen/arm-neon-dot-product.c +++ b/clang/test/CodeGen/arm-neon-dot-product.c @@ -8,35 +8,35 @@ #include uint32x2_t test_vdot_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) { -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) // CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) // CHECK: ret <2 x i32> [[RESULT]] return vdot_u32(a, b, c); } uint32x4_t test_vdotq_u32(uint32x4_t a, uint8x16_t b, uint8x16_t c) { -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) // CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) // CHECK: ret <4 x i32> [[RESULT]] return vdotq_u32(a, b, c); } int32x2_t test_vdot_s32(int32x2_t a, int8x8_t b, int8x8_t c) { -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) // CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) // CHECK: ret <2 x i32> [[RESULT]] return vdot_s32(a, b, c); } int32x4_t test_vdotq_s32(int32x4_t a, int8x16_t b, int8x16_t c) { -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) // CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) // CHECK: ret <4 x i32> [[RESULT]] return vdotq_s32(a, b, c); } uint32x2_t test_vdot_lane_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) { -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) // CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32> // CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <2 x i32> // CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> @@ -46,7 +46,7 @@ uint32x2_t test_vdot_lane_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) { } uint32x4_t test_vdotq_lane_u32(uint32x4_t a, uint8x16_t b, uint8x8_t c) { -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_u32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) // CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32> // CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <4 x i32> // CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8> @@ -56,7 +56,7 @@ uint32x4_t test_vdotq_lane_u32(uint32x4_t a, uint8x16_t b, uint8x8_t c) { } int32x2_t test_vdot_lane_s32(int32x2_t a, int8x8_t b, int8x8_t c) { -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) // CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32> // CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <2 x i32> // CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8> @@ -66,7 +66,7 @@ int32x2_t test_vdot_lane_s32(int32x2_t a, int8x8_t b, int8x8_t c) { } int32x4_t test_vdotq_lane_s32(int32x4_t a, int8x16_t b, int8x8_t c) { -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_s32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) // CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32> // CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <4 x i32> // CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8> diff --git a/clang/test/CodeGen/arm-neon-fma.c b/clang/test/CodeGen/arm-neon-fma.c index 644627b23792d5032962a9da9f66f0bab35f5d51..889a752fc970a1dce11d9c9075321ff926a02d93 100644 --- a/clang/test/CodeGen/arm-neon-fma.c +++ b/clang/test/CodeGen/arm-neon-fma.c @@ -7,21 +7,21 @@ #include -// CHECK-LABEL: define{{.*}} <2 x float> @test_fma_order(<2 x float> noundef %accum, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_fma_order(<2 x float> %accum, <2 x float> %lhs, <2 x float> %rhs) #0 { // CHECK: [[TMP6:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> %lhs, <2 x float> %rhs, <2 x float> %accum) #3 // CHECK: ret <2 x float> [[TMP6]] float32x2_t test_fma_order(float32x2_t accum, float32x2_t lhs, float32x2_t rhs) { return vfma_f32(accum, lhs, rhs); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_fmaq_order(<4 x float> noundef %accum, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_fmaq_order(<4 x float> %accum, <4 x float> %lhs, <4 x float> %rhs) #1 { // CHECK: [[TMP6:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %lhs, <4 x float> %rhs, <4 x float> %accum) #3 // CHECK: ret <4 x float> [[TMP6]] float32x4_t test_fmaq_order(float32x4_t accum, float32x4_t lhs, float32x4_t rhs) { return vfmaq_f32(accum, lhs, rhs); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vfma_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %n) #0 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vfma_n_f32(<2 x float> %a, <2 x float> %b, float %n) #0 { // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %n, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %n, i32 1 // CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8> @@ -32,7 +32,7 @@ float32x2_t test_vfma_n_f32(float32x2_t a, float32x2_t b, float32_t n) { return vfma_n_f32(a, b, n); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %n) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vfmaq_n_f32(<4 x float> %a, <4 x float> %b, float %n) #1 { // CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %n, i32 1 // CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %n, i32 2 diff --git a/clang/test/CodeGen/arm-neon-numeric-maxmin.c b/clang/test/CodeGen/arm-neon-numeric-maxmin.c index 0ff5bc8bc79c2cbc83474bcb81e57f450194367a..bf7d115f7da5daec0cd7e0db92e8974320e346cb 100644 --- a/clang/test/CodeGen/arm-neon-numeric-maxmin.c +++ b/clang/test/CodeGen/arm-neon-numeric-maxmin.c @@ -2,28 +2,28 @@ #include -// CHECK-LABEL: define{{.*}} <2 x float> @test_vmaxnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vmaxnm_f32(<2 x float> %a, <2 x float> %b) #0 { // CHECK: [[VMAXNM_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %a, <2 x float> %b) #3 // CHECK: ret <2 x float> [[VMAXNM_V2_I]] float32x2_t test_vmaxnm_f32(float32x2_t a, float32x2_t b) { return vmaxnm_f32(a, b); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vmaxnmq_f32(<4 x float> %a, <4 x float> %b) #1 { // CHECK: [[VMAXNMQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %a, <4 x float> %b) #3 // CHECK: ret <4 x float> [[VMAXNMQ_V2_I]] float32x4_t test_vmaxnmq_f32(float32x4_t a, float32x4_t b) { return vmaxnmq_f32(a, b); } -// CHECK-LABEL: define{{.*}} <2 x float> @test_vminnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 { +// CHECK-LABEL: define{{.*}} <2 x float> @test_vminnm_f32(<2 x float> %a, <2 x float> %b) #0 { // CHECK: [[VMINNM_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %a, <2 x float> %b) #3 // CHECK: ret <2 x float> [[VMINNM_V2_I]] float32x2_t test_vminnm_f32(float32x2_t a, float32x2_t b) { return vminnm_f32(a, b); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #1 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vminnmq_f32(<4 x float> %a, <4 x float> %b) #1 { // CHECK: [[VMINNMQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %a, <4 x float> %b) #3 // CHECK: ret <4 x float> [[VMINNMQ_V2_I]] float32x4_t test_vminnmq_f32(float32x4_t a, float32x4_t b) { diff --git a/clang/test/CodeGen/arm-neon-vcvtX.c b/clang/test/CodeGen/arm-neon-vcvtX.c index aff5847519f749eec79666c78d75be501f847291..79813711ab825afb1346f92afc22dd24557268b7 100644 --- a/clang/test/CodeGen/arm-neon-vcvtX.c +++ b/clang/test/CodeGen/arm-neon-vcvtX.c @@ -2,112 +2,112 @@ #include -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvta_s32_f32(<2 x float> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvta_s32_f32(<2 x float> %a) #0 { // CHECK: [[VCVTA_S32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %a) #3 // CHECK: ret <2 x i32> [[VCVTA_S32_V1_I]] int32x2_t test_vcvta_s32_f32(float32x2_t a) { return vcvta_s32_f32(a); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvta_u32_f32(<2 x float> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvta_u32_f32(<2 x float> %a) #0 { // CHECK: [[VCVTA_U32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %a) #3 // CHECK: ret <2 x i32> [[VCVTA_U32_V1_I]] uint32x2_t test_vcvta_u32_f32(float32x2_t a) { return vcvta_u32_f32(a); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtaq_s32_f32(<4 x float> %a) #1 { // CHECK: [[VCVTAQ_S32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %a) #3 // CHECK: ret <4 x i32> [[VCVTAQ_S32_V1_I]] int32x4_t test_vcvtaq_s32_f32(float32x4_t a) { return vcvtaq_s32_f32(a); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtaq_u32_f32(<4 x float> %a) #1 { // CHECK: [[VCVTAQ_U32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %a) #3 // CHECK: ret <4 x i32> [[VCVTAQ_U32_V1_I]] uint32x4_t test_vcvtaq_u32_f32(float32x4_t a) { return vcvtaq_u32_f32(a); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvtn_s32_f32(<2 x float> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvtn_s32_f32(<2 x float> %a) #0 { // CHECK: [[VCVTN_S32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %a) #3 // CHECK: ret <2 x i32> [[VCVTN_S32_V1_I]] int32x2_t test_vcvtn_s32_f32(float32x2_t a) { return vcvtn_s32_f32(a); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvtn_u32_f32(<2 x float> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvtn_u32_f32(<2 x float> %a) #0 { // CHECK: [[VCVTN_U32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %a) #3 // CHECK: ret <2 x i32> [[VCVTN_U32_V1_I]] uint32x2_t test_vcvtn_u32_f32(float32x2_t a) { return vcvtn_u32_f32(a); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtnq_s32_f32(<4 x float> %a) #1 { // CHECK: [[VCVTNQ_S32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %a) #3 // CHECK: ret <4 x i32> [[VCVTNQ_S32_V1_I]] int32x4_t test_vcvtnq_s32_f32(float32x4_t a) { return vcvtnq_s32_f32(a); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtnq_u32_f32(<4 x float> %a) #1 { // CHECK: [[VCVTNQ_U32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %a) #3 // CHECK: ret <4 x i32> [[VCVTNQ_U32_V1_I]] uint32x4_t test_vcvtnq_u32_f32(float32x4_t a) { return vcvtnq_u32_f32(a); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvtp_s32_f32(<2 x float> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvtp_s32_f32(<2 x float> %a) #0 { // CHECK: [[VCVTP_S32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %a) #3 // CHECK: ret <2 x i32> [[VCVTP_S32_V1_I]] int32x2_t test_vcvtp_s32_f32(float32x2_t a) { return vcvtp_s32_f32(a); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvtp_u32_f32(<2 x float> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvtp_u32_f32(<2 x float> %a) #0 { // CHECK: [[VCVTP_U32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %a) #3 // CHECK: ret <2 x i32> [[VCVTP_U32_V1_I]] uint32x2_t test_vcvtp_u32_f32(float32x2_t a) { return vcvtp_u32_f32(a); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtpq_s32_f32(<4 x float> %a) #1 { // CHECK: [[VCVTPQ_S32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %a) #3 // CHECK: ret <4 x i32> [[VCVTPQ_S32_V1_I]] int32x4_t test_vcvtpq_s32_f32(float32x4_t a) { return vcvtpq_s32_f32(a); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtpq_u32_f32(<4 x float> %a) #1 { // CHECK: [[VCVTPQ_U32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %a) #3 // CHECK: ret <4 x i32> [[VCVTPQ_U32_V1_I]] uint32x4_t test_vcvtpq_u32_f32(float32x4_t a) { return vcvtpq_u32_f32(a); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvtm_s32_f32(<2 x float> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvtm_s32_f32(<2 x float> %a) #0 { // CHECK: [[VCVTM_S32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float> %a) #3 // CHECK: ret <2 x i32> [[VCVTM_S32_V1_I]] int32x2_t test_vcvtm_s32_f32(float32x2_t a) { return vcvtm_s32_f32(a); } -// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvtm_u32_f32(<2 x float> noundef %a) #0 { +// CHECK-LABEL: define{{.*}} <2 x i32> @test_vcvtm_u32_f32(<2 x float> %a) #0 { // CHECK: [[VCVTM_U32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtmu.v2i32.v2f32(<2 x float> %a) #3 // CHECK: ret <2 x i32> [[VCVTM_U32_V1_I]] uint32x2_t test_vcvtm_u32_f32(float32x2_t a) { return vcvtm_u32_f32(a); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtmq_s32_f32(<4 x float> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtmq_s32_f32(<4 x float> %a) #1 { // CHECK: [[VCVTMQ_S32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float> %a) #3 // CHECK: ret <4 x i32> [[VCVTMQ_S32_V1_I]] int32x4_t test_vcvtmq_s32_f32(float32x4_t a) { return vcvtmq_s32_f32(a); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtmq_u32_f32(<4 x float> noundef %a) #1 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcvtmq_u32_f32(<4 x float> %a) #1 { // CHECK: [[VCVTMQ_U32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float> %a) #3 // CHECK: ret <4 x i32> [[VCVTMQ_U32_V1_I]] uint32x4_t test_vcvtmq_u32_f32(float32x4_t a) { diff --git a/clang/test/CodeGen/arm-swiftcall.c b/clang/test/CodeGen/arm-swiftcall.c index 22806ea6f35a440b603d75dddb709629f06d3db3..0104ccf2f7d85325c6245e4113af55f751547f41 100644 --- a/clang/test/CodeGen/arm-swiftcall.c +++ b/clang/test/CodeGen/arm-swiftcall.c @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple armv7-apple-darwin9 -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple armv7s-apple-ios9 -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple armv7k-apple-ios9 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple armv7-apple-darwin9 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple armv7s-apple-ios9 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple armv7k-apple-ios9 -emit-llvm -o - %s | FileCheck %s #define SWIFTCALL __attribute__((swiftcall)) #define SWIFTASYNCCALL __attribute__((swiftasynccall)) diff --git a/clang/test/CodeGen/arm-varargs.c b/clang/test/CodeGen/arm-varargs.c index 5ebaabde46d664fae92e66534cc3260811474dca..f5391b83bfb7a66dadd9ea8800226edce144147a 100644 --- a/clang/test/CodeGen/arm-varargs.c +++ b/clang/test/CodeGen/arm-varargs.c @@ -312,7 +312,7 @@ overaligned_long_long_struct_member overaligned_long_long_struct_member_test() { } void check_start(int n, ...) { -// CHECK-LABEL: define{{.*}} void @check_start(i32 noundef %n, ...) +// CHECK-LABEL: define{{.*}} void @check_start(i32 %n, ...) va_list the_list; va_start(the_list, n); diff --git a/clang/test/CodeGen/arm-vector-arguments.c b/clang/test/CodeGen/arm-vector-arguments.c index 66d131649d0f1225810012cd4aa1ae27b3d8330d..0086270d1807b4df533536aaec64d0fcd50b015a 100644 --- a/clang/test/CodeGen/arm-vector-arguments.c +++ b/clang/test/CodeGen/arm-vector-arguments.c @@ -9,7 +9,7 @@ #include -// CHECK: define{{.*}} void @f0(%struct.int8x16x2_t* noalias sret(%struct.int8x16x2_t) align 16 %agg.result, <16 x i8> noundef %{{.*}}, <16 x i8> noundef %{{.*}}) +// CHECK: define{{.*}} void @f0(%struct.int8x16x2_t* noalias sret(%struct.int8x16x2_t) align 16 %agg.result, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}) int8x16x2_t f0(int8x16_t a0, int8x16_t a1) { return vzipq_s8(a0, a1); } @@ -21,11 +21,11 @@ typedef float T_float32x4 __attribute__ ((__vector_size__ (16))); typedef float T_float32x8 __attribute__ ((__vector_size__ (32))); typedef float T_float32x16 __attribute__ ((__vector_size__ (64))); -// CHECK: define{{.*}} <2 x float> @f1_0(<2 x float> noundef %{{.*}}) +// CHECK: define{{.*}} <2 x float> @f1_0(<2 x float> %{{.*}}) T_float32x2 f1_0(T_float32x2 a0) { return a0; } -// CHECK: define{{.*}} <4 x float> @f1_1(<4 x float> noundef %{{.*}}) +// CHECK: define{{.*}} <4 x float> @f1_1(<4 x float> %{{.*}}) T_float32x4 f1_1(T_float32x4 a0) { return a0; } -// CHECK: define{{.*}} void @f1_2(<8 x float>* noalias sret(<8 x float>) align 32 %{{.*}}, <8 x float> noundef %{{.*}}) +// CHECK: define{{.*}} void @f1_2(<8 x float>* noalias sret(<8 x float>) align 32 %{{.*}}, <8 x float> %{{.*}}) T_float32x8 f1_2(T_float32x8 a0) { return a0; } -// CHECK: define{{.*}} void @f1_3(<16 x float>* noalias sret(<16 x float>) align 64 %{{.*}}, <16 x float> noundef %{{.*}}) +// CHECK: define{{.*}} void @f1_3(<16 x float>* noalias sret(<16 x float>) align 64 %{{.*}}, <16 x float> %{{.*}}) T_float32x16 f1_3(T_float32x16 a0) { return a0; } diff --git a/clang/test/CodeGen/arm-vfp16-arguments.c b/clang/test/CodeGen/arm-vfp16-arguments.c index 29e69e4a75cb39270c5b3e09fa52c28abf834902..e11ec1508bbff9487fca471363b8d3c1d376d734 100644 --- a/clang/test/CodeGen/arm-vfp16-arguments.c +++ b/clang/test/CodeGen/arm-vfp16-arguments.c @@ -19,13 +19,13 @@ float16x4_t g4; float16x8_t g8; void st4(float16x4_t a) { g4 = a; } -// CHECK-SOFT: define{{.*}} void @st4(<2 x i32> noundef %a.coerce) +// CHECK-SOFT: define{{.*}} void @st4(<2 x i32> %a.coerce) // CHECK-SOFT: store <2 x i32> %a.coerce, <2 x i32>* bitcast (<4 x half>* @g4 to <2 x i32>*) // -// CHECK-HARD: define{{.*}} arm_aapcs_vfpcc void @st4(<2 x i32> noundef %a.coerce) +// CHECK-HARD: define{{.*}} arm_aapcs_vfpcc void @st4(<2 x i32> %a.coerce) // CHECK-HARD: store <2 x i32> %a.coerce, <2 x i32>* bitcast (<4 x half>* @g4 to <2 x i32>*) // -// CHECK-FULL: define{{.*}} arm_aapcs_vfpcc void @st4(<4 x half> noundef %a) +// CHECK-FULL: define{{.*}} arm_aapcs_vfpcc void @st4(<4 x half> %a) // CHECK-FULL: store <4 x half> %a, <4 x half>* @g4 float16x4_t ld4(void) { return g4; } @@ -42,13 +42,13 @@ float16x4_t ld4(void) { return g4; } // CHECK-FULL: ret <4 x half> %0 void st8(float16x8_t a) { g8 = a; } -// CHECK-SOFT: define{{.*}} void @st8(<4 x i32> noundef %a.coerce) +// CHECK-SOFT: define{{.*}} void @st8(<4 x i32> %a.coerce) // CHECK-SOFT: store <4 x i32> %a.coerce, <4 x i32>* bitcast (<8 x half>* @g8 to <4 x i32>*) // -// CHECK-HARD: define{{.*}} arm_aapcs_vfpcc void @st8(<4 x i32> noundef %a.coerce) +// CHECK-HARD: define{{.*}} arm_aapcs_vfpcc void @st8(<4 x i32> %a.coerce) // CHECK-HARD: store <4 x i32> %a.coerce, <4 x i32>* bitcast (<8 x half>* @g8 to <4 x i32>*) // -// CHECK-FULL: define{{.*}} arm_aapcs_vfpcc void @st8(<8 x half> noundef %a) +// CHECK-FULL: define{{.*}} arm_aapcs_vfpcc void @st8(<8 x half> %a) // CHECK-FULL: store <8 x half> %a, <8 x half>* @g8 float16x8_t ld8(void) { return g8; } diff --git a/clang/test/CodeGen/arm64-aapcs-arguments.c b/clang/test/CodeGen/arm64-aapcs-arguments.c index 77776d5d1908edfb2ba61c2e11d25cb46e5c8c17..eb98148b211d677a21764f89079f151adc216ef1 100644 --- a/clang/test/CodeGen/arm64-aapcs-arguments.c +++ b/clang/test/CodeGen/arm64-aapcs-arguments.c @@ -3,13 +3,13 @@ // AAPCS clause C.8 says: If the argument has an alignment of 16 then the NGRN // is rounded up to the next even number. -// CHECK: void @test1(i32 noundef %x0, i128 noundef %x2_x3, i128 noundef %x4_x5, i128 noundef %x6_x7, i128 %sp.coerce) +// CHECK: void @test1(i32 %x0, i128 %x2_x3, i128 %x4_x5, i128 %x6_x7, i128 %sp.coerce) typedef union { __int128 a; } Small; void test1(int x0, __int128 x2_x3, __int128 x4_x5, __int128 x6_x7, Small sp) { } -// CHECK: void @test2(i32 noundef %x0, i128 %x2_x3.coerce, i32 noundef %x4, i128 %x6_x7.coerce, i32 noundef %sp, i128 %sp16.coerce) +// CHECK: void @test2(i32 %x0, i128 %x2_x3.coerce, i32 %x4, i128 %x6_x7.coerce, i32 %sp, i128 %sp16.coerce) void test2(int x0, Small x2_x3, int x4, Small x6_x7, int sp, Small sp16) { } @@ -17,7 +17,7 @@ void test2(int x0, Small x2_x3, int x4, Small x6_x7, int sp, Small sp16) { // stack in order to avoid holes. Make sure we get all of them, and not just the // first: -// CHECK: void @test3([4 x float] %s0_s3.coerce, float noundef %s4, [4 x float] %sp.coerce, [4 x float] %sp16.coerce) +// CHECK: void @test3([4 x float] %s0_s3.coerce, float %s4, [4 x float] %sp.coerce, [4 x float] %sp16.coerce) typedef struct { float arr[4]; } HFA; void test3(HFA s0_s3, float s4, HFA sp, HFA sp16) { } @@ -28,7 +28,7 @@ void test3(HFA s0_s3, float s4, HFA sp, HFA sp16) { // fp128] or something, but leaving them as-is retains more information for // users to debug. -// CHECK: void @test4([3 x <16 x i8>] %v0_v2.coerce, [3 x <16 x i8>] %v3_v5.coerce, [3 x <16 x i8>] %sp.coerce, double noundef %sp48, [3 x <16 x i8>] %sp64.coerce) +// CHECK: void @test4([3 x <16 x i8>] %v0_v2.coerce, [3 x <16 x i8>] %v3_v5.coerce, [3 x <16 x i8>] %sp.coerce, double %sp48, [3 x <16 x i8>] %sp64.coerce) typedef __attribute__((neon_vector_type(16))) signed char int8x16_t; typedef struct { int8x16_t arr[3]; } BigHFA; void test4(BigHFA v0_v2, BigHFA v3_v5, BigHFA sp, double sp48, BigHFA sp64) { @@ -37,12 +37,12 @@ void test4(BigHFA v0_v2, BigHFA v3_v5, BigHFA sp, double sp48, BigHFA sp64) { // It's the job of the argument *consumer* to perform the required sign & zero // extensions under AAPCS. There shouldn't be -// CHECK: define{{.*}} i8 @test5(i8 noundef %a, i16 noundef %b) +// CHECK: define{{.*}} i8 @test5(i8 %a, i16 %b) unsigned char test5(unsigned char a, signed short b) { } // __fp16 can be used as a function argument or return type (ACLE 2.0) -// CHECK: define{{.*}} half @test_half(half noundef %{{.*}}) +// CHECK: define{{.*}} half @test_half(half %{{.*}}) __fp16 test_half(__fp16 A) { } // __fp16 is a base type for homogeneous floating-point aggregates for AArch64 (but not 32-bit ARM). diff --git a/clang/test/CodeGen/arm64-abi-vector.c b/clang/test/CodeGen/arm64-abi-vector.c index 0d2fbcbf2237f1d8612a1dab4f3a68aab92373c1..da4af7a8cc82df914597c85fc55592762e53d284 100644 --- a/clang/test/CodeGen/arm64-abi-vector.c +++ b/clang/test/CodeGen/arm64-abi-vector.c @@ -31,7 +31,7 @@ double varargs_vec_2c(int fixed, ...) { } double test_2c(__char2 *in) { -// ANDROID: call double (i32, ...) @varargs_vec_2c(i32 noundef 3, i16 noundef {{%.*}}) +// ANDROID: call double (i32, ...) @varargs_vec_2c(i32 3, i16 {{%.*}}) return varargs_vec_2c(3, *in); } @@ -51,7 +51,7 @@ double varargs_vec_3c(int fixed, ...) { double test_3c(__char3 *in) { // CHECK: test_3c -// CHECK: call double (i32, ...) @varargs_vec_3c(i32 noundef 3, i32 {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_3c(i32 3, i32 {{%.*}}) return varargs_vec_3c(3, *in); } @@ -71,7 +71,7 @@ double varargs_vec_4c(int fixed, ...) { double test_4c(__char4 *in) { // CHECK: test_4c -// CHECK: call double (i32, ...) @varargs_vec_4c(i32 noundef 4, i32 noundef {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_4c(i32 4, i32 {{%.*}}) return varargs_vec_4c(4, *in); } @@ -91,7 +91,7 @@ double varargs_vec_5c(int fixed, ...) { double test_5c(__char5 *in) { // CHECK: test_5c -// CHECK: call double (i32, ...) @varargs_vec_5c(i32 noundef 5, <2 x i32> {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_5c(i32 5, <2 x i32> {{%.*}}) return varargs_vec_5c(5, *in); } @@ -113,7 +113,7 @@ double varargs_vec_9c(int fixed, ...) { double test_9c(__char9 *in) { // CHECK: test_9c -// CHECK: call double (i32, ...) @varargs_vec_9c(i32 noundef 9, <4 x i32> {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_9c(i32 9, <4 x i32> {{%.*}}) return varargs_vec_9c(9, *in); } @@ -133,7 +133,7 @@ double varargs_vec_19c(int fixed, ...) { double test_19c(__char19 *in) { // CHECK: test_19c -// CHECK: call double (i32, ...) @varargs_vec_19c(i32 noundef 19, <19 x i8>* noundef {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_19c(i32 19, <19 x i8>* {{%.*}}) return varargs_vec_19c(19, *in); } @@ -153,7 +153,7 @@ double varargs_vec_3s(int fixed, ...) { double test_3s(__short3 *in) { // CHECK: test_3s -// CHECK: call double (i32, ...) @varargs_vec_3s(i32 noundef 3, <2 x i32> {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_3s(i32 3, <2 x i32> {{%.*}}) return varargs_vec_3s(3, *in); } @@ -175,7 +175,7 @@ double varargs_vec_5s(int fixed, ...) { double test_5s(__short5 *in) { // CHECK: test_5s -// CHECK: call double (i32, ...) @varargs_vec_5s(i32 noundef 5, <4 x i32> {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_5s(i32 5, <4 x i32> {{%.*}}) return varargs_vec_5s(5, *in); } @@ -197,7 +197,7 @@ double varargs_vec_3i(int fixed, ...) { double test_3i(__int3 *in) { // CHECK: test_3i -// CHECK: call double (i32, ...) @varargs_vec_3i(i32 noundef 3, <4 x i32> {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_3i(i32 3, <4 x i32> {{%.*}}) return varargs_vec_3i(3, *in); } @@ -218,7 +218,7 @@ double varargs_vec_5i(int fixed, ...) { double test_5i(__int5 *in) { // CHECK: test_5i -// CHECK: call double (i32, ...) @varargs_vec_5i(i32 noundef 5, <5 x i32>* noundef {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_5i(i32 5, <5 x i32>* {{%.*}}) return varargs_vec_5i(5, *in); } @@ -239,7 +239,7 @@ double varargs_vec_3d(int fixed, ...) { double test_3d(__double3 *in) { // CHECK: test_3d -// CHECK: call double (i32, ...) @varargs_vec_3d(i32 noundef 3, <3 x double>* noundef {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_3d(i32 3, <3 x double>* {{%.*}}) return varargs_vec_3d(3, *in); } @@ -301,7 +301,7 @@ double test(__char3 *c3, __char5 *c5, __char9 *c9, __char19 *c19, __short3 *s3, __short5 *s5, __int3 *i3, __int5 *i5, __double3 *d3) { double ret = varargs_vec(3, *c3, *c5, *c9, *c19, *s3, *s5, *i3, *i5, *d3); -// CHECK: call double (i32, ...) @varargs_vec(i32 noundef 3, i32 {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> {{%.*}}, <19 x i8>* noundef {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <5 x i32>* noundef {{%.*}}, <3 x double>* noundef {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec(i32 3, i32 {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> {{%.*}}, <19 x i8>* {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <5 x i32>* {{%.*}}, <3 x double>* {{%.*}}) return ret; } @@ -317,7 +317,7 @@ __attribute__((noinline)) double args_vec_3c(int fixed, __char3 c3) { double fixed_3c(__char3 *in) { // CHECK: fixed_3c -// CHECK: call double @args_vec_3c(i32 noundef 3, i32 {{%.*}}) +// CHECK: call double @args_vec_3c(i32 3, i32 {{%.*}}) return args_vec_3c(3, *in); } @@ -333,7 +333,7 @@ __attribute__((noinline)) double args_vec_5c(int fixed, __char5 c5) { double fixed_5c(__char5 *in) { // CHECK: fixed_5c -// CHECK: call double @args_vec_5c(i32 noundef 5, <2 x i32> {{%.*}}) +// CHECK: call double @args_vec_5c(i32 5, <2 x i32> {{%.*}}) return args_vec_5c(5, *in); } @@ -349,7 +349,7 @@ __attribute__((noinline)) double args_vec_9c(int fixed, __char9 c9) { double fixed_9c(__char9 *in) { // CHECK: fixed_9c -// CHECK: call double @args_vec_9c(i32 noundef 9, <4 x i32> {{%.*}}) +// CHECK: call double @args_vec_9c(i32 9, <4 x i32> {{%.*}}) return args_vec_9c(9, *in); } @@ -363,7 +363,7 @@ __attribute__((noinline)) double args_vec_19c(int fixed, __char19 c19) { double fixed_19c(__char19 *in) { // CHECK: fixed_19c -// CHECK: call double @args_vec_19c(i32 noundef 19, <19 x i8>* noundef {{%.*}}) +// CHECK: call double @args_vec_19c(i32 19, <19 x i8>* {{%.*}}) return args_vec_19c(19, *in); } @@ -379,7 +379,7 @@ __attribute__((noinline)) double args_vec_3s(int fixed, __short3 c3) { double fixed_3s(__short3 *in) { // CHECK: fixed_3s -// CHECK: call double @args_vec_3s(i32 noundef 3, <2 x i32> {{%.*}}) +// CHECK: call double @args_vec_3s(i32 3, <2 x i32> {{%.*}}) return args_vec_3s(3, *in); } @@ -395,7 +395,7 @@ __attribute__((noinline)) double args_vec_5s(int fixed, __short5 c5) { double fixed_5s(__short5 *in) { // CHECK: fixed_5s -// CHECK: call double @args_vec_5s(i32 noundef 5, <4 x i32> {{%.*}}) +// CHECK: call double @args_vec_5s(i32 5, <4 x i32> {{%.*}}) return args_vec_5s(5, *in); } @@ -411,7 +411,7 @@ __attribute__((noinline)) double args_vec_3i(int fixed, __int3 c3) { double fixed_3i(__int3 *in) { // CHECK: fixed_3i -// CHECK: call double @args_vec_3i(i32 noundef 3, <4 x i32> {{%.*}}) +// CHECK: call double @args_vec_3i(i32 3, <4 x i32> {{%.*}}) return args_vec_3i(3, *in); } @@ -425,7 +425,7 @@ __attribute__((noinline)) double args_vec_5i(int fixed, __int5 c5) { double fixed_5i(__int5 *in) { // CHECK: fixed_5i -// CHECK: call double @args_vec_5i(i32 noundef 5, <5 x i32>* noundef {{%.*}}) +// CHECK: call double @args_vec_5i(i32 5, <5 x i32>* {{%.*}}) return args_vec_5i(5, *in); } @@ -441,6 +441,6 @@ __attribute__((noinline)) double args_vec_3d(int fixed, __double3 c3) { double fixed_3d(__double3 *in) { // CHECK: fixed_3d -// CHECK: call double @args_vec_3d(i32 noundef 3, <3 x double>* noundef {{%.*}}) +// CHECK: call double @args_vec_3d(i32 3, <3 x double>* {{%.*}}) return args_vec_3d(3, *in); } diff --git a/clang/test/CodeGen/arm64-arguments.c b/clang/test/CodeGen/arm64-arguments.c index 0468f2c29fdf01e0b617eec784148f6257bf09b1..b362346aa8a82052c760e032d5a93da49f54dff6 100644 --- a/clang/test/CodeGen/arm64-arguments.c +++ b/clang/test/CodeGen/arm64-arguments.c @@ -161,12 +161,12 @@ void f32(struct s32 s) { } // A composite type larger than 16 bytes should be passed indirectly. struct s33 { char buf[32*32]; }; void f33(struct s33 s) { } -// CHECK: define{{.*}} void @f33(%struct.s33* noundef %s) +// CHECK: define{{.*}} void @f33(%struct.s33* %s) struct s34 { char c; }; void f34(struct s34 s); void g34(struct s34 *s) { f34(*s); } -// CHECK: @g34(%struct.s34* noundef %s) +// CHECK: @g34(%struct.s34* %s) // CHECK: %[[a:.*]] = load i8, i8* %{{.*}} // CHECK: zext i8 %[[a]] to i64 // CHECK: call void @f34(i64 %{{.*}}) @@ -198,7 +198,7 @@ double t2(int i, ...) { #include // Homogeneous Vector Aggregate as return type and argument type. -// CHECK: define{{.*}} %struct.int8x16x2_t @f0_0(<16 x i8> noundef %{{.*}}, <16 x i8> noundef %{{.*}}) +// CHECK: define{{.*}} %struct.int8x16x2_t @f0_0(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) int8x16x2_t f0_0(int8x16_t a0, int8x16_t a1) { return vzipq_s8(a0, a1); } @@ -209,14 +209,14 @@ typedef float T_float32x4 __attribute__ ((__vector_size__ (16))); typedef float T_float32x8 __attribute__ ((__vector_size__ (32))); typedef float T_float32x16 __attribute__ ((__vector_size__ (64))); -// CHECK: define{{.*}} <2 x float> @f1_0(<2 x float> noundef %{{.*}}) +// CHECK: define{{.*}} <2 x float> @f1_0(<2 x float> %{{.*}}) T_float32x2 f1_0(T_float32x2 a0) { return a0; } -// CHECK: define{{.*}} <4 x float> @f1_1(<4 x float> noundef %{{.*}}) +// CHECK: define{{.*}} <4 x float> @f1_1(<4 x float> %{{.*}}) T_float32x4 f1_1(T_float32x4 a0) { return a0; } // Vector with length bigger than 16-byte is illegal and is passed indirectly. -// CHECK: define{{.*}} void @f1_2(<8 x float>* noalias sret(<8 x float>) align 16 %{{.*}}, <8 x float>* noundef %0) +// CHECK: define{{.*}} void @f1_2(<8 x float>* noalias sret(<8 x float>) align 16 %{{.*}}, <8 x float>* %0) T_float32x8 f1_2(T_float32x8 a0) { return a0; } -// CHECK: define{{.*}} void @f1_3(<16 x float>* noalias sret(<16 x float>) align 16 %{{.*}}, <16 x float>* noundef %0) +// CHECK: define{{.*}} void @f1_3(<16 x float>* noalias sret(<16 x float>) align 16 %{{.*}}, <16 x float>* %0) T_float32x16 f1_3(T_float32x16 a0) { return a0; } // Testing alignment with aggregates: HFA, aggregates with size <= 16 bytes and @@ -229,7 +229,7 @@ typedef struct s35 s35_with_align; typedef __attribute__((neon_vector_type(4))) float float32x4_t; float32x4_t f35(int i, s35_with_align s1, s35_with_align s2) { -// CHECK: define{{.*}} <4 x float> @f35(i32 noundef %i, [4 x float] %s1.coerce, [4 x float] %s2.coerce) +// CHECK: define{{.*}} <4 x float> @f35(i32 %i, [4 x float] %s1.coerce, [4 x float] %s2.coerce) // CHECK: %s1 = alloca %struct.s35, align 16 // CHECK: %s2 = alloca %struct.s35, align 16 // CHECK: %[[a:.*]] = bitcast %struct.s35* %s1 to <4 x float>* @@ -249,7 +249,7 @@ typedef struct s36 s36_with_align; typedef __attribute__((neon_vector_type(4))) int int32x4_t; int32x4_t f36(int i, s36_with_align s1, s36_with_align s2) { -// CHECK: define{{.*}} <4 x i32> @f36(i32 noundef %i, i128 %s1.coerce, i128 %s2.coerce) +// CHECK: define{{.*}} <4 x i32> @f36(i32 %i, i128 %s1.coerce, i128 %s2.coerce) // CHECK: %s1 = alloca %struct.s36, align 16 // CHECK: %s2 = alloca %struct.s36, align 16 // CHECK: store i128 %s1.coerce, i128* %{{.*}}, align 16 @@ -270,7 +270,7 @@ struct s37 typedef struct s37 s37_with_align; int32x4_t f37(int i, s37_with_align s1, s37_with_align s2) { -// CHECK: define{{.*}} <4 x i32> @f37(i32 noundef %i, %struct.s37* noundef %s1, %struct.s37* noundef %s2) +// CHECK: define{{.*}} <4 x i32> @f37(i32 %i, %struct.s37* %s1, %struct.s37* %s2) // CHECK: %[[a:.*]] = bitcast %struct.s37* %s1 to <4 x i32>* // CHECK: load <4 x i32>, <4 x i32>* %[[a]], align 16 // CHECK: %[[b:.*]] = bitcast %struct.s37* %s2 to <4 x i32>* @@ -286,7 +286,7 @@ int32x4_t caller37() { // CHECK: %[[b:.*]] = alloca %struct.s37, align 16 // CHECK: call void @llvm.memcpy // CHECK: call void @llvm.memcpy -// CHECK: call <4 x i32> @f37(i32 noundef 3, %struct.s37* noundef %[[a]], %struct.s37* noundef %[[b]]) +// CHECK: call <4 x i32> @f37(i32 3, %struct.s37* %[[a]], %struct.s37* %[[b]]) return f37(3, g37, g37); } @@ -305,7 +305,7 @@ typedef struct s38 s38_no_align; // passing structs in registers __attribute__ ((noinline)) int f38(int i, s38_no_align s1, s38_no_align s2) { -// CHECK: define{{.*}} i32 @f38(i32 noundef %i, i64 %s1.coerce, i64 %s2.coerce) +// CHECK: define{{.*}} i32 @f38(i32 %i, i64 %s1.coerce, i64 %s2.coerce) // CHECK: %s1 = alloca %struct.s38, align 4 // CHECK: %s2 = alloca %struct.s38, align 4 // CHECK: store i64 %s1.coerce, i64* %{{.*}}, align 4 @@ -322,14 +322,14 @@ int caller38() { // CHECK: define{{.*}} i32 @caller38() // CHECK: %[[a:.*]] = load i64, i64* bitcast (%struct.s38* @g38 to i64*), align 4 // CHECK: %[[b:.*]] = load i64, i64* bitcast (%struct.s38* @g38_2 to i64*), align 4 -// CHECK: call i32 @f38(i32 noundef 3, i64 %[[a]], i64 %[[b]]) +// CHECK: call i32 @f38(i32 3, i64 %[[a]], i64 %[[b]]) return f38(3, g38, g38_2); } // passing structs on stack __attribute__ ((noinline)) int f38_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, s38_no_align s1, s38_no_align s2) { -// CHECK: define{{.*}} i32 @f38_stack(i32 noundef %i, i32 noundef %i2, i32 noundef %i3, i32 noundef %i4, i32 noundef %i5, i32 noundef %i6, i32 noundef %i7, i32 noundef %i8, i32 noundef %i9, i64 %s1.coerce, i64 %s2.coerce) +// CHECK: define{{.*}} i32 @f38_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i64 %s1.coerce, i64 %s2.coerce) // CHECK: %s1 = alloca %struct.s38, align 4 // CHECK: %s2 = alloca %struct.s38, align 4 // CHECK: store i64 %s1.coerce, i64* %{{.*}}, align 4 @@ -344,7 +344,7 @@ int caller38_stack() { // CHECK: define{{.*}} i32 @caller38_stack() // CHECK: %[[a:.*]] = load i64, i64* bitcast (%struct.s38* @g38 to i64*), align 4 // CHECK: %[[b:.*]] = load i64, i64* bitcast (%struct.s38* @g38_2 to i64*), align 4 -// CHECK: call i32 @f38_stack(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8, i32 noundef 9, i64 %[[a]], i64 %[[b]]) +// CHECK: call i32 @f38_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i64 %[[a]], i64 %[[b]]) return f38_stack(1, 2, 3, 4, 5, 6, 7, 8, 9, g38, g38_2); } @@ -358,7 +358,7 @@ typedef struct s39 s39_with_align; // passing aligned structs in registers __attribute__ ((noinline)) int f39(int i, s39_with_align s1, s39_with_align s2) { -// CHECK: define{{.*}} i32 @f39(i32 noundef %i, i128 %s1.coerce, i128 %s2.coerce) +// CHECK: define{{.*}} i32 @f39(i32 %i, i128 %s1.coerce, i128 %s2.coerce) // CHECK: %s1 = alloca %struct.s39, align 16 // CHECK: %s2 = alloca %struct.s39, align 16 // CHECK: store i128 %s1.coerce, i128* %{{.*}}, align 16 @@ -375,14 +375,14 @@ int caller39() { // CHECK: define{{.*}} i32 @caller39() // CHECK: %[[a:.*]] = load i128, i128* bitcast (%struct.s39* @g39 to i128*), align 16 // CHECK: %[[b:.*]] = load i128, i128* bitcast (%struct.s39* @g39_2 to i128*), align 16 -// CHECK: call i32 @f39(i32 noundef 3, i128 %[[a]], i128 %[[b]]) +// CHECK: call i32 @f39(i32 3, i128 %[[a]], i128 %[[b]]) return f39(3, g39, g39_2); } // passing aligned structs on stack __attribute__ ((noinline)) int f39_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, s39_with_align s1, s39_with_align s2) { -// CHECK: define{{.*}} i32 @f39_stack(i32 noundef %i, i32 noundef %i2, i32 noundef %i3, i32 noundef %i4, i32 noundef %i5, i32 noundef %i6, i32 noundef %i7, i32 noundef %i8, i32 noundef %i9, i128 %s1.coerce, i128 %s2.coerce) +// CHECK: define{{.*}} i32 @f39_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i128 %s1.coerce, i128 %s2.coerce) // CHECK: %s1 = alloca %struct.s39, align 16 // CHECK: %s2 = alloca %struct.s39, align 16 // CHECK: store i128 %s1.coerce, i128* %{{.*}}, align 16 @@ -397,7 +397,7 @@ int caller39_stack() { // CHECK: define{{.*}} i32 @caller39_stack() // CHECK: %[[a:.*]] = load i128, i128* bitcast (%struct.s39* @g39 to i128*), align 16 // CHECK: %[[b:.*]] = load i128, i128* bitcast (%struct.s39* @g39_2 to i128*), align 16 -// CHECK: call i32 @f39_stack(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8, i32 noundef 9, i128 %[[a]], i128 %[[b]]) +// CHECK: call i32 @f39_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i128 %[[a]], i128 %[[b]]) return f39_stack(1, 2, 3, 4, 5, 6, 7, 8, 9, g39, g39_2); } @@ -413,7 +413,7 @@ typedef struct s40 s40_no_align; // passing structs in registers __attribute__ ((noinline)) int f40(int i, s40_no_align s1, s40_no_align s2) { -// CHECK: define{{.*}} i32 @f40(i32 noundef %i, [2 x i64] %s1.coerce, [2 x i64] %s2.coerce) +// CHECK: define{{.*}} i32 @f40(i32 %i, [2 x i64] %s1.coerce, [2 x i64] %s2.coerce) // CHECK: %s1 = alloca %struct.s40, align 4 // CHECK: %s2 = alloca %struct.s40, align 4 // CHECK: store [2 x i64] %s1.coerce, [2 x i64]* %{{.*}}, align 4 @@ -430,14 +430,14 @@ int caller40() { // CHECK: define{{.*}} i32 @caller40() // CHECK: %[[a:.*]] = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4 // CHECK: %[[b:.*]] = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 4 -// CHECK: call i32 @f40(i32 noundef 3, [2 x i64] %[[a]], [2 x i64] %[[b]]) +// CHECK: call i32 @f40(i32 3, [2 x i64] %[[a]], [2 x i64] %[[b]]) return f40(3, g40, g40_2); } // passing structs on stack __attribute__ ((noinline)) int f40_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, s40_no_align s1, s40_no_align s2) { -// CHECK: define{{.*}} i32 @f40_stack(i32 noundef %i, i32 noundef %i2, i32 noundef %i3, i32 noundef %i4, i32 noundef %i5, i32 noundef %i6, i32 noundef %i7, i32 noundef %i8, i32 noundef %i9, [2 x i64] %s1.coerce, [2 x i64] %s2.coerce) +// CHECK: define{{.*}} i32 @f40_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, [2 x i64] %s1.coerce, [2 x i64] %s2.coerce) // CHECK: %s1 = alloca %struct.s40, align 4 // CHECK: %s2 = alloca %struct.s40, align 4 // CHECK: store [2 x i64] %s1.coerce, [2 x i64]* %{{.*}}, align 4 @@ -452,7 +452,7 @@ int caller40_stack() { // CHECK: define{{.*}} i32 @caller40_stack() // CHECK: %[[a:.*]] = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4 // CHECK: %[[b:.*]] = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 4 -// CHECK: call i32 @f40_stack(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8, i32 noundef 9, [2 x i64] %[[a]], [2 x i64] %[[b]]) +// CHECK: call i32 @f40_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, [2 x i64] %[[a]], [2 x i64] %[[b]]) return f40_stack(1, 2, 3, 4, 5, 6, 7, 8, 9, g40, g40_2); } @@ -468,7 +468,7 @@ typedef struct s41 s41_with_align; // passing aligned structs in registers __attribute__ ((noinline)) int f41(int i, s41_with_align s1, s41_with_align s2) { -// CHECK: define{{.*}} i32 @f41(i32 noundef %i, i128 %s1.coerce, i128 %s2.coerce) +// CHECK: define{{.*}} i32 @f41(i32 %i, i128 %s1.coerce, i128 %s2.coerce) // CHECK: %s1 = alloca %struct.s41, align 16 // CHECK: %s2 = alloca %struct.s41, align 16 // CHECK: store i128 %s1.coerce, i128* %{{.*}}, align 16 @@ -485,14 +485,14 @@ int caller41() { // CHECK: define{{.*}} i32 @caller41() // CHECK: %[[a:.*]] = load i128, i128* bitcast (%struct.s41* @g41 to i128*), align 16 // CHECK: %[[b:.*]] = load i128, i128* bitcast (%struct.s41* @g41_2 to i128*), align 16 -// CHECK: call i32 @f41(i32 noundef 3, i128 %[[a]], i128 %[[b]]) +// CHECK: call i32 @f41(i32 3, i128 %[[a]], i128 %[[b]]) return f41(3, g41, g41_2); } // passing aligned structs on stack __attribute__ ((noinline)) int f41_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, s41_with_align s1, s41_with_align s2) { -// CHECK: define{{.*}} i32 @f41_stack(i32 noundef %i, i32 noundef %i2, i32 noundef %i3, i32 noundef %i4, i32 noundef %i5, i32 noundef %i6, i32 noundef %i7, i32 noundef %i8, i32 noundef %i9, i128 %s1.coerce, i128 %s2.coerce) +// CHECK: define{{.*}} i32 @f41_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i128 %s1.coerce, i128 %s2.coerce) // CHECK: %s1 = alloca %struct.s41, align 16 // CHECK: %s2 = alloca %struct.s41, align 16 // CHECK: store i128 %s1.coerce, i128* %{{.*}}, align 16 @@ -507,7 +507,7 @@ int caller41_stack() { // CHECK: define{{.*}} i32 @caller41_stack() // CHECK: %[[a:.*]] = load i128, i128* bitcast (%struct.s41* @g41 to i128*), align 16 // CHECK: %[[b:.*]] = load i128, i128* bitcast (%struct.s41* @g41_2 to i128*), align 16 -// CHECK: call i32 @f41_stack(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8, i32 noundef 9, i128 %[[a]], i128 %[[b]]) +// CHECK: call i32 @f41_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i128 %[[a]], i128 %[[b]]) return f41_stack(1, 2, 3, 4, 5, 6, 7, 8, 9, g41, g41_2); } @@ -525,7 +525,7 @@ typedef struct s42 s42_no_align; // passing structs in registers __attribute__ ((noinline)) int f42(int i, s42_no_align s1, s42_no_align s2) { -// CHECK: define{{.*}} i32 @f42(i32 noundef %i, %struct.s42* noundef %s1, %struct.s42* noundef %s2) +// CHECK: define{{.*}} i32 @f42(i32 %i, %struct.s42* %s1, %struct.s42* %s2) // CHECK: getelementptr inbounds %struct.s42, %struct.s42* %s1, i32 0, i32 0 // CHECK: getelementptr inbounds %struct.s42, %struct.s42* %s2, i32 0, i32 0 // CHECK: getelementptr inbounds %struct.s42, %struct.s42* %s1, i32 0, i32 1 @@ -542,14 +542,14 @@ int caller42() { // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64 // CHECK: %[[d:.*]] = bitcast %struct.s42* %[[b]] to i8* // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64 -// CHECK: call i32 @f42(i32 noundef 3, %struct.s42* noundef %[[a]], %struct.s42* noundef %[[b]]) +// CHECK: call i32 @f42(i32 3, %struct.s42* %[[a]], %struct.s42* %[[b]]) return f42(3, g42, g42_2); } // passing structs on stack __attribute__ ((noinline)) int f42_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, s42_no_align s1, s42_no_align s2) { -// CHECK: define{{.*}} i32 @f42_stack(i32 noundef %i, i32 noundef %i2, i32 noundef %i3, i32 noundef %i4, i32 noundef %i5, i32 noundef %i6, i32 noundef %i7, i32 noundef %i8, i32 noundef %i9, %struct.s42* noundef %s1, %struct.s42* noundef %s2) +// CHECK: define{{.*}} i32 @f42_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, %struct.s42* %s1, %struct.s42* %s2) // CHECK: getelementptr inbounds %struct.s42, %struct.s42* %s1, i32 0, i32 0 // CHECK: getelementptr inbounds %struct.s42, %struct.s42* %s2, i32 0, i32 0 // CHECK: getelementptr inbounds %struct.s42, %struct.s42* %s1, i32 0, i32 1 @@ -564,7 +564,7 @@ int caller42_stack() { // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64 // CHECK: %[[d:.*]] = bitcast %struct.s42* %[[b]] to i8* // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64 -// CHECK: call i32 @f42_stack(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8, i32 noundef 9, %struct.s42* noundef %[[a]], %struct.s42* noundef %[[b]]) +// CHECK: call i32 @f42_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, %struct.s42* %[[a]], %struct.s42* %[[b]]) return f42_stack(1, 2, 3, 4, 5, 6, 7, 8, 9, g42, g42_2); } @@ -582,7 +582,7 @@ typedef struct s43 s43_with_align; // passing aligned structs in registers __attribute__ ((noinline)) int f43(int i, s43_with_align s1, s43_with_align s2) { -// CHECK: define{{.*}} i32 @f43(i32 noundef %i, %struct.s43* noundef %s1, %struct.s43* noundef %s2) +// CHECK: define{{.*}} i32 @f43(i32 %i, %struct.s43* %s1, %struct.s43* %s2) // CHECK: getelementptr inbounds %struct.s43, %struct.s43* %s1, i32 0, i32 0 // CHECK: getelementptr inbounds %struct.s43, %struct.s43* %s2, i32 0, i32 0 // CHECK: getelementptr inbounds %struct.s43, %struct.s43* %s1, i32 0, i32 1 @@ -599,14 +599,14 @@ int caller43() { // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64 // CHECK: %[[d:.*]] = bitcast %struct.s43* %[[b]] to i8* // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64 -// CHECK: call i32 @f43(i32 noundef 3, %struct.s43* noundef %[[a]], %struct.s43* noundef %[[b]]) +// CHECK: call i32 @f43(i32 3, %struct.s43* %[[a]], %struct.s43* %[[b]]) return f43(3, g43, g43_2); } // passing aligned structs on stack __attribute__ ((noinline)) int f43_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, s43_with_align s1, s43_with_align s2) { -// CHECK: define{{.*}} i32 @f43_stack(i32 noundef %i, i32 noundef %i2, i32 noundef %i3, i32 noundef %i4, i32 noundef %i5, i32 noundef %i6, i32 noundef %i7, i32 noundef %i8, i32 noundef %i9, %struct.s43* noundef %s1, %struct.s43* noundef %s2) +// CHECK: define{{.*}} i32 @f43_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, %struct.s43* %s1, %struct.s43* %s2) // CHECK: getelementptr inbounds %struct.s43, %struct.s43* %s1, i32 0, i32 0 // CHECK: getelementptr inbounds %struct.s43, %struct.s43* %s2, i32 0, i32 0 // CHECK: getelementptr inbounds %struct.s43, %struct.s43* %s1, i32 0, i32 1 @@ -621,7 +621,7 @@ int caller43_stack() { // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64 // CHECK: %[[d:.*]] = bitcast %struct.s43* %[[b]] to i8* // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64 -// CHECK: call i32 @f43_stack(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8, i32 noundef 9, %struct.s43* noundef %[[a]], %struct.s43* noundef %[[b]]) +// CHECK: call i32 @f43_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, %struct.s43* %[[a]], %struct.s43* %[[b]]) return f43_stack(1, 2, 3, 4, 5, 6, 7, 8, 9, g43, g43_2); } @@ -630,24 +630,24 @@ int caller43_stack() { __attribute__ ((noinline)) int f40_split(int i, int i2, int i3, int i4, int i5, int i6, int i7, s40_no_align s1, s40_no_align s2) { -// CHECK: define{{.*}} i32 @f40_split(i32 noundef %i, i32 noundef %i2, i32 noundef %i3, i32 noundef %i4, i32 noundef %i5, i32 noundef %i6, i32 noundef %i7, [2 x i64] %s1.coerce, [2 x i64] %s2.coerce) +// CHECK: define{{.*}} i32 @f40_split(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, [2 x i64] %s1.coerce, [2 x i64] %s2.coerce) return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + s1.s + s2.s; } int caller40_split() { // CHECK: define{{.*}} i32 @caller40_split() -// CHECK: call i32 @f40_split(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, [2 x i64] %{{.*}} [2 x i64] %{{.*}}) +// CHECK: call i32 @f40_split(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, [2 x i64] %{{.*}} [2 x i64] %{{.*}}) return f40_split(1, 2, 3, 4, 5, 6, 7, g40, g40_2); } __attribute__ ((noinline)) int f41_split(int i, int i2, int i3, int i4, int i5, int i6, int i7, s41_with_align s1, s41_with_align s2) { -// CHECK: define{{.*}} i32 @f41_split(i32 noundef %i, i32 noundef %i2, i32 noundef %i3, i32 noundef %i4, i32 noundef %i5, i32 noundef %i6, i32 noundef %i7, i128 %s1.coerce, i128 %s2.coerce) +// CHECK: define{{.*}} i32 @f41_split(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i128 %s1.coerce, i128 %s2.coerce) return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + s1.s + s2.s; } int caller41_split() { // CHECK: define{{.*}} i32 @caller41_split() -// CHECK: call i32 @f41_split(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, i32 noundef 6, i32 noundef 7, i128 %{{.*}}, i128 %{{.*}}) +// CHECK: call i32 @f41_split(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i128 %{{.*}}, i128 %{{.*}}) return f41_split(1, 2, 3, 4, 5, 6, 7, g41, g41_2); } @@ -657,7 +657,7 @@ struct HFA { }; float test_hfa(int n, ...) { -// CHECK-LE-LABEL: define{{.*}} float @test_hfa(i32 noundef %n, ...) +// CHECK-LE-LABEL: define{{.*}} float @test_hfa(i32 %n, ...) // CHECK-LE: [[THELIST:%.*]] = alloca i8* // CHECK-LE: [[CURLIST:%.*]] = load i8*, i8** [[THELIST]] @@ -673,8 +673,8 @@ float test_hfa(int n, ...) { } float test_hfa_call(struct HFA *a) { -// CHECK-LABEL: define{{.*}} float @test_hfa_call(%struct.HFA* noundef %a) -// CHECK: call float (i32, ...) @test_hfa(i32 noundef 1, [4 x float] {{.*}}) +// CHECK-LABEL: define{{.*}} float @test_hfa_call(%struct.HFA* %a) +// CHECK: call float (i32, ...) @test_hfa(i32 1, [4 x float] {{.*}}) test_hfa(1, *a); } @@ -683,7 +683,7 @@ struct TooBigHFA { }; float test_toobig_hfa(int n, ...) { -// CHECK-LE-LABEL: define{{.*}} float @test_toobig_hfa(i32 noundef %n, ...) +// CHECK-LE-LABEL: define{{.*}} float @test_toobig_hfa(i32 %n, ...) // CHECK-LE: [[THELIST:%.*]] = alloca i8* // CHECK-LE: [[CURLIST:%.*]] = load i8*, i8** [[THELIST]] @@ -705,7 +705,7 @@ struct HVA { }; int32x4_t test_hva(int n, ...) { -// CHECK-LE-LABEL: define{{.*}} <4 x i32> @test_hva(i32 noundef %n, ...) +// CHECK-LE-LABEL: define{{.*}} <4 x i32> @test_hva(i32 %n, ...) // CHECK-LE: [[THELIST:%.*]] = alloca i8* // CHECK-LE: [[CURLIST:%.*]] = load i8*, i8** [[THELIST]] @@ -731,7 +731,7 @@ struct TooBigHVA { }; int32x4_t test_toobig_hva(int n, ...) { -// CHECK-LE-LABEL: define{{.*}} <4 x i32> @test_toobig_hva(i32 noundef %n, ...) +// CHECK-LE-LABEL: define{{.*}} <4 x i32> @test_toobig_hva(i32 %n, ...) // CHECK-LE: [[THELIST:%.*]] = alloca i8* // CHECK-LE: [[CURLIST:%.*]] = load i8*, i8** [[THELIST]] @@ -752,7 +752,7 @@ typedef __attribute__((__ext_vector_type__(3))) float float32x3_t; typedef struct { float32x3_t arr[4]; } HFAv3; float32x3_t test_hva_v3(int n, ...) { -// CHECK-LE-LABEL: define{{.*}} <3 x float> @test_hva_v3(i32 noundef %n, ...) +// CHECK-LE-LABEL: define{{.*}} <3 x float> @test_hva_v3(i32 %n, ...) // CHECK-LE: [[THELIST:%.*]] = alloca i8* // CHECK-LE: [[CURLIST:%.*]] = load i8*, i8** [[THELIST]] @@ -774,7 +774,7 @@ float32x3_t test_hva_v3(int n, ...) { } float32x3_t test_hva_v3_call(HFAv3 *a) { -// CHECK-LABEL: define{{.*}} <3 x float> @test_hva_v3_call(%struct.HFAv3* noundef %a) -// CHECK: call <3 x float> (i32, ...) @test_hva_v3(i32 noundef 1, [4 x <4 x float>] {{.*}}) +// CHECK-LABEL: define{{.*}} <3 x float> @test_hva_v3_call(%struct.HFAv3* %a) +// CHECK: call <3 x float> (i32, ...) @test_hva_v3(i32 1, [4 x <4 x float>] {{.*}}) return test_hva_v3(1, *a); } diff --git a/clang/test/CodeGen/arm64-microsoft-arguments.cpp b/clang/test/CodeGen/arm64-microsoft-arguments.cpp index 8d5183c6c9a18d99148ae9176694adbfac722ed3..d9160f8ded0cdaa3e587bd64472c4fe4b3672ef4 100644 --- a/clang/test/CodeGen/arm64-microsoft-arguments.cpp +++ b/clang/test/CodeGen/arm64-microsoft-arguments.cpp @@ -29,7 +29,7 @@ S2 f2() { // Pass and return for type size > 16 bytes. // CHECK: define {{.*}} void @{{.*}}f3{{.*}}(%struct.S3* noalias sret(%struct.S3) align 4 %agg.result) -// CHECK: call void {{.*}}func3{{.*}}(%struct.S3* sret(%struct.S3) align 4 %agg.result, %struct.S3* noundef %agg.tmp) +// CHECK: call void {{.*}}func3{{.*}}(%struct.S3* sret(%struct.S3) align 4 %agg.result, %struct.S3* %agg.tmp) struct S3 { int a[5]; }; @@ -57,7 +57,7 @@ S4 f4() { // Pass and return from instance method called from instance method. // CHECK: define {{.*}} void @{{.*}}bar@Q1{{.*}}(%class.Q1* {{[^,]*}} %this, %class.P1* inreg noalias sret(%class.P1) align 1 %agg.result) -// CHECK: call void {{.*}}foo@P1{{.*}}(%class.P1* noundef{{[^,]*}} %ref.tmp, %class.P1* inreg sret(%class.P1) align 1 %agg.result, i8 %1) +// CHECK: call void {{.*}}foo@P1{{.*}}(%class.P1* {{[^,]*}} %ref.tmp, %class.P1* inreg sret(%class.P1) align 1 %agg.result, i8 %1) class P1 { public: @@ -76,7 +76,7 @@ P1 Q1::bar() { // Pass and return from instance method called from free function. // CHECK: define {{.*}} void {{.*}}bar{{.*}}() -// CHECK: call void {{.*}}foo@P2{{.*}}(%class.P2* noundef{{[^,]*}} %ref.tmp, %class.P2* inreg sret(%class.P2) align 1 %retval, i8 %0) +// CHECK: call void {{.*}}foo@P2{{.*}}(%class.P2* {{[^,]*}} %ref.tmp, %class.P2* inreg sret(%class.P2) align 1 %retval, i8 %0) class P2 { public: P2 foo(P2 x); diff --git a/clang/test/CodeGen/arm64_32.c b/clang/test/CodeGen/arm64_32.c index 75eff32481da0edf49644c4521bad029b3602e36..c2e44c71f4bf986ebca3e136c24c991042aff901 100644 --- a/clang/test/CodeGen/arm64_32.c +++ b/clang/test/CodeGen/arm64_32.c @@ -27,4 +27,4 @@ long double LongDoubleVar = 0.0; typedef float __attribute__((ext_vector_type(16))) v16f32; v16f32 func(v16f32 in) { return in; } -// CHECK: define{{.*}} void @func(<16 x float>* noalias sret(<16 x float>) align 16 {{%.*}}, <16 x float> noundef {{%.*}}) +// CHECK: define{{.*}} void @func(<16 x float>* noalias sret(<16 x float>) align 16 {{%.*}}, <16 x float> {{%.*}}) diff --git a/clang/test/CodeGen/arm64_vcopy.c b/clang/test/CodeGen/arm64_vcopy.c index 440e119aefa73a633018594e4d8252b4855db045..ece0623bfcc5cd52ec73b1b79d20860b310010a8 100644 --- a/clang/test/CodeGen/arm64_vcopy.c +++ b/clang/test/CodeGen/arm64_vcopy.c @@ -4,7 +4,7 @@ #include -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> %a1, <16 x i8> %a2) #0 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a2, i32 13 // CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %a1, i8 [[VGETQ_LANE]], i32 3 // CHECK: ret <16 x i8> [[VSET_LANE]] @@ -12,7 +12,7 @@ int8x16_t test_vcopyq_laneq_s8(int8x16_t a1, int8x16_t a2) { return vcopyq_laneq_s8(a1, (int64_t) 3, a2, (int64_t) 13); } -// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcopyq_laneq_u8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 { +// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcopyq_laneq_u8(<16 x i8> %a1, <16 x i8> %a2) #0 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a2, i32 13 // CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %a1, i8 [[VGETQ_LANE]], i32 3 // CHECK: ret <16 x i8> [[VSET_LANE]] @@ -21,7 +21,7 @@ uint8x16_t test_vcopyq_laneq_u8(uint8x16_t a1, uint8x16_t a2) { } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcopyq_laneq_s16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcopyq_laneq_s16(<8 x i16> %a1, <8 x i16> %a2) #0 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a2, i32 7 // CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> %a1, i16 [[VGETQ_LANE]], i32 3 // CHECK: ret <8 x i16> [[VSET_LANE]] @@ -30,7 +30,7 @@ int16x8_t test_vcopyq_laneq_s16(int16x8_t a1, int16x8_t a2) { } -// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcopyq_laneq_u16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 { +// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcopyq_laneq_u16(<8 x i16> %a1, <8 x i16> %a2) #0 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a2, i32 7 // CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> %a1, i16 [[VGETQ_LANE]], i32 3 // CHECK: ret <8 x i16> [[VSET_LANE]] @@ -39,7 +39,7 @@ uint16x8_t test_vcopyq_laneq_u16(uint16x8_t a1, uint16x8_t a2) { } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcopyq_laneq_s32(<4 x i32> noundef %a1, <4 x i32> noundef %a2) #0 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcopyq_laneq_s32(<4 x i32> %a1, <4 x i32> %a2) #0 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a2, i32 3 // CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i32> %a1, i32 [[VGETQ_LANE]], i32 3 // CHECK: ret <4 x i32> [[VSET_LANE]] @@ -47,7 +47,7 @@ int32x4_t test_vcopyq_laneq_s32(int32x4_t a1, int32x4_t a2) { return vcopyq_laneq_s32(a1, (int64_t) 3, a2, (int64_t) 3); } -// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcopyq_laneq_u32(<4 x i32> noundef %a1, <4 x i32> noundef %a2) #0 { +// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcopyq_laneq_u32(<4 x i32> %a1, <4 x i32> %a2) #0 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a2, i32 3 // CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i32> %a1, i32 [[VGETQ_LANE]], i32 3 // CHECK: ret <4 x i32> [[VSET_LANE]] @@ -55,7 +55,7 @@ uint32x4_t test_vcopyq_laneq_u32(uint32x4_t a1, uint32x4_t a2) { return vcopyq_laneq_u32(a1, (int64_t) 3, a2, (int64_t) 3); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcopyq_laneq_s64(<2 x i64> noundef %a1, <2 x i64> noundef %a2) #0 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcopyq_laneq_s64(<2 x i64> %a1, <2 x i64> %a2) #0 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a2, i32 1 // CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %a1, i64 [[VGETQ_LANE]], i32 0 // CHECK: ret <2 x i64> [[VSET_LANE]] @@ -63,7 +63,7 @@ int64x2_t test_vcopyq_laneq_s64(int64x2_t a1, int64x2_t a2) { return vcopyq_laneq_s64(a1, (int64_t) 0, a2, (int64_t) 1); } -// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcopyq_laneq_u64(<2 x i64> noundef %a1, <2 x i64> noundef %a2) #0 { +// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcopyq_laneq_u64(<2 x i64> %a1, <2 x i64> %a2) #0 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a2, i32 1 // CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %a1, i64 [[VGETQ_LANE]], i32 0 // CHECK: ret <2 x i64> [[VSET_LANE]] @@ -71,7 +71,7 @@ uint64x2_t test_vcopyq_laneq_u64(uint64x2_t a1, uint64x2_t a2) { return vcopyq_laneq_u64(a1, (int64_t) 0, a2, (int64_t) 1); } -// CHECK-LABEL: define{{.*}} <4 x float> @test_vcopyq_laneq_f32(<4 x float> noundef %a1, <4 x float> noundef %a2) #0 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vcopyq_laneq_f32(<4 x float> %a1, <4 x float> %a2) #0 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x float> %a2, i32 3 // CHECK: [[VSET_LANE:%.*]] = insertelement <4 x float> %a1, float [[VGETQ_LANE]], i32 0 // CHECK: ret <4 x float> [[VSET_LANE]] @@ -79,7 +79,7 @@ float32x4_t test_vcopyq_laneq_f32(float32x4_t a1, float32x4_t a2) { return vcopyq_laneq_f32(a1, 0, a2, 3); } -// CHECK-LABEL: define{{.*}} <2 x double> @test_vcopyq_laneq_f64(<2 x double> noundef %a1, <2 x double> noundef %a2) #0 { +// CHECK-LABEL: define{{.*}} <2 x double> @test_vcopyq_laneq_f64(<2 x double> %a1, <2 x double> %a2) #0 { // CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x double> %a2, i32 1 // CHECK: [[VSET_LANE:%.*]] = insertelement <2 x double> %a1, double [[VGETQ_LANE]], i32 0 // CHECK: ret <2 x double> [[VSET_LANE]] diff --git a/clang/test/CodeGen/arm64_vdupq_n_f64.c b/clang/test/CodeGen/arm64_vdupq_n_f64.c index 99c8193133a7cabf83c150a764ea57c2714f2109..ac5d1a9436a3644437fc183741ec9c4cbd7ea8eb 100644 --- a/clang/test/CodeGen/arm64_vdupq_n_f64.c +++ b/clang/test/CodeGen/arm64_vdupq_n_f64.c @@ -4,7 +4,7 @@ // vdupq_n_f64 -> dup.2d v0, v0[0] // -// CHECK-LABEL: define{{.*}} <2 x double> @test_vdupq_n_f64(double noundef %w) #0 { +// CHECK-LABEL: define{{.*}} <2 x double> @test_vdupq_n_f64(double %w) #0 { // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %w, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %w, i32 1 // CHECK: ret <2 x double> [[VECINIT1_I]] @@ -14,7 +14,7 @@ float64x2_t test_vdupq_n_f64(float64_t w) { // might as well test this while we're here // vdupq_n_f32 -> dup.4s v0, v0[0] -// CHECK-LABEL: define{{.*}} <4 x float> @test_vdupq_n_f32(float noundef %w) #0 { +// CHECK-LABEL: define{{.*}} <4 x float> @test_vdupq_n_f32(float %w) #0 { // CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %w, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %w, i32 1 // CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %w, i32 2 @@ -27,7 +27,7 @@ float32x4_t test_vdupq_n_f32(float32_t w) { // vdupq_lane_f64 -> dup.2d v0, v0[0] // this was in , but had already been implemented, // test anyway -// CHECK-LABEL: define{{.*}} <2 x double> @test_vdupq_lane_f64(<1 x double> noundef %V) #0 { +// CHECK-LABEL: define{{.*}} <2 x double> @test_vdupq_lane_f64(<1 x double> %V) #0 { // CHECK: [[TMP0:%.*]] = bitcast <1 x double> %V to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x double> // CHECK: [[SHUFFLE:%.*]] = shufflevector <1 x double> [[TMP1]], <1 x double> [[TMP1]], <2 x i32> zeroinitializer @@ -38,7 +38,7 @@ float64x2_t test_vdupq_lane_f64(float64x1_t V) { // vmovq_n_f64 -> dup Vd.2d,X0 // this wasn't in , but it was between the vdups -// CHECK-LABEL: define{{.*}} <2 x double> @test_vmovq_n_f64(double noundef %w) #0 { +// CHECK-LABEL: define{{.*}} <2 x double> @test_vmovq_n_f64(double %w) #0 { // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %w, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %w, i32 1 // CHECK: ret <2 x double> [[VECINIT1_I]] @@ -46,7 +46,7 @@ float64x2_t test_vmovq_n_f64(float64_t w) { return vmovq_n_f64(w); } -// CHECK-LABEL: define{{.*}} <4 x half> @test_vmov_n_f16(half* noundef %a1) #1 { +// CHECK-LABEL: define{{.*}} <4 x half> @test_vmov_n_f16(half* %a1) #1 { // CHECK: [[TMP0:%.*]] = load half, half* %a1, align 2 // CHECK: [[VECINIT:%.*]] = insertelement <4 x half> undef, half [[TMP0]], i32 0 // CHECK: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[TMP0]], i32 1 @@ -63,7 +63,7 @@ float64x1_t test_vmov_n_f64(float64_t a1) { } */ -// CHECK-LABEL: define{{.*}} <8 x half> @test_vmovq_n_f16(half* noundef %a1) #0 { +// CHECK-LABEL: define{{.*}} <8 x half> @test_vmovq_n_f16(half* %a1) #0 { // CHECK: [[TMP0:%.*]] = load half, half* %a1, align 2 // CHECK: [[VECINIT:%.*]] = insertelement <8 x half> undef, half [[TMP0]], i32 0 // CHECK: [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[TMP0]], i32 1 diff --git a/clang/test/CodeGen/armv7k-abi.c b/clang/test/CodeGen/armv7k-abi.c index a2f1328db60b805b861bc79e7e53bb6caad71125..a7e04dc3611b20893c6a268d6201c18ef183f661 100644 --- a/clang/test/CodeGen/armv7k-abi.c +++ b/clang/test/CodeGen/armv7k-abi.c @@ -23,7 +23,7 @@ typedef struct { // We don't want any padding type to be included by Clang when using the // APCS-VFP ABI, that needs to be handled by LLVM if needed. -// CHECK: void @no_padding(i32 noundef %r0, i32 noundef %r1, i32 noundef %r2, [4 x double] %d0_d3.coerce, [4 x double] %d4_d7.coerce, [4 x double] %sp.coerce, i64 noundef %split) +// CHECK: void @no_padding(i32 %r0, i32 %r1, i32 %r2, [4 x double] %d0_d3.coerce, [4 x double] %d4_d7.coerce, [4 x double] %sp.coerce, i64 %split) void no_padding(int r0, int r1, int r2, BigHFA d0_d3, BigHFA d4_d7, BigHFA sp, long long split) {} @@ -37,7 +37,7 @@ typedef struct { double z; } BigStruct; -// CHECK: define{{.*}} void @big_struct_indirect(%struct.BigStruct* noundef %b) +// CHECK: define{{.*}} void @big_struct_indirect(%struct.BigStruct* %b) void big_struct_indirect(BigStruct b) {} // CHECK: define{{.*}} void @return_big_struct_indirect(%struct.BigStruct* noalias sret @@ -82,7 +82,7 @@ typedef struct { // CHECK: define{{.*}} [2 x i32] @return_oddly_sized_struct() OddlySizedStruct return_oddly_sized_struct() {} -// CHECK: define{{.*}} <4 x float> @test_va_arg_vec(i8* noundef %l) +// CHECK: define{{.*}} <4 x float> @test_va_arg_vec(i8* %l) // CHECK: [[ALIGN_TMP:%.*]] = add i32 {{%.*}}, 15 // CHECK: [[ALIGNED:%.*]] = and i32 [[ALIGN_TMP]], -16 // CHECK: [[ALIGNED_I8:%.*]] = inttoptr i32 [[ALIGNED]] to i8* diff --git a/clang/test/CodeGen/asm-label.c b/clang/test/CodeGen/asm-label.c index cd63fdf968fff5f52547da81b637429072f7051f..c9f30cc3be5a3ef2529c6547ea9530a9c9061a03 100644 --- a/clang/test/CodeGen/asm-label.c +++ b/clang/test/CodeGen/asm-label.c @@ -12,11 +12,11 @@ int *test(void) { // LINUX: @bar = internal global i32 0 // LINUX: @foo ={{.*}} global i32 0 -// LINUX: declare i8* @alias(i32 noundef) +// LINUX: declare i8* @alias(i32) // DARWIN: @"\01bar" = internal global i32 0 // DARWIN: @"\01foo" ={{.*}} global i32 0 -// DARWIN: declare i8* @"\01alias"(i32 noundef) +// DARWIN: declare i8* @"\01alias"(i32) extern void *memcpy(void *__restrict, const void *__restrict, unsigned long); extern __typeof(memcpy) memcpy asm("__GI_memcpy"); @@ -25,9 +25,9 @@ void test_memcpy(void *dst, void *src, unsigned long n) { } // CHECK-LABEL: @test_memcpy( // LINUX: call i8* @__GI_memcpy( -// LINUX: declare i8* @__GI_memcpy(i8* noundef, i8* noundef, i32 noundef) +// LINUX: declare i8* @__GI_memcpy(i8*, i8*, i32) // DARWIN: call i8* @"\01__GI_memcpy"( -// DARWIN: declare i8* @"\01__GI_memcpy"(i8* noundef, i8* noundef, i32 noundef) +// DARWIN: declare i8* @"\01__GI_memcpy"(i8*, i8*, i32) long lrint(double x) asm("__GI_lrint"); long test_lrint(double x) { @@ -35,9 +35,9 @@ long test_lrint(double x) { } // CHECK-LABEL: @test_lrint( // LINUX: call i32 @__GI_lrint( -// LINUX: declare i32 @__GI_lrint(double noundef) +// LINUX: declare i32 @__GI_lrint(double) // DARWIN: call i32 @"\01__GI_lrint"( -// DARWIN: declare i32 @"\01__GI_lrint"(double noundef) +// DARWIN: declare i32 @"\01__GI_lrint"(double) /// NOTE: GCC can optimize out abs in -O1 or above. Clang does not /// communicate the mapping to the backend so the libcall cannot be eliminated. diff --git a/clang/test/CodeGen/assume-aligned-and-alloc-align-attributes.c b/clang/test/CodeGen/assume-aligned-and-alloc-align-attributes.c index a5f3a940228317fe586bcb64ee1e9a9434f09a4a..cd8a6f19b4f49a361441d00079311e8b482cfdf9 100644 --- a/clang/test/CodeGen/assume-aligned-and-alloc-align-attributes.c +++ b/clang/test/CodeGen/assume-aligned-and-alloc-align-attributes.c @@ -5,7 +5,7 @@ void *my_aligned_alloc(int size, int alignment) __attribute__((assume_aligned(32 // CHECK-LABEL: @t0_immediate0( // CHECK-NEXT: entry: -// CHECK-NEXT: [[CALL:%.*]] = call align 32 i8* @my_aligned_alloc(i32 noundef 320, i32 noundef 16) +// CHECK-NEXT: [[CALL:%.*]] = call align 32 i8* @my_aligned_alloc(i32 320, i32 16) // CHECK-NEXT: ret i8* [[CALL]] // void *t0_immediate0() { @@ -14,7 +14,7 @@ void *t0_immediate0() { // CHECK-LABEL: @t1_immediate1( // CHECK-NEXT: entry: -// CHECK-NEXT: [[CALL:%.*]] = call align 32 i8* @my_aligned_alloc(i32 noundef 320, i32 noundef 32) +// CHECK-NEXT: [[CALL:%.*]] = call align 32 i8* @my_aligned_alloc(i32 320, i32 32) // CHECK-NEXT: ret i8* [[CALL]] // void *t1_immediate1() { @@ -23,7 +23,7 @@ void *t1_immediate1() { // CHECK-LABEL: @t2_immediate2( // CHECK-NEXT: entry: -// CHECK-NEXT: [[CALL:%.*]] = call align 64 i8* @my_aligned_alloc(i32 noundef 320, i32 noundef 64) +// CHECK-NEXT: [[CALL:%.*]] = call align 64 i8* @my_aligned_alloc(i32 320, i32 64) // CHECK-NEXT: ret i8* [[CALL]] // void *t2_immediate2() { @@ -35,9 +35,9 @@ void *t2_immediate2() { // CHECK-NEXT: [[ALIGNMENT_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: store i32 [[ALIGNMENT:%.*]], i32* [[ALIGNMENT_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[ALIGNMENT_ADDR]], align 4 -// CHECK-NEXT: [[CALL:%.*]] = call align 32 i8* @my_aligned_alloc(i32 noundef 320, i32 noundef [[TMP0]]) -// CHECK-NEXT: [[CASTED_ALIGN:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* [[CALL]], i64 [[CASTED_ALIGN]]) ] +// CHECK-NEXT: [[CALL:%.*]] = call align 32 i8* @my_aligned_alloc(i32 320, i32 [[TMP0]]) +// CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* [[CALL]], i64 [[TMP1]]) ] // CHECK-NEXT: ret i8* [[CALL]] // void *t3_variable(int alignment) { diff --git a/clang/test/CodeGen/atomic-arm64.c b/clang/test/CodeGen/atomic-arm64.c index 2d5a2fbe9d365548b1033a802f2ae10204e2f762..ed229920372cc5195fdbdb54ee1bfb5f42d1a9d4 100644 --- a/clang/test/CodeGen/atomic-arm64.c +++ b/clang/test/CodeGen/atomic-arm64.c @@ -68,7 +68,7 @@ void test3(pointer_pair_t pair) { // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[T0]], i8* align 8 [[T1]], i64 32, i1 false) // CHECK-NEXT: [[T0:%.*]] = bitcast [[QUAD_T]]* [[TEMP]] to i256* // CHECK-NEXT: [[T1:%.*]] = bitcast i256* [[T0]] to i8* -// CHECK-NEXT: call void @__atomic_store(i64 noundef 32, i8* noundef bitcast ([[QUAD_T]]* @a_pointer_quad to i8*), i8* noundef [[T1]], i32 noundef 5) +// CHECK-NEXT: call void @__atomic_store(i64 32, i8* bitcast ([[QUAD_T]]* @a_pointer_quad to i8*), i8* [[T1]], i32 5) void test4(pointer_quad_t quad) { __c11_atomic_store(&a_pointer_quad, quad, memory_order_seq_cst); } diff --git a/clang/test/CodeGen/atomic-ops-libcall.c b/clang/test/CodeGen/atomic-ops-libcall.c index 55e279b8eecd24abdb5a31489d975cdc7bdd0971..ca79688c8a0c4e6a549ea98cd83311bc4570d294 100644 --- a/clang/test/CodeGen/atomic-ops-libcall.c +++ b/clang/test/CodeGen/atomic-ops-libcall.c @@ -10,109 +10,109 @@ enum memory_order { int *test_c11_atomic_fetch_add_int_ptr(_Atomic(int *) *p) { // CHECK: test_c11_atomic_fetch_add_int_ptr - // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_add_4(i8* noundef {{%[0-9]+}}, i32 noundef 12, i32 noundef 5) + // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_add_4(i8* {{%[0-9]+}}, i32 12, i32 5) return __c11_atomic_fetch_add(p, 3, memory_order_seq_cst); } int *test_c11_atomic_fetch_sub_int_ptr(_Atomic(int *) *p) { // CHECK: test_c11_atomic_fetch_sub_int_ptr - // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_sub_4(i8* noundef {{%[0-9]+}}, i32 noundef 20, i32 noundef 5) + // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_sub_4(i8* {{%[0-9]+}}, i32 20, i32 5) return __c11_atomic_fetch_sub(p, 5, memory_order_seq_cst); } int test_c11_atomic_fetch_add_int(_Atomic(int) *p) { // CHECK: test_c11_atomic_fetch_add_int - // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_add_4(i8* noundef {{%[0-9]+}}, i32 noundef 3, i32 noundef 5) + // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_add_4(i8* {{%[0-9]+}}, i32 3, i32 5) return __c11_atomic_fetch_add(p, 3, memory_order_seq_cst); } int test_c11_atomic_fetch_sub_int(_Atomic(int) *p) { // CHECK: test_c11_atomic_fetch_sub_int - // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_sub_4(i8* noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5) + // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_sub_4(i8* {{%[0-9]+}}, i32 5, i32 5) return __c11_atomic_fetch_sub(p, 5, memory_order_seq_cst); } int *fp2a(int **p) { // CHECK: @fp2a - // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_sub_4(i8* noundef {{%[0-9]+}}, i32 noundef 4, i32 noundef 0) + // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_sub_4(i8* {{%[0-9]+}}, i32 4, i32 0) // Note, the GNU builtins do not multiply by sizeof(T)! return __atomic_fetch_sub(p, 4, memory_order_relaxed); } int test_atomic_fetch_add(int *p) { // CHECK: test_atomic_fetch_add - // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_add_4(i8* noundef {{%[0-9]+}}, i32 noundef 55, i32 noundef 5) + // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_add_4(i8* {{%[0-9]+}}, i32 55, i32 5) return __atomic_fetch_add(p, 55, memory_order_seq_cst); } int test_atomic_fetch_sub(int *p) { // CHECK: test_atomic_fetch_sub - // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_sub_4(i8* noundef {{%[0-9]+}}, i32 noundef 55, i32 noundef 5) + // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_sub_4(i8* {{%[0-9]+}}, i32 55, i32 5) return __atomic_fetch_sub(p, 55, memory_order_seq_cst); } int test_atomic_fetch_and(int *p) { // CHECK: test_atomic_fetch_and - // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_and_4(i8* noundef {{%[0-9]+}}, i32 noundef 55, i32 noundef 5) + // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_and_4(i8* {{%[0-9]+}}, i32 55, i32 5) return __atomic_fetch_and(p, 55, memory_order_seq_cst); } int test_atomic_fetch_or(int *p) { // CHECK: test_atomic_fetch_or - // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_or_4(i8* noundef {{%[0-9]+}}, i32 noundef 55, i32 noundef 5) + // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_or_4(i8* {{%[0-9]+}}, i32 55, i32 5) return __atomic_fetch_or(p, 55, memory_order_seq_cst); } int test_atomic_fetch_xor(int *p) { // CHECK: test_atomic_fetch_xor - // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_xor_4(i8* noundef {{%[0-9]+}}, i32 noundef 55, i32 noundef 5) + // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_xor_4(i8* {{%[0-9]+}}, i32 55, i32 5) return __atomic_fetch_xor(p, 55, memory_order_seq_cst); } int test_atomic_fetch_nand(int *p) { // CHECK: test_atomic_fetch_nand - // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_nand_4(i8* noundef {{%[0-9]+}}, i32 noundef 55, i32 noundef 5) + // CHECK: {{%[^ ]*}} = call i32 @__atomic_fetch_nand_4(i8* {{%[0-9]+}}, i32 55, i32 5) return __atomic_fetch_nand(p, 55, memory_order_seq_cst); } int test_atomic_add_fetch(int *p) { // CHECK: test_atomic_add_fetch - // CHECK: [[CALL:%[^ ]*]] = call i32 @__atomic_fetch_add_4(i8* noundef {{%[0-9]+}}, i32 noundef 55, i32 noundef 5) + // CHECK: [[CALL:%[^ ]*]] = call i32 @__atomic_fetch_add_4(i8* {{%[0-9]+}}, i32 55, i32 5) // CHECK: {{%[^ ]*}} = add i32 [[CALL]], 55 return __atomic_add_fetch(p, 55, memory_order_seq_cst); } int test_atomic_sub_fetch(int *p) { // CHECK: test_atomic_sub_fetch - // CHECK: [[CALL:%[^ ]*]] = call i32 @__atomic_fetch_sub_4(i8* noundef {{%[0-9]+}}, i32 noundef 55, i32 noundef 5) + // CHECK: [[CALL:%[^ ]*]] = call i32 @__atomic_fetch_sub_4(i8* {{%[0-9]+}}, i32 55, i32 5) // CHECK: {{%[^ ]*}} = add i32 [[CALL]], -55 return __atomic_sub_fetch(p, 55, memory_order_seq_cst); } int test_atomic_and_fetch(int *p) { // CHECK: test_atomic_and_fetch - // CHECK: [[CALL:%[^ ]*]] = call i32 @__atomic_fetch_and_4(i8* noundef {{%[0-9]+}}, i32 noundef 55, i32 noundef 5) + // CHECK: [[CALL:%[^ ]*]] = call i32 @__atomic_fetch_and_4(i8* {{%[0-9]+}}, i32 55, i32 5) // CHECK: {{%[^ ]*}} = and i32 [[CALL]], 55 return __atomic_and_fetch(p, 55, memory_order_seq_cst); } int test_atomic_or_fetch(int *p) { // CHECK: test_atomic_or_fetch - // CHECK: [[CALL:%[^ ]*]] = call i32 @__atomic_fetch_or_4(i8* noundef {{%[0-9]+}}, i32 noundef 55, i32 noundef 5) + // CHECK: [[CALL:%[^ ]*]] = call i32 @__atomic_fetch_or_4(i8* {{%[0-9]+}}, i32 55, i32 5) // CHECK: {{%[^ ]*}} = or i32 [[CALL]], 55 return __atomic_or_fetch(p, 55, memory_order_seq_cst); } int test_atomic_xor_fetch(int *p) { // CHECK: test_atomic_xor_fetch - // CHECK: [[CALL:%[^ ]*]] = call i32 @__atomic_fetch_xor_4(i8* noundef {{%[0-9]+}}, i32 noundef 55, i32 noundef 5) + // CHECK: [[CALL:%[^ ]*]] = call i32 @__atomic_fetch_xor_4(i8* {{%[0-9]+}}, i32 55, i32 5) // CHECK: {{%[^ ]*}} = xor i32 [[CALL]], 55 return __atomic_xor_fetch(p, 55, memory_order_seq_cst); } int test_atomic_nand_fetch(int *p) { // CHECK: test_atomic_nand_fetch - // CHECK: [[CALL:%[^ ]*]] = call i32 @__atomic_fetch_nand_4(i8* noundef {{%[0-9]+}}, i32 noundef 55, i32 noundef 5) + // CHECK: [[CALL:%[^ ]*]] = call i32 @__atomic_fetch_nand_4(i8* {{%[0-9]+}}, i32 55, i32 5) // FIXME: We should not be checking optimized IR. It changes independently of clang. // FIXME-CHECK: [[AND:%[^ ]*]] = and i32 [[CALL]], 55 // FIXME-CHECK: {{%[^ ]*}} = xor i32 [[AND]], -1 diff --git a/clang/test/CodeGen/atomic-ops.c b/clang/test/CodeGen/atomic-ops.c index c7cec67e81b47ab941e2e9b24342e0f23c4e537a..02edec19bca93cb421428ffceb97d3db9d6c01b9 100644 --- a/clang/test/CodeGen/atomic-ops.c +++ b/clang/test/CodeGen/atomic-ops.c @@ -202,7 +202,7 @@ struct S fd1(struct S *a) { // CHECK: [[CAST:%.*]] = bitcast %struct.S* [[RETVAL]] to i64* // CHECK: [[SRC:%.*]] = bitcast i64* [[A]] to i8* // CHECK: [[DEST:%.*]] = bitcast i64* [[CAST]] to i8* - // CHECK: call void @__atomic_load(i32 noundef 8, i8* noundef [[SRC]], i8* noundef [[DEST]], i32 noundef 5) + // CHECK: call void @__atomic_load(i32 8, i8* [[SRC]], i8* [[DEST]], i32 5) // CHECK: ret struct S ret; __atomic_load(a, &ret, memory_order_seq_cst); @@ -221,7 +221,7 @@ void fd2(struct S *a, struct S *b) { // CHECK-NEXT: [[COERCED_B:%.*]] = bitcast %struct.S* [[LOAD_B_PTR]] to i64* // CHECK-NEXT: [[COERCED_A:%.*]] = bitcast i64* [[COERCED_A_TMP]] to i8* // CHECK-NEXT: [[CAST_B:%.*]] = bitcast i64* [[COERCED_B]] to i8* - // CHECK-NEXT: call void @__atomic_store(i32 noundef 8, i8* noundef [[COERCED_A]], i8* noundef [[CAST_B]], + // CHECK-NEXT: call void @__atomic_store(i32 8, i8* [[COERCED_A]], i8* [[CAST_B]], // CHECK-NEXT: ret void __atomic_store(a, b, memory_order_seq_cst); } @@ -243,7 +243,7 @@ void fd3(struct S *a, struct S *b, struct S *c) { // CHECK-NEXT: [[COERCED_A:%.*]] = bitcast i64* [[COERCED_A_TMP]] to i8* // CHECK-NEXT: [[CAST_B:%.*]] = bitcast i64* [[COERCED_B]] to i8* // CHECK-NEXT: [[CAST_C:%.*]] = bitcast i64* [[COERCED_C]] to i8* - // CHECK-NEXT: call void @__atomic_exchange(i32 noundef 8, i8* noundef [[COERCED_A]], i8* noundef [[CAST_B]], i8* noundef [[CAST_C]], + // CHECK-NEXT: call void @__atomic_exchange(i32 8, i8* [[COERCED_A]], i8* [[CAST_B]], i8* [[CAST_C]], __atomic_exchange(a, b, c, memory_order_seq_cst); } @@ -265,7 +265,7 @@ _Bool fd4(struct S *a, struct S *b, struct S *c) { // CHECK-NEXT: [[COERCED_A:%.*]] = bitcast i64* [[COERCED_A_TMP]] to i8* // CHECK-NEXT: [[COERCED_B:%.*]] = bitcast i64* [[COERCED_B_TMP]] to i8* // CHECK-NEXT: [[CAST_C:%.*]] = bitcast i64* [[COERCED_C]] to i8* - // CHECK-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 8, i8* noundef [[COERCED_A]], i8* noundef [[COERCED_B]], i8* noundef [[CAST_C]], + // CHECK-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 8, i8* [[COERCED_A]], i8* [[COERCED_B]], i8* [[CAST_C]], // CHECK-NEXT: ret i1 [[CALL]] return __atomic_compare_exchange(a, b, c, 1, 5, 5); } @@ -343,20 +343,20 @@ struct Incomplete; int lock_free(struct Incomplete *incomplete) { // CHECK-LABEL: @lock_free - // CHECK: call zeroext i1 @__atomic_is_lock_free(i32 noundef 3, i8* noundef null) + // CHECK: call zeroext i1 @__atomic_is_lock_free(i32 3, i8* null) __c11_atomic_is_lock_free(3); - // CHECK: call zeroext i1 @__atomic_is_lock_free(i32 noundef 16, i8* noundef {{.*}}@sixteen{{.*}}) + // CHECK: call zeroext i1 @__atomic_is_lock_free(i32 16, i8* {{.*}}@sixteen{{.*}}) __atomic_is_lock_free(16, &sixteen); - // CHECK: call zeroext i1 @__atomic_is_lock_free(i32 noundef 17, i8* noundef {{.*}}@seventeen{{.*}}) + // CHECK: call zeroext i1 @__atomic_is_lock_free(i32 17, i8* {{.*}}@seventeen{{.*}}) __atomic_is_lock_free(17, &seventeen); - // CHECK: call zeroext i1 @__atomic_is_lock_free(i32 noundef 4, {{.*}}) + // CHECK: call zeroext i1 @__atomic_is_lock_free(i32 4, {{.*}}) __atomic_is_lock_free(4, incomplete); char cs[20]; - // CHECK: call zeroext i1 @__atomic_is_lock_free(i32 noundef 4, {{.*}}) + // CHECK: call zeroext i1 @__atomic_is_lock_free(i32 4, {{.*}}) __atomic_is_lock_free(4, cs+1); // CHECK-NOT: call @@ -393,36 +393,36 @@ void structAtomicStore() { struct foo f = {0}; struct bar b = {0}; __atomic_store(&smallThing, &b, 5); - // CHECK: call void @__atomic_store(i32 noundef 3, i8* noundef {{.*}} @smallThing + // CHECK: call void @__atomic_store(i32 3, i8* {{.*}} @smallThing __atomic_store(&bigThing, &f, 5); - // CHECK: call void @__atomic_store(i32 noundef 512, i8* noundef {{.*}} @bigThing + // CHECK: call void @__atomic_store(i32 512, i8* {{.*}} @bigThing } void structAtomicLoad() { // CHECK-LABEL: @structAtomicLoad struct bar b; __atomic_load(&smallThing, &b, 5); - // CHECK: call void @__atomic_load(i32 noundef 3, i8* noundef {{.*}} @smallThing + // CHECK: call void @__atomic_load(i32 3, i8* {{.*}} @smallThing struct foo f = {0}; __atomic_load(&bigThing, &f, 5); - // CHECK: call void @__atomic_load(i32 noundef 512, i8* noundef {{.*}} @bigThing + // CHECK: call void @__atomic_load(i32 512, i8* {{.*}} @bigThing } struct foo structAtomicExchange() { // CHECK-LABEL: @structAtomicExchange struct foo f = {0}; struct foo old; __atomic_exchange(&f, &bigThing, &old, 5); - // CHECK: call void @__atomic_exchange(i32 noundef 512, {{.*}}, i8* noundef bitcast ({{.*}} @bigThing to i8*), + // CHECK: call void @__atomic_exchange(i32 512, {{.*}}, i8* bitcast ({{.*}} @bigThing to i8*), return __c11_atomic_exchange(&bigAtomic, f, 5); - // CHECK: call void @__atomic_exchange(i32 noundef 512, i8* noundef bitcast ({{.*}} @bigAtomic to i8*), + // CHECK: call void @__atomic_exchange(i32 512, i8* bitcast ({{.*}} @bigAtomic to i8*), } int structAtomicCmpExchange() { // CHECK-LABEL: @structAtomicCmpExchange // CHECK: %[[x_mem:.*]] = alloca i8 _Bool x = __atomic_compare_exchange(&smallThing, &thing1, &thing2, 1, 5, 5); - // CHECK: %[[call1:.*]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 3, {{.*}} @smallThing{{.*}} @thing1{{.*}} @thing2 + // CHECK: %[[call1:.*]] = call zeroext i1 @__atomic_compare_exchange(i32 3, {{.*}} @smallThing{{.*}} @thing1{{.*}} @thing2 // CHECK: %[[zext1:.*]] = zext i1 %[[call1]] to i8 // CHECK: store i8 %[[zext1]], i8* %[[x_mem]], align 1 // CHECK: %[[x:.*]] = load i8, i8* %[[x_mem]] @@ -433,7 +433,7 @@ int structAtomicCmpExchange() { struct foo g = {0}; g.big[12] = 12; return x & __c11_atomic_compare_exchange_strong(&bigAtomic, &f, g, 5, 5); - // CHECK: %[[call2:.*]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 512, i8* noundef bitcast ({{.*}} @bigAtomic to i8*), + // CHECK: %[[call2:.*]] = call zeroext i1 @__atomic_compare_exchange(i32 512, i8* bitcast ({{.*}} @bigAtomic to i8*), // CHECK: %[[conv2:.*]] = zext i1 %[[call2]] to i32 // CHECK: %[[and:.*]] = and i32 %[[conv1]], %[[conv2]] // CHECK: ret i32 %[[and]] @@ -702,13 +702,13 @@ void test_underaligned() { // CHECK-LABEL: @test_underaligned struct Underaligned { char c[8]; } underaligned_a, underaligned_b, underaligned_c; - // CHECK: call void @__atomic_load(i32 noundef 8, + // CHECK: call void @__atomic_load(i32 8, __atomic_load(&underaligned_a, &underaligned_b, memory_order_seq_cst); - // CHECK: call void @__atomic_store(i32 noundef 8, + // CHECK: call void @__atomic_store(i32 8, __atomic_store(&underaligned_a, &underaligned_b, memory_order_seq_cst); - // CHECK: call void @__atomic_exchange(i32 noundef 8, + // CHECK: call void @__atomic_exchange(i32 8, __atomic_exchange(&underaligned_a, &underaligned_b, &underaligned_c, memory_order_seq_cst); - // CHECK: call {{.*}} @__atomic_compare_exchange(i32 noundef 8, + // CHECK: call {{.*}} @__atomic_compare_exchange(i32 8, __atomic_compare_exchange(&underaligned_a, &underaligned_b, &underaligned_c, 1, memory_order_seq_cst, memory_order_seq_cst); __attribute__((aligned)) struct Underaligned aligned_a, aligned_b, aligned_c; @@ -792,7 +792,7 @@ void test_minmax_postop(int *si, unsigned *ui, unsigned short *us, signed char * // CHECK: store i8 [[NEW]], i8* *sc = __atomic_min_fetch(sc, 42, memory_order_release); - // CHECK: [[OLD:%.*]] = call i64 @__atomic_fetch_umin_8(i8* noundef {{%.*}}, i64 noundef [[RHS:%.*]], + // CHECK: [[OLD:%.*]] = call i64 @__atomic_fetch_umin_8(i8* {{%.*}}, i64 [[RHS:%.*]], // CHECK: [[TST:%.*]] = icmp ult i64 [[OLD]], [[RHS]] // CHECK: [[NEW:%.*]] = select i1 [[TST]], i64 [[OLD]], i64 [[RHS]] // CHECK: store i64 [[NEW]], i64* diff --git a/clang/test/CodeGen/atomic_ops.c b/clang/test/CodeGen/atomic_ops.c index 6e1982688b90bc7566121ca7627f92941f0bd827..f3754888a1c01c477712ad0681b6b355cb8bd50c 100644 --- a/clang/test/CodeGen/atomic_ops.c +++ b/clang/test/CodeGen/atomic_ops.c @@ -12,17 +12,17 @@ void foo(int x) // NATIVE: mul nsw i32 // NATIVE: cmpxchg i32* {{.*}} seq_cst, align 4 // LIBCALL: mul nsw i32 - // LIBCALL: i1 @__atomic_compare_exchange(i32 noundef 4, + // LIBCALL: i1 @__atomic_compare_exchange(i32 4, i /= 2; // NATIVE: sdiv i32 // NATIVE: cmpxchg i32* {{.*}} seq_cst, align 4 // LIBCALL: sdiv i32 - // LIBCALL: i1 @__atomic_compare_exchange(i32 noundef 4, + // LIBCALL: i1 @__atomic_compare_exchange(i32 4, j /= x; // NATIVE: sdiv i32 // NATIVE: cmpxchg i16* {{.*}} seq_cst, align 2 // LIBCALL: sdiv i32 - // LIBCALL: i1 @__atomic_compare_exchange(i32 noundef 2, + // LIBCALL: i1 @__atomic_compare_exchange(i32 2, } @@ -37,7 +37,7 @@ _Bool bar() { // NATIVE: %[[tobool:.*]] = trunc i8 %[[load]] to i1 // NATIVE: ret i1 %[[tobool]] // LIBCALL-LABEL: @bar -// LIBCALL: call void @__atomic_load(i32 noundef 1, i8* noundef @b, i8* noundef %atomic-temp, i32 noundef 5) +// LIBCALL: call void @__atomic_load(i32 1, i8* @b, i8* %atomic-temp, i32 5) // LIBCALL: %[[load:.*]] = load i8, i8* %atomic-temp // LIBCALL: %[[tobool:.*]] = trunc i8 %[[load]] to i1 // LIBCALL: ret i1 %[[tobool]] @@ -108,7 +108,7 @@ _Atomic(int) compound_mul(_Atomic(int) in) { // NATIVE: cmpxchg i32* {{%.*}}, i32 {{%.*}}, i32 [[NEW:%.*]] seq_cst seq_cst, align 4 // NATIVE: ret i32 [[NEW]] // LIBCALL-LABEL: @compound_mul -// LIBCALL: i1 @__atomic_compare_exchange(i32 noundef 4, +// LIBCALL: i1 @__atomic_compare_exchange(i32 4, return (in *= 5); } diff --git a/clang/test/CodeGen/atomics-inlining.c b/clang/test/CodeGen/atomics-inlining.c index 1aa042b37f4ef5f47d7f8a7e79f10060e0db5f79..1931a19c3f3195cb65974e9d225b754274fecf40 100644 --- a/clang/test/CodeGen/atomics-inlining.c +++ b/clang/test/CodeGen/atomics-inlining.c @@ -37,16 +37,16 @@ void test1(void) { (void)__atomic_store(&a1, &a2, memory_order_seq_cst); // ARM-LABEL: define{{.*}} void @test1 -// ARM: = call{{.*}} zeroext i8 @__atomic_load_1(i8* noundef @c1 -// ARM: call{{.*}} void @__atomic_store_1(i8* noundef @c1, i8 noundef zeroext -// ARM: = call{{.*}} zeroext i16 @__atomic_load_2(i8* noundef bitcast (i16* @s1 to i8*) -// ARM: call{{.*}} void @__atomic_store_2(i8* noundef bitcast (i16* @s1 to i8*), i16 noundef zeroext -// ARM: = call{{.*}} i32 @__atomic_load_4(i8* noundef bitcast (i32* @i1 to i8*) -// ARM: call{{.*}} void @__atomic_store_4(i8* noundef bitcast (i32* @i1 to i8*), i32 noundef -// ARM: = call{{.*}} i64 @__atomic_load_8(i8* noundef bitcast (i64* @ll1 to i8*) -// ARM: call{{.*}} void @__atomic_store_8(i8* noundef bitcast (i64* @ll1 to i8*), i64 noundef -// ARM: call{{.*}} void @__atomic_load(i32 noundef 100, i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) -// ARM: call{{.*}} void @__atomic_store(i32 noundef 100, i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) +// ARM: = call{{.*}} zeroext i8 @__atomic_load_1(i8* @c1 +// ARM: call{{.*}} void @__atomic_store_1(i8* @c1, i8 zeroext +// ARM: = call{{.*}} zeroext i16 @__atomic_load_2(i8* bitcast (i16* @s1 to i8*) +// ARM: call{{.*}} void @__atomic_store_2(i8* bitcast (i16* @s1 to i8*), i16 zeroext +// ARM: = call{{.*}} i32 @__atomic_load_4(i8* bitcast (i32* @i1 to i8*) +// ARM: call{{.*}} void @__atomic_store_4(i8* bitcast (i32* @i1 to i8*), i32 +// ARM: = call{{.*}} i64 @__atomic_load_8(i8* bitcast (i64* @ll1 to i8*) +// ARM: call{{.*}} void @__atomic_store_8(i8* bitcast (i64* @ll1 to i8*), i64 +// ARM: call{{.*}} void @__atomic_load(i32 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) +// ARM: call{{.*}} void @__atomic_store(i32 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) // PPC32-LABEL: define{{.*}} void @test1 // PPC32: = load atomic i8, i8* @c1 seq_cst, align 1 @@ -55,10 +55,10 @@ void test1(void) { // PPC32: store atomic i16 {{.*}}, i16* @s1 seq_cst, align 2 // PPC32: = load atomic i32, i32* @i1 seq_cst, align 4 // PPC32: store atomic i32 {{.*}}, i32* @i1 seq_cst, align 4 -// PPC32: = call i64 @__atomic_load_8(i8* noundef bitcast (i64* @ll1 to i8*) -// PPC32: call void @__atomic_store_8(i8* noundef bitcast (i64* @ll1 to i8*), i64 -// PPC32: call void @__atomic_load(i32 noundef 100, i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) -// PPC32: call void @__atomic_store(i32 noundef 100, i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) +// PPC32: = call i64 @__atomic_load_8(i8* bitcast (i64* @ll1 to i8*) +// PPC32: call void @__atomic_store_8(i8* bitcast (i64* @ll1 to i8*), i64 +// PPC32: call void @__atomic_load(i32 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) +// PPC32: call void @__atomic_store(i32 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) // PPC64-LABEL: define{{.*}} void @test1 // PPC64: = load atomic i8, i8* @c1 seq_cst, align 1 @@ -69,8 +69,8 @@ void test1(void) { // PPC64: store atomic i32 {{.*}}, i32* @i1 seq_cst, align 4 // PPC64: = load atomic i64, i64* @ll1 seq_cst, align 8 // PPC64: store atomic i64 {{.*}}, i64* @ll1 seq_cst, align 8 -// PPC64: call void @__atomic_load(i64 noundef 100, i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) -// PPC64: call void @__atomic_store(i64 noundef 100, i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) +// PPC64: call void @__atomic_load(i64 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) +// PPC64: call void @__atomic_store(i64 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) // MIPS32-LABEL: define{{.*}} void @test1 // MIPS32: = load atomic i8, i8* @c1 seq_cst, align 1 @@ -79,10 +79,10 @@ void test1(void) { // MIPS32: store atomic i16 {{.*}}, i16* @s1 seq_cst, align 2 // MIPS32: = load atomic i32, i32* @i1 seq_cst, align 4 // MIPS32: store atomic i32 {{.*}}, i32* @i1 seq_cst, align 4 -// MIPS32: call i64 @__atomic_load_8(i8* noundef bitcast (i64* @ll1 to i8*) -// MIPS32: call void @__atomic_store_8(i8* noundef bitcast (i64* @ll1 to i8*), i64 -// MIPS32: call void @__atomic_load(i32 noundef signext 100, i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) -// MIPS32: call void @__atomic_store(i32 noundef signext 100, i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) +// MIPS32: call i64 @__atomic_load_8(i8* bitcast (i64* @ll1 to i8*) +// MIPS32: call void @__atomic_store_8(i8* bitcast (i64* @ll1 to i8*), i64 +// MIPS32: call void @__atomic_load(i32 signext 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) +// MIPS32: call void @__atomic_store(i32 signext 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) // MIPS64-LABEL: define{{.*}} void @test1 // MIPS64: = load atomic i8, i8* @c1 seq_cst, align 1 @@ -93,8 +93,8 @@ void test1(void) { // MIPS64: store atomic i32 {{.*}}, i32* @i1 seq_cst, align 4 // MIPS64: = load atomic i64, i64* @ll1 seq_cst, align 8 // MIPS64: store atomic i64 {{.*}}, i64* @ll1 seq_cst, align 8 -// MIPS64: call void @__atomic_load(i64 noundef zeroext 100, i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0) -// MIPS64: call void @__atomic_store(i64 noundef zeroext 100, i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) +// MIPS64: call void @__atomic_load(i64 zeroext 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0) +// MIPS64: call void @__atomic_store(i64 zeroext 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) // SPARC-LABEL: define{{.*}} void @test1 // SPARC: = load atomic i8, i8* @c1 seq_cst, align 1 @@ -103,10 +103,10 @@ void test1(void) { // SPARC: store atomic i16 {{.*}}, i16* @s1 seq_cst, align 2 // SPARC: = load atomic i32, i32* @i1 seq_cst, align 4 // SPARC: store atomic i32 {{.*}}, i32* @i1 seq_cst, align 4 -// SPARCV8: call i64 @__atomic_load_8(i8* noundef bitcast (i64* @ll1 to i8*) -// SPARCV8: call void @__atomic_store_8(i8* noundef bitcast (i64* @ll1 to i8*), i64 +// SPARCV8: call i64 @__atomic_load_8(i8* bitcast (i64* @ll1 to i8*) +// SPARCV8: call void @__atomic_store_8(i8* bitcast (i64* @ll1 to i8*), i64 // SPARCV9: load atomic i64, i64* @ll1 seq_cst, align 8 // SPARCV9: store atomic i64 {{.*}}, i64* @ll1 seq_cst, align 8 -// SPARCV8: call void @__atomic_load(i32 noundef 100, i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) -// SPARCV8: call void @__atomic_store(i32 noundef 100, i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* noundef getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) +// SPARCV8: call void @__atomic_load(i32 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) +// SPARCV8: call void @__atomic_store(i32 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) } diff --git a/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c b/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c index 752341d9fd7147324faac08972d7b0ca64e20663..7ebed483c090cade5c0e89971f860c1dec0e6cec 100644 --- a/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c +++ b/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -fallow-half-arguments-and-returns -fno-experimental-new-pass-manager -S -O1 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -fallow-half-arguments-and-returns -S -O1 -emit-llvm -o - %s | FileCheck %s #include diff --git a/clang/test/CodeGen/attr-func-def.c b/clang/test/CodeGen/attr-func-def.c index d0c79c6505bb95b9a4b072fa325e0764844dbe8e..36210977f020c26cb5dec4cf2e82899baab1239c 100644 --- a/clang/test/CodeGen/attr-func-def.c +++ b/clang/test/CodeGen/attr-func-def.c @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -triple x86_64-apple-macosx10.10.0 -emit-llvm -Oz -o - %s | FileCheck %s -// CHECK: define{{.*}} i32 @foo2(i32 noundef %a) local_unnamed_addr [[ATTRS2:#[0-9]+]] { -// CHECK: define{{.*}} i32 @foo1(i32 noundef %a) local_unnamed_addr [[ATTRS1:#[0-9]+]] { +// CHECK: define{{.*}} i32 @foo2(i32 %a) local_unnamed_addr [[ATTRS2:#[0-9]+]] { +// CHECK: define{{.*}} i32 @foo1(i32 %a) local_unnamed_addr [[ATTRS1:#[0-9]+]] { int foo1(int); diff --git a/clang/test/CodeGen/attr-naked.c b/clang/test/CodeGen/attr-naked.c index d760683874c130935d944b8874330099589b6b55..1a3e73eef36fce6f16039f32fdb76366a7e9388a 100644 --- a/clang/test/CodeGen/attr-naked.c +++ b/clang/test/CodeGen/attr-naked.c @@ -17,7 +17,7 @@ __attribute((naked, always_inline)) void t2() { // Make sure not to generate prolog or epilog for naked functions. __attribute((naked)) void t3(int x) { -// CHECK: define{{.*}} void @t3(i32 noundef %0) +// CHECK: define{{.*}} void @t3(i32 %0) // CHECK-NOT: alloca // CHECK-NOT: store // CHECK: unreachable diff --git a/clang/test/CodeGen/attr-no-tail.c b/clang/test/CodeGen/attr-no-tail.c index ced6ce65e7bf015dfd2976ee6f2a7b402ae2a5c1..1c9aca6edf8357e5c3cb566530bb577be88e4a3f 100644 --- a/clang/test/CodeGen/attr-no-tail.c +++ b/clang/test/CodeGen/attr-no-tail.c @@ -1,14 +1,14 @@ // RUN: %clang_cc1 -triple x86_64-apple-macosx10.7.0 %s -emit-llvm -o - | FileCheck %s -// CHECK: %{{[a-z0-9]+}} = notail call i32 @callee0(i32 noundef % -// CHECK: %{{[a-z0-9]+}} = notail call i32 @callee1(i32 noundef % +// CHECK: %{{[a-z0-9]+}} = notail call i32 @callee0(i32 % +// CHECK: %{{[a-z0-9]+}} = notail call i32 @callee1(i32 % // Check that indirect calls do not have the notail marker. // CHECK: store i32 (i32)* @callee1, i32 (i32)** [[ALLOCA1:%[A-Za-z0-9]+]], align 8 // CHECK: [[INDIRFUNC:%[0-9]+]] = load i32 (i32)*, i32 (i32)** [[ALLOCA1]], align 8 -// CHECK: %{{[a-z0-9]+}} = call i32 [[INDIRFUNC]](i32 noundef %{{[0-9]+}} +// CHECK: %{{[a-z0-9]+}} = call i32 [[INDIRFUNC]](i32 %{{[0-9]+}} -// CHECK: %{{[a-z0-9]+}} = call i32 @callee2(i32 noundef % +// CHECK: %{{[a-z0-9]+}} = call i32 @callee2(i32 % int callee0(int a) __attribute__((not_tail_called)) { return a + 1; diff --git a/clang/test/CodeGen/attr-nomerge.cpp b/clang/test/CodeGen/attr-nomerge.cpp index 05b481e207654a96d8aa3dcadc626e71b0d9cb35..da0c33bb384c74b4830e4a2e2314fbadd841958d 100644 --- a/clang/test/CodeGen/attr-nomerge.cpp +++ b/clang/test/CodeGen/attr-nomerge.cpp @@ -60,24 +60,24 @@ void something_else_again() { g(1); } -// CHECK: call noundef zeroext i1 @_Z3barv() #[[ATTR0:[0-9]+]] -// CHECK: call noundef zeroext i1 @_Z3barv() #[[ATTR0]] -// CHECK: call noundef zeroext i1 @_Z3barv() #[[ATTR0]] -// CHECK: call noundef zeroext i1 @_Z3barv(){{$}} -// CHECK: call noundef zeroext i1 @_Z3barv(){{$}} +// CHECK: call zeroext i1 @_Z3barv() #[[ATTR0:[0-9]+]] +// CHECK: call zeroext i1 @_Z3barv() #[[ATTR0]] +// CHECK: call zeroext i1 @_Z3barv() #[[ATTR0]] +// CHECK: call zeroext i1 @_Z3barv(){{$}} +// CHECK: call zeroext i1 @_Z3barv(){{$}} // CHECK: call void @_Z1fbb({{.*}}) #[[ATTR0]] // CHECK: call void @"_ZZ3fooiP1AP1BENK3$_0clEv"{{.*}} #[[ATTR0]] -// CHECK: call noundef zeroext i1 @_Z3barv() #[[ATTR0]] +// CHECK: call zeroext i1 @_Z3barv() #[[ATTR0]] // CHECK-LABEL: for.cond: -// CHECK: call noundef zeroext i1 @_Z3barv() #[[ATTR0]] +// CHECK: call zeroext i1 @_Z3barv() #[[ATTR0]] // CHECK-LABEL: for.inc: -// CHECK: call noundef zeroext i1 @_Z3barv() #[[ATTR0]] +// CHECK: call zeroext i1 @_Z3barv() #[[ATTR0]] // CHECK: call void asm sideeffect "nop"{{.*}} #[[ATTR1:[0-9]+]] -// CHECK: call noundef zeroext i1 @_Z3barv(){{$}} +// CHECK: call zeroext i1 @_Z3barv(){{$}} // CHECK: %[[AG:.*]] = load void (%class.A*)*, void (%class.A*)** // CHECK-NEXT: call void %[[AG]](%class.A* {{.*}}) #[[ATTR0]] // CHECK: %[[BG:.*]] = load void (%class.B*)*, void (%class.B*)** -// CHECK-NEXT: call void %[[BG]](%class.B* noundef{{.*}} +// CHECK-NEXT: call void %[[BG]](%class.B* nonnull align {{.*}} dereferenceable // CHECK: call void @_ZN1AC1Ev({{.*}}) #[[ATTR0]] // CHECK: call void @_ZN1A1fEv({{.*}}) #[[ATTR0]] // CHECK: call void @_ZN1A1gEv({{.*}}) #[[ATTR0]] diff --git a/clang/test/CodeGen/attr-noundef.cpp b/clang/test/CodeGen/attr-noundef.cpp index 799dbb8bb6597a4a6fc6ce6b679e1d447ad5ea01..949e051104182669b698a9f8ca02c0592ed4aa18 100644 --- a/clang/test/CodeGen/attr-noundef.cpp +++ b/clang/test/CodeGen/attr-noundef.cpp @@ -1,5 +1,5 @@ -// RUN: %clang -cc1 -triple x86_64-gnu-linux -x c++ -S -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-INTEL -// RUN: %clang -cc1 -triple aarch64-gnu-linux -x c++ -S -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH +// RUN: %clang -cc1 -triple x86_64-gnu-linux -x c++ -S -emit-llvm -enable-noundef-analysis %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-INTEL +// RUN: %clang -cc1 -triple aarch64-gnu-linux -x c++ -S -emit-llvm -enable-noundef-analysis %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH //************ Passing structs by value // TODO: No structs may currently be marked noundef diff --git a/clang/test/CodeGen/attr-target-mv-func-ptrs.c b/clang/test/CodeGen/attr-target-mv-func-ptrs.c index aace370e0bba55b997761c69395815cad7d7edab..6c20f9d46f041451dba3f5ca75e99973d9f470c0 100644 --- a/clang/test/CodeGen/attr-target-mv-func-ptrs.c +++ b/clang/test/CodeGen/attr-target-mv-func-ptrs.c @@ -33,12 +33,12 @@ int bar() { // WINDOWS: ret i32 2 // LINUX: define{{.*}} i32 @bar() -// LINUX: call void @func(i32 (i32)* noundef @foo.ifunc) +// LINUX: call void @func(i32 (i32)* @foo.ifunc) // LINUX: store i32 (i32)* @foo.ifunc // LINUX: store i32 (i32)* @foo.ifunc // WINDOWS: define dso_local i32 @bar() -// WINDOWS: call void @func(i32 (i32)* noundef @foo.resolver) +// WINDOWS: call void @func(i32 (i32)* @foo.resolver) // WINDOWS: store i32 (i32)* @foo.resolver // WINDOWS: store i32 (i32)* @foo.resolver diff --git a/clang/test/CodeGen/attr-target-mv-va-args.c b/clang/test/CodeGen/attr-target-mv-va-args.c index 03ba995da35fe300745d7beea6990e4e84e0aac8..4a13fde38480a0125f037ca5ceb69c93942d6fb4 100644 --- a/clang/test/CodeGen/attr-target-mv-va-args.c +++ b/clang/test/CodeGen/attr-target-mv-va-args.c @@ -10,36 +10,36 @@ int bar() { } // LINUX: @foo.ifunc = weak_odr ifunc i32 (i32, ...), i32 (i32, ...)* ()* @foo.resolver -// LINUX: define{{.*}} i32 @foo.sse4.2(i32 noundef %i, ...) +// LINUX: define{{.*}} i32 @foo.sse4.2(i32 %i, ...) // LINUX: ret i32 0 -// LINUX: define{{.*}} i32 @foo.arch_ivybridge(i32 noundef %i, ...) +// LINUX: define{{.*}} i32 @foo.arch_ivybridge(i32 %i, ...) // LINUX: ret i32 1 -// LINUX: define{{.*}} i32 @foo(i32 noundef %i, ...) +// LINUX: define{{.*}} i32 @foo(i32 %i, ...) // LINUX: ret i32 2 // LINUX: define{{.*}} i32 @bar() -// LINUX: call i32 (i32, ...) @foo.ifunc(i32 noundef 1, i32 noundef 97, double -// LINUX: call i32 (i32, ...) @foo.ifunc(i32 noundef 2, double noundef 2.2{{[0-9Ee+]+}}, i8* noundef getelementptr inbounds +// LINUX: call i32 (i32, ...) @foo.ifunc(i32 1, i32 97, double +// LINUX: call i32 (i32, ...) @foo.ifunc(i32 2, double 2.2{{[0-9Ee+]+}}, i8* getelementptr inbounds // LINUX: define weak_odr i32 (i32, ...)* @foo.resolver() comdat // LINUX: ret i32 (i32, ...)* @foo.arch_sandybridge // LINUX: ret i32 (i32, ...)* @foo.arch_ivybridge // LINUX: ret i32 (i32, ...)* @foo.sse4.2 // LINUX: ret i32 (i32, ...)* @foo -// LINUX: declare i32 @foo.arch_sandybridge(i32 noundef, ...) +// LINUX: declare i32 @foo.arch_sandybridge(i32, ...) -// WINDOWS: define dso_local i32 @foo.sse4.2(i32 noundef %i, ...) +// WINDOWS: define dso_local i32 @foo.sse4.2(i32 %i, ...) // WINDOWS: ret i32 0 -// WINDOWS: define dso_local i32 @foo.arch_ivybridge(i32 noundef %i, ...) +// WINDOWS: define dso_local i32 @foo.arch_ivybridge(i32 %i, ...) // WINDOWS: ret i32 1 -// WINDOWS: define dso_local i32 @foo(i32 noundef %i, ...) +// WINDOWS: define dso_local i32 @foo(i32 %i, ...) // WINDOWS: ret i32 2 // WINDOWS: define dso_local i32 @bar() -// WINDOWS: call i32 (i32, ...) @foo.resolver(i32 noundef 1, i32 noundef 97, double -// WINDOWS: call i32 (i32, ...) @foo.resolver(i32 noundef 2, double noundef 2.2{{[0-9Ee+]+}}, i8* noundef getelementptr inbounds +// WINDOWS: call i32 (i32, ...) @foo.resolver(i32 1, i32 97, double +// WINDOWS: call i32 (i32, ...) @foo.resolver(i32 2, double 2.2{{[0-9Ee+]+}}, i8* getelementptr inbounds // WINDOWS: define weak_odr dso_local i32 @foo.resolver(i32 %0, ...) comdat // WINDOWS: musttail call i32 (i32, ...) @foo.arch_sandybridge // WINDOWS: musttail call i32 (i32, ...) @foo.arch_ivybridge // WINDOWS: musttail call i32 (i32, ...) @foo.sse4.2 // WINDOWS: musttail call i32 (i32, ...) @foo -// WINDOWS: declare dso_local i32 @foo.arch_sandybridge(i32 noundef, ...) +// WINDOWS: declare dso_local i32 @foo.arch_sandybridge(i32, ...) diff --git a/clang/test/CodeGen/attr-target-mv.c b/clang/test/CodeGen/attr-target-mv.c index 6755f3f02a6a04a1c8c80ab48ea1a5223baf9df7..9fa3e3b5f415e64420ad686eaac57a5f9e7ea4eb 100644 --- a/clang/test/CodeGen/attr-target-mv.c +++ b/clang/test/CodeGen/attr-target-mv.c @@ -193,10 +193,10 @@ void calls_pr50025c() { pr50025c(); } // WINDOWS: call void @foo_decls // LINUX: define{{.*}} void @bar4() -// LINUX: call void @foo_multi.ifunc(i32 noundef 1, double noundef 5.{{[0+e]*}}) +// LINUX: call void @foo_multi.ifunc(i32 1, double 5.{{[0+e]*}}) // WINDOWS: define dso_local void @bar4() -// WINDOWS: call void @foo_multi.resolver(i32 noundef 1, double noundef 5.{{[0+e]*}}) +// WINDOWS: call void @foo_multi.resolver(i32 1, double 5.{{[0+e]*}}) // LINUX: define weak_odr void (i32, double)* @foo_multi.resolver() comdat // LINUX: and i32 %{{.*}}, 4352 @@ -272,15 +272,15 @@ void calls_pr50025c() { pr50025c(); } // WINDOWS: define dso_local i32 @changed_to_mv.avx() // WINDOWS: define dso_local i32 @changed_to_mv.fma4() -// LINUX: define linkonce void @foo_used(i32 noundef %{{.*}}, double noundef %{{.*}}) +// LINUX: define linkonce void @foo_used(i32 %{{.*}}, double %{{.*}}) // LINUX-NOT: @foo_used.avx_sse4.2( // LINUX-NOT: @foo_used2( -// LINUX: define linkonce void @foo_used2.avx_sse4.2(i32 noundef %{{.*}}, double noundef %{{.*}}) +// LINUX: define linkonce void @foo_used2.avx_sse4.2(i32 %{{.*}}, double %{{.*}}) -// WINDOWS: define linkonce_odr dso_local void @foo_used(i32 noundef %{{.*}}, double noundef %{{.*}}) +// WINDOWS: define linkonce_odr dso_local void @foo_used(i32 %{{.*}}, double %{{.*}}) // WINDOWS-NOT: @foo_used.avx_sse4.2( // WINDOWS-NOT: @foo_used2( -// WINDOWS: define linkonce_odr dso_local void @foo_used2.avx_sse4.2(i32 noundef %{{.*}}, double noundef %{{.*}}) +// WINDOWS: define linkonce_odr dso_local void @foo_used2.avx_sse4.2(i32 %{{.*}}, double %{{.*}}) // LINUX: declare i32 @foo.arch_sandybridge() // WINDOWS: declare dso_local i32 @foo.arch_sandybridge() @@ -311,15 +311,15 @@ void calls_pr50025c() { pr50025c(); } // WINDOWS: define linkonce_odr dso_local void @foo_decls() // WINDOWS: define linkonce_odr dso_local void @foo_decls.sse4.2() -// LINUX: define linkonce void @foo_multi(i32 noundef %{{[^,]+}}, double noundef %{{[^\)]+}}) -// LINUX: define linkonce void @foo_multi.avx_sse4.2(i32 noundef %{{[^,]+}}, double noundef %{{[^\)]+}}) -// LINUX: define linkonce void @foo_multi.fma4_sse4.2(i32 noundef %{{[^,]+}}, double noundef %{{[^\)]+}}) -// LINUX: define linkonce void @foo_multi.arch_ivybridge_fma4_sse4.2(i32 noundef %{{[^,]+}}, double noundef %{{[^\)]+}}) +// LINUX: define linkonce void @foo_multi(i32 %{{[^,]+}}, double %{{[^\)]+}}) +// LINUX: define linkonce void @foo_multi.avx_sse4.2(i32 %{{[^,]+}}, double %{{[^\)]+}}) +// LINUX: define linkonce void @foo_multi.fma4_sse4.2(i32 %{{[^,]+}}, double %{{[^\)]+}}) +// LINUX: define linkonce void @foo_multi.arch_ivybridge_fma4_sse4.2(i32 %{{[^,]+}}, double %{{[^\)]+}}) -// WINDOWS: define linkonce_odr dso_local void @foo_multi(i32 noundef %{{[^,]+}}, double noundef %{{[^\)]+}}) -// WINDOWS: define linkonce_odr dso_local void @foo_multi.avx_sse4.2(i32 noundef %{{[^,]+}}, double noundef %{{[^\)]+}}) -// WINDOWS: define linkonce_odr dso_local void @foo_multi.fma4_sse4.2(i32 noundef %{{[^,]+}}, double noundef %{{[^\)]+}}) -// WINDOWS: define linkonce_odr dso_local void @foo_multi.arch_ivybridge_fma4_sse4.2(i32 noundef %{{[^,]+}}, double noundef %{{[^\)]+}}) +// WINDOWS: define linkonce_odr dso_local void @foo_multi(i32 %{{[^,]+}}, double %{{[^\)]+}}) +// WINDOWS: define linkonce_odr dso_local void @foo_multi.avx_sse4.2(i32 %{{[^,]+}}, double %{{[^\)]+}}) +// WINDOWS: define linkonce_odr dso_local void @foo_multi.fma4_sse4.2(i32 %{{[^,]+}}, double %{{[^\)]+}}) +// WINDOWS: define linkonce_odr dso_local void @foo_multi.arch_ivybridge_fma4_sse4.2(i32 %{{[^,]+}}, double %{{[^\)]+}}) // Ensure that we emit the 'static' function here. // LINUX: define linkonce void @pr50025() diff --git a/clang/test/CodeGen/attr-x86-interrupt.c b/clang/test/CodeGen/attr-x86-interrupt.c index 94206da95490bc3c0a9d03ff7d75ba8ad620562e..3453784dcc3a9d9964e9fb839cad55589075ae1d 100644 --- a/clang/test/CodeGen/attr-x86-interrupt.c +++ b/clang/test/CodeGen/attr-x86-interrupt.c @@ -13,22 +13,22 @@ typedef __UINT32_TYPE__ uword; __attribute__((interrupt)) void foo7(int *a, uword b) {} __attribute__((interrupt)) void foo8(int *a) {} // X86_64_LINUX: @llvm.compiler.used = appending global [2 x i8*] [i8* bitcast (void (i32*, i64)* @foo7 to i8*), i8* bitcast (void (i32*)* @foo8 to i8*)], section "llvm.metadata" -// X86_64_LINUX: define{{.*}} x86_intrcc void @foo7(i32* noundef byval(i32) %{{.+}}, i64 noundef %{{.+}}) -// X86_64_LINUX: define{{.*}} x86_intrcc void @foo8(i32* noundef byval(i32) %{{.+}}) +// X86_64_LINUX: define{{.*}} x86_intrcc void @foo7(i32* byval(i32) %{{.+}}, i64 %{{.+}}) +// X86_64_LINUX: define{{.*}} x86_intrcc void @foo8(i32* byval(i32) %{{.+}}) // X86_64_LINUX: "disable-tail-calls"="true" // X86_64_LINUX-NOT: "disable-tail-calls"="false" // X86_LINUX: @llvm.compiler.used = appending global [2 x i8*] [i8* bitcast (void (i32*, i32)* @foo7 to i8*), i8* bitcast (void (i32*)* @foo8 to i8*)], section "llvm.metadata" -// X86_LINUX: define{{.*}} x86_intrcc void @foo7(i32* noundef byval(i32) %{{.+}}, i32 noundef %{{.+}}) -// X86_LINUX: define{{.*}} x86_intrcc void @foo8(i32* noundef byval(i32) %{{.+}}) +// X86_LINUX: define{{.*}} x86_intrcc void @foo7(i32* byval(i32) %{{.+}}, i32 %{{.+}}) +// X86_LINUX: define{{.*}} x86_intrcc void @foo8(i32* byval(i32) %{{.+}}) // X86_LINUX: "disable-tail-calls"="true" // X86_LINUX-NOT: "disable-tail-calls"="false" // X86_64_WIN: @llvm.used = appending global [2 x i8*] [i8* bitcast (void (i32*, i64)* @foo7 to i8*), i8* bitcast (void (i32*)* @foo8 to i8*)], section "llvm.metadata" -// X86_64_WIN: define dso_local x86_intrcc void @foo7(i32* noundef byval(i32) %{{.+}}, i64 noundef %{{.+}}) -// X86_64_WIN: define dso_local x86_intrcc void @foo8(i32* noundef byval(i32) %{{.+}}) +// X86_64_WIN: define dso_local x86_intrcc void @foo7(i32* byval(i32) %{{.+}}, i64 %{{.+}}) +// X86_64_WIN: define dso_local x86_intrcc void @foo8(i32* byval(i32) %{{.+}}) // X86_64_WIN: "disable-tail-calls"="true" // X86_64_WIN-NOT: "disable-tail-calls"="false" // X86_WIN: @llvm.used = appending global [2 x i8*] [i8* bitcast (void (i32*, i32)* @foo7 to i8*), i8* bitcast (void (i32*)* @foo8 to i8*)], section "llvm.metadata" -// X86_WIN: define dso_local x86_intrcc void @foo7(i32* noundef byval(i32) %{{.+}}, i32 noundef %{{.+}}) -// X86_WIN: define dso_local x86_intrcc void @foo8(i32* noundef byval(i32) %{{.+}}) +// X86_WIN: define dso_local x86_intrcc void @foo7(i32* byval(i32) %{{.+}}, i32 %{{.+}}) +// X86_WIN: define dso_local x86_intrcc void @foo8(i32* byval(i32) %{{.+}}) // X86_WIN: "disable-tail-calls"="true" // X86_WIN-NOT: "disable-tail-calls"="false" diff --git a/clang/test/CodeGen/attributes.c b/clang/test/CodeGen/attributes.c index 02a6243a50e26f9f2b96925c66b38fae58a65682..d09d0e830abfaa370b4778aea0fd431a3188e4ef 100644 --- a/clang/test/CodeGen/attributes.c +++ b/clang/test/CodeGen/attributes.c @@ -97,7 +97,7 @@ void t21(void) { fptr(10); } // CHECK: [[FPTRVAR:%[a-z0-9]+]] = load void (i32)*, void (i32)** @fptr -// CHECK-NEXT: call x86_fastcallcc void [[FPTRVAR]](i32 inreg noundef 10) +// CHECK-NEXT: call x86_fastcallcc void [[FPTRVAR]](i32 inreg 10) // PR9356: We might want to err on this, but for now at least make sure we diff --git a/clang/test/CodeGen/available-externally-hidden.cpp b/clang/test/CodeGen/available-externally-hidden.cpp index 6ad1a4213b37b6b87428a2d0134c17045f57bc97..88ebfa9684a5970162b61c9d0a3b1f921caeff13 100644 --- a/clang/test/CodeGen/available-externally-hidden.cpp +++ b/clang/test/CodeGen/available-externally-hidden.cpp @@ -17,7 +17,7 @@ class Sender { virtual ~Sender() {} }; -// CHECK: declare noundef zeroext i1 @_ZThn16_N17SyncMessageFilter4SendEP7Message +// CHECK: declare zeroext i1 @_ZThn16_N17SyncMessageFilter4SendEP7Message class SyncMessageFilter : public Filter, public Sender { public: bool Send(Message* message) override; diff --git a/clang/test/CodeGen/available-externally-suppress.c b/clang/test/CodeGen/available-externally-suppress.c index a51519f29917ca1d15311001bb6d18d779caae0d..d229938a4450b22c9f810d9079d741eabf068785 100644 --- a/clang/test/CodeGen/available-externally-suppress.c +++ b/clang/test/CodeGen/available-externally-suppress.c @@ -1,9 +1,6 @@ -// RUN: %clang_cc1 -fno-experimental-new-pass-manager -emit-llvm -o - -triple x86_64-apple-darwin10 %s | FileCheck %s -// RUN: %clang_cc1 -fno-experimental-new-pass-manager -O2 -fno-inline -emit-llvm -o - -triple x86_64-apple-darwin10 %s | FileCheck %s -// RUN: %clang_cc1 -fno-experimental-new-pass-manager -flto -O2 -fno-inline -emit-llvm -o - -triple x86_64-apple-darwin10 %s | FileCheck %s -check-prefix=LTO -// RUN: %clang_cc1 -fexperimental-new-pass-manager -emit-llvm -o - -triple x86_64-apple-darwin10 %s | FileCheck %s -// RUN: %clang_cc1 -fexperimental-new-pass-manager -O2 -fno-inline -emit-llvm -o - -triple x86_64-apple-darwin10 %s | FileCheck %s -// RUN: %clang_cc1 -fexperimental-new-pass-manager -flto -O2 -fno-inline -emit-llvm -o - -triple x86_64-apple-darwin10 %s | FileCheck %s -check-prefix=LTO +// RUN: %clang_cc1 -emit-llvm -o - -triple x86_64-apple-darwin10 %s | FileCheck %s +// RUN: %clang_cc1 -O2 -fno-inline -emit-llvm -o - -triple x86_64-apple-darwin10 %s | FileCheck %s +// RUN: %clang_cc1 -flto -O2 -fno-inline -emit-llvm -o - -triple x86_64-apple-darwin10 %s | FileCheck %s -check-prefix=LTO // Ensure that we don't emit available_externally functions at -O0. // Also should not emit them at -O2, unless -flto is present in which case @@ -13,7 +10,7 @@ int x; inline void f0(int y) { x = y; } // CHECK-LABEL: define{{.*}} void @test() -// CHECK: declare void @f0(i32 noundef) +// CHECK: declare void @f0(i32) // LTO-LABEL: define{{.*}} void @test() // LTO: define available_externally void @f0 void test() { diff --git a/clang/test/CodeGen/avr/struct.c b/clang/test/CodeGen/avr/struct.c index 54fb59e4292e8972c86f41139b1aa9fd2f14fd5a..cb4e84522df63e35152658a2ce1f6644e1487e59 100644 --- a/clang/test/CodeGen/avr/struct.c +++ b/clang/test/CodeGen/avr/struct.c @@ -22,5 +22,5 @@ struct s06 foo06(int a, int b, int c) { // CHECK: %struct.s10 = type { i16, i16, i16, i16, i16 } // CHECK: %struct.s06 = type { i16, i16, i16 } -// CHECK: define{{.*}} void @foo10(%struct.s10* {{.*}}, i16 noundef %a, i16 noundef %b, i16 noundef %c) -// CHECK: define{{.*}} %struct.s06 @foo06(i16 noundef %a, i16 noundef %b, i16 noundef %c) +// CHECK: define{{.*}} void @foo10(%struct.s10* {{.*}}, i16 %a, i16 %b, i16 %c) +// CHECK: define{{.*}} %struct.s06 @foo06(i16 %a, i16 %b, i16 %c) diff --git a/clang/test/CodeGen/big-atomic-ops.c b/clang/test/CodeGen/big-atomic-ops.c index 108ccc9a69b5368e2eb41f2e8debd1fed51e1117..0dc43caa6472331d069a9c1f865530bf8ef706ce 100644 --- a/clang/test/CodeGen/big-atomic-ops.c +++ b/clang/test/CodeGen/big-atomic-ops.c @@ -198,20 +198,20 @@ struct Seventeen { int lock_free(struct Incomplete *incomplete) { // CHECK: @lock_free - // CHECK: call zeroext i1 @__atomic_is_lock_free(i64 noundef 3, i8* noundef null) + // CHECK: call zeroext i1 @__atomic_is_lock_free(i64 3, i8* null) __c11_atomic_is_lock_free(3); - // CHECK: call zeroext i1 @__atomic_is_lock_free(i64 noundef 16, i8* noundef {{.*}}@sixteen{{.*}}) + // CHECK: call zeroext i1 @__atomic_is_lock_free(i64 16, i8* {{.*}}@sixteen{{.*}}) __atomic_is_lock_free(16, &sixteen); - // CHECK: call zeroext i1 @__atomic_is_lock_free(i64 noundef 17, i8* noundef {{.*}}@seventeen{{.*}}) + // CHECK: call zeroext i1 @__atomic_is_lock_free(i64 17, i8* {{.*}}@seventeen{{.*}}) __atomic_is_lock_free(17, &seventeen); - // CHECK: call zeroext i1 @__atomic_is_lock_free(i64 noundef 4, {{.*}}) + // CHECK: call zeroext i1 @__atomic_is_lock_free(i64 4, {{.*}}) __atomic_is_lock_free(4, incomplete); char cs[20]; - // CHECK: call zeroext i1 @__atomic_is_lock_free(i64 noundef 4, {{.*}}) + // CHECK: call zeroext i1 @__atomic_is_lock_free(i64 4, {{.*}}) __atomic_is_lock_free(4, cs+1); // CHECK-NOT: call @@ -247,47 +247,47 @@ void structAtomicStore() { // CHECK: @structAtomicStore struct foo f = {0}; __c11_atomic_store(&bigAtomic, f, 5); - // CHECK: call void @__atomic_store(i64 noundef 512, i8* noundef bitcast ({{.*}} @bigAtomic to i8*), + // CHECK: call void @__atomic_store(i64 512, i8* bitcast ({{.*}} @bigAtomic to i8*), struct bar b = {0}; __atomic_store(&smallThing, &b, 5); - // CHECK: call void @__atomic_store(i64 noundef 3, i8* noundef {{.*}} @smallThing + // CHECK: call void @__atomic_store(i64 3, i8* {{.*}} @smallThing __atomic_store(&bigThing, &f, 5); - // CHECK: call void @__atomic_store(i64 noundef 512, i8* noundef {{.*}} @bigThing + // CHECK: call void @__atomic_store(i64 512, i8* {{.*}} @bigThing } void structAtomicLoad() { // CHECK: @structAtomicLoad struct foo f = __c11_atomic_load(&bigAtomic, 5); - // CHECK: call void @__atomic_load(i64 noundef 512, i8* noundef bitcast ({{.*}} @bigAtomic to i8*), + // CHECK: call void @__atomic_load(i64 512, i8* bitcast ({{.*}} @bigAtomic to i8*), struct bar b; __atomic_load(&smallThing, &b, 5); - // CHECK: call void @__atomic_load(i64 noundef 3, i8* noundef {{.*}} @smallThing + // CHECK: call void @__atomic_load(i64 3, i8* {{.*}} @smallThing __atomic_load(&bigThing, &f, 5); - // CHECK: call void @__atomic_load(i64 noundef 512, i8* noundef {{.*}} @bigThing + // CHECK: call void @__atomic_load(i64 512, i8* {{.*}} @bigThing } struct foo structAtomicExchange() { // CHECK: @structAtomicExchange struct foo f = {0}; struct foo old; __atomic_exchange(&f, &bigThing, &old, 5); - // CHECK: call void @__atomic_exchange(i64 noundef 512, {{.*}}, i8* noundef bitcast ({{.*}} @bigThing to i8*), + // CHECK: call void @__atomic_exchange(i64 512, {{.*}}, i8* bitcast ({{.*}} @bigThing to i8*), return __c11_atomic_exchange(&bigAtomic, f, 5); - // CHECK: call void @__atomic_exchange(i64 noundef 512, i8* noundef bitcast ({{.*}} @bigAtomic to i8*), + // CHECK: call void @__atomic_exchange(i64 512, i8* bitcast ({{.*}} @bigAtomic to i8*), } int structAtomicCmpExchange() { // CHECK: @structAtomicCmpExchange _Bool x = __atomic_compare_exchange(&smallThing, &thing1, &thing2, 1, 5, 5); - // CHECK: call zeroext i1 @__atomic_compare_exchange(i64 noundef 3, {{.*}} @smallThing{{.*}} @thing1{{.*}} @thing2 + // CHECK: call zeroext i1 @__atomic_compare_exchange(i64 3, {{.*}} @smallThing{{.*}} @thing1{{.*}} @thing2 struct foo f = {0}; struct foo g = {0}; g.big[12] = 12; return x & __c11_atomic_compare_exchange_strong(&bigAtomic, &f, g, 5, 5); - // CHECK: call zeroext i1 @__atomic_compare_exchange(i64 noundef 512, i8* noundef bitcast ({{.*}} @bigAtomic to i8*), + // CHECK: call zeroext i1 @__atomic_compare_exchange(i64 512, i8* bitcast ({{.*}} @bigAtomic to i8*), } // Check that no atomic operations are used in any initialisation of _Atomic diff --git a/clang/test/CodeGen/bittest-intrin.c b/clang/test/CodeGen/bittest-intrin.c index 20b2d2bd6913dc5a3bd5edc5a4c4f384cc0166e8..0add34d61e6f53102bd31bd34613f21aade8741d 100644 --- a/clang/test/CodeGen/bittest-intrin.c +++ b/clang/test/CodeGen/bittest-intrin.c @@ -33,7 +33,7 @@ void test_arm(long *base, long idx) { } #endif -// X64-LABEL: define dso_local void @test32(i32* noundef %base, i32 noundef %idx) +// X64-LABEL: define dso_local void @test32(i32* %base, i32 %idx) // X64: call i8 asm sideeffect "btl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}}) // X64: call i8 asm sideeffect "btcl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}}) // X64: call i8 asm sideeffect "btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}}) @@ -41,7 +41,7 @@ void test_arm(long *base, long idx) { // X64: call i8 asm sideeffect "lock btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}}) // X64: call i8 asm sideeffect "lock btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}}) -// X64-LABEL: define dso_local void @test64(i64* noundef %base, i64 noundef %idx) +// X64-LABEL: define dso_local void @test64(i64* %base, i64 %idx) // X64: call i8 asm sideeffect "btq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}}) // X64: call i8 asm sideeffect "btcq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}}) // X64: call i8 asm sideeffect "btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}}) @@ -49,7 +49,7 @@ void test_arm(long *base, long idx) { // X64: call i8 asm sideeffect "lock btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}}) // X64: call i8 asm sideeffect "lock btsq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}}) -// ARM-LABEL: define dso_local {{.*}}void @test32(i32* noundef %base, i32 noundef %idx) +// ARM-LABEL: define dso_local {{.*}}void @test32(i32* %base, i32 %idx) // ARM: %[[IDXHI:[^ ]*]] = ashr i32 %{{.*}}, 3 // ARM: %[[BASE:[^ ]*]] = bitcast i32* %{{.*}} to i8* // ARM: %[[BYTEADDR:[^ ]*]] = getelementptr inbounds i8, i8* %[[BASE]], i32 %[[IDXHI]] @@ -126,7 +126,7 @@ void test_arm(long *base, long idx) { // Just look for the atomicrmw instructions. -// ARM-LABEL: define dso_local {{.*}}void @test_arm(i32* noundef %base, i32 noundef %idx) +// ARM-LABEL: define dso_local {{.*}}void @test_arm(i32* %base, i32 %idx) // ARM: atomicrmw and i8* %{{.*}}, i8 {{.*}} acquire, align 1 // ARM: atomicrmw and i8* %{{.*}}, i8 {{.*}} release, align 1 // ARM: atomicrmw and i8* %{{.*}}, i8 {{.*}} monotonic, align 1 diff --git a/clang/test/CodeGen/blocks.c b/clang/test/CodeGen/blocks.c index 95535545b1cf1fd2c702de0924c45d99d0763b76..d12be614fe51ad8cf8fea130825c96c4c06250ed 100644 --- a/clang/test/CodeGen/blocks.c +++ b/clang/test/CodeGen/blocks.c @@ -18,7 +18,7 @@ struct s0 { int a[64]; }; -// CHECK: define internal void @__f2_block_invoke(%struct.s0* noalias sret(%struct.s0) align 4 {{%.*}}, i8* noundef {{%.*}}, %struct.s0* noundef byval(%struct.s0) align 4 {{.*}}) +// CHECK: define internal void @__f2_block_invoke(%struct.s0* noalias sret(%struct.s0) align 4 {{%.*}}, i8* {{%.*}}, %struct.s0* byval(%struct.s0) align 4 {{.*}}) struct s0 f2(struct s0 a0) { return ^(struct s0 a1){ return a1; }(a0); } @@ -33,7 +33,7 @@ void (^test1)(void) = ^(void) { ^ { i = 1; }(); }; -// CHECK-LABEL: define linkonce_odr hidden void @__copy_helper_block_4_20r(i8* noundef %0, i8* noundef %1) unnamed_addr +// CHECK-LABEL: define linkonce_odr hidden void @__copy_helper_block_4_20r(i8* %0, i8* %1) unnamed_addr // CHECK: %[[_ADDR:.*]] = alloca i8*, align 4 // CHECK-NEXT: %[[_ADDR1:.*]] = alloca i8*, align 4 // CHECK-NEXT: store i8* %0, i8** %[[_ADDR]], align 4 @@ -49,7 +49,7 @@ void (^test1)(void) = ^(void) { // CHECK-NEXT: call void @_Block_object_assign(i8* %[[V6]], i8* %[[BLOCKCOPY_SRC]], i32 8) // CHECK-NEXT: ret void -// CHECK-LABEL: define linkonce_odr hidden void @__destroy_helper_block_4_20r(i8* noundef %0) unnamed_addr +// CHECK-LABEL: define linkonce_odr hidden void @__destroy_helper_block_4_20r(i8* %0) unnamed_addr // CHECK: %[[_ADDR:.*]] = alloca i8*, align 4 // CHECK-NEXT: store i8* %0, i8** %[[_ADDR]], align 4 // CHECK-NEXT: %[[V1:.*]] = load i8*, i8** %[[_ADDR]], align 4 diff --git a/clang/test/CodeGen/bool-convert.c b/clang/test/CodeGen/bool-convert.c index 96d0b03671b5f1a69f62771c151b84ea3465e5de..12bd67ec6cd583e846cacfbed3e1f340dc4cab44 100644 --- a/clang/test/CodeGen/bool-convert.c +++ b/clang/test/CodeGen/bool-convert.c @@ -14,7 +14,7 @@ _Bool test3[10]; // CHECK-LABEL: @test4 ={{.*}} global [0 x i8]* null _Bool (*test4)[]; -// CHECK-LABEL: define{{.*}} void @f(i32 noundef %x) +// CHECK-LABEL: define{{.*}} void @f(i32 %x) void f(int x) { // CHECK: alloca i8, align 1 _Bool test5; diff --git a/clang/test/CodeGen/builtin-align-array.c b/clang/test/CodeGen/builtin-align-array.c index b64d26623a3c63b3a4ea38529e78c7ccba6eda76..31f7b42b56170b6d33c377e557b3c1b9241fc05e 100644 --- a/clang/test/CodeGen/builtin-align-array.c +++ b/clang/test/CodeGen/builtin-align-array.c @@ -13,7 +13,7 @@ extern int func(char *c); // CHECK-NEXT: [[DIFF:%.*]] = sub i64 [[ALIGNED_INTPTR]], [[INTPTR]] // CHECK-NEXT: [[ALIGNED_RESULT:%.*]] = getelementptr inbounds i8, i8* [[ARRAYIDX]], i64 [[DIFF]] // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* [[ALIGNED_RESULT]], i64 16) ] -// CHECK-NEXT: [[CALL:%.*]] = call i32 @func(i8* noundef [[ALIGNED_RESULT]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32 @func(i8* [[ALIGNED_RESULT]]) // CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [1024 x i8], [1024 x i8]* [[BUF]], i64 0, i64 22 // CHECK-NEXT: [[INTPTR2:%.*]] = ptrtoint i8* [[ARRAYIDX1]] to i64 // CHECK-NEXT: [[OVER_BOUNDARY:%.*]] = add i64 [[INTPTR2]], 31 @@ -21,7 +21,7 @@ extern int func(char *c); // CHECK-NEXT: [[DIFF5:%.*]] = sub i64 [[ALIGNED_INTPTR4]], [[INTPTR2]] // CHECK-NEXT: [[ALIGNED_RESULT6:%.*]] = getelementptr inbounds i8, i8* [[ARRAYIDX1]], i64 [[DIFF5]] // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* [[ALIGNED_RESULT6]], i64 32) ] -// CHECK-NEXT: [[CALL7:%.*]] = call i32 @func(i8* noundef [[ALIGNED_RESULT6]]) +// CHECK-NEXT: [[CALL7:%.*]] = call i32 @func(i8* [[ALIGNED_RESULT6]]) // CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1024 x i8], [1024 x i8]* [[BUF]], i64 0, i64 16 // CHECK-NEXT: [[SRC_ADDR:%.*]] = ptrtoint i8* [[ARRAYIDX8]] to i64 // CHECK-NEXT: [[SET_BITS:%.*]] = and i64 [[SRC_ADDR]], 63 @@ -45,7 +45,7 @@ int test_array(void) { // CHECK-NEXT: [[DIFF:%.*]] = sub i64 [[ALIGNED_INTPTR]], [[INTPTR]] // CHECK-NEXT: [[ALIGNED_RESULT:%.*]] = getelementptr inbounds i8, i8* [[ARRAYIDX]], i64 [[DIFF]] // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* [[ALIGNED_RESULT]], i64 16) ] -// CHECK-NEXT: [[CALL:%.*]] = call i32 @func(i8* noundef [[ALIGNED_RESULT]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32 @func(i8* [[ALIGNED_RESULT]]) // CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [1024 x i8], [1024 x i8]* [[BUF]], i64 0, i64 32 // CHECK-NEXT: [[INTPTR2:%.*]] = ptrtoint i8* [[ARRAYIDX1]] to i64 // CHECK-NEXT: [[OVER_BOUNDARY:%.*]] = add i64 [[INTPTR2]], 31 @@ -53,7 +53,7 @@ int test_array(void) { // CHECK-NEXT: [[DIFF5:%.*]] = sub i64 [[ALIGNED_INTPTR4]], [[INTPTR2]] // CHECK-NEXT: [[ALIGNED_RESULT6:%.*]] = getelementptr inbounds i8, i8* [[ARRAYIDX1]], i64 [[DIFF5]] // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* [[ALIGNED_RESULT6]], i64 32) ] -// CHECK-NEXT: [[CALL7:%.*]] = call i32 @func(i8* noundef [[ALIGNED_RESULT6]]) +// CHECK-NEXT: [[CALL7:%.*]] = call i32 @func(i8* [[ALIGNED_RESULT6]]) // CHECK-NEXT: ret i32 1 // int test_array_should_not_mask(void) { diff --git a/clang/test/CodeGen/builtin-align.c b/clang/test/CodeGen/builtin-align.c index a70219716de322244bf99b540487a33bc7fc47e1..75e9346200b0f95281b14f310abe1ce528a46b21 100644 --- a/clang/test/CodeGen/builtin-align.c +++ b/clang/test/CodeGen/builtin-align.c @@ -69,7 +69,7 @@ TYPE get_type(void) { } // CHECK-VOID_PTR-LABEL: define {{[^@]+}}@is_aligned -// CHECK-VOID_PTR-SAME: (i8* noundef [[PTR:%.*]], i32 noundef [[ALIGN:%.*]]) #0 +// CHECK-VOID_PTR-SAME: (i8* [[PTR:%.*]], i32 [[ALIGN:%.*]]) #0 // CHECK-VOID_PTR-NEXT: entry: // CHECK-VOID_PTR-NEXT: [[ALIGNMENT:%.*]] = zext i32 [[ALIGN]] to i64 // CHECK-VOID_PTR-NEXT: [[MASK:%.*]] = sub i64 [[ALIGNMENT]], 1 @@ -79,7 +79,7 @@ TYPE get_type(void) { // CHECK-VOID_PTR-NEXT: ret i1 [[IS_ALIGNED]] // // CHECK-FLOAT_PTR-LABEL: define {{[^@]+}}@is_aligned -// CHECK-FLOAT_PTR-SAME: (float* noundef [[PTR:%.*]], i32 noundef [[ALIGN:%.*]]) #0 +// CHECK-FLOAT_PTR-SAME: (float* [[PTR:%.*]], i32 [[ALIGN:%.*]]) #0 // CHECK-FLOAT_PTR-NEXT: entry: // CHECK-FLOAT_PTR-NEXT: [[ALIGNMENT:%.*]] = zext i32 [[ALIGN]] to i64 // CHECK-FLOAT_PTR-NEXT: [[MASK:%.*]] = sub i64 [[ALIGNMENT]], 1 @@ -89,7 +89,7 @@ TYPE get_type(void) { // CHECK-FLOAT_PTR-NEXT: ret i1 [[IS_ALIGNED]] // // CHECK-LONG-LABEL: define {{[^@]+}}@is_aligned -// CHECK-LONG-SAME: (i64 noundef [[PTR:%.*]], i32 noundef [[ALIGN:%.*]]) #0 +// CHECK-LONG-SAME: (i64 [[PTR:%.*]], i32 [[ALIGN:%.*]]) #0 // CHECK-LONG-NEXT: entry: // CHECK-LONG-NEXT: [[ALIGNMENT:%.*]] = zext i32 [[ALIGN]] to i64 // CHECK-LONG-NEXT: [[MASK:%.*]] = sub i64 [[ALIGNMENT]], 1 @@ -98,7 +98,7 @@ TYPE get_type(void) { // CHECK-LONG-NEXT: ret i1 [[IS_ALIGNED]] // // CHECK-USHORT-LABEL: define {{[^@]+}}@is_aligned -// CHECK-USHORT-SAME: (i16 noundef zeroext [[PTR:%.*]], i32 noundef [[ALIGN:%.*]]) #0 +// CHECK-USHORT-SAME: (i16 zeroext [[PTR:%.*]], i32 [[ALIGN:%.*]]) #0 // CHECK-USHORT-NEXT: entry: // CHECK-USHORT-NEXT: [[ALIGNMENT:%.*]] = trunc i32 [[ALIGN]] to i16 // CHECK-USHORT-NEXT: [[MASK:%.*]] = sub i16 [[ALIGNMENT]], 1 @@ -112,7 +112,7 @@ _Bool is_aligned(TYPE ptr, unsigned align) { // NOTYET-POINTER-NEXT: [[ALIGNED_RESULT:%.*]] = call [[$TYPE]] @llvm.ptrmask.p0[[$PTRTYPE]].p0i8.i64(i8* [[OVER_BOUNDARY]], [[ALIGN_TYPE]] [[INVERTED_MASK]]) // CHECK-VOID_PTR-LABEL: define {{[^@]+}}@align_up -// CHECK-VOID_PTR-SAME: (i8* noundef [[PTR:%.*]], i32 noundef [[ALIGN:%.*]]) #0 +// CHECK-VOID_PTR-SAME: (i8* [[PTR:%.*]], i32 [[ALIGN:%.*]]) #0 // CHECK-VOID_PTR-NEXT: entry: // CHECK-VOID_PTR-NEXT: [[ALIGNMENT:%.*]] = zext i32 [[ALIGN]] to i64 // CHECK-VOID_PTR-NEXT: [[MASK:%.*]] = sub i64 [[ALIGNMENT]], 1 @@ -126,7 +126,7 @@ _Bool is_aligned(TYPE ptr, unsigned align) { // CHECK-VOID_PTR-NEXT: ret i8* [[ALIGNED_RESULT]] // // CHECK-FLOAT_PTR-LABEL: define {{[^@]+}}@align_up -// CHECK-FLOAT_PTR-SAME: (float* noundef [[PTR:%.*]], i32 noundef [[ALIGN:%.*]]) #0 +// CHECK-FLOAT_PTR-SAME: (float* [[PTR:%.*]], i32 [[ALIGN:%.*]]) #0 // CHECK-FLOAT_PTR-NEXT: entry: // CHECK-FLOAT_PTR-NEXT: [[ALIGNMENT:%.*]] = zext i32 [[ALIGN]] to i64 // CHECK-FLOAT_PTR-NEXT: [[MASK:%.*]] = sub i64 [[ALIGNMENT]], 1 @@ -142,7 +142,7 @@ _Bool is_aligned(TYPE ptr, unsigned align) { // CHECK-FLOAT_PTR-NEXT: ret float* [[TMP1]] // // CHECK-LONG-LABEL: define {{[^@]+}}@align_up -// CHECK-LONG-SAME: (i64 noundef [[PTR:%.*]], i32 noundef [[ALIGN:%.*]]) #0 +// CHECK-LONG-SAME: (i64 [[PTR:%.*]], i32 [[ALIGN:%.*]]) #0 // CHECK-LONG-NEXT: entry: // CHECK-LONG-NEXT: [[ALIGNMENT:%.*]] = zext i32 [[ALIGN]] to i64 // CHECK-LONG-NEXT: [[MASK:%.*]] = sub i64 [[ALIGNMENT]], 1 @@ -152,7 +152,7 @@ _Bool is_aligned(TYPE ptr, unsigned align) { // CHECK-LONG-NEXT: ret i64 [[ALIGNED_RESULT]] // // CHECK-USHORT-LABEL: define {{[^@]+}}@align_up -// CHECK-USHORT-SAME: (i16 noundef zeroext [[PTR:%.*]], i32 noundef [[ALIGN:%.*]]) #0 +// CHECK-USHORT-SAME: (i16 zeroext [[PTR:%.*]], i32 [[ALIGN:%.*]]) #0 // CHECK-USHORT-NEXT: entry: // CHECK-USHORT-NEXT: [[ALIGNMENT:%.*]] = trunc i32 [[ALIGN]] to i16 // CHECK-USHORT-NEXT: [[MASK:%.*]] = sub i16 [[ALIGNMENT]], 1 @@ -167,7 +167,7 @@ TYPE align_up(TYPE ptr, unsigned align) { // NOTYET-POINTER-NEXT: [[ALIGNED_RESULT:%.*]] = call [[$TYPE]] @llvm.ptrmask.p0[[$PTRTYPE]].p0[[$PTRTYPE]].i64([[$TYPE]] [[PTR]], [[ALIGN_TYPE]] [[INVERTED_MASK]]) // CHECK-VOID_PTR-LABEL: define {{[^@]+}}@align_down -// CHECK-VOID_PTR-SAME: (i8* noundef [[PTR:%.*]], i32 noundef [[ALIGN:%.*]]) #0 +// CHECK-VOID_PTR-SAME: (i8* [[PTR:%.*]], i32 [[ALIGN:%.*]]) #0 // CHECK-VOID_PTR-NEXT: entry: // CHECK-VOID_PTR-NEXT: [[ALIGNMENT:%.*]] = zext i32 [[ALIGN]] to i64 // CHECK-VOID_PTR-NEXT: [[MASK:%.*]] = sub i64 [[ALIGNMENT]], 1 @@ -180,7 +180,7 @@ TYPE align_up(TYPE ptr, unsigned align) { // CHECK-VOID_PTR-NEXT: ret i8* [[ALIGNED_RESULT]] // // CHECK-FLOAT_PTR-LABEL: define {{[^@]+}}@align_down -// CHECK-FLOAT_PTR-SAME: (float* noundef [[PTR:%.*]], i32 noundef [[ALIGN:%.*]]) #0 +// CHECK-FLOAT_PTR-SAME: (float* [[PTR:%.*]], i32 [[ALIGN:%.*]]) #0 // CHECK-FLOAT_PTR-NEXT: entry: // CHECK-FLOAT_PTR-NEXT: [[ALIGNMENT:%.*]] = zext i32 [[ALIGN]] to i64 // CHECK-FLOAT_PTR-NEXT: [[MASK:%.*]] = sub i64 [[ALIGNMENT]], 1 @@ -195,7 +195,7 @@ TYPE align_up(TYPE ptr, unsigned align) { // CHECK-FLOAT_PTR-NEXT: ret float* [[TMP1]] // // CHECK-LONG-LABEL: define {{[^@]+}}@align_down -// CHECK-LONG-SAME: (i64 noundef [[PTR:%.*]], i32 noundef [[ALIGN:%.*]]) #0 +// CHECK-LONG-SAME: (i64 [[PTR:%.*]], i32 [[ALIGN:%.*]]) #0 // CHECK-LONG-NEXT: entry: // CHECK-LONG-NEXT: [[ALIGNMENT:%.*]] = zext i32 [[ALIGN]] to i64 // CHECK-LONG-NEXT: [[MASK:%.*]] = sub i64 [[ALIGNMENT]], 1 @@ -204,7 +204,7 @@ TYPE align_up(TYPE ptr, unsigned align) { // CHECK-LONG-NEXT: ret i64 [[ALIGNED_RESULT]] // // CHECK-USHORT-LABEL: define {{[^@]+}}@align_down -// CHECK-USHORT-SAME: (i16 noundef zeroext [[PTR:%.*]], i32 noundef [[ALIGN:%.*]]) #0 +// CHECK-USHORT-SAME: (i16 zeroext [[PTR:%.*]], i32 [[ALIGN:%.*]]) #0 // CHECK-USHORT-NEXT: entry: // CHECK-USHORT-NEXT: [[ALIGNMENT:%.*]] = trunc i32 [[ALIGN]] to i16 // CHECK-USHORT-NEXT: [[MASK:%.*]] = sub i16 [[ALIGNMENT]], 1 diff --git a/clang/test/CodeGen/builtin-assume-aligned.c b/clang/test/CodeGen/builtin-assume-aligned.c index 7510820f5650f92db75ece3ae444891ba5723b2d..fc49eda839307d2df37b644deda6a1740519bdb2 100644 --- a/clang/test/CodeGen/builtin-assume-aligned.c +++ b/clang/test/CodeGen/builtin-assume-aligned.c @@ -1,10 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | FileCheck %s -// CHECK-LABEL: @test1( +// CHECK-LABEL: define {{[^@]+}}@test1 +// CHECK-SAME: (i32* [[A:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: store i32* [[A:%.*]], i32** [[A_ADDR]], align 8 +// CHECK-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* [[TMP1]], i64 32, i64 0) ] @@ -20,10 +21,11 @@ int test1(int *a) { return a[0]; } -// CHECK-LABEL: @test2( +// CHECK-LABEL: define {{[^@]+}}@test2 +// CHECK-SAME: (i32* [[A:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: store i32* [[A:%.*]], i32** [[A_ADDR]], align 8 +// CHECK-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* [[TMP1]], i64 32, i64 0) ] @@ -39,10 +41,11 @@ int test2(int *a) { return a[0]; } -// CHECK-LABEL: @test3( +// CHECK-LABEL: define {{[^@]+}}@test3 +// CHECK-SAME: (i32* [[A:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: store i32* [[A:%.*]], i32** [[A_ADDR]], align 8 +// CHECK-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* [[TMP1]], i64 32) ] @@ -58,12 +61,13 @@ int test3(int *a) { return a[0]; } -// CHECK-LABEL: @test4( +// CHECK-LABEL: define {{[^@]+}}@test4 +// CHECK-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32* [[A:%.*]], i32** [[A_ADDR]], align 8 -// CHECK-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4 +// CHECK-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 +// CHECK-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 @@ -83,7 +87,7 @@ int test4(int *a, int b) { int *m1() __attribute__((assume_aligned(64))); -// CHECK-LABEL: @test5( +// CHECK-LABEL: define {{[^@]+}}@test5() #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[CALL:%.*]] = call align 64 i32* (...) @m1() // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[CALL]], align 4 @@ -95,7 +99,7 @@ int test5() { int *m2() __attribute__((assume_aligned(64, 12))); -// CHECK-LABEL: @test6( +// CHECK-LABEL: define {{[^@]+}}@test6() #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[CALL:%.*]] = call i32* (...) @m2() // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[CALL]], i64 64, i64 12) ] @@ -106,10 +110,11 @@ int test6() { return *m2(); } -// CHECK-LABEL: @pr43638( +// CHECK-LABEL: define {{[^@]+}}@pr43638 +// CHECK-SAME: (i32* [[A:%.*]]) #0 // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: store i32* [[A:%.*]], i32** [[A_ADDR]], align 8 +// CHECK-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* [[TMP1]], i64 4294967296) ] diff --git a/clang/test/CodeGen/builtin-attributes.c b/clang/test/CodeGen/builtin-attributes.c index 1d39b46e7b8ba8b0535c356283809ed8d8ffd280..c5c35c389940e65dfc225947d345f07968ce9376 100644 --- a/clang/test/CodeGen/builtin-attributes.c +++ b/clang/test/CodeGen/builtin-attributes.c @@ -1,7 +1,7 @@ // REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple arm-unknown-linux-gnueabi -emit-llvm -o - %s | FileCheck %s -// CHECK: declare i32 @printf(i8* noundef, ...) +// CHECK: declare i32 @printf(i8*, ...) void f0() { printf("a\n"); } @@ -21,27 +21,27 @@ char* f2(char* a, char* b) { // // // CHECK: f3 -// CHECK: call double @frexp(double noundef % +// CHECK: call double @frexp(double % // CHECK-NOT: readnone -// CHECK: call float @frexpf(float noundef % +// CHECK: call float @frexpf(float % // CHECK-NOT: readnone -// CHECK: call double @frexpl(double noundef % +// CHECK: call double @frexpl(double % // CHECK-NOT: readnone // // Same thing for modf and friends. // -// CHECK: call double @modf(double noundef % +// CHECK: call double @modf(double % // CHECK-NOT: readnone -// CHECK: call float @modff(float noundef % +// CHECK: call float @modff(float % // CHECK-NOT: readnone -// CHECK: call double @modfl(double noundef % +// CHECK: call double @modfl(double % // CHECK-NOT: readnone // -// CHECK: call double @remquo(double noundef % +// CHECK: call double @remquo(double % // CHECK-NOT: readnone -// CHECK: call float @remquof(float noundef % +// CHECK: call float @remquof(float % // CHECK-NOT: readnone -// CHECK: call double @remquol(double noundef % +// CHECK: call double @remquol(double % // CHECK-NOT: readnone // CHECK: ret int f3(double x) { diff --git a/clang/test/CodeGen/builtin-memfns.c b/clang/test/CodeGen/builtin-memfns.c index 33e64dc054baf22b0f9c2fb57d223f65e9a63113..14ffbe90032156cb02a87a6b95cb9d7654eeec0c 100644 --- a/clang/test/CodeGen/builtin-memfns.c +++ b/clang/test/CodeGen/builtin-memfns.c @@ -96,10 +96,10 @@ wchar_t src; // CHECK-LABEL: @test10 // FIXME: Consider lowering these to llvm.memcpy / llvm.memmove. void test10() { - // CHECK: call i32* @wmemcpy(i32* noundef @dest, i32* noundef @src, i32 noundef 4) + // CHECK: call i32* @wmemcpy(i32* @dest, i32* @src, i32 4) __builtin_wmemcpy(&dest, &src, 4); - // CHECK: call i32* @wmemmove(i32* noundef @dest, i32* noundef @src, i32 noundef 4) + // CHECK: call i32* @wmemmove(i32* @dest, i32* @src, i32 4) __builtin_wmemmove(&dest, &src, 4); } diff --git a/clang/test/CodeGen/builtin-sqrt.c b/clang/test/CodeGen/builtin-sqrt.c index 070d6f175216f6161c9f8a136f50af464bc656ce..b997b77ebd58aa2602448cb59a19164195195d18 100644 --- a/clang/test/CodeGen/builtin-sqrt.c +++ b/clang/test/CodeGen/builtin-sqrt.c @@ -7,7 +7,7 @@ float foo(float X) { return __builtin_sqrtf(X); } -// HAS_ERRNO: declare float @sqrtf(float noundef) [[ATTR:#[0-9]+]] +// HAS_ERRNO: declare float @sqrtf(float) [[ATTR:#[0-9]+]] // HAS_ERRNO-NOT: attributes [[ATTR]] = {{{.*}} readnone // NO_ERRNO: declare float @llvm.sqrt.f32(float) [[ATTR:#[0-9]+]] diff --git a/clang/test/CodeGen/builtins-arm.c b/clang/test/CodeGen/builtins-arm.c index b1544a29daf55ebd81b20567150f717b9eab7166..1acd55d461586c9f675555b8a18b17952fe6f475 100644 --- a/clang/test/CodeGen/builtins-arm.c +++ b/clang/test/CodeGen/builtins-arm.c @@ -102,56 +102,56 @@ void prefetch(int i) { } void ldc(const void *i) { - // CHECK: define{{.*}} void @ldc(i8* noundef %i) + // CHECK: define{{.*}} void @ldc(i8* %i) // CHECK: call void @llvm.arm.ldc(i32 1, i32 2, i8* %i) // CHECK-NEXT: ret void __builtin_arm_ldc(1, 2, i); } void ldcl(const void *i) { - // CHECK: define{{.*}} void @ldcl(i8* noundef %i) + // CHECK: define{{.*}} void @ldcl(i8* %i) // CHECK: call void @llvm.arm.ldcl(i32 1, i32 2, i8* %i) // CHECK-NEXT: ret void __builtin_arm_ldcl(1, 2, i); } void ldc2(const void *i) { - // CHECK: define{{.*}} void @ldc2(i8* noundef %i) + // CHECK: define{{.*}} void @ldc2(i8* %i) // CHECK: call void @llvm.arm.ldc2(i32 1, i32 2, i8* %i) // CHECK-NEXT: ret void __builtin_arm_ldc2(1, 2, i); } void ldc2l(const void *i) { - // CHECK: define{{.*}} void @ldc2l(i8* noundef %i) + // CHECK: define{{.*}} void @ldc2l(i8* %i) // CHECK: call void @llvm.arm.ldc2l(i32 1, i32 2, i8* %i) // CHECK-NEXT: ret void __builtin_arm_ldc2l(1, 2, i); } void stc(void *i) { - // CHECK: define{{.*}} void @stc(i8* noundef %i) + // CHECK: define{{.*}} void @stc(i8* %i) // CHECK: call void @llvm.arm.stc(i32 1, i32 2, i8* %i) // CHECK-NEXT: ret void __builtin_arm_stc(1, 2, i); } void stcl(void *i) { - // CHECK: define{{.*}} void @stcl(i8* noundef %i) + // CHECK: define{{.*}} void @stcl(i8* %i) // CHECK: call void @llvm.arm.stcl(i32 1, i32 2, i8* %i) // CHECK-NEXT: ret void __builtin_arm_stcl(1, 2, i); } void stc2(void *i) { - // CHECK: define{{.*}} void @stc2(i8* noundef %i) + // CHECK: define{{.*}} void @stc2(i8* %i) // CHECK: call void @llvm.arm.stc2(i32 1, i32 2, i8* %i) // CHECK-NEXT: ret void __builtin_arm_stc2(1, 2, i); } void stc2l(void *i) { - // CHECK: define{{.*}} void @stc2l(i8* noundef %i) + // CHECK: define{{.*}} void @stc2l(i8* %i) // CHECK: call void @llvm.arm.stc2l(i32 1, i32 2, i8* %i) // CHECK-NEXT: ret void __builtin_arm_stc2l(1, 2, i); @@ -186,25 +186,25 @@ unsigned mrc2() { } void mcr(unsigned a) { - // CHECK: define{{.*}} void @mcr(i32 noundef [[A:%.*]]) + // CHECK: define{{.*}} void @mcr(i32 [[A:%.*]]) // CHECK: call void @llvm.arm.mcr(i32 15, i32 0, i32 [[A]], i32 13, i32 0, i32 3) __builtin_arm_mcr(15, 0, a, 13, 0, 3); } void mcr2(unsigned a) { - // CHECK: define{{.*}} void @mcr2(i32 noundef [[A:%.*]]) + // CHECK: define{{.*}} void @mcr2(i32 [[A:%.*]]) // CHECK: call void @llvm.arm.mcr2(i32 15, i32 0, i32 [[A]], i32 13, i32 0, i32 3) __builtin_arm_mcr2(15, 0, a, 13, 0, 3); } void mcrr(uint64_t a) { - // CHECK: define{{.*}} void @mcrr(i64 noundef %{{.*}}) + // CHECK: define{{.*}} void @mcrr(i64 %{{.*}}) // CHECK: call void @llvm.arm.mcrr(i32 15, i32 0, i32 %{{[0-9]+}}, i32 %{{[0-9]+}}, i32 0) __builtin_arm_mcrr(15, 0, a, 0); } void mcrr2(uint64_t a) { - // CHECK: define{{.*}} void @mcrr2(i64 noundef %{{.*}}) + // CHECK: define{{.*}} void @mcrr2(i64 %{{.*}}) // CHECK: call void @llvm.arm.mcrr2(i32 15, i32 0, i32 %{{[0-9]+}}, i32 %{{[0-9]+}}, i32 0) __builtin_arm_mcrr2(15, 0, a, 0); } diff --git a/clang/test/CodeGen/builtins-memcpy-inline.c b/clang/test/CodeGen/builtins-memcpy-inline.c index e4e3cdbde42d3b8b197c45f247701c9376e02f94..4cdf4dfe212a1590f347d34cd6e2dffd2c509d67 100644 --- a/clang/test/CodeGen/builtins-memcpy-inline.c +++ b/clang/test/CodeGen/builtins-memcpy-inline.c @@ -1,25 +1,25 @@ // REQUIRES: x86-registered-target // RUN: %clang_cc1 -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s -// CHECK-LABEL: define{{.*}} void @test_memcpy_inline_0(i8* noundef %dst, i8* noundef %src) +// CHECK-LABEL: define{{.*}} void @test_memcpy_inline_0(i8* %dst, i8* %src) void test_memcpy_inline_0(void *dst, const void *src) { // CHECK: call void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* align 1 %0, i8* align 1 %1, i64 0, i1 false) __builtin_memcpy_inline(dst, src, 0); } -// CHECK-LABEL: define{{.*}} void @test_memcpy_inline_1(i8* noundef %dst, i8* noundef %src) +// CHECK-LABEL: define{{.*}} void @test_memcpy_inline_1(i8* %dst, i8* %src) void test_memcpy_inline_1(void *dst, const void *src) { // CHECK: call void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* align 1 %0, i8* align 1 %1, i64 1, i1 false) __builtin_memcpy_inline(dst, src, 1); } -// CHECK-LABEL: define{{.*}} void @test_memcpy_inline_4(i8* noundef %dst, i8* noundef %src) +// CHECK-LABEL: define{{.*}} void @test_memcpy_inline_4(i8* %dst, i8* %src) void test_memcpy_inline_4(void *dst, const void *src) { // CHECK: call void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* align 1 %0, i8* align 1 %1, i64 4, i1 false) __builtin_memcpy_inline(dst, src, 4); } -// CHECK-LABEL: define{{.*}} void @test_memcpy_inline_aligned_buffers(i64* noundef %dst, i64* noundef %src) +// CHECK-LABEL: define{{.*}} void @test_memcpy_inline_aligned_buffers(i64* %dst, i64* %src) void test_memcpy_inline_aligned_buffers(unsigned long long *dst, const unsigned long long *src) { // CHECK: call void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* align 8 %2, i8* align 8 %3, i64 4, i1 false) __builtin_memcpy_inline(dst, src, 4); diff --git a/clang/test/CodeGen/builtins-ms.c b/clang/test/CodeGen/builtins-ms.c index 9bd96bf38187f25e06befa5e7775a6ba72061e95..915cc17e002c48fcfa3d73148134b0d07d939d4c 100644 --- a/clang/test/CodeGen/builtins-ms.c +++ b/clang/test/CodeGen/builtins-ms.c @@ -5,12 +5,12 @@ void capture(void *); void test_alloca(int n) { capture(_alloca(n)); // CHECK: %[[arg:.*]] = alloca i8, i32 %{{.*}}, align 16 - // CHECK: call void @capture(i8* noundef %[[arg]]) + // CHECK: call void @capture(i8* %[[arg]]) } // CHECK-LABEL: define dso_local void @test_alloca_with_align( void test_alloca_with_align(int n) { capture(__builtin_alloca_with_align(n, 64)); // CHECK: %[[arg:.*]] = alloca i8, i32 %{{.*}}, align 8 - // CHECK: call void @capture(i8* noundef %[[arg]]) + // CHECK: call void @capture(i8* %[[arg]]) } diff --git a/clang/test/CodeGen/builtins-multiprecision.c b/clang/test/CodeGen/builtins-multiprecision.c index 9b4054bd5618d08d3b97763ec97922a0750e45df..4d196088d3d87f34369c314b38925ad3defbc811 100644 --- a/clang/test/CodeGen/builtins-multiprecision.c +++ b/clang/test/CodeGen/builtins-multiprecision.c @@ -60,7 +60,7 @@ unsigned test_addc(unsigned x, unsigned y, unsigned carryin, unsigned *z) { unsigned long test_addcl(unsigned long x, unsigned long y, unsigned long carryin, unsigned long *z) { // long is i32 on i686, i64 on x86_64. - // CHECK: @test_addcl([[UL:i32|i64]] noundef %x + // CHECK: @test_addcl([[UL:i32|i64]] %x // CHECK: %{{.+}} = {{.*}} call { [[UL]], i1 } @llvm.uadd.with.overflow.[[UL]]([[UL]] %x, [[UL]] %y) // CHECK: %{{.+}} = extractvalue { [[UL]], i1 } %{{.+}}, 1 // CHECK: %{{.+}} = extractvalue { [[UL]], i1 } %{{.+}}, 0 @@ -152,7 +152,7 @@ unsigned test_subc(unsigned x, unsigned y, unsigned carryin, unsigned *z) { unsigned long test_subcl(unsigned long x, unsigned long y, unsigned long carryin, unsigned long *z) { - // CHECK: @test_subcl([[UL:i32|i64]] noundef %x + // CHECK: @test_subcl([[UL:i32|i64]] %x // CHECK: %{{.+}} = {{.*}} call { [[UL]], i1 } @llvm.usub.with.overflow.[[UL]]([[UL]] %x, [[UL]] %y) // CHECK: %{{.+}} = extractvalue { [[UL]], i1 } %{{.+}}, 1 // CHECK: %{{.+}} = extractvalue { [[UL]], i1 } %{{.+}}, 0 diff --git a/clang/test/CodeGen/builtins-overflow.c b/clang/test/CodeGen/builtins-overflow.c index 2526604d327e4c018f04b7eab1ba4380b17ab82c..636a571d136404f4e564631fb66395748d197040 100644 --- a/clang/test/CodeGen/builtins-overflow.c +++ b/clang/test/CodeGen/builtins-overflow.c @@ -302,7 +302,7 @@ unsigned test_uadd_overflow(unsigned x, unsigned y) { } unsigned long test_uaddl_overflow(unsigned long x, unsigned long y) { -// CHECK: @test_uaddl_overflow([[UL:i32|i64]] noundef %x +// CHECK: @test_uaddl_overflow([[UL:i32|i64]] %x // CHECK: %{{.+}} = call { [[UL]], i1 } @llvm.uadd.with.overflow.[[UL]]([[UL]] %{{.+}}, [[UL]] %{{.+}}) unsigned long result; if (__builtin_uaddl_overflow(x, y, &result)) @@ -329,7 +329,7 @@ unsigned test_usub_overflow(unsigned x, unsigned y) { } unsigned long test_usubl_overflow(unsigned long x, unsigned long y) { -// CHECK: @test_usubl_overflow([[UL:i32|i64]] noundef %x +// CHECK: @test_usubl_overflow([[UL:i32|i64]] %x // CHECK: %{{.+}} = call { [[UL]], i1 } @llvm.usub.with.overflow.[[UL]]([[UL]] %{{.+}}, [[UL]] %{{.+}}) unsigned long result; if (__builtin_usubl_overflow(x, y, &result)) @@ -356,7 +356,7 @@ unsigned test_umul_overflow(unsigned x, unsigned y) { } unsigned long test_umull_overflow(unsigned long x, unsigned long y) { -// CHECK: @test_umull_overflow([[UL:i32|i64]] noundef %x +// CHECK: @test_umull_overflow([[UL:i32|i64]] %x // CHECK: %{{.+}} = call { [[UL]], i1 } @llvm.umul.with.overflow.[[UL]]([[UL]] %{{.+}}, [[UL]] %{{.+}}) unsigned long result; if (__builtin_umull_overflow(x, y, &result)) @@ -383,7 +383,7 @@ int test_sadd_overflow(int x, int y) { } long test_saddl_overflow(long x, long y) { -// CHECK: @test_saddl_overflow([[UL:i32|i64]] noundef %x +// CHECK: @test_saddl_overflow([[UL:i32|i64]] %x // CHECK: %{{.+}} = call { [[UL]], i1 } @llvm.sadd.with.overflow.[[UL]]([[UL]] %{{.+}}, [[UL]] %{{.+}}) long result; if (__builtin_saddl_overflow(x, y, &result)) @@ -410,7 +410,7 @@ int test_ssub_overflow(int x, int y) { } long test_ssubl_overflow(long x, long y) { -// CHECK: @test_ssubl_overflow([[UL:i32|i64]] noundef %x +// CHECK: @test_ssubl_overflow([[UL:i32|i64]] %x // CHECK: %{{.+}} = call { [[UL]], i1 } @llvm.ssub.with.overflow.[[UL]]([[UL]] %{{.+}}, [[UL]] %{{.+}}) long result; if (__builtin_ssubl_overflow(x, y, &result)) @@ -437,7 +437,7 @@ int test_smul_overflow(int x, int y) { } long test_smull_overflow(long x, long y) { -// CHECK: @test_smull_overflow([[UL:i32|i64]] noundef %x +// CHECK: @test_smull_overflow([[UL:i32|i64]] %x // CHECK: %{{.+}} = call { [[UL]], i1 } @llvm.smul.with.overflow.[[UL]]([[UL]] %{{.+}}, [[UL]] %{{.+}}) long result; if (__builtin_smull_overflow(x, y, &result)) diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-macros.c b/clang/test/CodeGen/builtins-ppc-xlcompat-macros.c index 52273a2a26df2324b55c05ee01f4074221d54206..a331fb7300c5cf0dc0956ab79eb77cb4c874d94d 100644 --- a/clang/test/CodeGen/builtins-ppc-xlcompat-macros.c +++ b/clang/test/CodeGen/builtins-ppc-xlcompat-macros.c @@ -154,11 +154,11 @@ void testalignx(const void *pointer) { } // 64BIT-LABEL: @testbcopy( -// 64BIT: call void @bcopy(i8* noundef {{%.*}}, i8* noundef {{%.*}}, i64 noundef {{%.*}}) +// 64BIT: call void @bcopy(i8* {{%.*}}, i8* {{%.*}}, i64 {{%.*}}) // 64BIT-NEXT: ret void // // 32BIT-LABEL: @testbcopy( -// 32BIT: call void @bcopy(i8* noundef {{%.*}}, i8* noundef {{%.*}}, i32 noundef {{%.*}}) +// 32BIT: call void @bcopy(i8* {{%.*}}, i8* {{%.*}}, i32 {{%.*}}) // 32BIT-NEXT: ret void // void testbcopy(const void *src, void *dest, size_t n) { diff --git a/clang/test/CodeGen/builtins.c b/clang/test/CodeGen/builtins.c index 87cdca01e6230a23e194b4422a06a0a14ae586b6..9ecb4a2a3c0a834d566f7eb0ce3561ad7face248 100644 --- a/clang/test/CodeGen/builtins.c +++ b/clang/test/CodeGen/builtins.c @@ -482,7 +482,7 @@ void test___warn_memset_zero_len() { #ifdef __x86_64__ // CHECK-LABEL: define{{.*}} void @test_builtin_os_log -// CHECK: (i8* noundef %[[BUF:.*]], i32 noundef %[[I:.*]], i8* noundef %[[DATA:.*]]) +// CHECK: (i8* %[[BUF:.*]], i32 %[[I:.*]], i8* %[[DATA:.*]]) void test_builtin_os_log(void *buf, int i, const char *data) { volatile int len; // CHECK: %[[BUF_ADDR:.*]] = alloca i8*, align 8 @@ -502,7 +502,7 @@ void test_builtin_os_log(void *buf, int i, const char *data) { // CHECK: %[[V4:.*]] = ptrtoint i8* %[[V3]] to i64 // CHECK: %[[V5:.*]] = load i8*, i8** %[[DATA_ADDR]] // CHECK: %[[V6:.*]] = ptrtoint i8* %[[V5]] to i64 - // CHECK: call void @__os_log_helper_1_3_4_4_0_8_34_4_17_8_49(i8* noundef %[[V1]], i32 noundef %[[V2]], i64 noundef %[[V4]], i32 noundef 16, i64 noundef %[[V6]]) + // CHECK: call void @__os_log_helper_1_3_4_4_0_8_34_4_17_8_49(i8* %[[V1]], i32 %[[V2]], i64 %[[V4]], i32 16, i64 %[[V6]]) __builtin_os_log_format(buf, "%d %{public}s %{private}.16P", i, data, data); // privacy annotations aren't recognized when they are preceded or followed @@ -540,10 +540,10 @@ void test_builtin_os_log(void *buf, int i, const char *data) { // CHECK: store volatile i32 22, i32* %[[LEN]], align 4 len = __builtin_os_log_format_buffer_size("%{mask.xyz}s", "abc"); - // CHECK: call void @__os_log_helper_1_2_2_8_112_8_34(i8* noundef {{.*}}, i64 noundef 8026488 + // CHECK: call void @__os_log_helper_1_2_2_8_112_8_34(i8* {{.*}}, i64 8026488 __builtin_os_log_format(buf, "%{mask.xyz, public}s", "abc"); - // CHECK: call void @__os_log_helper_1_3_2_8_112_4_1(i8* noundef {{.*}}, i64 noundef 8026488 + // CHECK: call void @__os_log_helper_1_3_2_8_112_4_1(i8* {{.*}}, i64 8026488 __builtin_os_log_format(buf, "%{ mask.xyz, private }d", 11); // Mask type is silently ignored. @@ -555,7 +555,7 @@ void test_builtin_os_log(void *buf, int i, const char *data) { } // CHECK-LABEL: define linkonce_odr hidden void @__os_log_helper_1_3_4_4_0_8_34_4_17_8_49 -// CHECK: (i8* noundef %[[BUFFER:.*]], i32 noundef %[[ARG0:.*]], i64 noundef %[[ARG1:.*]], i32 noundef %[[ARG2:.*]], i64 noundef %[[ARG3:.*]]) +// CHECK: (i8* %[[BUFFER:.*]], i32 %[[ARG0:.*]], i64 %[[ARG1:.*]], i32 %[[ARG2:.*]], i64 %[[ARG3:.*]]) // CHECK: %[[BUFFER_ADDR:.*]] = alloca i8*, align 8 // CHECK: %[[ARG0_ADDR:.*]] = alloca i32, align 4 @@ -606,7 +606,7 @@ void test_builtin_os_log(void *buf, int i, const char *data) { // CHECK: store i64 %[[V3]], i64* %[[ARGDATACAST12]], align 1 // CHECK-LABEL: define{{.*}} void @test_builtin_os_log_wide -// CHECK: (i8* noundef %[[BUF:.*]], i8* noundef %[[DATA:.*]], i32* noundef %[[STR:.*]]) +// CHECK: (i8* %[[BUF:.*]], i8* %[[DATA:.*]], i32* %[[STR:.*]]) typedef int wchar_t; void test_builtin_os_log_wide(void *buf, const char *data, wchar_t *str) { volatile int len; @@ -625,13 +625,13 @@ void test_builtin_os_log_wide(void *buf, const char *data, wchar_t *str) { // CHECK: %[[V1:.*]] = load i8*, i8** %[[BUF_ADDR]], align 8 // CHECK: %[[V2:.*]] = load i32*, i32** %[[STR_ADDR]], align 8 // CHECK: %[[V3:.*]] = ptrtoint i32* %[[V2]] to i64 - // CHECK: call void @__os_log_helper_1_2_1_8_80(i8* noundef %[[V1]], i64 noundef %[[V3]]) + // CHECK: call void @__os_log_helper_1_2_1_8_80(i8* %[[V1]], i64 %[[V3]]) __builtin_os_log_format(buf, "%S", str); } // CHECK-LABEL: define linkonce_odr hidden void @__os_log_helper_1_2_1_8_80 -// CHECK: (i8* noundef %[[BUFFER:.*]], i64 noundef %[[ARG0:.*]]) +// CHECK: (i8* %[[BUFFER:.*]], i64 %[[ARG0:.*]]) // CHECK: %[[BUFFER_ADDR:.*]] = alloca i8*, align 8 // CHECK: %[[ARG0_ADDR:.*]] = alloca i64, align 8 @@ -652,7 +652,7 @@ void test_builtin_os_log_wide(void *buf, const char *data, wchar_t *str) { // CHECK: store i64 %[[V0]], i64* %[[ARGDATACAST]], align 1 // CHECK-LABEL: define{{.*}} void @test_builtin_os_log_precision_width -// CHECK: (i8* noundef %[[BUF:.*]], i8* noundef %[[DATA:.*]], i32 noundef %[[PRECISION:.*]], i32 noundef %[[WIDTH:.*]]) +// CHECK: (i8* %[[BUF:.*]], i8* %[[DATA:.*]], i32 %[[PRECISION:.*]], i32 %[[WIDTH:.*]]) void test_builtin_os_log_precision_width(void *buf, const char *data, int precision, int width) { volatile int len; @@ -674,12 +674,12 @@ void test_builtin_os_log_precision_width(void *buf, const char *data, // CHECK: %[[V3:.*]] = load i32, i32* %[[WIDTH_ADDR]], align 4 // CHECK: %[[V4:.*]] = load i8*, i8** %[[DATA_ADDR]], align 8 // CHECK: %[[V5:.*]] = ptrtoint i8* %[[V4]] to i64 - // CHECK: call void @__os_log_helper_1_2_3_4_0_4_16_8_32(i8* noundef %[[V1]], i32 noundef %[[V2]], i32 noundef %[[V3]], i64 noundef %[[V5]]) + // CHECK: call void @__os_log_helper_1_2_3_4_0_4_16_8_32(i8* %[[V1]], i32 %[[V2]], i32 %[[V3]], i64 %[[V5]]) __builtin_os_log_format(buf, "Hello %*.*s World", precision, width, data); } // CHECK-LABEL: define linkonce_odr hidden void @__os_log_helper_1_2_3_4_0_4_16_8_32 -// CHECK: (i8* noundef %[[BUFFER:.*]], i32 noundef %[[ARG0:.*]], i32 noundef %[[ARG1:.*]], i64 noundef %[[ARG2:.*]]) +// CHECK: (i8* %[[BUFFER:.*]], i32 %[[ARG0:.*]], i32 %[[ARG1:.*]], i64 %[[ARG2:.*]]) // CHECK: %[[BUFFER_ADDR:.*]] = alloca i8*, align 8 // CHECK: %[[ARG0_ADDR:.*]] = alloca i32, align 4 @@ -720,7 +720,7 @@ void test_builtin_os_log_precision_width(void *buf, const char *data, // CHECK: store i64 %[[V2]], i64* %[[ARGDATACAST8]], align 1 // CHECK-LABEL: define{{.*}} void @test_builtin_os_log_invalid -// CHECK: (i8* noundef %[[BUF:.*]], i32 noundef %[[DATA:.*]]) +// CHECK: (i8* %[[BUF:.*]], i32 %[[DATA:.*]]) void test_builtin_os_log_invalid(void *buf, int data) { volatile int len; // CHECK: %[[BUF_ADDR:.*]] = alloca i8*, align 8 @@ -734,13 +734,13 @@ void test_builtin_os_log_invalid(void *buf, int data) { // CHECK: %[[V1:.*]] = load i8*, i8** %[[BUF_ADDR]], align 8 // CHECK: %[[V2:.*]] = load i32, i32* %[[DATA_ADDR]], align 4 - // CHECK: call void @__os_log_helper_1_0_1_4_0(i8* noundef %[[V1]], i32 noundef %[[V2]]) + // CHECK: call void @__os_log_helper_1_0_1_4_0(i8* %[[V1]], i32 %[[V2]]) __builtin_os_log_format(buf, "invalid specifier %: %d even a trailing one%", data); } // CHECK-LABEL: define linkonce_odr hidden void @__os_log_helper_1_0_1_4_0 -// CHECK: (i8* noundef %[[BUFFER:.*]], i32 noundef %[[ARG0:.*]]) +// CHECK: (i8* %[[BUFFER:.*]], i32 %[[ARG0:.*]]) // CHECK: %[[BUFFER_ADDR:.*]] = alloca i8*, align 8 // CHECK: %[[ARG0_ADDR:.*]] = alloca i32, align 4 @@ -761,7 +761,7 @@ void test_builtin_os_log_invalid(void *buf, int data) { // CHECK: store i32 %[[V0]], i32* %[[ARGDATACAST]], align 1 // CHECK-LABEL: define{{.*}} void @test_builtin_os_log_percent -// CHECK: (i8* noundef %[[BUF:.*]], i8* noundef %[[DATA1:.*]], i8* noundef %[[DATA2:.*]]) +// CHECK: (i8* %[[BUF:.*]], i8* %[[DATA1:.*]], i8* %[[DATA2:.*]]) // Check that the %% which does not consume any argument is correctly handled void test_builtin_os_log_percent(void *buf, const char *data1, const char *data2) { volatile int len; @@ -781,13 +781,13 @@ void test_builtin_os_log_percent(void *buf, const char *data1, const char *data2 // CHECK: %[[V3:.*]] = ptrtoint i8* %[[V2]] to i64 // CHECK: %[[V4:.*]] = load i8*, i8** %[[DATA2_ADDR]], align 8 // CHECK: %[[V5:.*]] = ptrtoint i8* %[[V4]] to i64 - // CHECK: call void @__os_log_helper_1_2_2_8_32_8_32(i8* noundef %[[V1]], i64 noundef %[[V3]], i64 noundef %[[V5]]) + // CHECK: call void @__os_log_helper_1_2_2_8_32_8_32(i8* %[[V1]], i64 %[[V3]], i64 %[[V5]]) __builtin_os_log_format(buf, "%s %% %s", data1, data2); } // CHECK-LABEL: define linkonce_odr hidden void @__os_log_helper_1_2_2_8_32_8_32 -// CHECK: (i8* noundef %[[BUFFER:.*]], i64 noundef %[[ARG0:.*]], i64 noundef %[[ARG1:.*]]) +// CHECK: (i8* %[[BUFFER:.*]], i64 %[[ARG0:.*]], i64 %[[ARG1:.*]]) // CHECK: %[[BUFFER_ADDR:.*]] = alloca i8*, align 8 // CHECK: %[[ARG0_ADDR:.*]] = alloca i64, align 8 @@ -840,7 +840,7 @@ void test_builtin_os_log_errno() { // CHECK-NOT: @stacksave // CHECK: %[[BUF:.*]] = alloca [4 x i8], align 1 // CHECK: %[[DECAY:.*]] = getelementptr inbounds [4 x i8], [4 x i8]* %[[BUF]], i64 0, i64 0 - // CHECK: call void @__os_log_helper_1_2_1_0_96(i8* noundef %[[DECAY]]) + // CHECK: call void @__os_log_helper_1_2_1_0_96(i8* %[[DECAY]]) // CHECK-NOT: @stackrestore char buf[__builtin_os_log_format_buffer_size("%m")]; @@ -848,7 +848,7 @@ void test_builtin_os_log_errno() { } // CHECK-LABEL: define linkonce_odr hidden void @__os_log_helper_1_2_1_0_96 -// CHECK: (i8* noundef %[[BUFFER:.*]]) +// CHECK: (i8* %[[BUFFER:.*]]) // CHECK: %[[BUFFER_ADDR:.*]] = alloca i8*, align 8 // CHECK: store i8* %[[BUFFER]], i8** %[[BUFFER_ADDR]], align 8 @@ -864,7 +864,7 @@ void test_builtin_os_log_errno() { // CHECK-NEXT: ret void // CHECK-LABEL: define{{.*}} void @test_builtin_os_log_long_double -// CHECK: (i8* noundef %[[BUF:.*]], x86_fp80 noundef %[[LD:.*]]) +// CHECK: (i8* %[[BUF:.*]], x86_fp80 %[[LD:.*]]) void test_builtin_os_log_long_double(void *buf, long double ld) { // CHECK: %[[BUF_ADDR:.*]] = alloca i8*, align 8 // CHECK: %[[LD_ADDR:.*]] = alloca x86_fp80, align 16 @@ -881,13 +881,13 @@ void test_builtin_os_log_long_double(void *buf, long double ld) { // CHECK: %[[V6:.*]] = load i64, i64* %[[V5]], align 16 // CHECK: %[[V7:.*]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* %[[V4]], i32 0, i32 1 // CHECK: %[[V8:.*]] = load i64, i64* %[[V7]], align 8 - // CHECK: call void @__os_log_helper_1_0_1_16_0(i8* noundef %[[V0]], i64 noundef %[[V6]], i64 noundef %[[V8]]) + // CHECK: call void @__os_log_helper_1_0_1_16_0(i8* %[[V0]], i64 %[[V6]], i64 %[[V8]]) __builtin_os_log_format(buf, "%Lf", ld); } // CHECK-LABEL: define linkonce_odr hidden void @__os_log_helper_1_0_1_16_0 -// CHECK: (i8* noundef %[[BUFFER:.*]], i64 noundef %[[ARG0_COERCE0:.*]], i64 noundef %[[ARG0_COERCE1:.*]]) +// CHECK: (i8* %[[BUFFER:.*]], i64 %[[ARG0_COERCE0:.*]], i64 %[[ARG0_COERCE1:.*]]) // CHECK: %[[ARG0:.*]] = alloca i128, align 16 // CHECK: %[[BUFFER_ADDR:.*]] = alloca i8*, align 8 diff --git a/clang/test/CodeGen/c-strings.c b/clang/test/CodeGen/c-strings.c index d8277eb3357656d68ce956649f063a40e4a166d3..a94cd8920e067fa3aa4828f78de19ccc58672d84 100644 --- a/clang/test/CodeGen/c-strings.c +++ b/clang/test/CodeGen/c-strings.c @@ -40,7 +40,7 @@ void f1() { static char *x = "hello"; bar(x); // CHECK: [[T1:%.*]] = load i8*, i8** @f1.x - // CHECK: call {{.*}}void @bar(i8* noundef [[T1:%.*]]) + // CHECK: call {{.*}}void @bar(i8* [[T1:%.*]]) } // CHECK-LABEL: define {{.*}}void @f2() diff --git a/clang/test/CodeGen/c11atomics-ios.c b/clang/test/CodeGen/c11atomics-ios.c index b3d32f1c4a3d44e28c4808e6b546d2c82dc27e2f..0aac32e4c6154ba608edcca904e6599a4b11e680 100644 --- a/clang/test/CodeGen/c11atomics-ios.c +++ b/clang/test/CodeGen/c11atomics-ios.c @@ -203,7 +203,7 @@ void testPromotedStruct(_Atomic(PS) *fp) { } PS test_promoted_load(_Atomic(PS) *addr) { - // CHECK-LABEL: @test_promoted_load(%struct.PS* noalias sret(%struct.PS) align 2 %agg.result, { %struct.PS, [2 x i8] }* noundef %addr) + // CHECK-LABEL: @test_promoted_load(%struct.PS* noalias sret(%struct.PS) align 2 %agg.result, { %struct.PS, [2 x i8] }* %addr) // CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4 // CHECK: [[ATOMIC_RES:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8 // CHECK: store { %struct.PS, [2 x i8] }* %addr, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4 @@ -221,7 +221,7 @@ PS test_promoted_load(_Atomic(PS) *addr) { } void test_promoted_store(_Atomic(PS) *addr, PS *val) { - // CHECK-LABEL: @test_promoted_store({ %struct.PS, [2 x i8] }* noundef %addr, %struct.PS* noundef %val) + // CHECK-LABEL: @test_promoted_store({ %struct.PS, [2 x i8] }* %addr, %struct.PS* %val) // CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4 // CHECK: [[VAL_ARG:%.*]] = alloca %struct.PS*, align 4 // CHECK: [[NONATOMIC_TMP:%.*]] = alloca %struct.PS, align 2 @@ -245,7 +245,7 @@ void test_promoted_store(_Atomic(PS) *addr, PS *val) { } PS test_promoted_exchange(_Atomic(PS) *addr, PS *val) { - // CHECK-LABEL: @test_promoted_exchange(%struct.PS* noalias sret(%struct.PS) align 2 %agg.result, { %struct.PS, [2 x i8] }* noundef %addr, %struct.PS* noundef %val) + // CHECK-LABEL: @test_promoted_exchange(%struct.PS* noalias sret(%struct.PS) align 2 %agg.result, { %struct.PS, [2 x i8] }* %addr, %struct.PS* %val) // CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4 // CHECK: [[VAL_ARG:%.*]] = alloca %struct.PS*, align 4 // CHECK: [[NONATOMIC_TMP:%.*]] = alloca %struct.PS, align 2 @@ -275,7 +275,7 @@ PS test_promoted_exchange(_Atomic(PS) *addr, PS *val) { } _Bool test_promoted_cmpxchg(_Atomic(PS) *addr, PS *desired, PS *new) { - // CHECK: define{{.*}} zeroext i1 @test_promoted_cmpxchg({ %struct.PS, [2 x i8] }* noundef %addr, %struct.PS* noundef %desired, %struct.PS* noundef %new) #0 { + // CHECK: define{{.*}} zeroext i1 @test_promoted_cmpxchg({ %struct.PS, [2 x i8] }* %addr, %struct.PS* %desired, %struct.PS* %new) #0 { // CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4 // CHECK: [[DESIRED_ARG:%.*]] = alloca %struct.PS*, align 4 // CHECK: [[NEW_ARG:%.*]] = alloca %struct.PS*, align 4 diff --git a/clang/test/CodeGen/c11atomics.c b/clang/test/CodeGen/c11atomics.c index 3c6ca95784805acb5360d9689a94379485cd1ef2..92fdad3134a69206b4f1412c1d82f5ce93530dcc 100644 --- a/clang/test/CodeGen/c11atomics.c +++ b/clang/test/CodeGen/c11atomics.c @@ -73,7 +73,7 @@ void testinc(void) // CHECK: testdec void testdec(void) { - // CHECK: call arm_aapcscc zeroext i1 @__atomic_compare_exchange(i32 noundef 1, i8* noundef @b + // CHECK: call arm_aapcscc zeroext i1 @__atomic_compare_exchange(i32 1, i8* @b b--; // CHECK: atomicrmw sub i32* @i, i32 1 seq_cst, align 4 i--; @@ -81,7 +81,7 @@ void testdec(void) l--; // CHECK: atomicrmw sub i16* @s, i16 1 seq_cst, align 2 s--; - // CHECK: call arm_aapcscc zeroext i1 @__atomic_compare_exchange(i32 noundef 1, i8* noundef @b + // CHECK: call arm_aapcscc zeroext i1 @__atomic_compare_exchange(i32 1, i8* @b --b; // CHECK: atomicrmw sub i32* @i, i32 1 seq_cst, align 4 // CHECK: sub i32 @@ -96,7 +96,7 @@ void testdec(void) // CHECK: testaddeq void testaddeq(void) { - // CHECK: call arm_aapcscc zeroext i1 @__atomic_compare_exchange(i32 noundef 1, i8* noundef @b + // CHECK: call arm_aapcscc zeroext i1 @__atomic_compare_exchange(i32 1, i8* @b // CHECK: atomicrmw add i32* @i, i32 42 seq_cst, align 4 // CHECK: atomicrmw add i64* @l, i64 42 seq_cst, align 8 // CHECK: atomicrmw add i16* @s, i16 42 seq_cst, align 2 @@ -108,7 +108,7 @@ void testaddeq(void) // CHECK: testsubeq void testsubeq(void) { - // CHECK: call arm_aapcscc zeroext i1 @__atomic_compare_exchange(i32 noundef 1, i8* noundef @b + // CHECK: call arm_aapcscc zeroext i1 @__atomic_compare_exchange(i32 1, i8* @b // CHECK: atomicrmw sub i32* @i, i32 42 seq_cst, align 4 // CHECK: atomicrmw sub i64* @l, i64 42 seq_cst, align 8 // CHECK: atomicrmw sub i16* @s, i16 42 seq_cst, align 2 @@ -120,7 +120,7 @@ void testsubeq(void) // CHECK: testxoreq void testxoreq(void) { - // CHECK: call arm_aapcscc zeroext i1 @__atomic_compare_exchange(i32 noundef 1, i8* noundef @b + // CHECK: call arm_aapcscc zeroext i1 @__atomic_compare_exchange(i32 1, i8* @b // CHECK: atomicrmw xor i32* @i, i32 42 seq_cst, align 4 // CHECK: atomicrmw xor i64* @l, i64 42 seq_cst, align 8 // CHECK: atomicrmw xor i16* @s, i16 42 seq_cst, align 2 @@ -132,7 +132,7 @@ void testxoreq(void) // CHECK: testoreq void testoreq(void) { - // CHECK: call arm_aapcscc zeroext i1 @__atomic_compare_exchange(i32 noundef 1, i8* noundef @b + // CHECK: call arm_aapcscc zeroext i1 @__atomic_compare_exchange(i32 1, i8* @b // CHECK: atomicrmw or i32* @i, i32 42 seq_cst, align 4 // CHECK: atomicrmw or i64* @l, i64 42 seq_cst, align 8 // CHECK: atomicrmw or i16* @s, i16 42 seq_cst, align 2 @@ -144,7 +144,7 @@ void testoreq(void) // CHECK: testandeq void testandeq(void) { - // CHECK: call arm_aapcscc zeroext i1 @__atomic_compare_exchange(i32 noundef 1, i8* noundef @b + // CHECK: call arm_aapcscc zeroext i1 @__atomic_compare_exchange(i32 1, i8* @b // CHECK: atomicrmw and i32* @i, i32 42 seq_cst, align 4 // CHECK: atomicrmw and i64* @l, i64 42 seq_cst, align 8 // CHECK: atomicrmw and i16* @s, i16 42 seq_cst, align 2 @@ -173,7 +173,7 @@ void testFloat(_Atomic(float) *fp) { // CHECK-NEXT: [[T0:%.*]] = load float*, float** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast float* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast float* [[TMP0]] to i8* -// CHECK-NEXT: call arm_aapcscc void @__atomic_load(i32 noundef 4, i8* noundef [[T1]], i8* noundef [[T2]], i32 noundef 5) +// CHECK-NEXT: call arm_aapcscc void @__atomic_load(i32 4, i8* [[T1]], i8* [[T2]], i32 5) // CHECK-NEXT: [[T3:%.*]] = load float, float* [[TMP0]], align 4 // CHECK-NEXT: store float [[T3]], float* [[F]] float f = *fp; @@ -183,7 +183,7 @@ void testFloat(_Atomic(float) *fp) { // CHECK-NEXT: store float [[T0]], float* [[TMP1]], align 4 // CHECK-NEXT: [[T2:%.*]] = bitcast float* [[T1]] to i8* // CHECK-NEXT: [[T3:%.*]] = bitcast float* [[TMP1]] to i8* -// CHECK-NEXT: call arm_aapcscc void @__atomic_store(i32 noundef 4, i8* noundef [[T2]], i8* noundef [[T3]], i32 noundef 5) +// CHECK-NEXT: call arm_aapcscc void @__atomic_store(i32 4, i8* [[T2]], i8* [[T3]], i32 5) *fp = f; // CHECK-NEXT: ret void @@ -214,7 +214,7 @@ void testComplexFloat(_Atomic(_Complex float) *fp) { // CHECK-NEXT: [[T0:%.*]] = load [[CF]]*, [[CF]]** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast [[CF]]* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [[CF]]* [[TMP0]] to i8* -// CHECK-NEXT: call arm_aapcscc void @__atomic_load(i32 noundef 8, i8* noundef [[T1]], i8* noundef [[T2]], i32 noundef 5) +// CHECK-NEXT: call arm_aapcscc void @__atomic_load(i32 8, i8* [[T1]], i8* [[T2]], i32 5) // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[TMP0]], i32 0, i32 0 // CHECK-NEXT: [[R:%.*]] = load float, float* [[T0]] // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[TMP0]], i32 0, i32 1 @@ -236,7 +236,7 @@ void testComplexFloat(_Atomic(_Complex float) *fp) { // CHECK-NEXT: store float [[I]], float* [[T1]] // CHECK-NEXT: [[T0:%.*]] = bitcast [[CF]]* [[DEST]] to i8* // CHECK-NEXT: [[T1:%.*]] = bitcast [[CF]]* [[TMP1]] to i8* -// CHECK-NEXT: call arm_aapcscc void @__atomic_store(i32 noundef 8, i8* noundef [[T0]], i8* noundef [[T1]], i32 noundef 5) +// CHECK-NEXT: call arm_aapcscc void @__atomic_store(i32 8, i8* [[T0]], i8* [[T1]], i32 5) *fp = f; // CHECK-NEXT: ret void @@ -276,7 +276,7 @@ void testStruct(_Atomic(S) *fp) { // CHECK-NEXT: [[T0:%.*]] = load [[S]]*, [[S]]** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast [[S]]* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [[S]]* [[F]] to i8* -// CHECK-NEXT: call arm_aapcscc void @__atomic_load(i32 noundef 8, i8* noundef [[T1]], i8* noundef [[T2]], i32 noundef 5) +// CHECK-NEXT: call arm_aapcscc void @__atomic_load(i32 8, i8* [[T1]], i8* [[T2]], i32 5) S f = *fp; // CHECK-NEXT: [[T0:%.*]] = load [[S]]*, [[S]]** [[FP]] @@ -285,7 +285,7 @@ void testStruct(_Atomic(S) *fp) { // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[T1]], i8* align 2 [[T2]], i32 8, i1 false) // CHECK-NEXT: [[T3:%.*]] = bitcast [[S]]* [[T0]] to i8* // CHECK-NEXT: [[T4:%.*]] = bitcast [[S]]* [[TMP0]] to i8* -// CHECK-NEXT: call arm_aapcscc void @__atomic_store(i32 noundef 8, i8* noundef [[T3]], i8* noundef [[T4]], i32 noundef 5) +// CHECK-NEXT: call arm_aapcscc void @__atomic_store(i32 8, i8* [[T3]], i8* [[T4]], i32 5) *fp = f; // CHECK-NEXT: ret void @@ -331,7 +331,7 @@ void testPromotedStruct(_Atomic(PS) *fp) { // CHECK-NEXT: [[T0:%.*]] = load [[APS]]*, [[APS]]** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast [[APS]]* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [[APS]]* [[TMP0]] to i8* -// CHECK-NEXT: call arm_aapcscc void @__atomic_load(i32 noundef 8, i8* noundef [[T1]], i8* noundef [[T2]], i32 noundef 5) +// CHECK-NEXT: call arm_aapcscc void @__atomic_load(i32 8, i8* [[T1]], i8* [[T2]], i32 5) // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[TMP0]], i32 0, i32 0 // CHECK-NEXT: [[T1:%.*]] = bitcast [[PS]]* [[F]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [[PS]]* [[T0]] to i8* @@ -347,13 +347,13 @@ void testPromotedStruct(_Atomic(PS) *fp) { // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[T2]], i8* align 2 [[T3]], i32 6, i1 false) // CHECK-NEXT: [[T4:%.*]] = bitcast [[APS]]* [[T0]] to i8* // CHECK-NEXT: [[T5:%.*]] = bitcast [[APS]]* [[TMP1]] to i8* -// CHECK-NEXT: call arm_aapcscc void @__atomic_store(i32 noundef 8, i8* noundef [[T4]], i8* noundef [[T5]], i32 noundef 5) +// CHECK-NEXT: call arm_aapcscc void @__atomic_store(i32 8, i8* [[T4]], i8* [[T5]], i32 5) *fp = f; // CHECK-NEXT: [[T0:%.*]] = load [[APS]]*, [[APS]]** [[FP]], align 4 // CHECK-NEXT: [[T1:%.*]] = bitcast [[APS]]* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [[APS]]* [[TMP3]] to i8* -// CHECK-NEXT: call arm_aapcscc void @__atomic_load(i32 noundef 8, i8* noundef [[T1]], i8* noundef [[T2]], i32 noundef 5) +// CHECK-NEXT: call arm_aapcscc void @__atomic_load(i32 8, i8* [[T1]], i8* [[T2]], i32 5) // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[TMP3]], i32 0, i32 0 // CHECK-NEXT: [[T1:%.*]] = bitcast %struct.PS* [[TMP2]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast %struct.PS* [[T0]] to i8* @@ -368,7 +368,7 @@ void testPromotedStruct(_Atomic(PS) *fp) { } PS test_promoted_load(_Atomic(PS) *addr) { - // CHECK-LABEL: @test_promoted_load(%struct.PS* noalias sret(%struct.PS) align 2 %agg.result, { %struct.PS, [2 x i8] }* noundef %addr) + // CHECK-LABEL: @test_promoted_load(%struct.PS* noalias sret(%struct.PS) align 2 %agg.result, { %struct.PS, [2 x i8] }* %addr) // CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4 // CHECK: [[ATOMIC_RES:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8 // CHECK: store { %struct.PS, [2 x i8] }* %addr, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4 @@ -376,7 +376,7 @@ PS test_promoted_load(_Atomic(PS) *addr) { // CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64* // CHECK: [[ATOMIC_RES64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_RES]] to i64* // CHECK: [[ADDR8:%.*]] = bitcast i64* [[ADDR64]] to i8* - // CHECK: [[RES:%.*]] = call arm_aapcscc i64 @__atomic_load_8(i8* noundef [[ADDR8]], i32 noundef 5) + // CHECK: [[RES:%.*]] = call arm_aapcscc i64 @__atomic_load_8(i8* [[ADDR8]], i32 5) // CHECK: store i64 [[RES]], i64* [[ATOMIC_RES64]], align 8 // CHECK: [[ATOMIC_RES_STRUCT:%.*]] = bitcast i64* [[ATOMIC_RES64]] to %struct.PS* // CHECK: [[AGG_RESULT8:%.*]] = bitcast %struct.PS* %agg.result to i8* @@ -387,7 +387,7 @@ PS test_promoted_load(_Atomic(PS) *addr) { } void test_promoted_store(_Atomic(PS) *addr, PS *val) { - // CHECK-LABEL: @test_promoted_store({ %struct.PS, [2 x i8] }* noundef %addr, %struct.PS* noundef %val) + // CHECK-LABEL: @test_promoted_store({ %struct.PS, [2 x i8] }* %addr, %struct.PS* %val) // CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4 // CHECK: [[VAL_ARG:%.*]] = alloca %struct.PS*, align 4 // CHECK: [[NONATOMIC_TMP:%.*]] = alloca %struct.PS, align 2 @@ -406,12 +406,12 @@ void test_promoted_store(_Atomic(PS) *addr, PS *val) { // CHECK: [[ATOMIC_VAL64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i64* // CHECK: [[ADDR8:%.*]] = bitcast i64* [[ADDR64]] to i8* // CHECK: [[VAL64:%.*]] = load i64, i64* [[ATOMIC_VAL64]], align 2 - // CHECK: call arm_aapcscc void @__atomic_store_8(i8* noundef [[ADDR8]], i64 noundef [[VAL64]], i32 noundef 5) + // CHECK: call arm_aapcscc void @__atomic_store_8(i8* [[ADDR8]], i64 [[VAL64]], i32 5) __c11_atomic_store(addr, *val, 5); } PS test_promoted_exchange(_Atomic(PS) *addr, PS *val) { - // CHECK-LABEL: @test_promoted_exchange(%struct.PS* noalias sret(%struct.PS) align 2 %agg.result, { %struct.PS, [2 x i8] }* noundef %addr, %struct.PS* noundef %val) + // CHECK-LABEL: @test_promoted_exchange(%struct.PS* noalias sret(%struct.PS) align 2 %agg.result, { %struct.PS, [2 x i8] }* %addr, %struct.PS* %val) // CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4 // CHECK: [[VAL_ARG:%.*]] = alloca %struct.PS*, align 4 // CHECK: [[NONATOMIC_TMP:%.*]] = alloca %struct.PS, align 2 @@ -432,7 +432,7 @@ PS test_promoted_exchange(_Atomic(PS) *addr, PS *val) { // CHECK: [[ATOMIC_RES64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_RES]] to i64* // CHECK: [[ADDR8:%.*]] = bitcast i64* [[ADDR64]] to i8* // CHECK: [[VAL64:%.*]] = load i64, i64* [[ATOMIC_VAL64]], align 2 - // CHECK: [[RES:%.*]] = call arm_aapcscc i64 @__atomic_exchange_8(i8* noundef [[ADDR8]], i64 noundef [[VAL64]], i32 noundef 5) + // CHECK: [[RES:%.*]] = call arm_aapcscc i64 @__atomic_exchange_8(i8* [[ADDR8]], i64 [[VAL64]], i32 5) // CHECK: store i64 [[RES]], i64* [[ATOMIC_RES64]], align 8 // CHECK: [[ATOMIC_RES_STRUCT:%.*]] = bitcast i64* [[ATOMIC_RES64]] to %struct.PS* // CHECK: [[AGG_RESULT8:%.*]] = bitcast %struct.PS* %agg.result to i8* @@ -442,7 +442,7 @@ PS test_promoted_exchange(_Atomic(PS) *addr, PS *val) { } _Bool test_promoted_cmpxchg(_Atomic(PS) *addr, PS *desired, PS *new) { - // CHECK-LABEL: i1 @test_promoted_cmpxchg({ %struct.PS, [2 x i8] }* noundef %addr, %struct.PS* noundef %desired, %struct.PS* noundef %new) #0 { + // CHECK-LABEL: i1 @test_promoted_cmpxchg({ %struct.PS, [2 x i8] }* %addr, %struct.PS* %desired, %struct.PS* %new) #0 { // CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4 // CHECK: [[DESIRED_ARG:%.*]] = alloca %struct.PS*, align 4 // CHECK: [[NEW_ARG:%.*]] = alloca %struct.PS*, align 4 @@ -470,7 +470,7 @@ _Bool test_promoted_cmpxchg(_Atomic(PS) *addr, PS *desired, PS *new) { // CHECK: [[ADDR8:%.*]] = bitcast i64* [[ADDR64]] to i8* // CHECK: [[ATOMIC_DESIRED8:%.*]] = bitcast i64* [[ATOMIC_DESIRED64]] to i8* // CHECK: [[NEW64:%.*]] = load i64, i64* [[ATOMIC_NEW64]], align 2 - // CHECK: [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_compare_exchange_8(i8* noundef [[ADDR8]], i8* noundef [[ATOMIC_DESIRED8]], i64 noundef [[NEW64]], i32 noundef 5, i32 noundef 5) + // CHECK: [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_compare_exchange_8(i8* [[ADDR8]], i8* [[ATOMIC_DESIRED8]], i64 [[NEW64]], i32 5, i32 5) // CHECK: ret i1 [[RES]] return __c11_atomic_compare_exchange_strong(addr, desired, *new, 5, 5); } @@ -479,12 +479,12 @@ struct Empty {}; struct Empty test_empty_struct_load(_Atomic(struct Empty)* empty) { // CHECK-LABEL: @test_empty_struct_load( - // CHECK: call arm_aapcscc zeroext i8 @__atomic_load_1(i8* noundef %{{.*}}, i32 noundef 5) + // CHECK: call arm_aapcscc zeroext i8 @__atomic_load_1(i8* %{{.*}}, i32 5) return __c11_atomic_load(empty, 5); } void test_empty_struct_store(_Atomic(struct Empty)* empty, struct Empty value) { // CHECK-LABEL: @test_empty_struct_store( - // CHECK: call arm_aapcscc void @__atomic_store_1(i8* noundef %{{.*}}, i8 noundef zeroext %{{.*}}, i32 noundef 5) + // CHECK: call arm_aapcscc void @__atomic_store_1(i8* %{{.*}}, i8 zeroext %{{.*}}, i32 5) __c11_atomic_store(empty, value, 5); } diff --git a/clang/test/CodeGen/callback_annotated.c b/clang/test/CodeGen/callback_annotated.c index 83a79c3491dafbafeafb6d9857ae52ac0c6b12fe..7b69a4de3897d201039c2533ea7a90cc8b79dc2b 100644 --- a/clang/test/CodeGen/callback_annotated.c +++ b/clang/test/CodeGen/callback_annotated.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple i386-unknown-unknown -fopenmp -fno-experimental-new-pass-manager %s -emit-llvm -o - -disable-llvm-optzns | FileCheck %s --check-prefix=RUN1 +// RUN: %clang_cc1 -triple i386-unknown-unknown -fopenmp %s -emit-llvm -o - -disable-llvm-optzns | FileCheck %s --check-prefix=RUN1 // RUN1-DAG: @broker0({{[^#]*#[0-9]+}} !callback ![[cid0:[0-9]+]] __attribute__((callback(1, 2))) void *broker0(void *(*callee)(void *), void *payload) { diff --git a/clang/test/CodeGen/calling-conv-ignored.c b/clang/test/CodeGen/calling-conv-ignored.c index 15801633a0338f30b1bdc68fecec8833f75a4ff2..e49d4c4b0d704ada1cbcd8f9c1e3e0403fcc5d56 100644 --- a/clang/test/CodeGen/calling-conv-ignored.c +++ b/clang/test/CodeGen/calling-conv-ignored.c @@ -16,30 +16,30 @@ void __cdecl bar() { } // X86-LABEL: define dso_local void @bar() -// X86: call void @foo_default(i8* noundef null, i8* noundef null) -// X86: call x86_stdcallcc void @"\01_foo_std@8"(i8* noundef null, i8* noundef null) -// X86: call x86_fastcallcc void @"\01@foo_fast@8"(i8* inreg noundef null, i8* inreg noundef null) -// X86: call x86_vectorcallcc void @"\01foo_vector@@8"(i8* inreg noundef null, i8* inreg noundef null) +// X86: call void @foo_default(i8* null, i8* null) +// X86: call x86_stdcallcc void @"\01_foo_std@8"(i8* null, i8* null) +// X86: call x86_fastcallcc void @"\01@foo_fast@8"(i8* inreg null, i8* inreg null) +// X86: call x86_vectorcallcc void @"\01foo_vector@@8"(i8* inreg null, i8* inreg null) // X86: ret void // X64-LABEL: define dso_local void @bar() -// X64: call void @foo_default(i8* noundef null, i8* noundef null) -// X64: call void @foo_std(i8* noundef null, i8* noundef null) -// X64: call void @foo_fast(i8* noundef null, i8* noundef null) -// X64: call x86_vectorcallcc void @"\01foo_vector@@16"(i8* noundef null, i8* noundef null) +// X64: call void @foo_default(i8* null, i8* null) +// X64: call void @foo_std(i8* null, i8* null) +// X64: call void @foo_fast(i8* null, i8* null) +// X64: call x86_vectorcallcc void @"\01foo_vector@@16"(i8* null, i8* null) // X64: ret void // X86-VEC-LABEL: define dso_local void @bar() -// X86-VEC: call x86_vectorcallcc void @"\01foo_default@@8"(i8* inreg noundef null, i8* inreg noundef null) -// X86-VEC: call x86_stdcallcc void @"\01_foo_std@8"(i8* noundef null, i8* noundef null) -// X86-VEC: call x86_fastcallcc void @"\01@foo_fast@8"(i8* inreg noundef null, i8* inreg noundef null) -// X86-VEC: call x86_vectorcallcc void @"\01foo_vector@@8"(i8* inreg noundef null, i8* inreg noundef null) +// X86-VEC: call x86_vectorcallcc void @"\01foo_default@@8"(i8* inreg null, i8* inreg null) +// X86-VEC: call x86_stdcallcc void @"\01_foo_std@8"(i8* null, i8* null) +// X86-VEC: call x86_fastcallcc void @"\01@foo_fast@8"(i8* inreg null, i8* inreg null) +// X86-VEC: call x86_vectorcallcc void @"\01foo_vector@@8"(i8* inreg null, i8* inreg null) // X86-VEC: ret void // X64-VEC-LABEL: define dso_local void @bar() -// X64-VEC: call x86_vectorcallcc void @"\01foo_default@@16"(i8* noundef null, i8* noundef null) -// X64-VEC: call void @foo_std(i8* noundef null, i8* noundef null) -// X64-VEC: call void @foo_fast(i8* noundef null, i8* noundef null) -// X64-VEC: call x86_vectorcallcc void @"\01foo_vector@@16"(i8* noundef null, i8* noundef null) +// X64-VEC: call x86_vectorcallcc void @"\01foo_default@@16"(i8* null, i8* null) +// X64-VEC: call void @foo_std(i8* null, i8* null) +// X64-VEC: call void @foo_fast(i8* null, i8* null) +// X64-VEC: call x86_vectorcallcc void @"\01foo_vector@@16"(i8* null, i8* null) // X64-VEC: ret void diff --git a/clang/test/CodeGen/catch-alignment-assumption-attribute-align_value-on-lvalue.cpp b/clang/test/CodeGen/catch-alignment-assumption-attribute-align_value-on-lvalue.cpp index e700adbbb56d625b6e23373b80d18cfd6a82df2e..a68d3e2aba6e6d8cb7a3afb82e576f336011f652 100644 --- a/clang/test/CodeGen/catch-alignment-assumption-attribute-align_value-on-lvalue.cpp +++ b/clang/test/CodeGen/catch-alignment-assumption-attribute-align_value-on-lvalue.cpp @@ -14,7 +14,7 @@ struct ac_struct { // CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_ALIGNMENT_ASSUMPTION:.*]] = {{.*}}, i32 100, i32 13 }, {{.*}}* @[[ALIGNED_CHAR]] } char **load_from_ac_struct(struct ac_struct *x) { - // CHECK: define{{.*}} i8** @{{.*}}(%[[STRUCT_AC_STRUCT]]* noundef %[[X:.*]]) + // CHECK: define{{.*}} i8** @{{.*}}(%[[STRUCT_AC_STRUCT]]* %[[X:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[STRUCT_AC_STRUCT_ADDR:.*]] = alloca %[[STRUCT_AC_STRUCT]]*, align 8 // CHECK-NEXT: store %[[STRUCT_AC_STRUCT]]* %[[X]], %[[STRUCT_AC_STRUCT]]** %[[STRUCT_AC_STRUCT_ADDR]], align 8 diff --git a/clang/test/CodeGen/catch-alignment-assumption-attribute-align_value-on-paramvar.cpp b/clang/test/CodeGen/catch-alignment-assumption-attribute-align_value-on-paramvar.cpp index 65d161012f4a4ba794883f933e408f9d4d02422e..a53544c48e4c72e3dfd6543a1d12c988a95eb385 100644 --- a/clang/test/CodeGen/catch-alignment-assumption-attribute-align_value-on-paramvar.cpp +++ b/clang/test/CodeGen/catch-alignment-assumption-attribute-align_value-on-paramvar.cpp @@ -7,8 +7,8 @@ // CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_ALIGNMENT_ASSUMPTION:.*]] = {{.*}}, i32 100, i32 10 }, {{.*}}* @[[CHAR]] } char **passthrough(__attribute__((align_value(0x100000000))) char **x) { - // CHECK-NOSANITIZE: define{{.*}} i8** @{{.*}}(i8** noundef align 4294967296 %[[X:.*]]) - // CHECK-SANITIZE: define{{.*}} i8** @{{.*}}(i8** noundef %[[X:.*]]) + // CHECK-NOSANITIZE: define{{.*}} i8** @{{.*}}(i8** align 4294967296 %[[X:.*]]) + // CHECK-SANITIZE: define{{.*}} i8** @{{.*}}(i8** %[[X:.*]]) // CHECK-NEXT: [[entry:.*]]: // CHECK-NEXT: %[[X_ADDR:.*]] = alloca i8**, align 8 // CHECK-NEXT: store i8** %[[X]], i8*** %[[X_ADDR]], align 8 diff --git a/clang/test/CodeGen/catch-alignment-assumption-attribute-alloc_align-on-function-variable.cpp b/clang/test/CodeGen/catch-alignment-assumption-attribute-alloc_align-on-function-variable.cpp index 0b7d8589dc75dfb0c27c09fa88d2c4adde5ca6d2..3d39b59b85a866ee7be386464fa536871e3109d5 100644 --- a/clang/test/CodeGen/catch-alignment-assumption-attribute-alloc_align-on-function-variable.cpp +++ b/clang/test/CodeGen/catch-alignment-assumption-attribute-alloc_align-on-function-variable.cpp @@ -8,7 +8,7 @@ char **__attribute__((alloc_align(2))) passthrough(char **x, unsigned long alignment) { - // CHECK: define{{.*}} i8** @[[PASSTHROUGH:.*]](i8** noundef %[[X:.*]], i64 noundef %[[ALIGNMENT:.*]]) + // CHECK: define{{.*}} i8** @[[PASSTHROUGH:.*]](i8** %[[X:.*]], i64 %[[ALIGNMENT:.*]]) // CHECK-NEXT: entry: // CHECK-NEXT: %[[X_ADDR:.*]] = alloca i8**, align 8 // CHECK-NEXT: %[[ALIGNMENT_ADDR:.*]] = alloca i64, align 8 @@ -21,7 +21,7 @@ passthrough(char **x, unsigned long alignment) { } char **caller(char **x, unsigned long alignment) { - // CHECK: define{{.*}} i8** @{{.*}}(i8** noundef %[[X:.*]], i64 noundef %[[ALIGNMENT:.*]]) + // CHECK: define{{.*}} i8** @{{.*}}(i8** %[[X:.*]], i64 %[[ALIGNMENT:.*]]) // CHECK-NEXT: entry: // CHECK-NEXT: %[[X_ADDR:.*]] = alloca i8**, align 8 // CHECK-NEXT: %[[ALIGNMENT_ADDR:.*]] = alloca i64, align 8 @@ -29,7 +29,7 @@ char **caller(char **x, unsigned long alignment) { // CHECK-NEXT: store i64 %[[ALIGNMENT]], i64* %[[ALIGNMENT_ADDR]], align 8 // CHECK-NEXT: %[[X_RELOADED:.*]] = load i8**, i8*** %[[X_ADDR]], align 8 // CHECK-NEXT: %[[ALIGNMENT_RELOADED:.*]] = load i64, i64* %[[ALIGNMENT_ADDR]], align 8 - // CHECK-NEXT: %[[X_RETURNED:.*]] = call noundef i8** @[[PASSTHROUGH]](i8** noundef %[[X_RELOADED]], i64 noundef %[[ALIGNMENT_RELOADED]]) + // CHECK-NEXT: %[[X_RETURNED:.*]] = call i8** @[[PASSTHROUGH]](i8** %[[X_RELOADED]], i64 %[[ALIGNMENT_RELOADED]]) // CHECK-SANITIZE-NEXT: %[[PTRINT:.*]] = ptrtoint i8** %[[X_RETURNED]] to i64 // CHECK-SANITIZE-NEXT: %[[MASK:.*]] = sub i64 %[[ALIGNMENT_RELOADED]], 1 // CHECK-SANITIZE-NEXT: %[[MASKEDPTR:.*]] = and i64 %[[PTRINT]], %[[MASK]] diff --git a/clang/test/CodeGen/catch-alignment-assumption-attribute-alloc_align-on-function.cpp b/clang/test/CodeGen/catch-alignment-assumption-attribute-alloc_align-on-function.cpp index 467bc043c3fe4066b631277d8c769077b206af25..d7b27e2961512479946b634e90d251c5e802d7ce 100644 --- a/clang/test/CodeGen/catch-alignment-assumption-attribute-alloc_align-on-function.cpp +++ b/clang/test/CodeGen/catch-alignment-assumption-attribute-alloc_align-on-function.cpp @@ -8,7 +8,7 @@ char **__attribute__((alloc_align(2))) passthrough(char **x, unsigned long alignment) { - // CHECK: define{{.*}} i8** @[[PASSTHROUGH:.*]](i8** noundef %[[X:.*]], i64 noundef %[[ALIGNMENT:.*]]) + // CHECK: define{{.*}} i8** @[[PASSTHROUGH:.*]](i8** %[[X:.*]], i64 %[[ALIGNMENT:.*]]) // CHECK-NEXT: entry: // CHECK-NEXT: %[[X_ADDR:.*]] = alloca i8**, align 8 // CHECK-NEXT: %[[ALIGNMENT_ADDR:.*]] = alloca i64, align 8 @@ -21,13 +21,13 @@ passthrough(char **x, unsigned long alignment) { } char **caller(char **x) { - // CHECK: define{{.*}} i8** @{{.*}}(i8** noundef %[[X:.*]]) + // CHECK: define{{.*}} i8** @{{.*}}(i8** %[[X:.*]]) // CHECK-NEXT: entry: // CHECK-NEXT: %[[X_ADDR:.*]] = alloca i8**, align 8 // CHECK-NEXT: store i8** %[[X]], i8*** %[[X_ADDR]], align 8 // CHECK-NEXT: %[[X_RELOADED:.*]] = load i8**, i8*** %[[X_ADDR]], align 8 - // CHECK-NOSANITIZE-NEXT: %[[X_RETURNED:.*]] = call noundef align 128 i8** @[[PASSTHROUGH]](i8** noundef %[[X_RELOADED]], i64 noundef 128) - // CHECK-SANITIZE-NEXT: %[[X_RETURNED:.*]] = call noundef i8** @[[PASSTHROUGH]](i8** noundef %[[X_RELOADED]], i64 noundef 128) + // CHECK-NOSANITIZE-NEXT: %[[X_RETURNED:.*]] = call align 128 i8** @[[PASSTHROUGH]](i8** %[[X_RELOADED]], i64 128) + // CHECK-SANITIZE-NEXT: %[[X_RETURNED:.*]] = call i8** @[[PASSTHROUGH]](i8** %[[X_RELOADED]], i64 128) // CHECK-SANITIZE-NEXT: %[[PTRINT:.*]] = ptrtoint i8** %[[X_RETURNED]] to i64 // CHECK-SANITIZE-NEXT: %[[MASKEDPTR:.*]] = and i64 %[[PTRINT]], 127 // CHECK-SANITIZE-NEXT: %[[MASKCOND:.*]] = icmp eq i64 %[[MASKEDPTR]], 0 diff --git a/clang/test/CodeGen/catch-alignment-assumption-attribute-assume_aligned-on-function-two-params.cpp b/clang/test/CodeGen/catch-alignment-assumption-attribute-assume_aligned-on-function-two-params.cpp index 055d46c5633ac852e09eb07ae3f3f2a9988e1f1f..fcf6430dc83866cfebdd505f23e084d68bffaaec 100644 --- a/clang/test/CodeGen/catch-alignment-assumption-attribute-assume_aligned-on-function-two-params.cpp +++ b/clang/test/CodeGen/catch-alignment-assumption-attribute-assume_aligned-on-function-two-params.cpp @@ -7,7 +7,7 @@ // CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_ALIGNMENT_ASSUMPTION:.*]] = {{.*}}, i32 100, i32 10 }, {{.*}}* @[[CHAR]] } char **__attribute__((assume_aligned(0x100000000, 42))) passthrough(char **x) { - // CHECK: define{{.*}} i8** @[[PASSTHROUGH:.*]](i8** noundef %[[X:.*]]) + // CHECK: define{{.*}} i8** @[[PASSTHROUGH:.*]](i8** %[[X:.*]]) // CHECK-NEXT: entry: // CHECK-NEXT: %[[X_ADDR:.*]] = alloca i8**, align 8 // CHECK-NEXT: store i8** %[[X]], i8*** %[[X_ADDR]], align 8 @@ -18,12 +18,12 @@ char **__attribute__((assume_aligned(0x100000000, 42))) passthrough(char **x) { } char **caller(char **x) { - // CHECK: define{{.*}} i8** @{{.*}}(i8** noundef %[[X:.*]]) + // CHECK: define{{.*}} i8** @{{.*}}(i8** %[[X:.*]]) // CHECK-NEXT: entry: // CHECK-NEXT: %[[X_ADDR:.*]] = alloca i8**, align 8 // CHECK-NEXT: store i8** %[[X]], i8*** %[[X_ADDR]], align 8 // CHECK-NEXT: %[[X_RELOADED:.*]] = load i8**, i8*** %[[X_ADDR]], align 8 - // CHECK-NEXT: %[[X_RETURNED:.*]] = call noundef i8** @[[PASSTHROUGH]](i8** noundef %[[X_RELOADED]]) + // CHECK-NEXT: %[[X_RETURNED:.*]] = call i8** @[[PASSTHROUGH]](i8** %[[X_RELOADED]]) // CHECK-SANITIZE-NEXT: %[[PTRINT:.*]] = ptrtoint i8** %[[X_RETURNED]] to i64 // CHECK-SANITIZE-NEXT: %[[OFFSETPTR:.*]] = sub i64 %[[PTRINT]], 42 // CHECK-SANITIZE-NEXT: %[[MASKEDPTR:.*]] = and i64 %[[OFFSETPTR]], 4294967295 diff --git a/clang/test/CodeGen/catch-alignment-assumption-attribute-assume_aligned-on-function.cpp b/clang/test/CodeGen/catch-alignment-assumption-attribute-assume_aligned-on-function.cpp index 5b15c55971ad9ed1d0d4f7d76898db974a2365ad..e3cd84d7133dd363bcbb9c5cd55ec5730ff97174 100644 --- a/clang/test/CodeGen/catch-alignment-assumption-attribute-assume_aligned-on-function.cpp +++ b/clang/test/CodeGen/catch-alignment-assumption-attribute-assume_aligned-on-function.cpp @@ -7,7 +7,7 @@ // CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_ALIGNMENT_ASSUMPTION:.*]] = {{.*}}, i32 100, i32 10 }, {{.*}}* @[[CHAR]] } char **__attribute__((assume_aligned(128))) passthrough(char **x) { - // CHECK: define{{.*}} i8** @[[PASSTHROUGH:.*]](i8** noundef %[[X:.*]]) + // CHECK: define{{.*}} i8** @[[PASSTHROUGH:.*]](i8** %[[X:.*]]) // CHECK-NEXT: entry: // CHECK-NEXT: %[[X_ADDR:.*]] = alloca i8**, align 8 // CHECK-NEXT: store i8** %[[X]], i8*** %[[X_ADDR]], align 8 @@ -18,13 +18,13 @@ char **__attribute__((assume_aligned(128))) passthrough(char **x) { } char **caller(char **x) { - // CHECK: define{{.*}} i8** @{{.*}}(i8** noundef %[[X]]) + // CHECK: define{{.*}} i8** @{{.*}}(i8** %[[X]]) // CHECK-NEXT: entry: // CHECK-NEXT: %[[X_ADDR]] = alloca i8**, align 8 // CHECK-NEXT: store i8** %[[X]], i8*** %[[X_ADDR]], align 8 // CHECK-NEXT: %[[X_RELOADED:.*]] = load i8**, i8*** %[[X_ADDR]], align 8 - // CHECK-NOSANITIZE-NEXT: %[[X_RETURNED:.*]] = call noundef align 128 i8** @[[PASSTHROUGH]](i8** noundef %[[X_RELOADED]]) - // CHECK-SANITIZE-NEXT: %[[X_RETURNED:.*]] = call noundef i8** @[[PASSTHROUGH]](i8** noundef %[[X_RELOADED]]) + // CHECK-NOSANITIZE-NEXT: %[[X_RETURNED:.*]] = call align 128 i8** @[[PASSTHROUGH]](i8** %[[X_RELOADED]]) + // CHECK-SANITIZE-NEXT: %[[X_RETURNED:.*]] = call i8** @[[PASSTHROUGH]](i8** %[[X_RELOADED]]) // CHECK-SANITIZE-NEXT: %[[PTRINT:.*]] = ptrtoint i8** %[[X_RETURNED]] to i64 // CHECK-SANITIZE-NEXT: %[[MASKEDPTR:.*]] = and i64 %[[PTRINT]], 127 // CHECK-SANITIZE-NEXT: %[[MASKCOND:.*]] = icmp eq i64 %[[MASKEDPTR]], 0 diff --git a/clang/test/CodeGen/catch-alignment-assumption-builtin_assume_aligned-three-params-variable.cpp b/clang/test/CodeGen/catch-alignment-assumption-builtin_assume_aligned-three-params-variable.cpp index c242b83c3aa87482be6cfee5a1487e820b5b9e88..17db95572c8a4f396db499991a8bcc3ff8ee7e91 100644 --- a/clang/test/CodeGen/catch-alignment-assumption-builtin_assume_aligned-three-params-variable.cpp +++ b/clang/test/CodeGen/catch-alignment-assumption-builtin_assume_aligned-three-params-variable.cpp @@ -7,7 +7,7 @@ // CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_ALIGNMENT_ASSUMPTION:.*]] = {{.*}}, i32 100, i32 35 }, {{.*}}* @[[CHAR]] } void *caller(char **x, unsigned long offset) { - // CHECK: define{{.*}} i8* @{{.*}}(i8** noundef %[[X:.*]], i64 noundef %[[OFFSET:.*]]) + // CHECK: define{{.*}} i8* @{{.*}}(i8** %[[X:.*]], i64 %[[OFFSET:.*]]) // CHECK-NEXT: entry: // CHECK-NEXT: %[[X_ADDR:.*]] = alloca i8**, align 8 // CHECK-NEXT: %[[OFFSET_ADDR:.*]] = alloca i64, align 8 diff --git a/clang/test/CodeGen/catch-alignment-assumption-builtin_assume_aligned-three-params.cpp b/clang/test/CodeGen/catch-alignment-assumption-builtin_assume_aligned-three-params.cpp index 6ce18034b409837c46014d3fb267a5499c517f2c..6b6b389ae337558ef2c24b086b82280e5cc26285 100644 --- a/clang/test/CodeGen/catch-alignment-assumption-builtin_assume_aligned-three-params.cpp +++ b/clang/test/CodeGen/catch-alignment-assumption-builtin_assume_aligned-three-params.cpp @@ -7,7 +7,7 @@ // CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_ALIGNMENT_ASSUMPTION:.*]] = {{.*}}, i32 100, i32 35 }, {{.*}}* @[[CHAR]] } void *caller(char **x) { - // CHECK: define{{.*}} i8* @{{.*}}(i8** noundef %[[X:.*]]) + // CHECK: define{{.*}} i8* @{{.*}}(i8** %[[X:.*]]) // CHECK-NEXT: entry: // CHECK-NEXT: %[[X_ADDR:.*]] = alloca i8**, align 8 // CHECK-NEXT: store i8** %[[X]], i8*** %[[X_ADDR]], align 8 diff --git a/clang/test/CodeGen/catch-alignment-assumption-builtin_assume_aligned-two-params.cpp b/clang/test/CodeGen/catch-alignment-assumption-builtin_assume_aligned-two-params.cpp index 0775fb1993c1a197446e4f2542afc4f39d8eb563..0cf836174ff865e0aaa73186f5069dcff83299b3 100644 --- a/clang/test/CodeGen/catch-alignment-assumption-builtin_assume_aligned-two-params.cpp +++ b/clang/test/CodeGen/catch-alignment-assumption-builtin_assume_aligned-two-params.cpp @@ -7,7 +7,7 @@ // CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_ALIGNMENT_ASSUMPTION:.*]] = {{.*}}, i32 100, i32 35 }, {{.*}}* @[[CHAR]] } void *caller(char **x) { - // CHECK: define{{.*}} i8* @{{.*}}(i8** noundef %[[X:.*]]) + // CHECK: define{{.*}} i8* @{{.*}}(i8** %[[X:.*]]) // CHECK-NEXT: entry: // CHECK-NEXT: %[[X_ADDR:.*]] = alloca i8**, align 8 // CHECK-NEXT: store i8** %[[X]], i8*** %[[X_ADDR]], align 8 diff --git a/clang/test/CodeGen/catch-alignment-assumption-openmp.cpp b/clang/test/CodeGen/catch-alignment-assumption-openmp.cpp index 6a06c0c83a48368bdd03d2fbe6f71915ca9b8df1..e6a1434d07914dc009a0fc176844853359f68865 100644 --- a/clang/test/CodeGen/catch-alignment-assumption-openmp.cpp +++ b/clang/test/CodeGen/catch-alignment-assumption-openmp.cpp @@ -7,7 +7,7 @@ // CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_ALIGNMENT_ASSUMPTION:.*]] = {{.*}}, i32 100, i32 30 }, {{.*}}* @[[CHAR]] } void func(char *data) { - // CHECK: define{{.*}} void @{{.*}}(i8* noundef %[[DATA:.*]]) + // CHECK: define{{.*}} void @{{.*}}(i8* %[[DATA:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[DATA_ADDR:.*]] = alloca i8*, align 8 // CHECK: store i8* %[[DATA]], i8** %[[DATA_ADDR]], align 8 diff --git a/clang/test/CodeGen/catch-implicit-integer-sign-changes.c b/clang/test/CodeGen/catch-implicit-integer-sign-changes.c index 6ad16ae91628f64173e1955aa638aecaaaa6d5d5..eca79718a4889304abe44a4972ea4ea411b1936c 100644 --- a/clang/test/CodeGen/catch-implicit-integer-sign-changes.c +++ b/clang/test/CodeGen/catch-implicit-integer-sign-changes.c @@ -27,7 +27,7 @@ // These 3 result (after optimizations) in simple 'icmp sge i32 %src, 0'. // CHECK-LABEL: @unsigned_int_to_signed_int -// CHECK-SAME: i32 noundef %[[SRC:.*]]) +// CHECK-SAME: (i32 %[[SRC:.*]]) signed int unsigned_int_to_signed_int(unsigned int src) { // CHECK: %[[SRC_ADDR:.*]] = alloca i32 // CHECK-NEXT: store i32 %[[SRC]], i32* %[[SRC_ADDR]] @@ -50,7 +50,7 @@ signed int unsigned_int_to_signed_int(unsigned int src) { } // CHECK-LABEL: @signed_int_to_unsigned_int -// CHECK-SAME: i32 noundef %[[SRC:.*]]) +// CHECK-SAME: (i32 %[[SRC:.*]]) unsigned int signed_int_to_unsigned_int(signed int src) { // CHECK: %[[SRC_ADDR:.*]] = alloca i32 // CHECK-NEXT: store i32 %[[SRC]], i32* %[[SRC_ADDR]] @@ -73,7 +73,7 @@ unsigned int signed_int_to_unsigned_int(signed int src) { } // CHECK-LABEL: @signed_int_to_unsigned_char -// CHECK-SAME: i32 noundef %[[SRC:.*]]) +// CHECK-SAME: (i32 %[[SRC:.*]]) unsigned char signed_int_to_unsigned_char(signed int src) { // CHECK: %[[SRC_ADDR:.*]] = alloca i32 // CHECK-NEXT: store i32 %[[SRC]], i32* %[[SRC_ADDR]] @@ -99,7 +99,7 @@ unsigned char signed_int_to_unsigned_char(signed int src) { // These 3 result (after optimizations) in simple 'icmp sge i8 %src, 0' // CHECK-LABEL: @signed_char_to_unsigned_char -// CHECK-SAME: (i8 noundef signext %[[SRC:.*]]) +// CHECK-SAME: (i8 signext %[[SRC:.*]]) unsigned char signed_char_to_unsigned_char(signed char src) { // CHECK: %[[SRC_ADDR:.*]] = alloca i8 // CHECK-NEXT: store i8 %[[SRC]], i8* %[[SRC_ADDR]] @@ -122,7 +122,7 @@ unsigned char signed_char_to_unsigned_char(signed char src) { } // CHECK-LABEL: @unsigned_char_to_signed_char -// CHECK-SAME: (i8 noundef zeroext %[[SRC:.*]]) +// CHECK-SAME: (i8 zeroext %[[SRC:.*]]) signed char unsigned_char_to_signed_char(unsigned char src) { // CHECK: %[[SRC_ADDR:.*]] = alloca i8 // CHECK-NEXT: store i8 %[[SRC]], i8* %[[SRC_ADDR]] @@ -145,7 +145,7 @@ signed char unsigned_char_to_signed_char(unsigned char src) { } // CHECK-LABEL: @signed_char_to_unsigned_int -// CHECK-SAME: (i8 noundef signext %[[SRC:.*]]) +// CHECK-SAME: (i8 signext %[[SRC:.*]]) unsigned int signed_char_to_unsigned_int(signed char src) { // CHECK: %[[SRC_ADDR:.*]] = alloca i8 // CHECK-NEXT: store i8 %[[SRC]], i8* %[[SRC_ADDR]] @@ -171,7 +171,7 @@ unsigned int signed_char_to_unsigned_int(signed char src) { // This one result (after optimizations) in 'icmp sge i8 (trunc i32 %src), 0' // CHECK-LABEL: @unsigned_int_to_signed_char -// CHECK-SAME: i32 noundef %[[SRC:.*]]) +// CHECK-SAME: (i32 %[[SRC:.*]]) signed char unsigned_int_to_signed_char(unsigned int src) { // CHECK: %[[SRC_ADDR:.*]] = alloca i32 // CHECK-NEXT: store i32 %[[SRC]], i32* %[[SRC_ADDR]] @@ -197,7 +197,7 @@ signed char unsigned_int_to_signed_char(unsigned int src) { // The worst one: 'xor i1 (icmp sge i8 (trunc i32 %x), 0), (icmp sge i32 %x, 0)' // CHECK-LABEL: @signed_int_to_signed_char -// CHECK-SAME: i32 noundef %[[SRC:.*]]) +// CHECK-SAME: (i32 %[[SRC:.*]]) signed char signed_int_to_signed_char(signed int x) { // CHECK: %[[SRC_ADDR:.*]] = alloca i32 // CHECK-NEXT: store i32 %[[SRC]], i32* %[[SRC_ADDR]] @@ -229,7 +229,7 @@ typedef unsigned int uint32_t; typedef signed int int32_t; // CHECK-LABEL: @uint32_t_to_int32_t -// CHECK-SAME: i32 noundef %[[SRC:.*]]) +// CHECK-SAME: (i32 %[[SRC:.*]]) int32_t uint32_t_to_int32_t(uint32_t src) { // CHECK: %[[SRC_ADDR:.*]] = alloca i32 // CHECK-NEXT: store i32 %[[SRC]], i32* %[[SRC_ADDR]] diff --git a/clang/test/CodeGen/catch-implicit-signed-integer-truncation-or-sign-change.c b/clang/test/CodeGen/catch-implicit-signed-integer-truncation-or-sign-change.c index a94dd2adf3a02a75c2bc79e1d4060e9cce6d4a3e..d2df707f2eccf756c2f53c8890128c7ac13b57dd 100644 --- a/clang/test/CodeGen/catch-implicit-signed-integer-truncation-or-sign-change.c +++ b/clang/test/CodeGen/catch-implicit-signed-integer-truncation-or-sign-change.c @@ -15,7 +15,7 @@ //============================================================================// // CHECK-LABEL: @unsigned_int_to_signed_char -// CHECK-SAME: i32 noundef %[[SRC:.*]]) +// CHECK-SAME: (i32 %[[SRC:.*]]) signed char unsigned_int_to_signed_char(unsigned int src) { // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[SRC_ADDR:.*]] = alloca i32 @@ -47,7 +47,7 @@ signed char unsigned_int_to_signed_char(unsigned int src) { //============================================================================// // CHECK-LABEL: @unsigned_int_to_signed_char__no_truncation_sanitizer -// CHECK-SAME: i32 noundef %[[SRC:.*]]) +// CHECK-SAME: (i32 %[[SRC:.*]]) __attribute__((no_sanitize("implicit-integer-truncation"))) signed char unsigned_int_to_signed_char__no_truncation_sanitizer(unsigned int src) { // CHECK-NEXT: [[ENTRY:.*]]: @@ -77,7 +77,7 @@ unsigned_int_to_signed_char__no_truncation_sanitizer(unsigned int src) { //============================================================================// // CHECK-LABEL: @unsigned_int_to_signed_char__no_signed_truncation_sanitizer -// CHECK-SAME: i32 noundef %[[SRC:.*]]) +// CHECK-SAME: (i32 %[[SRC:.*]]) __attribute__((no_sanitize("implicit-signed-integer-truncation"))) signed char unsigned_int_to_signed_char__no_signed_truncation_sanitizer(unsigned int src) { // CHECK-NEXT: [[ENTRY:.*]]: @@ -107,7 +107,7 @@ unsigned_int_to_signed_char__no_signed_truncation_sanitizer(unsigned int src) { //============================================================================// // CHECK-LABEL: @unsigned_int_to_signed_char__no_sign_change_sanitizer -// CHECK-SAME: i32 noundef %[[SRC:.*]]) +// CHECK-SAME: (i32 %[[SRC:.*]]) __attribute__((no_sanitize("implicit-integer-sign-change"))) signed char unsigned_int_to_signed_char__no_sign_change_sanitizer(unsigned int src) { // CHECK-NEXT: [[ENTRY:.*]]: @@ -137,7 +137,7 @@ unsigned_int_to_signed_char__no_sign_change_sanitizer(unsigned int src) { //============================================================================// // CHECK-LABEL: @unsigned_int_to_signed_char__no_sanitizers -// CHECK-SAME: i32 noundef %[[SRC:.*]]) +// CHECK-SAME: (i32 %[[SRC:.*]]) __attribute__((no_sanitize("implicit-integer-truncation"), no_sanitize("implicit-integer-sign-change"))) signed char unsigned_int_to_signed_char__no_sanitizers(unsigned int src) { diff --git a/clang/test/CodeGen/catch-nullptr-and-nonzero-offset-when-nullptr-is-defined.c b/clang/test/CodeGen/catch-nullptr-and-nonzero-offset-when-nullptr-is-defined.c index 5cd5b31eee6a9b9d694fbf124b489e624a3b44ec..e0b538a2a48032409f1d02bf5700e88d8da47c43 100644 --- a/clang/test/CodeGen/catch-nullptr-and-nonzero-offset-when-nullptr-is-defined.c +++ b/clang/test/CodeGen/catch-nullptr-and-nonzero-offset-when-nullptr-is-defined.c @@ -25,7 +25,7 @@ extern "C" { #endif char *add_unsigned(char *base, unsigned long offset) { - // CHECK: define{{.*}} i8* @add_unsigned(i8* noundef %[[BASE:.*]], i64 noundef %[[OFFSET:.*]]) + // CHECK: define{{.*}} i8* @add_unsigned(i8* %[[BASE:.*]], i64 %[[OFFSET:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[BASE_ADDR:.*]] = alloca i8*, align 8 // CHECK-NEXT: %[[OFFSET_ADDR:.*]] = alloca i64, align 8 diff --git a/clang/test/CodeGen/catch-nullptr-and-nonzero-offset.c b/clang/test/CodeGen/catch-nullptr-and-nonzero-offset.c index a98353b59b8c54cf43124940003f679da9cf5428..5c233a6ce26444d8a505cd82f3f4f096f3774efd 100644 --- a/clang/test/CodeGen/catch-nullptr-and-nonzero-offset.c +++ b/clang/test/CodeGen/catch-nullptr-and-nonzero-offset.c @@ -41,7 +41,7 @@ extern "C" { #endif char *var_var(char *base, unsigned long offset) { - // CHECK: define{{.*}} i8* @var_var(i8* noundef %[[BASE:.*]], i64 noundef %[[OFFSET:.*]]) + // CHECK: define{{.*}} i8* @var_var(i8* %[[BASE:.*]], i64 %[[OFFSET:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[BASE_ADDR:.*]] = alloca i8*, align 8 // CHECK-NEXT: %[[OFFSET_ADDR:.*]] = alloca i64, align 8 @@ -76,7 +76,7 @@ char *var_var(char *base, unsigned long offset) { } char *var_zero(char *base) { - // CHECK: define{{.*}} i8* @var_zero(i8* noundef %[[BASE:.*]]) + // CHECK: define{{.*}} i8* @var_zero(i8* %[[BASE:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[BASE_ADDR:.*]] = alloca i8*, align 8 // CHECK-NEXT: store i8* %[[BASE]], i8** %[[BASE_ADDR]], align 8 @@ -103,7 +103,7 @@ char *var_zero(char *base) { } char *var_one(char *base) { - // CHECK: define{{.*}} i8* @var_one(i8* noundef %[[BASE:.*]]) + // CHECK: define{{.*}} i8* @var_one(i8* %[[BASE:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[BASE_ADDR:.*]] = alloca i8*, align 8 // CHECK-NEXT: store i8* %[[BASE]], i8** %[[BASE_ADDR]], align 8 @@ -131,7 +131,7 @@ char *var_one(char *base) { } char *var_allones(char *base) { - // CHECK: define{{.*}} i8* @var_allones(i8* noundef %[[BASE:.*]]) + // CHECK: define{{.*}} i8* @var_allones(i8* %[[BASE:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[BASE_ADDR:.*]] = alloca i8*, align 8 // CHECK-NEXT: store i8* %[[BASE]], i8** %[[BASE_ADDR]], align 8 @@ -161,7 +161,7 @@ char *var_allones(char *base) { //------------------------------------------------------------------------------ char *nullptr_var(unsigned long offset) { - // CHECK: define{{.*}} i8* @nullptr_var(i64 noundef %[[OFFSET:.*]]) + // CHECK: define{{.*}} i8* @nullptr_var(i64 %[[OFFSET:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[OFFSET_ADDR:.*]] = alloca i64, align 8 // CHECK-NEXT: store i64 %[[OFFSET]], i64* %[[OFFSET_ADDR]], align 8 @@ -247,7 +247,7 @@ char *nullptr_allones_BAD() { //------------------------------------------------------------------------------ char *one_var(unsigned long offset) { - // CHECK: define{{.*}} i8* @one_var(i64 noundef %[[OFFSET:.*]]) + // CHECK: define{{.*}} i8* @one_var(i64 %[[OFFSET:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[OFFSET_ADDR:.*]] = alloca i64, align 8 // CHECK-NEXT: store i64 %[[OFFSET]], i64* %[[OFFSET_ADDR]], align 8 @@ -333,7 +333,7 @@ char *one_allones_BAD() { //------------------------------------------------------------------------------ char *allones_var(unsigned long offset) { - // CHECK: define{{.*}} i8* @allones_var(i64 noundef %[[OFFSET:.*]]) + // CHECK: define{{.*}} i8* @allones_var(i64 %[[OFFSET:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[OFFSET_ADDR:.*]] = alloca i64, align 8 // CHECK-NEXT: store i64 %[[OFFSET]], i64* %[[OFFSET_ADDR]], align 8 diff --git a/clang/test/CodeGen/catch-pointer-overflow-volatile.c b/clang/test/CodeGen/catch-pointer-overflow-volatile.c index cf5b57b76d1beb007e2af7072b3526d5579c44b6..b1b809e4217c15e5f15ad87290abd44549d1e9a8 100644 --- a/clang/test/CodeGen/catch-pointer-overflow-volatile.c +++ b/clang/test/CodeGen/catch-pointer-overflow-volatile.c @@ -15,7 +15,7 @@ extern "C" { #endif char *volatile_ptr(char *volatile base, unsigned long offset) { - // CHECK: define{{.*}} i8* @volatile_ptr(i8* noundef %[[BASE:.*]], i64 noundef %[[OFFSET:.*]]) + // CHECK: define{{.*}} i8* @volatile_ptr(i8* %[[BASE:.*]], i64 %[[OFFSET:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[BASE_ADDR:.*]] = alloca i8*, align 8 // CHECK-NEXT: %[[OFFSET_ADDR:.*]] = alloca i64, align 8 diff --git a/clang/test/CodeGen/catch-pointer-overflow.c b/clang/test/CodeGen/catch-pointer-overflow.c index 29e00f7702ffcd6f0aa10bdc433b8fdae2cdc363..bd01d77222e83468bd0fc46fe0edf766fc2d400e 100644 --- a/clang/test/CodeGen/catch-pointer-overflow.c +++ b/clang/test/CodeGen/catch-pointer-overflow.c @@ -22,7 +22,7 @@ extern "C" { #endif char *add_unsigned(char *base, unsigned long offset) { - // CHECK: define{{.*}} i8* @add_unsigned(i8* noundef %[[BASE:.*]], i64 noundef %[[OFFSET:.*]]) + // CHECK: define{{.*}} i8* @add_unsigned(i8* %[[BASE:.*]], i64 %[[OFFSET:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[BASE_ADDR:.*]] = alloca i8*, align 8 // CHECK-NEXT: %[[OFFSET_ADDR:.*]] = alloca i64, align 8 @@ -57,7 +57,7 @@ char *add_unsigned(char *base, unsigned long offset) { } char *sub_unsigned(char *base, unsigned long offset) { - // CHECK: define{{.*}} i8* @sub_unsigned(i8* noundef %[[BASE:.*]], i64 noundef %[[OFFSET:.*]]) + // CHECK: define{{.*}} i8* @sub_unsigned(i8* %[[BASE:.*]], i64 %[[OFFSET:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[BASE_ADDR:.*]] = alloca i8*, align 8 // CHECK-NEXT: %[[OFFSET_ADDR:.*]] = alloca i64, align 8 @@ -93,7 +93,7 @@ char *sub_unsigned(char *base, unsigned long offset) { } char *add_signed(char *base, signed long offset) { - // CHECK: define{{.*}} i8* @add_signed(i8* noundef %[[BASE:.*]], i64 noundef %[[OFFSET:.*]]) + // CHECK: define{{.*}} i8* @add_signed(i8* %[[BASE:.*]], i64 %[[OFFSET:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[BASE_ADDR:.*]] = alloca i8*, align 8 // CHECK-NEXT: %[[OFFSET_ADDR:.*]] = alloca i64, align 8 @@ -131,7 +131,7 @@ char *add_signed(char *base, signed long offset) { } char *sub_signed(char *base, signed long offset) { - // CHECK: define{{.*}} i8* @sub_signed(i8* noundef %[[BASE:.*]], i64 noundef %[[OFFSET:.*]]) + // CHECK: define{{.*}} i8* @sub_signed(i8* %[[BASE:.*]], i64 %[[OFFSET:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[BASE_ADDR:.*]] = alloca i8*, align 8 // CHECK-NEXT: %[[OFFSET_ADDR:.*]] = alloca i64, align 8 @@ -170,7 +170,7 @@ char *sub_signed(char *base, signed long offset) { } char *postinc(char *base) { - // CHECK: define{{.*}} i8* @postinc(i8* noundef %[[BASE:.*]]) + // CHECK: define{{.*}} i8* @postinc(i8* %[[BASE:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[BASE_ADDR:.*]] = alloca i8*, align 8 // CHECK-NEXT: store i8* %[[BASE]], i8** %[[BASE_ADDR]], align 8 @@ -200,7 +200,7 @@ char *postinc(char *base) { } char *postdec(char *base) { - // CHECK: define{{.*}} i8* @postdec(i8* noundef %[[BASE:.*]]) + // CHECK: define{{.*}} i8* @postdec(i8* %[[BASE:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[BASE_ADDR:.*]] = alloca i8*, align 8 // CHECK-NEXT: store i8* %[[BASE]], i8** %[[BASE_ADDR]], align 8 @@ -230,7 +230,7 @@ char *postdec(char *base) { } char *preinc(char *base) { - // CHECK: define{{.*}} i8* @preinc(i8* noundef %[[BASE:.*]]) + // CHECK: define{{.*}} i8* @preinc(i8* %[[BASE:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[BASE_ADDR:.*]] = alloca i8*, align 8 // CHECK-NEXT: store i8* %[[BASE]], i8** %[[BASE_ADDR]], align 8 @@ -260,7 +260,7 @@ char *preinc(char *base) { } char *predec(char *base) { - // CHECK: define{{.*}} i8* @predec(i8* noundef %[[BASE:.*]]) + // CHECK: define{{.*}} i8* @predec(i8* %[[BASE:.*]]) // CHECK-NEXT: [[ENTRY:.*]]: // CHECK-NEXT: %[[BASE_ADDR:.*]] = alloca i8*, align 8 // CHECK-NEXT: store i8* %[[BASE]], i8** %[[BASE_ADDR]], align 8 diff --git a/clang/test/CodeGen/cfi-check-fail.c b/clang/test/CodeGen/cfi-check-fail.c index 5cf62c0e6b876a4fce1674a5da89943b248ef815..f608e7d62e5035cba6b3139635dff9dbb54e52a4 100644 --- a/clang/test/CodeGen/cfi-check-fail.c +++ b/clang/test/CodeGen/cfi-check-fail.c @@ -7,7 +7,7 @@ void caller(void (*f)()) { f(); } -// CHECK: define weak_odr hidden void @__cfi_check_fail(i8* noundef %0, i8* noundef %1) +// CHECK: define weak_odr hidden void @__cfi_check_fail(i8* %0, i8* %1) // CHECK: store i8* %0, i8** %[[ALLOCA0:.*]], align 8 // CHECK: store i8* %1, i8** %[[ALLOCA1:.*]], align 8 // CHECK: %[[DATA:.*]] = load i8*, i8** %[[ALLOCA0]], align 8 diff --git a/clang/test/CodeGen/cfi-check-fail2.c b/clang/test/CodeGen/cfi-check-fail2.c index 45fd7d3db555a93ba0a2f566d0466c52efbbdc13..f2e3238434341f3a402493d8700b08079e6fd60f 100644 --- a/clang/test/CodeGen/cfi-check-fail2.c +++ b/clang/test/CodeGen/cfi-check-fail2.c @@ -13,7 +13,7 @@ void caller(void (*f)()) { f(); } -// CHECK: define weak_odr hidden void @__cfi_check_fail(i8* noundef %0, i8* noundef %1) +// CHECK: define weak_odr hidden void @__cfi_check_fail(i8* %0, i8* %1) // CHECK: store i8* %0, i8** %[[ALLOCA0:.*]], align 8 // CHECK: store i8* %1, i8** %[[ALLOCA1:.*]], align 8 // CHECK: %[[DATA:.*]] = load i8*, i8** %[[ALLOCA0]], align 8 diff --git a/clang/test/CodeGen/cmse-clear-arg.c b/clang/test/CodeGen/cmse-clear-arg.c index 4c7eef82d45624e73236ec3402721b31de832962..1447eb61b66e56d831b3c9b1cb2103099e7e18cf 100644 --- a/clang/test/CodeGen/cmse-clear-arg.c +++ b/clang/test/CodeGen/cmse-clear-arg.c @@ -87,7 +87,7 @@ void f15_1() { // CHECK-LE: %cmse.clear1 = and i32 {{.*}}, 134215708 // CHECK-BE: %cmse.clear1 = and i32 {{.*}}, 941621216 // CHECK: %[[R1:.*]] = insertvalue [2 x i32] %[[R0]], i32 %cmse.clear1, 1 -// CHECK: call {{.*}} void %[[FN]](i32 noundef 0, i32 noundef 1, i32 noundef 2, [2 x i32] %[[R1]]) +// CHECK: call {{.*}} void %[[FN]](i32 0, i32 1, i32 2, [2 x i32] %[[R1]]) // LE: 11111111 ........ 11111111 11111111 1111.... ...11111 ........ .111111. // LE: 0xff00fffff01f007e/9079291968726434047 diff --git a/clang/test/CodeGen/complex-builtins.c b/clang/test/CodeGen/complex-builtins.c index 272388be8baa3aafcbfafe03e9c24fc107aaf41f..6fea8a9f028c941c38c0d9681d4ae5ce01a2073a 100644 --- a/clang/test/CodeGen/complex-builtins.c +++ b/clang/test/CodeGen/complex-builtins.c @@ -6,102 +6,102 @@ void foo(float f) { __builtin_cabs(f); __builtin_cabsf(f); __builtin_cabsl(f); -// NO__ERRNO: declare double @cabs(double noundef, double noundef) [[READNONE:#[0-9]+]] -// NO__ERRNO: declare float @cabsf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @cabsl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE:#[0-9]+]] -// HAS_ERRNO: declare double @cabs(double noundef, double noundef) [[NOT_READNONE:#[0-9]+]] -// HAS_ERRNO: declare float @cabsf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @cabsl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare double @cabs(double, double) [[READNONE:#[0-9]+]] +// NO__ERRNO: declare float @cabsf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @cabsl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE:#[0-9]+]] +// HAS_ERRNO: declare double @cabs(double, double) [[NOT_READNONE:#[0-9]+]] +// HAS_ERRNO: declare float @cabsf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @cabsl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_cacos(f); __builtin_cacosf(f); __builtin_cacosl(f); -// NO__ERRNO: declare { double, double } @cacos(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @cacosf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cacosl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @cacos(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @cacosf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cacosl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @cacos(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @cacosf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cacosl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @cacos(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @cacosf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cacosl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_cacosh(f); __builtin_cacoshf(f); __builtin_cacoshl(f); -// NO__ERRNO: declare { double, double } @cacosh(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @cacoshf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cacoshl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @cacosh(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @cacoshf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cacoshl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @cacosh(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @cacoshf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cacoshl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @cacosh(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @cacoshf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cacoshl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_carg(f); __builtin_cargf(f); __builtin_cargl(f); -// NO__ERRNO: declare double @carg(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare float @cargf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @cargl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare double @carg(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @cargf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @cargl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare double @carg(double, double) [[READNONE]] +// NO__ERRNO: declare float @cargf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @cargl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare double @carg(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @cargf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @cargl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_casin(f); __builtin_casinf(f); __builtin_casinl(f); -// NO__ERRNO: declare { double, double } @casin(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @casinf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @casinl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @casin(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @casinf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @casinl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @casin(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @casinf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @casinl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @casin(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @casinf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @casinl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_casinh(f); __builtin_casinhf(f); __builtin_casinhl(f); -// NO__ERRNO: declare { double, double } @casinh(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @casinhf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @casinhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @casinh(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @casinhf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @casinhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @casinh(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @casinhf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @casinhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @casinh(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @casinhf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @casinhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_catan(f); __builtin_catanf(f); __builtin_catanl(f); -// NO__ERRNO: declare { double, double } @catan(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @catanf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @catanl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @catan(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @catanf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @catanl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @catan(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @catanf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @catanl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @catan(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @catanf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @catanl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_catanh(f); __builtin_catanhf(f); __builtin_catanhl(f); -// NO__ERRNO: declare { double, double } @catanh(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @catanhf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @catanhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @catanh(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @catanhf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @catanhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @catanh(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @catanhf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @catanhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @catanh(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @catanhf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @catanhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_ccos(f); __builtin_ccosf(f); __builtin_ccosl(f); -// NO__ERRNO: declare { double, double } @ccos(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @ccosf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ccosl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @ccos(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @ccosf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ccosl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @ccos(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @ccosf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ccosl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @ccos(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @ccosf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ccosl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_ccosh(f); __builtin_ccoshf(f); __builtin_ccoshl(f); -// NO__ERRNO: declare { double, double } @ccosh(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @ccoshf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ccoshl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @ccosh(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @ccoshf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ccoshl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @ccosh(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @ccoshf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ccoshl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @ccosh(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @ccoshf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ccoshl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_cexp(f); __builtin_cexpf(f); __builtin_cexpl(f); -// NO__ERRNO: declare { double, double } @cexp(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @cexpf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cexpl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @cexp(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @cexpf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cexpl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @cexp(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @cexpf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cexpl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @cexp(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @cexpf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cexpl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_cimag(f); __builtin_cimagf(f); __builtin_cimagl(f); @@ -119,30 +119,30 @@ void foo(float f) { __builtin_clog(f); __builtin_clogf(f); __builtin_clogl(f); -// NO__ERRNO: declare { double, double } @clog(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @clogf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @clogl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @clog(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @clogf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @clogl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @clog(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @clogf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @clogl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @clog(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @clogf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @clogl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_cproj(f); __builtin_cprojf(f); __builtin_cprojl(f); -// NO__ERRNO: declare { double, double } @cproj(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @cprojf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cprojl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @cproj(double noundef, double noundef) [[READNONE:#[0-9]+]] -// HAS_ERRNO: declare <2 x float> @cprojf(<2 x float> noundef) [[READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cprojl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[WILLRETURN_NOT_READNONE:#[0-9]+]] +// NO__ERRNO: declare { double, double } @cproj(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @cprojf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cprojl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @cproj(double, double) [[READNONE:#[0-9]+]] +// HAS_ERRNO: declare <2 x float> @cprojf(<2 x float>) [[READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cprojl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[WILLRETURN_NOT_READNONE:#[0-9]+]] __builtin_cpow(f,f); __builtin_cpowf(f,f); __builtin_cpowl(f,f); -// NO__ERRNO: declare { double, double } @cpow(double noundef, double noundef, double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @cpowf(<2 x float> noundef, <2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cpowl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16, { x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @cpow(double noundef, double noundef, double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @cpowf(<2 x float> noundef, <2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cpowl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16, { x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @cpow(double, double, double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @cpowf(<2 x float>, <2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cpowl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16, { x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @cpow(double, double, double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @cpowf(<2 x float>, <2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cpowl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16, { x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_creal(f); __builtin_crealf(f); __builtin_creall(f); @@ -153,48 +153,48 @@ void foo(float f) { __builtin_csin(f); __builtin_csinf(f); __builtin_csinl(f); -// NO__ERRNO: declare { double, double } @csin(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @csinf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @csinl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @csin(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @csinf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @csinl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @csin(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @csinf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @csinl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @csin(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @csinf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @csinl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_csinh(f); __builtin_csinhf(f); __builtin_csinhl(f); -// NO__ERRNO: declare { double, double } @csinh(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @csinhf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @csinhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @csinh(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @csinhf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @csinhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @csinh(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @csinhf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @csinhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @csinh(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @csinhf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @csinhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_csqrt(f); __builtin_csqrtf(f); __builtin_csqrtl(f); -// NO__ERRNO: declare { double, double } @csqrt(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @csqrtf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @csqrtl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @csqrt(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @csqrtf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @csqrtl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @csqrt(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @csqrtf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @csqrtl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @csqrt(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @csqrtf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @csqrtl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_ctan(f); __builtin_ctanf(f); __builtin_ctanl(f); -// NO__ERRNO: declare { double, double } @ctan(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @ctanf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ctanl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @ctan(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @ctanf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ctanl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @ctan(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @ctanf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ctanl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @ctan(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @ctanf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ctanl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] __builtin_ctanh(f); __builtin_ctanhf(f); __builtin_ctanhl(f); -// NO__ERRNO: declare { double, double } @ctanh(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @ctanhf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ctanhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @ctanh(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @ctanhf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ctanhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @ctanh(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @ctanhf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ctanhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @ctanh(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @ctanhf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ctanhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] }; // NO__ERRNO: attributes [[READNONE]] = { {{.*}}readnone{{.*}} } diff --git a/clang/test/CodeGen/complex-indirect.c b/clang/test/CodeGen/complex-indirect.c index 2dc164f895956fe1e13151cb708f6e10687329d6..783b8269637f8cf456cbc6a8bb573f75fe10dc33 100644 --- a/clang/test/CodeGen/complex-indirect.c +++ b/clang/test/CodeGen/complex-indirect.c @@ -9,4 +9,4 @@ void a(int,int,int,int,int,int,__complex__ char); void b(__complex__ char *y) { a(0,0,0,0,0,0,*y); } // CHECK-LABEL: define{{.*}} void @b // CHECK: alloca { i8, i8 }*, align 8 -// CHECK: call void @a(i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i32 noundef 0, i16 {{.*}}) +// CHECK: call void @a(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i16 {{.*}}) diff --git a/clang/test/CodeGen/complex-libcalls.c b/clang/test/CodeGen/complex-libcalls.c index c33f058baede9a3672c2d071f8162eb141298c67..44d6849c0a71763dbc4cc4158ca092373df35121 100644 --- a/clang/test/CodeGen/complex-libcalls.c +++ b/clang/test/CodeGen/complex-libcalls.c @@ -6,102 +6,102 @@ void foo(float f) { cabs(f); cabsf(f); cabsl(f); -// NO__ERRNO: declare double @cabs(double noundef, double noundef) [[READNONE:#[0-9]+]] -// NO__ERRNO: declare float @cabsf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @cabsl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE:#[0-9]+]] -// HAS_ERRNO: declare double @cabs(double noundef, double noundef) [[NOT_READNONE:#[0-9]+]] -// HAS_ERRNO: declare float @cabsf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @cabsl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare double @cabs(double, double) [[READNONE:#[0-9]+]] +// NO__ERRNO: declare float @cabsf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @cabsl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE:#[0-9]+]] +// HAS_ERRNO: declare double @cabs(double, double) [[NOT_READNONE:#[0-9]+]] +// HAS_ERRNO: declare float @cabsf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @cabsl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] cacos(f); cacosf(f); cacosl(f); -// NO__ERRNO: declare { double, double } @cacos(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @cacosf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cacosl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @cacos(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @cacosf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cacosl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @cacos(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @cacosf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cacosl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @cacos(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @cacosf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cacosl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] cacosh(f); cacoshf(f); cacoshl(f); -// NO__ERRNO: declare { double, double } @cacosh(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @cacoshf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cacoshl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @cacosh(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @cacoshf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cacoshl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @cacosh(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @cacoshf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cacoshl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @cacosh(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @cacoshf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cacoshl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] carg(f); cargf(f); cargl(f); -// NO__ERRNO: declare double @carg(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare float @cargf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @cargl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare double @carg(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @cargf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @cargl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare double @carg(double, double) [[READNONE]] +// NO__ERRNO: declare float @cargf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @cargl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare double @carg(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @cargf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @cargl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] casin(f); casinf(f); casinl(f); -// NO__ERRNO: declare { double, double } @casin(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @casinf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @casinl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @casin(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @casinf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @casinl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @casin(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @casinf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @casinl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @casin(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @casinf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @casinl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] casinh(f); casinhf(f); casinhl(f); -// NO__ERRNO: declare { double, double } @casinh(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @casinhf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @casinhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @casinh(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @casinhf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @casinhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @casinh(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @casinhf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @casinhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @casinh(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @casinhf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @casinhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] catan(f); catanf(f); catanl(f); -// NO__ERRNO: declare { double, double } @catan(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @catanf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @catanl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @catan(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @catanf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @catanl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @catan(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @catanf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @catanl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @catan(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @catanf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @catanl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] catanh(f); catanhf(f); catanhl(f); -// NO__ERRNO: declare { double, double } @catanh(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @catanhf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @catanhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @catanh(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @catanhf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @catanhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @catanh(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @catanhf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @catanhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @catanh(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @catanhf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @catanhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] ccos(f); ccosf(f); ccosl(f); -// NO__ERRNO: declare { double, double } @ccos(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @ccosf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ccosl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @ccos(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @ccosf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ccosl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @ccos(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @ccosf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ccosl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @ccos(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @ccosf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ccosl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] ccosh(f); ccoshf(f); ccoshl(f); -// NO__ERRNO: declare { double, double } @ccosh(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @ccoshf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ccoshl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @ccosh(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @ccoshf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ccoshl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @ccosh(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @ccoshf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ccoshl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @ccosh(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @ccoshf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ccoshl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] cexp(f); cexpf(f); cexpl(f); -// NO__ERRNO: declare { double, double } @cexp(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @cexpf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cexpl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @cexp(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @cexpf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cexpl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @cexp(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @cexpf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cexpl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @cexp(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @cexpf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cexpl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] cimag(f); cimagf(f); cimagl(f); @@ -119,30 +119,30 @@ void foo(float f) { clog(f); clogf(f); clogl(f); -// NO__ERRNO: declare { double, double } @clog(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @clogf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @clogl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @clog(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @clogf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @clogl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @clog(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @clogf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @clogl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @clog(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @clogf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @clogl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] cproj(f); cprojf(f); cprojl(f); -// NO__ERRNO: declare { double, double } @cproj(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @cprojf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cprojl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @cproj(double noundef, double noundef) [[READNONE:#[0-9]+]] -// HAS_ERRNO: declare <2 x float> @cprojf(<2 x float> noundef) [[READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cprojl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[WILLRETURN_NOT_READNONE:#[0-9]+]] +// NO__ERRNO: declare { double, double } @cproj(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @cprojf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cprojl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @cproj(double, double) [[READNONE:#[0-9]+]] +// HAS_ERRNO: declare <2 x float> @cprojf(<2 x float>) [[READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cprojl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[WILLRETURN_NOT_READNONE:#[0-9]+]] cpow(f,f); cpowf(f,f); cpowl(f,f); -// NO__ERRNO: declare { double, double } @cpow(double noundef, double noundef, double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @cpowf(<2 x float> noundef, <2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cpowl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16, { x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @cpow(double noundef, double noundef, double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @cpowf(<2 x float> noundef, <2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cpowl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16, { x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @cpow(double, double, double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @cpowf(<2 x float>, <2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @cpowl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16, { x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @cpow(double, double, double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @cpowf(<2 x float>, <2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @cpowl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16, { x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] creal(f); crealf(f); creall(f); @@ -153,48 +153,48 @@ void foo(float f) { csin(f); csinf(f); csinl(f); -// NO__ERRNO: declare { double, double } @csin(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @csinf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @csinl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @csin(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @csinf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @csinl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @csin(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @csinf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @csinl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @csin(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @csinf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @csinl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] csinh(f); csinhf(f); csinhl(f); -// NO__ERRNO: declare { double, double } @csinh(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @csinhf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @csinhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @csinh(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @csinhf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @csinhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @csinh(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @csinhf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @csinhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @csinh(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @csinhf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @csinhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] csqrt(f); csqrtf(f); csqrtl(f); -// NO__ERRNO: declare { double, double } @csqrt(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @csqrtf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @csqrtl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @csqrt(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @csqrtf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @csqrtl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @csqrt(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @csqrtf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @csqrtl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @csqrt(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @csqrtf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @csqrtl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] ctan(f); ctanf(f); ctanl(f); -// NO__ERRNO: declare { double, double } @ctan(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @ctanf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ctanl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @ctan(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @ctanf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ctanl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @ctan(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @ctanf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ctanl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @ctan(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @ctanf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ctanl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] ctanh(f); ctanhf(f); ctanhl(f); -// NO__ERRNO: declare { double, double } @ctanh(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare <2 x float> @ctanhf(<2 x float> noundef) [[READNONE]] -// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ctanhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] -// HAS_ERRNO: declare { double, double } @ctanh(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare <2 x float> @ctanhf(<2 x float> noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ctanhl({ x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// NO__ERRNO: declare { double, double } @ctanh(double, double) [[READNONE]] +// NO__ERRNO: declare <2 x float> @ctanhf(<2 x float>) [[READNONE]] +// NO__ERRNO: declare { x86_fp80, x86_fp80 } @ctanhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] +// HAS_ERRNO: declare { double, double } @ctanh(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare <2 x float> @ctanhf(<2 x float>) [[NOT_READNONE]] +// HAS_ERRNO: declare { x86_fp80, x86_fp80 } @ctanhl({ x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16) [[NOT_READNONE]] }; // NO__ERRNO: attributes [[READNONE]] = { {{.*}}readnone{{.*}} } diff --git a/clang/test/CodeGen/complex-math.c b/clang/test/CodeGen/complex-math.c index 90de7ae989eeba92f94bf0faac0988d652ff77a9..d8ddb65f4628dbdd9ad4603383dc653cbe702956 100644 --- a/clang/test/CodeGen/complex-math.c +++ b/clang/test/CodeGen/complex-math.c @@ -1,12 +1,12 @@ -// RUN: %clang_cc1 %s -O0 -fno-experimental-new-pass-manager -emit-llvm -triple x86_64-unknown-unknown -o - | FileCheck %s --check-prefix=X86 -// RUN: %clang_cc1 %s -O0 -fno-experimental-new-pass-manager -emit-llvm -triple x86_64-pc-win64 -o - | FileCheck %s --check-prefix=X86 -// RUN: %clang_cc1 %s -O0 -fno-experimental-new-pass-manager -emit-llvm -triple i686-unknown-unknown -o - | FileCheck %s --check-prefix=X86 -// RUN: %clang_cc1 %s -O0 -fno-experimental-new-pass-manager -emit-llvm -triple powerpc-unknown-unknown -o - | FileCheck %s --check-prefix=PPC -// RUN: %clang_cc1 %s -O0 -fno-experimental-new-pass-manager -emit-llvm -triple armv7-none-linux-gnueabi -o - | FileCheck %s --check-prefix=ARM -// RUN: %clang_cc1 %s -O0 -fno-experimental-new-pass-manager -emit-llvm -triple armv7-none-linux-gnueabihf -o - | FileCheck %s --check-prefix=ARMHF -// RUN: %clang_cc1 %s -O0 -fno-experimental-new-pass-manager -emit-llvm -triple thumbv7k-apple-watchos2.0 -o - -target-abi aapcs16 | FileCheck %s --check-prefix=ARM7K -// RUN: %clang_cc1 %s -O0 -fno-experimental-new-pass-manager -emit-llvm -triple aarch64-unknown-unknown -ffast-math -ffp-contract=fast -o - | FileCheck %s --check-prefix=AARCH64-FASTMATH -// RUN: %clang_cc1 %s -O0 -fno-experimental-new-pass-manager -emit-llvm -triple spir -o - | FileCheck %s --check-prefix=SPIR +// RUN: %clang_cc1 %s -O0 -emit-llvm -triple x86_64-unknown-unknown -o - | FileCheck %s --check-prefix=X86 +// RUN: %clang_cc1 %s -O0 -emit-llvm -triple x86_64-pc-win64 -o - | FileCheck %s --check-prefix=X86 +// RUN: %clang_cc1 %s -O0 -emit-llvm -triple i686-unknown-unknown -o - | FileCheck %s --check-prefix=X86 +// RUN: %clang_cc1 %s -O0 -emit-llvm -triple powerpc-unknown-unknown -o - | FileCheck %s --check-prefix=PPC +// RUN: %clang_cc1 %s -O0 -emit-llvm -triple armv7-none-linux-gnueabi -o - | FileCheck %s --check-prefix=ARM +// RUN: %clang_cc1 %s -O0 -emit-llvm -triple armv7-none-linux-gnueabihf -o - | FileCheck %s --check-prefix=ARMHF +// RUN: %clang_cc1 %s -O0 -emit-llvm -triple thumbv7k-apple-watchos2.0 -o - -target-abi aapcs16 | FileCheck %s --check-prefix=ARM7K +// RUN: %clang_cc1 %s -O0 -emit-llvm -triple aarch64-unknown-unknown -ffast-math -ffp-contract=fast -o - | FileCheck %s --check-prefix=AARCH64-FASTMATH +// RUN: %clang_cc1 %s -O0 -emit-llvm -triple spir -o - | FileCheck %s --check-prefix=SPIR float _Complex add_float_rr(float a, float b) { // X86-LABEL: @add_float_rr( @@ -136,7 +136,7 @@ float _Complex div_float_rc(float a, float _Complex b) { // SPIR: call spir_func {{.*}} @__divsc3( // a / b = (A+iB) / (C+iD) = ((AC+BD)/(CC+DD)) + i((BC-AD)/(CC+DD)) - // AARCH64-FASTMATH-LABEL: @div_float_rc(float noundef %a, [2 x float] noundef %b.coerce) + // AARCH64-FASTMATH-LABEL: @div_float_rc(float %a, [2 x float] %b.coerce) // A = a // B = 0 // @@ -165,7 +165,7 @@ float _Complex div_float_cc(float _Complex a, float _Complex b) { // SPIR: call spir_func {{.*}} @__divsc3( // a / b = (A+iB) / (C+iD) = ((AC+BD)/(CC+DD)) + i((BC-AD)/(CC+DD)) - // AARCH64-FASTMATH-LABEL: @div_float_cc([2 x float] noundef %a.coerce, [2 x float] noundef %b.coerce) + // AARCH64-FASTMATH-LABEL: @div_float_cc([2 x float] %a.coerce, [2 x float] %b.coerce) // // AARCH64-FASTMATH: [[AC:%.*]] = fmul fast float // AARCH64-FASTMATH: [[BD:%.*]] = fmul fast float @@ -313,7 +313,7 @@ double _Complex div_double_rc(double a, double _Complex b) { // SPIR: call spir_func {{.*}} @__divdc3( // a / b = (A+iB) / (C+iD) = ((AC+BD)/(CC+DD)) + i((BC-AD)/(CC+DD)) - // AARCH64-FASTMATH-LABEL: @div_double_rc(double noundef %a, [2 x double] noundef %b.coerce) + // AARCH64-FASTMATH-LABEL: @div_double_rc(double %a, [2 x double] %b.coerce) // A = a // B = 0 // @@ -342,7 +342,7 @@ double _Complex div_double_cc(double _Complex a, double _Complex b) { // SPIR: call spir_func {{.*}} @__divdc3( // a / b = (A+iB) / (C+iD) = ((AC+BD)/(CC+DD)) + i((BC-AD)/(CC+DD)) - // AARCH64-FASTMATH-LABEL: @div_double_cc([2 x double] noundef %a.coerce, [2 x double] noundef %b.coerce) + // AARCH64-FASTMATH-LABEL: @div_double_cc([2 x double] %a.coerce, [2 x double] %b.coerce) // // AARCH64-FASTMATH: [[AC:%.*]] = fmul fast double // AARCH64-FASTMATH: [[BD:%.*]] = fmul fast double @@ -506,7 +506,7 @@ long double _Complex div_long_double_rc(long double a, long double _Complex b) { // SPIR: call spir_func {{.*}} @__divdc3( // a / b = (A+iB) / (C+iD) = ((AC+BD)/(CC+DD)) + i((BC-AD)/(CC+DD)) - // AARCH64-FASTMATH-LABEL: @div_long_double_rc(fp128 noundef %a, [2 x fp128] noundef %b.coerce) + // AARCH64-FASTMATH-LABEL: @div_long_double_rc(fp128 %a, [2 x fp128] %b.coerce) // A = a // B = 0 // @@ -538,7 +538,7 @@ long double _Complex div_long_double_cc(long double _Complex a, long double _Com // SPIR: call spir_func {{.*}} @__divdc3( // a / b = (A+iB) / (C+iD) = ((AC+BD)/(CC+DD)) + i((BC-AD)/(CC+DD)) - // AARCH64-FASTMATH-LABEL: @div_long_double_cc([2 x fp128] noundef %a.coerce, [2 x fp128] noundef %b.coerce) + // AARCH64-FASTMATH-LABEL: @div_long_double_cc([2 x fp128] %a.coerce, [2 x fp128] %b.coerce) // // AARCH64-FASTMATH: [[AC:%.*]] = fmul fast fp128 // AARCH64-FASTMATH: [[BD:%.*]] = fmul fast fp128 diff --git a/clang/test/CodeGen/complex-strictfp.c b/clang/test/CodeGen/complex-strictfp.c index b1eff08640118b5bf2dab07291768c790e94921d..d493002d1445d2adb6fd6174470b9d52521b127b 100644 --- a/clang/test/CodeGen/complex-strictfp.c +++ b/clang/test/CodeGen/complex-strictfp.c @@ -20,11 +20,11 @@ double D; // CHECK-NEXT: [[TMP0:%.*]] = load double, double* @D, align 8 // CHECK-NEXT: [[CF_REAL:%.*]] = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 0), align 4 // CHECK-NEXT: [[CF_IMAG:%.*]] = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 1), align 4 -// CHECK-NEXT: [[CONV:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float [[CF_REAL]], metadata !"fpexcept.strict") #[[ATTR2:[0-9]+]] -// CHECK-NEXT: [[CONV1:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float [[CF_IMAG]], metadata !"fpexcept.strict") #[[ATTR2]] -// CHECK-NEXT: [[ADD_R:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double [[CONV]], double [[TMP0]], metadata !"round.upward", metadata !"fpexcept.strict") #[[ATTR2]] -// CHECK-NEXT: [[CONV2:%.*]] = call float @llvm.experimental.constrained.fptrunc.f32.f64(double [[ADD_R]], metadata !"round.upward", metadata !"fpexcept.strict") #[[ATTR2]] -// CHECK-NEXT: [[CONV3:%.*]] = call float @llvm.experimental.constrained.fptrunc.f32.f64(double [[CONV1]], metadata !"round.upward", metadata !"fpexcept.strict") #[[ATTR2]] +// CHECK-NEXT: [[CONV:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float [[CF_REAL]], metadata !"fpexcept.strict") [[ATTR2:#.*]] +// CHECK-NEXT: [[CONV1:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float [[CF_IMAG]], metadata !"fpexcept.strict") [[ATTR2]] +// CHECK-NEXT: [[ADD_R:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double [[CONV]], double [[TMP0]], metadata !"round.upward", metadata !"fpexcept.strict") [[ATTR2]] +// CHECK-NEXT: [[CONV2:%.*]] = call float @llvm.experimental.constrained.fptrunc.f32.f64(double [[ADD_R]], metadata !"round.upward", metadata !"fpexcept.strict") [[ATTR2]] +// CHECK-NEXT: [[CONV3:%.*]] = call float @llvm.experimental.constrained.fptrunc.f32.f64(double [[CONV1]], metadata !"round.upward", metadata !"fpexcept.strict") [[ATTR2]] // CHECK-NEXT: store float [[CONV2]], float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 0), align 4 // CHECK-NEXT: store float [[CONV3]], float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 1), align 4 // CHECK-NEXT: ret void @@ -37,10 +37,10 @@ void test3a() { // CHECK-NEXT: entry: // CHECK-NEXT: [[CF_REAL:%.*]] = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 0), align 4 // CHECK-NEXT: [[CF_IMAG:%.*]] = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 1), align 4 -// CHECK-NEXT: [[CONV:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float [[CF_REAL]], metadata !"fpexcept.strict") #[[ATTR2]] -// CHECK-NEXT: [[CONV1:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float [[CF_IMAG]], metadata !"fpexcept.strict") #[[ATTR2]] +// CHECK-NEXT: [[CONV:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float [[CF_REAL]], metadata !"fpexcept.strict") [[ATTR2]] +// CHECK-NEXT: [[CONV1:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float [[CF_IMAG]], metadata !"fpexcept.strict") [[ATTR2]] // CHECK-NEXT: [[TMP0:%.*]] = load double, double* @D, align 8 -// CHECK-NEXT: [[ADD_R:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double [[TMP0]], double [[CONV]], metadata !"round.upward", metadata !"fpexcept.strict") #[[ATTR2]] +// CHECK-NEXT: [[ADD_R:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double [[TMP0]], double [[CONV]], metadata !"round.upward", metadata !"fpexcept.strict") [[ATTR2]] // CHECK-NEXT: store double [[ADD_R]], double* @D, align 8 // CHECK-NEXT: ret void // @@ -54,13 +54,13 @@ void test3b() { // CHECK-NEXT: [[G1_IMAG:%.*]] = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @g1, i32 0, i32 1), align 8 // CHECK-NEXT: [[CF_REAL:%.*]] = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 0), align 4 // CHECK-NEXT: [[CF_IMAG:%.*]] = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 1), align 4 -// CHECK-NEXT: [[CONV:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float [[CF_REAL]], metadata !"fpexcept.strict") #[[ATTR2]] -// CHECK-NEXT: [[CONV1:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float [[CF_IMAG]], metadata !"fpexcept.strict") #[[ATTR2]] -// CHECK-NEXT: [[CALL:%.*]] = call { double, double } @__divdc3(double noundef [[CONV]], double noundef [[CONV1]], double noundef [[G1_REAL]], double noundef [[G1_IMAG]]) #[[ATTR3:[0-9]+]] +// CHECK-NEXT: [[CONV:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float [[CF_REAL]], metadata !"fpexcept.strict") [[ATTR2]] +// CHECK-NEXT: [[CONV1:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float [[CF_IMAG]], metadata !"fpexcept.strict") [[ATTR2]] +// CHECK-NEXT: [[CALL:%.*]] = call { double, double } @__divdc3(double [[CONV]], double [[CONV1]], double [[G1_REAL]], double [[G1_IMAG]]) [[ATTR3:#.*]] // CHECK-NEXT: [[TMP0:%.*]] = extractvalue { double, double } [[CALL]], 0 // CHECK-NEXT: [[TMP1:%.*]] = extractvalue { double, double } [[CALL]], 1 -// CHECK-NEXT: [[CONV2:%.*]] = call float @llvm.experimental.constrained.fptrunc.f32.f64(double [[TMP0]], metadata !"round.upward", metadata !"fpexcept.strict") #[[ATTR2]] -// CHECK-NEXT: [[CONV3:%.*]] = call float @llvm.experimental.constrained.fptrunc.f32.f64(double [[TMP1]], metadata !"round.upward", metadata !"fpexcept.strict") #[[ATTR2]] +// CHECK-NEXT: [[CONV2:%.*]] = call float @llvm.experimental.constrained.fptrunc.f32.f64(double [[TMP0]], metadata !"round.upward", metadata !"fpexcept.strict") [[ATTR2]] +// CHECK-NEXT: [[CONV3:%.*]] = call float @llvm.experimental.constrained.fptrunc.f32.f64(double [[TMP1]], metadata !"round.upward", metadata !"fpexcept.strict") [[ATTR2]] // CHECK-NEXT: store float [[CONV2]], float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 0), align 4 // CHECK-NEXT: store float [[CONV3]], float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 1), align 4 // CHECK-NEXT: ret void @@ -74,7 +74,7 @@ void test3c() { // CHECK-NEXT: [[G1_REAL:%.*]] = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @g1, i32 0, i32 0), align 8 // CHECK-NEXT: [[G1_IMAG:%.*]] = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @g1, i32 0, i32 1), align 8 // CHECK-NEXT: [[TMP0:%.*]] = load double, double* @D, align 8 -// CHECK-NEXT: [[ADD_R:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double [[G1_REAL]], double [[TMP0]], metadata !"round.tonearest", metadata !"fpexcept.maytrap") #[[ATTR2]] +// CHECK-NEXT: [[ADD_R:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double [[G1_REAL]], double [[TMP0]], metadata !"round.tonearest", metadata !"fpexcept.maytrap") [[ATTR2]] // CHECK-NEXT: store double [[ADD_R]], double* getelementptr inbounds ({ double, double }, { double, double }* @g1, i32 0, i32 0), align 8 // CHECK-NEXT: store double [[G1_IMAG]], double* getelementptr inbounds ({ double, double }, { double, double }* @g1, i32 0, i32 1), align 8 // CHECK-NEXT: ret void @@ -88,7 +88,7 @@ void test3d() { // CHECK-NEXT: [[TMP0:%.*]] = load double, double* @D, align 8 // CHECK-NEXT: [[G1_REAL:%.*]] = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @g1, i32 0, i32 0), align 8 // CHECK-NEXT: [[G1_IMAG:%.*]] = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @g1, i32 0, i32 1), align 8 -// CHECK-NEXT: [[ADD_R:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double [[TMP0]], double [[G1_REAL]], metadata !"round.tonearest", metadata !"fpexcept.maytrap") #[[ATTR2]] +// CHECK-NEXT: [[ADD_R:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double [[TMP0]], double [[G1_REAL]], metadata !"round.tonearest", metadata !"fpexcept.maytrap") [[ATTR2]] // CHECK-NEXT: store double [[ADD_R]], double* getelementptr inbounds ({ double, double }, { double, double }* @g1, i32 0, i32 0), align 8 // CHECK-NEXT: store double [[G1_IMAG]], double* getelementptr inbounds ({ double, double }, { double, double }* @g1, i32 0, i32 1), align 8 // CHECK-NEXT: ret void @@ -99,7 +99,7 @@ void test3e() { // CHECK-LABEL: @t1( // CHECK-NEXT: entry: -// CHECK-NEXT: [[CONV:%.*]] = call float @llvm.experimental.constrained.fptrunc.f32.f64(double 4.000000e+00, metadata !"round.upward", metadata !"fpexcept.strict") #[[ATTR2]] +// CHECK-NEXT: [[CONV:%.*]] = call float @llvm.experimental.constrained.fptrunc.f32.f64(double 4.000000e+00, metadata !"round.upward", metadata !"fpexcept.strict") [[ATTR2]] // CHECK-NEXT: store float [[CONV]], float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 0), align 4 // CHECK-NEXT: ret void // @@ -109,7 +109,7 @@ void t1() { // CHECK-LABEL: @t2( // CHECK-NEXT: entry: -// CHECK-NEXT: [[CONV:%.*]] = call float @llvm.experimental.constrained.fptrunc.f32.f64(double 4.000000e+00, metadata !"round.upward", metadata !"fpexcept.strict") #[[ATTR2]] +// CHECK-NEXT: [[CONV:%.*]] = call float @llvm.experimental.constrained.fptrunc.f32.f64(double 4.000000e+00, metadata !"round.upward", metadata !"fpexcept.strict") [[ATTR2]] // CHECK-NEXT: store float [[CONV]], float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 1), align 4 // CHECK-NEXT: ret void // @@ -122,10 +122,10 @@ void t2() { // CHECK-NEXT: [[C:%.*]] = alloca [0 x i8], align 1 // CHECK-NEXT: br i1 false, label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK: cond.true: -// CHECK-NEXT: [[CONV:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float 2.000000e+00, metadata !"fpexcept.strict") #[[ATTR2]] +// CHECK-NEXT: [[CONV:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float 2.000000e+00, metadata !"fpexcept.strict") [[ATTR2]] // CHECK-NEXT: br label [[COND_END:%.*]] // CHECK: cond.false: -// CHECK-NEXT: [[CONV1:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float 2.000000e+00, metadata !"fpexcept.strict") #[[ATTR2]] +// CHECK-NEXT: [[CONV1:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float 2.000000e+00, metadata !"fpexcept.strict") [[ATTR2]] // CHECK-NEXT: br label [[COND_END]] // CHECK: cond.end: // CHECK-NEXT: [[COND_R:%.*]] = phi double [ [[CONV]], [[COND_TRUE]] ], [ [[CONV1]], [[COND_FALSE]] ] @@ -144,10 +144,10 @@ void t91() { // CHECK-NEXT: [[C:%.*]] = alloca [0 x i8], align 1 // CHECK-NEXT: br i1 false, label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK: cond.true: -// CHECK-NEXT: [[CONV:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float 2.000000e+00, metadata !"fpexcept.strict") #[[ATTR2]] +// CHECK-NEXT: [[CONV:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float 2.000000e+00, metadata !"fpexcept.strict") [[ATTR2]] // CHECK-NEXT: br label [[COND_END:%.*]] // CHECK: cond.false: -// CHECK-NEXT: [[CONV1:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float 2.000000e+00, metadata !"fpexcept.strict") #[[ATTR2]] +// CHECK-NEXT: [[CONV1:%.*]] = call double @llvm.experimental.constrained.fpext.f64.f32(float 2.000000e+00, metadata !"fpexcept.strict") [[ATTR2]] // CHECK-NEXT: br label [[COND_END]] // CHECK: cond.end: // CHECK-NEXT: [[COND_R:%.*]] = phi double [ [[CONV]], [[COND_TRUE]] ], [ [[CONV1]], [[COND_FALSE]] ] diff --git a/clang/test/CodeGen/constructor-attribute.c b/clang/test/CodeGen/constructor-attribute.c index 491ec6f8f2e31590fda5bd2e540ddc4345be5557..f7c9c202f49784ce4b44b3c8398331ff42b12161 100644 --- a/clang/test/CodeGen/constructor-attribute.c +++ b/clang/test/CodeGen/constructor-attribute.c @@ -12,7 +12,7 @@ // CHECK: define internal void @E() // CHECK: define internal void @F() // CHECK: define internal void @G() -// CHECK: define{{.*}} i32 @__GLOBAL_init_789(i32 noundef %{{.*}}) +// CHECK: define{{.*}} i32 @__GLOBAL_init_789(i32 %{{.*}}) // CHECK: define internal void @C() // CHECK: define internal void @D() // CHECK: define{{.*}} i32 @main() diff --git a/clang/test/CodeGen/cspgo-instrumentation.c b/clang/test/CodeGen/cspgo-instrumentation.c index d348ceab4865dba9561efd7a79b47d51cad1042a..3f90bb4396d70ac114825eed62504c1ab3b1945c 100644 --- a/clang/test/CodeGen/cspgo-instrumentation.c +++ b/clang/test/CodeGen/cspgo-instrumentation.c @@ -1,41 +1,27 @@ // Test if CSPGO instrumentation and use pass are invoked. // // Ensure Pass PGOInstrumentationGenPass is invoked. -// RUN: %clang_cc1 -O2 -fno-experimental-new-pass-manager -fprofile-instrument=csllvm -fprofile-instrument-path=default.profraw %s -mllvm -debug-pass=Structure -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN -// RUN: %clang_cc1 -O2 -fprofile-instrument=csllvm -fprofile-instrument-path=default.profraw %s -fexperimental-new-pass-manager -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-NEWPM -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN: PGOInstrumentationGenCreateVarPass -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN: PGOInstrumentationGenPass -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-NEWPM: Running pass: PGOInstrumentationGenCreateVar on -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-NEWPM: Running pass: PGOInstrumentationGen on +// RUN: %clang_cc1 -O2 -fprofile-instrument=csllvm -fprofile-instrument-path=default.profraw %s -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN +// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN: Running pass: PGOInstrumentationGenCreateVar on +// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN: Running pass: PGOInstrumentationGen on // // RUN: rm -rf %t && mkdir %t // RUN: llvm-profdata merge -o %t/noncs.profdata %S/Inputs/pgotestir.proftext // // Ensure Pass PGOInstrumentationUsePass and PGOInstrumentationGenPass are invoked. -// RUN: %clang_cc1 -O2 -fno-experimental-new-pass-manager -fprofile-instrument-use-path=%t/noncs.profdata -fprofile-instrument=csllvm -fprofile-instrument-path=default.profraw %s -mllvm -debug-pass=Structure -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN2 -// RUN: %clang_cc1 -O2 -fprofile-instrument-use-path=%t/noncs.profdata -fprofile-instrument=csllvm -fprofile-instrument-path=default.profraw %s -fexperimental-new-pass-manager -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN2-NEWPM -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN2: PGOInstrumentationUsePass -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN2: PGOInstrumentationGenCreateVarPass -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN2: PGOInstrumentationGenPass -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN2-NEWPM: Running pass: PGOInstrumentationUse -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN2-NEWPM: Running pass: PGOInstrumentationGenCreateVar on -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN2-NEWPM: Running pass: PGOInstrumentationGen on +// RUN: %clang_cc1 -O2 -fprofile-instrument-use-path=%t/noncs.profdata -fprofile-instrument=csllvm -fprofile-instrument-path=default.profraw %s -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN2 +// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN2: Running pass: PGOInstrumentationUse +// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN2: Running pass: PGOInstrumentationGenCreateVar on +// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN2: Running pass: PGOInstrumentationGen on // Ensure Pass PGOInstrumentationUsePass is invoked only once. -// RUN: %clang_cc1 -O2 -fno-experimental-new-pass-manager -fprofile-instrument-use-path=%t/noncs.profdata %s -mllvm -debug-pass=Structure -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOUSEPASS-INVOKED-USE -// RUN: %clang_cc1 -O2 -fprofile-instrument-use-path=%t/noncs.profdata %s -fexperimental-new-pass-manager -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOUSEPASS-INVOKED-USE-NEWPM -// CHECK-PGOUSEPASS-INVOKED-USE: PGOInstrumentationUsePass -// CHECK-PGOUSEPASS-INVOKED-USE-NOT: PGOInstrumentationGenCreateVarPass -// CHECK-PGOUSEPASS-INVOKED-USE-NOT: PGOInstrumentationUsePass -// CHECK-PGOUSEPASS-INVOKED-USE-NEWPM: Running pass: PGOInstrumentationUse -// CHECK-PGOUSEPASS-INVOKED-USE-NEWPM-NOT: Running pass: PGOInstrumentationGenCreateVar -// CHECK-PGOUSEPASS-INVOKED-USE-NEWPM-NOT: Running pass: PGOInstrumentationUse +// RUN: %clang_cc1 -O2 -fprofile-instrument-use-path=%t/noncs.profdata %s -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOUSEPASS-INVOKED-USE +// CHECK-PGOUSEPASS-INVOKED-USE: Running pass: PGOInstrumentationUse +// CHECK-PGOUSEPASS-INVOKED-USE-NOT: Running pass: PGOInstrumentationGenCreateVar +// CHECK-PGOUSEPASS-INVOKED-USE-NOT: Running pass: PGOInstrumentationUse // // Ensure Pass PGOInstrumentationUsePass is invoked twice. // RUN: llvm-profdata merge -o %t/cs.profdata %S/Inputs/pgotestir_cs.proftext -// RUN: %clang_cc1 -O2 -fno-experimental-new-pass-manager -fprofile-instrument-use-path=%t/cs.profdata %s -mllvm -debug-pass=Structure -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOUSEPASS-INVOKED-USE2 -// RUN: %clang_cc1 -O2 -fprofile-instrument-use-path=%t/cs.profdata %s -fexperimental-new-pass-manager -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOUSEPASS-INVOKED-USE2-NEWPM -// CHECK-PGOUSEPASS-INVOKED-USE2: PGOInstrumentationUsePass -// CHECK-PGOUSEPASS-INVOKED-USE2: PGOInstrumentationUsePass -// CHECK-PGOUSEPASS-INVOKED-USE2-NEWPM: Running pass: PGOInstrumentationUse -// CHECK-PGOUSEPASS-INVOKED-USE2-NEWPM: Running pass: PGOInstrumentationUse +// RUN: %clang_cc1 -O2 -fprofile-instrument-use-path=%t/cs.profdata %s -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOUSEPASS-INVOKED-USE2 +// CHECK-PGOUSEPASS-INVOKED-USE2: Running pass: PGOInstrumentationUse +// CHECK-PGOUSEPASS-INVOKED-USE2: Running pass: PGOInstrumentationUse diff --git a/clang/test/CodeGen/cspgo-instrumentation_lto.c b/clang/test/CodeGen/cspgo-instrumentation_lto.c index 7d65428a82ecd91b41fb9439b58893ff779c3525..c4296842ae50e97d8ce6d9a0af84fe6f69808923 100644 --- a/clang/test/CodeGen/cspgo-instrumentation_lto.c +++ b/clang/test/CodeGen/cspgo-instrumentation_lto.c @@ -4,41 +4,26 @@ // RUN: llvm-profdata merge -o %t/noncs.profdata %S/Inputs/pgotestir.proftext // // Ensure Pass PGOInstrumentationGenPass is not invoked in PreLink. -// RUN: %clang_cc1 -O2 -fno-experimental-new-pass-manager -fprofile-instrument-use-path=%t/noncs.profdata -fprofile-instrument=csllvm %s -flto -mllvm -debug-pass=Structure -emit-llvm-bc -o %t/foo_fe.bc 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-PRE -// RUN: %clang_cc1 -O2 -fprofile-instrument-use-path=%t/noncs.profdata -fprofile-instrument=csllvm %s -flto -fexperimental-new-pass-manager -fdebug-pass-manager -emit-llvm-bc -o %t/foo_fe_pm.bc 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-PRE-NEWPM -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-PRE: PGOInstrumentationUsePass -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-PRE: PGOInstrumentationGenCreateVarPass -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-PRE-NOT: PGOInstrumentationGenPass -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-PRE-NEWPM: Running pass: PGOInstrumentationUse -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-PRE-NEWPM: Running pass: PGOInstrumentationGenCreateVar -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-PRE-NEWPM-NOT: Running pass: PGOInstrumentationGen on +// RUN: %clang_cc1 -O2 -fprofile-instrument-use-path=%t/noncs.profdata -fprofile-instrument=csllvm %s -flto -fdebug-pass-manager -emit-llvm-bc -o %t/foo_fe_pm.bc 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-PRE +// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-PRE: Running pass: PGOInstrumentationUse +// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-PRE: Running pass: PGOInstrumentationGenCreateVar +// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-PRE-NOT: Running pass: PGOInstrumentationGen on // // Ensure Pass PGOInstrumentationGenPass is invoked in PostLink. -// RUN: %clang_cc1 -O2 -fno-experimental-new-pass-manager -x ir %t/foo_fe.bc -fprofile-instrument=csllvm -emit-llvm -mllvm -debug-pass=Structure -o - 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-POST -// RUN: %clang_cc1 -O2 -x ir %t/foo_fe_pm.bc -fexperimental-new-pass-manager -fdebug-pass-manager -fprofile-instrument=csllvm -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-POST-NEWPM -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-POST-NOT: PGOInstrumentationUsePass -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-POST: PGOInstrumentationGenPass -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-POST-NOT: PGOInstrumentationGenCreateVarPass -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-POST-NEWPM-NOT: Running pass: PGOInstrumentationUse -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-POST-NEWPM: Running pass: PGOInstrumentationGen on -// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-POST-NEWPM-NOT: Running pass: PGOInstrumentationGenCreateVar +// RUN: %clang_cc1 -O2 -x ir %t/foo_fe_pm.bc -fdebug-pass-manager -fprofile-instrument=csllvm -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-POST +// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-POST-NOT: Running pass: PGOInstrumentationUse +// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-POST: Running pass: PGOInstrumentationGen on +// CHECK-CSPGOGENPASS-INVOKED-INSTR-GEN-POST-NOT: Running pass: PGOInstrumentationGenCreateVar // // RUN: llvm-profdata merge -o %t/cs.profdata %S/Inputs/pgotestir_cs.proftext // // Ensure Pass PGOInstrumentationUsePass is invoked Once in PreLink. -// RUN: %clang_cc1 -O2 -fno-experimental-new-pass-manager -fprofile-instrument-use-path=%t/cs.profdata %s -flto -mllvm -debug-pass=Structure -emit-llvm-bc -o %t/foo_fe.bc 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-PRE -// RUN: %clang_cc1 -O2 -fprofile-instrument-use-path=%t/cs.profdata %s -flto -fexperimental-new-pass-manager -fdebug-pass-manager -emit-llvm-bc -o %t/foo_fe_pm.bc 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-PRE-NEWPM -// CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-PRE: PGOInstrumentationUsePass -// CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-PRE-NOT: PGOInstrumentationGenCreateVarPass -// CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-PRE-NOT: PGOInstrumentationUsePass -// CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-PRE-NEWPM: Running pass: PGOInstrumentationUse -// CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-PRE-NEWPM-NOT: Running pass: PGOInstrumentationGenCreateVar -// CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-PRE-NEWPM-NOT: Running pass: PGOInstrumentationUse +// RUN: %clang_cc1 -O2 -fprofile-instrument-use-path=%t/cs.profdata %s -flto -fdebug-pass-manager -emit-llvm-bc -o %t/foo_fe_pm.bc 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-PRE +// CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-PRE: Running pass: PGOInstrumentationUse +// CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-PRE-NOT: Running pass: PGOInstrumentationGenCreateVar +// CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-PRE-NOT: Running pass: PGOInstrumentationUse // // Ensure Pass PGOInstrumentationUSEPass is invoked in PostLink. -// RUN: %clang_cc1 -O2 -fno-experimental-new-pass-manager -x ir %t/foo_fe.bc -fprofile-instrument-use-path=%t/cs.profdata -flto -emit-llvm -mllvm -debug-pass=Structure -o - 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-POST -// RUN: %clang_cc1 -O2 -x ir %t/foo_fe_pm.bc -fexperimental-new-pass-manager -fdebug-pass-manager -fprofile-instrument-use-path=%t/cs.profdata -flto -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-POST-NEWPM -// CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-POST: PGOInstrumentationUsePass -// CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-POST-NOT: PGOInstrumentationUsePass -// CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-POST-NEWPM: Running pass: PGOInstrumentationUse -// CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-POST-NEWPM-NOT: Running pass: PGOInstrumentationUse +// RUN: %clang_cc1 -O2 -x ir %t/foo_fe_pm.bc -fdebug-pass-manager -fprofile-instrument-use-path=%t/cs.profdata -flto -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-POST +// CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-POST: Running pass: PGOInstrumentationUse +// CHECK-CSPGOUSEPASS-INVOKED-INSTR-USE-POST-NOT: Running pass: PGOInstrumentationUse diff --git a/clang/test/CodeGen/debug-info-block-vars.c b/clang/test/CodeGen/debug-info-block-vars.c index 05758a6cfc72e28842fe0da021474a821a3e6086..e0bb61e5e85f2cd7fa9769094ad4b8259ee62d5c 100644 --- a/clang/test/CodeGen/debug-info-block-vars.c +++ b/clang/test/CodeGen/debug-info-block-vars.c @@ -4,7 +4,7 @@ // RUN: -triple x86_64-apple-darwin -o - %s \ // RUN: | FileCheck --check-prefix=CHECK-OPT %s -// CHECK: define internal void @__f_block_invoke(i8* noundef %.block_descriptor) +// CHECK: define internal void @__f_block_invoke(i8* %.block_descriptor) // CHECK: %.block_descriptor.addr = alloca i8*, align 8 // CHECK: %block.addr = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 // CHECK: store i8* %.block_descriptor, i8** %.block_descriptor.addr, align 8 diff --git a/clang/test/CodeGen/debug-info-pseudo-probe.cpp b/clang/test/CodeGen/debug-info-pseudo-probe.cpp index b1b9c8e342a0d89a442eb1b92c8e24edf385a11d..78a684cd1f394ea7df566ace84ebbc6479997a27 100644 --- a/clang/test/CodeGen/debug-info-pseudo-probe.cpp +++ b/clang/test/CodeGen/debug-info-pseudo-probe.cpp @@ -6,7 +6,7 @@ int foo() { return 0; } -// PLAIN: define dso_local noundef i32 @_Z3foov() +// PLAIN: define dso_local i32 @_Z3foov() // PLAIN: distinct !DISubprogram(name: "foo", scope: -// MANGLE: define dso_local noundef i32 @_Z3foov() +// MANGLE: define dso_local i32 @_Z3foov() // MANGLE: distinct !DISubprogram(name: "foo", linkageName: "_Z3foov" diff --git a/clang/test/CodeGen/decl.c b/clang/test/CodeGen/decl.c index 1ceb8fa9e310584600d5c85e1ca7598e6013371f..22c2d034ad61d34005847afdf0327172280c9c41 100644 --- a/clang/test/CodeGen/decl.c +++ b/clang/test/CodeGen/decl.c @@ -28,7 +28,7 @@ void test2() { // CHECK: @test2() // CHECK: %x = alloca [13 x i32] // CHECK: call void @llvm.memcpy - // CHECK: call{{.*}}@foo{{.*}}i32* noundef % + // CHECK: call{{.*}}@foo{{.*}}i32* % } diff --git a/clang/test/CodeGen/default-address-space.c b/clang/test/CodeGen/default-address-space.c index fd719df3d8c3ecb3f3ca00c8d61f3d7aac6a2a9a..2707455afde17901eb8ebbec6ff1a85a47e4d724 100644 --- a/clang/test/CodeGen/default-address-space.c +++ b/clang/test/CodeGen/default-address-space.c @@ -15,7 +15,7 @@ int *B; // CHECK: load i32, i32* addrspacecast{{[^@]+}} @foo int test1() { return foo; } -// CHECK-LABEL: define{{.*}} i32 @test2(i32 noundef %i) +// CHECK-LABEL: define{{.*}} i32 @test2(i32 %i) // CHECK: %[[addr:.*]] = getelementptr // CHECK: load i32, i32* %[[addr]] // CHECK-NEXT: ret i32 @@ -30,7 +30,7 @@ void test3() { *A = *B; } -// CHECK-LABEL: define{{.*}} void @test4(i32* noundef %a) +// CHECK-LABEL: define{{.*}} void @test4(i32* %a) // CHECK: %[[alloca:.*]] = alloca i32*, align 8, addrspace(5) // CHECK: %[[a_addr:.*]] ={{.*}} addrspacecast{{.*}} %[[alloca]] to i32** // CHECK: store i32* %a, i32** %[[a_addr]] diff --git a/clang/test/CodeGen/exceptions-seh-finally.c b/clang/test/CodeGen/exceptions-seh-finally.c index cf123a6279ae0cb3d0535c8d1524cd1a590b7964..8aafeb23090d01f4f7901fe0440efb62b276cba7 100644 --- a/clang/test/CodeGen/exceptions-seh-finally.c +++ b/clang/test/CodeGen/exceptions-seh-finally.c @@ -21,13 +21,13 @@ void basic_finally(void) { // // CHECK: [[invoke_cont]] // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK: call void @"?fin$0@0@basic_finally@@"({{i8 noundef( zeroext)?}} 0, i8* noundef %[[fp]]) +// CHECK: call void @"?fin$0@0@basic_finally@@"({{i8( zeroext)?}} 0, i8* %[[fp]]) // CHECK-NEXT: ret void // // CHECK: [[lpad]] // CHECK-NEXT: %[[pad:[^ ]*]] = cleanuppad // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK: call void @"?fin$0@0@basic_finally@@"({{i8 noundef( zeroext)?}} 1, i8* noundef %[[fp]]) +// CHECK: call void @"?fin$0@0@basic_finally@@"({{i8( zeroext)?}} 1, i8* %[[fp]]) // CHECK-NEXT: cleanupret from %[[pad]] unwind to caller // CHECK: define internal void @"?fin$0@0@basic_finally@@"({{.*}}) @@ -61,7 +61,7 @@ l: // // CHECK: [[invoke_cont]] // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK: call void @"?fin$0@0@label_in_finally@@"({{i8 noundef( zeroext)?}} 0, i8* noundef %[[fp]]) +// CHECK: call void @"?fin$0@0@label_in_finally@@"({{i8( zeroext)?}} 0, i8* %[[fp]]) // CHECK: ret void // CHECK: define internal void @"?fin$0@0@label_in_finally@@"({{.*}}) @@ -89,16 +89,16 @@ void use_abnormal_termination(void) { // // CHECK: [[invoke_cont]] // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK: call void @"?fin$0@0@use_abnormal_termination@@"({{i8 noundef( zeroext)?}} 0, i8* noundef %[[fp]]) +// CHECK: call void @"?fin$0@0@use_abnormal_termination@@"({{i8( zeroext)?}} 0, i8* %[[fp]]) // CHECK: ret void // // CHECK: [[lpad]] // CHECK-NEXT: %[[pad:[^ ]*]] = cleanuppad // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK: call void @"?fin$0@0@use_abnormal_termination@@"({{i8 noundef( zeroext)?}} 1, i8* noundef %[[fp]]) +// CHECK: call void @"?fin$0@0@use_abnormal_termination@@"({{i8( zeroext)?}} 1, i8* %[[fp]]) // CHECK-NEXT: cleanupret from %[[pad]] unwind to caller -// CHECK: define internal void @"?fin$0@0@use_abnormal_termination@@"({{i8 noundef( zeroext)?}} %[[abnormal:abnormal_termination]], i8* noundef %frame_pointer) +// CHECK: define internal void @"?fin$0@0@use_abnormal_termination@@"({{i8( zeroext)?}} %[[abnormal:abnormal_termination]], i8* %frame_pointer) // CHECK-SAME: [[finally_attrs]] // CHECK: %[[abnormal_zext:[^ ]*]] = zext i8 %[[abnormal]] to i32 // CHECK: store i32 %[[abnormal_zext]], i32* @crashed @@ -280,7 +280,7 @@ void finally_with_func() { } // CHECK-LABEL: define internal void @"?fin$0@0@finally_with_func@@"({{[^)]*}}) -// CHECK: call void @cleanup_with_func(i8* noundef getelementptr inbounds ([18 x i8], [18 x i8]* @"??_C@_0BC@COAGBPGM@finally_with_func?$AA@", i{{32|64}} 0, i{{32|64}} 0)) +// CHECK: call void @cleanup_with_func(i8* getelementptr inbounds ([18 x i8], [18 x i8]* @"??_C@_0BC@COAGBPGM@finally_with_func?$AA@", i{{32|64}} 0, i{{32|64}} 0)) // Look for the absence of noinline. nounwind is expected; any further // attributes should be string attributes. diff --git a/clang/test/CodeGen/exceptions-seh-leave.c b/clang/test/CodeGen/exceptions-seh-leave.c index d8f60f2a874e5765e350793e3efd19c004cfbc68..e977e32e9fa4a5f2179107830f571ff219f45f33 100644 --- a/clang/test/CodeGen/exceptions-seh-leave.c +++ b/clang/test/CodeGen/exceptions-seh-leave.c @@ -75,7 +75,7 @@ int __leave_with___finally_simple() { // CHECK-NOT: store i32 23 // CHECK: [[tryleave]] // CHECK-NEXT: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK-NEXT: call void @"?fin$0@0@__leave_with___finally_simple@@"(i8 noundef 0, i8* noundef %[[fp]]) +// CHECK-NEXT: call void @"?fin$0@0@__leave_with___finally_simple@@"(i8 0, i8* %[[fp]]) // __finally block doesn't return, __finally.cont doesn't exist. int __leave_with___finally_noreturn() { @@ -95,7 +95,7 @@ int __leave_with___finally_noreturn() { // CHECK-NOT: store i32 23 // CHECK: [[tryleave]] // CHECK-NEXT: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK-NEXT: call void @"?fin$0@0@__leave_with___finally_noreturn@@"(i8 noundef 0, i8* noundef %[[fp]]) +// CHECK-NEXT: call void @"?fin$0@0@__leave_with___finally_noreturn@@"(i8 0, i8* %[[fp]]) // The "normal" case. int __leave_with___finally() { @@ -119,7 +119,7 @@ int __leave_with___finally() { // CHECK-NOT: store i32 23 // CHECK: [[tryleave]] // CHECK-NEXT: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK-NEXT: call void @"?fin$0@0@__leave_with___finally@@"(i8 noundef 0, i8* noundef %[[fp]]) +// CHECK-NEXT: call void @"?fin$0@0@__leave_with___finally@@"(i8 0, i8* %[[fp]]) ////////////////////////////////////////////////////////////////////////////// @@ -149,7 +149,7 @@ int nested___except___finally() { // CHECK: [[g1_cont1]] // CHECK-NEXT: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK-NEXT: invoke void @"?fin$0@0@nested___except___finally@@"(i8 noundef 0, i8* noundef %[[fp]]) +// CHECK-NEXT: invoke void @"?fin$0@0@nested___except___finally@@"(i8 0, i8* %[[fp]]) // CHECK-NEXT: to label %[[fin_cont:.*]] unwind label %[[g2_lpad:.*]] // CHECK: [[fin_cont]] @@ -159,7 +159,7 @@ int nested___except___finally() { // CHECK: [[g1_lpad]] // CHECK-NEXT: cleanuppad // CHECK-NEXT: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK-NEXT: invoke void @"?fin$0@0@nested___except___finally@@"(i8 noundef 1, i8* noundef %[[fp]]) +// CHECK-NEXT: invoke void @"?fin$0@0@nested___except___finally@@"(i8 1, i8* %[[fp]]) // CHECK-NEXT: to label %[[g1_resume:.*]] unwind label %[[g2_lpad]] // CHECK: cleanupret {{.*}} unwind label %[[g2_lpad]] @@ -171,7 +171,7 @@ int nested___except___finally() { // CHECK: [[trycont]] // CHECK-NEXT: ret i32 1 -// CHECK-LABEL: define internal void @"?fin$0@0@nested___except___finally@@"(i8 noundef %abnormal_termination, i8* noundef %frame_pointer) +// CHECK-LABEL: define internal void @"?fin$0@0@nested___except___finally@@"(i8 %abnormal_termination, i8* %frame_pointer) // CHECK: call void @g() // CHECK: unreachable @@ -271,16 +271,16 @@ int nested___finally___except() { // CHECK: [[tryleave]] // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK-NEXT: call void @"?fin$0@0@nested___finally___except@@"(i8 noundef 0, i8* noundef %[[fp]]) +// CHECK-NEXT: call void @"?fin$0@0@nested___finally___except@@"(i8 0, i8* %[[fp]]) // CHECK-NEXT: ret i32 1 // CHECK: [[g2_lpad]] // CHECK: cleanuppad // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK-NEXT: call void @"?fin$0@0@nested___finally___except@@"(i8 noundef 1, i8* noundef %[[fp]]) +// CHECK-NEXT: call void @"?fin$0@0@nested___finally___except@@"(i8 1, i8* %[[fp]]) // CHECK: cleanupret {{.*}} unwind to caller -// CHECK-LABEL: define internal void @"?fin$0@0@nested___finally___except@@"(i8 noundef %abnormal_termination, i8* noundef %frame_pointer) +// CHECK-LABEL: define internal void @"?fin$0@0@nested___finally___except@@"(i8 %abnormal_termination, i8* %frame_pointer) // CHECK: ret void int nested___finally___finally() { @@ -310,19 +310,19 @@ int nested___finally___finally() { // CHECK: [[g1_cont]] // CHECK: store i32 16, i32* %[[myres:[^ ]*]], // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK-NEXT: invoke void @"?fin$1@0@nested___finally___finally@@"(i8 noundef 0, i8* noundef %[[fp]]) +// CHECK-NEXT: invoke void @"?fin$1@0@nested___finally___finally@@"(i8 0, i8* %[[fp]]) // CHECK-NEXT: to label %[[finally_cont:.*]] unwind label %[[g2_lpad:.*]] // CHECK: [[finally_cont]] // CHECK: store i32 51, i32* %[[myres]] // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK-NEXT: call void @"?fin$0@0@nested___finally___finally@@"(i8 noundef 0, i8* noundef %[[fp]]) +// CHECK-NEXT: call void @"?fin$0@0@nested___finally___finally@@"(i8 0, i8* %[[fp]]) // CHECK-NEXT: ret i32 1 // CHECK: [[g1_lpad]] // CHECK-NEXT: %[[padtoken:[^ ]*]] = cleanuppad within none [] // CHECK-NEXT: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK-NEXT: invoke void @"?fin$1@0@nested___finally___finally@@"(i8 noundef 1, i8* noundef %[[fp]]) +// CHECK-NEXT: invoke void @"?fin$1@0@nested___finally___finally@@"(i8 1, i8* %[[fp]]) // CHECK-NEXT: to label %[[finally_cont2:.*]] unwind label %[[g2_lpad]] // CHECK: [[finally_cont2]] // CHECK: cleanupret from %[[padtoken]] unwind label %[[g2_lpad]] @@ -330,12 +330,12 @@ int nested___finally___finally() { // CHECK: [[g2_lpad]] // CHECK-NEXT: %[[padtoken:[^ ]*]] = cleanuppad within none [] // CHECK-NEXT: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK-NEXT: call void @"?fin$0@0@nested___finally___finally@@"(i8 noundef 1, i8* noundef %[[fp]]) +// CHECK-NEXT: call void @"?fin$0@0@nested___finally___finally@@"(i8 1, i8* %[[fp]]) // CHECK: cleanupret from %[[padtoken]] unwind to caller -// CHECK-LABEL: define internal void @"?fin$0@0@nested___finally___finally@@"(i8 noundef %abnormal_termination, i8* noundef %frame_pointer) +// CHECK-LABEL: define internal void @"?fin$0@0@nested___finally___finally@@"(i8 %abnormal_termination, i8* %frame_pointer) // CHECK: ret void -// CHECK-LABEL: define internal void @"?fin$1@0@nested___finally___finally@@"(i8 noundef %abnormal_termination, i8* noundef %frame_pointer) +// CHECK-LABEL: define internal void @"?fin$1@0@nested___finally___finally@@"(i8 %abnormal_termination, i8* %frame_pointer) // CHECK: call void @g() // CHECK: unreachable diff --git a/clang/test/CodeGen/exceptions-seh-nested-finally.c b/clang/test/CodeGen/exceptions-seh-nested-finally.c index 332006ab7e2214c53875fa8eae0bd9e460ff0ffc..7385d18f0cd8a42740481f8af6d747cb1b9619c2 100644 --- a/clang/test/CodeGen/exceptions-seh-nested-finally.c +++ b/clang/test/CodeGen/exceptions-seh-nested-finally.c @@ -8,8 +8,8 @@ // Check that the first finally block passes the enclosing function's frame // pointer to the second finally block, instead of generating it via localaddr. -// CHECK-LABEL: define internal void @"?fin$0@0@main@@"({{i8 noundef( zeroext)?}} %abnormal_termination, i8* noundef %frame_pointer) -// CHECK: call void @"?fin$1@0@main@@"({{i8 noundef( zeroext)?}} 0, i8* noundef %frame_pointer) +// CHECK-LABEL: define internal void @"?fin$0@0@main@@"({{i8( zeroext)?}} %abnormal_termination, i8* %frame_pointer) +// CHECK: call void @"?fin$1@0@main@@"({{i8( zeroext)?}} 0, i8* %frame_pointer) int main() { int Check = 0; diff --git a/clang/test/CodeGen/exceptions-seh.c b/clang/test/CodeGen/exceptions-seh.c index 0792e595c76484788f83e2728162345cbf48e7a7..8a54a56d1971dae78d8906a164f68fdeae422399 100644 --- a/clang/test/CodeGen/exceptions-seh.c +++ b/clang/test/CodeGen/exceptions-seh.c @@ -12,7 +12,7 @@ void try_body(int numerator, int denominator, int *myres) { *myres = numerator / denominator; } -// CHECK-LABEL: define dso_local void @try_body(i32 noundef %numerator, i32 noundef %denominator, i32* noundef %myres) +// CHECK-LABEL: define dso_local void @try_body(i32 %numerator, i32 %denominator, i32* %myres) // CHECK: sdiv i32 // CHECK: store i32 %{{.*}}, i32* // CHECK: ret void @@ -29,11 +29,11 @@ int safe_div(int numerator, int denominator, int *res) { return success; } -// CHECK-LABEL: define dso_local i32 @safe_div(i32 noundef %numerator, i32 noundef %denominator, i32* noundef %res) +// CHECK-LABEL: define dso_local i32 @safe_div(i32 %numerator, i32 %denominator, i32* %res) // X64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) // ARM64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) // X86-SAME: personality i8* bitcast (i32 (...)* @_except_handler3 to i8*) -// CHECK: invoke void @try_body(i32 noundef %{{.*}}, i32 noundef %{{.*}}, i32* noundef %{{.*}}) #[[NOINLINE:[0-9]+]] +// CHECK: invoke void @try_body(i32 %{{.*}}, i32 %{{.*}}, i32* %{{.*}}) #[[NOINLINE:[0-9]+]] // CHECK: to label %{{.*}} unwind label %[[catchpad:[^ ]*]] // // CHECK: [[catchpad]] @@ -61,9 +61,9 @@ int safe_div(int numerator, int denominator, int *res) { // X86: ret i32 1 // Mingw uses msvcrt, so it can also use _except_handler3. -// X86-GNU-LABEL: define dso_local i32 @safe_div(i32 noundef %numerator, i32 noundef %denominator, i32* noundef %res) +// X86-GNU-LABEL: define dso_local i32 @safe_div(i32 %numerator, i32 %denominator, i32* %res) // X86-GNU-SAME: personality i8* bitcast (i32 (...)* @_except_handler3 to i8*) -// X64-GNU-LABEL: define dso_local i32 @safe_div(i32 noundef %numerator, i32 noundef %denominator, i32* noundef %res) +// X64-GNU-LABEL: define dso_local i32 @safe_div(i32 %numerator, i32 %denominator, i32* %res) // X64-GNU-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) void j(void); @@ -94,11 +94,11 @@ int filter_expr_capture(void) { // CHECK: %[[rv:[^ ]*]] = load i32, i32* %[[r]] // CHECK: ret i32 %[[rv]] -// X64-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"(i8* noundef %exception_pointers, i8* noundef %frame_pointer) +// X64-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"(i8* %exception_pointers, i8* %frame_pointer) // X64: %[[fp:[^ ]*]] = call i8* @llvm.eh.recoverfp(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %frame_pointer) // X64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %[[fp]], i32 0) // -// ARM64-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"(i8* noundef %exception_pointers, i8* noundef %frame_pointer) +// ARM64-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"(i8* %exception_pointers, i8* %frame_pointer) // ARM64: %[[fp:[^ ]*]] = call i8* @llvm.eh.recoverfp(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %frame_pointer) // ARM64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %[[fp]], i32 0) // @@ -185,7 +185,7 @@ int basic_finally(int g) { } return g; } -// CHECK-LABEL: define dso_local i32 @basic_finally(i32 noundef %g) +// CHECK-LABEL: define dso_local i32 @basic_finally(i32 %g) // X64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) // ARM64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) // X86-SAME: personality i8* bitcast (i32 (...)* @_except_handler3 to i8*) @@ -198,17 +198,17 @@ int basic_finally(int g) { // // CHECK: [[cont]] // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK: call void @"?fin$0@0@basic_finally@@"({{i8 noundef( zeroext)?}} 0, i8* noundef %[[fp]]) +// CHECK: call void @"?fin$0@0@basic_finally@@"({{i8( zeroext)?}} 0, i8* %[[fp]]) // CHECK: load i32, i32* %[[g_addr]], align 4 // CHECK: ret i32 // // CHECK: [[cleanuppad]] // CHECK: %[[padtoken:[^ ]*]] = cleanuppad within none [] // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK: call void @"?fin$0@0@basic_finally@@"({{i8 noundef( zeroext)?}} 1, i8* noundef %[[fp]]) +// CHECK: call void @"?fin$0@0@basic_finally@@"({{i8( zeroext)?}} 1, i8* %[[fp]]) // CHECK: cleanupret from %[[padtoken]] unwind to caller -// CHECK: define internal void @"?fin$0@0@basic_finally@@"({{i8 noundef( zeroext)?}} %abnormal_termination, i8* noundef %frame_pointer) +// CHECK: define internal void @"?fin$0@0@basic_finally@@"({{i8( zeroext)?}} %abnormal_termination, i8* %frame_pointer) // CHECK: call i8* @llvm.localrecover(i8* bitcast (i32 (i32)* @basic_finally to i8*), i8* %frame_pointer, i32 0) // CHECK: load i32, i32* %{{.*}}, align 4 // CHECK: add nsw i32 %{{.*}}, 1 @@ -257,7 +257,7 @@ void finally_capture_twice(int x) { // CHECK: call void (...) @llvm.localescape(i32* [[X]]) // CHECK-NEXT: store i32 {{.*}}, i32* [[X]], align 4 // CHECK-NEXT: [[LOCAL:%.*]] = call i8* @llvm.localaddress() -// CHECK-NEXT: call void [[FINALLY:@.*]](i8 noundef{{ zeroext | }}0, i8* noundef [[LOCAL]]) +// CHECK-NEXT: call void [[FINALLY:@.*]](i8{{ zeroext | }}0, i8* [[LOCAL]]) // CHECK: define internal void [[FINALLY]]( // CHECK: [[LOCAL:%.*]] = call i8* @llvm.localrecover( // CHECK: [[X:%.*]] = bitcast i8* [[LOCAL]] to i32* @@ -282,7 +282,7 @@ int exception_code_in_except(void) { // CHECK-LABEL: define dso_local i32 @exception_code_in_except() // CHECK: %[[ret_slot:[^ ]*]] = alloca i32 // CHECK: %[[code_slot:[^ ]*]] = alloca i32 -// CHECK: invoke void @try_body(i32 noundef 0, i32 noundef 0, i32* noundef null) +// CHECK: invoke void @try_body(i32 0, i32 0, i32* null) // CHECK: %[[pad:[^ ]*]] = catchpad // CHECK: catchret from %[[pad]] // X64: %[[code:[^ ]*]] = call i32 @llvm.eh.exceptioncode(token %[[pad]]) diff --git a/clang/test/CodeGen/exceptions.c b/clang/test/CodeGen/exceptions.c index d69a55568d6e49fcd98db16db6e4be5f4244c5e2..1618add8954257ef21613464453f814c526ca837 100644 --- a/clang/test/CodeGen/exceptions.c +++ b/clang/test/CodeGen/exceptions.c @@ -28,4 +28,4 @@ void test2() { } void test2_helper(int x, int y) { } -// CHECK: invoke void @test2_helper(i32 noundef 5, i32 noundef 6) +// CHECK: invoke void @test2_helper(i32 5, i32 6) diff --git a/clang/test/CodeGen/ext-int-cc.c b/clang/test/CodeGen/ext-int-cc.c index 5614693db73c949e574e3abcf3e2b976cfd79590..1073c63e3c64a8e2b59e36fa6417bf96e80ba63c 100644 --- a/clang/test/CodeGen/ext-int-cc.c +++ b/clang/test/CodeGen/ext-int-cc.c @@ -1,32 +1,32 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-gnu-linux -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=LIN64 -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-windows-pc -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=WIN64 -// RUN: %clang_cc1 -disable-noundef-analysis -triple i386-gnu-linux -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=LIN32 -// RUN: %clang_cc1 -disable-noundef-analysis -triple i386-windows-pc -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=WIN32 -// RUN: %clang_cc1 -disable-noundef-analysis -triple nvptx64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=NVPTX64 -// RUN: %clang_cc1 -disable-noundef-analysis -triple nvptx -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=NVPTX -// RUN: %clang_cc1 -disable-noundef-analysis -triple sparcv9 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=SPARCV9 -// RUN: %clang_cc1 -disable-noundef-analysis -triple sparc -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=SPARC -// RUN: %clang_cc1 -disable-noundef-analysis -triple mips64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=MIPS64 -// RUN: %clang_cc1 -disable-noundef-analysis -triple mips -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=MIPS -// RUN: %clang_cc1 -disable-noundef-analysis -triple spir64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=SPIR64 -// RUN: %clang_cc1 -disable-noundef-analysis -triple spir -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=SPIR -// RUN: %clang_cc1 -disable-noundef-analysis -triple hexagon -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=HEX -// RUN: %clang_cc1 -disable-noundef-analysis -triple lanai -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=LANAI -// RUN: %clang_cc1 -disable-noundef-analysis -triple r600 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=R600 -// RUN: %clang_cc1 -disable-noundef-analysis -triple arc -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=ARC -// RUN: %clang_cc1 -disable-noundef-analysis -triple xcore -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=XCORE -// RUN: %clang_cc1 -disable-noundef-analysis -triple riscv64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=RISCV64 -// RUN: %clang_cc1 -disable-noundef-analysis -triple riscv32 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=RISCV32 -// RUN: %clang_cc1 -disable-noundef-analysis -triple wasm64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=WASM -// RUN: %clang_cc1 -disable-noundef-analysis -triple wasm32 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=WASM -// RUN: %clang_cc1 -disable-noundef-analysis -triple systemz -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=SYSTEMZ -// RUN: %clang_cc1 -disable-noundef-analysis -triple ppc64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=PPC64 -// RUN: %clang_cc1 -disable-noundef-analysis -triple ppc -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=PPC32 -// RUN: %clang_cc1 -disable-noundef-analysis -triple aarch64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=AARCH64 -// RUN: %clang_cc1 -disable-noundef-analysis -triple aarch64 -target-abi darwinpcs -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=AARCH64DARWIN -// RUN: %clang_cc1 -disable-noundef-analysis -triple arm64_32-apple-ios -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=AARCH64 -// RUN: %clang_cc1 -disable-noundef-analysis -triple arm64_32-apple-ios -target-abi darwinpcs -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=AARCH64DARWIN -// RUN: %clang_cc1 -disable-noundef-analysis -triple arm -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=ARM +// RUN: %clang_cc1 -triple x86_64-gnu-linux -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=LIN64 +// RUN: %clang_cc1 -triple x86_64-windows-pc -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=WIN64 +// RUN: %clang_cc1 -triple i386-gnu-linux -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=LIN32 +// RUN: %clang_cc1 -triple i386-windows-pc -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=WIN32 +// RUN: %clang_cc1 -triple nvptx64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=NVPTX64 +// RUN: %clang_cc1 -triple nvptx -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=NVPTX +// RUN: %clang_cc1 -triple sparcv9 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=SPARCV9 +// RUN: %clang_cc1 -triple sparc -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=SPARC +// RUN: %clang_cc1 -triple mips64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=MIPS64 +// RUN: %clang_cc1 -triple mips -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=MIPS +// RUN: %clang_cc1 -triple spir64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=SPIR64 +// RUN: %clang_cc1 -triple spir -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=SPIR +// RUN: %clang_cc1 -triple hexagon -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=HEX +// RUN: %clang_cc1 -triple lanai -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=LANAI +// RUN: %clang_cc1 -triple r600 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=R600 +// RUN: %clang_cc1 -triple arc -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=ARC +// RUN: %clang_cc1 -triple xcore -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=XCORE +// RUN: %clang_cc1 -triple riscv64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=RISCV64 +// RUN: %clang_cc1 -triple riscv32 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=RISCV32 +// RUN: %clang_cc1 -triple wasm64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=WASM +// RUN: %clang_cc1 -triple wasm32 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=WASM +// RUN: %clang_cc1 -triple systemz -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=SYSTEMZ +// RUN: %clang_cc1 -triple ppc64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=PPC64 +// RUN: %clang_cc1 -triple ppc -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=PPC32 +// RUN: %clang_cc1 -triple aarch64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=AARCH64 +// RUN: %clang_cc1 -triple aarch64 -target-abi darwinpcs -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=AARCH64DARWIN +// RUN: %clang_cc1 -triple arm64_32-apple-ios -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=AARCH64 +// RUN: %clang_cc1 -triple arm64_32-apple-ios -target-abi darwinpcs -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=AARCH64DARWIN +// RUN: %clang_cc1 -triple arm -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=ARM // Make sure 128 and 64 bit versions are passed like integers, and that >128 // is passed indirectly. diff --git a/clang/test/CodeGen/extend-arg-64.c b/clang/test/CodeGen/extend-arg-64.c index 32e1c913eaf70c8dfa14db9b1307d9ab1e8210e0..8cdbda8e4ff5b47aa90b69cabc4820bf56f99f38 100644 --- a/clang/test/CodeGen/extend-arg-64.c +++ b/clang/test/CodeGen/extend-arg-64.c @@ -59,7 +59,7 @@ int test() { // CHECKEXT: [[TAG_s8:%.*]] = load i8, i8* @s8 // CHECKEXT: [[CONV_s8:%.*]] = sext i8 [[TAG_s8]] to i64 - // CHECKEXT: call{{.*}} @vararg(i32 noundef %0, i64 noundef [[CONV_u32]], i64 noundef [[CONV_s32]], i64 noundef [[CONV_u16]], i64 noundef [[CONV_s16]], i64 noundef [[CONV_u8]], i64 noundef [[CONV_s8]] + // CHECKEXT: call{{.*}} @vararg(i32 %0, i64 [[CONV_u32]], i64 [[CONV_s32]], i64 [[CONV_u16]], i64 [[CONV_s16]], i64 [[CONV_u8]], i64 [[CONV_s8]] int sum = 0; sum = vararg(sum, u32, s32, u16, s16, u8, s8); diff --git a/clang/test/CodeGen/fp-function-attrs.cpp b/clang/test/CodeGen/fp-function-attrs.cpp index f975446f61d6e8b33d4d3a7b4527e07c9e756931..8a126d0c55d00feec72e1a46679198df5e25cf50 100644 --- a/clang/test/CodeGen/fp-function-attrs.cpp +++ b/clang/test/CodeGen/fp-function-attrs.cpp @@ -7,7 +7,7 @@ float test_default(float a, float b, float c) { return tmp; } -// CHECK: define{{.*}} float @_Z12test_defaultfff(float noundef %a, float noundef %b, float noundef %c) [[FAST_ATTRS:#[0-9]+]] +// CHECK: define{{.*}} float @_Z12test_defaultfff(float %a, float %b, float %c) [[FAST_ATTRS:#[0-9]+]] // CHECK: fadd fast float {{%.+}}, {{%.+}} // CHECK: fadd fast float {{%.+}}, {{%.+}} @@ -21,7 +21,7 @@ float test_precise_on_pragma(float a, float b, float c) { return tmp; } -// CHECK: define{{.*}} float @_Z22test_precise_on_pragmafff(float noundef %a, float noundef %b, float noundef %c) [[PRECISE_ATTRS:#[0-9]+]] +// CHECK: define{{.*}} float @_Z22test_precise_on_pragmafff(float %a, float %b, float %c) [[PRECISE_ATTRS:#[0-9]+]] // CHECK: fadd float {{%.+}}, {{%.+}} // CHECK: fadd fast float {{%.+}}, {{%.+}} @@ -35,7 +35,7 @@ float test_reassociate_off_pragma(float a, float b, float c) { return tmp; } -// CHECK: define{{.*}} float @_Z27test_reassociate_off_pragmafff(float noundef %a, float noundef %b, float noundef %c) [[NOREASSOC_ATTRS:#[0-9]+]] +// CHECK: define{{.*}} float @_Z27test_reassociate_off_pragmafff(float %a, float %b, float %c) [[NOREASSOC_ATTRS:#[0-9]+]] // CHECK: fadd nnan ninf nsz arcp contract afn float {{%.+}}, {{%.+}} // CHECK: fadd fast float {{%.+}}, {{%.+}} diff --git a/clang/test/CodeGen/fp-options-to-fast-math-flags.c b/clang/test/CodeGen/fp-options-to-fast-math-flags.c index 129e8c1bd6faf2c27b1a76ea8b1e633f0657bb98..ce2522f81a8ee8b38d900742634e1d8785ec87c1 100644 --- a/clang/test/CodeGen/fp-options-to-fast-math-flags.c +++ b/clang/test/CodeGen/fp-options-to-fast-math-flags.c @@ -14,29 +14,29 @@ float test(float a) { return a + fn(a); } -// CHECK-PRECISE: [[CALL_RES:%.+]] = call float @fn(float noundef {{%.+}}) +// CHECK-PRECISE: [[CALL_RES:%.+]] = call float @fn(float {{%.+}}) // CHECK-PRECISE: {{%.+}} = fadd float {{%.+}}, [[CALL_RES]] -// CHECK-NO-NANS: [[CALL_RES:%.+]] = call nnan float @fn(float noundef {{%.+}}) +// CHECK-NO-NANS: [[CALL_RES:%.+]] = call nnan float @fn(float {{%.+}}) // CHECK-NO-NANS: {{%.+}} = fadd nnan float {{%.+}}, [[CALL_RES]] -// CHECK-NO-INFS: [[CALL_RES:%.+]] = call ninf float @fn(float noundef {{%.+}}) +// CHECK-NO-INFS: [[CALL_RES:%.+]] = call ninf float @fn(float {{%.+}}) // CHECK-NO-INFS: {{%.+}} = fadd ninf float {{%.+}}, [[CALL_RES]] -// CHECK-FINITE: [[CALL_RES:%.+]] = call nnan ninf float @fn(float noundef {{%.+}}) +// CHECK-FINITE: [[CALL_RES:%.+]] = call nnan ninf float @fn(float {{%.+}}) // CHECK-FINITE: {{%.+}} = fadd nnan ninf float {{%.+}}, [[CALL_RES]] -// CHECK-NO-SIGNED-ZEROS: [[CALL_RES:%.+]] = call nsz float @fn(float noundef {{%.+}}) +// CHECK-NO-SIGNED-ZEROS: [[CALL_RES:%.+]] = call nsz float @fn(float {{%.+}}) // CHECK-NO-SIGNED-ZEROS: {{%.+}} = fadd nsz float {{%.+}}, [[CALL_RES]] -// CHECK-REASSOC: [[CALL_RES:%.+]] = call reassoc float @fn(float noundef {{%.+}}) +// CHECK-REASSOC: [[CALL_RES:%.+]] = call reassoc float @fn(float {{%.+}}) // CHECK-REASSOC: {{%.+}} = fadd reassoc float {{%.+}}, [[CALL_RES]] -// CHECK-RECIP: [[CALL_RES:%.+]] = call arcp float @fn(float noundef {{%.+}}) +// CHECK-RECIP: [[CALL_RES:%.+]] = call arcp float @fn(float {{%.+}}) // CHECK-RECIP: {{%.+}} = fadd arcp float {{%.+}}, [[CALL_RES]] -// CHECK-UNSAFE: [[CALL_RES:%.+]] = call reassoc nsz arcp afn float @fn(float noundef {{%.+}}) +// CHECK-UNSAFE: [[CALL_RES:%.+]] = call reassoc nsz arcp afn float @fn(float {{%.+}}) // CHECK-UNSAFE: {{%.+}} = fadd reassoc nsz arcp afn float {{%.+}}, [[CALL_RES]] -// CHECK-FAST: [[CALL_RES:%.+]] = call reassoc nnan ninf nsz arcp afn float @fn(float noundef {{%.+}}) +// CHECK-FAST: [[CALL_RES:%.+]] = call reassoc nnan ninf nsz arcp afn float @fn(float {{%.+}}) // CHECK-FAST: {{%.+}} = fadd reassoc nnan ninf nsz arcp afn float {{%.+}}, [[CALL_RES]] diff --git a/clang/test/CodeGen/fpconstrained-cmp-double.c b/clang/test/CodeGen/fpconstrained-cmp-double.c index 83446fc10595e1a4559f740f9d973f566ce0f7f4..335b7e49b01dfcb1c8c5a00857cb1a84f259969e 100644 --- a/clang/test/CodeGen/fpconstrained-cmp-double.c +++ b/clang/test/CodeGen/fpconstrained-cmp-double.c @@ -6,7 +6,7 @@ // RUN: %clang_cc1 -frounding-math -ffp-exception-behavior=maytrap -fexperimental-strict-floating-point -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=MAYTRAP _Bool QuietEqual(double f1, double f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietEqual(double noundef %f1, double noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietEqual(double %f1, double %f2) // FCMP: fcmp oeq double %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f64(double %{{.*}}, double %{{.*}}, metadata !"oeq", metadata !"fpexcept.ignore") @@ -18,7 +18,7 @@ _Bool QuietEqual(double f1, double f2) { } _Bool QuietNotEqual(double f1, double f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietNotEqual(double noundef %f1, double noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietNotEqual(double %f1, double %f2) // FCMP: fcmp une double %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f64(double %{{.*}}, double %{{.*}}, metadata !"une", metadata !"fpexcept.ignore") @@ -30,7 +30,7 @@ _Bool QuietNotEqual(double f1, double f2) { } _Bool SignalingLess(double f1, double f2) { - // CHECK-LABEL: define {{.*}}i1 @SignalingLess(double noundef %f1, double noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @SignalingLess(double %f1, double %f2) // FCMP: fcmp olt double %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmps.f64(double %{{.*}}, double %{{.*}}, metadata !"olt", metadata !"fpexcept.ignore") @@ -42,7 +42,7 @@ _Bool SignalingLess(double f1, double f2) { } _Bool SignalingLessEqual(double f1, double f2) { - // CHECK-LABEL: define {{.*}}i1 @SignalingLessEqual(double noundef %f1, double noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @SignalingLessEqual(double %f1, double %f2) // FCMP: fcmp ole double %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmps.f64(double %{{.*}}, double %{{.*}}, metadata !"ole", metadata !"fpexcept.ignore") @@ -54,7 +54,7 @@ _Bool SignalingLessEqual(double f1, double f2) { } _Bool SignalingGreater(double f1, double f2) { - // CHECK-LABEL: define {{.*}}i1 @SignalingGreater(double noundef %f1, double noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @SignalingGreater(double %f1, double %f2) // FCMP: fcmp ogt double %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmps.f64(double %{{.*}}, double %{{.*}}, metadata !"ogt", metadata !"fpexcept.ignore") @@ -66,7 +66,7 @@ _Bool SignalingGreater(double f1, double f2) { } _Bool SignalingGreaterEqual(double f1, double f2) { - // CHECK-LABEL: define {{.*}}i1 @SignalingGreaterEqual(double noundef %f1, double noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @SignalingGreaterEqual(double %f1, double %f2) // FCMP: fcmp oge double %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmps.f64(double %{{.*}}, double %{{.*}}, metadata !"oge", metadata !"fpexcept.ignore") @@ -78,7 +78,7 @@ _Bool SignalingGreaterEqual(double f1, double f2) { } _Bool QuietLess(double f1, double f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietLess(double noundef %f1, double noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietLess(double %f1, double %f2) // FCMP: fcmp olt double %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f64(double %{{.*}}, double %{{.*}}, metadata !"olt", metadata !"fpexcept.ignore") @@ -90,7 +90,7 @@ _Bool QuietLess(double f1, double f2) { } _Bool QuietLessEqual(double f1, double f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietLessEqual(double noundef %f1, double noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietLessEqual(double %f1, double %f2) // FCMP: fcmp ole double %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f64(double %{{.*}}, double %{{.*}}, metadata !"ole", metadata !"fpexcept.ignore") @@ -102,7 +102,7 @@ _Bool QuietLessEqual(double f1, double f2) { } _Bool QuietGreater(double f1, double f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietGreater(double noundef %f1, double noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietGreater(double %f1, double %f2) // FCMP: fcmp ogt double %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f64(double %{{.*}}, double %{{.*}}, metadata !"ogt", metadata !"fpexcept.ignore") @@ -114,7 +114,7 @@ _Bool QuietGreater(double f1, double f2) { } _Bool QuietGreaterEqual(double f1, double f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietGreaterEqual(double noundef %f1, double noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietGreaterEqual(double %f1, double %f2) // FCMP: fcmp oge double %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f64(double %{{.*}}, double %{{.*}}, metadata !"oge", metadata !"fpexcept.ignore") @@ -126,7 +126,7 @@ _Bool QuietGreaterEqual(double f1, double f2) { } _Bool QuietLessGreater(double f1, double f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietLessGreater(double noundef %f1, double noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietLessGreater(double %f1, double %f2) // FCMP: fcmp one double %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f64(double %{{.*}}, double %{{.*}}, metadata !"one", metadata !"fpexcept.ignore") @@ -138,7 +138,7 @@ _Bool QuietLessGreater(double f1, double f2) { } _Bool QuietUnordered(double f1, double f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietUnordered(double noundef %f1, double noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietUnordered(double %f1, double %f2) // FCMP: fcmp uno double %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f64(double %{{.*}}, double %{{.*}}, metadata !"uno", metadata !"fpexcept.ignore") diff --git a/clang/test/CodeGen/fpconstrained-cmp-float.c b/clang/test/CodeGen/fpconstrained-cmp-float.c index 0854774d840e83114683d622db5375e73042b6ba..e9667904122baee88d21d33866be4410b68d3379 100644 --- a/clang/test/CodeGen/fpconstrained-cmp-float.c +++ b/clang/test/CodeGen/fpconstrained-cmp-float.c @@ -6,7 +6,7 @@ // RUN: %clang_cc1 -frounding-math -ffp-exception-behavior=maytrap -fexperimental-strict-floating-point -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=MAYTRAP _Bool QuietEqual(float f1, float f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietEqual(float noundef %f1, float noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietEqual(float %f1, float %f2) // FCMP: fcmp oeq float %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f32(float %{{.*}}, float %{{.*}}, metadata !"oeq", metadata !"fpexcept.ignore") @@ -18,7 +18,7 @@ _Bool QuietEqual(float f1, float f2) { } _Bool QuietNotEqual(float f1, float f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietNotEqual(float noundef %f1, float noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietNotEqual(float %f1, float %f2) // FCMP: fcmp une float %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f32(float %{{.*}}, float %{{.*}}, metadata !"une", metadata !"fpexcept.ignore") @@ -30,7 +30,7 @@ _Bool QuietNotEqual(float f1, float f2) { } _Bool SignalingLess(float f1, float f2) { - // CHECK-LABEL: define {{.*}}i1 @SignalingLess(float noundef %f1, float noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @SignalingLess(float %f1, float %f2) // FCMP: fcmp olt float %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmps.f32(float %{{.*}}, float %{{.*}}, metadata !"olt", metadata !"fpexcept.ignore") @@ -42,7 +42,7 @@ _Bool SignalingLess(float f1, float f2) { } _Bool SignalingLessEqual(float f1, float f2) { - // CHECK-LABEL: define {{.*}}i1 @SignalingLessEqual(float noundef %f1, float noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @SignalingLessEqual(float %f1, float %f2) // FCMP: fcmp ole float %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmps.f32(float %{{.*}}, float %{{.*}}, metadata !"ole", metadata !"fpexcept.ignore") @@ -54,7 +54,7 @@ _Bool SignalingLessEqual(float f1, float f2) { } _Bool SignalingGreater(float f1, float f2) { - // CHECK-LABEL: define {{.*}}i1 @SignalingGreater(float noundef %f1, float noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @SignalingGreater(float %f1, float %f2) // FCMP: fcmp ogt float %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmps.f32(float %{{.*}}, float %{{.*}}, metadata !"ogt", metadata !"fpexcept.ignore") @@ -66,7 +66,7 @@ _Bool SignalingGreater(float f1, float f2) { } _Bool SignalingGreaterEqual(float f1, float f2) { - // CHECK-LABEL: define {{.*}}i1 @SignalingGreaterEqual(float noundef %f1, float noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @SignalingGreaterEqual(float %f1, float %f2) // FCMP: fcmp oge float %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmps.f32(float %{{.*}}, float %{{.*}}, metadata !"oge", metadata !"fpexcept.ignore") @@ -78,7 +78,7 @@ _Bool SignalingGreaterEqual(float f1, float f2) { } _Bool QuietLess(float f1, float f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietLess(float noundef %f1, float noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietLess(float %f1, float %f2) // FCMP: fcmp olt float %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f32(float %{{.*}}, float %{{.*}}, metadata !"olt", metadata !"fpexcept.ignore") @@ -90,7 +90,7 @@ _Bool QuietLess(float f1, float f2) { } _Bool QuietLessEqual(float f1, float f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietLessEqual(float noundef %f1, float noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietLessEqual(float %f1, float %f2) // FCMP: fcmp ole float %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f32(float %{{.*}}, float %{{.*}}, metadata !"ole", metadata !"fpexcept.ignore") @@ -102,7 +102,7 @@ _Bool QuietLessEqual(float f1, float f2) { } _Bool QuietGreater(float f1, float f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietGreater(float noundef %f1, float noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietGreater(float %f1, float %f2) // FCMP: fcmp ogt float %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f32(float %{{.*}}, float %{{.*}}, metadata !"ogt", metadata !"fpexcept.ignore") @@ -114,7 +114,7 @@ _Bool QuietGreater(float f1, float f2) { } _Bool QuietGreaterEqual(float f1, float f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietGreaterEqual(float noundef %f1, float noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietGreaterEqual(float %f1, float %f2) // FCMP: fcmp oge float %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f32(float %{{.*}}, float %{{.*}}, metadata !"oge", metadata !"fpexcept.ignore") @@ -126,7 +126,7 @@ _Bool QuietGreaterEqual(float f1, float f2) { } _Bool QuietLessGreater(float f1, float f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietLessGreater(float noundef %f1, float noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietLessGreater(float %f1, float %f2) // FCMP: fcmp one float %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f32(float %{{.*}}, float %{{.*}}, metadata !"one", metadata !"fpexcept.ignore") @@ -138,7 +138,7 @@ _Bool QuietLessGreater(float f1, float f2) { } _Bool QuietUnordered(float f1, float f2) { - // CHECK-LABEL: define {{.*}}i1 @QuietUnordered(float noundef %f1, float noundef %f2) + // CHECK-LABEL: define {{.*}}i1 @QuietUnordered(float %f1, float %f2) // FCMP: fcmp uno float %{{.*}}, %{{.*}} // IGNORE: call i1 @llvm.experimental.constrained.fcmp.f32(float %{{.*}}, float %{{.*}}, metadata !"uno", metadata !"fpexcept.ignore") diff --git a/clang/test/CodeGen/function-attributes.c b/clang/test/CodeGen/function-attributes.c index 04130e16a8304573491851fc16ba15e873ace866..f14f24801006b7713bf422794a7d517ec032f096 100644 --- a/clang/test/CodeGen/function-attributes.c +++ b/clang/test/CodeGen/function-attributes.c @@ -1,14 +1,14 @@ // RUN: %clang_cc1 -triple i386-unknown-unknown -emit-llvm -disable-llvm-passes -Os -o - %s | FileCheck %s // RUN: %clang_cc1 -triple i386-unknown-unknown -emit-llvm -disable-llvm-passes -Os -std=c99 -o - %s | FileCheck %s // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -disable-llvm-passes -Os -std=c99 -o - %s | FileCheck %s -// CHECK: define{{.*}} signext i8 @f0(i32 noundef %x) [[NUW:#[0-9]+]] -// CHECK: define{{.*}} zeroext i8 @f1(i32 noundef %x) [[NUW]] -// CHECK: define{{.*}} void @f2(i8 noundef signext %x) [[NUW]] -// CHECK: define{{.*}} void @f3(i8 noundef zeroext %x) [[NUW]] -// CHECK: define{{.*}} signext i16 @f4(i32 noundef %x) [[NUW]] -// CHECK: define{{.*}} zeroext i16 @f5(i32 noundef %x) [[NUW]] -// CHECK: define{{.*}} void @f6(i16 noundef signext %x) [[NUW]] -// CHECK: define{{.*}} void @f7(i16 noundef zeroext %x) [[NUW]] +// CHECK: define{{.*}} signext i8 @f0(i32 %x) [[NUW:#[0-9]+]] +// CHECK: define{{.*}} zeroext i8 @f1(i32 %x) [[NUW]] +// CHECK: define{{.*}} void @f2(i8 signext %x) [[NUW]] +// CHECK: define{{.*}} void @f3(i8 zeroext %x) [[NUW]] +// CHECK: define{{.*}} signext i16 @f4(i32 %x) [[NUW]] +// CHECK: define{{.*}} zeroext i16 @f5(i32 %x) [[NUW]] +// CHECK: define{{.*}} void @f6(i16 signext %x) [[NUW]] +// CHECK: define{{.*}} void @f7(i16 zeroext %x) [[NUW]] signed char f0(int x) { return x; } @@ -90,7 +90,7 @@ __attribute__ ((returns_twice)) void f18(void) { // CHECK-LABEL: define{{.*}} void @f19() // CHECK: { -// CHECK: call i32 @setjmp(i32* noundef null) +// CHECK: call i32 @setjmp(i32* null) // CHECK: [[RT_CALL]] // CHECK: ret void typedef int jmp_buf[((9 * 2) + 3 + 16)]; @@ -101,7 +101,7 @@ void f19(void) { // CHECK-LABEL: define{{.*}} void @f20() // CHECK: { -// CHECK: call i32 @_setjmp(i32* noundef null) +// CHECK: call i32 @_setjmp(i32* null) // CHECK: [[RT_CALL]] // CHECK: ret void int _setjmp(jmp_buf); diff --git a/clang/test/CodeGen/functions.c b/clang/test/CodeGen/functions.c index 0731b608961285c556e0c3ef0e516e237828d77c..a34ca979d8483ed3f1bd5c2af9ff75ae9abc15a5 100644 --- a/clang/test/CodeGen/functions.c +++ b/clang/test/CodeGen/functions.c @@ -55,8 +55,8 @@ void f8_user(void (*callback)(struct Incomplete)); void f8_test() { f8_user(&f8_callback); // CHECK-LABEL: define{{.*}} void @f8_test() -// CHECK: call void @f8_user({{.*}}* noundef bitcast (void ()* @f8_callback to {{.*}}*)) -// CHECK: declare void @f8_user({{.*}}* noundef) +// CHECK: call void @f8_user({{.*}}* bitcast (void ()* @f8_callback to {{.*}}*)) +// CHECK: declare void @f8_user({{.*}}*) // CHECK: declare void @f8_callback() } diff --git a/clang/test/CodeGen/hexagon-hvx-abi.c b/clang/test/CodeGen/hexagon-hvx-abi.c index 1fec27b77719b064bfd6eafbfcdf5145ef213646..cd70f57e4ffca7dc1b9cb2b9d6a99c7f2336b952 100644 --- a/clang/test/CodeGen/hexagon-hvx-abi.c +++ b/clang/test/CodeGen/hexagon-hvx-abi.c @@ -6,14 +6,14 @@ typedef long HVX_Vector __attribute__((__vector_size__(__HVX_LENGTH__))) typedef long HVX_VectorPair __attribute__((__vector_size__(2*__HVX_LENGTH__))) __attribute__((aligned(__HVX_LENGTH__))); -// CHECK-HVX64: define {{.*}} <16 x i32> @foo(<16 x i32> noundef %a, <32 x i32> noundef %b) -// CHECK-HVX128: define {{.*}} <32 x i32> @foo(<32 x i32> noundef %a, <64 x i32> noundef %b) +// CHECK-HVX64: define {{.*}} <16 x i32> @foo(<16 x i32> %a, <32 x i32> %b) +// CHECK-HVX128: define {{.*}} <32 x i32> @foo(<32 x i32> %a, <64 x i32> %b) HVX_Vector foo(HVX_Vector a, HVX_VectorPair b) { return a; } -// CHECK-HVX64: define {{.*}} <32 x i32> @bar(<16 x i32> noundef %a, <32 x i32> noundef %b) -// CHECK-HVX128: define {{.*}} <64 x i32> @bar(<32 x i32> noundef %a, <64 x i32> noundef %b) +// CHECK-HVX64: define {{.*}} <32 x i32> @bar(<16 x i32> %a, <32 x i32> %b) +// CHECK-HVX128: define {{.*}} <64 x i32> @bar(<32 x i32> %a, <64 x i32> %b) HVX_VectorPair bar(HVX_Vector a, HVX_VectorPair b) { return b; } diff --git a/clang/test/CodeGen/incomplete-function-type-2.c b/clang/test/CodeGen/incomplete-function-type-2.c index 20f5ad32040f5d6ca0b4f02a4caa1661b7539bac..caf9a7a56ead507b1f44ef779ac225595230ab26 100644 --- a/clang/test/CodeGen/incomplete-function-type-2.c +++ b/clang/test/CodeGen/incomplete-function-type-2.c @@ -2,7 +2,7 @@ // PR14355: don't crash // Keep this test in its own file because CodeGenTypes has global state. -// CHECK: define{{.*}} void @test10_foo({}* noundef %p1.coerce) [[NUW:#[0-9]+]] { +// CHECK: define{{.*}} void @test10_foo({}* %p1.coerce) [[NUW:#[0-9]+]] { struct test10_B; typedef struct test10_B test10_F3(double); void test10_foo(test10_F3 p1); diff --git a/clang/test/CodeGen/indirect-noundef.cpp b/clang/test/CodeGen/indirect-noundef.cpp index 82816296cefdc50bbe7403b609348a65c35113d2..6eccf8c6fb3a6e989c4e56967b64026fc8c714a7 100644 --- a/clang/test/CodeGen/indirect-noundef.cpp +++ b/clang/test/CodeGen/indirect-noundef.cpp @@ -1,4 +1,4 @@ -// RUN: %clang -cc1 -x c++ -triple x86_64-unknown-unknown -O0 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang -cc1 -x c++ -triple x86_64-unknown-unknown -O0 -emit-llvm -enable-noundef-analysis -o - %s | FileCheck %s union u1 { int val; diff --git a/clang/test/CodeGen/inline.c b/clang/test/CodeGen/inline.c index a9cd88cabd8a3a585e9a7f69d70d7aa278d6774c..e1fdea34633589648be5f353e62af7f8bf853dec 100644 --- a/clang/test/CodeGen/inline.c +++ b/clang/test/CodeGen/inline.c @@ -50,12 +50,12 @@ // RUN: %clang_cc1 -x c++ %s -triple i386-unknown-unknown -O1 -disable-llvm-passes -emit-llvm -o - -std=c++98 | FileCheck %s --check-prefix=CHECK3 // RUN: %clang_cc1 -x c++ %s -triple i386-unknown-unknown -fexperimental-new-pass-manager -O1 -disable-llvm-passes -emit-llvm -o - -std=c++98 | FileCheck %s --check-prefix=CHECK3 // CHECK3-LABEL: define{{.*}} i32 @_Z3barv() -// CHECK3-LABEL: define linkonce_odr noundef i32 @_Z3foov() +// CHECK3-LABEL: define linkonce_odr i32 @_Z3foov() // CHECK3-NOT: unreferenced // CHECK3-LABEL: define available_externally void @_Z10gnu_inlinev() // CHECK3-LABEL: define available_externally void @_Z13gnu_ei_inlinev() // CHECK3-NOT: @_Z5testCv -// CHECK3-LABEL: define linkonce_odr noundef i32 @_Z2eiv() +// CHECK3-LABEL: define linkonce_odr i32 @_Z2eiv() // RUN: echo "MS C Mode tests:" // RUN: %clang_cc1 %s -triple i386-pc-win32 -O1 -disable-llvm-passes -emit-llvm -o - -std=c99 | FileCheck %s --check-prefix=CHECK4 diff --git a/clang/test/CodeGen/lanai-arguments.c b/clang/test/CodeGen/lanai-arguments.c index 52e929527397024bb897690ea34ac8275bea9830..8f75c59cf6b5bec91cea54f4bc6ef422f86f1bb2 100644 --- a/clang/test/CodeGen/lanai-arguments.c +++ b/clang/test/CodeGen/lanai-arguments.c @@ -3,7 +3,7 @@ // Basic argument/attribute tests for Lanai. -// CHECK: define{{.*}} void @f0(i32 inreg noundef %i, i32 inreg noundef %j, i64 inreg noundef %k) +// CHECK: define{{.*}} void @f0(i32 inreg %i, i32 inreg %j, i64 inreg %k) void f0(int i, long j, long long k) {} typedef struct { @@ -32,13 +32,13 @@ s3 f3() { return foo; } -// CHECK: define{{.*}} void @f4(i64 inreg noundef %i) +// CHECK: define{{.*}} void @f4(i64 inreg %i) void f4(long long i) {} -// CHECK: define{{.*}} void @f5(i8 inreg noundef %a, i16 inreg noundef %b) +// CHECK: define{{.*}} void @f5(i8 inreg %a, i16 inreg %b) void f5(char a, short b) {} -// CHECK: define{{.*}} void @f6(i8 inreg noundef %a, i16 inreg noundef %b) +// CHECK: define{{.*}} void @f6(i8 inreg %a, i16 inreg %b) void f6(unsigned char a, unsigned short b) {} enum my_enum { @@ -47,14 +47,14 @@ enum my_enum { ENUM3, }; // Enums should be treated as the underlying i32. -// CHECK: define{{.*}} void @f7(i32 inreg noundef %a) +// CHECK: define{{.*}} void @f7(i32 inreg %a) void f7(enum my_enum a) {} enum my_big_enum { ENUM4 = 0xFFFFFFFFFFFFFFFF, }; // Big enums should be treated as the underlying i64. -// CHECK: define{{.*}} void @f8(i64 inreg noundef %a) +// CHECK: define{{.*}} void @f8(i64 inreg %a) void f8(enum my_big_enum a) {} union simple_union { diff --git a/clang/test/CodeGen/lanai-regparm.c b/clang/test/CodeGen/lanai-regparm.c index 12d1cb1102754ddc7d6fdc85038c5cb90574d489..c315f43bca736961c4102fe9f5ed90ddb9441c7b 100644 --- a/clang/test/CodeGen/lanai-regparm.c +++ b/clang/test/CodeGen/lanai-regparm.c @@ -6,13 +6,13 @@ void f1(int a, int b, int c, int d, void f2(int a, int b) __attribute((regparm(0))); void f0() { -// CHECK: call void @f1(i32 inreg noundef 1, i32 inreg noundef 2, i32 inreg noundef 3, i32 inreg noundef 4, -// CHECK: i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8) +// CHECK: call void @f1(i32 inreg 1, i32 inreg 2, i32 inreg 3, i32 inreg 4, +// CHECK: i32 5, i32 6, i32 7, i32 8) f1(1, 2, 3, 4, 5, 6, 7, 8); -// CHECK: call void @f2(i32 noundef 1, i32 noundef 2) +// CHECK: call void @f2(i32 1, i32 2) f2(1, 2); } -// CHECK: declare void @f1(i32 inreg noundef, i32 inreg noundef, i32 inreg noundef, i32 inreg noundef, -// CHECK: i32 noundef, i32 noundef, i32 noundef, i32 noundef) -// CHECK: declare void @f2(i32 noundef, i32 noundef) +// CHECK: declare void @f1(i32 inreg, i32 inreg, i32 inreg, i32 inreg, +// CHECK: i32, i32, i32, i32) +// CHECK: declare void @f2(i32, i32) diff --git a/clang/test/CodeGen/libcall-declarations.c b/clang/test/CodeGen/libcall-declarations.c index e9d768dd80ed239d9e4aff909cccf3b69c9fb9e8..7492995be892723f49bfd5c54c80ac057b82a399 100644 --- a/clang/test/CodeGen/libcall-declarations.c +++ b/clang/test/CodeGen/libcall-declarations.c @@ -7,34 +7,34 @@ #ifdef __cplusplus extern "C" { #endif -double atan2(double noundef, double); +double atan2(double, double); float atan2f(float, float); long double atan2l(long double, long double); int abs(int); long int labs(long int); long long int llabs(long long int); -double copysign(double noundef, double); +double copysign(double, double); float copysignf(float, float); long double copysignl(long double, long double); double fabs(double); float fabsf(float); long double fabsl(long double); -double fmod(double noundef, double); +double fmod(double, double); float fmodf(float, float); long double fmodl(long double, long double); -double frexp(double noundef, int *); +double frexp(double, int *); float frexpf(float, int *); -long double frexpl(long double noundef, int *); -double ldexp(double noundef, int); +long double frexpl(long double, int *); +double ldexp(double, int); float ldexpf(float, int); -long double ldexpl(long double noundef, int); -double modf(double noundef, double *); +long double ldexpl(long double, int); +double modf(double, double *); float modff(float, float *); long double modfl(long double, long double *); double nan(const char *); float nanf(const char *); long double nanl(const char *); -double pow(double noundef, double); +double pow(double, double); float powf(float, float); long double powl(long double, long double); double acos(double); @@ -82,22 +82,22 @@ long double exp2l(long double); double expm1(double); float expm1f(float); long double expm1l(long double); -double fdim(double noundef, double); +double fdim(double, double); float fdimf(float, float); long double fdiml(long double, long double); double floor(double); float floorf(float); long double floorl(long double); -double fma(double noundef, double, double); +double fma(double, double, double); float fmaf(float, float, float); long double fmal(long double, long double, long double); -double fmax(double noundef, double); +double fmax(double, double); float fmaxf(float, float); long double fmaxl(long double, long double); -double fmin(double noundef, double); +double fmin(double, double); float fminf(float, float); long double fminl(long double, long double); -double hypot(double noundef, double); +double hypot(double, double); float hypotf(float, float); long double hypotl(long double, long double); int ilogb(double); @@ -136,13 +136,13 @@ long int lroundl(long double); double nearbyint(double); float nearbyintf(float); long double nearbyintl(long double); -double nextafter(double noundef, double); +double nextafter(double, double); float nextafterf(float, float); long double nextafterl(long double, long double); double nexttoward(double, long double); float nexttowardf(float, long double); long double nexttowardl(long double, long double); -double remainder(double noundef, double); +double remainder(double, double); float remainderf(float, float); long double remainderl(long double, long double); double rint(double); @@ -154,9 +154,9 @@ long double roundl(long double); double scalbln(double, long int exp); float scalblnf(float, long int exp); long double scalblnl(long double, long int exp); -double scalbn(double noundef, int exp); +double scalbn(double, int exp); float scalbnf(float, int exp); -long double scalbnl(long double noundef, int exp); +long double scalbnl(long double, int exp); double sin(double); float sinf(float); long double sinl(long double); @@ -312,307 +312,307 @@ void *use[] = { F(__cospif), F(__tanpi), F(__tanpif), F(__exp10), F(__exp10f) }; -// CHECK-NOERRNO: declare double @atan2(double noundef, double noundef) [[NUWRN:#[0-9]+]] -// CHECK-NOERRNO: declare float @atan2f(float noundef, float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @atan2l(x86_fp80 noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i32 @abs(i32 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i64 @labs(i64 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i64 @llabs(i64 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @copysign(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @copysignf(float noundef, float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @copysignl(x86_fp80 noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @fabs(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @fabsf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @fabsl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @fmod(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @fmodf(float noundef, float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @fmodl(x86_fp80 noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @ldexp(double noundef, i32 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @ldexpf(float noundef, i32 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @ldexpl(x86_fp80 noundef, i32 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @nan(i8* noundef) [[NUWRO:#[0-9]+]] -// CHECK-NOERRNO: declare float @nanf(i8* noundef) [[NUWRO]] -// CHECK-NOERRNO: declare x86_fp80 @nanl(i8* noundef) [[NUWRO]] -// CHECK-NOERRNO: declare double @pow(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @powf(float noundef, float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @powl(x86_fp80 noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @acos(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @acosf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @acosl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @acosh(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @acoshf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @acoshl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @asin(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @asinf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @asinl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @asinh(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @asinhf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @asinhl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @atan(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @atanf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @atanl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @atanh(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @atanhf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @atanhl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @cbrt(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @cbrtf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @cbrtl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @ceil(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @ceilf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @ceill(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @cos(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @cosf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @cosl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @cosh(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @coshf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @coshl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @erf(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @erff(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @erfl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @erfc(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @erfcf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @erfcl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @exp(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @expf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @expl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @exp2(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @exp2f(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @exp2l(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @expm1(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @expm1f(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @expm1l(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @fdim(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @fdimf(float noundef, float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @fdiml(x86_fp80 noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @floor(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @floorf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @floorl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @fma(double noundef, double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @fmaf(float noundef, float noundef, float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @fmal(x86_fp80 noundef, x86_fp80 noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @fmax(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @fmaxf(float noundef, float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @fmaxl(x86_fp80 noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @fmin(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @fminf(float noundef, float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @fminl(x86_fp80 noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @hypot(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @hypotf(float noundef, float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @hypotl(x86_fp80 noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i32 @ilogb(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i32 @ilogbf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i32 @ilogbl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @lgamma(double noundef) [[NONCONST:#[0-9]+]] -// CHECK-NOERRNO: declare float @lgammaf(float noundef) [[NONCONST]] -// CHECK-NOERRNO: declare x86_fp80 @lgammal(x86_fp80 noundef) [[NONCONST]] -// CHECK-NOERRNO: declare i64 @llrint(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i64 @llrintf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i64 @llrintl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i64 @llround(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i64 @llroundf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i64 @llroundl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @log(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @logf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @logl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @log10(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @log10f(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @log10l(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @log1p(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @log1pf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @log1pl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @log2(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @log2f(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @log2l(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @logb(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @logbf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @logbl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i64 @lrint(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i64 @lrintf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i64 @lrintl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i64 @lround(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i64 @lroundf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare i64 @lroundl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @nearbyint(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @nearbyintf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @nearbyintl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @nextafter(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @nextafterf(float noundef, float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @nextafterl(x86_fp80 noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @nexttoward(double noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @nexttowardf(float noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @nexttowardl(x86_fp80 noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @remainder(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @remainderf(float noundef, float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @remainderl(x86_fp80 noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @rint(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @rintf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @rintl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @round(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @roundf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @roundl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @scalbln(double noundef, i64 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @scalblnf(float noundef, i64 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @scalblnl(x86_fp80 noundef, i64 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @scalbn(double noundef, i32 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @scalbnf(float noundef, i32 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @scalbnl(x86_fp80 noundef, i32 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @sin(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @sinf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @sinl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @sinh(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @sinhf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @sinhl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @sqrt(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @sqrtf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @sqrtl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @tan(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @tanf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @tanl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @tanh(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @tanhf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @tanhl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @tgamma(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @tgammaf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @tgammal(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @trunc(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @truncf(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare x86_fp80 @truncl(x86_fp80 noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @cabs(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @cabsf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @cacos(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @cacosf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @cacosh(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @cacoshf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @carg(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @cargf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @casin(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @casinf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @casinh(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @casinhf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @catan(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @catanf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @catanh(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @catanhf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @ccos(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @ccosf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @ccosh(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @ccoshf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @cexp(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @cexpf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @cimag(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @cimagf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @conj(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @conjf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @clog(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @clogf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @cproj(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @cprojf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @cpow(double noundef, double noundef, double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @cpowf(<2 x float> noundef, <2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @creal(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @crealf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @csin(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @csinf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @csinh(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @csinhf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @csqrt(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @csqrtf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @ctan(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @ctanf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare { double, double } @ctanh(double noundef, double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare <2 x float> @ctanhf(<2 x float> noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @__sinpi(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @__sinpif(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @__cospi(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @__cospif(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @__tanpi(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @__tanpif(float noundef) [[NUWRN]] -// CHECK-NOERRNO: declare double @__exp10(double noundef) [[NUWRN]] -// CHECK-NOERRNO: declare float @__exp10f(float noundef) [[NUWRN]] +// CHECK-NOERRNO: declare double @atan2(double, double) [[NUWRN:#[0-9]+]] +// CHECK-NOERRNO: declare float @atan2f(float, float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @atan2l(x86_fp80, x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare i32 @abs(i32) [[NUWRN]] +// CHECK-NOERRNO: declare i64 @labs(i64) [[NUWRN]] +// CHECK-NOERRNO: declare i64 @llabs(i64) [[NUWRN]] +// CHECK-NOERRNO: declare double @copysign(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare float @copysignf(float, float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @copysignl(x86_fp80, x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @fabs(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @fabsf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @fabsl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @fmod(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare float @fmodf(float, float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @fmodl(x86_fp80, x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @ldexp(double, i32) [[NUWRN]] +// CHECK-NOERRNO: declare float @ldexpf(float, i32) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @ldexpl(x86_fp80, i32) [[NUWRN]] +// CHECK-NOERRNO: declare double @nan(i8*) [[NUWRO:#[0-9]+]] +// CHECK-NOERRNO: declare float @nanf(i8*) [[NUWRO]] +// CHECK-NOERRNO: declare x86_fp80 @nanl(i8*) [[NUWRO]] +// CHECK-NOERRNO: declare double @pow(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare float @powf(float, float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @powl(x86_fp80, x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @acos(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @acosf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @acosl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @acosh(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @acoshf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @acoshl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @asin(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @asinf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @asinl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @asinh(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @asinhf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @asinhl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @atan(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @atanf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @atanl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @atanh(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @atanhf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @atanhl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @cbrt(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @cbrtf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @cbrtl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @ceil(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @ceilf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @ceill(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @cos(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @cosf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @cosl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @cosh(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @coshf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @coshl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @erf(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @erff(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @erfl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @erfc(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @erfcf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @erfcl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @exp(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @expf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @expl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @exp2(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @exp2f(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @exp2l(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @expm1(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @expm1f(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @expm1l(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @fdim(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare float @fdimf(float, float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @fdiml(x86_fp80, x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @floor(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @floorf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @floorl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @fma(double, double, double) [[NUWRN]] +// CHECK-NOERRNO: declare float @fmaf(float, float, float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @fmal(x86_fp80, x86_fp80, x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @fmax(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare float @fmaxf(float, float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @fmaxl(x86_fp80, x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @fmin(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare float @fminf(float, float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @fminl(x86_fp80, x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @hypot(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare float @hypotf(float, float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @hypotl(x86_fp80, x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare i32 @ilogb(double) [[NUWRN]] +// CHECK-NOERRNO: declare i32 @ilogbf(float) [[NUWRN]] +// CHECK-NOERRNO: declare i32 @ilogbl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @lgamma(double) [[NONCONST:#[0-9]+]] +// CHECK-NOERRNO: declare float @lgammaf(float) [[NONCONST]] +// CHECK-NOERRNO: declare x86_fp80 @lgammal(x86_fp80) [[NONCONST]] +// CHECK-NOERRNO: declare i64 @llrint(double) [[NUWRN]] +// CHECK-NOERRNO: declare i64 @llrintf(float) [[NUWRN]] +// CHECK-NOERRNO: declare i64 @llrintl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare i64 @llround(double) [[NUWRN]] +// CHECK-NOERRNO: declare i64 @llroundf(float) [[NUWRN]] +// CHECK-NOERRNO: declare i64 @llroundl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @log(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @logf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @logl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @log10(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @log10f(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @log10l(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @log1p(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @log1pf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @log1pl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @log2(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @log2f(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @log2l(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @logb(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @logbf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @logbl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare i64 @lrint(double) [[NUWRN]] +// CHECK-NOERRNO: declare i64 @lrintf(float) [[NUWRN]] +// CHECK-NOERRNO: declare i64 @lrintl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare i64 @lround(double) [[NUWRN]] +// CHECK-NOERRNO: declare i64 @lroundf(float) [[NUWRN]] +// CHECK-NOERRNO: declare i64 @lroundl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @nearbyint(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @nearbyintf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @nearbyintl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @nextafter(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare float @nextafterf(float, float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @nextafterl(x86_fp80, x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @nexttoward(double, x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare float @nexttowardf(float, x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @nexttowardl(x86_fp80, x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @remainder(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare float @remainderf(float, float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @remainderl(x86_fp80, x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @rint(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @rintf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @rintl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @round(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @roundf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @roundl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @scalbln(double, i64) [[NUWRN]] +// CHECK-NOERRNO: declare float @scalblnf(float, i64) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @scalblnl(x86_fp80, i64) [[NUWRN]] +// CHECK-NOERRNO: declare double @scalbn(double, i32) [[NUWRN]] +// CHECK-NOERRNO: declare float @scalbnf(float, i32) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @scalbnl(x86_fp80, i32) [[NUWRN]] +// CHECK-NOERRNO: declare double @sin(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @sinf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @sinl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @sinh(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @sinhf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @sinhl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @sqrt(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @sqrtf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @sqrtl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @tan(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @tanf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @tanl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @tanh(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @tanhf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @tanhl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @tgamma(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @tgammaf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @tgammal(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @trunc(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @truncf(float) [[NUWRN]] +// CHECK-NOERRNO: declare x86_fp80 @truncl(x86_fp80) [[NUWRN]] +// CHECK-NOERRNO: declare double @cabs(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare float @cabsf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @cacos(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @cacosf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @cacosh(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @cacoshf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare double @carg(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare float @cargf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @casin(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @casinf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @casinh(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @casinhf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @catan(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @catanf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @catanh(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @catanhf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @ccos(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @ccosf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @ccosh(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @ccoshf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @cexp(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @cexpf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare double @cimag(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare float @cimagf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @conj(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @conjf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @clog(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @clogf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @cproj(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @cprojf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @cpow(double, double, double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @cpowf(<2 x float>, <2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare double @creal(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare float @crealf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @csin(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @csinf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @csinh(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @csinhf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @csqrt(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @csqrtf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @ctan(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @ctanf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare { double, double } @ctanh(double, double) [[NUWRN]] +// CHECK-NOERRNO: declare <2 x float> @ctanhf(<2 x float>) [[NUWRN]] +// CHECK-NOERRNO: declare double @__sinpi(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @__sinpif(float) [[NUWRN]] +// CHECK-NOERRNO: declare double @__cospi(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @__cospif(float) [[NUWRN]] +// CHECK-NOERRNO: declare double @__tanpi(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @__tanpif(float) [[NUWRN]] +// CHECK-NOERRNO: declare double @__exp10(double) [[NUWRN]] +// CHECK-NOERRNO: declare float @__exp10f(float) [[NUWRN]] -// CHECK-ERRNO: declare i32 @abs(i32 noundef) [[NUWRN:#[0-9]+]] -// CHECK-ERRNO: declare i64 @labs(i64 noundef) [[NUWRN]] -// CHECK-ERRNO: declare i64 @llabs(i64 noundef) [[NUWRN]] -// CHECK-ERRNO: declare double @copysign(double noundef, double noundef) [[NUWRN]] -// CHECK-ERRNO: declare float @copysignf(float noundef, float noundef) [[NUWRN]] -// CHECK-ERRNO: declare x86_fp80 @copysignl(x86_fp80 noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-ERRNO: declare double @fabs(double noundef) [[NUWRN]] -// CHECK-ERRNO: declare float @fabsf(float noundef) [[NUWRN]] -// CHECK-ERRNO: declare x86_fp80 @fabsl(x86_fp80 noundef) [[NUWRN]] -// CHECK-ERRNO: declare double @nan(i8* noundef) [[NUWRO:#[0-9]+]] -// CHECK-ERRNO: declare float @nanf(i8* noundef) [[NUWRO]] -// CHECK-ERRNO: declare x86_fp80 @nanl(i8* noundef) [[NUWRO]] -// CHECK-ERRNO: declare double @ceil(double noundef) [[NUWRN]] -// CHECK-ERRNO: declare float @ceilf(float noundef) [[NUWRN]] -// CHECK-ERRNO: declare x86_fp80 @ceill(x86_fp80 noundef) [[NUWRN]] -// CHECK-ERRNO: declare double @floor(double noundef) [[NUWRN]] -// CHECK-ERRNO: declare float @floorf(float noundef) [[NUWRN]] -// CHECK-ERRNO: declare x86_fp80 @floorl(x86_fp80 noundef) [[NUWRN]] -// CHECK-ERRNO: declare double @fmax(double noundef, double noundef) [[NUWRN]] -// CHECK-ERRNO: declare float @fmaxf(float noundef, float noundef) [[NUWRN]] -// CHECK-ERRNO: declare x86_fp80 @fmaxl(x86_fp80 noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-ERRNO: declare double @fmin(double noundef, double noundef) [[NUWRN]] -// CHECK-ERRNO: declare float @fminf(float noundef, float noundef) [[NUWRN]] -// CHECK-ERRNO: declare x86_fp80 @fminl(x86_fp80 noundef, x86_fp80 noundef) [[NUWRN]] -// CHECK-ERRNO: declare double @lgamma(double noundef) [[NONCONST:#[0-9]+]] -// CHECK-ERRNO: declare float @lgammaf(float noundef) [[NONCONST]] -// CHECK-ERRNO: declare x86_fp80 @lgammal(x86_fp80 noundef) [[NONCONST]] -// CHECK-ERRNO: declare double @nearbyint(double noundef) [[NUWRN]] -// CHECK-ERRNO: declare float @nearbyintf(float noundef) [[NUWRN]] -// CHECK-ERRNO: declare x86_fp80 @nearbyintl(x86_fp80 noundef) [[NUWRN]] -// CHECK-ERRNO: declare double @rint(double noundef) [[NUWRN]] -// CHECK-ERRNO: declare float @rintf(float noundef) [[NUWRN]] -// CHECK-ERRNO: declare x86_fp80 @rintl(x86_fp80 noundef) [[NUWRN]] -// CHECK-ERRNO: declare double @round(double noundef) [[NUWRN]] -// CHECK-ERRNO: declare float @roundf(float noundef) [[NUWRN]] -// CHECK-ERRNO: declare x86_fp80 @roundl(x86_fp80 noundef) [[NUWRN]] -// CHECK-ERRNO: declare double @trunc(double noundef) [[NUWRN]] -// CHECK-ERRNO: declare float @truncf(float noundef) [[NUWRN]] -// CHECK-ERRNO: declare x86_fp80 @truncl(x86_fp80 noundef) [[NUWRN]] -// CHECK-ERRNO: declare double @cabs(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare float @cabsf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare { double, double } @cacos(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @cacosf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare { double, double } @cacosh(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @cacoshf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare double @carg(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare float @cargf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare { double, double } @casin(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @casinf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare { double, double } @casinh(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @casinhf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare { double, double } @catan(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @catanf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare { double, double } @catanh(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @catanhf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare { double, double } @ccos(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @ccosf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare { double, double } @ccosh(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @ccoshf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare { double, double } @cexp(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @cexpf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare double @cimag(double noundef, double noundef) [[NUWRN]] -// CHECK-ERRNO: declare float @cimagf(<2 x float> noundef) [[NUWRN]] -// CHECK-ERRNO: declare { double, double } @conj(double noundef, double noundef) [[NUWRN]] -// CHECK-ERRNO: declare <2 x float> @conjf(<2 x float> noundef) [[NUWRN]] -// CHECK-ERRNO: declare { double, double } @clog(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @clogf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare { double, double } @cproj(double noundef, double noundef) [[NUWRN]] -// CHECK-ERRNO: declare <2 x float> @cprojf(<2 x float> noundef) [[NUWRN]] -// CHECK-ERRNO: declare { double, double } @cpow(double noundef, double noundef, double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @cpowf(<2 x float> noundef, <2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare double @creal(double noundef, double noundef) [[NUWRN]] -// CHECK-ERRNO: declare float @crealf(<2 x float> noundef) [[NUWRN]] -// CHECK-ERRNO: declare { double, double } @csin(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @csinf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare { double, double } @csinh(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @csinhf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare { double, double } @csqrt(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @csqrtf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare { double, double } @ctan(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @ctanf(<2 x float> noundef) [[NONCONST]] -// CHECK-ERRNO: declare { double, double } @ctanh(double noundef, double noundef) [[NONCONST]] -// CHECK-ERRNO: declare <2 x float> @ctanhf(<2 x float> noundef) [[NONCONST]] +// CHECK-ERRNO: declare i32 @abs(i32) [[NUWRN:#[0-9]+]] +// CHECK-ERRNO: declare i64 @labs(i64) [[NUWRN]] +// CHECK-ERRNO: declare i64 @llabs(i64) [[NUWRN]] +// CHECK-ERRNO: declare double @copysign(double, double) [[NUWRN]] +// CHECK-ERRNO: declare float @copysignf(float, float) [[NUWRN]] +// CHECK-ERRNO: declare x86_fp80 @copysignl(x86_fp80, x86_fp80) [[NUWRN]] +// CHECK-ERRNO: declare double @fabs(double) [[NUWRN]] +// CHECK-ERRNO: declare float @fabsf(float) [[NUWRN]] +// CHECK-ERRNO: declare x86_fp80 @fabsl(x86_fp80) [[NUWRN]] +// CHECK-ERRNO: declare double @nan(i8*) [[NUWRO:#[0-9]+]] +// CHECK-ERRNO: declare float @nanf(i8*) [[NUWRO]] +// CHECK-ERRNO: declare x86_fp80 @nanl(i8*) [[NUWRO]] +// CHECK-ERRNO: declare double @ceil(double) [[NUWRN]] +// CHECK-ERRNO: declare float @ceilf(float) [[NUWRN]] +// CHECK-ERRNO: declare x86_fp80 @ceill(x86_fp80) [[NUWRN]] +// CHECK-ERRNO: declare double @floor(double) [[NUWRN]] +// CHECK-ERRNO: declare float @floorf(float) [[NUWRN]] +// CHECK-ERRNO: declare x86_fp80 @floorl(x86_fp80) [[NUWRN]] +// CHECK-ERRNO: declare double @fmax(double, double) [[NUWRN]] +// CHECK-ERRNO: declare float @fmaxf(float, float) [[NUWRN]] +// CHECK-ERRNO: declare x86_fp80 @fmaxl(x86_fp80, x86_fp80) [[NUWRN]] +// CHECK-ERRNO: declare double @fmin(double, double) [[NUWRN]] +// CHECK-ERRNO: declare float @fminf(float, float) [[NUWRN]] +// CHECK-ERRNO: declare x86_fp80 @fminl(x86_fp80, x86_fp80) [[NUWRN]] +// CHECK-ERRNO: declare double @lgamma(double) [[NONCONST:#[0-9]+]] +// CHECK-ERRNO: declare float @lgammaf(float) [[NONCONST]] +// CHECK-ERRNO: declare x86_fp80 @lgammal(x86_fp80) [[NONCONST]] +// CHECK-ERRNO: declare double @nearbyint(double) [[NUWRN]] +// CHECK-ERRNO: declare float @nearbyintf(float) [[NUWRN]] +// CHECK-ERRNO: declare x86_fp80 @nearbyintl(x86_fp80) [[NUWRN]] +// CHECK-ERRNO: declare double @rint(double) [[NUWRN]] +// CHECK-ERRNO: declare float @rintf(float) [[NUWRN]] +// CHECK-ERRNO: declare x86_fp80 @rintl(x86_fp80) [[NUWRN]] +// CHECK-ERRNO: declare double @round(double) [[NUWRN]] +// CHECK-ERRNO: declare float @roundf(float) [[NUWRN]] +// CHECK-ERRNO: declare x86_fp80 @roundl(x86_fp80) [[NUWRN]] +// CHECK-ERRNO: declare double @trunc(double) [[NUWRN]] +// CHECK-ERRNO: declare float @truncf(float) [[NUWRN]] +// CHECK-ERRNO: declare x86_fp80 @truncl(x86_fp80) [[NUWRN]] +// CHECK-ERRNO: declare double @cabs(double, double) [[NONCONST]] +// CHECK-ERRNO: declare float @cabsf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare { double, double } @cacos(double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @cacosf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare { double, double } @cacosh(double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @cacoshf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare double @carg(double, double) [[NONCONST]] +// CHECK-ERRNO: declare float @cargf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare { double, double } @casin(double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @casinf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare { double, double } @casinh(double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @casinhf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare { double, double } @catan(double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @catanf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare { double, double } @catanh(double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @catanhf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare { double, double } @ccos(double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @ccosf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare { double, double } @ccosh(double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @ccoshf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare { double, double } @cexp(double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @cexpf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare double @cimag(double, double) [[NUWRN]] +// CHECK-ERRNO: declare float @cimagf(<2 x float>) [[NUWRN]] +// CHECK-ERRNO: declare { double, double } @conj(double, double) [[NUWRN]] +// CHECK-ERRNO: declare <2 x float> @conjf(<2 x float>) [[NUWRN]] +// CHECK-ERRNO: declare { double, double } @clog(double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @clogf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare { double, double } @cproj(double, double) [[NUWRN]] +// CHECK-ERRNO: declare <2 x float> @cprojf(<2 x float>) [[NUWRN]] +// CHECK-ERRNO: declare { double, double } @cpow(double, double, double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @cpowf(<2 x float>, <2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare double @creal(double, double) [[NUWRN]] +// CHECK-ERRNO: declare float @crealf(<2 x float>) [[NUWRN]] +// CHECK-ERRNO: declare { double, double } @csin(double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @csinf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare { double, double } @csinh(double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @csinhf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare { double, double } @csqrt(double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @csqrtf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare { double, double } @ctan(double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @ctanf(<2 x float>) [[NONCONST]] +// CHECK-ERRNO: declare { double, double } @ctanh(double, double) [[NONCONST]] +// CHECK-ERRNO: declare <2 x float> @ctanhf(<2 x float>) [[NONCONST]] // CHECK-NOERRNO: attributes [[NUWRN]] = { nounwind readnone{{.*}} } // CHECK-NOERRNO: attributes [[NUWRO]] = { nounwind readonly{{.*}} } diff --git a/clang/test/CodeGen/libcalls.c b/clang/test/CodeGen/libcalls.c index 7c7c1fc8275fe0bd235e4c2cfe9253ef9dfcb013..627732916f259cb18cd86972f2cca50c5514360f 100644 --- a/clang/test/CodeGen/libcalls.c +++ b/clang/test/CodeGen/libcalls.c @@ -22,9 +22,9 @@ void test_sqrt(float a0, double a1, long double a2) { long double l2 = sqrtl(a2); } -// CHECK-YES: declare float @sqrtf(float noundef) -// CHECK-YES: declare double @sqrt(double noundef) -// CHECK-YES: declare x86_fp80 @sqrtl(x86_fp80 noundef) +// CHECK-YES: declare float @sqrtf(float) +// CHECK-YES: declare double @sqrt(double) +// CHECK-YES: declare x86_fp80 @sqrtl(x86_fp80) // CHECK-NO: declare float @llvm.sqrt.f32(float) // CHECK-NO: declare double @llvm.sqrt.f64(double) // CHECK-NO: declare x86_fp80 @llvm.sqrt.f80(x86_fp80) @@ -48,9 +48,9 @@ void test_pow(float a0, double a1, long double a2) { long double l2 = powl(a2, a2); } -// CHECK-YES: declare float @powf(float noundef, float noundef) -// CHECK-YES: declare double @pow(double noundef, double noundef) -// CHECK-YES: declare x86_fp80 @powl(x86_fp80 noundef, x86_fp80 noundef) +// CHECK-YES: declare float @powf(float, float) +// CHECK-YES: declare double @pow(double, double) +// CHECK-YES: declare x86_fp80 @powl(x86_fp80, x86_fp80) // CHECK-NO: declare float @llvm.pow.f32(float, float) [[NUW_RNI:#[0-9]+]] // CHECK-NO: declare double @llvm.pow.f64(double, double) [[NUW_RNI]] // CHECK-NO: declare x86_fp80 @llvm.pow.f80(x86_fp80, x86_fp80) [[NUW_RNI]] @@ -71,9 +71,9 @@ void test_fma(float a0, double a1, long double a2) { long double l2 = fmal(a2, a2, a2); } -// CHECK-YES: declare float @fmaf(float noundef, float noundef, float noundef) -// CHECK-YES: declare double @fma(double noundef, double noundef, double noundef) -// CHECK-YES: declare x86_fp80 @fmal(x86_fp80 noundef, x86_fp80 noundef, x86_fp80 noundef) +// CHECK-YES: declare float @fmaf(float, float, float) +// CHECK-YES: declare double @fma(double, double, double) +// CHECK-YES: declare x86_fp80 @fmal(x86_fp80, x86_fp80, x86_fp80) // CHECK-NO: declare float @llvm.fma.f32(float, float, float) [[NUW_RN2:#[0-9]+]] // CHECK-NO: declare double @llvm.fma.f64(double, double, double) [[NUW_RN2]] // CHECK-NO: declare x86_fp80 @llvm.fma.f80(x86_fp80, x86_fp80, x86_fp80) [[NUW_RN2]] @@ -85,22 +85,22 @@ void test_builtins(double d, float f, long double ld) { double atan_ = atan(d); long double atanl_ = atanl(ld); float atanf_ = atanf(f); -// CHECK-NO: declare double @atan(double noundef) [[NUW_RN:#[0-9]+]] -// CHECK-NO: declare x86_fp80 @atanl(x86_fp80 noundef) [[NUW_RN]] -// CHECK-NO: declare float @atanf(float noundef) [[NUW_RN]] -// CHECK-YES: declare double @atan(double noundef) [[NUW:#[0-9]+]] -// CHECK-YES: declare x86_fp80 @atanl(x86_fp80 noundef) [[NUW]] -// CHECK-YES: declare float @atanf(float noundef) [[NUW]] +// CHECK-NO: declare double @atan(double) [[NUW_RN:#[0-9]+]] +// CHECK-NO: declare x86_fp80 @atanl(x86_fp80) [[NUW_RN]] +// CHECK-NO: declare float @atanf(float) [[NUW_RN]] +// CHECK-YES: declare double @atan(double) [[NUW:#[0-9]+]] +// CHECK-YES: declare x86_fp80 @atanl(x86_fp80) [[NUW]] +// CHECK-YES: declare float @atanf(float) [[NUW]] double atan2_ = atan2(d, 2); long double atan2l_ = atan2l(ld, ld); float atan2f_ = atan2f(f, f); -// CHECK-NO: declare double @atan2(double noundef, double noundef) [[NUW_RN]] -// CHECK-NO: declare x86_fp80 @atan2l(x86_fp80 noundef, x86_fp80 noundef) [[NUW_RN]] -// CHECK-NO: declare float @atan2f(float noundef, float noundef) [[NUW_RN]] -// CHECK-YES: declare double @atan2(double noundef, double noundef) [[NUW]] -// CHECK-YES: declare x86_fp80 @atan2l(x86_fp80 noundef, x86_fp80 noundef) [[NUW]] -// CHECK-YES: declare float @atan2f(float noundef, float noundef) [[NUW]] +// CHECK-NO: declare double @atan2(double, double) [[NUW_RN]] +// CHECK-NO: declare x86_fp80 @atan2l(x86_fp80, x86_fp80) [[NUW_RN]] +// CHECK-NO: declare float @atan2f(float, float) [[NUW_RN]] +// CHECK-YES: declare double @atan2(double, double) [[NUW]] +// CHECK-YES: declare x86_fp80 @atan2l(x86_fp80, x86_fp80) [[NUW]] +// CHECK-YES: declare float @atan2f(float, float) [[NUW]] double exp_ = exp(d); long double expl_ = expl(ld); @@ -108,9 +108,9 @@ void test_builtins(double d, float f, long double ld) { // CHECK-NO: declare double @llvm.exp.f64(double) [[NUW_RNI]] // CHECK-NO: declare x86_fp80 @llvm.exp.f80(x86_fp80) [[NUW_RNI]] // CHECK-NO: declare float @llvm.exp.f32(float) [[NUW_RNI]] -// CHECK-YES: declare double @exp(double noundef) [[NUW]] -// CHECK-YES: declare x86_fp80 @expl(x86_fp80 noundef) [[NUW]] -// CHECK-YES: declare float @expf(float noundef) [[NUW]] +// CHECK-YES: declare double @exp(double) [[NUW]] +// CHECK-YES: declare x86_fp80 @expl(x86_fp80) [[NUW]] +// CHECK-YES: declare float @expf(float) [[NUW]] double log_ = log(d); long double logl_ = logl(ld); @@ -118,9 +118,9 @@ void test_builtins(double d, float f, long double ld) { // CHECK-NO: declare double @llvm.log.f64(double) [[NUW_RNI]] // CHECK-NO: declare x86_fp80 @llvm.log.f80(x86_fp80) [[NUW_RNI]] // CHECK-NO: declare float @llvm.log.f32(float) [[NUW_RNI]] -// CHECK-YES: declare double @log(double noundef) [[NUW]] -// CHECK-YES: declare x86_fp80 @logl(x86_fp80 noundef) [[NUW]] -// CHECK-YES: declare float @logf(float noundef) [[NUW]] +// CHECK-YES: declare double @log(double) [[NUW]] +// CHECK-YES: declare x86_fp80 @logl(x86_fp80) [[NUW]] +// CHECK-YES: declare float @logf(float) [[NUW]] } // CHECK-YES: attributes [[NUW]] = { nounwind "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" } diff --git a/clang/test/CodeGen/lifetime.c b/clang/test/CodeGen/lifetime.c index e1b45e4f6475612d7d7cd8432c2b078d87a65fe8..2203840d4b8065614c7b4c1d720a69b1eed2c30d 100644 --- a/clang/test/CodeGen/lifetime.c +++ b/clang/test/CodeGen/lifetime.c @@ -1,8 +1,7 @@ -// RUN: %clang -S -emit-llvm -o - -O0 -fno-experimental-new-pass-manager %s | FileCheck %s -check-prefix=O0 -// RUN: %clang -S -emit-llvm -o - -O1 -fno-experimental-new-pass-manager %s | FileCheck %s -check-prefix=O1 -// RUN: %clang -S -emit-llvm -o - -O2 -fno-experimental-new-pass-manager %s | FileCheck %s -check-prefix=O2 -// RUN: %clang -S -emit-llvm -o - -O3 -fno-experimental-new-pass-manager %s | FileCheck %s -check-prefix=O3 -// RUN: %clang -S -emit-llvm -o - -O0 -fexperimental-new-pass-manager %s | FileCheck %s -check-prefix=O0 +// RUN: %clang -S -emit-llvm -o - -O0 %s | FileCheck %s -check-prefix=O0 +// RUN: %clang -S -emit-llvm -o - -O1 %s | FileCheck %s -check-prefix=O1 +// RUN: %clang -S -emit-llvm -o - -O2 %s | FileCheck %s -check-prefix=O2 +// RUN: %clang -S -emit-llvm -o - -O3 %s | FileCheck %s -check-prefix=O3 extern void use(char *a); diff --git a/clang/test/CodeGen/long_double_fp128.cpp b/clang/test/CodeGen/long_double_fp128.cpp index eba78c1219cd64a32f9202e1a0dbce3a6bec7598..30b8f08a308771770dd97b577e87c9114c76fe93 100644 --- a/clang/test/CodeGen/long_double_fp128.cpp +++ b/clang/test/CodeGen/long_double_fp128.cpp @@ -17,10 +17,10 @@ // Android's gcc and llvm use fp128 for long double. // NaCl uses double format for long double, but still has separate overloads. void test(long, float, double, long double, long double _Complex) { } -// A64: define{{.*}} void @_Z4testlfdgCg(i64 noundef %0, float noundef %1, double noundef %2, fp128 noundef %3, { fp128, fp128 }* -// G64: define{{.*}} void @_Z4testlfdeCe(i64 noundef %0, float noundef %1, double noundef %2, x86_fp80 noundef %3, { x86_fp80, x86_fp80 }* -// P64: define{{.*}} void @_Z4testlfdgCg(i64 noundef %0, float noundef %1, double noundef %2, ppc_fp128 noundef %3, ppc_fp128 {{.*}}, ppc_fp128 -// A32: define{{.*}} void @_Z4testlfdeCe(i32 noundef %0, float noundef %1, double noundef %2, double noundef %3, { double, double }* -// G32: define{{.*}} void @_Z4testlfdeCe(i32 noundef %0, float noundef %1, double noundef %2, x86_fp80 noundef %3, { x86_fp80, x86_fp80 }* -// P32: define{{.*}} void @_Z4testlfdgCg(i32 noundef %0, float noundef %1, double noundef %2, ppc_fp128 noundef %3, { ppc_fp128, ppc_fp128 }* -// N64: define{{.*}} void @_Z4testlfdeCe(i32 noundef %0, float noundef %1, double noundef %2, double noundef %3, double noundef {{.*}}, double +// A64: define{{.*}} void @_Z4testlfdgCg(i64 %0, float %1, double %2, fp128 %3, { fp128, fp128 }* +// G64: define{{.*}} void @_Z4testlfdeCe(i64 %0, float %1, double %2, x86_fp80 %3, { x86_fp80, x86_fp80 }* +// P64: define{{.*}} void @_Z4testlfdgCg(i64 %0, float %1, double %2, ppc_fp128 %3, ppc_fp128 {{.*}}, ppc_fp128 +// A32: define{{.*}} void @_Z4testlfdeCe(i32 %0, float %1, double %2, double %3, { double, double }* +// G32: define{{.*}} void @_Z4testlfdeCe(i32 %0, float %1, double %2, x86_fp80 %3, { x86_fp80, x86_fp80 }* +// P32: define{{.*}} void @_Z4testlfdgCg(i32 %0, float %1, double %2, ppc_fp128 %3, { ppc_fp128, ppc_fp128 }* +// N64: define{{.*}} void @_Z4testlfdeCe(i32 %0, float %1, double %2, double %3, double {{.*}}, double diff --git a/clang/test/CodeGen/malign-double-x86-nacl.c b/clang/test/CodeGen/malign-double-x86-nacl.c index a415a46221f8b607f0ba291ab36bf5b8c54ecbfa..175484c3af37e3333592ead28392aaf9593ca241 100644 --- a/clang/test/CodeGen/malign-double-x86-nacl.c +++ b/clang/test/CodeGen/malign-double-x86-nacl.c @@ -5,7 +5,7 @@ int checksize[sizeof(long double) == 8 ? 1 : -1]; int checkalign[__alignof(long double) == 8 ? 1 : -1]; -// CHECK-LABEL: define{{.*}} void @s1(double noundef %a) +// CHECK-LABEL: define{{.*}} void @s1(double %a) void s1(long double a) {} struct st_ld { @@ -18,7 +18,7 @@ int checkalign2[__alignof(struct st_ld) == 8 ? 1 : -1]; int checksize3[sizeof(double) == 8 ? 1 : -1]; int checkalign3[__alignof(double) == 8 ? 1 : -1]; -// CHECK-LABEL: define{{.*}} void @s2(double noundef %a) +// CHECK-LABEL: define{{.*}} void @s2(double %a) void s2(double a) {} struct st_d { @@ -32,7 +32,7 @@ int checkalign4[__alignof(struct st_d) == 8 ? 1 : -1]; int checksize5[sizeof(long long) == 8 ? 1 : -1]; int checkalign5[__alignof(long long) == 8 ? 1 : -1]; -// CHECK-LABEL: define{{.*}} void @s3(i64 noundef %a) +// CHECK-LABEL: define{{.*}} void @s3(i64 %a) void s3(long long a) {} struct st_ll { diff --git a/clang/test/CodeGen/mangle-blocks.c b/clang/test/CodeGen/mangle-blocks.c index a0fcf554a2ac539ae1a576bfa25e0d01d786ed22..4ea5a550c8bd935e8c9130f817fa99cbf11b3dad 100644 --- a/clang/test/CodeGen/mangle-blocks.c +++ b/clang/test/CodeGen/mangle-blocks.c @@ -15,9 +15,9 @@ void (^mangle(void))(void) { // CHECK: @.str{{.*}} = private unnamed_addr constant {{.*}}, align 1 // CHECK: @.str[[STR1:.*]] = private unnamed_addr constant [7 x i8] c"mangle\00", align 1 -// CHECK: define internal void @__mangle_block_invoke(i8* noundef %.block_descriptor) +// CHECK: define internal void @__mangle_block_invoke(i8* %.block_descriptor) -// CHECK: define internal void @__mangle_block_invoke_2(i8* noundef %.block_descriptor){{.*}}{ -// CHECK: call void @__assert_rtn(i8* noundef getelementptr inbounds ([22 x i8], [22 x i8]* @__func__.__mangle_block_invoke_2, i32 0, i32 0), i8* noundef getelementptr inbounds {{.*}}, i32 noundef 9, i8* noundef getelementptr inbounds ([7 x i8], [7 x i8]* @.str[[STR1]], i32 0, i32 0)) +// CHECK: define internal void @__mangle_block_invoke_2(i8* %.block_descriptor){{.*}}{ +// CHECK: call void @__assert_rtn(i8* getelementptr inbounds ([22 x i8], [22 x i8]* @__func__.__mangle_block_invoke_2, i32 0, i32 0), i8* getelementptr inbounds {{.*}}, i32 9, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str[[STR1]], i32 0, i32 0)) // CHECK: } diff --git a/clang/test/CodeGen/mangle-windows.c b/clang/test/CodeGen/mangle-windows.c index c717439e67b3f5a9d9cd550a946e043aed1b0c05..9e7aaec21dfba145c5a2cafc94490ec6137218ef 100644 --- a/clang/test/CodeGen/mangle-windows.c +++ b/clang/test/CodeGen/mangle-windows.c @@ -47,7 +47,7 @@ void __fastcall f8(long long a) {} // X64: define dso_local void @f8( void __fastcall f9(long long a, char b, char c, short d) {} -// CHECK: define dso_local x86_fastcallcc void @"\01@f9@20"(i64 noundef %a, i8 noundef signext %b, i8 noundef signext %c, i16 noundef signext %d) +// CHECK: define dso_local x86_fastcallcc void @"\01@f9@20"(i64 %a, i8 signext %b, i8 signext %c, i16 signext %d) // X64: define dso_local void @f9( void f12(void) {} diff --git a/clang/test/CodeGen/math-builtins-long.c b/clang/test/CodeGen/math-builtins-long.c index 6231bb6a63696406974ff4d75225fbbd0eb95a26..f5cee75acad639e60315d46c2623ab422835b5c0 100644 --- a/clang/test/CodeGen/math-builtins-long.c +++ b/clang/test/CodeGen/math-builtins-long.c @@ -10,16 +10,16 @@ void bar(long double); void foo(long double f, long double *l, int *i, const char *c) { - // F80: call x86_fp80 @fmodl(x86_fp80 noundef %{{.+}}, x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @fmodl(ppc_fp128 noundef %{{.+}}, ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @fmodl(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) - // PPCF128: call fp128 @fmodf128(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) + // F80: call x86_fp80 @fmodl(x86_fp80 %{{.+}}, x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @fmodl(ppc_fp128 %{{.+}}, ppc_fp128 %{{.+}}) + // X86F128: call fp128 @fmodl(fp128 %{{.+}}, fp128 %{{.+}}) + // PPCF128: call fp128 @fmodf128(fp128 %{{.+}}, fp128 %{{.+}}) __builtin_fmodl(f,f); - // F80: call x86_fp80 @atan2l(x86_fp80 noundef %{{.+}}, x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @atan2l(ppc_fp128 noundef %{{.+}}, ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @atan2l(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) - // PPCF128: call fp128 @atan2f128(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) + // F80: call x86_fp80 @atan2l(x86_fp80 %{{.+}}, x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @atan2l(ppc_fp128 %{{.+}}, ppc_fp128 %{{.+}}) + // X86F128: call fp128 @atan2l(fp128 %{{.+}}, fp128 %{{.+}}) + // PPCF128: call fp128 @atan2f128(fp128 %{{.+}}, fp128 %{{.+}}) __builtin_atan2l(f,f); // F80: call x86_fp80 @llvm.copysign.f80(x86_fp80 %{{.+}}, x86_fp80 %{{.+}}) @@ -34,10 +34,10 @@ void foo(long double f, long double *l, int *i, const char *c) { // PPCF128: call fp128 @llvm.fabs.f128(fp128 %{{.+}}) __builtin_fabsl(f); - // F80: call x86_fp80 @frexpl(x86_fp80 noundef %{{.+}}, i32* noundef %{{.+}}) - // PPC: call ppc_fp128 @frexpl(ppc_fp128 noundef %{{.+}}, i32* noundef %{{.+}}) - // X86F128: call fp128 @frexpl(fp128 noundef %{{.+}}, i32* noundef %{{.+}}) - // PPCF128: call fp128 @frexpf128(fp128 noundef %{{.+}}, i32* noundef %{{.+}}) + // F80: call x86_fp80 @frexpl(x86_fp80 %{{.+}}, i32* %{{.+}}) + // PPC: call ppc_fp128 @frexpl(ppc_fp128 %{{.+}}, i32* %{{.+}}) + // X86F128: call fp128 @frexpl(fp128 %{{.+}}, i32* %{{.+}}) + // PPCF128: call fp128 @frexpf128(fp128 %{{.+}}, i32* %{{.+}}) __builtin_frexpl(f,i); // F80: store x86_fp80 0xK7FFF8000000000000000, x86_fp80* @@ -52,76 +52,76 @@ void foo(long double f, long double *l, int *i, const char *c) { // PPCF128: store fp128 0xL00000000000000007FFF000000000000, fp128* *l = __builtin_infl(); - // F80: call x86_fp80 @ldexpl(x86_fp80 noundef %{{.+}}, i32 noundef %{{.+}}) - // PPC: call ppc_fp128 @ldexpl(ppc_fp128 noundef %{{.+}}, {{(signext)?.+}}) - // X86F128: call fp128 @ldexpl(fp128 noundef %{{.+}}, {{(signext)?.+}}) - // PPCF128: call fp128 @ldexpf128(fp128 noundef %{{.+}}, {{(signext)?.+}}) + // F80: call x86_fp80 @ldexpl(x86_fp80 %{{.+}}, i32 %{{.+}}) + // PPC: call ppc_fp128 @ldexpl(ppc_fp128 %{{.+}}, {{(signext)?.+}}) + // X86F128: call fp128 @ldexpl(fp128 %{{.+}}, {{(signext)?.+}}) + // PPCF128: call fp128 @ldexpf128(fp128 %{{.+}}, {{(signext)?.+}}) __builtin_ldexpl(f,f); - // F80: call x86_fp80 @modfl(x86_fp80 noundef %{{.+}}, x86_fp80* noundef %{{.+}}) - // PPC: call ppc_fp128 @modfl(ppc_fp128 noundef %{{.+}}, ppc_fp128* noundef %{{.+}}) - // X86F128: call fp128 @modfl(fp128 noundef %{{.+}}, fp128* noundef %{{.+}}) - // PPCF128: call fp128 @modff128(fp128 noundef %{{.+}}, fp128* noundef %{{.+}}) + // F80: call x86_fp80 @modfl(x86_fp80 %{{.+}}, x86_fp80* %{{.+}}) + // PPC: call ppc_fp128 @modfl(ppc_fp128 %{{.+}}, ppc_fp128* %{{.+}}) + // X86F128: call fp128 @modfl(fp128 %{{.+}}, fp128* %{{.+}}) + // PPCF128: call fp128 @modff128(fp128 %{{.+}}, fp128* %{{.+}}) __builtin_modfl(f,l); - // F80: call x86_fp80 @nanl(i8* noundef %{{.+}}) - // PPC: call ppc_fp128 @nanl(i8* noundef %{{.+}}) - // X86F128: call fp128 @nanl(i8* noundef %{{.+}}) - // PPCF128: call fp128 @nanf128(i8* noundef %{{.+}}) + // F80: call x86_fp80 @nanl(i8* %{{.+}}) + // PPC: call ppc_fp128 @nanl(i8* %{{.+}}) + // X86F128: call fp128 @nanl(i8* %{{.+}}) + // PPCF128: call fp128 @nanf128(i8* %{{.+}}) __builtin_nanl(c); - // F80: call x86_fp80 @nansl(i8* noundef %{{.+}}) - // PPC: call ppc_fp128 @nansl(i8* noundef %{{.+}}) - // X86F128: call fp128 @nansl(i8* noundef %{{.+}}) - // PPCF128: call fp128 @nansf128(i8* noundef %{{.+}}) + // F80: call x86_fp80 @nansl(i8* %{{.+}}) + // PPC: call ppc_fp128 @nansl(i8* %{{.+}}) + // X86F128: call fp128 @nansl(i8* %{{.+}}) + // PPCF128: call fp128 @nansf128(i8* %{{.+}}) __builtin_nansl(c); - // F80: call x86_fp80 @powl(x86_fp80 noundef %{{.+}}, x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @powl(ppc_fp128 noundef %{{.+}}, ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @powl(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) - // PPCF128: call fp128 @powf128(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) + // F80: call x86_fp80 @powl(x86_fp80 %{{.+}}, x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @powl(ppc_fp128 %{{.+}}, ppc_fp128 %{{.+}}) + // X86F128: call fp128 @powl(fp128 %{{.+}}, fp128 %{{.+}}) + // PPCF128: call fp128 @powf128(fp128 %{{.+}}, fp128 %{{.+}}) __builtin_powl(f,f); - // F80: call x86_fp80 @acosl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @acosl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @acosl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @acosf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @acosl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @acosl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @acosl(fp128 %{{.+}}) + // PPCF128: call fp128 @acosf128(fp128 %{{.+}}) __builtin_acosl(f); - // F80: call x86_fp80 @acoshl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @acoshl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @acoshl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @acoshf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @acoshl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @acoshl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @acoshl(fp128 %{{.+}}) + // PPCF128: call fp128 @acoshf128(fp128 %{{.+}}) __builtin_acoshl(f); - // F80: call x86_fp80 @asinl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @asinl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @asinl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @asinf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @asinl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @asinl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @asinl(fp128 %{{.+}}) + // PPCF128: call fp128 @asinf128(fp128 %{{.+}}) __builtin_asinl(f); - // F80: call x86_fp80 @asinhl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @asinhl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @asinhl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @asinhf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @asinhl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @asinhl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @asinhl(fp128 %{{.+}}) + // PPCF128: call fp128 @asinhf128(fp128 %{{.+}}) __builtin_asinhl(f); - // F80: call x86_fp80 @atanl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @atanl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @atanl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @atanf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @atanl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @atanl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @atanl(fp128 %{{.+}}) + // PPCF128: call fp128 @atanf128(fp128 %{{.+}}) __builtin_atanl(f); - // F80: call x86_fp80 @atanhl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @atanhl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @atanhl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @atanhf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @atanhl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @atanhl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @atanhl(fp128 %{{.+}}) + // PPCF128: call fp128 @atanhf128(fp128 %{{.+}}) __builtin_atanhl(f); - // F80: call x86_fp80 @cbrtl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @cbrtl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @cbrtl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @cbrtf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @cbrtl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @cbrtl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @cbrtl(fp128 %{{.+}}) + // PPCF128: call fp128 @cbrtf128(fp128 %{{.+}}) __builtin_cbrtl(f); // F80: call x86_fp80 @llvm.ceil.f80(x86_fp80 %{{.+}}) @@ -130,16 +130,16 @@ void foo(long double f, long double *l, int *i, const char *c) { // PPCF128: call fp128 @llvm.ceil.f128(fp128 %{{.+}}) __builtin_ceill(f); - // F80: call x86_fp80 @cosl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @cosl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @cosl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @cosf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @cosl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @cosl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @cosl(fp128 %{{.+}}) + // PPCF128: call fp128 @cosf128(fp128 %{{.+}}) __builtin_cosl(f); - // F80: call x86_fp80 @coshl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @coshl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @coshl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @coshf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @coshl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @coshl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @coshl(fp128 %{{.+}}) + // PPCF128: call fp128 @coshf128(fp128 %{{.+}}) __builtin_coshl(f); // F80: call x86_fp80 @llvm.floor.f80(x86_fp80 %{{.+}}) @@ -167,7 +167,7 @@ void foo(long double f, long double *l, int *i, const char *c) { __builtin_nearbyintl(f); // F80: call x86_fp80 @llvm.trunc.f80(x86_fp80 %{{.+}}) - // PPC: call ppc_fp128 @llvm.trunc.ppcf128(ppc_fp128 %{{.+}}) + // PPC: call ppc_fp128 @llvm.trunc.ppcf128(ppc_fp128 %{{.+}}) // X86F128: call fp128 @llvm.trunc.f128(fp128 %{{.+}}) // PPCF128: call fp128 @llvm.trunc.f128(fp128 %{{.+}}) __builtin_truncl(f); @@ -184,189 +184,189 @@ void foo(long double f, long double *l, int *i, const char *c) { // PPCF128: call fp128 @llvm.round.f128(fp128 %{{.+}}) __builtin_roundl(f); - // F80: call x86_fp80 @erfl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @erfl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @erfl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @erff128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @erfl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @erfl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @erfl(fp128 %{{.+}}) + // PPCF128: call fp128 @erff128(fp128 %{{.+}}) __builtin_erfl(f); - // F80: call x86_fp80 @erfcl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @erfcl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @erfcl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @erfcf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @erfcl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @erfcl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @erfcl(fp128 %{{.+}}) + // PPCF128: call fp128 @erfcf128(fp128 %{{.+}}) __builtin_erfcl(f); - // F80: call x86_fp80 @expl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @expl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @expl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @expf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @expl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @expl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @expl(fp128 %{{.+}}) + // PPCF128: call fp128 @expf128(fp128 %{{.+}}) __builtin_expl(f); - // F80: call x86_fp80 @exp2l(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @exp2l(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @exp2l(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @exp2f128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @exp2l(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @exp2l(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @exp2l(fp128 %{{.+}}) + // PPCF128: call fp128 @exp2f128(fp128 %{{.+}}) __builtin_exp2l(f); - // F80: call x86_fp80 @expm1l(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @expm1l(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @expm1l(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @expm1f128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @expm1l(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @expm1l(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @expm1l(fp128 %{{.+}}) + // PPCF128: call fp128 @expm1f128(fp128 %{{.+}}) __builtin_expm1l(f); - // F80: call x86_fp80 @fdiml(x86_fp80 noundef %{{.+}}, x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @fdiml(ppc_fp128 noundef %{{.+}}, ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @fdiml(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) - // PPCF128: call fp128 @fdimf128(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) + // F80: call x86_fp80 @fdiml(x86_fp80 %{{.+}}, x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @fdiml(ppc_fp128 %{{.+}}, ppc_fp128 %{{.+}}) + // X86F128: call fp128 @fdiml(fp128 %{{.+}}, fp128 %{{.+}}) + // PPCF128: call fp128 @fdimf128(fp128 %{{.+}}, fp128 %{{.+}}) __builtin_fdiml(f,f); - // F80: call x86_fp80 @fmal(x86_fp80 noundef %{{.+}}, x86_fp80 noundef %{{.+}}, x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @fmal(ppc_fp128 noundef %{{.+}}, ppc_fp128 noundef %{{.+}}, ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @fmal(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) - // PPCF128: call fp128 @fmaf128(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) + // F80: call x86_fp80 @fmal(x86_fp80 %{{.+}}, x86_fp80 %{{.+}}, x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @fmal(ppc_fp128 %{{.+}}, ppc_fp128 %{{.+}}, ppc_fp128 %{{.+}}) + // X86F128: call fp128 @fmal(fp128 %{{.+}}, fp128 %{{.+}}, fp128 %{{.+}}) + // PPCF128: call fp128 @fmaf128(fp128 %{{.+}}, fp128 %{{.+}}, fp128 %{{.+}}) __builtin_fmal(f,f,f); - // F80: call x86_fp80 @hypotl(x86_fp80 noundef %{{.+}}, x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @hypotl(ppc_fp128 noundef %{{.+}}, ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @hypotl(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) - // PPCF128: call fp128 @hypotf128(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) + // F80: call x86_fp80 @hypotl(x86_fp80 %{{.+}}, x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @hypotl(ppc_fp128 %{{.+}}, ppc_fp128 %{{.+}}) + // X86F128: call fp128 @hypotl(fp128 %{{.+}}, fp128 %{{.+}}) + // PPCF128: call fp128 @hypotf128(fp128 %{{.+}}, fp128 %{{.+}}) __builtin_hypotl(f,f); - // F80: call i32 @ilogbl(x86_fp80 noundef %{{.+}}) - // PPC: call {{(i32)|(signext i32)}} @ilogbl(ppc_fp128 noundef %{{.+}}) - // X86F128: call {{(i32)|(signext i32)}} @ilogbl(fp128 noundef %{{.+}}) - // PPCF128: call {{(i32)|(signext i32)}} @ilogbf128(fp128 noundef %{{.+}}) + // F80: call i32 @ilogbl(x86_fp80 %{{.+}}) + // PPC: call {{(i32)|(signext i32)}} @ilogbl(ppc_fp128 %{{.+}}) + // X86F128: call {{(i32)|(signext i32)}} @ilogbl(fp128 %{{.+}}) + // PPCF128: call {{(i32)|(signext i32)}} @ilogbf128(fp128 %{{.+}}) __builtin_ilogbl(f); - // F80: call x86_fp80 @lgammal(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @lgammal(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @lgammal(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @lgammaf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @lgammal(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @lgammal(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @lgammal(fp128 %{{.+}}) + // PPCF128: call fp128 @lgammaf128(fp128 %{{.+}}) __builtin_lgammal(f); - // F80: call i64 @llrintl(x86_fp80 noundef %{{.+}}) - // PPC: call i64 @llrintl(ppc_fp128 noundef %{{.+}}) - // X86F128: call i64 @llrintl(fp128 noundef %{{.+}}) - // PPCF128: call i64 @llrintf128(fp128 noundef %{{.+}}) + // F80: call i64 @llrintl(x86_fp80 %{{.+}}) + // PPC: call i64 @llrintl(ppc_fp128 %{{.+}}) + // X86F128: call i64 @llrintl(fp128 %{{.+}}) + // PPCF128: call i64 @llrintf128(fp128 %{{.+}}) __builtin_llrintl(f); - // F80: call i64 @llroundl(x86_fp80 noundef %{{.+}}) - // PPC: call i64 @llroundl(ppc_fp128 noundef %{{.+}}) - // X86F128: call i64 @llroundl(fp128 noundef %{{.+}}) - // PPCF128: call i64 @llroundf128(fp128 noundef %{{.+}}) + // F80: call i64 @llroundl(x86_fp80 %{{.+}}) + // PPC: call i64 @llroundl(ppc_fp128 %{{.+}}) + // X86F128: call i64 @llroundl(fp128 %{{.+}}) + // PPCF128: call i64 @llroundf128(fp128 %{{.+}}) __builtin_llroundl(f); - // F80: call x86_fp80 @logl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @logl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @logl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @logf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @logl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @logl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @logl(fp128 %{{.+}}) + // PPCF128: call fp128 @logf128(fp128 %{{.+}}) __builtin_logl(f); - // F80: call x86_fp80 @log10l(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @log10l(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @log10l(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @log10f128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @log10l(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @log10l(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @log10l(fp128 %{{.+}}) + // PPCF128: call fp128 @log10f128(fp128 %{{.+}}) __builtin_log10l(f); - // F80: call x86_fp80 @log1pl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @log1pl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @log1pl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @log1pf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @log1pl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @log1pl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @log1pl(fp128 %{{.+}}) + // PPCF128: call fp128 @log1pf128(fp128 %{{.+}}) __builtin_log1pl(f); - // F80: call x86_fp80 @log2l(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @log2l(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @log2l(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @log2f128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @log2l(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @log2l(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @log2l(fp128 %{{.+}}) + // PPCF128: call fp128 @log2f128(fp128 %{{.+}}) __builtin_log2l(f); - // F80: call x86_fp80 @logbl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @logbl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @logbl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @logbf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @logbl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @logbl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @logbl(fp128 %{{.+}}) + // PPCF128: call fp128 @logbf128(fp128 %{{.+}}) __builtin_logbl(f); - // F80: call i64 @lrintl(x86_fp80 noundef %{{.+}}) - // PPC: call i64 @lrintl(ppc_fp128 noundef %{{.+}}) - // X86F128: call i64 @lrintl(fp128 noundef %{{.+}}) - // PPCF128: call i64 @lrintf128(fp128 noundef %{{.+}}) + // F80: call i64 @lrintl(x86_fp80 %{{.+}}) + // PPC: call i64 @lrintl(ppc_fp128 %{{.+}}) + // X86F128: call i64 @lrintl(fp128 %{{.+}}) + // PPCF128: call i64 @lrintf128(fp128 %{{.+}}) __builtin_lrintl(f); - // F80: call i64 @lroundl(x86_fp80 noundef %{{.+}}) - // PPC: call i64 @lroundl(ppc_fp128 noundef %{{.+}}) - // X86F128: call i64 @lroundl(fp128 noundef %{{.+}}) - // PPCF128: call i64 @lroundf128(fp128 noundef %{{.+}}) + // F80: call i64 @lroundl(x86_fp80 %{{.+}}) + // PPC: call i64 @lroundl(ppc_fp128 %{{.+}}) + // X86F128: call i64 @lroundl(fp128 %{{.+}}) + // PPCF128: call i64 @lroundf128(fp128 %{{.+}}) __builtin_lroundl(f); - // F80: call x86_fp80 @nextafterl(x86_fp80 noundef %{{.+}}, x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @nextafterl(ppc_fp128 noundef %{{.+}}, ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @nextafterl(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) - // PPCF128: call fp128 @nextafterf128(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) + // F80: call x86_fp80 @nextafterl(x86_fp80 %{{.+}}, x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @nextafterl(ppc_fp128 %{{.+}}, ppc_fp128 %{{.+}}) + // X86F128: call fp128 @nextafterl(fp128 %{{.+}}, fp128 %{{.+}}) + // PPCF128: call fp128 @nextafterf128(fp128 %{{.+}}, fp128 %{{.+}}) __builtin_nextafterl(f,f); - // F80: call x86_fp80 @nexttowardl(x86_fp80 noundef %{{.+}}, x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @nexttowardl(ppc_fp128 noundef %{{.+}}, ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @nexttowardl(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) - // PPCF128: call fp128 @nexttowardf128(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) + // F80: call x86_fp80 @nexttowardl(x86_fp80 %{{.+}}, x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @nexttowardl(ppc_fp128 %{{.+}}, ppc_fp128 %{{.+}}) + // X86F128: call fp128 @nexttowardl(fp128 %{{.+}}, fp128 %{{.+}}) + // PPCF128: call fp128 @nexttowardf128(fp128 %{{.+}}, fp128 %{{.+}}) __builtin_nexttowardl(f,f); - // F80: call x86_fp80 @remainderl(x86_fp80 noundef %{{.+}}, x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @remainderl(ppc_fp128 noundef %{{.+}}, ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @remainderl(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) - // PPCF128: call fp128 @remainderf128(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}) + // F80: call x86_fp80 @remainderl(x86_fp80 %{{.+}}, x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @remainderl(ppc_fp128 %{{.+}}, ppc_fp128 %{{.+}}) + // X86F128: call fp128 @remainderl(fp128 %{{.+}}, fp128 %{{.+}}) + // PPCF128: call fp128 @remainderf128(fp128 %{{.+}}, fp128 %{{.+}}) __builtin_remainderl(f,f); - // F80: call x86_fp80 @remquol(x86_fp80 noundef %{{.+}}, x86_fp80 noundef %{{.+}}, i32* noundef %{{.+}}) - // PPC: call ppc_fp128 @remquol(ppc_fp128 noundef %{{.+}}, ppc_fp128 noundef %{{.+}}, i32* noundef %{{.+}}) - // X86F128: call fp128 @remquol(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}, i32* noundef %{{.+}}) - // PPCF128: call fp128 @remquof128(fp128 noundef %{{.+}}, fp128 noundef %{{.+}}, i32* noundef %{{.+}}) + // F80: call x86_fp80 @remquol(x86_fp80 %{{.+}}, x86_fp80 %{{.+}}, i32* %{{.+}}) + // PPC: call ppc_fp128 @remquol(ppc_fp128 %{{.+}}, ppc_fp128 %{{.+}}, i32* %{{.+}}) + // X86F128: call fp128 @remquol(fp128 %{{.+}}, fp128 %{{.+}}, i32* %{{.+}}) + // PPCF128: call fp128 @remquof128(fp128 %{{.+}}, fp128 %{{.+}}, i32* %{{.+}}) __builtin_remquol(f,f,i); - // F80: call x86_fp80 @scalblnl(x86_fp80 noundef %{{.+}}, i64 noundef %{{.+}}) - // PPC: call ppc_fp128 @scalblnl(ppc_fp128 noundef %{{.+}}, i64 noundef %{{.+}}) - // X86F128: call fp128 @scalblnl(fp128 noundef %{{.+}}, i64 noundef %{{.+}}) - // PPCF128: call fp128 @scalblnf128(fp128 noundef %{{.+}}, i64 noundef %{{.+}}) + // F80: call x86_fp80 @scalblnl(x86_fp80 %{{.+}}, i64 %{{.+}}) + // PPC: call ppc_fp128 @scalblnl(ppc_fp128 %{{.+}}, i64 %{{.+}}) + // X86F128: call fp128 @scalblnl(fp128 %{{.+}}, i64 %{{.+}}) + // PPCF128: call fp128 @scalblnf128(fp128 %{{.+}}, i64 %{{.+}}) __builtin_scalblnl(f,f); - // F80: call x86_fp80 @scalbnl(x86_fp80 noundef %{{.+}}, i32 noundef %{{.+}}) - // PPC: call ppc_fp128 @scalbnl(ppc_fp128 noundef %{{.+}}, {{(signext)?.+}}) - // X86F128: call fp128 @scalbnl(fp128 noundef %{{.+}}, {{(signext)?.+}}) - // PPCF128: call fp128 @scalbnf128(fp128 noundef %{{.+}}, {{(signext)?.+}}) + // F80: call x86_fp80 @scalbnl(x86_fp80 %{{.+}}, i32 %{{.+}}) + // PPC: call ppc_fp128 @scalbnl(ppc_fp128 %{{.+}}, {{(signext)?.+}}) + // X86F128: call fp128 @scalbnl(fp128 %{{.+}}, {{(signext)?.+}}) + // PPCF128: call fp128 @scalbnf128(fp128 %{{.+}}, {{(signext)?.+}}) __builtin_scalbnl(f,f); - // F80: call x86_fp80 @sinl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @sinl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @sinl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @sinf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @sinl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @sinl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @sinl(fp128 %{{.+}}) + // PPCF128: call fp128 @sinf128(fp128 %{{.+}}) __builtin_sinl(f); - // F80: call x86_fp80 @sinhl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @sinhl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @sinhl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @sinhf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @sinhl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @sinhl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @sinhl(fp128 %{{.+}}) + // PPCF128: call fp128 @sinhf128(fp128 %{{.+}}) __builtin_sinhl(f); - // F80: call x86_fp80 @sqrtl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @sqrtl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @sqrtl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @sqrtf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @sqrtl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @sqrtl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @sqrtl(fp128 %{{.+}}) + // PPCF128: call fp128 @sqrtf128(fp128 %{{.+}}) __builtin_sqrtl(f); - // F80: call x86_fp80 @tanl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @tanl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @tanl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @tanf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @tanl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @tanl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @tanl(fp128 %{{.+}}) + // PPCF128: call fp128 @tanf128(fp128 %{{.+}}) __builtin_tanl(f); - // F80: call x86_fp80 @tanhl(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @tanhl(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @tanhl(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @tanhf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @tanhl(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @tanhl(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @tanhl(fp128 %{{.+}}) + // PPCF128: call fp128 @tanhf128(fp128 %{{.+}}) __builtin_tanhl(f); - // F80: call x86_fp80 @tgammal(x86_fp80 noundef %{{.+}}) - // PPC: call ppc_fp128 @tgammal(ppc_fp128 noundef %{{.+}}) - // X86F128: call fp128 @tgammal(fp128 noundef %{{.+}}) - // PPCF128: call fp128 @tgammaf128(fp128 noundef %{{.+}}) + // F80: call x86_fp80 @tgammal(x86_fp80 %{{.+}}) + // PPC: call ppc_fp128 @tgammal(ppc_fp128 %{{.+}}) + // X86F128: call fp128 @tgammal(fp128 %{{.+}}) + // PPCF128: call fp128 @tgammaf128(fp128 %{{.+}}) __builtin_tgammal(f); } diff --git a/clang/test/CodeGen/math-builtins.c b/clang/test/CodeGen/math-builtins.c index 4c30ed40cd9eb1dbee34c39d7a66e8f0401894ec..80e463c7ddb4ab22a50f44e38589c89ebfa2829f 100644 --- a/clang/test/CodeGen/math-builtins.c +++ b/clang/test/CodeGen/math-builtins.c @@ -13,21 +13,21 @@ void foo(double *d, float f, float *fp, long double *l, int *i, const char *c) { // NO__ERRNO: frem float // NO__ERRNO: frem x86_fp80 // NO__ERRNO: frem fp128 -// HAS_ERRNO: declare double @fmod(double noundef, double noundef) [[NOT_READNONE:#[0-9]+]] -// HAS_ERRNO: declare float @fmodf(float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @fmodl(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @fmodf128(fp128 noundef, fp128 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @fmod(double, double) [[NOT_READNONE:#[0-9]+]] +// HAS_ERRNO: declare float @fmodf(float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @fmodl(x86_fp80, x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @fmodf128(fp128, fp128) [[NOT_READNONE]] __builtin_atan2(f,f); __builtin_atan2f(f,f) ; __builtin_atan2l(f, f); __builtin_atan2f128(f,f); -// NO__ERRNO: declare double @atan2(double noundef, double noundef) [[READNONE:#[0-9]+]] -// NO__ERRNO: declare float @atan2f(float noundef, float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @atan2l(x86_fp80 noundef, x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @atan2f128(fp128 noundef, fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @atan2(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @atan2f(float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @atan2l(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @atan2f128(fp128 noundef, fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @atan2(double, double) [[READNONE:#[0-9]+]] +// NO__ERRNO: declare float @atan2f(float, float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @atan2l(x86_fp80, x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @atan2f128(fp128, fp128) [[READNONE]] +// HAS_ERRNO: declare double @atan2(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @atan2f(float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @atan2l(x86_fp80, x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @atan2f128(fp128, fp128) [[NOT_READNONE]] __builtin_copysign(f,f); __builtin_copysignf(f,f); __builtin_copysignl(f,f); __builtin_copysignf128(f,f); @@ -53,14 +53,14 @@ void foo(double *d, float f, float *fp, long double *l, int *i, const char *c) { __builtin_frexp(f,i); __builtin_frexpf(f,i); __builtin_frexpl(f,i); __builtin_frexpf128(f,i); -// NO__ERRNO: declare double @frexp(double noundef, i32* noundef) [[NOT_READNONE:#[0-9]+]] -// NO__ERRNO: declare float @frexpf(float noundef, i32* noundef) [[NOT_READNONE]] -// NO__ERRNO: declare x86_fp80 @frexpl(x86_fp80 noundef, i32* noundef) [[NOT_READNONE]] -// NO__ERRNO: declare fp128 @frexpf128(fp128 noundef, i32* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare double @frexp(double noundef, i32* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @frexpf(float noundef, i32* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @frexpl(x86_fp80 noundef, i32* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @frexpf128(fp128 noundef, i32* noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @frexp(double, i32*) [[NOT_READNONE:#[0-9]+]] +// NO__ERRNO: declare float @frexpf(float, i32*) [[NOT_READNONE]] +// NO__ERRNO: declare x86_fp80 @frexpl(x86_fp80, i32*) [[NOT_READNONE]] +// NO__ERRNO: declare fp128 @frexpf128(fp128, i32*) [[NOT_READNONE]] +// HAS_ERRNO: declare double @frexp(double, i32*) [[NOT_READNONE]] +// HAS_ERRNO: declare float @frexpf(float, i32*) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @frexpl(x86_fp80, i32*) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @frexpf128(fp128, i32*) [[NOT_READNONE]] __builtin_huge_val(); __builtin_huge_valf(); __builtin_huge_vall(); __builtin_huge_valf128(); @@ -78,47 +78,47 @@ void foo(double *d, float f, float *fp, long double *l, int *i, const char *c) { __builtin_ldexp(f,f); __builtin_ldexpf(f,f); __builtin_ldexpl(f,f); __builtin_ldexpf128(f,f); -// NO__ERRNO: declare double @ldexp(double noundef, i32 noundef) [[READNONE]] -// NO__ERRNO: declare float @ldexpf(float noundef, i32 noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @ldexpl(x86_fp80 noundef, i32 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @ldexpf128(fp128 noundef, i32 noundef) [[READNONE]] -// HAS_ERRNO: declare double @ldexp(double noundef, i32 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @ldexpf(float noundef, i32 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @ldexpl(x86_fp80 noundef, i32 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @ldexpf128(fp128 noundef, i32 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @ldexp(double, i32) [[READNONE]] +// NO__ERRNO: declare float @ldexpf(float, i32) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @ldexpl(x86_fp80, i32) [[READNONE]] +// NO__ERRNO: declare fp128 @ldexpf128(fp128, i32) [[READNONE]] +// HAS_ERRNO: declare double @ldexp(double, i32) [[NOT_READNONE]] +// HAS_ERRNO: declare float @ldexpf(float, i32) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @ldexpl(x86_fp80, i32) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @ldexpf128(fp128, i32) [[NOT_READNONE]] __builtin_modf(f,d); __builtin_modff(f,fp); __builtin_modfl(f,l); __builtin_modff128(f,l); -// NO__ERRNO: declare double @modf(double noundef, double* noundef) [[NOT_READNONE]] -// NO__ERRNO: declare float @modff(float noundef, float* noundef) [[NOT_READNONE]] -// NO__ERRNO: declare x86_fp80 @modfl(x86_fp80 noundef, x86_fp80* noundef) [[NOT_READNONE]] -// NO__ERRNO: declare fp128 @modff128(fp128 noundef, fp128* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare double @modf(double noundef, double* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @modff(float noundef, float* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @modfl(x86_fp80 noundef, x86_fp80* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @modff128(fp128 noundef, fp128* noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @modf(double, double*) [[NOT_READNONE]] +// NO__ERRNO: declare float @modff(float, float*) [[NOT_READNONE]] +// NO__ERRNO: declare x86_fp80 @modfl(x86_fp80, x86_fp80*) [[NOT_READNONE]] +// NO__ERRNO: declare fp128 @modff128(fp128, fp128*) [[NOT_READNONE]] +// HAS_ERRNO: declare double @modf(double, double*) [[NOT_READNONE]] +// HAS_ERRNO: declare float @modff(float, float*) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @modfl(x86_fp80, x86_fp80*) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @modff128(fp128, fp128*) [[NOT_READNONE]] __builtin_nan(c); __builtin_nanf(c); __builtin_nanl(c); __builtin_nanf128(c); -// NO__ERRNO: declare double @nan(i8* noundef) [[PURE:#[0-9]+]] -// NO__ERRNO: declare float @nanf(i8* noundef) [[PURE]] -// NO__ERRNO: declare x86_fp80 @nanl(i8* noundef) [[PURE]] -// NO__ERRNO: declare fp128 @nanf128(i8* noundef) [[PURE]] -// HAS_ERRNO: declare double @nan(i8* noundef) [[PURE:#[0-9]+]] -// HAS_ERRNO: declare float @nanf(i8* noundef) [[PURE]] -// HAS_ERRNO: declare x86_fp80 @nanl(i8* noundef) [[PURE]] -// HAS_ERRNO: declare fp128 @nanf128(i8* noundef) [[PURE]] +// NO__ERRNO: declare double @nan(i8*) [[PURE:#[0-9]+]] +// NO__ERRNO: declare float @nanf(i8*) [[PURE]] +// NO__ERRNO: declare x86_fp80 @nanl(i8*) [[PURE]] +// NO__ERRNO: declare fp128 @nanf128(i8*) [[PURE]] +// HAS_ERRNO: declare double @nan(i8*) [[PURE:#[0-9]+]] +// HAS_ERRNO: declare float @nanf(i8*) [[PURE]] +// HAS_ERRNO: declare x86_fp80 @nanl(i8*) [[PURE]] +// HAS_ERRNO: declare fp128 @nanf128(i8*) [[PURE]] __builtin_nans(c); __builtin_nansf(c); __builtin_nansl(c); __builtin_nansf128(c); -// NO__ERRNO: declare double @nans(i8* noundef) [[PURE]] -// NO__ERRNO: declare float @nansf(i8* noundef) [[PURE]] -// NO__ERRNO: declare x86_fp80 @nansl(i8* noundef) [[PURE]] -// NO__ERRNO: declare fp128 @nansf128(i8* noundef) [[PURE]] -// HAS_ERRNO: declare double @nans(i8* noundef) [[PURE]] -// HAS_ERRNO: declare float @nansf(i8* noundef) [[PURE]] -// HAS_ERRNO: declare x86_fp80 @nansl(i8* noundef) [[PURE]] -// HAS_ERRNO: declare fp128 @nansf128(i8* noundef) [[PURE]] +// NO__ERRNO: declare double @nans(i8*) [[PURE]] +// NO__ERRNO: declare float @nansf(i8*) [[PURE]] +// NO__ERRNO: declare x86_fp80 @nansl(i8*) [[PURE]] +// NO__ERRNO: declare fp128 @nansf128(i8*) [[PURE]] +// HAS_ERRNO: declare double @nans(i8*) [[PURE]] +// HAS_ERRNO: declare float @nansf(i8*) [[PURE]] +// HAS_ERRNO: declare x86_fp80 @nansl(i8*) [[PURE]] +// HAS_ERRNO: declare fp128 @nansf128(i8*) [[PURE]] __builtin_pow(f,f); __builtin_powf(f,f); __builtin_powl(f,f); __builtin_powf128(f,f); @@ -126,10 +126,10 @@ void foo(double *d, float f, float *fp, long double *l, int *i, const char *c) { // NO__ERRNO: declare float @llvm.pow.f32(float, float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.pow.f80(x86_fp80, x86_fp80) [[READNONE_INTRINSIC]] // NO__ERRNO: declare fp128 @llvm.pow.f128(fp128, fp128) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @pow(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @powf(float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @powl(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @powf128(fp128 noundef, fp128 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @pow(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @powf(float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @powl(x86_fp80, x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @powf128(fp128, fp128) [[NOT_READNONE]] __builtin_powi(f,f); __builtin_powif(f,f); __builtin_powil(f,f); @@ -143,80 +143,80 @@ void foo(double *d, float f, float *fp, long double *l, int *i, const char *c) { /* math */ __builtin_acos(f); __builtin_acosf(f); __builtin_acosl(f); __builtin_acosf128(f); -// NO__ERRNO: declare double @acos(double noundef) [[READNONE]] -// NO__ERRNO: declare float @acosf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @acosl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @acosf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @acos(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @acosf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @acosl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @acosf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @acos(double) [[READNONE]] +// NO__ERRNO: declare float @acosf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @acosl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @acosf128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @acos(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @acosf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @acosl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @acosf128(fp128) [[NOT_READNONE]] __builtin_acosh(f); __builtin_acoshf(f); __builtin_acoshl(f); __builtin_acoshf128(f); -// NO__ERRNO: declare double @acosh(double noundef) [[READNONE]] -// NO__ERRNO: declare float @acoshf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @acoshl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @acoshf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @acosh(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @acoshf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @acoshl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @acoshf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @acosh(double) [[READNONE]] +// NO__ERRNO: declare float @acoshf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @acoshl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @acoshf128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @acosh(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @acoshf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @acoshl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @acoshf128(fp128) [[NOT_READNONE]] __builtin_asin(f); __builtin_asinf(f); __builtin_asinl(f); __builtin_asinf128(f); -// NO__ERRNO: declare double @asin(double noundef) [[READNONE]] -// NO__ERRNO: declare float @asinf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @asinl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @asinf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @asin(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @asinf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @asinl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @asinf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @asin(double) [[READNONE]] +// NO__ERRNO: declare float @asinf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @asinl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @asinf128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @asin(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @asinf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @asinl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @asinf128(fp128) [[NOT_READNONE]] __builtin_asinh(f); __builtin_asinhf(f); __builtin_asinhl(f); __builtin_asinhf128(f); -// NO__ERRNO: declare double @asinh(double noundef) [[READNONE]] -// NO__ERRNO: declare float @asinhf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @asinhl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @asinhf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @asinh(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @asinhf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @asinhl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @asinhf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @asinh(double) [[READNONE]] +// NO__ERRNO: declare float @asinhf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @asinhl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @asinhf128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @asinh(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @asinhf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @asinhl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @asinhf128(fp128) [[NOT_READNONE]] __builtin_atan(f); __builtin_atanf(f); __builtin_atanl(f); __builtin_atanf128(f); -// NO__ERRNO: declare double @atan(double noundef) [[READNONE]] -// NO__ERRNO: declare float @atanf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @atanl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @atanf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @atan(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @atanf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @atanl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @atanf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @atan(double) [[READNONE]] +// NO__ERRNO: declare float @atanf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @atanl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @atanf128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @atan(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @atanf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @atanl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @atanf128(fp128) [[NOT_READNONE]] __builtin_atanh(f); __builtin_atanhf(f); __builtin_atanhl(f); __builtin_atanhf128(f); -// NO__ERRNO: declare double @atanh(double noundef) [[READNONE]] -// NO__ERRNO: declare float @atanhf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @atanhl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @atanhf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @atanh(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @atanhf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @atanhl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @atanhf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @atanh(double) [[READNONE]] +// NO__ERRNO: declare float @atanhf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @atanhl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @atanhf128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @atanh(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @atanhf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @atanhl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @atanhf128(fp128) [[NOT_READNONE]] __builtin_cbrt(f); __builtin_cbrtf(f); __builtin_cbrtl(f); __builtin_cbrtf128(f); -// NO__ERRNO: declare double @cbrt(double noundef) [[READNONE]] -// NO__ERRNO: declare float @cbrtf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @cbrtl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @cbrtf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @cbrt(double noundef) [[READNONE:#[0-9]+]] -// HAS_ERRNO: declare float @cbrtf(float noundef) [[READNONE]] -// HAS_ERRNO: declare x86_fp80 @cbrtl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare fp128 @cbrtf128(fp128 noundef) [[READNONE]] +// NO__ERRNO: declare double @cbrt(double) [[READNONE]] +// NO__ERRNO: declare float @cbrtf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @cbrtl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @cbrtf128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @cbrt(double) [[READNONE:#[0-9]+]] +// HAS_ERRNO: declare float @cbrtf(float) [[READNONE]] +// HAS_ERRNO: declare x86_fp80 @cbrtl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare fp128 @cbrtf128(fp128) [[READNONE]] __builtin_ceil(f); __builtin_ceilf(f); __builtin_ceill(f); __builtin_ceilf128(f); @@ -235,43 +235,43 @@ void foo(double *d, float f, float *fp, long double *l, int *i, const char *c) { // NO__ERRNO: declare float @llvm.cos.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.cos.f80(x86_fp80) [[READNONE_INTRINSIC]] // NO__ERRNO: declare fp128 @llvm.cos.f128(fp128) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @cos(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @cosf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @cosl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @cosf128(fp128 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @cos(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @cosf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @cosl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @cosf128(fp128) [[NOT_READNONE]] __builtin_cosh(f); __builtin_coshf(f); __builtin_coshl(f); __builtin_coshf128(f); -// NO__ERRNO: declare double @cosh(double noundef) [[READNONE]] -// NO__ERRNO: declare float @coshf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @coshl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @coshf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @cosh(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @coshf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @coshl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @coshf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @cosh(double) [[READNONE]] +// NO__ERRNO: declare float @coshf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @coshl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @coshf128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @cosh(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @coshf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @coshl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @coshf128(fp128) [[NOT_READNONE]] __builtin_erf(f); __builtin_erff(f); __builtin_erfl(f); __builtin_erff128(f); -// NO__ERRNO: declare double @erf(double noundef) [[READNONE]] -// NO__ERRNO: declare float @erff(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @erfl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @erff128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @erf(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @erff(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @erfl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @erff128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @erf(double) [[READNONE]] +// NO__ERRNO: declare float @erff(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @erfl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @erff128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @erf(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @erff(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @erfl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @erff128(fp128) [[NOT_READNONE]] __builtin_erfc(f); __builtin_erfcf(f); __builtin_erfcl(f); __builtin_erfcf128(f); -// NO__ERRNO: declare double @erfc(double noundef) [[READNONE]] -// NO__ERRNO: declare float @erfcf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @erfcl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @erfcf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @erfc(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @erfcf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @erfcl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @erfcf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @erfc(double) [[READNONE]] +// NO__ERRNO: declare float @erfcf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @erfcl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @erfcf128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @erfc(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @erfcf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @erfcl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @erfcf128(fp128) [[NOT_READNONE]] __builtin_exp(f); __builtin_expf(f); __builtin_expl(f); __builtin_expf128(f); @@ -279,10 +279,10 @@ __builtin_exp(f); __builtin_expf(f); __builtin_expl(f); __builtin_e // NO__ERRNO: declare float @llvm.exp.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.exp.f80(x86_fp80) [[READNONE_INTRINSIC]] // NO__ERRNO: declare fp128 @llvm.exp.f128(fp128) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @exp(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @expf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @expl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @expf128(fp128 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @exp(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @expf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @expl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @expf128(fp128) [[NOT_READNONE]] __builtin_exp2(f); __builtin_exp2f(f); __builtin_exp2l(f); __builtin_exp2f128(f); @@ -290,32 +290,32 @@ __builtin_exp2(f); __builtin_exp2f(f); __builtin_exp2l(f); __builtin_ // NO__ERRNO: declare float @llvm.exp2.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.exp2.f80(x86_fp80) [[READNONE_INTRINSIC]] // NO__ERRNO: declare fp128 @llvm.exp2.f128(fp128) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @exp2(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @exp2f(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @exp2l(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @exp2f128(fp128 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @exp2(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @exp2f(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @exp2l(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @exp2f128(fp128) [[NOT_READNONE]] __builtin_expm1(f); __builtin_expm1f(f); __builtin_expm1l(f); __builtin_expm1f128(f); -// NO__ERRNO: declare double @expm1(double noundef) [[READNONE]] -// NO__ERRNO: declare float @expm1f(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @expm1l(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @expm1f128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @expm1(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @expm1f(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @expm1l(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @expm1f128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @expm1(double) [[READNONE]] +// NO__ERRNO: declare float @expm1f(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @expm1l(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @expm1f128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @expm1(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @expm1f(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @expm1l(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @expm1f128(fp128) [[NOT_READNONE]] __builtin_fdim(f,f); __builtin_fdimf(f,f); __builtin_fdiml(f,f); __builtin_fdimf128(f,f); -// NO__ERRNO: declare double @fdim(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare float @fdimf(float noundef, float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @fdiml(x86_fp80 noundef, x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @fdimf128(fp128 noundef, fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @fdim(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @fdimf(float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @fdiml(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @fdimf128(fp128 noundef, fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @fdim(double, double) [[READNONE]] +// NO__ERRNO: declare float @fdimf(float, float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @fdiml(x86_fp80, x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @fdimf128(fp128, fp128) [[READNONE]] +// HAS_ERRNO: declare double @fdim(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @fdimf(float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @fdiml(x86_fp80, x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @fdimf128(fp128, fp128) [[NOT_READNONE]] __builtin_floor(f); __builtin_floorf(f); __builtin_floorl(f); __builtin_floorf128(f); @@ -334,10 +334,10 @@ __builtin_fma(f,f,f); __builtin_fmaf(f,f,f); __builtin_fmal(f,f,f); // NO__ERRNO: declare float @llvm.fma.f32(float, float, float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.fma.f80(x86_fp80, x86_fp80, x86_fp80) [[READNONE_INTRINSIC]] // NO__ERRNO: declare fp128 @llvm.fma.f128(fp128, fp128, fp128) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @fma(double noundef, double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @fmaf(float noundef, float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @fmal(x86_fp80 noundef, x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @fmaf128(fp128 noundef, fp128 noundef, fp128 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @fma(double, double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @fmaf(float, float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @fmal(x86_fp80, x86_fp80, x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @fmaf128(fp128, fp128, fp128) [[NOT_READNONE]] // On GNU or Win, fma never sets errno, so we can convert to the intrinsic. @@ -378,36 +378,36 @@ __builtin_fmin(f,f); __builtin_fminf(f,f); __builtin_fminl(f,f); __bu __builtin_hypot(f,f); __builtin_hypotf(f,f); __builtin_hypotl(f,f); __builtin_hypotf128(f,f); -// NO__ERRNO: declare double @hypot(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare float @hypotf(float noundef, float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @hypotl(x86_fp80 noundef, x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @hypotf128(fp128 noundef, fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @hypot(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @hypotf(float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @hypotl(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @hypotf128(fp128 noundef, fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @hypot(double, double) [[READNONE]] +// NO__ERRNO: declare float @hypotf(float, float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @hypotl(x86_fp80, x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @hypotf128(fp128, fp128) [[READNONE]] +// HAS_ERRNO: declare double @hypot(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @hypotf(float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @hypotl(x86_fp80, x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @hypotf128(fp128, fp128) [[NOT_READNONE]] __builtin_ilogb(f); __builtin_ilogbf(f); __builtin_ilogbl(f); __builtin_ilogbf128(f); -// NO__ERRNO: declare i32 @ilogb(double noundef) [[READNONE]] -// NO__ERRNO: declare i32 @ilogbf(float noundef) [[READNONE]] -// NO__ERRNO: declare i32 @ilogbl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare i32 @ilogbf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare i32 @ilogb(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i32 @ilogbf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i32 @ilogbl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i32 @ilogbf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare i32 @ilogb(double) [[READNONE]] +// NO__ERRNO: declare i32 @ilogbf(float) [[READNONE]] +// NO__ERRNO: declare i32 @ilogbl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare i32 @ilogbf128(fp128) [[READNONE]] +// HAS_ERRNO: declare i32 @ilogb(double) [[NOT_READNONE]] +// HAS_ERRNO: declare i32 @ilogbf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare i32 @ilogbl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare i32 @ilogbf128(fp128) [[NOT_READNONE]] __builtin_lgamma(f); __builtin_lgammaf(f); __builtin_lgammal(f); __builtin_lgammaf128(f); -// NO__ERRNO: declare double @lgamma(double noundef) [[NOT_READNONE]] -// NO__ERRNO: declare float @lgammaf(float noundef) [[NOT_READNONE]] -// NO__ERRNO: declare x86_fp80 @lgammal(x86_fp80 noundef) [[NOT_READNONE]] -// NO__ERRNO: declare fp128 @lgammaf128(fp128 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare double @lgamma(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @lgammaf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @lgammal(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @lgammaf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @lgamma(double) [[NOT_READNONE]] +// NO__ERRNO: declare float @lgammaf(float) [[NOT_READNONE]] +// NO__ERRNO: declare x86_fp80 @lgammal(x86_fp80) [[NOT_READNONE]] +// NO__ERRNO: declare fp128 @lgammaf128(fp128) [[NOT_READNONE]] +// HAS_ERRNO: declare double @lgamma(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @lgammaf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @lgammal(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @lgammaf128(fp128) [[NOT_READNONE]] __builtin_llrint(f); __builtin_llrintf(f); __builtin_llrintl(f); __builtin_llrintf128(f); @@ -415,10 +415,10 @@ __builtin_llrint(f); __builtin_llrintf(f); __builtin_llrintl(f); __builti // NO__ERRNO: declare i64 @llvm.llrint.i64.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.llrint.i64.f80(x86_fp80) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.llrint.i64.f128(fp128) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare i64 @llrint(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @llrintf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @llrintl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @llrintf128(fp128 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @llrint(double) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @llrintf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @llrintl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @llrintf128(fp128) [[NOT_READNONE]] __builtin_llround(f); __builtin_llroundf(f); __builtin_llroundl(f); __builtin_llroundf128(f); @@ -426,10 +426,10 @@ __builtin_llround(f); __builtin_llroundf(f); __builtin_llroundl(f); __built // NO__ERRNO: declare i64 @llvm.llround.i64.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.llround.i64.f80(x86_fp80) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.llround.i64.f128(fp128) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare i64 @llround(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @llroundf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @llroundl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @llroundf128(fp128 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @llround(double) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @llroundf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @llroundl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @llroundf128(fp128) [[NOT_READNONE]] __builtin_log(f); __builtin_logf(f); __builtin_logl(f); __builtin_logf128(f); @@ -437,10 +437,10 @@ __builtin_log(f); __builtin_logf(f); __builtin_logl(f); __builtin_l // NO__ERRNO: declare float @llvm.log.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.log.f80(x86_fp80) [[READNONE_INTRINSIC]] // NO__ERRNO: declare fp128 @llvm.log.f128(fp128) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @log(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @logf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @logl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @logf128(fp128 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @log(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @logf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @logl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @logf128(fp128) [[NOT_READNONE]] __builtin_log10(f); __builtin_log10f(f); __builtin_log10l(f); __builtin_log10f128(f); @@ -448,21 +448,21 @@ __builtin_log10(f); __builtin_log10f(f); __builtin_log10l(f); __builtin // NO__ERRNO: declare float @llvm.log10.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.log10.f80(x86_fp80) [[READNONE_INTRINSIC]] // NO__ERRNO: declare fp128 @llvm.log10.f128(fp128) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @log10(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @log10f(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @log10l(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @log10f128(fp128 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @log10(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @log10f(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @log10l(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @log10f128(fp128) [[NOT_READNONE]] __builtin_log1p(f); __builtin_log1pf(f); __builtin_log1pl(f); __builtin_log1pf128(f); -// NO__ERRNO: declare double @log1p(double noundef) [[READNONE]] -// NO__ERRNO: declare float @log1pf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @log1pl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @log1pf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @log1p(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @log1pf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @log1pl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @log1pf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @log1p(double) [[READNONE]] +// NO__ERRNO: declare float @log1pf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @log1pl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @log1pf128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @log1p(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @log1pf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @log1pl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @log1pf128(fp128) [[NOT_READNONE]] __builtin_log2(f); __builtin_log2f(f); __builtin_log2l(f); __builtin_log2f128(f); @@ -470,21 +470,21 @@ __builtin_log2(f); __builtin_log2f(f); __builtin_log2l(f); __builtin_ // NO__ERRNO: declare float @llvm.log2.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.log2.f80(x86_fp80) [[READNONE_INTRINSIC]] // NO__ERRNO: declare fp128 @llvm.log2.f128(fp128) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @log2(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @log2f(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @log2l(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @log2f128(fp128 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @log2(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @log2f(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @log2l(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @log2f128(fp128) [[NOT_READNONE]] __builtin_logb(f); __builtin_logbf(f); __builtin_logbl(f); __builtin_logbf128(f); -// NO__ERRNO: declare double @logb(double noundef) [[READNONE]] -// NO__ERRNO: declare float @logbf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @logbl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @logbf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @logb(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @logbf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @logbl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @logbf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @logb(double) [[READNONE]] +// NO__ERRNO: declare float @logbf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @logbl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @logbf128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @logb(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @logbf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @logbl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @logbf128(fp128) [[NOT_READNONE]] __builtin_lrint(f); __builtin_lrintf(f); __builtin_lrintl(f); __builtin_lrintf128(f); @@ -492,10 +492,10 @@ __builtin_lrint(f); __builtin_lrintf(f); __builtin_lrintl(f); __builtin // NO__ERRNO: declare i64 @llvm.lrint.i64.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.lrint.i64.f80(x86_fp80) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.lrint.i64.f128(fp128) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare i64 @lrint(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @lrintf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @lrintl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @lrintf128(fp128 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @lrint(double) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @lrintf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @lrintl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @lrintf128(fp128) [[NOT_READNONE]] __builtin_lround(f); __builtin_lroundf(f); __builtin_lroundl(f); __builtin_lroundf128(f); @@ -503,10 +503,10 @@ __builtin_lround(f); __builtin_lroundf(f); __builtin_lroundl(f); __built // NO__ERRNO: declare i64 @llvm.lround.i64.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.lround.i64.f80(x86_fp80) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.lround.i64.f128(fp128) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare i64 @lround(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @lroundf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @lroundl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @lroundf128(fp128 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @lround(double) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @lroundf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @lroundl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @lroundf128(fp128) [[NOT_READNONE]] __builtin_nearbyint(f); __builtin_nearbyintf(f); __builtin_nearbyintl(f); __builtin_nearbyintf128(f); @@ -521,47 +521,47 @@ __builtin_nearbyint(f); __builtin_nearbyintf(f); __builtin_nearbyintl(f); __bui __builtin_nextafter(f,f); __builtin_nextafterf(f,f); __builtin_nextafterl(f,f); __builtin_nextafterf128(f,f); -// NO__ERRNO: declare double @nextafter(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare float @nextafterf(float noundef, float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @nextafterl(x86_fp80 noundef, x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @nextafterf128(fp128 noundef, fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @nextafter(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @nextafterf(float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @nextafterl(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @nextafterf128(fp128 noundef, fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @nextafter(double, double) [[READNONE]] +// NO__ERRNO: declare float @nextafterf(float, float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @nextafterl(x86_fp80, x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @nextafterf128(fp128, fp128) [[READNONE]] +// HAS_ERRNO: declare double @nextafter(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @nextafterf(float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @nextafterl(x86_fp80, x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @nextafterf128(fp128, fp128) [[NOT_READNONE]] __builtin_nexttoward(f,f); __builtin_nexttowardf(f,f);__builtin_nexttowardl(f,f); __builtin_nexttowardf128(f,f); -// NO__ERRNO: declare double @nexttoward(double noundef, x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare float @nexttowardf(float noundef, x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @nexttowardl(x86_fp80 noundef, x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @nexttowardf128(fp128 noundef, fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @nexttoward(double noundef, x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @nexttowardf(float noundef, x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @nexttowardl(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @nexttowardf128(fp128 noundef, fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @nexttoward(double, x86_fp80) [[READNONE]] +// NO__ERRNO: declare float @nexttowardf(float, x86_fp80) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @nexttowardl(x86_fp80, x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @nexttowardf128(fp128, fp128) [[READNONE]] +// HAS_ERRNO: declare double @nexttoward(double, x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare float @nexttowardf(float, x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @nexttowardl(x86_fp80, x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @nexttowardf128(fp128, fp128) [[NOT_READNONE]] __builtin_remainder(f,f); __builtin_remainderf(f,f); __builtin_remainderl(f,f); __builtin_remainderf128(f,f); -// NO__ERRNO: declare double @remainder(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare float @remainderf(float noundef, float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @remainderl(x86_fp80 noundef, x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @remainderf128(fp128 noundef, fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @remainder(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @remainderf(float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @remainderl(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @remainderf128(fp128 noundef, fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @remainder(double, double) [[READNONE]] +// NO__ERRNO: declare float @remainderf(float, float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @remainderl(x86_fp80, x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @remainderf128(fp128, fp128) [[READNONE]] +// HAS_ERRNO: declare double @remainder(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @remainderf(float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @remainderl(x86_fp80, x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @remainderf128(fp128, fp128) [[NOT_READNONE]] __builtin_remquo(f,f,i); __builtin_remquof(f,f,i); __builtin_remquol(f,f,i); __builtin_remquof128(f,f,i); -// NO__ERRNO: declare double @remquo(double noundef, double noundef, i32* noundef) [[NOT_READNONE]] -// NO__ERRNO: declare float @remquof(float noundef, float noundef, i32* noundef) [[NOT_READNONE]] -// NO__ERRNO: declare x86_fp80 @remquol(x86_fp80 noundef, x86_fp80 noundef, i32* noundef) [[NOT_READNONE]] -// NO__ERRNO: declare fp128 @remquof128(fp128 noundef, fp128 noundef, i32* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare double @remquo(double noundef, double noundef, i32* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @remquof(float noundef, float noundef, i32* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @remquol(x86_fp80 noundef, x86_fp80 noundef, i32* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @remquof128(fp128 noundef, fp128 noundef, i32* noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @remquo(double, double, i32*) [[NOT_READNONE]] +// NO__ERRNO: declare float @remquof(float, float, i32*) [[NOT_READNONE]] +// NO__ERRNO: declare x86_fp80 @remquol(x86_fp80, x86_fp80, i32*) [[NOT_READNONE]] +// NO__ERRNO: declare fp128 @remquof128(fp128, fp128, i32*) [[NOT_READNONE]] +// HAS_ERRNO: declare double @remquo(double, double, i32*) [[NOT_READNONE]] +// HAS_ERRNO: declare float @remquof(float, float, i32*) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @remquol(x86_fp80, x86_fp80, i32*) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @remquof128(fp128, fp128, i32*) [[NOT_READNONE]] __builtin_rint(f); __builtin_rintf(f); __builtin_rintl(f); __builtin_rintf128(f); @@ -587,25 +587,25 @@ __builtin_round(f); __builtin_roundf(f); __builtin_roundl(f); __builtin __builtin_scalbln(f,f); __builtin_scalblnf(f,f); __builtin_scalblnl(f,f); __builtin_scalblnf128(f,f); -// NO__ERRNO: declare double @scalbln(double noundef, i64 noundef) [[READNONE]] -// NO__ERRNO: declare float @scalblnf(float noundef, i64 noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @scalblnl(x86_fp80 noundef, i64 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @scalblnf128(fp128 noundef, i64 noundef) [[READNONE]] -// HAS_ERRNO: declare double @scalbln(double noundef, i64 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @scalblnf(float noundef, i64 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @scalblnl(x86_fp80 noundef, i64 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @scalblnf128(fp128 noundef, i64 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @scalbln(double, i64) [[READNONE]] +// NO__ERRNO: declare float @scalblnf(float, i64) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @scalblnl(x86_fp80, i64) [[READNONE]] +// NO__ERRNO: declare fp128 @scalblnf128(fp128, i64) [[READNONE]] +// HAS_ERRNO: declare double @scalbln(double, i64) [[NOT_READNONE]] +// HAS_ERRNO: declare float @scalblnf(float, i64) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @scalblnl(x86_fp80, i64) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @scalblnf128(fp128, i64) [[NOT_READNONE]] __builtin_scalbn(f,f); __builtin_scalbnf(f,f); __builtin_scalbnl(f,f); __builtin_scalbnf128(f,f); -// NO__ERRNO: declare double @scalbn(double noundef, i32 noundef) [[READNONE]] -// NO__ERRNO: declare float @scalbnf(float noundef, i32 noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @scalbnl(x86_fp80 noundef, i32 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @scalbnf128(fp128 noundef, i32 noundef) [[READNONE]] -// HAS_ERRNO: declare double @scalbn(double noundef, i32 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @scalbnf(float noundef, i32 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @scalbnl(x86_fp80 noundef, i32 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @scalbnf128(fp128 noundef, i32 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @scalbn(double, i32) [[READNONE]] +// NO__ERRNO: declare float @scalbnf(float, i32) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @scalbnl(x86_fp80, i32) [[READNONE]] +// NO__ERRNO: declare fp128 @scalbnf128(fp128, i32) [[READNONE]] +// HAS_ERRNO: declare double @scalbn(double, i32) [[NOT_READNONE]] +// HAS_ERRNO: declare float @scalbnf(float, i32) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @scalbnl(x86_fp80, i32) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @scalbnf128(fp128, i32) [[NOT_READNONE]] __builtin_sin(f); __builtin_sinf(f); __builtin_sinl(f); __builtin_sinf128(f); @@ -613,21 +613,21 @@ __builtin_sin(f); __builtin_sinf(f); __builtin_sinl(f); __builtin_s // NO__ERRNO: declare float @llvm.sin.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.sin.f80(x86_fp80) [[READNONE_INTRINSIC]] // NO__ERRNO: declare fp128 @llvm.sin.f128(fp128) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @sin(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @sinf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @sinl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @sinf128(fp128 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @sin(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @sinf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @sinl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @sinf128(fp128) [[NOT_READNONE]] __builtin_sinh(f); __builtin_sinhf(f); __builtin_sinhl(f); __builtin_sinhf128(f); -// NO__ERRNO: declare double @sinh(double noundef) [[READNONE]] -// NO__ERRNO: declare float @sinhf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @sinhl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @sinhf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @sinh(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @sinhf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @sinhl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @sinhf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @sinh(double) [[READNONE]] +// NO__ERRNO: declare float @sinhf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @sinhl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @sinhf128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @sinh(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @sinhf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @sinhl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @sinhf128(fp128) [[NOT_READNONE]] __builtin_sqrt(f); __builtin_sqrtf(f); __builtin_sqrtl(f); __builtin_sqrtf128(f); @@ -635,43 +635,43 @@ __builtin_sqrt(f); __builtin_sqrtf(f); __builtin_sqrtl(f); __builtin_ // NO__ERRNO: declare float @llvm.sqrt.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.sqrt.f80(x86_fp80) [[READNONE_INTRINSIC]] // NO__ERRNO: declare fp128 @llvm.sqrt.f128(fp128) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @sqrt(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @sqrtf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @sqrtl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @sqrtf128(fp128 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @sqrt(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @sqrtf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @sqrtl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @sqrtf128(fp128) [[NOT_READNONE]] __builtin_tan(f); __builtin_tanf(f); __builtin_tanl(f); __builtin_tanf128(f); -// NO__ERRNO: declare double @tan(double noundef) [[READNONE]] -// NO__ERRNO: declare float @tanf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @tanl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @tanf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @tan(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @tanf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @tanl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @tanf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @tan(double) [[READNONE]] +// NO__ERRNO: declare float @tanf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @tanl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @tanf128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @tan(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @tanf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @tanl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @tanf128(fp128) [[NOT_READNONE]] __builtin_tanh(f); __builtin_tanhf(f); __builtin_tanhl(f); __builtin_tanhf128(f); -// NO__ERRNO: declare double @tanh(double noundef) [[READNONE]] -// NO__ERRNO: declare float @tanhf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @tanhl(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @tanhf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @tanh(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @tanhf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @tanhl(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @tanhf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @tanh(double) [[READNONE]] +// NO__ERRNO: declare float @tanhf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @tanhl(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @tanhf128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @tanh(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @tanhf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @tanhl(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @tanhf128(fp128) [[NOT_READNONE]] __builtin_tgamma(f); __builtin_tgammaf(f); __builtin_tgammal(f); __builtin_tgammaf128(f); -// NO__ERRNO: declare double @tgamma(double noundef) [[READNONE]] -// NO__ERRNO: declare float @tgammaf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @tgammal(x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare fp128 @tgammaf128(fp128 noundef) [[READNONE]] -// HAS_ERRNO: declare double @tgamma(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @tgammaf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @tgammal(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare fp128 @tgammaf128(fp128 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @tgamma(double) [[READNONE]] +// NO__ERRNO: declare float @tgammaf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @tgammal(x86_fp80) [[READNONE]] +// NO__ERRNO: declare fp128 @tgammaf128(fp128) [[READNONE]] +// HAS_ERRNO: declare double @tgamma(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @tgammaf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @tgammal(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare fp128 @tgammaf128(fp128) [[NOT_READNONE]] __builtin_trunc(f); __builtin_truncf(f); __builtin_truncl(f); __builtin_truncf128(f); diff --git a/clang/test/CodeGen/math-libcalls.c b/clang/test/CodeGen/math-libcalls.c index 965eacb110d9dc4a25701e438d464cb99f951b2d..51bdc5218fde5cd9f0b3a49de5b5b26a1274bbcd 100644 --- a/clang/test/CodeGen/math-libcalls.c +++ b/clang/test/CodeGen/math-libcalls.c @@ -11,18 +11,18 @@ void foo(double *d, float f, float *fp, long double *l, int *i, const char *c) { // NO__ERRNO: frem double // NO__ERRNO: frem float // NO__ERRNO: frem x86_fp80 -// HAS_ERRNO: declare double @fmod(double noundef, double noundef) [[NOT_READNONE:#[0-9]+]] -// HAS_ERRNO: declare float @fmodf(float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @fmodl(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @fmod(double, double) [[NOT_READNONE:#[0-9]+]] +// HAS_ERRNO: declare float @fmodf(float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @fmodl(x86_fp80, x86_fp80) [[NOT_READNONE]] atan2(f,f); atan2f(f,f) ; atan2l(f, f); -// NO__ERRNO: declare double @atan2(double noundef, double noundef) [[READNONE:#[0-9]+]] -// NO__ERRNO: declare float @atan2f(float noundef, float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @atan2l(x86_fp80 noundef, x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @atan2(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @atan2f(float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @atan2l(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @atan2(double, double) [[READNONE:#[0-9]+]] +// NO__ERRNO: declare float @atan2f(float, float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @atan2l(x86_fp80, x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @atan2(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @atan2f(float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @atan2l(x86_fp80, x86_fp80) [[NOT_READNONE]] copysign(f,f); copysignf(f,f);copysignl(f,f); @@ -44,112 +44,112 @@ void foo(double *d, float f, float *fp, long double *l, int *i, const char *c) { frexp(f,i); frexpf(f,i); frexpl(f,i); -// NO__ERRNO: declare double @frexp(double noundef, i32* noundef) [[NOT_READNONE:#[0-9]+]] -// NO__ERRNO: declare float @frexpf(float noundef, i32* noundef) [[NOT_READNONE]] -// NO__ERRNO: declare x86_fp80 @frexpl(x86_fp80 noundef, i32* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare double @frexp(double noundef, i32* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @frexpf(float noundef, i32* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @frexpl(x86_fp80 noundef, i32* noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @frexp(double, i32*) [[NOT_READNONE:#[0-9]+]] +// NO__ERRNO: declare float @frexpf(float, i32*) [[NOT_READNONE]] +// NO__ERRNO: declare x86_fp80 @frexpl(x86_fp80, i32*) [[NOT_READNONE]] +// HAS_ERRNO: declare double @frexp(double, i32*) [[NOT_READNONE]] +// HAS_ERRNO: declare float @frexpf(float, i32*) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @frexpl(x86_fp80, i32*) [[NOT_READNONE]] ldexp(f,f); ldexpf(f,f); ldexpl(f,f); -// NO__ERRNO: declare double @ldexp(double noundef, i32 noundef) [[READNONE]] -// NO__ERRNO: declare float @ldexpf(float noundef, i32 noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @ldexpl(x86_fp80 noundef, i32 noundef) [[READNONE]] -// HAS_ERRNO: declare double @ldexp(double noundef, i32 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @ldexpf(float noundef, i32 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @ldexpl(x86_fp80 noundef, i32 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @ldexp(double, i32) [[READNONE]] +// NO__ERRNO: declare float @ldexpf(float, i32) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @ldexpl(x86_fp80, i32) [[READNONE]] +// HAS_ERRNO: declare double @ldexp(double, i32) [[NOT_READNONE]] +// HAS_ERRNO: declare float @ldexpf(float, i32) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @ldexpl(x86_fp80, i32) [[NOT_READNONE]] modf(f,d); modff(f,fp); modfl(f,l); -// NO__ERRNO: declare double @modf(double noundef, double* noundef) [[NOT_READNONE]] -// NO__ERRNO: declare float @modff(float noundef, float* noundef) [[NOT_READNONE]] -// NO__ERRNO: declare x86_fp80 @modfl(x86_fp80 noundef, x86_fp80* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare double @modf(double noundef, double* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @modff(float noundef, float* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @modfl(x86_fp80 noundef, x86_fp80* noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @modf(double, double*) [[NOT_READNONE]] +// NO__ERRNO: declare float @modff(float, float*) [[NOT_READNONE]] +// NO__ERRNO: declare x86_fp80 @modfl(x86_fp80, x86_fp80*) [[NOT_READNONE]] +// HAS_ERRNO: declare double @modf(double, double*) [[NOT_READNONE]] +// HAS_ERRNO: declare float @modff(float, float*) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @modfl(x86_fp80, x86_fp80*) [[NOT_READNONE]] nan(c); nanf(c); nanl(c); -// NO__ERRNO: declare double @nan(i8* noundef) [[READONLY:#[0-9]+]] -// NO__ERRNO: declare float @nanf(i8* noundef) [[READONLY]] -// NO__ERRNO: declare x86_fp80 @nanl(i8* noundef) [[READONLY]] -// HAS_ERRNO: declare double @nan(i8* noundef) [[READONLY:#[0-9]+]] -// HAS_ERRNO: declare float @nanf(i8* noundef) [[READONLY]] -// HAS_ERRNO: declare x86_fp80 @nanl(i8* noundef) [[READONLY]] +// NO__ERRNO: declare double @nan(i8*) [[READONLY:#[0-9]+]] +// NO__ERRNO: declare float @nanf(i8*) [[READONLY]] +// NO__ERRNO: declare x86_fp80 @nanl(i8*) [[READONLY]] +// HAS_ERRNO: declare double @nan(i8*) [[READONLY:#[0-9]+]] +// HAS_ERRNO: declare float @nanf(i8*) [[READONLY]] +// HAS_ERRNO: declare x86_fp80 @nanl(i8*) [[READONLY]] pow(f,f); powf(f,f); powl(f,f); // NO__ERRNO: declare double @llvm.pow.f64(double, double) [[READNONE_INTRINSIC]] // NO__ERRNO: declare float @llvm.pow.f32(float, float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.pow.f80(x86_fp80, x86_fp80) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @pow(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @powf(float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @powl(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @pow(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @powf(float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @powl(x86_fp80, x86_fp80) [[NOT_READNONE]] /* math */ acos(f); acosf(f); acosl(f); -// NO__ERRNO: declare double @acos(double noundef) [[READNONE]] -// NO__ERRNO: declare float @acosf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @acosl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @acos(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @acosf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @acosl(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @acos(double) [[READNONE]] +// NO__ERRNO: declare float @acosf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @acosl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @acos(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @acosf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @acosl(x86_fp80) [[NOT_READNONE]] acosh(f); acoshf(f); acoshl(f); -// NO__ERRNO: declare double @acosh(double noundef) [[READNONE]] -// NO__ERRNO: declare float @acoshf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @acoshl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @acosh(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @acoshf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @acoshl(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @acosh(double) [[READNONE]] +// NO__ERRNO: declare float @acoshf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @acoshl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @acosh(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @acoshf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @acoshl(x86_fp80) [[NOT_READNONE]] asin(f); asinf(f); asinl(f); -// NO__ERRNO: declare double @asin(double noundef) [[READNONE]] -// NO__ERRNO: declare float @asinf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @asinl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @asin(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @asinf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @asinl(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @asin(double) [[READNONE]] +// NO__ERRNO: declare float @asinf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @asinl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @asin(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @asinf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @asinl(x86_fp80) [[NOT_READNONE]] asinh(f); asinhf(f); asinhl(f); -// NO__ERRNO: declare double @asinh(double noundef) [[READNONE]] -// NO__ERRNO: declare float @asinhf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @asinhl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @asinh(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @asinhf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @asinhl(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @asinh(double) [[READNONE]] +// NO__ERRNO: declare float @asinhf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @asinhl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @asinh(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @asinhf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @asinhl(x86_fp80) [[NOT_READNONE]] atan(f); atanf(f); atanl(f); -// NO__ERRNO: declare double @atan(double noundef) [[READNONE]] -// NO__ERRNO: declare float @atanf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @atanl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @atan(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @atanf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @atanl(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @atan(double) [[READNONE]] +// NO__ERRNO: declare float @atanf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @atanl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @atan(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @atanf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @atanl(x86_fp80) [[NOT_READNONE]] atanh(f); atanhf(f); atanhl(f); -// NO__ERRNO: declare double @atanh(double noundef) [[READNONE]] -// NO__ERRNO: declare float @atanhf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @atanhl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @atanh(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @atanhf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @atanhl(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @atanh(double) [[READNONE]] +// NO__ERRNO: declare float @atanhf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @atanhl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @atanh(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @atanhf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @atanhl(x86_fp80) [[NOT_READNONE]] cbrt(f); cbrtf(f); cbrtl(f); -// NO__ERRNO: declare double @cbrt(double noundef) [[READNONE]] -// NO__ERRNO: declare float @cbrtf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @cbrtl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @cbrt(double noundef) [[READNONE:#[0-9]+]] -// HAS_ERRNO: declare float @cbrtf(float noundef) [[READNONE]] -// HAS_ERRNO: declare x86_fp80 @cbrtl(x86_fp80 noundef) [[READNONE]] +// NO__ERRNO: declare double @cbrt(double) [[READNONE]] +// NO__ERRNO: declare float @cbrtf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @cbrtl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @cbrt(double) [[READNONE:#[0-9]+]] +// HAS_ERRNO: declare float @cbrtf(float) [[READNONE]] +// HAS_ERRNO: declare x86_fp80 @cbrtl(x86_fp80) [[READNONE]] ceil(f); ceilf(f); ceill(f); @@ -165,72 +165,72 @@ void foo(double *d, float f, float *fp, long double *l, int *i, const char *c) { // NO__ERRNO: declare double @llvm.cos.f64(double) [[READNONE_INTRINSIC]] // NO__ERRNO: declare float @llvm.cos.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.cos.f80(x86_fp80) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @cos(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @cosf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @cosl(x86_fp80 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @cos(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @cosf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @cosl(x86_fp80) [[NOT_READNONE]] cosh(f); coshf(f); coshl(f); -// NO__ERRNO: declare double @cosh(double noundef) [[READNONE]] -// NO__ERRNO: declare float @coshf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @coshl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @cosh(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @coshf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @coshl(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @cosh(double) [[READNONE]] +// NO__ERRNO: declare float @coshf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @coshl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @cosh(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @coshf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @coshl(x86_fp80) [[NOT_READNONE]] erf(f); erff(f); erfl(f); -// NO__ERRNO: declare double @erf(double noundef) [[READNONE]] -// NO__ERRNO: declare float @erff(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @erfl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @erf(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @erff(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @erfl(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @erf(double) [[READNONE]] +// NO__ERRNO: declare float @erff(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @erfl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @erf(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @erff(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @erfl(x86_fp80) [[NOT_READNONE]] erfc(f); erfcf(f); erfcl(f); -// NO__ERRNO: declare double @erfc(double noundef) [[READNONE]] -// NO__ERRNO: declare float @erfcf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @erfcl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @erfc(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @erfcf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @erfcl(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @erfc(double) [[READNONE]] +// NO__ERRNO: declare float @erfcf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @erfcl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @erfc(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @erfcf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @erfcl(x86_fp80) [[NOT_READNONE]] exp(f); expf(f); expl(f); // NO__ERRNO: declare double @llvm.exp.f64(double) [[READNONE_INTRINSIC]] // NO__ERRNO: declare float @llvm.exp.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.exp.f80(x86_fp80) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @exp(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @expf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @expl(x86_fp80 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @exp(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @expf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @expl(x86_fp80) [[NOT_READNONE]] exp2(f); exp2f(f); exp2l(f); // NO__ERRNO: declare double @llvm.exp2.f64(double) [[READNONE_INTRINSIC]] // NO__ERRNO: declare float @llvm.exp2.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.exp2.f80(x86_fp80) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @exp2(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @exp2f(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @exp2l(x86_fp80 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @exp2(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @exp2f(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @exp2l(x86_fp80) [[NOT_READNONE]] expm1(f); expm1f(f); expm1l(f); -// NO__ERRNO: declare double @expm1(double noundef) [[READNONE]] -// NO__ERRNO: declare float @expm1f(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @expm1l(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @expm1(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @expm1f(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @expm1l(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @expm1(double) [[READNONE]] +// NO__ERRNO: declare float @expm1f(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @expm1l(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @expm1(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @expm1f(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @expm1l(x86_fp80) [[NOT_READNONE]] fdim(f,f); fdimf(f,f); fdiml(f,f); -// NO__ERRNO: declare double @fdim(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare float @fdimf(float noundef, float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @fdiml(x86_fp80 noundef, x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @fdim(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @fdimf(float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @fdiml(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @fdim(double, double) [[READNONE]] +// NO__ERRNO: declare float @fdimf(float, float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @fdiml(x86_fp80, x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @fdim(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @fdimf(float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @fdiml(x86_fp80, x86_fp80) [[NOT_READNONE]] floor(f); floorf(f); floorl(f); @@ -246,9 +246,9 @@ void foo(double *d, float f, float *fp, long double *l, int *i, const char *c) { // NO__ERRNO: declare double @llvm.fma.f64(double, double, double) [[READNONE_INTRINSIC]] // NO__ERRNO: declare float @llvm.fma.f32(float, float, float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.fma.f80(x86_fp80, x86_fp80, x86_fp80) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @fma(double noundef, double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @fmaf(float noundef, float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @fmal(x86_fp80 noundef, x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @fma(double, double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @fmaf(float, float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @fmal(x86_fp80, x86_fp80, x86_fp80) [[NOT_READNONE]] // On GNU or Win, fma never sets errno, so we can convert to the intrinsic. @@ -281,111 +281,111 @@ void foo(double *d, float f, float *fp, long double *l, int *i, const char *c) { hypot(f,f); hypotf(f,f); hypotl(f,f); -// NO__ERRNO: declare double @hypot(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare float @hypotf(float noundef, float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @hypotl(x86_fp80 noundef, x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @hypot(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @hypotf(float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @hypotl(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @hypot(double, double) [[READNONE]] +// NO__ERRNO: declare float @hypotf(float, float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @hypotl(x86_fp80, x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @hypot(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @hypotf(float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @hypotl(x86_fp80, x86_fp80) [[NOT_READNONE]] ilogb(f); ilogbf(f); ilogbl(f); -// NO__ERRNO: declare i32 @ilogb(double noundef) [[READNONE]] -// NO__ERRNO: declare i32 @ilogbf(float noundef) [[READNONE]] -// NO__ERRNO: declare i32 @ilogbl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare i32 @ilogb(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i32 @ilogbf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i32 @ilogbl(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare i32 @ilogb(double) [[READNONE]] +// NO__ERRNO: declare i32 @ilogbf(float) [[READNONE]] +// NO__ERRNO: declare i32 @ilogbl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare i32 @ilogb(double) [[NOT_READNONE]] +// HAS_ERRNO: declare i32 @ilogbf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare i32 @ilogbl(x86_fp80) [[NOT_READNONE]] lgamma(f); lgammaf(f); lgammal(f); -// NO__ERRNO: declare double @lgamma(double noundef) [[NOT_READNONE]] -// NO__ERRNO: declare float @lgammaf(float noundef) [[NOT_READNONE]] -// NO__ERRNO: declare x86_fp80 @lgammal(x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare double @lgamma(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @lgammaf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @lgammal(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @lgamma(double) [[NOT_READNONE]] +// NO__ERRNO: declare float @lgammaf(float) [[NOT_READNONE]] +// NO__ERRNO: declare x86_fp80 @lgammal(x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare double @lgamma(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @lgammaf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @lgammal(x86_fp80) [[NOT_READNONE]] llrint(f); llrintf(f); llrintl(f); // NO__ERRNO: declare i64 @llvm.llrint.i64.f64(double) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.llrint.i64.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.llrint.i64.f80(x86_fp80) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare i64 @llrint(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @llrintf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @llrintl(x86_fp80 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @llrint(double) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @llrintf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @llrintl(x86_fp80) [[NOT_READNONE]] llround(f); llroundf(f); llroundl(f); // NO__ERRNO: declare i64 @llvm.llround.i64.f64(double) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.llround.i64.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.llround.i64.f80(x86_fp80) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare i64 @llround(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @llroundf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @llroundl(x86_fp80 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @llround(double) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @llroundf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @llroundl(x86_fp80) [[NOT_READNONE]] log(f); logf(f); logl(f); // NO__ERRNO: declare double @llvm.log.f64(double) [[READNONE_INTRINSIC]] // NO__ERRNO: declare float @llvm.log.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.log.f80(x86_fp80) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @log(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @logf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @logl(x86_fp80 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @log(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @logf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @logl(x86_fp80) [[NOT_READNONE]] log10(f); log10f(f); log10l(f); // NO__ERRNO: declare double @llvm.log10.f64(double) [[READNONE_INTRINSIC]] // NO__ERRNO: declare float @llvm.log10.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.log10.f80(x86_fp80) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @log10(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @log10f(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @log10l(x86_fp80 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @log10(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @log10f(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @log10l(x86_fp80) [[NOT_READNONE]] log1p(f); log1pf(f); log1pl(f); -// NO__ERRNO: declare double @log1p(double noundef) [[READNONE]] -// NO__ERRNO: declare float @log1pf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @log1pl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @log1p(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @log1pf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @log1pl(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @log1p(double) [[READNONE]] +// NO__ERRNO: declare float @log1pf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @log1pl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @log1p(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @log1pf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @log1pl(x86_fp80) [[NOT_READNONE]] log2(f); log2f(f); log2l(f); // NO__ERRNO: declare double @llvm.log2.f64(double) [[READNONE_INTRINSIC]] // NO__ERRNO: declare float @llvm.log2.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.log2.f80(x86_fp80) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @log2(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @log2f(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @log2l(x86_fp80 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @log2(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @log2f(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @log2l(x86_fp80) [[NOT_READNONE]] logb(f); logbf(f); logbl(f); -// NO__ERRNO: declare double @logb(double noundef) [[READNONE]] -// NO__ERRNO: declare float @logbf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @logbl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @logb(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @logbf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @logbl(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @logb(double) [[READNONE]] +// NO__ERRNO: declare float @logbf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @logbl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @logb(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @logbf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @logbl(x86_fp80) [[NOT_READNONE]] lrint(f); lrintf(f); lrintl(f); // NO__ERRNO: declare i64 @llvm.lrint.i64.f64(double) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.lrint.i64.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.lrint.i64.f80(x86_fp80) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare i64 @lrint(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @lrintf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @lrintl(x86_fp80 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @lrint(double) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @lrintf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @lrintl(x86_fp80) [[NOT_READNONE]] lround(f); lroundf(f); lroundl(f); // NO__ERRNO: declare i64 @llvm.lround.i64.f64(double) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.lround.i64.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare i64 @llvm.lround.i64.f80(x86_fp80) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare i64 @lround(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @lroundf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare i64 @lroundl(x86_fp80 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @lround(double) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @lroundf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare i64 @lroundl(x86_fp80) [[NOT_READNONE]] nearbyint(f); nearbyintf(f); nearbyintl(f); @@ -398,39 +398,39 @@ void foo(double *d, float f, float *fp, long double *l, int *i, const char *c) { nextafter(f,f); nextafterf(f,f); nextafterl(f,f); -// NO__ERRNO: declare double @nextafter(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare float @nextafterf(float noundef, float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @nextafterl(x86_fp80 noundef, x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @nextafter(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @nextafterf(float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @nextafterl(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @nextafter(double, double) [[READNONE]] +// NO__ERRNO: declare float @nextafterf(float, float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @nextafterl(x86_fp80, x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @nextafter(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @nextafterf(float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @nextafterl(x86_fp80, x86_fp80) [[NOT_READNONE]] nexttoward(f,f); nexttowardf(f,f);nexttowardl(f,f); -// NO__ERRNO: declare double @nexttoward(double noundef, x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare float @nexttowardf(float noundef, x86_fp80 noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @nexttowardl(x86_fp80 noundef, x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @nexttoward(double noundef, x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @nexttowardf(float noundef, x86_fp80 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @nexttowardl(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @nexttoward(double, x86_fp80) [[READNONE]] +// NO__ERRNO: declare float @nexttowardf(float, x86_fp80) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @nexttowardl(x86_fp80, x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @nexttoward(double, x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare float @nexttowardf(float, x86_fp80) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @nexttowardl(x86_fp80, x86_fp80) [[NOT_READNONE]] remainder(f,f); remainderf(f,f); remainderl(f,f); -// NO__ERRNO: declare double @remainder(double noundef, double noundef) [[READNONE]] -// NO__ERRNO: declare float @remainderf(float noundef, float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @remainderl(x86_fp80 noundef, x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @remainder(double noundef, double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @remainderf(float noundef, float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @remainderl(x86_fp80 noundef, x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @remainder(double, double) [[READNONE]] +// NO__ERRNO: declare float @remainderf(float, float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @remainderl(x86_fp80, x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @remainder(double, double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @remainderf(float, float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @remainderl(x86_fp80, x86_fp80) [[NOT_READNONE]] remquo(f,f,i); remquof(f,f,i); remquol(f,f,i); -// NO__ERRNO: declare double @remquo(double noundef, double noundef, i32* noundef) [[NOT_READNONE]] -// NO__ERRNO: declare float @remquof(float noundef, float noundef, i32* noundef) [[NOT_READNONE]] -// NO__ERRNO: declare x86_fp80 @remquol(x86_fp80 noundef, x86_fp80 noundef, i32* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare double @remquo(double noundef, double noundef, i32* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @remquof(float noundef, float noundef, i32* noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @remquol(x86_fp80 noundef, x86_fp80 noundef, i32* noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @remquo(double, double, i32*) [[NOT_READNONE]] +// NO__ERRNO: declare float @remquof(float, float, i32*) [[NOT_READNONE]] +// NO__ERRNO: declare x86_fp80 @remquol(x86_fp80, x86_fp80, i32*) [[NOT_READNONE]] +// HAS_ERRNO: declare double @remquo(double, double, i32*) [[NOT_READNONE]] +// HAS_ERRNO: declare float @remquof(float, float, i32*) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @remquol(x86_fp80, x86_fp80, i32*) [[NOT_READNONE]] rint(f); rintf(f); rintl(f); @@ -452,75 +452,75 @@ void foo(double *d, float f, float *fp, long double *l, int *i, const char *c) { scalbln(f,f); scalblnf(f,f); scalblnl(f,f); -// NO__ERRNO: declare double @scalbln(double noundef, i64 noundef) [[READNONE]] -// NO__ERRNO: declare float @scalblnf(float noundef, i64 noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @scalblnl(x86_fp80 noundef, i64 noundef) [[READNONE]] -// HAS_ERRNO: declare double @scalbln(double noundef, i64 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @scalblnf(float noundef, i64 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @scalblnl(x86_fp80 noundef, i64 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @scalbln(double, i64) [[READNONE]] +// NO__ERRNO: declare float @scalblnf(float, i64) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @scalblnl(x86_fp80, i64) [[READNONE]] +// HAS_ERRNO: declare double @scalbln(double, i64) [[NOT_READNONE]] +// HAS_ERRNO: declare float @scalblnf(float, i64) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @scalblnl(x86_fp80, i64) [[NOT_READNONE]] scalbn(f,f); scalbnf(f,f); scalbnl(f,f); -// NO__ERRNO: declare double @scalbn(double noundef, i32 noundef) [[READNONE]] -// NO__ERRNO: declare float @scalbnf(float noundef, i32 noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @scalbnl(x86_fp80 noundef, i32 noundef) [[READNONE]] -// HAS_ERRNO: declare double @scalbn(double noundef, i32 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @scalbnf(float noundef, i32 noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @scalbnl(x86_fp80 noundef, i32 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @scalbn(double, i32) [[READNONE]] +// NO__ERRNO: declare float @scalbnf(float, i32) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @scalbnl(x86_fp80, i32) [[READNONE]] +// HAS_ERRNO: declare double @scalbn(double, i32) [[NOT_READNONE]] +// HAS_ERRNO: declare float @scalbnf(float, i32) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @scalbnl(x86_fp80, i32) [[NOT_READNONE]] sin(f); sinf(f); sinl(f); // NO__ERRNO: declare double @llvm.sin.f64(double) [[READNONE_INTRINSIC]] // NO__ERRNO: declare float @llvm.sin.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.sin.f80(x86_fp80) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @sin(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @sinf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @sinl(x86_fp80 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @sin(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @sinf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @sinl(x86_fp80) [[NOT_READNONE]] sinh(f); sinhf(f); sinhl(f); -// NO__ERRNO: declare double @sinh(double noundef) [[READNONE]] -// NO__ERRNO: declare float @sinhf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @sinhl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @sinh(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @sinhf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @sinhl(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @sinh(double) [[READNONE]] +// NO__ERRNO: declare float @sinhf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @sinhl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @sinh(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @sinhf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @sinhl(x86_fp80) [[NOT_READNONE]] sqrt(f); sqrtf(f); sqrtl(f); // NO__ERRNO: declare double @llvm.sqrt.f64(double) [[READNONE_INTRINSIC]] // NO__ERRNO: declare float @llvm.sqrt.f32(float) [[READNONE_INTRINSIC]] // NO__ERRNO: declare x86_fp80 @llvm.sqrt.f80(x86_fp80) [[READNONE_INTRINSIC]] -// HAS_ERRNO: declare double @sqrt(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @sqrtf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @sqrtl(x86_fp80 noundef) [[NOT_READNONE]] +// HAS_ERRNO: declare double @sqrt(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @sqrtf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @sqrtl(x86_fp80) [[NOT_READNONE]] tan(f); tanf(f); tanl(f); -// NO__ERRNO: declare double @tan(double noundef) [[READNONE]] -// NO__ERRNO: declare float @tanf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @tanl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @tan(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @tanf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @tanl(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @tan(double) [[READNONE]] +// NO__ERRNO: declare float @tanf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @tanl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @tan(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @tanf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @tanl(x86_fp80) [[NOT_READNONE]] tanh(f); tanhf(f); tanhl(f); -// NO__ERRNO: declare double @tanh(double noundef) [[READNONE]] -// NO__ERRNO: declare float @tanhf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @tanhl(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @tanh(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @tanhf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @tanhl(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @tanh(double) [[READNONE]] +// NO__ERRNO: declare float @tanhf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @tanhl(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @tanh(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @tanhf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @tanhl(x86_fp80) [[NOT_READNONE]] tgamma(f); tgammaf(f); tgammal(f); -// NO__ERRNO: declare double @tgamma(double noundef) [[READNONE]] -// NO__ERRNO: declare float @tgammaf(float noundef) [[READNONE]] -// NO__ERRNO: declare x86_fp80 @tgammal(x86_fp80 noundef) [[READNONE]] -// HAS_ERRNO: declare double @tgamma(double noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare float @tgammaf(float noundef) [[NOT_READNONE]] -// HAS_ERRNO: declare x86_fp80 @tgammal(x86_fp80 noundef) [[NOT_READNONE]] +// NO__ERRNO: declare double @tgamma(double) [[READNONE]] +// NO__ERRNO: declare float @tgammaf(float) [[READNONE]] +// NO__ERRNO: declare x86_fp80 @tgammal(x86_fp80) [[READNONE]] +// HAS_ERRNO: declare double @tgamma(double) [[NOT_READNONE]] +// HAS_ERRNO: declare float @tgammaf(float) [[NOT_READNONE]] +// HAS_ERRNO: declare x86_fp80 @tgammal(x86_fp80) [[NOT_READNONE]] trunc(f); truncf(f); truncl(f); diff --git a/clang/test/CodeGen/matrix-cast.c b/clang/test/CodeGen/matrix-cast.c index 2cda3f8f92b681dbcb73bb0b19f5b4182b2bf563..ad8f67acacdfb5a3bd1846cc8f0d818dd5050c3e 100644 --- a/clang/test/CodeGen/matrix-cast.c +++ b/clang/test/CodeGen/matrix-cast.c @@ -10,7 +10,7 @@ typedef unsigned int unsigned_int_5x5 __attribute__((matrix_type(5, 5))); typedef unsigned long unsigned_long_int_5x5 __attribute__((matrix_type(5, 5))); void cast_char_matrix_to_int(cx5x5 c, ix5x5 i) { - // CHECK-LABEL: define{{.*}} void @cast_char_matrix_to_int(<25 x i8> noundef %c, <25 x i32> noundef %i) + // CHECK-LABEL: define{{.*}} void @cast_char_matrix_to_int(<25 x i8> %c, <25 x i32> %i) // CHECK: [[C:%.*]] = load <25 x i8>, <25 x i8>* {{.*}}, align 1 // CHECK-NEXT: [[CONV:%.*]] = sext <25 x i8> [[C]] to <25 x i32> // CHECK-NEXT: store <25 x i32> [[CONV]], <25 x i32>* {{.*}}, align 4 @@ -20,7 +20,7 @@ void cast_char_matrix_to_int(cx5x5 c, ix5x5 i) { } void cast_char_matrix_to_unsigned_int(cx5x5 c, unsigned_int_5x5 u) { - // CHECK-LABEL: define{{.*}} void @cast_char_matrix_to_unsigned_int(<25 x i8> noundef %c, <25 x i32> noundef %u) + // CHECK-LABEL: define{{.*}} void @cast_char_matrix_to_unsigned_int(<25 x i8> %c, <25 x i32> %u) // CHECK: [[C:%.*]] = load <25 x i8>, <25 x i8>* {{.*}}, align 1 // CHECK-NEXT: [[CONV:%.*]] = sext <25 x i8> [[C]] to <25 x i32> // CHECK-NEXT: store <25 x i32> [[CONV]], <25 x i32>* {{.*}}, align 4 @@ -30,7 +30,7 @@ void cast_char_matrix_to_unsigned_int(cx5x5 c, unsigned_int_5x5 u) { } void cast_unsigned_long_int_matrix_to_short(unsigned_long_int_5x5 u, sx5x5 s) { - // CHECK-LABEL: define{{.*}} void @cast_unsigned_long_int_matrix_to_short(<25 x i64> noundef %u, <25 x i16> noundef %s) + // CHECK-LABEL: define{{.*}} void @cast_unsigned_long_int_matrix_to_short(<25 x i64> %u, <25 x i16> %s) // CHECK: [[U:%.*]] = load <25 x i64>, <25 x i64>* {{.*}}, align 8 // CHECK-NEXT: [[CONV:%.*]] = trunc <25 x i64> [[U]] to <25 x i16> // CHECK-NEXT: store <25 x i16> [[CONV]], <25 x i16>* {{.*}}, align 2 @@ -40,7 +40,7 @@ void cast_unsigned_long_int_matrix_to_short(unsigned_long_int_5x5 u, sx5x5 s) { } void cast_int_matrix_to_short(ix5x5 i, sx5x5 s) { - // CHECK-LABEL: define{{.*}} void @cast_int_matrix_to_short(<25 x i32> noundef %i, <25 x i16> noundef %s) + // CHECK-LABEL: define{{.*}} void @cast_int_matrix_to_short(<25 x i32> %i, <25 x i16> %s) // CHECK: [[I:%.*]] = load <25 x i32>, <25 x i32>* {{.*}}, align 4 // CHECK-NEXT: [[CONV:%.*]] = trunc <25 x i32> [[I]] to <25 x i16> // CHECK-NEXT: store <25 x i16> [[CONV]], <25 x i16>* {{.*}}, align 2 @@ -50,7 +50,7 @@ void cast_int_matrix_to_short(ix5x5 i, sx5x5 s) { } void cast_int_matrix_to_float(ix5x5 i, fx5x5 f) { - // CHECK-LABEL: define{{.*}} void @cast_int_matrix_to_float(<25 x i32> noundef %i, <25 x float> noundef %f) + // CHECK-LABEL: define{{.*}} void @cast_int_matrix_to_float(<25 x i32> %i, <25 x float> %f) // CHECK: [[I:%.*]] = load <25 x i32>, <25 x i32>* {{.*}}, align 4 // CHECK-NEXT: [[CONV:%.*]] = sitofp <25 x i32> [[I]] to <25 x float> // CHECK-NEXT: store <25 x float> [[CONV]], <25 x float>* {{.*}}, align 4 @@ -60,7 +60,7 @@ void cast_int_matrix_to_float(ix5x5 i, fx5x5 f) { } void cast_unsigned_int_matrix_to_float(unsigned_short_int_5x5 u, fx5x5 f) { - // CHECK-LABEL: define{{.*}} void @cast_unsigned_int_matrix_to_float(<25 x i16> noundef %u, <25 x float> noundef %f) + // CHECK-LABEL: define{{.*}} void @cast_unsigned_int_matrix_to_float(<25 x i16> %u, <25 x float> %f) // CHECK: [[U:%.*]] = load <25 x i16>, <25 x i16>* {{.*}}, align 2 // CHECK-NEXT: [[CONV:%.*]] = uitofp <25 x i16> [[U]] to <25 x float> // CHECK-NEXT: store <25 x float> [[CONV]], <25 x float>* {{.*}}, align 4 @@ -70,7 +70,7 @@ void cast_unsigned_int_matrix_to_float(unsigned_short_int_5x5 u, fx5x5 f) { } void cast_double_matrix_to_int(dx5x5 d, ix5x5 i) { - // CHECK-LABEL: define{{.*}} void @cast_double_matrix_to_int(<25 x double> noundef %d, <25 x i32> noundef %i) + // CHECK-LABEL: define{{.*}} void @cast_double_matrix_to_int(<25 x double> %d, <25 x i32> %i) // CHECK: [[D:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[CONV:%.*]] = fptosi <25 x double> [[D]] to <25 x i32> // CHECK-NEXT: store <25 x i32> [[CONV]], <25 x i32>* {{.*}}, align 4 @@ -80,7 +80,7 @@ void cast_double_matrix_to_int(dx5x5 d, ix5x5 i) { } void cast_float_matrix_to_unsigned_short_int(fx5x5 f, unsigned_short_int_5x5 i) { - // CHECK-LABEL: define{{.*}} void @cast_float_matrix_to_unsigned_short_int(<25 x float> noundef %f, <25 x i16> noundef %i) + // CHECK-LABEL: define{{.*}} void @cast_float_matrix_to_unsigned_short_int(<25 x float> %f, <25 x i16> %i) // CHECK: [[F:%.*]] = load <25 x float>, <25 x float>* {{.*}}, align 4 // CHECK-NEXT: [[CONV:%.*]] = fptoui <25 x float> [[F]] to <25 x i16> // CHECK-NEXT: store <25 x i16> [[CONV]], <25 x i16>* %1, align 2 @@ -90,7 +90,7 @@ void cast_float_matrix_to_unsigned_short_int(fx5x5 f, unsigned_short_int_5x5 i) } void cast_double_matrix_to_float(dx5x5 d, fx5x5 f) { - // CHECK-LABEL: define{{.*}} void @cast_double_matrix_to_float(<25 x double> noundef %d, <25 x float> noundef %f) + // CHECK-LABEL: define{{.*}} void @cast_double_matrix_to_float(<25 x double> %d, <25 x float> %f) // CHECK: [[D:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[CONV:%.*]] = fptrunc <25 x double> [[D]] to <25 x float> // CHECK-NEXT: store <25 x float> [[CONV]], <25 x float>* {{.*}}, align 4 @@ -100,7 +100,7 @@ void cast_double_matrix_to_float(dx5x5 d, fx5x5 f) { } void cast_unsigned_short_int_to_unsigned_int(unsigned_short_int_5x5 s, unsigned_int_5x5 i) { - // CHECK-LABEL: define{{.*}} void @cast_unsigned_short_int_to_unsigned_int(<25 x i16> noundef %s, <25 x i32> noundef %i) + // CHECK-LABEL: define{{.*}} void @cast_unsigned_short_int_to_unsigned_int(<25 x i16> %s, <25 x i32> %i) // CHECK: [[S:%.*]] = load <25 x i16>, <25 x i16>* {{.*}}, align 2 // CHECK-NEXT: [[CONV:%.*]] = zext <25 x i16> [[S]] to <25 x i32> // CHECK-NEXT: store <25 x i32> [[CONV]], <25 x i32>* {{.*}}, align 4 @@ -110,7 +110,7 @@ void cast_unsigned_short_int_to_unsigned_int(unsigned_short_int_5x5 s, unsigned_ } void cast_unsigned_long_int_to_unsigned_short_int(unsigned_long_int_5x5 l, unsigned_short_int_5x5 s) { - // CHECK-LABEL: define{{.*}} void @cast_unsigned_long_int_to_unsigned_short_int(<25 x i64> noundef %l, <25 x i16> noundef %s) + // CHECK-LABEL: define{{.*}} void @cast_unsigned_long_int_to_unsigned_short_int(<25 x i64> %l, <25 x i16> %s) // CHECK: [[L:%.*]] = load <25 x i64>, <25 x i64>* %0, align 8 // CHECK-NEXT: [[CONV:%.*]] = trunc <25 x i64> [[L]] to <25 x i16> // CHECK-NEXT: store <25 x i16> [[CONV]], <25 x i16>* {{.*}}, align 2 @@ -120,7 +120,7 @@ void cast_unsigned_long_int_to_unsigned_short_int(unsigned_long_int_5x5 l, unsig } void cast_unsigned_short_int_to_int(unsigned_short_int_5x5 u, ix5x5 i) { - // CHECK-LABEL: define{{.*}} void @cast_unsigned_short_int_to_int(<25 x i16> noundef %u, <25 x i32> noundef %i) + // CHECK-LABEL: define{{.*}} void @cast_unsigned_short_int_to_int(<25 x i16> %u, <25 x i32> %i) // CHECK: [[U:%.*]] = load <25 x i16>, <25 x i16>* %0, align 2 // CHECK-NEXT: [[CONV:%.*]] = zext <25 x i16> [[U]] to <25 x i32> // CHECK-NEXT: store <25 x i32> [[CONV]], <25 x i32>* {{.*}}, align 4 @@ -130,7 +130,7 @@ void cast_unsigned_short_int_to_int(unsigned_short_int_5x5 u, ix5x5 i) { } void cast_int_to_unsigned_long_int(ix5x5 i, unsigned_long_int_5x5 u) { - // CHECK-LABEL: define{{.*}} void @cast_int_to_unsigned_long_int(<25 x i32> noundef %i, <25 x i64> noundef %u) + // CHECK-LABEL: define{{.*}} void @cast_int_to_unsigned_long_int(<25 x i32> %i, <25 x i64> %u) // CHECK: [[I:%.*]] = load <25 x i32>, <25 x i32>* %0, align 4 // CHECK-NEXT: [[CONV:%.*]] = sext <25 x i32> [[I]] to <25 x i64> // CHECK-NEXT: store <25 x i64> [[CONV]], <25 x i64>* {{.*}}, align 8 diff --git a/clang/test/CodeGen/matrix-type-builtins.c b/clang/test/CodeGen/matrix-type-builtins.c index c2868fa26752535c40bd55c996bf9c0405ed3879..ec0be85b7151eab28823973e018694fde3459745 100644 --- a/clang/test/CodeGen/matrix-type-builtins.c +++ b/clang/test/CodeGen/matrix-type-builtins.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -fenable-matrix -triple x86_64-apple-darwin %s -emit-llvm -disable-llvm-passes -o - | FileCheck --check-prefixes=COMMON,CHECK64 %s -// RUN: %clang_cc1 -disable-noundef-analysis -fenable-matrix -triple i386-apple-darwin %s -emit-llvm -disable-llvm-passes -o - | FileCheck --check-prefixes=COMMON,CHECK32 %s +// RUN: %clang_cc1 -fenable-matrix -triple x86_64-apple-darwin %s -emit-llvm -disable-llvm-passes -o - | FileCheck --check-prefixes=COMMON,CHECK64 %s +// RUN: %clang_cc1 -fenable-matrix -triple i386-apple-darwin %s -emit-llvm -disable-llvm-passes -o - | FileCheck --check-prefixes=COMMON,CHECK32 %s // Also check we do not crash when running some middle-end passes. Most // importantly this includes the IR verifier, to ensure we emit valid IR. diff --git a/clang/test/CodeGen/matrix-type-operators-fast-math.c b/clang/test/CodeGen/matrix-type-operators-fast-math.c index 8290173c07b674256d96f4a89714b4b47e0815c1..33b9a51a736a32eb17bf0fc3494e0899237c87c6 100644 --- a/clang/test/CodeGen/matrix-type-operators-fast-math.c +++ b/clang/test/CodeGen/matrix-type-operators-fast-math.c @@ -8,7 +8,7 @@ typedef unsigned long long ullx4x2_t __attribute__((matrix_type(4, 2))); // Floating point matrix/scalar additions. void add_matrix_matrix_double(dx5x5_t a, dx5x5_t b, dx5x5_t c) { - // CHECK-LABEL: define{{.*}} void @add_matrix_matrix_double(<25 x double> noundef %a, <25 x double> noundef %b, <25 x double> noundef %c) + // CHECK-LABEL: define{{.*}} void @add_matrix_matrix_double(<25 x double> %a, <25 x double> %b, <25 x double> %c) // CHECK: [[B:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[C:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[RES:%.*]] = fadd reassoc nnan ninf nsz arcp afn <25 x double> [[B]], [[C]] @@ -18,7 +18,7 @@ void add_matrix_matrix_double(dx5x5_t a, dx5x5_t b, dx5x5_t c) { } void add_compound_assign_matrix_double(dx5x5_t a, dx5x5_t b) { - // CHECK-LABEL: define{{.*}} void @add_compound_assign_matrix_double(<25 x double> noundef %a, <25 x double> noundef %b) + // CHECK-LABEL: define{{.*}} void @add_compound_assign_matrix_double(<25 x double> %a, <25 x double> %b) // CHECK: [[B:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[A:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[RES:%.*]] = fadd reassoc nnan ninf nsz arcp afn <25 x double> [[A]], [[B]] @@ -28,7 +28,7 @@ void add_compound_assign_matrix_double(dx5x5_t a, dx5x5_t b) { } void subtract_compound_assign_matrix_double(dx5x5_t a, dx5x5_t b) { - // CHECK-LABEL: define{{.*}} void @subtract_compound_assign_matrix_double(<25 x double> noundef %a, <25 x double> noundef %b) + // CHECK-LABEL: define{{.*}} void @subtract_compound_assign_matrix_double(<25 x double> %a, <25 x double> %b) // CHECK: [[B:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[A:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[RES:%.*]] = fsub reassoc nnan ninf nsz arcp afn <25 x double> [[A]], [[B]] @@ -38,7 +38,7 @@ void subtract_compound_assign_matrix_double(dx5x5_t a, dx5x5_t b) { } void add_matrix_scalar_double_float(dx5x5_t a, float vf) { - // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_double_float(<25 x double> noundef %a, float noundef %vf) + // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_double_float(<25 x double> %a, float %vf) // CHECK: [[MATRIX:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[SCALAR:%.*]] = load float, float* %vf.addr, align 4 // CHECK-NEXT: [[SCALAR_EXT:%.*]] = fpext float [[SCALAR]] to double @@ -51,7 +51,7 @@ void add_matrix_scalar_double_float(dx5x5_t a, float vf) { } void add_compound_matrix_scalar_double_float(dx5x5_t a, float vf) { - // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_double_float(<25 x double> noundef %a, float noundef %vf) + // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_double_float(<25 x double> %a, float %vf) // CHECK: [[SCALAR:%.*]] = load float, float* %vf.addr, align 4 // CHECK-NEXT: [[SCALAR_EXT:%.*]] = fpext float [[SCALAR]] to double // CHECK-NEXT: [[MATRIX:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 @@ -64,7 +64,7 @@ void add_compound_matrix_scalar_double_float(dx5x5_t a, float vf) { } void subtract_compound_matrix_scalar_double_float(dx5x5_t a, float vf) { - // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_double_float(<25 x double> noundef %a, float noundef %vf) + // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_double_float(<25 x double> %a, float %vf) // CHECK: [[SCALAR:%.*]] = load float, float* %vf.addr, align 4 // CHECK-NEXT: [[SCALAR_EXT:%.*]] = fpext float [[SCALAR]] to double // CHECK-NEXT: [[MATRIX:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 diff --git a/clang/test/CodeGen/matrix-type-operators.c b/clang/test/CodeGen/matrix-type-operators.c index 95ab5b8aee0225e365fe6d16136d0de7c44101e7..34ce57c0702a2f092d8c8860b88925e5a94d0efa 100644 --- a/clang/test/CodeGen/matrix-type-operators.c +++ b/clang/test/CodeGen/matrix-type-operators.c @@ -9,7 +9,7 @@ typedef unsigned long long ullx4x2_t __attribute__((matrix_type(4, 2))); // Floating point matrix/scalar additions. void add_matrix_matrix_double(dx5x5_t a, dx5x5_t b, dx5x5_t c) { - // CHECK-LABEL: define{{.*}} void @add_matrix_matrix_double(<25 x double> noundef %a, <25 x double> noundef %b, <25 x double> noundef %c) + // CHECK-LABEL: define{{.*}} void @add_matrix_matrix_double(<25 x double> %a, <25 x double> %b, <25 x double> %c) // CHECK: [[B:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[C:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[RES:%.*]] = fadd <25 x double> [[B]], [[C]] @@ -19,7 +19,7 @@ void add_matrix_matrix_double(dx5x5_t a, dx5x5_t b, dx5x5_t c) { } void add_compound_assign_matrix_double(dx5x5_t a, dx5x5_t b) { - // CHECK-LABEL: define{{.*}} void @add_compound_assign_matrix_double(<25 x double> noundef %a, <25 x double> noundef %b) + // CHECK-LABEL: define{{.*}} void @add_compound_assign_matrix_double(<25 x double> %a, <25 x double> %b) // CHECK: [[B:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[A:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[RES:%.*]] = fadd <25 x double> [[A]], [[B]] @@ -29,7 +29,7 @@ void add_compound_assign_matrix_double(dx5x5_t a, dx5x5_t b) { } void subtract_compound_assign_matrix_double(dx5x5_t a, dx5x5_t b) { - // CHECK-LABEL: define{{.*}} void @subtract_compound_assign_matrix_double(<25 x double> noundef %a, <25 x double> noundef %b) + // CHECK-LABEL: define{{.*}} void @subtract_compound_assign_matrix_double(<25 x double> %a, <25 x double> %b) // CHECK: [[B:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[A:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[RES:%.*]] = fsub <25 x double> [[A]], [[B]] @@ -39,7 +39,7 @@ void subtract_compound_assign_matrix_double(dx5x5_t a, dx5x5_t b) { } void add_matrix_matrix_float(fx2x3_t a, fx2x3_t b, fx2x3_t c) { - // CHECK-LABEL: define{{.*}} void @add_matrix_matrix_float(<6 x float> noundef %a, <6 x float> noundef %b, <6 x float> noundef %c) + // CHECK-LABEL: define{{.*}} void @add_matrix_matrix_float(<6 x float> %a, <6 x float> %b, <6 x float> %c) // CHECK: [[B:%.*]] = load <6 x float>, <6 x float>* {{.*}}, align 4 // CHECK-NEXT: [[C:%.*]] = load <6 x float>, <6 x float>* {{.*}}, align 4 // CHECK-NEXT: [[RES:%.*]] = fadd <6 x float> [[B]], [[C]] @@ -49,7 +49,7 @@ void add_matrix_matrix_float(fx2x3_t a, fx2x3_t b, fx2x3_t c) { } void add_compound_assign_matrix_float(fx2x3_t a, fx2x3_t b) { - // CHECK-LABEL: define{{.*}} void @add_compound_assign_matrix_float(<6 x float> noundef %a, <6 x float> noundef %b) + // CHECK-LABEL: define{{.*}} void @add_compound_assign_matrix_float(<6 x float> %a, <6 x float> %b) // CHECK: [[B:%.*]] = load <6 x float>, <6 x float>* {{.*}}, align 4 // CHECK-NEXT: [[A:%.*]] = load <6 x float>, <6 x float>* {{.*}}, align 4 // CHECK-NEXT: [[RES:%.*]] = fadd <6 x float> [[A]], [[B]] @@ -59,7 +59,7 @@ void add_compound_assign_matrix_float(fx2x3_t a, fx2x3_t b) { } void subtract_compound_assign_matrix_float(fx2x3_t a, fx2x3_t b) { - // CHECK-LABEL: define{{.*}} void @subtract_compound_assign_matrix_float(<6 x float> noundef %a, <6 x float> noundef %b) + // CHECK-LABEL: define{{.*}} void @subtract_compound_assign_matrix_float(<6 x float> %a, <6 x float> %b) // CHECK: [[B:%.*]] = load <6 x float>, <6 x float>* {{.*}}, align 4 // CHECK-NEXT: [[A:%.*]] = load <6 x float>, <6 x float>* {{.*}}, align 4 // CHECK-NEXT: [[RES:%.*]] = fsub <6 x float> [[A]], [[B]] @@ -69,7 +69,7 @@ void subtract_compound_assign_matrix_float(fx2x3_t a, fx2x3_t b) { } void add_matrix_scalar_double_float(dx5x5_t a, float vf) { - // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_double_float(<25 x double> noundef %a, float noundef %vf) + // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_double_float(<25 x double> %a, float %vf) // CHECK: [[MATRIX:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[SCALAR:%.*]] = load float, float* %vf.addr, align 4 // CHECK-NEXT: [[SCALAR_EXT:%.*]] = fpext float [[SCALAR]] to double @@ -82,7 +82,7 @@ void add_matrix_scalar_double_float(dx5x5_t a, float vf) { } void add_compound_matrix_scalar_double_float(dx5x5_t a, float vf) { - // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_double_float(<25 x double> noundef %a, float noundef %vf) + // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_double_float(<25 x double> %a, float %vf) // CHECK: [[SCALAR:%.*]] = load float, float* %vf.addr, align 4 // CHECK-NEXT: [[SCALAR_EXT:%.*]] = fpext float [[SCALAR]] to double // CHECK-NEXT: [[MATRIX:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 @@ -95,7 +95,7 @@ void add_compound_matrix_scalar_double_float(dx5x5_t a, float vf) { } void subtract_compound_matrix_scalar_double_float(dx5x5_t a, float vf) { - // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_double_float(<25 x double> noundef %a, float noundef %vf) + // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_double_float(<25 x double> %a, float %vf) // CHECK: [[SCALAR:%.*]] = load float, float* %vf.addr, align 4 // CHECK-NEXT: [[SCALAR_EXT:%.*]] = fpext float [[SCALAR]] to double // CHECK-NEXT: [[MATRIX:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 @@ -108,7 +108,7 @@ void subtract_compound_matrix_scalar_double_float(dx5x5_t a, float vf) { } void add_matrix_scalar_double_double(dx5x5_t a, double vd) { - // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_double_double(<25 x double> noundef %a, double noundef %vd) + // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_double_double(<25 x double> %a, double %vd) // CHECK: [[MATRIX:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[SCALAR:%.*]] = load double, double* %vd.addr, align 8 // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <25 x double> poison, double [[SCALAR]], i32 0 @@ -120,7 +120,7 @@ void add_matrix_scalar_double_double(dx5x5_t a, double vd) { } void add_compound_matrix_scalar_double_double(dx5x5_t a, double vd) { - // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_double_double(<25 x double> noundef %a, double noundef %vd) + // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_double_double(<25 x double> %a, double %vd) // CHECK: [[SCALAR:%.*]] = load double, double* %vd.addr, align 8 // CHECK-NEXT: [[MATRIX:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <25 x double> poison, double [[SCALAR]], i32 0 @@ -131,7 +131,7 @@ void add_compound_matrix_scalar_double_double(dx5x5_t a, double vd) { } void subtract_compound_matrix_scalar_double_double(dx5x5_t a, double vd) { - // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_double_double(<25 x double> noundef %a, double noundef %vd) + // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_double_double(<25 x double> %a, double %vd) // CHECK: [[SCALAR:%.*]] = load double, double* %vd.addr, align 8 // CHECK-NEXT: [[MATRIX:%.*]] = load <25 x double>, <25 x double>* {{.*}}, align 8 // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <25 x double> poison, double [[SCALAR]], i32 0 @@ -142,7 +142,7 @@ void subtract_compound_matrix_scalar_double_double(dx5x5_t a, double vd) { } void add_matrix_scalar_float_float(fx2x3_t b, float vf) { - // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_float_float(<6 x float> noundef %b, float noundef %vf) + // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_float_float(<6 x float> %b, float %vf) // CHECK: [[MATRIX:%.*]] = load <6 x float>, <6 x float>* {{.*}}, align 4 // CHECK-NEXT: [[SCALAR:%.*]] = load float, float* %vf.addr, align 4 // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <6 x float> poison, float [[SCALAR]], i32 0 @@ -154,7 +154,7 @@ void add_matrix_scalar_float_float(fx2x3_t b, float vf) { } void add_compound_matrix_scalar_float_float(fx2x3_t b, float vf) { - // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_float_float(<6 x float> noundef %b, float noundef %vf) + // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_float_float(<6 x float> %b, float %vf) // CHECK: [[SCALAR:%.*]] = load float, float* %vf.addr, align 4 // CHECK-NEXT: [[MATRIX:%.*]] = load <6 x float>, <6 x float>* %0, align 4 // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <6 x float> poison, float [[SCALAR]], i32 0 @@ -165,7 +165,7 @@ void add_compound_matrix_scalar_float_float(fx2x3_t b, float vf) { } void subtract_compound_matrix_scalar_float_float(fx2x3_t b, float vf) { - // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_float_float(<6 x float> noundef %b, float noundef %vf) + // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_float_float(<6 x float> %b, float %vf) // CHECK: [[SCALAR:%.*]] = load float, float* %vf.addr, align 4 // CHECK-NEXT: [[MATRIX:%.*]] = load <6 x float>, <6 x float>* %0, align 4 // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <6 x float> poison, float [[SCALAR]], i32 0 @@ -176,7 +176,7 @@ void subtract_compound_matrix_scalar_float_float(fx2x3_t b, float vf) { } void add_matrix_scalar_float_double(fx2x3_t b, double vd) { - // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_float_double(<6 x float> noundef %b, double noundef %vd) + // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_float_double(<6 x float> %b, double %vd) // CHECK: [[MATRIX:%.*]] = load <6 x float>, <6 x float>* {{.*}}, align 4 // CHECK-NEXT: [[SCALAR:%.*]] = load double, double* %vd.addr, align 8 // CHECK-NEXT: [[SCALAR_TRUNC:%.*]] = fptrunc double [[SCALAR]] to float @@ -189,7 +189,7 @@ void add_matrix_scalar_float_double(fx2x3_t b, double vd) { } void add_compound_matrix_scalar_float_double(fx2x3_t b, double vd) { - // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_float_double(<6 x float> noundef %b, double noundef %vd) + // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_float_double(<6 x float> %b, double %vd) // CHECK: [[SCALAR:%.*]] = load double, double* %vd.addr, align 8 // CHECK-NEXT: [[SCALAR_TRUNC:%.*]] = fptrunc double [[SCALAR]] to float // CHECK-NEXT: [[MATRIX:%.*]] = load <6 x float>, <6 x float>* {{.*}}, align 4 @@ -201,7 +201,7 @@ void add_compound_matrix_scalar_float_double(fx2x3_t b, double vd) { } void subtract_compound_matrix_scalar_float_double(fx2x3_t b, double vd) { - // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_float_double(<6 x float> noundef %b, double noundef %vd) + // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_float_double(<6 x float> %b, double %vd) // CHECK: [[SCALAR:%.*]] = load double, double* %vd.addr, align 8 // CHECK-NEXT: [[SCALAR_TRUNC:%.*]] = fptrunc double [[SCALAR]] to float // CHECK-NEXT: [[MATRIX:%.*]] = load <6 x float>, <6 x float>* {{.*}}, align 4 @@ -215,7 +215,7 @@ void subtract_compound_matrix_scalar_float_double(fx2x3_t b, double vd) { // Integer matrix/scalar additions void add_matrix_matrix_int(ix9x3_t a, ix9x3_t b, ix9x3_t c) { - // CHECK-LABEL: define{{.*}} void @add_matrix_matrix_int(<27 x i32> noundef %a, <27 x i32> noundef %b, <27 x i32> noundef %c) + // CHECK-LABEL: define{{.*}} void @add_matrix_matrix_int(<27 x i32> %a, <27 x i32> %b, <27 x i32> %c) // CHECK: [[B:%.*]] = load <27 x i32>, <27 x i32>* {{.*}}, align 4 // CHECK-NEXT: [[C:%.*]] = load <27 x i32>, <27 x i32>* {{.*}}, align 4 // CHECK-NEXT: [[RES:%.*]] = add <27 x i32> [[B]], [[C]] @@ -224,7 +224,7 @@ void add_matrix_matrix_int(ix9x3_t a, ix9x3_t b, ix9x3_t c) { } void add_compound_matrix_matrix_int(ix9x3_t a, ix9x3_t b) { - // CHECK-LABEL: define{{.*}} void @add_compound_matrix_matrix_int(<27 x i32> noundef %a, <27 x i32> noundef %b) + // CHECK-LABEL: define{{.*}} void @add_compound_matrix_matrix_int(<27 x i32> %a, <27 x i32> %b) // CHECK: [[B:%.*]] = load <27 x i32>, <27 x i32>* {{.*}}, align 4 // CHECK: [[A:%.*]] = load <27 x i32>, <27 x i32>* {{.*}}, align 4 // CHECK: [[RES:%.*]] = add <27 x i32> [[A]], [[B]] @@ -233,7 +233,7 @@ void add_compound_matrix_matrix_int(ix9x3_t a, ix9x3_t b) { } void subtract_compound_matrix_matrix_int(ix9x3_t a, ix9x3_t b) { - // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_matrix_int(<27 x i32> noundef %a, <27 x i32> noundef %b) + // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_matrix_int(<27 x i32> %a, <27 x i32> %b) // CHECK: [[B:%.*]] = load <27 x i32>, <27 x i32>* {{.*}}, align 4 // CHECK: [[A:%.*]] = load <27 x i32>, <27 x i32>* {{.*}}, align 4 // CHECK: [[RES:%.*]] = sub <27 x i32> [[A]], [[B]] @@ -242,7 +242,7 @@ void subtract_compound_matrix_matrix_int(ix9x3_t a, ix9x3_t b) { } void add_matrix_matrix_unsigned_long_long(ullx4x2_t a, ullx4x2_t b, ullx4x2_t c) { - // CHECK-LABEL: define{{.*}} void @add_matrix_matrix_unsigned_long_long(<8 x i64> noundef %a, <8 x i64> noundef %b, <8 x i64> noundef %c) + // CHECK-LABEL: define{{.*}} void @add_matrix_matrix_unsigned_long_long(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c) // CHECK: [[B:%.*]] = load <8 x i64>, <8 x i64>* {{.*}}, align 8 // CHECK-NEXT: [[C:%.*]] = load <8 x i64>, <8 x i64>* {{.*}}, align 8 // CHECK-NEXT: [[RES:%.*]] = add <8 x i64> [[B]], [[C]] @@ -252,7 +252,7 @@ void add_matrix_matrix_unsigned_long_long(ullx4x2_t a, ullx4x2_t b, ullx4x2_t c) } void add_compound_matrix_matrix_unsigned_long_long(ullx4x2_t a, ullx4x2_t b) { - // CHECK-LABEL: define{{.*}} void @add_compound_matrix_matrix_unsigned_long_long(<8 x i64> noundef %a, <8 x i64> noundef %b) + // CHECK-LABEL: define{{.*}} void @add_compound_matrix_matrix_unsigned_long_long(<8 x i64> %a, <8 x i64> %b) // CHECK: [[B:%.*]] = load <8 x i64>, <8 x i64>* {{.*}}, align 8 // CHECK-NEXT: [[A:%.*]] = load <8 x i64>, <8 x i64>* {{.*}}, align 8 // CHECK-NEXT: [[RES:%.*]] = add <8 x i64> [[A]], [[B]] @@ -262,7 +262,7 @@ void add_compound_matrix_matrix_unsigned_long_long(ullx4x2_t a, ullx4x2_t b) { } void subtract_compound_matrix_matrix_unsigned_long_long(ullx4x2_t a, ullx4x2_t b) { - // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_matrix_unsigned_long_long(<8 x i64> noundef %a, <8 x i64> noundef %b) + // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_matrix_unsigned_long_long(<8 x i64> %a, <8 x i64> %b) // CHECK: [[B:%.*]] = load <8 x i64>, <8 x i64>* {{.*}}, align 8 // CHECK-NEXT: [[A:%.*]] = load <8 x i64>, <8 x i64>* {{.*}}, align 8 // CHECK-NEXT: [[RES:%.*]] = sub <8 x i64> [[A]], [[B]] @@ -272,7 +272,7 @@ void subtract_compound_matrix_matrix_unsigned_long_long(ullx4x2_t a, ullx4x2_t b } void add_matrix_scalar_int_short(ix9x3_t a, short vs) { - // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_int_short(<27 x i32> noundef %a, i16 noundef signext %vs) + // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_int_short(<27 x i32> %a, i16 signext %vs) // CHECK: [[MATRIX:%.*]] = load <27 x i32>, <27 x i32>* [[MAT_ADDR:%.*]], align 4 // CHECK-NEXT: [[SCALAR:%.*]] = load i16, i16* %vs.addr, align 2 // CHECK-NEXT: [[SCALAR_EXT:%.*]] = sext i16 [[SCALAR]] to i32 @@ -285,7 +285,7 @@ void add_matrix_scalar_int_short(ix9x3_t a, short vs) { } void add_compound_matrix_scalar_int_short(ix9x3_t a, short vs) { - // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_int_short(<27 x i32> noundef %a, i16 noundef signext %vs) + // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_int_short(<27 x i32> %a, i16 signext %vs) // CHECK: [[SCALAR:%.*]] = load i16, i16* %vs.addr, align 2 // CHECK-NEXT: [[SCALAR_EXT:%.*]] = sext i16 [[SCALAR]] to i32 // CHECK-NEXT: [[MATRIX:%.*]] = load <27 x i32>, <27 x i32>* %0, align 4 @@ -298,7 +298,7 @@ void add_compound_matrix_scalar_int_short(ix9x3_t a, short vs) { } void subtract_compound_matrix_scalar_int_short(ix9x3_t a, short vs) { - // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_int_short(<27 x i32> noundef %a, i16 noundef signext %vs) + // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_int_short(<27 x i32> %a, i16 signext %vs) // CHECK: [[SCALAR:%.*]] = load i16, i16* %vs.addr, align 2 // CHECK-NEXT: [[SCALAR_EXT:%.*]] = sext i16 [[SCALAR]] to i32 // CHECK-NEXT: [[MATRIX:%.*]] = load <27 x i32>, <27 x i32>* %0, align 4 @@ -311,7 +311,7 @@ void subtract_compound_matrix_scalar_int_short(ix9x3_t a, short vs) { } void add_matrix_scalar_int_long_int(ix9x3_t a, long int vli) { - // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_int_long_int(<27 x i32> noundef %a, i64 noundef %vli) + // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_int_long_int(<27 x i32> %a, i64 %vli) // CHECK: [[MATRIX:%.*]] = load <27 x i32>, <27 x i32>* [[MAT_ADDR:%.*]], align 4 // CHECK-NEXT: [[SCALAR:%.*]] = load i64, i64* %vli.addr, align 8 // CHECK-NEXT: [[SCALAR_TRUNC:%.*]] = trunc i64 [[SCALAR]] to i32 @@ -324,7 +324,7 @@ void add_matrix_scalar_int_long_int(ix9x3_t a, long int vli) { } void add_compound_matrix_scalar_int_long_int(ix9x3_t a, long int vli) { - // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_int_long_int(<27 x i32> noundef %a, i64 noundef %vli) + // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_int_long_int(<27 x i32> %a, i64 %vli) // CHECK: [[SCALAR:%.*]] = load i64, i64* %vli.addr, align 8 // CHECK-NEXT: [[SCALAR_TRUNC:%.*]] = trunc i64 %1 to i32 // CHECK-NEXT: [[MATRIX:%.*]] = load <27 x i32>, <27 x i32>* %0, align 4 @@ -337,7 +337,7 @@ void add_compound_matrix_scalar_int_long_int(ix9x3_t a, long int vli) { } void subtract_compound_matrix_scalar_int_long_int(ix9x3_t a, long int vli) { - // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_int_long_int(<27 x i32> noundef %a, i64 noundef %vli) + // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_int_long_int(<27 x i32> %a, i64 %vli) // CHECK: [[SCALAR:%.*]] = load i64, i64* %vli.addr, align 8 // CHECK-NEXT: [[SCALAR_TRUNC:%.*]] = trunc i64 %1 to i32 // CHECK-NEXT: [[MATRIX:%.*]] = load <27 x i32>, <27 x i32>* %0, align 4 @@ -350,7 +350,7 @@ void subtract_compound_matrix_scalar_int_long_int(ix9x3_t a, long int vli) { } void add_matrix_scalar_int_unsigned_long_long(ix9x3_t a, unsigned long long int vulli) { - // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_int_unsigned_long_long(<27 x i32> noundef %a, i64 noundef %vulli) + // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_int_unsigned_long_long(<27 x i32> %a, i64 %vulli) // CHECK: [[MATRIX:%.*]] = load <27 x i32>, <27 x i32>* [[MAT_ADDR:%.*]], align 4 // CHECK-NEXT: [[SCALAR:%.*]] = load i64, i64* %vulli.addr, align 8 // CHECK-NEXT: [[SCALAR_TRUNC:%.*]] = trunc i64 [[SCALAR]] to i32 @@ -363,7 +363,7 @@ void add_matrix_scalar_int_unsigned_long_long(ix9x3_t a, unsigned long long int } void add_compound_matrix_scalar_int_unsigned_long_long(ix9x3_t a, unsigned long long int vulli) { - // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_int_unsigned_long_long(<27 x i32> noundef %a, i64 noundef %vulli) + // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_int_unsigned_long_long(<27 x i32> %a, i64 %vulli) // CHECK: [[SCALAR:%.*]] = load i64, i64* %vulli.addr, align 8 // CHECK-NEXT: [[SCALAR_TRUNC:%.*]] = trunc i64 [[SCALAR]] to i32 // CHECK-NEXT: [[MATRIX:%.*]] = load <27 x i32>, <27 x i32>* [[MATRIX_ADDR:%.*]], align 4 @@ -376,7 +376,7 @@ void add_compound_matrix_scalar_int_unsigned_long_long(ix9x3_t a, unsigned long } void subtract_compound_matrix_scalar_int_unsigned_long_long(ix9x3_t a, unsigned long long int vulli) { - // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_int_unsigned_long_long(<27 x i32> noundef %a, i64 noundef %vulli) + // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_int_unsigned_long_long(<27 x i32> %a, i64 %vulli) // CHECK: [[SCALAR:%.*]] = load i64, i64* %vulli.addr, align 8 // CHECK-NEXT: [[SCALAR_TRUNC:%.*]] = trunc i64 [[SCALAR]] to i32 // CHECK-NEXT: [[MATRIX:%.*]] = load <27 x i32>, <27 x i32>* [[MATRIX_ADDR:%.*]], align 4 @@ -389,7 +389,7 @@ void subtract_compound_matrix_scalar_int_unsigned_long_long(ix9x3_t a, unsigned } void add_matrix_scalar_long_long_int_short(ullx4x2_t b, short vs) { - // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_long_long_int_short(<8 x i64> noundef %b, i16 noundef signext %vs) + // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_long_long_int_short(<8 x i64> %b, i16 signext %vs) // CHECK: [[SCALAR:%.*]] = load i16, i16* %vs.addr, align 2 // CHECK-NEXT: [[SCALAR_EXT:%.*]] = sext i16 [[SCALAR]] to i64 // CHECK-NEXT: [[MATRIX:%.*]] = load <8 x i64>, <8 x i64>* {{.*}}, align 8 @@ -402,7 +402,7 @@ void add_matrix_scalar_long_long_int_short(ullx4x2_t b, short vs) { } void add_compound_matrix_scalar_long_long_int_short(ullx4x2_t b, short vs) { - // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_long_long_int_short(<8 x i64> noundef %b, i16 noundef signext %vs) + // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_long_long_int_short(<8 x i64> %b, i16 signext %vs) // CHECK: [[SCALAR:%.*]] = load i16, i16* %vs.addr, align 2 // CHECK-NEXT: [[SCALAR_EXT:%.*]] = sext i16 [[SCALAR]] to i64 // CHECK-NEXT: [[MATRIX:%.*]] = load <8 x i64>, <8 x i64>* %0, align 8 @@ -415,7 +415,7 @@ void add_compound_matrix_scalar_long_long_int_short(ullx4x2_t b, short vs) { } void subtract_compound_matrix_scalar_long_long_int_short(ullx4x2_t b, short vs) { - // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_long_long_int_short(<8 x i64> noundef %b, i16 noundef signext %vs) + // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_long_long_int_short(<8 x i64> %b, i16 signext %vs) // CHECK: [[SCALAR:%.*]] = load i16, i16* %vs.addr, align 2 // CHECK-NEXT: [[SCALAR_EXT:%.*]] = sext i16 [[SCALAR]] to i64 // CHECK-NEXT: [[MATRIX:%.*]] = load <8 x i64>, <8 x i64>* %0, align 8 @@ -428,7 +428,7 @@ void subtract_compound_matrix_scalar_long_long_int_short(ullx4x2_t b, short vs) } void add_matrix_scalar_long_long_int_int(ullx4x2_t b, long int vli) { - // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_long_long_int_int(<8 x i64> noundef %b, i64 noundef %vli) + // CHECK-LABEL: define{{.*}} void @add_matrix_scalar_long_long_int_int(<8 x i64> %b, i64 %vli) // CHECK: [[SCALAR:%.*]] = load i64, i64* %vli.addr, align 8 // CHECK-NEXT: [[MATRIX:%.*]] = load <8 x i64>, <8 x i64>* {{.*}}, align 8 // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <8 x i64> poison, i64 [[SCALAR]], i32 0 @@ -440,7 +440,7 @@ void add_matrix_scalar_long_long_int_int(ullx4x2_t b, long int vli) { } void add_compound_matrix_scalar_long_long_int_int(ullx4x2_t b, long int vli) { - // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_long_long_int_int(<8 x i64> noundef %b, i64 noundef %vli) + // CHECK-LABEL: define{{.*}} void @add_compound_matrix_scalar_long_long_int_int(<8 x i64> %b, i64 %vli) // CHECK: [[SCALAR:%.*]] = load i64, i64* %vli.addr, align 8 // CHECK-NEXT: [[MATRIX:%.*]] = load <8 x i64>, <8 x i64>* {{.*}}, align 8 // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <8 x i64> poison, i64 [[SCALAR]], i32 0 @@ -452,7 +452,7 @@ void add_compound_matrix_scalar_long_long_int_int(ullx4x2_t b, long int vli) { } void subtract_compound_matrix_scalar_long_long_int_int(ullx4x2_t b, long int vli) { - // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_long_long_int_int(<8 x i64> noundef %b, i64 noundef %vli) + // CHECK-LABEL: define{{.*}} void @subtract_compound_matrix_scalar_long_long_int_int(<8 x i64> %b, i64 %vli) // CHECK: [[SCALAR:%.*]] = load i64, i64* %vli.addr, align 8 // CHECK-NEXT: [[MATRIX:%.*]] = load <8 x i64>, <8 x i64>* {{.*}}, align 8 // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <8 x i64> poison, i64 [[SCALAR]], i32 0 @@ -1058,7 +1058,7 @@ void insert_extract(dx5x5_t a, fx3x3_t b, unsigned long j, short k) { } void insert_compound_stmt(dx5x5_t a) { - // CHECK-LABEL: define{{.*}} void @insert_compound_stmt(<25 x double> noundef %a) + // CHECK-LABEL: define{{.*}} void @insert_compound_stmt(<25 x double> %a) // CHECK: [[A:%.*]] = load <25 x double>, <25 x double>* [[A_PTR:%.*]], align 8 // CHECK-NEXT: [[EXT:%.*]] = extractelement <25 x double> [[A]], i64 17 // CHECK-NEXT: [[SUB:%.*]] = fsub double [[EXT]], 1.000000e+00 @@ -1075,7 +1075,7 @@ struct Foo { }; void insert_compound_stmt_field(struct Foo *a, float f, unsigned i, unsigned j) { - // CHECK-LABEL: define{{.*}} void @insert_compound_stmt_field(%struct.Foo* noundef %a, float noundef %f, i32 noundef %i, i32 noundef %j) + // CHECK-LABEL: define{{.*}} void @insert_compound_stmt_field(%struct.Foo* %a, float %f, i32 %i, i32 %j) // CHECK: [[I:%.*]] = load i32, i32* %i.addr, align 4 // CHECK-NEXT: [[I_EXT:%.*]] = zext i32 [[I]] to i64 // CHECK-NEXT: [[J:%.*]] = load i32, i32* %j.addr, align 4 @@ -1099,7 +1099,7 @@ void insert_compound_stmt_field(struct Foo *a, float f, unsigned i, unsigned j) } void matrix_as_idx(ix9x3_t a, int i, int j, dx5x5_t b) { - // CHECK-LABEL: define{{.*}} void @matrix_as_idx(<27 x i32> noundef %a, i32 noundef %i, i32 noundef %j, <25 x double> noundef %b) + // CHECK-LABEL: define{{.*}} void @matrix_as_idx(<27 x i32> %a, i32 %i, i32 %j, <25 x double> %b) // CHECK: [[I1:%.*]] = load i32, i32* %i.addr, align 4 // CHECK-NEXT: [[I1_EXT:%.*]] = sext i32 [[I1]] to i64 // CHECK-NEXT: [[J1:%.*]] = load i32, i32* %j.addr, align 4 diff --git a/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c b/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c index 25ae279ebc6dabdfe162463d19d0521261a87617..7b90f03d45f2fab97d2aecd1c1138b81d5692b3f 100644 --- a/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c +++ b/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c @@ -28,7 +28,7 @@ int memcmp(const void *p, const void *q, unsigned long size) { // CHECK-NEXT: [[TMP1:%.*]] = load i8*, i8** [[P_ADDR_I]], align 8 // CHECK-NEXT: [[TMP2:%.*]] = load i8*, i8** [[Q_ADDR_I]], align 8 // CHECK-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIZE_ADDR_I]], align 8 -// CHECK-NEXT: [[CALL_I:%.*]] = call i32 @memcmp(i8* noundef [[TMP1]], i8* noundef [[TMP2]], i64 noundef [[TMP3]]) #[[ATTR3:[0-9]+]] +// CHECK-NEXT: [[CALL_I:%.*]] = call i32 @memcmp(i8* [[TMP1]], i8* [[TMP2]], i64 [[TMP3]]) #[[ATTR3:[0-9]+]] // CHECK-NEXT: ret i32 [[CALL_I]] // int con_unify_unimap_q1(void) { diff --git a/clang/test/CodeGen/memcpy-inline-builtin.c b/clang/test/CodeGen/memcpy-inline-builtin.c index 86e70207903eddeeb44f0fc8de0a197ff8ecb390..e63e77c8ba45571c0c2a01d0373ca6c2e4e2858e 100644 --- a/clang/test/CodeGen/memcpy-inline-builtin.c +++ b/clang/test/CodeGen/memcpy-inline-builtin.c @@ -61,7 +61,7 @@ void *foo(void *a, const void *b, size_t c) { // CHECK-NEXT: [[TMP3:%.*]] = load i8*, i8** [[A_ADDR]], align 8 // CHECK-NEXT: [[TMP4:%.*]] = load i8*, i8** [[B_ADDR]], align 8 // CHECK-NEXT: [[TMP5:%.*]] = load i64, i64* [[C_ADDR]], align 8 -// CHECK-NEXT: [[CALL:%.*]] = call i8* [[TMP2]](i8* noundef [[TMP3]], i8* noundef [[TMP4]], i64 noundef [[TMP5]]) +// CHECK-NEXT: [[CALL:%.*]] = call i8* [[TMP2]](i8* [[TMP3]], i8* [[TMP4]], i64 [[TMP5]]) // CHECK-NEXT: ret void // void bar(void *a, const void *b, size_t c) { diff --git a/clang/test/CodeGen/microsoft-call-conv-x64.c b/clang/test/CodeGen/microsoft-call-conv-x64.c index 6724d35f27c40a9f735bb45f9731b4ecd04c5e6c..5be748f94c5a8f82c95a0965f137eb35b1dcdc8c 100644 --- a/clang/test/CodeGen/microsoft-call-conv-x64.c +++ b/clang/test/CodeGen/microsoft-call-conv-x64.c @@ -35,5 +35,5 @@ int main(void) { void __stdcall f7(foo) int foo; {} void f8(void) { f7(0); - // CHECK: call void @f7(i32 noundef 0) + // CHECK: call void @f7(i32 0) } diff --git a/clang/test/CodeGen/microsoft-call-conv.c b/clang/test/CodeGen/microsoft-call-conv.c index a94cbdb1a58d29184407b4a1bbd90f5e1f0c14c4..ff60a106ce47f7eea826b3ff501b6f14e2da2c86 100644 --- a/clang/test/CodeGen/microsoft-call-conv.c +++ b/clang/test/CodeGen/microsoft-call-conv.c @@ -56,7 +56,7 @@ int main(void) { void __stdcall f7(foo) int foo; {} void f8(void) { f7(0); - // CHECK: call x86_stdcallcc void @f7(i32 noundef 0) + // CHECK: call x86_stdcallcc void @f7(i32 0) } // PR12535 diff --git a/clang/test/CodeGen/mingw-long-double.c b/clang/test/CodeGen/mingw-long-double.c index 46c3f9a775b9d09a94c1e125d4d28825131b401b..39ce4689848566624efa05c0c856712727b6c0f6 100644 --- a/clang/test/CodeGen/mingw-long-double.c +++ b/clang/test/CodeGen/mingw-long-double.c @@ -31,16 +31,16 @@ long double _Complex dataLDC = {1.0L, 1.0L}; long double TestLD(long double x) { return x * x; } -// GNU32: define dso_local x86_fp80 @TestLD(x86_fp80 noundef %x) -// GNU64: define dso_local void @TestLD(x86_fp80* noalias sret(x86_fp80) align 16 %agg.result, x86_fp80* noundef %0) -// MSC64: define dso_local double @TestLD(double noundef %x) +// GNU32: define dso_local x86_fp80 @TestLD(x86_fp80 %x) +// GNU64: define dso_local void @TestLD(x86_fp80* noalias sret(x86_fp80) align 16 %agg.result, x86_fp80* %0) +// MSC64: define dso_local double @TestLD(double %x) long double _Complex TestLDC(long double _Complex x) { return x * x; } -// GNU32: define dso_local void @TestLDC({ x86_fp80, x86_fp80 }* noalias sret({ x86_fp80, x86_fp80 }) align 4 %agg.result, { x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 4 %x) -// GNU64: define dso_local void @TestLDC({ x86_fp80, x86_fp80 }* noalias sret({ x86_fp80, x86_fp80 }) align 16 %agg.result, { x86_fp80, x86_fp80 }* noundef %x) -// MSC64: define dso_local void @TestLDC({ double, double }* noalias sret({ double, double }) align 8 %agg.result, { double, double }* noundef %x) +// GNU32: define dso_local void @TestLDC({ x86_fp80, x86_fp80 }* noalias sret({ x86_fp80, x86_fp80 }) align 4 %agg.result, { x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 4 %x) +// GNU64: define dso_local void @TestLDC({ x86_fp80, x86_fp80 }* noalias sret({ x86_fp80, x86_fp80 }) align 16 %agg.result, { x86_fp80, x86_fp80 }* %x) +// MSC64: define dso_local void @TestLDC({ double, double }* noalias sret({ double, double }) align 8 %agg.result, { double, double }* %x) // GNU32: declare dso_local void @__mulxc3 // GNU64: declare dso_local void @__mulxc3 diff --git a/clang/test/CodeGen/mips-unsigned-ext-var.c b/clang/test/CodeGen/mips-unsigned-ext-var.c index 09e5a8f3b36ef3f8c39b862e03ed5a01cebb5dca..a4dae53c184ba64b04878e23ed34a236c645a3b9 100644 --- a/clang/test/CodeGen/mips-unsigned-ext-var.c +++ b/clang/test/CodeGen/mips-unsigned-ext-var.c @@ -17,6 +17,6 @@ void foo1() { foo(1,f); } -//N64: call signext i32 (i32, ...) @foo(i32 signext undef, i32 noundef signext -32) -//N32: call signext i32 (i32, ...) @foo(i32 signext undef, i32 noundef signext -32) -//O32: call i32 (i32, ...) @foo(i32 signext undef, i32 noundef signext -32) +//N64: call signext i32 (i32, ...) @foo(i32 signext undef, i32 signext -32) +//N32: call signext i32 (i32, ...) @foo(i32 signext undef, i32 signext -32) +//O32: call i32 (i32, ...) @foo(i32 signext undef, i32 signext -32) diff --git a/clang/test/CodeGen/mips-unsigned-extend.c b/clang/test/CodeGen/mips-unsigned-extend.c index 51f0f95140fccb56e9747382fc1a7ee2fc6c0541..039d3800667e6e6c394c002f78a1ebcbe48785da 100644 --- a/clang/test/CodeGen/mips-unsigned-extend.c +++ b/clang/test/CodeGen/mips-unsigned-extend.c @@ -10,6 +10,6 @@ void foo1() { foo(f); } -// N64: call void @foo(i32 noundef signext %{{[0-9]+}}) -// N32: call void @foo(i32 noundef signext %{{[0-9]+}}) -// O32: call void @foo(i32 noundef signext %{{[0-9]+}}) +// N64: call void @foo(i32 signext %{{[0-9]+}}) +// N32: call void @foo(i32 signext %{{[0-9]+}}) +// O32: call void @foo(i32 signext %{{[0-9]+}}) diff --git a/clang/test/CodeGen/mips-vector-arg.c b/clang/test/CodeGen/mips-vector-arg.c index 511fca8e0e55fa5cfac1c27f4eaac07b584c0349..5ba4884f3aa6e5c34fdb69ee4f9ae1ccd7d95b4c 100644 --- a/clang/test/CodeGen/mips-vector-arg.c +++ b/clang/test/CodeGen/mips-vector-arg.c @@ -8,19 +8,19 @@ typedef float v4sf __attribute__ ((__vector_size__ (16))); typedef int v4i32 __attribute__ ((__vector_size__ (16))); -// O32: define{{.*}} void @test_v4sf(i32 inreg noundef %a1.coerce0, i32 inreg noundef %a1.coerce1, i32 inreg noundef %a1.coerce2, i32 inreg noundef %a1.coerce3, i32 noundef signext %a2, i32 %0, i32 inreg noundef %a3.coerce0, i32 inreg noundef %a3.coerce1, i32 inreg noundef %a3.coerce2, i32 inreg noundef %a3.coerce3) local_unnamed_addr [[NUW:#[0-9]+]] -// O32: declare i32 @test_v4sf_2(i32 inreg noundef, i32 inreg noundef, i32 inreg noundef, i32 inreg noundef, i32 noundef signext, i32, i32 inreg noundef, i32 inreg noundef, i32 inreg noundef, i32 inreg noundef) -// N64: define{{.*}} void @test_v4sf(i64 inreg noundef %a1.coerce0, i64 inreg noundef %a1.coerce1, i32 noundef signext %a2, i64 %0, i64 inreg noundef %a3.coerce0, i64 inreg noundef %a3.coerce1) local_unnamed_addr [[NUW:#[0-9]+]] -// N64: declare signext i32 @test_v4sf_2(i64 inreg noundef, i64 inreg noundef, i32 noundef signext, i64, i64 inreg noundef, i64 inreg noundef) +// O32: define{{.*}} void @test_v4sf(i32 inreg %a1.coerce0, i32 inreg %a1.coerce1, i32 inreg %a1.coerce2, i32 inreg %a1.coerce3, i32 signext %a2, i32 %0, i32 inreg %a3.coerce0, i32 inreg %a3.coerce1, i32 inreg %a3.coerce2, i32 inreg %a3.coerce3) local_unnamed_addr [[NUW:#[0-9]+]] +// O32: declare i32 @test_v4sf_2(i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 signext, i32, i32 inreg, i32 inreg, i32 inreg, i32 inreg) +// N64: define{{.*}} void @test_v4sf(i64 inreg %a1.coerce0, i64 inreg %a1.coerce1, i32 signext %a2, i64 %0, i64 inreg %a3.coerce0, i64 inreg %a3.coerce1) local_unnamed_addr [[NUW:#[0-9]+]] +// N64: declare signext i32 @test_v4sf_2(i64 inreg, i64 inreg, i32 signext, i64, i64 inreg, i64 inreg) extern test_v4sf_2(v4sf, int, v4sf); void test_v4sf(v4sf a1, int a2, v4sf a3) { test_v4sf_2(a3, a2, a1); } -// O32: define{{.*}} void @test_v4i32(i32 inreg noundef %a1.coerce0, i32 inreg noundef %a1.coerce1, i32 inreg noundef %a1.coerce2, i32 inreg noundef %a1.coerce3, i32 noundef signext %a2, i32 %0, i32 inreg noundef %a3.coerce0, i32 inreg noundef %a3.coerce1, i32 inreg noundef %a3.coerce2, i32 inreg noundef %a3.coerce3) local_unnamed_addr [[NUW]] -// O32: declare i32 @test_v4i32_2(i32 inreg noundef, i32 inreg noundef, i32 inreg noundef, i32 inreg noundef, i32 noundef signext, i32, i32 inreg noundef, i32 inreg noundef, i32 inreg noundef, i32 inreg noundef) -// N64: define{{.*}} void @test_v4i32(i64 inreg noundef %a1.coerce0, i64 inreg noundef %a1.coerce1, i32 noundef signext %a2, i64 %0, i64 inreg noundef %a3.coerce0, i64 inreg noundef %a3.coerce1) local_unnamed_addr [[NUW]] -// N64: declare signext i32 @test_v4i32_2(i64 inreg noundef, i64 inreg noundef, i32 noundef signext, i64, i64 inreg noundef, i64 inreg noundef) +// O32: define{{.*}} void @test_v4i32(i32 inreg %a1.coerce0, i32 inreg %a1.coerce1, i32 inreg %a1.coerce2, i32 inreg %a1.coerce3, i32 signext %a2, i32 %0, i32 inreg %a3.coerce0, i32 inreg %a3.coerce1, i32 inreg %a3.coerce2, i32 inreg %a3.coerce3) local_unnamed_addr [[NUW]] +// O32: declare i32 @test_v4i32_2(i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 signext, i32, i32 inreg, i32 inreg, i32 inreg, i32 inreg) +// N64: define{{.*}} void @test_v4i32(i64 inreg %a1.coerce0, i64 inreg %a1.coerce1, i32 signext %a2, i64 %0, i64 inreg %a3.coerce0, i64 inreg %a3.coerce1) local_unnamed_addr [[NUW]] +// N64: declare signext i32 @test_v4i32_2(i64 inreg, i64 inreg, i32 signext, i64, i64 inreg, i64 inreg) extern test_v4i32_2(v4i32, int, v4i32); void test_v4i32(v4i32 a1, int a2, v4i32 a3) { test_v4i32_2(a3, a2, a1); diff --git a/clang/test/CodeGen/mips-zero-sized-struct.c b/clang/test/CodeGen/mips-zero-sized-struct.c index 97cf1cfc13cdaa7c368c3cde99e6c94bd52c1ad2..7b626226a6683fd27167ebf62d369a4efa87c44c 100644 --- a/clang/test/CodeGen/mips-zero-sized-struct.c +++ b/clang/test/CodeGen/mips-zero-sized-struct.c @@ -19,9 +19,9 @@ // RUN: %clang_cc1 -triple mipsisa64r6-unknown-linux-gnuabi64 -S -emit-llvm -o - %s | FileCheck -check-prefix=N64 %s // RUN: %clang_cc1 -triple mipsisa64r6el-unknown-linux-gnuabi64 -S -emit-llvm -o - %s | FileCheck -check-prefix=N64 %s -// O32: define{{.*}} void @fn28(%struct.T2* noalias sret(%struct.T2) align 1 %agg.result, i8 noundef signext %arg0) -// N32: define{{.*}} void @fn28(i8 noundef signext %arg0) -// N64: define{{.*}} void @fn28(i8 noundef signext %arg0) +// O32: define{{.*}} void @fn28(%struct.T2* noalias sret(%struct.T2) align 1 %agg.result, i8 signext %arg0) +// N32: define{{.*}} void @fn28(i8 signext %arg0) +// N64: define{{.*}} void @fn28(i8 signext %arg0) typedef struct T2 { } T2; T2 T2_retval; diff --git a/clang/test/CodeGen/mips64-padding-arg.c b/clang/test/CodeGen/mips64-padding-arg.c index 7f12d4024b1048632187d919d2b2ed3efb07e5f1..844660cc18d07a68ddb5dc45da0684db33f7b2b7 100644 --- a/clang/test/CodeGen/mips64-padding-arg.c +++ b/clang/test/CodeGen/mips64-padding-arg.c @@ -9,9 +9,9 @@ typedef struct { // Insert padding to ensure arguments of type S0 are aligned to 16-byte boundaries. -// N64-LABEL: define{{.*}} void @foo1(i32 noundef signext %a0, i64 %0, double inreg %a1.coerce0, i64 inreg %a1.coerce1, i64 inreg %a1.coerce2, i64 inreg %a1.coerce3, double inreg %a2.coerce0, i64 inreg %a2.coerce1, i64 inreg %a2.coerce2, i64 inreg %a2.coerce3, i32 noundef signext %b, i64 %1, double inreg %a3.coerce0, i64 inreg %a3.coerce1, i64 inreg %a3.coerce2, i64 inreg %a3.coerce3) -// N64: tail call void @foo2(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext %a0, i64 undef, double inreg %a1.coerce0, i64 inreg %a1.coerce1, i64 inreg %a1.coerce2, i64 inreg %a1.coerce3, double inreg %a2.coerce0, i64 inreg %a2.coerce1, i64 inreg %a2.coerce2, i64 inreg %a2.coerce3, i32 noundef signext 3, i64 undef, double inreg %a3.coerce0, i64 inreg %a3.coerce1, i64 inreg %a3.coerce2, i64 inreg %a3.coerce3) -// N64: declare void @foo2(i32 noundef signext, i32 noundef signext, i32 noundef signext, i64, double inreg, i64 inreg, i64 inreg, i64 inreg, double inreg, i64 inreg, i64 inreg, i64 inreg, i32 noundef signext, i64, double inreg, i64 inreg, i64 inreg, i64 inreg) +// N64-LABEL: define{{.*}} void @foo1(i32 signext %a0, i64 %0, double inreg %a1.coerce0, i64 inreg %a1.coerce1, i64 inreg %a1.coerce2, i64 inreg %a1.coerce3, double inreg %a2.coerce0, i64 inreg %a2.coerce1, i64 inreg %a2.coerce2, i64 inreg %a2.coerce3, i32 signext %b, i64 %1, double inreg %a3.coerce0, i64 inreg %a3.coerce1, i64 inreg %a3.coerce2, i64 inreg %a3.coerce3) +// N64: tail call void @foo2(i32 signext 1, i32 signext 2, i32 signext %a0, i64 undef, double inreg %a1.coerce0, i64 inreg %a1.coerce1, i64 inreg %a1.coerce2, i64 inreg %a1.coerce3, double inreg %a2.coerce0, i64 inreg %a2.coerce1, i64 inreg %a2.coerce2, i64 inreg %a2.coerce3, i32 signext 3, i64 undef, double inreg %a3.coerce0, i64 inreg %a3.coerce1, i64 inreg %a3.coerce2, i64 inreg %a3.coerce3) +// N64: declare void @foo2(i32 signext, i32 signext, i32 signext, i64, double inreg, i64 inreg, i64 inreg, i64 inreg, double inreg, i64 inreg, i64 inreg, i64 inreg, i32 signext, i64, double inreg, i64 inreg, i64 inreg, i64 inreg) extern void foo2(int, int, int, S0, S0, int, S0); @@ -21,9 +21,9 @@ void foo1(int a0, S0 a1, S0 a2, int b, S0 a3) { // Insert padding before long double argument. // -// N64-LABEL: define{{.*}} void @foo3(i32 noundef signext %a0, i64 %0, fp128 noundef %a1) -// N64: tail call void @foo4(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext %a0, i64 undef, fp128 noundef %a1) -// N64: declare void @foo4(i32 noundef signext, i32 noundef signext, i32 noundef signext, i64, fp128 noundef) +// N64-LABEL: define{{.*}} void @foo3(i32 signext %a0, i64 %0, fp128 %a1) +// N64: tail call void @foo4(i32 signext 1, i32 signext 2, i32 signext %a0, i64 undef, fp128 %a1) +// N64: declare void @foo4(i32 signext, i32 signext, i32 signext, i64, fp128) extern void foo4(int, int, int, long double); @@ -33,9 +33,9 @@ void foo3(int a0, long double a1) { // Insert padding after hidden argument. // -// N64-LABEL: define{{.*}} void @foo5(%struct.S0* noalias sret(%struct.S0) align 16 %agg.result, i64 %0, fp128 noundef %a0) -// N64: call void @foo6(%struct.S0* sret(%struct.S0) align 16 %agg.result, i32 noundef signext 1, i32 noundef signext 2, i64 undef, fp128 noundef %a0) -// N64: declare void @foo6(%struct.S0* sret(%struct.S0) align 16, i32 noundef signext, i32 noundef signext, i64, fp128 noundef) +// N64-LABEL: define{{.*}} void @foo5(%struct.S0* noalias sret(%struct.S0) align 16 %agg.result, i64 %0, fp128 %a0) +// N64: call void @foo6(%struct.S0* sret(%struct.S0) align 16 %agg.result, i32 signext 1, i32 signext 2, i64 undef, fp128 %a0) +// N64: declare void @foo6(%struct.S0* sret(%struct.S0) align 16, i32 signext, i32 signext, i64, fp128) extern S0 foo6(int, int, long double); @@ -45,8 +45,8 @@ S0 foo5(long double a0) { // Do not insert padding if ABI is O32. // -// O32-LABEL: define{{.*}} void @foo7(float noundef %a0, double noundef %a1) -// O32: declare void @foo8(float noundef, double noundef) +// O32-LABEL: define{{.*}} void @foo7(float %a0, double %a1) +// O32: declare void @foo8(float, double) extern void foo8(float, double); @@ -55,7 +55,7 @@ void foo7(float a0, double a1) { } // O32-LABEL: define{{.*}} void @foo9() -// O32: declare void @foo10(i32 noundef signext, i32 +// O32: declare void @foo10(i32 signext, i32 typedef struct __attribute__((aligned(16))) { int a; diff --git a/clang/test/CodeGen/mrtd.c b/clang/test/CodeGen/mrtd.c index 3baed2b9f3e7a794b576e0d03ba9153b26a8ec77..88af0c0a9500312ed9ccec1619f6e005a5778506 100644 --- a/clang/test/CodeGen/mrtd.c +++ b/clang/test/CodeGen/mrtd.c @@ -4,7 +4,7 @@ void baz(int arg); -// CHECK: define{{.*}} x86_stdcallcc void @foo(i32 noundef %arg) [[NUW:#[0-9]+]] +// CHECK: define{{.*}} x86_stdcallcc void @foo(i32 %arg) [[NUW:#[0-9]+]] void foo(int arg) { // CHECK: call x86_stdcallcc i32 bitcast (i32 (...)* @bar to i32 (i32)*)( bar(arg); @@ -14,10 +14,10 @@ void foo(int arg) { // CHECK: declare x86_stdcallcc i32 @bar(...) -// CHECK: declare x86_stdcallcc void @baz(i32 noundef) +// CHECK: declare x86_stdcallcc void @baz(i32) void qux(int arg, ...) { } -// CHECK: define{{.*}} void @qux(i32 noundef %arg, ...) +// CHECK: define{{.*}} void @qux(i32 %arg, ...) void quux(int a1, int a2, int a3) { qux(a1, a2, a3); diff --git a/clang/test/CodeGen/ms-inline-asm.c b/clang/test/CodeGen/ms-inline-asm.c index e19ac1b4503871fa66f6fe5b4404fdc7f4bdff37..ef0345b2a867cd9b00ab777b7276434e449a2c85 100644 --- a/clang/test/CodeGen/ms-inline-asm.c +++ b/clang/test/CodeGen/ms-inline-asm.c @@ -581,7 +581,7 @@ void t40(float a) { } void t41(unsigned short a) { -// CHECK-LABEL: define{{.*}} void @t41(i16 noundef zeroext %a) +// CHECK-LABEL: define{{.*}} void @t41(i16 zeroext %a) __asm mov cs, a; // CHECK: mov cs, $0 __asm mov ds, a; diff --git a/clang/test/CodeGen/ms-intrinsics-cpuid.c b/clang/test/CodeGen/ms-intrinsics-cpuid.c index 5448a6925714c4c10f6c149ad277f00e8b70c567..e8be5ad23d7e0bc75a9a8c8b206b08bcccf685c3 100644 --- a/clang/test/CodeGen/ms-intrinsics-cpuid.c +++ b/clang/test/CodeGen/ms-intrinsics-cpuid.c @@ -12,12 +12,12 @@ typedef __SIZE_TYPE__ size_t; void test__cpuid(int *info, int level) { __cpuid(info, level); } -// X86-LABEL: define {{.*}} @test__cpuid(i32* noundef %{{.*}}, i32 noundef %{{.*}}) +// X86-LABEL: define {{.*}} @test__cpuid(i32* %{{.*}}, i32 %{{.*}}) // X86: call { i32, i32, i32, i32 } asm "cpuid", // X86-SAME: "={ax},={bx},={cx},={dx},0,2,~{dirflag},~{fpsr},~{flags}" // X86-SAME: (i32 %{{.*}}, i32 0) -// X64-LABEL: define {{.*}} @test__cpuid(i32* noundef %{{.*}}, i32 noundef %{{.*}}) +// X64-LABEL: define {{.*}} @test__cpuid(i32* %{{.*}}, i32 %{{.*}}) // X64: call { i32, i32, i32, i32 } asm "xchgq %rbx{{.*}}cpuid{{.*}}xchgq %rbx{{.*}}", // X64-SAME: "={ax},=r,={cx},={dx},0,2,~{dirflag},~{fpsr},~{flags}" // X64-SAME: (i32 %{{.*}}, i32 0) diff --git a/clang/test/CodeGen/ms-intrinsics-other.c b/clang/test/CodeGen/ms-intrinsics-other.c index 5ff4105bc62764a537b0236436025e5d01e0f63b..a1f337b8c0facc0536a77b77efbf292395687c1f 100644 --- a/clang/test/CodeGen/ms-intrinsics-other.c +++ b/clang/test/CodeGen/ms-intrinsics-other.c @@ -211,7 +211,7 @@ LONG test_InterlockedAdd(LONG volatile *Addend, LONG Value) { return _InterlockedAdd(Addend, Value); } -// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedAdd(i32*{{[a-z_ ]*}}%Addend, i32 noundef %Value) {{.*}} { +// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedAdd(i32*{{[a-z_ ]*}}%Addend, i32 %Value) {{.*}} { // CHECK-ARM-ARM64: %[[OLDVAL:[0-9]+]] = atomicrmw add i32* %Addend, i32 %Value seq_cst, align 4 // CHECK-ARM-ARM64: %[[NEWVAL:[0-9]+]] = add i32 %[[OLDVAL:[0-9]+]], %Value // CHECK-ARM-ARM64: ret i32 %[[NEWVAL:[0-9]+]] diff --git a/clang/test/CodeGen/ms-mixed-ptr-sizes.c b/clang/test/CodeGen/ms-mixed-ptr-sizes.c index 7823d3b014c2f6ac0d82c063d108703f369174fc..ececa42a4c4dd8f4331805f322b49611ee1e30b5 100644 --- a/clang/test/CodeGen/ms-mixed-ptr-sizes.c +++ b/clang/test/CodeGen/ms-mixed-ptr-sizes.c @@ -7,32 +7,32 @@ struct Foo { }; void use_foo(struct Foo *f); void test_sign_ext(struct Foo *f, int * __ptr32 __sptr i) { -// X64-LABEL: define dso_local void @test_sign_ext({{.*}}i32 addrspace(270)* noundef %i) -// X86-LABEL: define dso_local void @test_sign_ext(%struct.Foo* noundef %f, i32* noundef %i) +// X64-LABEL: define dso_local void @test_sign_ext({{.*}}i32 addrspace(270)* %i) +// X86-LABEL: define dso_local void @test_sign_ext(%struct.Foo* %f, i32* %i) // X64: %{{.+}} = addrspacecast i32 addrspace(270)* %i to i32* // X86: %{{.+}} = addrspacecast i32* %i to i32 addrspace(272)* f->p64 = i; use_foo(f); } void test_zero_ext(struct Foo *f, int * __ptr32 __uptr i) { -// X64-LABEL: define dso_local void @test_zero_ext({{.*}}i32 addrspace(271)* noundef %i) -// X86-LABEL: define dso_local void @test_zero_ext({{.*}}i32 addrspace(271)* noundef %i) +// X64-LABEL: define dso_local void @test_zero_ext({{.*}}i32 addrspace(271)* %i) +// X86-LABEL: define dso_local void @test_zero_ext({{.*}}i32 addrspace(271)* %i) // X64: %{{.+}} = addrspacecast i32 addrspace(271)* %i to i32* // X86: %{{.+}} = addrspacecast i32 addrspace(271)* %i to i32 addrspace(272)* f->p64 = i; use_foo(f); } void test_trunc(struct Foo *f, int * __ptr64 i) { -// X64-LABEL: define dso_local void @test_trunc(%struct.Foo* noundef %f, i32* noundef %i) -// X86-LABEL: define dso_local void @test_trunc({{.*}}i32 addrspace(272)* noundef %i) +// X64-LABEL: define dso_local void @test_trunc(%struct.Foo* %f, i32* %i) +// X86-LABEL: define dso_local void @test_trunc({{.*}}i32 addrspace(272)* %i) // X64: %{{.+}} = addrspacecast i32* %i to i32 addrspace(270)* // X86: %{{.+}} = addrspacecast i32 addrspace(272)* %i to i32* f->p32 = i; use_foo(f); } void test_noop(struct Foo *f, int * __ptr32 i) { -// X64-LABEL: define dso_local void @test_noop({{.*}}i32 addrspace(270)* noundef %i) -// X86-LABEL: define dso_local void @test_noop({{.*}}i32* noundef %i) +// X64-LABEL: define dso_local void @test_noop({{.*}}i32 addrspace(270)* %i) +// X86-LABEL: define dso_local void @test_noop({{.*}}i32* %i) // X64-NOT: addrspacecast // X86-NOT: addrspacecast f->p32 = i; @@ -40,8 +40,8 @@ void test_noop(struct Foo *f, int * __ptr32 i) { } void test_other(struct Foo *f, __attribute__((address_space(10))) int *i) { -// X64-LABEL: define dso_local void @test_other({{.*}}i32 addrspace(10)* noundef %i) -// X86-LABEL: define dso_local void @test_other({{.*}}i32 addrspace(10)* noundef %i) +// X64-LABEL: define dso_local void @test_other({{.*}}i32 addrspace(10)* %i) +// X86-LABEL: define dso_local void @test_other({{.*}}i32 addrspace(10)* %i) // X64: %{{.+}} = addrspacecast i32 addrspace(10)* %i to i32 addrspace(270)* // X86: %{{.+}} = addrspacecast i32 addrspace(10)* %i to i32* f->p32 = (int * __ptr32)i; diff --git a/clang/test/CodeGen/ms_abi.c b/clang/test/CodeGen/ms_abi.c index a134e841c565d020cda2b932d117547f36a30ead..33165385b3f04237ad96a26550c706079e77c279 100644 --- a/clang/test/CodeGen/ms_abi.c +++ b/clang/test/CodeGen/ms_abi.c @@ -156,7 +156,7 @@ struct i128 { }; __attribute__((ms_abi)) struct i128 f7(struct i128 a) { - // WIN64: define dso_local void @f7(%struct.i128* noalias sret(%struct.i128) align 8 %agg.result, %struct.i128* noundef %a) - // FREEBSD: define{{.*}} win64cc void @f7(%struct.i128* noalias sret(%struct.i128) align 8 %agg.result, %struct.i128* noundef %a) + // WIN64: define dso_local void @f7(%struct.i128* noalias sret(%struct.i128) align 8 %agg.result, %struct.i128* %a) + // FREEBSD: define{{.*}} win64cc void @f7(%struct.i128* noalias sret(%struct.i128) align 8 %agg.result, %struct.i128* %a) return a; } diff --git a/clang/test/CodeGen/ms_abi_aarch64.c b/clang/test/CodeGen/ms_abi_aarch64.c index 24208a0fbe0488f94ccdce85df60f90534d50d16..cf244420296d9d46332250341f632972f9f0334a 100644 --- a/clang/test/CodeGen/ms_abi_aarch64.c +++ b/clang/test/CodeGen/ms_abi_aarch64.c @@ -101,8 +101,8 @@ void call_msabi_hfa(void) { void call_msabi_hfa_vararg(void) { // COMMON-LABEL: define{{.*}} void @call_msabi_hfa_vararg() - // WIN64: call void ([2 x i64], i32, ...) @msabi_hfa_vararg([2 x i64] {{.*}}, i32 noundef 4, [2 x i64] {{.*}}) - // LINUX: call win64cc void ([2 x i64], i32, ...) @msabi_hfa_vararg([2 x i64] {{.*}}, i32 noundef 4, [2 x i64] {{.*}}) + // WIN64: call void ([2 x i64], i32, ...) @msabi_hfa_vararg([2 x i64] {{.*}}, i32 4, [2 x i64] {{.*}}) + // LINUX: call win64cc void ([2 x i64], i32, ...) @msabi_hfa_vararg([2 x i64] {{.*}}, i32 4, [2 x i64] {{.*}}) msabi_hfa_vararg((struct HFA){1.0f, 2.0f, 3.0f}, 4, (struct HFA){5.0f, 6.0f, 7.0f}); } diff --git a/clang/test/CodeGen/named_reg_global.c b/clang/test/CodeGen/named_reg_global.c index 719e61a97a9db2e467d092b10413c7bfad74e8b9..232b74de1cab2c928201316aadfb082e8952934b 100644 --- a/clang/test/CodeGen/named_reg_global.c +++ b/clang/test/CodeGen/named_reg_global.c @@ -30,7 +30,7 @@ unsigned long get_stack_pointer_addr() { } // CHECK: declare{{.*}} i[[bits]] @llvm.read_register.i[[bits]](metadata) -// CHECK: define{{.*}} void @set_stack_pointer_addr(i[[bits]] noundef %addr) #0 { +// CHECK: define{{.*}} void @set_stack_pointer_addr(i[[bits]] %addr) #0 { // CHECK: [[sto:%[0-9]+]] = load i[[bits]], i[[bits]]* % // CHECK: call void @llvm.write_register.i[[bits]](metadata !0, i[[bits]] [[sto]]) // CHECK: ret void diff --git a/clang/test/CodeGen/no-bitfield-type-align.c b/clang/test/CodeGen/no-bitfield-type-align.c index 5e4a61879c666abe708ac0ad6b3169645b39a40b..99e9d4aaae0dcf6cff39d05e884e3479221be0f1 100644 --- a/clang/test/CodeGen/no-bitfield-type-align.c +++ b/clang/test/CodeGen/no-bitfield-type-align.c @@ -9,7 +9,7 @@ struct S { unsigned short f2:15; }; -// CHECK: define{{.*}} void @test_zero_width_bitfield(%[[STRUCT_S]]* noundef %[[A:.*]]) +// CHECK: define{{.*}} void @test_zero_width_bitfield(%[[STRUCT_S]]* %[[A:.*]]) // CHECK: %[[BF_LOAD:.*]] = load i32, i32* %[[V1:.*]], align 1 // CHECK: %[[BF_CLEAR:.*]] = and i32 %[[BF_LOAD]], 32767 // CHECK: %[[BF_CAST:.*]] = trunc i32 %[[BF_CLEAR]] to i16 diff --git a/clang/test/CodeGen/no-builtin.cpp b/clang/test/CodeGen/no-builtin.cpp index 85624e074c00ae91cf384f5865f0b8d5eac71080..fed4c41e22a03c5e1edd60835dc9c949c2554397 100644 --- a/clang/test/CodeGen/no-builtin.cpp +++ b/clang/test/CodeGen/no-builtin.cpp @@ -29,15 +29,15 @@ struct B : public A { virtual ~B(); }; -// CHECK-LABEL: define{{.*}} void @call_a_foo(%struct.A* noundef %a) #3 +// CHECK-LABEL: define{{.*}} void @call_a_foo(%struct.A* %a) #3 extern "C" void call_a_foo(A *a) { - // CHECK: %call = call noundef i32 %2(%struct.A* {{[^,]*}} %0) + // CHECK: %call = call i32 %2(%struct.A* {{[^,]*}} %0) a->foo(); // virtual call is not annotated } -// CHECK-LABEL: define{{.*}} void @call_b_foo(%struct.B* noundef %b) #3 +// CHECK-LABEL: define{{.*}} void @call_b_foo(%struct.B* %b) #3 extern "C" void call_b_foo(B *b) { - // CHECK: %call = call noundef i32 %2(%struct.B* {{[^,]*}} %0) + // CHECK: %call = call i32 %2(%struct.B* {{[^,]*}} %0) b->foo(); // virtual call is not annotated } @@ -50,8 +50,8 @@ extern "C" void call_foo_no_mempcy() { A::~A() {} // Anchoring A so A::foo() gets generated B::~B() {} // Anchoring B so B::foo() gets generated -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZNK1A3fooEv(%struct.A* noundef{{[^,]*}} %this) unnamed_addr #0 comdat align 2 -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZNK1B3fooEv(%struct.B* noundef{{[^,]*}} %this) unnamed_addr #6 comdat align 2 +// CHECK-LABEL: define linkonce_odr i32 @_ZNK1A3fooEv(%struct.A* {{[^,]*}} %this) unnamed_addr #0 comdat align 2 +// CHECK-LABEL: define linkonce_odr i32 @_ZNK1B3fooEv(%struct.B* {{[^,]*}} %this) unnamed_addr #6 comdat align 2 // CHECK: attributes #0 = {{{.*}}"no-builtin-memcpy"{{.*}}} // CHECK-NOT: attributes #0 = {{{.*}}"no-builtin-memmove"{{.*}}} diff --git a/clang/test/CodeGen/no-prototype.c b/clang/test/CodeGen/no-prototype.c index f95fc7532e90561eea1021e53bc9cbdcd4b8b057..6030357b70f79cdd8a1e06c68bc14ed8dfd46bb3 100644 --- a/clang/test/CodeGen/no-prototype.c +++ b/clang/test/CodeGen/no-prototype.c @@ -11,7 +11,7 @@ int baz() { return foo(); } -// CHECK: define i32 @bar(i32 noundef %a) [[BAR_ATTR:#[0-9]+]] { +// CHECK: define i32 @bar(i32 %a) [[BAR_ATTR:#[0-9]+]] { // CHECK: declare i32 @foo(...) [[FOO_ATTR:#[0-9]+]] // CHECK: define i32 @baz() [[BAZ_ATTR:#[0-9]+]] { diff --git a/clang/test/CodeGen/noduplicate-cxx11-test.cpp b/clang/test/CodeGen/noduplicate-cxx11-test.cpp index c2a81d4b89ad827f9fc20756fd1c96fdcd30f4a5..0033192b4053bf653312a2bb9b27cfbae331275a 100644 --- a/clang/test/CodeGen/noduplicate-cxx11-test.cpp +++ b/clang/test/CodeGen/noduplicate-cxx11-test.cpp @@ -3,7 +3,7 @@ // This was a problem in Sema, but only shows up as noinline missing // in CodeGen. -// CHECK: define{{.*}} i32 @_Z15noduplicatedfuni(i32 noundef %a) [[NI:#[0-9]+]] +// CHECK: define{{.*}} i32 @_Z15noduplicatedfuni(i32 %a) [[NI:#[0-9]+]] int noduplicatedfun [[clang::noduplicate]] (int a) { diff --git a/clang/test/CodeGen/non-power-of-2-alignment-assumptions.c b/clang/test/CodeGen/non-power-of-2-alignment-assumptions.c index a6e07d7c6dfac9d05be343272462a5afc89bc2bd..b8ce1699f7ed066a7f59af348b1b95cb0bf5ccb8 100644 --- a/clang/test/CodeGen/non-power-of-2-alignment-assumptions.c +++ b/clang/test/CodeGen/non-power-of-2-alignment-assumptions.c @@ -8,9 +8,9 @@ void *__attribute__((alloc_align(1))) alloc(int align); // CHECK-NEXT: [[ALIGN_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: store i32 [[ALIGN:%.*]], i32* [[ALIGN_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[ALIGN_ADDR]], align 4 -// CHECK-NEXT: [[CALL:%.*]] = call i8* @alloc(i32 noundef [[TMP0]]) -// CHECK-NEXT: [[CASTED_ALIGN:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* [[CALL]], i64 [[CASTED_ALIGN]]) ] +// CHECK-NEXT: [[CALL:%.*]] = call i8* @alloc(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* [[CALL]], i64 [[TMP1]]) ] // CHECK-NEXT: ret void // void t0(int align) { @@ -20,7 +20,7 @@ void t0(int align) { // CHECK-NEXT: entry: // CHECK-NEXT: [[ALIGN_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: store i32 [[ALIGN:%.*]], i32* [[ALIGN_ADDR]], align 4 -// CHECK-NEXT: [[CALL:%.*]] = call i8* @alloc(i32 noundef 7) +// CHECK-NEXT: [[CALL:%.*]] = call i8* @alloc(i32 7) // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* [[CALL]], i64 7) ] // CHECK-NEXT: ret void // @@ -31,7 +31,7 @@ void t1(int align) { // CHECK-NEXT: entry: // CHECK-NEXT: [[ALIGN_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: store i32 [[ALIGN:%.*]], i32* [[ALIGN_ADDR]], align 4 -// CHECK-NEXT: [[CALL:%.*]] = call align 8 i8* @alloc(i32 noundef 8) +// CHECK-NEXT: [[CALL:%.*]] = call align 8 i8* @alloc(i32 8) // CHECK-NEXT: ret void // void t2(int align) { diff --git a/clang/test/CodeGen/nonnull.c b/clang/test/CodeGen/nonnull.c index a36e29f8e2e921e1997d9a06003b95b109ffef4e..112304e3066c6ba9359f262e99c41eceeb83a755 100644 --- a/clang/test/CodeGen/nonnull.c +++ b/clang/test/CodeGen/nonnull.c @@ -1,20 +1,20 @@ // RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm < %s | FileCheck -check-prefix=NULL-INVALID %s // RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -fno-delete-null-pointer-checks < %s | FileCheck -check-prefix=NULL-VALID %s -// NULL-INVALID: define{{.*}} void @foo(i32* noundef nonnull %x) -// NULL-VALID: define{{.*}} void @foo(i32* noundef %x) +// NULL-INVALID: define{{.*}} void @foo(i32* nonnull %x) +// NULL-VALID: define{{.*}} void @foo(i32* %x) void foo(int * __attribute__((nonnull)) x) { *x = 0; } -// NULL-INVALID: define{{.*}} void @bar(i32* noundef nonnull %x) -// NULL-VALID: define{{.*}} void @bar(i32* noundef %x) +// NULL-INVALID: define{{.*}} void @bar(i32* nonnull %x) +// NULL-VALID: define{{.*}} void @bar(i32* %x) void bar(int * x) __attribute__((nonnull(1))) { *x = 0; } -// NULL-INVALID: define{{.*}} void @bar2(i32* noundef %x, i32* noundef nonnull %y) -// NULL-VALID: define{{.*}} void @bar2(i32* noundef %x, i32* noundef %y) +// NULL-INVALID: define{{.*}} void @bar2(i32* %x, i32* nonnull %y) +// NULL-VALID: define{{.*}} void @bar2(i32* %x, i32* %y) void bar2(int * x, int * y) __attribute__((nonnull(2))) { *x = 0; } @@ -26,14 +26,14 @@ int * bar3() __attribute__((returns_nonnull)) { return &a; } -// NULL-INVALID: define{{.*}} i32 @bar4(i32 noundef %n, i32* noundef nonnull %p) -// NULL-VALID: define{{.*}} i32 @bar4(i32 noundef %n, i32* noundef %p) +// NULL-INVALID: define{{.*}} i32 @bar4(i32 %n, i32* nonnull %p) +// NULL-VALID: define{{.*}} i32 @bar4(i32 %n, i32* %p) int bar4(int n, int *p) __attribute__((nonnull)) { return n + *p; } -// NULL-INVALID: define{{.*}} i32 @bar5(i32 noundef %n, i32* noundef nonnull %p) -// NULL-VALID: define{{.*}} i32 @bar5(i32 noundef %n, i32* noundef %p) +// NULL-INVALID: define{{.*}} i32 @bar5(i32 %n, i32* nonnull %p) +// NULL-VALID: define{{.*}} i32 @bar5(i32 %n, i32* %p) int bar5(int n, int *p) __attribute__((nonnull(1, 2))) { return n + *p; } @@ -50,12 +50,12 @@ int bar6(TransparentUnion tu) __attribute__((nonnull(1))) { return *tu.p; } -// NULL-INVALID: define{{.*}} void @bar7(i32* noundef nonnull %a, i32* noundef nonnull %b) -// NULL-VALID: define{{.*}} void @bar7(i32* noundef %a, i32* noundef %b) +// NULL-INVALID: define{{.*}} void @bar7(i32* nonnull %a, i32* nonnull %b) +// NULL-VALID: define{{.*}} void @bar7(i32* %a, i32* %b) void bar7(int *a, int *b) __attribute__((nonnull(1))) __attribute__((nonnull(2))) {} -// NULL-INVALID: define{{.*}} void @bar8(i32* noundef nonnull %a, i32* noundef nonnull %b) -// NULL-VALID: define{{.*}} void @bar8(i32* noundef %a, i32* noundef %b) +// NULL-INVALID: define{{.*}} void @bar8(i32* nonnull %a, i32* nonnull %b) +// NULL-VALID: define{{.*}} void @bar8(i32* %a, i32* %b) void bar8(int *a, int *b) __attribute__((nonnull)) __attribute__((nonnull(1))) {} diff --git a/clang/test/CodeGen/nrvo-tracking.cpp b/clang/test/CodeGen/nrvo-tracking.cpp index 1acb9bb73555ac8c5a874ffe8863f4e002afd221..be405878f6f9b6225ac761dfa3f49b77e4f79898 100644 --- a/clang/test/CodeGen/nrvo-tracking.cpp +++ b/clang/test/CodeGen/nrvo-tracking.cpp @@ -301,7 +301,7 @@ struct A { }; // CHECK-LABEL: define{{.*}} void @_ZN7PR518624testINS_1AEEET_v -// CHECK: call noundef i32 @_ZN7PR518621AcviEv +// CHECK: call i32 @_ZN7PR518621AcviEv // CHECK-NEXT: call void @_ZN7PR518621AC1Ei // CHECK-NEXT: call void @llvm.lifetime.end template A test(); diff --git a/clang/test/CodeGen/nvptx-abi.c b/clang/test/CodeGen/nvptx-abi.c index c8a74aea8b87fb39d5ca1db10933c199b9b5a616..23683424a22c7f706cf7adb47b7746da47778c97 100644 --- a/clang/test/CodeGen/nvptx-abi.c +++ b/clang/test/CodeGen/nvptx-abi.c @@ -21,14 +21,14 @@ float bar(void) { void foo(float4_t x) { // CHECK-LABEL: @foo -// CHECK: %struct.float4_s* noundef byval(%struct.float4_s) align 4 %x +// CHECK: %struct.float4_s* byval(%struct.float4_s) align 4 %x } void fooN(float4_t x, float4_t y, float4_t z) { // CHECK-LABEL: @fooN -// CHECK: %struct.float4_s* noundef byval(%struct.float4_s) align 4 %x -// CHECK: %struct.float4_s* noundef byval(%struct.float4_s) align 4 %y -// CHECK: %struct.float4_s* noundef byval(%struct.float4_s) align 4 %z +// CHECK: %struct.float4_s* byval(%struct.float4_s) align 4 %x +// CHECK: %struct.float4_s* byval(%struct.float4_s) align 4 %y +// CHECK: %struct.float4_s* byval(%struct.float4_s) align 4 %z } typedef struct nested_s { @@ -39,5 +39,5 @@ typedef struct nested_s { void baz(nested_t x) { // CHECK-LABEL: @baz -// CHECK: %struct.nested_s* noundef byval(%struct.nested_s) align 8 %x) +// CHECK: %struct.nested_s* byval(%struct.nested_s) align 8 %x) } diff --git a/clang/test/CodeGen/object-size.c b/clang/test/CodeGen/object-size.c index e82829d9a3af21bbed0c297139295d9be204d893..ff54b11a0f042ebd31c5dc19881d51230c27bb7e 100644 --- a/clang/test/CodeGen/object-size.c +++ b/clang/test/CodeGen/object-size.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-apple-darwin -emit-llvm %s -o - 2>&1 | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis -DDYNAMIC -triple x86_64-apple-darwin -emit-llvm %s -o - 2>&1 | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm %s -o - 2>&1 | FileCheck %s +// RUN: %clang_cc1 -DDYNAMIC -triple x86_64-apple-darwin -emit-llvm %s -o - 2>&1 | FileCheck %s #ifndef DYNAMIC #define OBJECT_SIZE_BUILTIN __builtin_object_size diff --git a/clang/test/CodeGen/padding-init.c b/clang/test/CodeGen/padding-init.c index 4cec08974a9f81abc1a121ebc03d8101d4c4e757..0ff11efd64506aab9ebed85a6b4c900e380ec467 100644 --- a/clang/test/CodeGen/padding-init.c +++ b/clang/test/CodeGen/padding-init.c @@ -24,7 +24,7 @@ void use(struct S*); // CHECK: %s = alloca // CHECK-NEXT: %[[B:[0-9+]]] = bitcast %struct.S* %s to i8* // CHECK-NEXT: call void @llvm.memset{{.*}}(i8* align 8 %[[B]], i8 0, -// CHECK-NEXT: call void @use(%struct.S* noundef %s) +// CHECK-NEXT: call void @use(%struct.S* %s) void empty_braces() { struct S s = {}; return use(&s); @@ -34,7 +34,7 @@ void empty_braces() { // CHECK: %s = alloca // CHECK-NEXT: %[[B:[0-9+]]] = bitcast %struct.S* %s to i8* // CHECK-NEXT: call void @llvm.memcpy{{.*}}(i8* align 8 %[[B]], {{.*}}@__const.partial_init.s -// CHECK-NEXT: call void @use(%struct.S* noundef %s) +// CHECK-NEXT: call void @use(%struct.S* %s) void partial_init() { struct S s = { .c = 42 }; return use(&s); @@ -44,7 +44,7 @@ void partial_init() { // CHECK: %s = alloca // CHECK-NEXT: %[[B:[0-9+]]] = bitcast %struct.S* %s to i8* // CHECK-NEXT: call void @llvm.memcpy{{.*}}(i8* align 8 %[[B]], {{.*}}@__const.init_all.s -// CHECK-NEXT: call void @use(%struct.S* noundef %s) +// CHECK-NEXT: call void @use(%struct.S* %s) void init_all() { struct S s = { .c = 42, .l = 0xdeadbeefc0fedead }; return use(&s); diff --git a/clang/test/CodeGen/pass-by-value-noalias.c b/clang/test/CodeGen/pass-by-value-noalias.c index 28866ba2d79dbbecbc6224d42f6a3bb8a42ac097..6176f9e9a80ccd281fda66ca5b5d070eada80935 100644 --- a/clang/test/CodeGen/pass-by-value-noalias.c +++ b/clang/test/CodeGen/pass-by-value-noalias.c @@ -11,6 +11,6 @@ struct Foo { int f; }; -// WITH_NOALIAS: define{{.*}} void @take(%struct.Foo* noalias noundef %arg) -// NO_NOALIAS: define{{.*}} void @take(%struct.Foo* noundef %arg) +// WITH_NOALIAS: define{{.*}} void @take(%struct.Foo* noalias %arg) +// NO_NOALIAS: define{{.*}} void @take(%struct.Foo* %arg) void take(struct Foo arg) {} diff --git a/clang/test/CodeGen/pass-object-size.c b/clang/test/CodeGen/pass-object-size.c index cdefeebdd587c8c814a7a86c743943c3d94f6697..bdace09316944af6a221f372138be18635cbc02d 100644 --- a/clang/test/CodeGen/pass-object-size.c +++ b/clang/test/CodeGen/pass-object-size.c @@ -11,49 +11,49 @@ struct Foo { int gi = 0; -// CHECK-LABEL: define{{.*}} i32 @ObjectSize0(i8* noundef %{{.*}}, i64 noundef %0) +// CHECK-LABEL: define{{.*}} i32 @ObjectSize0(i8* %{{.*}}, i64 %0) int ObjectSize0(void *const p PS(0)) { // CHECK-NOT: @llvm.objectsize return __builtin_object_size(p, 0); } -// CHECK-LABEL: define{{.*}} i32 @DynamicObjectSize0(i8* noundef %{{.*}}, i64 noundef %0) +// CHECK-LABEL: define{{.*}} i32 @DynamicObjectSize0(i8* %{{.*}}, i64 %0) int DynamicObjectSize0(void *const p PDS(0)) { // CHECK-NOT: @llvm.objectsize return __builtin_dynamic_object_size(p, 0); } -// CHECK-LABEL: define{{.*}} i32 @ObjectSize1(i8* noundef %{{.*}}, i64 noundef %0) +// CHECK-LABEL: define{{.*}} i32 @ObjectSize1(i8* %{{.*}}, i64 %0) int ObjectSize1(void *const p PS(1)) { // CHECK-NOT: @llvm.objectsize return __builtin_object_size(p, 1); } -// CHECK-LABEL: define{{.*}} i32 @DynamicObjectSize1(i8* noundef %{{.*}}, i64 noundef %0) +// CHECK-LABEL: define{{.*}} i32 @DynamicObjectSize1(i8* %{{.*}}, i64 %0) int DynamicObjectSize1(void *const p PDS(1)) { // CHECK-NOT: @llvm.objectsize return __builtin_dynamic_object_size(p, 1); } -// CHECK-LABEL: define{{.*}} i32 @ObjectSize2(i8* noundef %{{.*}}, i64 noundef %0) +// CHECK-LABEL: define{{.*}} i32 @ObjectSize2(i8* %{{.*}}, i64 %0) int ObjectSize2(void *const p PS(2)) { // CHECK-NOT: @llvm.objectsize return __builtin_object_size(p, 2); } -// CHECK-LABEL: define{{.*}} i32 @DynamicObjectSize2(i8* noundef %{{.*}}, i64 noundef %0) +// CHECK-LABEL: define{{.*}} i32 @DynamicObjectSize2(i8* %{{.*}}, i64 %0) int DynamicObjectSize2(void *const p PDS(2)) { // CHECK-NOT: @llvm.objectsize return __builtin_object_size(p, 2); } -// CHECK-LABEL: define{{.*}} i32 @ObjectSize3(i8* noundef %{{.*}}, i64 noundef %0) +// CHECK-LABEL: define{{.*}} i32 @ObjectSize3(i8* %{{.*}}, i64 %0) int ObjectSize3(void *const p PS(3)) { // CHECK-NOT: @llvm.objectsize return __builtin_object_size(p, 3); } -// CHECK-LABEL: define{{.*}} i32 @DynamicObjectSize3(i8* noundef %{{.*}}, i64 noundef %0) +// CHECK-LABEL: define{{.*}} i32 @DynamicObjectSize3(i8* %{{.*}}, i64 %0) int DynamicObjectSize3(void *const p PDS(3)) { // CHECK-NOT: @llvm.objectsize return __builtin_object_size(p, 3); @@ -65,46 +65,46 @@ void *malloc(unsigned long) __attribute__((alloc_size(1))); void test1(unsigned long sz) { struct Foo t[10]; - // CHECK: call i32 @ObjectSize0(i8* noundef %{{.*}}, i64 noundef 360) + // CHECK: call i32 @ObjectSize0(i8* %{{.*}}, i64 360) gi = ObjectSize0(&t[1]); - // CHECK: call i32 @ObjectSize1(i8* noundef %{{.*}}, i64 noundef 360) + // CHECK: call i32 @ObjectSize1(i8* %{{.*}}, i64 360) gi = ObjectSize1(&t[1]); - // CHECK: call i32 @ObjectSize2(i8* noundef %{{.*}}, i64 noundef 360) + // CHECK: call i32 @ObjectSize2(i8* %{{.*}}, i64 360) gi = ObjectSize2(&t[1]); - // CHECK: call i32 @ObjectSize3(i8* noundef %{{.*}}, i64 noundef 360) + // CHECK: call i32 @ObjectSize3(i8* %{{.*}}, i64 360) gi = ObjectSize3(&t[1]); - // CHECK: call i32 @ObjectSize0(i8* noundef %{{.*}}, i64 noundef 356) + // CHECK: call i32 @ObjectSize0(i8* %{{.*}}, i64 356) gi = ObjectSize0(&t[1].t[1]); - // CHECK: call i32 @ObjectSize1(i8* noundef %{{.*}}, i64 noundef 36) + // CHECK: call i32 @ObjectSize1(i8* %{{.*}}, i64 36) gi = ObjectSize1(&t[1].t[1]); - // CHECK: call i32 @ObjectSize2(i8* noundef %{{.*}}, i64 noundef 356) + // CHECK: call i32 @ObjectSize2(i8* %{{.*}}, i64 356) gi = ObjectSize2(&t[1].t[1]); - // CHECK: call i32 @ObjectSize3(i8* noundef %{{.*}}, i64 noundef 36) + // CHECK: call i32 @ObjectSize3(i8* %{{.*}}, i64 36) gi = ObjectSize3(&t[1].t[1]); char *ptr = (char *)malloc(sz); // CHECK: [[REG:%.*]] = call i64 @llvm.objectsize.i64.p0i8({{.*}}, i1 false, i1 true, i1 true) - // CHECK: call i32 @DynamicObjectSize0(i8* noundef %{{.*}}, i64 noundef [[REG]]) + // CHECK: call i32 @DynamicObjectSize0(i8* %{{.*}}, i64 [[REG]]) gi = DynamicObjectSize0(ptr); // CHECK: [[WITH_OFFSET:%.*]] = getelementptr // CHECK: [[REG:%.*]] = call i64 @llvm.objectsize.i64.p0i8(i8* [[WITH_OFFSET]], i1 false, i1 true, i1 true) - // CHECK: call i32 @DynamicObjectSize0(i8* noundef {{.*}}, i64 noundef [[REG]]) + // CHECK: call i32 @DynamicObjectSize0(i8* {{.*}}, i64 [[REG]]) gi = DynamicObjectSize0(ptr+10); // CHECK: [[REG:%.*]] = call i64 @llvm.objectsize.i64.p0i8({{.*}}, i1 true, i1 true, i1 true) - // CHECK: call i32 @DynamicObjectSize2(i8* noundef {{.*}}, i64 noundef [[REG]]) + // CHECK: call i32 @DynamicObjectSize2(i8* {{.*}}, i64 [[REG]]) gi = DynamicObjectSize2(ptr); } // CHECK-LABEL: define{{.*}} void @test2 void test2(struct Foo *t) { // CHECK: [[VAR:%[0-9]+]] = call i64 @llvm.objectsize - // CHECK: call i32 @ObjectSize1(i8* noundef %{{.*}}, i64 noundef [[VAR]]) + // CHECK: call i32 @ObjectSize1(i8* %{{.*}}, i64 [[VAR]]) gi = ObjectSize1(&t->t[1]); - // CHECK: call i32 @ObjectSize3(i8* noundef %{{.*}}, i64 noundef 36) + // CHECK: call i32 @ObjectSize3(i8* %{{.*}}, i64 36) gi = ObjectSize3(&t->t[1]); } @@ -191,47 +191,47 @@ int NoViableOverloadObjectSize3(void *const p PS(3)) void test3() { struct Foo t[10]; - // CHECK: call i32 @_Z27NoViableOverloadObjectSize0PvU17pass_object_size0(i8* noundef %{{.*}}, i64 noundef 360) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize0PvU17pass_object_size0(i8* %{{.*}}, i64 360) gi = NoViableOverloadObjectSize0(&t[1]); - // CHECK: call i32 @_Z27NoViableOverloadObjectSize1PvU17pass_object_size1(i8* noundef %{{.*}}, i64 noundef 360) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize1PvU17pass_object_size1(i8* %{{.*}}, i64 360) gi = NoViableOverloadObjectSize1(&t[1]); - // CHECK: call i32 @_Z27NoViableOverloadObjectSize2PvU17pass_object_size2(i8* noundef %{{.*}}, i64 noundef 360) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize2PvU17pass_object_size2(i8* %{{.*}}, i64 360) gi = NoViableOverloadObjectSize2(&t[1]); - // CHECK: call i32 @_Z27NoViableOverloadObjectSize3PvU17pass_object_size3(i8* noundef %{{.*}}, i64 noundef 360) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize3PvU17pass_object_size3(i8* %{{.*}}, i64 360) gi = NoViableOverloadObjectSize3(&t[1]); - // CHECK: call i32 @_Z27NoViableOverloadObjectSize0PvU17pass_object_size0(i8* noundef %{{.*}}, i64 noundef 356) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize0PvU17pass_object_size0(i8* %{{.*}}, i64 356) gi = NoViableOverloadObjectSize0(&t[1].t[1]); - // CHECK: call i32 @_Z27NoViableOverloadObjectSize1PvU17pass_object_size1(i8* noundef %{{.*}}, i64 noundef 36) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize1PvU17pass_object_size1(i8* %{{.*}}, i64 36) gi = NoViableOverloadObjectSize1(&t[1].t[1]); - // CHECK: call i32 @_Z27NoViableOverloadObjectSize2PvU17pass_object_size2(i8* noundef %{{.*}}, i64 noundef 356) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize2PvU17pass_object_size2(i8* %{{.*}}, i64 356) gi = NoViableOverloadObjectSize2(&t[1].t[1]); - // CHECK: call i32 @_Z27NoViableOverloadObjectSize3PvU17pass_object_size3(i8* noundef %{{.*}}, i64 noundef 36) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize3PvU17pass_object_size3(i8* %{{.*}}, i64 36) gi = NoViableOverloadObjectSize3(&t[1].t[1]); - // CHECK: call i32 @_Z34NoViableOverloadDynamicObjectSize0PvU25pass_dynamic_object_size0(i8* noundef %{{.*}}, i64 noundef 360) + // CHECK: call i32 @_Z34NoViableOverloadDynamicObjectSize0PvU25pass_dynamic_object_size0(i8* %{{.*}}, i64 360) gi = NoViableOverloadDynamicObjectSize0(&t[1]); } // CHECK-LABEL: define{{.*}} void @test4 void test4(struct Foo *t) { - // CHECK: call i32 @_Z27NoViableOverloadObjectSize0PvU17pass_object_size0(i8* noundef %{{.*}}, i64 noundef %{{.*}}) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize0PvU17pass_object_size0(i8* %{{.*}}, i64 %{{.*}}) gi = NoViableOverloadObjectSize0(&t[1]); - // CHECK: call i32 @_Z27NoViableOverloadObjectSize1PvU17pass_object_size1(i8* noundef %{{.*}}, i64 noundef %{{.*}}) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize1PvU17pass_object_size1(i8* %{{.*}}, i64 %{{.*}}) gi = NoViableOverloadObjectSize1(&t[1]); - // CHECK: call i32 @_Z27NoViableOverloadObjectSize2PvU17pass_object_size2(i8* noundef %{{.*}}, i64 noundef %{{.*}}) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize2PvU17pass_object_size2(i8* %{{.*}}, i64 %{{.*}}) gi = NoViableOverloadObjectSize2(&t[1]); - // CHECK: call i32 @_Z27NoViableOverloadObjectSize3PvU17pass_object_size3(i8* noundef %{{.*}}, i64 noundef 0) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize3PvU17pass_object_size3(i8* %{{.*}}, i64 0) gi = NoViableOverloadObjectSize3(&t[1]); - // CHECK: call i32 @_Z27NoViableOverloadObjectSize0PvU17pass_object_size0(i8* noundef %{{.*}}, i64 noundef %{{.*}}) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize0PvU17pass_object_size0(i8* %{{.*}}, i64 %{{.*}}) gi = NoViableOverloadObjectSize0(&t[1].t[1]); // CHECK: [[VAR:%[0-9]+]] = call i64 @llvm.objectsize - // CHECK: call i32 @_Z27NoViableOverloadObjectSize1PvU17pass_object_size1(i8* noundef %{{.*}}, i64 noundef [[VAR]]) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize1PvU17pass_object_size1(i8* %{{.*}}, i64 [[VAR]]) gi = NoViableOverloadObjectSize1(&t[1].t[1]); - // CHECK: call i32 @_Z27NoViableOverloadObjectSize2PvU17pass_object_size2(i8* noundef %{{.*}}, i64 noundef %{{.*}}) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize2PvU17pass_object_size2(i8* %{{.*}}, i64 %{{.*}}) gi = NoViableOverloadObjectSize2(&t[1].t[1]); - // CHECK: call i32 @_Z27NoViableOverloadObjectSize3PvU17pass_object_size3(i8* noundef %{{.*}}, i64 noundef 36) + // CHECK: call i32 @_Z27NoViableOverloadObjectSize3PvU17pass_object_size3(i8* %{{.*}}, i64 36) gi = NoViableOverloadObjectSize3(&t[1].t[1]); } @@ -247,34 +247,34 @@ void test5() { // CHECK-LABEL: define{{.*}} i32 @IndirectObjectSize0 int IndirectObjectSize0(void *const p PS(0)) { - // CHECK: call i32 @ObjectSize0(i8* noundef %{{.*}}, i64 noundef %{{.*}}) + // CHECK: call i32 @ObjectSize0(i8* %{{.*}}, i64 %{{.*}}) // CHECK-NOT: @llvm.objectsize return ObjectSize0(p); } // CHECK-LABEL: define{{.*}} i32 @IndirectObjectSize1 int IndirectObjectSize1(void *const p PS(1)) { - // CHECK: call i32 @ObjectSize1(i8* noundef %{{.*}}, i64 noundef %{{.*}}) + // CHECK: call i32 @ObjectSize1(i8* %{{.*}}, i64 %{{.*}}) // CHECK-NOT: @llvm.objectsize return ObjectSize1(p); } // CHECK-LABEL: define{{.*}} i32 @IndirectObjectSize2 int IndirectObjectSize2(void *const p PS(2)) { - // CHECK: call i32 @ObjectSize2(i8* noundef %{{.*}}, i64 noundef %{{.*}}) + // CHECK: call i32 @ObjectSize2(i8* %{{.*}}, i64 %{{.*}}) // CHECK-NOT: @llvm.objectsize return ObjectSize2(p); } // CHECK-LABEL: define{{.*}} i32 @IndirectObjectSize3 int IndirectObjectSize3(void *const p PS(3)) { - // CHECK: call i32 @ObjectSize3(i8* noundef %{{.*}}, i64 noundef %{{.*}}) + // CHECK: call i32 @ObjectSize3(i8* %{{.*}}, i64 %{{.*}}) // CHECK-NOT: @llvm.objectsize return ObjectSize3(p); } int IndirectDynamicObjectSize0(void *const p PDS(0)) { - // CHECK: call i32 @ObjectSize0(i8* noundef %{{.*}}, i64 noundef %{{.*}}) + // CHECK: call i32 @ObjectSize0(i8* %{{.*}}, i64 %{{.*}}) // CHECK-NOT: @llvm.objectsize return ObjectSize0(p); } @@ -321,31 +321,31 @@ int AsmObjectSize3(void *const p PS(3)) __asm__("Identity"); void test7() { struct Foo t[10]; - // CHECK: call i32 @"\01Identity"(i8* noundef %{{.*}}, i64 noundef 360) + // CHECK: call i32 @"\01Identity"(i8* %{{.*}}, i64 360) gi = AsmObjectSize0(&t[1]); - // CHECK: call i32 @"\01Identity"(i8* noundef %{{.*}}, i64 noundef 360) + // CHECK: call i32 @"\01Identity"(i8* %{{.*}}, i64 360) gi = AsmObjectSize1(&t[1]); - // CHECK: call i32 @"\01Identity"(i8* noundef %{{.*}}, i64 noundef 360) + // CHECK: call i32 @"\01Identity"(i8* %{{.*}}, i64 360) gi = AsmObjectSize2(&t[1]); - // CHECK: call i32 @"\01Identity"(i8* noundef %{{.*}}, i64 noundef 360) + // CHECK: call i32 @"\01Identity"(i8* %{{.*}}, i64 360) gi = AsmObjectSize3(&t[1]); - // CHECK: call i32 @"\01Identity"(i8* noundef %{{.*}}, i64 noundef 356) + // CHECK: call i32 @"\01Identity"(i8* %{{.*}}, i64 356) gi = AsmObjectSize0(&t[1].t[1]); - // CHECK: call i32 @"\01Identity"(i8* noundef %{{.*}}, i64 noundef 36) + // CHECK: call i32 @"\01Identity"(i8* %{{.*}}, i64 36) gi = AsmObjectSize1(&t[1].t[1]); - // CHECK: call i32 @"\01Identity"(i8* noundef %{{.*}}, i64 noundef 356) + // CHECK: call i32 @"\01Identity"(i8* %{{.*}}, i64 356) gi = AsmObjectSize2(&t[1].t[1]); - // CHECK: call i32 @"\01Identity"(i8* noundef %{{.*}}, i64 noundef 36) + // CHECK: call i32 @"\01Identity"(i8* %{{.*}}, i64 36) gi = AsmObjectSize3(&t[1].t[1]); } // CHECK-LABEL: define{{.*}} void @test8 void test8(struct Foo *t) { // CHECK: [[VAR:%[0-9]+]] = call i64 @llvm.objectsize - // CHECK: call i32 @"\01Identity"(i8* noundef %{{.*}}, i64 noundef [[VAR]]) + // CHECK: call i32 @"\01Identity"(i8* %{{.*}}, i64 [[VAR]]) gi = AsmObjectSize1(&t[1].t[1]); - // CHECK: call i32 @"\01Identity"(i8* noundef %{{.*}}, i64 noundef 36) + // CHECK: call i32 @"\01Identity"(i8* %{{.*}}, i64 36) gi = AsmObjectSize3(&t[1].t[1]); } @@ -363,7 +363,7 @@ void test9(void *const p __attribute__((pass_object_size(0)))) { DifferingObjectSize0(p); DifferingObjectSize1(p); - // CHECK: call void @DifferingObjectSize3(i8* noundef %{{.*}}, i64 noundef 0) + // CHECK: call void @DifferingObjectSize3(i8* %{{.*}}, i64 0) DifferingObjectSize3(p); } @@ -377,7 +377,7 @@ void test10(void *const p __attribute__((pass_object_size(1)))) { // CHECK-NOT: @llvm.objectsize DifferingObjectSize1(p); - // CHECK: call void @DifferingObjectSize3(i8* noundef %{{.*}}, i64 noundef 0) + // CHECK: call void @DifferingObjectSize3(i8* %{{.*}}, i64 0) DifferingObjectSize3(p); } @@ -391,7 +391,7 @@ void test11(void *const p __attribute__((pass_object_size(2)))) { // CHECK-NOT: @llvm.objectsize DifferingObjectSize2(p); - // CHECK: call void @DifferingObjectSize3(i8* noundef %{{.*}}, i64 noundef 0) + // CHECK: call void @DifferingObjectSize3(i8* %{{.*}}, i64 0) DifferingObjectSize3(p); } @@ -481,7 +481,7 @@ void test17(char *C) { // CHECK-NOT: 65535 // CHECK: @llvm.objectsize.i64.p0i8(i8* [[PTR:%[^,]+]], // CHECK-NOT: 65535 - // CHECK: call i32 @ObjectSize0(i8* noundef [[PTR]] + // CHECK: call i32 @ObjectSize0(i8* [[PTR]] ObjectSize0(C + ({ int a = 65535; a; })); } diff --git a/clang/test/CodeGen/pch-dllexport.cpp b/clang/test/CodeGen/pch-dllexport.cpp index 357a7263cc66106a815873ee50bfe577cf1381b5..72f344c77be1d22592889e5c1ae1909ad425605a 100644 --- a/clang/test/CodeGen/pch-dllexport.cpp +++ b/clang/test/CodeGen/pch-dllexport.cpp @@ -91,7 +91,7 @@ template void __declspec(dllexport) explicitInstantiationDef(int); // PCHWITHOBJ: define weak_odr dso_local dllexport void @"??$explicitInstantiationDef@H@@YAXH@Z" template void __declspec(dllexport) explicitInstantiationDefAfterDecl(int); -// PCHWITHOBJ: define weak_odr dso_local dllexport void @"??$explicitInstantiationDefAfterDecl@H@@YAXH@Z"(i32 noundef %0) +// PCHWITHOBJ: define weak_odr dso_local dllexport void @"??$explicitInstantiationDefAfterDecl@H@@YAXH@Z"(i32 %0) template int __declspec(dllexport) variableTemplate; // PCHWITHOBJVARS: @"??$variableTemplate@H@@3HA" = weak_odr dso_local dllexport global @@ -99,6 +99,6 @@ template int __declspec(dllexport) variableTemplate; // PR38934: Make sure S::operator= gets emitted. While it itself isn't a // template specialization, its parent is. template struct __declspec(dllexport) pr38934::S; -// PCHWITHOBJ: define weak_odr dso_local dllexport x86_thiscallcc noundef nonnull align 1 dereferenceable(1) %"struct.pr38934::S"* @"??4?$S@H@pr38934@@QAEAAU01@ABU01@@Z" +// PCHWITHOBJ: define weak_odr dso_local dllexport x86_thiscallcc nonnull align 1 dereferenceable(1) %"struct.pr38934::S"* @"??4?$S@H@pr38934@@QAEAAU01@ABU01@@Z" #endif diff --git a/clang/test/CodeGen/pgo-instrumentation.c b/clang/test/CodeGen/pgo-instrumentation.c index 36c6724d82815a23d8903c511fefdcc4f7007908..a65c6712291bd26c414e88d29498339f599ada6e 100644 --- a/clang/test/CodeGen/pgo-instrumentation.c +++ b/clang/test/CodeGen/pgo-instrumentation.c @@ -1,36 +1,24 @@ // Test if PGO instrumentation and use pass are invoked. // // Ensure Pass PGOInstrumentationGenPass is invoked. -// RUN: %clang_cc1 -O2 -fno-experimental-new-pass-manager -fprofile-instrument=llvm %s -mllvm -debug-pass=Structure -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOGENPASS-INVOKED-INSTR-GEN --check-prefix=CHECK-INSTRPROF -// RUN: %clang_cc1 -O2 -fprofile-instrument=llvm %s -fexperimental-new-pass-manager -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOGENPASS-INVOKED-INSTR-GEN-NEWPM --check-prefix=CHECK-INSTRPROF-NEWPM -// CHECK-PGOGENPASS-INVOKED-INSTR-GEN: PGOInstrumentationGenPass -// CHECK-INSTRPROF: Frontend instrumentation-based coverage lowering -// CHECK-PGOGENPASS-INVOKED-INSTR-GEN-NEWPM: Running pass: PGOInstrumentationGen on -// CHECK-INSTRPROF-NEWPM: Running pass: InstrProfiling on +// RUN: %clang_cc1 -O2 -fprofile-instrument=llvm %s -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOGENPASS-INVOKED-INSTR-GEN --check-prefix=CHECK-INSTRPROF +// CHECK-PGOGENPASS-INVOKED-INSTR-GEN: Running pass: PGOInstrumentationGen on +// CHECK-INSTRPROF: Running pass: InstrProfiling on // // Ensure Pass PGOInstrumentationGenPass is not invoked. -// RUN: %clang_cc1 -O2 -fprofile-instrument=clang %s -mllvm -debug-pass=Structure -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOGENPASS-INVOKED-INSTR-GEN-CLANG -// RUN: %clang_cc1 -O2 -fprofile-instrument=clang %s -fexperimental-new-pass-manager -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOGENPASS-INVOKED-INSTR-GEN-CLANG-NEWPM -// CHECK-PGOGENPASS-INVOKED-INSTR-GEN-CLANG-NOT: PGOInstrumentationGenPass -// CHECK-PGOGENPASS-INVOKED-INSTR-GEN-CLANG-NEWPM-NOT: Running pass: PGOInstrumentationGen on +// RUN: %clang_cc1 -O2 -fprofile-instrument=clang %s -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOGENPASS-INVOKED-INSTR-GEN-CLANG +// CHECK-PGOGENPASS-INVOKED-INSTR-GEN-CLANG-NOT: Running pass: PGOInstrumentationGen on -// RUN: %clang_cc1 -O2 -fno-experimental-new-pass-manager -fprofile-instrument=clang %s -mllvm -debug-pass=Structure -emit-llvm -o - 2>&1 | FileCheck %s --check-prefix=CHECK-CLANG-INSTRPROF -// RUN: %clang_cc1 -O2 -fprofile-instrument=clang %s -fexperimental-new-pass-manager -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s --check-prefix=CHECK-CLANG-INSTRPROF-NEWPM -// RUN: %clang_cc1 -O0 -fno-experimental-new-pass-manager -fprofile-instrument=clang %s -mllvm -debug-pass=Structure -emit-llvm -o - 2>&1 | FileCheck %s --check-prefix=CHECK-CLANG-INSTRPROF -// RUN: %clang_cc1 -O0 -fprofile-instrument=clang %s -fexperimental-new-pass-manager -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s --check-prefix=CHECK-CLANG-INSTRPROF-NEWPM -// CHECK-CLANG-INSTRPROF: Frontend instrumentation-based coverage lowering -// CHECK-CLANG-INSTRPROF-NEWPM: Running pass: InstrProfiling on +// RUN: %clang_cc1 -O2 -fprofile-instrument=clang %s -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s --check-prefix=CHECK-CLANG-INSTRPROF +// RUN: %clang_cc1 -O0 -fprofile-instrument=clang %s -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s --check-prefix=CHECK-CLANG-INSTRPROF +// CHECK-CLANG-INSTRPROF: Running pass: InstrProfiling on // Ensure Pass PGOInstrumentationUsePass is invoked. // RUN: llvm-profdata merge -o %t.profdata %S/Inputs/pgotestir.profraw -// RUN: %clang_cc1 -O2 -fno-experimental-new-pass-manager -fprofile-instrument-use-path=%t.profdata %s -mllvm -debug-pass=Structure -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOUSEPASS-INVOKED-INSTR-USE -// RUN: %clang_cc1 -O2 -fprofile-instrument-use-path=%t.profdata %s -fexperimental-new-pass-manager -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOUSEPASS-INVOKED-INSTR-USE-NEWPM -// CHECK-PGOUSEPASS-INVOKED-INSTR-USE: PGOInstrumentationUsePass -// CHECK-PGOUSEPASS-INVOKED-INSTR-USE-NEWPM: Running pass: PGOInstrumentationUse on +// RUN: %clang_cc1 -O2 -fprofile-instrument-use-path=%t.profdata %s -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOUSEPASS-INVOKED-INSTR-USE +// CHECK-PGOUSEPASS-INVOKED-INSTR-USE: Running pass: PGOInstrumentationUse on // // Ensure Pass PGOInstrumentationUsePass is not invoked. // RUN: llvm-profdata merge -o %t.profdata %S/Inputs/pgotestclang.profraw -// RUN: %clang_cc1 -O2 -fprofile-instrument-use-path=%t.profdata %s -mllvm -debug-pass=Structure -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOUSEPASS-INVOKED-USE-CLANG -// RUN: %clang_cc1 -O2 -fprofile-instrument-use-path=%t.profdata %s -fexperimental-new-pass-manager -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOUSEPASS-INVOKED-USE-CLANG-NEWPM -// CHECK-PGOUSEPASS-INVOKED-USE-CLANG-NOT: PGOInstrumentationUsePass -// CHECK-PGOUSEPASS-INVOKED-USE-CLANG-NEWPM-NOT: Running pass: PGOInstrumentationUse on +// RUN: %clang_cc1 -O2 -fprofile-instrument-use-path=%t.profdata %s -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PGOUSEPASS-INVOKED-USE-CLANG +// CHECK-PGOUSEPASS-INVOKED-USE-CLANG-NOT: Running pass: PGOInstrumentationUse on diff --git a/clang/test/CodeGen/pgo-sample.c b/clang/test/CodeGen/pgo-sample.c index f0e73ec076ef4bc8825027f119e8bbb430bdf464..07cabb3cf16ad2bbddc33ea2659bc02cbea1e035 100644 --- a/clang/test/CodeGen/pgo-sample.c +++ b/clang/test/CodeGen/pgo-sample.c @@ -1,13 +1,9 @@ // Test if PGO sample use passes are invoked. // // Ensure Pass PGOInstrumentationGenPass is invoked. -// RUN: %clang_cc1 -O2 -fno-experimental-new-pass-manager -fprofile-sample-use=%S/Inputs/pgo-sample.prof %s -mllvm -debug-pass=Structure -emit-llvm -o - 2>&1 | FileCheck %s --check-prefix=LEGACY -// RUN: %clang_cc1 -O2 -fexperimental-new-pass-manager -fprofile-sample-use=%S/Inputs/pgo-sample.prof %s -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s --check-prefix=NEWPM +// RUN: %clang_cc1 -O2 -fprofile-sample-use=%S/Inputs/pgo-sample.prof %s -fdebug-pass-manager -emit-llvm -o - 2>&1 | FileCheck %s -// LEGACY: Remove unused exception handling info -// LEGACY: Sample profile pass - -// NEWPM: SimplifyCFGPass -// NEWPM: SampleProfileLoaderPass +// CHECK: SimplifyCFGPass +// CHECK: SampleProfileLoaderPass int func(int a) { return a; } diff --git a/clang/test/CodeGen/powerpc-c99complex.c b/clang/test/CodeGen/powerpc-c99complex.c index 19d81573c6699658f4e37ffae95a2ca473ae3da0..0b012e9b909ddc12c9607c7c77469e7201dcc612 100644 --- a/clang/test/CodeGen/powerpc-c99complex.c +++ b/clang/test/CodeGen/powerpc-c99complex.c @@ -6,10 +6,10 @@ _Complex float foo1(_Complex float x) { return x; -// CHECK-LABEL: define{{.*}} { float, float } @foo1(float noundef %x.{{.*}}, float noundef %x.{{.*}}) #0 { +// CHECK-LABEL: define{{.*}} { float, float } @foo1(float %x.{{.*}}, float %x.{{.*}}) #0 { // CHECK: ret { float, float } -// PPC32LNX-LABEL: define{{.*}} void @foo1({ float, float }* noalias sret({ float, float }) align 4 %agg.result, { float, float }* noundef byval({ float, float }) align 4 %x) #0 { +// PPC32LNX-LABEL: define{{.*}} void @foo1({ float, float }* noalias sret({ float, float }) align 4 %agg.result, { float, float }* byval({ float, float }) align 4 %x) #0 { // PPC32LNX: [[RETREAL:%.*]] = getelementptr inbounds { float, float }, { float, float }* %agg.result, i32 0, i32 0 // PPC32LNX-NEXT: [[RETIMAG:%.*]] = getelementptr inbounds { float, float }, { float, float }* %agg.result, i32 0, i32 1 // PPC32LNX-NEXT: store float %{{.*}}, float* [[RETREAL]], align 4 @@ -18,10 +18,10 @@ _Complex float foo1(_Complex float x) { _Complex double foo2(_Complex double x) { return x; -// CHECK-LABEL: define{{.*}} { double, double } @foo2(double noundef %x.{{.*}}, double noundef %x.{{.*}}) #0 { +// CHECK-LABEL: define{{.*}} { double, double } @foo2(double %x.{{.*}}, double %x.{{.*}}) #0 { // CHECK: ret { double, double } -// PPC32LNX-LABEL: define{{.*}} void @foo2({ double, double }* noalias sret({ double, double }) align 8 %agg.result, { double, double }* noundef byval({ double, double }) align 8 %x) #0 { +// PPC32LNX-LABEL: define{{.*}} void @foo2({ double, double }* noalias sret({ double, double }) align 8 %agg.result, { double, double }* byval({ double, double }) align 8 %x) #0 { // PPC32LNX: [[RETREAL:%.*]] = getelementptr inbounds { double, double }, { double, double }* %agg.result, i32 0, i32 0 // PPC32LNX-NEXT: [[RETIMAG:%.*]] = getelementptr inbounds { double, double }, { double, double }* %agg.result, i32 0, i32 1 // PPC32LNX-NEXT: store double %{{.*}}, double* [[RETREAL]], align 8 @@ -30,13 +30,13 @@ _Complex double foo2(_Complex double x) { _Complex long double foo3(_Complex long double x) { return x; -// CHECK-NOLDBL128-LABEL: define{{.*}} { double, double } @foo3(double noundef %x.{{.*}}, double noundef %x.{{.*}}) #0 { +// CHECK-NOLDBL128-LABEL: define{{.*}} { double, double } @foo3(double %x.{{.*}}, double %x.{{.*}}) #0 { // CHECK-NOLDBL128: ret { double, double } -// CHECK-LDBL128-LABEL: define{{.*}} { ppc_fp128, ppc_fp128 } @foo3(ppc_fp128 noundef %x.{{.*}}, ppc_fp128 noundef %x.{{.*}}) #0 { +// CHECK-LDBL128-LABEL: define{{.*}} { ppc_fp128, ppc_fp128 } @foo3(ppc_fp128 %x.{{.*}}, ppc_fp128 %x.{{.*}}) #0 { // CHECK-LDBL128: ret { ppc_fp128, ppc_fp128 } -// PPC32LNX-LABEL: define{{.*}} void @foo3({ ppc_fp128, ppc_fp128 }* noalias sret({ ppc_fp128, ppc_fp128 }) align 16 %agg.result, { ppc_fp128, ppc_fp128 }* noundef byval({ ppc_fp128, ppc_fp128 }) align 16 %x) #0 { +// PPC32LNX-LABEL: define{{.*}} void @foo3({ ppc_fp128, ppc_fp128 }* noalias sret({ ppc_fp128, ppc_fp128 }) align 16 %agg.result, { ppc_fp128, ppc_fp128 }* byval({ ppc_fp128, ppc_fp128 }) align 16 %x) #0 { // PPC32LNX: [[RETREAL:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %agg.result, i32 0, i32 0 // PPC32LNX-NEXT: [[RETIMAG:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %agg.result, i32 0, i32 1 // PPC32LNX-NEXT: store ppc_fp128 %{{.*}}, ppc_fp128* [[RETREAL]], align 16 diff --git a/clang/test/CodeGen/ppc-emmintrin.c b/clang/test/CodeGen/ppc-emmintrin.c index 03e91f06bb16e030d1cbafee0008f6663d6ca8a2..fa3801f50a019b6457faec65977493134f6e47d6 100644 --- a/clang/test/CodeGen/ppc-emmintrin.c +++ b/clang/test/CodeGen/ppc-emmintrin.c @@ -47,7 +47,7 @@ test_add() { // CHECK-LABEL: @test_add -// CHECK: define available_externally <2 x i64> @_mm_add_epi64(<2 x i64> noundef [[REG1:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG2:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_add_epi64(<2 x i64> [[REG1:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG2:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1]], <2 x i64>* [[REG3:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG2]], <2 x i64>* [[REG4:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG5:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG3]], align 16 @@ -55,7 +55,7 @@ test_add() { // CHECK-NEXT: [[REG7:[0-9a-zA-Z_%.]+]] = add <2 x i64> [[REG5]], [[REG6]] // CHECK-NEXT: ret <2 x i64> [[REG7]] -// CHECK: define available_externally <2 x i64> @_mm_add_epi32(<2 x i64> noundef [[REG8:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG9:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_add_epi32(<2 x i64> [[REG8:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG9:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG8]], <2 x i64>* [[REG10:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG9]], <2 x i64>* [[REG11:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG12:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG10]], align 16 @@ -66,7 +66,7 @@ test_add() { // CHECK-NEXT: [[REG17:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG16]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG17]] -// CHECK: define available_externally <2 x i64> @_mm_add_epi16(<2 x i64> noundef [[REG18:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG19:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_add_epi16(<2 x i64> [[REG18:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG19:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG18]], <2 x i64>* [[REG20:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG19]], <2 x i64>* [[REG21:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG22:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG20]], align 16 @@ -77,7 +77,7 @@ test_add() { // CHECK-NEXT: [[REG27:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG26]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG27]] -// CHECK: define available_externally <2 x i64> @_mm_add_epi8(<2 x i64> noundef [[REG28:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG29:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_add_epi8(<2 x i64> [[REG28:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG29:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG28]], <2 x i64>* [[REG30:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG29]], <2 x i64>* [[REG31:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG32:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG30]], align 16 @@ -88,7 +88,7 @@ test_add() { // CHECK-NEXT: [[REG37:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG36]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG37]] -// CHECK: define available_externally <2 x double> @_mm_add_pd(<2 x double> noundef [[REG38:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG39:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_add_pd(<2 x double> [[REG38:[0-9a-zA-Z_%.]+]], <2 x double> [[REG39:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG38]], <2 x double>* [[REG40:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG39]], <2 x double>* [[REG41:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG42:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG40]], align 16 @@ -96,7 +96,7 @@ test_add() { // CHECK-NEXT: [[REG44:[0-9a-zA-Z_%.]+]] = fadd <2 x double> [[REG42]], [[REG43]] // CHECK-NEXT: ret <2 x double> [[REG44]] -// CHECK: define available_externally <2 x double> @_mm_add_sd(<2 x double> noundef [[REG45:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG46:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_add_sd(<2 x double> [[REG45:[0-9a-zA-Z_%.]+]], <2 x double> [[REG46:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG45]], <2 x double>* [[REG47:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG46]], <2 x double>* [[REG48:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG49:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG47]], align 16 @@ -110,7 +110,7 @@ test_add() { // CHECK-NEXT: [[REG56:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG47]], align 16 // CHECK-NEXT: ret <2 x double> [[REG56]] -// CHECK: define available_externally i64 @_mm_add_si64(i64 noundef [[REG57:[0-9a-zA-Z_%.]+]], i64 noundef [[REG58:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_add_si64(i64 [[REG57:[0-9a-zA-Z_%.]+]], i64 [[REG58:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG57]], i64* [[REG59:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG58]], i64* [[REG60:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG61:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG59]], align 8 @@ -118,47 +118,47 @@ test_add() { // CHECK-NEXT: [[REG63:[0-9a-zA-Z_%.]+]] = add i64 [[REG61]], [[REG62]] // CHECK-NEXT: ret i64 [[REG63]] -// CHECK: define available_externally <2 x i64> @_mm_adds_epi16(<2 x i64> noundef [[REG64:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG65:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_adds_epi16(<2 x i64> [[REG64:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG65:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG64]], <2 x i64>* [[REG66:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG65]], <2 x i64>* [[REG67:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG68:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG66]], align 16 // CHECK-NEXT: [[REG69:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG68]] to <8 x i16> // CHECK-NEXT: [[REG70:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG67]], align 16 // CHECK-NEXT: [[REG71:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG70]] to <8 x i16> -// CHECK-NEXT: [[REG72:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_adds(short vector[8], short vector[8])(<8 x i16> noundef [[REG69]], <8 x i16> noundef [[REG71]]) +// CHECK-NEXT: [[REG72:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_adds(short vector[8], short vector[8])(<8 x i16> [[REG69]], <8 x i16> [[REG71]]) // CHECK-NEXT: [[REG73:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG72]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG73]] -// CHECK: define available_externally <2 x i64> @_mm_adds_epi8(<2 x i64> noundef [[REG74:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG75:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_adds_epi8(<2 x i64> [[REG74:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG75:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG74]], <2 x i64>* [[REG76:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG75]], <2 x i64>* [[REG77:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG78:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG76]], align 16 // CHECK-NEXT: [[REG79:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG78]] to <16 x i8> // CHECK-NEXT: [[REG80:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG77]], align 16 // CHECK-NEXT: [[REG81:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG80]] to <16 x i8> -// CHECK-NEXT: [[REG82:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_adds(signed char vector[16], signed char vector[16])(<16 x i8> noundef [[REG79]], <16 x i8> noundef [[REG81]]) +// CHECK-NEXT: [[REG82:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_adds(signed char vector[16], signed char vector[16])(<16 x i8> [[REG79]], <16 x i8> [[REG81]]) // CHECK-NEXT: [[REG83:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG82]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG83]] -// CHECK: define available_externally <2 x i64> @_mm_adds_epu16(<2 x i64> noundef [[REG84:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG85:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_adds_epu16(<2 x i64> [[REG84:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG85:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG84]], <2 x i64>* [[REG86:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG85]], <2 x i64>* [[REG87:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG88:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG86]], align 16 // CHECK-NEXT: [[REG89:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG88]] to <8 x i16> // CHECK-NEXT: [[REG90:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG87]], align 16 // CHECK-NEXT: [[REG91:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG90]] to <8 x i16> -// CHECK-NEXT: [[REG92:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_adds(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG89]], <8 x i16> noundef [[REG91]]) +// CHECK-NEXT: [[REG92:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_adds(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG89]], <8 x i16> [[REG91]]) // CHECK-NEXT: [[REG93:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG92]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG93]] -// CHECK: define available_externally <2 x i64> @_mm_adds_epu8(<2 x i64> noundef [[REG94:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG95:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_adds_epu8(<2 x i64> [[REG94:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG95:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG94]], <2 x i64>* [[REG96:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG95]], <2 x i64>* [[REG97:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG98:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG96]], align 16 // CHECK-NEXT: [[REG99:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG98]] to <16 x i8> // CHECK-NEXT: [[REG100:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG97]], align 16 // CHECK-NEXT: [[REG101:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG100]] to <16 x i8> -// CHECK-NEXT: [[REG102:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_adds(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG99]], <16 x i8> noundef [[REG101]]) +// CHECK-NEXT: [[REG102:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_adds(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG99]], <16 x i8> [[REG101]]) // CHECK-NEXT: [[REG103:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG102]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG103]] @@ -170,25 +170,25 @@ test_avg() { // CHECK-LABEL: @test_avg -// CHECK: define available_externally <2 x i64> @_mm_avg_epu16(<2 x i64> noundef [[REG104:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG105:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_avg_epu16(<2 x i64> [[REG104:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG105:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG104]], <2 x i64>* [[REG106:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG105]], <2 x i64>* [[REG107:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG108:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG106]], align 16 // CHECK-NEXT: [[REG109:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG108]] to <8 x i16> // CHECK-NEXT: [[REG110:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG107]], align 16 // CHECK-NEXT: [[REG111:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG110]] to <8 x i16> -// CHECK-NEXT: [[REG112:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_avg(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG109]], <8 x i16> noundef [[REG111]]) +// CHECK-NEXT: [[REG112:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_avg(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG109]], <8 x i16> [[REG111]]) // CHECK-NEXT: [[REG113:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG112]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG113]] -// CHECK: define available_externally <2 x i64> @_mm_avg_epu8(<2 x i64> noundef [[REG114:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG115:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_avg_epu8(<2 x i64> [[REG114:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG115:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG114]], <2 x i64>* [[REG116:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG115]], <2 x i64>* [[REG117:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG118:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG116]], align 16 // CHECK-NEXT: [[REG119:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG118]] to <16 x i8> // CHECK-NEXT: [[REG120:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG117]], align 16 // CHECK-NEXT: [[REG121:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG120]] to <16 x i8> -// CHECK-NEXT: [[REG122:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_avg(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG119]], <16 x i8> noundef [[REG121]]) +// CHECK-NEXT: [[REG122:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_avg(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG119]], <16 x i8> [[REG121]]) // CHECK-NEXT: [[REG123:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG122]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG123]] @@ -200,7 +200,7 @@ test_bs() { // CHECK-LABEL: @test_bs -// CHECK: define available_externally <2 x i64> @_mm_bslli_si128(<2 x i64> noundef [[REG124:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG125:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_bslli_si128(<2 x i64> [[REG124:[0-9a-zA-Z_%.]+]], i32 signext [[REG125:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG124]], <2 x i64>* [[REG126:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG125]], i32* [[REG127:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store <16 x i8> zeroinitializer, <16 x i8>* [[REG128:[0-9a-zA-Z_%.]+]], align 16 @@ -211,7 +211,7 @@ test_bs() { // CHECK-NEXT: [[REG133:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG126]], align 16 // CHECK-NEXT: [[REG134:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG133]] to <16 x i8> // CHECK-NEXT: [[REG135:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG127]], align 4 -// CHECK-NEXT: [[REG136:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sld(unsigned char vector[16], unsigned char vector[16], unsigned int)(<16 x i8> noundef [[REG134]], <16 x i8> noundef zeroinitializer, i32 noundef zeroext [[REG135]]) +// CHECK-NEXT: [[REG136:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sld(unsigned char vector[16], unsigned char vector[16], unsigned int)(<16 x i8> [[REG134]], <16 x i8> zeroinitializer, i32 zeroext [[REG135]]) // CHECK-NEXT: store <16 x i8> [[REG136]], <16 x i8>* [[REG137:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: br label %[[REG138:[0-9a-zA-Z_%.]+]] // CHECK: [[REG132]]: @@ -222,7 +222,7 @@ test_bs() { // CHECK-NEXT: [[REG140:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG139]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG140]] -// CHECK: define available_externally <2 x i64> @_mm_bsrli_si128(<2 x i64> noundef [[REG141:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG142:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_bsrli_si128(<2 x i64> [[REG141:[0-9a-zA-Z_%.]+]], i32 signext [[REG142:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG141]], <2 x i64>* [[REG143:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG142]], i32* [[REG144:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store <16 x i8> zeroinitializer, <16 x i8>* [[REG145:[0-9a-zA-Z_%.]+]], align 16 @@ -239,19 +239,19 @@ test_bs() { // CHECK-LE-NEXT: [[REG153:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG152]] to <16 x i8> // CHECK-LE-NEXT: [[REG154:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG144]], align 4 // CHECK-LE-NEXT: [[REG155:[0-9a-zA-Z_%.]+]] = sub nsw i32 16, [[REG154]] -// CHECK-LE-NEXT: [[REG156:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sld(unsigned char vector[16], unsigned char vector[16], unsigned int)(<16 x i8> noundef zeroinitializer, <16 x i8> noundef [[REG153]], i32 noundef zeroext [[REG155]]) +// CHECK-LE-NEXT: [[REG156:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sld(unsigned char vector[16], unsigned char vector[16], unsigned int)(<16 x i8> zeroinitializer, <16 x i8> [[REG153]], i32 zeroext [[REG155]]) // CHECK-LE-NEXT: store <16 x i8> [[REG156]], <16 x i8>* [[REG157:[0-9a-zA-Z_%.]+]], align 16 // CHECK-LE-NEXT: br label %[[REG158:[0-9a-zA-Z_%.]+]] // CHECK-LE: [[REG151]]: // CHECK-LE: [[REG159:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG144]], align 4 // CHECK-LE-NEXT: [[REG160:[0-9a-zA-Z_%.]+]] = mul nsw i32 [[REG159]], 8 // CHECK-LE-NEXT: [[REG161:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG160]] to i8 -// CHECK-LE-NEXT: [[REG162:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 noundef zeroext [[REG161]]) +// CHECK-LE-NEXT: [[REG162:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 zeroext [[REG161]]) // CHECK-LE-NEXT: store <16 x i8> [[REG162]], <16 x i8>* [[REG163:[0-9a-zA-Z_%.]+]], align 16 // CHECK-LE-NEXT: [[REG164:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG143]], align 16 // CHECK-LE-NEXT: [[REG165:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG164]] to <16 x i8> // CHECK-LE-NEXT: [[REG166:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG163]], align 16 -// CHECK-LE-NEXT: [[REG167:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sro(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG165]], <16 x i8> noundef [[REG166]]) +// CHECK-LE-NEXT: [[REG167:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sro(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG165]], <16 x i8> [[REG166]]) // CHECK-LE-NEXT: store <16 x i8> [[REG167]], <16 x i8>* [[REG157]], align 16 // CHECK-LE-NEXT: br label %[[REG158:[0-9a-zA-Z_%.]+]] // CHECK-LE: [[REG158]]: @@ -267,12 +267,12 @@ test_bs() { // CHECK-BE: [[REG171:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG144]], align 4 // CHECK-BE-NEXT: [[REG172:[0-9a-zA-Z_%.]+]] = mul nsw i32 [[REG171]], 8 // CHECK-BE-NEXT: [[REG173:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG172]] to i8 -// CHECK-BE-NEXT: [[REG174:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 noundef zeroext [[REG173]]) +// CHECK-BE-NEXT: [[REG174:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 zeroext [[REG173]]) // CHECK-BE-NEXT: store <16 x i8> [[REG174]], <16 x i8>* [[REG175:[0-9a-zA-Z_%.]+]], align 16 // CHECK-BE-NEXT: [[REG176:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG143]], align 16 // CHECK-BE-NEXT: [[REG177:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG176]] to <16 x i8> // CHECK-BE-NEXT: [[REG178:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG175]], align 16 -// CHECK-BE-NEXT: [[REG179:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_slo(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG177]], <16 x i8> noundef [[REG178]]) +// CHECK-BE-NEXT: [[REG179:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_slo(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG177]], <16 x i8> [[REG178]]) // CHECK-BE-NEXT: store <16 x i8> [[REG179]], <16 x i8>* [[REG180:[0-9a-zA-Z_%.]+]], align 16 // CHECK-BE-NEXT: br label %[[REG181:[0-9a-zA-Z_%.]+]] // CHECK-BE: [[REG149]]: @@ -295,37 +295,37 @@ test_cast() { // CHECK-LABEL: @test_cast -// CHECK: define available_externally <4 x float> @_mm_castpd_ps(<2 x double> noundef [[REG184:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_castpd_ps(<2 x double> [[REG184:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG184]], <2 x double>* [[REG185:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG186:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG185]], align 16 // CHECK-NEXT: [[REG187:[0-9a-zA-Z_%.]+]] = bitcast <2 x double> [[REG186]] to <4 x float> // CHECK-NEXT: ret <4 x float> [[REG187]] -// CHECK: define available_externally <2 x i64> @_mm_castpd_si128(<2 x double> noundef [[REG188:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_castpd_si128(<2 x double> [[REG188:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG188]], <2 x double>* [[REG189:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG190:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG189]], align 16 // CHECK-NEXT: [[REG191:[0-9a-zA-Z_%.]+]] = bitcast <2 x double> [[REG190]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG191]] -// CHECK: define available_externally <2 x double> @_mm_castps_pd(<4 x float> noundef [[REG192:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_castps_pd(<4 x float> [[REG192:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG192]], <4 x float>* [[REG193:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG194:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG193]], align 16 // CHECK-NEXT: [[REG195:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG194]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG195]] -// CHECK: define available_externally <2 x i64> @_mm_castps_si128(<4 x float> noundef [[REG196:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_castps_si128(<4 x float> [[REG196:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG196]], <4 x float>* [[REG197:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG198:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG197]], align 16 // CHECK-NEXT: [[REG199:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG198]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG199]] -// CHECK: define available_externally <2 x double> @_mm_castsi128_pd(<2 x i64> noundef [[REG200:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_castsi128_pd(<2 x i64> [[REG200:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG200]], <2 x i64>* [[REG201:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG202:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG201]], align 16 // CHECK-NEXT: [[REG203:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG202]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG203]] -// CHECK: define available_externally <4 x float> @_mm_castsi128_ps(<2 x i64> noundef [[REG204:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_castsi128_ps(<2 x i64> [[REG204:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG204]], <2 x i64>* [[REG205:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG206:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG205]], align 16 // CHECK-NEXT: [[REG207:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG206]] to <4 x float> @@ -376,7 +376,7 @@ test_cmp() { // CHECK-NEXT: ret <2 x i64> [[REG209]] // CHECK: define available_externally <2 x i64> @_mm_cmpeq_epi16 -// CHECK: [[REG210:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmpeq(short vector[8], short vector[8])(<8 x i16> noundef {{[0-9a-zA-Z_%.]+}}, <8 x i16> noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG210:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmpeq(short vector[8], short vector[8])(<8 x i16> {{[0-9a-zA-Z_%.]+}}, <8 x i16> {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG211:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG210]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG211]] @@ -420,27 +420,27 @@ test_cmp() { // CHECK-NEXT: [[REG227:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG226]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG227]] -// CHECK: define available_externally <2 x double> @_mm_cmpeq_sd(<2 x double> noundef [[REG228:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG229:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmpeq_sd(<2 x double> [[REG228:[0-9a-zA-Z_%.]+]], <2 x double> [[REG229:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG228]], <2 x double>* [[REG230:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG229]], <2 x double>* [[REG231:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG232:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG230]], align 16 // CHECK-NEXT: [[REG233:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG232]], i32 0 -// CHECK-NEXT: [[REG234:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG233]]) +// CHECK-NEXT: [[REG234:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG233]]) // CHECK-NEXT: store <2 x double> [[REG234]], <2 x double>* [[REG235:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG236:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG231]], align 16 // CHECK-NEXT: [[REG237:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG236]], i32 0 -// CHECK-NEXT: [[REG238:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG237]]) +// CHECK-NEXT: [[REG238:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG237]]) // CHECK-NEXT: store <2 x double> [[REG238]], <2 x double>* [[REG239:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG240:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG235]], align 16 // CHECK-NEXT: [[REG241:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG239]], align 16 -// CHECK-NEXT: [[REG242:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> noundef [[REG240]], <2 x double> noundef [[REG241]]) +// CHECK-NEXT: [[REG242:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> [[REG240]], <2 x double> [[REG241]]) // CHECK-NEXT: [[REG243:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG242]] to <2 x double> // CHECK-NEXT: store <2 x double> [[REG243]], <2 x double>* [[REG244:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG245:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG244]], align 16 // CHECK-NEXT: [[REG246:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG245]], i32 0 // CHECK-NEXT: [[REG247:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG230]], align 16 // CHECK-NEXT: [[REG248:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG247]], i32 1 -// CHECK-NEXT: [[REG249:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double noundef [[REG246]], double noundef [[REG248]]) +// CHECK-NEXT: [[REG249:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG246]], double [[REG248]]) // CHECK-NEXT: ret <2 x double> [[REG249]] // CHECK: define available_externally <2 x double> @_mm_cmpge_pd @@ -448,27 +448,27 @@ test_cmp() { // CHECK-NEXT: [[REG251:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG250]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG251]] -// CHECK: define available_externally <2 x double> @_mm_cmpge_sd(<2 x double> noundef [[REG252:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG253:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmpge_sd(<2 x double> [[REG252:[0-9a-zA-Z_%.]+]], <2 x double> [[REG253:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG252]], <2 x double>* [[REG254:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG253]], <2 x double>* [[REG255:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG256:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG254]], align 16 // CHECK-NEXT: [[REG257:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG256]], i32 0 -// CHECK-NEXT: [[REG258:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG257]]) +// CHECK-NEXT: [[REG258:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG257]]) // CHECK-NEXT: store <2 x double> [[REG258]], <2 x double>* [[REG259:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG260:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG255]], align 16 // CHECK-NEXT: [[REG261:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG260]], i32 0 -// CHECK-NEXT: [[REG262:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG261]]) +// CHECK-NEXT: [[REG262:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG261]]) // CHECK-NEXT: store <2 x double> [[REG262]], <2 x double>* [[REG263:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG264:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG259]], align 16 // CHECK-NEXT: [[REG265:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG263]], align 16 -// CHECK-NEXT: [[REG266:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpge(double vector[2], double vector[2])(<2 x double> noundef [[REG264]], <2 x double> noundef [[REG265]]) +// CHECK-NEXT: [[REG266:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpge(double vector[2], double vector[2])(<2 x double> [[REG264]], <2 x double> [[REG265]]) // CHECK-NEXT: [[REG267:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG266]] to <2 x double> // CHECK-NEXT: store <2 x double> [[REG267]], <2 x double>* [[REG268:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG269:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG268]], align 16 // CHECK-NEXT: [[REG270:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG269]], i32 0 // CHECK-NEXT: [[REG271:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG254]], align 16 // CHECK-NEXT: [[REG272:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG271]], i32 1 -// CHECK-NEXT: [[REG273:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double noundef [[REG270]], double noundef [[REG272]]) +// CHECK-NEXT: [[REG273:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG270]], double [[REG272]]) // CHECK-NEXT: ret <2 x double> [[REG273]] // CHECK: define available_externally <2 x double> @_mm_cmpgt_pd @@ -476,27 +476,27 @@ test_cmp() { // CHECK-NEXT: [[REG275:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG274]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG275]] -// CHECK: define available_externally <2 x double> @_mm_cmpgt_sd(<2 x double> noundef [[REG276:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG277:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmpgt_sd(<2 x double> [[REG276:[0-9a-zA-Z_%.]+]], <2 x double> [[REG277:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG276]], <2 x double>* [[REG278:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG277]], <2 x double>* [[REG279:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG280:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG278]], align 16 // CHECK-NEXT: [[REG281:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG280]], i32 0 -// CHECK-NEXT: [[REG282:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG281]]) +// CHECK-NEXT: [[REG282:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG281]]) // CHECK-NEXT: store <2 x double> [[REG282]], <2 x double>* [[REG283:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG284:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG279]], align 16 // CHECK-NEXT: [[REG285:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG284]], i32 0 -// CHECK-NEXT: [[REG286:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG285]]) +// CHECK-NEXT: [[REG286:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG285]]) // CHECK-NEXT: store <2 x double> [[REG286]], <2 x double>* [[REG287:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG288:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG283]], align 16 // CHECK-NEXT: [[REG289:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG287]], align 16 -// CHECK-NEXT: [[REG290:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpgt(double vector[2], double vector[2])(<2 x double> noundef [[REG288]], <2 x double> noundef [[REG289]]) +// CHECK-NEXT: [[REG290:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpgt(double vector[2], double vector[2])(<2 x double> [[REG288]], <2 x double> [[REG289]]) // CHECK-NEXT: [[REG291:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG290]] to <2 x double> // CHECK-NEXT: store <2 x double> [[REG291]], <2 x double>* [[REG292:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG293:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG292]], align 16 // CHECK-NEXT: [[REG294:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG293]], i32 0 // CHECK-NEXT: [[REG295:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG278]], align 16 // CHECK-NEXT: [[REG296:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG295]], i32 1 -// CHECK-NEXT: [[REG297:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double noundef [[REG294]], double noundef [[REG296]]) +// CHECK-NEXT: [[REG297:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG294]], double [[REG296]]) // CHECK-NEXT: ret <2 x double> [[REG297]] // CHECK: define available_externally <2 x double> @_mm_cmple_pd @@ -504,27 +504,27 @@ test_cmp() { // CHECK-NEXT: [[REG299:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG298]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG299]] -// CHECK: define available_externally <2 x double> @_mm_cmple_sd(<2 x double> noundef [[REG300:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG301:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmple_sd(<2 x double> [[REG300:[0-9a-zA-Z_%.]+]], <2 x double> [[REG301:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG300]], <2 x double>* [[REG302:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG301]], <2 x double>* [[REG303:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG304:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG302]], align 16 // CHECK-NEXT: [[REG305:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG304]], i32 0 -// CHECK-NEXT: [[REG306:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG305]]) +// CHECK-NEXT: [[REG306:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG305]]) // CHECK-NEXT: store <2 x double> [[REG306]], <2 x double>* [[REG307:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG308:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG303]], align 16 // CHECK-NEXT: [[REG309:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG308]], i32 0 -// CHECK-NEXT: [[REG310:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG309]]) +// CHECK-NEXT: [[REG310:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG309]]) // CHECK-NEXT: store <2 x double> [[REG310]], <2 x double>* [[REG311:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG312:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG307]], align 16 // CHECK-NEXT: [[REG313:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG311]], align 16 -// CHECK-NEXT: [[REG314:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmple(double vector[2], double vector[2])(<2 x double> noundef [[REG312]], <2 x double> noundef [[REG313]]) +// CHECK-NEXT: [[REG314:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmple(double vector[2], double vector[2])(<2 x double> [[REG312]], <2 x double> [[REG313]]) // CHECK-NEXT: [[REG315:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG314]] to <2 x double> // CHECK-NEXT: store <2 x double> [[REG315]], <2 x double>* [[REG316:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG317:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG316]], align 16 // CHECK-NEXT: [[REG318:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG317]], i32 0 // CHECK-NEXT: [[REG319:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG302]], align 16 // CHECK-NEXT: [[REG320:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG319]], i32 1 -// CHECK-NEXT: [[REG321:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double noundef [[REG318]], double noundef [[REG320]]) +// CHECK-NEXT: [[REG321:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG318]], double [[REG320]]) // CHECK-NEXT: ret <2 x double> [[REG321]] // CHECK: define available_externally <2 x double> @_mm_cmplt_pd @@ -532,67 +532,67 @@ test_cmp() { // CHECK-NEXT: [[REG323:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG322]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG323]] -// CHECK: define available_externally <2 x double> @_mm_cmplt_sd(<2 x double> noundef [[REG324:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG325:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmplt_sd(<2 x double> [[REG324:[0-9a-zA-Z_%.]+]], <2 x double> [[REG325:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG324]], <2 x double>* [[REG326:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG325]], <2 x double>* [[REG327:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG328:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG326]], align 16 // CHECK-NEXT: [[REG329:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG328]], i32 0 -// CHECK-NEXT: [[REG330:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG329]]) +// CHECK-NEXT: [[REG330:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG329]]) // CHECK-NEXT: store <2 x double> [[REG330]], <2 x double>* [[REG331:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG332:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG327]], align 16 // CHECK-NEXT: [[REG333:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG332]], i32 0 -// CHECK-NEXT: [[REG334:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG333]]) +// CHECK-NEXT: [[REG334:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG333]]) // CHECK-NEXT: store <2 x double> [[REG334]], <2 x double>* [[REG335:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG336:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG331]], align 16 // CHECK-NEXT: [[REG337:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG335]], align 16 -// CHECK-NEXT: [[REG338:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmplt(double vector[2], double vector[2])(<2 x double> noundef [[REG336]], <2 x double> noundef [[REG337]]) +// CHECK-NEXT: [[REG338:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmplt(double vector[2], double vector[2])(<2 x double> [[REG336]], <2 x double> [[REG337]]) // CHECK-NEXT: [[REG339:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG338]] to <2 x double> // CHECK-NEXT: store <2 x double> [[REG339]], <2 x double>* [[REG340:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG341:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG340]], align 16 // CHECK-NEXT: [[REG342:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG341]], i32 0 // CHECK-NEXT: [[REG343:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG326]], align 16 // CHECK-NEXT: [[REG344:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG343]], i32 1 -// CHECK-NEXT: [[REG345:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double noundef [[REG342]], double noundef [[REG344]]) +// CHECK-NEXT: [[REG345:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG342]], double [[REG344]]) // CHECK-NEXT: ret <2 x double> [[REG345]] -// CHECK: define available_externally <2 x double> @_mm_cmpneq_pd(<2 x double> noundef [[REG346:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG347:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmpneq_pd(<2 x double> [[REG346:[0-9a-zA-Z_%.]+]], <2 x double> [[REG347:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG346]], <2 x double>* [[REG348:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG347]], <2 x double>* [[REG349:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG350:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG348]], align 16 // CHECK-NEXT: [[REG351:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG349]], align 16 -// CHECK-NEXT: [[REG352:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> noundef [[REG350]], <2 x double> noundef [[REG351]]) +// CHECK-NEXT: [[REG352:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> [[REG350]], <2 x double> [[REG351]]) // CHECK-NEXT: [[REG353:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG352]] to <2 x double> // CHECK-NEXT: store <2 x double> [[REG353]], <2 x double>* [[REG354:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG355:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG354]], align 16 // CHECK-NEXT: [[REG356:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG354]], align 16 -// CHECK-NEXT: [[REG357:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_nor(double vector[2], double vector[2])(<2 x double> noundef [[REG355]], <2 x double> noundef [[REG356]]) +// CHECK-NEXT: [[REG357:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_nor(double vector[2], double vector[2])(<2 x double> [[REG355]], <2 x double> [[REG356]]) // CHECK-NEXT: ret <2 x double> [[REG357]] -// CHECK: define available_externally <2 x double> @_mm_cmpneq_sd(<2 x double> noundef [[REG358:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG359:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmpneq_sd(<2 x double> [[REG358:[0-9a-zA-Z_%.]+]], <2 x double> [[REG359:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG358]], <2 x double>* [[REG360:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG359]], <2 x double>* [[REG361:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG362:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG360]], align 16 // CHECK-NEXT: [[REG363:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG362]], i32 0 -// CHECK-NEXT: [[REG364:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG363]]) +// CHECK-NEXT: [[REG364:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG363]]) // CHECK-NEXT: store <2 x double> [[REG364]], <2 x double>* [[REG365:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG366:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG361]], align 16 // CHECK-NEXT: [[REG367:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG366]], i32 0 -// CHECK-NEXT: [[REG368:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG367]]) +// CHECK-NEXT: [[REG368:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG367]]) // CHECK-NEXT: store <2 x double> [[REG368]], <2 x double>* [[REG369:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG370:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG365]], align 16 // CHECK-NEXT: [[REG371:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG369]], align 16 -// CHECK-NEXT: [[REG372:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> noundef [[REG370]], <2 x double> noundef [[REG371]]) +// CHECK-NEXT: [[REG372:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> [[REG370]], <2 x double> [[REG371]]) // CHECK-NEXT: [[REG373:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG372]] to <2 x double> // CHECK-NEXT: store <2 x double> [[REG373]], <2 x double>* [[REG374:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG375:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG374]], align 16 // CHECK-NEXT: [[REG376:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG374]], align 16 -// CHECK-NEXT: [[REG377:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_nor(double vector[2], double vector[2])(<2 x double> noundef [[REG375]], <2 x double> noundef [[REG376]]) +// CHECK-NEXT: [[REG377:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_nor(double vector[2], double vector[2])(<2 x double> [[REG375]], <2 x double> [[REG376]]) // CHECK-NEXT: store <2 x double> [[REG377]], <2 x double>* [[REG374]], align 16 // CHECK-NEXT: [[REG378:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG374]], align 16 // CHECK-NEXT: [[REG379:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG378]], i32 0 // CHECK-NEXT: [[REG380:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG360]], align 16 // CHECK-NEXT: [[REG381:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG380]], i32 1 -// CHECK-NEXT: [[REG382:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double noundef [[REG379]], double noundef [[REG381]]) +// CHECK-NEXT: [[REG382:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG379]], double [[REG381]]) // CHECK-NEXT: ret <2 x double> [[REG382]] // CHECK: define available_externally <2 x double> @_mm_cmpnge_pd @@ -600,59 +600,59 @@ test_cmp() { // CHECK-NEXT: [[REG384:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG383]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG384]] -// CHECK: define available_externally <2 x double> @_mm_cmpnge_sd(<2 x double> noundef [[REG385:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG386:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmpnge_sd(<2 x double> [[REG385:[0-9a-zA-Z_%.]+]], <2 x double> [[REG386:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG385]], <2 x double>* [[REG387:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG386]], <2 x double>* [[REG388:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG389:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG387]], align 16 // CHECK-NEXT: [[REG390:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG389]], i32 0 -// CHECK-NEXT: [[REG391:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG390]]) +// CHECK-NEXT: [[REG391:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG390]]) // CHECK-NEXT: store <2 x double> [[REG391]], <2 x double>* [[REG392:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG393:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG388]], align 16 // CHECK-NEXT: [[REG394:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG393]], i32 0 -// CHECK-NEXT: [[REG395:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG394]]) +// CHECK-NEXT: [[REG395:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG394]]) // CHECK-NEXT: store <2 x double> [[REG395]], <2 x double>* [[REG396:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG397:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG392]], align 16 // CHECK-NEXT: [[REG398:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG396]], align 16 -// CHECK-NEXT: [[REG399:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmplt(double vector[2], double vector[2])(<2 x double> noundef [[REG397]], <2 x double> noundef [[REG398]]) +// CHECK-NEXT: [[REG399:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmplt(double vector[2], double vector[2])(<2 x double> [[REG397]], <2 x double> [[REG398]]) // CHECK-NEXT: [[REG400:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG399]] to <2 x double> // CHECK-NEXT: store <2 x double> [[REG400]], <2 x double>* [[REG401:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG402:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG401]], align 16 // CHECK-NEXT: [[REG403:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG402]], i32 0 // CHECK-NEXT: [[REG404:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG387]], align 16 // CHECK-NEXT: [[REG405:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG404]], i32 1 -// CHECK-NEXT: [[REG406:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double noundef [[REG403]], double noundef [[REG405]]) +// CHECK-NEXT: [[REG406:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG403]], double [[REG405]]) // CHECK-NEXT: ret <2 x double> [[REG406]] -// CHECK: define available_externally <2 x double> @_mm_cmpngt_pd(<2 x double> noundef [[REG407:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG408:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmpngt_pd(<2 x double> [[REG407:[0-9a-zA-Z_%.]+]], <2 x double> [[REG408:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG407]], <2 x double>* [[REG409:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG408]], <2 x double>* [[REG410:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG411:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG409]], align 16 // CHECK-NEXT: [[REG412:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG410]], align 16 -// CHECK-NEXT: [[REG413:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmple(double vector[2], double vector[2])(<2 x double> noundef [[REG411]], <2 x double> noundef [[REG412]]) +// CHECK-NEXT: [[REG413:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmple(double vector[2], double vector[2])(<2 x double> [[REG411]], <2 x double> [[REG412]]) // CHECK-NEXT: [[REG414:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG413]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG414]] -// CHECK: define available_externally <2 x double> @_mm_cmpngt_sd(<2 x double> noundef [[REG415:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG416:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmpngt_sd(<2 x double> [[REG415:[0-9a-zA-Z_%.]+]], <2 x double> [[REG416:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG415]], <2 x double>* [[REG417:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG416]], <2 x double>* [[REG418:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG419:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG417]], align 16 // CHECK-NEXT: [[REG420:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG419]], i32 0 -// CHECK-NEXT: [[REG421:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG420]]) +// CHECK-NEXT: [[REG421:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG420]]) // CHECK-NEXT: store <2 x double> [[REG421]], <2 x double>* [[REG422:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG423:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG418]], align 16 // CHECK-NEXT: [[REG424:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG423]], i32 0 -// CHECK-NEXT: [[REG425:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG424]]) +// CHECK-NEXT: [[REG425:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG424]]) // CHECK-NEXT: store <2 x double> [[REG425]], <2 x double>* [[REG426:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG427:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG422]], align 16 // CHECK-NEXT: [[REG428:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG426]], align 16 -// CHECK-NEXT: [[REG429:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmple(double vector[2], double vector[2])(<2 x double> noundef [[REG427]], <2 x double> noundef [[REG428]]) +// CHECK-NEXT: [[REG429:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmple(double vector[2], double vector[2])(<2 x double> [[REG427]], <2 x double> [[REG428]]) // CHECK-NEXT: [[REG430:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG429]] to <2 x double> // CHECK-NEXT: store <2 x double> [[REG430]], <2 x double>* [[REG431:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG432:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG431]], align 16 // CHECK-NEXT: [[REG433:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG432]], i32 0 // CHECK-NEXT: [[REG434:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG417]], align 16 // CHECK-NEXT: [[REG435:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG434]], i32 1 -// CHECK-NEXT: [[REG436:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double noundef [[REG433]], double noundef [[REG435]]) +// CHECK-NEXT: [[REG436:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG433]], double [[REG435]]) // CHECK-NEXT: ret <2 x double> [[REG436]] // CHECK: define available_externally <2 x double> @_mm_cmpnle_pd @@ -660,27 +660,27 @@ test_cmp() { // CHECK-NEXT: [[REG438:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG437]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG438]] -// CHECK: define available_externally <2 x double> @_mm_cmpnle_sd(<2 x double> noundef [[REG439:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG440:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmpnle_sd(<2 x double> [[REG439:[0-9a-zA-Z_%.]+]], <2 x double> [[REG440:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG439]], <2 x double>* [[REG441:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG440]], <2 x double>* [[REG442:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG443:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG441]], align 16 // CHECK-NEXT: [[REG444:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG443]], i32 0 -// CHECK-NEXT: [[REG445:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG444]]) +// CHECK-NEXT: [[REG445:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG444]]) // CHECK-NEXT: store <2 x double> [[REG445]], <2 x double>* [[REG446:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG447:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG442]], align 16 // CHECK-NEXT: [[REG448:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG447]], i32 0 -// CHECK-NEXT: [[REG449:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG448]]) +// CHECK-NEXT: [[REG449:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG448]]) // CHECK-NEXT: store <2 x double> [[REG449]], <2 x double>* [[REG450:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG451:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG446]], align 16 // CHECK-NEXT: [[REG452:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG450]], align 16 -// CHECK-NEXT: [[REG453:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpge(double vector[2], double vector[2])(<2 x double> noundef [[REG451]], <2 x double> noundef [[REG452]]) +// CHECK-NEXT: [[REG453:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpge(double vector[2], double vector[2])(<2 x double> [[REG451]], <2 x double> [[REG452]]) // CHECK-NEXT: [[REG454:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG453]] to <2 x double> // CHECK-NEXT: store <2 x double> [[REG454]], <2 x double>* [[REG455:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG456:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG455]], align 16 // CHECK-NEXT: [[REG457:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG456]], i32 0 // CHECK-NEXT: [[REG458:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG441]], align 16 // CHECK-NEXT: [[REG459:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG458]], i32 1 -// CHECK-NEXT: [[REG460:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double noundef [[REG457]], double noundef [[REG459]]) +// CHECK-NEXT: [[REG460:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG457]], double [[REG459]]) // CHECK-NEXT: ret <2 x double> [[REG460]] // CHECK: define available_externally <2 x double> @_mm_cmpnlt_pd @@ -688,101 +688,101 @@ test_cmp() { // CHECK-NEXT: [[REG462:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG461]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG462]] -// CHECK: define available_externally <2 x double> @_mm_cmpnlt_sd(<2 x double> noundef [[REG463:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG464:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmpnlt_sd(<2 x double> [[REG463:[0-9a-zA-Z_%.]+]], <2 x double> [[REG464:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG463]], <2 x double>* [[REG465:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG464]], <2 x double>* [[REG466:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG467:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG465]], align 16 // CHECK-NEXT: [[REG468:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG467]], i32 0 -// CHECK-NEXT: [[REG469:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG468]]) +// CHECK-NEXT: [[REG469:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG468]]) // CHECK-NEXT: store <2 x double> [[REG469]], <2 x double>* [[REG470:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG471:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG466]], align 16 // CHECK-NEXT: [[REG472:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG471]], i32 0 -// CHECK-NEXT: [[REG473:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG472]]) +// CHECK-NEXT: [[REG473:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG472]]) // CHECK-NEXT: store <2 x double> [[REG473]], <2 x double>* [[REG474:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG475:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG470]], align 16 // CHECK-NEXT: [[REG476:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG474]], align 16 -// CHECK-NEXT: [[REG477:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpge(double vector[2], double vector[2])(<2 x double> noundef [[REG475]], <2 x double> noundef [[REG476]]) +// CHECK-NEXT: [[REG477:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpge(double vector[2], double vector[2])(<2 x double> [[REG475]], <2 x double> [[REG476]]) // CHECK-NEXT: [[REG478:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG477]] to <2 x double> // CHECK-NEXT: store <2 x double> [[REG478]], <2 x double>* [[REG479:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG480:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG479]], align 16 // CHECK-NEXT: [[REG481:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG480]], i32 0 // CHECK-NEXT: [[REG482:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG465]], align 16 // CHECK-NEXT: [[REG483:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG482]], i32 1 -// CHECK-NEXT: [[REG484:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double noundef [[REG481]], double noundef [[REG483]]) +// CHECK-NEXT: [[REG484:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG481]], double [[REG483]]) // CHECK-NEXT: ret <2 x double> [[REG484]] -// CHECK: define available_externally <2 x double> @_mm_cmpord_pd(<2 x double> noundef [[REG485:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG486:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmpord_pd(<2 x double> [[REG485:[0-9a-zA-Z_%.]+]], <2 x double> [[REG486:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG485]], <2 x double>* [[REG487:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG486]], <2 x double>* [[REG488:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG489:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG487]], align 16 // CHECK-NEXT: [[REG490:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG487]], align 16 -// CHECK-NEXT: [[REG491:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> noundef [[REG489]], <2 x double> noundef [[REG490]]) +// CHECK-NEXT: [[REG491:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> [[REG489]], <2 x double> [[REG490]]) // CHECK-NEXT: store <2 x i64> [[REG491]], <2 x i64>* [[REG492:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG493:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG488]], align 16 // CHECK-NEXT: [[REG494:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG488]], align 16 -// CHECK-NEXT: [[REG495:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> noundef [[REG493]], <2 x double> noundef [[REG494]]) +// CHECK-NEXT: [[REG495:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> [[REG493]], <2 x double> [[REG494]]) // CHECK-NEXT: store <2 x i64> [[REG495]], <2 x i64>* [[REG496:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG497:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG492]], align 16 // CHECK-NEXT: [[REG498:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG496]], align 16 -// CHECK-NEXT: [[REG499:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_and(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> noundef [[REG497]], <2 x i64> noundef [[REG498]]) +// CHECK-NEXT: [[REG499:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_and(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> [[REG497]], <2 x i64> [[REG498]]) // CHECK-NEXT: [[REG500:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG499]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG500]] -// CHECK: define available_externally <2 x double> @_mm_cmpord_sd(<2 x double> noundef [[REG501:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG502:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmpord_sd(<2 x double> [[REG501:[0-9a-zA-Z_%.]+]], <2 x double> [[REG502:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG501]], <2 x double>* [[REG503:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG502]], <2 x double>* [[REG504:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG505:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG503]], align 16 // CHECK-NEXT: [[REG506:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG505]], i32 0 -// CHECK-NEXT: [[REG507:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG506]]) +// CHECK-NEXT: [[REG507:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG506]]) // CHECK-NEXT: [[REG508:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG504]], align 16 // CHECK-NEXT: [[REG509:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG508]], i32 0 -// CHECK-NEXT: [[REG510:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG509]]) -// CHECK-NEXT: [[REG511:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_cmpord_pd(<2 x double> noundef [[REG507]], <2 x double> noundef [[REG510]]) +// CHECK-NEXT: [[REG510:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG509]]) +// CHECK-NEXT: [[REG511:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_cmpord_pd(<2 x double> [[REG507]], <2 x double> [[REG510]]) // CHECK-NEXT: store <2 x double> [[REG511]], <2 x double>* [[REG512:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG513:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG512]], align 16 // CHECK-NEXT: [[REG514:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG513]], i32 0 // CHECK-NEXT: [[REG515:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG503]], align 16 // CHECK-NEXT: [[REG516:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG515]], i32 1 -// CHECK-NEXT: [[REG517:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double noundef [[REG514]], double noundef [[REG516]]) +// CHECK-NEXT: [[REG517:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG514]], double [[REG516]]) // CHECK-NEXT: ret <2 x double> [[REG517]] -// CHECK: define available_externally <2 x double> @_mm_cmpunord_pd(<2 x double> noundef [[REG518:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG519:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmpunord_pd(<2 x double> [[REG518:[0-9a-zA-Z_%.]+]], <2 x double> [[REG519:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG518]], <2 x double>* [[REG520:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG519]], <2 x double>* [[REG521:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG522:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG520]], align 16 // CHECK-NEXT: [[REG523:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG520]], align 16 -// CHECK-NEXT: [[REG524:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> noundef [[REG522]], <2 x double> noundef [[REG523]]) +// CHECK-NEXT: [[REG524:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> [[REG522]], <2 x double> [[REG523]]) // CHECK-NEXT: store <2 x i64> [[REG524]], <2 x i64>* [[REG525:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG526:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG521]], align 16 // CHECK-NEXT: [[REG527:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG521]], align 16 -// CHECK-NEXT: [[REG528:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> noundef [[REG526]], <2 x double> noundef [[REG527]]) +// CHECK-NEXT: [[REG528:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> [[REG526]], <2 x double> [[REG527]]) // CHECK-NEXT: store <2 x i64> [[REG528]], <2 x i64>* [[REG529:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG530:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG525]], align 16 // CHECK-NEXT: [[REG531:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG525]], align 16 -// CHECK-NEXT: [[REG532:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_nor(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> noundef [[REG530]], <2 x i64> noundef [[REG531]]) +// CHECK-NEXT: [[REG532:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_nor(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> [[REG530]], <2 x i64> [[REG531]]) // CHECK-NEXT: store <2 x i64> [[REG532]], <2 x i64>* [[REG525]], align 16 // CHECK-NEXT: [[REG533:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG525]], align 16 // CHECK-NEXT: [[REG534:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG529]], align 16 -// CHECK-NEXT: [[REG535:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_orc(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> noundef [[REG533]], <2 x i64> noundef [[REG534]]) +// CHECK-NEXT: [[REG535:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_orc(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> [[REG533]], <2 x i64> [[REG534]]) // CHECK-NEXT: [[REG536:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG535]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG536]] -// CHECK: define available_externally <2 x double> @_mm_cmpunord_sd(<2 x double> noundef [[REG537:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG538:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cmpunord_sd(<2 x double> [[REG537:[0-9a-zA-Z_%.]+]], <2 x double> [[REG538:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG537]], <2 x double>* [[REG539:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG538]], <2 x double>* [[REG540:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG541:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG539]], align 16 // CHECK-NEXT: [[REG542:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG541]], i32 0 -// CHECK-NEXT: [[REG543:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG542]]) +// CHECK-NEXT: [[REG543:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG542]]) // CHECK-NEXT: [[REG544:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG540]], align 16 // CHECK-NEXT: [[REG545:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG544]], i32 0 -// CHECK-NEXT: [[REG546:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG545]]) -// CHECK-NEXT: [[REG547:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_cmpunord_pd(<2 x double> noundef [[REG543]], <2 x double> noundef [[REG546]]) +// CHECK-NEXT: [[REG546:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG545]]) +// CHECK-NEXT: [[REG547:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_cmpunord_pd(<2 x double> [[REG543]], <2 x double> [[REG546]]) // CHECK-NEXT: store <2 x double> [[REG547]], <2 x double>* [[REG548:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG549:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG548]], align 16 // CHECK-NEXT: [[REG550:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG549]], i32 0 // CHECK-NEXT: [[REG551:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG539]], align 16 // CHECK-NEXT: [[REG552:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG551]], i32 1 -// CHECK-NEXT: [[REG553:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double noundef [[REG550]], double noundef [[REG552]]) +// CHECK-NEXT: [[REG553:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG550]], double [[REG552]]) // CHECK-NEXT: ret <2 x double> [[REG553]] void __attribute__((noinline)) @@ -797,7 +797,7 @@ test_comi() { // CHECK-LABEL: @test_comi -// CHECK: define available_externally signext i32 @_mm_comieq_sd(<2 x double> noundef [[REG554:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG555:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally signext i32 @_mm_comieq_sd(<2 x double> [[REG554:[0-9a-zA-Z_%.]+]], <2 x double> [[REG555:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG554]], <2 x double>* [[REG556:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG555]], <2 x double>* [[REG557:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG558:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG556]], align 16 @@ -843,7 +843,7 @@ test_control() { // CHECK-LABEL: @test_control -// CHECK: define available_externally void @_mm_clflush(i8* noundef [[REG574:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_clflush(i8* [[REG574:[0-9a-zA-Z_%.]+]]) // CHECK: store i8* [[REG574]], i8** [[REG575:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG576:[0-9a-zA-Z_%.]+]] = load i8*, i8** [[REG575]], align 8 // CHECK-NEXT: call void asm sideeffect "dcbf 0,$0", "b,~{memory}"(i8* [[REG576]]) @@ -897,28 +897,28 @@ test_converts() { // CHECK-LABEL: @test_converts -// CHECK: define available_externally <2 x double> @_mm_cvtepi32_pd(<2 x i64> noundef [[REG579:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cvtepi32_pd(<2 x i64> [[REG579:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG579]], <2 x i64>* [[REG580:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG581:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG580]], align 16 // CHECK-NEXT: [[REG582:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG581]] to <4 x i32> -// CHECK-NEXT: [[REG583:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_unpackh(int vector[4])(<4 x i32> noundef [[REG582]]) +// CHECK-NEXT: [[REG583:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_unpackh(int vector[4])(<4 x i32> [[REG582]]) // CHECK-NEXT: store <2 x i64> [[REG583]], <2 x i64>* [[REG584:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG585:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG584]], align 16 // CHECK-NEXT: [[REG586:[0-9a-zA-Z_%.]+]] = sitofp <2 x i64> [[REG585]] to <2 x double> // CHECK-NEXT: [[REG587:[0-9a-zA-Z_%.]+]] = fmul <2 x double> [[REG586]], // CHECK-NEXT: ret <2 x double> [[REG587]] -// CHECK: define available_externally <4 x float> @_mm_cvtepi32_ps(<2 x i64> noundef [[REG588:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_cvtepi32_ps(<2 x i64> [[REG588:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG588]], <2 x i64>* [[REG589:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG590:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG589]], align 16 // CHECK-NEXT: [[REG591:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG590]] to <4 x i32> // CHECK-NEXT: [[REG592:[0-9a-zA-Z_%.]+]] = call <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> [[REG591]], i32 0) // CHECK-NEXT: ret <4 x float> [[REG592]] -// CHECK: define available_externally <2 x i64> @_mm_cvtpd_epi32(<2 x double> noundef [[REG593:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_cvtpd_epi32(<2 x double> [[REG593:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG593]], <2 x double>* [[REG594:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: %[[REG595:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG594]], align 16 -// CHECK-NEXT: [[REG596:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_rint(double vector[2])(<2 x double> noundef %[[REG595:[0-9a-zA-Z_%.]+]]) +// CHECK-NEXT: [[REG596:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_rint(double vector[2])(<2 x double> %[[REG595:[0-9a-zA-Z_%.]+]]) // CHECK-NEXT: store <2 x double> [[REG596]], <2 x double>* [[REG597:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* [[REG598:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG599:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG597]], align 16 @@ -926,26 +926,26 @@ test_converts() { // CHECK-NEXT: store <4 x i32> [[REG600]], <4 x i32>* [[REG601:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG602:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG601]], align 16 // CHECK-NEXT: [[REG603:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG601]], align 16 -// CHECK-NEXT: [[REG604:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mergeo(int vector[4], int vector[4])(<4 x i32> noundef [[REG602]], <4 x i32> noundef [[REG603]]) +// CHECK-NEXT: [[REG604:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mergeo(int vector[4], int vector[4])(<4 x i32> [[REG602]], <4 x i32> [[REG603]]) // CHECK-NEXT: store <4 x i32> [[REG604]], <4 x i32>* [[REG601]], align 16 // CHECK-NEXT: [[REG605:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG601]], align 16 // CHECK-NEXT: [[REG606:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG605]] to <2 x i64> -// CHECK-NEXT: [[REG607:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vpkudum(long long vector[2], long long vector[2])(<2 x i64> noundef [[REG606]], <2 x i64> noundef zeroinitializer) +// CHECK-NEXT: [[REG607:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vpkudum(long long vector[2], long long vector[2])(<2 x i64> [[REG606]], <2 x i64> zeroinitializer) // CHECK-NEXT: store <4 x i32> [[REG607]], <4 x i32>* [[REG608:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG609:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG608]], align 16 // CHECK-NEXT: [[REG610:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG609]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG610]] -// CHECK: define available_externally i64 @_mm_cvtpd_pi32(<2 x double> noundef [[REG611:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_cvtpd_pi32(<2 x double> [[REG611:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG611]], <2 x double>* [[REG612:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG613:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG612]], align 16 -// CHECK-NEXT: [[REG614:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_cvtpd_epi32(<2 x double> noundef [[REG613]]) +// CHECK-NEXT: [[REG614:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_cvtpd_epi32(<2 x double> [[REG613]]) // CHECK-NEXT: store <2 x i64> [[REG614]], <2 x i64>* [[REG615:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG616:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG615]], align 16 // CHECK-NEXT: [[REG617:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG616]], i32 0 // CHECK-NEXT: ret i64 [[REG617]] -// CHECK: define available_externally <4 x float> @_mm_cvtpd_ps(<2 x double> noundef [[REG618:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_cvtpd_ps(<2 x double> [[REG618:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG618]], <2 x double>* [[REG619:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* [[REG620:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: %[[REG621:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG619]], align 16 @@ -953,24 +953,24 @@ test_converts() { // CHECK-NEXT: store <4 x i32> [[REG622]], <4 x i32>* [[REG623:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG624:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG623]], align 16 // CHECK-NEXT: [[REG625:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG623]], align 16 -// CHECK-NEXT: [[REG626:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mergeo(int vector[4], int vector[4])(<4 x i32> noundef [[REG624]], <4 x i32> noundef [[REG625]]) +// CHECK-NEXT: [[REG626:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mergeo(int vector[4], int vector[4])(<4 x i32> [[REG624]], <4 x i32> [[REG625]]) // CHECK-NEXT: store <4 x i32> [[REG626]], <4 x i32>* [[REG623]], align 16 // CHECK-NEXT: [[REG627:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG623]], align 16 // CHECK-NEXT: [[REG628:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG627]] to <2 x i64> -// CHECK-NEXT: [[REG629:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vpkudum(long long vector[2], long long vector[2])(<2 x i64> noundef [[REG628]], <2 x i64> noundef zeroinitializer) +// CHECK-NEXT: [[REG629:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vpkudum(long long vector[2], long long vector[2])(<2 x i64> [[REG628]], <2 x i64> zeroinitializer) // CHECK-NEXT: [[REG630:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG629]] to <4 x float> // CHECK-NEXT: store <4 x float> [[REG630]], <4 x float>* [[REG631:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG632:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG631]], align 16 // CHECK-NEXT: ret <4 x float> [[REG632]] -// CHECK: define available_externally <2 x double> @_mm_cvtpi32_pd(i64 noundef [[REG633:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cvtpi32_pd(i64 [[REG633:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG633]], i64* [[REG634:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG635:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG634]], align 8 -// CHECK-NEXT: [[REG636:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG635]]) +// CHECK-NEXT: [[REG636:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG635]]) // CHECK-NEXT: [[REG637:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG636]] to <4 x i32> // CHECK-NEXT: store <4 x i32> [[REG637]], <4 x i32>* [[REG638:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG639:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG638]], align 16 -// CHECK-NEXT: [[REG640:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_unpackl(int vector[4])(<4 x i32> noundef [[REG639]]) +// CHECK-NEXT: [[REG640:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_unpackl(int vector[4])(<4 x i32> [[REG639]]) // CHECK-NEXT: store <2 x i64> [[REG640]], <2 x i64>* [[REG641:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG642:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG641]], align 16 // CHECK-NEXT: [[REG643:[0-9a-zA-Z_%.]+]] = sitofp <2 x i64> [[REG642]] to <2 x double> @@ -979,10 +979,10 @@ test_converts() { // CHECK-NEXT: [[REG646:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG645]], align 16 // CHECK-NEXT: ret <2 x double> [[REG646]] -// CHECK: define available_externally <2 x i64> @_mm_cvtps_epi32(<4 x float> noundef [[REG647:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_cvtps_epi32(<4 x float> [[REG647:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG647]], <4 x float>* [[REG648:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG649:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG648]], align 16 -// CHECK-NEXT: [[REG650:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_rint(float vector[4])(<4 x float> noundef [[REG649]]) +// CHECK-NEXT: [[REG650:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_rint(float vector[4])(<4 x float> [[REG649]]) // CHECK-NEXT: store <4 x float> [[REG650]], <4 x float>* [[REG651:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG652:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG651]], align 16 // CHECK-NEXT: [[REG653:[0-9a-zA-Z_%.]+]] = call <4 x i32> @llvm.ppc.altivec.vctsxs(<4 x float> [[REG652]], i32 0) @@ -991,14 +991,14 @@ test_converts() { // CHECK-NEXT: [[REG656:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG655]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG656]] -// CHECK: define available_externally <2 x double> @_mm_cvtps_pd(<4 x float> noundef [[REG657:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cvtps_pd(<4 x float> [[REG657:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG657]], <4 x float>* [[REG658:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: %[[REG659:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG658]], align 16 // CHECK-NEXT: store <4 x float> %[[REG659:[0-9a-zA-Z_%.]+]], <4 x float>* [[REG660:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG661:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG660]], align 16 // CHECK-NEXT: [[REG662:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG660]], align 16 -// CHECK-BE-NEXT: [[REG663:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_vmrghw(float vector[4], float vector[4])(<4 x float> noundef [[REG664:[0-9a-zA-Z_%.]+]], <4 x float> noundef [[REG665:[0-9a-zA-Z_%.]+]]) +// CHECK-BE-NEXT: [[REG663:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_vmrghw(float vector[4], float vector[4])(<4 x float> [[REG664:[0-9a-zA-Z_%.]+]], <4 x float> [[REG665:[0-9a-zA-Z_%.]+]]) // CHECK-BE-NEXT: store <4 x float> [[REG663]], <4 x float>* [[REG666:[0-9a-zA-Z_%.]+]], align 16 // CHECK-BE-NEXT: [[REG667:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG666]], align 16 // CHECK-BE-NEXT: [[REG668:[0-9a-zA-Z_%.]+]] = call <2 x double> asm " xvcvspdp ${0:x},${1:x}", "=^wa,^wa"(<4 x float> [[REG667]]) @@ -1024,16 +1024,16 @@ test_converts() { // CHECK-LE-NEXT: [[REG683:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG669]], align 16 // CHECK-LE-NEXT: ret <2 x double> [[REG683]] -// CHECK: define available_externally double @_mm_cvtsd_f64(<2 x double> noundef [[REG684:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally double @_mm_cvtsd_f64(<2 x double> [[REG684:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG684]], <2 x double>* [[REG685:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG686:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG685]], align 16 // CHECK-NEXT: [[REG687:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG686]], i32 0 // CHECK-NEXT: ret double [[REG687]] -// CHECK: define available_externally signext i32 @_mm_cvtsd_si32(<2 x double> noundef [[REG688:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally signext i32 @_mm_cvtsd_si32(<2 x double> [[REG688:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG688]], <2 x double>* [[REG689:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG690:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG689]], align 16 -// CHECK-NEXT: [[REG691:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_rint(double vector[2])(<2 x double> noundef [[REG690]]) +// CHECK-NEXT: [[REG691:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_rint(double vector[2])(<2 x double> [[REG690]]) // CHECK-NEXT: store <2 x double> [[REG691]], <2 x double>* [[REG692:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG693:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG692]], align 16 // CHECK-NEXT: [[REG694:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG693]], i32 0 @@ -1042,10 +1042,10 @@ test_converts() { // CHECK-NEXT: [[REG697:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG696]], align 4 // CHECK-NEXT: ret i32 [[REG697]] -// CHECK: define available_externally i64 @_mm_cvtsd_si64(<2 x double> noundef [[REG698:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_cvtsd_si64(<2 x double> [[REG698:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG698]], <2 x double>* [[REG699:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG700:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG699]], align 16 -// CHECK-NEXT: [[REG701:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_rint(double vector[2])(<2 x double> noundef [[REG700]]) +// CHECK-NEXT: [[REG701:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_rint(double vector[2])(<2 x double> [[REG700]]) // CHECK-NEXT: store <2 x double> [[REG701]], <2 x double>* [[REG702:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG703:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG702]], align 16 // CHECK-NEXT: [[REG704:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG703]], i32 0 @@ -1054,20 +1054,20 @@ test_converts() { // CHECK-NEXT: [[REG707:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG706]], align 8 // CHECK-NEXT: ret i64 [[REG707]] -// CHECK: define available_externally i64 @_mm_cvtsd_si64x(<2 x double> noundef [[REG708:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_cvtsd_si64x(<2 x double> [[REG708:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG708]], <2 x double>* [[REG709:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG710:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG709]], align 16 -// CHECK-NEXT: [[REG711:[0-9a-zA-Z_%.]+]] = call i64 @_mm_cvtsd_si64(<2 x double> noundef [[REG710]]) +// CHECK-NEXT: [[REG711:[0-9a-zA-Z_%.]+]] = call i64 @_mm_cvtsd_si64(<2 x double> [[REG710]]) // CHECK-NEXT: ret i64 [[REG711]] -// CHECK: define available_externally <4 x float> @_mm_cvtsd_ss(<4 x float> noundef [[REG712:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG713:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_cvtsd_ss(<4 x float> [[REG712:[0-9a-zA-Z_%.]+]], <2 x double> [[REG713:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG712]], <4 x float>* [[REG714:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG713]], <2 x double>* [[REG715:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: %[[REG716:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG714]], align 16 // CHECK-NEXT: store <4 x float> %[[REG716:[0-9a-zA-Z_%.]+]], <4 x float>* [[REG717:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG718:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG715]], align 16 -// CHECK-LE-NEXT: [[REG719:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splat(double vector[2], unsigned int)(<2 x double> noundef [[REG718]], i32 noundef zeroext 0) +// CHECK-LE-NEXT: [[REG719:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splat(double vector[2], unsigned int)(<2 x double> [[REG718]], i32 zeroext 0) // CHECK-LE-NEXT: store <2 x double> [[REG719]], <2 x double>* [[REG720:[0-9a-zA-Z_%.]+]], align 16 // CHECK-BE-NEXT: [[REG721:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG718]], i32 0 @@ -1100,26 +1100,26 @@ test_converts() { // CHECK-LE-NEXT: [[REG739:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG717]], align 16 // CHECK-LE-NEXT: ret <4 x float> [[REG739]] -// CHECK: define available_externally signext i32 @_mm_cvtsi128_si32(<2 x i64> noundef [[REG740:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally signext i32 @_mm_cvtsi128_si32(<2 x i64> [[REG740:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG740]], <2 x i64>* [[REG741:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG742:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG741]], align 16 // CHECK-NEXT: [[REG743:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG742]] to <4 x i32> // CHECK-NEXT: [[REG744:[0-9a-zA-Z_%.]+]] = extractelement <4 x i32> [[REG743]], i32 0 // CHECK-NEXT: ret i32 [[REG744]] -// CHECK: define available_externally i64 @_mm_cvtsi128_si64(<2 x i64> noundef [[REG745:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_cvtsi128_si64(<2 x i64> [[REG745:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG745]], <2 x i64>* [[REG746:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG747:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG746]], align 16 // CHECK-NEXT: [[REG748:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG747]], i32 0 // CHECK-NEXT: ret i64 [[REG748]] -// CHECK: define available_externally i64 @_mm_cvtsi128_si64x(<2 x i64> noundef [[REG749:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_cvtsi128_si64x(<2 x i64> [[REG749:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG749]], <2 x i64>* [[REG750:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG751:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG750]], align 16 // CHECK-NEXT: [[REG752:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG751]], i32 0 // CHECK-NEXT: ret i64 [[REG752]] -// CHECK: define available_externally <2 x double> @_mm_cvtsi32_sd(<2 x double> noundef [[REG753:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG754:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cvtsi32_sd(<2 x double> [[REG753:[0-9a-zA-Z_%.]+]], i32 signext [[REG754:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG753]], <2 x double>* [[REG755:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG754]], i32* [[REG756:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG757:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG755]], align 16 @@ -1134,13 +1134,13 @@ test_converts() { // CHECK-NEXT: [[REG765:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG758]], align 16 // CHECK-NEXT: ret <2 x double> [[REG765]] -// CHECK: define available_externally <2 x i64> @_mm_cvtsi32_si128(i32 noundef signext [[REG766:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_cvtsi32_si128(i32 signext [[REG766:[0-9a-zA-Z_%.]+]]) // CHECK: store i32 [[REG766]], i32* [[REG767:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG768:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG767]], align 4 -// CHECK-NEXT: [[REG769:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi32(i32 noundef signext 0, i32 noundef signext 0, i32 noundef signext 0, i32 noundef signext [[REG768]]) +// CHECK-NEXT: [[REG769:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi32(i32 signext 0, i32 signext 0, i32 signext 0, i32 signext [[REG768]]) // CHECK-NEXT: ret <2 x i64> [[REG769]] -// CHECK: define available_externally <2 x double> @_mm_cvtsi64_sd(<2 x double> noundef [[REG770:[0-9a-zA-Z_%.]+]], i64 noundef [[REG771:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cvtsi64_sd(<2 x double> [[REG770:[0-9a-zA-Z_%.]+]], i64 [[REG771:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG770]], <2 x double>* [[REG772:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i64 [[REG771]], i64* [[REG773:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG774:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG772]], align 16 @@ -1155,7 +1155,7 @@ test_converts() { // CHECK-NEXT: [[REG782:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG775]], align 16 // CHECK-NEXT: ret <2 x double> [[REG782]] -// CHECK: define available_externally <2 x i64> @_mm_cvtsi64_si128(i64 noundef [[REG783:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_cvtsi64_si128(i64 [[REG783:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG783]], i64* [[REG784:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG785:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG784]], align 8 // CHECK-NEXT: [[REG786:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG785]], i32 0 @@ -1164,15 +1164,15 @@ test_converts() { // CHECK-NEXT: [[REG789:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG788]], align 16 // CHECK-NEXT: ret <2 x i64> [[REG789]] -// CHECK: define available_externally <2 x double> @_mm_cvtsi64x_sd(<2 x double> noundef [[REG790:[0-9a-zA-Z_%.]+]], i64 noundef [[REG791:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cvtsi64x_sd(<2 x double> [[REG790:[0-9a-zA-Z_%.]+]], i64 [[REG791:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG790]], <2 x double>* [[REG792:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i64 [[REG791]], i64* [[REG793:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG794:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG792]], align 16 // CHECK-NEXT: [[REG795:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG793]], align 8 -// CHECK-NEXT: [[REG796:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_cvtsi64_sd(<2 x double> noundef [[REG794]], i64 noundef [[REG795]]) +// CHECK-NEXT: [[REG796:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_cvtsi64_sd(<2 x double> [[REG794]], i64 [[REG795]]) // CHECK-NEXT: ret <2 x double> [[REG796]] -// CHECK: define available_externally <2 x i64> @_mm_cvtsi64x_si128(i64 noundef [[REG797:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_cvtsi64x_si128(i64 [[REG797:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG797]], i64* [[REG798:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG799:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG798]], align 8 // CHECK-NEXT: [[REG800:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG799]], i32 0 @@ -1181,7 +1181,7 @@ test_converts() { // CHECK-NEXT: [[REG803:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG802]], align 16 // CHECK-NEXT: ret <2 x i64> [[REG803]] -// CHECK: define available_externally <2 x double> @_mm_cvtss_sd(<2 x double> noundef [[REG804:[0-9a-zA-Z_%.]+]], <4 x float> noundef [[REG805:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_cvtss_sd(<2 x double> [[REG804:[0-9a-zA-Z_%.]+]], <4 x float> [[REG805:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG804]], <2 x double>* [[REG806:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x float> [[REG805]], <4 x float>* [[REG807:[0-9a-zA-Z_%.]+]], align 16 @@ -1197,17 +1197,17 @@ test_converts() { // CHECK-BE-NEXT: ret <2 x double> [[REG815]] // CHECK-LE-NEXT: [[REG816:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG807]], align 16 -// CHECK-LE-NEXT: [[REG817:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef [[REG816:[0-9a-zA-Z_%.]+]], i32 noundef zeroext 0) +// CHECK-LE-NEXT: [[REG817:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> [[REG816:[0-9a-zA-Z_%.]+]], i32 zeroext 0) // CHECK-LE-NEXT: store <4 x float> [[REG817]], <4 x float>* [[REG818:[0-9a-zA-Z_%.]+]], align 16 // CHECK-LE-NEXT: [[REG819:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG818]], align 16 // CHECK-LE-NEXT: [[REG820:[0-9a-zA-Z_%.]+]] = call <2 x double> asm "xscvspdp ${0:x},${1:x}", "=^wa,^wa"(<4 x float> [[REG819]]) // CHECK-LE-NEXT: store <2 x double> [[REG820]], <2 x double>* [[REG809:[0-9a-zA-Z_%.]+]], align 16 // CHECK-LE-NEXT: [[REG821:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG809]], align 16 // CHECK-LE-NEXT: [[REG822:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG806]], align 16 -// CHECK-LE-NEXT: [[REG823:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_mergel(double vector[2], double vector[2])(<2 x double> noundef [[REG821]], <2 x double> noundef [[REG822]]) +// CHECK-LE-NEXT: [[REG823:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_mergel(double vector[2], double vector[2])(<2 x double> [[REG821]], <2 x double> [[REG822]]) // CHECK-LE-NEXT: ret <2 x double> [[REG823]] -// CHECK: define available_externally <2 x i64> @_mm_cvttpd_epi32(<2 x double> noundef [[REG824:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_cvttpd_epi32(<2 x double> [[REG824:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG824]], <2 x double>* [[REG825:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* [[REG826:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: %[[REG827:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG825]], align 16 @@ -1215,26 +1215,26 @@ test_converts() { // CHECK-NEXT: store <4 x i32> [[REG828]], <4 x i32>* [[REG829:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG830:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG829]], align 16 // CHECK-NEXT: [[REG831:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG829]], align 16 -// CHECK-NEXT: [[REG832:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mergeo(int vector[4], int vector[4])(<4 x i32> noundef [[REG830]], <4 x i32> noundef [[REG831]]) +// CHECK-NEXT: [[REG832:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mergeo(int vector[4], int vector[4])(<4 x i32> [[REG830]], <4 x i32> [[REG831]]) // CHECK-NEXT: store <4 x i32> [[REG832]], <4 x i32>* [[REG829]], align 16 // CHECK-NEXT: [[REG833:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG829]], align 16 // CHECK-NEXT: [[REG834:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG833]] to <2 x i64> -// CHECK-NEXT: [[REG835:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vpkudum(long long vector[2], long long vector[2])(<2 x i64> noundef [[REG834]], <2 x i64> noundef zeroinitializer) +// CHECK-NEXT: [[REG835:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vpkudum(long long vector[2], long long vector[2])(<2 x i64> [[REG834]], <2 x i64> zeroinitializer) // CHECK-NEXT: store <4 x i32> [[REG835]], <4 x i32>* [[REG836:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG837:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG836]], align 16 // CHECK-NEXT: [[REG838:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG837]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG838]] -// CHECK: define available_externally i64 @_mm_cvttpd_pi32(<2 x double> noundef [[REG839:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_cvttpd_pi32(<2 x double> [[REG839:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG839]], <2 x double>* [[REG840:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG841:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG840]], align 16 -// CHECK-NEXT: [[REG842:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_cvttpd_epi32(<2 x double> noundef [[REG841]]) +// CHECK-NEXT: [[REG842:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_cvttpd_epi32(<2 x double> [[REG841]]) // CHECK-NEXT: store <2 x i64> [[REG842]], <2 x i64>* [[REG843:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG844:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG843]], align 16 // CHECK-NEXT: [[REG845:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG844]], i32 0 // CHECK-NEXT: ret i64 [[REG845]] -// CHECK: define available_externally <2 x i64> @_mm_cvttps_epi32(<4 x float> noundef [[REG846:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_cvttps_epi32(<4 x float> [[REG846:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG846]], <4 x float>* [[REG847:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG848:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG847]], align 16 // CHECK-NEXT: [[REG849:[0-9a-zA-Z_%.]+]] = call <4 x i32> @llvm.ppc.altivec.vctsxs(<4 x float> [[REG848]], i32 0) @@ -1243,7 +1243,7 @@ test_converts() { // CHECK-NEXT: [[REG852:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG851]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG852]] -// CHECK: define available_externally signext i32 @_mm_cvttsd_si32(<2 x double> noundef [[REG853:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally signext i32 @_mm_cvttsd_si32(<2 x double> [[REG853:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG853]], <2 x double>* [[REG854:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG855:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG854]], align 16 // CHECK-NEXT: [[REG856:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG855]], i32 0 @@ -1252,7 +1252,7 @@ test_converts() { // CHECK-NEXT: [[REG859:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG858]], align 4 // CHECK-NEXT: ret i32 [[REG859]] -// CHECK: define available_externally i64 @_mm_cvttsd_si64(<2 x double> noundef [[REG860:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_cvttsd_si64(<2 x double> [[REG860:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG860]], <2 x double>* [[REG861:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG862:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG861]], align 16 // CHECK-NEXT: [[REG863:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG862]], i32 0 @@ -1261,10 +1261,10 @@ test_converts() { // CHECK-NEXT: [[REG866:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG865]], align 8 // CHECK-NEXT: ret i64 [[REG866]] -// CHECK: define available_externally i64 @_mm_cvttsd_si64x(<2 x double> noundef [[REG867:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_cvttsd_si64x(<2 x double> [[REG867:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG867]], <2 x double>* [[REG868:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG869:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG868]], align 16 -// CHECK-NEXT: [[REG870:[0-9a-zA-Z_%.]+]] = call i64 @_mm_cvttsd_si64(<2 x double> noundef [[REG869]]) +// CHECK-NEXT: [[REG870:[0-9a-zA-Z_%.]+]] = call i64 @_mm_cvttsd_si64(<2 x double> [[REG869]]) // CHECK-NEXT: ret i64 [[REG870]] void __attribute__((noinline)) @@ -1275,7 +1275,7 @@ test_div() { // CHECK-LABEL: @test_div -// CHECK: define available_externally <2 x double> @_mm_div_pd(<2 x double> noundef [[REG871:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG872:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_div_pd(<2 x double> [[REG871:[0-9a-zA-Z_%.]+]], <2 x double> [[REG872:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG871]], <2 x double>* [[REG873:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG872]], <2 x double>* [[REG874:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG875:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG873]], align 16 @@ -1283,7 +1283,7 @@ test_div() { // CHECK-NEXT: [[REG877:[0-9a-zA-Z_%.]+]] = fdiv <2 x double> [[REG875]], [[REG876]] // CHECK-NEXT: ret <2 x double> [[REG877]] -// CHECK: define available_externally <2 x double> @_mm_div_sd(<2 x double> noundef [[REG878:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG879:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_div_sd(<2 x double> [[REG878:[0-9a-zA-Z_%.]+]], <2 x double> [[REG879:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG878]], <2 x double>* [[REG880:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG879]], <2 x double>* [[REG881:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG882:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG880]], align 16 @@ -1304,7 +1304,7 @@ test_extract() { // CHECK-LABEL: @test_extract -// CHECK: define available_externally signext i32 @_mm_extract_epi16(<2 x i64> noundef [[REG890:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG891:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally signext i32 @_mm_extract_epi16(<2 x i64> [[REG890:[0-9a-zA-Z_%.]+]], i32 signext [[REG891:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG890]], <2 x i64>* [[REG892:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG891]], i32* [[REG893:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG894:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG892]], align 16 @@ -1322,7 +1322,7 @@ test_insert() { // CHECK-LABEL: @test_insert -// CHECK: define available_externally <2 x i64> @_mm_insert_epi16(<2 x i64> noundef [[REG900:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG901:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG902:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_insert_epi16(<2 x i64> [[REG900:[0-9a-zA-Z_%.]+]], i32 signext [[REG901:[0-9a-zA-Z_%.]+]], i32 signext [[REG902:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG900]], <2 x i64>* [[REG903:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG901]], i32* [[REG904:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store i32 [[REG902]], i32* [[REG905:[0-9a-zA-Z_%.]+]], align 4 @@ -1357,41 +1357,41 @@ test_load() { // CHECK-LABEL: @test_load -// CHECK: define available_externally <2 x double> @_mm_load_pd(double* noundef [[REG917:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_load_pd(double* [[REG917:[0-9a-zA-Z_%.]+]]) // CHECK: store double* [[REG917]], double** [[REG918:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG919:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG918]], align 8 // CHECK-NEXT: [[REG920:[0-9a-zA-Z_%.]+]] = bitcast double* [[REG919]] to <16 x i8>* -// CHECK-NEXT: [[REG921:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_ld(long, unsigned char vector[16] const*)(i64 noundef 0, <16 x i8>* noundef [[REG920]]) +// CHECK-NEXT: [[REG921:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_ld(long, unsigned char vector[16] const*)(i64 0, <16 x i8>* [[REG920]]) // CHECK-NEXT: [[REG922:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG921]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG922]] -// CHECK: define available_externally <2 x double> @_mm_load_pd1(double* noundef [[REG923:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_load_pd1(double* [[REG923:[0-9a-zA-Z_%.]+]]) // CHECK: store double* [[REG923]], double** [[REG924:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG925:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG924]], align 8 -// CHECK-NEXT: [[REG926:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_load1_pd(double* noundef [[REG925]]) +// CHECK-NEXT: [[REG926:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_load1_pd(double* [[REG925]]) // CHECK-NEXT: ret <2 x double> [[REG926]] -// CHECK: define available_externally <2 x double> @_mm_load_sd(double* noundef [[REG927:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_load_sd(double* [[REG927:[0-9a-zA-Z_%.]+]]) // CHECK: store double* [[REG927]], double** [[REG928:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG929:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG928]], align 8 // CHECK-NEXT: [[REG930:[0-9a-zA-Z_%.]+]] = load double, double* [[REG929]], align 8 -// CHECK-NEXT: [[REG931:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_set_sd(double noundef [[REG930]]) +// CHECK-NEXT: [[REG931:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_set_sd(double [[REG930]]) // CHECK-NEXT: ret <2 x double> [[REG931]] -// CHECK: define available_externally <2 x i64> @_mm_load_si128(<2 x i64>* noundef [[REG932:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_load_si128(<2 x i64>* [[REG932:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64>* [[REG932]], <2 x i64>** [[REG933:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG934:[0-9a-zA-Z_%.]+]] = load <2 x i64>*, <2 x i64>** [[REG933]], align 8 // CHECK-NEXT: [[REG935:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG934]], align 16 // CHECK-NEXT: ret <2 x i64> [[REG935]] -// CHECK: define available_externally <2 x double> @_mm_load1_pd(double* noundef [[REG936:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_load1_pd(double* [[REG936:[0-9a-zA-Z_%.]+]]) // CHECK: store double* [[REG936]], double** [[REG937:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG938:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG937]], align 8 // CHECK-NEXT: [[REG939:[0-9a-zA-Z_%.]+]] = load double, double* [[REG938]], align 8 -// CHECK-NEXT: [[REG940:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG939]]) +// CHECK-NEXT: [[REG940:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG939]]) // CHECK-NEXT: ret <2 x double> [[REG940]] -// CHECK: define available_externally <2 x double> @_mm_loadh_pd(<2 x double> noundef [[REG941:[0-9a-zA-Z_%.]+]], double* noundef [[REG942:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_loadh_pd(<2 x double> [[REG941:[0-9a-zA-Z_%.]+]], double* [[REG942:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG941]], <2 x double>* [[REG943:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store double* [[REG942]], double** [[REG944:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG945:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG943]], align 16 @@ -1404,15 +1404,15 @@ test_load() { // CHECK-NEXT: [[REG951:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG946]], align 16 // CHECK-NEXT: ret <2 x double> [[REG951]] -// CHECK: define available_externally <2 x i64> @_mm_loadl_epi64(<2 x i64>* noundef [[REG952:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_loadl_epi64(<2 x i64>* [[REG952:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64>* [[REG952]], <2 x i64>** [[REG953:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG954:[0-9a-zA-Z_%.]+]] = load <2 x i64>*, <2 x i64>** [[REG953]], align 8 // CHECK-NEXT: [[REG955:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64>* [[REG954]] to i64* // CHECK-NEXT: [[REG956:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG955]], align 8 -// CHECK-NEXT: [[REG957:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi64(i64 noundef 0, i64 noundef [[REG956]]) +// CHECK-NEXT: [[REG957:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi64(i64 0, i64 [[REG956]]) // CHECK-NEXT: ret <2 x i64> [[REG957]] -// CHECK: define available_externally <2 x double> @_mm_loadl_pd(<2 x double> noundef [[REG958:[0-9a-zA-Z_%.]+]], double* noundef [[REG959:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_loadl_pd(<2 x double> [[REG958:[0-9a-zA-Z_%.]+]], double* [[REG959:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG958]], <2 x double>* [[REG960:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store double* [[REG959]], double** [[REG961:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG962:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG960]], align 16 @@ -1425,10 +1425,10 @@ test_load() { // CHECK-NEXT: [[REG968:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG963]], align 16 // CHECK-NEXT: ret <2 x double> [[REG968]] -// CHECK: define available_externally <2 x double> @_mm_loadr_pd(double* noundef [[REG969:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_loadr_pd(double* [[REG969:[0-9a-zA-Z_%.]+]]) // CHECK: store double* [[REG969]], double** [[REG970:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG971:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG970]], align 8 -// CHECK-NEXT: [[REG972:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_load_pd(double* noundef [[REG971]]) +// CHECK-NEXT: [[REG972:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_load_pd(double* [[REG971]]) // CHECK-NEXT: store <2 x double> [[REG972]], <2 x double>* [[REG973:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG974:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG973]], align 16 // CHECK-NEXT: [[REG975:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG973]], align 16 @@ -1438,17 +1438,17 @@ test_load() { // CHECK-NEXT: [[REG979:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG978]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG979]] -// CHECK: define available_externally <2 x double> @_mm_loadu_pd(double* noundef [[REG980:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_loadu_pd(double* [[REG980:[0-9a-zA-Z_%.]+]]) // CHECK: store double* [[REG980]], double** [[REG981:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG982:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG981]], align 8 -// CHECK-NEXT: [[REG983:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_vsx_ld(int, double const*)(i32 noundef signext 0, double* noundef [[REG982]]) +// CHECK-NEXT: [[REG983:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_vsx_ld(int, double const*)(i32 signext 0, double* [[REG982]]) // CHECK-NEXT: ret <2 x double> [[REG983]] -// CHECK: define available_externally <2 x i64> @_mm_loadu_si128(<2 x i64>* noundef [[REG984:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_loadu_si128(<2 x i64>* [[REG984:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64>* [[REG984]], <2 x i64>** [[REG985:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG986:[0-9a-zA-Z_%.]+]] = load <2 x i64>*, <2 x i64>** [[REG985]], align 8 // CHECK-NEXT: [[REG987:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64>* [[REG986]] to i32* -// CHECK-NEXT: [[REG988:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vsx_ld(int, int const*)(i32 noundef signext 0, i32* noundef [[REG987]]) +// CHECK-NEXT: [[REG988:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vsx_ld(int, int const*)(i32 signext 0, i32* [[REG987]]) // CHECK-NEXT: [[REG989:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG988]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG989]] @@ -1466,68 +1466,68 @@ test_logical() { // CHECK-LABEL: @test_logical -// CHECK: define available_externally <2 x double> @_mm_and_pd(<2 x double> noundef [[REG990:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG991:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_and_pd(<2 x double> [[REG990:[0-9a-zA-Z_%.]+]], <2 x double> [[REG991:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG990]], <2 x double>* [[REG992:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG991]], <2 x double>* [[REG993:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG994:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG992]], align 16 // CHECK-NEXT: [[REG995:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG993]], align 16 -// CHECK-NEXT: [[REG996:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_and(double vector[2], double vector[2])(<2 x double> noundef [[REG994]], <2 x double> noundef [[REG995]]) +// CHECK-NEXT: [[REG996:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_and(double vector[2], double vector[2])(<2 x double> [[REG994]], <2 x double> [[REG995]]) // CHECK-NEXT: ret <2 x double> [[REG996]] -// CHECK: define available_externally <2 x i64> @_mm_and_si128(<2 x i64> noundef [[REG997:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG998:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_and_si128(<2 x i64> [[REG997:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG998:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG997]], <2 x i64>* [[REG999:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG998]], <2 x i64>* [[REG1000:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1001:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG999]], align 16 // CHECK-NEXT: [[REG1002:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1000]], align 16 -// CHECK-NEXT: [[REG1003:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_and(long long vector[2], long long vector[2])(<2 x i64> noundef [[REG1001]], <2 x i64> noundef [[REG1002]]) +// CHECK-NEXT: [[REG1003:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_and(long long vector[2], long long vector[2])(<2 x i64> [[REG1001]], <2 x i64> [[REG1002]]) // CHECK-NEXT: ret <2 x i64> [[REG1003]] -// CHECK: define available_externally <2 x double> @_mm_andnot_pd(<2 x double> noundef [[REG1004:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1005:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_andnot_pd(<2 x double> [[REG1004:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1005:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG1004]], <2 x double>* [[REG1006:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG1005]], <2 x double>* [[REG1007:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1008:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1007]], align 16 // CHECK-NEXT: [[REG1009:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1006]], align 16 -// CHECK-NEXT: [[REG1010:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_andc(double vector[2], double vector[2])(<2 x double> noundef [[REG1008]], <2 x double> noundef [[REG1009]]) +// CHECK-NEXT: [[REG1010:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_andc(double vector[2], double vector[2])(<2 x double> [[REG1008]], <2 x double> [[REG1009]]) // CHECK-NEXT: ret <2 x double> [[REG1010]] -// CHECK: define available_externally <2 x i64> @_mm_andnot_si128(<2 x i64> noundef [[REG1011:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1012:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_andnot_si128(<2 x i64> [[REG1011:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1012:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1011]], <2 x i64>* [[REG1013:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG1012]], <2 x i64>* [[REG1014:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1015:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1014]], align 16 // CHECK-NEXT: [[REG1016:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1013]], align 16 -// CHECK-NEXT: [[REG1017:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_andc(long long vector[2], long long vector[2])(<2 x i64> noundef [[REG1015]], <2 x i64> noundef [[REG1016]]) +// CHECK-NEXT: [[REG1017:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_andc(long long vector[2], long long vector[2])(<2 x i64> [[REG1015]], <2 x i64> [[REG1016]]) // CHECK-NEXT: ret <2 x i64> [[REG1017]] -// CHECK: define available_externally <2 x double> @_mm_xor_pd(<2 x double> noundef [[REG1018:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1019:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_xor_pd(<2 x double> [[REG1018:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1019:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG1018]], <2 x double>* [[REG1020:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG1019]], <2 x double>* [[REG1021:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1022:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1020]], align 16 // CHECK-NEXT: [[REG1023:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1021]], align 16 -// CHECK-NEXT: [[REG1024:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_xor(double vector[2], double vector[2])(<2 x double> noundef [[REG1022]], <2 x double> noundef [[REG1023]]) +// CHECK-NEXT: [[REG1024:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_xor(double vector[2], double vector[2])(<2 x double> [[REG1022]], <2 x double> [[REG1023]]) // CHECK-NEXT: ret <2 x double> [[REG1024]] -// CHECK: define available_externally <2 x i64> @_mm_xor_si128(<2 x i64> noundef [[REG1025:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1026:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_xor_si128(<2 x i64> [[REG1025:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1026:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1025]], <2 x i64>* [[REG1027:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG1026]], <2 x i64>* [[REG1028:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1029:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1027]], align 16 // CHECK-NEXT: [[REG1030:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1028]], align 16 -// CHECK-NEXT: [[REG1031:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_xor(long long vector[2], long long vector[2])(<2 x i64> noundef [[REG1029]], <2 x i64> noundef [[REG1030]]) +// CHECK-NEXT: [[REG1031:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_xor(long long vector[2], long long vector[2])(<2 x i64> [[REG1029]], <2 x i64> [[REG1030]]) // CHECK-NEXT: ret <2 x i64> [[REG1031]] -// CHECK: define available_externally <2 x double> @_mm_or_pd(<2 x double> noundef [[REG1032:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1033:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_or_pd(<2 x double> [[REG1032:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1033:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG1032]], <2 x double>* [[REG1034:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG1033]], <2 x double>* [[REG1035:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1036:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1034]], align 16 // CHECK-NEXT: [[REG1037:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1035]], align 16 -// CHECK-NEXT: [[REG1038:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_or(double vector[2], double vector[2])(<2 x double> noundef [[REG1036]], <2 x double> noundef [[REG1037]]) +// CHECK-NEXT: [[REG1038:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_or(double vector[2], double vector[2])(<2 x double> [[REG1036]], <2 x double> [[REG1037]]) // CHECK-NEXT: ret <2 x double> [[REG1038]] -// CHECK: define available_externally <2 x i64> @_mm_or_si128(<2 x i64> noundef [[REG1039:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1040:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_or_si128(<2 x i64> [[REG1039:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1040:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1039]], <2 x i64>* [[REG1041:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG1040]], <2 x i64>* [[REG1042:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1043:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1041]], align 16 // CHECK-NEXT: [[REG1044:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1042]], align 16 -// CHECK-NEXT: [[REG1045:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_or(long long vector[2], long long vector[2])(<2 x i64> noundef [[REG1043]], <2 x i64> noundef [[REG1044]]) +// CHECK-NEXT: [[REG1045:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_or(long long vector[2], long long vector[2])(<2 x i64> [[REG1043]], <2 x i64> [[REG1044]]) // CHECK-NEXT: ret <2 x i64> [[REG1045]] void __attribute__((noinline)) @@ -1554,26 +1554,26 @@ test_max() { // CHECK: [[REG1050:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_max(double vector[2], double vector[2]) // CHECK-NEXT: ret <2 x double> [[REG1050]] -// CHECK: define available_externally <2 x double> @_mm_max_sd(<2 x double> noundef [[REG1051:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1052:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_max_sd(<2 x double> [[REG1051:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1052:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG1051]], <2 x double>* [[REG1053:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG1052]], <2 x double>* [[REG1054:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1055:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1053]], align 16 // CHECK-NEXT: [[REG1056:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1055]], i32 0 -// CHECK-NEXT: [[REG1057:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG1056]]) +// CHECK-NEXT: [[REG1057:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG1056]]) // CHECK-NEXT: store <2 x double> [[REG1057]], <2 x double>* [[REG1058:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1059:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1054]], align 16 // CHECK-NEXT: [[REG1060:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1059]], i32 0 -// CHECK-NEXT: [[REG1061:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG1060]]) +// CHECK-NEXT: [[REG1061:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG1060]]) // CHECK-NEXT: store <2 x double> [[REG1061]], <2 x double>* [[REG1062:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1063:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1058]], align 16 // CHECK-NEXT: [[REG1064:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1062]], align 16 -// CHECK-NEXT: [[REG1065:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_max(double vector[2], double vector[2])(<2 x double> noundef [[REG1063]], <2 x double> noundef [[REG1064]]) +// CHECK-NEXT: [[REG1065:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_max(double vector[2], double vector[2])(<2 x double> [[REG1063]], <2 x double> [[REG1064]]) // CHECK-NEXT: store <2 x double> [[REG1065]], <2 x double>* [[REG1066:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1067:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1066]], align 16 // CHECK-NEXT: [[REG1068:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1067]], i32 0 // CHECK-NEXT: [[REG1069:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1053]], align 16 // CHECK-NEXT: [[REG1070:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1069]], i32 1 -// CHECK-NEXT: [[REG1071:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double noundef [[REG1068]], double noundef [[REG1070]]) +// CHECK-NEXT: [[REG1071:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG1068]], double [[REG1070]]) // CHECK-NEXT: ret <2 x double> [[REG1071]] void __attribute__((noinline)) @@ -1600,26 +1600,26 @@ test_min() { // CHECK: [[REG1076:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_min(double vector[2], double vector[2]) // CHECK-NEXT: ret <2 x double> [[REG1076]] -// CHECK: define available_externally <2 x double> @_mm_min_sd(<2 x double> noundef [[REG1077:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1078:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_min_sd(<2 x double> [[REG1077:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1078:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG1077]], <2 x double>* [[REG1079:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG1078]], <2 x double>* [[REG1080:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1081:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1079]], align 16 // CHECK-NEXT: [[REG1082:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1081]], i32 0 -// CHECK-NEXT: [[REG1083:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG1082]]) +// CHECK-NEXT: [[REG1083:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG1082]]) // CHECK-NEXT: store <2 x double> [[REG1083]], <2 x double>* [[REG1084:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1085:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1080]], align 16 // CHECK-NEXT: [[REG1086:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1085]], i32 0 -// CHECK-NEXT: [[REG1087:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double noundef [[REG1086]]) +// CHECK-NEXT: [[REG1087:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG1086]]) // CHECK-NEXT: store <2 x double> [[REG1087]], <2 x double>* [[REG1088:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1089:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1084]], align 16 // CHECK-NEXT: [[REG1090:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1088]], align 16 -// CHECK-NEXT: [[REG1091:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_min(double vector[2], double vector[2])(<2 x double> noundef [[REG1089]], <2 x double> noundef [[REG1090]]) +// CHECK-NEXT: [[REG1091:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_min(double vector[2], double vector[2])(<2 x double> [[REG1089]], <2 x double> [[REG1090]]) // CHECK-NEXT: store <2 x double> [[REG1091]], <2 x double>* [[REG1092:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1093:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1092]], align 16 // CHECK-NEXT: [[REG1094:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1093]], i32 0 // CHECK-NEXT: [[REG1095:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1079]], align 16 // CHECK-NEXT: [[REG1096:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1095]], i32 1 -// CHECK-NEXT: [[REG1097:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double noundef [[REG1094]], double noundef [[REG1096]]) +// CHECK-NEXT: [[REG1097:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG1094]], double [[REG1096]]) // CHECK-NEXT: ret <2 x double> [[REG1097]] void __attribute__((noinline)) @@ -1635,14 +1635,14 @@ test_move() { // CHECK-LABEL: @test_move -// CHECK: define available_externally <2 x i64> @_mm_move_epi64(<2 x i64> noundef [[REG1098:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_move_epi64(<2 x i64> [[REG1098:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1098]], <2 x i64>* [[REG1099:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1100:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1099]], align 16 // CHECK-NEXT: [[REG1101:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG1100]], i32 0 -// CHECK-NEXT: [[REG1102:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi64(i64 noundef 0, i64 noundef [[REG1101]]) +// CHECK-NEXT: [[REG1102:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi64(i64 0, i64 [[REG1101]]) // CHECK-NEXT: ret <2 x i64> [[REG1102]] -// CHECK: define available_externally <2 x double> @_mm_move_sd(<2 x double> noundef [[REG1103:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1104:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_move_sd(<2 x double> [[REG1103:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1104:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG1103]], <2 x double>* [[REG1105:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG1104]], <2 x double>* [[REG1106:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1107:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1105]], align 16 @@ -1655,11 +1655,11 @@ test_move() { // CHECK-NEXT: [[REG1113:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1108]], align 16 // CHECK-NEXT: ret <2 x double> [[REG1113]] -// CHECK: define available_externally signext i32 @_mm_movemask_epi8(<2 x i64> noundef [[REG1114:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally signext i32 @_mm_movemask_epi8(<2 x i64> [[REG1114:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1114]], <2 x i64>* [[REG1115:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1116:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1115]], align 16 // CHECK-NEXT: [[REG1117:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1116]] to <16 x i8> -// CHECK-NEXT: [[REG1118:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG1117]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG1118:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG1117]], <16 x i8> ) // CHECK-NEXT: store <2 x i64> [[REG1118]], <2 x i64>* [[REG1119:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1120:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1119]], align 16 // CHECK-LE-NEXT: [[REG1121:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG1120]], i32 1 @@ -1667,12 +1667,12 @@ test_move() { // CHECK-NEXT: [[REG1122:[0-9a-zA-Z_%.]+]] = trunc i64 [[REG1121]] to i32 // CHECK-NEXT: ret i32 [[REG1122]] -// CHECK: define available_externally signext i32 @_mm_movemask_pd(<2 x double> noundef [[REG1123:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally signext i32 @_mm_movemask_pd(<2 x double> [[REG1123:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG1123]], <2 x double>* [[REG1124:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1125:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1124]], align 16 // CHECK-NEXT: [[REG1126:[0-9a-zA-Z_%.]+]] = bitcast <2 x double> [[REG1125]] to <16 x i8> -// CHECK-LE-NEXT: [[REG1127:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG1126]], <16 x i8> noundef bitcast (<4 x i32> to <16 x i8>)) -// CHECK-BE-NEXT: [[REG1127:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG1126]], <16 x i8> noundef bitcast (<4 x i32> to <16 x i8>)) +// CHECK-LE-NEXT: [[REG1127:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG1126]], <16 x i8> bitcast (<4 x i32> to <16 x i8>)) +// CHECK-BE-NEXT: [[REG1127:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG1126]], <16 x i8> bitcast (<4 x i32> to <16 x i8>)) // CHECK-NEXT: store <2 x i64> [[REG1127]], <2 x i64>* [[REG1128:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1129:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1128]], align 16 // CHECK-LE-NEXT: [[REG1130:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG1129]], i32 1 @@ -1680,19 +1680,19 @@ test_move() { // CHECK-NEXT: [[REG1131:[0-9a-zA-Z_%.]+]] = trunc i64 [[REG1130]] to i32 // CHECK-NEXT: ret i32 [[REG1131]] -// CHECK: define available_externally i64 @_mm_movepi64_pi64(<2 x i64> noundef [[REG1132:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_movepi64_pi64(<2 x i64> [[REG1132:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1132]], <2 x i64>* [[REG1133:[0-9a-zA-Z_%.]+]], align 1 // CHECK-NEXT: [[REG1134:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1133]], align 1 // CHECK-NEXT: [[REG1135:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG1134]], i32 0 // CHECK-NEXT: ret i64 [[REG1135]] -// CHECK: define available_externally <2 x i64> @_mm_movpi64_epi64(i64 noundef [[REG1136:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_movpi64_epi64(i64 [[REG1136:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG1136]], i64* [[REG1137:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG1138:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG1137]], align 8 -// CHECK-NEXT: [[REG1139:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi64(i64 noundef 0, i64 noundef [[REG1138]]) +// CHECK-NEXT: [[REG1139:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi64(i64 0, i64 [[REG1138]]) // CHECK-NEXT: ret <2 x i64> [[REG1139]] -// CHECK: define available_externally void @_mm_maskmoveu_si128(<2 x i64> noundef [[REG1140:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1141:[0-9a-zA-Z_%.]+]], i8* noundef [[REG1142:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_maskmoveu_si128(<2 x i64> [[REG1140:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1141:[0-9a-zA-Z_%.]+]], i8* [[REG1142:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1140]], <2 x i64>* [[REG1143:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG1141]], <2 x i64>* [[REG1144:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i8* [[REG1142]], i8** [[REG1145:[0-9a-zA-Z_%.]+]], align 8 @@ -1701,25 +1701,25 @@ test_move() { // CHECK-NEXT: [[REG1148:[0-9a-zA-Z_%.]+]] = bitcast i8* [[REG1147]] to <2 x i64>* // CHECK-NEXT: store <2 x i64>* [[REG1148]], <2 x i64>** [[REG1149:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG1150:[0-9a-zA-Z_%.]+]] = load <2 x i64>*, <2 x i64>** [[REG1149]], align 8 -// CHECK-NEXT: [[REG1151:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_loadu_si128(<2 x i64>* noundef [[REG1150]]) +// CHECK-NEXT: [[REG1151:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_loadu_si128(<2 x i64>* [[REG1150]]) // CHECK-NEXT: [[REG1152:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1151]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG1152]], <16 x i8>* [[REG1153:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1154:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1144]], align 16 // CHECK-NEXT: [[REG1155:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1154]] to <16 x i8> // CHECK-NEXT: [[REG1156:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1146]], align 16 // CHECK-NEXT: [[REG1157:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1156]] to <16 x i8> -// CHECK-NEXT: [[REG1158:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmpgt(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG1155]], <16 x i8> noundef [[REG1157]]) +// CHECK-NEXT: [[REG1158:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmpgt(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG1155]], <16 x i8> [[REG1157]]) // CHECK-NEXT: store <16 x i8> [[REG1158]], <16 x i8>* [[REG1159:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1160:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG1153]], align 16 // CHECK-NEXT: [[REG1161:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1143]], align 16 // CHECK-NEXT: [[REG1162:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1161]] to <16 x i8> // CHECK-NEXT: [[REG1163:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG1159]], align 16 -// CHECK-NEXT: [[REG1164:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG1160]], <16 x i8> noundef [[REG1162]], <16 x i8> noundef [[REG1163]]) +// CHECK-NEXT: [[REG1164:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG1160]], <16 x i8> [[REG1162]], <16 x i8> [[REG1163]]) // CHECK-NEXT: store <16 x i8> [[REG1164]], <16 x i8>* [[REG1153]], align 16 // CHECK-NEXT: [[REG1165:[0-9a-zA-Z_%.]+]] = load <2 x i64>*, <2 x i64>** [[REG1149]], align 8 // CHECK-NEXT: [[REG1166:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG1153]], align 16 // CHECK-NEXT: [[REG1167:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG1166]] to <2 x i64> -// CHECK-NEXT: call void @_mm_storeu_si128(<2 x i64>* noundef [[REG1165]], <2 x i64> noundef [[REG1167]]) +// CHECK-NEXT: call void @_mm_storeu_si128(<2 x i64>* [[REG1165]], <2 x i64> [[REG1167]]) // CHECK-NEXT: ret void void __attribute__((noinline)) @@ -1735,7 +1735,7 @@ test_mul() { // CHECK-LABEL: @test_mul -// CHECK: define available_externally <2 x i64> @_mm_mul_epu32(<2 x i64> noundef [[REG1168:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1169:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_mul_epu32(<2 x i64> [[REG1168:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1169:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1168]], <2 x i64>* [[REG1170:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG1169]], <2 x i64>* [[REG1171:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1172:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1170]], align 16 @@ -1746,7 +1746,7 @@ test_mul() { // CHECK-NEXT: [[REG1176:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1175]], align 16 // CHECK-NEXT: ret <2 x i64> [[REG1176]] -// CHECK: define available_externally <2 x double> @_mm_mul_pd(<2 x double> noundef [[REG1177:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1178:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_mul_pd(<2 x double> [[REG1177:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1178:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG1177]], <2 x double>* [[REG1179:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG1178]], <2 x double>* [[REG1180:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1181:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1179]], align 16 @@ -1754,7 +1754,7 @@ test_mul() { // CHECK-NEXT: [[REG1183:[0-9a-zA-Z_%.]+]] = fmul <2 x double> [[REG1181]], [[REG1182]] // CHECK-NEXT: ret <2 x double> [[REG1183]] -// CHECK: define available_externally <2 x double> @_mm_mul_sd(<2 x double> noundef [[REG1184:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1185:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_mul_sd(<2 x double> [[REG1184:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1185:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG1184]], <2 x double>* [[REG1186:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG1185]], <2 x double>* [[REG1187:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1188:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1186]], align 16 @@ -1768,7 +1768,7 @@ test_mul() { // CHECK-NEXT: [[REG1195:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1186]], align 16 // CHECK-NEXT: ret <2 x double> [[REG1195]] -// CHECK: define available_externally i64 @_mm_mul_su32(i64 noundef [[REG1196:[0-9a-zA-Z_%.]+]], i64 noundef [[REG1197:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_mul_su32(i64 [[REG1196:[0-9a-zA-Z_%.]+]], i64 [[REG1197:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG1196]], i64* [[REG1198:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG1197]], i64* [[REG1199:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG1200:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG1198]], align 8 @@ -1784,7 +1784,7 @@ test_mul() { // CHECK-NEXT: [[REG1210:[0-9a-zA-Z_%.]+]] = mul i64 [[REG1207]], [[REG1209]] // CHECK-NEXT: ret i64 [[REG1210]] -// CHECK: define available_externally <2 x i64> @_mm_mulhi_epi16(<2 x i64> noundef [[REG1211:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1212:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_mulhi_epi16(<2 x i64> [[REG1211:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1212:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1211]], <2 x i64>* [[REG1213:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG1212]], <2 x i64>* [[REG1214:[0-9a-zA-Z_%.]+]], align 16 // CHECK-LE-NEXT: store <16 x i8> , <16 x i8>* [[REG1215:[0-9a-zA-Z_%.]+]], align 16 @@ -1793,22 +1793,22 @@ test_mul() { // CHECK-NEXT: [[REG1217:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1216]] to <8 x i16> // CHECK-NEXT: [[REG1218:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1214]], align 16 // CHECK-NEXT: [[REG1219:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1218]] to <8 x i16> -// CHECK-NEXT: [[REG1220:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmulesh(<8 x i16> noundef [[REG1217]], <8 x i16> noundef [[REG1219]]) +// CHECK-NEXT: [[REG1220:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmulesh(<8 x i16> [[REG1217]], <8 x i16> [[REG1219]]) // CHECK-NEXT: store <4 x i32> [[REG1220]], <4 x i32>* [[REG1221:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1222:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1213]], align 16 // CHECK-NEXT: [[REG1223:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1222]] to <8 x i16> // CHECK-NEXT: [[REG1224:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1214]], align 16 // CHECK-NEXT: [[REG1225:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1224]] to <8 x i16> -// CHECK-NEXT: [[REG1226:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmulosh(<8 x i16> noundef [[REG1223]], <8 x i16> noundef [[REG1225]]) +// CHECK-NEXT: [[REG1226:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmulosh(<8 x i16> [[REG1223]], <8 x i16> [[REG1225]]) // CHECK-NEXT: store <4 x i32> [[REG1226]], <4 x i32>* [[REG1227:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1228:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1221]], align 16 // CHECK-NEXT: [[REG1229:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1227]], align 16 // CHECK-NEXT: [[REG1230:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG1215]], align 16 -// CHECK-NEXT: [[REG1231:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> noundef [[REG1228]], <4 x i32> noundef [[REG1229]], <16 x i8> noundef [[REG1230]]) +// CHECK-NEXT: [[REG1231:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> [[REG1228]], <4 x i32> [[REG1229]], <16 x i8> [[REG1230]]) // CHECK-NEXT: [[REG1232:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1231]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG1232]] -// CHECK: define available_externally <2 x i64> @_mm_mulhi_epu16(<2 x i64> noundef [[REG1233:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1234:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_mulhi_epu16(<2 x i64> [[REG1233:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1234:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1233]], <2 x i64>* [[REG1235:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG1234]], <2 x i64>* [[REG1236:[0-9a-zA-Z_%.]+]], align 16 // CHECK-LE-NEXT: store <16 x i8> , <16 x i8>* [[REG1237:[0-9a-zA-Z_%.]+]], align 16 @@ -1817,22 +1817,22 @@ test_mul() { // CHECK-NEXT: [[REG1239:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1238]] to <8 x i16> // CHECK-NEXT: [[REG1240:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1236]], align 16 // CHECK-NEXT: [[REG1241:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1240]] to <8 x i16> -// CHECK-NEXT: [[REG1242:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmuleuh(<8 x i16> noundef [[REG1239]], <8 x i16> noundef [[REG1241]]) +// CHECK-NEXT: [[REG1242:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmuleuh(<8 x i16> [[REG1239]], <8 x i16> [[REG1241]]) // CHECK-NEXT: store <4 x i32> [[REG1242]], <4 x i32>* [[REG1243:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1244:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1235]], align 16 // CHECK-NEXT: [[REG1245:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1244]] to <8 x i16> // CHECK-NEXT: [[REG1246:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1236]], align 16 // CHECK-NEXT: [[REG1247:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1246]] to <8 x i16> -// CHECK-NEXT: [[REG1248:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmulouh(<8 x i16> noundef [[REG1245]], <8 x i16> noundef [[REG1247]]) +// CHECK-NEXT: [[REG1248:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmulouh(<8 x i16> [[REG1245]], <8 x i16> [[REG1247]]) // CHECK-NEXT: store <4 x i32> [[REG1248]], <4 x i32>* [[REG1249:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1250:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1243]], align 16 // CHECK-NEXT: [[REG1251:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1249]], align 16 // CHECK-NEXT: [[REG1252:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG1237]], align 16 -// CHECK-NEXT: [[REG1253:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(unsigned int vector[4], unsigned int vector[4], unsigned char vector[16])(<4 x i32> noundef [[REG1250]], <4 x i32> noundef [[REG1251]], <16 x i8> noundef [[REG1252]]) +// CHECK-NEXT: [[REG1253:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(unsigned int vector[4], unsigned int vector[4], unsigned char vector[16])(<4 x i32> [[REG1250]], <4 x i32> [[REG1251]], <16 x i8> [[REG1252]]) // CHECK-NEXT: [[REG1254:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1253]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG1254]] -// CHECK: define available_externally <2 x i64> @_mm_mullo_epi16(<2 x i64> noundef [[REG1255:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1256:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_mullo_epi16(<2 x i64> [[REG1255:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1256:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1255]], <2 x i64>* [[REG1257:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG1256]], <2 x i64>* [[REG1258:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1259:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1257]], align 16 @@ -1878,10 +1878,10 @@ test_sad() { // CHECK: call <16 x i8> @vec_min(unsigned char vector[16], unsigned char vector[16]) // CHECK: call <16 x i8> @vec_max(unsigned char vector[16], unsigned char vector[16]) // CHECK: call <16 x i8> @vec_sub(unsigned char vector[16], unsigned char vector[16]) -// CHECK: call <4 x i32> @vec_sum4s(unsigned char vector[16], unsigned int vector[4])(<16 x i8> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef zeroinitializer) -// CHECK: call <4 x i32> @vec_sum2s(<4 x i32> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef zeroinitializer) -// CHECK-LE: [[REG1271:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sld(int vector[4], int vector[4], unsigned int)(<4 x i32> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef {{[0-9a-zA-Z_%.]+}}, i32 noundef zeroext 4) -// CHECK-BE: [[REG1271:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sld(int vector[4], int vector[4], unsigned int)(<4 x i32> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef {{[0-9a-zA-Z_%.]+}}, i32 noundef zeroext 6) +// CHECK: call <4 x i32> @vec_sum4s(unsigned char vector[16], unsigned int vector[4])(<16 x i8> {{[0-9a-zA-Z_%.]+}}, <4 x i32> zeroinitializer) +// CHECK: call <4 x i32> @vec_sum2s(<4 x i32> {{[0-9a-zA-Z_%.]+}}, <4 x i32> zeroinitializer) +// CHECK-LE: [[REG1271:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sld(int vector[4], int vector[4], unsigned int)(<4 x i32> {{[0-9a-zA-Z_%.]+}}, <4 x i32> {{[0-9a-zA-Z_%.]+}}, i32 zeroext 4) +// CHECK-BE: [[REG1271:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sld(int vector[4], int vector[4], unsigned int)(<4 x i32> {{[0-9a-zA-Z_%.]+}}, <4 x i32> {{[0-9a-zA-Z_%.]+}}, i32 zeroext 6) // CHECK-NEXT: store <4 x i32> [[REG1271]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG1272:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG1273:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1272]] to <2 x i64> @@ -1924,15 +1924,15 @@ test_set() { // CHECK: insertelement <4 x i32> undef, i32 {{[0-9a-zA-Z_%.]+}}, i32 0 // CHECK-COUNT-3: insertelement <4 x i32> {{[0-9a-zA-Z_%.]+}}, i32 {{[0-9a-zA-Z_%.]+}}, i32 {{[1-3]}} -// CHECK: define available_externally <2 x i64> @_mm_set_epi64(i64 noundef [[REG1274:[0-9a-zA-Z_%.]+]], i64 noundef [[REG1275:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_set_epi64(i64 [[REG1274:[0-9a-zA-Z_%.]+]], i64 [[REG1275:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG1274]], i64* [[REG1276:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG1275]], i64* [[REG1277:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG1278:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG1276]], align 8 // CHECK-NEXT: [[REG1279:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG1277]], align 8 -// CHECK-NEXT: [[REG1280:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi64x(i64 noundef [[REG1278]], i64 noundef [[REG1279]]) +// CHECK-NEXT: [[REG1280:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi64x(i64 [[REG1278]], i64 [[REG1279]]) // CHECK-NEXT: ret <2 x i64> [[REG1280]] -// CHECK: define available_externally <2 x i64> @_mm_set_epi64x(i64 noundef [[REG1281:[0-9a-zA-Z_%.]+]], i64 noundef [[REG1282:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_set_epi64x(i64 [[REG1281:[0-9a-zA-Z_%.]+]], i64 [[REG1282:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG1281]], i64* [[REG1283:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG1282]], i64* [[REG1284:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG1285:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG1284]], align 8 @@ -1952,7 +1952,7 @@ test_set() { // CHECK-NEXT: [[REG1293:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG1292]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG1293]] -// CHECK: define available_externally <2 x double> @_mm_set_pd(double noundef [[REG1294:[0-9a-zA-Z_%.]+]], double noundef [[REG1295:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_set_pd(double [[REG1294:[0-9a-zA-Z_%.]+]], double [[REG1295:[0-9a-zA-Z_%.]+]]) // CHECK: store double [[REG1294]], double* [[REG1296:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store double [[REG1295]], double* [[REG1297:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG1298:[0-9a-zA-Z_%.]+]] = load double, double* [[REG1297]], align 8 @@ -1963,13 +1963,13 @@ test_set() { // CHECK-NEXT: [[REG1303:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1302]], align 16 // CHECK-NEXT: ret <2 x double> [[REG1303]] -// CHECK: define available_externally <2 x double> @_mm_set_pd1(double noundef [[REG1304:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_set_pd1(double [[REG1304:[0-9a-zA-Z_%.]+]]) // CHECK: store double [[REG1304]], double* [[REG1305:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG1306:[0-9a-zA-Z_%.]+]] = load double, double* [[REG1305]], align 8 -// CHECK-NEXT: [[REG1307:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_set1_pd(double noundef [[REG1306]]) +// CHECK-NEXT: [[REG1307:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_set1_pd(double [[REG1306]]) // CHECK-NEXT: ret <2 x double> [[REG1307]] -// CHECK: define available_externally <2 x double> @_mm_set_sd(double noundef [[REG1308:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_set_sd(double [[REG1308:[0-9a-zA-Z_%.]+]]) // CHECK: store double [[REG1308]], double* [[REG1309:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG1310:[0-9a-zA-Z_%.]+]] = load double, double* [[REG1309]], align 8 // CHECK-NEXT: [[REG1311:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG1310]], i32 0 @@ -1978,39 +1978,39 @@ test_set() { // CHECK-NEXT: [[REG1314:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1313]], align 16 // CHECK-NEXT: ret <2 x double> [[REG1314]] -// CHECK: define available_externally <2 x i64> @_mm_set1_epi16(i16 noundef signext [[REG1315:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_set1_epi16(i16 signext [[REG1315:[0-9a-zA-Z_%.]+]]) // CHECK: store i16 [[REG1315]], i16* [[REG1316:[0-9a-zA-Z_%.]+]], align 2 // CHECK-COUNT-8: load i16, i16* [[REG1316]], align 2 // CHECK-NEXT: [[REG1317:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi16 // CHECK-NEXT: ret <2 x i64> [[REG1317]] -// CHECK: define available_externally <2 x i64> @_mm_set1_epi32(i32 noundef signext [[REG1318:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_set1_epi32(i32 signext [[REG1318:[0-9a-zA-Z_%.]+]]) // CHECK: store i32 [[REG1318]], i32* [[REG1319:[0-9a-zA-Z_%.]+]], align 4 // CHECK-COUNT-4: load i32, i32* [[REG1319]], align 4 // CHECK-NEXT: [[REG1320:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi32 // CHECK-NEXT: ret <2 x i64> [[REG1320]] -// CHECK: define available_externally <2 x i64> @_mm_set1_epi64(i64 noundef [[REG1321:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_set1_epi64(i64 [[REG1321:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG1321]], i64* [[REG1322:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG1323:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG1322]], align 8 // CHECK-NEXT: [[REG1324:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG1322]], align 8 -// CHECK-NEXT: [[REG1325:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi64(i64 noundef [[REG1323]], i64 noundef [[REG1324]]) +// CHECK-NEXT: [[REG1325:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi64(i64 [[REG1323]], i64 [[REG1324]]) // CHECK-NEXT: ret <2 x i64> [[REG1325]] -// CHECK: define available_externally <2 x i64> @_mm_set1_epi64x(i64 noundef [[REG1326:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_set1_epi64x(i64 [[REG1326:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG1326]], i64* [[REG1327:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG1328:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG1327]], align 8 // CHECK-NEXT: [[REG1329:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG1327]], align 8 -// CHECK-NEXT: [[REG1330:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi64x(i64 noundef [[REG1328]], i64 noundef [[REG1329]]) +// CHECK-NEXT: [[REG1330:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi64x(i64 [[REG1328]], i64 [[REG1329]]) // CHECK-NEXT: ret <2 x i64> [[REG1330]] -// CHECK: define available_externally <2 x i64> @_mm_set1_epi8(i8 noundef zeroext [[REG1331:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_set1_epi8(i8 zeroext [[REG1331:[0-9a-zA-Z_%.]+]]) // CHECK: store i8 [[REG1331]], i8* [[REG1332:[0-9a-zA-Z_%.]+]], align 1 // CHECK-COUNT-16: load i8, i8* [[REG1332]], align 1 // CHECK: [[REG1333:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi8 // CHECK-NEXT: ret <2 x i64> [[REG1333]] -// CHECK: define available_externally <2 x double> @_mm_set1_pd(double noundef [[REG1334:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_set1_pd(double [[REG1334:[0-9a-zA-Z_%.]+]]) // CHECK: store double [[REG1334]], double* [[REG1335:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG1336:[0-9a-zA-Z_%.]+]] = load double, double* [[REG1335]], align 8 // CHECK-NEXT: [[REG1337:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG1336]], i32 0 @@ -2020,7 +2020,7 @@ test_set() { // CHECK-NEXT: [[REG1341:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1340]], align 16 // CHECK-NEXT: ret <2 x double> [[REG1341]] -// CHECK: define available_externally <2 x i64> @_mm_setr_epi16(i16 noundef signext [[REG1342:[0-9a-zA-Z_%.]+]], i16 noundef signext [[REG1343:[0-9a-zA-Z_%.]+]], i16 noundef signext [[REG1344:[0-9a-zA-Z_%.]+]], i16 noundef signext [[REG1345:[0-9a-zA-Z_%.]+]], i16 noundef signext [[REG1346:[0-9a-zA-Z_%.]+]], i16 noundef signext [[REG1347:[0-9a-zA-Z_%.]+]], i16 noundef signext [[REG1348:[0-9a-zA-Z_%.]+]], i16 noundef signext [[REG1349:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_setr_epi16(i16 signext [[REG1342:[0-9a-zA-Z_%.]+]], i16 signext [[REG1343:[0-9a-zA-Z_%.]+]], i16 signext [[REG1344:[0-9a-zA-Z_%.]+]], i16 signext [[REG1345:[0-9a-zA-Z_%.]+]], i16 signext [[REG1346:[0-9a-zA-Z_%.]+]], i16 signext [[REG1347:[0-9a-zA-Z_%.]+]], i16 signext [[REG1348:[0-9a-zA-Z_%.]+]], i16 signext [[REG1349:[0-9a-zA-Z_%.]+]]) // CHECK-COUNT-8: store i16 {{[0-9a-zA-Z_%.]+}}, i16* {{[0-9a-zA-Z_%.]+}}, align 2 // CHECK-COUNT-8: load i16, i16* {{[0-9a-zA-Z_%.]+}}, align 2 // CHECK-NEXT: [[REG1350:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi16 @@ -2032,12 +2032,12 @@ test_set() { // CHECK-NEXT: [[REG1351:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi32 // CHECK-NEXT: ret <2 x i64> [[REG1351]] -// CHECK: define available_externally <2 x i64> @_mm_setr_epi64(i64 noundef [[REG1352:[0-9a-zA-Z_%.]+]], i64 noundef [[REG1353:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_setr_epi64(i64 [[REG1352:[0-9a-zA-Z_%.]+]], i64 [[REG1353:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG1352]], i64* [[REG1354:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG1353]], i64* [[REG1355:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG1356:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG1355]], align 8 // CHECK-NEXT: [[REG1357:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG1354]], align 8 -// CHECK-NEXT: [[REG1358:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi64(i64 noundef [[REG1356]], i64 noundef [[REG1357]]) +// CHECK-NEXT: [[REG1358:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi64(i64 [[REG1356]], i64 [[REG1357]]) // CHECK-NEXT: ret <2 x i64> [[REG1358]] // CHECK: define available_externally <2 x i64> @_mm_setr_epi8 @@ -2046,7 +2046,7 @@ test_set() { // CHECK-NEXT: [[REG1359:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_set_epi8 // CHECK-NEXT: ret <2 x i64> [[REG1359]] -// CHECK: define available_externally <2 x double> @_mm_setr_pd(double noundef [[REG1360:[0-9a-zA-Z_%.]+]], double noundef [[REG1361:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_setr_pd(double [[REG1360:[0-9a-zA-Z_%.]+]], double [[REG1361:[0-9a-zA-Z_%.]+]]) // CHECK: store double [[REG1360]], double* [[REG1362:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store double [[REG1361]], double* [[REG1363:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG1364:[0-9a-zA-Z_%.]+]] = load double, double* [[REG1362]], align 8 @@ -2058,7 +2058,7 @@ test_set() { // CHECK-NEXT: ret <2 x double> [[REG1369]] // CHECK: define available_externally <2 x double> @_mm_setzero_pd() -// CHECK: [[REG1370:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(int)(i32 noundef signext 0) +// CHECK: [[REG1370:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(int)(i32 signext 0) // CHECK-NEXT: [[REG1371:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1370]] to <2 x double> // CHECK-NEXT: ret <2 x double> [[REG1371]] @@ -2078,7 +2078,7 @@ test_shuffle() { // CHECK-LABEL: @test_shuffle -// CHECK: define available_externally <2 x i64> @_mm_shuffle_epi32(<2 x i64> noundef [[REG1375:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG1376:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_shuffle_epi32(<2 x i64> [[REG1375:[0-9a-zA-Z_%.]+]], i32 signext [[REG1376:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1375]], <2 x i64>* [[REG1377:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG1376]], i32* [[REG1378:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG1379:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1378]], align 4 @@ -2132,11 +2132,11 @@ test_shuffle() { // CHECK-NEXT: [[REG1424:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1423]] to <4 x i32> // CHECK-NEXT: [[REG1425:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1402]], align 16 // CHECK-NEXT: [[REG1426:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1425]] to <16 x i8> -// CHECK-NEXT: [[REG1427:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> noundef [[REG1422]], <4 x i32> noundef [[REG1424]], <16 x i8> noundef [[REG1426]]) +// CHECK-NEXT: [[REG1427:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> [[REG1422]], <4 x i32> [[REG1424]], <16 x i8> [[REG1426]]) // CHECK-NEXT: [[REG1428:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1427]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG1428]] -// CHECK: define available_externally <2 x double> @_mm_shuffle_pd(<2 x double> noundef [[REG1429:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1430:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG1431:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_shuffle_pd(<2 x double> [[REG1429:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1430:[0-9a-zA-Z_%.]+]], i32 signext [[REG1431:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG1429]], <2 x double>* [[REG1432:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG1430]], <2 x double>* [[REG1433:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG1431]], i32* [[REG1434:[0-9a-zA-Z_%.]+]], align 4 @@ -2150,7 +2150,7 @@ test_shuffle() { // CHECK: [[REG1440]]: // CHECK-NEXT: [[REG1442:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1432]], align 16 // CHECK-NEXT: [[REG1443:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1433]], align 16 -// CHECK-NEXT: [[REG1444:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_mergeh(double vector[2], double vector[2])(<2 x double> noundef [[REG1442]], <2 x double> noundef [[REG1443]]) +// CHECK-NEXT: [[REG1444:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_mergeh(double vector[2], double vector[2])(<2 x double> [[REG1442]], <2 x double> [[REG1443]]) // CHECK-NEXT: store <2 x double> [[REG1444]], <2 x double>* [[REG1445:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: br label %[[REG1446:[0-9a-zA-Z_%.]+]] @@ -2187,7 +2187,7 @@ test_shuffle() { // CHECK: [[REG1450]]: // CHECK-NEXT: [[REG1467:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1432]], align 16 // CHECK-NEXT: [[REG1468:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1433]], align 16 -// CHECK-NEXT: [[REG1469:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_mergel(double vector[2], double vector[2])(<2 x double> noundef [[REG1467]], <2 x double> noundef [[REG1468]]) +// CHECK-NEXT: [[REG1469:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_mergel(double vector[2], double vector[2])(<2 x double> [[REG1467]], <2 x double> [[REG1468]]) // CHECK-NEXT: store <2 x double> [[REG1469]], <2 x double>* [[REG1445]], align 16 // CHECK-NEXT: br label %[[REG1466:[0-9a-zA-Z_%.]+]] @@ -2201,7 +2201,7 @@ test_shuffle() { // CHECK-NEXT: [[REG1470:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1445]], align 16 // CHECK-NEXT: ret <2 x double> [[REG1470]] -// CHECK: define available_externally <2 x i64> @_mm_shufflehi_epi16(<2 x i64> noundef [[REG1471:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG1472:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_shufflehi_epi16(<2 x i64> [[REG1471:[0-9a-zA-Z_%.]+]], i32 signext [[REG1472:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1471]], <2 x i64>* [[REG1473:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG1472]], i32* [[REG1474:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG1475:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1474]], align 4 @@ -2265,48 +2265,48 @@ test_sll() { // CHECK-LABEL: @test_sll -// CHECK: define available_externally <2 x i64> @_mm_sll_epi16(<2 x i64> noundef [[REG1513:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1514:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_sll_epi16(<2 x i64> [[REG1513:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1514:[0-9a-zA-Z_%.]+]]) // CHECK: store <8 x i16> , <8 x i16>* [[REG1515:[0-9a-zA-Z_%.]+]], align 16 // CHECK-LE: [[REG1516:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int) // CHECK-BE: [[REG1516:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int) // CHECK-NEXT: store <8 x i16> [[REG1516]], <8 x i16>* [[REG1517:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1518:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1517]], align 16 -// CHECK-NEXT: [[REG1519:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmple(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG1518]], <8 x i16> noundef ) +// CHECK-NEXT: [[REG1519:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmple(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG1518]], <8 x i16> ) // CHECK-NEXT: store <8 x i16> [[REG1519]], <8 x i16>* [[REG1520:[0-9a-zA-Z_%.]+]], align 16 // CHECK: [[REG1521:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sl(unsigned short vector[8], unsigned short vector[8]) // CHECK-NEXT: store <8 x i16> [[REG1521]], <8 x i16>* [[REG1522:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1523:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1520]], align 16 // CHECK-NEXT: [[REG1524:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1522]], align 16 // CHECK-NEXT: [[REG1525:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1520]], align 16 -// CHECK-NEXT: [[REG1526:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sel(unsigned short vector[8], unsigned short vector[8], bool vector[8])(<8 x i16> noundef [[REG1523]], <8 x i16> noundef [[REG1524]], <8 x i16> noundef [[REG1525]]) +// CHECK-NEXT: [[REG1526:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sel(unsigned short vector[8], unsigned short vector[8], bool vector[8])(<8 x i16> [[REG1523]], <8 x i16> [[REG1524]], <8 x i16> [[REG1525]]) // CHECK-NEXT: store <8 x i16> [[REG1526]], <8 x i16>* [[REG1522]], align 16 // CHECK-NEXT: [[REG1527:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1522]], align 16 // CHECK-NEXT: [[REG1528:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG1527]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG1528]] -// CHECK: define available_externally <2 x i64> @_mm_sll_epi32(<2 x i64> noundef [[REG1529:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1530:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_sll_epi32(<2 x i64> [[REG1529:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1530:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1529]], <2 x i64>* [[REG1531:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG1530]], <2 x i64>* [[REG1532:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x i32> , <4 x i32>* [[REG1533:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1534:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1532]], align 16 // CHECK-NEXT: [[REG1535:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1534]] to <4 x i32> -// CHECK-LE-NEXT: [[REG1536:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat(unsigned int vector[4], unsigned int)(<4 x i32> noundef [[REG1535]], i32 noundef zeroext 0) -// CHECK-BE-NEXT: [[REG1536:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat(unsigned int vector[4], unsigned int)(<4 x i32> noundef [[REG1535]], i32 noundef zeroext 1) -// CHECK: call <4 x i32> @vec_cmplt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef ) +// CHECK-LE-NEXT: [[REG1536:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat(unsigned int vector[4], unsigned int)(<4 x i32> [[REG1535]], i32 zeroext 0) +// CHECK-BE-NEXT: [[REG1536:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat(unsigned int vector[4], unsigned int)(<4 x i32> [[REG1535]], i32 zeroext 1) +// CHECK: call <4 x i32> @vec_cmplt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> {{[0-9a-zA-Z_%.]+}}, <4 x i32> ) // CHECK: [[REG1537:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sl(unsigned int vector[4], unsigned int vector[4]) // CHECK-NEXT: store <4 x i32> [[REG1537]], <4 x i32>* [[REG1538:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1539:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG1540:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1538]], align 16 // CHECK-NEXT: [[REG1541:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG1542:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sel(unsigned int vector[4], unsigned int vector[4], bool vector[4])(<4 x i32> noundef [[REG1539]], <4 x i32> noundef [[REG1540]], <4 x i32> noundef [[REG1541]]) +// CHECK-NEXT: [[REG1542:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sel(unsigned int vector[4], unsigned int vector[4], bool vector[4])(<4 x i32> [[REG1539]], <4 x i32> [[REG1540]], <4 x i32> [[REG1541]]) // CHECK-NEXT: store <4 x i32> [[REG1542]], <4 x i32>* [[REG1538]], align 16 // CHECK-NEXT: [[REG1543:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1538]], align 16 // CHECK-NEXT: [[REG1544:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1543]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG1544]] // CHECK: define available_externally <2 x i64> @_mm_sll_epi64 -// CHECK: call <2 x i64> @vec_splat(unsigned long long vector[2], unsigned int)(<2 x i64> noundef {{[0-9a-zA-Z_%.]+}}, i32 noundef zeroext 0) -// CHECK: call <2 x i64> @vec_cmplt(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> noundef {{[0-9a-zA-Z_%.]+}}, <2 x i64> noundef ) +// CHECK: call <2 x i64> @vec_splat(unsigned long long vector[2], unsigned int)(<2 x i64> {{[0-9a-zA-Z_%.]+}}, i32 zeroext 0) +// CHECK: call <2 x i64> @vec_cmplt(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> {{[0-9a-zA-Z_%.]+}}, <2 x i64> ) // CHECK: call <2 x i64> @vec_sl(unsigned long long vector[2], unsigned long long vector[2]) // CHECK: [[REG1545:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_sel(double vector[2], double vector[2], bool vector[2]) // CHECK-NEXT: [[REG1546:[0-9a-zA-Z_%.]+]] = bitcast <2 x double> [[REG1545]] to <2 x i64> @@ -2314,7 +2314,7 @@ test_sll() { // CHECK-NEXT: [[REG1548:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1547]], align 16 // CHECK-NEXT: ret <2 x i64> [[REG1548]] -// CHECK: define available_externally <2 x i64> @_mm_slli_epi16(<2 x i64> noundef [[REG1549:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG1550:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_slli_epi16(<2 x i64> [[REG1549:[0-9a-zA-Z_%.]+]], i32 signext [[REG1550:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1549]], <2 x i64>* [[REG1551:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG1550]], i32* [[REG1552:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store <8 x i16> zeroinitializer, <8 x i16>* [[REG1553:[0-9a-zA-Z_%.]+]], align 16 @@ -2335,14 +2335,14 @@ test_sll() { // CHECK: [[REG1561]]: // CHECK-NEXT: [[REG1563:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1552]], align 4 // CHECK-NEXT: [[REG1564:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1563]] to i8 -// CHECK-NEXT: [[REG1565:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat_s16(signed char)(i8 noundef signext [[REG1564]]) +// CHECK-NEXT: [[REG1565:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat_s16(signed char)(i8 signext [[REG1564]]) // CHECK-NEXT: store <8 x i16> [[REG1565]], <8 x i16>* [[REG1566:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: br label %[[REG1567:[0-9a-zA-Z_%.]+]] // CHECK: [[REG1562]]: // CHECK-NEXT: [[REG1568:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1552]], align 4 // CHECK-NEXT: [[REG1569:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1568]] to i16 -// CHECK-NEXT: [[REG1570:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 noundef zeroext [[REG1569]]) +// CHECK-NEXT: [[REG1570:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 zeroext [[REG1569]]) // CHECK-NEXT: store <8 x i16> [[REG1570]], <8 x i16>* [[REG1566]], align 16 // CHECK-NEXT: br label %[[REG1567:[0-9a-zA-Z_%.]+]] @@ -2350,7 +2350,7 @@ test_sll() { // CHECK-NEXT: [[REG1571:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1551]], align 16 // CHECK-NEXT: [[REG1572:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1571]] to <8 x i16> // CHECK-NEXT: [[REG1573:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1566]], align 16 -// CHECK-NEXT: [[REG1574:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sl(short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG1572]], <8 x i16> noundef [[REG1573]]) +// CHECK-NEXT: [[REG1574:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sl(short vector[8], unsigned short vector[8])(<8 x i16> [[REG1572]], <8 x i16> [[REG1573]]) // CHECK-NEXT: store <8 x i16> [[REG1574]], <8 x i16>* [[REG1553]], align 16 // CHECK-NEXT: br label %[[REG1557:[0-9a-zA-Z_%.]+]] @@ -2359,7 +2359,7 @@ test_sll() { // CHECK-NEXT: [[REG1576:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG1575]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG1576]] -// CHECK: define available_externally <2 x i64> @_mm_slli_epi32(<2 x i64> noundef [[REG1577:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG1578:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_slli_epi32(<2 x i64> [[REG1577:[0-9a-zA-Z_%.]+]], i32 signext [[REG1578:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1577]], <2 x i64>* [[REG1579:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG1578]], i32* [[REG1580:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* [[REG1581:[0-9a-zA-Z_%.]+]], align 16 @@ -2385,13 +2385,13 @@ test_sll() { // CHECK: [[REG1593]]: // CHECK-NEXT: [[REG1594:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1580]], align 4 // CHECK-NEXT: [[REG1595:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1594]] to i8 -// CHECK-NEXT: [[REG1596:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat_s32(signed char)(i8 noundef signext [[REG1595]]) +// CHECK-NEXT: [[REG1596:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat_s32(signed char)(i8 signext [[REG1595]]) // CHECK-NEXT: store <4 x i32> [[REG1596]], <4 x i32>* [[REG1597:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: br label %[[REG1598:[0-9a-zA-Z_%.]+]] // CHECK: [[REG1590]]: // CHECK-NEXT: [[REG1599:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1580]], align 4 -// CHECK-NEXT: [[REG1600:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 noundef zeroext [[REG1599]]) +// CHECK-NEXT: [[REG1600:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1599]]) // CHECK-NEXT: store <4 x i32> [[REG1600]], <4 x i32>* [[REG1597]], align 16 // CHECK-NEXT: br label %[[REG1598:[0-9a-zA-Z_%.]+]] @@ -2399,7 +2399,7 @@ test_sll() { // CHECK-NEXT: [[REG1601:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1579]], align 16 // CHECK-NEXT: [[REG1602:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1601]] to <4 x i32> // CHECK-NEXT: [[REG1603:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1597]], align 16 -// CHECK-NEXT: [[REG1604:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sl(int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG1602]], <4 x i32> noundef [[REG1603]]) +// CHECK-NEXT: [[REG1604:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sl(int vector[4], unsigned int vector[4])(<4 x i32> [[REG1602]], <4 x i32> [[REG1603]]) // CHECK-NEXT: store <4 x i32> [[REG1604]], <4 x i32>* [[REG1581]], align 16 // CHECK-NEXT: br label %[[REG1585:[0-9a-zA-Z_%.]+]] @@ -2408,7 +2408,7 @@ test_sll() { // CHECK-NEXT: [[REG1606:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1605]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG1606]] -// CHECK: define available_externally <2 x i64> @_mm_slli_epi64(<2 x i64> noundef [[REG1607:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG1608:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_slli_epi64(<2 x i64> [[REG1607:[0-9a-zA-Z_%.]+]], i32 signext [[REG1608:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1607]], <2 x i64>* [[REG1609:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG1608]], i32* [[REG1610:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* [[REG1611:[0-9a-zA-Z_%.]+]], align 16 @@ -2434,14 +2434,14 @@ test_sll() { // CHECK: [[REG1623]]: // CHECK-NEXT: [[REG1624:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1610]], align 4 // CHECK-NEXT: [[REG1625:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1624]] to i8 -// CHECK-NEXT: [[REG1626:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat_s32(signed char)(i8 noundef signext [[REG1625]]) +// CHECK-NEXT: [[REG1626:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat_s32(signed char)(i8 signext [[REG1625]]) // CHECK-NEXT: [[REG1627:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1626]] to <2 x i64> // CHECK-NEXT: store <2 x i64> [[REG1627]], <2 x i64>* [[REG1628:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: br label %[[REG1629:[0-9a-zA-Z_%.]+]] // CHECK: [[REG1620]]: // CHECK-NEXT: [[REG1630:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1610]], align 4 -// CHECK-NEXT: [[REG1631:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 noundef zeroext [[REG1630]]) +// CHECK-NEXT: [[REG1631:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1630]]) // CHECK-NEXT: [[REG1632:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1631]] to <2 x i64> // CHECK-NEXT: store <2 x i64> [[REG1632]], <2 x i64>* [[REG1628]], align 16 // CHECK-NEXT: br label %[[REG1629:[0-9a-zA-Z_%.]+]] @@ -2449,7 +2449,7 @@ test_sll() { // CHECK: [[REG1629]]: // CHECK-NEXT: [[REG1633:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1609]], align 16 // CHECK-NEXT: [[REG1634:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1628]], align 16 -// CHECK-NEXT: [[REG1635:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_sl(long long vector[2], unsigned long long vector[2])(<2 x i64> noundef [[REG1633]], <2 x i64> noundef [[REG1634]]) +// CHECK-NEXT: [[REG1635:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_sl(long long vector[2], unsigned long long vector[2])(<2 x i64> [[REG1633]], <2 x i64> [[REG1634]]) // CHECK-NEXT: store <2 x i64> [[REG1635]], <2 x i64>* [[REG1611]], align 16 // CHECK-NEXT: br label %[[REG1615:[0-9a-zA-Z_%.]+]] @@ -2457,7 +2457,7 @@ test_sll() { // CHECK-NEXT: [[REG1636:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1611]], align 16 // CHECK-NEXT: ret <2 x i64> [[REG1636]] -// CHECK: define available_externally <2 x i64> @_mm_slli_si128(<2 x i64> noundef [[REG1637:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG1638:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_slli_si128(<2 x i64> [[REG1637:[0-9a-zA-Z_%.]+]], i32 signext [[REG1638:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1637]], <2 x i64>* [[REG1639:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG1638]], i32* [[REG1640:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store <16 x i8> zeroinitializer, <16 x i8>* [[REG1641:[0-9a-zA-Z_%.]+]], align 16 @@ -2470,8 +2470,8 @@ test_sll() { // CHECK-NEXT: [[REG1647:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1646]] to <16 x i8> // CHECK-NEXT: [[REG1648:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1640]], align 4 // CHECK-BE-NEXT: [[REG1649:[0-9a-zA-Z_%.]+]] = sub nsw i32 16, [[REG1648]] -// CHECK-BE-NEXT: [[REG1650:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sld(unsigned char vector[16], unsigned char vector[16], unsigned int)(<16 x i8> noundef zeroinitializer, <16 x i8> noundef [[REG1647]], i32 noundef zeroext [[REG1649]]) -// CHECK-LE-NEXT: [[REG1650:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sld(unsigned char vector[16], unsigned char vector[16], unsigned int)(<16 x i8> noundef [[REG1647]], <16 x i8> noundef zeroinitializer, i32 noundef zeroext [[REG1648]]) +// CHECK-BE-NEXT: [[REG1650:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sld(unsigned char vector[16], unsigned char vector[16], unsigned int)(<16 x i8> zeroinitializer, <16 x i8> [[REG1647]], i32 zeroext [[REG1649]]) +// CHECK-LE-NEXT: [[REG1650:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sld(unsigned char vector[16], unsigned char vector[16], unsigned int)(<16 x i8> [[REG1647]], <16 x i8> zeroinitializer, i32 zeroext [[REG1648]]) // CHECK-NEXT: store <16 x i8> [[REG1650]], <16 x i8>* [[REG1651:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: br label %[[REG1652:[0-9a-zA-Z_%.]+]] // CHECK: [[REG1645]]: @@ -2492,22 +2492,22 @@ test_sqrt() { // CHECK-LABEL: @test_sqrt // CHECK: define available_externally <2 x double> @_mm_sqrt_pd -// CHECK: [[REG1655:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_sqrt(double vector[2])(<2 x double> noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG1655:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_sqrt(double vector[2])(<2 x double> {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: ret <2 x double> [[REG1655]] -// CHECK: define available_externally <2 x double> @_mm_sqrt_sd(<2 x double> noundef [[REG1656:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1657:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_sqrt_sd(<2 x double> [[REG1656:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1657:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG1656]], <2 x double>* [[REG1658:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG1657]], <2 x double>* [[REG1659:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1660:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1659]], align 16 // CHECK-NEXT: [[REG1661:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1660]], i32 0 -// CHECK-NEXT: [[REG1662:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_set1_pd(double noundef [[REG1661]]) -// CHECK-NEXT: [[REG1663:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_sqrt(double vector[2])(<2 x double> noundef [[REG1662]]) +// CHECK-NEXT: [[REG1662:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_set1_pd(double [[REG1661]]) +// CHECK-NEXT: [[REG1663:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_sqrt(double vector[2])(<2 x double> [[REG1662]]) // CHECK-NEXT: store <2 x double> [[REG1663]], <2 x double>* [[REG1664:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1665:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1664]], align 16 // CHECK-NEXT: [[REG1666:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1665]], i32 0 // CHECK-NEXT: [[REG1667:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1658]], align 16 // CHECK-NEXT: [[REG1668:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1667]], i32 1 -// CHECK-NEXT: [[REG1669:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double noundef [[REG1666]], double noundef [[REG1668]]) +// CHECK-NEXT: [[REG1669:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG1666]], double [[REG1668]]) // CHECK-NEXT: ret <2 x double> [[REG1669]] void __attribute__((noinline)) @@ -2520,49 +2520,49 @@ test_sra() { // CHECK-LABEL: @test_sra -// CHECK: define available_externally <2 x i64> @_mm_sra_epi16(<2 x i64> noundef [[REG1670:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1671:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_sra_epi16(<2 x i64> [[REG1670:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1671:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1670]], <2 x i64>* [[REG1672:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG1671]], <2 x i64>* [[REG1673:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <8 x i16> , <8 x i16>* [[REG1674:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1675:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1673]], align 16 // CHECK-NEXT: [[REG1676:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1675]] to <8 x i16> -// CHECK-LE-NEXT: [[REG1677:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int)(<8 x i16> noundef [[REG1676]], i32 noundef zeroext 0) -// CHECK-BE-NEXT: [[REG1677:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int)(<8 x i16> noundef [[REG1676]], i32 noundef zeroext 3) +// CHECK-LE-NEXT: [[REG1677:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int)(<8 x i16> [[REG1676]], i32 zeroext 0) +// CHECK-BE-NEXT: [[REG1677:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int)(<8 x i16> [[REG1676]], i32 zeroext 3) // CHECK-NEXT: store <8 x i16> [[REG1677]], <8 x i16>* [[REG1678:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1679:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1678]], align 16 -// CHECK-NEXT: [[REG1680:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_min(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG1679]], <8 x i16> noundef ) +// CHECK-NEXT: [[REG1680:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_min(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG1679]], <8 x i16> ) // CHECK-NEXT: store <8 x i16> [[REG1680]], <8 x i16>* [[REG1678]], align 16 // CHECK-NEXT: [[REG1681:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1672]], align 16 // CHECK-NEXT: [[REG1682:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1681]] to <8 x i16> // CHECK-NEXT: [[REG1683:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1678]], align 16 -// CHECK-NEXT: [[REG1684:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sra(short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG1682]], <8 x i16> noundef [[REG1683]]) +// CHECK-NEXT: [[REG1684:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sra(short vector[8], unsigned short vector[8])(<8 x i16> [[REG1682]], <8 x i16> [[REG1683]]) // CHECK-NEXT: store <8 x i16> [[REG1684]], <8 x i16>* [[REG1685:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1686:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1685]], align 16 // CHECK-NEXT: [[REG1687:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG1686]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG1687]] -// CHECK: define available_externally <2 x i64> @_mm_sra_epi32(<2 x i64> noundef [[REG1688:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1689:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_sra_epi32(<2 x i64> [[REG1688:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1689:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1688]], <2 x i64>* [[REG1690:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG1689]], <2 x i64>* [[REG1691:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x i32> , <4 x i32>* [[REG1692:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1693:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1691]], align 16 // CHECK-NEXT: [[REG1694:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1693]] to <4 x i32> -// CHECK-LE-NEXT: [[REG1695:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat(unsigned int vector[4], unsigned int)(<4 x i32> noundef [[REG1694]], i32 noundef zeroext 0) -// CHECK-BE-NEXT: [[REG1695:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat(unsigned int vector[4], unsigned int)(<4 x i32> noundef [[REG1694]], i32 noundef zeroext 1) +// CHECK-LE-NEXT: [[REG1695:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat(unsigned int vector[4], unsigned int)(<4 x i32> [[REG1694]], i32 zeroext 0) +// CHECK-BE-NEXT: [[REG1695:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat(unsigned int vector[4], unsigned int)(<4 x i32> [[REG1694]], i32 zeroext 1) // CHECK-NEXT: store <4 x i32> [[REG1695]], <4 x i32>* [[REG1696:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1697:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1696]], align 16 -// CHECK-NEXT: [[REG1698:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_min(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG1697]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG1698:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_min(unsigned int vector[4], unsigned int vector[4])(<4 x i32> [[REG1697]], <4 x i32> ) // CHECK-NEXT: store <4 x i32> [[REG1698]], <4 x i32>* [[REG1696]], align 16 // CHECK-NEXT: [[REG1699:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1690]], align 16 // CHECK-NEXT: [[REG1700:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1699]] to <4 x i32> // CHECK-NEXT: [[REG1701:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1696]], align 16 -// CHECK-NEXT: [[REG1702:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sra(int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG1700]], <4 x i32> noundef [[REG1701]]) +// CHECK-NEXT: [[REG1702:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sra(int vector[4], unsigned int vector[4])(<4 x i32> [[REG1700]], <4 x i32> [[REG1701]]) // CHECK-NEXT: store <4 x i32> [[REG1702]], <4 x i32>* [[REG1703:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1704:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1703]], align 16 // CHECK-NEXT: [[REG1705:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1704]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG1705]] -// CHECK: define available_externally <2 x i64> @_mm_srai_epi16(<2 x i64> noundef [[REG1706:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG1707:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_srai_epi16(<2 x i64> [[REG1706:[0-9a-zA-Z_%.]+]], i32 signext [[REG1707:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1706]], <2 x i64>* [[REG1708:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG1707]], i32* [[REG1709:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store <8 x i16> , <8 x i16>* [[REG1710:[0-9a-zA-Z_%.]+]], align 16 @@ -2578,14 +2578,14 @@ test_sra() { // CHECK: [[REG1715]]: // CHECK-NEXT: [[REG1717:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1709]], align 4 // CHECK-NEXT: [[REG1718:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1717]] to i8 -// CHECK-NEXT: [[REG1719:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat_s16(signed char)(i8 noundef signext [[REG1718]]) +// CHECK-NEXT: [[REG1719:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat_s16(signed char)(i8 signext [[REG1718]]) // CHECK-NEXT: store <8 x i16> [[REG1719]], <8 x i16>* [[REG1710]], align 16 // CHECK-NEXT: br label %[[REG1720:[0-9a-zA-Z_%.]+]] // CHECK: [[REG1716]]: // CHECK-NEXT: [[REG1721:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1709]], align 4 // CHECK-NEXT: [[REG1722:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1721]] to i16 -// CHECK-NEXT: [[REG1723:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 noundef zeroext [[REG1722]]) +// CHECK-NEXT: [[REG1723:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 zeroext [[REG1722]]) // CHECK-NEXT: store <8 x i16> [[REG1723]], <8 x i16>* [[REG1710]], align 16 // CHECK-NEXT: br label %[[REG1720:[0-9a-zA-Z_%.]+]] @@ -2596,13 +2596,13 @@ test_sra() { // CHECK-NEXT: [[REG1724:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1708]], align 16 // CHECK-NEXT: [[REG1725:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1724]] to <8 x i16> // CHECK-NEXT: [[REG1726:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1710]], align 16 -// CHECK-NEXT: [[REG1727:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sra(short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG1725]], <8 x i16> noundef [[REG1726]]) +// CHECK-NEXT: [[REG1727:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sra(short vector[8], unsigned short vector[8])(<8 x i16> [[REG1725]], <8 x i16> [[REG1726]]) // CHECK-NEXT: store <8 x i16> [[REG1727]], <8 x i16>* [[REG1728:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1729:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1728]], align 16 // CHECK-NEXT: [[REG1730:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG1729]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG1730]] -// CHECK: define available_externally <2 x i64> @_mm_srai_epi32(<2 x i64> noundef [[REG1731:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG1732:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_srai_epi32(<2 x i64> [[REG1731:[0-9a-zA-Z_%.]+]], i32 signext [[REG1732:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1731]], <2 x i64>* [[REG1733:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG1732]], i32* [[REG1734:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store <4 x i32> , <4 x i32>* [[REG1735:[0-9a-zA-Z_%.]+]], align 16 @@ -2623,13 +2623,13 @@ test_sra() { // CHECK: [[REG1744]]: // CHECK-NEXT: [[REG1746:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1734]], align 4 // CHECK-NEXT: [[REG1747:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1746]] to i8 -// CHECK-NEXT: [[REG1748:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat_s32(signed char)(i8 noundef signext [[REG1747]]) +// CHECK-NEXT: [[REG1748:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat_s32(signed char)(i8 signext [[REG1747]]) // CHECK-NEXT: store <4 x i32> [[REG1748]], <4 x i32>* [[REG1735]], align 16 // CHECK-NEXT: br label %[[REG1749:[0-9a-zA-Z_%.]+]] // CHECK: [[REG1745]]: // CHECK-NEXT: [[REG1750:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1734]], align 4 -// CHECK-NEXT: [[REG1751:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 noundef zeroext [[REG1750]]) +// CHECK-NEXT: [[REG1751:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1750]]) // CHECK-NEXT: store <4 x i32> [[REG1751]], <4 x i32>* [[REG1735]], align 16 // CHECK-NEXT: br label %[[REG1749:[0-9a-zA-Z_%.]+]] @@ -2638,7 +2638,7 @@ test_sra() { // CHECK: [[REG1741]]: // CHECK-NEXT: [[REG1753:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1734]], align 4 -// CHECK-NEXT: [[REG1754:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 noundef zeroext [[REG1753]]) +// CHECK-NEXT: [[REG1754:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1753]]) // CHECK-NEXT: store <4 x i32> [[REG1754]], <4 x i32>* [[REG1735]], align 16 // CHECK-NEXT: br label %[[REG1752:[0-9a-zA-Z_%.]+]] @@ -2649,7 +2649,7 @@ test_sra() { // CHECK-NEXT: [[REG1755:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1733]], align 16 // CHECK-NEXT: [[REG1756:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1755]] to <4 x i32> // CHECK-NEXT: [[REG1757:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1735]], align 16 -// CHECK-NEXT: [[REG1758:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sra(int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG1756]], <4 x i32> noundef [[REG1757]]) +// CHECK-NEXT: [[REG1758:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sra(int vector[4], unsigned int vector[4])(<4 x i32> [[REG1756]], <4 x i32> [[REG1757]]) // CHECK-NEXT: store <4 x i32> [[REG1758]], <4 x i32>* [[REG1759:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1760:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1759]], align 16 // CHECK-NEXT: [[REG1761:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1760]] to <2 x i64> @@ -2668,84 +2668,84 @@ test_srl() { // CHECK-LABEL: @test_srl -// CHECK: define available_externally <2 x i64> @_mm_srl_epi16(<2 x i64> noundef [[REG1762:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1763:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_srl_epi16(<2 x i64> [[REG1762:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1763:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1762]], <2 x i64>* [[REG1764:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG1763]], <2 x i64>* [[REG1765:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <8 x i16> , <8 x i16>* [[REG1766:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1767:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1765]], align 16 // CHECK-NEXT: [[REG1768:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1767]] to <8 x i16> -// CHECK-LE-NEXT: [[REG1769:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int)(<8 x i16> noundef [[REG1768]], i32 noundef zeroext 0) -// CHECK-BE-NEXT: [[REG1769:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int)(<8 x i16> noundef [[REG1768]], i32 noundef zeroext 3) +// CHECK-LE-NEXT: [[REG1769:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int)(<8 x i16> [[REG1768]], i32 zeroext 0) +// CHECK-BE-NEXT: [[REG1769:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int)(<8 x i16> [[REG1768]], i32 zeroext 3) // CHECK-NEXT: store <8 x i16> [[REG1769]], <8 x i16>* [[REG1770:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1771:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1770]], align 16 -// CHECK-NEXT: [[REG1772:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmple(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG1771]], <8 x i16> noundef ) +// CHECK-NEXT: [[REG1772:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmple(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG1771]], <8 x i16> ) // CHECK-NEXT: store <8 x i16> [[REG1772]], <8 x i16>* [[REG1773:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1774:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1764]], align 16 // CHECK-NEXT: [[REG1775:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1774]] to <8 x i16> // CHECK-NEXT: [[REG1776:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1770]], align 16 -// CHECK-NEXT: [[REG1777:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sr(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG1775]], <8 x i16> noundef [[REG1776]]) +// CHECK-NEXT: [[REG1777:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sr(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG1775]], <8 x i16> [[REG1776]]) // CHECK-NEXT: store <8 x i16> [[REG1777]], <8 x i16>* [[REG1778:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1779:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1773]], align 16 // CHECK-NEXT: [[REG1780:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1778]], align 16 // CHECK-NEXT: [[REG1781:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1773]], align 16 -// CHECK-NEXT: [[REG1782:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sel(unsigned short vector[8], unsigned short vector[8], bool vector[8])(<8 x i16> noundef [[REG1779]], <8 x i16> noundef [[REG1780]], <8 x i16> noundef [[REG1781]]) +// CHECK-NEXT: [[REG1782:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sel(unsigned short vector[8], unsigned short vector[8], bool vector[8])(<8 x i16> [[REG1779]], <8 x i16> [[REG1780]], <8 x i16> [[REG1781]]) // CHECK-NEXT: store <8 x i16> [[REG1782]], <8 x i16>* [[REG1778]], align 16 // CHECK-NEXT: [[REG1783:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1778]], align 16 // CHECK-NEXT: [[REG1784:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG1783]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG1784]] -// CHECK: define available_externally <2 x i64> @_mm_srl_epi32(<2 x i64> noundef [[REG1785:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1786:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_srl_epi32(<2 x i64> [[REG1785:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1786:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1785]], <2 x i64>* [[REG1787:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG1786]], <2 x i64>* [[REG1788:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x i32> , <4 x i32>* [[REG1789:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1790:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1788]], align 16 // CHECK-NEXT: [[REG1791:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1790]] to <4 x i32> -// CHECK-LE-NEXT: [[REG1792:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat(unsigned int vector[4], unsigned int)(<4 x i32> noundef [[REG1791]], i32 noundef zeroext 0) -// CHECK-BE-NEXT: [[REG1792:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat(unsigned int vector[4], unsigned int)(<4 x i32> noundef [[REG1791]], i32 noundef zeroext 1) +// CHECK-LE-NEXT: [[REG1792:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat(unsigned int vector[4], unsigned int)(<4 x i32> [[REG1791]], i32 zeroext 0) +// CHECK-BE-NEXT: [[REG1792:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat(unsigned int vector[4], unsigned int)(<4 x i32> [[REG1791]], i32 zeroext 1) // CHECK-NEXT: store <4 x i32> [[REG1792]], <4 x i32>* [[REG1793:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1794:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1793]], align 16 -// CHECK-NEXT: [[REG1795:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmplt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG1794]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG1795:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmplt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> [[REG1794]], <4 x i32> ) // CHECK-NEXT: store <4 x i32> [[REG1795]], <4 x i32>* [[REG1796:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1797:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1787]], align 16 // CHECK-NEXT: [[REG1798:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1797]] to <4 x i32> // CHECK-NEXT: [[REG1799:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1793]], align 16 -// CHECK-NEXT: [[REG1800:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG1798]], <4 x i32> noundef [[REG1799]]) +// CHECK-NEXT: [[REG1800:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(unsigned int vector[4], unsigned int vector[4])(<4 x i32> [[REG1798]], <4 x i32> [[REG1799]]) // CHECK-NEXT: store <4 x i32> [[REG1800]], <4 x i32>* [[REG1801:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1802:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1796]], align 16 // CHECK-NEXT: [[REG1803:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1801]], align 16 // CHECK-NEXT: [[REG1804:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1796]], align 16 -// CHECK-NEXT: [[REG1805:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sel(unsigned int vector[4], unsigned int vector[4], bool vector[4])(<4 x i32> noundef [[REG1802]], <4 x i32> noundef [[REG1803]], <4 x i32> noundef [[REG1804]]) +// CHECK-NEXT: [[REG1805:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sel(unsigned int vector[4], unsigned int vector[4], bool vector[4])(<4 x i32> [[REG1802]], <4 x i32> [[REG1803]], <4 x i32> [[REG1804]]) // CHECK-NEXT: store <4 x i32> [[REG1805]], <4 x i32>* [[REG1801]], align 16 // CHECK-NEXT: [[REG1806:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1801]], align 16 // CHECK-NEXT: [[REG1807:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1806]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG1807]] -// CHECK: define available_externally <2 x i64> @_mm_srl_epi64(<2 x i64> noundef [[REG1808:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1809:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_srl_epi64(<2 x i64> [[REG1808:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1809:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1808]], <2 x i64>* [[REG1810:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG1809]], <2 x i64>* [[REG1811:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> , <2 x i64>* [[REG1812:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1813:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1811]], align 16 -// CHECK-NEXT: [[REG1814:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splat(unsigned long long vector[2], unsigned int)(<2 x i64> noundef [[REG1813]], i32 noundef zeroext 0) +// CHECK-NEXT: [[REG1814:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splat(unsigned long long vector[2], unsigned int)(<2 x i64> [[REG1813]], i32 zeroext 0) // CHECK-NEXT: store <2 x i64> [[REG1814]], <2 x i64>* [[REG1815:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1816:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1815]], align 16 -// CHECK-NEXT: [[REG1817:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmplt(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> noundef [[REG1816]], <2 x i64> noundef ) +// CHECK-NEXT: [[REG1817:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmplt(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> [[REG1816]], <2 x i64> ) // CHECK-NEXT: store <2 x i64> [[REG1817]], <2 x i64>* [[REG1818:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1819:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1810]], align 16 // CHECK-NEXT: [[REG1820:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1815]], align 16 -// CHECK-NEXT: [[REG1821:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_sr(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> noundef [[REG1819]], <2 x i64> noundef [[REG1820]]) +// CHECK-NEXT: [[REG1821:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_sr(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> [[REG1819]], <2 x i64> [[REG1820]]) // CHECK-NEXT: store <2 x i64> [[REG1821]], <2 x i64>* [[REG1822:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1823:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1818]], align 16 // CHECK-NEXT: [[REG1824:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1823]] to <2 x double> // CHECK-NEXT: [[REG1825:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1822]], align 16 // CHECK-NEXT: [[REG1826:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1825]] to <2 x double> // CHECK-NEXT: [[REG1827:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1818]], align 16 -// CHECK-NEXT: [[REG1828:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_sel(double vector[2], double vector[2], bool vector[2])(<2 x double> noundef [[REG1824]], <2 x double> noundef [[REG1826]], <2 x i64> noundef [[REG1827]]) +// CHECK-NEXT: [[REG1828:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_sel(double vector[2], double vector[2], bool vector[2])(<2 x double> [[REG1824]], <2 x double> [[REG1826]], <2 x i64> [[REG1827]]) // CHECK-NEXT: [[REG1829:[0-9a-zA-Z_%.]+]] = bitcast <2 x double> [[REG1828]] to <2 x i64> // CHECK-NEXT: store <2 x i64> [[REG1829]], <2 x i64>* [[REG1822]], align 16 // CHECK-NEXT: [[REG1830:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1822]], align 16 // CHECK-NEXT: ret <2 x i64> [[REG1830]] -// CHECK: define available_externally <2 x i64> @_mm_srli_epi16(<2 x i64> noundef [[REG1831:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG1832:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_srli_epi16(<2 x i64> [[REG1831:[0-9a-zA-Z_%.]+]], i32 signext [[REG1832:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1831]], <2 x i64>* [[REG1833:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG1832]], i32* [[REG1834:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store <8 x i16> zeroinitializer, <8 x i16>* [[REG1835:[0-9a-zA-Z_%.]+]], align 16 @@ -2759,20 +2759,20 @@ test_srl() { // CHECK: [[REG1840]]: // CHECK-NEXT: [[REG1842:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1834]], align 4 // CHECK-NEXT: [[REG1843:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1842]] to i8 -// CHECK-NEXT: [[REG1844:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat_s16(signed char)(i8 noundef signext [[REG1843]]) +// CHECK-NEXT: [[REG1844:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat_s16(signed char)(i8 signext [[REG1843]]) // CHECK-NEXT: store <8 x i16> [[REG1844]], <8 x i16>* [[REG1845:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: br label %[[REG1846:[0-9a-zA-Z_%.]+]] // CHECK: [[REG1841]]: // CHECK-NEXT: [[REG1847:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1834]], align 4 // CHECK-NEXT: [[REG1848:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1847]] to i16 -// CHECK-NEXT: [[REG1849:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 noundef zeroext [[REG1848]]) +// CHECK-NEXT: [[REG1849:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 zeroext [[REG1848]]) // CHECK-NEXT: store <8 x i16> [[REG1849]], <8 x i16>* [[REG1845]], align 16 // CHECK-NEXT: br label %[[REG1846:[0-9a-zA-Z_%.]+]] // CHECK: [[REG1846]]: // CHECK-NEXT: [[REG1850:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1833]], align 16 // CHECK-NEXT: [[REG1851:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1850]] to <8 x i16> // CHECK-NEXT: [[REG1852:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1845]], align 16 -// CHECK-NEXT: [[REG1853:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sr(short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG1851]], <8 x i16> noundef [[REG1852]]) +// CHECK-NEXT: [[REG1853:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sr(short vector[8], unsigned short vector[8])(<8 x i16> [[REG1851]], <8 x i16> [[REG1852]]) // CHECK-NEXT: store <8 x i16> [[REG1853]], <8 x i16>* [[REG1835]], align 16 // CHECK-NEXT: br label %[[REG1839:[0-9a-zA-Z_%.]+]] // CHECK: [[REG1839]]: @@ -2780,7 +2780,7 @@ test_srl() { // CHECK-NEXT: [[REG1855:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG1854]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG1855]] -// CHECK: define available_externally <2 x i64> @_mm_srli_epi32(<2 x i64> noundef [[REG1856:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG1857:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_srli_epi32(<2 x i64> [[REG1856:[0-9a-zA-Z_%.]+]], i32 signext [[REG1857:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1856]], <2 x i64>* [[REG1858:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG1857]], i32* [[REG1859:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* [[REG1860:[0-9a-zA-Z_%.]+]], align 16 @@ -2801,13 +2801,13 @@ test_srl() { // CHECK: [[REG1869]]: // CHECK-NEXT: [[REG1871:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1859]], align 4 // CHECK-NEXT: [[REG1872:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1871]] to i8 -// CHECK-NEXT: [[REG1873:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat_s32(signed char)(i8 noundef signext [[REG1872]]) +// CHECK-NEXT: [[REG1873:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat_s32(signed char)(i8 signext [[REG1872]]) // CHECK-NEXT: store <4 x i32> [[REG1873]], <4 x i32>* [[REG1874:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: br label %[[REG1875:[0-9a-zA-Z_%.]+]] // CHECK: [[REG1870]]: // CHECK-NEXT: [[REG1876:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1859]], align 4 -// CHECK-NEXT: [[REG1877:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 noundef zeroext [[REG1876]]) +// CHECK-NEXT: [[REG1877:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1876]]) // CHECK-NEXT: store <4 x i32> [[REG1877]], <4 x i32>* [[REG1874]], align 16 // CHECK-NEXT: br label %[[REG1875:[0-9a-zA-Z_%.]+]] @@ -2816,7 +2816,7 @@ test_srl() { // CHECK: [[REG1866]]: // CHECK-NEXT: [[REG1879:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1859]], align 4 -// CHECK-NEXT: [[REG1880:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 noundef zeroext [[REG1879]]) +// CHECK-NEXT: [[REG1880:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1879]]) // CHECK-NEXT: store <4 x i32> [[REG1880]], <4 x i32>* [[REG1874]], align 16 // CHECK-NEXT: br label %[[REG1878:[0-9a-zA-Z_%.]+]] @@ -2824,7 +2824,7 @@ test_srl() { // CHECK-NEXT: [[REG1881:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1858]], align 16 // CHECK-NEXT: [[REG1882:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1881]] to <4 x i32> // CHECK-NEXT: [[REG1883:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1874]], align 16 -// CHECK-NEXT: [[REG1884:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG1882]], <4 x i32> noundef [[REG1883]]) +// CHECK-NEXT: [[REG1884:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG1882]], <4 x i32> [[REG1883]]) // CHECK-NEXT: store <4 x i32> [[REG1884]], <4 x i32>* [[REG1860]], align 16 // CHECK-NEXT: br label %[[REG1864:[0-9a-zA-Z_%.]+]] @@ -2833,7 +2833,7 @@ test_srl() { // CHECK-NEXT: [[REG1886:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1885]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG1886]] -// CHECK: define available_externally <2 x i64> @_mm_srli_epi64(<2 x i64> noundef [[REG1887:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG1888:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_srli_epi64(<2 x i64> [[REG1887:[0-9a-zA-Z_%.]+]], i32 signext [[REG1888:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1887]], <2 x i64>* [[REG1889:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG1888]], i32* [[REG1890:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* [[REG1891:[0-9a-zA-Z_%.]+]], align 16 @@ -2854,7 +2854,7 @@ test_srl() { // CHECK: [[REG1900]]: // CHECK-NEXT: [[REG1902:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1890]], align 4 // CHECK-NEXT: [[REG1903:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1902]] to i8 -// CHECK-NEXT: [[REG1904:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat_s32(signed char)(i8 noundef signext [[REG1903]]) +// CHECK-NEXT: [[REG1904:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat_s32(signed char)(i8 signext [[REG1903]]) // CHECK-NEXT: [[REG1905:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1904]] to <2 x i64> // CHECK-NEXT: store <2 x i64> [[REG1905]], <2 x i64>* [[REG1906:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: br label %[[REG1907:[0-9a-zA-Z_%.]+]] @@ -2862,7 +2862,7 @@ test_srl() { // CHECK: [[REG1901]]: // CHECK-NEXT: [[REG1908:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1890]], align 4 // CHECK-NEXT: [[REG1909:[0-9a-zA-Z_%.]+]] = sext i32 [[REG1908]] to i64 -// CHECK-NEXT: [[REG1910:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG1909]]) +// CHECK-NEXT: [[REG1910:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG1909]]) // CHECK-NEXT: store <2 x i64> [[REG1910]], <2 x i64>* [[REG1906]], align 16 // CHECK-NEXT: br label %[[REG1907:[0-9a-zA-Z_%.]+]] @@ -2871,7 +2871,7 @@ test_srl() { // CHECK: [[REG1897]]: // CHECK-NEXT: [[REG1912:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1890]], align 4 -// CHECK-NEXT: [[REG1913:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 noundef zeroext [[REG1912]]) +// CHECK-NEXT: [[REG1913:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1912]]) // CHECK-NEXT: [[REG1914:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1913]] to <2 x i64> // CHECK-NEXT: store <2 x i64> [[REG1914]], <2 x i64>* [[REG1906]], align 16 // CHECK-NEXT: br label %[[REG1911:[0-9a-zA-Z_%.]+]] @@ -2879,7 +2879,7 @@ test_srl() { // CHECK: [[REG1911]]: // CHECK-NEXT: [[REG1915:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1889]], align 16 // CHECK-NEXT: [[REG1916:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1906]], align 16 -// CHECK-NEXT: [[REG1917:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_sr(long long vector[2], unsigned long long vector[2])(<2 x i64> noundef [[REG1915]], <2 x i64> noundef [[REG1916]]) +// CHECK-NEXT: [[REG1917:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_sr(long long vector[2], unsigned long long vector[2])(<2 x i64> [[REG1915]], <2 x i64> [[REG1916]]) // CHECK-NEXT: store <2 x i64> [[REG1917]], <2 x i64>* [[REG1891]], align 16 // CHECK-NEXT: br label %[[REG1895:[0-9a-zA-Z_%.]+]] @@ -2908,25 +2908,25 @@ test_store() { // CHECK-LABEL: @test_store -// CHECK: define available_externally void @_mm_store_pd(double* noundef [[REG1920:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1921:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_store_pd(double* [[REG1920:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1921:[0-9a-zA-Z_%.]+]]) // CHECK: store double* [[REG1920]], double** [[REG1922:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <2 x double> [[REG1921]], <2 x double>* [[REG1923:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1924:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1923]], align 16 // CHECK-NEXT: [[REG1925:[0-9a-zA-Z_%.]+]] = bitcast <2 x double> [[REG1924]] to <16 x i8> // CHECK-NEXT: [[REG1926:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG1922]], align 8 // CHECK-NEXT: [[REG1927:[0-9a-zA-Z_%.]+]] = bitcast double* [[REG1926]] to <16 x i8>* -// CHECK-NEXT: call void @vec_st(unsigned char vector[16], long, unsigned char vector[16]*)(<16 x i8> noundef [[REG1925]], i64 noundef 0, <16 x i8>* noundef [[REG1927]]) +// CHECK-NEXT: call void @vec_st(unsigned char vector[16], long, unsigned char vector[16]*)(<16 x i8> [[REG1925]], i64 0, <16 x i8>* [[REG1927]]) // CHECK-NEXT: ret void -// CHECK: define available_externally void @_mm_store_pd1(double* noundef [[REG1928:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1929:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_store_pd1(double* [[REG1928:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1929:[0-9a-zA-Z_%.]+]]) // CHECK: store double* [[REG1928]], double** [[REG1930:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <2 x double> [[REG1929]], <2 x double>* [[REG1931:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1932:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG1930]], align 8 // CHECK-NEXT: [[REG1933:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1931]], align 16 -// CHECK-NEXT: call void @_mm_store1_pd(double* noundef [[REG1932]], <2 x double> noundef [[REG1933]]) +// CHECK-NEXT: call void @_mm_store1_pd(double* [[REG1932]], <2 x double> [[REG1933]]) // CHECK-NEXT: ret void -// CHECK: define available_externally void @_mm_store_sd(double* noundef [[REG1934:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1935:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_store_sd(double* [[REG1934:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1935:[0-9a-zA-Z_%.]+]]) // CHECK: store double* [[REG1934]], double** [[REG1936:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <2 x double> [[REG1935]], <2 x double>* [[REG1937:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1938:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1937]], align 16 @@ -2935,26 +2935,26 @@ test_store() { // CHECK-NEXT: store double [[REG1939]], double* [[REG1940]], align 8 // CHECK-NEXT: ret void -// CHECK: define available_externally void @_mm_store_si128(<2 x i64>* noundef [[REG1941:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1942:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_store_si128(<2 x i64>* [[REG1941:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1942:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64>* [[REG1941]], <2 x i64>** [[REG1943:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <2 x i64> [[REG1942]], <2 x i64>* [[REG1944:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1945:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1944]], align 16 // CHECK-NEXT: [[REG1946:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1945]] to <16 x i8> // CHECK-NEXT: [[REG1947:[0-9a-zA-Z_%.]+]] = load <2 x i64>*, <2 x i64>** [[REG1943]], align 8 // CHECK-NEXT: [[REG1948:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64>* [[REG1947]] to <16 x i8>* -// CHECK-NEXT: call void @vec_st(unsigned char vector[16], long, unsigned char vector[16]*)(<16 x i8> noundef [[REG1946]], i64 noundef 0, <16 x i8>* noundef [[REG1948]]) +// CHECK-NEXT: call void @vec_st(unsigned char vector[16], long, unsigned char vector[16]*)(<16 x i8> [[REG1946]], i64 0, <16 x i8>* [[REG1948]]) // CHECK-NEXT: ret void -// CHECK: define available_externally void @_mm_store1_pd(double* noundef [[REG1949:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1950:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_store1_pd(double* [[REG1949:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1950:[0-9a-zA-Z_%.]+]]) // CHECK: store double* [[REG1949]], double** [[REG1951:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <2 x double> [[REG1950]], <2 x double>* [[REG1952:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1953:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG1951]], align 8 // CHECK-NEXT: [[REG1954:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1952]], align 16 -// CHECK-NEXT: [[REG1955:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splat(double vector[2], unsigned int)(<2 x double> noundef [[REG1954]], i32 noundef zeroext 0) -// CHECK-NEXT: call void @_mm_store_pd(double* noundef [[REG1953]], <2 x double> noundef [[REG1955]]) +// CHECK-NEXT: [[REG1955:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splat(double vector[2], unsigned int)(<2 x double> [[REG1954]], i32 zeroext 0) +// CHECK-NEXT: call void @_mm_store_pd(double* [[REG1953]], <2 x double> [[REG1955]]) // CHECK-NEXT: ret void -// CHECK: define available_externally void @_mm_storeh_pd(double* noundef [[REG1956:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1957:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_storeh_pd(double* [[REG1956:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1957:[0-9a-zA-Z_%.]+]]) // CHECK: store double* [[REG1956]], double** [[REG1958:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <2 x double> [[REG1957]], <2 x double>* [[REG1959:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1960:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1959]], align 16 @@ -2963,7 +2963,7 @@ test_store() { // CHECK-NEXT: store double [[REG1961]], double* [[REG1962]], align 8 // CHECK-NEXT: ret void -// CHECK: define available_externally void @_mm_storel_epi64(<2 x i64>* noundef [[REG1963:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1964:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_storel_epi64(<2 x i64>* [[REG1963:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1964:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64>* [[REG1963]], <2 x i64>** [[REG1965:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <2 x i64> [[REG1964]], <2 x i64>* [[REG1966:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1967:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1966]], align 16 @@ -2973,15 +2973,15 @@ test_store() { // CHECK-NEXT: store i64 [[REG1968]], i64* [[REG1970]], align 8 // CHECK-NEXT: ret void -// CHECK: define available_externally void @_mm_storel_pd(double* noundef [[REG1971:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1972:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_storel_pd(double* [[REG1971:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1972:[0-9a-zA-Z_%.]+]]) // CHECK: store double* [[REG1971]], double** [[REG1973:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <2 x double> [[REG1972]], <2 x double>* [[REG1974:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1975:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG1973]], align 8 // CHECK-NEXT: [[REG1976:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1974]], align 16 -// CHECK-NEXT: call void @_mm_store_sd(double* noundef [[REG1975]], <2 x double> noundef [[REG1976]]) +// CHECK-NEXT: call void @_mm_store_sd(double* [[REG1975]], <2 x double> [[REG1976]]) // CHECK-NEXT: ret void -// CHECK: define available_externally void @_mm_storer_pd(double* noundef [[REG1977:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1978:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_storer_pd(double* [[REG1977:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1978:[0-9a-zA-Z_%.]+]]) // CHECK: store double* [[REG1977]], double** [[REG1979:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <2 x double> [[REG1978]], <2 x double>* [[REG1980:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1981:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG1979]], align 8 @@ -2991,10 +2991,10 @@ test_store() { // CHECK-NEXT: [[REG1985:[0-9a-zA-Z_%.]+]] = bitcast <2 x double> [[REG1983]] to <2 x i64> // CHECK-NEXT: [[REG1986:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG1984]], <2 x i64> [[REG1985]], <2 x i32> // CHECK-NEXT: [[REG1987:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1986]] to <2 x double> -// CHECK-NEXT: call void @_mm_store_pd(double* noundef [[REG1981]], <2 x double> noundef [[REG1987]]) +// CHECK-NEXT: call void @_mm_store_pd(double* [[REG1981]], <2 x double> [[REG1987]]) // CHECK-NEXT: ret void -// CHECK: define available_externally void @_mm_storeu_pd(double* noundef [[REG1988:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG1989:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_storeu_pd(double* [[REG1988:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1989:[0-9a-zA-Z_%.]+]]) // CHECK: store double* [[REG1988]], double** [[REG1990:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <2 x double> [[REG1989]], <2 x double>* [[REG1991:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1992:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1991]], align 16 @@ -3003,7 +3003,7 @@ test_store() { // CHECK-NEXT: store <2 x double> [[REG1992]], <2 x double>* [[REG1994]], align 1 // CHECK-NEXT: ret void -// CHECK: define available_externally void @_mm_storeu_si128(<2 x i64>* noundef [[REG1995:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG1996:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_storeu_si128(<2 x i64>* [[REG1995:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG1996:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64>* [[REG1995]], <2 x i64>** [[REG1997:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <2 x i64> [[REG1996]], <2 x i64>* [[REG1998:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1999:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1998]], align 16 @@ -3021,7 +3021,7 @@ test_stream() { // CHECK-LABEL: @test_stream -// CHECK: define available_externally void @_mm_stream_pd(double* noundef [[REG2001:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG2002:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_stream_pd(double* [[REG2001:[0-9a-zA-Z_%.]+]], <2 x double> [[REG2002:[0-9a-zA-Z_%.]+]]) // CHECK: store double* [[REG2001]], double** [[REG2003:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <2 x double> [[REG2002]], <2 x double>* [[REG2004:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG2005:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG2003]], align 8 @@ -3032,7 +3032,7 @@ test_stream() { // CHECK-NEXT: store <2 x double> [[REG2006]], <2 x double>* [[REG2008]], align 16 // CHECK-NEXT: ret void -// CHECK: define available_externally void @_mm_stream_si128(<2 x i64>* noundef [[REG2009:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG2010:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_stream_si128(<2 x i64>* [[REG2009:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG2010:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64>* [[REG2009]], <2 x i64>** [[REG2011:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <2 x i64> [[REG2010]], <2 x i64>* [[REG2012:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG2013:[0-9a-zA-Z_%.]+]] = load <2 x i64>*, <2 x i64>** [[REG2011]], align 8 @@ -3042,7 +3042,7 @@ test_stream() { // CHECK-NEXT: store <2 x i64> [[REG2014]], <2 x i64>* [[REG2015]], align 16 // CHECK-NEXT: ret void -// CHECK: define available_externally void @_mm_stream_si32(i32* noundef [[REG2016:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG2017:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_stream_si32(i32* [[REG2016:[0-9a-zA-Z_%.]+]], i32 signext [[REG2017:[0-9a-zA-Z_%.]+]]) // CHECK: store i32* [[REG2016]], i32** [[REG2018:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i32 [[REG2017]], i32* [[REG2019:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG2020:[0-9a-zA-Z_%.]+]] = load i32*, i32** [[REG2018]], align 8 @@ -3052,7 +3052,7 @@ test_stream() { // CHECK-NEXT: store i32 [[REG2021]], i32* [[REG2022]], align 4 // CHECK-NEXT: ret void -// CHECK: define available_externally void @_mm_stream_si64(i64* noundef [[REG2023:[0-9a-zA-Z_%.]+]], i64 noundef [[REG2024:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally void @_mm_stream_si64(i64* [[REG2023:[0-9a-zA-Z_%.]+]], i64 [[REG2024:[0-9a-zA-Z_%.]+]]) // CHECK: store i64* [[REG2023]], i64** [[REG2025:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG2024]], i64* [[REG2026:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG2027:[0-9a-zA-Z_%.]+]] = load i64*, i64** [[REG2025]], align 8 @@ -3102,7 +3102,7 @@ test_sub() { // CHECK: [[REG2037:[0-9a-zA-Z_%.]+]] = fsub <2 x double> {{[0-9a-zA-Z_%.]+}}, {{[0-9a-zA-Z_%.]+}} // CHECK-NEXT: ret <2 x double> [[REG2037]] -// CHECK: define available_externally <2 x double> @_mm_sub_sd(<2 x double> noundef [[REG2038:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG2039:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x double> @_mm_sub_sd(<2 x double> [[REG2038:[0-9a-zA-Z_%.]+]], <2 x double> [[REG2039:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG2038]], <2 x double>* [[REG2040:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG2039]], <2 x double>* [[REG2041:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG2042:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG2040]], align 16 @@ -3152,7 +3152,7 @@ test_ucomi() { // CHECK-LABEL: @test_ucomi -// CHECK: define available_externally signext i32 @_mm_ucomieq_sd(<2 x double> noundef [[REG2059:[0-9a-zA-Z_%.]+]], <2 x double> noundef [[REG2060:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally signext i32 @_mm_ucomieq_sd(<2 x double> [[REG2059:[0-9a-zA-Z_%.]+]], <2 x double> [[REG2060:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x double> [[REG2059]], <2 x double>* [[REG2061:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x double> [[REG2060]], <2 x double>* [[REG2062:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG2063:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG2061]], align 16 diff --git a/clang/test/CodeGen/ppc-mm-malloc-le.c b/clang/test/CodeGen/ppc-mm-malloc-le.c index f68577c8edcddf789d6cc922c6a3279145919088..ba888afcd194f8e5a11056aa3f0605d410701083 100644 --- a/clang/test/CodeGen/ppc-mm-malloc-le.c +++ b/clang/test/CodeGen/ppc-mm-malloc-le.c @@ -19,7 +19,7 @@ test_mm_malloc() { // CHECK-LABEL: @test_mm_malloc -// CHECK: define internal i8* @_mm_malloc(i64 noundef [[REG1:[0-9a-zA-Z_%.]+]], i64 noundef [[REG2:[0-9a-zA-Z_%.]+]]) +// CHECK: define internal i8* @_mm_malloc(i64 [[REG1:[0-9a-zA-Z_%.]+]], i64 [[REG2:[0-9a-zA-Z_%.]+]]) // CHECK: [[REG3:[0-9a-zA-Z_%.]+]] = alloca i8*, align 8 // CHECK: store i64 [[REG1]], i64* [[REG4:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG2]], i64* [[REG5:[0-9a-zA-Z_%.]+]], align 8 @@ -35,7 +35,7 @@ test_mm_malloc() { // CHECK: [[REG24]]: // CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG5]], align 8 // CHECK-NEXT: [[REG27:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG4]], align 8 -// CHECK-NEXT: [[REG28:[0-9a-zA-Z_%.]+]] = call signext i32 @posix_memalign(i8** noundef [[REG29:[0-9a-zA-Z_%.]+]], i64 noundef [[REG26]], i64 noundef [[REG27]]) +// CHECK-NEXT: [[REG28:[0-9a-zA-Z_%.]+]] = call signext i32 @posix_memalign(i8** [[REG29:[0-9a-zA-Z_%.]+]], i64 [[REG26]], i64 [[REG27]]) // CHECK-NEXT: [[REG30:[0-9a-zA-Z_%.]+]] = icmp eq i32 [[REG28]], 0 // CHECK-NEXT: br i1 [[REG30]], label %[[REG31:[0-9a-zA-Z_%.]+]], label %[[REG32:[0-9a-zA-Z_%.]+]] // CHECK: [[REG31]]: @@ -49,8 +49,8 @@ test_mm_malloc() { // CHECK-NEXT: [[REG34:[0-9a-zA-Z_%.]+]] = load i8*, i8** [[REG3]], align 8 // CHECK-NEXT: ret i8* [[REG34]] -// CHECK: define internal void @_mm_free(i8* noundef [[REG35:[0-9a-zA-Z_%.]+]]) +// CHECK: define internal void @_mm_free(i8* [[REG35:[0-9a-zA-Z_%.]+]]) // CHECK: store i8* [[REG35]], i8** [[REG36:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG37:[0-9a-zA-Z_%.]+]] = load i8*, i8** [[REG36]], align 8 -// CHECK-NEXT: call void @free(i8* noundef [[REG37]]) +// CHECK-NEXT: call void @free(i8* [[REG37]]) // CHECK-NEXT: ret void diff --git a/clang/test/CodeGen/ppc-mm-malloc.c b/clang/test/CodeGen/ppc-mm-malloc.c index 25711e80fffd2e83294c27aa184c2c07273423f2..6e8f6807b50bbc4e375e4c8180538a02ef63ff6f 100644 --- a/clang/test/CodeGen/ppc-mm-malloc.c +++ b/clang/test/CodeGen/ppc-mm-malloc.c @@ -19,7 +19,7 @@ test_mm_malloc() { // CHECK-LABEL: @test_mm_malloc -// CHECK: define internal i8* @_mm_malloc(i64 noundef [[REG1:[0-9a-zA-Z_%.]+]], i64 noundef [[REG2:[0-9a-zA-Z_%.]+]]) +// CHECK: define internal i8* @_mm_malloc(i64 [[REG1:[0-9a-zA-Z_%.]+]], i64 [[REG2:[0-9a-zA-Z_%.]+]]) // CHECK: [[REG3:[0-9a-zA-Z_%.]+]] = alloca i8*, align 8 // CHECK: store i64 [[REG1]], i64* [[REG4:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG2]], i64* [[REG5:[0-9a-zA-Z_%.]+]], align 8 @@ -35,7 +35,7 @@ test_mm_malloc() { // CHECK: [[REG24]]: // CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG5]], align 8 // CHECK-NEXT: [[REG27:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG4]], align 8 -// CHECK-NEXT: [[REG28:[0-9a-zA-Z_%.]+]] = call signext i32 @posix_memalign(i8** noundef [[REG29:[0-9a-zA-Z_%.]+]], i64 noundef [[REG26]], i64 noundef [[REG27]]) +// CHECK-NEXT: [[REG28:[0-9a-zA-Z_%.]+]] = call signext i32 @posix_memalign(i8** [[REG29:[0-9a-zA-Z_%.]+]], i64 [[REG26]], i64 [[REG27]]) // CHECK-NEXT: [[REG30:[0-9a-zA-Z_%.]+]] = icmp eq i32 [[REG28]], 0 // CHECK-NEXT: br i1 [[REG30]], label %[[REG31:[0-9a-zA-Z_%.]+]], label %[[REG32:[0-9a-zA-Z_%.]+]] // CHECK: [[REG31]]: @@ -49,8 +49,8 @@ test_mm_malloc() { // CHECK-NEXT: [[REG34:[0-9a-zA-Z_%.]+]] = load i8*, i8** [[REG3]], align 8 // CHECK-NEXT: ret i8* [[REG34]] -// CHECK: define internal void @_mm_free(i8* noundef [[REG35:[0-9a-zA-Z_%.]+]]) +// CHECK: define internal void @_mm_free(i8* [[REG35:[0-9a-zA-Z_%.]+]]) // CHECK: store i8* [[REG35]], i8** [[REG36:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG37:[0-9a-zA-Z_%.]+]] = load i8*, i8** [[REG36]], align 8 -// CHECK-NEXT: call void @free(i8* noundef [[REG37]]) +// CHECK-NEXT: call void @free(i8* [[REG37]]) // CHECK-NEXT: ret void diff --git a/clang/test/CodeGen/ppc-mmintrin.c b/clang/test/CodeGen/ppc-mmintrin.c index e1f3abbe00f1f9eea7a24552e41ffb62b942a8b4..0a43f32fb0b07d799de720020907064c11d65e42 100644 --- a/clang/test/CodeGen/ppc-mmintrin.c +++ b/clang/test/CodeGen/ppc-mmintrin.c @@ -43,7 +43,7 @@ test_add() { // CHECK-P9-NEXT: store <4 x i32> [[REG6]], <4 x i32>* [[REG7:[0-9a-zA-Z_%.]+]], align 16 // CHECK-P9-NEXT: [[REG8:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG3]], align 16 // CHECK-P9-NEXT: [[REG9:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG7]], align 16 -// CHECK-P9-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> noundef [[REG8]], <4 x i32> noundef [[REG9]]) +// CHECK-P9-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG8]], <4 x i32> [[REG9]]) // CHECK-P9-NEXT: store <4 x i32> [[REG10]], <4 x i32>* [[REG11:[0-9a-zA-Z_%.]+]], align 16 // CHECK-P9-NEXT: [[REG12:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG11]], align 16 // CHECK-P9-NEXT: [[REG13:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> %6 to <2 x i64> @@ -70,7 +70,7 @@ test_add() { // CHECK-NEXT: store <8 x i16> [[REG27]], <8 x i16>* [[REG28:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG29:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG25]], align 16 // CHECK-NEXT: [[REG30:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG28]], align 16 -// CHECK-NEXT: call <8 x i16> @vec_add(short vector[8], short vector[8])(<8 x i16> noundef [[REG29]], <8 x i16> noundef [[REG30]]) +// CHECK-NEXT: call <8 x i16> @vec_add(short vector[8], short vector[8])(<8 x i16> [[REG29]], <8 x i16> [[REG30]]) // CHECK: define available_externally i64 @_mm_add_pi8 // CHECK: [[REG31:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats @@ -81,7 +81,7 @@ test_add() { // CHECK-NEXT: store <16 x i8> [[REG35]], <16 x i8>* [[REG36:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG37:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG33]], align 16 // CHECK-NEXT: [[REG38:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG36]], align 16 -// CHECK-NEXT: call <16 x i8> @vec_add(signed char vector[16], signed char vector[16])(<16 x i8> noundef [[REG37]], <16 x i8> noundef [[REG38]]) +// CHECK-NEXT: call <16 x i8> @vec_add(signed char vector[16], signed char vector[16])(<16 x i8> [[REG37]], <16 x i8> [[REG38]]) // CHECK: define available_externally i64 @_mm_adds_pu16 // CHECK: [[REG39:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats @@ -92,7 +92,7 @@ test_add() { // CHECK-NEXT: store <8 x i16> [[REG43]], <8 x i16>* [[REG44:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG45:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG41]], align 16 // CHECK-NEXT: [[REG46:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG44]], align 16 -// CHECK-NEXT: call <8 x i16> @vec_adds(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG45]], <8 x i16> noundef [[REG46]]) +// CHECK-NEXT: call <8 x i16> @vec_adds(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG45]], <8 x i16> [[REG46]]) // CHECK: define available_externally i64 @_mm_adds_pu8 // CHECK: [[REG47:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats @@ -103,7 +103,7 @@ test_add() { // CHECK-NEXT: store <16 x i8> [[REG51]], <16 x i8>* [[REG52:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG53:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG49]], align 16 // CHECK-NEXT: [[REG54:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG52]], align 16 -// CHECK-NEXT: call <16 x i8> @vec_adds(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG53]], <16 x i8> noundef [[REG54]]) +// CHECK-NEXT: call <16 x i8> @vec_adds(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG53]], <16 x i8> [[REG54]]) // CHECK: define available_externally i64 @_mm_adds_pi16 // CHECK: [[REG55:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats @@ -114,7 +114,7 @@ test_add() { // CHECK-NEXT: store <8 x i16> [[REG59]], <8 x i16>* [[REG60:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG61:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG57]], align 16 // CHECK-NEXT: [[REG62:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG60]], align 16 -// CHECK-NEXT: call <8 x i16> @vec_adds(short vector[8], short vector[8])(<8 x i16> noundef [[REG61]], <8 x i16> noundef [[REG62]]) +// CHECK-NEXT: call <8 x i16> @vec_adds(short vector[8], short vector[8])(<8 x i16> [[REG61]], <8 x i16> [[REG62]]) // CHECK: define available_externally i64 @_mm_adds_pi8 // CHECK: [[REG63:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats @@ -125,7 +125,7 @@ test_add() { // CHECK-NEXT: store <16 x i8> [[REG67]], <16 x i8>* [[REG68:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG69:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG65]], align 16 // CHECK-NEXT: [[REG70:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG68]], align 16 -// CHECK-NEXT: call <16 x i8> @vec_adds(signed char vector[16], signed char vector[16])(<16 x i8> noundef [[REG69]], <16 x i8> noundef [[REG70]]) +// CHECK-NEXT: call <16 x i8> @vec_adds(signed char vector[16], signed char vector[16])(<16 x i8> [[REG69]], <16 x i8> [[REG70]]) void __attribute__((noinline)) test_alt_name_add() { @@ -190,7 +190,7 @@ test_cmp() { // CHECK-P9-NEXT: store <4 x i32> [[REG82]], <4 x i32>* [[REG83:[0-9a-zA-Z_%.]+]] // CHECK-P9-NEXT: [[REG84:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG80]] // CHECK-P9-NEXT: [[REG85:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG83]] -// CHECK-P9-NEXT: call <4 x i32> @vec_cmpeq(int vector[4], int vector[4])(<4 x i32> noundef [[REG84]], <4 x i32> noundef [[REG85]]) +// CHECK-P9-NEXT: call <4 x i32> @vec_cmpeq(int vector[4], int vector[4])(<4 x i32> [[REG84]], <4 x i32> [[REG85]]) // CHECK-P8-COUNT-2: {{[0-9a-zA-Z_%.]+}} = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}} // CHECK-P8: [[REG86:[0-9a-zA-Z_%.]+]] = icmp eq i32 {{[0-9a-zA-Z_%.]+}}, {{[0-9a-zA-Z_%.]+}} @@ -209,7 +209,7 @@ test_cmp() { // CHECK-NEXT: store <8 x i16> [[REG92]], <8 x i16>* [[REG93:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG94:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG90]], align 16 // CHECK-NEXT: [[REG95:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG93]], align 16 -// CHECK-NEXT: call <8 x i16> @vec_cmpeq(short vector[8], short vector[8])(<8 x i16> noundef [[REG94]], <8 x i16> noundef [[REG95]]) +// CHECK-NEXT: call <8 x i16> @vec_cmpeq(short vector[8], short vector[8])(<8 x i16> [[REG94]], <8 x i16> [[REG95]]) // CHECK: define available_externally i64 @_mm_cmpeq_pi8 // CHECK: call i64 asm "cmpb $0,$1,$2;\0A", "=r,r,r" @@ -227,7 +227,7 @@ test_cmp() { // CHECK-P9-NEXT: store <4 x i32> [[REG102]], <4 x i32>* [[REG103:[0-9a-zA-Z_%.]+]] // CHECK-P9-NEXT: [[REG104:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG100]] // CHECK-P9-NEXT: [[REG105:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG103]] -// CHECK-P9-NEXT: call <4 x i32> @vec_cmpgt(int vector[4], int vector[4])(<4 x i32> noundef [[REG104]], <4 x i32> noundef [[REG85]]) +// CHECK-P9-NEXT: call <4 x i32> @vec_cmpgt(int vector[4], int vector[4])(<4 x i32> [[REG104]], <4 x i32> [[REG85]]) // CHECK-P8-COUNT-2: {{[0-9a-zA-Z_%.]+}} = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}} // CHECK-P8: [[REG106:[0-9a-zA-Z_%.]+]] = icmp sgt i32 {{[0-9a-zA-Z_%.]+}}, {{[0-9a-zA-Z_%.]+}} @@ -246,7 +246,7 @@ test_cmp() { // CHECK-NEXT: store <8 x i16> [[REG112]], <8 x i16>* [[REG113:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG114:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG110]] // CHECK-NEXT: [[REG115:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG113]] -// CHECK-NEXT: call <8 x i16> @vec_cmpgt(short vector[8], short vector[8])(<8 x i16> noundef [[REG114]], <8 x i16> noundef [[REG115]]) +// CHECK-NEXT: call <8 x i16> @vec_cmpgt(short vector[8], short vector[8])(<8 x i16> [[REG114]], <8 x i16> [[REG115]]) // CHECK: define available_externally i64 @_mm_cmpgt_pi8 // CHECK: [[REG116:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) @@ -257,7 +257,7 @@ test_cmp() { // CHECK-NEXT: store <16 x i8> [[REG120]], <16 x i8>* [[REG121:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG122:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG118]] // CHECK-NEXT: [[REG123:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG121]] -// CHECK-NEXT: call <16 x i8> @vec_cmpgt(signed char vector[16], signed char vector[16])(<16 x i8> noundef [[REG122]], <16 x i8> noundef [[REG123]]) +// CHECK-NEXT: call <16 x i8> @vec_cmpgt(signed char vector[16], signed char vector[16])(<16 x i8> [[REG122]], <16 x i8> [[REG123]]) void __attribute__((noinline)) test_alt_name_cmp() { @@ -428,16 +428,16 @@ test_madd() { // CHECK: define available_externally i64 @_mm_madd_pi16 // CHECK: store <4 x i32> zeroinitializer, <4 x i32>* [[REG149:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG150:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG150:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG151:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG150]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG151]], <8 x i16>* [[REG152:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG153:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG153:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG154:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG153]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG154]], <8 x i16>* [[REG155:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG156:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG152]], align 16 // CHECK-NEXT: [[REG157:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG155]], align 16 // CHECK-NEXT: [[REG158:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG149]], align 16 -// CHECK-NEXT: [[REG159:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmsumshm(<8 x i16> noundef [[REG156]], <8 x i16> noundef [[REG157]], <4 x i32> noundef [[REG158]]) +// CHECK-NEXT: [[REG159:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmsumshm(<8 x i16> [[REG156]], <8 x i16> [[REG157]], <4 x i32> [[REG158]]) // CHECK-NEXT: store <4 x i32> [[REG159]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK: define available_externally i64 @_m_pmaddwd @@ -463,16 +463,16 @@ test_mul() { // CHECK-NEXT: store <8 x i16> [[REG165]], <8 x i16>* [[REG166:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG167:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG162]], align 16 // CHECK-NEXT: [[REG168:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG166]], align 16 -// CHECK-NEXT: [[REG169:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmulesh(<8 x i16> noundef [[REG167]], <8 x i16> noundef [[REG168]]) +// CHECK-NEXT: [[REG169:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmulesh(<8 x i16> [[REG167]], <8 x i16> [[REG168]]) // CHECK-NEXT: store <4 x i32> [[REG169]], <4 x i32>* [[REG170:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG171:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG162]], align 16 // CHECK-NEXT: [[REG172:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG166]], align 16 -// CHECK-NEXT: [[REG173:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmulosh(<8 x i16> noundef [[REG171]], <8 x i16> noundef [[REG172]]) +// CHECK-NEXT: [[REG173:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmulosh(<8 x i16> [[REG171]], <8 x i16> [[REG172]]) // CHECK-NEXT: store <4 x i32> [[REG173]], <4 x i32>* [[REG174:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG175:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG170]], align 16 // CHECK-NEXT: [[REG176:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG174]], align 16 // CHECK-NEXT: [[REG177:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> noundef [[REG175]], <4 x i32> noundef [[REG176]], <16 x i8> noundef [[REG177]]) +// CHECK-NEXT: call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> [[REG175]], <4 x i32> [[REG176]], <16 x i8> [[REG177]]) // CHECK: define available_externally i64 @_mm_mullo_pi16 // CHECK: [[REG178:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) @@ -512,7 +512,7 @@ test_packs() { // CHECK-LABEL: @test_packs -// CHECK: define available_externally i64 @_mm_packs_pu16(i64 noundef [[REG190:[0-9a-zA-Z_%.]+]], i64 noundef [[REG191:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_packs_pu16(i64 [[REG190:[0-9a-zA-Z_%.]+]], i64 [[REG191:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG190]], i64* [[REG192:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG191]], i64* [[REG193:[0-9a-zA-Z_%.]+]], align 8 // CHECK-LE: load i64, i64* [[REG192]], align 8 @@ -522,17 +522,17 @@ test_packs() { // CHECK-NEXT: store <8 x i16> [[REG194]], <8 x i16>* [[REG195:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG196:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG197:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG198:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG197]], align 16 -// CHECK-NEXT: [[REG199:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_packs(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG196]], <8 x i16> noundef [[REG198]]) +// CHECK-NEXT: [[REG199:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_packs(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG196]], <8 x i16> [[REG198]]) // CHECK-NEXT: store <16 x i8> [[REG199]], <16 x i8>* [[REG200:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG201:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG195]], align 16 // CHECK-NEXT: [[REG202:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG195]], align 16 -// CHECK-NEXT: [[REG203:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_pack(bool vector[8], bool vector[8])(<8 x i16> noundef [[REG201]], <8 x i16> noundef [[REG202]]) +// CHECK-NEXT: [[REG203:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_pack(bool vector[8], bool vector[8])(<8 x i16> [[REG201]], <8 x i16> [[REG202]]) // CHECK-NEXT: store <16 x i8> [[REG203]], <16 x i8>* [[REG204:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG205:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG200]], align 16 // CHECK-NEXT: [[REG206:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG204]], align 16 -// CHECK-NEXT: call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], bool vector[16])(<16 x i8> noundef [[REG205]], <16 x i8> noundef zeroinitializer, <16 x i8> noundef [[REG206]]) +// CHECK-NEXT: call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], bool vector[16])(<16 x i8> [[REG205]], <16 x i8> zeroinitializer, <16 x i8> [[REG206]]) -// CHECK: define available_externally i64 @_mm_packs_pi16(i64 noundef [[REG207:[0-9a-zA-Z_%.]+]], i64 noundef [[REG208:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_packs_pi16(i64 [[REG207:[0-9a-zA-Z_%.]+]], i64 [[REG208:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG207]], i64* [[REG209:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG208]], i64* [[REG210:[0-9a-zA-Z_%.]+]], align 8 // CHECK-LE: load i64, i64* [[REG209]], align 8 @@ -540,9 +540,9 @@ test_packs() { // CHECK-BE: load i64, i64* [[REG209]], align 8 // CHECK: [[REG211:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG212:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG213:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG212]], align 16 -// CHECK-NEXT: call <16 x i8> @vec_packs(short vector[8], short vector[8])(<8 x i16> noundef [[REG211]], <8 x i16> noundef [[REG213]]) +// CHECK-NEXT: call <16 x i8> @vec_packs(short vector[8], short vector[8])(<8 x i16> [[REG211]], <8 x i16> [[REG213]]) -// CHECK: define available_externally i64 @_mm_packs_pi32(i64 noundef [[REG214:[0-9a-zA-Z_%.]+]], i64 noundef [[REG215:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_packs_pi32(i64 [[REG214:[0-9a-zA-Z_%.]+]], i64 [[REG215:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG214]], i64* [[REG216:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG215]], i64* [[REG217:[0-9a-zA-Z_%.]+]], align 8 // CHECK-LE: load i64, i64* [[REG216]], align 8 @@ -550,7 +550,7 @@ test_packs() { // CHECK-BE: load i64, i64* [[REG216]], align 8 // CHECK: [[REG218:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG219:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG220:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG219]], align 16 -// CHECK-NEXT: call <8 x i16> @vec_packs(int vector[4], int vector[4])(<4 x i32> noundef [[REG218]], <4 x i32> noundef [[REG220]]) +// CHECK-NEXT: call <8 x i16> @vec_packs(int vector[4], int vector[4])(<4 x i32> [[REG218]], <4 x i32> [[REG220]]) void __attribute__((noinline)) test_alt_name_packs() { @@ -635,7 +635,7 @@ test_set1() { // CHECK: define available_externally i64 @_mm_set1_pi16 // CHECK-P9: [[REG247:[0-9a-zA-Z_%.]+]] = load i16, i16* {{[0-9a-zA-Z_%.]+}}, align 2 -// CHECK-P9-NEXT: [[REG248:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(short)(i16 noundef signext [[REG247]]) +// CHECK-P9-NEXT: [[REG248:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(short)(i16 signext [[REG247]]) // CHECK-P9-NEXT: store <8 x i16> %call, <8 x i16>* [[REG249:[0-9a-zA-Z_%.]+]], align 16 // CHECK-P9-NEXT: [[REG250:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG249:[0-9a-zA-Z_%.]+]], align 16 // CHECK-P9-NEXT: [[REG251:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG250]] to <2 x i64> @@ -656,7 +656,7 @@ test_set1() { // CHECK-P8-NEXT: store i16 [[REG258]], i16* [[REG259]], align 2 // CHECK: define available_externally i64 @_mm_set1_pi8 -// CHECK: [[REG260:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(signed char)(i8 noundef signext {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG260:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(signed char)(i8 signext {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: store <16 x i8> [[REG260]], <16 x i8>* [[REG261:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG262:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG261:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG263:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> %1 to <2 x i64> @@ -749,12 +749,12 @@ test_sll() { // CHECK: define available_externally i64 @_mm_slli_pi16 // CHECK: [[REG289:[0-9a-zA-Z_%.]+]] = sext i32 {{[0-9a-zA-Z_%.]+}} to i64 -// CHECK-NEXT: [[REG290:[0-9a-zA-Z_%.]+]] = call i64 @_mm_sll_pi16(i64 noundef {{[0-9a-zA-Z_%.]+}}, i64 noundef [[REG289]]) +// CHECK-NEXT: [[REG290:[0-9a-zA-Z_%.]+]] = call i64 @_mm_sll_pi16(i64 {{[0-9a-zA-Z_%.]+}}, i64 [[REG289]]) // CHECK-NEXT: ret i64 [[REG290]] // CHECK: define available_externally i64 @_mm_slli_pi32 // CHECK: [[REG291:[0-9a-zA-Z_%.]+]] = sext i32 {{[0-9a-zA-Z_%.]+}} to i64 -// CHECK-NEXT: [[REG292:[0-9a-zA-Z_%.]+]] = call i64 @_mm_sll_pi32(i64 noundef {{[0-9a-zA-Z_%.]+}}, i64 noundef [[REG291]]) +// CHECK-NEXT: [[REG292:[0-9a-zA-Z_%.]+]] = call i64 @_mm_sll_pi32(i64 {{[0-9a-zA-Z_%.]+}}, i64 [[REG291]]) // CHECK-NEXT: ret i64 [[REG292]] // CHECK: define available_externally i64 @_mm_slli_si64 @@ -828,16 +828,16 @@ test_sra() { // CHECK: [[REG313:[0-9a-zA-Z_%.]+]] = icmp ule i64 {{[0-9a-zA-Z_%.]+}}, 15 // CHECK-NEXT: br i1 [[REG313]], label %[[REG314:[0-9a-zA-Z_%.]+]], label %[[REG315:[0-9a-zA-Z_%.]+]] // CHECK: [[REG314]] -// CHECK: [[REG316:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG316:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG317:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG316]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG317]], <8 x i16>* [[REG318:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG319:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG320:[0-9a-zA-Z_%.]+]] = trunc i64 [[REG319]] to i16 -// CHECK-NEXT: [[REG321:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 noundef zeroext [[REG320]]) +// CHECK-NEXT: [[REG321:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 zeroext [[REG320]]) // CHECK-NEXT: store <8 x i16> [[REG321]], <8 x i16>* [[REG322:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG323:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG318]], align 16 // CHECK-NEXT: [[REG324:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG322]], align 16 -// CHECK-NEXT: call <8 x i16> @vec_sra(short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG323]], <8 x i16> noundef [[REG324]]) +// CHECK-NEXT: call <8 x i16> @vec_sra(short vector[8], unsigned short vector[8])(<8 x i16> [[REG323]], <8 x i16> [[REG324]]) // CHECK: store i64 {{[0-9a-zA-Z_%.]+}}, i64* [[REG325:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: br label %[[REG326:[0-9a-zA-Z_%.]+]] // CHECK: [[REG315]] @@ -849,12 +849,12 @@ test_sra() { // CHECK: define available_externally i64 @_mm_srai_pi32 // CHECK: [[REG328:[0-9a-zA-Z_%.]+]] = sext i32 {{[0-9a-zA-Z_%.]+}} to i64 -// CHECK-NEXT: [[REG329:[0-9a-zA-Z_%.]+]] = call i64 @_mm_sra_pi32(i64 noundef {{[0-9a-zA-Z_%.]+}}, i64 noundef [[REG328]]) +// CHECK-NEXT: [[REG329:[0-9a-zA-Z_%.]+]] = call i64 @_mm_sra_pi32(i64 {{[0-9a-zA-Z_%.]+}}, i64 [[REG328]]) // CHECK-NEXT: ret i64 [[REG329]] // CHECK: define available_externally i64 @_mm_srai_pi16 // CHECK: [[REG330:[0-9a-zA-Z_%.]+]] = sext i32 {{[0-9a-zA-Z_%.]+}} to i64 -// CHECK-NEXT: [[REG331:[0-9a-zA-Z_%.]+]] = call i64 @_mm_sra_pi16(i64 noundef {{[0-9a-zA-Z_%.]+}}, i64 noundef [[REG330]]) +// CHECK-NEXT: [[REG331:[0-9a-zA-Z_%.]+]] = call i64 @_mm_sra_pi16(i64 {{[0-9a-zA-Z_%.]+}}, i64 [[REG330]]) // CHECK-NEXT: ret i64 [[REG331]] void __attribute__((noinline)) @@ -919,16 +919,16 @@ test_srl() { // CHECK: [[REG349:[0-9a-zA-Z_%.]+]] = icmp ule i64 {{[0-9a-zA-Z_%.]+}}, 15 // CHECK-NEXT: br i1 [[REG349]], label %[[REG350:[0-9a-zA-Z_%.]+]], label %[[REG351:[0-9a-zA-Z_%.]+]] // CHECK: [[REG350]] -// CHECK: [[REG352:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG352:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG353:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG352]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG353]], <8 x i16>* [[REG354:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG355:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG356:[0-9a-zA-Z_%.]+]] = trunc i64 [[REG355]] to i16 -// CHECK-NEXT: [[REG357:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 noundef zeroext [[REG356]]) +// CHECK-NEXT: [[REG357:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 zeroext [[REG356]]) // CHECK-NEXT: store <8 x i16> [[REG357]], <8 x i16>* [[REG358:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG359:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG354]], align 16 // CHECK-NEXT: [[REG360:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG358]], align 16 -// CHECK-NEXT: call <8 x i16> @vec_sr(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG359]], <8 x i16> noundef [[REG360]]) +// CHECK-NEXT: call <8 x i16> @vec_sr(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG359]], <8 x i16> [[REG360]]) // CHECK: store i64 {{[0-9a-zA-Z_%.]+}}, i64* [[REG361:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: br label %[[REG362:[0-9a-zA-Z_%.]+]] // CHECK: [[REG351]] @@ -945,12 +945,12 @@ test_srl() { // CHECK: define available_externally i64 @_mm_srli_pi32 // CHECK: [[REG366:[0-9a-zA-Z_%.]+]] = sext i32 {{[0-9a-zA-Z_%.]+}} to i64 -// CHECK-NEXT: [[REG367:[0-9a-zA-Z_%.]+]] = call i64 @_mm_srl_pi32(i64 noundef {{[0-9a-zA-Z_%.]+}}, i64 noundef [[REG366]]) +// CHECK-NEXT: [[REG367:[0-9a-zA-Z_%.]+]] = call i64 @_mm_srl_pi32(i64 {{[0-9a-zA-Z_%.]+}}, i64 [[REG366]]) // CHECK-NEXT: ret i64 [[REG367]] // CHECK: define available_externally i64 @_mm_srli_pi16 // CHECK: [[REG366:[0-9a-zA-Z_%.]+]] = sext i32 {{[0-9a-zA-Z_%.]+}} to i64 -// CHECK-NEXT: [[REG368:[0-9a-zA-Z_%.]+]] = call i64 @_mm_srl_pi16(i64 noundef {{[0-9a-zA-Z_%.]+}}, i64 noundef [[REG366]]) +// CHECK-NEXT: [[REG368:[0-9a-zA-Z_%.]+]] = call i64 @_mm_srl_pi16(i64 {{[0-9a-zA-Z_%.]+}}, i64 [[REG366]]) // CHECK-NEXT: ret i64 [[REG368]] void __attribute__((noinline)) @@ -1015,81 +1015,81 @@ test_sub() { // CHECK-P8-NEXT: [[REG382:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG381]], align 4 // CHECK-P8-NEXT: sub nsw i32 [[REG380]], [[REG382]] -// CHECK-P9: [[REG383:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK-P9: [[REG383:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-P9-NEXT: [[REG384:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG383]] to <4 x i32> // CHECK-P9-NEXT: store <4 x i32> [[REG384]], <4 x i32>* [[REG385:[0-9a-zA-Z_%.]+]], align 16 -// CHECK-P9: [[REG386:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK-P9: [[REG386:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-P9-NEXT: [[REG387:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG386]] to <4 x i32> // CHECK-P9-NEXT: store <4 x i32> [[REG387]], <4 x i32>* [[REG388:[0-9a-zA-Z_%.]+]], align 16 // CHECK-P9-NEXT: [[REG389:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG385]], align 16 // CHECK-P9-NEXT: [[REG390:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG388]], align 16 -// CHECK-P9-NEXT: call <4 x i32> @vec_sub(int vector[4], int vector[4])(<4 x i32> noundef [[REG389]], <4 x i32> noundef [[REG390]]) +// CHECK-P9-NEXT: call <4 x i32> @vec_sub(int vector[4], int vector[4])(<4 x i32> [[REG389]], <4 x i32> [[REG390]]) // CHECK: define available_externally i64 @_mm_sub_pi16 -// CHECK: [[REG391:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG391:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG392:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG391]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG392]], <8 x i16>* [[REG393:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG394:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG394:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG395:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG394]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG395]], <8 x i16>* [[REG396:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG397:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG393]], align 16 // CHECK-NEXT: [[REG398:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG396]], align 16 -// CHECK-NEXT: call <8 x i16> @vec_sub(short vector[8], short vector[8])(<8 x i16> noundef [[REG397]], <8 x i16> noundef [[REG398]]) +// CHECK-NEXT: call <8 x i16> @vec_sub(short vector[8], short vector[8])(<8 x i16> [[REG397]], <8 x i16> [[REG398]]) // CHECK: define available_externally i64 @_mm_sub_pi8 -// CHECK: [[REG399:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG399:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG400:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG399]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG400]], <16 x i8>* [[REG401:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG402:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG402:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG403:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG402]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG403]], <16 x i8>* [[REG404:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG405:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG401]], align 16 // CHECK-NEXT: [[REG406:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG404]], align 16 -// CHECK-NEXT: call <16 x i8> @vec_sub(signed char vector[16], signed char vector[16])(<16 x i8> noundef [[REG405]], <16 x i8> noundef [[REG406]]) +// CHECK-NEXT: call <16 x i8> @vec_sub(signed char vector[16], signed char vector[16])(<16 x i8> [[REG405]], <16 x i8> [[REG406]]) // CHECK: define available_externally i64 @_mm_subs_pi16 -// CHECK: [[REG407:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG407:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG408:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG407]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG408]], <8 x i16>* [[REG409:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG410:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG410:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG411:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG410]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG411]], <8 x i16>* [[REG412:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG413:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG409]], align 16 // CHECK-NEXT: [[REG414:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG412]], align 16 -// CHECK-NEXT: call <8 x i16> @vec_subs(short vector[8], short vector[8])(<8 x i16> noundef [[REG413]], <8 x i16> noundef [[REG414]]) +// CHECK-NEXT: call <8 x i16> @vec_subs(short vector[8], short vector[8])(<8 x i16> [[REG413]], <8 x i16> [[REG414]]) // CHECK: define available_externally i64 @_mm_subs_pi8 -// CHECK: [[REG415:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG415:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG416:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG415]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG416]], <16 x i8>* [[REG417:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG418:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG418:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG419:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG418]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG419]], <16 x i8>* [[REG420:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG421:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG417]], align 16 // CHECK-NEXT: [[REG422:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG420]], align 16 -// CHECK-NEXT: call <16 x i8> @vec_subs(signed char vector[16], signed char vector[16])(<16 x i8> noundef [[REG421]], <16 x i8> noundef [[REG422]]) +// CHECK-NEXT: call <16 x i8> @vec_subs(signed char vector[16], signed char vector[16])(<16 x i8> [[REG421]], <16 x i8> [[REG422]]) // CHECK: define available_externally i64 @_mm_subs_pu16 -// CHECK: [[REG423:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG423:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG424:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG423]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG424]], <8 x i16>* [[REG425:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG426:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG426:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG427:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG426]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG427]], <8 x i16>* [[REG428:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG429:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG425]], align 16 // CHECK-NEXT: [[REG430:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG428]], align 16 -// CHECK-NEXT: call <8 x i16> @vec_subs(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG429]], <8 x i16> noundef [[REG430]]) +// CHECK-NEXT: call <8 x i16> @vec_subs(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG429]], <8 x i16> [[REG430]]) // CHECK: define available_externally i64 @_mm_subs_pu8 -// CHECK: [[REG431:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG431:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG432:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG431]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG432]], <16 x i8>* [[REG433:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG434:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG434:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG435:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG434]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG435]], <16 x i8>* [[REG436:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG437:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG433]], align 16 // CHECK-NEXT: [[REG438:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG436]], align 16 -// CHECK-NEXT: call <16 x i8> @vec_subs(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG437]], <16 x i8> noundef [[REG438]]) +// CHECK-NEXT: call <16 x i8> @vec_subs(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG437]], <16 x i8> [[REG438]]) void __attribute__((noinline)) test_alt_name_sub() { @@ -1184,7 +1184,7 @@ test_unpack() { // CHECK-NEXT: store <16 x i8> [[REG472]], <16 x i8>* [[REG473:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG474:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG469]], align 16 // CHECK-NEXT: [[REG475:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG473]], align 16 -// CHECK-NEXT: call <16 x i8> @vec_mergel(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG474]], <16 x i8> noundef [[REG475]]) +// CHECK-NEXT: call <16 x i8> @vec_mergel(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG474]], <16 x i8> [[REG475]]) // CHECK: define available_externally i64 @_mm_unpacklo_pi32 // CHECK: [[REG476:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 0 diff --git a/clang/test/CodeGen/ppc-pmmintrin.c b/clang/test/CodeGen/ppc-pmmintrin.c index 8c91c16347e30649defcd31a557cfb4bbca54d3a..f56a6a9993dfdabfadb9772dd41d7fb1cfb35d7a 100644 --- a/clang/test/CodeGen/ppc-pmmintrin.c +++ b/clang/test/CodeGen/ppc-pmmintrin.c @@ -14,53 +14,10 @@ __m128i resi, mi; double *d; void __attribute__((noinline)) -// CHECK-LABEL: @test_pmmintrin( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @md1, align 16 -// CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, <2 x double>* @md2, align 16 -// CHECK-NEXT: [[CALL:%.*]] = call <2 x double> @_mm_addsub_pd(<2 x double> noundef [[TMP0]], <2 x double> noundef [[TMP1]]) #[[ATTR4:[0-9]+]] -// CHECK-NEXT: store <2 x double> [[CALL]], <2 x double>* @resd, align 16 -// CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, <4 x float>* @m1, align 16 -// CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, <4 x float>* @m2, align 16 -// CHECK-NEXT: [[CALL1:%.*]] = call <4 x float> @_mm_addsub_ps(<4 x float> noundef [[TMP2]], <4 x float> noundef [[TMP3]]) #[[ATTR4]] -// CHECK-NEXT: store <4 x float> [[CALL1]], <4 x float>* @res, align 16 -// CHECK-NEXT: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @md1, align 16 -// CHECK-NEXT: [[TMP5:%.*]] = load <2 x double>, <2 x double>* @md2, align 16 -// CHECK-NEXT: [[CALL2:%.*]] = call <2 x double> @_mm_hadd_pd(<2 x double> noundef [[TMP4]], <2 x double> noundef [[TMP5]]) #[[ATTR4]] -// CHECK-NEXT: store <2 x double> [[CALL2]], <2 x double>* @resd, align 16 -// CHECK-NEXT: [[TMP6:%.*]] = load <4 x float>, <4 x float>* @m1, align 16 -// CHECK-NEXT: [[TMP7:%.*]] = load <4 x float>, <4 x float>* @m2, align 16 -// CHECK-NEXT: [[CALL3:%.*]] = call <4 x float> @_mm_hadd_ps(<4 x float> noundef [[TMP6]], <4 x float> noundef [[TMP7]]) #[[ATTR4]] -// CHECK-NEXT: store <4 x float> [[CALL3]], <4 x float>* @res, align 16 -// CHECK-NEXT: [[TMP8:%.*]] = load <2 x double>, <2 x double>* @md1, align 16 -// CHECK-NEXT: [[TMP9:%.*]] = load <2 x double>, <2 x double>* @md2, align 16 -// CHECK-NEXT: [[CALL4:%.*]] = call <2 x double> @_mm_hsub_pd(<2 x double> noundef [[TMP8]], <2 x double> noundef [[TMP9]]) #[[ATTR4]] -// CHECK-NEXT: store <2 x double> [[CALL4]], <2 x double>* @resd, align 16 -// CHECK-NEXT: [[TMP10:%.*]] = load <4 x float>, <4 x float>* @m1, align 16 -// CHECK-NEXT: [[TMP11:%.*]] = load <4 x float>, <4 x float>* @m2, align 16 -// CHECK-NEXT: [[CALL5:%.*]] = call <4 x float> @_mm_hsub_ps(<4 x float> noundef [[TMP10]], <4 x float> noundef [[TMP11]]) #[[ATTR4]] -// CHECK-NEXT: store <4 x float> [[CALL5]], <4 x float>* @res, align 16 -// CHECK-NEXT: [[CALL6:%.*]] = call <2 x i64> @_mm_lddqu_si128(<2 x i64>* noundef @mi) #[[ATTR4]] -// CHECK-NEXT: store <2 x i64> [[CALL6]], <2 x i64>* @resi, align 16 -// CHECK-NEXT: [[TMP12:%.*]] = load double*, double** @d, align 8 -// CHECK-NEXT: [[CALL7:%.*]] = call <2 x double> @_mm_loaddup_pd(double* noundef [[TMP12]]) #[[ATTR4]] -// CHECK-NEXT: store <2 x double> [[CALL7]], <2 x double>* @resd, align 16 -// CHECK-NEXT: [[TMP13:%.*]] = load <2 x double>, <2 x double>* @md1, align 16 -// CHECK-NEXT: [[CALL8:%.*]] = call <2 x double> @_mm_movedup_pd(<2 x double> noundef [[TMP13]]) #[[ATTR4]] -// CHECK-NEXT: store <2 x double> [[CALL8]], <2 x double>* @resd, align 16 -// CHECK-NEXT: [[TMP14:%.*]] = load <4 x float>, <4 x float>* @m1, align 16 -// CHECK-NEXT: [[CALL9:%.*]] = call <4 x float> @_mm_movehdup_ps(<4 x float> noundef [[TMP14]]) #[[ATTR4]] -// CHECK-NEXT: store <4 x float> [[CALL9]], <4 x float>* @res, align 16 -// CHECK-NEXT: [[TMP15:%.*]] = load <4 x float>, <4 x float>* @m1, align 16 -// CHECK-NEXT: [[CALL10:%.*]] = call <4 x float> @_mm_moveldup_ps(<4 x float> noundef [[TMP15]]) #[[ATTR4]] -// CHECK-NEXT: store <4 x float> [[CALL10]], <4 x float>* @res, align 16 -// CHECK-NEXT: ret void -// test_pmmintrin() { resd = _mm_addsub_pd(md1, md2); res = _mm_addsub_ps(m1, m2); resd = _mm_hadd_pd(md1, md2); -// res = _mm_hadd_ps(m1, m2); resd = _mm_hsub_pd(md1, md2); res = _mm_hsub_ps(m1, m2); @@ -71,14 +28,126 @@ test_pmmintrin() { res = _mm_moveldup_ps(m1); } - - - - - - - - - - - +// CHECK-LABEL: @test_pmmintrin + +// CHECK: define available_externally <2 x double> @_mm_addsub_pd(<2 x double> [[REG1:[0-9a-zA-Z_%.]+]], <2 x double> [[REG2:[0-9a-zA-Z_%.]+]]) +// CHECK: store <2 x double> [[REG1]], <2 x double>* [[REG3:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <2 x double> [[REG2]], <2 x double>* [[REG4:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <2 x double> , <2 x double>* [[REG5:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: [[REG7:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG4]], align 16 +// CHECK-NEXT: [[REG8:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_xor(double vector[2], double vector[2])(<2 x double> [[REG7]], <2 x double> ) +// CHECK-NEXT: store <2 x double> [[REG8]], <2 x double>* [[REG6:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: [[REG9:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG3]], align 16 +// CHECK-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG6]], align 16 +// CHECK-NEXT: [[REG11:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_add(double vector[2], double vector[2])(<2 x double> [[REG9]], <2 x double> [[REG10]]) +// CHECK-NEXT: ret <2 x double> [[REG11]] + +// CHECK: define available_externally <4 x float> @_mm_addsub_ps(<4 x float> [[REG12:[0-9a-zA-Z_%.]+]], <4 x float> [[REG13:[0-9a-zA-Z_%.]+]]) +// CHECK: store <4 x float> [[REG12]], <4 x float>* [[REG14:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <4 x float> [[REG13]], <4 x float>* [[REG15:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <4 x float> , <4 x float>* [[REG16:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: [[REG18:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG15]], align 16 +// CHECK-NEXT: [[REG19:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_xor(float vector[4], float vector[4])(<4 x float> [[REG18]], <4 x float> ) +// CHECK-NEXT: store <4 x float> [[REG19]], <4 x float>* [[REG17:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: [[REG20:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG14]], align 16 +// CHECK-NEXT: [[REG21:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG17]], align 16 +// CHECK-NEXT: [[REG22:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_add(float vector[4], float vector[4])(<4 x float> [[REG20]], <4 x float> [[REG21]]) +// CHECK-NEXT: ret <4 x float> [[REG22]] + +// CHECK: define available_externally <2 x double> @_mm_hadd_pd(<2 x double> [[REG23:[0-9a-zA-Z_%.]+]], <2 x double> [[REG24:[0-9a-zA-Z_%.]+]]) +// CHECK: store <2 x double> [[REG23]], <2 x double>* [[REG25:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <2 x double> [[REG24]], <2 x double>* [[REG26:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: [[REG27:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG25]], align 16 +// CHECK-NEXT: [[REG28:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG26]], align 16 +// CHECK-NEXT: [[REG29:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_mergeh(double vector[2], double vector[2])(<2 x double> [[REG27]], <2 x double> [[REG28]]) +// CHECK-NEXT: [[REG30:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG25]], align 16 +// CHECK-NEXT: [[REG31:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG26]], align 16 +// CHECK-NEXT: [[REG32:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_mergel(double vector[2], double vector[2])(<2 x double> [[REG30]], <2 x double> [[REG31]]) +// CHECK-NEXT: [[REG33:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_add(double vector[2], double vector[2])(<2 x double> [[REG29]], <2 x double> [[REG32]]) +// CHECK-NEXT: ret <2 x double> [[REG33]] + +// CHECK: define available_externally <4 x float> @_mm_hadd_ps(<4 x float> [[REG34:[0-9a-zA-Z_%.]+]], <4 x float> [[REG35:[0-9a-zA-Z_%.]+]]) +// CHECK: store <4 x float> [[REG34]], <4 x float>* [[REG36:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <4 x float> [[REG35]], <4 x float>* [[REG37:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG38:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG39:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: [[REG40:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG36]], align 16 +// CHECK-NEXT: [[REG41:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG37]], align 16 +// CHECK-NEXT: [[REG42:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG38:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: [[REG43:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_perm(float vector[4], float vector[4], unsigned char vector[16])(<4 x float> [[REG40]], <4 x float> [[REG41]], <16 x i8> [[REG42]]) +// CHECK-NEXT: [[REG44:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG36]], align 16 +// CHECK-NEXT: [[REG45:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG37]], align 16 +// CHECK-NEXT: [[REG46:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG39:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: [[REG47:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_perm(float vector[4], float vector[4], unsigned char vector[16])(<4 x float> [[REG44]], <4 x float> [[REG45]], <16 x i8> [[REG46]]) +// CHECK-NEXT: [[REG48:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_add(float vector[4], float vector[4])(<4 x float> [[REG43]], <4 x float> [[REG47]]) +// CHECK-NEXT: ret <4 x float> [[REG48]] + +// CHECK: define available_externally <2 x double> @_mm_hsub_pd(<2 x double> [[REG49:[0-9a-zA-Z_%.]+]], <2 x double> [[REG50:[0-9a-zA-Z_%.]+]]) +// CHECK: store <2 x double> [[REG49]], <2 x double>* [[REG51:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <2 x double> [[REG50]], <2 x double>* [[REG52:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: [[REG53:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG51]], align 16 +// CHECK-NEXT: [[REG54:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG52]], align 16 +// CHECK-NEXT: [[REG55:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_mergeh(double vector[2], double vector[2])(<2 x double> [[REG53]], <2 x double> [[REG54]]) +// CHECK-NEXT: [[REG56:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG51]], align 16 +// CHECK-NEXT: [[REG57:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG52]], align 16 +// CHECK-NEXT: [[REG58:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_mergel(double vector[2], double vector[2])(<2 x double> [[REG56]], <2 x double> [[REG57]]) +// CHECK-NEXT: [[REG59:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_sub(double vector[2], double vector[2])(<2 x double> [[REG55]], <2 x double> [[REG58]]) +// CHECK-NEXT: ret <2 x double> [[REG59]] + +// CHECK: define available_externally <4 x float> @_mm_hsub_ps(<4 x float> [[REG60:[0-9a-zA-Z_%.]+]], <4 x float> [[REG61:[0-9a-zA-Z_%.]+]]) +// CHECK: store <4 x float> [[REG60]], <4 x float>* [[REG62:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <4 x float> [[REG61]], <4 x float>* [[REG63:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG64:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG65:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: [[REG66:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG62]], align 16 +// CHECK-NEXT: [[REG67:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG63]], align 16 +// CHECK-NEXT: [[REG68:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG64]], align 16 +// CHECK-NEXT: [[REG69:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_perm(float vector[4], float vector[4], unsigned char vector[16])(<4 x float> [[REG66]], <4 x float> [[REG67]], <16 x i8> [[REG68]]) +// CHECK-NEXT: [[REG70:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG62]], align 16 +// CHECK-NEXT: [[REG71:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG63]], align 16 +// CHECK-NEXT: [[REG72:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG65]], align 16 +// CHECK-NEXT: [[REG73:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_perm(float vector[4], float vector[4], unsigned char vector[16])(<4 x float> [[REG70]], <4 x float> [[REG71]], <16 x i8> [[REG72]]) +// CHECK-NEXT: [[REG74:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sub(float vector[4], float vector[4])(<4 x float> [[REG69]], <4 x float> [[REG73]]) +// CHECK-NEXT: ret <4 x float> [[REG74]] + +// CHECK: define available_externally <2 x i64> @_mm_lddqu_si128(<2 x i64>* [[REG75:[0-9a-zA-Z_%.]+]]) +// CHECK: store <2 x i64>* [[REG75]], <2 x i64>** [[REG76:[0-9a-zA-Z_%.]+]], align 8 +// CHECK-NEXT: [[REG77:[0-9a-zA-Z_%.]+]] = load <2 x i64>*, <2 x i64>** [[REG76]], align 8 +// CHECK-NEXT: [[REG78:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64>* [[REG77]] to i32* +// CHECK-NEXT: [[REG79:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vsx_ld(int, int const*)(i32 signext 0, i32* [[REG78]]) +// CHECK-NEXT: [[REG80:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG79]] to <2 x i64> +// CHECK-NEXT: ret <2 x i64> [[REG80]] + +// CHECK: define available_externally <2 x double> @_mm_loaddup_pd(double* [[REG81:[0-9a-zA-Z_%.]+]]) +// CHECK: store double* [[REG81]], double** [[REG82:[0-9a-zA-Z_%.]+]], align 8 +// CHECK-NEXT: [[REG83:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG82]], align 8 +// CHECK-NEXT: [[REG84:[0-9a-zA-Z_%.]+]] = load double, double* [[REG83]], align 8 +// CHECK-NEXT: [[REG85:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG84]]) +// CHECK-NEXT: ret <2 x double> [[REG85]] + +// CHECK: define available_externally <2 x double> @_mm_movedup_pd(<2 x double> [[REG86:[0-9a-zA-Z_%.]+]]) +// CHECK: store <2 x double> [[REG86]], <2 x double>* [[REG87:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: [[REG88:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG87]], align 16 +// CHECK-NEXT: [[REG89:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG87]], align 16 +// CHECK-NEXT: [[REG90:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_shuffle_pd(<2 x double> [[REG88]], <2 x double> [[REG89]], i32 signext 0) +// CHECK-NEXT: ret <2 x double> [[REG90]] + +// CHECK: define available_externally <4 x float> @_mm_movehdup_ps(<4 x float> [[REG91:[0-9a-zA-Z_%.]+]]) +// CHECK: store <4 x float> [[REG91]], <4 x float>* [[REG92:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: [[REG93:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG92]], align 16 +// CHECK-NEXT: [[REG94:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG93]] to <4 x i32> +// CHECK-NEXT: [[REG95:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG92]], align 16 +// CHECK-NEXT: [[REG96:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG95]] to <4 x i32> +// CHECK-NEXT: [[REG97:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mergeo(unsigned int vector[4], unsigned int vector[4])(<4 x i32> [[REG94]], <4 x i32> [[REG96]]) +// CHECK-NEXT: [[REG98:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG97]] to <4 x float> +// CHECK-NEXT: ret <4 x float> [[REG98]] + +// CHECK: define available_externally <4 x float> @_mm_moveldup_ps(<4 x float> [[REG99:[0-9a-zA-Z_%.]+]]) +// CHECK: store <4 x float> [[REG99]], <4 x float>* [[REG100:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: [[REG101:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG100]], align 16 +// CHECK-NEXT: [[REG102:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG101]] to <4 x i32> +// CHECK-NEXT: [[REG103:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG100]], align 16 +// CHECK-NEXT: [[REG104:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG103]] to <4 x i32> +// CHECK-NEXT: [[REG105:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mergee(unsigned int vector[4], unsigned int vector[4])(<4 x i32> [[REG102]], <4 x i32> [[REG104]]) +// CHECK-NEXT: [[REG106:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG105]] to <4 x float> +// CHECK-NEXT: ret <4 x float> [[REG106]] diff --git a/clang/test/CodeGen/ppc-signbit.c b/clang/test/CodeGen/ppc-signbit.c index c19a038c9ba31086ef652c677e32722e26422c32..adf37c9ef23b6ed50dfc363acfa32333526515dc 100644 --- a/clang/test/CodeGen/ppc-signbit.c +++ b/clang/test/CodeGen/ppc-signbit.c @@ -3,7 +3,7 @@ int test(long double x) { return __builtin_signbitl(x); } -// CHECK-LABEL: define{{.*}} signext i32 @test(ppc_fp128 noundef %x) +// CHECK-LABEL: define{{.*}} signext i32 @test(ppc_fp128 %x) // CHECK: bitcast ppc_fp128 %{{.*}} to i128 // CHECK: trunc i128 %{{.*}} to i64 // CHECK: icmp slt i64 %{{.*}}, 0 diff --git a/clang/test/CodeGen/ppc-smmintrin.c b/clang/test/CodeGen/ppc-smmintrin.c index 1e0a4117f65d2c0582a16f94f066ee309b5ce5c0..6b88b7ac0931004e3dad2adc5af07b9ee5a016a3 100644 --- a/clang/test/CodeGen/ppc-smmintrin.c +++ b/clang/test/CodeGen/ppc-smmintrin.c @@ -20,7 +20,7 @@ test_extract() { // CHECK-LABEL: @test_extract -// CHECK: define available_externally signext i32 @_mm_extract_epi8(<2 x i64> noundef [[REG1:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG2:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally signext i32 @_mm_extract_epi8(<2 x i64> [[REG1:[0-9a-zA-Z_%.]+]], i32 signext [[REG2:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1]], <2 x i64>* [[REG3:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG2]], i32* [[REG4:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG5:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG3]], align 16 @@ -31,7 +31,7 @@ test_extract() { // CHECK-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = zext i8 [[REG9]] to i32 // CHECK-NEXT: ret i32 [[REG10]] -// CHECK: define available_externally signext i32 @_mm_extract_epi32(<2 x i64> noundef [[REG11:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG12:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally signext i32 @_mm_extract_epi32(<2 x i64> [[REG11:[0-9a-zA-Z_%.]+]], i32 signext [[REG12:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG11]], <2 x i64>* [[REG13:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG12]], i32* [[REG14:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG15:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG13]], align 16 @@ -41,7 +41,7 @@ test_extract() { // CHECK-NEXT: [[REG19:[0-9a-zA-Z_%.]+]] = extractelement <4 x i32> [[REG16]], i32 [[REG18]] // CHECK-NEXT: ret i32 [[REG19]] -// CHECK: define available_externally signext i32 @_mm_extract_epi64(<2 x i64> noundef [[REG20:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG21:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally signext i32 @_mm_extract_epi64(<2 x i64> [[REG20:[0-9a-zA-Z_%.]+]], i32 signext [[REG21:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG20]], <2 x i64>* [[REG22:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG21]], i32* [[REG23:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG24:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG22]], align 16 @@ -51,7 +51,7 @@ test_extract() { // CHECK-NEXT: [[REG28:[0-9a-zA-Z_%.]+]] = trunc i64 [[REG27]] to i32 // CHECK-NEXT: ret i32 [[REG28]] -// CHECK: define available_externally signext i32 @_mm_extract_ps(<4 x float> noundef [[REG29:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG30:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally signext i32 @_mm_extract_ps(<4 x float> [[REG29:[0-9a-zA-Z_%.]+]], i32 signext [[REG30:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG29]], <4 x float>* [[REG31:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG30]], i32* [[REG32:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG33:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG31]], align 16 @@ -69,19 +69,19 @@ test_blend() { // CHECK-LABEL: @test_blend -// CHECK: define available_externally <2 x i64> @_mm_blend_epi16(<2 x i64> noundef [[REG38:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG39:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG40:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_blend_epi16(<2 x i64> [[REG38:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG39:[0-9a-zA-Z_%.]+]], i32 signext [[REG40:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG38]], <2 x i64>* [[REG41:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG39]], <2 x i64>* [[REG42:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG40]], i32* [[REG43:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG44:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG43]], align 4 // CHECK-NEXT: [[REG45:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG44]] to i8 -// CHECK-NEXT: [[REG46:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(signed char)(i8 noundef signext [[REG45]]) +// CHECK-NEXT: [[REG46:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(signed char)(i8 signext [[REG45]]) // CHECK-NEXT: store <16 x i8> [[REG46]], <16 x i8>* [[REG47:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG48:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG47]], align 16 // CHECK-NEXT: [[REG49:[0-9a-zA-Z_%.]+]] = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> [[REG48]]) // CHECK-NEXT: store <16 x i8> [[REG49]], <16 x i8>* [[REG47]], align 16 // CHECK-NEXT: [[REG50:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG47]], align 16 -// CHECK-NEXT: [[REG51:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackh(signed char vector[16])(<16 x i8> noundef [[REG50]]) +// CHECK-NEXT: [[REG51:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackh(signed char vector[16])(<16 x i8> [[REG50]]) // CHECK-NEXT: store <8 x i16> [[REG51]], <8 x i16>* [[REG52:[0-9a-zA-Z_%.]+]], align 16 // BE: [[REG53:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG52]], align 16 @@ -93,27 +93,27 @@ test_blend() { // CHECK-NEXT: [[REG57:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG42]], align 16 // CHECK-NEXT: [[REG58:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG57]] to <8 x i16> // CHECK-NEXT: [[REG59:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG52]], align 16 -// CHECK-NEXT: [[REG60:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sel(unsigned short vector[8], unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG56]], <8 x i16> noundef [[REG58]], <8 x i16> noundef [[REG59]]) +// CHECK-NEXT: [[REG60:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sel(unsigned short vector[8], unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG56]], <8 x i16> [[REG58]], <8 x i16> [[REG59]]) // CHECK-NEXT: [[REG61:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG60]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG61]] -// CHECK: define available_externally <2 x i64> @_mm_blendv_epi8(<2 x i64> noundef [[REG62:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG63:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG64:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_blendv_epi8(<2 x i64> [[REG62:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG63:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG64:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG62]], <2 x i64>* [[REG65:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG63]], <2 x i64>* [[REG66:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG64]], <2 x i64>* [[REG67:[0-9a-zA-Z_%.]+]], align 16 -// CHECK-NEXT: [[REG68:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 noundef zeroext 7) +// CHECK-NEXT: [[REG68:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 zeroext 7) // CHECK-NEXT: store <16 x i8> [[REG68]], <16 x i8>* [[REG69:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG70:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG67]], align 16 // CHECK-NEXT: [[REG71:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG70]] to <16 x i8> // CHECK-NEXT: [[REG72:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG69]], align 16 -// CHECK-NEXT: [[REG73:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sra(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG71]], <16 x i8> noundef [[REG72]]) +// CHECK-NEXT: [[REG73:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sra(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG71]], <16 x i8> [[REG72]]) // CHECK-NEXT: store <16 x i8> [[REG73]], <16 x i8>* [[REG74:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG75:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG65]], align 16 // CHECK-NEXT: [[REG76:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG75]] to <16 x i8> // CHECK-NEXT: [[REG77:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG66]], align 16 // CHECK-NEXT: [[REG78:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG77]] to <16 x i8> // CHECK-NEXT: [[REG79:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG74]], align 16 -// CHECK-NEXT: [[REG80:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG76]], <16 x i8> noundef [[REG78]], <16 x i8> noundef [[REG79]]) +// CHECK-NEXT: [[REG80:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG76]], <16 x i8> [[REG78]], <16 x i8> [[REG79]]) // CHECK-NEXT: [[REG81:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG80]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG81]] @@ -126,7 +126,7 @@ test_insert() { // CHECK-LABEL: @test_insert -// CHECK: define available_externally <2 x i64> @_mm_insert_epi8(<2 x i64> noundef {{[0-9a-zA-Z_%.]+}}, i32 noundef signext {{[0-9a-zA-Z_%.]+}}, i32 noundef signext {{[0-9a-zA-Z_%.]+}}) +// CHECK: define available_externally <2 x i64> @_mm_insert_epi8(<2 x i64> {{[0-9a-zA-Z_%.]+}}, i32 signext {{[0-9a-zA-Z_%.]+}}, i32 signext {{[0-9a-zA-Z_%.]+}}) // CHECK: %{{[0-9a-zA-Z_.]+}} = bitcast <2 x i64> %{{[0-9a-zA-Z_.]+}} to <16 x i8> // CHECK: %[[R0:[0-9a-zA-Z_.]+]] = trunc i32 %{{[0-9a-zA-Z_.]+}} to i8 // CHECK: %[[R1:[0-9a-zA-Z_.]+]] = and i32 %{{[0-9a-zA-Z_.]+}}, 15 @@ -134,14 +134,14 @@ test_insert() { // CHECK: %[[R2:[0-9a-zA-Z_.]+]] = bitcast <16 x i8> %{{[0-9a-zA-Z_.]+}} to <2 x i64> // CHECK: ret <2 x i64> %[[R2]] -// CHECK: define available_externally <2 x i64> @_mm_insert_epi32(<2 x i64> noundef {{[0-9a-zA-Z_%.]+}}, i32 noundef signext {{[0-9a-zA-Z_%.]+}}, i32 noundef signext {{[0-9a-zA-Z_%.]+}}) +// CHECK: define available_externally <2 x i64> @_mm_insert_epi32(<2 x i64> {{[0-9a-zA-Z_%.]+}}, i32 signext {{[0-9a-zA-Z_%.]+}}, i32 signext {{[0-9a-zA-Z_%.]+}}) // CHECK: %{{[0-9a-zA-Z_.]+}} = bitcast <2 x i64> %{{[0-9a-zA-Z_.]+}} to <4 x i32> // CHECK: %[[R0:[0-9a-zA-Z_.]+]] = and i32 %{{[0-9a-zA-Z_.]+}}, 3 // CHECK: %{{[0-9a-zA-Z_.]+}} = insertelement <4 x i32> %{{[0-9a-zA-Z_.]+}}, i32 %{{[0-9a-zA-Z_.]+}}, i32 %[[R0]] // CHECK: %[[R1:[0-9a-zA-Z_.]+]] = bitcast <4 x i32> %{{[0-9a-zA-Z_.]+}} to <2 x i64> // CHECK: ret <2 x i64> %[[R1]] -// CHECK: define available_externally <2 x i64> @_mm_insert_epi64(<2 x i64> noundef {{[0-9a-zA-Z_%.]+}}, i64 noundef {{[0-9a-zA-Z_%.]+}}, i32 noundef signext {{[0-9a-zA-Z_%.]+}}) +// CHECK: define available_externally <2 x i64> @_mm_insert_epi64(<2 x i64> {{[0-9a-zA-Z_%.]+}}, i64 {{[0-9a-zA-Z_%.]+}}, i32 signext {{[0-9a-zA-Z_%.]+}}) // CHECK: %[[R0:[0-9a-zA-Z_.]+]] = and i32 %{{[0-9a-zA-Z_.]+}}, 1 // CHECK: %{{[0-9a-zA-Z_.]+}} = insertelement <2 x i64> %{{[0-9a-zA-Z_.]+}}, i64 %{{[0-9a-zA-Z_.]+}}, i32 %[[R0:[0-9a-zA-Z_.]+]] // CHECK: ret <2 x i64> %{{[0-9a-zA-Z_.]+}} @@ -155,4 +155,4 @@ test_abs_ssse3() { // CHECK-LABEL: @test_abs_ssse3 -// CHECK: define available_externally <2 x i64> @_mm_abs_epi16(<2 x i64> noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: define available_externally <2 x i64> @_mm_abs_epi16(<2 x i64> {{[0-9a-zA-Z_%.]+}}) diff --git a/clang/test/CodeGen/ppc-tmmintrin.c b/clang/test/CodeGen/ppc-tmmintrin.c index 29e42ffdaaeb960ddd935d122995a7a14b9d3498..099c165d9ba8c9f9568f13243498b5f465e36bdf 100644 --- a/clang/test/CodeGen/ppc-tmmintrin.c +++ b/clang/test/CodeGen/ppc-tmmintrin.c @@ -23,31 +23,31 @@ test_abs() { // CHECK-LABEL: @test_abs -// CHECK: define available_externally <2 x i64> @_mm_abs_epi16(<2 x i64> noundef [[REG1:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_abs_epi16(<2 x i64> [[REG1:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG1]], <2 x i64>* [[REG2:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG3:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG2]], align 16 // CHECK-NEXT: [[REG4:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG3]] to <8 x i16> -// CHECK-NEXT: [[REG5:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_abs(short vector[8])(<8 x i16> noundef [[REG4]]) +// CHECK-NEXT: [[REG5:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_abs(short vector[8])(<8 x i16> [[REG4]]) // CHECK-NEXT: [[REG6:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG5]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG6]] -// CHECK: define available_externally <2 x i64> @_mm_abs_epi32(<2 x i64> noundef [[REG7:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_abs_epi32(<2 x i64> [[REG7:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG7]], <2 x i64>* [[REG8:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG9:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG8]], align 16 // CHECK-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG9]] to <4 x i32> -// CHECK-NEXT: [[REG11:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_abs(int vector[4])(<4 x i32> noundef [[REG10]]) +// CHECK-NEXT: [[REG11:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_abs(int vector[4])(<4 x i32> [[REG10]]) // CHECK-NEXT: [[REG12:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG11]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG12]] -// CHECK: define available_externally <2 x i64> @_mm_abs_epi8(<2 x i64> noundef [[REG13:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_abs_epi8(<2 x i64> [[REG13:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG13]], <2 x i64>* [[REG14:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG15:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG14]], align 16 // CHECK-NEXT: [[REG16:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG15]] to <16 x i8> -// CHECK-NEXT: [[REG17:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_abs(signed char vector[16])(<16 x i8> noundef [[REG16]]) +// CHECK-NEXT: [[REG17:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_abs(signed char vector[16])(<16 x i8> [[REG16]]) // CHECK-NEXT: [[REG18:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG17]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG18]] -// CHECK: define available_externally i64 @_mm_abs_pi16(i64 noundef [[REG19:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_abs_pi16(i64 [[REG19:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG19]], i64* [[REG20:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG21:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG20]], align 8 // CHECK-NEXT: [[REG22:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG21]], i32 0 @@ -58,12 +58,12 @@ test_abs() { // CHECK-NEXT: [[REG27:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG26]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG27]], <8 x i16>* [[REG28:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG29:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG28]], align 16 -// CHECK-NEXT: [[REG30:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_abs(short vector[8])(<8 x i16> noundef [[REG29]]) +// CHECK-NEXT: [[REG30:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_abs(short vector[8])(<8 x i16> [[REG29]]) // CHECK-NEXT: [[REG31:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG30]] to <2 x i64> // CHECK-NEXT: [[REG32:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG31]], i32 0 // CHECK-NEXT: ret i64 [[REG32]] -// CHECK: define available_externally i64 @_mm_abs_pi32(i64 noundef [[REG33:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_abs_pi32(i64 [[REG33:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG33]], i64* [[REG34:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG35:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG34]], align 8 // CHECK-NEXT: [[REG36:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG35]], i32 0 @@ -74,12 +74,12 @@ test_abs() { // CHECK-NEXT: [[REG41:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG40]] to <4 x i32> // CHECK-NEXT: store <4 x i32> [[REG41]], <4 x i32>* [[REG42:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG43:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG42]], align 16 -// CHECK-NEXT: [[REG44:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_abs(int vector[4])(<4 x i32> noundef [[REG43]]) +// CHECK-NEXT: [[REG44:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_abs(int vector[4])(<4 x i32> [[REG43]]) // CHECK-NEXT: [[REG45:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG44]] to <2 x i64> // CHECK-NEXT: [[REG46:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG45]], i32 0 // CHECK-NEXT: ret i64 [[REG46]] -// CHECK: define available_externally i64 @_mm_abs_pi8(i64 noundef [[REG47:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_abs_pi8(i64 [[REG47:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG47]], i64* [[REG48:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG49:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG48]], align 8 // CHECK-NEXT: [[REG50:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG49]], i32 0 @@ -90,7 +90,7 @@ test_abs() { // CHECK-NEXT: [[REG55:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG54]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG55]], <16 x i8>* [[REG56:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG57:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG56]], align 16 -// CHECK-NEXT: [[REG58:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_abs(signed char vector[16])(<16 x i8> noundef [[REG57]]) +// CHECK-NEXT: [[REG58:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_abs(signed char vector[16])(<16 x i8> [[REG57]]) // CHECK-NEXT: [[REG59:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG58]] to <2 x i64> // CHECK-NEXT: [[REG60:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG59]], i32 0 // CHECK-NEXT: ret i64 [[REG60]] @@ -103,7 +103,7 @@ test_alignr() { // CHECK-LABEL: @test_alignr -// CHECK: define available_externally <2 x i64> @_mm_alignr_epi8(<2 x i64> noundef [[REG61:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG62:[0-9a-zA-Z_%.]+]], i32 noundef zeroext [[REG63:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_alignr_epi8(<2 x i64> [[REG61:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG62:[0-9a-zA-Z_%.]+]], i32 zeroext [[REG63:[0-9a-zA-Z_%.]+]]) // CHECK: [[REG64:[0-9a-zA-Z_%.]+]] = alloca i32, align 4 // CHECK: store <2 x i64> [[REG61]], <2 x i64>* [[REG65:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG62]], <2 x i64>* [[REG66:[0-9a-zA-Z_%.]+]], align 16 @@ -156,7 +156,7 @@ test_alignr() { // CHECK-NEXT: [[REG88:[0-9a-zA-Z_%.]+]] = sub i32 [[REG87]], 16 // CHECK-NEXT: [[REG89:[0-9a-zA-Z_%.]+]] = mul i32 [[REG88]], 8 // CHECK-NEXT: [[REG90:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG89]] to i8 -// CHECK-NEXT: [[REG91:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 noundef zeroext [[REG90]]) +// CHECK-NEXT: [[REG91:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 zeroext [[REG90]]) // CHECK-NEXT: store <16 x i8> [[REG91]], <16 x i8>* [[REG92:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG93:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG65]], align 16 // CHECK-NEXT: [[REG94:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG93]] to <16 x i8> @@ -173,7 +173,7 @@ test_alignr() { // CHECK-NEXT: [[REG100:[0-9a-zA-Z_%.]+]] = mul i32 [[REG99]], 8 // CHECK-BE: [[REG101:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG100]] to i8 -// CHECK-BE: [[REG102:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 noundef zeroext [[REG101]]) +// CHECK-BE: [[REG102:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 zeroext [[REG101]]) // CHECK-BE: mul i32 {{[0-9a-zA-Z_%.]+}}, 8 // CHECK-BE: call <16 x i8> @vec_sro(unsigned char vector[16], unsigned char vector[16]) // CHECK-BE: call <16 x i8> @vec_slo(unsigned char vector[16], unsigned char vector[16]) @@ -195,7 +195,7 @@ test_alignr() { // CHECK-NEXT: [[REG108:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: ret <2 x i64> [[REG108]] -// CHECK: define available_externally i64 @_mm_alignr_pi8(i64 noundef [[REG109:[0-9a-zA-Z_%.]+]], i64 noundef [[REG110:[0-9a-zA-Z_%.]+]], i32 noundef zeroext [[REG111:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_alignr_pi8(i64 [[REG109:[0-9a-zA-Z_%.]+]], i64 [[REG110:[0-9a-zA-Z_%.]+]], i32 zeroext [[REG111:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG109]], i64* [[REG112:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG110]], i64* [[REG113:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i32 [[REG111]], i32* [[REG114:[0-9a-zA-Z_%.]+]], align 4 @@ -221,8 +221,8 @@ test_alignr() { // CHECK-NEXT: [[REG132:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG131]] to <16 x i8> // CHECK-NEXT: [[REG133:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG130]], align 16 // CHECK-NEXT: [[REG134:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG133]] to <16 x i8> -// CHECK-BE-NEXT: [[REG135:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_slo(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG132]], <16 x i8> noundef [[REG134]]) -// CHECK-LE-NEXT: [[REG135:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sro(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG132]], <16 x i8> noundef [[REG134]]) +// CHECK-BE-NEXT: [[REG135:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_slo(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG132]], <16 x i8> [[REG134]]) +// CHECK-LE-NEXT: [[REG135:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sro(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG132]], <16 x i8> [[REG134]]) // CHECK-NEXT: [[REG136:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG135]] to <2 x i64> // CHECK-NEXT: store <2 x i64> [[REG136]], <2 x i64>* [[REG123]], align 16 // CHECK-NEXT: [[REG137:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG123]], align 16 @@ -251,7 +251,7 @@ test_hadd() { // CHECK-LABEL: @test_hadd -// CHECK: define available_externally <2 x i64> @_mm_hadd_epi16(<2 x i64> noundef [[REG143:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG144:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_hadd_epi16(<2 x i64> [[REG143:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG144:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG143]], <2 x i64>* [[REG145:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG144]], <2 x i64>* [[REG146:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG147:[0-9a-zA-Z_%.]+]], align 16 @@ -260,21 +260,21 @@ test_hadd() { // CHECK-NEXT: [[REG150:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG149]] to <8 x i16> // CHECK-NEXT: [[REG151:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG146]], align 16 // CHECK-NEXT: [[REG152:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG151]] to <8 x i16> -// CHECK-NEXT: [[REG153:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG150]], <8 x i16> noundef [[REG152]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG153:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG150]], <8 x i16> [[REG152]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG153]], <8 x i16>* [[REG154:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG155:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG145]], align 16 // CHECK-NEXT: [[REG156:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG155]] to <8 x i16> // CHECK-NEXT: [[REG157:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG146]], align 16 // CHECK-NEXT: [[REG158:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG157]] to <8 x i16> -// CHECK-NEXT: [[REG159:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG156]], <8 x i16> noundef [[REG158]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG159:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG156]], <8 x i16> [[REG158]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG159]], <8 x i16>* [[REG160:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG161:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG154]], align 16 // CHECK-NEXT: [[REG162:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG160]], align 16 -// CHECK-NEXT: [[REG163:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_add(short vector[8], short vector[8])(<8 x i16> noundef [[REG161]], <8 x i16> noundef [[REG162]]) +// CHECK-NEXT: [[REG163:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_add(short vector[8], short vector[8])(<8 x i16> [[REG161]], <8 x i16> [[REG162]]) // CHECK-NEXT: [[REG164:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG163]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG164]] -// CHECK: define available_externally <2 x i64> @_mm_hadd_epi32(<2 x i64> noundef [[REG165:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG166:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_hadd_epi32(<2 x i64> [[REG165:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG166:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG165]], <2 x i64>* [[REG167:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG166]], <2 x i64>* [[REG168:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG169:[0-9a-zA-Z_%.]+]], align 16 @@ -283,21 +283,21 @@ test_hadd() { // CHECK-NEXT: [[REG172:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG171]] to <4 x i32> // CHECK-NEXT: [[REG173:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG168]], align 16 // CHECK-NEXT: [[REG174:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG173]] to <4 x i32> -// CHECK-NEXT: [[REG175:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> noundef [[REG172]], <4 x i32> noundef [[REG174]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG175:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> [[REG172]], <4 x i32> [[REG174]], <16 x i8> ) // CHECK-NEXT: store <4 x i32> [[REG175]], <4 x i32>* [[REG176:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG177:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG167]], align 16 // CHECK-NEXT: [[REG178:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG177]] to <4 x i32> // CHECK-NEXT: [[REG179:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG168]], align 16 // CHECK-NEXT: [[REG180:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG179]] to <4 x i32> -// CHECK-NEXT: [[REG181:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> noundef [[REG178]], <4 x i32> noundef [[REG180]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG181:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> [[REG178]], <4 x i32> [[REG180]], <16 x i8> ) // CHECK-NEXT: store <4 x i32> [[REG181]], <4 x i32>* [[REG182:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG183:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG176]], align 16 // CHECK-NEXT: [[REG184:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG182]], align 16 -// CHECK-NEXT: [[REG185:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> noundef [[REG183]], <4 x i32> noundef [[REG184]]) +// CHECK-NEXT: [[REG185:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG183]], <4 x i32> [[REG184]]) // CHECK-NEXT: [[REG186:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG185]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG186]] -// CHECK: define available_externally i64 @_mm_hadd_pi16(i64 noundef [[REG187:[0-9a-zA-Z_%.]+]], i64 noundef [[REG188:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_hadd_pi16(i64 [[REG187:[0-9a-zA-Z_%.]+]], i64 [[REG188:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG187]], i64* [[REG189:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG188]], i64* [[REG190:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG191:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG189]], align 8 @@ -312,22 +312,22 @@ test_hadd() { // CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG200:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG201:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG198]], align 16 // CHECK-NEXT: [[REG202:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG198]], align 16 -// CHECK-NEXT: [[REG203:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG201]], <8 x i16> noundef [[REG202]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG203:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG201]], <8 x i16> [[REG202]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG203]], <8 x i16>* [[REG204:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG205:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG198]], align 16 // CHECK-NEXT: [[REG206:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG198]], align 16 -// CHECK-NEXT: [[REG207:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG205]], <8 x i16> noundef [[REG206]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG207:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG205]], <8 x i16> [[REG206]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG207]], <8 x i16>* [[REG198]], align 16 // CHECK-NEXT: [[REG208:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG198]], align 16 // CHECK-NEXT: [[REG209:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG204]], align 16 -// CHECK-NEXT: [[REG210:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_add(short vector[8], short vector[8])(<8 x i16> noundef [[REG208]], <8 x i16> noundef [[REG209]]) +// CHECK-NEXT: [[REG210:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_add(short vector[8], short vector[8])(<8 x i16> [[REG208]], <8 x i16> [[REG209]]) // CHECK-NEXT: store <8 x i16> [[REG210]], <8 x i16>* [[REG198]], align 16 // CHECK-NEXT: [[REG211:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG198]], align 16 // CHECK-NEXT: [[REG212:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG211]] to <2 x i64> // CHECK-NEXT: [[REG213:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG212]], i32 1 // CHECK-NEXT: ret i64 [[REG213]] -// CHECK: define available_externally i64 @_mm_hadd_pi32(i64 noundef [[REG214:[0-9a-zA-Z_%.]+]], i64 noundef [[REG215:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_hadd_pi32(i64 [[REG214:[0-9a-zA-Z_%.]+]], i64 [[REG215:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG214]], i64* [[REG216:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG215]], i64* [[REG217:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG218:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG216]], align 8 @@ -342,22 +342,22 @@ test_hadd() { // CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG227:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG228:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG225]], align 16 // CHECK-NEXT: [[REG229:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG225]], align 16 -// CHECK-NEXT: [[REG230:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> noundef [[REG228]], <4 x i32> noundef [[REG229]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG230:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> [[REG228]], <4 x i32> [[REG229]], <16 x i8> ) // CHECK-NEXT: store <4 x i32> [[REG230]], <4 x i32>* [[REG231:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG232:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG225]], align 16 // CHECK-NEXT: [[REG233:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG225]], align 16 -// CHECK-NEXT: [[REG234:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> noundef [[REG232]], <4 x i32> noundef [[REG233]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG234:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> [[REG232]], <4 x i32> [[REG233]], <16 x i8> ) // CHECK-NEXT: store <4 x i32> [[REG234]], <4 x i32>* [[REG225]], align 16 // CHECK-NEXT: [[REG235:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG225]], align 16 // CHECK-NEXT: [[REG236:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG231]], align 16 -// CHECK-NEXT: [[REG237:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> noundef [[REG235]], <4 x i32> noundef [[REG236]]) +// CHECK-NEXT: [[REG237:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG235]], <4 x i32> [[REG236]]) // CHECK-NEXT: store <4 x i32> [[REG237]], <4 x i32>* [[REG225]], align 16 // CHECK-NEXT: [[REG238:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG225]], align 16 // CHECK-NEXT: [[REG239:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG238]] to <2 x i64> // CHECK-NEXT: [[REG240:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG239]], i32 1 // CHECK-NEXT: ret i64 [[REG240]] -// CHECK: define available_externally <2 x i64> @_mm_hadds_epi16(<2 x i64> noundef [[REG241:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG242:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_hadds_epi16(<2 x i64> [[REG241:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG242:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG241]], <2 x i64>* [[REG243:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG242]], <2 x i64>* [[REG244:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* [[REG245:[0-9a-zA-Z_%.]+]], align 16 @@ -365,23 +365,23 @@ test_hadd() { // CHECK-NEXT: [[REG247:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG243]], align 16 // CHECK-NEXT: [[REG248:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG247]] to <8 x i16> // CHECK-NEXT: [[REG249:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG245]], align 16 -// CHECK-NEXT: [[REG250:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sum4s(short vector[8], int vector[4])(<8 x i16> noundef [[REG248]], <4 x i32> noundef [[REG249]]) +// CHECK-NEXT: [[REG250:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sum4s(short vector[8], int vector[4])(<8 x i16> [[REG248]], <4 x i32> [[REG249]]) // CHECK-NEXT: store <4 x i32> [[REG250]], <4 x i32>* [[REG245]], align 16 // CHECK-NEXT: [[REG251:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG244]], align 16 // CHECK-NEXT: [[REG252:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG251]] to <8 x i16> // CHECK-NEXT: [[REG253:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG246]], align 16 -// CHECK-NEXT: [[REG254:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sum4s(short vector[8], int vector[4])(<8 x i16> noundef [[REG252]], <4 x i32> noundef [[REG253]]) +// CHECK-NEXT: [[REG254:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sum4s(short vector[8], int vector[4])(<8 x i16> [[REG252]], <4 x i32> [[REG253]]) // CHECK-NEXT: store <4 x i32> [[REG254]], <4 x i32>* [[REG246]], align 16 // CHECK-NEXT: [[REG255:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG245]], align 16 // CHECK-NEXT: [[REG256:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG246]], align 16 -// CHECK-NEXT: [[REG257:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_packs(int vector[4], int vector[4])(<4 x i32> noundef [[REG255]], <4 x i32> noundef [[REG256]]) +// CHECK-NEXT: [[REG257:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_packs(int vector[4], int vector[4])(<4 x i32> [[REG255]], <4 x i32> [[REG256]]) // CHECK-NEXT: [[REG258:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG257]] to <4 x i32> // CHECK-NEXT: store <4 x i32> [[REG258]], <4 x i32>* [[REG245]], align 16 // CHECK-NEXT: [[REG259:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG245]], align 16 // CHECK-NEXT: [[REG260:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG259]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG260]] -// CHECK: define available_externally i64 @_mm_hadds_pi16(i64 noundef [[REG261:[0-9a-zA-Z_%.]+]], i64 noundef [[REG262:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_hadds_pi16(i64 [[REG261:[0-9a-zA-Z_%.]+]], i64 [[REG262:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG261]], i64* [[REG263:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG262]], i64* [[REG264:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* [[REG265:[0-9a-zA-Z_%.]+]], align 16 @@ -394,11 +394,11 @@ test_hadd() { // CHECK-NEXT: [[REG272:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG271]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG272]], <8 x i16>* [[REG273:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG274:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG273]], align 16 -// CHECK-NEXT: [[REG275:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sum4s(short vector[8], int vector[4])(<8 x i16> noundef [[REG274]], <4 x i32> noundef zeroinitializer) +// CHECK-NEXT: [[REG275:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sum4s(short vector[8], int vector[4])(<8 x i16> [[REG274]], <4 x i32> zeroinitializer) // CHECK-NEXT: store <4 x i32> [[REG275]], <4 x i32>* [[REG276:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG277:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG276]], align 16 // CHECK-NEXT: [[REG278:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG276]], align 16 -// CHECK-NEXT: [[REG279:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_packs(int vector[4], int vector[4])(<4 x i32> noundef [[REG277]], <4 x i32> noundef [[REG278]]) +// CHECK-NEXT: [[REG279:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_packs(int vector[4], int vector[4])(<4 x i32> [[REG277]], <4 x i32> [[REG278]]) // CHECK-NEXT: store <8 x i16> [[REG279]], <8 x i16>* [[REG273]], align 16 // CHECK-NEXT: [[REG280:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG273]], align 16 // CHECK-NEXT: [[REG281:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG280]] to <2 x i64> @@ -417,7 +417,7 @@ test_hsub() { // CHECK-LABEL: @test_hsub -// CHECK: define available_externally <2 x i64> @_mm_hsub_epi16(<2 x i64> noundef [[REG283:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG284:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_hsub_epi16(<2 x i64> [[REG283:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG284:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG283]], <2 x i64>* [[REG285:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG284]], <2 x i64>* [[REG286:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG287:[0-9a-zA-Z_%.]+]], align 16 @@ -426,21 +426,21 @@ test_hsub() { // CHECK-NEXT: [[REG290:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG289]] to <8 x i16> // CHECK-NEXT: [[REG291:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG286]], align 16 // CHECK-NEXT: [[REG292:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG291]] to <8 x i16> -// CHECK-NEXT: [[REG293:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG290]], <8 x i16> noundef [[REG292]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG293:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG290]], <8 x i16> [[REG292]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG293]], <8 x i16>* [[REG294:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG295:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG285]], align 16 // CHECK-NEXT: [[REG296:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG295]] to <8 x i16> // CHECK-NEXT: [[REG297:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG286]], align 16 // CHECK-NEXT: [[REG298:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG297]] to <8 x i16> -// CHECK-NEXT: [[REG299:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG296]], <8 x i16> noundef [[REG298]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG299:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG296]], <8 x i16> [[REG298]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG299]], <8 x i16>* [[REG300:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG301:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG294]], align 16 // CHECK-NEXT: [[REG302:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG300]], align 16 -// CHECK-NEXT: [[REG303:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sub(short vector[8], short vector[8])(<8 x i16> noundef [[REG301]], <8 x i16> noundef [[REG302]]) +// CHECK-NEXT: [[REG303:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sub(short vector[8], short vector[8])(<8 x i16> [[REG301]], <8 x i16> [[REG302]]) // CHECK-NEXT: [[REG304:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG303]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG304]] -// CHECK: define available_externally <2 x i64> @_mm_hsub_epi32(<2 x i64> noundef [[REG305:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG306:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_hsub_epi32(<2 x i64> [[REG305:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG306:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG305]], <2 x i64>* [[REG307:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG306]], <2 x i64>* [[REG308:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG309:[0-9a-zA-Z_%.]+]], align 16 @@ -449,21 +449,21 @@ test_hsub() { // CHECK-NEXT: [[REG312:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG311]] to <4 x i32> // CHECK-NEXT: [[REG313:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG308]], align 16 // CHECK-NEXT: [[REG314:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG313]] to <4 x i32> -// CHECK-NEXT: [[REG315:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> noundef [[REG312]], <4 x i32> noundef [[REG314]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG315:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> [[REG312]], <4 x i32> [[REG314]], <16 x i8> ) // CHECK-NEXT: store <4 x i32> [[REG315]], <4 x i32>* [[REG316:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG317:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG307]], align 16 // CHECK-NEXT: [[REG318:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG317]] to <4 x i32> // CHECK-NEXT: [[REG319:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG308]], align 16 // CHECK-NEXT: [[REG320:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG319]] to <4 x i32> -// CHECK-NEXT: [[REG321:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> noundef [[REG318]], <4 x i32> noundef [[REG320]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG321:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> [[REG318]], <4 x i32> [[REG320]], <16 x i8> ) // CHECK-NEXT: store <4 x i32> [[REG321]], <4 x i32>* [[REG322:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG323:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG316]], align 16 // CHECK-NEXT: [[REG324:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG322]], align 16 -// CHECK-NEXT: [[REG325:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sub(int vector[4], int vector[4])(<4 x i32> noundef [[REG323]], <4 x i32> noundef [[REG324]]) +// CHECK-NEXT: [[REG325:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sub(int vector[4], int vector[4])(<4 x i32> [[REG323]], <4 x i32> [[REG324]]) // CHECK-NEXT: [[REG326:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG325]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG326]] -// CHECK: define available_externally i64 @_mm_hsub_pi16(i64 noundef [[REG327:[0-9a-zA-Z_%.]+]], i64 noundef [[REG328:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_hsub_pi16(i64 [[REG327:[0-9a-zA-Z_%.]+]], i64 [[REG328:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG327]], i64* [[REG329:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG328]], i64* [[REG330:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG331:[0-9a-zA-Z_%.]+]], align 16 @@ -478,22 +478,22 @@ test_hsub() { // CHECK-NEXT: store <8 x i16> [[REG339]], <8 x i16>* [[REG340:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG341:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG340]], align 16 // CHECK-NEXT: [[REG342:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG340]], align 16 -// CHECK-NEXT: [[REG343:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG341]], <8 x i16> noundef [[REG342]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG343:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG341]], <8 x i16> [[REG342]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG343]], <8 x i16>* [[REG344:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG345:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG340]], align 16 // CHECK-NEXT: [[REG346:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG340]], align 16 -// CHECK-NEXT: [[REG347:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG345]], <8 x i16> noundef [[REG346]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG347:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG345]], <8 x i16> [[REG346]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG347]], <8 x i16>* [[REG340]], align 16 // CHECK-NEXT: [[REG348:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG340]], align 16 // CHECK-NEXT: [[REG349:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG344]], align 16 -// CHECK-NEXT: [[REG350:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sub(short vector[8], short vector[8])(<8 x i16> noundef [[REG348]], <8 x i16> noundef [[REG349]]) +// CHECK-NEXT: [[REG350:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sub(short vector[8], short vector[8])(<8 x i16> [[REG348]], <8 x i16> [[REG349]]) // CHECK-NEXT: store <8 x i16> [[REG350]], <8 x i16>* [[REG340]], align 16 // CHECK-NEXT: [[REG351:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG340]], align 16 // CHECK-NEXT: [[REG352:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG351]] to <2 x i64> // CHECK-NEXT: [[REG353:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG352]], i32 1 // CHECK-NEXT: ret i64 [[REG353]] -// CHECK: define available_externally i64 @_mm_hsub_pi32(i64 noundef [[REG354:[0-9a-zA-Z_%.]+]], i64 noundef [[REG355:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_hsub_pi32(i64 [[REG354:[0-9a-zA-Z_%.]+]], i64 [[REG355:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG354]], i64* [[REG356:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG355]], i64* [[REG357:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG358:[0-9a-zA-Z_%.]+]], align 16 @@ -508,22 +508,22 @@ test_hsub() { // CHECK-NEXT: store <4 x i32> [[REG366]], <4 x i32>* [[REG367:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG368:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG367]], align 16 // CHECK-NEXT: [[REG369:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG367]], align 16 -// CHECK-NEXT: [[REG370:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> noundef [[REG368]], <4 x i32> noundef [[REG369]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG370:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> [[REG368]], <4 x i32> [[REG369]], <16 x i8> ) // CHECK-NEXT: store <4 x i32> [[REG370]], <4 x i32>* [[REG371:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG372:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG367]], align 16 // CHECK-NEXT: [[REG373:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG367]], align 16 -// CHECK-NEXT: [[REG374:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> noundef [[REG372]], <4 x i32> noundef [[REG373]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG374:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> [[REG372]], <4 x i32> [[REG373]], <16 x i8> ) // CHECK-NEXT: store <4 x i32> [[REG374]], <4 x i32>* [[REG367]], align 16 // CHECK-NEXT: [[REG375:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG367]], align 16 // CHECK-NEXT: [[REG376:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG371]], align 16 -// CHECK-NEXT: [[REG377:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sub(int vector[4], int vector[4])(<4 x i32> noundef [[REG375]], <4 x i32> noundef [[REG376]]) +// CHECK-NEXT: [[REG377:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sub(int vector[4], int vector[4])(<4 x i32> [[REG375]], <4 x i32> [[REG376]]) // CHECK-NEXT: store <4 x i32> [[REG377]], <4 x i32>* [[REG367]], align 16 // CHECK-NEXT: [[REG378:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG367]], align 16 // CHECK-NEXT: [[REG379:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG378]] to <2 x i64> // CHECK-NEXT: [[REG380:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG379]], i32 1 // CHECK-NEXT: ret i64 [[REG380]] -// CHECK: define available_externally <2 x i64> @_mm_hsubs_epi16(<2 x i64> noundef [[REG381:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG382:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_hsubs_epi16(<2 x i64> [[REG381:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG382:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG381]], <2 x i64>* [[REG383:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG382]], <2 x i64>* [[REG384:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG385:[0-9a-zA-Z_%.]+]], align 16 @@ -532,21 +532,21 @@ test_hsub() { // CHECK-NEXT: [[REG388:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG387]] to <8 x i16> // CHECK-NEXT: [[REG389:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG384]], align 16 // CHECK-NEXT: [[REG390:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG389]] to <8 x i16> -// CHECK-NEXT: [[REG391:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG388]], <8 x i16> noundef [[REG390]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG391:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG388]], <8 x i16> [[REG390]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG391]], <8 x i16>* [[REG392:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG393:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG383]], align 16 // CHECK-NEXT: [[REG394:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG393]] to <8 x i16> // CHECK-NEXT: [[REG395:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG384]], align 16 // CHECK-NEXT: [[REG396:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG395]] to <8 x i16> -// CHECK-NEXT: [[REG397:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG394]], <8 x i16> noundef [[REG396]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG397:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG394]], <8 x i16> [[REG396]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG397]], <8 x i16>* [[REG398:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG399:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG392]], align 16 // CHECK-NEXT: [[REG400:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG398]], align 16 -// CHECK-NEXT: [[REG401:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_subs(short vector[8], short vector[8])(<8 x i16> noundef [[REG399]], <8 x i16> noundef [[REG400]]) +// CHECK-NEXT: [[REG401:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_subs(short vector[8], short vector[8])(<8 x i16> [[REG399]], <8 x i16> [[REG400]]) // CHECK-NEXT: [[REG402:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG401]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG402]] -// CHECK: define available_externally i64 @_mm_hsubs_pi16(i64 noundef [[REG403:[0-9a-zA-Z_%.]+]], i64 noundef [[REG404:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_hsubs_pi16(i64 [[REG403:[0-9a-zA-Z_%.]+]], i64 [[REG404:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG403]], i64* [[REG405:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG404]], i64* [[REG406:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG407:[0-9a-zA-Z_%.]+]], align 16 @@ -561,15 +561,15 @@ test_hsub() { // CHECK-NEXT: store <8 x i16> [[REG415]], <8 x i16>* [[REG416:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG417:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG416]], align 16 // CHECK-NEXT: [[REG418:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG416]], align 16 -// CHECK-NEXT: [[REG419:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG417]], <8 x i16> noundef [[REG418]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG419:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG417]], <8 x i16> [[REG418]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG419]], <8 x i16>* [[REG420:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG421:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG416]], align 16 // CHECK-NEXT: [[REG422:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG416]], align 16 -// CHECK-NEXT: [[REG423:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG421]], <8 x i16> noundef [[REG422]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG423:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG421]], <8 x i16> [[REG422]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG423]], <8 x i16>* [[REG424:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG425:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG420]], align 16 // CHECK-NEXT: [[REG426:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG424]], align 16 -// CHECK-NEXT: [[REG427:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_subs(short vector[8], short vector[8])(<8 x i16> noundef [[REG425]], <8 x i16> noundef [[REG426]]) +// CHECK-NEXT: [[REG427:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_subs(short vector[8], short vector[8])(<8 x i16> [[REG425]], <8 x i16> [[REG426]]) // CHECK-NEXT: store <8 x i16> [[REG427]], <8 x i16>* [[REG416]], align 16 // CHECK-NEXT: [[REG428:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG416]], align 16 // CHECK-NEXT: [[REG429:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG428]] to <2 x i64> @@ -584,13 +584,13 @@ test_shuffle() { // CHECK-LABEL: @test_shuffle -// CHECK: define available_externally <2 x i64> @_mm_shuffle_epi8(<2 x i64> noundef [[REG431:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG432:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_shuffle_epi8(<2 x i64> [[REG431:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG432:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG431]], <2 x i64>* [[REG433:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG432]], <2 x i64>* [[REG434:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <16 x i8> zeroinitializer, <16 x i8>* [[REG435:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG436:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG434]], align 16 // CHECK-NEXT: [[REG437:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG436]] to <16 x i8> -// CHECK-NEXT: [[REG438:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmplt(signed char vector[16], signed char vector[16])(<16 x i8> noundef [[REG437]], <16 x i8> noundef zeroinitializer) +// CHECK-NEXT: [[REG438:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmplt(signed char vector[16], signed char vector[16])(<16 x i8> [[REG437]], <16 x i8> zeroinitializer) // CHECK-NEXT: store <16 x i8> [[REG438]], <16 x i8>* [[REG439:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG440:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG433]], align 16 // CHECK-NEXT: [[REG441:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG440]] to <16 x i8> @@ -598,15 +598,15 @@ test_shuffle() { // CHECK-NEXT: [[REG443:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG442]] to <16 x i8> // CHECK-NEXT: [[REG444:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG434]], align 16 // CHECK-NEXT: [[REG445:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG444]] to <16 x i8> -// CHECK-NEXT: [[REG446:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_perm(signed char vector[16], signed char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG441]], <16 x i8> noundef [[REG443]], <16 x i8> noundef [[REG445]]) +// CHECK-NEXT: [[REG446:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_perm(signed char vector[16], signed char vector[16], unsigned char vector[16])(<16 x i8> [[REG441]], <16 x i8> [[REG443]], <16 x i8> [[REG445]]) // CHECK-NEXT: store <16 x i8> [[REG446]], <16 x i8>* [[REG447:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG448:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG447]], align 16 // CHECK-NEXT: [[REG449:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG439]], align 16 -// CHECK-NEXT: [[REG450:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sel(signed char vector[16], signed char vector[16], bool vector[16])(<16 x i8> noundef [[REG448]], <16 x i8> noundef zeroinitializer, <16 x i8> noundef [[REG449]]) +// CHECK-NEXT: [[REG450:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sel(signed char vector[16], signed char vector[16], bool vector[16])(<16 x i8> [[REG448]], <16 x i8> zeroinitializer, <16 x i8> [[REG449]]) // CHECK-NEXT: [[REG451:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG450]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG451]] -// CHECK: define available_externally i64 @_mm_shuffle_pi8(i64 noundef [[REG452:[0-9a-zA-Z_%.]+]], i64 noundef [[REG453:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_shuffle_pi8(i64 [[REG452:[0-9a-zA-Z_%.]+]], i64 [[REG453:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG452]], i64* [[REG454:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG453]], i64* [[REG455:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <16 x i8> zeroinitializer, <16 x i8>* [[REG456:[0-9a-zA-Z_%.]+]], align 16 @@ -627,16 +627,16 @@ test_shuffle() { // CHECK-NEXT: [[REG471:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG470]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG471]], <16 x i8>* [[REG472:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG473:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG472]], align 16 -// CHECK-NEXT: [[REG474:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmplt(signed char vector[16], signed char vector[16])(<16 x i8> noundef [[REG473]], <16 x i8> noundef zeroinitializer) +// CHECK-NEXT: [[REG474:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmplt(signed char vector[16], signed char vector[16])(<16 x i8> [[REG473]], <16 x i8> zeroinitializer) // CHECK-NEXT: store <16 x i8> [[REG474]], <16 x i8>* [[REG475:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG476:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG464]], align 16 // CHECK-NEXT: [[REG477:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG464]], align 16 // CHECK-NEXT: [[REG478:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG472]], align 16 -// CHECK-NEXT: [[REG479:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_perm(signed char vector[16], signed char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG476]], <16 x i8> noundef [[REG477]], <16 x i8> noundef [[REG478]]) +// CHECK-NEXT: [[REG479:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_perm(signed char vector[16], signed char vector[16], unsigned char vector[16])(<16 x i8> [[REG476]], <16 x i8> [[REG477]], <16 x i8> [[REG478]]) // CHECK-NEXT: store <16 x i8> [[REG479]], <16 x i8>* [[REG464]], align 16 // CHECK-NEXT: [[REG480:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG464]], align 16 // CHECK-NEXT: [[REG481:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG475]], align 16 -// CHECK-NEXT: [[REG482:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sel(signed char vector[16], signed char vector[16], bool vector[16])(<16 x i8> noundef [[REG480]], <16 x i8> noundef zeroinitializer, <16 x i8> noundef [[REG481]]) +// CHECK-NEXT: [[REG482:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sel(signed char vector[16], signed char vector[16], bool vector[16])(<16 x i8> [[REG480]], <16 x i8> zeroinitializer, <16 x i8> [[REG481]]) // CHECK-NEXT: store <16 x i8> [[REG482]], <16 x i8>* [[REG464]], align 16 // CHECK-NEXT: [[REG483:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG464]], align 16 // CHECK-NEXT: [[REG484:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG483]] to <2 x i64> @@ -655,79 +655,79 @@ test_sign() { // CHECK-LABEL: @test_sign -// CHECK: define available_externally <2 x i64> @_mm_sign_epi8(<2 x i64> noundef [[REG486:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG487:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_sign_epi8(<2 x i64> [[REG486:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG487:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG486]], <2 x i64>* [[REG488:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG487]], <2 x i64>* [[REG489:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <16 x i8> zeroinitializer, <16 x i8>* [[REG490:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG491:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG489]], align 16 // CHECK-NEXT: [[REG492:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG491]] to <16 x i8> -// CHECK-NEXT: [[REG493:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmplt(signed char vector[16], signed char vector[16])(<16 x i8> noundef [[REG492]], <16 x i8> noundef zeroinitializer) +// CHECK-NEXT: [[REG493:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmplt(signed char vector[16], signed char vector[16])(<16 x i8> [[REG492]], <16 x i8> zeroinitializer) // CHECK-NEXT: store <16 x i8> [[REG493]], <16 x i8>* [[REG494:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG495:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG489]], align 16 // CHECK-NEXT: [[REG496:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG495]] to <16 x i8> -// CHECK-NEXT: [[REG497:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmpgt(signed char vector[16], signed char vector[16])(<16 x i8> noundef [[REG496]], <16 x i8> noundef zeroinitializer) -// CHECK-NEXT: [[REG498:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_neg(signed char vector[16])(<16 x i8> noundef [[REG497]]) +// CHECK-NEXT: [[REG497:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmpgt(signed char vector[16], signed char vector[16])(<16 x i8> [[REG496]], <16 x i8> zeroinitializer) +// CHECK-NEXT: [[REG498:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_neg(signed char vector[16])(<16 x i8> [[REG497]]) // CHECK-NEXT: store <16 x i8> [[REG498]], <16 x i8>* [[REG499:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG500:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG494]], align 16 // CHECK-NEXT: [[REG501:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG499]], align 16 -// CHECK-NEXT: [[REG502:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_add(signed char vector[16], signed char vector[16])(<16 x i8> noundef [[REG500]], <16 x i8> noundef [[REG501]]) +// CHECK-NEXT: [[REG502:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_add(signed char vector[16], signed char vector[16])(<16 x i8> [[REG500]], <16 x i8> [[REG501]]) // CHECK-NEXT: store <16 x i8> [[REG502]], <16 x i8>* [[REG503:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG504:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG488]], align 16 // CHECK-NEXT: [[REG505:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG504]] to <16 x i8> // CHECK-NEXT: [[REG506:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG503]], align 16 -// CHECK-NEXT: [[REG507:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_mul(signed char vector[16], signed char vector[16])(<16 x i8> noundef [[REG505]], <16 x i8> noundef [[REG506]]) +// CHECK-NEXT: [[REG507:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_mul(signed char vector[16], signed char vector[16])(<16 x i8> [[REG505]], <16 x i8> [[REG506]]) // CHECK-NEXT: [[REG508:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG507]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG508]] -// CHECK: define available_externally <2 x i64> @_mm_sign_epi16(<2 x i64> noundef [[REG509:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG510:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_sign_epi16(<2 x i64> [[REG509:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG510:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG509]], <2 x i64>* [[REG511:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG510]], <2 x i64>* [[REG512:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <8 x i16> zeroinitializer, <8 x i16>* [[REG513:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG514:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG512]], align 16 // CHECK-NEXT: [[REG515:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG514]] to <8 x i16> -// CHECK-NEXT: [[REG516:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmplt(short vector[8], short vector[8])(<8 x i16> noundef [[REG515]], <8 x i16> noundef zeroinitializer) +// CHECK-NEXT: [[REG516:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmplt(short vector[8], short vector[8])(<8 x i16> [[REG515]], <8 x i16> zeroinitializer) // CHECK-NEXT: store <8 x i16> [[REG516]], <8 x i16>* [[REG517:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG518:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG512]], align 16 // CHECK-NEXT: [[REG519:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG518]] to <8 x i16> -// CHECK-NEXT: [[REG520:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmpgt(short vector[8], short vector[8])(<8 x i16> noundef [[REG519]], <8 x i16> noundef zeroinitializer) -// CHECK-NEXT: [[REG521:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_neg(short vector[8])(<8 x i16> noundef [[REG520]]) +// CHECK-NEXT: [[REG520:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmpgt(short vector[8], short vector[8])(<8 x i16> [[REG519]], <8 x i16> zeroinitializer) +// CHECK-NEXT: [[REG521:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_neg(short vector[8])(<8 x i16> [[REG520]]) // CHECK-NEXT: store <8 x i16> [[REG521]], <8 x i16>* [[REG522:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG523:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG517]], align 16 // CHECK-NEXT: [[REG524:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG522]], align 16 -// CHECK-NEXT: [[REG525:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_add(short vector[8], short vector[8])(<8 x i16> noundef [[REG523]], <8 x i16> noundef [[REG524]]) +// CHECK-NEXT: [[REG525:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_add(short vector[8], short vector[8])(<8 x i16> [[REG523]], <8 x i16> [[REG524]]) // CHECK-NEXT: store <8 x i16> [[REG525]], <8 x i16>* [[REG526:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG527:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG511]], align 16 // CHECK-NEXT: [[REG528:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG527]] to <8 x i16> // CHECK-NEXT: [[REG529:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG526]], align 16 -// CHECK-NEXT: [[REG530:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mul(short vector[8], short vector[8])(<8 x i16> noundef [[REG528]], <8 x i16> noundef [[REG529]]) +// CHECK-NEXT: [[REG530:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mul(short vector[8], short vector[8])(<8 x i16> [[REG528]], <8 x i16> [[REG529]]) // CHECK-NEXT: [[REG531:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG530]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG531]] -// CHECK: define available_externally <2 x i64> @_mm_sign_epi32(<2 x i64> noundef [[REG532:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG533:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_sign_epi32(<2 x i64> [[REG532:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG533:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG532]], <2 x i64>* [[REG534:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG533]], <2 x i64>* [[REG535:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* [[REG536:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG537:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG535]], align 16 // CHECK-NEXT: [[REG538:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG537]] to <4 x i32> -// CHECK-NEXT: [[REG539:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmplt(int vector[4], int vector[4])(<4 x i32> noundef [[REG538]], <4 x i32> noundef zeroinitializer) +// CHECK-NEXT: [[REG539:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmplt(int vector[4], int vector[4])(<4 x i32> [[REG538]], <4 x i32> zeroinitializer) // CHECK-NEXT: store <4 x i32> [[REG539]], <4 x i32>* [[REG540:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG541:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG535]], align 16 // CHECK-NEXT: [[REG542:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG541]] to <4 x i32> -// CHECK-NEXT: [[REG543:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(int vector[4], int vector[4])(<4 x i32> noundef [[REG542]], <4 x i32> noundef zeroinitializer) -// CHECK-NEXT: [[REG544:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_neg(int vector[4])(<4 x i32> noundef [[REG543]]) +// CHECK-NEXT: [[REG543:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(int vector[4], int vector[4])(<4 x i32> [[REG542]], <4 x i32> zeroinitializer) +// CHECK-NEXT: [[REG544:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_neg(int vector[4])(<4 x i32> [[REG543]]) // CHECK-NEXT: store <4 x i32> [[REG544]], <4 x i32>* [[REG545:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG546:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG540]], align 16 // CHECK-NEXT: [[REG547:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG545]], align 16 -// CHECK-NEXT: [[REG548:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> noundef [[REG546]], <4 x i32> noundef [[REG547]]) +// CHECK-NEXT: [[REG548:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG546]], <4 x i32> [[REG547]]) // CHECK-NEXT: store <4 x i32> [[REG548]], <4 x i32>* [[REG549:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG550:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG534]], align 16 // CHECK-NEXT: [[REG551:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG550]] to <4 x i32> // CHECK-NEXT: [[REG552:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG549]], align 16 -// CHECK-NEXT: [[REG553:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mul(int vector[4], int vector[4])(<4 x i32> noundef [[REG551]], <4 x i32> noundef [[REG552]]) +// CHECK-NEXT: [[REG553:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mul(int vector[4], int vector[4])(<4 x i32> [[REG551]], <4 x i32> [[REG552]]) // CHECK-NEXT: [[REG554:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG553]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG554]] -// CHECK: define available_externally i64 @_mm_sign_pi8(i64 noundef [[REG555:[0-9a-zA-Z_%.]+]], i64 noundef [[REG556:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_sign_pi8(i64 [[REG555:[0-9a-zA-Z_%.]+]], i64 [[REG556:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG555]], i64* [[REG557:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG556]], i64* [[REG558:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <16 x i8> zeroinitializer, <16 x i8>* [[REG559:[0-9a-zA-Z_%.]+]], align 16 @@ -751,7 +751,7 @@ test_sign() { // CHECK-NEXT: [[REG577:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG576]] to <2 x i64> // CHECK-NEXT: [[REG578:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG575]], align 16 // CHECK-NEXT: [[REG579:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG578]] to <2 x i64> -// CHECK-NEXT: [[REG580:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_sign_epi8(<2 x i64> noundef [[REG577]], <2 x i64> noundef [[REG579]]) +// CHECK-NEXT: [[REG580:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_sign_epi8(<2 x i64> [[REG577]], <2 x i64> [[REG579]]) // CHECK-NEXT: [[REG581:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG580]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG581]], <16 x i8>* [[REG567]], align 16 // CHECK-NEXT: [[REG582:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG567]], align 16 @@ -759,7 +759,7 @@ test_sign() { // CHECK-NEXT: [[REG584:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG583]], i32 0 // CHECK-NEXT: ret i64 [[REG584]] -// CHECK: define available_externally i64 @_mm_sign_pi16(i64 noundef [[REG585:[0-9a-zA-Z_%.]+]], i64 noundef [[REG586:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_sign_pi16(i64 [[REG585:[0-9a-zA-Z_%.]+]], i64 [[REG586:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG585]], i64* [[REG587:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG586]], i64* [[REG588:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <8 x i16> zeroinitializer, <8 x i16>* [[REG589:[0-9a-zA-Z_%.]+]], align 16 @@ -783,7 +783,7 @@ test_sign() { // CHECK-NEXT: [[REG607:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG606]] to <2 x i64> // CHECK-NEXT: [[REG608:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG605]], align 16 // CHECK-NEXT: [[REG609:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG608]] to <2 x i64> -// CHECK-NEXT: [[REG610:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_sign_epi16(<2 x i64> noundef [[REG607]], <2 x i64> noundef [[REG609]]) +// CHECK-NEXT: [[REG610:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_sign_epi16(<2 x i64> [[REG607]], <2 x i64> [[REG609]]) // CHECK-NEXT: [[REG611:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG610]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG611]], <8 x i16>* [[REG597]], align 16 // CHECK-NEXT: [[REG612:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG597]], align 16 @@ -791,7 +791,7 @@ test_sign() { // CHECK-NEXT: [[REG614:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG613]], i32 0 // CHECK-NEXT: ret i64 [[REG614]] -// CHECK: define available_externally i64 @_mm_sign_pi32(i64 noundef [[REG615:[0-9a-zA-Z_%.]+]], i64 noundef [[REG616:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_sign_pi32(i64 [[REG615:[0-9a-zA-Z_%.]+]], i64 [[REG616:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG615]], i64* [[REG617:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG616]], i64* [[REG618:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* [[REG619:[0-9a-zA-Z_%.]+]], align 16 @@ -815,7 +815,7 @@ test_sign() { // CHECK-NEXT: [[REG637:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG636]] to <2 x i64> // CHECK-NEXT: [[REG638:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG635]], align 16 // CHECK-NEXT: [[REG639:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG638]] to <2 x i64> -// CHECK-NEXT: [[REG640:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_sign_epi32(<2 x i64> noundef [[REG637]], <2 x i64> noundef [[REG639]]) +// CHECK-NEXT: [[REG640:[0-9a-zA-Z_%.]+]] = call <2 x i64> @_mm_sign_epi32(<2 x i64> [[REG637]], <2 x i64> [[REG639]]) // CHECK-NEXT: [[REG641:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG640]] to <4 x i32> // CHECK-NEXT: store <4 x i32> [[REG641]], <4 x i32>* [[REG627]], align 16 // CHECK-NEXT: [[REG642:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG627]], align 16 @@ -831,56 +831,56 @@ test_maddubs() { // CHECK-LABEL: @test_maddubs -// CHECK: define available_externally <2 x i64> @_mm_maddubs_epi16(<2 x i64> noundef [[REG645:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG646:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_maddubs_epi16(<2 x i64> [[REG645:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG646:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG645]], <2 x i64>* [[REG647:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG646]], <2 x i64>* [[REG648:[0-9a-zA-Z_%.]+]], align 16 -// CHECK-NEXT: [[REG649:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(short)(i16 noundef signext 255) +// CHECK-NEXT: [[REG649:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(short)(i16 signext 255) // CHECK-NEXT: store <8 x i16> [[REG649]], <8 x i16>* [[REG650:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG651:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG647]], align 16 // CHECK-NEXT: [[REG652:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG651]] to <16 x i8> -// CHECK-NEXT: [[REG653:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackh(signed char vector[16])(<16 x i8> noundef [[REG652]]) +// CHECK-NEXT: [[REG653:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackh(signed char vector[16])(<16 x i8> [[REG652]]) // CHECK-NEXT: [[REG654:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG650]], align 16 -// CHECK-NEXT: [[REG655:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_and(short vector[8], short vector[8])(<8 x i16> noundef [[REG653]], <8 x i16> noundef [[REG654]]) +// CHECK-NEXT: [[REG655:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_and(short vector[8], short vector[8])(<8 x i16> [[REG653]], <8 x i16> [[REG654]]) // CHECK-NEXT: store <8 x i16> [[REG655]], <8 x i16>* [[REG656:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG657:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG647]], align 16 // CHECK-NEXT: [[REG658:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG657]] to <16 x i8> -// CHECK-NEXT: [[REG659:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackl(signed char vector[16])(<16 x i8> noundef [[REG658]]) +// CHECK-NEXT: [[REG659:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackl(signed char vector[16])(<16 x i8> [[REG658]]) // CHECK-NEXT: [[REG660:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG650]], align 16 -// CHECK-NEXT: [[REG661:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_and(short vector[8], short vector[8])(<8 x i16> noundef [[REG659]], <8 x i16> noundef [[REG660]]) +// CHECK-NEXT: [[REG661:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_and(short vector[8], short vector[8])(<8 x i16> [[REG659]], <8 x i16> [[REG660]]) // CHECK-NEXT: store <8 x i16> [[REG661]], <8 x i16>* [[REG662:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG663:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG648]], align 16 // CHECK-NEXT: [[REG664:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG663]] to <16 x i8> -// CHECK-NEXT: [[REG76:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackh(signed char vector[16])(<16 x i8> noundef [[REG664]]) +// CHECK-NEXT: [[REG76:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackh(signed char vector[16])(<16 x i8> [[REG664]]) // CHECK-NEXT: store <8 x i16> [[REG76]], <8 x i16>* [[REG665:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG666:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG648]], align 16 // CHECK-NEXT: [[REG667:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG666]] to <16 x i8> -// CHECK-NEXT: [[REG668:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackl(signed char vector[16])(<16 x i8> noundef [[REG667]]) +// CHECK-NEXT: [[REG668:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackl(signed char vector[16])(<16 x i8> [[REG667]]) // CHECK-NEXT: store <8 x i16> [[REG668]], <8 x i16>* [[REG669:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG670:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG656]], align 16 // CHECK-NEXT: [[REG671:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG665]], align 16 -// CHECK-NEXT: [[REG672:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mul(short vector[8], short vector[8])(<8 x i16> noundef [[REG670]], <8 x i16> noundef [[REG671]]) +// CHECK-NEXT: [[REG672:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mul(short vector[8], short vector[8])(<8 x i16> [[REG670]], <8 x i16> [[REG671]]) // CHECK-NEXT: store <8 x i16> [[REG672]], <8 x i16>* [[REG656]], align 16 // CHECK-NEXT: [[REG673:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG662]], align 16 // CHECK-NEXT: [[REG674:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG669]], align 16 -// CHECK-NEXT: [[REG675:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mul(short vector[8], short vector[8])(<8 x i16> noundef [[REG673]], <8 x i16> noundef [[REG674]]) +// CHECK-NEXT: [[REG675:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mul(short vector[8], short vector[8])(<8 x i16> [[REG673]], <8 x i16> [[REG674]]) // CHECK-NEXT: store <8 x i16> [[REG675]], <8 x i16>* [[REG662]], align 16 // CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG676:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG677:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG678:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG656]], align 16 // CHECK-NEXT: [[REG679:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG662]], align 16 -// CHECK-NEXT: [[REG680:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG678]], <8 x i16> noundef [[REG679]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG680:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG678]], <8 x i16> [[REG679]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG680]], <8 x i16>* [[REG665]], align 16 // CHECK-NEXT: [[REG681:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG656]], align 16 // CHECK-NEXT: [[REG682:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG662]], align 16 -// CHECK-NEXT: [[REG683:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG681]], <8 x i16> noundef [[REG682]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG683:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG681]], <8 x i16> [[REG682]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG683]], <8 x i16>* [[REG669]], align 16 // CHECK-NEXT: [[REG684:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG665]], align 16 // CHECK-NEXT: [[REG685:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG669]], align 16 -// CHECK-NEXT: [[REG686:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_adds(short vector[8], short vector[8])(<8 x i16> noundef [[REG684]], <8 x i16> noundef [[REG685]]) +// CHECK-NEXT: [[REG686:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_adds(short vector[8], short vector[8])(<8 x i16> [[REG684]], <8 x i16> [[REG685]]) // CHECK-NEXT: [[REG687:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG686]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG687]] -// CHECK: define available_externally i64 @_mm_maddubs_pi16(i64 noundef [[REG688:[0-9a-zA-Z_%.]+]], i64 noundef [[REG689:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_maddubs_pi16(i64 [[REG688:[0-9a-zA-Z_%.]+]], i64 [[REG689:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG688]], i64* [[REG690:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG689]], i64* [[REG691:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG692:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG690]], align 8 @@ -893,13 +893,13 @@ test_maddubs() { // CHECK-NEXT: store <8 x i16> [[REG84]], <8 x i16>* [[REG696:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG697:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG696]], align 16 // CHECK-NEXT: [[REG698:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG697]] to <16 x i8> -// CHECK-NEXT: [[REG699:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackl(signed char vector[16])(<16 x i8> noundef [[REG698]]) +// CHECK-NEXT: [[REG699:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackl(signed char vector[16])(<16 x i8> [[REG698]]) // CHECK-NEXT: store <8 x i16> [[REG699]], <8 x i16>* [[REG696]], align 16 -// CHECK-NEXT: [[REG700:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(short)(i16 noundef signext 255) +// CHECK-NEXT: [[REG700:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(short)(i16 signext 255) // CHECK-NEXT: store <8 x i16> [[REG700]], <8 x i16>* [[REG701:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG702:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG696]], align 16 // CHECK-NEXT: [[REG703:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG701]], align 16 -// CHECK-NEXT: [[REG704:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_and(short vector[8], short vector[8])(<8 x i16> noundef [[REG702]], <8 x i16> noundef [[REG703]]) +// CHECK-NEXT: [[REG704:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_and(short vector[8], short vector[8])(<8 x i16> [[REG702]], <8 x i16> [[REG703]]) // CHECK-NEXT: store <8 x i16> [[REG704]], <8 x i16>* [[REG696]], align 16 // CHECK-NEXT: [[REG705:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG691]], align 8 // CHECK-NEXT: [[REG706:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG705]], i32 0 @@ -911,25 +911,25 @@ test_maddubs() { // CHECK-NEXT: store <8 x i16> [[REG711]], <8 x i16>* [[REG712:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG713:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG712]], align 16 // CHECK-NEXT: [[REG714:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG713]] to <16 x i8> -// CHECK-NEXT: [[REG715:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackl(signed char vector[16])(<16 x i8> noundef [[REG714]]) +// CHECK-NEXT: [[REG715:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackl(signed char vector[16])(<16 x i8> [[REG714]]) // CHECK-NEXT: store <8 x i16> [[REG715]], <8 x i16>* [[REG712]], align 16 // CHECK-NEXT: [[REG716:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG696]], align 16 // CHECK-NEXT: [[REG717:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG712]], align 16 -// CHECK-NEXT: [[REG718:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mul(short vector[8], short vector[8])(<8 x i16> noundef [[REG716]], <8 x i16> noundef [[REG717]]) +// CHECK-NEXT: [[REG718:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mul(short vector[8], short vector[8])(<8 x i16> [[REG716]], <8 x i16> [[REG717]]) // CHECK-NEXT: store <8 x i16> [[REG718]], <8 x i16>* [[REG712]], align 16 // CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG719:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG720:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG721:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG712]], align 16 // CHECK-NEXT: [[REG722:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG712]], align 16 -// CHECK-NEXT: [[REG723:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG721]], <8 x i16> noundef [[REG722]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG723:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG721]], <8 x i16> [[REG722]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG723]], <8 x i16>* [[REG696]], align 16 // CHECK-NEXT: [[REG724:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG712]], align 16 // CHECK-NEXT: [[REG725:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG712]], align 16 -// CHECK-NEXT: [[REG726:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> noundef [[REG724]], <8 x i16> noundef [[REG725]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG726:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_perm(short vector[8], short vector[8], unsigned char vector[16])(<8 x i16> [[REG724]], <8 x i16> [[REG725]], <16 x i8> ) // CHECK-NEXT: store <8 x i16> [[REG726]], <8 x i16>* [[REG712]], align 16 // CHECK-NEXT: [[REG727:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG696]], align 16 // CHECK-NEXT: [[REG728:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG712]], align 16 -// CHECK-NEXT: [[REG729:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_adds(short vector[8], short vector[8])(<8 x i16> noundef [[REG727]], <8 x i16> noundef [[REG728]]) +// CHECK-NEXT: [[REG729:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_adds(short vector[8], short vector[8])(<8 x i16> [[REG727]], <8 x i16> [[REG728]]) // CHECK-NEXT: store <8 x i16> [[REG729]], <8 x i16>* [[REG696]], align 16 // CHECK-NEXT: [[REG730:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG696]], align 16 // CHECK-NEXT: [[REG731:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG730]] to <2 x i64> @@ -944,68 +944,68 @@ test_mulhrs() { // CHECK-LABEL: @test_mulhrs -// CHECK: define available_externally <2 x i64> @_mm_mulhrs_epi16(<2 x i64> noundef [[REG733:[0-9a-zA-Z_%.]+]], <2 x i64> noundef [[REG734:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <2 x i64> @_mm_mulhrs_epi16(<2 x i64> [[REG733:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG734:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG733]], <2 x i64>* [[REG735:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG734]], <2 x i64>* [[REG736:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG737:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG735]], align 16 // CHECK-NEXT: [[REG738:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG737]] to <8 x i16> -// CHECK-NEXT: [[REG739:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_unpackh(short vector[8])(<8 x i16> noundef [[REG738]]) +// CHECK-NEXT: [[REG739:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_unpackh(short vector[8])(<8 x i16> [[REG738]]) // CHECK-NEXT: store <4 x i32> [[REG739]], <4 x i32>* [[REG740:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG741:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG736]], align 16 // CHECK-NEXT: [[REG742:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG741]] to <8 x i16> -// CHECK-NEXT: [[REG743:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_unpackh(short vector[8])(<8 x i16> noundef [[REG742]]) +// CHECK-NEXT: [[REG743:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_unpackh(short vector[8])(<8 x i16> [[REG742]]) // CHECK-NEXT: store <4 x i32> [[REG743]], <4 x i32>* [[REG744:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG745:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG740]], align 16 // CHECK-NEXT: [[REG746:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG744]], align 16 -// CHECK-NEXT: [[REG747:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mul(int vector[4], int vector[4])(<4 x i32> noundef [[REG745]], <4 x i32> noundef [[REG746]]) +// CHECK-NEXT: [[REG747:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mul(int vector[4], int vector[4])(<4 x i32> [[REG745]], <4 x i32> [[REG746]]) // CHECK-NEXT: store <4 x i32> [[REG747]], <4 x i32>* [[REG740]], align 16 // CHECK-NEXT: [[REG748:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG735]], align 16 // CHECK-NEXT: [[REG749:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG748]] to <8 x i16> -// CHECK-NEXT: [[REG750:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_unpackl(short vector[8])(<8 x i16> noundef [[REG749]]) +// CHECK-NEXT: [[REG750:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_unpackl(short vector[8])(<8 x i16> [[REG749]]) // CHECK-NEXT: store <4 x i32> [[REG750]], <4 x i32>* [[REG744]], align 16 // CHECK-NEXT: [[REG751:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG736]], align 16 // CHECK-NEXT: [[REG752:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG751]] to <8 x i16> -// CHECK-NEXT: [[REG753:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_unpackl(short vector[8])(<8 x i16> noundef [[REG752]]) +// CHECK-NEXT: [[REG753:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_unpackl(short vector[8])(<8 x i16> [[REG752]]) // CHECK-NEXT: store <4 x i32> [[REG753]], <4 x i32>* [[REG754:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG755:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG744]], align 16 // CHECK-NEXT: [[REG756:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG754]], align 16 -// CHECK-NEXT: [[REG757:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mul(int vector[4], int vector[4])(<4 x i32> noundef [[REG755]], <4 x i32> noundef [[REG756]]) +// CHECK-NEXT: [[REG757:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mul(int vector[4], int vector[4])(<4 x i32> [[REG755]], <4 x i32> [[REG756]]) // CHECK-NEXT: store <4 x i32> [[REG757]], <4 x i32>* [[REG744]], align 16 -// CHECK-NEXT: [[REG758:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 noundef zeroext 14) +// CHECK-NEXT: [[REG758:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext 14) // CHECK-NEXT: store <4 x i32> [[REG758]], <4 x i32>* [[REG759:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG760:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG740]], align 16 // CHECK-NEXT: [[REG761:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG759]], align 16 -// CHECK-NEXT: [[REG762:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG760]], <4 x i32> noundef [[REG761]]) +// CHECK-NEXT: [[REG762:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG760]], <4 x i32> [[REG761]]) // CHECK-NEXT: store <4 x i32> [[REG762]], <4 x i32>* [[REG740]], align 16 // CHECK-NEXT: [[REG763:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG744]], align 16 // CHECK-NEXT: [[REG764:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG759]], align 16 -// CHECK-NEXT: [[REG765:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG763]], <4 x i32> noundef [[REG764]]) +// CHECK-NEXT: [[REG765:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG763]], <4 x i32> [[REG764]]) // CHECK-NEXT: store <4 x i32> [[REG765]], <4 x i32>* [[REG744]], align 16 -// CHECK-NEXT: [[REG766:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(int)(i32 noundef signext 1) +// CHECK-NEXT: [[REG766:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(int)(i32 signext 1) // CHECK-NEXT: store <4 x i32> [[REG766]], <4 x i32>* [[REG767:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG768:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG740]], align 16 // CHECK-NEXT: [[REG769:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG767]], align 16 -// CHECK-NEXT: [[REG770:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> noundef [[REG768]], <4 x i32> noundef [[REG769]]) +// CHECK-NEXT: [[REG770:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG768]], <4 x i32> [[REG769]]) // CHECK-NEXT: store <4 x i32> [[REG770]], <4 x i32>* [[REG740]], align 16 // CHECK-NEXT: [[REG771:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG740]], align 16 // CHECK-NEXT: [[REG772:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG767]], align 16 -// CHECK-NEXT: [[REG773:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG771]], <4 x i32> noundef [[REG772]]) +// CHECK-NEXT: [[REG773:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG771]], <4 x i32> [[REG772]]) // CHECK-NEXT: store <4 x i32> [[REG773]], <4 x i32>* [[REG740]], align 16 // CHECK-NEXT: [[REG774:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG744]], align 16 // CHECK-NEXT: [[REG775:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG767]], align 16 -// CHECK-NEXT: [[REG776:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> noundef [[REG774]], <4 x i32> noundef [[REG775]]) +// CHECK-NEXT: [[REG776:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG774]], <4 x i32> [[REG775]]) // CHECK-NEXT: store <4 x i32> [[REG776]], <4 x i32>* [[REG744]], align 16 // CHECK-NEXT: [[REG777:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG744]], align 16 // CHECK-NEXT: [[REG778:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG767]], align 16 -// CHECK-NEXT: [[REG779:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG777]], <4 x i32> noundef [[REG778]]) +// CHECK-NEXT: [[REG779:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG777]], <4 x i32> [[REG778]]) // CHECK-NEXT: store <4 x i32> [[REG779]], <4 x i32>* [[REG744]], align 16 // CHECK-NEXT: [[REG780:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG740]], align 16 // CHECK-NEXT: [[REG781:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG744]], align 16 -// CHECK-NEXT: [[REG782:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_pack(int vector[4], int vector[4])(<4 x i32> noundef [[REG780]], <4 x i32> noundef [[REG781]]) +// CHECK-NEXT: [[REG782:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_pack(int vector[4], int vector[4])(<4 x i32> [[REG780]], <4 x i32> [[REG781]]) // CHECK-NEXT: [[REG783:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG782]] to <2 x i64> // CHECK-NEXT: ret <2 x i64> [[REG783]] -// CHECK: define available_externally i64 @_mm_mulhrs_pi16(i64 noundef [[REG784:[0-9a-zA-Z_%.]+]], i64 noundef [[REG785:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_mulhrs_pi16(i64 [[REG784:[0-9a-zA-Z_%.]+]], i64 [[REG785:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG784]], i64* [[REG786:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG785]], i64* [[REG787:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG788:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG786]], align 8 @@ -1018,7 +1018,7 @@ test_mulhrs() { // CHECK-NEXT: store <4 x i32> [[REG794]], <4 x i32>* [[REG795:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG796:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG795]], align 16 // CHECK-NEXT: [[REG797:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG796]] to <8 x i16> -// CHECK-NEXT: [[REG798:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_unpackh(short vector[8])(<8 x i16> noundef [[REG797]]) +// CHECK-NEXT: [[REG798:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_unpackh(short vector[8])(<8 x i16> [[REG797]]) // CHECK-NEXT: store <4 x i32> [[REG798]], <4 x i32>* [[REG795]], align 16 // CHECK-NEXT: [[REG799:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG787]], align 8 // CHECK-NEXT: [[REG800:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG799]], i32 0 @@ -1030,31 +1030,31 @@ test_mulhrs() { // CHECK-NEXT: store <4 x i32> [[REG805]], <4 x i32>* [[REG806:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG807:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG806]], align 16 // CHECK-NEXT: [[REG808:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG807]] to <8 x i16> -// CHECK-NEXT: [[REG809:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_unpackh(short vector[8])(<8 x i16> noundef [[REG808]]) +// CHECK-NEXT: [[REG809:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_unpackh(short vector[8])(<8 x i16> [[REG808]]) // CHECK-NEXT: store <4 x i32> [[REG809]], <4 x i32>* [[REG806]], align 16 // CHECK-NEXT: [[REG810:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG795]], align 16 // CHECK-NEXT: [[REG811:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG806]], align 16 -// CHECK-NEXT: [[REG812:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mul(int vector[4], int vector[4])(<4 x i32> noundef [[REG810]], <4 x i32> noundef [[REG811]]) +// CHECK-NEXT: [[REG812:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mul(int vector[4], int vector[4])(<4 x i32> [[REG810]], <4 x i32> [[REG811]]) // CHECK-NEXT: store <4 x i32> [[REG812]], <4 x i32>* [[REG795]], align 16 -// CHECK-NEXT: [[REG813:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 noundef zeroext 14) +// CHECK-NEXT: [[REG813:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext 14) // CHECK-NEXT: store <4 x i32> [[REG813]], <4 x i32>* [[REG814:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG815:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG795]], align 16 // CHECK-NEXT: [[REG816:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG814]], align 16 -// CHECK-NEXT: [[REG817:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG815]], <4 x i32> noundef [[REG816]]) +// CHECK-NEXT: [[REG817:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG815]], <4 x i32> [[REG816]]) // CHECK-NEXT: store <4 x i32> [[REG817]], <4 x i32>* [[REG795]], align 16 -// CHECK-NEXT: [[REG818:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(int)(i32 noundef signext 1) +// CHECK-NEXT: [[REG818:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(int)(i32 signext 1) // CHECK-NEXT: store <4 x i32> [[REG818]], <4 x i32>* [[REG819:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG820:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG795]], align 16 // CHECK-NEXT: [[REG821:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG819]], align 16 -// CHECK-NEXT: [[REG822:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> noundef [[REG820]], <4 x i32> noundef [[REG821]]) +// CHECK-NEXT: [[REG822:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG820]], <4 x i32> [[REG821]]) // CHECK-NEXT: store <4 x i32> [[REG822]], <4 x i32>* [[REG795]], align 16 // CHECK-NEXT: [[REG823:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG795]], align 16 // CHECK-NEXT: [[REG824:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG819]], align 16 -// CHECK-NEXT: [[REG825:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG823]], <4 x i32> noundef [[REG824]]) +// CHECK-NEXT: [[REG825:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG823]], <4 x i32> [[REG824]]) // CHECK-NEXT: store <4 x i32> [[REG825]], <4 x i32>* [[REG795]], align 16 // CHECK-NEXT: [[REG826:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG795]], align 16 // CHECK-NEXT: [[REG827:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG806]], align 16 -// CHECK-NEXT: [[REG828:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_pack(int vector[4], int vector[4])(<4 x i32> noundef [[REG826]], <4 x i32> noundef [[REG827]]) +// CHECK-NEXT: [[REG828:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_pack(int vector[4], int vector[4])(<4 x i32> [[REG826]], <4 x i32> [[REG827]]) // CHECK-NEXT: store <8 x i16> [[REG828]], <8 x i16>* [[REG829:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG830:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG829]], align 16 // CHECK-NEXT: [[REG831:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG830]] to <2 x i64> diff --git a/clang/test/CodeGen/ppc-xmmintrin.c b/clang/test/CodeGen/ppc-xmmintrin.c index 9706a4f729b8adaad5b4a13c810f43389abd99c0..d3f18bfbb1e5b9425562247f8a7e3b94ed4614ab 100644 --- a/clang/test/CodeGen/ppc-xmmintrin.c +++ b/clang/test/CodeGen/ppc-xmmintrin.c @@ -32,7 +32,7 @@ test_add() { // CHECK-LABEL: @test_add -// CHECK: define available_externally <4 x float> @_mm_add_ps(<4 x float> noundef [[REG1:[0-9a-zA-Z_%.]+]], <4 x float> noundef [[REG2:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_add_ps(<4 x float> [[REG1:[0-9a-zA-Z_%.]+]], <4 x float> [[REG2:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG1]], <4 x float>* [[REG3:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x float> [[REG2]], <4 x float>* [[REG4:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG5:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG3]], align 16 @@ -40,14 +40,14 @@ test_add() { // CHECK-NEXT: [[REG7:[0-9a-zA-Z_%.]+]] = fadd <4 x float> [[REG5]], [[REG6]] // CHECK-NEXT: ret <4 x float> [[REG7]] -// CHECK: define available_externally <4 x float> @_mm_add_ss(<4 x float> noundef [[REG8:[0-9a-zA-Z_%.]+]], <4 x float> noundef [[REG9:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_add_ss(<4 x float> [[REG8:[0-9a-zA-Z_%.]+]], <4 x float> [[REG9:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG8]], <4 x float>* [[REG10:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x float> [[REG9]], <4 x float>* [[REG11:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG12:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG10]], align 16 -// CHECK-NEXT: [[REG13:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef [[REG12]], i32 noundef zeroext 0) +// CHECK-NEXT: [[REG13:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> [[REG12]], i32 zeroext 0) // CHECK-NEXT: store <4 x float> [[REG13]], <4 x float>* [[REG14:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG15:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG11]], align 16 -// CHECK-NEXT: [[REG16:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef [[REG15]], i32 noundef zeroext 0) +// CHECK-NEXT: [[REG16:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> [[REG15]], i32 zeroext 0) // CHECK-NEXT: store <4 x float> [[REG16]], <4 x float>* [[REG17:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG18:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG14]], align 16 // CHECK-NEXT: [[REG19:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG17]], align 16 @@ -55,7 +55,7 @@ test_add() { // CHECK-NEXT: store <4 x float> [[REG20]], <4 x float>* [[REG21:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG22:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG10]], align 16 // CHECK-NEXT: [[REG23:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG21]], align 16 -// CHECK-NEXT: [[REG24:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef [[REG22]], <4 x float> noundef [[REG23]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG24:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> [[REG22]], <4 x float> [[REG23]], <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG24]] void __attribute__((noinline)) @@ -70,16 +70,16 @@ test_avg() { // CHECK: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG25:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG25]]) +// CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG25]]) // CHECK-NEXT: [[REG27:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG26]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG27]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG28:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG29:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG28]]) +// CHECK-NEXT: [[REG29:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG28]]) // CHECK-NEXT: [[REG30:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG29]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG30]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG31:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG32:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG33:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_avg(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG31]], <8 x i16> noundef [[REG32]]) +// CHECK-NEXT: [[REG33:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_avg(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG31]], <8 x i16> [[REG32]]) // CHECK-NEXT: store <8 x i16> [[REG33]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG34:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG35:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG34]] to <2 x i64> @@ -90,16 +90,16 @@ test_avg() { // CHECK: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG37:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG38:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG37]]) +// CHECK-NEXT: [[REG38:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG37]]) // CHECK-NEXT: [[REG39:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG38]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG39]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG40:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG41:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG40]]) +// CHECK-NEXT: [[REG41:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG40]]) // CHECK-NEXT: [[REG42:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG41]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG42]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG43:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG44:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG45:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_avg(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG43]], <16 x i8> noundef [[REG44]]) +// CHECK-NEXT: [[REG45:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_avg(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG43]], <16 x i8> [[REG44]]) // CHECK-NEXT: store <16 x i8> [[REG45]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG46:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG47:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG46]] to <2 x i64> @@ -158,14 +158,14 @@ test_cmp() { // CHECK-NEXT: ret <4 x float> [[REG52]] // CHECK: define available_externally <4 x float> @_mm_cmpeq_ss -// CHECK: [[REG53:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG53:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG53]], <4 x float>* [[REG54:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG55:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG55:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG55]], <4 x float>* [[REG56:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG57:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG54]], align 16 // CHECK-NEXT: [[REG58:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG56]], align 16 -// CHECK-NEXT: call <4 x i32> @vec_cmpeq(float vector[4], float vector[4])(<4 x float> noundef [[REG57]], <4 x float> noundef [[REG58]]) -// CHECK: [[REG59:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef ) +// CHECK-NEXT: call <4 x i32> @vec_cmpeq(float vector[4], float vector[4])(<4 x float> [[REG57]], <4 x float> [[REG58]]) +// CHECK: [[REG59:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG59]] // CHECK: define available_externally <4 x float> @_mm_cmpge_ps @@ -174,14 +174,14 @@ test_cmp() { // CHECK-NEXT: ret <4 x float> [[REG61]] // CHECK: define available_externally <4 x float> @_mm_cmpge_ss -// CHECK: [[REG62:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG62:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG62]], <4 x float>* [[REG63:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG64:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG64:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG64]], <4 x float>* [[REG65:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG66:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG63]], align 16 // CHECK-NEXT: [[REG67:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG65]], align 16 -// CHECK-NEXT: call <4 x i32> @vec_cmpge(float vector[4], float vector[4])(<4 x float> noundef [[REG66]], <4 x float> noundef [[REG67]]) -// CHECK: [[REG68:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef ) +// CHECK-NEXT: call <4 x i32> @vec_cmpge(float vector[4], float vector[4])(<4 x float> [[REG66]], <4 x float> [[REG67]]) +// CHECK: [[REG68:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG68]] // CHECK: define available_externally <4 x float> @_mm_cmpgt_ps @@ -190,14 +190,14 @@ test_cmp() { // CHECK-NEXT: ret <4 x float> [[REG70]] // CHECK: define available_externally <4 x float> @_mm_cmpgt_ss -// CHECK: [[REG71:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG71:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG71]], <4 x float>* [[REG72:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG73:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG73:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG73]], <4 x float>* [[REG74:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG75:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG72]], align 16 // CHECK-NEXT: [[REG76:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG74]], align 16 -// CHECK-NEXT: call <4 x i32> @vec_cmpgt(float vector[4], float vector[4])(<4 x float> noundef [[REG75]], <4 x float> noundef [[REG76]]) -// CHECK: [[REG77:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef ) +// CHECK-NEXT: call <4 x i32> @vec_cmpgt(float vector[4], float vector[4])(<4 x float> [[REG75]], <4 x float> [[REG76]]) +// CHECK: [[REG77:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG77]] // CHECK: define available_externally <4 x float> @_mm_cmple_ps @@ -206,14 +206,14 @@ test_cmp() { // CHECK-NEXT: ret <4 x float> [[REG79]] // CHECK: define available_externally <4 x float> @_mm_cmple_ss -// CHECK: [[REG80:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG80:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG80]], <4 x float>* [[REG81:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG82:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG82:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG82]], <4 x float>* [[REG83:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG84:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG81]], align 16 // CHECK-NEXT: [[REG85:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG83]], align 16 -// CHECK-NEXT: call <4 x i32> @vec_cmple(float vector[4], float vector[4])(<4 x float> noundef [[REG84]], <4 x float> noundef [[REG85]]) -// CHECK: [[REG86:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef ) +// CHECK-NEXT: call <4 x i32> @vec_cmple(float vector[4], float vector[4])(<4 x float> [[REG84]], <4 x float> [[REG85]]) +// CHECK: [[REG86:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG86]] // CHECK: define available_externally <4 x float> @_mm_cmplt_ps @@ -222,14 +222,14 @@ test_cmp() { // CHECK-NEXT: ret <4 x float> [[REG88]] // CHECK: @_mm_cmplt_ss -// CHECK: [[REG89:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, i32 noundef zeroext 0) +// CHECK: [[REG89:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, i32 zeroext 0) // CHECK-NEXT: store <4 x float> [[REG89]], <4 x float>* [[REG90:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG91:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, i32 noundef zeroext 0) +// CHECK: [[REG91:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, i32 zeroext 0) // CHECK-NEXT: store <4 x float> [[REG91]], <4 x float>* [[REG92:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG93:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG90]], align 16 // CHECK-NEXT: [[REG94:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG92]], align 16 -// CHECK-NEXT: call <4 x i32> @vec_cmplt(float vector[4], float vector[4])(<4 x float> noundef [[REG93]], <4 x float> noundef [[REG94]]) -// CHECK: [[REG95:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef ) +// CHECK-NEXT: call <4 x i32> @vec_cmplt(float vector[4], float vector[4])(<4 x float> [[REG93]], <4 x float> [[REG94]]) +// CHECK: [[REG95:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG95]] // CHECK: define available_externally <4 x float> @_mm_cmpneq_ps @@ -238,19 +238,19 @@ test_cmp() { // CHECK-NEXT: store <4 x float> [[REG97]], <4 x float>* [[REG98:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG99:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG98]], align 16 // CHECK-NEXT: [[REG100:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG98]], align 16 -// CHECK-NEXT: [[REG101:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_nor(float vector[4], float vector[4])(<4 x float> noundef [[REG99]], <4 x float> noundef [[REG100]]) +// CHECK-NEXT: [[REG101:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_nor(float vector[4], float vector[4])(<4 x float> [[REG99]], <4 x float> [[REG100]]) // CHECK-NEXT: ret <4 x float> [[REG101]] // CHECK: define available_externally <4 x float> @_mm_cmpneq_ss -// CHECK: [[REG102:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG102:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG102]], <4 x float>* [[REG103:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG104:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG104:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG104]], <4 x float>* [[REG105:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG106:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG103]], align 16 // CHECK-NEXT: [[REG107:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG105]], align 16 -// CHECK-NEXT: call <4 x i32> @vec_cmpeq(float vector[4], float vector[4])(<4 x float> noundef [[REG106]], <4 x float> noundef [[REG107]]) +// CHECK-NEXT: call <4 x i32> @vec_cmpeq(float vector[4], float vector[4])(<4 x float> [[REG106]], <4 x float> [[REG107]]) // CHECK: call <4 x float> @vec_nor(float vector[4], float vector[4]) -// CHECK: [[REG108:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef ) +// CHECK: [[REG108:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG108]] // CHECK: define available_externally <4 x float> @_mm_cmpnge_ps @@ -259,14 +259,14 @@ test_cmp() { // CHECK-NEXT: ret <4 x float> [[REG110]] // CHECK: define available_externally <4 x float> @_mm_cmpnge_ss -// CHECK: [[REG111:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG111:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG111]], <4 x float>* [[REG112:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG113:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG113:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG113]], <4 x float>* [[REG114:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG115:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG112]], align 16 // CHECK-NEXT: [[REG116:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG114]], align 16 -// CHECK-NEXT: call <4 x i32> @vec_cmplt(float vector[4], float vector[4])(<4 x float> noundef [[REG115]], <4 x float> noundef [[REG116]]) -// CHECK: [[REG117:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef ) +// CHECK-NEXT: call <4 x i32> @vec_cmplt(float vector[4], float vector[4])(<4 x float> [[REG115]], <4 x float> [[REG116]]) +// CHECK: [[REG117:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG117]] // CHECK: define available_externally <4 x float> @_mm_cmpngt_ps @@ -275,14 +275,14 @@ test_cmp() { // CHECK-NEXT: ret <4 x float> [[REG119]] // CHECK: define available_externally <4 x float> @_mm_cmpngt_ss -// CHECK: [[REG120:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG120:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG120]], <4 x float>* [[REG121:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG122:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG122:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG122]], <4 x float>* [[REG123:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG124:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG121]], align 16 // CHECK-NEXT: [[REG125:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG123]], align 16 -// CHECK-NEXT: call <4 x i32> @vec_cmple(float vector[4], float vector[4])(<4 x float> noundef [[REG124]], <4 x float> noundef [[REG125]]) -// CHECK: [[REG126:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef ) +// CHECK-NEXT: call <4 x i32> @vec_cmple(float vector[4], float vector[4])(<4 x float> [[REG124]], <4 x float> [[REG125]]) +// CHECK: [[REG126:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG126]] // CHECK: define available_externally <4 x float> @_mm_cmpnle_ps @@ -291,14 +291,14 @@ test_cmp() { // CHECK-NEXT: ret <4 x float> [[REG128]] // CHECK: define available_externally <4 x float> @_mm_cmpnle_ss -// CHECK: [[REG129:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG129:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG129]], <4 x float>* [[REG130:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG131:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG131:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG131]], <4 x float>* [[REG132:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG133:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG130]], align 16 // CHECK-NEXT: [[REG134:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG132]], align 16 -// CHECK-NEXT: call <4 x i32> @vec_cmpgt(float vector[4], float vector[4])(<4 x float> noundef [[REG133]], <4 x float> noundef [[REG134]]) -// CHECK: [[REG135:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef ) +// CHECK-NEXT: call <4 x i32> @vec_cmpgt(float vector[4], float vector[4])(<4 x float> [[REG133]], <4 x float> [[REG134]]) +// CHECK: [[REG135:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG135]] // CHECK: define available_externally <4 x float> @_mm_cmpnlt_ps @@ -307,32 +307,32 @@ test_cmp() { // CHECK-NEXT: ret <4 x float> [[REG137]] // CHECK: define available_externally <4 x float> @_mm_cmpnlt_ss -// CHECK: [[REG138:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG138:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG138]], <4 x float>* [[REG139:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG140:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG140:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG140]], <4 x float>* [[REG141:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG142:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG139]], align 16 // CHECK-NEXT: [[REG143:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG141]], align 16 -// CHECK-NEXT: call <4 x i32> @vec_cmpge(float vector[4], float vector[4])(<4 x float> noundef [[REG142]], <4 x float> noundef [[REG143]]) -// CHECK: [[REG144:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef ) +// CHECK-NEXT: call <4 x i32> @vec_cmpge(float vector[4], float vector[4])(<4 x float> [[REG142]], <4 x float> [[REG143]]) +// CHECK: [[REG144:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG144]] // CHECK: define available_externally <4 x float> @_mm_cmpord_ps -// CHECK: [[REG145:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_abs(float vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG145:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_abs(float vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG146:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG145]] to <4 x i32> // CHECK-NEXT: store <4 x i32> [[REG146]], <4 x i32>* [[REG147:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG148:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_abs(float vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG148:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_abs(float vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG149:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG148]] to <4 x i32> // CHECK-NEXT: store <4 x i32> [[REG149]], <4 x i32>* [[REG150:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG151:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG147]], align 16 -// CHECK-NEXT: [[REG152:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef , <4 x i32> noundef [[REG151]]) +// CHECK-NEXT: [[REG152:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> , <4 x i32> [[REG151]]) // CHECK-NEXT: store <4 x i32> [[REG152]], <4 x i32>* [[REG153:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG154:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG150]], align 16 -// CHECK-NEXT: [[REG155:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef , <4 x i32> noundef [[REG154]]) +// CHECK-NEXT: [[REG155:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> , <4 x i32> [[REG154]]) // CHECK-NEXT: store <4 x i32> [[REG155]], <4 x i32>* [[REG156:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG157:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG153]], align 16 // CHECK-NEXT: [[REG158:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG156]], align 16 -// CHECK-NEXT: [[REG159:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_and(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK-NEXT: [[REG159:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_and(unsigned int vector[4], unsigned int vector[4])(<4 x i32> {{[0-9a-zA-Z_%.]+}}, <4 x i32> {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: [[REG160:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG159]] to <4 x float> // CHECK-NEXT: ret <4 x float> [[REG160]] @@ -344,64 +344,64 @@ test_cmp() { // CHECK-NEXT: [[REG165:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG164]] to <4 x i32> // CHECK-NEXT: store <4 x i32> [[REG165]], <4 x i32>* [[REG166:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG167:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG163]], align 16 -// CHECK-NEXT: [[REG168:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef , <4 x i32> noundef [[REG167]]) +// CHECK-NEXT: [[REG168:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> , <4 x i32> [[REG167]]) // CHECK-NEXT: store <4 x i32> [[REG168]], <4 x i32>* [[REG161:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG169:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG166]], align 16 -// CHECK-NEXT: [[REG170:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef , <4 x i32> noundef [[REG169]]) +// CHECK-NEXT: [[REG170:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> , <4 x i32> [[REG169]]) // CHECK-NEXT: store <4 x i32> [[REG170]], <4 x i32>* [[REG171:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG172:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG161]], align 16 // CHECK-NEXT: [[REG173:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG171]], align 16 -// CHECK-NEXT: [[REG174:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_and(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG172]], <4 x i32> noundef [[REG173]]) +// CHECK-NEXT: [[REG174:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_and(unsigned int vector[4], unsigned int vector[4])(<4 x i32> [[REG172]], <4 x i32> [[REG173]]) // CHECK-NEXT: store <4 x i32> [[REG174]], <4 x i32>* [[REG161]], align 16 // CHECK: [[REG175:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG161]], align 16 // CHECK-NEXT: [[REG176:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG175]] to <4 x float> -// CHECK-NEXT: [[REG177:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x float> noundef [[REG176]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG177:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float> [[REG176]], <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG177]] // CHECK: define available_externally <4 x float> @_mm_cmpunord_ps // CHECK: [[REG178:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG179:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_abs(float vector[4])(<4 x float> noundef [[REG178]]) +// CHECK-NEXT: [[REG179:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_abs(float vector[4])(<4 x float> [[REG178]]) // CHECK-NEXT: [[REG180:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG179]] to <4 x i32> // CHECK-NEXT: store <4 x i32> [[REG180]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG181:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG182:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_abs(float vector[4])(<4 x float> noundef [[REG181]]) +// CHECK-NEXT: [[REG182:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_abs(float vector[4])(<4 x float> [[REG181]]) // CHECK-NEXT: [[REG183:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG182]] to <4 x i32> // CHECK-NEXT: store <4 x i32> [[REG183]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG184:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG185:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG184]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG185:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> [[REG184]], <4 x i32> ) // CHECK-NEXT: store <4 x i32> [[REG185]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG186:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG187:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG186]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG187:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> [[REG186]], <4 x i32> ) // CHECK-NEXT: store <4 x i32> [[REG187]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG188:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG189:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG190:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_or(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG188]], <4 x i32> noundef [[REG189]]) +// CHECK-NEXT: [[REG190:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_or(unsigned int vector[4], unsigned int vector[4])(<4 x i32> [[REG188]], <4 x i32> [[REG189]]) // CHECK-NEXT: [[REG191:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG190]] to <4 x float> // CHECK-NEXT: ret <4 x float> [[REG191]] // CHECK: define available_externally <4 x float> @_mm_cmpunord_ss // CHECK: [[REG192:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG193:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_abs(float vector[4])(<4 x float> noundef [[REG192]]) +// CHECK-NEXT: [[REG193:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_abs(float vector[4])(<4 x float> [[REG192]]) // CHECK-NEXT: [[REG194:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG193]] to <4 x i32> // CHECK-NEXT: store <4 x i32> [[REG194]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG195:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG196:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_abs(float vector[4])(<4 x float> noundef [[REG195]]) +// CHECK-NEXT: [[REG196:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_abs(float vector[4])(<4 x float> [[REG195]]) // CHECK-NEXT: [[REG197:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG196]] to <4 x i32> // CHECK-NEXT: store <4 x i32> [[REG197]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG198:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG199:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG198]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG199:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> [[REG198]], <4 x i32> ) // CHECK-NEXT: store <4 x i32> [[REG199]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG200:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG201:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG200]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG201:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(unsigned int vector[4], unsigned int vector[4])(<4 x i32> [[REG200]], <4 x i32> ) // CHECK-NEXT: store <4 x i32> [[REG201]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG202:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG203:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG204:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_or(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef [[REG202]], <4 x i32> noundef [[REG203]]) +// CHECK-NEXT: [[REG204:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_or(unsigned int vector[4], unsigned int vector[4])(<4 x i32> [[REG202]], <4 x i32> [[REG203]]) // CHECK-NEXT: store <4 x i32> [[REG204]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG205:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG206:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG207:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG206]] to <4 x float> -// CHECK-NEXT: [[REG208:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef [[REG205]], <4 x float> noundef [[REG207]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG208:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> [[REG205]], <4 x float> [[REG207]], <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG208]] void __attribute__((noinline)) @@ -516,13 +516,13 @@ test_convert() { // CHECK-NEXT: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG245:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG246:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG247:[0-9a-zA-Z_%.]+]] = call <4 x float> @_mm_cvtpi32_ps(<4 x float> noundef [[REG245]], i64 noundef [[REG246]]) +// CHECK-NEXT: [[REG247:[0-9a-zA-Z_%.]+]] = call <4 x float> @_mm_cvtpi32_ps(<4 x float> [[REG245]], i64 [[REG246]]) // CHECK-NEXT: ret <4 x float> [[REG247]] // CHECK: define available_externally i64 @_mm_cvt_ps2pi // CHECK: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG248:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG249:[0-9a-zA-Z_%.]+]] = call i64 @_mm_cvtps_pi32(<4 x float> noundef [[REG248]]) +// CHECK-NEXT: [[REG249:[0-9a-zA-Z_%.]+]] = call i64 @_mm_cvtps_pi32(<4 x float> [[REG248]]) // CHECK-NEXT: ret i64 [[REG249]] // CHECK: define available_externally <4 x float> @_mm_cvt_si2ss @@ -530,13 +530,13 @@ test_convert() { // CHECK-NEXT: store i32 {{[0-9a-zA-Z_%.]+}}, i32* {{[0-9a-zA-Z_%.]+}}, align 4 // CHECK-NEXT: [[REG250:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG251:[0-9a-zA-Z_%.]+]] = load i32, i32* {{[0-9a-zA-Z_%.]+}}, align 4 -// CHECK-NEXT: [[REG252:[0-9a-zA-Z_%.]+]] = call <4 x float> @_mm_cvtsi32_ss(<4 x float> noundef [[REG250]], i32 noundef signext [[REG251]]) +// CHECK-NEXT: [[REG252:[0-9a-zA-Z_%.]+]] = call <4 x float> @_mm_cvtsi32_ss(<4 x float> [[REG250]], i32 signext [[REG251]]) // CHECK-NEXT: ret <4 x float> [[REG252]] // CHECK: define available_externally signext i32 @_mm_cvt_ss2si // CHECK: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG253:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG254:[0-9a-zA-Z_%.]+]] = call signext i32 @_mm_cvtss_si32(<4 x float> noundef [[REG253]]) +// CHECK-NEXT: [[REG254:[0-9a-zA-Z_%.]+]] = call signext i32 @_mm_cvtss_si32(<4 x float> [[REG253]]) // CHECK-NEXT: ret i32 [[REG254]] // CHECK: define available_externally <4 x float> @_mm_cvtpi16_ps @@ -550,7 +550,7 @@ test_convert() { // CHECK-NEXT: [[REG260:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG259]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG260]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG261:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG262:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vupklsh(short vector[8])(<8 x i16> noundef [[REG261]]) +// CHECK-NEXT: [[REG262:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vupklsh(short vector[8])(<8 x i16> [[REG261]]) // CHECK-NEXT: store <4 x i32> [[REG262]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG263:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG264:[0-9a-zA-Z_%.]+]] = call <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> [[REG263]], i32 0) @@ -613,10 +613,10 @@ test_convert() { // CHECK-NEXT: [[REG298:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG297]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG298]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG299:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG300:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_vupkhsb(signed char vector[16])(<16 x i8> noundef [[REG299]]) +// CHECK-NEXT: [[REG300:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_vupkhsb(signed char vector[16])(<16 x i8> [[REG299]]) // CHECK-NEXT: store <8 x i16> [[REG300]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG301:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG302:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vupkhsh(short vector[8])(<8 x i16> noundef [[REG301]]) +// CHECK-NEXT: [[REG302:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vupkhsh(short vector[8])(<8 x i16> [[REG301]]) // CHECK-NEXT: store <4 x i32> [[REG302]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG303:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG304:[0-9a-zA-Z_%.]+]] = call <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> [[REG303]], i32 0) @@ -627,14 +627,14 @@ test_convert() { // CHECK: define available_externally i64 @_mm_cvtps_pi16 // CHECK: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG306:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG307:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_rint(float vector[4])(<4 x float> noundef [[REG306]]) +// CHECK-NEXT: [[REG307:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_rint(float vector[4])(<4 x float> [[REG306]]) // CHECK-NEXT: store <4 x float> [[REG307]], <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG308:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG309:[0-9a-zA-Z_%.]+]] = call <4 x i32> @llvm.ppc.altivec.vctsxs(<4 x float> [[REG308]], i32 0) // CHECK-NEXT: store <4 x i32> [[REG309]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG310:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG311:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG312:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_pack(int vector[4], int vector[4])(<4 x i32> noundef [[REG310]], <4 x i32> noundef [[REG311]]) +// CHECK-NEXT: [[REG312:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_pack(int vector[4], int vector[4])(<4 x i32> [[REG310]], <4 x i32> [[REG311]]) // CHECK-NEXT: [[REG313:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG312]] to <2 x i64> // CHECK-NEXT: store <2 x i64> [[REG313]], <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG314:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 @@ -645,11 +645,11 @@ test_convert() { // CHECK: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG316:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG317:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG316]] to <2 x i64> -// CHECK-NEXT: [[REG318:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splat(long long vector[2], unsigned int)(<2 x i64> noundef [[REG317]], i32 noundef zeroext 0) +// CHECK-NEXT: [[REG318:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splat(long long vector[2], unsigned int)(<2 x i64> [[REG317]], i32 zeroext 0) // CHECK-NEXT: [[REG319:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG318]] to <4 x float> // CHECK-NEXT: store <4 x float> [[REG319]], <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG320:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG321:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_rint(float vector[4])(<4 x float> noundef [[REG320]]) +// CHECK-NEXT: [[REG321:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_rint(float vector[4])(<4 x float> [[REG320]]) // CHECK-NEXT: store <4 x float> [[REG321]], <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG322:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG323:[0-9a-zA-Z_%.]+]] = call <4 x i32> @llvm.ppc.altivec.vctsxs(<4 x float> [[REG322]], i32 0) @@ -662,17 +662,17 @@ test_convert() { // CHECK: define available_externally i64 @_mm_cvtps_pi8 // CHECK: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG327:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG328:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_rint(float vector[4])(<4 x float> noundef [[REG327]]) +// CHECK-NEXT: [[REG328:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_rint(float vector[4])(<4 x float> [[REG327]]) // CHECK-NEXT: store <4 x float> [[REG328]], <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG329:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG330:[0-9a-zA-Z_%.]+]] = call <4 x i32> @llvm.ppc.altivec.vctsxs(<4 x float> [[REG329]], i32 0) // CHECK-NEXT: store <4 x i32> [[REG330]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG331:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG332:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_pack(int vector[4], int vector[4])(<4 x i32> noundef [[REG331]], <4 x i32> noundef zeroinitializer) +// CHECK-NEXT: [[REG332:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_pack(int vector[4], int vector[4])(<4 x i32> [[REG331]], <4 x i32> zeroinitializer) // CHECK-NEXT: store <8 x i16> [[REG332]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG333:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG334:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG335:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_pack(short vector[8], short vector[8])(<8 x i16> noundef [[REG333]], <8 x i16> noundef [[REG334]]) +// CHECK-NEXT: [[REG335:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_pack(short vector[8], short vector[8])(<8 x i16> [[REG333]], <8 x i16> [[REG334]]) // CHECK-NEXT: store <16 x i8> [[REG335]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG336:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG337:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG336]] to <2 x i64> @@ -691,8 +691,8 @@ test_convert() { // CHECK-NEXT: [[REG344:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG343]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG344]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG345:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-LE-NEXT: [[REG346:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mergel(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG345]], <8 x i16> noundef zeroinitializer) -// CHECK-BE-NEXT: [[REG346:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mergel(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef zeroinitializer, <8 x i16> noundef [[REG345]]) +// CHECK-LE-NEXT: [[REG346:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mergel(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG345]], <8 x i16> zeroinitializer) +// CHECK-BE-NEXT: [[REG346:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mergel(unsigned short vector[8], unsigned short vector[8])(<8 x i16> zeroinitializer, <8 x i16> [[REG345]]) // CHECK-NEXT: [[REG347:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG346]] to <4 x i32> // CHECK-NEXT: store <4 x i32> [[REG347]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG348:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 @@ -713,13 +713,13 @@ test_convert() { // CHECK-NEXT: [[REG356:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG355]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG356]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG357:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-LE-NEXT: [[REG358:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_mergel(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG357]], <16 x i8> noundef zeroinitializer) -// CHECK-BE-NEXT: [[REG358:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_mergel(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef zeroinitializer, <16 x i8> noundef [[REG357]]) +// CHECK-LE-NEXT: [[REG358:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_mergel(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG357]], <16 x i8> zeroinitializer) +// CHECK-BE-NEXT: [[REG358:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_mergel(unsigned char vector[16], unsigned char vector[16])(<16 x i8> zeroinitializer, <16 x i8> [[REG357]]) // CHECK-NEXT: [[REG359:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG358]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG359]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG360:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-LE-NEXT: [[REG361:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mergeh(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef [[REG360]], <8 x i16> noundef zeroinitializer) -// CHECK-BE-NEXT: [[REG361:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mergeh(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef zeroinitializer, <8 x i16> noundef [[REG360]]) +// CHECK-LE-NEXT: [[REG361:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mergeh(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG360]], <8 x i16> zeroinitializer) +// CHECK-BE-NEXT: [[REG361:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_mergeh(unsigned short vector[8], unsigned short vector[8])(<8 x i16> zeroinitializer, <8 x i16> [[REG360]]) // CHECK-NEXT: [[REG362:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG361]] to <4 x i32> // CHECK-NEXT: store <4 x i32> [[REG362]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG363:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 @@ -794,20 +794,20 @@ test_convert() { // CHECK: define available_externally i64 @_mm_cvtt_ps2pi // CHECK: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK: [[REG393:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG394:[0-9a-zA-Z_%.]+]] = call i64 @_mm_cvttps_pi32(<4 x float> noundef [[REG393]]) +// CHECK-NEXT: [[REG394:[0-9a-zA-Z_%.]+]] = call i64 @_mm_cvttps_pi32(<4 x float> [[REG393]]) // CHECK-NEXT: ret i64 [[REG394]] // CHECK: define available_externally signext i32 @_mm_cvtt_ss2si // CHECK: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG395:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG396:[0-9a-zA-Z_%.]+]] = call signext i32 @_mm_cvttss_si32(<4 x float> noundef [[REG395]]) +// CHECK-NEXT: [[REG396:[0-9a-zA-Z_%.]+]] = call signext i32 @_mm_cvttss_si32(<4 x float> [[REG395]]) // CHECK-NEXT: ret i32 [[REG396]] // CHECK: define available_externally i64 @_mm_cvttps_pi32 // CHECK: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG397:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG398:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG397]] to <2 x i64> -// CHECK-NEXT: [[REG399:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splat(long long vector[2], unsigned int)(<2 x i64> noundef [[REG398]], i32 noundef zeroext 0) +// CHECK-NEXT: [[REG399:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splat(long long vector[2], unsigned int)(<2 x i64> [[REG398]], i32 zeroext 0) // CHECK-NEXT: [[REG400:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG399]] to <4 x float> // CHECK-NEXT: store <4 x float> [[REG400]], <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG401:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 @@ -844,7 +844,7 @@ test_div() { // CHECK-LABEL: @test_div -// CHECK: define available_externally <4 x float> @_mm_div_ps(<4 x float> noundef [[REG414:[0-9a-zA-Z_%.]+]], <4 x float> noundef [[REG415:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_div_ps(<4 x float> [[REG414:[0-9a-zA-Z_%.]+]], <4 x float> [[REG415:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG414]], <4 x float>* [[REG416:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x float> [[REG415]], <4 x float>* [[REG417:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG418:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG416]], align 16 @@ -852,14 +852,14 @@ test_div() { // CHECK-NEXT: [[REG420:[0-9a-zA-Z_%.]+]] = fdiv <4 x float> [[REG418]], [[REG419]] // CHECK-NEXT: ret <4 x float> [[REG420]] -// CHECK: define available_externally <4 x float> @_mm_div_ss(<4 x float> noundef [[REG421:[0-9a-zA-Z_%.]+]], <4 x float> noundef [[REG422:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_div_ss(<4 x float> [[REG421:[0-9a-zA-Z_%.]+]], <4 x float> [[REG422:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG421]], <4 x float>* [[REG423:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x float> [[REG422]], <4 x float>* [[REG424:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG425:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG423]], align 16 -// CHECK-NEXT: [[REG426:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef [[REG425]], i32 noundef zeroext 0) +// CHECK-NEXT: [[REG426:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> [[REG425]], i32 zeroext 0) // CHECK-NEXT: store <4 x float> [[REG426]], <4 x float>* [[REG427:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG428:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG424]], align 16 -// CHECK-NEXT: [[REG429:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef [[REG428]], i32 noundef zeroext 0) +// CHECK-NEXT: [[REG429:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> [[REG428]], i32 zeroext 0) // CHECK-NEXT: store <4 x float> [[REG429]], <4 x float>* [[REG430:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG431:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG427]], align 16 // CHECK-NEXT: [[REG432:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG430]], align 16 @@ -867,7 +867,7 @@ test_div() { // CHECK-NEXT: store <4 x float> [[REG433]], <4 x float>* [[REG434:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG435:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG423]], align 16 // CHECK-NEXT: [[REG436:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG434]], align 16 -// CHECK-NEXT: [[REG437:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef [[REG435]], <4 x float> noundef [[REG436]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG437:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> [[REG435]], <4 x float> [[REG436]], <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG437]] void __attribute__((noinline)) @@ -997,7 +997,7 @@ test_load() { // CHECK-NEXT: store <4 x float> [[REG491]], <4 x float>* [[REG492:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG493:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG492]], align 16 // CHECK-NEXT: [[REG494:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG492]], align 16 -// CHECK-NEXT: [[REG495:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_perm(float vector[4], float vector[4], unsigned char vector[16])(<4 x float> noundef [[REG493]], <4 x float> noundef [[REG494]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG495:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_perm(float vector[4], float vector[4], unsigned char vector[16])(<4 x float> [[REG493]], <4 x float> [[REG494]], <16 x i8> ) // CHECK-NEXT: store <4 x float> [[REG495]], <4 x float>* [[REG496:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG497:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG496]], align 16 // CHECK-NEXT: ret <4 x float> [[REG497]] @@ -1021,7 +1021,7 @@ test_logic() { // CHECK-NEXT: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG499:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG500:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG501:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_or(float vector[4], float vector[4])(<4 x float> noundef [[REG499]], <4 x float> noundef [[REG500]]) +// CHECK-NEXT: [[REG501:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_or(float vector[4], float vector[4])(<4 x float> [[REG499]], <4 x float> [[REG500]]) // CHECK-NEXT: ret <4 x float> [[REG501]] // CHECK: define available_externally <4 x float> @_mm_and_ps @@ -1029,7 +1029,7 @@ test_logic() { // CHECK-NEXT: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG502:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG503:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG504:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_and(float vector[4], float vector[4])(<4 x float> noundef [[REG502]], <4 x float> noundef [[REG503]]) +// CHECK-NEXT: [[REG504:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_and(float vector[4], float vector[4])(<4 x float> [[REG502]], <4 x float> [[REG503]]) // CHECK-NEXT: ret <4 x float> [[REG504]] // CHECK: define available_externally <4 x float> @_mm_andnot_ps @@ -1037,7 +1037,7 @@ test_logic() { // CHECK-NEXT: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG505:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG506:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG507:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_andc(float vector[4], float vector[4])(<4 x float> noundef [[REG505]], <4 x float> noundef [[REG506]]) +// CHECK-NEXT: [[REG507:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_andc(float vector[4], float vector[4])(<4 x float> [[REG505]], <4 x float> [[REG506]]) // CHECK-NEXT: ret <4 x float> [[REG507]] // CHECK: define available_externally <4 x float> @_mm_xor_ps @@ -1045,7 +1045,7 @@ test_logic() { // CHECK-NEXT: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG508:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG509:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG510:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_xor(float vector[4], float vector[4])(<4 x float> noundef [[REG508]], <4 x float> noundef [[REG509]]) +// CHECK-NEXT: [[REG510:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_xor(float vector[4], float vector[4])(<4 x float> [[REG508]], <4 x float> [[REG509]]) // CHECK-NEXT: ret <4 x float> [[REG510]] void __attribute__((noinline)) @@ -1058,47 +1058,47 @@ test_max() { // CHECK-LABEL: @test_max -// CHECK: define available_externally <4 x float> @_mm_max_ps(<4 x float> noundef [[REG511:[0-9a-zA-Z_%.]+]], <4 x float> noundef [[REG512:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_max_ps(<4 x float> [[REG511:[0-9a-zA-Z_%.]+]], <4 x float> [[REG512:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG511]], <4 x float>* [[REG513:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x float> [[REG512]], <4 x float>* [[REG514:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG515:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG513]], align 16 // CHECK-NEXT: [[REG516:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG514]], align 16 -// CHECK-NEXT: [[REG517:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(float vector[4], float vector[4])(<4 x float> noundef [[REG515]], <4 x float> noundef [[REG516]]) +// CHECK-NEXT: [[REG517:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(float vector[4], float vector[4])(<4 x float> [[REG515]], <4 x float> [[REG516]]) // CHECK-NEXT: store <4 x i32> [[REG517]], <4 x i32>* [[REG518:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG519:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG514]], align 16 // CHECK-NEXT: [[REG520:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG513]], align 16 // CHECK-NEXT: [[REG521:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG518]], align 16 -// CHECK-NEXT: [[REG522:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], bool vector[4])(<4 x float> noundef [[REG519]], <4 x float> noundef [[REG520]], <4 x i32> noundef [[REG521]]) +// CHECK-NEXT: [[REG522:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], bool vector[4])(<4 x float> [[REG519]], <4 x float> [[REG520]], <4 x i32> [[REG521]]) // CHECK-NEXT: ret <4 x float> [[REG522]] // CHECK: define available_externally <4 x float> @_mm_max_ss -// CHECK: [[REG523:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG523:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG523]], <4 x float>* [[REG524:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG525:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG525:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG525]], <4 x float>* [[REG526:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG527:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG524]], align 16 // CHECK-NEXT: [[REG528:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG526]], align 16 -// CHECK-NEXT: call <4 x float> @vec_max(float vector[4], float vector[4])(<4 x float> noundef [[REG527]], <4 x float> noundef [[REG528]]) -// CHECK: [[REG529:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef ) +// CHECK-NEXT: call <4 x float> @vec_max(float vector[4], float vector[4])(<4 x float> [[REG527]], <4 x float> [[REG528]]) +// CHECK: [[REG529:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG529]] // CHECK: define available_externally i64 @_mm_max_pi16 // CHECK: [[REG530:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG531:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG530]]) +// CHECK-NEXT: [[REG531:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG530]]) // CHECK-NEXT: [[REG532:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG531]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG532]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG533:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG534:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG533]]) +// CHECK-NEXT: [[REG534:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG533]]) // CHECK-NEXT: [[REG535:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG534]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG535]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG536:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG537:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG538:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmpgt(short vector[8], short vector[8])(<8 x i16> noundef [[REG536]], <8 x i16> noundef [[REG537]]) +// CHECK-NEXT: [[REG538:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmpgt(short vector[8], short vector[8])(<8 x i16> [[REG536]], <8 x i16> [[REG537]]) // CHECK-NEXT: store <8 x i16> [[REG538]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG539:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG540:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG541:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG542:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sel(short vector[8], short vector[8], bool vector[8])(<8 x i16> noundef [[REG539]], <8 x i16> noundef [[REG540]], <8 x i16> noundef [[REG541]]) +// CHECK-NEXT: [[REG542:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sel(short vector[8], short vector[8], bool vector[8])(<8 x i16> [[REG539]], <8 x i16> [[REG540]], <8 x i16> [[REG541]]) // CHECK-NEXT: store <8 x i16> [[REG542]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG543:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG544:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG543]] to <2 x i64> @@ -1107,21 +1107,21 @@ test_max() { // CHECK: define available_externally i64 @_mm_max_pu8 // CHECK: [[REG546:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG547:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG546]]) +// CHECK-NEXT: [[REG547:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG546]]) // CHECK-NEXT: [[REG548:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG547]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG548]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG549:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG550:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG549]]) +// CHECK-NEXT: [[REG550:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG549]]) // CHECK-NEXT: [[REG551:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG550]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG551]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG552:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG553:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG554:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmpgt(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG552]], <16 x i8> noundef [[REG553]]) +// CHECK-NEXT: [[REG554:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmpgt(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG552]], <16 x i8> [[REG553]]) // CHECK-NEXT: store <16 x i8> [[REG554]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG555:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG556:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG557:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG558:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], bool vector[16])(<16 x i8> noundef [[REG555]], <16 x i8> noundef [[REG556]], <16 x i8> noundef [[REG557]]) +// CHECK-NEXT: [[REG558:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], bool vector[16])(<16 x i8> [[REG555]], <16 x i8> [[REG556]], <16 x i8> [[REG557]]) // CHECK-NEXT: store <16 x i8> [[REG558]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG559:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG560:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG559]] to <2 x i64> @@ -1154,47 +1154,47 @@ test_min() { // CHECK-LABEL: @test_min -// CHECK: define available_externally <4 x float> @_mm_min_ps(<4 x float> noundef [[REG517:[0-9a-zA-Z_%.]+]], <4 x float> noundef [[REG518:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_min_ps(<4 x float> [[REG517:[0-9a-zA-Z_%.]+]], <4 x float> [[REG518:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG517]], <4 x float>* [[REG564:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x float> [[REG518]], <4 x float>* [[REG565:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG566:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG565]], align 16 // CHECK-NEXT: [[REG567:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG564]], align 16 -// CHECK-NEXT: [[REG568:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(float vector[4], float vector[4])(<4 x float> noundef [[REG566]], <4 x float> noundef [[REG567]]) +// CHECK-NEXT: [[REG568:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_cmpgt(float vector[4], float vector[4])(<4 x float> [[REG566]], <4 x float> [[REG567]]) // CHECK-NEXT: store <4 x i32> [[REG568]], <4 x i32>* [[REG569:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG570:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG565]], align 16 // CHECK-NEXT: [[REG571:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG564]], align 16 // CHECK-NEXT: [[REG572:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG569]], align 16 -// CHECK-NEXT: [[REG573:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], bool vector[4])(<4 x float> noundef [[REG570]], <4 x float> noundef [[REG571]], <4 x i32> noundef [[REG572]]) +// CHECK-NEXT: [[REG573:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], bool vector[4])(<4 x float> [[REG570]], <4 x float> [[REG571]], <4 x i32> [[REG572]]) // CHECK-NEXT: ret <4 x float> [[REG573]] // CHECK: define available_externally <4 x float> @_mm_min_ss -// CHECK: [[REG574:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG574:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG574]], <4 x float>* [[REG575:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG576:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, {{i32|i32 noundef zeroext}} 0) +// CHECK: [[REG576:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, {{i32|i32 zeroext}} 0) // CHECK-NEXT: store <4 x float> [[REG576]], <4 x float>* [[REG577:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG578:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG575]], align 16 // CHECK-NEXT: [[REG579:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG577]], align 16 -// CHECK-NEXT: call <4 x float> @vec_min(float vector[4], float vector[4])(<4 x float> noundef [[REG578]], <4 x float> noundef [[REG579]]) -// CHECK: [[REG580:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x float> noundef {{[0-9a-zA-Z_%.]+}}, <4 x i32> noundef ) +// CHECK-NEXT: call <4 x float> @vec_min(float vector[4], float vector[4])(<4 x float> [[REG578]], <4 x float> [[REG579]]) +// CHECK: [[REG580:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG580]] // CHECK: define available_externally i64 @_mm_min_pi16 // CHECK: [[REG581:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG582:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG581]]) +// CHECK-NEXT: [[REG582:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG581]]) // CHECK-NEXT: [[REG583:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG582]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG583]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG584:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG585:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG584]]) +// CHECK-NEXT: [[REG585:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG584]]) // CHECK-NEXT: [[REG586:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG585]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG586]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG587:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG588:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG589:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmplt(short vector[8], short vector[8])(<8 x i16> noundef [[REG587]], <8 x i16> noundef [[REG588]]) +// CHECK-NEXT: [[REG589:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmplt(short vector[8], short vector[8])(<8 x i16> [[REG587]], <8 x i16> [[REG588]]) // CHECK-NEXT: store <8 x i16> [[REG589]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG590:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG591:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG592:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG593:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sel(short vector[8], short vector[8], bool vector[8])(<8 x i16> noundef [[REG590]], <8 x i16> noundef [[REG591]], <8 x i16> noundef [[REG592]]) +// CHECK-NEXT: [[REG593:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sel(short vector[8], short vector[8], bool vector[8])(<8 x i16> [[REG590]], <8 x i16> [[REG591]], <8 x i16> [[REG592]]) // CHECK-NEXT: store <8 x i16> [[REG593]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG594:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG595:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG594]] to <2 x i64> @@ -1203,21 +1203,21 @@ test_min() { // CHECK: define available_externally i64 @_mm_min_pu8 // CHECK: [[REG597:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG598:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG597]]) +// CHECK-NEXT: [[REG598:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG597]]) // CHECK-NEXT: [[REG599:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG598]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG599]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG600:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG601:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG600]]) +// CHECK-NEXT: [[REG601:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG600]]) // CHECK-NEXT: [[REG602:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG601]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG602]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG603:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG604:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG605:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmplt(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG603]], <16 x i8> noundef [[REG604]]) +// CHECK-NEXT: [[REG605:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmplt(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG603]], <16 x i8> [[REG604]]) // CHECK-NEXT: store <16 x i8> [[REG605]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG606:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG607:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG608:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG609:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], bool vector[16])(<16 x i8> noundef [[REG606]], <16 x i8> noundef [[REG607]], <16 x i8> noundef [[REG608]]) +// CHECK-NEXT: [[REG609:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], bool vector[16])(<16 x i8> [[REG606]], <16 x i8> [[REG607]], <16 x i8> [[REG608]]) // CHECK-NEXT: store <16 x i8> [[REG609]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG610:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG611:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG610]] to <2 x i64> @@ -1267,7 +1267,7 @@ test_move() { // CHECK-NEXT: [[REG620:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG621:[0-9a-zA-Z_%.]+]] = and i64 [[REG619]], [[REG620]] // CHECK-NEXT: [[REG622:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG623:[0-9a-zA-Z_%.]+]] = call i64 @_mm_cmpeq_pi8(i64 noundef [[REG621]], i64 noundef [[REG622]]) +// CHECK-NEXT: [[REG623:[0-9a-zA-Z_%.]+]] = call i64 @_mm_cmpeq_pi8(i64 [[REG621]], i64 [[REG622]]) // CHECK-NEXT: store i64 [[REG623]], i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG624:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG625:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 @@ -1288,7 +1288,7 @@ test_move() { // CHECK-NEXT: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG634:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG635:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG636:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef [[REG634]], <4 x float> noundef [[REG635]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG636:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> [[REG634]], <4 x float> [[REG635]], <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG636]] // CHECK: define available_externally <4 x float> @_mm_movehl_ps @@ -1298,7 +1298,7 @@ test_move() { // CHECK-NEXT: [[REG638:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG637]] to <2 x i64> // CHECK-NEXT: [[REG639:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG640:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG639]] to <2 x i64> -// CHECK-NEXT: [[REG641:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_mergel(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> noundef [[REG638]], <2 x i64> noundef [[REG640]]) +// CHECK-NEXT: [[REG641:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_mergel(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> [[REG638]], <2 x i64> [[REG640]]) // CHECK-NEXT: [[REG642:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG641]] to <4 x float> // CHECK-NEXT: ret <4 x float> [[REG642]] @@ -1309,7 +1309,7 @@ test_move() { // CHECK-NEXT: [[REG644:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG643]] to <2 x i64> // CHECK-NEXT: [[REG645:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG646:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG645]] to <2 x i64> -// CHECK-NEXT: [[REG647:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_mergeh(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> noundef [[REG644]], <2 x i64> noundef [[REG646]]) +// CHECK-NEXT: [[REG647:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_mergeh(unsigned long long vector[2], unsigned long long vector[2])(<2 x i64> [[REG644]], <2 x i64> [[REG646]]) // CHECK-NEXT: [[REG648:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG647]] to <4 x float> // CHECK-NEXT: ret <4 x float> [[REG648]] @@ -1327,8 +1327,8 @@ test_move() { // CHECK: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG653:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG654:[0-9a-zA-Z_%.]+]] = bitcast <4 x float> [[REG653]] to <16 x i8> -// CHECK-LE-NEXT: [[REG655:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG654]], <16 x i8> noundef bitcast (<4 x i32> to <16 x i8>)) -// CHECK-BE-NEXT: [[REG655:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG654]], <16 x i8> noundef bitcast (<4 x i32> to <16 x i8>)) +// CHECK-LE-NEXT: [[REG655:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG654]], <16 x i8> bitcast (<4 x i32> to <16 x i8>)) +// CHECK-BE-NEXT: [[REG655:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG654]], <16 x i8> bitcast (<4 x i32> to <16 x i8>)) // CHECK-NEXT: store <2 x i64> [[REG655]], <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG656:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-LE-NEXT: [[REG657:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG656]], i32 1 @@ -1362,7 +1362,7 @@ test_mul() { // CHECK-LABEL: @test_mul -// CHECK: define available_externally <4 x float> @_mm_mul_ps(<4 x float> noundef [[REG660:[0-9a-zA-Z_%.]+]], <4 x float> noundef [[REG661:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_mul_ps(<4 x float> [[REG660:[0-9a-zA-Z_%.]+]], <4 x float> [[REG661:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG660]], <4 x float>* [[REG662:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x float> [[REG661]], <4 x float>* [[REG663:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG664:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG662]], align 16 @@ -1370,14 +1370,14 @@ test_mul() { // CHECK-NEXT: [[REG666:[0-9a-zA-Z_%.]+]] = fmul <4 x float> [[REG664]], [[REG665]] // CHECK-NEXT: ret <4 x float> [[REG666]] -// CHECK: define available_externally <4 x float> @_mm_mul_ss(<4 x float> noundef [[REG667:[0-9a-zA-Z_%.]+]], <4 x float> noundef [[REG668:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_mul_ss(<4 x float> [[REG667:[0-9a-zA-Z_%.]+]], <4 x float> [[REG668:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG667]], <4 x float>* [[REG669:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x float> [[REG668]], <4 x float>* [[REG670:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG671:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG669]], align 16 -// CHECK-NEXT: [[REG672:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef [[REG671]], i32 noundef zeroext 0) +// CHECK-NEXT: [[REG672:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> [[REG671]], i32 zeroext 0) // CHECK-NEXT: store <4 x float> [[REG672]], <4 x float>* [[REG673:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG674:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG670]], align 16 -// CHECK-NEXT: [[REG675:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef [[REG674]], i32 noundef zeroext 0) +// CHECK-NEXT: [[REG675:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> [[REG674]], i32 zeroext 0) // CHECK-NEXT: store <4 x float> [[REG675]], <4 x float>* [[REG676:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG677:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG673]], align 16 // CHECK-NEXT: [[REG678:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG676]], align 16 @@ -1385,34 +1385,34 @@ test_mul() { // CHECK-NEXT: store <4 x float> [[REG679]], <4 x float>* [[REG680:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG681:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG669]], align 16 // CHECK-NEXT: [[REG682:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG680]], align 16 -// CHECK-NEXT: [[REG683:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef [[REG681]], <4 x float> noundef [[REG682]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG683:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> [[REG681]], <4 x float> [[REG682]], <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG683]] -// CHECK: define available_externally i64 @_mm_mulhi_pu16(i64 noundef [[REG684:[0-9a-zA-Z_%.]+]], i64 noundef [[REG685:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_mulhi_pu16(i64 [[REG684:[0-9a-zA-Z_%.]+]], i64 [[REG685:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG684]], i64* [[REG686:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG685]], i64* [[REG687:[0-9a-zA-Z_%.]+]], align 8 // CHECK-LE-NEXT: store <16 x i8> , <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-BE-NEXT: store <16 x i8> , <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG688:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG686]], align 8 -// CHECK-NEXT: [[REG689:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG688]]) +// CHECK-NEXT: [[REG689:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG688]]) // CHECK-NEXT: [[REG690:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG689]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG690]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG691:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG687]], align 8 -// CHECK-NEXT: [[REG692:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG691]]) +// CHECK-NEXT: [[REG692:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG691]]) // CHECK-NEXT: [[REG693:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG692]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG693]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG694:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG695:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG696:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmuleuh(<8 x i16> noundef [[REG694]], <8 x i16> noundef [[REG695]]) +// CHECK-NEXT: [[REG696:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmuleuh(<8 x i16> [[REG694]], <8 x i16> [[REG695]]) // CHECK-NEXT: store <4 x i32> [[REG696]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG697:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG698:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG699:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmulouh(<8 x i16> noundef [[REG697]], <8 x i16> noundef [[REG698]]) +// CHECK-NEXT: [[REG699:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmulouh(<8 x i16> [[REG697]], <8 x i16> [[REG698]]) // CHECK-NEXT: store <4 x i32> [[REG699]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG700:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG701:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG702:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG703:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(unsigned int vector[4], unsigned int vector[4], unsigned char vector[16])(<4 x i32> noundef [[REG700]], <4 x i32> noundef [[REG701]], <16 x i8> noundef [[REG702]]) +// CHECK-NEXT: [[REG703:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_perm(unsigned int vector[4], unsigned int vector[4], unsigned char vector[16])(<4 x i32> [[REG700]], <4 x i32> [[REG701]], <16 x i8> [[REG702]]) // CHECK-NEXT: [[REG704:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG703]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG704]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG705:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 @@ -1420,12 +1420,12 @@ test_mul() { // CHECK-NEXT: [[REG707:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG706]], i32 0 // CHECK-NEXT: ret i64 [[REG707]] -// CHECK: define available_externally i64 @_m_pmulhuw(i64 noundef [[REG708:[0-9a-zA-Z_%.]+]], i64 noundef [[REG709:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_m_pmulhuw(i64 [[REG708:[0-9a-zA-Z_%.]+]], i64 [[REG709:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG708]], i64* [[REG710:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG709]], i64* [[REG711:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG712:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG710]], align 8 // CHECK-NEXT: [[REG713:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG711]], align 8 -// CHECK-NEXT: [[REG714:[0-9a-zA-Z_%.]+]] = call i64 @_mm_mulhi_pu16(i64 noundef [[REG712]], i64 noundef [[REG713]]) +// CHECK-NEXT: [[REG714:[0-9a-zA-Z_%.]+]] = call i64 @_mm_mulhi_pu16(i64 [[REG712]], i64 [[REG713]]) // CHECK-NEXT: ret i64 [[REG714]] void __attribute__((noinline)) @@ -1453,20 +1453,20 @@ test_rcp() { // CHECK: define available_externally <4 x float> @_mm_rcp_ps // CHECK: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG716:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG717:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_re(float vector[4])(<4 x float> noundef [[REG716]]) +// CHECK-NEXT: [[REG717:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_re(float vector[4])(<4 x float> [[REG716]]) // CHECK-NEXT: ret <4 x float> [[REG717]] // CHECK: define available_externally <4 x float> @_mm_rcp_ss // CHECK: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG718:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG719:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef [[REG718]], i32 noundef zeroext 0) +// CHECK-NEXT: [[REG719:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> [[REG718]], i32 zeroext 0) // CHECK-NEXT: store <4 x float> [[REG719]], <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG720:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG721:[0-9a-zA-Z_%.]+]] = call <4 x float> @_mm_rcp_ps(<4 x float> noundef [[REG720]]) +// CHECK-NEXT: [[REG721:[0-9a-zA-Z_%.]+]] = call <4 x float> @_mm_rcp_ps(<4 x float> [[REG720]]) // CHECK-NEXT: store <4 x float> [[REG721]], <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG722:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG723:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG724:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef [[REG722]], <4 x float> noundef [[REG723]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG724:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> [[REG722]], <4 x float> [[REG723]], <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG724]] void __attribute__((noinline)) @@ -1478,18 +1478,18 @@ test_rsqrt() { // CHECK-LABEL: @test_rsqrt // CHECK: define available_externally <4 x float> @_mm_rsqrt_ps -// CHECK: [[REG725:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_rsqrte(float vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG725:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_rsqrte(float vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: ret <4 x float> [[REG725]] // CHECK: define available_externally <4 x float> @_mm_rsqrt_ss -// CHECK: [[REG726:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}, i32 noundef zeroext 0) +// CHECK: [[REG726:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> {{[0-9a-zA-Z_%.]+}}, i32 zeroext 0) // CHECK-NEXT: store <4 x float> [[REG726]], <4 x float>* [[REG727:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG728:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG727]], align 16 -// CHECK-NEXT: [[REG729:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_rsqrte(float vector[4])(<4 x float> noundef [[REG728]]) +// CHECK-NEXT: [[REG729:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_rsqrte(float vector[4])(<4 x float> [[REG728]]) // CHECK-NEXT: store <4 x float> [[REG729]], <4 x float>* [[REG730:[0-9a-zA_Z_%.]+]], align 16 // CHECK-NEXT: [[REG731:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG732:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG730]], align 16 -// CHECK-NEXT: [[REG733:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef [[REG731]], <4 x float> noundef [[REG732]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG733:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> [[REG731]], <4 x float> [[REG732]], <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG733]] void __attribute__((noinline)) @@ -1500,7 +1500,7 @@ test_sad() { // CHECK-LABEL: @test_sad -// CHECK: define available_externally i64 @_mm_sad_pu8(i64 noundef [[REG734:[0-9a-zA-Z_%.]+]], i64 noundef [[REG735:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_sad_pu8(i64 [[REG734:[0-9a-zA-Z_%.]+]], i64 [[REG735:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG734]], i64* [[REG736:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i64 [[REG735]], i64* [[REG737:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 @@ -1520,21 +1520,21 @@ test_sad() { // CHECK-NEXT: store <16 x i8> [[REG746]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG747:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG748:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG749:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_min(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG747]], <16 x i8> noundef [[REG748]]) +// CHECK-NEXT: [[REG749:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_min(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG747]], <16 x i8> [[REG748]]) // CHECK-NEXT: store <16 x i8> [[REG749]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG750:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG751:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG752:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_max(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG750]], <16 x i8> noundef [[REG751]]) +// CHECK-NEXT: [[REG752:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_max(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG750]], <16 x i8> [[REG751]]) // CHECK-NEXT: store <16 x i8> [[REG752]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG753:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG754:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG755:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sub(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef [[REG753]], <16 x i8> noundef [[REG754]]) +// CHECK-NEXT: [[REG755:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sub(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG753]], <16 x i8> [[REG754]]) // CHECK-NEXT: store <16 x i8> [[REG755]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG756:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG757:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sum4s(unsigned char vector[16], unsigned int vector[4])(<16 x i8> noundef [[REG756]], <4 x i32> noundef zeroinitializer) +// CHECK-NEXT: [[REG757:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sum4s(unsigned char vector[16], unsigned int vector[4])(<16 x i8> [[REG756]], <4 x i32> zeroinitializer) // CHECK-NEXT: store <4 x i32> [[REG757]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG758:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG759:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sums(<4 x i32> noundef [[REG758]], <4 x i32> noundef zeroinitializer) +// CHECK-NEXT: [[REG759:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sums(<4 x i32> [[REG758]], <4 x i32> zeroinitializer) // CHECK-NEXT: store <4 x i32> [[REG759]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG760:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG761:[0-9a-zA-Z_%.]+]] = extractelement <4 x i32> [[REG760]], i32 3 @@ -1561,7 +1561,7 @@ test_set() { // CHECK-LABEL: @test_set -// CHECK: define available_externally <4 x float> @_mm_set_ps(float noundef [[REG768:[0-9a-zA-Z_%.]+]], float noundef [[REG769:[0-9a-zA-Z_%.]+]], float noundef [[REG770:[0-9a-zA-Z_%.]+]], float noundef [[REG771:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_set_ps(float [[REG768:[0-9a-zA-Z_%.]+]], float [[REG769:[0-9a-zA-Z_%.]+]], float [[REG770:[0-9a-zA-Z_%.]+]], float [[REG771:[0-9a-zA-Z_%.]+]]) // CHECK: store float [[REG768]], float* [[REG772:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store float [[REG769]], float* [[REG773:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store float [[REG770]], float* [[REG774:[0-9a-zA-Z_%.]+]], align 4 @@ -1578,13 +1578,13 @@ test_set() { // CHECK-NEXT: [[REG784:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: ret <4 x float> [[REG784]] -// CHECK: define available_externally <4 x float> @_mm_set_ps1(float noundef [[REG785:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_set_ps1(float [[REG785:[0-9a-zA-Z_%.]+]]) // CHECK: store float [[REG785]], float* [[REG786:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG787:[0-9a-zA-Z_%.]+]] = load float, float* [[REG786]], align 4 -// CHECK-NEXT: [[REG788:[0-9a-zA-Z_%.]+]] = call <4 x float> @_mm_set1_ps(float noundef [[REG787]]) +// CHECK-NEXT: [[REG788:[0-9a-zA-Z_%.]+]] = call <4 x float> @_mm_set1_ps(float [[REG787]]) // CHECK-NEXT: ret <4 x float> [[REG788]] -// CHECK: define available_externally <4 x float> @_mm_set_ss(float noundef [[REG789:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_set_ss(float [[REG789:[0-9a-zA-Z_%.]+]]) // CHECK: store float [[REG789:[0-9a-zA-Z_%.]+]], float* [[REG790:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG791:[0-9a-zA-Z_%.]+]] = load float, float* [[REG790]], align 4 // CHECK-NEXT: [[REG792:[0-9a-zA-Z_%.]+]] = insertelement <4 x float> undef, float [[REG791]], i32 0 @@ -1595,7 +1595,7 @@ test_set() { // CHECK-NEXT: [[REG797:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG796]], align 16 // CHECK-NEXT: ret <4 x float> [[REG797]] -// CHECK: define available_externally <4 x float> @_mm_set1_ps(float noundef [[REG798:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_set1_ps(float [[REG798:[0-9a-zA-Z_%.]+]]) // CHECK: store float [[REG798]], float* [[REG799:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG800:[0-9a-zA-Z_%.]+]] = load float, float* [[REG799]], align 4 // CHECK-NEXT: [[REG801:[0-9a-zA-Z_%.]+]] = insertelement <4 x float> undef, float [[REG800]], i32 0 @@ -1609,7 +1609,7 @@ test_set() { // CHECK-NEXT: [[REG809:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG808]], align 16 // CHECK-NEXT: ret <4 x float> [[REG809]] -// CHECK: define available_externally <4 x float> @_mm_setr_ps(float noundef [[REG810:[0-9a-zA-Z_%.]+]], float noundef [[REG811:[0-9a-zA-Z_%.]+]], float noundef [[REG812:[0-9a-zA-Z_%.]+]], float noundef [[REG813:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_setr_ps(float [[REG810:[0-9a-zA-Z_%.]+]], float [[REG811:[0-9a-zA-Z_%.]+]], float [[REG812:[0-9a-zA-Z_%.]+]], float [[REG813:[0-9a-zA-Z_%.]+]]) // CHECK: store float [[REG810]], float* [[REG814:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store float [[REG811]], float* [[REG815:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: store float [[REG812]], float* [[REG816:[0-9a-zA-Z_%.]+]], align 4 @@ -1658,7 +1658,7 @@ test_shuffle() { // CHECK-LABEL: @test_shuffle -// CHECK: define available_externally i64 @_mm_shuffle_pi16(i64 noundef [[REG829:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG830:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally i64 @_mm_shuffle_pi16(i64 [[REG829:[0-9a-zA-Z_%.]+]], i32 signext [[REG830:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG829]], i64* [[REG831:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: store i32 [[REG830]], i32* [[REG832:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG833:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG832]], align 4 @@ -1710,22 +1710,22 @@ test_shuffle() { // CHECK-NEXT: store i16 [[REG865]], i16* [[REG867]] // CHECK-NEXT: [[REG868:[0-9a-zA-Z_%.]+]] = bitcast {{[0-9a-zA-Z_%.]+}}* {{[0-9a-zA-Z_%.]+}} to i64* // CHECK-NEXT: [[REG869:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG868]], align 8 -// CHECK-NEXT: [[REG870:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG869]]) +// CHECK-NEXT: [[REG870:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG869]]) // CHECK-NEXT: store <2 x i64> [[REG870]], <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG871:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG831]], align 8 -// CHECK-NEXT: [[REG872:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 noundef [[REG871]]) +// CHECK-NEXT: [[REG872:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG871]]) // CHECK-NEXT: store <2 x i64> [[REG872]], <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG873:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG874:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG875:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG876:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG875]] to <16 x i8> -// CHECK-NEXT: [[REG877:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_perm(unsigned long long vector[2], unsigned long long vector[2], unsigned char vector[16])(<2 x i64> noundef [[REG873]], <2 x i64> noundef [[REG874]], <16 x i8> noundef [[REG876]]) +// CHECK-NEXT: [[REG877:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_perm(unsigned long long vector[2], unsigned long long vector[2], unsigned char vector[16])(<2 x i64> [[REG873]], <2 x i64> [[REG874]], <16 x i8> [[REG876]]) // CHECK-NEXT: store <2 x i64> [[REG877]], <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG878:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG879:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG878]], i32 0 // CHECK-NEXT: ret i64 [[REG879]] -// CHECK: define available_externally <4 x float> @_mm_shuffle_ps(<4 x float> noundef [[REG880:[0-9a-zA-Z_%.]+]], <4 x float> noundef [[REG881:[0-9a-zA-Z_%.]+]], i32 noundef signext [[REG882:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_shuffle_ps(<4 x float> [[REG880:[0-9a-zA-Z_%.]+]], <4 x float> [[REG881:[0-9a-zA-Z_%.]+]], i32 signext [[REG882:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG880]], <4 x float>* [[REG883:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x float> [[REG881]], <4 x float>* [[REG884:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store i32 [[REG882]], i32* [[REG885:[0-9a-zA-Z_%.]+]], align 4 @@ -1778,7 +1778,7 @@ test_shuffle() { // CHECK-NEXT: [[REG924:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG925:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG926:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG925]] to <16 x i8> -// CHECK-NEXT: [[REG927:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_perm(float vector[4], float vector[4], unsigned char vector[16])(<4 x float> noundef [[REG923]], <4 x float> noundef [[REG924]], <16 x i8> noundef [[REG926]]) +// CHECK-NEXT: [[REG927:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_perm(float vector[4], float vector[4], unsigned char vector[16])(<4 x float> [[REG923]], <4 x float> [[REG924]], <16 x i8> [[REG926]]) // CHECK-NEXT: ret <4 x float> [[REG927]] // CHECK: define available_externally i64 @_m_pshufw @@ -1794,19 +1794,19 @@ test_sqrt() { // CHECK-LABEL: @test_sqrt // CHECK: define available_externally <4 x float> @_mm_sqrt_ps -// CHECK: [[REG929:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sqrt(float vector[4])(<4 x float> noundef {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG929:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sqrt(float vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}) // CHECK-NEXT: ret <4 x float> [[REG929]] // CHECK: define available_externally <4 x float> @_mm_sqrt_ss // CHECK: [[REG930:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG931:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef [[REG930]], i32 noundef zeroext 0) +// CHECK-NEXT: [[REG931:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> [[REG930]], i32 zeroext 0) // CHECK-NEXT: store <4 x float> [[REG931]], <4 x float>* [[REG932:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG933:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG932]], align 16 -// CHECK-NEXT: [[REG934:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sqrt(float vector[4])(<4 x float> noundef [[REG933]]) +// CHECK-NEXT: [[REG934:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sqrt(float vector[4])(<4 x float> [[REG933]]) // CHECK-NEXT: store <4 x float> [[REG934]], <4 x float>* [[REG935:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG936:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG937:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG935]], align 16 -// CHECK-NEXT: [[REG938:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef [[REG936]], <4 x float> noundef [[REG937]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG938:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> [[REG936]], <4 x float> [[REG937]], <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG938]] void __attribute__((noinline)) @@ -1828,7 +1828,7 @@ test_store() { // CHECK-NEXT: [[REG939:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG940:[0-9a-zA-Z_%.]+]] = load float*, float** {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG941:[0-9a-zA-Z_%.]+]] = bitcast float* [[REG940]] to <4 x float>* -// CHECK-NEXT: call void @vec_st(float vector[4], long, float vector[4]*)(<4 x float> noundef [[REG939]], i64 noundef 0, <4 x float>* noundef [[REG941]]) +// CHECK-NEXT: call void @vec_st(float vector[4], long, float vector[4]*)(<4 x float> [[REG939]], i64 0, <4 x float>* [[REG941]]) // CHECK-NEXT: ret void // CHECK: define available_externally void @_mm_store_ps1 @@ -1836,7 +1836,7 @@ test_store() { // CHECK-NEXT: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG942:[0-9a-zA-Z_%.]+]] = load float*, float** {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG943:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: call void @_mm_store1_ps(float* noundef [[REG942]], <4 x float> noundef [[REG943]]) +// CHECK-NEXT: call void @_mm_store1_ps(float* [[REG942]], <4 x float> [[REG943]]) // CHECK-NEXT: ret void // CHECK: define available_externally void @_mm_store_ss @@ -1852,11 +1852,11 @@ test_store() { // CHECK: store float* {{[0-9a-zA-Z_%.]+}}, float** {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG947:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG948:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef [[REG947]], i32 noundef zeroext 0) +// CHECK-NEXT: [[REG948:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> [[REG947]], i32 zeroext 0) // CHECK-NEXT: store <4 x float> [[REG948]], <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG949:[0-9a-zA-Z_%.]+]] = load float*, float** {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG950:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: call void @_mm_store_ps(float* noundef [[REG949]], <4 x float> noundef [[REG950]]) +// CHECK-NEXT: call void @_mm_store_ps(float* [[REG949]], <4 x float> [[REG950]]) // CHECK-NEXT: ret void // CHECK: define available_externally void @_mm_storeh_pi @@ -1888,11 +1888,11 @@ test_store() { // CHECK-NEXT: store <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG961:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG962:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: [[REG963:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_perm(float vector[4], float vector[4], unsigned char vector[16])(<4 x float> noundef [[REG961]], <4 x float> noundef [[REG962]], <16 x i8> noundef ) +// CHECK-NEXT: [[REG963:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_perm(float vector[4], float vector[4], unsigned char vector[16])(<4 x float> [[REG961]], <4 x float> [[REG962]], <16 x i8> ) // CHECK-NEXT: store <4 x float> [[REG963]], <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG964:[0-9a-zA-Z_%.]+]] = load float*, float** {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG965:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: call void @_mm_store_ps(float* noundef [[REG964]], <4 x float> noundef [[REG965]]) +// CHECK-NEXT: call void @_mm_store_ps(float* [[REG964]], <4 x float> [[REG965]]) // CHECK-NEXT: ret void void __attribute__((noinline)) @@ -1920,7 +1920,7 @@ test_stream() { // CHECK-NEXT: call void asm sideeffect "\09dcbtstt\090,$0", "b,~{memory}"(float* [[REG969]]) // CHECK-NEXT: [[REG970:[0-9a-zA-Z_%.]+]] = load float*, float** {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG971:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK-NEXT: call void @_mm_store_ps(float* noundef [[REG970]], <4 x float> noundef [[REG971]]) +// CHECK-NEXT: call void @_mm_store_ps(float* [[REG970]], <4 x float> [[REG971]]) // CHECK-NEXT: ret void void __attribute__((noinline)) @@ -1931,7 +1931,7 @@ test_sub() { // CHECK-LABEL: @test_sub -// CHECK: define available_externally <4 x float> @_mm_sub_ps(<4 x float> noundef [[REG972:[0-9a-zA-Z_%.]+]], <4 x float> noundef [[REG973:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_sub_ps(<4 x float> [[REG972:[0-9a-zA-Z_%.]+]], <4 x float> [[REG973:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG972]], <4 x float>* [[REG974:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x float> [[REG973]], <4 x float>* [[REG975:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG976:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG974]], align 16 @@ -1939,14 +1939,14 @@ test_sub() { // CHECK-NEXT: [[REG978:[0-9a-zA-Z_%.]+]] = fsub <4 x float> [[REG976]], [[REG977]] // CHECK-NEXT: ret <4 x float> [[REG978]] -// CHECK: define available_externally <4 x float> @_mm_sub_ss(<4 x float> noundef [[REG979:[0-9a-zA-Z_%.]+]], <4 x float> noundef [[REG980:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_sub_ss(<4 x float> [[REG979:[0-9a-zA-Z_%.]+]], <4 x float> [[REG980:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG979]], <4 x float>* [[REG981:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x float> [[REG980]], <4 x float>* [[REG982:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG983:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG981]], align 16 -// CHECK-NEXT: [[REG984:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef [[REG983]], i32 noundef zeroext 0) +// CHECK-NEXT: [[REG984:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> [[REG983]], i32 zeroext 0) // CHECK-NEXT: store <4 x float> [[REG984]], <4 x float>* [[REG985:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG986:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG982]], align 16 -// CHECK-NEXT: [[REG987:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef [[REG986]], i32 noundef zeroext 0) +// CHECK-NEXT: [[REG987:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> [[REG986]], i32 zeroext 0) // CHECK-NEXT: store <4 x float> [[REG987]], <4 x float>* [[REG988:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG989:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG985:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG990:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG988:[0-9a-zA-Z_%.]+]], align 16 @@ -1954,7 +1954,7 @@ test_sub() { // CHECK-NEXT: store <4 x float> [[REG991]], <4 x float>* [[REG992:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG993:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG981]], align 16 // CHECK-NEXT: [[REG994:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG992]], align 16 -// CHECK-NEXT: [[REG995:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef [[REG993]], <4 x float> noundef [[REG994]], <4 x i32> noundef ) +// CHECK-NEXT: [[REG995:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> [[REG993]], <4 x float> [[REG994]], <4 x i32> ) // CHECK-NEXT: ret <4 x float> [[REG995]] void __attribute__((noinline)) @@ -2077,18 +2077,18 @@ test_unpack() { // CHECK-LABEL: @test_unpack -// CHECK: define available_externally <4 x float> @_mm_unpackhi_ps(<4 x float> noundef [[REG1044:[0-9a-zA-Z_%.]+]], <4 x float> noundef [[REG1045:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_unpackhi_ps(<4 x float> [[REG1044:[0-9a-zA-Z_%.]+]], <4 x float> [[REG1045:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG1044]], <4 x float>* [[REG1046:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x float> [[REG1045]], <4 x float>* [[REG1047:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1048:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG1046]], align 16 // CHECK-NEXT: [[REG1049:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG1047]], align 16 -// CHECK-NEXT: [[REG1050:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_vmrglw(float vector[4], float vector[4])(<4 x float> noundef [[REG1048]], <4 x float> noundef [[REG1049]]) +// CHECK-NEXT: [[REG1050:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_vmrglw(float vector[4], float vector[4])(<4 x float> [[REG1048]], <4 x float> [[REG1049]]) // CHECK-NEXT: ret <4 x float> [[REG1050]] -// CHECK: define available_externally <4 x float> @_mm_unpacklo_ps(<4 x float> noundef [[REG1051:[0-9a-zA-Z_%.]+]], <4 x float> noundef [[REG1052:[0-9a-zA-Z_%.]+]]) +// CHECK: define available_externally <4 x float> @_mm_unpacklo_ps(<4 x float> [[REG1051:[0-9a-zA-Z_%.]+]], <4 x float> [[REG1052:[0-9a-zA-Z_%.]+]]) // CHECK: store <4 x float> [[REG1051]], <4 x float>* [[REG1053:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <4 x float> [[REG1052]], <4 x float>* [[REG1054:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1055:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG1053]], align 16 // CHECK-NEXT: [[REG1056:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG1054]], align 16 -// CHECK-NEXT: [[REG1057:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_vmrghw(float vector[4], float vector[4])(<4 x float> noundef [[REG1055]], <4 x float> noundef [[REG1056]]) +// CHECK-NEXT: [[REG1057:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_vmrghw(float vector[4], float vector[4])(<4 x float> [[REG1055]], <4 x float> [[REG1056]]) // CHECK-NEXT: ret <4 x float> [[REG1057]] diff --git a/clang/test/CodeGen/ppc64-align-struct.c b/clang/test/CodeGen/ppc64-align-struct.c index f341700c43ec7c0a0049c09b7a26f2243c99063f..08f311d9ac7122b70a1c61a8e9d09f5d0bd01f97 100644 --- a/clang/test/CodeGen/ppc64-align-struct.c +++ b/clang/test/CodeGen/ppc64-align-struct.c @@ -10,45 +10,45 @@ struct test5 { int x[17]; }; struct test6 { int x[17]; } __attribute__((aligned (16))); struct test7 { int x[17]; } __attribute__((aligned (32))); -// CHECK: define{{.*}} void @test1(i32 noundef signext %x, i64 %y.coerce) +// CHECK: define{{.*}} void @test1(i32 signext %x, i64 %y.coerce) void test1 (int x, struct test1 y) { } -// CHECK: define{{.*}} void @test2(i32 noundef signext %x, [1 x i128] %y.coerce) +// CHECK: define{{.*}} void @test2(i32 signext %x, [1 x i128] %y.coerce) void test2 (int x, struct test2 y) { } -// CHECK: define{{.*}} void @test3(i32 noundef signext %x, [2 x i128] %y.coerce) +// CHECK: define{{.*}} void @test3(i32 signext %x, [2 x i128] %y.coerce) void test3 (int x, struct test3 y) { } -// CHECK: define{{.*}} void @test4(i32 noundef signext %x, [2 x i64] %y.coerce) +// CHECK: define{{.*}} void @test4(i32 signext %x, [2 x i64] %y.coerce) void test4 (int x, struct test4 y) { } -// CHECK: define{{.*}} void @test5(i32 noundef signext %x, %struct.test5* noundef byval(%struct.test5) align 8 %y) +// CHECK: define{{.*}} void @test5(i32 signext %x, %struct.test5* byval(%struct.test5) align 8 %y) void test5 (int x, struct test5 y) { } -// CHECK: define{{.*}} void @test6(i32 noundef signext %x, %struct.test6* noundef byval(%struct.test6) align 16 %y) +// CHECK: define{{.*}} void @test6(i32 signext %x, %struct.test6* byval(%struct.test6) align 16 %y) void test6 (int x, struct test6 y) { } // This case requires run-time realignment of the incoming struct -// CHECK-LABEL: define{{.*}} void @test7(i32 noundef signext %x, %struct.test7* noundef byval(%struct.test7) align 16 %0) +// CHECK-LABEL: define{{.*}} void @test7(i32 signext %x, %struct.test7* byval(%struct.test7) align 16 %0) // CHECK: %y = alloca %struct.test7, align 32 // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64 void test7 (int x, struct test7 y) { } -// CHECK: define{{.*}} void @test1va(%struct.test1* noalias sret(%struct.test1) align 4 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) +// CHECK: define{{.*}} void @test1va(%struct.test1* noalias sret(%struct.test1) align 4 %[[AGG_RESULT:.*]], i32 signext %x, ...) // CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap // CHECK: %[[NEXT:[^ ]+]] = getelementptr inbounds i8, i8* %[[CUR]], i64 8 // CHECK: store i8* %[[NEXT]], i8** %ap @@ -66,7 +66,7 @@ struct test1 test1va (int x, ...) return y; } -// CHECK: define{{.*}} void @test2va(%struct.test2* noalias sret(%struct.test2) align 16 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) +// CHECK: define{{.*}} void @test2va(%struct.test2* noalias sret(%struct.test2) align 16 %[[AGG_RESULT:.*]], i32 signext %x, ...) // CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap // CHECK: %[[TMP0:[^ ]+]] = ptrtoint i8* %[[CUR]] to i64 // CHECK: %[[TMP1:[^ ]+]] = add i64 %[[TMP0]], 15 @@ -88,7 +88,7 @@ struct test2 test2va (int x, ...) return y; } -// CHECK: define{{.*}} void @test3va(%struct.test3* noalias sret(%struct.test3) align 32 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) +// CHECK: define{{.*}} void @test3va(%struct.test3* noalias sret(%struct.test3) align 32 %[[AGG_RESULT:.*]], i32 signext %x, ...) // CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap // CHECK: %[[TMP0:[^ ]+]] = ptrtoint i8* %[[CUR]] to i64 // CHECK: %[[TMP1:[^ ]+]] = add i64 %[[TMP0]], 15 @@ -110,7 +110,7 @@ struct test3 test3va (int x, ...) return y; } -// CHECK: define{{.*}} void @test4va(%struct.test4* noalias sret(%struct.test4) align 4 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) +// CHECK: define{{.*}} void @test4va(%struct.test4* noalias sret(%struct.test4) align 4 %[[AGG_RESULT:.*]], i32 signext %x, ...) // CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap // CHECK: %[[NEXT:[^ ]+]] = getelementptr inbounds i8, i8* %[[CUR]], i64 16 // CHECK: store i8* %[[NEXT]], i8** %ap @@ -128,7 +128,7 @@ struct test4 test4va (int x, ...) return y; } -// CHECK: define{{.*}} void @testva_longdouble(%struct.test_longdouble* noalias sret(%struct.test_longdouble) align 16 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) +// CHECK: define{{.*}} void @testva_longdouble(%struct.test_longdouble* noalias sret(%struct.test_longdouble) align 16 %[[AGG_RESULT:.*]], i32 signext %x, ...) // CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap // CHECK: %[[NEXT:[^ ]+]] = getelementptr inbounds i8, i8* %[[CUR]], i64 16 // CHECK: store i8* %[[NEXT]], i8** %ap @@ -147,7 +147,7 @@ struct test_longdouble testva_longdouble (int x, ...) return y; } -// CHECK: define{{.*}} void @testva_vector(%struct.test_vector* noalias sret(%struct.test_vector) align 16 %[[AGG_RESULT:.*]], i32 noundef signext %x, ...) +// CHECK: define{{.*}} void @testva_vector(%struct.test_vector* noalias sret(%struct.test_vector) align 16 %[[AGG_RESULT:.*]], i32 signext %x, ...) // CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap // CHECK: %[[TMP0:[^ ]+]] = ptrtoint i8* %[[CUR]] to i64 // CHECK: %[[TMP1:[^ ]+]] = add i64 %[[TMP0]], 15 diff --git a/clang/test/CodeGen/ppc64-complex-parms.c b/clang/test/CodeGen/ppc64-complex-parms.c index 919bf60943683961a6a144564d1d1120ca542db7..1d5ffc840b79a3653813d68e2e609cc5f3b8f0a8 100644 --- a/clang/test/CodeGen/ppc64-complex-parms.c +++ b/clang/test/CodeGen/ppc64-complex-parms.c @@ -12,63 +12,63 @@ __float128 crealf128(_Complex __float128); __float128 foo_f128(_Complex __float128 x) { return crealf128(x); } -// CHECK-F128: define{{.*}} fp128 @foo_f128(fp128 noundef {{[%A-Za-z0-9.]+}}, fp128 noundef {{[%A-Za-z0-9.]+}}) +// CHECK-F128: define{{.*}} fp128 @foo_f128(fp128 {{[%A-Za-z0-9.]+}}, fp128 {{[%A-Za-z0-9.]+}}) #endif float foo_float(_Complex float x) { return crealf(x); } -// CHECK: define{{.*}} float @foo_float(float noundef {{[%A-Za-z0-9.]+}}, float noundef {{[%A-Za-z0-9.]+}}) [[NUW:#[0-9]+]] { +// CHECK: define{{.*}} float @foo_float(float {{[%A-Za-z0-9.]+}}, float {{[%A-Za-z0-9.]+}}) [[NUW:#[0-9]+]] { double foo_double(_Complex double x) { return creal(x); } -// CHECK: define{{.*}} double @foo_double(double noundef {{[%A-Za-z0-9.]+}}, double noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} double @foo_double(double {{[%A-Za-z0-9.]+}}, double {{[%A-Za-z0-9.]+}}) [[NUW]] { long double foo_long_double(_Complex long double x) { return creall(x); } -// CHECK: define{{.*}} ppc_fp128 @foo_long_double(ppc_fp128 noundef {{[%A-Za-z0-9.]+}}, ppc_fp128 noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} ppc_fp128 @foo_long_double(ppc_fp128 {{[%A-Za-z0-9.]+}}, ppc_fp128 {{[%A-Za-z0-9.]+}}) [[NUW]] { __ibm128 foo_ibm128(_Complex __ibm128 x) { // We don't have a suffix for explicit __ibm128 type yet. Use *l instead. return creall(x); } -// CHECK: define{{.*}} ppc_fp128 @foo_ibm128(ppc_fp128 noundef {{[%A-Za-z0-9.]+}}, ppc_fp128 noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} ppc_fp128 @foo_ibm128(ppc_fp128 {{[%A-Za-z0-9.]+}}, ppc_fp128 {{[%A-Za-z0-9.]+}}) [[NUW]] { int foo_int(_Complex int x) { return __real__ x; } -// CHECK: define{{.*}} signext i32 @foo_int(i32 noundef {{[%A-Za-z0-9.]+}}, i32 noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} signext i32 @foo_int(i32 {{[%A-Za-z0-9.]+}}, i32 {{[%A-Za-z0-9.]+}}) [[NUW]] { short foo_short(_Complex short x) { return __real__ x; } -// CHECK: define{{.*}} signext i16 @foo_short(i16 noundef {{[%A-Za-z0-9.]+}}, i16 noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} signext i16 @foo_short(i16 {{[%A-Za-z0-9.]+}}, i16 {{[%A-Za-z0-9.]+}}) [[NUW]] { signed char foo_char(_Complex signed char x) { return __real__ x; } -// CHECK: define{{.*}} signext i8 @foo_char(i8 noundef {{[%A-Za-z0-9.]+}}, i8 noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} signext i8 @foo_char(i8 {{[%A-Za-z0-9.]+}}, i8 {{[%A-Za-z0-9.]+}}) [[NUW]] { long foo_long(_Complex long x) { return __real__ x; } -// CHECK: define{{.*}} i64 @foo_long(i64 noundef {{[%A-Za-z0-9.]+}}, i64 noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} i64 @foo_long(i64 {{[%A-Za-z0-9.]+}}, i64 {{[%A-Za-z0-9.]+}}) [[NUW]] { long long foo_long_long(_Complex long long x) { return __real__ x; } -// CHECK: define{{.*}} i64 @foo_long_long(i64 noundef {{[%A-Za-z0-9.]+}}, i64 noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} i64 @foo_long_long(i64 {{[%A-Za-z0-9.]+}}, i64 {{[%A-Za-z0-9.]+}}) [[NUW]] { void bar_float(void) { foo_float(2.0f - 2.5fi); @@ -84,7 +84,7 @@ void bar_float(void) { // CHECK: %[[VAR5:[A-Za-z0-9.]+]] = load float, float* %[[VAR4]], align 4 // CHECK: %[[VAR6:[A-Za-z0-9.]+]] = getelementptr inbounds { float, float }, { float, float }* %[[VAR1]], i32 0, i32 1 // CHECK: %[[VAR7:[A-Za-z0-9.]+]] = load float, float* %[[VAR6]], align 4 -// CHECK: %{{[A-Za-z0-9.]+}} = call float @foo_float(float noundef %[[VAR5]], float noundef %[[VAR7]]) +// CHECK: %{{[A-Za-z0-9.]+}} = call float @foo_float(float %[[VAR5]], float %[[VAR7]]) void bar_double(void) { foo_double(2.0 - 2.5i); @@ -100,7 +100,7 @@ void bar_double(void) { // CHECK: %[[VAR15:[A-Za-z0-9.]+]] = load double, double* %[[VAR14]], align 8 // CHECK: %[[VAR16:[A-Za-z0-9.]+]] = getelementptr inbounds { double, double }, { double, double }* %[[VAR11]], i32 0, i32 1 // CHECK: %[[VAR17:[A-Za-z0-9.]+]] = load double, double* %[[VAR16]], align 8 -// CHECK: %{{[A-Za-z0-9.]+}} = call double @foo_double(double noundef %[[VAR15]], double noundef %[[VAR17]]) +// CHECK: %{{[A-Za-z0-9.]+}} = call double @foo_double(double %[[VAR15]], double %[[VAR17]]) void bar_long_double(void) { foo_long_double(2.0L - 2.5Li); @@ -116,7 +116,7 @@ void bar_long_double(void) { // CHECK: %[[VAR25:[A-Za-z0-9.]+]] = load ppc_fp128, ppc_fp128* %[[VAR24]], align 16 // CHECK: %[[VAR26:[A-Za-z0-9.]+]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %[[VAR21]], i32 0, i32 1 // CHECK: %[[VAR27:[A-Za-z0-9.]+]] = load ppc_fp128, ppc_fp128* %[[VAR26]], align 16 -// CHECK: %{{[A-Za-z0-9.]+}} = call ppc_fp128 @foo_long_double(ppc_fp128 noundef %[[VAR25]], ppc_fp128 noundef %[[VAR27]]) +// CHECK: %{{[A-Za-z0-9.]+}} = call ppc_fp128 @foo_long_double(ppc_fp128 %[[VAR25]], ppc_fp128 %[[VAR27]]) void bar_ibm128(void) { foo_ibm128(2.0L - 2.5Li); @@ -132,7 +132,7 @@ void bar_ibm128(void) { // CHECK: %[[VAR25:[A-Za-z0-9.]+]] = load ppc_fp128, ppc_fp128* %[[VAR24]], align 16 // CHECK: %[[VAR26:[A-Za-z0-9.]+]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %[[VAR21]], i32 0, i32 1 // CHECK: %[[VAR27:[A-Za-z0-9.]+]] = load ppc_fp128, ppc_fp128* %[[VAR26]], align 16 -// CHECK: %{{[A-Za-z0-9.]+}} = call ppc_fp128 @foo_ibm128(ppc_fp128 noundef %[[VAR25]], ppc_fp128 noundef %[[VAR27]]) +// CHECK: %{{[A-Za-z0-9.]+}} = call ppc_fp128 @foo_ibm128(ppc_fp128 %[[VAR25]], ppc_fp128 %[[VAR27]]) void bar_int(void) { foo_int(2 - 3i); @@ -148,7 +148,7 @@ void bar_int(void) { // CHECK: %[[VAR35:[A-Za-z0-9.]+]] = load i32, i32* %[[VAR34]], align 4 // CHECK: %[[VAR36:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* %[[VAR31]], i32 0, i32 1 // CHECK: %[[VAR37:[A-Za-z0-9.]+]] = load i32, i32* %[[VAR36]], align 4 -// CHECK: %{{[A-Za-z0-9.]+}} = call signext i32 @foo_int(i32 noundef %[[VAR35]], i32 noundef %[[VAR37]]) +// CHECK: %{{[A-Za-z0-9.]+}} = call signext i32 @foo_int(i32 %[[VAR35]], i32 %[[VAR37]]) void bar_short(void) { foo_short(2 - 3i); @@ -164,7 +164,7 @@ void bar_short(void) { // CHECK: %[[VAR45:[A-Za-z0-9.]+]] = load i16, i16* %[[VAR44]], align 2 // CHECK: %[[VAR46:[A-Za-z0-9.]+]] = getelementptr inbounds { i16, i16 }, { i16, i16 }* %[[VAR41]], i32 0, i32 1 // CHECK: %[[VAR47:[A-Za-z0-9.]+]] = load i16, i16* %[[VAR46]], align 2 -// CHECK: %{{[A-Za-z0-9.]+}} = call signext i16 @foo_short(i16 noundef %[[VAR45]], i16 noundef %[[VAR47]]) +// CHECK: %{{[A-Za-z0-9.]+}} = call signext i16 @foo_short(i16 %[[VAR45]], i16 %[[VAR47]]) void bar_char(void) { foo_char(2 - 3i); @@ -180,7 +180,7 @@ void bar_char(void) { // CHECK: %[[VAR55:[A-Za-z0-9.]+]] = load i8, i8* %[[VAR54]], align 1 // CHECK: %[[VAR56:[A-Za-z0-9.]+]] = getelementptr inbounds { i8, i8 }, { i8, i8 }* %[[VAR51]], i32 0, i32 1 // CHECK: %[[VAR57:[A-Za-z0-9.]+]] = load i8, i8* %[[VAR56]], align 1 -// CHECK: %{{[A-Za-z0-9.]+}} = call signext i8 @foo_char(i8 noundef %[[VAR55]], i8 noundef %[[VAR57]]) +// CHECK: %{{[A-Za-z0-9.]+}} = call signext i8 @foo_char(i8 %[[VAR55]], i8 %[[VAR57]]) void bar_long(void) { foo_long(2L - 3Li); @@ -196,7 +196,7 @@ void bar_long(void) { // CHECK: %[[VAR65:[A-Za-z0-9.]+]] = load i64, i64* %[[VAR64]], align 8 // CHECK: %[[VAR66:[A-Za-z0-9.]+]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* %[[VAR61]], i32 0, i32 1 // CHECK: %[[VAR67:[A-Za-z0-9.]+]] = load i64, i64* %[[VAR66]], align 8 -// CHECK: %{{[A-Za-z0-9.]+}} = call i64 @foo_long(i64 noundef %[[VAR65]], i64 noundef %[[VAR67]]) +// CHECK: %{{[A-Za-z0-9.]+}} = call i64 @foo_long(i64 %[[VAR65]], i64 %[[VAR67]]) void bar_long_long(void) { foo_long_long(2LL - 3LLi); @@ -212,6 +212,6 @@ void bar_long_long(void) { // CHECK: %[[VAR75:[A-Za-z0-9.]+]] = load i64, i64* %[[VAR74]], align 8 // CHECK: %[[VAR76:[A-Za-z0-9.]+]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* %[[VAR71]], i32 0, i32 1 // CHECK: %[[VAR77:[A-Za-z0-9.]+]] = load i64, i64* %[[VAR76]], align 8 -// CHECK: %{{[A-Za-z0-9.]+}} = call i64 @foo_long_long(i64 noundef %[[VAR75]], i64 noundef %[[VAR77]]) +// CHECK: %{{[A-Za-z0-9.]+}} = call i64 @foo_long_long(i64 %[[VAR75]], i64 %[[VAR77]]) // CHECK: attributes [[NUW]] = { noinline nounwind{{.*}} } diff --git a/clang/test/CodeGen/ppc64-complex-return.c b/clang/test/CodeGen/ppc64-complex-return.c index b57fbddf22b2ec30e35593c7bb5807af1e6950f8..474a75385c2444674486fe2710e7ebd38e183dff 100644 --- a/clang/test/CodeGen/ppc64-complex-return.c +++ b/clang/test/CodeGen/ppc64-complex-return.c @@ -13,62 +13,62 @@ _Complex __float128 foo_f128(_Complex __float128 x) { return x; } -// CHECK-F128: define{{.*}} { fp128, fp128 } @foo_f128(fp128 noundef {{[%A-Za-z0-9.]+}}, fp128 noundef {{[%A-Za-z0-9.]+}}) [[NUW:#[0-9]+]] { +// CHECK-F128: define{{.*}} { fp128, fp128 } @foo_f128(fp128 {{[%A-Za-z0-9.]+}}, fp128 {{[%A-Za-z0-9.]+}}) [[NUW:#[0-9]+]] { #endif _Complex float foo_float(_Complex float x) { return x; } -// CHECK: define{{.*}} { float, float } @foo_float(float noundef {{[%A-Za-z0-9.]+}}, float noundef {{[%A-Za-z0-9.]+}}) [[NUW:#[0-9]+]] { +// CHECK: define{{.*}} { float, float } @foo_float(float {{[%A-Za-z0-9.]+}}, float {{[%A-Za-z0-9.]+}}) [[NUW:#[0-9]+]] { _Complex double foo_double(_Complex double x) { return x; } -// CHECK: define{{.*}} { double, double } @foo_double(double noundef {{[%A-Za-z0-9.]+}}, double noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} { double, double } @foo_double(double {{[%A-Za-z0-9.]+}}, double {{[%A-Za-z0-9.]+}}) [[NUW]] { _Complex long double foo_long_double(_Complex long double x) { return x; } -// CHECK: define{{.*}} { ppc_fp128, ppc_fp128 } @foo_long_double(ppc_fp128 noundef {{[%A-Za-z0-9.]+}}, ppc_fp128 noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} { ppc_fp128, ppc_fp128 } @foo_long_double(ppc_fp128 {{[%A-Za-z0-9.]+}}, ppc_fp128 {{[%A-Za-z0-9.]+}}) [[NUW]] { _Complex __ibm128 foo_ibm128(_Complex __ibm128 x) { return x; } -// CHECK: define{{.*}} { ppc_fp128, ppc_fp128 } @foo_ibm128(ppc_fp128 noundef {{[%A-Za-z0-9.]+}}, ppc_fp128 noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} { ppc_fp128, ppc_fp128 } @foo_ibm128(ppc_fp128 {{[%A-Za-z0-9.]+}}, ppc_fp128 {{[%A-Za-z0-9.]+}}) [[NUW]] { _Complex int foo_int(_Complex int x) { return x; } -// CHECK: define{{.*}} { i32, i32 } @foo_int(i32 noundef {{[%A-Za-z0-9.]+}}, i32 noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} { i32, i32 } @foo_int(i32 {{[%A-Za-z0-9.]+}}, i32 {{[%A-Za-z0-9.]+}}) [[NUW]] { _Complex short foo_short(_Complex short x) { return x; } -// CHECK: define{{.*}} { i16, i16 } @foo_short(i16 noundef {{[%A-Za-z0-9.]+}}, i16 noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} { i16, i16 } @foo_short(i16 {{[%A-Za-z0-9.]+}}, i16 {{[%A-Za-z0-9.]+}}) [[NUW]] { _Complex signed char foo_char(_Complex signed char x) { return x; } -// CHECK: define{{.*}} { i8, i8 } @foo_char(i8 noundef {{[%A-Za-z0-9.]+}}, i8 noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} { i8, i8 } @foo_char(i8 {{[%A-Za-z0-9.]+}}, i8 {{[%A-Za-z0-9.]+}}) [[NUW]] { _Complex long foo_long(_Complex long x) { return x; } -// CHECK: define{{.*}} { i64, i64 } @foo_long(i64 noundef {{[%A-Za-z0-9.]+}}, i64 noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} { i64, i64 } @foo_long(i64 {{[%A-Za-z0-9.]+}}, i64 {{[%A-Za-z0-9.]+}}) [[NUW]] { _Complex long long foo_long_long(_Complex long long x) { return x; } -// CHECK: define{{.*}} { i64, i64 } @foo_long_long(i64 noundef {{[%A-Za-z0-9.]+}}, i64 noundef {{[%A-Za-z0-9.]+}}) [[NUW]] { +// CHECK: define{{.*}} { i64, i64 } @foo_long_long(i64 {{[%A-Za-z0-9.]+}}, i64 {{[%A-Za-z0-9.]+}}) [[NUW]] { float bar_float(void) { return crealf(foo_float(2.0f - 2.5fi)); diff --git a/clang/test/CodeGen/ppc64-extend.c b/clang/test/CodeGen/ppc64-extend.c index 5d69cc958a42a39fee0e4f9cb63b422a05a12c9f..d358fdc914363ab643e612c75cb7f4dfaa5507d5 100644 --- a/clang/test/CodeGen/ppc64-extend.c +++ b/clang/test/CodeGen/ppc64-extend.c @@ -2,10 +2,10 @@ // RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s void f1(int x) { return; } -// CHECK: define{{.*}} void @f1(i32 noundef signext %x) [[NUW:#[0-9]+]] +// CHECK: define{{.*}} void @f1(i32 signext %x) [[NUW:#[0-9]+]] void f2(unsigned int x) { return; } -// CHECK: define{{.*}} void @f2(i32 noundef zeroext %x) [[NUW]] +// CHECK: define{{.*}} void @f2(i32 zeroext %x) [[NUW]] int f3(void) { return 0; } // CHECK: define{{.*}} signext i32 @f3() [[NUW]] diff --git a/clang/test/CodeGen/ppc64-inline-asm.c b/clang/test/CodeGen/ppc64-inline-asm.c index 4a901e23887c4015c0374010701a0b9d63e8902d..94c737a4e2433ea1fc92b210cbf293396e29f1b8 100644 --- a/clang/test/CodeGen/ppc64-inline-asm.c +++ b/clang/test/CodeGen/ppc64-inline-asm.c @@ -4,7 +4,7 @@ _Bool test_wc_i1(_Bool b1, _Bool b2) { _Bool o; asm("crand %0, %1, %2" : "=wc"(o) : "wc"(b1), "wc"(b2) : ); return o; -// CHECK-LABEL: define{{.*}} zeroext i1 @test_wc_i1(i1 noundef zeroext %b1, i1 noundef zeroext %b2) +// CHECK-LABEL: define{{.*}} zeroext i1 @test_wc_i1(i1 zeroext %b1, i1 zeroext %b2) // CHECK: call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) } @@ -12,7 +12,7 @@ int test_wc_i32(int b1, int b2) { int o; asm("crand %0, %1, %2" : "=wc"(o) : "wc"(b1), "wc"(b2) : ); return o; -// CHECK-LABEL: signext i32 @test_wc_i32(i32 noundef signext %b1, i32 noundef signext %b2) +// CHECK-LABEL: signext i32 @test_wc_i32(i32 signext %b1, i32 signext %b2) // CHECK: call i32 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i32 %b1, i32 %b2) } @@ -20,33 +20,33 @@ unsigned char test_wc_i8(unsigned char b1, unsigned char b2) { unsigned char o; asm("crand %0, %1, %2" : "=wc"(o) : "wc"(b1), "wc"(b2) : ); return o; -// CHECK-LABEL: zeroext i8 @test_wc_i8(i8 noundef zeroext %b1, i8 noundef zeroext %b2) +// CHECK-LABEL: zeroext i8 @test_wc_i8(i8 zeroext %b1, i8 zeroext %b2) // CHECK: call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i8 %b1, i8 %b2) } float test_fmaxf(float x, float y) { asm("xsmaxdp %x0, %x1, %x2" : "=ww"(x) : "ww"(x), "ww"(y)); return x; -// CHECK-LABEL: float @test_fmaxf(float noundef %x, float noundef %y) +// CHECK-LABEL: float @test_fmaxf(float %x, float %y) // CHECK: call float asm "xsmaxdp ${0:x}, ${1:x}, ${2:x}", "=^ww,^ww,^ww"(float %x, float %y) } double test_fmax(double x, double y) { asm("xsmaxdp %x0, %x1, %x2" : "=ws"(x) : "ws"(x), "ws"(y)); return x; -// CHECK-LABEL: double @test_fmax(double noundef %x, double noundef %y) +// CHECK-LABEL: double @test_fmax(double %x, double %y) // CHECK: call double asm "xsmaxdp ${0:x}, ${1:x}, ${2:x}", "=^ws,^ws,^ws"(double %x, double %y) } void testZ(void *addr) { asm volatile ("dcbz %y0\n" :: "Z"(*(unsigned char *)addr) : "memory"); -// CHECK-LABEL: void @testZ(i8* noundef %addr) +// CHECK-LABEL: void @testZ(i8* %addr) // CHECK: call void asm sideeffect "dcbz ${0:y}\0A", "*Z,~{memory}"(i8* %addr) } void testZwOff(void *addr, long long off) { asm volatile ("dcbz %y0\n" :: "Z"(*(unsigned char *)(addr + off)) : "memory"); -// CHECK-LABEL: void @testZwOff(i8* noundef %addr, i64 noundef %off) +// CHECK-LABEL: void @testZwOff(i8* %addr, i64 %off) // CHECK: %[[VAL:[^ ]+]] = getelementptr i8, i8* %addr, i64 %off // CHECK: call void asm sideeffect "dcbz ${0:y}\0A", "*Z,~{memory}"(i8* %[[VAL]]) } diff --git a/clang/test/CodeGen/ppc64-long-double.cpp b/clang/test/CodeGen/ppc64-long-double.cpp index e65b7412b0a10755c81333ba21c3ac120461849f..dac4a3537e3200751a6474ede0549ecabc20a9e0 100644 --- a/clang/test/CodeGen/ppc64-long-double.cpp +++ b/clang/test/CodeGen/ppc64-long-double.cpp @@ -42,6 +42,6 @@ int size = sizeof(x); long double foo(long double d) { return d; } -// FP64: double @_Z3fooe(double noundef %d) -// FP128: fp128 @_Z3foou9__ieee128(fp128 noundef %d) -// IBM128: ppc_fp128 @_Z3foog(ppc_fp128 noundef %d) +// FP64: double @_Z3fooe(double %d) +// FP128: fp128 @_Z3foou9__ieee128(fp128 %d) +// IBM128: ppc_fp128 @_Z3foog(ppc_fp128 %d) diff --git a/clang/test/CodeGen/ppc64-soft-float.c b/clang/test/CodeGen/ppc64-soft-float.c index 8bd8ceb06131938ac743bbcf133664e7e0c82026..eb96a63d3dd92dbf47fa97a3d225aaf9e7b5bef4 100644 --- a/clang/test/CodeGen/ppc64-soft-float.c +++ b/clang/test/CodeGen/ppc64-soft-float.c @@ -3,13 +3,13 @@ // Test float returns and params. -// CHECK: define{{.*}} float @func_p1(float noundef %x) +// CHECK: define{{.*}} float @func_p1(float %x) float func_p1(float x) { return x; } -// CHECK: define{{.*}} double @func_p2(double noundef %x) +// CHECK: define{{.*}} double @func_p2(double %x) double func_p2(double x) { return x; } -// CHECK: define{{.*}} ppc_fp128 @func_p3(ppc_fp128 noundef %x) +// CHECK: define{{.*}} ppc_fp128 @func_p3(ppc_fp128 %x) long double func_p3(long double x) { return x; } // Test homogeneous float aggregate passing and returning. diff --git a/clang/test/CodeGen/ppc64-vector.c b/clang/test/CodeGen/ppc64-vector.c index 31aa21904a54ce7fd9cf9dc7d3153e7455825b67..2b01a9e976bcea703f1cedb388f43e8ecb5795ee 100644 --- a/clang/test/CodeGen/ppc64-vector.c +++ b/clang/test/CodeGen/ppc64-vector.c @@ -9,7 +9,7 @@ typedef short v16i16 __attribute__((vector_size (32))); struct v16i16 { v16i16 x; }; -// CHECK: define{{.*}} i32 @test_v2i16(i32 noundef %x.coerce) +// CHECK: define{{.*}} i32 @test_v2i16(i32 %x.coerce) v2i16 test_v2i16(v2i16 x) { return x; @@ -21,25 +21,25 @@ v3i16 test_v3i16(v3i16 x) return x; } -// CHECK: define{{.*}} i64 @test_v4i16(i64 noundef %x.coerce) +// CHECK: define{{.*}} i64 @test_v4i16(i64 %x.coerce) v4i16 test_v4i16(v4i16 x) { return x; } -// CHECK: define{{.*}} <6 x i16> @test_v6i16(<6 x i16> noundef %x) +// CHECK: define{{.*}} <6 x i16> @test_v6i16(<6 x i16> %x) v6i16 test_v6i16(v6i16 x) { return x; } -// CHECK: define{{.*}} <8 x i16> @test_v8i16(<8 x i16> noundef %x) +// CHECK: define{{.*}} <8 x i16> @test_v8i16(<8 x i16> %x) v8i16 test_v8i16(v8i16 x) { return x; } -// CHECK: define{{.*}} void @test_v16i16(<16 x i16>* noalias sret(<16 x i16>) align 32 %agg.result, <16 x i16>* noundef %0) +// CHECK: define{{.*}} void @test_v16i16(<16 x i16>* noalias sret(<16 x i16>) align 32 %agg.result, <16 x i16>* %0) v16i16 test_v16i16(v16i16 x) { return x; diff --git a/clang/test/CodeGen/ppc64le-aggregates.c b/clang/test/CodeGen/ppc64le-aggregates.c index cc8606e31ae062c2d21534ccfcb579762b457e30..aca21761c9520605a2793dfdde4222de9ee4a7db 100644 --- a/clang/test/CodeGen/ppc64le-aggregates.c +++ b/clang/test/CodeGen/ppc64le-aggregates.c @@ -162,7 +162,7 @@ struct v7 func_v7(struct v7 x) { return x; } // CHECK: define{{.*}} [8 x <4 x i32>] @func_v8([8 x <4 x i32>] %x.coerce) struct v8 func_v8(struct v8 x) { return x; } -// CHECK: define{{.*}} void @func_v9(%struct.v9* noalias sret(%struct.v9) align 16 %agg.result, %struct.v9* noundef byval(%struct.v9) align 16 %x) +// CHECK: define{{.*}} void @func_v9(%struct.v9* noalias sret(%struct.v9) align 16 %agg.result, %struct.v9* byval(%struct.v9) align 16 %x) struct v9 func_v9(struct v9 x) { return x; } // CHECK: define{{.*}} [2 x <4 x i32>] @func_vab([2 x <4 x i32>] %x.coerce) @@ -220,7 +220,7 @@ struct v8 global_v8; void call_v8(void) { global_v8 = func_v8(global_v8); } // CHECK-LABEL: @call_v9 -// CHECK: call void @func_v9(%struct.v9* sret(%struct.v9) align 16 %{{[^ ]+}}, %struct.v9* noundef byval(%struct.v9) align 16 @global_v9) +// CHECK: call void @func_v9(%struct.v9* sret(%struct.v9) align 16 %{{[^ ]+}}, %struct.v9* byval(%struct.v9) align 16 @global_v9) struct v9 global_v9; void call_v9(void) { global_v9 = func_v9(global_v9); } @@ -279,7 +279,7 @@ struct v3f7 func_v3f7(struct v3f7 x) { return x; } // CHECK: define{{.*}} [8 x <4 x float>] @func_v3f8([8 x <4 x float>] %x.coerce) struct v3f8 func_v3f8(struct v3f8 x) { return x; } -// CHECK: define{{.*}} void @func_v3f9(%struct.v3f9* noalias sret(%struct.v3f9) align 16 %agg.result, %struct.v3f9* noundef byval(%struct.v3f9) align 16 %x) +// CHECK: define{{.*}} void @func_v3f9(%struct.v3f9* noalias sret(%struct.v3f9) align 16 %agg.result, %struct.v3f9* byval(%struct.v3f9) align 16 %x) struct v3f9 func_v3f9(struct v3f9 x) { return x; } // CHECK: define{{.*}} [2 x <4 x float>] @func_v3fab([2 x <4 x float>] %x.coerce) @@ -337,7 +337,7 @@ struct v3f8 global_v3f8; void call_v3f8(void) { global_v3f8 = func_v3f8(global_v3f8); } // CHECK-LABEL: @call_v3f9 -// CHECK: call void @func_v3f9(%struct.v3f9* sret(%struct.v3f9) align 16 %{{[^ ]+}}, %struct.v3f9* noundef byval(%struct.v3f9) align 16 @global_v3f9) +// CHECK: call void @func_v3f9(%struct.v3f9* sret(%struct.v3f9) align 16 %{{[^ ]+}}, %struct.v3f9* byval(%struct.v3f9) align 16 @global_v3f9) struct v3f9 global_v3f9; void call_v3f9(void) { global_v3f9 = func_v3f9(global_v3f9); } diff --git a/clang/test/CodeGen/ppc64le-f128Aggregates.c b/clang/test/CodeGen/ppc64le-f128Aggregates.c index 7d7fff4d51e2edec3ed97f13e582b644b3d72318..fb0ed01b7e1dc2e0f2edc867174a94bdd9149c55 100644 --- a/clang/test/CodeGen/ppc64le-f128Aggregates.c +++ b/clang/test/CodeGen/ppc64le-f128Aggregates.c @@ -42,7 +42,7 @@ struct fp7 func_f7(struct fp7 x) { return x; } // CHECK: define{{.*}} [8 x fp128] @func_f8([8 x fp128] %x.coerce) struct fp8 func_f8(struct fp8 x) { return x; } -// CHECK: define{{.*}} void @func_f9(%struct.fp9* noalias sret(%struct.fp9) align 16 %agg.result, %struct.fp9* noundef byval(%struct.fp9) align 16 %x) +// CHECK: define{{.*}} void @func_f9(%struct.fp9* noalias sret(%struct.fp9) align 16 %agg.result, %struct.fp9* byval(%struct.fp9) align 16 %x) struct fp9 func_f9(struct fp9 x) { return x; } // CHECK: define{{.*}} [2 x fp128] @func_fab([2 x fp128] %x.coerce) @@ -104,7 +104,7 @@ void call_fp8(void) { global_f8 = func_f8(global_f8); } // CHECK-LABEL: @call_fp9 // CHECK: %[[TMP1:[^ ]+]] = alloca %struct.fp9, align 16 -// CHECK: call void @func_f9(%struct.fp9* sret(%struct.fp9) align 16 %[[TMP2:[^ ]+]], %struct.fp9* noundef byval(%struct.fp9) align 16 @global_f9 +// CHECK: call void @func_f9(%struct.fp9* sret(%struct.fp9) align 16 %[[TMP2:[^ ]+]], %struct.fp9* byval(%struct.fp9) align 16 @global_f9 // CHECK: %[[TMP3:[^ ]+]] = bitcast %struct.fp9* %[[TMP2]] to i8* // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 bitcast (%struct.fp9* @global_f9 to i8*), i8* align 16 %[[TMP3]], i64 144, i1 false // CHECK: ret void diff --git a/clang/test/CodeGen/ppc64le-varargs-f128.c b/clang/test/CodeGen/ppc64le-varargs-f128.c index 1283aa49c9716bd5cfce19ba6f6bc074e4ae226b..246e77d8a19ff4655a283b520b8f8dde56b850f9 100644 --- a/clang/test/CodeGen/ppc64le-varargs-f128.c +++ b/clang/test/CodeGen/ppc64le-varargs-f128.c @@ -26,7 +26,7 @@ void foo_fq(__float128); // OMP-TARGET: %[[CUR:[0-9a-zA-Z_.]+]] = load i8*, i8** // OMP-TARGET: %[[V2:[0-9a-zA-Z_.]+]] = bitcast i8* %[[CUR]] to ppc_fp128* // OMP-TARGET: %[[V3:[0-9a-zA-Z_.]+]] = load ppc_fp128, ppc_fp128* %[[V2]], align 8 -// OMP-TARGET: call void @foo_ld(ppc_fp128 noundef %[[V3]]) +// OMP-TARGET: call void @foo_ld(ppc_fp128 %[[V3]]) // OMP-HOST-LABEL: define{{.*}} void @omp( // OMP-HOST: %[[AP1:[0-9a-zA-Z_.]+]] = bitcast i8** %[[AP:[0-9a-zA-Z_.]+]] to i8* @@ -38,7 +38,7 @@ void foo_fq(__float128); // OMP-HOST: %[[ALIGN:[0-9a-zA-Z_.]+]] = inttoptr i64 %[[V2]] to i8* // OMP-HOST: %[[V3:[0-9a-zA-Z_.]+]] = bitcast i8* %[[ALIGN]] to fp128* // OMP-HOST: %[[V4:[0-9a-zA-Z_.]+]] = load fp128, fp128* %[[V3]], align 16 -// OMP-HOST: call void @foo_ld(fp128 noundef %[[V4]]) +// OMP-HOST: call void @foo_ld(fp128 %[[V4]]) void omp(int n, ...) { va_list ap; va_start(ap, n); @@ -60,7 +60,7 @@ void omp(int n, ...) { // IEEE: %[[ALIGN:[0-9a-zA-Z_.]+]] = inttoptr i64 %[[V2]] to i8* // IEEE: %[[V3:[0-9a-zA-Z_.]+]] = bitcast i8* %[[ALIGN]] to fp128* // IEEE: %[[V4:[0-9a-zA-Z_.]+]] = load fp128, fp128* %[[V3]], align 16 -// IEEE: call void @foo_fq(fp128 noundef %[[V4]]) +// IEEE: call void @foo_fq(fp128 %[[V4]]) // IEEE: %[[AP2:[0-9a-zA-Z_.]+]] = bitcast i8** %[[AP]] to i8* // IEEE: call void @llvm.va_end(i8* %[[AP2]]) void f128(int n, ...) { @@ -80,17 +80,17 @@ void f128(int n, ...) { // IEEE: %[[ALIGN:[0-9a-zA-Z_.]+]] = inttoptr i64 %[[V2]] to i8* // IEEE: %[[V3:[0-9a-zA-Z_.]+]] = bitcast i8* %[[ALIGN]] to fp128* // IEEE: %[[V4:[0-9a-zA-Z_.]+]] = load fp128, fp128* %[[V3]], align 16 -// IEEE: call void @foo_ld(fp128 noundef %[[V4]]) +// IEEE: call void @foo_ld(fp128 %[[V4]]) // IEEE: %[[AP2:[0-9a-zA-Z_.]+]] = bitcast i8** %[[AP]] to i8* // IEEE: call void @llvm.va_end(i8* %[[AP2]]) // IBM-LABEL: define{{.*}} void @long_double // IBM: %[[AP1:[0-9a-zA-Z_.]+]] = bitcast i8** %[[AP:[0-9a-zA-Z_.]+]] to i8* -// IBM: call void @llvm.va_start(i8* %[[AP1]]) +// IBM: call void @llvm.va_start(i8* %[[AP1]]) // IBM: %[[CUR:[0-9a-zA-Z_.]+]] = load i8*, i8** %[[AP]] // IBM: %[[V3:[0-9a-zA-Z_.]+]] = bitcast i8* %[[CUR]] to ppc_fp128* // IBM: %[[V4:[0-9a-zA-Z_.]+]] = load ppc_fp128, ppc_fp128* %[[V3]], align 8 -// IBM: call void @foo_ld(ppc_fp128 noundef %[[V4]]) +// IBM: call void @foo_ld(ppc_fp128 %[[V4]]) // IBM: %[[AP2:[0-9a-zA-Z_.]+]] = bitcast i8** %[[AP]] to i8* // IBM: call void @llvm.va_end(i8* %[[AP2]]) void long_double(int n, ...) { diff --git a/clang/test/CodeGen/pr25786.c b/clang/test/CodeGen/pr25786.c index e31c3b1f0db18697e302a9161bed45b826362747..7f5ad5e0ad5062e3e10771fae938e8351a1def2d 100644 --- a/clang/test/CodeGen/pr25786.c +++ b/clang/test/CodeGen/pr25786.c @@ -5,7 +5,7 @@ void (__attribute__((regparm(3), stdcall)) *pf) (); void (__attribute__((regparm(2), stdcall)) foo)(int a) { } // CHECK: @pf ={{.*}} global void (...)* null -// CHECK: define{{.*}} void @foo(i32 noundef %a) +// CHECK: define{{.*}} void @foo(i32 %a) // CHECK-OK: @pf ={{.*}} global void (...)* null -// CHECK-OK: define{{.*}} x86_stdcallcc void @foo(i32 inreg noundef %a) +// CHECK-OK: define{{.*}} x86_stdcallcc void @foo(i32 inreg %a) diff --git a/clang/test/CodeGen/pr5406.c b/clang/test/CodeGen/pr5406.c index 81f02e96c776e2bb19c5423e3f78ecab891ac541..69038ac07f5e26d31a2c84a4edfa54461b23a34f 100644 --- a/clang/test/CodeGen/pr5406.c +++ b/clang/test/CodeGen/pr5406.c @@ -6,7 +6,7 @@ typedef struct { char x[3]; } A0; void foo (int i, ...); -// CHECK: call void (i32, ...) @foo(i32 noundef 1, [1 x i32] {{.*}}) +// CHECK: call void (i32, ...) @foo(i32 1, [1 x i32] {{.*}}) int main (void) { A0 a3; diff --git a/clang/test/CodeGen/pr9614.c b/clang/test/CodeGen/pr9614.c index 8542debdccd718e38c0fb24f27608610a02780bc..c153283a837783957adc6f480bcdb4f9921ea8ad 100644 --- a/clang/test/CodeGen/pr9614.c +++ b/clang/test/CodeGen/pr9614.c @@ -32,7 +32,7 @@ void f(void) { // CHECK-LABEL: define{{.*}} void @f() // CHECK: call void @foo() -// CHECK: call i32 @abs(i32 noundef 0) +// CHECK: call i32 @abs(i32 0) // CHECK: call i8* @strrchr( // CHECK: call void @llvm.prefetch.p0i8( // CHECK: call i8* @memchr( @@ -40,6 +40,6 @@ void f(void) { // CHECK: declare void @foo() // CHECK: declare i32 @abs(i32 -// CHECK: declare i8* @strrchr(i8* noundef, i32 noundef) +// CHECK: declare i8* @strrchr(i8*, i32) // CHECK: declare i8* @memchr( // CHECK: declare void @llvm.prefetch.p0i8( diff --git a/clang/test/CodeGen/pragma-weak.c b/clang/test/CodeGen/pragma-weak.c index 8d69211adc96aa45a47d525b749d880cd036d38d..e903b2894910ec901109f0df2f86518e47ef9a78 100644 --- a/clang/test/CodeGen/pragma-weak.c +++ b/clang/test/CodeGen/pragma-weak.c @@ -140,7 +140,7 @@ __attribute((pure,noinline,const)) void __xxx(void) { } void SHA512Pad(void *context) {} #pragma weak SHA384Pad = SHA512Pad void PR10878() { SHA384Pad(0); } -// CHECK: call void @SHA384Pad(i8* noundef null) +// CHECK: call void @SHA384Pad(i8* null) // PR14046: Parse #pragma weak in function-local context diff --git a/clang/test/CodeGen/ps4-dllimport-dllexport.c b/clang/test/CodeGen/ps4-dllimport-dllexport.c index 2c3a0be998ba6a9fcafd67b6b3bfd93d428322d6..d2aa9f6facfcdfaad7fd600a5e68a2c5abf0753e 100644 --- a/clang/test/CodeGen/ps4-dllimport-dllexport.c +++ b/clang/test/CodeGen/ps4-dllimport-dllexport.c @@ -24,4 +24,4 @@ void call_imported_function() { // CHECK-DAG: @import_int = external dllimport // CHECK-DAG: @export_int ={{.*}} dllexport global i32 0 // CHECK-DAG: define{{.*}} dllexport void @export_implemented_function() -// CHECK-DAG: declare dllimport void @import_function(i32 noundef) +// CHECK-DAG: declare dllimport void @import_function(i32) diff --git a/clang/test/CodeGen/regcall.c b/clang/test/CodeGen/regcall.c index b920122a68e1154a91620592caca13f703145fe4..302b8456cd7558620b7dd323396c7ae150d31fa1 100644 --- a/clang/test/CodeGen/regcall.c +++ b/clang/test/CodeGen/regcall.c @@ -6,71 +6,71 @@ #include void __regcall v1(int a, int b) {} -// Win32: define dso_local x86_regcallcc void @__regcall3__v1(i32 inreg noundef %a, i32 inreg noundef %b) -// Win64: define dso_local x86_regcallcc void @__regcall3__v1(i32 noundef %a, i32 noundef %b) -// Lin32: define{{.*}} x86_regcallcc void @__regcall3__v1(i32 inreg noundef %a, i32 inreg noundef %b) -// Lin64: define{{.*}} x86_regcallcc void @__regcall3__v1(i32 noundef %a, i32 noundef %b) +// Win32: define dso_local x86_regcallcc void @__regcall3__v1(i32 inreg %a, i32 inreg %b) +// Win64: define dso_local x86_regcallcc void @__regcall3__v1(i32 %a, i32 %b) +// Lin32: define{{.*}} x86_regcallcc void @__regcall3__v1(i32 inreg %a, i32 inreg %b) +// Lin64: define{{.*}} x86_regcallcc void @__regcall3__v1(i32 %a, i32 %b) void __attribute__((regcall)) v1b(int a, int b) {} -// Win32: define dso_local x86_regcallcc void @__regcall3__v1b(i32 inreg noundef %a, i32 inreg noundef %b) -// Win64: define dso_local x86_regcallcc void @__regcall3__v1b(i32 noundef %a, i32 noundef %b) -// Lin32: define{{.*}} x86_regcallcc void @__regcall3__v1b(i32 inreg noundef %a, i32 inreg noundef %b) -// Lin64: define{{.*}} x86_regcallcc void @__regcall3__v1b(i32 noundef %a, i32 noundef %b) +// Win32: define dso_local x86_regcallcc void @__regcall3__v1b(i32 inreg %a, i32 inreg %b) +// Win64: define dso_local x86_regcallcc void @__regcall3__v1b(i32 %a, i32 %b) +// Lin32: define{{.*}} x86_regcallcc void @__regcall3__v1b(i32 inreg %a, i32 inreg %b) +// Lin64: define{{.*}} x86_regcallcc void @__regcall3__v1b(i32 %a, i32 %b) void __regcall v2(char a, char b) {} -// Win32: define dso_local x86_regcallcc void @__regcall3__v2(i8 inreg noundef signext %a, i8 inreg noundef signext %b) -// Win64: define dso_local x86_regcallcc void @__regcall3__v2(i8 noundef %a, i8 noundef %b) -// Lin32: define{{.*}} x86_regcallcc void @__regcall3__v2(i8 inreg noundef signext %a, i8 inreg noundef signext %b) -// Lin64: define{{.*}} x86_regcallcc void @__regcall3__v2(i8 noundef signext %a, i8 noundef signext %b) +// Win32: define dso_local x86_regcallcc void @__regcall3__v2(i8 inreg signext %a, i8 inreg signext %b) +// Win64: define dso_local x86_regcallcc void @__regcall3__v2(i8 %a, i8 %b) +// Lin32: define{{.*}} x86_regcallcc void @__regcall3__v2(i8 inreg signext %a, i8 inreg signext %b) +// Lin64: define{{.*}} x86_regcallcc void @__regcall3__v2(i8 signext %a, i8 signext %b) struct Small { int x; }; void __regcall v3(int a, struct Small b, int c) {} -// Win32: define dso_local x86_regcallcc void @__regcall3__v3(i32 inreg noundef %a, i32 %b.0, i32 inreg noundef %c) -// Win64: define dso_local x86_regcallcc void @__regcall3__v3(i32 noundef %a, i32 %b.coerce, i32 noundef %c) -// Lin32: define{{.*}} x86_regcallcc void @__regcall3__v3(i32 inreg noundef %a, i32 inreg %0, i32 %b.0, i32 inreg noundef %c) -// Lin64: define{{.*}} x86_regcallcc void @__regcall3__v3(i32 noundef %a, i32 %b.coerce, i32 noundef %c) +// Win32: define dso_local x86_regcallcc void @__regcall3__v3(i32 inreg %a, i32 %b.0, i32 inreg %c) +// Win64: define dso_local x86_regcallcc void @__regcall3__v3(i32 %a, i32 %b.coerce, i32 %c) +// Lin32: define{{.*}} x86_regcallcc void @__regcall3__v3(i32 inreg %a, i32 inreg %0, i32 %b.0, i32 inreg %c) +// Lin64: define{{.*}} x86_regcallcc void @__regcall3__v3(i32 %a, i32 %b.coerce, i32 %c) struct Large { int a[5]; }; void __regcall v4(int a, struct Large b, int c) {} -// Win32: define dso_local x86_regcallcc void @__regcall3__v4(i32 inreg noundef %a, %struct.Large* noundef byval(%struct.Large) align 4 %b, i32 inreg noundef %c) -// Win64: define dso_local x86_regcallcc void @__regcall3__v4(i32 noundef %a, %struct.Large* noundef %b, i32 noundef %c) -// Lin32: define{{.*}} x86_regcallcc void @__regcall3__v4(i32 inreg noundef %a, %struct.Large* noundef byval(%struct.Large) align 4 %b, i32 noundef %c) -// Lin64: define{{.*}} x86_regcallcc void @__regcall3__v4(i32 noundef %a, [5 x i32] %b.coerce, i32 noundef %c) +// Win32: define dso_local x86_regcallcc void @__regcall3__v4(i32 inreg %a, %struct.Large* byval(%struct.Large) align 4 %b, i32 inreg %c) +// Win64: define dso_local x86_regcallcc void @__regcall3__v4(i32 %a, %struct.Large* %b, i32 %c) +// Lin32: define{{.*}} x86_regcallcc void @__regcall3__v4(i32 inreg %a, %struct.Large* byval(%struct.Large) align 4 %b, i32 %c) +// Lin64: define{{.*}} x86_regcallcc void @__regcall3__v4(i32 %a, [5 x i32] %b.coerce, i32 %c) struct HFA2 { double x, y; }; struct HFA4 { double w, x, y, z; }; struct HFA5 { double v, w, x, y, z; }; void __regcall hfa1(int a, struct HFA4 b, int c) {} -// Win32: define dso_local x86_regcallcc void @__regcall3__hfa1(i32 inreg noundef %a, double %b.0, double %b.1, double %b.2, double %b.3, i32 inreg noundef %c) -// Win64: define dso_local x86_regcallcc void @__regcall3__hfa1(i32 noundef %a, double %b.0, double %b.1, double %b.2, double %b.3, i32 noundef %c) -// Lin32: define{{.*}} x86_regcallcc void @__regcall3__hfa1(i32 inreg noundef %a, double %b.0, double %b.1, double %b.2, double %b.3, i32 inreg noundef %c) -// Lin64: define{{.*}} x86_regcallcc void @__regcall3__hfa1(i32 noundef %a, double %b.coerce0, double %b.coerce1, double %b.coerce2, double %b.coerce3, i32 noundef %c) +// Win32: define dso_local x86_regcallcc void @__regcall3__hfa1(i32 inreg %a, double %b.0, double %b.1, double %b.2, double %b.3, i32 inreg %c) +// Win64: define dso_local x86_regcallcc void @__regcall3__hfa1(i32 %a, double %b.0, double %b.1, double %b.2, double %b.3, i32 %c) +// Lin32: define{{.*}} x86_regcallcc void @__regcall3__hfa1(i32 inreg %a, double %b.0, double %b.1, double %b.2, double %b.3, i32 inreg %c) +// Lin64: define{{.*}} x86_regcallcc void @__regcall3__hfa1(i32 %a, double %b.coerce0, double %b.coerce1, double %b.coerce2, double %b.coerce3, i32 %c) // HFAs that would require more than six total SSE registers are passed // indirectly. Additional vector arguments can consume the rest of the SSE // registers. void __regcall hfa2(struct HFA4 a, struct HFA4 b, double c) {} -// Win32: define dso_local x86_regcallcc void @__regcall3__hfa2(double %a.0, double %a.1, double %a.2, double %a.3, double %b.0, double %b.1, double %b.2, double %b.3, double* inreg noundef %0) -// Win64: define dso_local x86_regcallcc void @__regcall3__hfa2(double %a.0, double %a.1, double %a.2, double %a.3, double %b.0, double %b.1, double %b.2, double %b.3, double noundef %c) -// Lin32: define{{.*}} x86_regcallcc void @__regcall3__hfa2(double %a.0, double %a.1, double %a.2, double %a.3, double %b.0, double %b.1, double %b.2, double %b.3, double* inreg noundef %0) -// Lin64: define{{.*}} x86_regcallcc void @__regcall3__hfa2(double %a.coerce0, double %a.coerce1, double %a.coerce2, double %a.coerce3, double %b.coerce0, double %b.coerce1, double %b.coerce2, double %b.coerce3, double noundef %c) +// Win32: define dso_local x86_regcallcc void @__regcall3__hfa2(double %a.0, double %a.1, double %a.2, double %a.3, double %b.0, double %b.1, double %b.2, double %b.3, double* inreg %0) +// Win64: define dso_local x86_regcallcc void @__regcall3__hfa2(double %a.0, double %a.1, double %a.2, double %a.3, double %b.0, double %b.1, double %b.2, double %b.3, double %c) +// Lin32: define{{.*}} x86_regcallcc void @__regcall3__hfa2(double %a.0, double %a.1, double %a.2, double %a.3, double %b.0, double %b.1, double %b.2, double %b.3, double* inreg %0) +// Lin64: define{{.*}} x86_regcallcc void @__regcall3__hfa2(double %a.coerce0, double %a.coerce1, double %a.coerce2, double %a.coerce3, double %b.coerce0, double %b.coerce1, double %b.coerce2, double %b.coerce3, double %c) // Ensure that we pass builtin types directly while counting them against the // SSE register usage. void __regcall hfa3(double a, double b, double c, double d, double e, struct HFA2 f) {} -// Win32: define dso_local x86_regcallcc void @__regcall3__hfa3(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double %f.0, double %f.1) -// Win64: define dso_local x86_regcallcc void @__regcall3__hfa3(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double %f.0, double %f.1) -// Lin32: define{{.*}} x86_regcallcc void @__regcall3__hfa3(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double %f.0, double %f.1) -// Lin64: define{{.*}} x86_regcallcc void @__regcall3__hfa3(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double %f.coerce0, double %f.coerce1) +// Win32: define dso_local x86_regcallcc void @__regcall3__hfa3(double %a, double %b, double %c, double %d, double %e, double %f.0, double %f.1) +// Win64: define dso_local x86_regcallcc void @__regcall3__hfa3(double %a, double %b, double %c, double %d, double %e, double %f.0, double %f.1) +// Lin32: define{{.*}} x86_regcallcc void @__regcall3__hfa3(double %a, double %b, double %c, double %d, double %e, double %f.0, double %f.1) +// Lin64: define{{.*}} x86_regcallcc void @__regcall3__hfa3(double %a, double %b, double %c, double %d, double %e, double %f.coerce0, double %f.coerce1) -// Aggregates with more than four elements are not HFAs and are passed byval(%b.3, double noundef). +// Aggregates with more than four elements are not HFAs and are passed byval(%b.3, double). // Because they are not classified as homogeneous, they don't get special // handling to ensure alignment. void __regcall hfa4(struct HFA5 a) {} -// Win32: define dso_local x86_regcallcc void @__regcall3__hfa4(%struct.HFA5* noundef byval(%struct.HFA5) align 4 %0) -// Win64: define dso_local x86_regcallcc void @__regcall3__hfa4(%struct.HFA5* noundef %a) -// Lin32: define{{.*}} x86_regcallcc void @__regcall3__hfa4(%struct.HFA5* noundef byval(%struct.HFA5) align 4 %a) +// Win32: define dso_local x86_regcallcc void @__regcall3__hfa4(%struct.HFA5* byval(%struct.HFA5) align 4 %0) +// Win64: define dso_local x86_regcallcc void @__regcall3__hfa4(%struct.HFA5* %a) +// Lin32: define{{.*}} x86_regcallcc void @__regcall3__hfa4(%struct.HFA5* byval(%struct.HFA5) align 4 %a) // Lin64: define{{.*}} x86_regcallcc void @__regcall3__hfa4(double %a.coerce0, double %a.coerce1, double %a.coerce2, double %a.coerce3, double %a.coerce4) // Return HFAs of 4 or fewer elements in registers. @@ -86,22 +86,22 @@ struct HVA2 { v4f32 x, y; }; struct HVA4 { v4f32 w, x, y, z; }; void __regcall hva1(int a, struct HVA4 b, int c) {} -// Win32: define dso_local x86_regcallcc void @__regcall3__hva1(i32 inreg noundef %a, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, i32 inreg noundef %c) -// Win64: define dso_local x86_regcallcc void @__regcall3__hva1(i32 noundef %a, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, i32 noundef %c) -// Lin32: define{{.*}} x86_regcallcc void @__regcall3__hva1(i32 inreg noundef %a, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, i32 inreg noundef %c) -// Lin64: define{{.*}} x86_regcallcc void @__regcall3__hva1(i32 noundef %a, <4 x float> %b.coerce0, <4 x float> %b.coerce1, <4 x float> %b.coerce2, <4 x float> %b.coerce3, i32 noundef %c) +// Win32: define dso_local x86_regcallcc void @__regcall3__hva1(i32 inreg %a, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, i32 inreg %c) +// Win64: define dso_local x86_regcallcc void @__regcall3__hva1(i32 %a, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, i32 %c) +// Lin32: define{{.*}} x86_regcallcc void @__regcall3__hva1(i32 inreg %a, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, i32 inreg %c) +// Lin64: define{{.*}} x86_regcallcc void @__regcall3__hva1(i32 %a, <4 x float> %b.coerce0, <4 x float> %b.coerce1, <4 x float> %b.coerce2, <4 x float> %b.coerce3, i32 %c) void __regcall hva2(struct HVA4 a, struct HVA4 b, v4f32 c) {} -// Win32: define dso_local x86_regcallcc void @__regcall3__hva2(<4 x float> %a.0, <4 x float> %a.1, <4 x float> %a.2, <4 x float> %a.3, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, <4 x float>* inreg noundef %0) -// Win64: define dso_local x86_regcallcc void @__regcall3__hva2(<4 x float> %a.0, <4 x float> %a.1, <4 x float> %a.2, <4 x float> %a.3, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, <4 x float> noundef %c) -// Lin32: define{{.*}} x86_regcallcc void @__regcall3__hva2(<4 x float> %a.0, <4 x float> %a.1, <4 x float> %a.2, <4 x float> %a.3, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, <4 x float>* inreg noundef %0) -// Lin64: define{{.*}} x86_regcallcc void @__regcall3__hva2(<4 x float> %a.coerce0, <4 x float> %a.coerce1, <4 x float> %a.coerce2, <4 x float> %a.coerce3, <4 x float> %b.coerce0, <4 x float> %b.coerce1, <4 x float> %b.coerce2, <4 x float> %b.coerce3, <4 x float> noundef %c) +// Win32: define dso_local x86_regcallcc void @__regcall3__hva2(<4 x float> %a.0, <4 x float> %a.1, <4 x float> %a.2, <4 x float> %a.3, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, <4 x float>* inreg %0) +// Win64: define dso_local x86_regcallcc void @__regcall3__hva2(<4 x float> %a.0, <4 x float> %a.1, <4 x float> %a.2, <4 x float> %a.3, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, <4 x float> %c) +// Lin32: define{{.*}} x86_regcallcc void @__regcall3__hva2(<4 x float> %a.0, <4 x float> %a.1, <4 x float> %a.2, <4 x float> %a.3, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, <4 x float>* inreg %0) +// Lin64: define{{.*}} x86_regcallcc void @__regcall3__hva2(<4 x float> %a.coerce0, <4 x float> %a.coerce1, <4 x float> %a.coerce2, <4 x float> %a.coerce3, <4 x float> %b.coerce0, <4 x float> %b.coerce1, <4 x float> %b.coerce2, <4 x float> %b.coerce3, <4 x float> %c) void __regcall hva3(v4f32 a, v4f32 b, v4f32 c, v4f32 d, v4f32 e, struct HVA2 f) {} -// Win32: define dso_local x86_regcallcc void @__regcall3__hva3(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, <4 x float> noundef %d, <4 x float> noundef %e, <4 x float> %f.0, <4 x float> %f.1) -// Win64: define dso_local x86_regcallcc void @__regcall3__hva3(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, <4 x float> noundef %d, <4 x float> noundef %e, <4 x float> %f.0, <4 x float> %f.1) -// Lin32: define{{.*}} x86_regcallcc void @__regcall3__hva3(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, <4 x float> noundef %d, <4 x float> noundef %e, <4 x float> %f.0, <4 x float> %f.1) -// Lin64: define{{.*}} x86_regcallcc void @__regcall3__hva3(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, <4 x float> noundef %d, <4 x float> noundef %e, <4 x float> %f.coerce0, <4 x float> %f.coerce1) +// Win32: define dso_local x86_regcallcc void @__regcall3__hva3(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, <4 x float> %e, <4 x float> %f.0, <4 x float> %f.1) +// Win64: define dso_local x86_regcallcc void @__regcall3__hva3(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, <4 x float> %e, <4 x float> %f.0, <4 x float> %f.1) +// Lin32: define{{.*}} x86_regcallcc void @__regcall3__hva3(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, <4 x float> %e, <4 x float> %f.0, <4 x float> %f.1) +// Lin64: define{{.*}} x86_regcallcc void @__regcall3__hva3(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, <4 x float> %e, <4 x float> %f.coerce0, <4 x float> %f.coerce1) typedef float __attribute__((ext_vector_type(3))) v3f32; struct OddSizeHVA { v3f32 x, y; }; @@ -114,7 +114,7 @@ void __regcall odd_size_hva(struct OddSizeHVA a) {} struct HFA6 { __m128 f[4]; }; struct HFA6 __regcall ret_reg_reused(struct HFA6 a, struct HFA6 b, struct HFA6 c, struct HFA6 d){ struct HFA6 h; return h;} -// Win32: define dso_local x86_regcallcc %struct.HFA6 @__regcall3__ret_reg_reused(<4 x float> %a.0, <4 x float> %a.1, <4 x float> %a.2, <4 x float> %a.3, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, %struct.HFA6* inreg noundef %c, %struct.HFA6* inreg noundef %d) +// Win32: define dso_local x86_regcallcc %struct.HFA6 @__regcall3__ret_reg_reused(<4 x float> %a.0, <4 x float> %a.1, <4 x float> %a.2, <4 x float> %a.3, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, %struct.HFA6* inreg %c, %struct.HFA6* inreg %d) // Win64: define dso_local x86_regcallcc %struct.HFA6 @__regcall3__ret_reg_reused(<4 x float> %a.0, <4 x float> %a.1, <4 x float> %a.2, <4 x float> %a.3, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, <4 x float> %c.0, <4 x float> %c.1, <4 x float> %c.2, <4 x float> %c.3, <4 x float> %d.0, <4 x float> %d.1, <4 x float> %d.2, <4 x float> %d.3) -// Lin32: define{{.*}} x86_regcallcc %struct.HFA6 @__regcall3__ret_reg_reused(<4 x float> %a.0, <4 x float> %a.1, <4 x float> %a.2, <4 x float> %a.3, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, %struct.HFA6* inreg noundef %c, %struct.HFA6* inreg noundef %d) +// Lin32: define{{.*}} x86_regcallcc %struct.HFA6 @__regcall3__ret_reg_reused(<4 x float> %a.0, <4 x float> %a.1, <4 x float> %a.2, <4 x float> %a.3, <4 x float> %b.0, <4 x float> %b.1, <4 x float> %b.2, <4 x float> %b.3, %struct.HFA6* inreg %c, %struct.HFA6* inreg %d) // Lin64: define{{.*}} x86_regcallcc %struct.HFA6 @__regcall3__ret_reg_reused([4 x <4 x float>] %a.coerce, [4 x <4 x float>] %b.coerce, [4 x <4 x float>] %c.coerce, [4 x <4 x float>] %d.coerce) diff --git a/clang/test/CodeGen/regparm-flag.c b/clang/test/CodeGen/regparm-flag.c index 166864ee989e37188f2da52210a934526b978291..1330663e45289aa62d7e387910f4d302fe01653e 100644 --- a/clang/test/CodeGen/regparm-flag.c +++ b/clang/test/CodeGen/regparm-flag.c @@ -6,14 +6,14 @@ void f1(int a, int b, int c, int d, void f2(int a, int b) __attribute((regparm(0))); void f0() { -// CHECK: call void @f1(i32 inreg noundef 1, i32 inreg noundef 2, i32 inreg noundef 3, i32 inreg noundef 4, -// CHECK: i32 noundef 5, i32 noundef 6, i32 noundef 7, i32 noundef 8) +// CHECK: call void @f1(i32 inreg 1, i32 inreg 2, i32 inreg 3, i32 inreg 4, +// CHECK: i32 5, i32 6, i32 7, i32 8) f1(1, 2, 3, 4, 5, 6, 7, 8); -// CHECK: call void @f2(i32 noundef 1, i32 noundef 2) +// CHECK: call void @f2(i32 1, i32 2) f2(1, 2); } -// CHECK: declare void @f1(i32 inreg noundef, i32 inreg noundef, i32 inreg noundef, i32 inreg noundef, -// CHECK: i32 noundef, i32 noundef, i32 noundef, i32 noundef) -// CHECK: declare void @f2(i32 noundef, i32 noundef) +// CHECK: declare void @f1(i32 inreg, i32 inreg, i32 inreg, i32 inreg, +// CHECK: i32, i32, i32, i32) +// CHECK: declare void @f2(i32, i32) diff --git a/clang/test/CodeGen/regparm-struct.c b/clang/test/CodeGen/regparm-struct.c index b0cb036413525353834270fc8e584eadade055e4..f2aa4712d2bd4b4ba282c2c1c50eaf0eba0d0854 100644 --- a/clang/test/CodeGen/regparm-struct.c +++ b/clang/test/CodeGen/regparm-struct.c @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -triple i386-unknown-unknown %s -emit-llvm -o - | FileCheck %s __attribute__((regparm(3))) void f1(int a, int b, int c, int d); -// CHECK: declare void @f1(i32 inreg noundef, i32 inreg noundef, i32 inreg noundef, i32 noundef) +// CHECK: declare void @f1(i32 inreg, i32 inreg, i32 inreg, i32) void g1() { f1(41, 42, 43, 44); } @@ -10,7 +10,7 @@ struct s1 { int x1; }; __attribute__((regparm(3))) void f2(int a, int b, struct s1 c, int d); -// CHECK: declare void @f2(i32 inreg noundef, i32 inreg noundef, i32 inreg, i32 noundef) +// CHECK: declare void @f2(i32 inreg, i32 inreg, i32 inreg, i32) void g2() { struct s1 x = {43}; f2(41, 42, x, 44); @@ -21,13 +21,13 @@ struct s2 { int x2; }; __attribute__((regparm(3))) void f3(int a, int b, struct s2 c, int d); -// CHECK: declare void @f3(i32 inreg noundef, i32 inreg noundef, i32, i32, i32 noundef) +// CHECK: declare void @f3(i32 inreg, i32 inreg, i32, i32, i32) void g3() { struct s2 x = {43, 44}; f3(41, 42, x, 45); } __attribute__((regparm(3))) void f4(int a, struct s2 b, int c); -// CHECK: declare void @f4(i32 inreg noundef, i32 inreg, i32 inreg, i32 noundef) +// CHECK: declare void @f4(i32 inreg, i32 inreg, i32 inreg, i32) void g4() { struct s2 x = {42, 43}; f4(41, x, 44); @@ -39,13 +39,13 @@ struct s3 { int x3; }; __attribute__((regparm(3))) void f5(int a, struct s3 b, int c); -// CHECK: declare void @f5(i32 inreg noundef, i32, i32, i32, i32 noundef) +// CHECK: declare void @f5(i32 inreg, i32, i32, i32, i32) void g5() { struct s3 x = {42, 43, 44}; f5(41, x, 45); } __attribute__((regparm(3))) void f6(struct s3 a, int b); -// CHECK: declare void @f6(i32 inreg, i32 inreg, i32 inreg, i32 noundef) +// CHECK: declare void @f6(i32 inreg, i32 inreg, i32 inreg, i32) void g6() { struct s3 x = {41, 42, 43}; f6(x, 44); @@ -58,14 +58,14 @@ struct s4 { int x4; }; __attribute__((regparm(3))) void f7(struct s4 a, int b); -// CHECK: declare void @f7(i32, i32, i32, i32, i32 noundef) +// CHECK: declare void @f7(i32, i32, i32, i32, i32) void g7() { struct s4 x = {41, 42, 43, 44}; f7(x, 45); } __attribute__((regparm(3))) void f8(float a, int b); -// CHECK: declare void @f8(float noundef, i32 inreg noundef) +// CHECK: declare void @f8(float, i32 inreg) void g8(void) { f8(41, 42); } @@ -74,7 +74,7 @@ struct s5 { float x1; }; __attribute__((regparm(3))) void f9(struct s5 a, int b); -// CHECK: declare void @f9(float, i32 inreg noundef) +// CHECK: declare void @f9(float, i32 inreg) void g9(void) { struct s5 x = {41}; f9(x, 42); @@ -85,7 +85,7 @@ struct s6 { int x2; }; __attribute__((regparm(3))) void f10(struct s6 a, int b); -// CHECK: declare void @f10(i32 inreg, i32 inreg, i32 inreg noundef) +// CHECK: declare void @f10(i32 inreg, i32 inreg, i32 inreg) void g10(void) { struct s6 x = {41, 42}; f10(x, 43); @@ -97,7 +97,7 @@ struct s7 { float x3; }; __attribute__((regparm(3))) void f11(struct s7 a, int b); -// CHECK: declare void @f11(i32 inreg, i32 inreg, i32 inreg, i32 noundef) +// CHECK: declare void @f11(i32 inreg, i32 inreg, i32 inreg, i32) void g11(void) { struct s7 x = {41, 42, 43}; f11(x, 44); @@ -108,7 +108,7 @@ struct s8 { float x2; }; __attribute__((regparm(3))) void f12(struct s8 a, int b); -// CHECK: declare void @f12(i32 inreg, i32 inreg, i32 inreg noundef) +// CHECK: declare void @f12(i32 inreg, i32 inreg, i32 inreg) void g12(void) { struct s8 x = {41, 42}; f12(x, 43); @@ -120,7 +120,7 @@ struct s9 { float x3; }; __attribute__((regparm(3))) void f13(struct s9 a, int b); -// CHECK: declare void @f13(i32 inreg, i32 inreg, i32 inreg, i32 noundef) +// CHECK: declare void @f13(i32 inreg, i32 inreg, i32 inreg, i32) void g13(void) { struct s9 x = {41, 42, 43}; f13(x, 44); @@ -130,7 +130,7 @@ struct s10 { double x1; }; __attribute__((regparm(3))) void f14(struct s10 a, int b, int c); -// CHECK: declare void @f14(double, i32 inreg noundef, i32 inreg noundef) +// CHECK: declare void @f14(double, i32 inreg, i32 inreg) void g14(void) { struct s10 x = { 41 }; f14(x, 42, 43); @@ -141,7 +141,7 @@ struct s11 { double x2; }; __attribute__((regparm(3))) void f15(struct s11 a, int b); -// CHECK: declare void @f15(double, double, i32 noundef) +// CHECK: declare void @f15(double, double, i32) void g15(void) { struct s11 x = { 41, 42 }; f15(x, 43); @@ -152,14 +152,14 @@ struct s12 { float x2; }; __attribute__((regparm(3))) void f16(struct s12 a, int b); -// CHECK: declare void @f16(i32 inreg, i32 inreg, i32 inreg, i32 noundef) +// CHECK: declare void @f16(i32 inreg, i32 inreg, i32 inreg, i32) void g16(void) { struct s12 x = { 41, 42 }; f16(x, 43); } __attribute__((regparm(3))) struct s12 f17(int a, int b, int c); -// CHECK: declare void @f17(%struct.s12* inreg sret(%struct.s12) align 4, i32 inreg noundef, i32 inreg noundef, i32 noundef) +// CHECK: declare void @f17(%struct.s12* inreg sret(%struct.s12) align 4, i32 inreg, i32 inreg, i32) void g17(void) { f17(41, 42, 43); } @@ -170,7 +170,7 @@ struct s13 { } y; }; __attribute__((regparm(3))) void f18(struct s13 a, int b, int c, int d); -// CHECK: declare void @f18(%struct.s13* noundef byval(%struct.s13) align 4, i32 inreg noundef, i32 inreg noundef, i32 inreg noundef) +// CHECK: declare void @f18(%struct.s13* byval(%struct.s13) align 4, i32 inreg, i32 inreg, i32 inreg) void g18(void) { struct s13 x = {{41}}; f18(x, 42, 43, 44); diff --git a/clang/test/CodeGen/regparm.c b/clang/test/CodeGen/regparm.c index 4891b63991eb260b869343ed8ed82b1fad7e1532..b53182e888f87212638524a7f038331d1853048a 100644 --- a/clang/test/CodeGen/regparm.c +++ b/clang/test/CodeGen/regparm.c @@ -15,13 +15,13 @@ extern void FASTCALL reduced(char b, double c, foo* d, double e, int f); // PR7025 void FASTCALL f1(int i, int j, int k); -// CHECK-LABEL: define{{.*}} void @f1(i32 inreg noundef %i, i32 inreg noundef %j, i32 noundef %k) +// CHECK-LABEL: define{{.*}} void @f1(i32 inreg %i, i32 inreg %j, i32 %k) void f1(int i, int j, int k) { } int main(void) { - // CHECK: call void @reduced(i8 inreg noundef signext 0, {{.*}} %struct.foo* inreg noundef null + // CHECK: call void @reduced(i8 inreg signext 0, {{.*}} %struct.foo* inreg null reduced(0, 0.0, 0, 0.0, 0); - // CHECK: call x86_stdcallcc void {{.*}}(i32 inreg noundef 1, i32 inreg noundef 2) + // CHECK: call x86_stdcallcc void {{.*}}(i32 inreg 1, i32 inreg 2) bar(1,2); } diff --git a/clang/test/CodeGen/renderscript.c b/clang/test/CodeGen/renderscript.c index d735155394f8145e428d3389af9ea31c1dce941b..51829396fa7ca98ed0b6430100e089ea0167a6a2 100644 --- a/clang/test/CodeGen/renderscript.c +++ b/clang/test/CodeGen/renderscript.c @@ -17,9 +17,9 @@ _Static_assert(sizeof(long) == LONG_WIDTH_AND_ALIGN, "sizeof long is wrong"); _Static_assert(_Alignof(long) == LONG_WIDTH_AND_ALIGN, "sizeof long is wrong"); -// CHECK-RS32: i64 @test_long(i64 noundef %v) -// CHECK-RS64: i64 @test_long(i64 noundef %v) -// CHECK-ARM: i32 @test_long(i32 noundef %v) +// CHECK-RS32: i64 @test_long(i64 %v) +// CHECK-RS64: i64 @test_long(i64 %v) +// CHECK-ARM: i32 @test_long(i32 %v) long test_long(long v) { return v + 1; } @@ -104,11 +104,11 @@ typedef struct {int i1, i2, i3, i4, i5; } sInt5; typedef struct {long l1, l2; char c; } sLong2Char; // CHECK-RS32: void @argInt5([5 x i32] %s.coerce) -// CHECK-RS64: void @argInt5(%struct.sInt5* noundef %s) +// CHECK-RS64: void @argInt5(%struct.sInt5* %s) void argInt5(sInt5 s) {} // CHECK-RS32: void @argLong2Char([3 x i64] %s.coerce) -// CHECK-RS64: void @argLong2Char(%struct.sLong2Char* noundef %s) +// CHECK-RS64: void @argLong2Char(%struct.sLong2Char* %s) void argLong2Char(sLong2Char s) {} // ============================================================================= @@ -131,8 +131,8 @@ sLong2Char retLong2Char() { sLong2Char r; return r;} typedef struct {long l1, l2, l3, l4, l5, l6, l7, l8, l9; } sLong9; -// CHECK-RS32: void @argLong9(%struct.sLong9* noundef byval(%struct.sLong9) align 8 %s) -// CHECK-RS64: void @argLong9(%struct.sLong9* noundef %s) +// CHECK-RS32: void @argLong9(%struct.sLong9* byval(%struct.sLong9) align 8 %s) +// CHECK-RS64: void @argLong9(%struct.sLong9* %s) void argLong9(sLong9 s) {} // CHECK-RS32: void @retLong9(%struct.sLong9* noalias sret(%struct.sLong9) align 8 %agg.result) diff --git a/clang/test/CodeGen/restrict.c b/clang/test/CodeGen/restrict.c index 7cd4b36dc10c2e9fb929b971b3c6841d8b5c9d80..639a7a8155b1336ae1c310c61cfdfbf7423ded37 100644 --- a/clang/test/CodeGen/restrict.c +++ b/clang/test/CodeGen/restrict.c @@ -2,25 +2,25 @@ // PR6695 -// CHECK: define{{.*}} void @test0(i32* noundef %{{.*}}, i32 noundef %{{.*}}) +// CHECK: define{{.*}} void @test0(i32* %{{.*}}, i32 %{{.*}}) void test0(int *x, int y) { } -// CHECK: define{{.*}} void @test1(i32* noalias noundef %{{.*}}, i32 noundef %{{.*}}) +// CHECK: define{{.*}} void @test1(i32* noalias %{{.*}}, i32 %{{.*}}) void test1(int * restrict x, int y) { } -// CHECK: define{{.*}} void @test2(i32* noundef %{{.*}}, i32* noalias noundef %{{.*}}) +// CHECK: define{{.*}} void @test2(i32* %{{.*}}, i32* noalias %{{.*}}) void test2(int *x, int * restrict y) { } typedef int * restrict rp; -// CHECK: define{{.*}} void @test3(i32* noalias noundef %{{.*}}, i32 noundef %{{.*}}) +// CHECK: define{{.*}} void @test3(i32* noalias %{{.*}}, i32 %{{.*}}) void test3(rp x, int y) { } -// CHECK: define{{.*}} void @test4(i32* noundef %{{.*}}, i32* noalias noundef %{{.*}}) +// CHECK: define{{.*}} void @test4(i32* %{{.*}}, i32* noalias %{{.*}}) void test4(int *x, rp y) { } diff --git a/clang/test/CodeGen/sanitize-thread-no-checking-at-run-time.m b/clang/test/CodeGen/sanitize-thread-no-checking-at-run-time.m index c2643c93ebf05d17d87239e63fb57620c6993816..e0d7eb52a4445fd86fec60406ccdbf871166a15e 100644 --- a/clang/test/CodeGen/sanitize-thread-no-checking-at-run-time.m +++ b/clang/test/CodeGen/sanitize-thread-no-checking-at-run-time.m @@ -35,7 +35,7 @@ public: void test2(id x) { extern void test2_helper(id (^)(void)); test2_helper(^{ return x; }); -// TSAN: define linkonce_odr hidden void @__destroy_helper_block_8_32o(i8* noundef %0) unnamed_addr [[ATTR:#[0-9]+]] +// TSAN: define linkonce_odr hidden void @__destroy_helper_block_8_32o(i8* %0) unnamed_addr [[ATTR:#[0-9]+]] } // TSAN: attributes [[ATTR]] = { noinline nounwind {{.*}} "sanitize_thread_no_checking_at_run_time" {{.*}} } diff --git a/clang/test/CodeGen/sparc-arguments.c b/clang/test/CodeGen/sparc-arguments.c index 319da92e8414a5dfb37be8a2706d09d028347032..7fba043bb0be6d0e95ab7ebbec0cca07ba755d0e 100644 --- a/clang/test/CodeGen/sparc-arguments.c +++ b/clang/test/CodeGen/sparc-arguments.c @@ -17,9 +17,9 @@ struct s1 x1; // Ensure the align 8 is passed through: // CHECK-LABEL: define{{.*}} void @f1() -// CHECK: call void @f1_helper(%struct.s1* noundef byval(%struct.s1) align 8 @x1) +// CHECK: call void @f1_helper(%struct.s1* byval(%struct.s1) align 8 @x1) // Also ensure the declaration of f1_helper includes it -// CHECK: declare void @f1_helper(%struct.s1* noundef byval(%struct.s1) align 8) +// CHECK: declare void @f1_helper(%struct.s1* byval(%struct.s1) align 8) void f1_helper(struct s1); void f1() { diff --git a/clang/test/CodeGen/sparcv8-abi.c b/clang/test/CodeGen/sparcv8-abi.c index bde11ac8499c98e40850eda80eb69d2d357ce2dc..dca49aa7fb1a1308f58bc40fd297985be258a61a 100644 --- a/clang/test/CodeGen/sparcv8-abi.c +++ b/clang/test/CodeGen/sparcv8-abi.c @@ -1,18 +1,18 @@ // RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - | FileCheck %s -// CHECK-LABEL: define{{.*}} { float, float } @p({ float, float }* noundef byval({ float, float }) align 4 %a, { float, float }* noundef byval({ float, float }) align 4 %b) #0 { +// CHECK-LABEL: define{{.*}} { float, float } @p({ float, float }* byval({ float, float }) align 4 %a, { float, float }* byval({ float, float }) align 4 %b) #0 { float __complex__ p (float __complex__ a, float __complex__ b) { } -// CHECK-LABEL: define{{.*}} { double, double } @q({ double, double }* noundef byval({ double, double }) align 8 %a, { double, double }* noundef byval({ double, double }) align 8 %b) #0 { +// CHECK-LABEL: define{{.*}} { double, double } @q({ double, double }* byval({ double, double }) align 8 %a, { double, double }* byval({ double, double }) align 8 %b) #0 { double __complex__ q (double __complex__ a, double __complex__ b) { } -// CHECK-LABEL: define{{.*}} { i64, i64 } @r({ i64, i64 }* noundef byval({ i64, i64 }) align 8 %a, { i64, i64 }* noundef byval({ i64, i64 }) align 8 %b) #0 { +// CHECK-LABEL: define{{.*}} { i64, i64 } @r({ i64, i64 }* byval({ i64, i64 }) align 8 %a, { i64, i64 }* byval({ i64, i64 }) align 8 %b) #0 { long long __complex__ r (long long __complex__ a, long long __complex__ b) { diff --git a/clang/test/CodeGen/sparcv8-inline-asm.c b/clang/test/CodeGen/sparcv8-inline-asm.c index f690c9e432397c203ff4620f528a31afb3dd7966..f8201e7540c96a686d5957318b98ca84bb9d7d11 100644 --- a/clang/test/CodeGen/sparcv8-inline-asm.c +++ b/clang/test/CodeGen/sparcv8-inline-asm.c @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - | FileCheck %s -// CHECK: define{{.*}} float @fabsf(float noundef %a) +// CHECK: define{{.*}} float @fabsf(float %a) // CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float %{{.*}}) float fabsf(float a) { float res; diff --git a/clang/test/CodeGen/sparcv9-abi.c b/clang/test/CodeGen/sparcv9-abi.c index bc62ad1c2937ca36ecc0c84767b75dbb6b44c539..8156dabe4c02acbb866f87513054f1df808dbb44 100644 --- a/clang/test/CodeGen/sparcv9-abi.c +++ b/clang/test/CodeGen/sparcv9-abi.c @@ -6,19 +6,19 @@ void f_void(void) {} // Arguments and return values smaller than the word size are extended. -// CHECK-LABEL: define{{.*}} signext i32 @f_int_1(i32 noundef signext %x) +// CHECK-LABEL: define{{.*}} signext i32 @f_int_1(i32 signext %x) int f_int_1(int x) { return x; } -// CHECK-LABEL: define{{.*}} zeroext i32 @f_int_2(i32 noundef zeroext %x) +// CHECK-LABEL: define{{.*}} zeroext i32 @f_int_2(i32 zeroext %x) unsigned f_int_2(unsigned x) { return x; } -// CHECK-LABEL: define{{.*}} i64 @f_int_3(i64 noundef %x) +// CHECK-LABEL: define{{.*}} i64 @f_int_3(i64 %x) long long f_int_3(long long x) { return x; } -// CHECK-LABEL: define{{.*}} signext i8 @f_int_4(i8 noundef signext %x) +// CHECK-LABEL: define{{.*}} signext i8 @f_int_4(i8 signext %x) char f_int_4(char x) { return x; } -// CHECK-LABEL: define{{.*}} fp128 @f_ld(fp128 noundef %x) +// CHECK-LABEL: define{{.*}} fp128 @f_ld(fp128 %x) long double f_ld(long double x) { return x; } // Small structs are passed in registers. @@ -39,7 +39,7 @@ struct medium { int *c, *d; }; -// CHECK-LABEL: define{{.*}} %struct.medium @f_medium(%struct.medium* noundef %x) +// CHECK-LABEL: define{{.*}} %struct.medium @f_medium(%struct.medium* %x) struct medium f_medium(struct medium x) { x.a += *x.b; x.b = 0; @@ -53,7 +53,7 @@ struct large { int x; }; -// CHECK-LABEL: define{{.*}} void @f_large(%struct.large* noalias sret(%struct.large) align 8 %agg.result, %struct.large* noundef %x) +// CHECK-LABEL: define{{.*}} void @f_large(%struct.large* noalias sret(%struct.large) align 8 %agg.result, %struct.large* %x) struct large f_large(struct large x) { x.a += *x.b; x.b = 0; @@ -120,7 +120,7 @@ void call_tiny() { f_tiny(x); } -// CHECK-LABEL: define{{.*}} signext i32 @f_variable(i8* noundef %f, ...) +// CHECK-LABEL: define{{.*}} signext i32 @f_variable(i8* %f, ...) // CHECK: %ap = alloca i8* // CHECK: call void @llvm.va_start // diff --git a/clang/test/CodeGen/spir-half-type.cpp b/clang/test/CodeGen/spir-half-type.cpp index 7a6631890c226d8cc085ac99820ad9292d63a802..4b56465e8f420b799e3f6bd500d4c3ee92a2550c 100644 --- a/clang/test/CodeGen/spir-half-type.cpp +++ b/clang/test/CodeGen/spir-half-type.cpp @@ -116,7 +116,7 @@ _Float16 fsub() { return a - b - 3.0f16; } -// CHECK: define{{.*}} spir_func noundef half @_Z4fmulDF16_(half noundef %arg) +// CHECK: define{{.*}} spir_func half @_Z4fmulDF16_(half %arg) _Float16 fmul(_Float16 arg) { _Float16 a = 1.0f16; const _Float16 b = 2.0f16; diff --git a/clang/test/CodeGen/split-debug-single-file.c b/clang/test/CodeGen/split-debug-single-file.c index 384e62cb50a598ba80ebd50dc2cd122982c9bf5a..0c38d0f927a14d0ab0590f581329ad40445d5833 100644 --- a/clang/test/CodeGen/split-debug-single-file.c +++ b/clang/test/CodeGen/split-debug-single-file.c @@ -2,20 +2,14 @@ // Testing to ensure that setting only -split-dwarf-file allows to place .dwo sections into regular output object. // RUN: %clang_cc1 -debug-info-kind=limited -triple x86_64-unknown-linux \ -// RUN: -split-dwarf-file %t.o -emit-obj -o %t.o %s -fno-experimental-new-pass-manager -// RUN: llvm-readobj -S %t.o | FileCheck --check-prefix=MODE-SINGLE %s -// RUN: %clang_cc1 -debug-info-kind=limited -triple x86_64-unknown-linux \ -// RUN: -split-dwarf-file %t.o -emit-obj -o %t.o %s -fexperimental-new-pass-manager +// RUN: -split-dwarf-file %t.o -emit-obj -o %t.o %s // RUN: llvm-readobj -S %t.o | FileCheck --check-prefix=MODE-SINGLE %s // MODE-SINGLE: .dwo // Testing to ensure that setting both -split-dwarf-file and -split-dwarf-output // does not place .dwo sections into regular output object. // RUN: %clang_cc1 -debug-info-kind=limited -triple x86_64-unknown-linux \ -// RUN: -split-dwarf-file %t.dwo -split-dwarf-output %t.dwo -emit-obj -o %t.o %s -fno-experimental-new-pass-manager -// RUN: llvm-readobj -S %t.o | FileCheck --check-prefix=MODE-SPLIT %s -// RUN: %clang_cc1 -debug-info-kind=limited -triple x86_64-unknown-linux \ -// RUN: -split-dwarf-file %t.dwo -split-dwarf-output %t.dwo -emit-obj -o %t.o %s -fexperimental-new-pass-manager +// RUN: -split-dwarf-file %t.dwo -split-dwarf-output %t.dwo -emit-obj -o %t.o %s // RUN: llvm-readobj -S %t.o | FileCheck --check-prefix=MODE-SPLIT %s // MODE-SPLIT-NOT: .dwo diff --git a/clang/test/CodeGen/split-lto-unit.c b/clang/test/CodeGen/split-lto-unit.c index bd15765643388c4dfb8918e49daa98ba96b27c2f..8e83ebaa6fb82ac5ab65d5c4e2a999f7e6f9324f 100644 --- a/clang/test/CodeGen/split-lto-unit.c +++ b/clang/test/CodeGen/split-lto-unit.c @@ -7,7 +7,6 @@ // SPLIT: !{i32 1, !"EnableSplitLTOUnit", i32 1} // // ; Check that regular LTO has EnableSplitLTOUnit = 1 -// RUN: %clang_cc1 -fno-experimental-new-pass-manager -flto -triple x86_64-pc-linux-gnu -emit-llvm-bc < %s | llvm-dis -o - | FileCheck %s --implicit-check-not="EnableSplitLTOUnit" --check-prefix=SPLIT -// RUN: %clang_cc1 -fexperimental-new-pass-manager -flto -triple x86_64-pc-linux-gnu -emit-llvm-bc < %s | llvm-dis -o - | FileCheck %s --implicit-check-not="EnableSplitLTOUnit" --check-prefix=SPLIT +// RUN: %clang_cc1 -flto -triple x86_64-pc-linux-gnu -emit-llvm-bc < %s | llvm-dis -o - | FileCheck %s --implicit-check-not="EnableSplitLTOUnit" --check-prefix=SPLIT int main() {} diff --git a/clang/test/CodeGen/stack-protector.c b/clang/test/CodeGen/stack-protector.c index 6feda0f8153d6ca57e75c0a921dbc2d076748061..5037a3e0d6fe16d5895ea4f246e8a6de65775af0 100644 --- a/clang/test/CodeGen/stack-protector.c +++ b/clang/test/CodeGen/stack-protector.c @@ -15,14 +15,14 @@ int printf(const char * _Format, ...); size_t strlen(const char *s); char *strcpy(char *s1, const char *s2); -// DEF: define {{.*}}void @test1(i8* noundef %msg) #[[A:.*]] { +// DEF: define {{.*}}void @test1(i8* %msg) #[[A:.*]] { void test1(const char *msg) { char a[strlen(msg) + 1]; strcpy(a, msg); printf("%s\n", a); } -// DEF: define {{.*}}void @test2(i8* noundef %msg) #[[B:.*]] { +// DEF: define {{.*}}void @test2(i8* %msg) #[[B:.*]] { __attribute__((no_stack_protector)) void test2(const char *msg) { char a[strlen(msg) + 1]; diff --git a/clang/test/CodeGen/stdcall-fastcall.c b/clang/test/CodeGen/stdcall-fastcall.c index dba1c185b8f0577bb89020dc4a10ad724895d70e..93f6167f7431acb2625fd1ef3a9c149bdd3a9e8c 100644 --- a/clang/test/CodeGen/stdcall-fastcall.c +++ b/clang/test/CodeGen/stdcall-fastcall.c @@ -46,13 +46,13 @@ int main(void) { void __attribute((stdcall)) f7(foo) int foo; {} void f8(void) { f7(0); - // CHECK: call x86_stdcallcc void @f7(i32 noundef 0) + // CHECK: call x86_stdcallcc void @f7(i32 0) } void __attribute__((fastcall)) foo1(int y); void bar1(int y) { // CHECK-LABEL: define{{.*}} void @bar1 - // CHECK: call x86_fastcallcc void @foo1(i32 inreg noundef % + // CHECK: call x86_fastcallcc void @foo1(i32 inreg % foo1(y); } @@ -69,7 +69,7 @@ void bar2(struct S1 y) { void __attribute__((fastcall)) foo3(int *y); void bar3(int *y) { // CHECK-LABEL: define{{.*}} void @bar3 - // CHECK: call x86_fastcallcc void @foo3(i32* inreg noundef % + // CHECK: call x86_fastcallcc void @foo3(i32* inreg % foo3(y); } @@ -77,7 +77,7 @@ enum Enum {Eval}; void __attribute__((fastcall)) foo4(enum Enum y); void bar4(enum Enum y) { // CHECK-LABEL: define{{.*}} void @bar4 - // CHECK: call x86_fastcallcc void @foo4(i32 inreg noundef % + // CHECK: call x86_fastcallcc void @foo4(i32 inreg % foo4(y); } @@ -89,49 +89,49 @@ struct S2 { void __attribute__((fastcall)) foo5(struct S2 y); void bar5(struct S2 y) { // CHECK-LABEL: define{{.*}} void @bar5 - // CHECK: call x86_fastcallcc void @foo5(%struct.S2* noundef byval(%struct.S2) align 4 % + // CHECK: call x86_fastcallcc void @foo5(%struct.S2* byval(%struct.S2) align 4 % foo5(y); } void __attribute__((fastcall)) foo6(long long y); void bar6(long long y) { // CHECK-LABEL: define{{.*}} void @bar6 - // CHECK: call x86_fastcallcc void @foo6(i64 noundef % + // CHECK: call x86_fastcallcc void @foo6(i64 % foo6(y); } void __attribute__((fastcall)) foo7(int a, struct S1 b, int c); void bar7(int a, struct S1 b, int c) { // CHECK-LABEL: define{{.*}} void @bar7 - // CHECK: call x86_fastcallcc void @foo7(i32 inreg noundef %{{.*}}, i32 %{{.*}}, i32 noundef %{{.*}} + // CHECK: call x86_fastcallcc void @foo7(i32 inreg %{{.*}}, i32 %{{.*}}, i32 %{{.*}} foo7(a, b, c); } void __attribute__((fastcall)) foo8(struct S1 a, int b); void bar8(struct S1 a, int b) { // CHECK-LABEL: define{{.*}} void @bar8 - // CHECK: call x86_fastcallcc void @foo8(i32 inreg undef, i32 %{{.*}}, i32 inreg noundef % + // CHECK: call x86_fastcallcc void @foo8(i32 inreg undef, i32 %{{.*}}, i32 inreg % foo8(a, b); } void __attribute__((fastcall)) foo9(struct S2 a, int b); void bar9(struct S2 a, int b) { // CHECK-LABEL: define{{.*}} void @bar9 - // CHECK: call x86_fastcallcc void @foo9(%struct.S2* noundef byval(%struct.S2) align 4 %{{.*}}, i32 noundef % + // CHECK: call x86_fastcallcc void @foo9(%struct.S2* byval(%struct.S2) align 4 %{{.*}}, i32 % foo9(a, b); } void __attribute__((fastcall)) foo10(float y, int x); void bar10(float y, int x) { // CHECK-LABEL: define{{.*}} void @bar10 - // CHECK: call x86_fastcallcc void @foo10(float noundef %{{.*}}, i32 inreg noundef % + // CHECK: call x86_fastcallcc void @foo10(float %{{.*}}, i32 inreg % foo10(y, x); } void __attribute__((fastcall)) foo11(double y, int x); void bar11(double y, int x) { // CHECK-LABEL: define{{.*}} void @bar11 - // CHECK: call x86_fastcallcc void @foo11(double noundef %{{.*}}, i32 inreg noundef % + // CHECK: call x86_fastcallcc void @foo11(double %{{.*}}, i32 inreg % foo11(y, x); } @@ -141,6 +141,6 @@ struct S3 { void __attribute__((fastcall)) foo12(struct S3 y, int x); void bar12(struct S3 y, int x) { // CHECK-LABEL: define{{.*}} void @bar12 - // CHECK: call x86_fastcallcc void @foo12(float %{{.*}}, i32 inreg noundef % + // CHECK: call x86_fastcallcc void @foo12(float %{{.*}}, i32 inreg % foo12(y, x); } diff --git a/clang/test/CodeGen/strictfp_builtins.c b/clang/test/CodeGen/strictfp_builtins.c index e74b879ea1e08279f772770c4cff502e725a38b3..fbf3c274bd6d8ecf1ab6a35d5bebeb5d9ce437bd 100644 --- a/clang/test/CodeGen/strictfp_builtins.c +++ b/clang/test/CodeGen/strictfp_builtins.c @@ -17,7 +17,7 @@ int printf(const char *, ...); // CHECK-NEXT: store i32 [[X:%.*]], i32* [[X_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[STR_ADDR]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[X_ADDR]], align 4 -// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8*, ...) @printf(i8* noundef getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i8* noundef [[TMP0]], i32 noundef [[TMP1]]) [[ATTR4:#.*]] +// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i8* [[TMP0]], i32 [[TMP1]]) [[ATTR4:#.*]] // CHECK-NEXT: ret void // void p(char *str, int x) { @@ -35,7 +35,7 @@ void p(char *str, int x) { // CHECK-NEXT: br i1 [[ISZERO]], label [[FPCLASSIFY_END:%.*]], label [[FPCLASSIFY_NOT_ZERO:%.*]] // CHECK: fpclassify_end: // CHECK-NEXT: [[FPCLASSIFY_RESULT:%.*]] = phi i32 [ 4, [[ENTRY:%.*]] ], [ 0, [[FPCLASSIFY_NOT_ZERO]] ], [ 1, [[FPCLASSIFY_NOT_NAN:%.*]] ], [ [[TMP2:%.*]], [[FPCLASSIFY_NOT_INF:%.*]] ] -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([29 x i8], [29 x i8]* @.str.1, i64 0, i64 0), i32 noundef [[FPCLASSIFY_RESULT]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([29 x i8], [29 x i8]* @.str.1, i64 0, i64 0), i32 [[FPCLASSIFY_RESULT]]) [[ATTR4]] // CHECK-NEXT: ret void // CHECK: fpclassify_not_zero: // CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double [[TMP0]], double [[TMP0]], metadata !"uno", metadata !"fpexcept.strict") [[ATTR4]] @@ -64,7 +64,7 @@ void test_fpclassify(double d) { // CHECK-NEXT: [[SHL1:%.*]] = shl i16 [[BITCAST]], 1 // CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[SHL1]], -2048 // CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:2]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:2]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_fp16_isinf(__fp16 h) { @@ -82,7 +82,7 @@ void test_fp16_isinf(__fp16 h) { // CHECK-NEXT: [[SHL1:%.*]] = shl i32 [[BITCAST]], 1 // CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[SHL1]], -16777216 // CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_float_isinf(float f) { @@ -100,7 +100,7 @@ void test_float_isinf(float f) { // CHECK-NEXT: [[SHL1:%.*]] = shl i64 [[BITCAST]], 1 // CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[SHL1]], -9007199254740992 // CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_double_isinf(double d) { @@ -118,7 +118,7 @@ void test_double_isinf(double d) { // CHECK-NEXT: [[SHL1:%.*]] = shl i16 [[BITCAST]], 1 // CHECK-NEXT: [[CMP:%.*]] = icmp ult i16 [[SHL1]], -2048 // CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([12 x i8], [12 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_fp16_isfinite(__fp16 h) { @@ -136,7 +136,7 @@ void test_fp16_isfinite(__fp16 h) { // CHECK-NEXT: [[SHL1:%.*]] = shl i32 [[BITCAST]], 1 // CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[SHL1]], -16777216 // CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([12 x i8], [12 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_float_isfinite(float f) { @@ -154,7 +154,7 @@ void test_float_isfinite(float f) { // CHECK-NEXT: [[SHL1:%.*]] = shl i64 [[BITCAST]], 1 // CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[SHL1]], -9007199254740992 // CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([12 x i8], [12 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_double_isfinite(double d) { @@ -174,7 +174,7 @@ void test_double_isfinite(double d) { // CHECK-NEXT: [[TMP3:%.*]] = icmp slt i64 [[TMP2]], 0 // CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 -1, i32 1 // CHECK-NEXT: [[TMP5:%.*]] = select i1 [[ISINF]], i32 [[TMP4]], i32 0 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([14 x i8], [14 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[TMP5]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[TMP5]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_isinf_sign(double d) { @@ -193,7 +193,7 @@ void test_isinf_sign(double d) { // CHECK-NEXT: [[TMP1:%.*]] = sub i16 [[#%u,0x7C00]], [[ABS]] // CHECK-NEXT: [[ISNAN:%.*]] = lshr i16 [[TMP1]], 15 // CHECK-NEXT: [[RES:%.*]] = zext i16 [[ISNAN]] to i32 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_fp16_isnan(__fp16 h) { @@ -211,7 +211,7 @@ void test_fp16_isnan(__fp16 h) { // CHECK-NEXT: [[ABS:%.*]] = and i32 [[BITCAST]], [[#%u,0x7FFFFFFF]] // CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[#%u,0x7F800000]], [[ABS]] // CHECK-NEXT: [[ISNAN:%.*]] = lshr i32 [[TMP1]], 31 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[ISNAN]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[ISNAN]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_float_isnan(float f) { @@ -230,7 +230,7 @@ void test_float_isnan(float f) { // CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[#%u,0x7FF0000000000000]], [[ABS]] // CHECK-NEXT: [[ISNAN:%.*]] = lshr i64 [[TMP1]], 63 // CHECK-NEXT: [[RES:%.*]] = trunc i64 [[ISNAN]] to i32 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_double_isnan(double d) { @@ -251,7 +251,7 @@ void test_double_isnan(double d) { // CHECK-NEXT: [[AND:%.*]] = and i1 [[ISEQ]], [[ISINF]] // CHECK-NEXT: [[AND1:%.*]] = and i1 [[AND]], [[ISNORMAL]] // CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[AND1]] to i32 -// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([12 x i8], [12 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[TMP2]]) [[ATTR4]] +// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[TMP2]]) [[ATTR4]] // CHECK-NEXT: ret void // void test_isnormal(double d) { diff --git a/clang/test/CodeGen/swift-async-call-conv.c b/clang/test/CodeGen/swift-async-call-conv.c index 0ab9b33dd3fb2ad77524e64d491fbe39989b2a44..2e261f14183e3e24c47de9ef0800273850c256f2 100644 --- a/clang/test/CodeGen/swift-async-call-conv.c +++ b/clang/test/CodeGen/swift-async-call-conv.c @@ -1,14 +1,14 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple armv7-apple-darwin9 -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple armv7s-apple-ios9 -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple armv7k-apple-ios9 -emit-llvm -o - %s | FileCheck %s - -// RUN: %clang_cc1 -disable-noundef-analysis -x c++ -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CPPONLY -// RUN: %clang_cc1 -disable-noundef-analysis -x c++ -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CPPONLY -// RUN: %clang_cc1 -disable-noundef-analysis -x c++ -triple armv7-apple-darwin9 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CPPONLY -// RUN: %clang_cc1 -disable-noundef-analysis -x c++ -triple armv7s-apple-ios9 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CPPONLY -// RUN: %clang_cc1 -disable-noundef-analysis -x c++ -triple armv7k-apple-ios9 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CPPONLY +// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple armv7-apple-darwin9 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple armv7s-apple-ios9 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple armv7k-apple-ios9 -emit-llvm -o - %s | FileCheck %s + +// RUN: %clang_cc1 -x c++ -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CPPONLY +// RUN: %clang_cc1 -x c++ -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CPPONLY +// RUN: %clang_cc1 -x c++ -triple armv7-apple-darwin9 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CPPONLY +// RUN: %clang_cc1 -x c++ -triple armv7s-apple-ios9 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CPPONLY +// RUN: %clang_cc1 -x c++ -triple armv7k-apple-ios9 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CPPONLY // Test tail call behavior when a swiftasynccall function is called // from another swiftasynccall function. diff --git a/clang/test/CodeGen/switch-dce.c b/clang/test/CodeGen/switch-dce.c index 044851922970c1ca222d12d9c4aced9070cf4774..5a68ff26c6f531cc1e63d9d29d48a0e2ad07a675 100644 --- a/clang/test/CodeGen/switch-dce.c +++ b/clang/test/CodeGen/switch-dce.c @@ -218,11 +218,11 @@ void test12() { // Verify that case 42 only calls test14 once. // CHECK: @test13 -// CHECK: call void @test13(i32 noundef 97) +// CHECK: call void @test13(i32 97) // CHECK-NEXT: br label %[[EPILOG2:[0-9.a-z]+]] // CHECK: [[EPILOG2]] // CHECK-NEXT: br label [[EPILOG:%[0-9.a-z]+]] -// CHECK: call void @test13(i32 noundef 42) +// CHECK: call void @test13(i32 42) // CHECK-NEXT: br label [[EPILOG]] void test13(int x) { switch (x) { diff --git a/clang/test/CodeGen/sysv_abi.c b/clang/test/CodeGen/sysv_abi.c index eeb9ac01fa748642d4bc2d233267264da27cf5cb..62b0062579c33c4896e081c8eed582424e7bf9e7 100644 --- a/clang/test/CodeGen/sysv_abi.c +++ b/clang/test/CodeGen/sysv_abi.c @@ -40,10 +40,10 @@ void use_vectors() { // CHECK: define {{(dso_local )?}}void @use_vectors() // AVX: call {{(x86_64_sysvcc )?}}<8 x float> @get_m256() -// AVX: call {{(x86_64_sysvcc )?}}void @take_m256(<8 x float> noundef %{{.*}}) +// AVX: call {{(x86_64_sysvcc )?}}void @take_m256(<8 x float> %{{.*}}) // AVX: call {{(x86_64_sysvcc )?}}<16 x float> @get_m512() -// AVX: call {{(x86_64_sysvcc )?}}void @take_m512(<16 x float> noundef %{{.*}}) +// AVX: call {{(x86_64_sysvcc )?}}void @take_m512(<16 x float> %{{.*}}) // NOAVX: call {{(x86_64_sysvcc )?}}<8 x float> @get_m256() -// NOAVX: call {{(x86_64_sysvcc )?}}void @take_m256(<8 x float>* noundef byval(<8 x float>) align 32 %{{.*}}) +// NOAVX: call {{(x86_64_sysvcc )?}}void @take_m256(<8 x float>* byval(<8 x float>) align 32 %{{.*}}) // NOAVX: call {{(x86_64_sysvcc )?}}<16 x float> @get_m512() -// NOAVX: call {{(x86_64_sysvcc )?}}void @take_m512(<16 x float>* noundef byval(<16 x float>) align 64 %{{.*}}) +// NOAVX: call {{(x86_64_sysvcc )?}}void @take_m512(<16 x float>* byval(<16 x float>) align 64 %{{.*}}) diff --git a/clang/test/CodeGen/temporary-lifetime.cpp b/clang/test/CodeGen/temporary-lifetime.cpp index af1907cb99158dc8b691c438dffcf8bfc60441f6..f03817f8281768bc43f68073c1990cd8d2d5c364 100644 --- a/clang/test/CodeGen/temporary-lifetime.cpp +++ b/clang/test/CodeGen/temporary-lifetime.cpp @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -disable-noundef-analysis %s -std=c++11 -O1 -DWITH_DTOR -triple x86_64 -emit-llvm -o - | FileCheck -check-prefix=CHECK-DTOR %s -// RUN: %clang_cc1 -disable-noundef-analysis %s -std=c++11 -O1 -triple x86_64 -emit-llvm -o - | FileCheck -check-prefix=CHECK-NO-DTOR %s +// RUN: %clang_cc1 %s -std=c++11 -O1 -DWITH_DTOR -triple x86_64 -emit-llvm -o - | FileCheck -check-prefix=CHECK-DTOR %s +// RUN: %clang_cc1 %s -std=c++11 -O1 -triple x86_64 -emit-llvm -o - | FileCheck -check-prefix=CHECK-NO-DTOR %s struct A { A(); diff --git a/clang/test/CodeGen/thinlto-debug-pm.c b/clang/test/CodeGen/thinlto-debug-pm.c index 4175c4ef37dbaa68ef9b73a0471de312b8b6b79a..b3a26acc290ab4f9f74bc4003534800a53e7b509 100644 --- a/clang/test/CodeGen/thinlto-debug-pm.c +++ b/clang/test/CodeGen/thinlto-debug-pm.c @@ -1,23 +1,17 @@ // Test to ensure the opt level is passed down to the ThinLTO backend. // REQUIRES: x86-registered-target -// RUN: %clang_cc1 -O2 -o %t.o -flto=thin -fexperimental-new-pass-manager -triple x86_64-unknown-linux-gnu -emit-llvm-bc %s +// RUN: %clang_cc1 -O2 -o %t.o -flto=thin -triple x86_64-unknown-linux-gnu -emit-llvm-bc %s // RUN: llvm-lto -thinlto -o %t %t.o -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-obj -O2 -o %t2.o -x ir %t.o -fthinlto-index=%t.thinlto.bc -fno-experimental-new-pass-manager -mllvm -debug-pass=Structure 2>&1 | FileCheck %s --check-prefix=O2-OLDPM -// O2-OLDPM: Loop Vectorization +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-obj -O2 -o %t2.o -x ir %t.o -fthinlto-index=%t.thinlto.bc -fdebug-pass-manager 2>&1 | FileCheck %s --check-prefix=O2 +// O2: Running pass: LoopVectorizePass -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-obj -O2 -o %t2.o -x ir %t.o -fthinlto-index=%t.thinlto.bc -fdebug-pass-manager -fexperimental-new-pass-manager 2>&1 | FileCheck %s --check-prefix=O2-NEWPM -// O2-NEWPM: Running pass: LoopVectorizePass - -// RUN: %clang_cc1 -O0 -o %t.o -flto=thin -fexperimental-new-pass-manager -triple x86_64-unknown-linux-gnu -emit-llvm-bc %s +// RUN: %clang_cc1 -O0 -o %t.o -flto=thin -triple x86_64-unknown-linux-gnu -emit-llvm-bc %s // RUN: llvm-lto -thinlto -o %t %t.o -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-obj -O0 -o %t2.o -x ir %t.o -fthinlto-index=%t.thinlto.bc -fdebug-pass-manager -fexperimental-new-pass-manager 2>&1 | FileCheck %s --check-prefix=O0-NEWPM -// O0-NEWPM-NOT: Running pass: LoopVectorizePass - -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-obj -O0 -o %t2.o -x ir %t.o -fthinlto-index=%t.thinlto.bc -fno-experimental-new-pass-manager -mllvm -debug-pass=Structure 2>&1 | FileCheck %s --check-prefix=O0-OLDPM -// O0-OLDPM-NOT: Loop Vectorization +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-obj -O0 -o %t2.o -x ir %t.o -fthinlto-index=%t.thinlto.bc -fdebug-pass-manager 2>&1 | FileCheck %s --check-prefix=O0 +// O0-NOT: Running pass: LoopVectorizePass void foo() { } diff --git a/clang/test/CodeGen/transparent-union-redecl.c b/clang/test/CodeGen/transparent-union-redecl.c index dd1c0ae7ab1d3b123f198a1e05e4d9e5e3484534..11fb60d0ee13e1431bbb82c298a70623a4638d7a 100644 --- a/clang/test/CodeGen/transparent-union-redecl.c +++ b/clang/test/CodeGen/transparent-union-redecl.c @@ -16,27 +16,27 @@ typedef union { void f0(TU tu) {} void f0(int i); -// CHECK-LABEL: define{{.*}} void @f1(i32 noundef %tu.coerce) +// CHECK-LABEL: define{{.*}} void @f1(i32 %tu.coerce) // CHECK: %tu = alloca %union.TU, align 4 // CHECK: %coerce.dive = getelementptr inbounds %union.TU, %union.TU* %tu, i32 0, i32 0 // CHECK: store i32 %tu.coerce, i32* %coerce.dive, align 4 void f1(int i); void f1(TU tu) {} -// CHECK-LABEL: define{{.*}} void @f2(i32 noundef %i) +// CHECK-LABEL: define{{.*}} void @f2(i32 %i) // CHECK: %i.addr = alloca i32, align 4 // CHECK: store i32 %i, i32* %i.addr, align 4 void f2(TU tu); void f2(int i) {} -// CHECK-LABEL: define{{.*}} void @f3(i32 noundef %i) +// CHECK-LABEL: define{{.*}} void @f3(i32 %i) // CHECK: %i.addr = alloca i32, align 4 // CHECK: store i32 %i, i32* %i.addr, align 4 void f3(int i) {} void f3(TU tu); // Also test functions with parameters specified K&R style. -// CHECK-LABEL: define{{.*}} void @knrStyle(i32 noundef %tu.coerce) +// CHECK-LABEL: define{{.*}} void @knrStyle(i32 %tu.coerce) // CHECK: %tu = alloca %union.TU, align 4 // CHECK: %coerce.dive = getelementptr inbounds %union.TU, %union.TU* %tu, i32 0, i32 0 // CHECK: store i32 %tu.coerce, i32* %coerce.dive, align 4 diff --git a/clang/test/CodeGen/transparent-union.c b/clang/test/CodeGen/transparent-union.c index 07df3a1e6ff365b4da8afb76e59db1bb21270169..6b05af1c63aa52588a858a0fa671809fd2117c24 100644 --- a/clang/test/CodeGen/transparent-union.c +++ b/clang/test/CodeGen/transparent-union.c @@ -21,14 +21,14 @@ typedef union { void f0(transp_t0 obj); -// CHECK-LABEL: define{{.*}} void @f1_0(i32* noundef %a0) +// CHECK-LABEL: define{{.*}} void @f1_0(i32* %a0) // CHECK: call void @f0(i8* %{{.*}}) -// CHECK: call void %{{.*}}(i8* noundef %{{[a-z0-9]*}}) +// CHECK: call void %{{.*}}(i8* %{{[a-z0-9]*}}) // CHECK: } -// ARM-LABEL: define{{.*}} arm_aapcscc void @f1_0(i32* noundef %a0) +// ARM-LABEL: define{{.*}} arm_aapcscc void @f1_0(i32* %a0) // ARM: call arm_aapcscc void @f0(i8* %{{.*}}) -// ARM: call arm_aapcscc void %{{.*}}(i8* noundef %{{[a-z0-9]*}}) +// ARM: call arm_aapcscc void %{{.*}}(i8* %{{[a-z0-9]*}}) // ARM: } void f1_0(int *a0) { void (*f0p)(void *) = f0; diff --git a/clang/test/CodeGen/ubsan-function.cpp b/clang/test/CodeGen/ubsan-function.cpp index 2466d8a2645d299698a03617aab0b40072417581..2413d516aae410f4eed0801da0603f50ffb6d2f4 100644 --- a/clang/test/CodeGen/ubsan-function.cpp +++ b/clang/test/CodeGen/ubsan-function.cpp @@ -3,7 +3,7 @@ // CHECK-LABEL: define{{.*}} void @_Z3funv() #0 prologue <{ i32, i32 }> <{ i32 846595819, i32 trunc (i64 sub (i64 ptrtoint (i8** @0 to i64), i64 ptrtoint (void ()* @_Z3funv to i64)) to i32) }> { void fun() {} -// CHECK-LABEL: define{{.*}} void @_Z6callerPFvvE(void ()* noundef %f) +// CHECK-LABEL: define{{.*}} void @_Z6callerPFvvE(void ()* %f) // CHECK: getelementptr <{ i32, i32 }>, <{ i32, i32 }>* {{.*}}, i32 0, i32 0, !nosanitize // CHECK: load i32, i32* {{.*}}, align {{.*}}, !nosanitize // CHECK: icmp eq i32 {{.*}}, 846595819, !nosanitize diff --git a/clang/test/CodeGen/unique-internal-linkage-names-dwarf.c b/clang/test/CodeGen/unique-internal-linkage-names-dwarf.c index 8ab3dcd7b82a8891fe0fb431054f772dd5a02535..cae839830c6e22e798979f7bef0d0ead929200d9 100644 --- a/clang/test/CodeGen/unique-internal-linkage-names-dwarf.c +++ b/clang/test/CodeGen/unique-internal-linkage-names-dwarf.c @@ -27,7 +27,7 @@ void baz() { // PLAIN: @glob = internal global i32 // PLAIN: define internal i32 @foo() -// PLAIN: define internal i32 @bar(i32 noundef %a) +// PLAIN: define internal i32 @bar(i32 %a) // PLAIN: distinct !DIGlobalVariable(name: "glob"{{.*}}) // PLAIN: distinct !DISubprogram(name: "foo"{{.*}}) // PLAIN: distinct !DISubprogram(name: "bar"{{.*}}) @@ -35,7 +35,7 @@ void baz() { // // UNIQUE: @glob = internal global i32 // UNIQUE: define internal i32 @_ZL3foov.[[MODHASH:__uniq.[0-9]+]]() -// UNIQUE: define internal i32 @_ZL3bari.[[MODHASH]](i32 noundef %a) +// UNIQUE: define internal i32 @_ZL3bari.[[MODHASH]](i32 %a) // UNIQUE: distinct !DIGlobalVariable(name: "glob"{{.*}}) // UNIQUE: distinct !DISubprogram(name: "foo", linkageName: "_ZL3foov.[[MODHASH]]"{{.*}}) // UNIQUE: distinct !DISubprogram(name: "bar", linkageName: "_ZL3bari.[[MODHASH]]"{{.*}}) diff --git a/clang/test/CodeGen/unique-internal-linkage-names-dwarf.cpp b/clang/test/CodeGen/unique-internal-linkage-names-dwarf.cpp index cdd7062a3a00943b52eb8981f4a98820625e14ec..37ebfe5eee17334b82078cc3385d8634c566b68f 100644 --- a/clang/test/CodeGen/unique-internal-linkage-names-dwarf.cpp +++ b/clang/test/CodeGen/unique-internal-linkage-names-dwarf.cpp @@ -34,27 +34,27 @@ void baz() { } // PLAIN-DAG: @_ZL8glob_foo = internal global i32 -// PLAIN-DAG: define internal noundef i32 @_ZL3foov() +// PLAIN-DAG: define internal i32 @_ZL3foov() // PLAIN-DAG: distinct !DIGlobalVariable(name: "glob_foo", linkageName: "_ZL8glob_foo"{{.*}}) // PLAIN-DAG: distinct !DISubprogram(name: "foo", linkageName: "_ZL3foov"{{.*}}) // PLAIN-DAG: @_ZN12_GLOBAL__N_18glob_barE = internal global i32 -// PLAIN-DAG: define internal noundef i32 @_ZN12_GLOBAL__N_13barEv() +// PLAIN-DAG: define internal i32 @_ZN12_GLOBAL__N_13barEv() // PLAIN-DAG: distinct !DIGlobalVariable(name: "glob_bar", linkageName: "_ZN12_GLOBAL__N_18glob_barE"{{.*}}) // PLAIN-DAG: distinct !DISubprogram(name: "bar", linkageName: "_ZN12_GLOBAL__N_13barEv"{{.*}}) // PLAIN-DAG: @_ZL8glob_zip = internal global i32 -// PLAIN-DAG: define internal noundef i32 @_ZL3zipv() +// PLAIN-DAG: define internal i32 @_ZL3zipv() // PLAIN-DAG: distinct !DIGlobalVariable(name: "glob_zip", linkageName: "_ZL8glob_zip"{{.*}}) // PLAIN-DAG: distinct !DISubprogram(name: "zip", linkageName: "_ZL3zipv"{{.*}}) // UNIQUE-DAG: @_ZL8glob_foo = internal global i32 -// UNIQUE-DAG: define internal noundef i32 @_ZL3foov.[[MODHASH:__uniq\.[0-9]+]]() +// UNIQUE-DAG: define internal i32 @_ZL3foov.[[MODHASH:__uniq\.[0-9]+]]() // UNIQUE-DAG: distinct !DIGlobalVariable(name: "glob_foo", linkageName: "_ZL8glob_foo"{{.*}}) // UNIQUE-DAG: distinct !DISubprogram(name: "foo", linkageName: "_ZL3foov.[[MODHASH]]"{{.*}}) // UNIQUE-DAG: @_ZN12_GLOBAL__N_18glob_barE = internal global i32 -// UNIQUE-DAG: define internal noundef i32 @_ZN12_GLOBAL__N_13barEv.[[MODHASH]]() +// UNIQUE-DAG: define internal i32 @_ZN12_GLOBAL__N_13barEv.[[MODHASH]]() // UNIQUE-DAG: distinct !DIGlobalVariable(name: "glob_bar", linkageName: "_ZN12_GLOBAL__N_18glob_barE"{{.*}}) // UNIQUE-DAG: distinct !DISubprogram(name: "bar", linkageName: "_ZN12_GLOBAL__N_13barEv.[[MODHASH]]"{{.*}}) // UNIQUE-DAG: @_ZL8glob_zip = internal global i32 -// UNIQUE-DAG: define internal noundef i32 @_ZL3zipv.[[MODHASH]]() +// UNIQUE-DAG: define internal i32 @_ZL3zipv.[[MODHASH]]() // UNIQUE-DAG: distinct !DIGlobalVariable(name: "glob_zip", linkageName: "_ZL8glob_zip"{{.*}}) // UNIQUE-DAG: distinct !DISubprogram(name: "zip", linkageName: "_ZL3zipv.[[MODHASH]]"{{.*}}) diff --git a/clang/test/CodeGen/unique-internal-linkage-names.cpp b/clang/test/CodeGen/unique-internal-linkage-names.cpp index f5b0200d28b57365803e905f52c59aa5e0b0ea69..65069c049b6378316b1833b152b8dfd8e17e3cfa 100644 --- a/clang/test/CodeGen/unique-internal-linkage-names.cpp +++ b/clang/test/CodeGen/unique-internal-linkage-names.cpp @@ -57,22 +57,22 @@ void test() { // PLAIN: @_ZL4glob = internal global // PLAIN: @_ZZ8retAnonMvE5fGlob = internal global // PLAIN: @_ZN12_GLOBAL__N_16anon_mE = internal global -// PLAIN: define internal noundef i32 @_ZL3foov() -// PLAIN: define internal noundef i32 @_ZN12_GLOBAL__N_14getMEv +// PLAIN: define internal i32 @_ZL3foov() +// PLAIN: define internal i32 @_ZN12_GLOBAL__N_14getMEv // PLAIN: define internal i32 ()* @_ZL4mverv.resolver() // PLAIN: define internal void @_ZN12_GLOBAL__N_11AC1Ev // PLAIN: define internal void @_ZN12_GLOBAL__N_11AD1Ev -// PLAIN: define internal noundef i32 @_ZL4mverv() -// PLAIN: define internal noundef i32 @_ZL4mverv.sse4.2() +// PLAIN: define internal i32 @_ZL4mverv() +// PLAIN: define internal i32 @_ZL4mverv.sse4.2() // PLAIN-NOT: "sample-profile-suffix-elision-policy" // UNIQUE: @_ZL4glob = internal global // UNIQUE: @_ZZ8retAnonMvE5fGlob = internal global // UNIQUE: @_ZN12_GLOBAL__N_16anon_mE = internal global -// UNIQUE: define internal noundef i32 @_ZL3foov.[[MODHASH:__uniq.[0-9]+]]() #[[#ATTR:]] { -// UNIQUE: define internal noundef i32 @_ZN12_GLOBAL__N_14getMEv.[[MODHASH]] +// UNIQUE: define internal i32 @_ZL3foov.[[MODHASH:__uniq.[0-9]+]]() #[[#ATTR:]] { +// UNIQUE: define internal i32 @_ZN12_GLOBAL__N_14getMEv.[[MODHASH]] // UNIQUE: define internal i32 ()* @_ZL4mverv.[[MODHASH]].resolver() // UNIQUE: define internal void @_ZN12_GLOBAL__N_11AC1Ev.__uniq.68358509610070717889884130747296293671 // UNIQUE: define internal void @_ZN12_GLOBAL__N_11AD1Ev.__uniq.68358509610070717889884130747296293671 -// UNIQUE: define internal noundef i32 @_ZL4mverv.[[MODHASH]]() -// UNIQUE: define internal noundef i32 @_ZL4mverv.[[MODHASH]].sse4.2 +// UNIQUE: define internal i32 @_ZL4mverv.[[MODHASH]]() +// UNIQUE: define internal i32 @_ZL4mverv.[[MODHASH]].sse4.2 // UNIQUE: attributes #[[#ATTR]] = { {{.*}}"sample-profile-suffix-elision-policy"{{.*}} } diff --git a/clang/test/CodeGen/use-sample-profile-attr.c b/clang/test/CodeGen/use-sample-profile-attr.c index ba6db07c322650cc2f628ba1cff10f26c330cd45..9c24355d67dba754e0f8703cd56093245bb5fa2f 100644 --- a/clang/test/CodeGen/use-sample-profile-attr.c +++ b/clang/test/CodeGen/use-sample-profile-attr.c @@ -1,15 +1,10 @@ // Test use-sample-profile attribute is present only when SampleFDO // is enabled. // -// RUN: %clang_cc1 -O2 -fno-experimental-new-pass-manager \ +// RUN: %clang_cc1 -O2 \ // RUN: -fprofile-sample-use=%S/Inputs/pgo-sample.prof %s -emit-llvm -o - \ // RUN: 2>&1 | FileCheck %s -// RUN: %clang_cc1 -O2 -fexperimental-new-pass-manager \ -// RUN: -fprofile-sample-use=%S/Inputs/pgo-sample.prof %s -emit-llvm -o - \ -// RUN: 2>&1 | FileCheck %s -// RUN: %clang_cc1 -O2 -fno-experimental-new-pass-manager %s \ -// RUN: -emit-llvm -o - 2>&1 | FileCheck %s --check-prefix=NOATTR -// RUN: %clang_cc1 -O2 -fexperimental-new-pass-manager %s -emit-llvm -o - \ +// RUN: %clang_cc1 -O2 %s -emit-llvm -o - \ // RUN: 2>&1 | FileCheck %s --check-prefix=NOATTR // CHECK: define{{.*}} @func{{.*}} #[[ATTRID:[0-9]+]] diff --git a/clang/test/CodeGen/variadic-null-win64.c b/clang/test/CodeGen/variadic-null-win64.c index ccd7b507829e6bb9393b3aa06d2f2fd6c944d777..5acf05fa6094f92bc9db0d40c9c2b6e1c7b41db4 100644 --- a/clang/test/CodeGen/variadic-null-win64.c +++ b/clang/test/CodeGen/variadic-null-win64.c @@ -15,9 +15,9 @@ void f(const char *f) { v(f, 1, 2, 3, NULL); kr(f, 1, 2, 3, 0); } -// WINDOWS: define dso_local void @f(i8* noundef %f) -// WINDOWS: call void (i8*, ...) @v(i8* {{.*}}, i32 noundef 1, i32 noundef 2, i32 noundef 3, i64 noundef 0) -// WINDOWS: call void bitcast (void (...)* @kr to void (i8*, i32, i32, i32, i32)*)(i8* noundef {{.*}}, i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 0) -// LINUX: define{{.*}} void @f(i8* noundef %f) -// LINUX: call void (i8*, ...) @v(i8* {{.*}}, i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 0) -// LINUX: call void (i8*, i32, i32, i32, i32, ...) bitcast (void (...)* @kr to void (i8*, i32, i32, i32, i32, ...)*)(i8* {{.*}}, i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 0) +// WINDOWS: define dso_local void @f(i8* %f) +// WINDOWS: call void (i8*, ...) @v(i8* {{.*}}, i32 1, i32 2, i32 3, i64 0) +// WINDOWS: call void bitcast (void (...)* @kr to void (i8*, i32, i32, i32, i32)*)(i8* {{.*}}, i32 1, i32 2, i32 3, i32 0) +// LINUX: define{{.*}} void @f(i8* %f) +// LINUX: call void (i8*, ...) @v(i8* {{.*}}, i32 1, i32 2, i32 3, i32 0) +// LINUX: call void (i8*, i32, i32, i32, i32, ...) bitcast (void (...)* @kr to void (i8*, i32, i32, i32, i32, ...)*)(i8* {{.*}}, i32 1, i32 2, i32 3, i32 0) diff --git a/clang/test/CodeGen/ve-abi.c b/clang/test/CodeGen/ve-abi.c index 74248c1ce049d94d5f9007df618b91fed8eb6784..511f1a69ae0fd340735d2b7e1c828a9c80063f17 100644 --- a/clang/test/CodeGen/ve-abi.c +++ b/clang/test/CodeGen/ve-abi.c @@ -10,87 +10,87 @@ // RUN: %clang_cc1 -triple ve-linux-gnu -emit-llvm %s -o - | FileCheck %s -// CHECK-LABEL: define{{.*}} signext i8 @fun_si8(i8 noundef signext %a, i8 noundef signext %b) #0 { +// CHECK-LABEL: define{{.*}} signext i8 @fun_si8(i8 signext %a, i8 signext %b) #0 { char fun_si8(char a, char b) { return a; } -// CHECK-LABEL: define{{.*}} zeroext i8 @fun_zi8(i8 noundef zeroext %a, i8 noundef zeroext %b) #0 { +// CHECK-LABEL: define{{.*}} zeroext i8 @fun_zi8(i8 zeroext %a, i8 zeroext %b) #0 { unsigned char fun_zi8(unsigned char a, unsigned char b) { return a; } -// CHECK-LABEL: define{{.*}} signext i16 @fun_si16(i16 noundef signext %a, i16 noundef signext %b) #0 { +// CHECK-LABEL: define{{.*}} signext i16 @fun_si16(i16 signext %a, i16 signext %b) #0 { short fun_si16(short a, short b) { return a; } -// CHECK-LABEL: define{{.*}} zeroext i16 @fun_zi16(i16 noundef zeroext %a, i16 noundef zeroext %b) #0 { +// CHECK-LABEL: define{{.*}} zeroext i16 @fun_zi16(i16 zeroext %a, i16 zeroext %b) #0 { unsigned short fun_zi16(unsigned short a, unsigned short b) { return a; } -// CHECK-LABEL: define{{.*}} signext i32 @fun_si32(i32 noundef signext %a, i32 noundef signext %b) #0 { +// CHECK-LABEL: define{{.*}} signext i32 @fun_si32(i32 signext %a, i32 signext %b) #0 { int fun_si32(int a, int b) { return a; } -// CHECK-LABEL: define{{.*}} zeroext i32 @fun_zi32(i32 noundef zeroext %a, i32 noundef zeroext %b) #0 { +// CHECK-LABEL: define{{.*}} zeroext i32 @fun_zi32(i32 zeroext %a, i32 zeroext %b) #0 { unsigned int fun_zi32(unsigned int a, unsigned int b) { return a; } -// CHECK-LABEL: define{{.*}} i64 @fun_si64(i64 noundef %a, i64 noundef %b) #0 { +// CHECK-LABEL: define{{.*}} i64 @fun_si64(i64 %a, i64 %b) #0 { long fun_si64(long a, long b) { return a; } -// CHECK-LABEL: define{{.*}} i64 @fun_zi64(i64 noundef %a, i64 noundef %b) #0 { +// CHECK-LABEL: define{{.*}} i64 @fun_zi64(i64 %a, i64 %b) #0 { unsigned long fun_zi64(unsigned long a, unsigned long b) { return a; } -// CHECK-LABEL: define{{.*}} i128 @fun_si128(i128 noundef %a, i128 noundef %b) #0 { +// CHECK-LABEL: define{{.*}} i128 @fun_si128(i128 %a, i128 %b) #0 { __int128 fun_si128(__int128 a, __int128 b) { } -// CHECK-LABEL: define{{.*}} i128 @fun_zi128(i128 noundef %a, i128 noundef %b) #0 { +// CHECK-LABEL: define{{.*}} i128 @fun_zi128(i128 %a, i128 %b) #0 { unsigned __int128 fun_zi128(unsigned __int128 a, unsigned __int128 b) { return a; } -// CHECK-LABEL: define{{.*}} float @fun_float(float noundef %a, float noundef %b) #0 { +// CHECK-LABEL: define{{.*}} float @fun_float(float %a, float %b) #0 { float fun_float(float a, float b) { return a; } -// CHECK-LABEL: define{{.*}} double @fun_double(double noundef %a, double noundef %b) #0 { +// CHECK-LABEL: define{{.*}} double @fun_double(double %a, double %b) #0 { double fun_double(double a, double b) { return a; } -// CHECK-LABEL: define{{.*}} fp128 @fun_quad(fp128 noundef %a, fp128 noundef %b) #0 { +// CHECK-LABEL: define{{.*}} fp128 @fun_quad(fp128 %a, fp128 %b) #0 { long double fun_quad(long double a, long double b) { return a; } -// CHECK-LABEL: define{{.*}} { float, float } @fun_fcomplex(float noundef %a.coerce0, float noundef %a.coerce1, float noundef %b.coerce0, float noundef %b.coerce1) #0 { +// CHECK-LABEL: define{{.*}} { float, float } @fun_fcomplex(float %a.coerce0, float %a.coerce1, float %b.coerce0, float %b.coerce1) #0 { float __complex__ fun_fcomplex(float __complex__ a, float __complex__ b) { return a; } -// CHECK-LABEL: define{{.*}} { double, double } @fun_dcomplex(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b.coerce0, double noundef %b.coerce1) #0 { +// CHECK-LABEL: define{{.*}} { double, double } @fun_dcomplex(double %a.coerce0, double %a.coerce1, double %b.coerce0, double %b.coerce1) #0 { double __complex__ fun_dcomplex(double __complex__ a, double __complex__ b) { return a; } -// CHECK-LABEL: define{{.*}} { fp128, fp128 } @fun_qcomplex(fp128 noundef %a.coerce0, fp128 noundef %a.coerce1, fp128 noundef %b.coerce0, fp128 noundef %b.coerce1) #0 { +// CHECK-LABEL: define{{.*}} { fp128, fp128 } @fun_qcomplex(fp128 %a.coerce0, fp128 %a.coerce1, fp128 %b.coerce0, fp128 %b.coerce1) #0 { long double __complex__ fun_qcomplex(long double __complex__ a, long double __complex__ b) { return a; } extern int hoge(); void func() { - // CHECK: %call = call signext i32 (i32, i32, i32, i32, i32, i32, i32, ...) bitcast (i32 (...)* @hoge to i32 (i32, i32, i32, i32, i32, i32, i32, ...)*)(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, i32 noundef signext 6, i32 noundef signext 7) + // CHECK: %call = call signext i32 (i32, i32, i32, i32, i32, i32, i32, ...) bitcast (i32 (...)* @hoge to i32 (i32, i32, i32, i32, i32, i32, i32, ...)*)(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, i32 signext 5, i32 signext 6, i32 signext 7) hoge(1, 2, 3, 4, 5, 6, 7); } diff --git a/clang/test/CodeGen/vectorcall.c b/clang/test/CodeGen/vectorcall.c index a1f781fee5df07437447ee0837c357596807998c..d4a944e64d25c0075dd2314110e799dac757de2d 100644 --- a/clang/test/CodeGen/vectorcall.c +++ b/clang/test/CodeGen/vectorcall.c @@ -2,50 +2,50 @@ // RUN: %clang_cc1 -emit-llvm %s -o - -ffreestanding -triple=x86_64-pc-win32 | FileCheck %s --check-prefix=X64 void __vectorcall v1(int a, int b) {} -// X32: define dso_local x86_vectorcallcc void @"\01v1@@8"(i32 inreg noundef %a, i32 inreg noundef %b) -// X64: define dso_local x86_vectorcallcc void @"\01v1@@16"(i32 noundef %a, i32 noundef %b) +// X32: define dso_local x86_vectorcallcc void @"\01v1@@8"(i32 inreg %a, i32 inreg %b) +// X64: define dso_local x86_vectorcallcc void @"\01v1@@16"(i32 %a, i32 %b) void __vectorcall v2(char a, char b) {} -// X32: define dso_local x86_vectorcallcc void @"\01v2@@8"(i8 inreg noundef signext %a, i8 inreg noundef signext %b) -// X64: define dso_local x86_vectorcallcc void @"\01v2@@16"(i8 noundef %a, i8 noundef %b) +// X32: define dso_local x86_vectorcallcc void @"\01v2@@8"(i8 inreg signext %a, i8 inreg signext %b) +// X64: define dso_local x86_vectorcallcc void @"\01v2@@16"(i8 %a, i8 %b) struct Small { int x; }; void __vectorcall v3(int a, struct Small b, int c) {} -// X32: define dso_local x86_vectorcallcc void @"\01v3@@12"(i32 inreg noundef %a, i32 %b.0, i32 inreg noundef %c) -// X64: define dso_local x86_vectorcallcc void @"\01v3@@24"(i32 noundef %a, i32 %b.coerce, i32 noundef %c) +// X32: define dso_local x86_vectorcallcc void @"\01v3@@12"(i32 inreg %a, i32 %b.0, i32 inreg %c) +// X64: define dso_local x86_vectorcallcc void @"\01v3@@24"(i32 %a, i32 %b.coerce, i32 %c) struct Large { int a[5]; }; void __vectorcall v4(int a, struct Large b, int c) {} -// X32: define dso_local x86_vectorcallcc void @"\01v4@@28"(i32 inreg noundef %a, %struct.Large* noundef byval(%struct.Large) align 4 %b, i32 inreg noundef %c) -// X64: define dso_local x86_vectorcallcc void @"\01v4@@40"(i32 noundef %a, %struct.Large* noundef %b, i32 noundef %c) +// X32: define dso_local x86_vectorcallcc void @"\01v4@@28"(i32 inreg %a, %struct.Large* byval(%struct.Large) align 4 %b, i32 inreg %c) +// X64: define dso_local x86_vectorcallcc void @"\01v4@@40"(i32 %a, %struct.Large* %b, i32 %c) struct HFA2 { double x, y; }; struct HFA4 { double w, x, y, z; }; struct HFA5 { double v, w, x, y, z; }; void __vectorcall hfa1(int a, struct HFA4 b, int c) {} -// X32: define dso_local x86_vectorcallcc void @"\01hfa1@@40"(i32 inreg noundef %a, %struct.HFA4 inreg %b.coerce, i32 inreg noundef %c) -// X64: define dso_local x86_vectorcallcc void @"\01hfa1@@48"(i32 noundef %a, %struct.HFA4 inreg %b.coerce, i32 noundef %c) +// X32: define dso_local x86_vectorcallcc void @"\01hfa1@@40"(i32 inreg %a, %struct.HFA4 inreg %b.coerce, i32 inreg %c) +// X64: define dso_local x86_vectorcallcc void @"\01hfa1@@48"(i32 %a, %struct.HFA4 inreg %b.coerce, i32 %c) // HFAs that would require more than six total SSE registers are passed // indirectly. Additional vector arguments can consume the rest of the SSE // registers. void __vectorcall hfa2(struct HFA4 a, struct HFA4 b, double c) {} -// X32: define dso_local x86_vectorcallcc void @"\01hfa2@@72"(%struct.HFA4 inreg %a.coerce, %struct.HFA4* inreg noundef %b, double inreg noundef %c) -// X64: define dso_local x86_vectorcallcc void @"\01hfa2@@72"(%struct.HFA4 inreg %a.coerce, %struct.HFA4* noundef %b, double noundef %c) +// X32: define dso_local x86_vectorcallcc void @"\01hfa2@@72"(%struct.HFA4 inreg %a.coerce, %struct.HFA4* inreg %b, double inreg %c) +// X64: define dso_local x86_vectorcallcc void @"\01hfa2@@72"(%struct.HFA4 inreg %a.coerce, %struct.HFA4* %b, double %c) // Ensure that we pass builtin types directly while counting them against the // SSE register usage. void __vectorcall hfa3(double a, double b, double c, double d, double e, struct HFA2 f) {} -// X32: define dso_local x86_vectorcallcc void @"\01hfa3@@56"(double inreg noundef %a, double inreg noundef %b, double inreg noundef %c, double inreg noundef %d, double inreg noundef %e, %struct.HFA2* inreg noundef %f) -// X64: define dso_local x86_vectorcallcc void @"\01hfa3@@56"(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, %struct.HFA2* noundef %f) +// X32: define dso_local x86_vectorcallcc void @"\01hfa3@@56"(double inreg %a, double inreg %b, double inreg %c, double inreg %d, double inreg %e, %struct.HFA2* inreg %f) +// X64: define dso_local x86_vectorcallcc void @"\01hfa3@@56"(double %a, double %b, double %c, double %d, double %e, %struct.HFA2* %f) // Aggregates with more than four elements are not HFAs and are passed byval. // Because they are not classified as homogeneous, they don't get special // handling to ensure alignment. void __vectorcall hfa4(struct HFA5 a) {} -// X32: define dso_local x86_vectorcallcc void @"\01hfa4@@40"(%struct.HFA5* noundef byval(%struct.HFA5) align 4 %0) -// X64: define dso_local x86_vectorcallcc void @"\01hfa4@@40"(%struct.HFA5* noundef %a) +// X32: define dso_local x86_vectorcallcc void @"\01hfa4@@40"(%struct.HFA5* byval(%struct.HFA5) align 4 %0) +// X64: define dso_local x86_vectorcallcc void @"\01hfa4@@40"(%struct.HFA5* %a) // Return HFAs of 4 or fewer elements in registers. static struct HFA2 g_hfa2; @@ -60,38 +60,38 @@ struct HVA4 { v4f32 w, x, y, z; }; struct HVA5 { v4f32 w, x, y, z, p; }; v4f32 __vectorcall hva1(int a, struct HVA4 b, int c) {return b.w;} -// X32: define dso_local x86_vectorcallcc <4 x float> @"\01hva1@@72"(i32 inreg noundef %a, %struct.HVA4 inreg %b.coerce, i32 inreg noundef %c) -// X64: define dso_local x86_vectorcallcc <4 x float> @"\01hva1@@80"(i32 noundef %a, %struct.HVA4 inreg %b.coerce, i32 noundef %c) +// X32: define dso_local x86_vectorcallcc <4 x float> @"\01hva1@@72"(i32 inreg %a, %struct.HVA4 inreg %b.coerce, i32 inreg %c) +// X64: define dso_local x86_vectorcallcc <4 x float> @"\01hva1@@80"(i32 %a, %struct.HVA4 inreg %b.coerce, i32 %c) v4f32 __vectorcall hva2(struct HVA4 a, struct HVA4 b, v4f32 c) {return c;} -// X32: define dso_local x86_vectorcallcc <4 x float> @"\01hva2@@144"(%struct.HVA4 inreg %a.coerce, %struct.HVA4* inreg noundef %b, <4 x float> inreg noundef %c) -// X64: define dso_local x86_vectorcallcc <4 x float> @"\01hva2@@144"(%struct.HVA4 inreg %a.coerce, %struct.HVA4* noundef %b, <4 x float> noundef %c) +// X32: define dso_local x86_vectorcallcc <4 x float> @"\01hva2@@144"(%struct.HVA4 inreg %a.coerce, %struct.HVA4* inreg %b, <4 x float> inreg %c) +// X64: define dso_local x86_vectorcallcc <4 x float> @"\01hva2@@144"(%struct.HVA4 inreg %a.coerce, %struct.HVA4* %b, <4 x float> %c) v4f32 __vectorcall hva3(v4f32 a, v4f32 b, v4f32 c, v4f32 d, v4f32 e, struct HVA2 f) {return f.x;} -// X32: define dso_local x86_vectorcallcc <4 x float> @"\01hva3@@112"(<4 x float> inreg noundef %a, <4 x float> inreg noundef %b, <4 x float> inreg noundef %c, <4 x float> inreg noundef %d, <4 x float> inreg noundef %e, %struct.HVA2* inreg noundef %f) -// X64: define dso_local x86_vectorcallcc <4 x float> @"\01hva3@@112"(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, <4 x float> noundef %d, <4 x float> noundef %e, %struct.HVA2* noundef %f) +// X32: define dso_local x86_vectorcallcc <4 x float> @"\01hva3@@112"(<4 x float> inreg %a, <4 x float> inreg %b, <4 x float> inreg %c, <4 x float> inreg %d, <4 x float> inreg %e, %struct.HVA2* inreg %f) +// X64: define dso_local x86_vectorcallcc <4 x float> @"\01hva3@@112"(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, <4 x float> %e, %struct.HVA2* %f) // vector types have higher priority then HVA structures, So vector types are allocated first // and HVAs are allocated if enough registers are available v4f32 __vectorcall hva4(struct HVA4 a, struct HVA2 b, v4f32 c) {return b.y;} -// X32: define dso_local x86_vectorcallcc <4 x float> @"\01hva4@@112"(%struct.HVA4 inreg %a.coerce, %struct.HVA2* inreg noundef %b, <4 x float> inreg noundef %c) -// X64: define dso_local x86_vectorcallcc <4 x float> @"\01hva4@@112"(%struct.HVA4 inreg %a.coerce, %struct.HVA2* noundef %b, <4 x float> noundef %c) +// X32: define dso_local x86_vectorcallcc <4 x float> @"\01hva4@@112"(%struct.HVA4 inreg %a.coerce, %struct.HVA2* inreg %b, <4 x float> inreg %c) +// X64: define dso_local x86_vectorcallcc <4 x float> @"\01hva4@@112"(%struct.HVA4 inreg %a.coerce, %struct.HVA2* %b, <4 x float> %c) v4f32 __vectorcall hva5(struct HVA3 a, struct HVA3 b, v4f32 c, struct HVA2 d) {return d.y;} -// X32: define dso_local x86_vectorcallcc <4 x float> @"\01hva5@@144"(%struct.HVA3 inreg %a.coerce, %struct.HVA3* inreg noundef %b, <4 x float> inreg noundef %c, %struct.HVA2 inreg %d.coerce) -// X64: define dso_local x86_vectorcallcc <4 x float> @"\01hva5@@144"(%struct.HVA3 inreg %a.coerce, %struct.HVA3* noundef %b, <4 x float> noundef %c, %struct.HVA2 inreg %d.coerce) +// X32: define dso_local x86_vectorcallcc <4 x float> @"\01hva5@@144"(%struct.HVA3 inreg %a.coerce, %struct.HVA3* inreg %b, <4 x float> inreg %c, %struct.HVA2 inreg %d.coerce) +// X64: define dso_local x86_vectorcallcc <4 x float> @"\01hva5@@144"(%struct.HVA3 inreg %a.coerce, %struct.HVA3* %b, <4 x float> %c, %struct.HVA2 inreg %d.coerce) struct HVA4 __vectorcall hva6(struct HVA4 a, struct HVA4 b) { return b;} -// X32: define dso_local x86_vectorcallcc %struct.HVA4 @"\01hva6@@128"(%struct.HVA4 inreg %a.coerce, %struct.HVA4* inreg noundef %b) -// X64: define dso_local x86_vectorcallcc %struct.HVA4 @"\01hva6@@128"(%struct.HVA4 inreg %a.coerce, %struct.HVA4* noundef %b) +// X32: define dso_local x86_vectorcallcc %struct.HVA4 @"\01hva6@@128"(%struct.HVA4 inreg %a.coerce, %struct.HVA4* inreg %b) +// X64: define dso_local x86_vectorcallcc %struct.HVA4 @"\01hva6@@128"(%struct.HVA4 inreg %a.coerce, %struct.HVA4* %b) struct HVA5 __vectorcall hva7() {struct HVA5 a = {}; return a;} // X32: define dso_local x86_vectorcallcc void @"\01hva7@@0"(%struct.HVA5* inreg noalias sret(%struct.HVA5) align 16 %agg.result) // X64: define dso_local x86_vectorcallcc void @"\01hva7@@0"(%struct.HVA5* noalias sret(%struct.HVA5) align 16 %agg.result) v4f32 __vectorcall hva8(v4f32 a, v4f32 b, v4f32 c, v4f32 d, int e, v4f32 f) {return f;} -// X32: define dso_local x86_vectorcallcc <4 x float> @"\01hva8@@84"(<4 x float> inreg noundef %a, <4 x float> inreg noundef %b, <4 x float> inreg noundef %c, <4 x float> inreg noundef %d, i32 inreg noundef %e, <4 x float> inreg noundef %f) -// X64: define dso_local x86_vectorcallcc <4 x float> @"\01hva8@@88"(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, <4 x float> noundef %d, i32 noundef %e, <4 x float> noundef %f) +// X32: define dso_local x86_vectorcallcc <4 x float> @"\01hva8@@84"(<4 x float> inreg %a, <4 x float> inreg %b, <4 x float> inreg %c, <4 x float> inreg %d, i32 inreg %e, <4 x float> inreg %f) +// X64: define dso_local x86_vectorcallcc <4 x float> @"\01hva8@@88"(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, i32 %e, <4 x float> %f) typedef float __attribute__((ext_vector_type(3))) v3f32; struct OddSizeHVA { v3f32 x, y; }; @@ -104,8 +104,8 @@ void __vectorcall odd_size_hva(struct OddSizeHVA a) {} // consider 'p7' as a register. Instead p5 gets put into the register on the second pass. // x86 should pass p2, p6 and p7 in registers, then p1 in the second pass. struct HFA2 __vectorcall AddParticles(struct HFA2 p1, float p2, struct HFA4 p3, int p4, struct HFA2 p5, float p6, float p7, int p8){ return p1;} -// X32: define dso_local x86_vectorcallcc %struct.HFA2 @"\01AddParticles@@84"(%struct.HFA2 inreg %p1.coerce, float inreg noundef %p2, %struct.HFA4* inreg noundef %p3, i32 inreg noundef %p4, %struct.HFA2* noundef %p5, float inreg noundef %p6, float inreg noundef %p7, i32 noundef %p8) -// X64: define dso_local x86_vectorcallcc %struct.HFA2 @"\01AddParticles@@104"(%struct.HFA2 inreg %p1.coerce, float noundef %p2, %struct.HFA4* noundef %p3, i32 noundef %p4, %struct.HFA2 inreg %p5.coerce, float noundef %p6, float noundef %p7, i32 noundef %p8) +// X32: define dso_local x86_vectorcallcc %struct.HFA2 @"\01AddParticles@@84"(%struct.HFA2 inreg %p1.coerce, float inreg %p2, %struct.HFA4* inreg %p3, i32 inreg %p4, %struct.HFA2* %p5, float inreg %p6, float inreg %p7, i32 %p8) +// X64: define dso_local x86_vectorcallcc %struct.HFA2 @"\01AddParticles@@104"(%struct.HFA2 inreg %p1.coerce, float %p2, %struct.HFA4* %p3, i32 %p4, %struct.HFA2 inreg %p5.coerce, float %p6, float %p7, i32 %p8) // Vectorcall in both architectures allows passing of an HVA as long as there is room, // even if it is not one of the first 6 arguments. First pass puts p4 into a @@ -113,8 +113,8 @@ struct HFA2 __vectorcall AddParticles(struct HFA2 p1, float p2, struct HFA4 p3, // in a register, does NOT put p7 in a register (since theres no room), then puts // p8 in a register. void __vectorcall HVAAnywhere(struct HFA2 p1, int p2, int p3, float p4, int p5, int p6, struct HFA4 p7, struct HFA2 p8, float p9){} -// X32: define dso_local x86_vectorcallcc void @"\01HVAAnywhere@@88"(%struct.HFA2 inreg %p1.coerce, i32 inreg noundef %p2, i32 inreg noundef %p3, float inreg noundef %p4, i32 noundef %p5, i32 noundef %p6, %struct.HFA4* noundef %p7, %struct.HFA2 inreg %p8.coerce, float inreg noundef %p9) -// X64: define dso_local x86_vectorcallcc void @"\01HVAAnywhere@@112"(%struct.HFA2 inreg %p1.coerce, i32 noundef %p2, i32 noundef %p3, float noundef %p4, i32 noundef %p5, i32 noundef %p6, %struct.HFA4* noundef %p7, %struct.HFA2 inreg %p8.coerce, float noundef %p9) +// X32: define dso_local x86_vectorcallcc void @"\01HVAAnywhere@@88"(%struct.HFA2 inreg %p1.coerce, i32 inreg %p2, i32 inreg %p3, float inreg %p4, i32 %p5, i32 %p6, %struct.HFA4* %p7, %struct.HFA2 inreg %p8.coerce, float inreg %p9) +// X64: define dso_local x86_vectorcallcc void @"\01HVAAnywhere@@112"(%struct.HFA2 inreg %p1.coerce, i32 %p2, i32 %p3, float %p4, i32 %p5, i32 %p6, %struct.HFA4* %p7, %struct.HFA2 inreg %p8.coerce, float %p9) #ifndef __x86_64__ // This covers the three ways XMM values can be passed on 32-bit x86: @@ -127,13 +127,13 @@ void __vectorcall vectorcall_indirect_vec( } // X32: define dso_local x86_vectorcallcc void @"\01vectorcall_indirect_vec@@{{[0-9]+}}" -// X32-SAME: (double inreg noundef %xmm0, -// X32-SAME: double inreg noundef %xmm1, -// X32-SAME: double inreg noundef %xmm2, -// X32-SAME: double inreg noundef %xmm3, -// X32-SAME: double inreg noundef %xmm4, -// X32-SAME: <4 x float> inreg noundef %xmm5, -// X32-SAME: <4 x float>* inreg noundef %0, -// X32-SAME: i32 inreg noundef %edx, -// X32-SAME: <4 x float>* noundef %1) +// X32-SAME: (double inreg %xmm0, +// X32-SAME: double inreg %xmm1, +// X32-SAME: double inreg %xmm2, +// X32-SAME: double inreg %xmm3, +// X32-SAME: double inreg %xmm4, +// X32-SAME: <4 x float> inreg %xmm5, +// X32-SAME: <4 x float>* inreg %0, +// X32-SAME: i32 inreg %edx, +// X32-SAME: <4 x float>* %1) #endif diff --git a/clang/test/CodeGen/vla.c b/clang/test/CodeGen/vla.c index 7ea9988536cbf7d6b9f1b72e5eaf061a82bda0a5..6d9be12c35f159c7d620e3b4afea228599b9b4e9 100644 --- a/clang/test/CodeGen/vla.c +++ b/clang/test/CodeGen/vla.c @@ -57,20 +57,20 @@ void function(short width, int data[][width]) {} // expected-note {{passing argu void test() { int bork[4][13]; - // CHECK: call void @function(i16 noundef signext 1, i32* noundef null) + // CHECK: call void @function(i16 signext 1, i32* null) function(1, 0); - // CHECK: call void @function(i16 noundef signext 1, i32* noundef inttoptr + // CHECK: call void @function(i16 signext 1, i32* inttoptr function(1, 0xbadbeef); // expected-warning {{incompatible integer to pointer conversion passing}} - // CHECK: call void @function(i16 noundef signext 1, i32* noundef {{.*}}) + // CHECK: call void @function(i16 signext 1, i32* {{.*}}) function(1, bork); } void function1(short width, int data[][width][width]) {} void test1() { int bork[4][13][15]; - // CHECK: call void @function1(i16 noundef signext 1, i32* noundef {{.*}}) + // CHECK: call void @function1(i16 signext 1, i32* {{.*}}) function1(1, bork); - // CHECK: call void @function(i16 noundef signext 1, i32* noundef {{.*}}) + // CHECK: call void @function(i16 signext 1, i32* {{.*}}) function(1, bork[2]); } @@ -194,22 +194,22 @@ void test6(void) // Follow gcc's behavior for VLAs in parameter lists. PR9559. void test7(int a[b(0)]) { // CHECK-LABEL: define{{.*}} void @test7( - // CHECK: call i32 @b(i8* noundef null) + // CHECK: call i32 @b(i8* null) } // Make sure we emit dereferenceable or nonnull when the static keyword is // provided. void test8(int a[static 3]) { } -// CHECK: define{{.*}} void @test8(i32* noundef align 4 dereferenceable(12) %a) +// CHECK: define{{.*}} void @test8(i32* align 4 dereferenceable(12) %a) void test9(int n, int a[static n]) { } -// NULL-INVALID: define{{.*}} void @test9(i32 noundef %n, i32* noundef nonnull align 4 %a) -// NULL-VALID: define{{.*}} void @test9(i32 noundef %n, i32* noundef align 4 %a) +// NULL-INVALID: define{{.*}} void @test9(i32 %n, i32* nonnull align 4 %a) +// NULL-VALID: define{{.*}} void @test9(i32 %n, i32* align 4 %a) // Make sure a zero-sized static array extent is still required to be nonnull. void test10(int a[static 0]) {} -// NULL-INVALID: define{{.*}} void @test10(i32* noundef nonnull align 4 %a) -// NULL-VALID: define{{.*}} void @test10(i32* noundef align 4 %a) +// NULL-INVALID: define{{.*}} void @test10(i32* nonnull align 4 %a) +// NULL-VALID: define{{.*}} void @test10(i32* align 4 %a) const int constant = 32; // CHECK: define {{.*}}pr44406( diff --git a/clang/test/CodeGen/win64-i128.c b/clang/test/CodeGen/win64-i128.c index 0adf617f9da1d666158e4d48ece1d205e3fbd12a..fe32c57e99cf2c4c88ebeb0a9d2a95c739aa859f 100644 --- a/clang/test/CodeGen/win64-i128.c +++ b/clang/test/CodeGen/win64-i128.c @@ -12,8 +12,8 @@ int128_t foo() { return 0; } int128_t bar(int128_t a, int128_t b) { return a * b; } -// GNU64: define dso_local <2 x i64> @bar(i128* noundef %0, i128* noundef %1) -// MSC64: define dso_local <2 x i64> @bar(i128* noundef %0, i128* noundef %1) +// GNU64: define dso_local <2 x i64> @bar(i128* %0, i128* %1) +// MSC64: define dso_local <2 x i64> @bar(i128* %0, i128* %1) void vararg(int a, ...) { // GNU64-LABEL: define{{.*}} void @vararg diff --git a/clang/test/CodeGen/windows-itanium.c b/clang/test/CodeGen/windows-itanium.c index 09613e19c125ea79d44ed8fbf04f395c722f3284..5bcd6dc710c1c01ad5c5b91345f939827f2927fa 100644 --- a/clang/test/CodeGen/windows-itanium.c +++ b/clang/test/CodeGen/windows-itanium.c @@ -9,7 +9,7 @@ int function() { } // CHECK-C: define dso_local i32 @function() {{.*}} { -// CHECK-CXX: define dso_local noundef i32 @_Z8functionv() {{.*}} { +// CHECK-CXX: define dso_local i32 @_Z8functionv() {{.*}} { // CHECK: ret i32 32 // CHECK: } diff --git a/clang/test/CodeGen/windows-on-arm-dllimport-dllexport.c b/clang/test/CodeGen/windows-on-arm-dllimport-dllexport.c index 47f7f990634504fd5634a6abca15ce6a0ad81af9..f2c5ff94ffae60192076672e64d299bc8d62acae 100644 --- a/clang/test/CodeGen/windows-on-arm-dllimport-dllexport.c +++ b/clang/test/CodeGen/windows-on-arm-dllimport-dllexport.c @@ -21,5 +21,5 @@ void call_imported_function() { // CHECK: define dso_local dllexport arm_aapcs_vfpcc void @export_implemented_function() -// CHECK: declare dllimport arm_aapcs_vfpcc void @import_function(i32 noundef) +// CHECK: declare dllimport arm_aapcs_vfpcc void @import_function(i32) diff --git a/clang/test/CodeGen/windows-seh-EHa-CppCatchDotDotDot.cpp b/clang/test/CodeGen/windows-seh-EHa-CppCatchDotDotDot.cpp index 8c4ede0efbcf186b71dfd5c59d55647bdfedea1f..efa574b2323d4a93dca2737f3333a331e6ae8c4c 100644 --- a/clang/test/CodeGen/windows-seh-EHa-CppCatchDotDotDot.cpp +++ b/clang/test/CodeGen/windows-seh-EHa-CppCatchDotDotDot.cpp @@ -11,7 +11,7 @@ // CHECK: invoke void @llvm.seh.try.begin() // CHECK: %[[src:[0-9-]+]] = load volatile i32, i32* %i -// CHECK-NEXT: invoke void @"?crash@@YAXH@Z"(i32 noundef %[[src]]) +// CHECK-NEXT: invoke void @"?crash@@YAXH@Z"(i32 %[[src]]) // CHECK: invoke void @llvm.seh.try.end() // ***************************************************************************** diff --git a/clang/test/CodeGen/windows-seh-EHa-CppCondiTemps.cpp b/clang/test/CodeGen/windows-seh-EHa-CppCondiTemps.cpp index 2ff76edfbe3aeae0dd9151b689800a40408833e7..b6a2acad4e9d9191896c1c5a7cd90c7fd6067433 100644 --- a/clang/test/CodeGen/windows-seh-EHa-CppCondiTemps.cpp +++ b/clang/test/CodeGen/windows-seh-EHa-CppCondiTemps.cpp @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -triple x86_64-windows -fasync-exceptions -fcxx-exceptions -fexceptions -fms-extensions -x c++ -Wno-implicit-function-declaration -S -emit-llvm %s -o - | FileCheck %s -// CHECK: define dso_local noundef i32 @"?bar@@YAHHVB1@@VB2@@@Z" +// CHECK: define dso_local i32 @"?bar@@YAHHVB1@@VB2@@@Z" // CHECK: %coerce.dive1 = getelementptr inbounds %class.B2 // CHECK: %coerce.dive2 = getelementptr inbounds %class.B1 // ----- scope begin of two passed-by-value temps @@ -19,14 +19,14 @@ // CHECK: call void @"??1B1@@QEAA@XZ" // CHECK: define dso_local void @"?goo@@YA?AVB1@@H@Z" -// CHECK: call noundef %class.B2* @"??0B2@@QEAA@XZ"(%class.B2* +// CHECK: call %class.B2* @"??0B2@@QEAA@XZ"(%class.B2* // CHECK: invoke void @llvm.seh.scope.begin() // check: call void @llvm.memcpy // CHECK: invoke void @llvm.seh.scope.end() // CHECK: call void @"??1B2@@QEAA@XZ"(%class.B2* -// CHECK: define linkonce_odr dso_local noundef %class.B2* @"??0B2@@QEAA@XZ" -// CHECK: call noundef %class.B1* @"??0B1@@QEAA@XZ"(%class.B1* +// CHECK: define linkonce_odr dso_local %class.B2* @"??0B2@@QEAA@XZ" +// CHECK: call %class.B1* @"??0B1@@QEAA@XZ"(%class.B1* // ----- scope begin of base ctor // CHECK: invoke void @llvm.seh.scope.begin() // CHECK: invoke void @llvm.seh.scope.end() @@ -79,12 +79,12 @@ class B1 goo(int w) return b2ingoo; } -// CHECK: define dso_local noundef i32 @main() +// CHECK: define dso_local i32 @main() // CHECK: invoke void @llvm.seh.scope.begin() // --- beginning of conditional temp test -// CHECK: invoke noundef %class.B2* @"??0B2@@QEAA@XZ" +// CHECK: invoke %class.B2* @"??0B2@@QEAA@XZ" // CHECK: invoke void @llvm.seh.scope.begin() -// CHECK: invoke noundef %class.B3* @"??0B3@@QEAA@XZ" +// CHECK: invoke %class.B3* @"??0B3@@QEAA@XZ" // CHECK: invoke void @llvm.seh.scope.begin() // CHECK: invoke void @llvm.seh.scope.end() // CHECK: call void @"??1B3@@QEAA@XZ" @@ -96,12 +96,12 @@ class B1 goo(int w) // setting scope in case exception occurs before the call // check: invoke %class.B2* @"??0B2@@QEAA@XZ" // CHECK: invoke void @llvm.seh.scope.begin() -// CHECK: invoke noundef %class.B1* @"??0B1@@QEAA@XZ" +// CHECK: invoke %class.B1* @"??0B1@@QEAA@XZ" // CHECK: invoke void @llvm.seh.scope.begin() // ----- end of temps' scope right before callee // CHECK: invoke void @llvm.seh.scope.end() // CHECK: invoke void @llvm.seh.scope.end() -// CHECK: invoke noundef i32 @"?bar@@YAHHVB1@@VB2@@@Z" +// CHECK: invoke i32 @"?bar@@YAHHVB1@@VB2@@@Z" // ----- testing caller's return-by-value temp // scope begins right after callee which is the ctor of return temp diff --git a/clang/test/CodeGen/windows-seh-EHa-CppDtors01.cpp b/clang/test/CodeGen/windows-seh-EHa-CppDtors01.cpp index 8e762b44d4d52e5f623ca04bf97739f5e08f8933..47117b4a961330b6df9fd597c815e933d616962f 100644 --- a/clang/test/CodeGen/windows-seh-EHa-CppDtors01.cpp +++ b/clang/test/CodeGen/windows-seh-EHa-CppDtors01.cpp @@ -9,7 +9,7 @@ // CHECK: invoke void @llvm.seh.try.begin() // CHECK: %[[src:[0-9-]+]] = load volatile i32, i32* %i -// CHECK-NEXT: invoke void @"?crash@@YAXH@Z"(i32 noundef %[[src]]) +// CHECK-NEXT: invoke void @"?crash@@YAXH@Z"(i32 %[[src]]) // CHECK: invoke void @llvm.seh.try.end() // **************************************************************************** diff --git a/clang/test/CodeGen/windows-seh-EHa-TryInFinally.cpp b/clang/test/CodeGen/windows-seh-EHa-TryInFinally.cpp index ad0244bb8dc2a5245d7644eda29bfb0563c113ce..aa605702a57c3a22f230b6b88c35d6afdf1622c4 100644 --- a/clang/test/CodeGen/windows-seh-EHa-TryInFinally.cpp +++ b/clang/test/CodeGen/windows-seh-EHa-TryInFinally.cpp @@ -3,11 +3,11 @@ // CHECK: invoke void @llvm.seh.try.begin() // CHECK: invoke void @llvm.seh.try.begin() // CHECK: %[[src:[0-9-]+]] = load volatile i32, i32* %i -// CHECK-NEXT: i32 noundef %[[src]] +// CHECK-NEXT: i32 %[[src]] // CHECK: invoke void @llvm.seh.try.end() // CHECK: invoke void @llvm.seh.try.end() -// CHECK: define internal void @"?fin$0@0@main@@"(i8 noundef %abnormal_termination +// CHECK: define internal void @"?fin$0@0@main@@"(i8 %abnormal_termination // CHECK: invoke void @llvm.seh.try.begin() // CHECK: invoke void @llvm.seh.try.end() diff --git a/clang/test/CodeGen/windows-seh-abnormal-exits.c b/clang/test/CodeGen/windows-seh-abnormal-exits.c index 2e994aa6c49e1cbe54686dd30d763a2e29cd87a5..971e4f008a4121b9ef5113b86500c360ae770e41 100644 --- a/clang/test/CodeGen/windows-seh-abnormal-exits.c +++ b/clang/test/CodeGen/windows-seh-abnormal-exits.c @@ -4,7 +4,7 @@ // CHECK-NEXT: %cleanup.dest = load i32, i32* %cleanup.dest.slot, align 4 // CHECK-NEXT: %[[src2:[0-9-]+]] = icmp ne i32 %cleanup.dest, 0 // CHECK-NEXT: %[[src3:[0-9-]+]] = zext i1 %[[src2]] to i8 -// CHECK-NEXT: call void @"?fin$0@0@seh_abnormal_exits@@"(i8 noundef %[[src3]], i8* noundef %[[src]]) +// CHECK-NEXT: call void @"?fin$0@0@seh_abnormal_exits@@"(i8 %[[src3]], i8* %[[src]]) void seh_abnormal_exits(int *Counter) { for (int i = 0; i < 5; i++) { diff --git a/clang/test/CodeGen/windows-swiftcall.c b/clang/test/CodeGen/windows-swiftcall.c index ce563676c735280f5948411de5483a53aed7145e..9a570f0b9e95b886a8276022aac5f184d0509814 100644 --- a/clang/test/CodeGen/windows-swiftcall.c +++ b/clang/test/CodeGen/windows-swiftcall.c @@ -12,24 +12,24 @@ /*****************************************************************************/ SWIFTCALL void indirect_result_1(OUT int *arg0, OUT float *arg1) {} -// CHECK-LABEL: define {{.*}} void @indirect_result_1(i32* noalias noundef sret(i32*) align 4 dereferenceable(4){{.*}}, float* noalias noundef align 4 dereferenceable(4){{.*}}) +// CHECK-LABEL: define {{.*}} void @indirect_result_1(i32* noalias sret(i32*) align 4 dereferenceable(4){{.*}}, float* noalias align 4 dereferenceable(4){{.*}}) // TODO: maybe this shouldn't suppress sret. SWIFTCALL int indirect_result_2(OUT int *arg0, OUT float *arg1) { __builtin_unreachable(); } -// CHECK-LABEL: define {{.*}} i32 @indirect_result_2(i32* noalias noundef align 4 dereferenceable(4){{.*}}, float* noalias noundef align 4 dereferenceable(4){{.*}}) +// CHECK-LABEL: define {{.*}} i32 @indirect_result_2(i32* noalias align 4 dereferenceable(4){{.*}}, float* noalias align 4 dereferenceable(4){{.*}}) typedef struct { char array[1024]; } struct_reallybig; SWIFTCALL struct_reallybig indirect_result_3(OUT int *arg0, OUT float *arg1) { __builtin_unreachable(); } -// CHECK-LABEL: define {{.*}} void @indirect_result_3({{.*}}* noalias sret({{.*}}) {{.*}}, i32* noalias noundef align 4 dereferenceable(4){{.*}}, float* noalias noundef align 4 dereferenceable(4){{.*}}) +// CHECK-LABEL: define {{.*}} void @indirect_result_3({{.*}}* noalias sret({{.*}}) {{.*}}, i32* noalias align 4 dereferenceable(4){{.*}}, float* noalias align 4 dereferenceable(4){{.*}}) SWIFTCALL void context_1(CONTEXT void *self) {} -// CHECK-LABEL: define {{.*}} void @context_1(i8* noundef swiftself +// CHECK-LABEL: define {{.*}} void @context_1(i8* swiftself SWIFTCALL void context_2(void *arg0, CONTEXT void *self) {} -// CHECK-LABEL: define {{.*}} void @context_2(i8*{{.*}}, i8* noundef swiftself +// CHECK-LABEL: define {{.*}} void @context_2(i8*{{.*}}, i8* swiftself SWIFTCALL void context_error_1(CONTEXT int *self, ERROR float **error) {} -// CHECK-LABEL: define {{.*}} void @context_error_1(i32* noundef swiftself{{.*}}, float** noundef swifterror %0) +// CHECK-LABEL: define {{.*}} void @context_error_1(i32* swiftself{{.*}}, float** swifterror %0) // CHECK: [[TEMP:%.*]] = alloca float*, align 8 // CHECK: [[T0:%.*]] = load float*, float** [[ERRORARG:%.*]], align 8 // CHECK: store float* [[T0]], float** [[TEMP]], align 8 @@ -46,12 +46,12 @@ void test_context_error_1() { // CHECK: [[TEMP:%.*]] = alloca swifterror float*, align 8 // CHECK: [[T0:%.*]] = load float*, float** [[ERROR]], align 8 // CHECK: store float* [[T0]], float** [[TEMP]], align 8 -// CHECK: call [[SWIFTCC:swiftcc]] void @context_error_1(i32* noundef swiftself [[X]], float** noundef swifterror [[TEMP]]) +// CHECK: call [[SWIFTCC:swiftcc]] void @context_error_1(i32* swiftself [[X]], float** swifterror [[TEMP]]) // CHECK: [[T0:%.*]] = load float*, float** [[TEMP]], align 8 // CHECK: store float* [[T0]], float** [[ERROR]], align 8 SWIFTCALL void context_error_2(short s, CONTEXT int *self, ERROR float **error) {} -// CHECK-LABEL: define {{.*}} void @context_error_2(i16{{.*}}, i32* noundef swiftself{{.*}}, float** noundef swifterror %0) +// CHECK-LABEL: define {{.*}} void @context_error_2(i16{{.*}}, i32* swiftself{{.*}}, float** swifterror %0) /*****************************************************************************/ /********************************** LOWERING *********************************/ @@ -235,7 +235,7 @@ TEST(struct_big_1) // CHECK-LABEL: define {{.*}} void @return_struct_big_1({{.*}} noalias sret // Should not be byval. -// CHECK-LABEL: define {{.*}} void @take_struct_big_1({{.*}}* noundef{{( %.*)?}}) +// CHECK-LABEL: define {{.*}} void @take_struct_big_1({{.*}}*{{( %.*)?}}) /*****************************************************************************/ /********************************* TYPE MERGING ******************************/ @@ -378,7 +378,7 @@ TEST(int8) // CHECK: [[T0:%.*]] = insertvalue [[UAGG:{ <4 x i32>, <4 x i32> }]] undef, <4 x i32> [[FIRST]], 0 // CHECK: [[T1:%.*]] = insertvalue [[UAGG]] [[T0]], <4 x i32> [[SECOND]], 1 // CHECK: ret [[UAGG]] [[T1]] -// CHECK-LABEL: define {{.*}} @take_int8(<4 x i32> noundef %0, <4 x i32> noundef %1) +// CHECK-LABEL: define {{.*}} @take_int8(<4 x i32> %0, <4 x i32> %1) // CHECK: [[V:%.*]] = alloca [[REC]], align // CHECK: [[CAST_TMP:%.*]] = bitcast [[REC]]* [[V]] to [[AGG]]* // CHECK: [[T0:%.*]] = getelementptr inbounds [[AGG]], [[AGG]]* [[CAST_TMP]], i32 0, i32 0 @@ -404,7 +404,7 @@ TEST(int8) // CHECK: [[FIRST:%.*]] = load <4 x i32>, <4 x i32>* [[T0]], align // CHECK: [[T0:%.*]] = getelementptr inbounds [[AGG]], [[AGG]]* [[CAST_TMP]], i32 0, i32 1 // CHECK: [[SECOND:%.*]] = load <4 x i32>, <4 x i32>* [[T0]], align -// CHECK: call [[SWIFTCC]] void @take_int8(<4 x i32> noundef [[FIRST]], <4 x i32> noundef [[SECOND]]) +// CHECK: call [[SWIFTCC]] void @take_int8(<4 x i32> [[FIRST]], <4 x i32> [[SECOND]]) // CHECK: ret void TEST(int5) diff --git a/clang/test/CodeGen/x86_32-align-linux.c b/clang/test/CodeGen/x86_32-align-linux.c index 771ee661061c187fca75398af0a0f5a921296dfc..df864588ae683b58c150ee4b3cbdb9fe4216cbc7 100644 --- a/clang/test/CodeGen/x86_32-align-linux.c +++ b/clang/test/CodeGen/x86_32-align-linux.c @@ -50,9 +50,9 @@ void testm512(int argCount, ...) { } // CHECK-LABEL: define dso_local void @testPastArguments -// CHECK: call void (i32, ...) @testm128(i32 noundef 1, <4 x float> noundef %0) -// CHECK: call void (i32, ...) @testm256(i32 noundef 1, <8 x float> noundef %1) -// CHECK: call void (i32, ...) @testm512(i32 noundef 1, <16 x float> noundef %2) +// CHECK: call void (i32, ...) @testm128(i32 1, <4 x float> %0) +// CHECK: call void (i32, ...) @testm256(i32 1, <8 x float> %1) +// CHECK: call void (i32, ...) @testm512(i32 1, <16 x float> %2) void testPastArguments(void) { __m128 a; __m256 b; diff --git a/clang/test/CodeGen/xcore-abi.c b/clang/test/CodeGen/xcore-abi.c index feb53b7f096c7a51987bdca9bf93f03070f3902e..4446aa13e515262ed95295181ef733cf7f1224a3 100644 --- a/clang/test/CodeGen/xcore-abi.c +++ b/clang/test/CodeGen/xcore-abi.c @@ -38,7 +38,7 @@ void testva (int n, ...) { // CHECK: [[V1:%[a-z0-9]+]] = load i8*, i8** [[P]] // CHECK: store i8* [[V1]], i8** [[V:%[a-z0-9]+]], align 4 // CHECK: [[V2:%[a-z0-9]+]] = load i8*, i8** [[V]], align 4 - // CHECK: call void @f(i8* noundef [[V2]]) + // CHECK: call void @f(i8* [[V2]]) char v2 = va_arg (ap, char); // expected-warning{{second argument to 'va_arg' is of promotable type 'char'}} f(&v2); @@ -47,7 +47,7 @@ void testva (int n, ...) { // CHECK: store i8* [[IN]], i8** [[AP]] // CHECK: [[V1:%[a-z0-9]+]] = load i8, i8* [[I]] // CHECK: store i8 [[V1]], i8* [[V:%[a-z0-9]+]], align 1 - // CHECK: call void @f(i8* noundef [[V]]) + // CHECK: call void @f(i8* [[V]]) int v3 = va_arg (ap, int); f(&v3); @@ -58,7 +58,7 @@ void testva (int n, ...) { // CHECK: [[V1:%[a-z0-9]+]] = load i32, i32* [[P]] // CHECK: store i32 [[V1]], i32* [[V:%[a-z0-9]+]], align 4 // CHECK: [[V2:%[a-z0-9]+]] = bitcast i32* [[V]] to i8* - // CHECK: call void @f(i8* noundef [[V2]]) + // CHECK: call void @f(i8* [[V2]]) long long int v4 = va_arg (ap, long long int); f(&v4); @@ -69,7 +69,7 @@ void testva (int n, ...) { // CHECK: [[V1:%[a-z0-9]+]] = load i64, i64* [[P]] // CHECK: store i64 [[V1]], i64* [[V:%[a-z0-9]+]], align 4 // CHECK:[[V2:%[a-z0-9]+]] = bitcast i64* [[V]] to i8* - // CHECK: call void @f(i8* noundef [[V2]]) + // CHECK: call void @f(i8* [[V2]]) struct x v5 = va_arg (ap, struct x); // typical aggregate type f(&v5); @@ -82,7 +82,7 @@ void testva (int n, ...) { // CHECK: [[P1:%[a-z0-9]+]] = bitcast %struct.x* [[P]] to i8* // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[V1]], i8* align 4 [[P1]], i32 20, i1 false) // CHECK: [[V2:%[a-z0-9]+]] = bitcast %struct.x* [[V]] to i8* - // CHECK: call void @f(i8* noundef [[V2]]) + // CHECK: call void @f(i8* [[V2]]) int* v6 = va_arg (ap, int[4]); // an unusual aggregate type f(v6); @@ -98,7 +98,7 @@ void testva (int n, ...) { // CHECK: store i32* [[V2]], i32** [[V:%[a-z0-9]+]], align 4 // CHECK: [[V3:%[a-z0-9]+]] = load i32*, i32** [[V]], align 4 // CHECK: [[V4:%[a-z0-9]+]] = bitcast i32* [[V3]] to i8* - // CHECK: call void @f(i8* noundef [[V4]]) + // CHECK: call void @f(i8* [[V4]]) double v7 = va_arg (ap, double); f(&v7); @@ -109,7 +109,7 @@ void testva (int n, ...) { // CHECK: [[V1:%[a-z0-9]+]] = load double, double* [[P]] // CHECK: store double [[V1]], double* [[V:%[a-z0-9]+]], align 4 // CHECK: [[V2:%[a-z0-9]+]] = bitcast double* [[V]] to i8* - // CHECK: call void @f(i8* noundef [[V2]]) + // CHECK: call void @f(i8* [[V2]]) } void testbuiltin (void) { diff --git a/clang/test/CodeGen/xray-log-args.cpp b/clang/test/CodeGen/xray-log-args.cpp index 1e1e7b51524e1638e14d65b65fdd5e3ccea18a4c..9efeda0111c72a4feb4c09e4e279853c0a4093db 100644 --- a/clang/test/CodeGen/xray-log-args.cpp +++ b/clang/test/CodeGen/xray-log-args.cpp @@ -2,11 +2,11 @@ // Make sure that the LLVM attribute for XRay-annotated functions do show up. [[clang::xray_always_instrument,clang::xray_log_args(1)]] void foo(int a) { -// CHECK: define{{.*}} void @_Z3fooi(i32 noundef %a) #0 +// CHECK: define{{.*}} void @_Z3fooi(i32 %a) #0 }; [[clang::xray_log_args(1)]] void bar(int a) { -// CHECK: define{{.*}} void @_Z3bari(i32 noundef %a) #1 +// CHECK: define{{.*}} void @_Z3bari(i32 %a) #1 }; // CHECK: #0 = {{.*}}"function-instrument"="xray-always"{{.*}}"xray-log-args"="1" diff --git a/clang/test/CodeGenCUDA/address-spaces.cu b/clang/test/CodeGenCUDA/address-spaces.cu index 94e3352d42c2b39eda6c37cefe11666ad140a3c2..24f1317e8c7a67c5c2e4cc4fc31e6560d82cff2a 100644 --- a/clang/test/CodeGenCUDA/address-spaces.cu +++ b/clang/test/CodeGenCUDA/address-spaces.cu @@ -60,7 +60,7 @@ __device__ void func1() { callee(&a); // implicit cast from parameters } // CHECK: define{{.*}} void @_Z5func1v() -// CHECK: call void @_Z6calleePf(float* noundef addrspacecast (float addrspace(3)* @_ZZ5func1vE1a to float*)) +// CHECK: call void @_Z6calleePf(float* addrspacecast (float addrspace(3)* @_ZZ5func1vE1a to float*)) __device__ void func2() { __shared__ float a[256]; diff --git a/clang/test/CodeGenCUDA/amdgpu-alias-undef-symbols.cu b/clang/test/CodeGenCUDA/amdgpu-alias-undef-symbols.cu new file mode 100644 index 0000000000000000000000000000000000000000..ec7b7c3b7ff4c5a501dd21a9869732d21d8cc7c4 --- /dev/null +++ b/clang/test/CodeGenCUDA/amdgpu-alias-undef-symbols.cu @@ -0,0 +1,17 @@ +// REQUIRES: amdgpu-registered-target, clang-driver + +// RUN: %clang -target x86_64-unknown-linux-gnu --offload-arch=gfx906 --cuda-device-only -nogpulib -nogpuinc -x hip -emit-llvm -S -o - %s \ +// RUN: -fgpu-rdc -O3 -mllvm -amdgpu-early-inline-all=true -mllvm -amdgpu-function-calls=false | \ +// RUN: FileCheck %s + +#include "Inputs/cuda.h" + +// CHECK: %struct.B = type { i8 } +struct B { + + // CHECK: @_ZN1BC1Ei = hidden unnamed_addr alias void (%struct.B*, i32), void (%struct.B*, i32)* @_ZN1BC2Ei + __device__ B(int x); +}; + +__device__ B::B(int x) { +} diff --git a/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu b/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu index d483803005074f987c01beb9cafab345a35e249f..2dcab7c86d5d587952563a851e15f986e150fb25 100644 --- a/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu +++ b/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu @@ -14,7 +14,7 @@ // HOST-NOT: %struct.S.coerce // HOST-NOT: %struct.T.coerce -// HOST: define{{.*}} void @_Z22__device_stub__kernel1Pi(i32* noundef %x) +// HOST: define{{.*}} void @_Z22__device_stub__kernel1Pi(i32* %x) // COMMON-LABEL: define{{.*}} amdgpu_kernel void @_Z7kernel1Pi(i32 addrspace(1)*{{.*}} %x.coerce) // CHECK: ={{.*}} addrspacecast [[TYPE:.*]] addrspace(1)* %{{.*}} to [[TYPE]]* // CHECK-NOT: ={{.*}} addrspacecast [[TYPE:.*]] addrspace(1)* %{{.*}} to [[TYPE]]* @@ -26,7 +26,7 @@ __global__ void kernel1(int *x) { x[0]++; } -// HOST: define{{.*}} void @_Z22__device_stub__kernel2Ri(i32* noundef nonnull align 4 dereferenceable(4) %x) +// HOST: define{{.*}} void @_Z22__device_stub__kernel2Ri(i32* nonnull align 4 dereferenceable(4) %x) // COMMON-LABEL: define{{.*}} amdgpu_kernel void @_Z7kernel2Ri(i32 addrspace(1)*{{.*}} nonnull align 4 dereferenceable(4) %x.coerce) // CHECK: ={{.*}} addrspacecast [[TYPE:.*]] addrspace(1)* %{{.*}} to [[TYPE]]* // CHECK-NOT: ={{.*}} addrspacecast [[TYPE:.*]] addrspace(1)* %{{.*}} to [[TYPE]]* @@ -38,7 +38,7 @@ __global__ void kernel2(int &x) { x++; } -// HOST: define{{.*}} void @_Z22__device_stub__kernel3PU3AS2iPU3AS1i(i32 addrspace(2)* noundef %x, i32 addrspace(1)* noundef %y) +// HOST: define{{.*}} void @_Z22__device_stub__kernel3PU3AS2iPU3AS1i(i32 addrspace(2)* %x, i32 addrspace(1)* %y) // CHECK-LABEL: define{{.*}} amdgpu_kernel void @_Z7kernel3PU3AS2iPU3AS1i(i32 addrspace(2)*{{.*}} %x, i32 addrspace(1)*{{.*}} %y) // CHECK-NOT: ={{.*}} addrspacecast [[TYPE:.*]] addrspace(1)* %{{.*}} to [[TYPE]]* __global__ void kernel3(__attribute__((address_space(2))) int *x, @@ -81,7 +81,7 @@ __global__ void kernel4(struct S s) { } // If a pointer to struct is passed, only the pointer itself is coerced into the global one. -// HOST: define{{.*}} void @_Z22__device_stub__kernel5P1S(%struct.S* noundef %s) +// HOST: define{{.*}} void @_Z22__device_stub__kernel5P1S(%struct.S* %s) // COMMON-LABEL: define{{.*}} amdgpu_kernel void @_Z7kernel5P1S(%struct.S addrspace(1)*{{.*}} %s.coerce) __global__ void kernel5(struct S *s) { s->x[0]++; @@ -116,7 +116,7 @@ __global__ void kernel6(struct T t) { } // Check that coerced pointers retain the noalias attribute when qualified with __restrict. -// HOST: define{{.*}} void @_Z22__device_stub__kernel7Pi(i32* noalias noundef %x) +// HOST: define{{.*}} void @_Z22__device_stub__kernel7Pi(i32* noalias %x) // COMMON-LABEL: define{{.*}} amdgpu_kernel void @_Z7kernel7Pi(i32 addrspace(1)* noalias{{.*}} %x.coerce) __global__ void kernel7(int *__restrict x) { x[0]++; diff --git a/clang/test/CodeGenCUDA/builtins-amdgcn.cu b/clang/test/CodeGenCUDA/builtins-amdgcn.cu index 3d467ebe2e29c747480ef155a6a9d54637a6b837..6ba606b4e82c250ef92f2f4a64d33044fbf742d9 100644 --- a/clang/test/CodeGenCUDA/builtins-amdgcn.cu +++ b/clang/test/CodeGenCUDA/builtins-amdgcn.cu @@ -194,7 +194,7 @@ __device__ void func(float *x); // CHECK-NEXT: [[TMP4:%.*]] = call contract float @llvm.amdgcn.ds.fmin.f32(float addrspace(3)* [[TMP2]], float [[TMP3]], i32 0, i32 0, i1 false) // CHECK-NEXT: store volatile float [[TMP4]], float* [[X_ASCAST]], align 4 // CHECK-NEXT: [[TMP5:%.*]] = load float*, float** [[SHARED_ADDR_ASCAST]], align 8 -// CHECK-NEXT: call void @_Z4funcPf(float* noundef [[TMP5]]) #[[ATTR8:[0-9]+]] +// CHECK-NEXT: call void @_Z4funcPf(float* [[TMP5]]) #[[ATTR8:[0-9]+]] // CHECK-NEXT: ret void // __global__ void test_ds_fmin_func(float src, float *__restrict shared) { diff --git a/clang/test/CodeGenCUDA/cuda-builtin-vars.cu b/clang/test/CodeGenCUDA/cuda-builtin-vars.cu index b7b484d47b416c4968e8a52a2433d7abadf1199a..9446619a71f7e9099e19459390ff0ebfa6beb4bd 100644 --- a/clang/test/CodeGenCUDA/cuda-builtin-vars.cu +++ b/clang/test/CodeGenCUDA/cuda-builtin-vars.cu @@ -2,7 +2,7 @@ #include "__clang_cuda_builtin_vars.h" -// CHECK: define{{.*}} void @_Z6kernelPi(i32* noundef %out) +// CHECK: define{{.*}} void @_Z6kernelPi(i32* %out) __attribute__((global)) void kernel(int *out) { int i = 0; diff --git a/clang/test/CodeGenCUDA/kernel-args-alignment.cu b/clang/test/CodeGenCUDA/kernel-args-alignment.cu index 6c5689b4a542545ba268360bb2561b73ceb7c4bb..2bfd098a8540a39b55e7d4deffd1ef67c78d62d5 100644 --- a/clang/test/CodeGenCUDA/kernel-args-alignment.cu +++ b/clang/test/CodeGenCUDA/kernel-args-alignment.cu @@ -36,5 +36,5 @@ static_assert(alignof(S) == 8, "Unexpected alignment."); // HOST-OLD: call i32 @cudaSetupArgument({{[^,]*}}, i64 8, i64 24) // DEVICE-LABEL: @_Z6kernelc1SPi -// DEVICE-SAME: i8{{[^,]*}}, %struct.S* noundef byval(%struct.S) align 8{{[^,]*}}, i32* +// DEVICE-SAME: i8{{[^,]*}}, %struct.S* byval(%struct.S) align 8{{[^,]*}}, i32* __global__ void kernel(char a, S s, int *b) {} diff --git a/clang/test/CodeGenCUDA/kernel-args.cu b/clang/test/CodeGenCUDA/kernel-args.cu index 5f725132496e878036088d60942300c7290265f8..60a2c87db2be4e0d23bbbbb72402d959a52f9b65 100644 --- a/clang/test/CodeGenCUDA/kernel-args.cu +++ b/clang/test/CodeGenCUDA/kernel-args.cu @@ -10,14 +10,14 @@ struct A { }; // AMDGCN: define{{.*}} amdgpu_kernel void @_Z6kernel1A(%struct.A addrspace(4)* byref(%struct.A) align 8 %{{.+}}) -// NVPTX: define{{.*}} void @_Z6kernel1A(%struct.A* noundef byval(%struct.A) align 8 %x) +// NVPTX: define{{.*}} void @_Z6kernel1A(%struct.A* byval(%struct.A) align 8 %x) __global__ void kernel(A x) { } class Kernel { public: // AMDGCN: define{{.*}} amdgpu_kernel void @_ZN6Kernel12memberKernelE1A(%struct.A addrspace(4)* byref(%struct.A) align 8 %{{.+}}) - // NVPTX: define{{.*}} void @_ZN6Kernel12memberKernelE1A(%struct.A* noundef byval(%struct.A) align 8 %x) + // NVPTX: define{{.*}} void @_ZN6Kernel12memberKernelE1A(%struct.A* byval(%struct.A) align 8 %x) static __global__ void memberKernel(A x){} template static __global__ void templateMemberKernel(T x) {} }; @@ -31,10 +31,10 @@ void launch(void*); void test() { Kernel K; // AMDGCN: define{{.*}} amdgpu_kernel void @_Z14templateKernelI1AEvT_(%struct.A addrspace(4)* byref(%struct.A) align 8 %{{.+}} - // NVPTX: define{{.*}} void @_Z14templateKernelI1AEvT_(%struct.A* noundef byval(%struct.A) align 8 %x) + // NVPTX: define{{.*}} void @_Z14templateKernelI1AEvT_(%struct.A* byval(%struct.A) align 8 %x) launch((void*)templateKernel); // AMDGCN: define{{.*}} amdgpu_kernel void @_ZN6Kernel20templateMemberKernelI1AEEvT_(%struct.A addrspace(4)* byref(%struct.A) align 8 %{{.+}} - // NVPTX: define{{.*}} void @_ZN6Kernel20templateMemberKernelI1AEEvT_(%struct.A* noundef byval(%struct.A) align 8 %x) + // NVPTX: define{{.*}} void @_ZN6Kernel20templateMemberKernelI1AEEvT_(%struct.A* byval(%struct.A) align 8 %x) launch((void*)Kernel::templateMemberKernel); } diff --git a/clang/test/CodeGenCUDA/kernel-stub-name.cu b/clang/test/CodeGenCUDA/kernel-stub-name.cu index 8c642dc9461412272b9278222fc133d00f3ede8a..460dd6010e8350cd22906fb2fa8421557aa93258 100644 --- a/clang/test/CodeGenCUDA/kernel-stub-name.cu +++ b/clang/test/CodeGenCUDA/kernel-stub-name.cu @@ -100,7 +100,7 @@ void fun3() { // CHECK-LABEL: define{{.*}}@_Z4fun4v() // CHECK: store void ()* bitcast (void ()** @[[HCKERN]] to void ()*), void ()** @kernel_ptr -// CHECK: call noundef i32 @_Z16hipConfigureCall4dim3S_mP9hipStream +// CHECK: call i32 @_Z16hipConfigureCall4dim3S_mP9hipStream // CHECK: %[[HANDLE:.*]] = load void ()*, void ()** @kernel_ptr, align 8 // CHECK: %[[CAST:.*]] = bitcast void ()* %[[HANDLE]] to void ()** // CHECK: %[[STUB:.*]] = load void ()*, void ()** %[[CAST]], align 8 @@ -116,7 +116,7 @@ void fun4() { // CHECK: store void ()* bitcast (void ()** @[[HCKERN]] to void ()*), void ()** @kernel_ptr // CHECK: %[[HANDLE:.*]] = load void ()*, void ()** @kernel_ptr, align 8 // CHECK: %[[CAST:.*]] = bitcast void ()* %[[HANDLE]] to i8* -// CHECK: call void @_Z6launchPv(i8* noundef %[[CAST]]) +// CHECK: call void @_Z6launchPv(i8* %[[CAST]]) void fun5() { kernel_ptr = ckernel; launch((void *)kernel_ptr); diff --git a/clang/test/CodeGenCUDA/lambda.cu b/clang/test/CodeGenCUDA/lambda.cu index 363c2022d7eb28b4834b513530f9f2527ff56f38..ffe2cb4cfa6f6d486287617eb2166005c57a4cd4 100644 --- a/clang/test/CodeGenCUDA/lambda.cu +++ b/clang/test/CodeGenCUDA/lambda.cu @@ -28,8 +28,8 @@ // HOST: call void @_Z16__device_stub__gIZ12test_resolvevEUlvE_EvT_ // HOST: call void @_ZZ12test_resolvevENKUlvE_clEv // HOST-LABEL: define internal void @_ZZ12test_resolvevENKUlvE_clEv -// HOST: call noundef i32 @_Z10overloadedIiET_v -// HOST-LABEL: define linkonce_odr noundef i32 @_Z10overloadedIiET_v +// HOST: call i32 @_Z10overloadedIiET_v +// HOST-LABEL: define linkonce_odr i32 @_Z10overloadedIiET_v // HOST: ret i32 2 // Check kernel is registered with correct device side kernel name. @@ -51,8 +51,8 @@ // DEV-LABEL: define{{.*}} amdgpu_kernel void @_Z1gIZ12test_resolvevEUlvE_EvT_ // DEV: call void @_ZZ12test_resolvevENKUlvE_clEv // DEV-LABEL: define internal void @_ZZ12test_resolvevENKUlvE_clEv -// DEV: call noundef i32 @_Z10overloadedIiET_v -// DEV-LABEL: define linkonce_odr noundef i32 @_Z10overloadedIiET_v +// DEV: call i32 @_Z10overloadedIiET_v +// DEV-LABEL: define linkonce_odr i32 @_Z10overloadedIiET_v // DEV: ret i32 1 __device__ int a; diff --git a/clang/test/CodeGenCUDA/redux-builtins.cu b/clang/test/CodeGenCUDA/redux-builtins.cu index c521b8d54399dc3b1c8bc0812db427af9548c1ec..bdcd00b567f7027ed4024cbe3f888587e674eb68 100644 --- a/clang/test/CodeGenCUDA/redux-builtins.cu +++ b/clang/test/CodeGenCUDA/redux-builtins.cu @@ -1,7 +1,7 @@ // RUN: %clang_cc1 "-triple" "nvptx-nvidia-cuda" "-target-feature" "+ptx70" "-target-cpu" "sm_80" -emit-llvm -fcuda-is-device -o - %s | FileCheck %s // RUN: %clang_cc1 "-triple" "nvptx64-nvidia-cuda" "-target-feature" "+ptx70" "-target-cpu" "sm_80" -emit-llvm -fcuda-is-device -o - %s | FileCheck %s -// CHECK: define{{.*}} void @_Z6kernelPi(i32* noundef %out) +// CHECK: define{{.*}} void @_Z6kernelPi(i32* %out) __attribute__((global)) void kernel(int *out) { int a = 1; unsigned int b = 5; diff --git a/clang/test/CodeGenCUDA/surface.cu b/clang/test/CodeGenCUDA/surface.cu index 5a2de55fabe4935bce3bd5ad370bbcbcf6d1e642..eedae5473fcfcdfbb00bd583f4b203086e3a5940 100644 --- a/clang/test/CodeGenCUDA/surface.cu +++ b/clang/test/CodeGenCUDA/surface.cu @@ -27,9 +27,9 @@ surface surf; __attribute__((device)) int suld_2d_zero(surface, int, int) asm("llvm.nvvm.suld.2d.i32.zero"); -// DEVICE-LABEL: i32 @_Z3fooii(i32 noundef %x, i32 noundef %y) +// DEVICE-LABEL: i32 @_Z3fooii(i32 %x, i32 %y) // DEVICE: call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @surf) -// DEVICE: call noundef i32 @llvm.nvvm.suld.2d.i32.zero(i64 %{{.*}}, i32 noundef %{{.*}}, i32 noundef %{{.*}}) +// DEVICE: call i32 @llvm.nvvm.suld.2d.i32.zero(i64 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) __attribute__((device)) int foo(int x, int y) { return suld_2d_zero(surf, x, y); } diff --git a/clang/test/CodeGenCUDA/texture.cu b/clang/test/CodeGenCUDA/texture.cu index 031d238e507cce3f6817eb9bc4f86af14cac4cfe..0bb8cd48dcaa719658f3f6c38fd5b3650aaa0b54 100644 --- a/clang/test/CodeGenCUDA/texture.cu +++ b/clang/test/CodeGenCUDA/texture.cu @@ -36,11 +36,11 @@ struct v4f { __attribute__((device)) v4f tex2d_ld(texture, float, float) asm("llvm.nvvm.tex.unified.2d.v4f32.f32"); __attribute__((device)) v4f tex2d_ld(texture, int, int) asm("llvm.nvvm.tex.unified.2d.v4f32.s32"); -// DEVICE-LABEL: float @_Z3fooff(float noundef %x, float noundef %y) +// DEVICE-LABEL: float @_Z3fooff(float %x, float %y) // DEVICE: call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @tex) -// DEVICE: call %struct.v4f @llvm.nvvm.tex.unified.2d.v4f32.f32(i64 %{{.*}}, float noundef %{{.*}}, float noundef %{{.*}}) +// DEVICE: call %struct.v4f @llvm.nvvm.tex.unified.2d.v4f32.f32(i64 %{{.*}}, float %{{.*}}, float %{{.*}}) // DEVICE: call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @norm) -// DEVICE: call %struct.v4f @llvm.nvvm.tex.unified.2d.v4f32.s32(i64 %{{.*}}, i32 noundef %{{.*}}, i32 noundef %{{.*}}) +// DEVICE: call %struct.v4f @llvm.nvvm.tex.unified.2d.v4f32.s32(i64 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) __attribute__((device)) float foo(float x, float y) { return tex2d_ld(tex, x, y).x + tex2d_ld(norm, int(x), int(y)).x; } diff --git a/clang/test/CodeGenCUDA/unnamed-types.cu b/clang/test/CodeGenCUDA/unnamed-types.cu index 6849df5a184ba24df9ed2ab4aefe5211810c0ae5..b59d5f448dde208ae87528150d99867d94d1513e 100644 --- a/clang/test/CodeGenCUDA/unnamed-types.cu +++ b/clang/test/CodeGenCUDA/unnamed-types.cu @@ -19,16 +19,16 @@ __device__ float d1(float x) { } // DEVICE: amdgpu_kernel void @_Z2k0IZZ2f1PfENKUlS0_E_clES0_EUlfE_EvS0_T_( -// DEVICE: define internal noundef float @_ZZZ2f1PfENKUlS_E_clES_ENKUlfE_clEf( +// DEVICE: define internal float @_ZZZ2f1PfENKUlS_E_clES_ENKUlfE_clEf( template __global__ void k0(float *p, F f) { p[0] = f(p[0]) + d0(p[1]) + d1(p[2]); } // DEVICE: amdgpu_kernel void @_Z2k1IZ2f1PfEUlfE_Z2f1S0_EUlffE_Z2f1S0_EUlfE0_EvS0_T_T0_T1_( -// DEVICE: define internal noundef float @_ZZ2f1PfENKUlfE_clEf( -// DEVICE: define internal noundef float @_ZZ2f1PfENKUlffE_clEff( -// DEVICE: define internal noundef float @_ZZ2f1PfENKUlfE0_clEf( +// DEVICE: define internal float @_ZZ2f1PfENKUlfE_clEf( +// DEVICE: define internal float @_ZZ2f1PfENKUlffE_clEff( +// DEVICE: define internal float @_ZZ2f1PfENKUlfE0_clEf( template __global__ void k1(float *p, F0 f0, F1 f1, F2 f2) { p[0] = f0(p[0]) + f1(p[1], p[2]) + f2(p[3]); diff --git a/clang/test/CodeGenCUDA/usual-deallocators.cu b/clang/test/CodeGenCUDA/usual-deallocators.cu index 21988c9ddcf75f2ae5a9717d3c6950f0f304a3c5..6f4cc267a23f38ab94c3f9c9736215a85676a41f 100644 --- a/clang/test/CodeGenCUDA/usual-deallocators.cu +++ b/clang/test/CodeGenCUDA/usual-deallocators.cu @@ -83,25 +83,25 @@ __host__ __device__ void tests_hd(void *t) { // COMMON: call void @_ZN4H1D1dlEPv test_hd(t); // COMMON-LABEL: define linkonce_odr void @_Z7test_hdI4H1D2EvPv - // DEVICE: call void @_ZN4H1D2dlEPvj(i8* noundef {{.*}}, i32 noundef 1) - // HOST: call void @_ZN4H1D2dlEPv(i8* noundef {{.*}}) + // DEVICE: call void @_ZN4H1D2dlEPvj(i8* {{.*}}, i32 1) + // HOST: call void @_ZN4H1D2dlEPv(i8* {{.*}}) test_hd(t); // COMMON-LABEL: define linkonce_odr void @_Z7test_hdI4H2D1EvPv // DEVICE: call void @_ZN4H2D1dlEPv(i8* {{.*}}) - // HOST: call void @_ZN4H2D1dlEPvj(i8* noundef %3, i32 noundef 1) + // HOST: call void @_ZN4H2D1dlEPvj(i8* %3, i32 1) test_hd(t); // COMMON-LABEL: define linkonce_odr void @_Z7test_hdI4H2D2EvPv - // COMMON: call void @_ZN4H2D2dlEPvj(i8* noundef {{.*}}, i32 noundef 1) + // COMMON: call void @_ZN4H2D2dlEPvj(i8* {{.*}}, i32 1) test_hd(t); // COMMON-LABEL: define linkonce_odr void @_Z7test_hdI6H1D1D2EvPv - // COMMON: call void @_ZN6H1D1D2dlEPv(i8* noundef %3) + // COMMON: call void @_ZN6H1D1D2dlEPv(i8* %3) test_hd(t); // COMMON-LABEL: define linkonce_odr void @_Z7test_hdI6H1H2D1EvPv // COMMON: call void @_ZN6H1H2D1dlEPv(i8* {{.*}}) test_hd(t); // COMMON-LABEL: define linkonce_odr void @_Z7test_hdI6H1H2D2EvPv - // DEVICE: call void @_ZN6H1H2D2dlEPvj(i8* noundef {{.*}}, i32 noundef 1) - // HOST: call void @_ZN6H1H2D2dlEPv(i8* noundef {{.*}}) + // DEVICE: call void @_ZN6H1H2D2dlEPvj(i8* {{.*}}, i32 1) + // HOST: call void @_ZN6H1H2D2dlEPv(i8* {{.*}}) test_hd(t); // COMMON-LABEL: define linkonce_odr void @_Z7test_hdI8H1H2D1D2EvPv // COMMON: call void @_ZN8H1H2D1D2dlEPv(i8* {{.*}}) @@ -113,38 +113,38 @@ __host__ __device__ void tests_hd(void *t) { // Make sure we've picked deallocator for the correct side of compilation. -// COMMON-LABEL: define linkonce_odr void @_ZN4H1D1dlEPv(i8* noundef %0) +// COMMON-LABEL: define linkonce_odr void @_ZN4H1D1dlEPv(i8* %0) // DEVICE: call void @dev_fn() // HOST: call void @host_fn() -// DEVICE-LABEL: define linkonce_odr void @_ZN4H1D2dlEPvj(i8* noundef %0, i32 noundef %1) +// DEVICE-LABEL: define linkonce_odr void @_ZN4H1D2dlEPvj(i8* %0, i32 %1) // DEVICE: call void @dev_fn() -// HOST-LABEL: define linkonce_odr void @_ZN4H1D2dlEPv(i8* noundef %0) +// HOST-LABEL: define linkonce_odr void @_ZN4H1D2dlEPv(i8* %0) // HOST: call void @host_fn() -// DEVICE-LABEL: define linkonce_odr void @_ZN4H2D1dlEPv(i8* noundef %0) +// DEVICE-LABEL: define linkonce_odr void @_ZN4H2D1dlEPv(i8* %0) // DEVICE: call void @dev_fn() -// HOST-LABEL: define linkonce_odr void @_ZN4H2D1dlEPvj(i8* noundef %0, i32 noundef %1) +// HOST-LABEL: define linkonce_odr void @_ZN4H2D1dlEPvj(i8* %0, i32 %1) // HOST: call void @host_fn() -// COMMON-LABEL: define linkonce_odr void @_ZN4H2D2dlEPvj(i8* noundef %0, i32 noundef %1) +// COMMON-LABEL: define linkonce_odr void @_ZN4H2D2dlEPvj(i8* %0, i32 %1) // DEVICE: call void @dev_fn() // HOST: call void @host_fn() -// COMMON-LABEL: define linkonce_odr void @_ZN6H1D1D2dlEPv(i8* noundef %0) +// COMMON-LABEL: define linkonce_odr void @_ZN6H1D1D2dlEPv(i8* %0) // DEVICE: call void @dev_fn() // HOST: call void @host_fn() -// COMMON-LABEL: define linkonce_odr void @_ZN6H1H2D1dlEPv(i8* noundef %0) +// COMMON-LABEL: define linkonce_odr void @_ZN6H1H2D1dlEPv(i8* %0) // DEVICE: call void @dev_fn() // HOST: call void @host_fn() -// DEVICE-LABEL: define linkonce_odr void @_ZN6H1H2D2dlEPvj(i8* noundef %0, i32 noundef %1) +// DEVICE-LABEL: define linkonce_odr void @_ZN6H1H2D2dlEPvj(i8* %0, i32 %1) // DEVICE: call void @dev_fn() -// HOST-LABEL: define linkonce_odr void @_ZN6H1H2D2dlEPv(i8* noundef %0) +// HOST-LABEL: define linkonce_odr void @_ZN6H1H2D2dlEPv(i8* %0) // HOST: call void @host_fn() -// COMMON-LABEL: define linkonce_odr void @_ZN8H1H2D1D2dlEPv(i8* noundef %0) +// COMMON-LABEL: define linkonce_odr void @_ZN8H1H2D1D2dlEPv(i8* %0) // DEVICE: call void @dev_fn() // HOST: call void @host_fn() diff --git a/clang/test/CodeGenCUDA/vtbl.cu b/clang/test/CodeGenCUDA/vtbl.cu index 9e2ff7280cf53bd3e4c11091707dbf1203d84cf3..e09d904c2aaded0da9651bc8163c8992b82e1d96 100644 --- a/clang/test/CodeGenCUDA/vtbl.cu +++ b/clang/test/CodeGenCUDA/vtbl.cu @@ -3,7 +3,7 @@ #include "Inputs/cuda.h" -// CHECK-LABEL: define {{.*}}@_ZN1AC2Ev(%struct.A* noundef %this) +// CHECK-LABEL: define {{.*}}@_ZN1AC2Ev(%struct.A* nonnull align 8 dereferenceable(8) %this) // CHECK: store %struct.A* %this, %struct.A** %this.addr.ascast // CHECK: %this1 = load %struct.A*, %struct.A** %this.addr.ascast // CHECK: %[[VTFIELD:.*]] = bitcast %struct.A* %this1 to i32 (...)* addrspace(1)** diff --git a/clang/test/CodeGenCXX/2009-05-04-PureConstNounwind.cpp b/clang/test/CodeGenCXX/2009-05-04-PureConstNounwind.cpp index 99d172239daa3cd7ad926473496bcdcd92f9f7f0..e1d539608fcc8499a43683402c65c46b98f647f2 100644 --- a/clang/test/CodeGenCXX/2009-05-04-PureConstNounwind.cpp +++ b/clang/test/CodeGenCXX/2009-05-04-PureConstNounwind.cpp @@ -5,14 +5,14 @@ int t(void); // CHECK: define{{.*}} i32 @_Z1fv() [[TF:#[0-9]+]] { int f(void) { - // CHECK: call noundef i32 @_Z1cv() [[NUW_RN_CALL:#[0-9]+]] - // CHECK: call noundef i32 @_Z1pv() [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call i32 @_Z1cv() [[NUW_RN_CALL:#[0-9]+]] + // CHECK: call i32 @_Z1pv() [[NUW_RO_CALL:#[0-9]+]] return c() + p() + t(); } -// CHECK: declare noundef i32 @_Z1cv() [[NUW_RN:#[0-9]+]] -// CHECK: declare noundef i32 @_Z1pv() [[NUW_RO:#[0-9]+]] -// CHECK: declare noundef i32 @_Z1tv() [[TF2:#[0-9]+]] +// CHECK: declare i32 @_Z1cv() [[NUW_RN:#[0-9]+]] +// CHECK: declare i32 @_Z1pv() [[NUW_RO:#[0-9]+]] +// CHECK: declare i32 @_Z1tv() [[TF2:#[0-9]+]] // CHECK: attributes [[TF]] = { {{.*}} } // CHECK: attributes [[NUW_RN]] = { nounwind readnone willreturn{{.*}} } diff --git a/clang/test/CodeGenCXX/2011-12-19-init-list-ctor.cpp b/clang/test/CodeGenCXX/2011-12-19-init-list-ctor.cpp index 9c402e709ffc6c09939a510d6f719cf57ac974f7..21a79872bc1993b5f240b9ed1226319e3666d35f 100644 --- a/clang/test/CodeGenCXX/2011-12-19-init-list-ctor.cpp +++ b/clang/test/CodeGenCXX/2011-12-19-init-list-ctor.cpp @@ -19,8 +19,8 @@ struct S { }; // CHECK: store i32 0, i32* getelementptr inbounds ([3 x %struct.S], [3 x %struct.S]* @arr, i64 0, i64 0, i32 0) -// CHECK: call void @_ZN1AC1EPKc(%struct.A* {{[^,]*}} getelementptr inbounds ([3 x %struct.S], [3 x %struct.S]* @arr, i64 0, i64 0, i32 1), i8* noundef getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0)) +// CHECK: call void @_ZN1AC1EPKc(%struct.A* {{[^,]*}} getelementptr inbounds ([3 x %struct.S], [3 x %struct.S]* @arr, i64 0, i64 0, i32 1), i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0)) // CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.S], [3 x %struct.S]* @arr, i64 0, i64 1, i32 0) -// CHECK: call void @_ZN1AC1EPKc(%struct.A* {{[^,]*}} getelementptr inbounds ([3 x %struct.S], [3 x %struct.S]* @arr, i64 0, i64 1, i32 1), i8* noundef getelementptr inbounds ([6 x i8], [6 x i8]* @.str.1, i64 0, i64 0)) +// CHECK: call void @_ZN1AC1EPKc(%struct.A* {{[^,]*}} getelementptr inbounds ([3 x %struct.S], [3 x %struct.S]* @arr, i64 0, i64 1, i32 1), i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str.1, i64 0, i64 0)) // CHECK: store i32 2, i32* getelementptr inbounds ([3 x %struct.S], [3 x %struct.S]* @arr, i64 0, i64 2, i32 0) -// CHECK: call void @_ZN1AC1EPKc(%struct.A* {{[^,]*}} getelementptr inbounds ([3 x %struct.S], [3 x %struct.S]* @arr, i64 0, i64 2, i32 1), i8* noundef getelementptr inbounds ([8 x i8], [8 x i8]* @.str.2, i64 0, i64 0)) +// CHECK: call void @_ZN1AC1EPKc(%struct.A* {{[^,]*}} getelementptr inbounds ([3 x %struct.S], [3 x %struct.S]* @arr, i64 0, i64 2, i32 1), i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str.2, i64 0, i64 0)) diff --git a/clang/test/CodeGenCXX/RelativeVTablesABI/diamond-virtual-inheritance.cpp b/clang/test/CodeGenCXX/RelativeVTablesABI/diamond-virtual-inheritance.cpp index 98c642ba72b5a6dcae8ce084ed1b2da161d5164f..88a40014bcdbe2868363ebde0e9de995ee399b98 100644 --- a/clang/test/CodeGenCXX/RelativeVTablesABI/diamond-virtual-inheritance.cpp +++ b/clang/test/CodeGenCXX/RelativeVTablesABI/diamond-virtual-inheritance.cpp @@ -42,7 +42,7 @@ // CHECK: @_ZTC1D8_1C ={{.*}} unnamed_addr alias { [4 x i32], [4 x i32] }, { [4 x i32], [4 x i32] }* @_ZTC1D8_1C.local // CHECK: @_ZTV1D ={{.*}} unnamed_addr alias { [5 x i32], [4 x i32], [4 x i32] }, { [5 x i32], [4 x i32], [4 x i32] }* @_ZTV1D.local -// CHECK: define{{.*}} void @_Z5D_fooP1D(%class.D* noundef %d) local_unnamed_addr +// CHECK: define{{.*}} void @_Z5D_fooP1D(%class.D* %d) local_unnamed_addr // CHECK-NEXT: entry: // CHECK-NEXT: [[d:%[0-9]+]] = bitcast %class.D* %d to i8** // CHECK-NEXT: [[vtable:%[a-z0-9]+]] = load i8*, i8** [[d]], align 8 diff --git a/clang/test/CodeGenCXX/RelativeVTablesABI/dynamic-cast.cpp b/clang/test/CodeGenCXX/RelativeVTablesABI/dynamic-cast.cpp index 9a955a7a8948b811b2f4af82fd68884a072a6436..7dbcefd7361bc33dbfe6134f4ce111d9fadc5d9c 100644 --- a/clang/test/CodeGenCXX/RelativeVTablesABI/dynamic-cast.cpp +++ b/clang/test/CodeGenCXX/RelativeVTablesABI/dynamic-cast.cpp @@ -3,13 +3,13 @@ // RUN: %clang_cc1 %s -triple=aarch64-unknown-fuchsia -O3 -S -o - -emit-llvm | FileCheck %s -// CHECK: define{{.*}} %class.A* @_Z6upcastP1B(%class.B* noundef readnone %b) local_unnamed_addr +// CHECK: define{{.*}} %class.A* @_Z6upcastP1B(%class.B* readnone %b) local_unnamed_addr // CHECK-NEXT: entry: // CHECK-NEXT: [[a:%[0-9]+]] = getelementptr %class.B, %class.B* %b, i64 0, i32 0 // CHECK-NEXT: ret %class.A* [[a]] // CHECK-NEXT: } -// CHECK: define{{.*}} %class.B* @_Z8downcastP1A(%class.A* noundef readonly %a) local_unnamed_addr +// CHECK: define{{.*}} %class.B* @_Z8downcastP1A(%class.A* readonly %a) local_unnamed_addr // CHECK-NEXT: entry: // CHECK-NEXT: [[isnull:%[0-9]+]] = icmp eq %class.A* %a, null // CHECK-NEXT: br i1 [[isnull]], label %[[dynamic_cast_end:[a-z0-9._]+]], label %[[dynamic_cast_notnull:[a-z0-9._]+]] @@ -25,12 +25,12 @@ // CHECK: declare i8* @__dynamic_cast(i8*, i8*, i8*, i64) local_unnamed_addr -// CHECK: define{{.*}} %class.B* @_Z8selfcastP1B(%class.B* noundef readnone returned %b) local_unnamed_addr +// CHECK: define{{.*}} %class.B* @_Z8selfcastP1B(%class.B* readnone returned %b) local_unnamed_addr // CHECK-NEXT: entry // CHECK-NEXT: ret %class.B* %b // CHECK-NEXT: } -// CHECK: define{{.*}} i8* @_Z9void_castP1B(%class.B* noundef readonly %b) local_unnamed_addr +// CHECK: define{{.*}} i8* @_Z9void_castP1B(%class.B* readonly %b) local_unnamed_addr // CHECK-NEXT: entry: // CHECK-NEXT: [[isnull:%[0-9]+]] = icmp eq %class.B* %b, null // CHECK-NEXT: br i1 [[isnull]], label %[[dynamic_cast_end:[a-z0-9._]+]], label %[[dynamic_cast_notnull:[a-z0-9._]+]] diff --git a/clang/test/CodeGenCXX/RelativeVTablesABI/member-function-pointer.cpp b/clang/test/CodeGenCXX/RelativeVTablesABI/member-function-pointer.cpp index a84e23d81e1455b5636dea72d971660834ceb984..35689b1c71a15609e6b7d8187058d6ab84162557 100644 --- a/clang/test/CodeGenCXX/RelativeVTablesABI/member-function-pointer.cpp +++ b/clang/test/CodeGenCXX/RelativeVTablesABI/member-function-pointer.cpp @@ -2,7 +2,7 @@ // RUN: %clang_cc1 %s -triple=aarch64-unknown-fuchsia -O3 -S -o - -emit-llvm | FileCheck %s -// CHECK: define{{.*}} void @_Z4funcP1AMS_FvvE(%class.A* noundef %a, [2 x i64] %fn.coerce) local_unnamed_addr +// CHECK: define{{.*}} void @_Z4funcP1AMS_FvvE(%class.A* %a, [2 x i64] %fn.coerce) local_unnamed_addr // CHECK-NEXT: entry: // CHECK-NEXT: [[fn_ptr:%.+]] = extractvalue [2 x i64] %fn.coerce, 0 // CHECK-NEXT: [[adjust:%.+]] = extractvalue [2 x i64] %fn.coerce, 1 diff --git a/clang/test/CodeGenCXX/RelativeVTablesABI/multiple-inheritance.cpp b/clang/test/CodeGenCXX/RelativeVTablesABI/multiple-inheritance.cpp index 39039c2aa7e4f5daa1b670abd9b3db6aca4202f2..3341e1091a8e444d26e00de09c6e1819a7711b53 100644 --- a/clang/test/CodeGenCXX/RelativeVTablesABI/multiple-inheritance.cpp +++ b/clang/test/CodeGenCXX/RelativeVTablesABI/multiple-inheritance.cpp @@ -13,7 +13,7 @@ // CHECK: @_ZTV1C ={{.*}} unnamed_addr alias { [4 x i32], [3 x i32] }, { [4 x i32], [3 x i32] }* @_ZTV1C.local -// CHECK: define{{.*}} void @_Z8C_foobarP1C(%class.C* noundef %c) local_unnamed_addr +// CHECK: define{{.*}} void @_Z8C_foobarP1C(%class.C* %c) local_unnamed_addr // CHECK-NEXT: entry: // CHECK-NEXT: [[c:%[0-9]+]] = bitcast %class.C* %c to i8** // CHECK-NEXT: [[vtable:%[a-z0-9]+]] = load i8*, i8** [[c]], align 8 diff --git a/clang/test/CodeGenCXX/RelativeVTablesABI/parent-and-child-in-comdats.cpp b/clang/test/CodeGenCXX/RelativeVTablesABI/parent-and-child-in-comdats.cpp index 3af393595ec11833f93fcb1d40b143eb17e317af..79962d552ba457d473e5f39d31b27edd086685a1 100644 --- a/clang/test/CodeGenCXX/RelativeVTablesABI/parent-and-child-in-comdats.cpp +++ b/clang/test/CodeGenCXX/RelativeVTablesABI/parent-and-child-in-comdats.cpp @@ -23,7 +23,7 @@ // CHECK: @_ZTV1A = linkonce_odr unnamed_addr alias { [3 x i32] }, { [3 x i32] }* @_ZTV1A.local // CHECK: @_ZTV1B = linkonce_odr unnamed_addr alias { [3 x i32] }, { [3 x i32] }* @_ZTV1B.local -// CHECK: declare void @_Z5A_fooP1A(%class.A* noundef) +// CHECK: declare void @_Z5A_fooP1A(%class.A*) // The stubs and implementations for foo() are in their own comdat sections. // CHECK: define linkonce_odr void @_ZN1A3fooEv(%class.A* {{.*}}%this) unnamed_addr #{{[0-9]+}} comdat diff --git a/clang/test/CodeGenCXX/RelativeVTablesABI/type-info.cpp b/clang/test/CodeGenCXX/RelativeVTablesABI/type-info.cpp index 6249726701152ff19bd72d303e5b69efbc82db63..c795fcaf1cc7852b6b922d35ca24d43c57548dfd 100644 --- a/clang/test/CodeGenCXX/RelativeVTablesABI/type-info.cpp +++ b/clang/test/CodeGenCXX/RelativeVTablesABI/type-info.cpp @@ -28,7 +28,7 @@ // CHECK-NEXT: ret i8* getelementptr inbounds ([3 x i8], [3 x i8]* @_ZTS1A, i64 0, i64 0) // CHECK-NEXT: } -// CHECK: define{{.*}} i1 @_Z5equalP1A(%class.A* noundef readonly %a) local_unnamed_addr +// CHECK: define{{.*}} i1 @_Z5equalP1A(%class.A* readonly %a) local_unnamed_addr // CHECK-NEXT: entry: // CHECK-NEXT: [[isnull:%[0-9]+]] = icmp eq %class.A* %a, null // CHECK-NEXT: br i1 [[isnull]], label %[[bad_typeid:[a-z0-9._]+]], label %[[end:[a-z0-9.+]+]] diff --git a/clang/test/CodeGenCXX/RelativeVTablesABI/vbase-offset.cpp b/clang/test/CodeGenCXX/RelativeVTablesABI/vbase-offset.cpp index c99cb5372d5b7a8d185c70d202cbe102f05570c1..6ad1d520d763fa2cb67665a530643be62c638f63 100644 --- a/clang/test/CodeGenCXX/RelativeVTablesABI/vbase-offset.cpp +++ b/clang/test/CodeGenCXX/RelativeVTablesABI/vbase-offset.cpp @@ -13,7 +13,7 @@ // CHECK-NEXT: [[vbase_offset:%.+]] = load i32, i32* [[vbase_offset_ptr2]], align 4 // CHECK-NEXT: [[adj_this:%.+]] = getelementptr inbounds i8, i8* [[this]], i32 [[vbase_offset]] // CHECK-NEXT: [[adj_this2:%.+]] = bitcast i8* [[adj_this]] to %class.Derived* -// CHECK: [[call:%.+]] = tail call noundef i32 @_ZN7Derived1fEi(%class.Derived* noundef{{[^,]*}} [[adj_this2]], i32 noundef {{.*}}) +// CHECK: [[call:%.+]] = tail call i32 @_ZN7Derived1fEi(%class.Derived* {{[^,]*}} [[adj_this2]], i32 {{.*}}) // CHECK: ret i32 [[call]] class Base { diff --git a/clang/test/CodeGenCXX/RelativeVTablesABI/virtual-function-call.cpp b/clang/test/CodeGenCXX/RelativeVTablesABI/virtual-function-call.cpp index 7aa14879361260d454dcfc1b2d6a892c3495d5d3..30d0772dee984735194dca02487362c661b70eb9 100644 --- a/clang/test/CodeGenCXX/RelativeVTablesABI/virtual-function-call.cpp +++ b/clang/test/CodeGenCXX/RelativeVTablesABI/virtual-function-call.cpp @@ -2,7 +2,7 @@ // RUN: %clang_cc1 %s -triple=aarch64-unknown-fuchsia -O3 -S -o - -emit-llvm | FileCheck %s -// CHECK: define{{.*}} void @_Z5A_fooP1A(%class.A* noundef %a) local_unnamed_addr +// CHECK: define{{.*}} void @_Z5A_fooP1A(%class.A* %a) local_unnamed_addr // CHECK-NEXT: entry: // CHECK-NEXT: [[this:%[0-9]+]] = bitcast %class.A* %a to i8** // CHECK-NEXT: %vtable1 = load i8*, i8** [[this]] diff --git a/clang/test/CodeGenCXX/address-space-cast.cpp b/clang/test/CodeGenCXX/address-space-cast.cpp index a9309d4ca180ed816130e18349d02b091cdfa156..7b0792df8588c44ceb6534a1381cd764a2142840 100644 --- a/clang/test/CodeGenCXX/address-space-cast.cpp +++ b/clang/test/CodeGenCXX/address-space-cast.cpp @@ -46,30 +46,30 @@ void test_cast(char *gen_char_ptr, void *gen_void_ptr, int *gen_int_ptr) { __private__ int *priv_int_ptr = (__private__ int *)gen_void_ptr; // CHECK: %[[cast:.*]] = addrspacecast i8* %{{.*}} to i8 addrspace(5)* - // CHECK-NEXT: call void @_Z10func_pcharPU3AS5c(i8 addrspace(5)* noundef %[[cast]]) + // CHECK-NEXT: call void @_Z10func_pcharPU3AS5c(i8 addrspace(5)* %[[cast]]) func_pchar((__private__ char *)gen_char_ptr); // CHECK: %[[cast:.*]] = addrspacecast i8* %{{.*}} to i8 addrspace(5)* - // CHECK-NEXT: call void @_Z10func_pcharPU3AS5c(i8 addrspace(5)* noundef %[[cast]]) + // CHECK-NEXT: call void @_Z10func_pcharPU3AS5c(i8 addrspace(5)* %[[cast]]) func_pchar((__private__ char *)gen_void_ptr); // CHECK: %[[cast:.*]] = addrspacecast i32* %{{.*}} to i8 addrspace(5)* - // CHECK-NEXT: call void @_Z10func_pcharPU3AS5c(i8 addrspace(5)* noundef %[[cast]]) + // CHECK-NEXT: call void @_Z10func_pcharPU3AS5c(i8 addrspace(5)* %[[cast]]) func_pchar((__private__ char *)gen_int_ptr); // CHECK: %[[cast:.*]] = addrspacecast i8* %{{.*}} to i8 addrspace(5)* - // CHECK-NEXT: call void @_Z10func_pvoidPU3AS5v(i8 addrspace(5)* noundef %[[cast]]) + // CHECK-NEXT: call void @_Z10func_pvoidPU3AS5v(i8 addrspace(5)* %[[cast]]) func_pvoid((__private__ void *)gen_char_ptr); // CHECK: %[[cast:.*]] = addrspacecast i8* %{{.*}} to i8 addrspace(5)* - // CHECK-NEXT: call void @_Z10func_pvoidPU3AS5v(i8 addrspace(5)* noundef %[[cast]]) + // CHECK-NEXT: call void @_Z10func_pvoidPU3AS5v(i8 addrspace(5)* %[[cast]]) func_pvoid((__private__ void *)gen_void_ptr); // CHECK: %[[cast:.*]] = addrspacecast i32* %{{.*}} to i8 addrspace(5)* - // CHECK-NEXT: call void @_Z10func_pvoidPU3AS5v(i8 addrspace(5)* noundef %[[cast]]) + // CHECK-NEXT: call void @_Z10func_pvoidPU3AS5v(i8 addrspace(5)* %[[cast]]) func_pvoid((__private__ void *)gen_int_ptr); // CHECK: %[[cast:.*]] = addrspacecast i8* %{{.*}} to i32 addrspace(5)* - // CHECK-NEXT: call void @_Z9func_pintPU3AS5i(i32 addrspace(5)* noundef %[[cast]]) + // CHECK-NEXT: call void @_Z9func_pintPU3AS5i(i32 addrspace(5)* %[[cast]]) func_pint((__private__ int *)gen_void_ptr); } diff --git a/clang/test/CodeGenCXX/address-space-ref.cpp b/clang/test/CodeGenCXX/address-space-ref.cpp index 8ae1dc34490d62911b9556a374ff9214a827f7de..33c42704d0cbb7fffc9b45171f2f31158c93983d 100644 --- a/clang/test/CodeGenCXX/address-space-ref.cpp +++ b/clang/test/CodeGenCXX/address-space-ref.cpp @@ -10,7 +10,7 @@ a & foo(a &x, a & y) { return x; } -// CHECK: define{{.*}} align 4 dereferenceable(4) i32 addrspace(1)* @_Z3fooRU3AS1iS0_(i32 addrspace(1)* noundef align 4 dereferenceable(4) %x, i32 addrspace(1)* noundef align 4 dereferenceable(4) %y) +// CHECK: define{{.*}} align 4 dereferenceable(4) i32 addrspace(1)* @_Z3fooRU3AS1iS0_(i32 addrspace(1)* align 4 dereferenceable(4) %x, i32 addrspace(1)* align 4 dereferenceable(4) %y) // For a reference to an incomplete type in an alternate address space, output // neither dereferenceable nor nonnull. @@ -22,7 +22,7 @@ b & bar(b &x, b & y) { return x; } -// CHECK: define{{.*}} align 1 %class.bc addrspace(1)* @_Z3barRU3AS12bcS1_(%class.bc addrspace(1)* noundef align 1 %x, %class.bc addrspace(1)* noundef align 1 %y) +// CHECK: define{{.*}} align 1 %class.bc addrspace(1)* @_Z3barRU3AS12bcS1_(%class.bc addrspace(1)* align 1 %x, %class.bc addrspace(1)* align 1 %y) // For a reference to an incomplete type in addrspace(0), output nonnull. @@ -30,7 +30,7 @@ bc & bar2(bc &x, bc & y) { return x; } -// NULL-INVALID: define{{.*}} nonnull align 1 %class.bc* @_Z4bar2R2bcS0_(%class.bc* noundef nonnull align 1 %x, %class.bc* noundef nonnull align 1 %y) -// NULL-VALID: define{{.*}} align 1 %class.bc* @_Z4bar2R2bcS0_(%class.bc* noundef align 1 %x, %class.bc* noundef align 1 %y) +// NULL-INVALID: define{{.*}} nonnull align 1 %class.bc* @_Z4bar2R2bcS0_(%class.bc* nonnull align 1 %x, %class.bc* nonnull align 1 %y) +// NULL-VALID: define{{.*}} align 1 %class.bc* @_Z4bar2R2bcS0_(%class.bc* align 1 %x, %class.bc* align 1 %y) diff --git a/clang/test/CodeGenCXX/aix-alignment.cpp b/clang/test/CodeGenCXX/aix-alignment.cpp index ccc427dca194eb1a6ffb696a021ad50b51b11950..56ed7a74b15d03871b1060403032de879108c199 100644 --- a/clang/test/CodeGenCXX/aix-alignment.cpp +++ b/clang/test/CodeGenCXX/aix-alignment.cpp @@ -11,8 +11,8 @@ struct B { ~B() {} }; -// AIX32: %call = call noalias noundef nonnull i8* @_Znam(i32 noundef 8) -// AIX64: %call = call noalias noundef nonnull i8* @_Znam(i64 noundef 8) +// AIX32: %call = call noalias nonnull i8* @_Znam(i32 8) +// AIX64: %call = call noalias nonnull i8* @_Znam(i64 8) B *allocBp() { return new B[0]; } // AIX-LABEL: delete.notnull: @@ -32,7 +32,7 @@ typedef struct D { ~D(){}; } D; -// AIX: define void @_Z3foo1D(%struct.D* noalias sret(%struct.D) align 4 %agg.result, %struct.D* noundef %x) +// AIX: define void @_Z3foo1D(%struct.D* noalias sret(%struct.D) align 4 %agg.result, %struct.D* %x) // AIX: %1 = bitcast %struct.D* %agg.result to i8* // AIX: %2 = bitcast %struct.D* %x to i8* // AIX32 call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %1, i8* align 4 %2, i32 16, i1 false) diff --git a/clang/test/CodeGenCXX/aix-static-init-temp-spec-and-inline-var.cpp b/clang/test/CodeGenCXX/aix-static-init-temp-spec-and-inline-var.cpp index f170b9343d56f1c62403143481e65ff699f39a86..799b158bcf603c5d140a20f83200c9d6bb80036c 100644 --- a/clang/test/CodeGenCXX/aix-static-init-temp-spec-and-inline-var.cpp +++ b/clang/test/CodeGenCXX/aix-static-init-temp-spec-and-inline-var.cpp @@ -52,8 +52,8 @@ A A::instance = bar(); // CHECK: define internal void @__cxx_global_var_init() [[ATTR:#[0-9]+]] { // CHECK: entry: -// CHECK32: call void @_ZN5test15Test1C1Ei(%"struct.test1::Test1"* noundef{{[^,]*}} @_ZN5test12t0E, i32 noundef 2) -// CHECK64: call void @_ZN5test15Test1C1Ei(%"struct.test1::Test1"* noundef{{[^,]*}} @_ZN5test12t0E, i32 noundef signext 2) +// CHECK32: call void @_ZN5test15Test1C1Ei(%"struct.test1::Test1"* {{[^,]*}} @_ZN5test12t0E, i32 2) +// CHECK64: call void @_ZN5test15Test1C1Ei(%"struct.test1::Test1"* {{[^,]*}} @_ZN5test12t0E, i32 signext 2) // CHECK: %0 = call i32 @atexit(void ()* @__dtor__ZN5test12t0E) // CHECK: ret void // CHECK: } @@ -90,8 +90,8 @@ A A::instance = bar(); // CHECK: br i1 %tobool, label %init, label %init.end // CHECK: init: -// CHECK32: call void @_ZN5test15Test1C1Ei(%"struct.test1::Test1"* noundef{{[^,]*}} @_ZN5test12t2E, i32 noundef 2) -// CHECK64: call void @_ZN5test15Test1C1Ei(%"struct.test1::Test1"* noundef{{[^,]*}} @_ZN5test12t2E, i32 noundef signext 2) +// CHECK32: call void @_ZN5test15Test1C1Ei(%"struct.test1::Test1"* {{[^,]*}} @_ZN5test12t2E, i32 2) +// CHECK64: call void @_ZN5test15Test1C1Ei(%"struct.test1::Test1"* {{[^,]*}} @_ZN5test12t2E, i32 signext 2) // CHECK: %2 = call i32 @atexit(void ()* @__dtor__ZN5test12t2E) // CHECK: call void @__cxa_guard_release(i64* @_ZGVN5test12t2E) // CHECK: br label %init.end @@ -158,7 +158,7 @@ A A::instance = bar(); // CHECK: define internal void @__cxx_global_var_init.3() [[ATTR:#[0-9]+]] { // CHECK: entry: -// CHECK: %call = call noundef nonnull align 1 dereferenceable(1) %"struct.test2::A.0"* @_ZN5test23barEv() +// CHECK: %call = call nonnull align 1 dereferenceable(1) %"struct.test2::A.0"* @_ZN5test23barEv() // CHECK: %0 = call i32 @atexit(void ()* @__dtor__ZN5test21AIiE8instanceE) // CHECK: ret void // CHECK: } @@ -190,8 +190,8 @@ A A::instance = bar(); // CHECK: br i1 %guard.uninitialized, label %init.check, label %init.end // CHECK: init.check: -// CHECK32: call void @_ZN5test15Test1C1Ei(%"struct.test1::Test1"* {{[^,]*}} @_ZN5test12t1IiEE, i32 noundef 2) -// CHECK64: call void @_ZN5test15Test1C1Ei(%"struct.test1::Test1"* {{[^,]*}} @_ZN5test12t1IiEE, i32 noundef signext 2) +// CHECK32: call void @_ZN5test15Test1C1Ei(%"struct.test1::Test1"* {{[^,]*}} @_ZN5test12t1IiEE, i32 2) +// CHECK64: call void @_ZN5test15Test1C1Ei(%"struct.test1::Test1"* {{[^,]*}} @_ZN5test12t1IiEE, i32 signext 2) // CHECK: %1 = call i32 @atexit(void ()* @__dtor__ZN5test12t1IiEE) // CHECK: store i8 1, i8* bitcast (i64* @_ZGVN5test12t1IiEE to i8*), align 8 // CHECK: br label %init.end diff --git a/clang/test/CodeGenCXX/aix-static-init.cpp b/clang/test/CodeGenCXX/aix-static-init.cpp index 878c5327e2831e56a2da6f5c0ee516cda3390a4c..dc0e9d39b7a32ec91118b91e68d6e9d88d9fa7e7 100644 --- a/clang/test/CodeGenCXX/aix-static-init.cpp +++ b/clang/test/CodeGenCXX/aix-static-init.cpp @@ -102,8 +102,8 @@ namespace test4 { // CHECK: define internal void @__cxx_global_var_init.2() [[ATTR:#[0-9]+]] { // CHECK: entry: -// CHECK32: %call = call noundef i32 @_ZN5test23fooEv() -// CHECK64: %call = call noundef signext i32 @_ZN5test23fooEv() +// CHECK32: %call = call i32 @_ZN5test23fooEv() +// CHECK64: %call = call signext i32 @_ZN5test23fooEv() // CHECK: store i32 %call, i32* @_ZN5test21xE // CHECK: ret void // CHECK: } diff --git a/clang/test/CodeGenCXX/align-avx-complete-objects.cpp b/clang/test/CodeGenCXX/align-avx-complete-objects.cpp index 2c3df4b48674822112c59d3f4423db332b8bf1e9..6477da5138b93b4b1106fe1c2ac8117318216ede 100644 --- a/clang/test/CodeGenCXX/align-avx-complete-objects.cpp +++ b/clang/test/CodeGenCXX/align-avx-complete-objects.cpp @@ -13,7 +13,7 @@ volatile float TestAlign(void) } // CHECK: [[R:%.*]] = alloca <8 x float>, align 32 -// CHECK-NEXT: [[CALL:%.*]] = call noalias noundef nonnull i8* @_Znwm(i64 noundef 32) +// CHECK-NEXT: [[CALL:%.*]] = call noalias nonnull i8* @_Znwm(i64 32) // CHECK-NEXT: [[ZERO:%.*]] = bitcast i8* [[CALL]] to <8 x float>* // CHECK-NEXT: store <8 x float>* [[ZERO]], <8 x float>** [[P:%.*]], align 8 // CHECK-NEXT: [[ONE:%.*]] = load <8 x float>*, <8 x float>** [[P]], align 8 @@ -42,7 +42,7 @@ volatile float TestAlign2(void) } // CHECK: [[R:%.*]] = alloca <8 x float>, align 32 -// CHECK-NEXT: [[CALL:%.*]] = call noalias noundef nonnull i8* @_Znwm(i64 noundef 32) +// CHECK-NEXT: [[CALL:%.*]] = call noalias nonnull i8* @_Znwm(i64 32) // CHECK-NEXT: [[ZERO:%.*]] = bitcast i8* [[CALL]] to <8 x float>* // CHECK-NEXT: store <8 x float>* [[ZERO]], <8 x float>** [[P:%.*]], align 8 // CHECK-NEXT: [[ONE:%.*]] = load <8 x float>*, <8 x float>** [[P]], align 8 diff --git a/clang/test/CodeGenCXX/alignment.cpp b/clang/test/CodeGenCXX/alignment.cpp index 51d45d4f9459e0f523fe5d5985624abb66a4afc3..c9378bf20a47c8b0aebb3b9d258abce5e7d3677e 100644 --- a/clang/test/CodeGenCXX/alignment.cpp +++ b/clang/test/CodeGenCXX/alignment.cpp @@ -24,7 +24,7 @@ namespace test0 { // in a reference with an assumed alignment of 4. // CHECK-LABEL: @_ZN5test01aERNS_1BE void a(B &b) { - // CHECK: [[CALL:%.*]] = call noundef i32 @_Z10int_sourcev() + // CHECK: [[CALL:%.*]] = call i32 @_Z10int_sourcev() // CHECK: [[B_P:%.*]] = load [[B:%.*]]*, [[B]]** // CHECK: [[FIELD_P:%.*]] = bitcast [[B]]* [[B_P]] to i8* // CHECK: [[TRUNC:%.*]] = trunc i32 [[CALL]] to i8 @@ -41,7 +41,7 @@ namespace test0 { // CHECK: [[T0:%.*]] = shl i8 [[VALUE]], 6 // CHECK: [[T1:%.*]] = ashr i8 [[T0]], 6 // CHECK: [[T2:%.*]] = sext i8 [[T1]] to i32 - // CHECK: call void @_Z8int_sinki(i32 noundef [[T2]]) + // CHECK: call void @_Z8int_sinki(i32 [[T2]]) int_sink(b.onebit); } @@ -49,7 +49,7 @@ namespace test0 { // in a reference/pointer with an assumed alignment of 2. // CHECK-LABEL: @_ZN5test01bERNS_1CE void b(C &c) { - // CHECK: [[CALL:%.*]] = call noundef i32 @_Z10int_sourcev() + // CHECK: [[CALL:%.*]] = call i32 @_Z10int_sourcev() // CHECK: [[C_P:%.*]] = load [[C:%.*]]*, [[C]]** // CHECK: [[T0:%.*]] = bitcast [[C]]* [[C_P]] to i8* // CHECK: [[T1:%.*]] = getelementptr inbounds i8, i8* [[T0]], i64 8 @@ -75,13 +75,13 @@ namespace test0 { // CHECK: [[T0:%.*]] = shl i8 [[VALUE]], 6 // CHECK: [[T1:%.*]] = ashr i8 [[T0]], 6 // CHECK: [[T2:%.*]] = sext i8 [[T1]] to i32 - // CHECK: call void @_Z8int_sinki(i32 noundef [[T2]]) + // CHECK: call void @_Z8int_sinki(i32 [[T2]]) int_sink(c.onebit); } // CHECK-LABEL: @_ZN5test01cEPNS_1CE void c(C *c) { - // CHECK: [[CALL:%.*]] = call noundef i32 @_Z10int_sourcev() + // CHECK: [[CALL:%.*]] = call i32 @_Z10int_sourcev() // CHECK: [[C_P:%.*]] = load [[C]]*, [[C]]** // CHECK: [[T0:%.*]] = bitcast [[C]]* [[C_P]] to i8* // CHECK: [[T1:%.*]] = getelementptr inbounds i8, i8* [[T0]], i64 8 @@ -107,7 +107,7 @@ namespace test0 { // CHECK: [[T0:%.*]] = shl i8 [[VALUE]], 6 // CHECK: [[T1:%.*]] = ashr i8 [[T0]], 6 // CHECK: [[T2:%.*]] = sext i8 [[T1]] to i32 - // CHECK: call void @_Z8int_sinki(i32 noundef [[T2]]) + // CHECK: call void @_Z8int_sinki(i32 [[T2]]) int_sink(c->onebit); } @@ -119,7 +119,7 @@ namespace test0 { // CHECK-NOCOMPAT: [[C_P:%.*]] = alloca [[C:%.*]], align 4 C c; - // CHECK: [[CALL:%.*]] = call noundef i32 @_Z10int_sourcev() + // CHECK: [[CALL:%.*]] = call i32 @_Z10int_sourcev() // CHECK: [[T0:%.*]] = bitcast [[C]]* [[C_P]] to i8* // CHECK: [[T1:%.*]] = getelementptr inbounds i8, i8* [[T0]], i64 8 // CHECK: [[B_P:%.*]] = bitcast i8* [[T1]] to [[B]]* @@ -143,7 +143,7 @@ namespace test0 { // CHECK: [[T0:%.*]] = shl i8 [[VALUE]], 6 // CHECK: [[T1:%.*]] = ashr i8 [[T0]], 6 // CHECK: [[T2:%.*]] = sext i8 [[T1]] to i32 - // CHECK: call void @_Z8int_sinki(i32 noundef [[T2]]) + // CHECK: call void @_Z8int_sinki(i32 [[T2]]) int_sink(c.onebit); } @@ -154,7 +154,7 @@ namespace test0 { // CHECK: [[C_P:%.*]] = alloca [[C:%.*]], align 16 __attribute__((aligned(16))) C c; - // CHECK: [[CALL:%.*]] = call noundef i32 @_Z10int_sourcev() + // CHECK: [[CALL:%.*]] = call i32 @_Z10int_sourcev() // CHECK: [[T0:%.*]] = bitcast [[C]]* [[C_P]] to i8* // CHECK: [[T1:%.*]] = getelementptr inbounds i8, i8* [[T0]], i64 8 // CHECK: [[B_P:%.*]] = bitcast i8* [[T1]] to [[B]]* @@ -175,7 +175,7 @@ namespace test0 { // CHECK: [[T0:%.*]] = shl i8 [[VALUE]], 6 // CHECK: [[T1:%.*]] = ashr i8 [[T0]], 6 // CHECK: [[T2:%.*]] = sext i8 [[T1]] to i32 - // CHECK: call void @_Z8int_sinki(i32 noundef [[T2]]) + // CHECK: call void @_Z8int_sinki(i32 [[T2]]) int_sink(c.onebit); } } diff --git a/clang/test/CodeGenCXX/alloc-size.cpp b/clang/test/CodeGenCXX/alloc-size.cpp index af64cff03394935f5e542a980975bea965288702..382caace7a5e7d0259448bae8b1b1544be49227f 100644 --- a/clang/test/CodeGenCXX/alloc-size.cpp +++ b/clang/test/CodeGenCXX/alloc-size.cpp @@ -14,12 +14,12 @@ template int callCalloc(); // CHECK-LABEL: define{{.*}} i32 @_ZN9templates6testItEv() int testIt() { - // CHECK: call noundef i32 @_ZN9templates10callMallocINS_6MyTypeEEEiv - // CHECK: call noundef i32 @_ZN9templates10callCallocINS_6MyTypeELi4EEEiv + // CHECK: call i32 @_ZN9templates10callMallocINS_6MyTypeEEEiv + // CHECK: call i32 @_ZN9templates10callCallocINS_6MyTypeELi4EEEiv return callMalloc() + callCalloc(); } -// CHECK-LABEL: define linkonce_odr noundef i32 +// CHECK-LABEL: define linkonce_odr i32 // @_ZN9templates10callMallocINS_6MyTypeEEEiv template int callMalloc() { static_assert(sizeof(T) == 16, ""); @@ -27,7 +27,7 @@ template int callMalloc() { return __builtin_object_size(my_malloc(sizeof(T)), 0); } -// CHECK-LABEL: define linkonce_odr noundef i32 +// CHECK-LABEL: define linkonce_odr i32 // @_ZN9templates10callCallocINS_6MyTypeELi4EEEiv template int callCalloc() { static_assert(sizeof(T) * N == 64, ""); @@ -59,7 +59,7 @@ template void *dependent_calloc2(size_t NT = sizeof(T), size_t MT = M) __attribute__((alloc_size(1, 2))); -// CHECK-LABEL: define{{.*}} noundef i32 @_ZN20templated_alloc_size6testItEv +// CHECK-LABEL: define{{.*}} i32 @_ZN20templated_alloc_size6testItEv int testIt() { // 122 = 4 + 5*4 + 6 + 7*8 + 4*9 // CHECK: ret i32 122 @@ -79,7 +79,7 @@ struct Foo { void *my_malloc(const Foo &, int N) __attribute__((alloc_size(2))); -// CHECK-LABEL: define{{.*}} noundef i32 @_ZN24alloc_size_with_cleanups6testItEv +// CHECK-LABEL: define{{.*}} i32 @_ZN24alloc_size_with_cleanups6testItEv int testIt() { int *const p = (int *)my_malloc(Foo{}, 3); // CHECK: ret i32 3 @@ -93,13 +93,13 @@ public: void *my_calloc(int N, int M) __attribute__((alloc_size(2, 3))); }; -// CHECK-LABEL: define{{.*}} noundef i32 @_Z16callMemberMallocv +// CHECK-LABEL: define{{.*}} i32 @_Z16callMemberMallocv int callMemberMalloc() { // CHECK: ret i32 16 return __builtin_object_size(C().my_malloc(16), 0); } -// CHECK-LABEL: define{{.*}} noundef i32 @_Z16callMemberCallocv +// CHECK-LABEL: define{{.*}} i32 @_Z16callMemberCallocv int callMemberCalloc() { // CHECK: ret i32 32 return __builtin_object_size(C().my_calloc(16, 2), 0); diff --git a/clang/test/CodeGenCXX/amdgcn-automatic-variable.cpp b/clang/test/CodeGenCXX/amdgcn-automatic-variable.cpp index 00de168673861f02eb842619c49a0690ac704abc..16eb318cd4f608953b79e8da2da5001a9fdf9a5c 100644 --- a/clang/test/CodeGenCXX/amdgcn-automatic-variable.cpp +++ b/clang/test/CodeGenCXX/amdgcn-automatic-variable.cpp @@ -35,7 +35,7 @@ void func1(int *x) { // CHECK-NEXT: store i32* [[LV1_ASCAST]], i32** [[LP1_ASCAST]], align 8 // CHECK-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* [[LA_ASCAST]], i64 0, i64 0 // CHECK-NEXT: store i32* [[ARRAYDECAY]], i32** [[LP2_ASCAST]], align 8 -// CHECK-NEXT: call void @_Z5func1Pi(i32* noundef [[LV1_ASCAST]]) +// CHECK-NEXT: call void @_Z5func1Pi(i32* [[LV1_ASCAST]]) // CHECK-NEXT: store i32 4, i32* [[LVC_ASCAST]], align 4 // CHECK-NEXT: store i32 4, i32* [[LV1_ASCAST]], align 4 // CHECK-NEXT: ret void @@ -74,8 +74,8 @@ public: // CHECK-NEXT: entry: // CHECK-NEXT: [[A:%.*]] = alloca [[CLASS_A:%.*]], align 4, addrspace(5) // CHECK-NEXT: [[A_ASCAST:%.*]] = addrspacecast [[CLASS_A]] addrspace(5)* [[A]] to %class.A* -// CHECK-NEXT: call void @_ZN1AC1Ev(%class.A* noundef [[A_ASCAST]]) -// CHECK-NEXT: call void @_ZN1AD1Ev(%class.A* noundef [[A_ASCAST]]) +// CHECK-NEXT: call void @_ZN1AC1Ev(%class.A* nonnull align 4 dereferenceable(4) [[A_ASCAST]]) +// CHECK-NEXT: call void @_ZN1AD1Ev(%class.A* nonnull align 4 dereferenceable(4) [[A_ASCAST]]) // CHECK-NEXT: ret void // void func3() { @@ -87,7 +87,7 @@ void func3() { // CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[X_ADDR_ASCAST:%.*]] = addrspacecast i32 addrspace(5)* [[X_ADDR]] to i32* // CHECK-NEXT: store i32 [[X:%.*]], i32* [[X_ADDR_ASCAST]], align 4 -// CHECK-NEXT: call void @_Z5func1Pi(i32* noundef [[X_ADDR_ASCAST]]) +// CHECK-NEXT: call void @_Z5func1Pi(i32* [[X_ADDR_ASCAST]]) // CHECK-NEXT: ret void // void func4(int x) { @@ -123,7 +123,7 @@ extern void use(int *); // CHECK-NEXT: [[X_ASCAST:%.*]] = addrspacecast i32 addrspace(5)* [[X]] to i32* // CHECK-NEXT: br label [[LATER:%.*]] // CHECK: later: -// CHECK-NEXT: call void @_Z3usePi(i32* noundef [[X_ASCAST]]) +// CHECK-NEXT: call void @_Z3usePi(i32* [[X_ASCAST]]) // CHECK-NEXT: ret void // void func7() { diff --git a/clang/test/CodeGenCXX/amdgcn-func-arg.cpp b/clang/test/CodeGenCXX/amdgcn-func-arg.cpp index 4799059f21ff0b2bcee652cfb31ae480d5a954bd..782ce83327500e64868adb4f1790862fdfb1cfe1 100644 --- a/clang/test/CodeGenCXX/amdgcn-func-arg.cpp +++ b/clang/test/CodeGenCXX/amdgcn-func-arg.cpp @@ -36,15 +36,15 @@ void func_with_indirect_arg(A a) { // CHECK-NEXT: [[A_ASCAST:%.*]] = addrspacecast [[CLASS_A]] addrspace(5)* [[A]] to %class.A* // CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_A]], align 4, addrspace(5) // CHECK-NEXT: [[AGG_TMP_ASCAST:%.*]] = addrspacecast [[CLASS_A]] addrspace(5)* [[AGG_TMP]] to %class.A* -// CHECK-NEXT: call void @_ZN1AC1Ev(%class.A* noundef [[A_ASCAST]]) +// CHECK-NEXT: call void @_ZN1AC1Ev(%class.A* nonnull align 4 dereferenceable(4) [[A_ASCAST]]) // CHECK-NEXT: [[TMP0:%.*]] = bitcast %class.A* [[AGG_TMP_ASCAST]] to i8* // CHECK-NEXT: [[TMP1:%.*]] = bitcast %class.A* [[A_ASCAST]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 [[TMP1]], i64 4, i1 false) // CHECK-NEXT: [[AGG_TMP_ASCAST_ASCAST:%.*]] = addrspacecast %class.A* [[AGG_TMP_ASCAST]] to [[CLASS_A]] addrspace(5)* -// CHECK-NEXT: call void @_Z22func_with_indirect_arg1A([[CLASS_A]] addrspace(5)* noundef [[AGG_TMP_ASCAST_ASCAST]]) -// CHECK-NEXT: call void @_ZN1AD1Ev(%class.A* noundef [[AGG_TMP_ASCAST]]) -// CHECK-NEXT: call void @_Z17func_with_ref_argR1A(%class.A* noundef nonnull align 4 dereferenceable(4) [[A_ASCAST]]) -// CHECK-NEXT: call void @_ZN1AD1Ev(%class.A* noundef [[A_ASCAST]]) +// CHECK-NEXT: call void @_Z22func_with_indirect_arg1A([[CLASS_A]] addrspace(5)* [[AGG_TMP_ASCAST_ASCAST]]) +// CHECK-NEXT: call void @_ZN1AD1Ev(%class.A* nonnull align 4 dereferenceable(4) [[AGG_TMP_ASCAST]]) +// CHECK-NEXT: call void @_Z17func_with_ref_argR1A(%class.A* nonnull align 4 dereferenceable(4) [[A_ASCAST]]) +// CHECK-NEXT: call void @_ZN1AD1Ev(%class.A* nonnull align 4 dereferenceable(4) [[A_ASCAST]]) // CHECK-NEXT: ret void // void test_indirect_arg_auto() { @@ -60,9 +60,9 @@ void test_indirect_arg_auto() { // CHECK-NEXT: [[TMP0:%.*]] = bitcast %class.A* [[AGG_TMP_ASCAST]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 addrspacecast (i8 addrspace(1)* bitcast ([[CLASS_A]] addrspace(1)* @g_a to i8 addrspace(1)*) to i8*), i64 4, i1 false) // CHECK-NEXT: [[AGG_TMP_ASCAST_ASCAST:%.*]] = addrspacecast %class.A* [[AGG_TMP_ASCAST]] to [[CLASS_A]] addrspace(5)* -// CHECK-NEXT: call void @_Z22func_with_indirect_arg1A([[CLASS_A]] addrspace(5)* noundef [[AGG_TMP_ASCAST_ASCAST]]) -// CHECK-NEXT: call void @_ZN1AD1Ev(%class.A* noundef [[AGG_TMP_ASCAST]]) -// CHECK-NEXT: call void @_Z17func_with_ref_argR1A(%class.A* noundef nonnull align 4 dereferenceable(4) addrspacecast ([[CLASS_A]] addrspace(1)* @g_a to %class.A*)) +// CHECK-NEXT: call void @_Z22func_with_indirect_arg1A([[CLASS_A]] addrspace(5)* [[AGG_TMP_ASCAST_ASCAST]]) +// CHECK-NEXT: call void @_ZN1AD1Ev(%class.A* nonnull align 4 dereferenceable(4) [[AGG_TMP_ASCAST]]) +// CHECK-NEXT: call void @_Z17func_with_ref_argR1A(%class.A* nonnull align 4 dereferenceable(4) addrspacecast ([[CLASS_A]] addrspace(1)* @g_a to %class.A*)) // CHECK-NEXT: ret void // void test_indirect_arg_global() { @@ -92,8 +92,8 @@ void func_with_byval_arg(B b) { // CHECK-NEXT: [[TMP1:%.*]] = bitcast %class.B* [[B_ASCAST]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 [[TMP1]], i64 400, i1 false) // CHECK-NEXT: [[AGG_TMP_ASCAST_ASCAST:%.*]] = addrspacecast %class.B* [[AGG_TMP_ASCAST]] to [[CLASS_B]] addrspace(5)* -// CHECK-NEXT: call void @_Z19func_with_byval_arg1B([[CLASS_B]] addrspace(5)* noundef byval([[CLASS_B]]) align 4 [[AGG_TMP_ASCAST_ASCAST]]) -// CHECK-NEXT: call void @_Z17func_with_ref_argR1B(%class.B* noundef nonnull align 4 dereferenceable(400) [[B_ASCAST]]) +// CHECK-NEXT: call void @_Z19func_with_byval_arg1B([[CLASS_B]] addrspace(5)* byval([[CLASS_B]]) align 4 [[AGG_TMP_ASCAST_ASCAST]]) +// CHECK-NEXT: call void @_Z17func_with_ref_argR1B(%class.B* nonnull align 4 dereferenceable(400) [[B_ASCAST]]) // CHECK-NEXT: ret void // void test_byval_arg_auto() { @@ -109,8 +109,8 @@ void test_byval_arg_auto() { // CHECK-NEXT: [[TMP0:%.*]] = bitcast %class.B* [[AGG_TMP_ASCAST]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 addrspacecast (i8 addrspace(1)* bitcast ([[CLASS_B]] addrspace(1)* @g_b to i8 addrspace(1)*) to i8*), i64 400, i1 false) // CHECK-NEXT: [[AGG_TMP_ASCAST_ASCAST:%.*]] = addrspacecast %class.B* [[AGG_TMP_ASCAST]] to [[CLASS_B]] addrspace(5)* -// CHECK-NEXT: call void @_Z19func_with_byval_arg1B([[CLASS_B]] addrspace(5)* noundef byval([[CLASS_B]]) align 4 [[AGG_TMP_ASCAST_ASCAST]]) -// CHECK-NEXT: call void @_Z17func_with_ref_argR1B(%class.B* noundef nonnull align 4 dereferenceable(400) addrspacecast ([[CLASS_B]] addrspace(1)* @g_b to %class.B*)) +// CHECK-NEXT: call void @_Z19func_with_byval_arg1B([[CLASS_B]] addrspace(5)* byval([[CLASS_B]]) align 4 [[AGG_TMP_ASCAST_ASCAST]]) +// CHECK-NEXT: call void @_Z17func_with_ref_argR1B(%class.B* nonnull align 4 dereferenceable(400) addrspacecast ([[CLASS_B]] addrspace(1)* @g_b to %class.B*)) // CHECK-NEXT: ret void // void test_byval_arg_global() { diff --git a/clang/test/CodeGenCXX/amdgcn_declspec_get.cpp b/clang/test/CodeGenCXX/amdgcn_declspec_get.cpp index 07026e9450ab487b88c7668eeb371e2aba87f387..a49d7214be217eec455ce9abc693483fbfdc8e03 100644 --- a/clang/test/CodeGenCXX/amdgcn_declspec_get.cpp +++ b/clang/test/CodeGenCXX/amdgcn_declspec_get.cpp @@ -17,7 +17,7 @@ extern const A a; // CHECK: %[[ii:.*]] = addrspacecast i32 addrspace(5)* %i to i32* // CHECK: %[[cast:.*]] = bitcast i32 addrspace(5)* %i to i8 addrspace(5)* // CHECK: call void @llvm.lifetime.start.p5i8(i64 4, i8 addrspace(5)* %[[cast]]) -// CHECK: %call = call noundef i32 @_ZN1A6_get_xEv() +// CHECK: %call = call i32 @_ZN1A6_get_xEv() // CHECK: store i32 %call, i32* %[[ii]] // CHECK: %[[cast2:.*]] = bitcast i32 addrspace(5)* %i to i8 addrspace(5)* // CHECK: call void @llvm.lifetime.end.p5i8(i64 4, i8 addrspace(5)* %[[cast2]]) diff --git a/clang/test/CodeGenCXX/anonymous-namespaces.cpp b/clang/test/CodeGenCXX/anonymous-namespaces.cpp index f40039c2a4f40066a1da307ef59dfb2861943831..429e73b8f9dc0d6e0fe99384c81cae9064c79a6f 100644 --- a/clang/test/CodeGenCXX/anonymous-namespaces.cpp +++ b/clang/test/CodeGenCXX/anonymous-namespaces.cpp @@ -35,12 +35,12 @@ namespace { struct E : public virtual EBase { virtual ~E() {} }; }; - // CHECK-1-LABEL: define internal noundef i32 @_ZN12_GLOBAL__N_13fooEv() + // CHECK-1-LABEL: define internal i32 @_ZN12_GLOBAL__N_13fooEv() int foo() { return 32; } - // CHECK-1-LABEL: define internal noundef i32 @_ZN12_GLOBAL__N_11A3fooEv() + // CHECK-1-LABEL: define internal i32 @_ZN12_GLOBAL__N_11A3fooEv() namespace A { int foo() { return 45; diff --git a/clang/test/CodeGenCXX/apple-kext-indirect-call-2.cpp b/clang/test/CodeGenCXX/apple-kext-indirect-call-2.cpp index 21045140803810ef443bc9917555f785c230eeca..b6d26259afc631c3658092586a8a73b6f3d10575 100644 --- a/clang/test/CodeGenCXX/apple-kext-indirect-call-2.cpp +++ b/clang/test/CodeGenCXX/apple-kext-indirect-call-2.cpp @@ -19,7 +19,7 @@ void B::VF() {} void FUNC(B* p) { // CHECK: [[T1:%.*]] = load i8* (%struct.A*)*, i8* (%struct.A*)** getelementptr inbounds (i8* (%struct.A*)*, i8* (%struct.A*)** bitcast ({ [4 x i8*] }* @_ZTV1A to i8* (%struct.A*)**), i64 2) -// CHECK-NEXT: [[T2:%.*]] = call noundef i8* [[T1]] +// CHECK-NEXT: [[T2:%.*]] = call i8* [[T1]] const char* c = p->A::abc(); } @@ -34,7 +34,7 @@ struct Derived : public Base { void FUNC1(Derived* p) { // CHECK: [[U1:%.*]] = load i8* (%struct.Base*)*, i8* (%struct.Base*)** getelementptr inbounds (i8* (%struct.Base*)*, i8* (%struct.Base*)** bitcast ({ [4 x i8*] }* @_ZTV4Base to i8* (%struct.Base*)**), i64 2) -// CHECK-NEXT: [[U2:%.*]] = call noundef i8* [[U1]] +// CHECK-NEXT: [[U2:%.*]] = call i8* [[U1]] char* c = p->Base::abc(); } @@ -50,7 +50,7 @@ char* Derived2::efg(void) const { return 0; } void FUNC2(Derived2* p) { // CHECK: [[V1:%.*]] = load i8* (%struct.Derived2*)*, i8* (%struct.Derived2*)** getelementptr inbounds (i8* (%struct.Derived2*)*, i8* (%struct.Derived2*)** bitcast ({ [5 x i8*] }* @_ZTV8Derived2 to i8* (%struct.Derived2*)**), i64 3) -// CHECK-NEXT: [[V2:%.*]] = call noundef i8* [[V1]] +// CHECK-NEXT: [[V2:%.*]] = call i8* [[V1]] char* c = p->Derived2::efg(); } @@ -71,7 +71,7 @@ char* D2::abc(void) const { return 0; } void FUNC3(Sub* p) { // CHECK: [[W1:%.*]] = load i8* (%struct.D2*)*, i8* (%struct.D2*)** getelementptr inbounds (i8* (%struct.D2*)*, i8* (%struct.D2*)** bitcast ({ [5 x i8*] }* @_ZTV2D2 to i8* (%struct.D2*)**), i64 3) -// CHECK-NEXT: [[W2:%.*]] = call noundef i8* [[W1]] +// CHECK-NEXT: [[W2:%.*]] = call i8* [[W1]] char* c = p->D2::abc(); } diff --git a/clang/test/CodeGenCXX/apple-kext-linkage.cpp b/clang/test/CodeGenCXX/apple-kext-linkage.cpp index 8e76084980d4d53875bd0c23ecbdd3aaa765c342..8e020944240f0ec4c6774116769cc4fcff48236c 100644 --- a/clang/test/CodeGenCXX/apple-kext-linkage.cpp +++ b/clang/test/CodeGenCXX/apple-kext-linkage.cpp @@ -13,7 +13,7 @@ void foo() { Derived d1; // ok } -// CHECK-LABEL: define internal noundef i32 @_Z1fj( +// CHECK-LABEL: define internal i32 @_Z1fj( inline unsigned f(unsigned n) { return n == 0 ? 0 : n + f(n-1); } unsigned g(unsigned n) { return f(n); } @@ -23,7 +23,7 @@ unsigned g(unsigned n) { return f(n); } template void bar() {} template void bar(); -// CHECK-LABEL: define internal noundef i32 @_Z5identIiET_S0_( +// CHECK-LABEL: define internal i32 @_Z5identIiET_S0_( template X ident(X x) { return x; } int foo(int n) { return ident(n); } diff --git a/clang/test/CodeGenCXX/arm-cc.cpp b/clang/test/CodeGenCXX/arm-cc.cpp index 47a8ffe62518b638b1fa42b1709d69a11f04bd3f..0d8033570c423b210234a9c77177e2e0ac21c815 100644 --- a/clang/test/CodeGenCXX/arm-cc.cpp +++ b/clang/test/CodeGenCXX/arm-cc.cpp @@ -16,5 +16,5 @@ void baz() { zed(a); } -// CHECK: declare void @_Z3fooPv(%class.SMLoc* sret(%class.SMLoc) align 4, i8* noundef) -// CHECK: declare void @_Z3zed5SMLoc(%class.SMLoc* noundef) +// CHECK: declare void @_Z3fooPv(%class.SMLoc* sret(%class.SMLoc) align 4, i8*) +// CHECK: declare void @_Z3zed5SMLoc(%class.SMLoc*) diff --git a/clang/test/CodeGenCXX/arm-swiftcall.cpp b/clang/test/CodeGenCXX/arm-swiftcall.cpp index 7393d7e705e7f46801f92773ef55175553c83bc1..2cad9af2e5d89993ae1c7975b6d5f046209d7a8f 100644 --- a/clang/test/CodeGenCXX/arm-swiftcall.cpp +++ b/clang/test/CodeGenCXX/arm-swiftcall.cpp @@ -112,7 +112,7 @@ TEST(struct_indirect_1) // CHECK-LABEL: define {{.*}} void @return_struct_indirect_1({{.*}} noalias sret // Should not be byval. -// CHECK-LABEL: define {{.*}} void @take_struct_indirect_1({{.*}}* noundef{{( %.*)?}}) +// CHECK-LABEL: define {{.*}} void @take_struct_indirect_1({{.*}}*{{( %.*)?}}) // Do a simple standalone test here of a function definition to ensure that // we don't have problems due to failure to eagerly synthesize a copy diff --git a/clang/test/CodeGenCXX/arm.cpp b/clang/test/CodeGenCXX/arm.cpp index 252880664dfa67b1ece85b0c5c7abf591ca0e177..746cde6b313641bb7db35162d2cbd58cd9cfb46c 100644 --- a/clang/test/CodeGenCXX/arm.cpp +++ b/clang/test/CodeGenCXX/arm.cpp @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -disable-noundef-analysis %s -triple=thumbv7-apple-ios6.0 -fno-use-cxa-atexit -target-abi apcs-gnu -emit-llvm -std=gnu++98 -o - -fexceptions | FileCheck -check-prefix=CHECK -check-prefix=CHECK98 %s -// RUN: %clang_cc1 -disable-noundef-analysis %s -triple=thumbv7-apple-ios6.0 -fno-use-cxa-atexit -target-abi apcs-gnu -emit-llvm -std=gnu++11 -o - -fexceptions | FileCheck -check-prefix=CHECK -check-prefix=CHECK11 %s +// RUN: %clang_cc1 %s -triple=thumbv7-apple-ios6.0 -fno-use-cxa-atexit -target-abi apcs-gnu -emit-llvm -std=gnu++98 -o - -fexceptions | FileCheck -check-prefix=CHECK -check-prefix=CHECK98 %s +// RUN: %clang_cc1 %s -triple=thumbv7-apple-ios6.0 -fno-use-cxa-atexit -target-abi apcs-gnu -emit-llvm -std=gnu++11 -o - -fexceptions | FileCheck -check-prefix=CHECK -check-prefix=CHECK11 %s // CHECK: @_ZZN5test74testEvE1x = internal global i32 0, align 4 // CHECK: @_ZGVZN5test74testEvE1x = internal global i32 0 diff --git a/clang/test/CodeGenCXX/arm64-constructor-return.cpp b/clang/test/CodeGenCXX/arm64-constructor-return.cpp index 00638f5f972fec973e5470f652a2d96a03041e6e..5365db8c4441211d71ad3b04c08f5ea980c5dd96 100644 --- a/clang/test/CodeGenCXX/arm64-constructor-return.cpp +++ b/clang/test/CodeGenCXX/arm64-constructor-return.cpp @@ -10,9 +10,9 @@ S::S() { iField = 1; }; -// CHECK: %struct.S* @_ZN1SC2Ev(%struct.S* {{[^,]*}} %this) +// CHECK: %struct.S* @_ZN1SC2Ev(%struct.S* {{[^,]*}} returned {{[^,]*}} %this) -// CHECK: %struct.S* @_ZN1SC1Ev(%struct.S* {{[^,]*}} returned %this) +// CHECK: %struct.S* @_ZN1SC1Ev(%struct.S* {{[^,]*}} returned {{[^,]*}} %this) // CHECK: [[THISADDR:%[a-zA-Z0-9.]+]] = alloca %struct.S* // CHECK: store %struct.S* %this, %struct.S** [[THISADDR]] // CHECK: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THISADDR]] diff --git a/clang/test/CodeGenCXX/arm64-darwinpcs.cpp b/clang/test/CodeGenCXX/arm64-darwinpcs.cpp index a0b0d9efdd4c4f751924eee2132dba346df98424..8592740942b651b6d808e2d76abb2076abad687a 100644 --- a/clang/test/CodeGenCXX/arm64-darwinpcs.cpp +++ b/clang/test/CodeGenCXX/arm64-darwinpcs.cpp @@ -2,8 +2,8 @@ // RUN: %clang_cc1 -triple arm64-linux-gnu -emit-llvm -o - %s -target-abi darwinpcs | FileCheck %s --check-prefix=CHECK-DARWIN void test_extensions(bool a, char b, short c) {} -// CHECK: define{{.*}} void @_Z15test_extensionsbcs(i1 noundef %a, i8 noundef %b, i16 noundef %c) -// CHECK-DARWIN: define{{.*}} void @_Z15test_extensionsbcs(i1 noundef zeroext %a, i8 noundef signext %b, i16 noundef signext %c) +// CHECK: define{{.*}} void @_Z15test_extensionsbcs(i1 %a, i8 %b, i16 %c) +// CHECK-DARWIN: define{{.*}} void @_Z15test_extensionsbcs(i1 zeroext %a, i8 signext %b, i16 signext %c) struct Empty {}; void test_empty(Empty e) {} diff --git a/clang/test/CodeGenCXX/atomic-dllexport.cpp b/clang/test/CodeGenCXX/atomic-dllexport.cpp index a961f1a30432ba5798d57831ce7f6230ed70af62..3a100ac2aa61a982e6212dde89436296cbc514a8 100644 --- a/clang/test/CodeGenCXX/atomic-dllexport.cpp +++ b/clang/test/CodeGenCXX/atomic-dllexport.cpp @@ -3,7 +3,7 @@ struct __declspec(dllexport) SomeStruct { // Copy assignment operator should be produced, and exported: - // M32: define weak_odr dso_local dllexport x86_thiscallcc noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.SomeStruct* @"??4SomeStruct@@QAEAAU0@ABU0@@Z" - // M64: define weak_odr dso_local dllexport noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.SomeStruct* @"??4SomeStruct@@QEAAAEAU0@AEBU0@@Z" + // M32: define weak_odr dso_local dllexport x86_thiscallcc nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.SomeStruct* @"??4SomeStruct@@QAEAAU0@ABU0@@Z" + // M64: define weak_odr dso_local dllexport nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.SomeStruct* @"??4SomeStruct@@QEAAAEAU0@AEBU0@@Z" _Atomic(int) mData; }; diff --git a/clang/test/CodeGenCXX/atomic-inline.cpp b/clang/test/CodeGenCXX/atomic-inline.cpp index d71734a6698188744d82904a3fa2fd59010a9505..b8c3fc880d9b8dc615612ab2f8ddbacc3fb33d81 100644 --- a/clang/test/CodeGenCXX/atomic-inline.cpp +++ b/clang/test/CodeGenCXX/atomic-inline.cpp @@ -61,7 +61,7 @@ void store16() { bool cmpxchg16() { AM16 am; // CHECK-LABEL: @_Z9cmpxchg16v - // CHECK: call noundef zeroext i1 @__atomic_compare_exchange + // CHECK: call zeroext i1 @__atomic_compare_exchange // CORE2-LABEL: @_Z9cmpxchg16v // CORE2: cmpxchg i128* {{.*}} monotonic monotonic, align 16 return __atomic_compare_exchange(&m16, &s16, &am, 0, 0, 0); diff --git a/clang/test/CodeGenCXX/atomicinit.cpp b/clang/test/CodeGenCXX/atomicinit.cpp index fd452f80b1b28d5b668f10dba2e6bf88cab35e58..8b2bec2fbbdf98bbfa0f86272f8755c2bc53884d 100644 --- a/clang/test/CodeGenCXX/atomicinit.cpp +++ b/clang/test/CodeGenCXX/atomicinit.cpp @@ -65,15 +65,15 @@ namespace PR18097 { }; // CHECK-LABEL: define {{.*}} @__cxx_global_var_init - // CHECK: call void @_ZN7PR180977dynamic1XC1Ei({{.*}}* noundef {{[^,]*}} @_ZN7PR180977dynamic1aE, i32 noundef 1) + // CHECK: call void @_ZN7PR180977dynamic1XC1Ei({{.*}}* nonnull {{[^,]*}} @_ZN7PR180977dynamic1aE, i32 1) _Atomic(X) a = X(1); // CHECK-LABEL: define {{.*}} @__cxx_global_var_init - // CHECK: call void @_ZN7PR180977dynamic1XC1Ei({{.*}}* noundef {{[^,]*}} @_ZN7PR180977dynamic1bE, i32 noundef 2) + // CHECK: call void @_ZN7PR180977dynamic1XC1Ei({{.*}}* nonnull {{[^,]*}} @_ZN7PR180977dynamic1bE, i32 2) _Atomic(X) b(X(2)); // CHECK-LABEL: define {{.*}} @__cxx_global_var_init - // CHECK: call void @_ZN7PR180977dynamic1XC1Ei({{.*}}* noundef {{[^,]*}} @_ZN7PR180977dynamic1cE, i32 noundef 3) + // CHECK: call void @_ZN7PR180977dynamic1XC1Ei({{.*}}* nonnull {{[^,]*}} @_ZN7PR180977dynamic1cE, i32 3) _Atomic(X) c{X(3)}; struct Y { @@ -81,7 +81,7 @@ namespace PR18097 { _Atomic(int) b; }; // CHECK-LABEL: define {{.*}} @__cxx_global_var_init - // CHECK: call void @_ZN7PR180977dynamic1XC1Ei({{.*}}* {{[^,]*}} getelementptr inbounds ({{.*}}, {{.*}}* @_ZN7PR180977dynamic1yE, i32 0, i32 0), i32 noundef 4) + // CHECK: call void @_ZN7PR180977dynamic1XC1Ei({{.*}}* {{[^,]*}} getelementptr inbounds ({{.*}}, {{.*}}* @_ZN7PR180977dynamic1yE, i32 0, i32 0), i32 4) // CHECK: store i32 5, i32* getelementptr inbounds ({{.*}}, {{.*}}* @_ZN7PR180977dynamic1yE, i32 0, i32 1) Y y = { X(4), 5 }; } diff --git a/clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp b/clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp index bfb0f1fa9edc651118f2e701da0915d6ad2e9043..a34a0b88e2814227b6d61bbead91012679cba03b 100644 --- a/clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp +++ b/clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp @@ -47,51 +47,51 @@ OutOfLineDefs::foo(int, int, int) { // LINUX: @_ZN13OutOfLineDefs3fooEiii.ifunc = weak_odr ifunc i32 (%struct.OutOfLineDefs*, i32, i32, i32), i32 (%struct.OutOfLineDefs*, i32, i32, i32)* ()* @_ZN13OutOfLineDefs3fooEiii.resolver // Arity 1 version: -// LINUX: define dso_local noundef i32 @_ZN13OutOfLineDefs3fooEi.O -// LINUX: define dso_local noundef i32 @_ZN13OutOfLineDefs3fooEi.S +// LINUX: define dso_local i32 @_ZN13OutOfLineDefs3fooEi.O +// LINUX: define dso_local i32 @_ZN13OutOfLineDefs3fooEi.S // LINUX: define weak_odr i32 (%struct.OutOfLineDefs*, i32)* @_ZN13OutOfLineDefs3fooEi.resolver() // LINUX: ret i32 (%struct.OutOfLineDefs*, i32)* @_ZN13OutOfLineDefs3fooEi.S // LINUX: ret i32 (%struct.OutOfLineDefs*, i32)* @_ZN13OutOfLineDefs3fooEi.O // LINUX: call void @llvm.trap -// WINDOWS: define dso_local noundef i32 @"?foo@OutOfLineDefs@@QEAAHH@Z.O" -// WINDOWS: define dso_local noundef i32 @"?foo@OutOfLineDefs@@QEAAHH@Z.S" +// WINDOWS: define dso_local i32 @"?foo@OutOfLineDefs@@QEAAHH@Z.O" +// WINDOWS: define dso_local i32 @"?foo@OutOfLineDefs@@QEAAHH@Z.S" // WINDOWS: define weak_odr dso_local i32 @"?foo@OutOfLineDefs@@QEAAHH@Z"(%struct.OutOfLineDefs* %0, i32 %1) // WINDOWS: musttail call i32 @"?foo@OutOfLineDefs@@QEAAHH@Z.S"(%struct.OutOfLineDefs* %0, i32 %1) // WINDOWS: musttail call i32 @"?foo@OutOfLineDefs@@QEAAHH@Z.O"(%struct.OutOfLineDefs* %0, i32 %1) // WINDOWS: call void @llvm.trap // Arity 2 version: -// LINUX: define dso_local noundef i32 @_ZN13OutOfLineDefs3fooEii.O -// LINUX: define dso_local noundef i32 @_ZN13OutOfLineDefs3fooEii.S +// LINUX: define dso_local i32 @_ZN13OutOfLineDefs3fooEii.O +// LINUX: define dso_local i32 @_ZN13OutOfLineDefs3fooEii.S // LINUX: define weak_odr i32 (%struct.OutOfLineDefs*, i32, i32)* @_ZN13OutOfLineDefs3fooEii.resolver() // LINUX: ret i32 (%struct.OutOfLineDefs*, i32, i32)* @_ZN13OutOfLineDefs3fooEii.S // LINUX: ret i32 (%struct.OutOfLineDefs*, i32, i32)* @_ZN13OutOfLineDefs3fooEii.O // LINUX: call void @llvm.trap -// WINDOWS: define dso_local noundef i32 @"?foo@OutOfLineDefs@@QEAAHHH@Z.O" -// WINDOWS: define dso_local noundef i32 @"?foo@OutOfLineDefs@@QEAAHHH@Z.S" +// WINDOWS: define dso_local i32 @"?foo@OutOfLineDefs@@QEAAHHH@Z.O" +// WINDOWS: define dso_local i32 @"?foo@OutOfLineDefs@@QEAAHHH@Z.S" // WINDOWS: define weak_odr dso_local i32 @"?foo@OutOfLineDefs@@QEAAHHH@Z"(%struct.OutOfLineDefs* %0, i32 %1, i32 %2) // WINDOWS: musttail call i32 @"?foo@OutOfLineDefs@@QEAAHHH@Z.S"(%struct.OutOfLineDefs* %0, i32 %1, i32 %2) // WINDOWS: musttail call i32 @"?foo@OutOfLineDefs@@QEAAHHH@Z.O"(%struct.OutOfLineDefs* %0, i32 %1, i32 %2) // WINDOWS: call void @llvm.trap // Arity 3 version: -// LINUX: define dso_local noundef i32 @_ZN13OutOfLineDefs3fooEiii.S -// LINUX: define dso_local noundef i32 @_ZN13OutOfLineDefs3fooEiii.R +// LINUX: define dso_local i32 @_ZN13OutOfLineDefs3fooEiii.S +// LINUX: define dso_local i32 @_ZN13OutOfLineDefs3fooEiii.R // LINUX: define weak_odr i32 (%struct.OutOfLineDefs*, i32, i32, i32)* @_ZN13OutOfLineDefs3fooEiii.resolver() // LINUX: ret i32 (%struct.OutOfLineDefs*, i32, i32, i32)* @_ZN13OutOfLineDefs3fooEiii.R // LINUX: ret i32 (%struct.OutOfLineDefs*, i32, i32, i32)* @_ZN13OutOfLineDefs3fooEiii.S // LINUX: ret i32 (%struct.OutOfLineDefs*, i32, i32, i32)* @_ZN13OutOfLineDefs3fooEiii.O // LINUX: call void @llvm.trap -// LINUX: define linkonce_odr noundef i32 @_ZN13OutOfLineDefs3fooEiii.O +// LINUX: define linkonce_odr i32 @_ZN13OutOfLineDefs3fooEiii.O -// WINDOWS: define dso_local noundef i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z.S" -// WINDOWS: define dso_local noundef i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z.R" +// WINDOWS: define dso_local i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z.S" +// WINDOWS: define dso_local i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z.R" // WINDOWS: define weak_odr dso_local i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z"(%struct.OutOfLineDefs* %0, i32 %1, i32 %2, i32 %3) // WINDOWS: musttail call i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z.R"(%struct.OutOfLineDefs* %0, i32 %1, i32 %2, i32 %3) // WINDOWS: musttail call i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z.S"(%struct.OutOfLineDefs* %0, i32 %1, i32 %2, i32 %3) // WINDOWS: musttail call i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z.O"(%struct.OutOfLineDefs* %0, i32 %1, i32 %2, i32 %3) // WINDOWS: call void @llvm.trap -// WINDOWS: define linkonce_odr dso_local noundef i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z.O" +// WINDOWS: define linkonce_odr dso_local i32 @"?foo@OutOfLineDefs@@QEAAHHHH@Z.O" diff --git a/clang/test/CodeGenCXX/attr-disable-tail-calls.cpp b/clang/test/CodeGenCXX/attr-disable-tail-calls.cpp index a70b08fea0ee370fd8215b56f6bc44f0488fceac..a7d28f2d009106329a9ab9bba2918f6fc228f665 100644 --- a/clang/test/CodeGenCXX/attr-disable-tail-calls.cpp +++ b/clang/test/CodeGenCXX/attr-disable-tail-calls.cpp @@ -23,12 +23,12 @@ int foo1() { return t; } -// CHECK: define linkonce_odr noundef i32 @_ZN1B2m3Ev(%class.B* {{[^,]*}} %this) [[ATTRFALSE:#[0-9]+]] -// CHECK: declare noundef i32 @_ZN1B2m4Ev(%class.B* {{[^,]*}}) [[ATTRTRUE0:#[0-9]+]] -// CHECK: define linkonce_odr noundef i32 @_ZN1B2m1Ev(%class.B* {{[^,]*}} %this) unnamed_addr [[ATTRTRUE1:#[0-9]+]] -// CHECK: define linkonce_odr noundef i32 @_ZN1B2m2Ev(%class.B* {{[^,]*}} %this) unnamed_addr [[ATTRFALSE:#[0-9]+]] -// CHECK: define linkonce_odr noundef i32 @_ZN1D2m1Ev(%class.D* {{[^,]*}} %this) unnamed_addr [[ATTRFALSE:#[0-9]+]] -// CHECK: define linkonce_odr noundef i32 @_ZN1D2m2Ev(%class.D* {{[^,]*}} %this) unnamed_addr [[ATTRTRUE1:#[0-9]+]] +// CHECK: define linkonce_odr i32 @_ZN1B2m3Ev(%class.B* {{[^,]*}} %this) [[ATTRFALSE:#[0-9]+]] +// CHECK: declare i32 @_ZN1B2m4Ev(%class.B* {{[^,]*}}) [[ATTRTRUE0:#[0-9]+]] +// CHECK: define linkonce_odr i32 @_ZN1B2m1Ev(%class.B* {{[^,]*}} %this) unnamed_addr [[ATTRTRUE1:#[0-9]+]] +// CHECK: define linkonce_odr i32 @_ZN1B2m2Ev(%class.B* {{[^,]*}} %this) unnamed_addr [[ATTRFALSE:#[0-9]+]] +// CHECK: define linkonce_odr i32 @_ZN1D2m1Ev(%class.D* {{[^,]*}} %this) unnamed_addr [[ATTRFALSE:#[0-9]+]] +// CHECK: define linkonce_odr i32 @_ZN1D2m2Ev(%class.D* {{[^,]*}} %this) unnamed_addr [[ATTRTRUE1:#[0-9]+]] // CHECK-NOT: attributes [[ATTRFALSE]] = { {{.*}}"disable-tail-calls"="false"{{.*}} } // CHECK: attributes [[ATTRTRUE0]] = { {{.*}}"disable-tail-calls"="true"{{.*}} } diff --git a/clang/test/CodeGenCXX/attr-musttail.cpp b/clang/test/CodeGenCXX/attr-musttail.cpp index 43c803c8742eee2b73575eeddba313703a5875e8..8f435eabab687bc4b4561ef7fd1c6c9fd7ee81b3 100644 --- a/clang/test/CodeGenCXX/attr-musttail.cpp +++ b/clang/test/CodeGenCXX/attr-musttail.cpp @@ -7,11 +7,11 @@ int Baz(int); int Func1(int x) { if (x) { - // CHECK: %call = musttail call noundef i32 @_Z3Bari(i32 noundef %1) + // CHECK: %call = musttail call i32 @_Z3Bari(i32 %1) // CHECK-NEXT: ret i32 %call [[clang::musttail]] return Bar(x); } else { - [[clang::musttail]] return Baz(x); // CHECK: %call1 = musttail call noundef i32 @_Z3Bazi(i32 noundef %3) + [[clang::musttail]] return Baz(x); // CHECK: %call1 = musttail call i32 @_Z3Bazi(i32 %3) } } @@ -21,7 +21,7 @@ int Func2(int x) { } } -// CHECK: %call1 = musttail call noundef i32 @_Z3Bari(i32 noundef %call) +// CHECK: %call1 = musttail call i32 @_Z3Bari(i32 %call) class Foo { public: @@ -36,20 +36,20 @@ int Foo::TailFrom(int x) { [[clang::musttail]] return MemberFunction(x); } -// CHECK: %call = musttail call noundef i32 @_ZN3Foo14MemberFunctionEi(%class.Foo* noundef %this1, i32 noundef %0) +// CHECK: %call = musttail call i32 @_ZN3Foo14MemberFunctionEi(%class.Foo* nonnull align 1 dereferenceable(1) %this1, i32 %0) int Func3(int x) { [[clang::musttail]] return Foo::StaticMethod(x); } -// CHECK: %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0) +// CHECK: %call = musttail call i32 @_ZN3Foo12StaticMethodEi(i32 %0) int Func4(int x) { Foo foo; // Object with trivial destructor. [[clang::musttail]] return foo.StaticMethod(x); } -// CHECK: %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0) +// CHECK: %call = musttail call i32 @_ZN3Foo12StaticMethodEi(i32 %0) int (Foo::*pmf)(int); @@ -57,13 +57,13 @@ int Foo::TailFrom2(int x) { [[clang::musttail]] return ((*this).*pmf)(x); } -// CHECK: %call = musttail call noundef i32 %8(%class.Foo* noundef %this.adjusted, i32 noundef %9) +// CHECK: %call = musttail call i32 %8(%class.Foo* nonnull align 1 dereferenceable(1) %this.adjusted, i32 %9) int Foo::TailFrom3(int x) { [[clang::musttail]] return (this->*pmf)(x); } -// CHECK: %call = musttail call noundef i32 %8(%class.Foo* noundef %this.adjusted, i32 noundef %9) +// CHECK: %call = musttail call i32 %8(%class.Foo* nonnull align 1 dereferenceable(1) %this.adjusted, i32 %9) void ReturnsVoid(); @@ -82,7 +82,7 @@ int Func6(int x) { [[clang::musttail]] return ReturnsInt(x); } -// CHECK: %call = musttail call noundef i32 @_Z10ReturnsInti(i32 noundef %0) +// CHECK: %call = musttail call i32 @_Z10ReturnsInti(i32 %0) struct Data { int (*fptr)(Data *); @@ -92,7 +92,7 @@ int Func7(Data *data) { [[clang::musttail]] return data->fptr(data); } -// CHECK: %call = musttail call noundef i32 %1(%struct.Data* noundef %2) +// CHECK: %call = musttail call i32 %1(%struct.Data* %2) template T TemplateFunc(T) { @@ -103,7 +103,7 @@ int Func9(int x) { [[clang::musttail]] return TemplateFunc(x); } -// CHECK: %call = musttail call noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0) +// CHECK: %call = musttail call i32 @_Z12TemplateFuncIiET_S0_(i32 %0) template int Func10(int x) { @@ -115,7 +115,7 @@ int Func11(int x) { return Func10(x); } -// CHECK: %call = musttail call noundef i32 @_Z3Bari(i32 noundef %0) +// CHECK: %call = musttail call i32 @_Z3Bari(i32 %0) template T Func12(T x) { @@ -126,14 +126,14 @@ int Func13(int x) { return Func12(x); } -// CHECK: %call = musttail call noundef i32 @_Z3Bari(i32 noundef %0) +// CHECK: %call = musttail call i32 @_Z3Bari(i32 %0) int Func14(int x) { int vla[x]; [[clang::musttail]] return Bar(x); } -// CHECK: %call = musttail call noundef i32 @_Z3Bari(i32 noundef %3) +// CHECK: %call = musttail call i32 @_Z3Bari(i32 %3) void TrivialDestructorParam(HasTrivialDestructor obj); @@ -152,7 +152,7 @@ void Struct3::NonConstMemberFunction(int *i) { [[clang::musttail]] return ConstMemberFunction(i); } -// CHECK: musttail call void @_ZNK7Struct319ConstMemberFunctionEPKi(%struct.Struct3* noundef %this1, i32* noundef %0) +// CHECK: musttail call void @_ZNK7Struct319ConstMemberFunctionEPKi(%struct.Struct3* nonnull align 1 dereferenceable(1) %this1, i32* %0) struct HasNonTrivialCopyConstructor { HasNonTrivialCopyConstructor(const HasNonTrivialCopyConstructor &); @@ -180,7 +180,7 @@ void TestFunctionPointer(int x) { [[clang::musttail]] return p(x); } -// CHECK: musttail call void %0(i32 noundef %1) +// CHECK: musttail call void %0(i32 %1) struct LargeWithCopyConstructor { LargeWithCopyConstructor(const LargeWithCopyConstructor &); @@ -200,7 +200,7 @@ int TestRValueFunctionPointer() { [[clang::musttail]] return ReturnsIntFunction()(); } -// CHECK: musttail call noundef i32 %call() +// CHECK: musttail call i32 %call() void(FuncWithParens)() { [[clang::musttail]] return FuncWithParens(); @@ -213,8 +213,8 @@ int TestNonCapturingLambda() { [[clang::musttail]] return (+lambda)(); } -// CHECK: %call = call noundef i32 ()* @"_ZZ22TestNonCapturingLambdavENK3$_0cvPFivEEv"(%class.anon* noundef %lambda) -// CHECK: musttail call noundef i32 %call() +// CHECK: %call = call i32 ()* @"_ZZ22TestNonCapturingLambdavENK3$_0cvPFivEEv"(%class.anon* nonnull align 1 dereferenceable(1) %lambda) +// CHECK: musttail call i32 %call() class TestVirtual { virtual void TailTo(); @@ -225,4 +225,4 @@ void TestVirtual::TailFrom() { [[clang::musttail]] return TailTo(); } -// CHECK: musttail call void %1(%class.TestVirtual* noundef %this1) +// CHECK: musttail call void %1(%class.TestVirtual* nonnull align 8 dereferenceable(8) %this1) diff --git a/clang/test/CodeGenCXX/attr-notail.cpp b/clang/test/CodeGenCXX/attr-notail.cpp index d8fba9415c86c7ef7b77ea305362dbaecc5bb33e..5e207cd3a280b76aeb72a11d635863303ae02535 100644 --- a/clang/test/CodeGenCXX/attr-notail.cpp +++ b/clang/test/CodeGenCXX/attr-notail.cpp @@ -24,8 +24,8 @@ int foo1(int a, Class1 *c1, Class2 &c2) { } // CHECK-LABEL: define{{.*}} i32 @_Z4foo1iP6Class1R6Class2( -// CHECK: %{{[a-z0-9]+}} = notail call noundef i32 @_ZN6Class12m1Ev(%class.Class1* -// CHECK: %{{[a-z0-9]+}} = notail call noundef i32 %{{[0-9]+}}(%class.Class1* -// CHECK-NOT: %{{[a-z0-9]+}} = notail call noundef i32 %{{[0-9]+}}(%class.Class1* -// CHECK: %{{[a-z0-9]+}} = notail call noundef i32 %{{[0-9]+}}(%class.Class2* -// CHECK: %{{[a-z0-9]+}} = call noundef i32 @_ZN6Class12m2Ev(%class.Class1* +// CHECK: %{{[a-z0-9]+}} = notail call i32 @_ZN6Class12m1Ev(%class.Class1* +// CHECK: %{{[a-z0-9]+}} = notail call i32 %{{[0-9]+}}(%class.Class1* +// CHECK-NOT: %{{[a-z0-9]+}} = notail call i32 %{{[0-9]+}}(%class.Class1* +// CHECK: %{{[a-z0-9]+}} = notail call i32 %{{[0-9]+}}(%class.Class2* +// CHECK: %{{[a-z0-9]+}} = call i32 @_ZN6Class12m2Ev(%class.Class1* diff --git a/clang/test/CodeGenCXX/attr-target-mv-diff-ns.cpp b/clang/test/CodeGenCXX/attr-target-mv-diff-ns.cpp index 7d1430f7e859c86fd0f56ff0335f8c9d035844be..4e461488f19f87b9466ec31d7865e65cd39791ef 100644 --- a/clang/test/CodeGenCXX/attr-target-mv-diff-ns.cpp +++ b/clang/test/CodeGenCXX/attr-target-mv-diff-ns.cpp @@ -21,41 +21,41 @@ int bar() { // LINUX: @_Z3fooi.ifunc = weak_odr ifunc i32 (i32), i32 (i32)* ()* @_Z3fooi.resolver // LINUX: @_ZN2ns3fooEi.ifunc = weak_odr ifunc i32 (i32), i32 (i32)* ()* @_ZN2ns3fooEi.resolver -// LINUX: define{{.*}} i32 @_Z3fooi.sse4.2(i32 noundef %0) +// LINUX: define{{.*}} i32 @_Z3fooi.sse4.2(i32 %0) // LINUX: ret i32 0 -// LINUX: define{{.*}} i32 @_Z3fooi.arch_ivybridge(i32 noundef %0) +// LINUX: define{{.*}} i32 @_Z3fooi.arch_ivybridge(i32 %0) // LINUX: ret i32 1 -// LINUX: define{{.*}} i32 @_Z3fooi(i32 noundef %0) +// LINUX: define{{.*}} i32 @_Z3fooi(i32 %0) // LINUX: ret i32 2 -// WINDOWS: define dso_local noundef i32 @"?foo@@YAHH@Z.sse4.2"(i32 noundef %0) +// WINDOWS: define dso_local i32 @"?foo@@YAHH@Z.sse4.2"(i32 %0) // WINDOWS: ret i32 0 -// WINDOWS: define dso_local noundef i32 @"?foo@@YAHH@Z.arch_ivybridge"(i32 noundef %0) +// WINDOWS: define dso_local i32 @"?foo@@YAHH@Z.arch_ivybridge"(i32 %0) // WINDOWS: ret i32 1 -// WINDOWS: define dso_local noundef i32 @"?foo@@YAHH@Z"(i32 noundef %0) +// WINDOWS: define dso_local i32 @"?foo@@YAHH@Z"(i32 %0) // WINDOWS: ret i32 2 -// LINUX: define{{.*}} i32 @_ZN2ns3fooEi.sse4.2(i32 noundef %0) +// LINUX: define{{.*}} i32 @_ZN2ns3fooEi.sse4.2(i32 %0) // LINUX: ret i32 0 -// LINUX: define{{.*}} i32 @_ZN2ns3fooEi.arch_ivybridge(i32 noundef %0) +// LINUX: define{{.*}} i32 @_ZN2ns3fooEi.arch_ivybridge(i32 %0) // LINUX: ret i32 1 -// LINUX: define{{.*}} i32 @_ZN2ns3fooEi(i32 noundef %0) +// LINUX: define{{.*}} i32 @_ZN2ns3fooEi(i32 %0) // LINUX: ret i32 2 -// WINDOWS: define dso_local noundef i32 @"?foo@ns@@YAHH@Z.sse4.2"(i32 noundef %0) +// WINDOWS: define dso_local i32 @"?foo@ns@@YAHH@Z.sse4.2"(i32 %0) // WINDOWS: ret i32 0 -// WINDOWS: define dso_local noundef i32 @"?foo@ns@@YAHH@Z.arch_ivybridge"(i32 noundef %0) +// WINDOWS: define dso_local i32 @"?foo@ns@@YAHH@Z.arch_ivybridge"(i32 %0) // WINDOWS: ret i32 1 -// WINDOWS: define dso_local noundef i32 @"?foo@ns@@YAHH@Z"(i32 noundef %0) +// WINDOWS: define dso_local i32 @"?foo@ns@@YAHH@Z"(i32 %0) // WINDOWS: ret i32 2 // LINUX: define{{.*}} i32 @_Z3barv() -// LINUX: call noundef i32 @_Z3fooi.ifunc(i32 noundef 1) -// LINUX: call noundef i32 @_ZN2ns3fooEi.ifunc(i32 noundef 2) +// LINUX: call i32 @_Z3fooi.ifunc(i32 1) +// LINUX: call i32 @_ZN2ns3fooEi.ifunc(i32 2) -// WINDOWS: define dso_local noundef i32 @"?bar@@YAHXZ"() -// WINDOWS: call noundef i32 @"?foo@@YAHH@Z.resolver"(i32 noundef 1) -// WINDOWS: call noundef i32 @"?foo@ns@@YAHH@Z.resolver"(i32 noundef 2) +// WINDOWS: define dso_local i32 @"?bar@@YAHXZ"() +// WINDOWS: call i32 @"?foo@@YAHH@Z.resolver"(i32 1) +// WINDOWS: call i32 @"?foo@ns@@YAHH@Z.resolver"(i32 2) // LINUX: define weak_odr i32 (i32)* @_Z3fooi.resolver() comdat // LINUX: ret i32 (i32)* @_Z3fooi.arch_sandybridge @@ -81,8 +81,8 @@ int bar() { // WINDOWS: call i32 @"?foo@ns@@YAHH@Z.sse4.2"(i32 %0) // WINDOWS: call i32 @"?foo@ns@@YAHH@Z"(i32 %0) -// LINUX: declare noundef i32 @_Z3fooi.arch_sandybridge(i32 noundef) -// LINUX: declare noundef i32 @_ZN2ns3fooEi.arch_sandybridge(i32 noundef) +// LINUX: declare i32 @_Z3fooi.arch_sandybridge(i32) +// LINUX: declare i32 @_ZN2ns3fooEi.arch_sandybridge(i32) -// WINDOWS: declare dso_local noundef i32 @"?foo@@YAHH@Z.arch_sandybridge"(i32 noundef) -// WINDOWS: declare dso_local noundef i32 @"?foo@ns@@YAHH@Z.arch_sandybridge"(i32 noundef) +// WINDOWS: declare dso_local i32 @"?foo@@YAHH@Z.arch_sandybridge"(i32) +// WINDOWS: declare dso_local i32 @"?foo@ns@@YAHH@Z.arch_sandybridge"(i32) diff --git a/clang/test/CodeGenCXX/attr-target-mv-func-ptrs.cpp b/clang/test/CodeGenCXX/attr-target-mv-func-ptrs.cpp index 7fdb36de94463214356e28040d5614d950d97d2c..826c1191e4126f784c129414f9d469bfb7e3a902 100644 --- a/clang/test/CodeGenCXX/attr-target-mv-func-ptrs.cpp +++ b/clang/test/CodeGenCXX/attr-target-mv-func-ptrs.cpp @@ -42,13 +42,13 @@ int bar() { // LINUX: store { i64, i64 } { i64 ptrtoint (i32 (%struct.S*, i32)* @_ZN1S3fooEi.ifunc to i64), i64 0 }, { i64, i64 }* [[MEMBER:%[a-z]+]] // Call to 'f' with the ifunc -// LINUX: call void @_Z1fPFiiEM1SFiiE(i32 (i32)* noundef @_Z3fooi.ifunc +// LINUX: call void @_Z1fPFiiEM1SFiiE(i32 (i32)* @_Z3fooi.ifunc -// WINDOWS: define dso_local noundef i32 @"?bar@@YAHXZ"() +// WINDOWS: define dso_local i32 @"?bar@@YAHXZ"() // Store to Free // WINDOWS: store i32 (i32)* @"?foo@@YAHH@Z.resolver", i32 (i32)** // Store to Member // WINDOWS: store i8* bitcast (i32 (%struct.S*, i32)* @"?foo@S@@QEAAHH@Z.resolver" to i8*), i8** // Call to 'f' -// WINDOWS: call void @"?f@@YAXP6AHH@ZP8S@@EAAHH@Z@Z"(i32 (i32)* noundef @"?foo@@YAHH@Z.resolver", i8* bitcast (i32 (%struct.S*, i32)* @"?foo@S@@QEAAHH@Z.resolver" to i8*)) +// WINDOWS: call void @"?f@@YAXP6AHH@ZP8S@@EAAHH@Z@Z"(i32 (i32)* @"?foo@@YAHH@Z.resolver", i8* bitcast (i32 (%struct.S*, i32)* @"?foo@S@@QEAAHH@Z.resolver" to i8*)) diff --git a/clang/test/CodeGenCXX/attr-target-mv-inalloca.cpp b/clang/test/CodeGenCXX/attr-target-mv-inalloca.cpp index e1bb1f9f6bdf22da399e7706506fa48e43ea367a..be9fc941c4809e13fb0de9f1de3cbdcc39ad117e 100644 --- a/clang/test/CodeGenCXX/attr-target-mv-inalloca.cpp +++ b/clang/test/CodeGenCXX/attr-target-mv-inalloca.cpp @@ -16,20 +16,20 @@ void usage() { bar(f); } -// WINDOWS: define dso_local noundef i32 @"?bar@@YAHUFoo@@@Z"(<{ %struct.Foo }>* inalloca(<{ %struct.Foo }>) %0) +// WINDOWS: define dso_local i32 @"?bar@@YAHUFoo@@@Z"(<{ %struct.Foo }>* inalloca(<{ %struct.Foo }>) %0) // WINDOWS: %[[O:[0-9a-zA-Z]+]] = getelementptr inbounds <{ %struct.Foo }>, <{ %struct.Foo }>* %0, i32 0, i32 0 // WINDOWS: %[[X:[0-9a-zA-Z]+]] = getelementptr inbounds %struct.Foo, %struct.Foo* %[[O]], i32 0, i32 0 // WINDOWS: %[[LOAD:[0-9a-zA-Z]+]] = load i32, i32* %[[X]] // WINDOWS: ret i32 %[[LOAD]] -// WINDOWS: define dso_local noundef i32 @"?bar@@YAHUFoo@@@Z.sse4.2"(<{ %struct.Foo }>* inalloca(<{ %struct.Foo }>) %0) +// WINDOWS: define dso_local i32 @"?bar@@YAHUFoo@@@Z.sse4.2"(<{ %struct.Foo }>* inalloca(<{ %struct.Foo }>) %0) // WINDOWS: %[[O:[0-9a-zA-Z]+]] = getelementptr inbounds <{ %struct.Foo }>, <{ %struct.Foo }>* %0, i32 0, i32 0 // WINDOWS: %[[X:[0-9a-zA-Z]+]] = getelementptr inbounds %struct.Foo, %struct.Foo* %[[O]], i32 0, i32 0 // WINDOWS: %[[LOAD:[0-9a-zA-Z]+]] = load i32, i32* %[[X]] // WINDOWS: %[[ADD:[0-9a-zA-Z]+]] = add nsw i32 %[[LOAD]], 1 // WINDOWS: ret i32 %[[ADD]] -// WINDOWS: define dso_local noundef i32 @"?bar@@YAHUFoo@@@Z.arch_ivybridge"(<{ %struct.Foo }>* inalloca(<{ %struct.Foo }>) %0) +// WINDOWS: define dso_local i32 @"?bar@@YAHUFoo@@@Z.arch_ivybridge"(<{ %struct.Foo }>* inalloca(<{ %struct.Foo }>) %0) // WINDOWS: %[[O:[0-9a-zA-Z]+]] = getelementptr inbounds <{ %struct.Foo }>, <{ %struct.Foo }>* %0, i32 0, i32 0 // WINDOWS: %[[X:[0-9a-zA-Z]+]] = getelementptr inbounds %struct.Foo, %struct.Foo* %[[O]], i32 0, i32 0 // WINDOWS: %[[LOAD:[0-9a-zA-Z]+]] = load i32, i32* %[[X]] @@ -39,7 +39,7 @@ void usage() { // WINDOWS: define dso_local void @"?usage@@YAXXZ"() // WINDOWS: %[[F:[0-9a-zA-Z]+]] = alloca %struct.Foo // WINDOWS: %[[ARGMEM:[0-9a-zA-Z]+]] = alloca inalloca <{ %struct.Foo }> -// WINDOWS: %[[CALL:[0-9a-zA-Z]+]] = call noundef i32 @"?bar@@YAHUFoo@@@Z.resolver"(<{ %struct.Foo }>* inalloca(<{ %struct.Foo }>) %[[ARGMEM]]) +// WINDOWS: %[[CALL:[0-9a-zA-Z]+]] = call i32 @"?bar@@YAHUFoo@@@Z.resolver"(<{ %struct.Foo }>* inalloca(<{ %struct.Foo }>) %[[ARGMEM]]) // WINDOWS: define weak_odr dso_local i32 @"?bar@@YAHUFoo@@@Z.resolver"(<{ %struct.Foo }>* %0) // WINDOWS: %[[RET:[0-9a-zA-Z]+]] = musttail call i32 @"?bar@@YAHUFoo@@@Z.arch_ivybridge"(<{ %struct.Foo }>* %0) @@ -50,18 +50,18 @@ void usage() { // WINDOWS-NEXT: ret i32 %[[RET]] -// WINDOWS64: define dso_local noundef i32 @"?bar@@YAHUFoo@@@Z"(%struct.Foo* noundef %[[O:[0-9a-zA-Z]+]]) +// WINDOWS64: define dso_local i32 @"?bar@@YAHUFoo@@@Z"(%struct.Foo* %[[O:[0-9a-zA-Z]+]]) // WINDOWS64: %[[X:[0-9a-zA-Z]+]] = getelementptr inbounds %struct.Foo, %struct.Foo* %[[O]], i32 0, i32 0 // WINDOWS64: %[[LOAD:[0-9a-zA-Z]+]] = load i32, i32* %[[X]] // WINDOWS64: ret i32 %[[LOAD]] -// WINDOWS64: define dso_local noundef i32 @"?bar@@YAHUFoo@@@Z.sse4.2"(%struct.Foo* noundef %[[O:[0-9a-zA-Z]+]]) +// WINDOWS64: define dso_local i32 @"?bar@@YAHUFoo@@@Z.sse4.2"(%struct.Foo* %[[O:[0-9a-zA-Z]+]]) // WINDOWS64: %[[X:[0-9a-zA-Z]+]] = getelementptr inbounds %struct.Foo, %struct.Foo* %[[O]], i32 0, i32 0 // WINDOWS64: %[[LOAD:[0-9a-zA-Z]+]] = load i32, i32* %[[X]] // WINDOWS64: %[[ADD:[0-9a-zA-Z]+]] = add nsw i32 %[[LOAD]], 1 // WINDOWS64: ret i32 %[[ADD]] -// WINDOWS64: define dso_local noundef i32 @"?bar@@YAHUFoo@@@Z.arch_ivybridge"(%struct.Foo* noundef %[[O:[0-9a-zA-Z]+]]) +// WINDOWS64: define dso_local i32 @"?bar@@YAHUFoo@@@Z.arch_ivybridge"(%struct.Foo* %[[O:[0-9a-zA-Z]+]]) // WINDOWS64: %[[X:[0-9a-zA-Z]+]] = getelementptr inbounds %struct.Foo, %struct.Foo* %[[O]], i32 0, i32 0 // WINDOWS64: %[[LOAD:[0-9a-zA-Z]+]] = load i32, i32* %[[X]] // WINDOWS64: %[[ADD:[0-9a-zA-Z]+]] = add nsw i32 %[[LOAD]], 2 @@ -70,7 +70,7 @@ void usage() { // WINDOWS64: define dso_local void @"?usage@@YAXXZ"() // WINDOWS64: %[[F:[0-9a-zA-Z]+]] = alloca %struct.Foo // WINDOWS64: %[[ARG:[0-9a-zA-Z.]+]] = alloca %struct.Foo -// WINDOWS64: %[[CALL:[0-9a-zA-Z]+]] = call noundef i32 @"?bar@@YAHUFoo@@@Z.resolver"(%struct.Foo* noundef %[[ARG]]) +// WINDOWS64: %[[CALL:[0-9a-zA-Z]+]] = call i32 @"?bar@@YAHUFoo@@@Z.resolver"(%struct.Foo* %[[ARG]]) // WINDOWS64: define weak_odr dso_local i32 @"?bar@@YAHUFoo@@@Z.resolver"(%struct.Foo* %0) // WINDOWS64: %[[RET:[0-9a-zA-Z]+]] = musttail call i32 @"?bar@@YAHUFoo@@@Z.arch_ivybridge"(%struct.Foo* %0) diff --git a/clang/test/CodeGenCXX/attr-target-mv-member-funcs.cpp b/clang/test/CodeGenCXX/attr-target-mv-member-funcs.cpp index b95d7ad599d0caf1237173437c16cdd6e07de402..24e3915c167d7aaa8754094586a0470344064c73 100644 --- a/clang/test/CodeGenCXX/attr-target-mv-member-funcs.cpp +++ b/clang/test/CodeGenCXX/attr-target-mv-member-funcs.cpp @@ -77,19 +77,19 @@ int templ_use() { // LINUX: %s = alloca %struct.S, align 1 // LINUX: %s2 = alloca %struct.S, align 1 // LINUX: %C = alloca %struct.ConvertTo, align 1 -// LINUX: call noundef nonnull align 1 dereferenceable(1) %struct.S* @_ZN1SaSERKS_.ifunc(%struct.S* {{[^,]*}} %s2 +// LINUX: call nonnull align 1 dereferenceable(1) %struct.S* @_ZN1SaSERKS_.ifunc(%struct.S* {{[^,]*}} %s2 // LINUX: call void @_ZNK9ConvertTocv1SEv.ifunc(%struct.ConvertTo* {{[^,]*}} %C) -// LINUX: call noundef nonnull align 1 dereferenceable(1) %struct.S* @_ZN1SaSERKS_.ifunc(%struct.S* {{[^,]*}} %s2 -// LINUX: call noundef i32 @_ZN1S3fooEi.ifunc(%struct.S* {{[^,]*}} %s, i32 noundef 0) +// LINUX: call nonnull align 1 dereferenceable(1) %struct.S* @_ZN1SaSERKS_.ifunc(%struct.S* {{[^,]*}} %s2 +// LINUX: call i32 @_ZN1S3fooEi.ifunc(%struct.S* {{[^,]*}} %s, i32 0) -// WINDOWS: define dso_local noundef i32 @"?bar@@YAHXZ"() +// WINDOWS: define dso_local i32 @"?bar@@YAHXZ"() // WINDOWS: %s = alloca %struct.S, align 1 // WINDOWS: %s2 = alloca %struct.S, align 1 // WINDOWS: %C = alloca %struct.ConvertTo, align 1 -// WINDOWS: call noundef nonnull align 1 dereferenceable(1) %struct.S* @"??4S@@QEAAAEAU0@AEBU0@@Z.resolver"(%struct.S* {{[^,]*}} %s2 +// WINDOWS: call nonnull align 1 dereferenceable(1) %struct.S* @"??4S@@QEAAAEAU0@AEBU0@@Z.resolver"(%struct.S* {{[^,]*}} %s2 // WINDOWS: call void @"??BConvertTo@@QEBA?AUS@@XZ.resolver"(%struct.ConvertTo* {{[^,]*}} %C -// WINDOWS: call noundef nonnull align 1 dereferenceable(1) %struct.S* @"??4S@@QEAAAEAU0@AEBU0@@Z.resolver"(%struct.S* {{[^,]*}} %s2 -// WINDOWS: call noundef i32 @"?foo@S@@QEAAHH@Z.resolver"(%struct.S* {{[^,]*}} %s, i32 noundef 0) +// WINDOWS: call nonnull align 1 dereferenceable(1) %struct.S* @"??4S@@QEAAAEAU0@AEBU0@@Z.resolver"(%struct.S* {{[^,]*}} %s2 +// WINDOWS: call i32 @"?foo@S@@QEAAHH@Z.resolver"(%struct.S* {{[^,]*}} %s, i32 0) // LINUX: define weak_odr %struct.S* (%struct.S*, %struct.S*)* @_ZN1SaSERKS_.resolver() comdat // LINUX: ret %struct.S* (%struct.S*, %struct.S*)* @_ZN1SaSERKS_.arch_ivybridge @@ -120,10 +120,10 @@ int templ_use() { // WINDOWS: call i32 @"?foo@S@@QEAAHH@Z" // LINUX: define{{.*}} i32 @_Z4bar2v() -// LINUX: call noundef i32 @_ZN2S23fooEi.ifunc +// LINUX: call i32 @_ZN2S23fooEi.ifunc -// WINDOWS: define dso_local noundef i32 @"?bar2@@YAHXZ"() -// WINDOWS: call noundef i32 @"?foo@S2@@QEAAHH@Z.resolver" +// WINDOWS: define dso_local i32 @"?bar2@@YAHXZ"() +// WINDOWS: call i32 @"?foo@S2@@QEAAHH@Z.resolver" // LINUX: define weak_odr i32 (%struct.S2*, i32)* @_ZN2S23fooEi.resolver() comdat // LINUX: ret i32 (%struct.S2*, i32)* @_ZN2S23fooEi.arch_sandybridge @@ -137,21 +137,21 @@ int templ_use() { // WINDOWS: call i32 @"?foo@S2@@QEAAHH@Z.sse4.2" // WINDOWS: call i32 @"?foo@S2@@QEAAHH@Z" -// LINUX: define{{.*}} i32 @_ZN2S23fooEi.sse4.2(%struct.S2* {{[^,]*}} %this, i32 noundef %0) -// LINUX: define{{.*}} i32 @_ZN2S23fooEi.arch_ivybridge(%struct.S2* {{[^,]*}} %this, i32 noundef %0) -// LINUX: define{{.*}} i32 @_ZN2S23fooEi(%struct.S2* {{[^,]*}} %this, i32 noundef %0) +// LINUX: define{{.*}} i32 @_ZN2S23fooEi.sse4.2(%struct.S2* {{[^,]*}} %this, i32 %0) +// LINUX: define{{.*}} i32 @_ZN2S23fooEi.arch_ivybridge(%struct.S2* {{[^,]*}} %this, i32 %0) +// LINUX: define{{.*}} i32 @_ZN2S23fooEi(%struct.S2* {{[^,]*}} %this, i32 %0) -// WINDOWS: define dso_local noundef i32 @"?foo@S2@@QEAAHH@Z.sse4.2"(%struct.S2* {{[^,]*}} %this, i32 noundef %0) -// WINDOWS: define dso_local noundef i32 @"?foo@S2@@QEAAHH@Z.arch_ivybridge"(%struct.S2* {{[^,]*}} %this, i32 noundef %0) -// WINDOWS: define dso_local noundef i32 @"?foo@S2@@QEAAHH@Z"(%struct.S2* {{[^,]*}} %this, i32 noundef %0) +// WINDOWS: define dso_local i32 @"?foo@S2@@QEAAHH@Z.sse4.2"(%struct.S2* {{[^,]*}} %this, i32 %0) +// WINDOWS: define dso_local i32 @"?foo@S2@@QEAAHH@Z.arch_ivybridge"(%struct.S2* {{[^,]*}} %this, i32 %0) +// WINDOWS: define dso_local i32 @"?foo@S2@@QEAAHH@Z"(%struct.S2* {{[^,]*}} %this, i32 %0) // LINUX: define{{.*}} i32 @_Z9templ_usev() -// LINUX: call noundef i32 @_ZN5templIiE3fooEi.ifunc -// LINUX: call noundef i32 @_ZN5templIdE3fooEi.ifunc +// LINUX: call i32 @_ZN5templIiE3fooEi.ifunc +// LINUX: call i32 @_ZN5templIdE3fooEi.ifunc -// WINDOWS: define dso_local noundef i32 @"?templ_use@@YAHXZ"() -// WINDOWS: call noundef i32 @"?foo@?$templ@H@@QEAAHH@Z.resolver" -// WINDOWS: call noundef i32 @"?foo@?$templ@N@@QEAAHH@Z.resolver" +// WINDOWS: define dso_local i32 @"?templ_use@@YAHXZ"() +// WINDOWS: call i32 @"?foo@?$templ@H@@QEAAHH@Z.resolver" +// WINDOWS: call i32 @"?foo@?$templ@N@@QEAAHH@Z.resolver" // LINUX: define weak_odr i32 (%struct.templ*, i32)* @_ZN5templIiE3fooEi.resolver() comdat // LINUX: ret i32 (%struct.templ*, i32)* @_ZN5templIiE3fooEi.arch_sandybridge @@ -177,44 +177,44 @@ int templ_use() { // WINDOWS: call i32 @"?foo@?$templ@N@@QEAAHH@Z.sse4.2" // WINDOWS: call i32 @"?foo@?$templ@N@@QEAAHH@Z" -// LINUX: define linkonce_odr noundef i32 @_ZN1S3fooEi.sse4.2(%struct.S* {{[^,]*}} %this, i32 noundef %0) +// LINUX: define linkonce_odr i32 @_ZN1S3fooEi.sse4.2(%struct.S* {{[^,]*}} %this, i32 %0) // LINUX: ret i32 0 -// WINDOWS: define linkonce_odr dso_local noundef i32 @"?foo@S@@QEAAHH@Z.sse4.2"(%struct.S* {{[^,]*}} %this, i32 noundef %0) +// WINDOWS: define linkonce_odr dso_local i32 @"?foo@S@@QEAAHH@Z.sse4.2"(%struct.S* {{[^,]*}} %this, i32 %0) // WINDOWS: ret i32 0 -// LINUX: declare noundef i32 @_ZN1S3fooEi.arch_sandybridge(%struct.S* {{[^,]*}}, i32 noundef) +// LINUX: declare i32 @_ZN1S3fooEi.arch_sandybridge(%struct.S* {{[^,]*}}, i32) -// WINDOWS: declare dso_local noundef i32 @"?foo@S@@QEAAHH@Z.arch_sandybridge"(%struct.S* {{[^,]*}}, i32 noundef) +// WINDOWS: declare dso_local i32 @"?foo@S@@QEAAHH@Z.arch_sandybridge"(%struct.S* {{[^,]*}}, i32) -// LINUX: define linkonce_odr noundef i32 @_ZN1S3fooEi.arch_ivybridge(%struct.S* {{[^,]*}} %this, i32 noundef %0) +// LINUX: define linkonce_odr i32 @_ZN1S3fooEi.arch_ivybridge(%struct.S* {{[^,]*}} %this, i32 %0) // LINUX: ret i32 1 -// WINDOWS: define linkonce_odr dso_local noundef i32 @"?foo@S@@QEAAHH@Z.arch_ivybridge"(%struct.S* {{[^,]*}} %this, i32 noundef %0) +// WINDOWS: define linkonce_odr dso_local i32 @"?foo@S@@QEAAHH@Z.arch_ivybridge"(%struct.S* {{[^,]*}} %this, i32 %0) // WINDOWS: ret i32 1 -// LINUX: define linkonce_odr noundef i32 @_ZN1S3fooEi(%struct.S* {{[^,]*}} %this, i32 noundef %0) +// LINUX: define linkonce_odr i32 @_ZN1S3fooEi(%struct.S* {{[^,]*}} %this, i32 %0) // LINUX: ret i32 2 -// WINDOWS: define linkonce_odr dso_local noundef i32 @"?foo@S@@QEAAHH@Z"(%struct.S* {{[^,]*}} %this, i32 noundef %0) +// WINDOWS: define linkonce_odr dso_local i32 @"?foo@S@@QEAAHH@Z"(%struct.S* {{[^,]*}} %this, i32 %0) // WINDOWS: ret i32 2 -// LINUX: define linkonce_odr noundef i32 @_ZN5templIiE3fooEi.sse4.2 -// LINUX: declare noundef i32 @_ZN5templIiE3fooEi.arch_sandybridge -// LINUX: define linkonce_odr noundef i32 @_ZN5templIiE3fooEi.arch_ivybridge -// LINUX: define linkonce_odr noundef i32 @_ZN5templIiE3fooEi - -// WINDOWS: define linkonce_odr dso_local noundef i32 @"?foo@?$templ@H@@QEAAHH@Z.sse4.2" -// WINDOWS: declare dso_local noundef i32 @"?foo@?$templ@H@@QEAAHH@Z.arch_sandybridge" -// WINDOWS: define linkonce_odr dso_local noundef i32 @"?foo@?$templ@H@@QEAAHH@Z.arch_ivybridge" -// WINDOWS: define linkonce_odr dso_local noundef i32 @"?foo@?$templ@H@@QEAAHH@Z" - -// LINUX: define linkonce_odr noundef i32 @_ZN5templIdE3fooEi.sse4.2 -// LINUX: declare noundef i32 @_ZN5templIdE3fooEi.arch_sandybridge -// LINUX: define linkonce_odr noundef i32 @_ZN5templIdE3fooEi.arch_ivybridge -// LINUX: define linkonce_odr noundef i32 @_ZN5templIdE3fooEi - -// WINDOWS: define linkonce_odr dso_local noundef i32 @"?foo@?$templ@N@@QEAAHH@Z.sse4.2" -// WINDOWS: declare dso_local noundef i32 @"?foo@?$templ@N@@QEAAHH@Z.arch_sandybridge" -// WINDOWS: define linkonce_odr dso_local noundef i32 @"?foo@?$templ@N@@QEAAHH@Z.arch_ivybridge" -// WINDOWS: define linkonce_odr dso_local noundef i32 @"?foo@?$templ@N@@QEAAHH@Z" +// LINUX: define linkonce_odr i32 @_ZN5templIiE3fooEi.sse4.2 +// LINUX: declare i32 @_ZN5templIiE3fooEi.arch_sandybridge +// LINUX: define linkonce_odr i32 @_ZN5templIiE3fooEi.arch_ivybridge +// LINUX: define linkonce_odr i32 @_ZN5templIiE3fooEi + +// WINDOWS: define linkonce_odr dso_local i32 @"?foo@?$templ@H@@QEAAHH@Z.sse4.2" +// WINDOWS: declare dso_local i32 @"?foo@?$templ@H@@QEAAHH@Z.arch_sandybridge" +// WINDOWS: define linkonce_odr dso_local i32 @"?foo@?$templ@H@@QEAAHH@Z.arch_ivybridge" +// WINDOWS: define linkonce_odr dso_local i32 @"?foo@?$templ@H@@QEAAHH@Z" + +// LINUX: define linkonce_odr i32 @_ZN5templIdE3fooEi.sse4.2 +// LINUX: declare i32 @_ZN5templIdE3fooEi.arch_sandybridge +// LINUX: define linkonce_odr i32 @_ZN5templIdE3fooEi.arch_ivybridge +// LINUX: define linkonce_odr i32 @_ZN5templIdE3fooEi + +// WINDOWS: define linkonce_odr dso_local i32 @"?foo@?$templ@N@@QEAAHH@Z.sse4.2" +// WINDOWS: declare dso_local i32 @"?foo@?$templ@N@@QEAAHH@Z.arch_sandybridge" +// WINDOWS: define linkonce_odr dso_local i32 @"?foo@?$templ@N@@QEAAHH@Z.arch_ivybridge" +// WINDOWS: define linkonce_odr dso_local i32 @"?foo@?$templ@N@@QEAAHH@Z" diff --git a/clang/test/CodeGenCXX/attr-target-mv-out-of-line-defs.cpp b/clang/test/CodeGenCXX/attr-target-mv-out-of-line-defs.cpp index a8e9e2713359ecbeef7e6151d14ba42be323caa8..071f5a341389d1a51aa92e520916c4d753d86f7d 100644 --- a/clang/test/CodeGenCXX/attr-target-mv-out-of-line-defs.cpp +++ b/clang/test/CodeGenCXX/attr-target-mv-out-of-line-defs.cpp @@ -18,31 +18,31 @@ int bar() { // LINUX: @_ZN1S3fooEi.ifunc = weak_odr ifunc i32 (%struct.S*, i32), i32 (%struct.S*, i32)* ()* @_ZN1S3fooEi.resolver -// LINUX: define{{.*}} i32 @_ZN1S3fooEi(%struct.S* {{[^,]*}} %this, i32 noundef %0) +// LINUX: define{{.*}} i32 @_ZN1S3fooEi(%struct.S* {{[^,]*}} %this, i32 %0) // LINUX: ret i32 2 -// WINDOWS: define dso_local noundef i32 @"?foo@S@@QEAAHH@Z"(%struct.S* {{[^,]*}} %this, i32 noundef %0) +// WINDOWS: define dso_local i32 @"?foo@S@@QEAAHH@Z"(%struct.S* {{[^,]*}} %this, i32 %0) // WINDOWS: ret i32 2 -// LINUX: define{{.*}} i32 @_ZN1S3fooEi.sse4.2(%struct.S* {{[^,]*}} %this, i32 noundef %0) +// LINUX: define{{.*}} i32 @_ZN1S3fooEi.sse4.2(%struct.S* {{[^,]*}} %this, i32 %0) // LINUX: ret i32 0 -// WINDOWS: define dso_local noundef i32 @"?foo@S@@QEAAHH@Z.sse4.2"(%struct.S* {{[^,]*}} %this, i32 noundef %0) +// WINDOWS: define dso_local i32 @"?foo@S@@QEAAHH@Z.sse4.2"(%struct.S* {{[^,]*}} %this, i32 %0) // WINDOWS: ret i32 0 -// LINUX: define{{.*}} i32 @_ZN1S3fooEi.arch_ivybridge(%struct.S* {{[^,]*}} %this, i32 noundef %0) +// LINUX: define{{.*}} i32 @_ZN1S3fooEi.arch_ivybridge(%struct.S* {{[^,]*}} %this, i32 %0) // LINUX: ret i32 1 -// WINDOWS: define dso_local noundef i32 @"?foo@S@@QEAAHH@Z.arch_ivybridge"(%struct.S* {{[^,]*}} %this, i32 noundef %0) +// WINDOWS: define dso_local i32 @"?foo@S@@QEAAHH@Z.arch_ivybridge"(%struct.S* {{[^,]*}} %this, i32 %0) // WINDOWS: ret i32 1 // LINUX: define{{.*}} i32 @_Z3barv() // LINUX: %s = alloca %struct.S, align 1 -// LINUX: %call = call noundef i32 @_ZN1S3fooEi.ifunc(%struct.S* {{[^,]*}} %s, i32 noundef 0) +// LINUX: %call = call i32 @_ZN1S3fooEi.ifunc(%struct.S* {{[^,]*}} %s, i32 0) -// WINDOWS: define dso_local noundef i32 @"?bar@@YAHXZ"() +// WINDOWS: define dso_local i32 @"?bar@@YAHXZ"() // WINDOWS: %s = alloca %struct.S, align 1 -// WINDOWS: %call = call noundef i32 @"?foo@S@@QEAAHH@Z.resolver"(%struct.S* {{[^,]*}} %s, i32 noundef 0) +// WINDOWS: %call = call i32 @"?foo@S@@QEAAHH@Z.resolver"(%struct.S* {{[^,]*}} %s, i32 0) // LINUX: define weak_odr i32 (%struct.S*, i32)* @_ZN1S3fooEi.resolver() comdat // LINUX: ret i32 (%struct.S*, i32)* @_ZN1S3fooEi.arch_sandybridge @@ -56,6 +56,6 @@ int bar() { // WINDOWS: call i32 @"?foo@S@@QEAAHH@Z.sse4.2"(%struct.S* %0, i32 %1) // WINDOWS: call i32 @"?foo@S@@QEAAHH@Z"(%struct.S* %0, i32 %1) -// LINUX: declare noundef i32 @_ZN1S3fooEi.arch_sandybridge(%struct.S* {{[^,]*}}, i32 noundef) +// LINUX: declare i32 @_ZN1S3fooEi.arch_sandybridge(%struct.S* {{[^,]*}}, i32) -// WINDOWS: declare dso_local noundef i32 @"?foo@S@@QEAAHH@Z.arch_sandybridge"(%struct.S* {{[^,]*}}, i32 noundef) +// WINDOWS: declare dso_local i32 @"?foo@S@@QEAAHH@Z.arch_sandybridge"(%struct.S* {{[^,]*}}, i32) diff --git a/clang/test/CodeGenCXX/attr-target-mv-overloads.cpp b/clang/test/CodeGenCXX/attr-target-mv-overloads.cpp index 9e9724ddb4fdbc483e9742f1eb061df655ef021a..65c6a894e956e085cdb0e772d5cc4ab4a67396fa 100644 --- a/clang/test/CodeGenCXX/attr-target-mv-overloads.cpp +++ b/clang/test/CodeGenCXX/attr-target-mv-overloads.cpp @@ -17,11 +17,11 @@ int bar2() { // LINUX: @_Z12foo_overloadv.ifunc = weak_odr ifunc i32 (), i32 ()* ()* @_Z12foo_overloadv.resolver // LINUX: @_Z12foo_overloadi.ifunc = weak_odr ifunc i32 (i32), i32 (i32)* ()* @_Z12foo_overloadi.resolver -// LINUX: define{{.*}} i32 @_Z12foo_overloadi.sse4.2(i32 noundef %0) +// LINUX: define{{.*}} i32 @_Z12foo_overloadi.sse4.2(i32 %0) // LINUX: ret i32 0 -// LINUX: define{{.*}} i32 @_Z12foo_overloadi.arch_ivybridge(i32 noundef %0) +// LINUX: define{{.*}} i32 @_Z12foo_overloadi.arch_ivybridge(i32 %0) // LINUX: ret i32 1 -// LINUX: define{{.*}} i32 @_Z12foo_overloadi(i32 noundef %0) +// LINUX: define{{.*}} i32 @_Z12foo_overloadi(i32 %0) // LINUX: ret i32 2 // LINUX: define{{.*}} i32 @_Z12foo_overloadv.sse4.2() // LINUX: ret i32 0 @@ -30,26 +30,26 @@ int bar2() { // LINUX: define{{.*}} i32 @_Z12foo_overloadv() // LINUX: ret i32 2 -// WINDOWS: define dso_local noundef i32 @"?foo_overload@@YAHH@Z.sse4.2"(i32 noundef %0) +// WINDOWS: define dso_local i32 @"?foo_overload@@YAHH@Z.sse4.2"(i32 %0) // WINDOWS: ret i32 0 -// WINDOWS: define dso_local noundef i32 @"?foo_overload@@YAHH@Z.arch_ivybridge"(i32 noundef %0) +// WINDOWS: define dso_local i32 @"?foo_overload@@YAHH@Z.arch_ivybridge"(i32 %0) // WINDOWS: ret i32 1 -// WINDOWS: define dso_local noundef i32 @"?foo_overload@@YAHH@Z"(i32 noundef %0) +// WINDOWS: define dso_local i32 @"?foo_overload@@YAHH@Z"(i32 %0) // WINDOWS: ret i32 2 -// WINDOWS: define dso_local noundef i32 @"?foo_overload@@YAHXZ.sse4.2"() +// WINDOWS: define dso_local i32 @"?foo_overload@@YAHXZ.sse4.2"() // WINDOWS: ret i32 0 -// WINDOWS: define dso_local noundef i32 @"?foo_overload@@YAHXZ.arch_ivybridge"() +// WINDOWS: define dso_local i32 @"?foo_overload@@YAHXZ.arch_ivybridge"() // WINDOWS: ret i32 1 -// WINDOWS: define dso_local noundef i32 @"?foo_overload@@YAHXZ"() +// WINDOWS: define dso_local i32 @"?foo_overload@@YAHXZ"() // WINDOWS: ret i32 2 // LINUX: define{{.*}} i32 @_Z4bar2v() -// LINUX: call noundef i32 @_Z12foo_overloadv.ifunc() -// LINUX: call noundef i32 @_Z12foo_overloadi.ifunc(i32 noundef 1) +// LINUX: call i32 @_Z12foo_overloadv.ifunc() +// LINUX: call i32 @_Z12foo_overloadi.ifunc(i32 1) -// WINDOWS: define dso_local noundef i32 @"?bar2@@YAHXZ"() -// WINDOWS: call noundef i32 @"?foo_overload@@YAHXZ.resolver"() -// WINDOWS: call noundef i32 @"?foo_overload@@YAHH@Z.resolver"(i32 noundef 1) +// WINDOWS: define dso_local i32 @"?bar2@@YAHXZ"() +// WINDOWS: call i32 @"?foo_overload@@YAHXZ.resolver"() +// WINDOWS: call i32 @"?foo_overload@@YAHH@Z.resolver"(i32 1) // LINUX: define weak_odr i32 ()* @_Z12foo_overloadv.resolver() comdat // LINUX: ret i32 ()* @_Z12foo_overloadv.arch_sandybridge @@ -75,8 +75,8 @@ int bar2() { // WINDOWS: call i32 @"?foo_overload@@YAHH@Z.sse4.2" // WINDOWS: call i32 @"?foo_overload@@YAHH@Z" -// LINUX: declare noundef i32 @_Z12foo_overloadv.arch_sandybridge() -// LINUX: declare noundef i32 @_Z12foo_overloadi.arch_sandybridge(i32 noundef) +// LINUX: declare i32 @_Z12foo_overloadv.arch_sandybridge() +// LINUX: declare i32 @_Z12foo_overloadi.arch_sandybridge(i32) -// WINDOWS: declare dso_local noundef i32 @"?foo_overload@@YAHXZ.arch_sandybridge"() -// WINDOWS: declare dso_local noundef i32 @"?foo_overload@@YAHH@Z.arch_sandybridge"(i32 noundef) +// WINDOWS: declare dso_local i32 @"?foo_overload@@YAHXZ.arch_sandybridge"() +// WINDOWS: declare dso_local i32 @"?foo_overload@@YAHH@Z.arch_sandybridge"(i32) diff --git a/clang/test/CodeGenCXX/attr-used-member-function-implicit-instantiation.cpp b/clang/test/CodeGenCXX/attr-used-member-function-implicit-instantiation.cpp index 64f5d50c7318e41d63de151c6799d96c522f3ed3..7d2062f989d684abfb11fcc336b47e4c68604f9d 100644 --- a/clang/test/CodeGenCXX/attr-used-member-function-implicit-instantiation.cpp +++ b/clang/test/CodeGenCXX/attr-used-member-function-implicit-instantiation.cpp @@ -13,7 +13,7 @@ struct S { void test() { // Check that InstantiateUsedMemberDefinition::S::f() is defined // as a result of the S class template implicit instantiation - // CHECK: define linkonce_odr noundef i32 @_ZN31InstantiateUsedMemberDefinition1SIiE1fEv + // CHECK: define linkonce_odr i32 @_ZN31InstantiateUsedMemberDefinition1SIiE1fEv S inst; } } // namespace InstantiateUsedMemberDefinition diff --git a/clang/test/CodeGenCXX/attr-x86-interrupt.cpp b/clang/test/CodeGenCXX/attr-x86-interrupt.cpp index 6eb0a0c78bcd210510791c29e69b3d40a6ad1d58..446d4d79a5a9bdd0fc89e481d13282f7c9d55122 100644 --- a/clang/test/CodeGenCXX/attr-x86-interrupt.cpp +++ b/clang/test/CodeGenCXX/attr-x86-interrupt.cpp @@ -18,18 +18,18 @@ struct St { static void foo9(int *a) __attribute__((interrupt)) {} }; // X86_64_LINUX: @llvm.compiler.used = appending global [3 x i8*] [i8* bitcast (void (i32*, i64)* @{{.*}}foo7{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo8{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo9{{.*}} to i8*)], section "llvm.metadata" -// X86_64_LINUX: define{{.*}} x86_intrcc void @{{.*}}foo7{{.*}}(i32* noundef byval(i32) %{{.+}}, i64 noundef %{{.+}}) -// X86_64_LINUX: define{{.*}} x86_intrcc void @{{.*}}foo8{{.*}}(i32* noundef byval(i32) %{{.+}}) -// X86_64_LINUX: define linkonce_odr x86_intrcc void @{{.*}}foo9{{.*}}(i32* noundef byval(i32) %{{.+}}) +// X86_64_LINUX: define{{.*}} x86_intrcc void @{{.*}}foo7{{.*}}(i32* byval(i32) %{{.+}}, i64 %{{.+}}) +// X86_64_LINUX: define{{.*}} x86_intrcc void @{{.*}}foo8{{.*}}(i32* byval(i32) %{{.+}}) +// X86_64_LINUX: define linkonce_odr x86_intrcc void @{{.*}}foo9{{.*}}(i32* byval(i32) %{{.+}}) // X86_LINUX: @llvm.compiler.used = appending global [3 x i8*] [i8* bitcast (void (i32*, i32)* @{{.*}}foo7{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo8{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo9{{.*}} to i8*)], section "llvm.metadata" -// X86_LINUX: define{{.*}} x86_intrcc void @{{.*}}foo7{{.*}}(i32* noundef byval(i32) %{{.+}}, i32 noundef %{{.+}}) -// X86_LINUX: define{{.*}} x86_intrcc void @{{.*}}foo8{{.*}}(i32* noundef byval(i32) %{{.+}}) -// X86_LINUX: define linkonce_odr x86_intrcc void @{{.*}}foo9{{.*}}(i32* noundef byval(i32) %{{.+}}) +// X86_LINUX: define{{.*}} x86_intrcc void @{{.*}}foo7{{.*}}(i32* byval(i32) %{{.+}}, i32 %{{.+}}) +// X86_LINUX: define{{.*}} x86_intrcc void @{{.*}}foo8{{.*}}(i32* byval(i32) %{{.+}}) +// X86_LINUX: define linkonce_odr x86_intrcc void @{{.*}}foo9{{.*}}(i32* byval(i32) %{{.+}}) // X86_64_WIN: @llvm.used = appending global [3 x i8*] [i8* bitcast (void (i32*, i64)* @{{.*}}foo7{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo8{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo9{{.*}} to i8*)], section "llvm.metadata" -// X86_64_WIN: define dso_local x86_intrcc void @{{.*}}foo7{{.*}}(i32* noundef byval(i32) %{{.+}}, i64 noundef %{{.+}}) -// X86_64_WIN: define dso_local x86_intrcc void @{{.*}}foo8{{.*}}(i32* noundef byval(i32) %{{.+}}) -// X86_64_WIN: define linkonce_odr dso_local x86_intrcc void @{{.*}}foo9{{.*}}(i32* noundef byval(i32) %{{.+}}) +// X86_64_WIN: define dso_local x86_intrcc void @{{.*}}foo7{{.*}}(i32* byval(i32) %{{.+}}, i64 %{{.+}}) +// X86_64_WIN: define dso_local x86_intrcc void @{{.*}}foo8{{.*}}(i32* byval(i32) %{{.+}}) +// X86_64_WIN: define linkonce_odr dso_local x86_intrcc void @{{.*}}foo9{{.*}}(i32* byval(i32) %{{.+}}) // X86_WIN: @llvm.used = appending global [3 x i8*] [i8* bitcast (void (i32*, i32)* @{{.*}}foo7{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo8{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo9{{.*}} to i8*)], section "llvm.metadata" -// X86_WIN: define dso_local x86_intrcc void @{{.*}}foo7{{.*}}(i32* noundef byval(i32) %{{.+}}, i32 noundef %{{.+}}) -// X86_WIN: define dso_local x86_intrcc void @{{.*}}foo8{{.*}}(i32* noundef byval(i32) %{{.+}}) -// X86_WIN: define linkonce_odr dso_local x86_intrcc void @{{.*}}foo9{{.*}}(i32* noundef byval(i32) %{{.+}}) +// X86_WIN: define dso_local x86_intrcc void @{{.*}}foo7{{.*}}(i32* byval(i32) %{{.+}}, i32 %{{.+}}) +// X86_WIN: define dso_local x86_intrcc void @{{.*}}foo8{{.*}}(i32* byval(i32) %{{.+}}) +// X86_WIN: define linkonce_odr dso_local x86_intrcc void @{{.*}}foo9{{.*}}(i32* byval(i32) %{{.+}}) diff --git a/clang/test/CodeGenCXX/blocks-cxx11.cpp b/clang/test/CodeGenCXX/blocks-cxx11.cpp index 2669dd6d25dcfb81518cd83152ca9de88c266681..ce3dbf22e6d027cf5458cc820a146fb070885d8d 100644 --- a/clang/test/CodeGenCXX/blocks-cxx11.cpp +++ b/clang/test/CodeGenCXX/blocks-cxx11.cpp @@ -8,7 +8,7 @@ namespace test_int { void test() { const int x = 100; takeABlock(^{ takeItByValue(x); }); - // CHECK: call void @_Z13takeItByValueIiEvT_(i32 noundef 100) + // CHECK: call void @_Z13takeItByValueIiEvT_(i32 100) } } @@ -19,7 +19,7 @@ namespace test_int_ref { takeABlock(^{ takeItByValue(x); }); // TODO: there's no good reason that this isn't foldable. - // CHECK: call void @_Z13takeItByValueIiEvT_(i32 noundef {{%.*}}) + // CHECK: call void @_Z13takeItByValueIiEvT_(i32 {{%.*}}) } } @@ -27,7 +27,7 @@ namespace test_float { void test() { const float x = 1; takeABlock(^{ takeItByValue(x); }); - // CHECK: call void @_Z13takeItByValueIfEvT_(float noundef 1.0 + // CHECK: call void @_Z13takeItByValueIfEvT_(float 1.0 } } @@ -38,7 +38,7 @@ namespace test_float_ref { takeABlock(^{ takeItByValue(x); }); // TODO: there's no good reason that this isn't foldable. - // CHECK: call void @_Z13takeItByValueIfEvT_(float noundef {{%.*}}) + // CHECK: call void @_Z13takeItByValueIfEvT_(float {{%.*}}) } } @@ -52,7 +52,7 @@ namespace test_complex_int { // CHECK-NEXT: store i32 0, // CHECK-NEXT: [[COERCE:%.*]] = bitcast // CHECK-NEXT: [[CVAL:%.*]] = load i64, i64* [[COERCE]] - // CHECK-NEXT: call void @_Z13takeItByValueICiEvT_(i64 noundef [[CVAL]]) + // CHECK-NEXT: call void @_Z13takeItByValueICiEvT_(i64 [[CVAL]]) } } @@ -78,7 +78,7 @@ namespace test_complex_int_ref_mutable { // CHECK-NEXT: store i32 [[I]], i32* [[ISLOT]] // CHECK-NEXT: [[COERCE:%.*]] = bitcast { i32, i32 }* [[CSLOT]] to i64* // CHECK-NEXT: [[CVAL:%.*]] = load i64, i64* [[COERCE]], - // CHECK-NEXT: call void @_Z13takeItByValueICiEvT_(i64 noundef [[CVAL]]) + // CHECK-NEXT: call void @_Z13takeItByValueICiEvT_(i64 [[CVAL]]) } } @@ -105,9 +105,9 @@ namespace test_block_in_lambda { // CHECK: [[THIS:%.*]] = load [[LAMBDA_T:%.*]]*, [[LAMBDA_T:%.*]]** // CHECK: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds [[BLOCK_T]], [[BLOCK_T]]* [[BLOCK]], i32 0, i32 5 // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[LAMBDA_T]], [[LAMBDA_T]]* [[THIS]], i32 0, i32 0 - // CHECK-NEXT: call void @_ZN20test_block_in_lambda1AC1ERKS0_({{.*}}* {{[^,]*}} [[BLOCK_CAPTURED]], {{.*}}* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[T1]]) + // CHECK-NEXT: call void @_ZN20test_block_in_lambda1AC1ERKS0_({{.*}}* {{[^,]*}} [[BLOCK_CAPTURED]], {{.*}}* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[T1]]) // CHECK-NEXT: [[T0:%.*]] = bitcast [[BLOCK_T]]* [[BLOCK]] to void ()* - // CHECK-NEXT: call void @_ZN20test_block_in_lambda9takeBlockEU13block_pointerFvvE(void ()* noundef [[T0]]) + // CHECK-NEXT: call void @_ZN20test_block_in_lambda9takeBlockEU13block_pointerFvvE(void ()* [[T0]]) // CHECK-NEXT: call void @_ZN20test_block_in_lambda1AD1Ev({{.*}}* {{[^,]*}} [[BLOCK_CAPTURED]]) // CHECK-NEXT: ret void } diff --git a/clang/test/CodeGenCXX/blocks.cpp b/clang/test/CodeGenCXX/blocks.cpp index 5e1c19042fa83980c70ec6e0a4eed4569b266720..93ddd4a436cf9bee0ef6e9ae31b5b9c482d52f7f 100644 --- a/clang/test/CodeGenCXX/blocks.cpp +++ b/clang/test/CodeGenCXX/blocks.cpp @@ -128,7 +128,7 @@ namespace test4 { // CHECK-NEXT: store i8* [[BLOCKDESC:%.*]], i8** {{.*}}, align 8 // CHECK-NEXT: bitcast i8* [[BLOCKDESC]] to <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]* }>* // CHECK: call void @_ZN5test41AC1Ev([[A]]* {{[^,]*}} [[TMP]]) - // CHECK-NEXT: call void @_ZN5test43fooENS_1AE([[A]]* noundef [[TMP]]) + // CHECK-NEXT: call void @_ZN5test43fooENS_1AE([[A]]* [[TMP]]) // CHECK-NEXT: call void @_ZN5test41AD1Ev([[A]]* {{[^,]*}} [[TMP]]) // CHECK-NEXT: ret void } @@ -167,7 +167,7 @@ namespace test5 { // CHECK-NOT: br // CHECK: [[CAPTURE:%.*]] = getelementptr inbounds [[BLOCK_T]], [[BLOCK_T]]* [[BLOCK]], i32 0, i32 5 - // CHECK-NEXT: call void @_ZN5test51AC1ERKS0_([[A]]* {{[^,]*}} [[CAPTURE]], [[A]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[X]]) + // CHECK-NEXT: call void @_ZN5test51AC1ERKS0_([[A]]* {{[^,]*}} [[CAPTURE]], [[A]]* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[X]]) // CHECK-NEXT: store i1 true, i1* [[CLEANUP_ACTIVE]] // CHECK-NEXT: store [[A]]* [[CAPTURE]], [[A]]** [[COND_CLEANUP_SAVE]], align 8 // CHECK-NEXT: bitcast [[BLOCK_T]]* [[BLOCK]] to void ()* diff --git a/clang/test/CodeGenCXX/builtin-calling-conv.cpp b/clang/test/CodeGenCXX/builtin-calling-conv.cpp index f02c0f8bd9b8c8f21a0d31fe948964a0baa97610..50357a37c3bc25b3c44404b6bb28f070add5a84d 100644 --- a/clang/test/CodeGenCXX/builtin-calling-conv.cpp +++ b/clang/test/CodeGenCXX/builtin-calling-conv.cpp @@ -27,27 +27,27 @@ void user() { } // LINUX: define{{.*}} void @_Z4userv() -// LINUX: call noalias noundef nonnull i8* @_Znwm +// LINUX: call noalias nonnull i8* @_Znwm // LINUX: call float @atan2f // LINUX: call void @_Z3foov -// LINUX: declare noundef nonnull i8* @_Znwm(i64 noundef) -// LINUX: declare float @atan2f(float noundef, float noundef) +// LINUX: declare nonnull i8* @_Znwm(i64) +// LINUX: declare float @atan2f(float, float) // LINUX: declare void @_Z3foov() // SPIR: define{{.*}} spir_func void @_Z4userv() -// SPIR: call spir_func noalias noundef nonnull i8* @_Znwj +// SPIR: call spir_func noalias nonnull i8* @_Znwj // SPIR: call spir_func float @atan2f // SPIR: call spir_func void @_Z3foov -// SPIR: declare spir_func noundef nonnull i8* @_Znwj(i32 noundef) -// SPIR: declare spir_func float @atan2f(float noundef, float noundef) +// SPIR: declare spir_func nonnull i8* @_Znwj(i32) +// SPIR: declare spir_func float @atan2f(float, float) // SPIR: declare spir_func void @_Z3foov() // Note: Windows /G options should not change the platform default calling // convention of builtins. // WIN32: define dso_local x86_stdcallcc void @"?user@@YGXXZ"() -// WIN32: call noalias noundef nonnull i8* @"??2@YAPAXI@Z" +// WIN32: call noalias nonnull i8* @"??2@YAPAXI@Z" // WIN32: call float @atan2f // WIN32: call x86_stdcallcc void @"?foo@@YGXXZ" -// WIN32: declare dso_local noundef nonnull i8* @"??2@YAPAXI@Z"( -// WIN32: declare dso_local float @atan2f(float noundef, float noundef) +// WIN32: declare dso_local nonnull i8* @"??2@YAPAXI@Z"( +// WIN32: declare dso_local float @atan2f(float, float) // WIN32: declare dso_local x86_stdcallcc void @"?foo@@YGXXZ"() diff --git a/clang/test/CodeGenCXX/builtin-is-constant-evaluated.cpp b/clang/test/CodeGenCXX/builtin-is-constant-evaluated.cpp index 748fcbcc135a5a20ec765b1a81f4dfd60e087731..d30fefe55b4f6028138178b30fe5b4ce2f6a24b7 100644 --- a/clang/test/CodeGenCXX/builtin-is-constant-evaluated.cpp +++ b/clang/test/CodeGenCXX/builtin-is-constant-evaluated.cpp @@ -26,7 +26,7 @@ bool foo() { return __builtin_is_constant_evaluated(); } -// CHECK-FN-CG-LABEL: define linkonce_odr noundef i32 @_Z1fv() +// CHECK-FN-CG-LABEL: define linkonce_odr i32 @_Z1fv() constexpr int f() { // CHECK-FN-CG: store i32 13, i32* %n, align 4 // CHECK-FN-CG: store i32 17, i32* %m, align 4 @@ -46,7 +46,7 @@ int p2 = f(); // same result without CONSTINIT // CHECK-DYN-LABEL: define internal void @__cxx_global_var_init() // CHECK-DYN: %0 = load i32, i32* @p, align 4 -// CHECK-DYN-NEXT: %call = call noundef i32 @_Z1fv() +// CHECK-DYN-NEXT: %call = call i32 @_Z1fv() // CHECK-DYN-NEXT: %add = add nsw i32 %0, %call // CHECK-DYN-NEXT: store i32 %add, i32* @q, align 4 // CHECK-DYN-NEXT: ret void @@ -85,7 +85,7 @@ void test_arr_expr() { // CHECK-ARR-LABEL: define{{.*}} void @_Z17test_new_arr_exprv void test_new_arr_expr() { - // CHECK-ARR: call noalias noundef nonnull i8* @_Znam(i64 noundef 17) + // CHECK-ARR: call noalias nonnull i8* @_Znam(i64 17) new char[std::is_constant_evaluated() || __builtin_is_constant_evaluated() ? 1 : 17]; } @@ -169,7 +169,7 @@ void test_dtor_bce_1() { // true during destruction. It would be OK if we replaced the constructor // call with a direct store, but we should emit the destructor call. - // CHECK-DTOR: call {{.*}} @_ZN13DestructorBCEC1Ei({{.*}}, i32 noundef 201) + // CHECK-DTOR: call {{.*}} @_ZN13DestructorBCEC1Ei({{.*}}, i32 201) DestructorBCE local(201); // CHECK-DTOR: call {{.*}} @_ZN13DestructorBCED // CHECK-DTOR: } diff --git a/clang/test/CodeGenCXX/builtin-operator-new-delete.cpp b/clang/test/CodeGenCXX/builtin-operator-new-delete.cpp index 795a35024fbf625c2218664ce580361928a3edd5..da0bf3c7b98aacea96a51a7b6246bec689af585a 100644 --- a/clang/test/CodeGenCXX/builtin-operator-new-delete.cpp +++ b/clang/test/CodeGenCXX/builtin-operator-new-delete.cpp @@ -37,30 +37,30 @@ void *operator new[](size_t, void*, bool) throw(); // CHECK-LABEL: define{{.*}} void @test_basic( extern "C" void test_basic() { - // CHECK: call noalias noundef nonnull i8* @_Znwm(i64 noundef 4) [[ATTR_BUILTIN_NEW:#[^ ]*]] + // CHECK: call noalias nonnull i8* @_Znwm(i64 4) [[ATTR_BUILTIN_NEW:#[^ ]*]] // CHECK: call void @_ZdlPv({{.*}}) [[ATTR_BUILTIN_DELETE:#[^ ]*]] // CHECK: ret void __builtin_operator_delete(__builtin_operator_new(4)); } -// CHECK: declare noundef nonnull i8* @_Znwm(i64 noundef) [[ATTR_NOBUILTIN:#[^ ]*]] -// CHECK: declare void @_ZdlPv(i8* noundef) [[ATTR_NOBUILTIN_NOUNWIND:#[^ ]*]] +// CHECK: declare nonnull i8* @_Znwm(i64) [[ATTR_NOBUILTIN:#[^ ]*]] +// CHECK: declare void @_ZdlPv(i8*) [[ATTR_NOBUILTIN_NOUNWIND:#[^ ]*]] // CHECK-LABEL: define{{.*}} void @test_aligned_alloc( extern "C" void test_aligned_alloc() { - // CHECK: call noalias noundef nonnull align 4 i8* @_ZnwmSt11align_val_t(i64 noundef 4, i64 noundef 4) [[ATTR_BUILTIN_NEW:#[^ ]*]] - // CHECK: call void @_ZdlPvSt11align_val_t({{.*}}, i64 noundef 4) [[ATTR_BUILTIN_DELETE:#[^ ]*]] + // CHECK: call noalias nonnull align 4 i8* @_ZnwmSt11align_val_t(i64 4, i64 4) [[ATTR_BUILTIN_NEW:#[^ ]*]] + // CHECK: call void @_ZdlPvSt11align_val_t({{.*}}, i64 4) [[ATTR_BUILTIN_DELETE:#[^ ]*]] __builtin_operator_delete(__builtin_operator_new(4, std::align_val_t(4)), std::align_val_t(4)); } -// CHECK: declare noundef nonnull i8* @_ZnwmSt11align_val_t(i64 noundef, i64 noundef) [[ATTR_NOBUILTIN:#[^ ]*]] -// CHECK: declare void @_ZdlPvSt11align_val_t(i8* noundef, i64 noundef) [[ATTR_NOBUILTIN_NOUNWIND:#[^ ]*]] +// CHECK: declare nonnull i8* @_ZnwmSt11align_val_t(i64, i64) [[ATTR_NOBUILTIN:#[^ ]*]] +// CHECK: declare void @_ZdlPvSt11align_val_t(i8*, i64) [[ATTR_NOBUILTIN_NOUNWIND:#[^ ]*]] // CHECK-LABEL: define{{.*}} void @test_sized_delete( extern "C" void test_sized_delete() { - // CHECK: call noalias noundef nonnull i8* @_Znwm(i64 noundef 4) [[ATTR_BUILTIN_NEW:#[^ ]*]] - // CHECK: call void @_ZdlPvm({{.*}}, i64 noundef 4) [[ATTR_BUILTIN_DELETE:#[^ ]*]] + // CHECK: call noalias nonnull i8* @_Znwm(i64 4) [[ATTR_BUILTIN_NEW:#[^ ]*]] + // CHECK: call void @_ZdlPvm({{.*}}, i64 4) [[ATTR_BUILTIN_DELETE:#[^ ]*]] __builtin_operator_delete(__builtin_operator_new(4), 4); } -// CHECK: declare void @_ZdlPvm(i8* noundef, i64 noundef) [[ATTR_NOBUILTIN_UNWIND:#[^ ]*]] +// CHECK: declare void @_ZdlPvm(i8*, i64) [[ATTR_NOBUILTIN_UNWIND:#[^ ]*]] // CHECK-DAG: attributes [[ATTR_NOBUILTIN]] = {{[{].*}} nobuiltin {{.*[}]}} diff --git a/clang/test/CodeGenCXX/builtin-source-location.cpp b/clang/test/CodeGenCXX/builtin-source-location.cpp index 2c5084c67742bc7db2a830c99a5316900fb41173..46be3889d38836b1028ef471d82e263a5d94185a 100644 --- a/clang/test/CodeGenCXX/builtin-source-location.cpp +++ b/clang/test/CodeGenCXX/builtin-source-location.cpp @@ -74,7 +74,7 @@ SL const_init_global = SL::current(); // CHECK-GLOBAL-TWO: define internal void @__cxx_global_var_init() // CHECK-GLOBAL-TWO-NOT: ret // CHECK-GLOBAL-TWO: call void @_ZN15source_location11bad_currentEjjPKcS1_(%struct.source_location* sret(%struct.source_location) align 8 @runtime_init_global, -// CHECK-GLOBAL-TWO-SAME: i32 noundef 1100, i32 noundef {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]], +// CHECK-GLOBAL-TWO-SAME: i32 1100, i32 {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]], #line 1100 "test_runtime_init.cpp" SL runtime_init_global = SL::bad_current(); @@ -86,7 +86,7 @@ extern "C" void test_function() { // CHECK-LOCAL-ONE-DAG: @[[FUNC:.*]] = {{.*}}c"test_function\00" // // CHECK-LOCAL-ONE: call void @_ZN15source_location7currentEjjPKcS1_(%struct.source_location* sret(%struct.source_location) align 8 %local, -// CHECK-LOCAL-ONE-SAME: i32 noundef 2100, i32 noundef {{[0-9]+}}, +// CHECK-LOCAL-ONE-SAME: i32 2100, i32 {{[0-9]+}}, // CHECK-LOCAL-ONE-SAME: {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]], #line 2100 "test_current.cpp" SL local = SL::current(); @@ -111,7 +111,7 @@ struct TestInit { // CHECK-CTOR-GLOBAL-NOT: ret // // CHECK-CTOR-GLOBAL: call void @_ZN15source_location7currentEjjPKcS1_(%struct.source_location* sret(%struct.source_location) align 8 %[[TMP_ONE:[^,]*]], -// CHECK-CTOR-GLOBAL-SAME: i32 noundef 3400, i32 noundef {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]], +// CHECK-CTOR-GLOBAL-SAME: i32 3400, i32 {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]], // CHECK-CTOR-GLOBAL-NEXT: call void @_ZN8TestInitC1E15source_location(%struct.TestInit* {{[^,]*}} @GlobalInitVal, %struct.source_location* {{.*}}%[[TMP_ONE]]) #line 3400 "GlobalInitVal.cpp" TestInit GlobalInitVal; @@ -126,7 +126,7 @@ extern "C" void test_init_function() { // CHECK-CTOR-LOCAL-NOT: ret // // CHECK-CTOR-LOCAL: call void @_ZN15source_location7currentEjjPKcS1_(%struct.source_location* sret(%struct.source_location) align 8 %[[TMP:[^,]*]], -// CHECK-CTOR-LOCAL-SAME: i32 noundef 3500, i32 noundef {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]], +// CHECK-CTOR-LOCAL-SAME: i32 3500, i32 {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]], // CHECK-CTOR-LOCAL-NEXT: call void @_ZN8TestInitC1E15source_location(%struct.TestInit* {{[^,]*}} %init_local, %struct.source_location* {{.*}}%[[TMP]]) #line 3500 "LocalInitVal.cpp" TestInit init_local; @@ -162,7 +162,7 @@ extern "C" void test_init_function_constexpr() { // // CHECK-CONSTEXPR-LOCAL: define{{.*}} void @test_init_function_constexpr() // CHECK-CONSTEXPR-LOCAL: call void @_ZN15source_location7currentEjjPKcS1_(%struct.source_location* sret(%struct.source_location) align 8 %[[TMP:[^,]*]], -// CHECK-CONSTEXPR-LOCAL-SAME: i32 noundef 4600, i32 noundef {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]] +// CHECK-CONSTEXPR-LOCAL-SAME: i32 4600, i32 {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]] // CHECK-CONSTEXPR-LOCAL: call void @_ZN17TestInitConstexprC1E15source_location(%struct.TestInitConstexpr* {{[^,]*}} %local_val, {{.*}}%[[TMP]]) #line 4600 "ConstexprLocal.cpp" TestInitConstexpr local_val; @@ -198,7 +198,7 @@ extern "C" void test_agg_init() { // CHECK-AGG-BRACE: define{{.*}} void @test_agg_init() // CHECK-AGG-BRACE: %[[I2:.*]] = getelementptr inbounds %struct.TestInitAgg, %struct.TestInitAgg* %local_brace_init, i32 0, i32 1 // CHECK-AGG-BRACE-NEXT: call void @_ZN15source_location7currentEjjPKcS1_(%struct.source_location* sret(%struct.source_location) align 8 %[[I2]], -// CHECK-AGG-BRACE-SAME: i32 noundef 5700, i32 noundef {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]] +// CHECK-AGG-BRACE-SAME: i32 5700, i32 {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]] #line 5600 "BraceInitStart.cpp" TestInitAgg local_brace_init{ #line 5700 "BraceInitEnd.cpp" @@ -212,7 +212,7 @@ extern "C" void test_agg_init() { // CHECK-AGG-EQUAL: define{{.*}} void @test_agg_init() // CHECK-AGG-EQUAL: %[[I2:.*]] = getelementptr inbounds %struct.TestInitAgg, %struct.TestInitAgg* %local_equal_init, i32 0, i32 1 // CHECK-AGG-EQUAL-NEXT: call void @_ZN15source_location7currentEjjPKcS1_(%struct.source_location* sret(%struct.source_location) align 8 %[[I2]], -// CHECK-AGG-EQUAL-SAME: i32 noundef 5900, i32 noundef {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]] +// CHECK-AGG-EQUAL-SAME: i32 5900, i32 {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]] #line 5800 "EqualInitStart.cpp" TestInitAgg local_equal_init = { @@ -229,11 +229,11 @@ extern "C" void test_agg_init() { // // CHECK-AGG-LIST: %[[I1:.*]] = getelementptr inbounds %struct.TestInitAgg, %struct.TestInitAgg* %local_list_init, i32 0, i32 0 // CHECK-AGG-LIST-NEXT: call void @_ZN15source_location7currentEjjPKcS1_(%struct.source_location* sret(%struct.source_location) align 8 %[[I1]], -// CHECK-AGG-LIST-SAME: i32 noundef 6100, i32 noundef {{[0-9]+}}, {{[^@]*}}@[[FILE_ELEM]], {{[^@]*}}@[[FUNC]] +// CHECK-AGG-LIST-SAME: i32 6100, i32 {{[0-9]+}}, {{[^@]*}}@[[FILE_ELEM]], {{[^@]*}}@[[FUNC]] // // CHECK-AGG-LIST: %[[I2:.*]] = getelementptr inbounds %struct.TestInitAgg, %struct.TestInitAgg* %local_list_init, i32 0, i32 1 // CHECK-AGG-LIST-NEXT: call void @_ZN15source_location7currentEjjPKcS1_(%struct.source_location* sret(%struct.source_location) align 8 %[[I2]], -// CHECK-AGG-LIST-SAME: i32 noundef 6200, i32 noundef {{[0-9]+}}, {{[^@]*}}@[[FILE_DEFAULT]], {{[^@]*}}@[[FUNC]] +// CHECK-AGG-LIST-SAME: i32 6200, i32 {{[0-9]+}}, {{[^@]*}}@[[FILE_DEFAULT]], {{[^@]*}}@[[FUNC]] #line 6000 "InitListStart.cpp" TestInitAgg local_list_init = { @@ -267,7 +267,7 @@ void test_template() { // CHECK-TEMPL-NOT: ret // // CHECK-TEMPL: call void @_ZN15source_location7currentEjjPKcS1_(%struct.source_location* sret(%struct.source_location) align 8 %[[TMP:[^,]*]], -// CHECK-TEMPL-SAME: i32 noundef 7300, i32 noundef {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]] +// CHECK-TEMPL-SAME: i32 7300, i32 {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]] #line 7300 "local_templ.cpp" TestTemplate local_templ; } diff --git a/clang/test/CodeGenCXX/builtin_FUNCTION.cpp b/clang/test/CodeGenCXX/builtin_FUNCTION.cpp index 9aff8bf9f9f3d41bd20071584b85a71c9e3e748c..02e616351a9395c6b994a56d8545cdfc4fd1f9f6 100644 --- a/clang/test/CodeGenCXX/builtin_FUNCTION.cpp +++ b/clang/test/CodeGenCXX/builtin_FUNCTION.cpp @@ -20,20 +20,20 @@ const char * const global_three = test_default_arg(); // CHECK: @[[STR_TWO:.+]] = private unnamed_addr constant [14 x i8] c"test_func_two\00" // CHECK: @[[STR_THREE:.+]] = private unnamed_addr constant [20 x i8] c"do_default_arg_test\00" -// CHECK: define {{(dso_local )?}}noundef i8* @_ZN9test_func13test_func_oneEv() +// CHECK: define {{(dso_local )?}}i8* @_ZN9test_func13test_func_oneEv() // CHECK: ret i8* getelementptr inbounds ([14 x i8], [14 x i8]* @[[STR_ONE]], i32 0, i32 0) const char *test_func_one() { return __builtin_FUNCTION(); } -// CHECK: define {{(dso_local )?}}noundef i8* @_ZN9test_func13test_func_twoEv() +// CHECK: define {{(dso_local )?}}i8* @_ZN9test_func13test_func_twoEv() // CHECK: ret i8* getelementptr inbounds ([14 x i8], [14 x i8]* @[[STR_TWO]], i32 0, i32 0) const char *test_func_two() { return __builtin_FUNCTION(); } // CHECK: define {{(dso_local )?}}void @_ZN9test_func19do_default_arg_testEv() -// CHECK: %call = call noundef i8* @_ZN9test_func16test_default_argEPKc(i8* noundef getelementptr inbounds ([20 x i8], [20 x i8]* @[[STR_THREE]], i32 0, i32 0)) +// CHECK: %call = call i8* @_ZN9test_func16test_default_argEPKc(i8* getelementptr inbounds ([20 x i8], [20 x i8]* @[[STR_THREE]], i32 0, i32 0)) void do_default_arg_test() { test_default_arg(); } diff --git a/clang/test/CodeGenCXX/builtin_LINE.cpp b/clang/test/CodeGenCXX/builtin_LINE.cpp index 9ef067dad21a2dca6db6075af3dc25cc0419448d..6ae61b43948981a4d23727a22becbcb97fc7f16a 100644 --- a/clang/test/CodeGenCXX/builtin_LINE.cpp +++ b/clang/test/CodeGenCXX/builtin_LINE.cpp @@ -32,7 +32,7 @@ int global_two = get_line_constexpr(); const int global_three(get_line_constexpr()); // CHECK-LABEL: define internal void @__cxx_global_var_init -// CHECK: %call = call noundef i32 @_Z21get_line_nonconstexpri(i32 noundef [[@LINE+2]]) +// CHECK: %call = call i32 @_Z21get_line_nonconstexpri(i32 [[@LINE+2]]) // CHECK-NEXT: store i32 %call, i32* @global_four, align 4 int global_four = get_line_nonconstexpr(); @@ -51,38 +51,38 @@ struct InClassInit { void InClassInit::test_class() { // CHECK: call void @_ZN11InClassInitC1Ev(%struct.InClassInit* {{[^,]*}} %test_one) InClassInit test_one; - // CHECK-NEXT: call void @_ZN11InClassInitC1E4Tag1i(%struct.InClassInit* {{[^,]*}} %test_two, i32 noundef [[@LINE+1]]) + // CHECK-NEXT: call void @_ZN11InClassInitC1E4Tag1i(%struct.InClassInit* {{[^,]*}} %test_two, i32 [[@LINE+1]]) InClassInit test_two{Tag1{}}; // CHECK-NEXT: call void @_ZN11InClassInitC1E4Tag2(%struct.InClassInit* {{[^,]*}} %test_three) InClassInit test_three{Tag2{}}; - // CHECK-NEXT: call void @_ZN11InClassInitC1E4Tag3i(%struct.InClassInit* {{[^,]*}} %test_four, i32 noundef [[@LINE+1]]) + // CHECK-NEXT: call void @_ZN11InClassInitC1E4Tag3i(%struct.InClassInit* {{[^,]*}} %test_four, i32 [[@LINE+1]]) InClassInit test_four(Tag3{}); - // CHECK-NEXT: %[[CALL:.+]] = call noundef i32 @_Z8get_linei(i32 noundef [[@LINE+3]]) - // CHECK-NEXT: %[[CALL2:.+]] = call noundef i32 @_Z9get_line2i(i32 noundef %[[CALL]]) - // CHECK-NEXT: call void @_ZN11InClassInitC1E4Tag4i(%struct.InClassInit* {{[^,]*}} %test_five, i32 noundef %[[CALL2]]) + // CHECK-NEXT: %[[CALL:.+]] = call i32 @_Z8get_linei(i32 [[@LINE+3]]) + // CHECK-NEXT: %[[CALL2:.+]] = call i32 @_Z9get_line2i(i32 %[[CALL]]) + // CHECK-NEXT: call void @_ZN11InClassInitC1E4Tag4i(%struct.InClassInit* {{[^,]*}} %test_five, i32 %[[CALL2]]) InClassInit test_five(Tag4{}); } // CHECK-LABEL: define{{.*}} void @_ZN11InClassInitC2Ev // CHECK: store i32 [[@LINE+4]], i32* %Init, align 4 -// CHECK: %call = call noundef i32 @_Z8get_linei(i32 noundef [[@LINE+3]]) -// CHECK-NEXT: %call2 = call noundef i32 @_Z9get_line2i(i32 noundef %call) +// CHECK: %call = call i32 @_Z8get_linei(i32 [[@LINE+3]]) +// CHECK-NEXT: %call2 = call i32 @_Z9get_line2i(i32 %call) // CHECK-NEXT: store i32 %call2, i32* %Init2, align 4 InClassInit::InClassInit() = default; InClassInit::InClassInit(Tag3, int l) : Init(l) {} -// CHECK-LABEL: define{{.*}} void @_ZN11InClassInitC2E4Tag4i(%struct.InClassInit* {{[^,]*}} %this, i32 noundef %arg) +// CHECK-LABEL: define{{.*}} void @_ZN11InClassInitC2E4Tag4i(%struct.InClassInit* {{[^,]*}} %this, i32 %arg) // CHECK: %[[TEMP:.+]] = load i32, i32* %arg.addr, align 4 // CHECK-NEXT: store i32 %[[TEMP]], i32* %Init, align 4 -// CHECK: %[[CALL:.+]] = call noundef i32 @_Z8get_linei(i32 noundef [[@LINE+3]]) -// CHECK-NEXT: %[[CALL2:.+]] = call noundef i32 @_Z9get_line2i(i32 noundef %[[CALL]]) +// CHECK: %[[CALL:.+]] = call i32 @_Z8get_linei(i32 [[@LINE+3]]) +// CHECK-NEXT: %[[CALL2:.+]] = call i32 @_Z9get_line2i(i32 %[[CALL]]) // CHECK-NEXT: store i32 %[[CALL2]], i32* %Init2, align 4 InClassInit::InClassInit(Tag4, int arg) : Init(arg) {} // CHECK-LABEL: define{{.*}} void @_Z13get_line_testv() void get_line_test() { - // CHECK: %[[CALL:.+]] = call noundef i32 @_Z8get_linei(i32 noundef [[@LINE+2]]) + // CHECK: %[[CALL:.+]] = call i32 @_Z8get_linei(i32 [[@LINE+2]]) // CHECK-NEXT: store i32 %[[CALL]], i32* @sink, align 4 sink = get_line(); // CHECK-NEXT: store i32 [[@LINE+1]], i32* @sink, align 4 diff --git a/clang/test/CodeGenCXX/builtins.cpp b/clang/test/CodeGenCXX/builtins.cpp index c71f01e90c9f615f53b4289c066d7d3cc28c9e24..5a95786beed542f75fd6a45e2aa137f2d15775ba 100644 --- a/clang/test/CodeGenCXX/builtins.cpp +++ b/clang/test/CodeGenCXX/builtins.cpp @@ -38,12 +38,12 @@ int x = __builtin_abs(-2); // CHECK: store i32 2, i32* @x, align 4 long y = __builtin_abs(-2l); -// CHECK: [[Y:%.+]] = call noundef i64 @_Z13__builtin_absl(i64 noundef -2) +// CHECK: [[Y:%.+]] = call i64 @_Z13__builtin_absl(i64 -2) // CHECK: store i64 [[Y]], i64* @y, align 8 extern const char char_memchr_arg[32]; char *memchr_result = __builtin_char_memchr(char_memchr_arg, 123, 32); -// CHECK: call i8* @memchr(i8* noundef getelementptr inbounds ([32 x i8], [32 x i8]* @char_memchr_arg, i64 0, i64 0), i32 noundef 123, i64 noundef 32) +// CHECK: call i8* @memchr(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @char_memchr_arg, i64 0, i64 0), i32 123, i64 32) int constexpr_overflow_result() { constexpr int x = 1; diff --git a/clang/test/CodeGenCXX/call-with-static-chain.cpp b/clang/test/CodeGenCXX/call-with-static-chain.cpp index 83313e4bfa4ac62673f04c374526841d809a6360..2c1e3b42b24ca6e02fd5585645c1af645aef34ce 100644 --- a/clang/test/CodeGenCXX/call-with-static-chain.cpp +++ b/clang/test/CodeGenCXX/call-with-static-chain.cpp @@ -21,19 +21,19 @@ A &f4(); void test() { A a; - // CHECK32: call i32 bitcast (i32 (i32, i32, i32, i32, i32, i32, i32, i32)* @f1 to i32 (i8*, i32, i32, i32, i32, i32, i32, i32, i32)*)(i8* nest noundef bitcast (i32 (i32, i32, i32, i32, i32, i32, i32, i32)* @f1 to i8*) - // CHECK64: call i32 bitcast (i32 (i64, i64, i64, i64, i64, i64, %struct.A*)* @f1 to i32 (i8*, i64, i64, i64, i64, i64, i64, %struct.A*)*)(i8* nest noundef bitcast (i32 (i64, i64, i64, i64, i64, i64, %struct.A*)* @f1 to i8*) + // CHECK32: call i32 bitcast (i32 (i32, i32, i32, i32, i32, i32, i32, i32)* @f1 to i32 (i8*, i32, i32, i32, i32, i32, i32, i32, i32)*)(i8* nest bitcast (i32 (i32, i32, i32, i32, i32, i32, i32, i32)* @f1 to i8*) + // CHECK64: call i32 bitcast (i32 (i64, i64, i64, i64, i64, i64, %struct.A*)* @f1 to i32 (i8*, i64, i64, i64, i64, i64, i64, %struct.A*)*)(i8* nest bitcast (i32 (i64, i64, i64, i64, i64, i64, %struct.A*)* @f1 to i8*) __builtin_call_with_static_chain(f1(a, a, a, a), f1); - // CHECK32: call void bitcast (void (%struct.B*)* @f2 to void (%struct.B*, i8*)*)(%struct.B* sret(%struct.B) align 4 %{{[0-9a-z]+}}, i8* nest noundef bitcast (void (%struct.B*)* @f2 to i8*)) - // CHECK64: call void bitcast (void (%struct.B*)* @f2 to void (%struct.B*, i8*)*)(%struct.B* sret(%struct.B) align 8 %{{[0-9a-z]+}}, i8* nest noundef bitcast (void (%struct.B*)* @f2 to i8*)) + // CHECK32: call void bitcast (void (%struct.B*)* @f2 to void (%struct.B*, i8*)*)(%struct.B* sret(%struct.B) align 4 %{{[0-9a-z]+}}, i8* nest bitcast (void (%struct.B*)* @f2 to i8*)) + // CHECK64: call void bitcast (void (%struct.B*)* @f2 to void (%struct.B*, i8*)*)(%struct.B* sret(%struct.B) align 8 %{{[0-9a-z]+}}, i8* nest bitcast (void (%struct.B*)* @f2 to i8*)) __builtin_call_with_static_chain(f2(), f2); - // CHECK32: call i64 bitcast (i64 ()* @f3 to i64 (i8*)*)(i8* nest noundef bitcast (i64 ()* @f3 to i8*)) - // CHECK64: call <2 x float> bitcast (<2 x float> ()* @f3 to <2 x float> (i8*)*)(i8* nest noundef bitcast (<2 x float> ()* @f3 to i8*)) + // CHECK32: call i64 bitcast (i64 ()* @f3 to i64 (i8*)*)(i8* nest bitcast (i64 ()* @f3 to i8*)) + // CHECK64: call <2 x float> bitcast (<2 x float> ()* @f3 to <2 x float> (i8*)*)(i8* nest bitcast (<2 x float> ()* @f3 to i8*)) __builtin_call_with_static_chain(f3(), f3); - // CHECK32: call nonnull align 4 dereferenceable(8) %struct.A* bitcast (%struct.A* ()* @f4 to %struct.A* (i8*)*)(i8* nest noundef bitcast (%struct.A* ()* @f4 to i8*)) - // CHECK64: call nonnull align 8 dereferenceable(16) %struct.A* bitcast (%struct.A* ()* @f4 to %struct.A* (i8*)*)(i8* nest noundef bitcast (%struct.A* ()* @f4 to i8*)) + // CHECK32: call nonnull align 4 dereferenceable(8) %struct.A* bitcast (%struct.A* ()* @f4 to %struct.A* (i8*)*)(i8* nest bitcast (%struct.A* ()* @f4 to i8*)) + // CHECK64: call nonnull align 8 dereferenceable(16) %struct.A* bitcast (%struct.A* ()* @f4 to %struct.A* (i8*)*)(i8* nest bitcast (%struct.A* ()* @f4 to i8*)) __builtin_call_with_static_chain(f4(), f4); } diff --git a/clang/test/CodeGenCXX/catch-undef-behavior.cpp b/clang/test/CodeGenCXX/catch-undef-behavior.cpp index d6b094cb5b82d438c76e5c4b472d285ce0944d4a..f0799d0dce3c85fd47bb23954345fd3c15dee098 100644 --- a/clang/test/CodeGenCXX/catch-undef-behavior.cpp +++ b/clang/test/CodeGenCXX/catch-undef-behavior.cpp @@ -1,8 +1,8 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -std=c++11 -fsanitize=signed-integer-overflow,integer-divide-by-zero,float-divide-by-zero,shift-base,shift-exponent,unreachable,return,vla-bound,alignment,null,vptr,object-size,float-cast-overflow,bool,enum,array-bounds,function -fsanitize-recover=signed-integer-overflow,integer-divide-by-zero,float-divide-by-zero,shift-base,shift-exponent,vla-bound,alignment,null,vptr,object-size,float-cast-overflow,bool,enum,array-bounds,function -emit-llvm %s -o - -triple x86_64-linux-gnu | opt -instnamer -S | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis -std=c++11 -fsanitize=vptr,address -fsanitize-recover=vptr,address -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-ASAN -// RUN: %clang_cc1 -disable-noundef-analysis -std=c++11 -fsanitize=vptr -fsanitize-recover=vptr -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=DOWNCAST-NULL -// RUN: %clang_cc1 -disable-noundef-analysis -std=c++11 -fsanitize=function -emit-llvm %s -o - -triple x86_64-linux-gnux32 | FileCheck %s --check-prefix=CHECK-X32 -// RUN: %clang_cc1 -disable-noundef-analysis -std=c++11 -fsanitize=function -emit-llvm %s -o - -triple i386-linux-gnu | FileCheck %s --check-prefix=CHECK-X86 +// RUN: %clang_cc1 -std=c++11 -fsanitize=signed-integer-overflow,integer-divide-by-zero,float-divide-by-zero,shift-base,shift-exponent,unreachable,return,vla-bound,alignment,null,vptr,object-size,float-cast-overflow,bool,enum,array-bounds,function -fsanitize-recover=signed-integer-overflow,integer-divide-by-zero,float-divide-by-zero,shift-base,shift-exponent,vla-bound,alignment,null,vptr,object-size,float-cast-overflow,bool,enum,array-bounds,function -emit-llvm %s -o - -triple x86_64-linux-gnu | opt -instnamer -S | FileCheck %s +// RUN: %clang_cc1 -std=c++11 -fsanitize=vptr,address -fsanitize-recover=vptr,address -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-ASAN +// RUN: %clang_cc1 -std=c++11 -fsanitize=vptr -fsanitize-recover=vptr -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=DOWNCAST-NULL +// RUN: %clang_cc1 -std=c++11 -fsanitize=function -emit-llvm %s -o - -triple x86_64-linux-gnux32 | FileCheck %s --check-prefix=CHECK-X32 +// RUN: %clang_cc1 -std=c++11 -fsanitize=function -emit-llvm %s -o - -triple i386-linux-gnu | FileCheck %s --check-prefix=CHECK-X86 struct S { double d; diff --git a/clang/test/CodeGenCXX/cfi-cast.cpp b/clang/test/CodeGenCXX/cfi-cast.cpp index 79e07300867b17441d964b9ab6049b3d67450ee1..014dbb2d226cba6f1673dc6e0e6669aaa4ca619b 100644 --- a/clang/test/CodeGenCXX/cfi-cast.cpp +++ b/clang/test/CodeGenCXX/cfi-cast.cpp @@ -125,8 +125,8 @@ void bcp_call(B *p) { ((C *)p)->f(); } -// CHECK-UCAST-LABEL: define hidden noundef i32 @_Z6a_callP1A -// CHECK-UCAST-STRICT-LABEL: define hidden noundef i32 @_Z6a_callP1A +// CHECK-UCAST-LABEL: define hidden i32 @_Z6a_callP1A +// CHECK-UCAST-STRICT-LABEL: define hidden i32 @_Z6a_callP1A int a_call(A *a) { // CHECK-UCAST-NOT: @llvm.type.test // CHECK-UCAST-STRICT-NOT: @llvm.type.test diff --git a/clang/test/CodeGenCXX/cfi-multiple-inheritance.cpp b/clang/test/CodeGenCXX/cfi-multiple-inheritance.cpp index 27dc0e36ddd8481834eeceaf8d792b128774532c..bebf30d22aada113b92cbc6a9c583deec31ca349 100644 --- a/clang/test/CodeGenCXX/cfi-multiple-inheritance.cpp +++ b/clang/test/CodeGenCXX/cfi-multiple-inheritance.cpp @@ -20,7 +20,7 @@ public: int f1() final { return 2; } }; -// CHECK-LABEL: define hidden noundef i32 @_Z3foov +// CHECK-LABEL: define hidden i32 @_Z3foov int foo() { B b; return static_cast(&b)->f2(); diff --git a/clang/test/CodeGenCXX/cfi-vcall-check-after-args.cpp b/clang/test/CodeGenCXX/cfi-vcall-check-after-args.cpp index 5474c315a95a4e086d5f742980d56b579f861d2d..4c2ea8c9e85fd94ef3fb6fd32add65499f915060 100644 --- a/clang/test/CodeGenCXX/cfi-vcall-check-after-args.cpp +++ b/clang/test/CodeGenCXX/cfi-vcall-check-after-args.cpp @@ -6,7 +6,7 @@ struct A { int g(); void f(A *a) { - // CHECK: call noundef i32 @_Z1gv() + // CHECK: call i32 @_Z1gv() // CHECK: call i1 @llvm.type.test a->f(g()); } diff --git a/clang/test/CodeGenCXX/clang-sections.cpp b/clang/test/CodeGenCXX/clang-sections.cpp index 8bac506e2982c265b5deabcfe491c62c2fd4015d..f252ece30b0c532793c8a59e815ae5241e0b3dfb 100644 --- a/clang/test/CodeGenCXX/clang-sections.cpp +++ b/clang/test/CodeGenCXX/clang-sections.cpp @@ -83,7 +83,7 @@ int hoo(void) { //CHECK: define{{.*}} i32 @foo() #5 { //CHECK: define{{.*}} i32 @goo() #6 { -//CHECK: declare i32 @zoo(i32* noundef, i32* noundef) #7 +//CHECK: declare i32 @zoo(i32*, i32*) #7 //CHECK: define{{.*}} i32 @hoo() #8 { //ELF: attributes #0 = { "bss-section"="my_bss.1" "data-section"="my_data.1" "rodata-section"="my_rodata.1" } diff --git a/clang/test/CodeGenCXX/compound-literals.cpp b/clang/test/CodeGenCXX/compound-literals.cpp index 532c68475bf74a5d7a6078074f92e92dd2202f1a..100f6255a1044bf203b78b5f11f5c3deffeda1a7 100644 --- a/clang/test/CodeGenCXX/compound-literals.cpp +++ b/clang/test/CodeGenCXX/compound-literals.cpp @@ -21,10 +21,10 @@ int f() { // CHECK-NEXT: [[I:%[a-z0-9]+]] = getelementptr inbounds {{.*}}, {{.*}}* [[LVALUE]], i32 0, i32 0 // CHECK-NEXT: store i32 17, i32* [[I]] // CHECK-NEXT: [[X:%[a-z0-9]+]] = getelementptr inbounds {{.*}} [[LVALUE]], i32 0, i32 1 - // CHECK-NEXT: call noundef %struct.X* @_ZN1XC1EPKc({{.*}}[[X]] + // CHECK-NEXT: call %struct.X* @_ZN1XC1EPKc({{.*}}[[X]] // CHECK-NEXT: [[I:%[a-z0-9]+]] = getelementptr inbounds {{.*}} [[LVALUE]], i32 0, i32 0 // CHECK-NEXT: [[RESULT:%[a-z0-9]+]] = load i32, i32* - // CHECK-NEXT: call noundef %struct.Y* @_ZN1YD1Ev + // CHECK-NEXT: call %struct.Y* @_ZN1YD1Ev // CHECK-NEXT: ret i32 [[RESULT]] return ((Y){17, "seventeen"}).i; } @@ -81,5 +81,5 @@ int computed_with_lambda = [] { int *array = (int[]) { 1, 3, 5, 7 }; return array[0]; }(); -// CHECK-LABEL: define internal noundef i32 @{{.*}}clEv +// CHECK-LABEL: define internal i32 @{{.*}}clEv // CHECK: alloca [4 x i32] diff --git a/clang/test/CodeGenCXX/condition.cpp b/clang/test/CodeGenCXX/condition.cpp index 1fcda1a6f643fbfbf1c0ac8446c223dfea664ac9..768c1edb95088f3f276fc0b9845a06b7fa022d6d 100644 --- a/clang/test/CodeGenCXX/condition.cpp +++ b/clang/test/CodeGenCXX/condition.cpp @@ -31,7 +31,7 @@ void if_destruct(int z) { // Verify that the condition variable is destroyed at the end of the // "if" statement. // CHECK: call void @_ZN1XC1Ev - // CHECK: call noundef zeroext i1 @_ZN1XcvbEv + // CHECK: call zeroext i1 @_ZN1XcvbEv if (X x = X()) { // CHECK: store i32 18 z = 18; @@ -50,7 +50,7 @@ void if_destruct(int z) { // CHECK: call void @_ZN1XD1Ev // CHECK: call void @_Z4getXv - // CHECK: call noundef zeroext i1 @_ZN1XcvbEv + // CHECK: call zeroext i1 @_ZN1XcvbEv // CHECK: call void @_ZN1XD1Ev // CHECK: br if (getX()) { } @@ -82,7 +82,7 @@ void switch_destruct(int z) { z = 20; // CHECK: call void @_Z12getConvToIntv - // CHECK: call noundef i32 @_ZN16ConvertibleToIntcviEv + // CHECK: call i32 @_ZN16ConvertibleToIntcviEv // CHECK: call void @_ZN16ConvertibleToIntD1Ev switch(getConvToInt()) { case 0: @@ -101,7 +101,7 @@ void while_destruct(int z) { // CHECK: [[CLEANUPDEST:%.*]] = alloca i32 while (X x = X()) { // CHECK: call void @_ZN1XC1Ev - // CHECK-NEXT: [[COND:%.*]] = call noundef zeroext i1 @_ZN1XcvbEv + // CHECK-NEXT: [[COND:%.*]] = call zeroext i1 @_ZN1XcvbEv // CHECK-NEXT: br i1 [[COND]] // Loop-exit staging block. @@ -124,7 +124,7 @@ void while_destruct(int z) { z = 22; // CHECK: call void @_Z4getXv - // CHECK-NEXT: call noundef zeroext i1 @_ZN1XcvbEv + // CHECK-NEXT: call zeroext i1 @_ZN1XcvbEv // CHECK-NEXT: call void @_ZN1XD1Ev // CHECK-NEXT: br while(getX()) { } @@ -147,7 +147,7 @@ void for_destruct(int z) { for(Y y = Y(); X x = X(); ++z) { // %for.cond: The loop condition. // CHECK: call void @_ZN1XC1Ev - // CHECK-NEXT: [[COND:%.*]] = call noundef zeroext i1 @_ZN1XcvbEv( + // CHECK-NEXT: [[COND:%.*]] = call zeroext i1 @_ZN1XcvbEv( // CHECK-NEXT: br i1 [[COND]] // -> %for.body, %for.cond.cleanup @@ -196,7 +196,7 @@ void for_destruct(int z) { // %for.cond6: // CHECK: call void @_Z4getXv - // CHECK-NEXT: call noundef zeroext i1 @_ZN1XcvbEv + // CHECK-NEXT: call zeroext i1 @_ZN1XcvbEv // CHECK-NEXT: call void @_ZN1XD1Ev // CHECK-NEXT: br // -> %for.body10, %for.end16 @@ -229,7 +229,7 @@ void do_destruct(int z) { // CHECK: store i32 77 z = 77; // CHECK: call void @_Z4getXv - // CHECK: call noundef zeroext i1 @_ZN1XcvbEv + // CHECK: call zeroext i1 @_ZN1XcvbEv // CHECK: call void @_ZN1XD1Ev // CHECK: br } while (getX()); @@ -245,7 +245,7 @@ int instantiated(T x) { int result; // CHECK: call void @_ZN1XC1ERKS_ - // CHECK: call noundef i32 @_Z1f1X + // CHECK: call i32 @_Z1f1X // CHECK: call void @_ZN1XD1Ev // CHECK: br // CHECK: store i32 2 @@ -254,7 +254,7 @@ int instantiated(T x) { if (f(x)) { result = 2; } else { result = 3; } // CHECK: call void @_ZN1XC1ERKS_ - // CHECK: call noundef i32 @_Z1f1X + // CHECK: call i32 @_Z1f1X // CHECK: call void @_ZN1XD1Ev // CHECK: br // CHECK: store i32 4 @@ -262,13 +262,13 @@ int instantiated(T x) { while (f(x)) { result = 4; } // CHECK: call void @_ZN1XC1ERKS_ - // CHECK: call noundef i32 @_Z1f1X + // CHECK: call i32 @_Z1f1X // CHECK: call void @_ZN1XD1Ev // CHECK: br // CHECK: store i32 6 // CHECK: br // CHECK: call void @_ZN1XC1ERKS_ - // CHECK: call noundef i32 @_Z1f1X + // CHECK: call i32 @_Z1f1X // CHECK: store i32 5 // CHECK: call void @_ZN1XD1Ev // CHECK: br @@ -277,7 +277,7 @@ int instantiated(T x) { } // CHECK: call void @_ZN1XC1ERKS_ - // CHECK: call noundef i32 @_Z1f1X + // CHECK: call i32 @_Z1f1X // CHECK: call void @_ZN1XD1Ev // CHECK: switch i32 // CHECK: store i32 7 @@ -294,7 +294,7 @@ int instantiated(T x) { // CHECK: store i32 9 // CHECK: br // CHECK: call void @_ZN1XC1ERKS_ - // CHECK: call noundef i32 @_Z1f1X + // CHECK: call i32 @_Z1f1X // CHECK: call void @_ZN1XD1Ev // CHECK: br do { @@ -303,7 +303,7 @@ int instantiated(T x) { // CHECK: store i32 10 // CHECK: call void @_ZN1XC1ERKS_ - // CHECK: call noundef zeroext i1 @_ZN1XcvbEv + // CHECK: call zeroext i1 @_ZN1XcvbEv // CHECK: call void @_ZN1XD1Ev // CHECK: br do { diff --git a/clang/test/CodeGenCXX/conditional-gnu-ext.cpp b/clang/test/CodeGenCXX/conditional-gnu-ext.cpp index 2920cbfee8696ad90021c0b70fcf439c83626506..ca51113a50e06bf6c660fbf36ddc56333894fcf8 100644 --- a/clang/test/CodeGenCXX/conditional-gnu-ext.cpp +++ b/clang/test/CodeGenCXX/conditional-gnu-ext.cpp @@ -5,7 +5,7 @@ extern "C" int printf(...); void test0() { -// CHECK: call i32 (...) @printf({{.*}}, i8* noundef inttoptr (i64 3735928559 to i8*)) +// CHECK: call i32 (...) @printf({{.*}}, i8* inttoptr (i64 3735928559 to i8*)) printf("%p\n", (void *)0xdeadbeef ? : (void *)0xaaaaaa); } @@ -81,9 +81,9 @@ namespace test3 { // CHECK: [[X:%.*]] = alloca [[B:%.*]]*, // CHECK: store [[B]]* {{%.*}}, [[B]]** [[X]] // CHECK-NEXT: [[T0:%.*]] = load [[B]]*, [[B]]** [[X]] - // CHECK-NEXT: [[BOOL:%.*]] = call noundef zeroext i1 @_ZN5test31BcvbEv([[B]]* {{[^,]*}} [[T0]]) + // CHECK-NEXT: [[BOOL:%.*]] = call zeroext i1 @_ZN5test31BcvbEv([[B]]* {{[^,]*}} [[T0]]) // CHECK-NEXT: br i1 [[BOOL]] - // CHECK: call void @_ZN5test31BC1ERKS0_([[B]]* {{[^,]*}} [[RESULT:%.*]], [[B]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[T0]]) + // CHECK: call void @_ZN5test31BC1ERKS0_([[B]]* {{[^,]*}} [[RESULT:%.*]], [[B]]* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[T0]]) // CHECK-NEXT: br label // CHECK: call void @_ZN5test31BC1Ev([[B]]* {{[^,]*}} [[RESULT]]) // CHECK-NEXT: br label @@ -95,9 +95,9 @@ namespace test3 { // CHECK-LABEL: define{{.*}} void @_ZN5test35test1Ev( // CHECK: [[TEMP:%.*]] = alloca [[B]], // CHECK: call void @_ZN5test312test1_helperEv([[B]]* sret([[B]]) align 1 [[TEMP]]) - // CHECK-NEXT: [[BOOL:%.*]] = call noundef zeroext i1 @_ZN5test31BcvbEv([[B]]* {{[^,]*}} [[TEMP]]) + // CHECK-NEXT: [[BOOL:%.*]] = call zeroext i1 @_ZN5test31BcvbEv([[B]]* {{[^,]*}} [[TEMP]]) // CHECK-NEXT: br i1 [[BOOL]] - // CHECK: call void @_ZN5test31BC1ERKS0_([[B]]* {{[^,]*}} [[RESULT:%.*]], [[B]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[TEMP]]) + // CHECK: call void @_ZN5test31BC1ERKS0_([[B]]* {{[^,]*}} [[RESULT:%.*]], [[B]]* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[TEMP]]) // CHECK-NEXT: br label // CHECK: call void @_ZN5test31BC1Ev([[B]]* {{[^,]*}} [[RESULT]]) // CHECK-NEXT: br label @@ -113,7 +113,7 @@ namespace test3 { // CHECK: [[X:%.*]] = alloca [[B]]*, // CHECK: store [[B]]* {{%.*}}, [[B]]** [[X]] // CHECK-NEXT: [[T0:%.*]] = load [[B]]*, [[B]]** [[X]] - // CHECK-NEXT: [[BOOL:%.*]] = call noundef zeroext i1 @_ZN5test31BcvbEv([[B]]* {{[^,]*}} [[T0]]) + // CHECK-NEXT: [[BOOL:%.*]] = call zeroext i1 @_ZN5test31BcvbEv([[B]]* {{[^,]*}} [[T0]]) // CHECK-NEXT: br i1 [[BOOL]] // CHECK: call void @_ZN5test31BcvNS_1AEEv([[A:%.*]]* sret([[A]]) align 1 [[RESULT:%.*]], [[B]]* {{[^,]*}} [[T0]]) // CHECK-NEXT: br label @@ -127,7 +127,7 @@ namespace test3 { // CHECK-LABEL: define{{.*}} void @_ZN5test35test3Ev( // CHECK: [[TEMP:%.*]] = alloca [[B]], // CHECK: call void @_ZN5test312test3_helperEv([[B]]* sret([[B]]) align 1 [[TEMP]]) - // CHECK-NEXT: [[BOOL:%.*]] = call noundef zeroext i1 @_ZN5test31BcvbEv([[B]]* {{[^,]*}} [[TEMP]]) + // CHECK-NEXT: [[BOOL:%.*]] = call zeroext i1 @_ZN5test31BcvbEv([[B]]* {{[^,]*}} [[TEMP]]) // CHECK-NEXT: br i1 [[BOOL]] // CHECK: call void @_ZN5test31BcvNS_1AEEv([[A]]* sret([[A]]) align 1 [[RESULT:%.*]], [[B]]* {{[^,]*}} [[TEMP]]) // CHECK-NEXT: br label diff --git a/clang/test/CodeGenCXX/conditional-temporaries.cpp b/clang/test/CodeGenCXX/conditional-temporaries.cpp index f697efa123dab2a6157ea3bf6fc9373fe5eb2c61..da692518782f26a9b75cf86aff93af2830913ec4 100644 --- a/clang/test/CodeGenCXX/conditional-temporaries.cpp +++ b/clang/test/CodeGenCXX/conditional-temporaries.cpp @@ -1,10 +1,7 @@ // REQUIRES: amdgpu-registered-target -// RUN: %clang_cc1 -emit-llvm %s -o - -triple=x86_64-apple-darwin9 -O2 -fno-experimental-new-pass-manager -disable-llvm-passes | FileCheck %s --check-prefixes=CHECK,CHECK-NOOPT -// RUN: %clang_cc1 -emit-llvm %s -o - -triple=x86_64-apple-darwin9 -O2 -fno-experimental-new-pass-manager | FileCheck %s --check-prefixes=CHECK,CHECK-OPT -// RUN: %clang_cc1 -emit-llvm %s -o - -triple=amdgcn-amd-amdhsa -O2 -fno-experimental-new-pass-manager | FileCheck %s --check-prefixes=CHECK,CHECK-OPT -// RUN: %clang_cc1 -emit-llvm %s -o - -triple=x86_64-apple-darwin9 -O2 -fexperimental-new-pass-manager -disable-llvm-passes | FileCheck %s --check-prefixes=CHECK,CHECK-NOOPT -// RUN: %clang_cc1 -emit-llvm %s -o - -triple=x86_64-apple-darwin9 -O2 -fexperimental-new-pass-manager | FileCheck %s --check-prefixes=CHECK,CHECK-OPT -// RUN: %clang_cc1 -emit-llvm %s -o - -triple=amdgcn-amd-amdhsa -O2 -fexperimental-new-pass-manager | FileCheck %s --check-prefixes=CHECK,CHECK-OPT +// RUN: %clang_cc1 -emit-llvm %s -o - -triple=x86_64-apple-darwin9 -O2 -disable-llvm-passes | FileCheck %s --check-prefixes=CHECK,CHECK-NOOPT +// RUN: %clang_cc1 -emit-llvm %s -o - -triple=x86_64-apple-darwin9 -O2 | FileCheck %s --check-prefixes=CHECK,CHECK-OPT +// RUN: %clang_cc1 -emit-llvm %s -o - -triple=amdgcn-amd-amdhsa -O2 | FileCheck %s --check-prefixes=CHECK,CHECK-OPT namespace { @@ -75,19 +72,19 @@ int lifetime_nontriv(bool cond) { // CHECK-NOOPT: call void @llvm.lifetime.start // CHECK-NOOPT: store i1 true, // CHECK-NOOPT: store i1 true, - // CHECK-NOOPT: call noundef i32 @_ZN1X1fEv( + // CHECK-NOOPT: call i32 @_ZN1X1fEv( // CHECK-NOOPT: call void @llvm.lifetime.start // CHECK-NOOPT: store i1 true, // CHECK-NOOPT: store i1 true, - // CHECK-NOOPT: call noundef i32 @_ZN1X1fEv( + // CHECK-NOOPT: call i32 @_ZN1X1fEv( // CHECK-NOOPT: call void @llvm.lifetime.start // CHECK-NOOPT: store i1 true, // CHECK-NOOPT: store i1 true, - // CHECK-NOOPT: call noundef i32 @_ZN1X1fEv( - // CHECK-NOOPT: call noundef i32 @_Z1giii( + // CHECK-NOOPT: call i32 @_ZN1X1fEv( + // CHECK-NOOPT: call i32 @_Z1giii( // CHECK-NOOPT: br label // - // CHECK-NOOPT: call noundef i32 @_Z1giii(i32 noundef 1, i32 noundef 2, i32 noundef 3) + // CHECK-NOOPT: call i32 @_Z1giii(i32 1, i32 2, i32 3) // CHECK-NOOPT: br label // // CHECK-NOOPT: load i1, @@ -125,12 +122,12 @@ int lifetime_nontriv(bool cond) { // CHECK-OPT: br i1 // // CHECK-OPT: call void @llvm.lifetime.start - // CHECK-OPT: call noundef i32 @_ZN1X1fEv( + // CHECK-OPT: call i32 @_ZN1X1fEv( // CHECK-OPT: call void @llvm.lifetime.start - // CHECK-OPT: call noundef i32 @_ZN1X1fEv( + // CHECK-OPT: call i32 @_ZN1X1fEv( // CHECK-OPT: call void @llvm.lifetime.start - // CHECK-OPT: call noundef i32 @_ZN1X1fEv( - // CHECK-OPT: call noundef i32 @_Z1giii( + // CHECK-OPT: call i32 @_ZN1X1fEv( + // CHECK-OPT: call i32 @_Z1giii( // CHECK-OPT: call void @_ZN1XD1Ev( // CHECK-OPT: call void @llvm.lifetime.end // CHECK-OPT: call void @_ZN1XD1Ev( @@ -150,13 +147,13 @@ int lifetime_triv(bool cond) { // CHECK-NOOPT: call void @llvm.lifetime.start // CHECK-NOOPT: br i1 // - // CHECK-NOOPT: call noundef i32 @_ZN1Y1fEv( - // CHECK-NOOPT: call noundef i32 @_ZN1Y1fEv( - // CHECK-NOOPT: call noundef i32 @_ZN1Y1fEv( - // CHECK-NOOPT: call noundef i32 @_Z1giii( + // CHECK-NOOPT: call i32 @_ZN1Y1fEv( + // CHECK-NOOPT: call i32 @_ZN1Y1fEv( + // CHECK-NOOPT: call i32 @_ZN1Y1fEv( + // CHECK-NOOPT: call i32 @_Z1giii( // CHECK-NOOPT: br label // - // CHECK-NOOPT: call noundef i32 @_Z1giii(i32 noundef 1, i32 noundef 2, i32 noundef 3) + // CHECK-NOOPT: call i32 @_Z1giii(i32 1, i32 2, i32 3) // CHECK-NOOPT: br label // // CHECK-NOOPT: call void @llvm.lifetime.end @@ -175,10 +172,10 @@ int lifetime_triv(bool cond) { // CHECK-OPT: call void @llvm.lifetime.start // CHECK-OPT: br i1 // - // CHECK-OPT: call noundef i32 @_ZN1Y1fEv( - // CHECK-OPT: call noundef i32 @_ZN1Y1fEv( - // CHECK-OPT: call noundef i32 @_ZN1Y1fEv( - // CHECK-OPT: call noundef i32 @_Z1giii( + // CHECK-OPT: call i32 @_ZN1Y1fEv( + // CHECK-OPT: call i32 @_ZN1Y1fEv( + // CHECK-OPT: call i32 @_ZN1Y1fEv( + // CHECK-OPT: call i32 @_Z1giii( // CHECK-OPT: br label // // CHECK-OPT: call void @llvm.lifetime.end @@ -194,12 +191,12 @@ int lifetime_nontriv_empty(bool cond) { // CHECK-OPT: br i1 // // CHECK-OPT: call void @llvm.lifetime.start - // CHECK-OPT: call noundef i32 @_ZN1Z1fEv( + // CHECK-OPT: call i32 @_ZN1Z1fEv( // CHECK-OPT: call void @llvm.lifetime.start - // CHECK-OPT: call noundef i32 @_ZN1Z1fEv( + // CHECK-OPT: call i32 @_ZN1Z1fEv( // CHECK-OPT: call void @llvm.lifetime.start - // CHECK-OPT: call noundef i32 @_ZN1Z1fEv( - // CHECK-OPT: call noundef i32 @_Z1giii( + // CHECK-OPT: call i32 @_ZN1Z1fEv( + // CHECK-OPT: call i32 @_Z1giii( // CHECK-OPT: call void @llvm.lifetime.end // CHECK-OPT: call void @llvm.lifetime.end // CHECK-OPT: call void @llvm.lifetime.end diff --git a/clang/test/CodeGenCXX/const-init-cxx11.cpp b/clang/test/CodeGenCXX/const-init-cxx11.cpp index f90281f2d2a799c46d47847ef8fc524a2a7018c5..52408cf3b077f344ffcec2bef218e6cd53f3d049 100644 --- a/clang/test/CodeGenCXX/const-init-cxx11.cpp +++ b/clang/test/CodeGenCXX/const-init-cxx11.cpp @@ -531,7 +531,7 @@ namespace Unreferenced { const int &rt = t; int f(int); int u = f(rt); - // CHECK: call noundef i32 @_ZN12Unreferenced1fEi(i32 noundef 1) + // CHECK: call i32 @_ZN12Unreferenced1fEi(i32 1) } namespace InitFromConst { @@ -549,28 +549,28 @@ namespace InitFromConst { constexpr int a[3] = { 1, 4, 9 }; void test() { - // CHECK: call void @_ZN13InitFromConst7consumeIbEEvT_(i1 noundef zeroext true) + // CHECK: call void @_ZN13InitFromConst7consumeIbEEvT_(i1 zeroext true) consume(b); - // CHECK: call void @_ZN13InitFromConst7consumeIiEEvT_(i32 noundef 5) + // CHECK: call void @_ZN13InitFromConst7consumeIiEEvT_(i32 5) consume(n); - // CHECK: call void @_ZN13InitFromConst7consumeIdEEvT_(double noundef 4.300000e+00) + // CHECK: call void @_ZN13InitFromConst7consumeIdEEvT_(double 4.300000e+00) consume(d); - // CHECK: call void @_ZN13InitFromConst7consumeIRKNS_1SEEEvT_(%"struct.InitFromConst::S"* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) @_ZN13InitFromConstL1sE) + // CHECK: call void @_ZN13InitFromConst7consumeIRKNS_1SEEEvT_(%"struct.InitFromConst::S"* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) @_ZN13InitFromConstL1sE) consume(s); - // CHECK: call void @_ZN13InitFromConst7consumeIRKNS_1SEEEvT_(%"struct.InitFromConst::S"* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) @_ZN13InitFromConstL1sE) + // CHECK: call void @_ZN13InitFromConst7consumeIRKNS_1SEEEvT_(%"struct.InitFromConst::S"* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) @_ZN13InitFromConstL1sE) consume(r); - // CHECK: call void @_ZN13InitFromConst7consumeIPKNS_1SEEEvT_(%"struct.InitFromConst::S"* noundef @_ZN13InitFromConstL1sE) + // CHECK: call void @_ZN13InitFromConst7consumeIPKNS_1SEEEvT_(%"struct.InitFromConst::S"* @_ZN13InitFromConstL1sE) consume(p); // CHECK: call void @_ZN13InitFromConst7consumeIMNS_1SEiEEvT_(i64 0) consume(mp); - // CHECK: call void @_ZN13InitFromConst7consumeIPKiEEvT_(i32* noundef getelementptr inbounds ([3 x i32], [3 x i32]* @_ZN13InitFromConstL1aE, i64 0, i64 0)) + // CHECK: call void @_ZN13InitFromConst7consumeIPKiEEvT_(i32* getelementptr inbounds ([3 x i32], [3 x i32]* @_ZN13InitFromConstL1aE, i64 0, i64 0)) consume(a); } } diff --git a/clang/test/CodeGenCXX/constructor-destructor-return-this.cpp b/clang/test/CodeGenCXX/constructor-destructor-return-this.cpp index cb0980aa341ef918126d85cf884ebc07ffd53f24..7c89eb0c0079331637301adb99d68902811fc4e6 100644 --- a/clang/test/CodeGenCXX/constructor-destructor-return-this.cpp +++ b/clang/test/CodeGenCXX/constructor-destructor-return-this.cpp @@ -32,27 +32,27 @@ private: B::B(int *i) : i_(i) { } B::~B() { } -// CHECKGEN-LABEL: define{{.*}} void @_ZN1BC2EPi(%class.B* {{[^,]*}} %this, i32* noundef %i) -// CHECKGEN-LABEL: define{{.*}} void @_ZN1BC1EPi(%class.B* {{[^,]*}} %this, i32* noundef %i) +// CHECKGEN-LABEL: define{{.*}} void @_ZN1BC2EPi(%class.B* {{[^,]*}} %this, i32* %i) +// CHECKGEN-LABEL: define{{.*}} void @_ZN1BC1EPi(%class.B* {{[^,]*}} %this, i32* %i) // CHECKGEN-LABEL: define{{.*}} void @_ZN1BD2Ev(%class.B* {{[^,]*}} %this) // CHECKGEN-LABEL: define{{.*}} void @_ZN1BD1Ev(%class.B* {{[^,]*}} %this) -// CHECKARM-LABEL: define{{.*}} %class.B* @_ZN1BC2EPi(%class.B* {{[^,]*}} returned %this, i32* noundef %i) -// CHECKARM-LABEL: define{{.*}} %class.B* @_ZN1BC1EPi(%class.B* {{[^,]*}} returned %this, i32* noundef %i) -// CHECKARM-LABEL: define{{.*}} %class.B* @_ZN1BD2Ev(%class.B* {{[^,]*}} returned %this) -// CHECKARM-LABEL: define{{.*}} %class.B* @_ZN1BD1Ev(%class.B* {{[^,]*}} returned %this) +// CHECKARM-LABEL: define{{.*}} %class.B* @_ZN1BC2EPi(%class.B* {{[^,]*}} returned {{[^,]*}} %this, i32* %i) +// CHECKARM-LABEL: define{{.*}} %class.B* @_ZN1BC1EPi(%class.B* {{[^,]*}} returned {{[^,]*}} %this, i32* %i) +// CHECKARM-LABEL: define{{.*}} %class.B* @_ZN1BD2Ev(%class.B* {{[^,]*}} returned {{[^,]*}} %this) +// CHECKARM-LABEL: define{{.*}} %class.B* @_ZN1BD1Ev(%class.B* {{[^,]*}} returned {{[^,]*}} %this) -// CHECKIOS5-LABEL: define{{.*}} %class.B* @_ZN1BC2EPi(%class.B* {{[^,]*}} %this, i32* noundef %i) -// CHECKIOS5-LABEL: define{{.*}} %class.B* @_ZN1BC1EPi(%class.B* {{[^,]*}} %this, i32* noundef %i) +// CHECKIOS5-LABEL: define{{.*}} %class.B* @_ZN1BC2EPi(%class.B* {{[^,]*}} %this, i32* %i) +// CHECKIOS5-LABEL: define{{.*}} %class.B* @_ZN1BC1EPi(%class.B* {{[^,]*}} %this, i32* %i) // CHECKIOS5-LABEL: define{{.*}} %class.B* @_ZN1BD2Ev(%class.B* {{[^,]*}} %this) // CHECKIOS5-LABEL: define{{.*}} %class.B* @_ZN1BD1Ev(%class.B* {{[^,]*}} %this) -// CHECKFUCHSIA-LABEL: define{{.*}} %class.B* @_ZN1BC2EPi(%class.B* {{[^,]*}} returned %this, i32* noundef %i) -// CHECKFUCHSIA-LABEL: define{{.*}} %class.B* @_ZN1BC1EPi(%class.B* {{[^,]*}} returned %this, i32* noundef %i) -// CHECKFUCHSIA-LABEL: define{{.*}} %class.B* @_ZN1BD2Ev(%class.B* {{[^,]*}} returned %this) -// CHECKFUCHSIA-LABEL: define{{.*}} %class.B* @_ZN1BD1Ev(%class.B* {{[^,]*}} returned %this) +// CHECKFUCHSIA-LABEL: define{{.*}} %class.B* @_ZN1BC2EPi(%class.B* {{[^,]*}} returned {{[^,]*}} %this, i32* %i) +// CHECKFUCHSIA-LABEL: define{{.*}} %class.B* @_ZN1BC1EPi(%class.B* {{[^,]*}} returned {{[^,]*}} %this, i32* %i) +// CHECKFUCHSIA-LABEL: define{{.*}} %class.B* @_ZN1BD2Ev(%class.B* {{[^,]*}} returned {{[^,]*}} %this) +// CHECKFUCHSIA-LABEL: define{{.*}} %class.B* @_ZN1BD1Ev(%class.B* {{[^,]*}} returned {{[^,]*}} %this) -// CHECKMS-LABEL: define dso_local x86_thiscallcc noundef %class.B* @"??0B@@QAE@PAH@Z"(%class.B* {{[^,]*}} returned %this, i32* noundef %i) +// CHECKMS-LABEL: define dso_local x86_thiscallcc %class.B* @"??0B@@QAE@PAH@Z"(%class.B* {{[^,]*}} returned {{[^,]*}} %this, i32* %i) // CHECKMS-LABEL: define dso_local x86_thiscallcc void @"??1B@@UAE@XZ"(%class.B* {{[^,]*}} %this) class C : public A, public B { @@ -66,39 +66,39 @@ private: C::C(int *i, char *c) : B(i), c_(c) { } C::~C() { } -// CHECKGEN-LABEL: define{{.*}} void @_ZN1CC2EPiPc(%class.C* {{[^,]*}} %this, i32* noundef %i, i8* noundef %c) -// CHECKGEN-LABEL: define{{.*}} void @_ZN1CC1EPiPc(%class.C* {{[^,]*}} %this, i32* noundef %i, i8* noundef %c) +// CHECKGEN-LABEL: define{{.*}} void @_ZN1CC2EPiPc(%class.C* {{[^,]*}} %this, i32* %i, i8* %c) +// CHECKGEN-LABEL: define{{.*}} void @_ZN1CC1EPiPc(%class.C* {{[^,]*}} %this, i32* %i, i8* %c) // CHECKGEN-LABEL: define{{.*}} void @_ZN1CD2Ev(%class.C* {{[^,]*}} %this) // CHECKGEN-LABEL: define{{.*}} void @_ZN1CD1Ev(%class.C* {{[^,]*}} %this) -// CHECKGEN-LABEL: define{{.*}} void @_ZThn8_N1CD1Ev(%class.C* noundef %this) +// CHECKGEN-LABEL: define{{.*}} void @_ZThn8_N1CD1Ev(%class.C* %this) // CHECKGEN-LABEL: define{{.*}} void @_ZN1CD0Ev(%class.C* {{[^,]*}} %this) -// CHECKGEN-LABEL: define{{.*}} void @_ZThn8_N1CD0Ev(%class.C* noundef %this) +// CHECKGEN-LABEL: define{{.*}} void @_ZThn8_N1CD0Ev(%class.C* %this) -// CHECKARM-LABEL: define{{.*}} %class.C* @_ZN1CC2EPiPc(%class.C* {{[^,]*}} returned %this, i32* noundef %i, i8* noundef %c) -// CHECKARM-LABEL: define{{.*}} %class.C* @_ZN1CC1EPiPc(%class.C* {{[^,]*}} returned %this, i32* noundef %i, i8* noundef %c) -// CHECKARM-LABEL: define{{.*}} %class.C* @_ZN1CD2Ev(%class.C* {{[^,]*}} returned %this) -// CHECKARM-LABEL: define{{.*}} %class.C* @_ZN1CD1Ev(%class.C* {{[^,]*}} returned %this) -// CHECKARM-LABEL: define{{.*}} %class.C* @_ZThn8_N1CD1Ev(%class.C* noundef %this) +// CHECKARM-LABEL: define{{.*}} %class.C* @_ZN1CC2EPiPc(%class.C* {{[^,]*}} returned {{[^,]*}} %this, i32* %i, i8* %c) +// CHECKARM-LABEL: define{{.*}} %class.C* @_ZN1CC1EPiPc(%class.C* {{[^,]*}} returned {{[^,]*}} %this, i32* %i, i8* %c) +// CHECKARM-LABEL: define{{.*}} %class.C* @_ZN1CD2Ev(%class.C* {{[^,]*}} returned {{[^,]*}} %this) +// CHECKARM-LABEL: define{{.*}} %class.C* @_ZN1CD1Ev(%class.C* {{[^,]*}} returned {{[^,]*}} %this) +// CHECKARM-LABEL: define{{.*}} %class.C* @_ZThn8_N1CD1Ev(%class.C* %this) // CHECKARM-LABEL: define{{.*}} void @_ZN1CD0Ev(%class.C* {{[^,]*}} %this) -// CHECKARM-LABEL: define{{.*}} void @_ZThn8_N1CD0Ev(%class.C* noundef %this) +// CHECKARM-LABEL: define{{.*}} void @_ZThn8_N1CD0Ev(%class.C* %this) -// CHECKIOS5-LABEL: define{{.*}} %class.C* @_ZN1CC2EPiPc(%class.C* {{[^,]*}} %this, i32* noundef %i, i8* noundef %c) -// CHECKIOS5-LABEL: define{{.*}} %class.C* @_ZN1CC1EPiPc(%class.C* {{[^,]*}} %this, i32* noundef %i, i8* noundef %c) +// CHECKIOS5-LABEL: define{{.*}} %class.C* @_ZN1CC2EPiPc(%class.C* {{[^,]*}} %this, i32* %i, i8* %c) +// CHECKIOS5-LABEL: define{{.*}} %class.C* @_ZN1CC1EPiPc(%class.C* {{[^,]*}} %this, i32* %i, i8* %c) // CHECKIOS5-LABEL: define{{.*}} %class.C* @_ZN1CD2Ev(%class.C* {{[^,]*}} %this) // CHECKIOS5-LABEL: define{{.*}} %class.C* @_ZN1CD1Ev(%class.C* {{[^,]*}} %this) -// CHECKIOS5-LABEL: define{{.*}} %class.C* @_ZThn8_N1CD1Ev(%class.C* noundef %this) +// CHECKIOS5-LABEL: define{{.*}} %class.C* @_ZThn8_N1CD1Ev(%class.C* %this) // CHECKIOS5-LABEL: define{{.*}} void @_ZN1CD0Ev(%class.C* {{[^,]*}} %this) -// CHECKIOS5-LABEL: define{{.*}} void @_ZThn8_N1CD0Ev(%class.C* noundef %this) +// CHECKIOS5-LABEL: define{{.*}} void @_ZThn8_N1CD0Ev(%class.C* %this) -// CHECKFUCHSIA-LABEL: define{{.*}} %class.C* @_ZN1CC2EPiPc(%class.C* {{[^,]*}} returned %this, i32* noundef %i, i8* noundef %c) -// CHECKFUCHSIA-LABEL: define{{.*}} %class.C* @_ZN1CC1EPiPc(%class.C* {{[^,]*}} returned %this, i32* noundef %i, i8* noundef %c) -// CHECKFUCHSIA-LABEL: define{{.*}} %class.C* @_ZN1CD2Ev(%class.C* {{[^,]*}} returned %this) -// CHECKFUCHSIA-LABEL: define{{.*}} %class.C* @_ZN1CD1Ev(%class.C* {{[^,]*}} returned %this) -// CHECKFUCHSIA-LABEL: define{{.*}} %class.C* @_ZThn16_N1CD1Ev(%class.C* noundef %this) +// CHECKFUCHSIA-LABEL: define{{.*}} %class.C* @_ZN1CC2EPiPc(%class.C* {{[^,]*}} returned {{[^,]*}} %this, i32* %i, i8* %c) +// CHECKFUCHSIA-LABEL: define{{.*}} %class.C* @_ZN1CC1EPiPc(%class.C* {{[^,]*}} returned {{[^,]*}} %this, i32* %i, i8* %c) +// CHECKFUCHSIA-LABEL: define{{.*}} %class.C* @_ZN1CD2Ev(%class.C* {{[^,]*}} returned {{[^,]*}} %this) +// CHECKFUCHSIA-LABEL: define{{.*}} %class.C* @_ZN1CD1Ev(%class.C* {{[^,]*}} returned {{[^,]*}} %this) +// CHECKFUCHSIA-LABEL: define{{.*}} %class.C* @_ZThn16_N1CD1Ev(%class.C* %this) // CHECKFUCHSIA-LABEL: define{{.*}} void @_ZN1CD0Ev(%class.C* {{[^,]*}} %this) -// CHECKFUCHSIA-LABEL: define{{.*}} void @_ZThn16_N1CD0Ev(%class.C* noundef %this) +// CHECKFUCHSIA-LABEL: define{{.*}} void @_ZThn16_N1CD0Ev(%class.C* %this) -// CHECKMS-LABEL: define dso_local x86_thiscallcc noundef %class.C* @"??0C@@QAE@PAHPAD@Z"(%class.C* {{[^,]*}} returned %this, i32* noundef %i, i8* noundef %c) +// CHECKMS-LABEL: define dso_local x86_thiscallcc %class.C* @"??0C@@QAE@PAHPAD@Z"(%class.C* {{[^,]*}} returned {{[^,]*}} %this, i32* %i, i8* %c) // CHECKMS-LABEL: define dso_local x86_thiscallcc void @"??1C@@UAE@XZ"(%class.C* {{[^,]*}} %this) class D : public virtual A { @@ -110,27 +110,27 @@ public: D::D() { } D::~D() { } -// CHECKGEN-LABEL: define{{.*}} void @_ZN1DC2Ev(%class.D* {{[^,]*}} %this, i8** noundef %vtt) +// CHECKGEN-LABEL: define{{.*}} void @_ZN1DC2Ev(%class.D* {{[^,]*}} %this, i8** %vtt) // CHECKGEN-LABEL: define{{.*}} void @_ZN1DC1Ev(%class.D* {{[^,]*}} %this) -// CHECKGEN-LABEL: define{{.*}} void @_ZN1DD2Ev(%class.D* {{[^,]*}} %this, i8** noundef %vtt) +// CHECKGEN-LABEL: define{{.*}} void @_ZN1DD2Ev(%class.D* {{[^,]*}} %this, i8** %vtt) // CHECKGEN-LABEL: define{{.*}} void @_ZN1DD1Ev(%class.D* {{[^,]*}} %this) -// CHECKARM-LABEL: define{{.*}} %class.D* @_ZN1DC2Ev(%class.D* {{[^,]*}} returned %this, i8** noundef %vtt) -// CHECKARM-LABEL: define{{.*}} %class.D* @_ZN1DC1Ev(%class.D* {{[^,]*}} returned %this) -// CHECKARM-LABEL: define{{.*}} %class.D* @_ZN1DD2Ev(%class.D* {{[^,]*}} returned %this, i8** noundef %vtt) -// CHECKARM-LABEL: define{{.*}} %class.D* @_ZN1DD1Ev(%class.D* {{[^,]*}} returned %this) +// CHECKARM-LABEL: define{{.*}} %class.D* @_ZN1DC2Ev(%class.D* {{[^,]*}} returned {{[^,]*}} %this, i8** %vtt) +// CHECKARM-LABEL: define{{.*}} %class.D* @_ZN1DC1Ev(%class.D* {{[^,]*}} returned {{[^,]*}} %this) +// CHECKARM-LABEL: define{{.*}} %class.D* @_ZN1DD2Ev(%class.D* {{[^,]*}} returned {{[^,]*}} %this, i8** %vtt) +// CHECKARM-LABEL: define{{.*}} %class.D* @_ZN1DD1Ev(%class.D* {{[^,]*}} returned {{[^,]*}} %this) -// CHECKIOS5-LABEL: define{{.*}} %class.D* @_ZN1DC2Ev(%class.D* {{[^,]*}} %this, i8** noundef %vtt) +// CHECKIOS5-LABEL: define{{.*}} %class.D* @_ZN1DC2Ev(%class.D* {{[^,]*}} %this, i8** %vtt) // CHECKIOS5-LABEL: define{{.*}} %class.D* @_ZN1DC1Ev(%class.D* {{[^,]*}} %this) -// CHECKIOS5-LABEL: define{{.*}} %class.D* @_ZN1DD2Ev(%class.D* {{[^,]*}} %this, i8** noundef %vtt) +// CHECKIOS5-LABEL: define{{.*}} %class.D* @_ZN1DD2Ev(%class.D* {{[^,]*}} %this, i8** %vtt) // CHECKIOS5-LABEL: define{{.*}} %class.D* @_ZN1DD1Ev(%class.D* {{[^,]*}} %this) -// CHECKFUCHSIA-LABEL: define{{.*}} %class.D* @_ZN1DC2Ev(%class.D* {{[^,]*}} returned %this, i8** noundef %vtt) -// CHECKFUCHSIA-LABEL: define{{.*}} %class.D* @_ZN1DC1Ev(%class.D* {{[^,]*}} returned %this) -// CHECKFUCHSIA-LABEL: define{{.*}} %class.D* @_ZN1DD2Ev(%class.D* {{[^,]*}} returned %this, i8** noundef %vtt) -// CHECKFUCHSIA-LABEL: define{{.*}} %class.D* @_ZN1DD1Ev(%class.D* {{[^,]*}} returned %this) +// CHECKFUCHSIA-LABEL: define{{.*}} %class.D* @_ZN1DC2Ev(%class.D* {{[^,]*}} returned {{[^,]*}} %this, i8** %vtt) +// CHECKFUCHSIA-LABEL: define{{.*}} %class.D* @_ZN1DC1Ev(%class.D* {{[^,]*}} returned {{[^,]*}} %this) +// CHECKFUCHSIA-LABEL: define{{.*}} %class.D* @_ZN1DD2Ev(%class.D* {{[^,]*}} returned {{[^,]*}} %this, i8** %vtt) +// CHECKFUCHSIA-LABEL: define{{.*}} %class.D* @_ZN1DD1Ev(%class.D* {{[^,]*}} returned {{[^,]*}} %this) -// CHECKMS-LABEL: define dso_local x86_thiscallcc noundef %class.D* @"??0D@@QAE@XZ"(%class.D* {{[^,]*}} returned %this, i32 noundef %is_most_derived) +// CHECKMS-LABEL: define dso_local x86_thiscallcc %class.D* @"??0D@@QAE@XZ"(%class.D* {{[^,]*}} returned {{[^,]*}} %this, i32 %is_most_derived) // CHECKMS-LABEL: define dso_local x86_thiscallcc void @"??1D@@UAE@XZ"(%class.D* {{[^,]*}} %this) class E { @@ -155,9 +155,9 @@ void test_destructor() { // CHECKARM: [[THUNK:%.*]] = load %class.E* (%class.E*)*, %class.E* (%class.E*)** [[VFN]] // CHECKFUCHSIA: [[THUNK_I8:%.*]] = call i8* @llvm.load.relative.i32(i8* {{.*}}, i32 0) // CHECKFUCHSIA: [[THUNK:%.*]] = bitcast i8* [[THUNK_I8]] to %class.E* (%class.E*)* -// CHECKARM,CHECKFUCHSIA: call noundef %class.E* [[THUNK]](%class.E* {{[^,]*}} % +// CHECKARM,CHECKFUCHSIA: call %class.E* [[THUNK]](%class.E* {{[^,]*}} % // ...but static calls create declarations with 'returned' this -// CHECKARM,CHECKFUCHSIA: {{%.*}} = call noundef %class.E* @_ZN1ED1Ev(%class.E* {{[^,]*}} % +// CHECKARM,CHECKFUCHSIA: {{%.*}} = call %class.E* @_ZN1ED1Ev(%class.E* {{[^,]*}} % -// CHECKARM,CHECKFUCHSIA: declare noundef %class.E* @_ZN1ED1Ev(%class.E* {{[^,]*}} returned) +// CHECKARM,CHECKFUCHSIA: declare %class.E* @_ZN1ED1Ev(%class.E* {{[^,]*}} returned {{[^,]*}}) diff --git a/clang/test/CodeGenCXX/constructor-direct-call.cpp b/clang/test/CodeGenCXX/constructor-direct-call.cpp index d1918ed7c6d5a832e325503878c5a5496540fab6..fba75350f67ba0a62260138307453802ccdad43d 100644 --- a/clang/test/CodeGenCXX/constructor-direct-call.cpp +++ b/clang/test/CodeGenCXX/constructor-direct-call.cpp @@ -25,11 +25,11 @@ public: void f2() { // CHECK: %var = alloca %class.Test2, align 4 // CHECK32-NEXT: call x86_thiscallcc void @_ZN5Test2C1Ev(%class.Test2* {{[^,]*}} %var) - // CHECK64-NEXT: %call = call noundef %class.Test2* @"??0Test2@@QEAA@XZ"(%class.Test2* {{[^,]*}} %var) + // CHECK64-NEXT: %call = call %class.Test2* @"??0Test2@@QEAA@XZ"(%class.Test2* {{[^,]*}} %var) Test2 var; // CHECK32-NEXT: call x86_thiscallcc void @_ZN5Test2C1Ev(%class.Test2* {{[^,]*}} %var) - // CHECK64-NEXT: %call1 = call noundef %class.Test2* @"??0Test2@@QEAA@XZ"(%class.Test2* {{[^,]*}} %var) + // CHECK64-NEXT: %call1 = call %class.Test2* @"??0Test2@@QEAA@XZ"(%class.Test2* {{[^,]*}} %var) var.Test2::Test2(); // CHECK32: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i32 8, i1 false) @@ -51,18 +51,18 @@ public: void f3() { // CHECK32: call x86_thiscallcc void @_ZN5Test3C1Ev(%class.Test3* {{[^,]*}} %var) - // CHECK64: %call = call noundef %class.Test3* @"??0Test3@@QEAA@XZ"(%class.Test3* {{[^,]*}} %var) + // CHECK64: %call = call %class.Test3* @"??0Test3@@QEAA@XZ"(%class.Test3* {{[^,]*}} %var) Test3 var; // CHECK32-NEXT: call x86_thiscallcc void @_ZN5Test3C1Ev(%class.Test3* {{[^,]*}} %var2) - // CHECK64-NEXT: %call1 = call noundef %class.Test3* @"??0Test3@@QEAA@XZ"(%class.Test3* {{[^,]*}} %var2) + // CHECK64-NEXT: %call1 = call %class.Test3* @"??0Test3@@QEAA@XZ"(%class.Test3* {{[^,]*}} %var2) Test3 var2; // CHECK32-NEXT: call x86_thiscallcc void @_ZN5Test3C1Ev(%class.Test3* {{[^,]*}} %var) - // CHECK64-NEXT: %call2 = call noundef %class.Test3* @"??0Test3@@QEAA@XZ"(%class.Test3* {{[^,]*}} %var) + // CHECK64-NEXT: %call2 = call %class.Test3* @"??0Test3@@QEAA@XZ"(%class.Test3* {{[^,]*}} %var) var.Test3::Test3(); - // CHECK32-NEXT: call x86_thiscallcc void @_ZN5Test3C1ERKS_(%class.Test3* {{[^,]*}} %var, %class.Test3* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %var2) - // CHECK64-NEXT: %call3 = call noundef %class.Test3* @"??0Test3@@QEAA@AEBV0@@Z"(%class.Test3* {{[^,]*}} %var, %class.Test3* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %var2) + // CHECK32-NEXT: call x86_thiscallcc void @_ZN5Test3C1ERKS_(%class.Test3* {{[^,]*}} %var, %class.Test3* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %var2) + // CHECK64-NEXT: %call3 = call %class.Test3* @"??0Test3@@QEAA@AEBV0@@Z"(%class.Test3* {{[^,]*}} %var, %class.Test3* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %var2) var.Test3::Test3(var2); } diff --git a/clang/test/CodeGenCXX/constructor-init.cpp b/clang/test/CodeGenCXX/constructor-init.cpp index 9692a67338bfe7231e60162c9b0827415c6c5dec..f34f851094f7db6b2f42f705c5b71cb9b5ce3b87 100644 --- a/clang/test/CodeGenCXX/constructor-init.cpp +++ b/clang/test/CodeGenCXX/constructor-init.cpp @@ -99,16 +99,16 @@ namespace InitVTable { // CHECK: [[VTBL:%.*]] = load i32 ([[B]]*)**, i32 ([[B]]*)*** {{%.*}} // CHECK-NEXT: [[FNP:%.*]] = getelementptr inbounds i32 ([[B]]*)*, i32 ([[B]]*)** [[VTBL]], i64 0 // CHECK-NEXT: [[FN:%.*]] = load i32 ([[B]]*)*, i32 ([[B]]*)** [[FNP]] - // CHECK-NEXT: [[ARG:%.*]] = call noundef i32 [[FN]]([[B]]* {{[^,]*}} [[THIS]]) - // CHECK-NEXT: call void @_ZN10InitVTable1AC2Ei({{.*}}* {{[^,]*}} {{%.*}}, i32 noundef [[ARG]]) + // CHECK-NEXT: [[ARG:%.*]] = call i32 [[FN]]([[B]]* {{[^,]*}} [[THIS]]) + // CHECK-NEXT: call void @_ZN10InitVTable1AC2Ei({{.*}}* {{[^,]*}} {{%.*}}, i32 [[ARG]]) // CHECK-NEXT: [[T0:%.*]] = bitcast [[B]]* [[THIS]] to i32 (...)*** // CHECK-NEXT: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [3 x i8*] }, { [3 x i8*] }* @_ZTVN10InitVTable1BE, i32 0, inrange i32 0, i32 2) to i32 (...)**), i32 (...)*** [[T0]] // CHECK-NEXT: ret void B::B() : A(foo()) {} - // CHECK-LABEL: define{{.*}} void @_ZN10InitVTable1BC2Ei(%"struct.InitVTable::B"* {{[^,]*}} %this, i32 noundef %x) unnamed_addr + // CHECK-LABEL: define{{.*}} void @_ZN10InitVTable1BC2Ei(%"struct.InitVTable::B"* {{[^,]*}} %this, i32 %x) unnamed_addr // CHECK: [[ARG:%.*]] = add nsw i32 {{%.*}}, 5 - // CHECK-NEXT: call void @_ZN10InitVTable1AC2Ei({{.*}}* {{[^,]*}} {{%.*}}, i32 noundef [[ARG]]) + // CHECK-NEXT: call void @_ZN10InitVTable1AC2Ei({{.*}}* {{[^,]*}} {{%.*}}, i32 [[ARG]]) // CHECK-NEXT: [[T0:%.*]] = bitcast [[B]]* {{%.*}} to i32 (...)*** // CHECK-NEXT: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [3 x i8*] }, { [3 x i8*] }* @_ZTVN10InitVTable1BE, i32 0, inrange i32 0, i32 2) to i32 (...)**), i32 (...)*** [[T0]] // CHECK-NEXT: ret void @@ -163,7 +163,7 @@ template struct X; // Make sure that the instantiated constructor initializes start and // end properly. -// CHECK-LABEL: define linkonce_odr void @_ZN1XIiEC2ERKS0_(%struct.X* {{[^,]*}} %this, %struct.X* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %other) unnamed_addr +// CHECK-LABEL: define linkonce_odr void @_ZN1XIiEC2ERKS0_(%struct.X* {{[^,]*}} %this, %struct.X* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %other) unnamed_addr // CHECK: {{store.*null}} // CHECK: {{store.*null}} // CHECK: ret diff --git a/clang/test/CodeGenCXX/constructors.cpp b/clang/test/CodeGenCXX/constructors.cpp index ac923ab8c51dcdd0c18aad312d52c2f3e67e20e1..1bf150c5cf439f5a1093c6b85df1be2d26736f12 100644 --- a/clang/test/CodeGenCXX/constructors.cpp +++ b/clang/test/CodeGenCXX/constructors.cpp @@ -22,12 +22,12 @@ struct A { A::A(struct Undeclared &ref) : mem(0) {} // Check that delegation works. -// NULL-INVALID-LABEL: define{{.*}} void @_ZN1AC2ER10Undeclared(%struct.A* {{[^,]*}} %this, %struct.Undeclared* noundef nonnull align 1 %ref) unnamed_addr -// NULL-VALID-LABEL: define{{.*}} void @_ZN1AC2ER10Undeclared(%struct.A* {{[^,]*}} %this, %struct.Undeclared* noundef align 1 %ref) unnamed_addr +// NULL-INVALID-LABEL: define{{.*}} void @_ZN1AC2ER10Undeclared(%struct.A* {{[^,]*}} %this, %struct.Undeclared* nonnull align 1 %ref) unnamed_addr +// NULL-VALID-LABEL: define{{.*}} void @_ZN1AC2ER10Undeclared(%struct.A* {{[^,]*}} %this, %struct.Undeclared* align 1 %ref) unnamed_addr // CHECK: call void @_ZN6MemberC1Ei( -// NULL-INVALID-LABEL: define{{.*}} void @_ZN1AC1ER10Undeclared(%struct.A* {{[^,]*}} %this, %struct.Undeclared* noundef nonnull align 1 %ref) unnamed_addr -// NULL-VALID-LABEL: define{{.*}} void @_ZN1AC1ER10Undeclared(%struct.A* {{[^,]*}} %this, %struct.Undeclared* noundef align 1 %ref) unnamed_addr +// NULL-INVALID-LABEL: define{{.*}} void @_ZN1AC1ER10Undeclared(%struct.A* {{[^,]*}} %this, %struct.Undeclared* nonnull align 1 %ref) unnamed_addr +// NULL-VALID-LABEL: define{{.*}} void @_ZN1AC1ER10Undeclared(%struct.A* {{[^,]*}} %this, %struct.Undeclared* align 1 %ref) unnamed_addr // CHECK: call void @_ZN1AC2ER10Undeclared( A::A(ValueClass v) : mem(v.y - v.x) {} @@ -46,13 +46,13 @@ struct B : A { B::B(struct Undeclared &ref) : A(ref), mem(1) {} -// NULL-INVALID-LABEL: define{{.*}} void @_ZN1BC2ER10Undeclared(%struct.B* {{[^,]*}} %this, %struct.Undeclared* noundef nonnull align 1 %ref) unnamed_addr -// NULL-VALID-LABEL: define{{.*}} void @_ZN1BC2ER10Undeclared(%struct.B* {{[^,]*}} %this, %struct.Undeclared* noundef align 1 %ref) unnamed_addr +// NULL-INVALID-LABEL: define{{.*}} void @_ZN1BC2ER10Undeclared(%struct.B* {{[^,]*}} %this, %struct.Undeclared* nonnull align 1 %ref) unnamed_addr +// NULL-VALID-LABEL: define{{.*}} void @_ZN1BC2ER10Undeclared(%struct.B* {{[^,]*}} %this, %struct.Undeclared* align 1 %ref) unnamed_addr // CHECK: call void @_ZN1AC2ER10Undeclared( // CHECK: call void @_ZN6MemberC1Ei( -// NULL-INVALID-LABEL: define{{.*}} void @_ZN1BC1ER10Undeclared(%struct.B* {{[^,]*}} %this, %struct.Undeclared* noundef nonnull align 1 %ref) unnamed_addr -// NULL-VALID-LABEL: define{{.*}} void @_ZN1BC1ER10Undeclared(%struct.B* {{[^,]*}} %this, %struct.Undeclared* noundef align 1 %ref) unnamed_addr +// NULL-INVALID-LABEL: define{{.*}} void @_ZN1BC1ER10Undeclared(%struct.B* {{[^,]*}} %this, %struct.Undeclared* nonnull align 1 %ref) unnamed_addr +// NULL-VALID-LABEL: define{{.*}} void @_ZN1BC1ER10Undeclared(%struct.B* {{[^,]*}} %this, %struct.Undeclared* align 1 %ref) unnamed_addr // CHECK: call void @_ZN1BC2ER10Undeclared( @@ -67,10 +67,10 @@ struct C : virtual A { }; C::C(int x) : A(ValueClass(x, x+1)), mem(x * x) {} -// CHECK-LABEL: define{{.*}} void @_ZN1CC2Ei(%struct.C* {{[^,]*}} %this, i8** noundef %vtt, i32 noundef %x) unnamed_addr +// CHECK-LABEL: define{{.*}} void @_ZN1CC2Ei(%struct.C* {{[^,]*}} %this, i8** %vtt, i32 %x) unnamed_addr // CHECK: call void @_ZN6MemberC1Ei( -// CHECK-LABEL: define{{.*}} void @_ZN1CC1Ei(%struct.C* {{[^,]*}} %this, i32 noundef %x) unnamed_addr +// CHECK-LABEL: define{{.*}} void @_ZN1CC1Ei(%struct.C* {{[^,]*}} %this, i32 %x) unnamed_addr // CHECK: call void @_ZN10ValueClassC1Eii( // CHECK: call void @_ZN1AC2E10ValueClass( // CHECK: call void @_ZN6MemberC1Ei( @@ -85,12 +85,12 @@ struct D : A { D::D(int x, ...) : A(ValueClass(x, x+1)), mem(x*x) {} -// CHECK-LABEL: define{{.*}} void @_ZN1DC2Eiz(%struct.D* {{[^,]*}} %this, i32 noundef %x, ...) unnamed_addr +// CHECK-LABEL: define{{.*}} void @_ZN1DC2Eiz(%struct.D* {{[^,]*}} %this, i32 %x, ...) unnamed_addr // CHECK: call void @_ZN10ValueClassC1Eii( // CHECK: call void @_ZN1AC2E10ValueClass( // CHECK: call void @_ZN6MemberC1Ei( -// CHECK-LABEL: define{{.*}} void @_ZN1DC1Eiz(%struct.D* {{[^,]*}} %this, i32 noundef %x, ...) unnamed_addr +// CHECK-LABEL: define{{.*}} void @_ZN1DC1Eiz(%struct.D* {{[^,]*}} %this, i32 %x, ...) unnamed_addr // CHECK: call void @_ZN10ValueClassC1Eii( // CHECK: call void @_ZN1AC2E10ValueClass( // CHECK: call void @_ZN6MemberC1Ei( diff --git a/clang/test/CodeGenCXX/convert-to-fptr.cpp b/clang/test/CodeGenCXX/convert-to-fptr.cpp index 08150f45f7852eef59ecdcb9ea0a9121bb50d0eb..c8830107c2cc8bd0811a4ac99a520302130ec875 100644 --- a/clang/test/CodeGenCXX/convert-to-fptr.cpp +++ b/clang/test/CodeGenCXX/convert-to-fptr.cpp @@ -38,5 +38,5 @@ int main() return 0; } -// CHECK: call noundef i32 (i32)* @_ZN1AcvPFiiEEv -// CHECK: call noundef nonnull i32 (i32)* @_ZN1BcvRFiiEEv +// CHECK: call i32 (i32)* @_ZN1AcvPFiiEEv +// CHECK: call nonnull i32 (i32)* @_ZN1BcvRFiiEEv diff --git a/clang/test/CodeGenCXX/copy-assign-synthesis-1.cpp b/clang/test/CodeGenCXX/copy-assign-synthesis-1.cpp index be1421029a0a938ce0f9bf57b61f0162b8ff6c15..76887fc5496be6c9d49d5e6e686a12ed6b31f663 100644 --- a/clang/test/CodeGenCXX/copy-assign-synthesis-1.cpp +++ b/clang/test/CodeGenCXX/copy-assign-synthesis-1.cpp @@ -92,4 +92,4 @@ int main() { dstY.pr(); } -// CHECK: define linkonce_odr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.X* @_ZN1XaSERKS_ +// CHECK: define linkonce_odr nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.X* @_ZN1XaSERKS_ diff --git a/clang/test/CodeGenCXX/copy-constructor-elim-2.cpp b/clang/test/CodeGenCXX/copy-constructor-elim-2.cpp index 37feae0ae4b727d25be015dfe6a0ad1d67164997..14fa1c85226320ed216876b9df10717f0ae9e137 100644 --- a/clang/test/CodeGenCXX/copy-constructor-elim-2.cpp +++ b/clang/test/CodeGenCXX/copy-constructor-elim-2.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple armv7-none-eabi -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple armv7-none-eabi -emit-llvm -o - %s | FileCheck %s struct A { int x; A(int); ~A(); }; A f() { return A(0); } diff --git a/clang/test/CodeGenCXX/copy-constructor-synthesis-2.cpp b/clang/test/CodeGenCXX/copy-constructor-synthesis-2.cpp index d44eae570948b03708cb9677711255382c14840e..dd962c64b30e7ed61505a8589511641851c4190a 100644 --- a/clang/test/CodeGenCXX/copy-constructor-synthesis-2.cpp +++ b/clang/test/CodeGenCXX/copy-constructor-synthesis-2.cpp @@ -23,5 +23,5 @@ void pr23373_g(PR23373 &a, PR23373 &b) { a = b; } struct A { virtual void a(); }; A x(A& y) { return y; } -// CHECK: define linkonce_odr {{.*}} @_ZN1AC1ERKS_(%struct.A* {{.*}}%this, %struct.A* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr +// CHECK: define linkonce_odr {{.*}} @_ZN1AC1ERKS_(%struct.A* {{.*}}%this, %struct.A* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr // CHECK: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [3 x i8*] }, { [3 x i8*] }* @_ZTV1A, i32 0, inrange i32 0, i32 2) to i32 (...)**) diff --git a/clang/test/CodeGenCXX/copy-constructor-synthesis.cpp b/clang/test/CodeGenCXX/copy-constructor-synthesis.cpp index 9b441943917d742e7b2699dd8d03cbda2cb4af30..9a9e825aabbe5dc87e9f40dac0d1237de27164e2 100644 --- a/clang/test/CodeGenCXX/copy-constructor-synthesis.cpp +++ b/clang/test/CodeGenCXX/copy-constructor-synthesis.cpp @@ -21,7 +21,7 @@ struct P { }; -// CHECK-LABEL: define linkonce_odr void @_ZN1XC1ERKS_(%struct.X* {{[^,]*}} %this, %struct.X* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr +// CHECK-LABEL: define linkonce_odr void @_ZN1XC1ERKS_(%struct.X* {{[^,]*}} %this, %struct.X* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr struct X : M, N, P { // ... X() : f1(1.0), d1(2.0), i1(3), name("HELLO"), bf1(0xff), bf2(0xabcd), au_i1(1234), au1_4("MASKED") {} @@ -136,7 +136,7 @@ void f(B b1) { B b2 = b1; } -// CHECK: define linkonce_odr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[A:%.*]]* @_ZN12rdar138169401AaSERKS0_( +// CHECK: define linkonce_odr nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[A:%.*]]* @_ZN12rdar138169401AaSERKS0_( // CHECK: [[THIS:%.*]] = load [[A]]*, [[A]]** // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[A]], [[A]]* [[THIS]], i32 0, i32 1 // CHECK-NEXT: [[OTHER:%.*]] = load [[A]]*, [[A]]** @@ -146,7 +146,7 @@ void f(B b1) { // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[T4]], i8* align 8 [[T5]], i64 8, i1 false) // CHECK-NEXT: ret [[A]]* [[THIS]] -// CHECK-LABEL: define linkonce_odr void @_ZN6PR66281BC2ERKS0_(%"struct.PR6628::B"* {{[^,]*}} %this, %"struct.PR6628::B"* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr +// CHECK-LABEL: define linkonce_odr void @_ZN6PR66281BC2ERKS0_(%"struct.PR6628::B"* {{[^,]*}} %this, %"struct.PR6628::B"* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr // CHECK: call void @_ZN6PR66281TC1Ev // CHECK: call void @_ZN6PR66281TC1Ev // CHECK: call void @_ZN6PR66281AC2ERKS0_RKNS_1TES5_ diff --git a/clang/test/CodeGenCXX/copy-elision.cpp b/clang/test/CodeGenCXX/copy-elision.cpp index 9250f50e16079303833af2fa6b2ee3388a13cc90..72b2a5e00264c97ce1ed44d1cc05ab10cc2938af 100644 --- a/clang/test/CodeGenCXX/copy-elision.cpp +++ b/clang/test/CodeGenCXX/copy-elision.cpp @@ -14,7 +14,7 @@ struct A { // FIXME: There should be copy elision here. // CHECK-LABEL: define{{.*}} void @_Z4testI1AET_v // CHECK: call void @_ZN1AC1Ev -// CHECK-NEXT: call noundef i32 @_ZN1AcviEv +// CHECK-NEXT: call i32 @_ZN1AcviEv // CHECK-NEXT: call void @_ZN1AC1Ei // CHECK-NEXT: call void @llvm.lifetime.end template A test(); diff --git a/clang/test/CodeGenCXX/copy-initialization.cpp b/clang/test/CodeGenCXX/copy-initialization.cpp index 2dcc44c9a2e5cac7f9800819b4c1380ce1ba3f4f..6840e1b03088e698388be32e37af88ac1e3e0275 100644 --- a/clang/test/CodeGenCXX/copy-initialization.cpp +++ b/clang/test/CodeGenCXX/copy-initialization.cpp @@ -12,7 +12,7 @@ struct Bar { void f(Foo); -// CHECK-LABEL: define{{.*}} void @_Z1g3Foo(%struct.Foo* noundef %foo) +// CHECK-LABEL: define{{.*}} void @_Z1g3Foo(%struct.Foo* %foo) void g(Foo foo) { // CHECK: call void @_ZN3BarC1Ev // CHECK: @_ZNK3BarcvRK3FooEv diff --git a/clang/test/CodeGenCXX/cxx-abi-switch.cpp b/clang/test/CodeGenCXX/cxx-abi-switch.cpp index 552501c7b438c495b23f10b55403d78166144bf1..809be6c7bf3aba58d91cd3f7b694dd0d4295953c 100644 --- a/clang/test/CodeGenCXX/cxx-abi-switch.cpp +++ b/clang/test/CodeGenCXX/cxx-abi-switch.cpp @@ -22,7 +22,7 @@ public: B::B(int *i) : i_(i) {} B::~B() {} -// CHECK: define{{.*}} void @_ZN1BC2EPi(%class.B* {{[^,]*}} %this, i32* noundef %i) -// CHECK: define{{.*}} void @_ZN1BC1EPi(%class.B* {{[^,]*}} %this, i32* noundef %i) +// CHECK: define{{.*}} void @_ZN1BC2EPi(%class.B* {{[^,]*}} %this, i32* %i) +// CHECK: define{{.*}} void @_ZN1BC1EPi(%class.B* {{[^,]*}} %this, i32* %i) // CHECK: define{{.*}} void @_ZN1BD2Ev(%class.B* {{[^,]*}} %this) // CHECK: define{{.*}} void @_ZN1BD1Ev(%class.B* {{[^,]*}} %this) diff --git a/clang/test/CodeGenCXX/cxx0x-delegating-ctors.cpp b/clang/test/CodeGenCXX/cxx0x-delegating-ctors.cpp index 14823f3f6a6341c40d4bdd64c0220f870a51b96d..2ed3586cd656133b104583a65d30ac24c438b278 100644 --- a/clang/test/CodeGenCXX/cxx0x-delegating-ctors.cpp +++ b/clang/test/CodeGenCXX/cxx0x-delegating-ctors.cpp @@ -65,7 +65,7 @@ namespace PR12890 { }; X::X(int) : X() {} } -// CHECK: define {{.*}} @_ZN7PR128901XC1Ei(%"class.PR12890::X"* {{[^,]*}} %this, i32 noundef %0) +// CHECK: define {{.*}} @_ZN7PR128901XC1Ei(%"class.PR12890::X"* {{[^,]*}} %this, i32 %0) // CHECK: call void @llvm.memset.p0i8.{{i32|i64}}(i8* align 4 {{.*}}, i8 0, {{i32|i64}} 4, i1 false) namespace PR14588 { diff --git a/clang/test/CodeGenCXX/cxx0x-initializer-constructors.cpp b/clang/test/CodeGenCXX/cxx0x-initializer-constructors.cpp index 7f13366da1a8d38452e3e9e7f4a042906b194790..0265ed2d25e3ea853bb5b9554e5081a00ec2e74a 100644 --- a/clang/test/CodeGenCXX/cxx0x-initializer-constructors.cpp +++ b/clang/test/CodeGenCXX/cxx0x-initializer-constructors.cpp @@ -9,31 +9,31 @@ void fn1() { // CHECK-LABEL: define{{.*}} void @_Z3fn1v S s { 1 }; // CHECK: alloca %struct.S, align 1 - // CHECK: call void @_ZN1SC1Ei(%struct.S* {{[^,]*}} %s, i32 noundef 1) + // CHECK: call void @_ZN1SC1Ei(%struct.S* {{[^,]*}} %s, i32 1) } void fn2() { // CHECK-LABEL: define{{.*}} void @_Z3fn2v S s { 1, 2.0, 3.0 }; // CHECK: alloca %struct.S, align 1 - // CHECK: call void @_ZN1SC1Eidd(%struct.S* {{[^,]*}} %s, i32 noundef 1, double noundef 2.000000e+00, double noundef 3.000000e+00) + // CHECK: call void @_ZN1SC1Eidd(%struct.S* {{[^,]*}} %s, i32 1, double 2.000000e+00, double 3.000000e+00) } void fn3() { // CHECK-LABEL: define{{.*}} void @_Z3fn3v S sa[] { { 1 }, { 2 }, { 3 } }; // CHECK: alloca [3 x %struct.S], align 1 - // CHECK: call void @_ZN1SC1Ei(%struct.S* {{[^,]*}} %{{.+}}, i32 noundef 1) - // CHECK: call void @_ZN1SC1Ei(%struct.S* {{[^,]*}} %{{.+}}, i32 noundef 2) - // CHECK: call void @_ZN1SC1Ei(%struct.S* {{[^,]*}} %{{.+}}, i32 noundef 3) + // CHECK: call void @_ZN1SC1Ei(%struct.S* {{[^,]*}} %{{.+}}, i32 1) + // CHECK: call void @_ZN1SC1Ei(%struct.S* {{[^,]*}} %{{.+}}, i32 2) + // CHECK: call void @_ZN1SC1Ei(%struct.S* {{[^,]*}} %{{.+}}, i32 3) } void fn4() { // CHECK-LABEL: define{{.*}} void @_Z3fn4v S sa[] { { 1, 2.0, 3.0 }, { 4, 5.0, 6.0 } }; // CHECK: alloca [2 x %struct.S], align 1 - // CHECK: call void @_ZN1SC1Eidd(%struct.S* {{[^,]*}} %{{.+}}, i32 noundef 1, double noundef 2.000000e+00, double noundef 3.000000e+00) - // CHECK: call void @_ZN1SC1Eidd(%struct.S* {{[^,]*}} %{{.+}}, i32 noundef 4, double noundef 5.000000e+00, double noundef 6.000000e+00) + // CHECK: call void @_ZN1SC1Eidd(%struct.S* {{[^,]*}} %{{.+}}, i32 1, double 2.000000e+00, double 3.000000e+00) + // CHECK: call void @_ZN1SC1Eidd(%struct.S* {{[^,]*}} %{{.+}}, i32 4, double 5.000000e+00, double 6.000000e+00) } namespace TreeTransformBracedInit { diff --git a/clang/test/CodeGenCXX/cxx0x-initializer-references.cpp b/clang/test/CodeGenCXX/cxx0x-initializer-references.cpp index 11412560e39ec418a3d791358e6b301540710e93..846de5058e1f3bc519abf5d60680bdc247760b4f 100644 --- a/clang/test/CodeGenCXX/cxx0x-initializer-references.cpp +++ b/clang/test/CodeGenCXX/cxx0x-initializer-references.cpp @@ -81,10 +81,10 @@ namespace reference { { // Ensure lifetime extension. - // CHECK: call noundef %"struct.reference::B"* @_ZN9reference1BC1Ev + // CHECK: call %"struct.reference::B"* @_ZN9reference1BC1Ev // CHECK-NEXT: store %{{.*}}* %{{.*}}, %{{.*}}** % const B &rb{ B() }; - // CHECK: call noundef %"struct.reference::B"* @_ZN9reference1BD1Ev + // CHECK: call %"struct.reference::B"* @_ZN9reference1BD1Ev } } diff --git a/clang/test/CodeGenCXX/cxx11-initializer-aggregate.cpp b/clang/test/CodeGenCXX/cxx11-initializer-aggregate.cpp index e894aa7b2e597ded177ec4de0973fc0aa3b93fe7..4e858c54b769b6ff8d7f4479f9556466349aa09d 100644 --- a/clang/test/CodeGenCXX/cxx11-initializer-aggregate.cpp +++ b/clang/test/CodeGenCXX/cxx11-initializer-aggregate.cpp @@ -55,7 +55,7 @@ int fn1(int x) { // CHECK: store i32 %{{.*}}, i32* %[[A]], align 4 // CHECK: %[[B:.*]] = getelementptr inbounds %struct.A, %struct.A* %[[INITLIST]], i32 0, i32 1 // CHECK: store i32 5, i32* %[[B]], align 4 - // CHECK: call noundef i32 @_ZN1A1fEv(%struct.A* {{[^,]*}} %[[INITLIST]]) + // CHECK: call i32 @_ZN1A1fEv(%struct.A* {{[^,]*}} %[[INITLIST]]) return A{x, 5}.f(); } @@ -66,7 +66,7 @@ int &fn2(int &v) { // CHECK: %[[INITLIST2:.*]] = alloca %struct.B, align 8 // CHECK: %[[R:.*]] = getelementptr inbounds %struct.B, %struct.B* %[[INITLIST2:.*]], i32 0, i32 0 // CHECK: store i32* %{{.*}}, i32** %[[R]], align 8 - // CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_ZN1B1fEv(%struct.B* {{[^,]*}} %[[INITLIST2:.*]]) + // CHECK: call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_ZN1B1fEv(%struct.B* {{[^,]*}} %[[INITLIST2:.*]]) return B{v}.f(); } diff --git a/clang/test/CodeGenCXX/cxx11-initializer-array-new.cpp b/clang/test/CodeGenCXX/cxx11-initializer-array-new.cpp index 0ec7c1a78bfc5cfcc8d55dd682625e13e6730f63..51dc0729b23c35b987a6f5cb194a4b3ac48f1d7f 100644 --- a/clang/test/CodeGenCXX/cxx11-initializer-array-new.cpp +++ b/clang/test/CodeGenCXX/cxx11-initializer-array-new.cpp @@ -7,7 +7,7 @@ struct S { S(); S(int); ~S(); int n; }; void *p = new S[2][3]{ { 1, 2, 3 }, { 4, 5, 6 } }; // CHECK-LABEL: define -// CHECK: %[[ALLOC:.*]] = call noalias noundef nonnull i8* @_Znam(i64 noundef 32) +// CHECK: %[[ALLOC:.*]] = call noalias nonnull i8* @_Znam(i64 32) // CHECK: %[[COOKIE:.*]] = bitcast i8* %[[ALLOC]] to i64* // CHECK: store i64 6, i64* %[[COOKIE]] // CHECK: %[[START_AS_i8:.*]] = getelementptr inbounds i8, i8* %[[ALLOC]], i64 8 @@ -20,22 +20,22 @@ void *p = new S[2][3]{ { 1, 2, 3 }, { 4, 5, 6 } }; // CHECK: %[[S_0:.*]] = bitcast %[[S]]* %[[START_AS_S]] to [3 x %[[S]]]* // // CHECK: %[[S_0_0:.*]] = getelementptr inbounds [3 x %[[S]]], [3 x %[[S]]]* %[[S_0]], i64 0, i64 0 -// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_0_0]], i32 noundef 1) +// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_0_0]], i32 1) // CHECK: %[[S_0_1:.*]] = getelementptr inbounds %[[S]], %[[S]]* %[[S_0_0]], i64 1 -// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_0_1]], i32 noundef 2) +// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_0_1]], i32 2) // CHECK: %[[S_0_2:.*]] = getelementptr inbounds %[[S]], %[[S]]* %[[S_0_1]], i64 1 -// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_0_2]], i32 noundef 3) +// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_0_2]], i32 3) // // { 4, 5, 6 } // // CHECK: %[[S_1:.*]] = getelementptr inbounds [3 x %[[S]]], [3 x %[[S]]]* %[[S_0]], i64 1 // // CHECK: %[[S_1_0:.*]] = getelementptr inbounds [3 x %[[S]]], [3 x %[[S]]]* %[[S_1]], i64 0, i64 0 -// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_1_0]], i32 noundef 4) +// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_1_0]], i32 4) // CHECK: %[[S_1_1:.*]] = getelementptr inbounds %[[S]], %[[S]]* %[[S_1_0]], i64 1 -// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_1_1]], i32 noundef 5) +// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_1_1]], i32 5) // CHECK: %[[S_1_2:.*]] = getelementptr inbounds %[[S]], %[[S]]* %[[S_1_1]], i64 1 -// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_1_2]], i32 noundef 6) +// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_1_2]], i32 6) // // CHECK-NOT: br i1 // CHECK-NOT: call @@ -50,7 +50,7 @@ void *q = new S[n][3]{ { 1, 2, 3 }, { 4, 5, 6 } }; // CHECK: call {{.*}} @llvm.umul.with.overflow.i64(i64 %[[N:.*]], i64 12) // CHECK: %[[ELTS:.*]] = mul i64 %[[N]], 3 // CHECK: call {{.*}} @llvm.uadd.with.overflow.i64(i64 %{{.*}}, i64 8) -// CHECK: %[[ALLOC:.*]] = call noalias noundef nonnull i8* @_Znam(i64 noundef %{{.*}}) +// CHECK: %[[ALLOC:.*]] = call noalias nonnull i8* @_Znam(i64 %{{.*}}) // // CHECK: %[[COOKIE:.*]] = bitcast i8* %[[ALLOC]] to i64* // CHECK: store i64 %[[ELTS]], i64* %[[COOKIE]] @@ -64,22 +64,22 @@ void *q = new S[n][3]{ { 1, 2, 3 }, { 4, 5, 6 } }; // CHECK: %[[S_0:.*]] = bitcast %[[S]]* %[[START_AS_S]] to [3 x %[[S]]]* // // CHECK: %[[S_0_0:.*]] = getelementptr inbounds [3 x %[[S]]], [3 x %[[S]]]* %[[S_0]], i64 0, i64 0 -// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_0_0]], i32 noundef 1) +// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_0_0]], i32 1) // CHECK: %[[S_0_1:.*]] = getelementptr inbounds %[[S]], %[[S]]* %[[S_0_0]], i64 1 -// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_0_1]], i32 noundef 2) +// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_0_1]], i32 2) // CHECK: %[[S_0_2:.*]] = getelementptr inbounds %[[S]], %[[S]]* %[[S_0_1]], i64 1 -// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_0_2]], i32 noundef 3) +// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_0_2]], i32 3) // // { 4, 5, 6 } // // CHECK: %[[S_1:.*]] = getelementptr inbounds [3 x %[[S]]], [3 x %[[S]]]* %[[S_0]], i64 1 // // CHECK: %[[S_1_0:.*]] = getelementptr inbounds [3 x %[[S]]], [3 x %[[S]]]* %[[S_1]], i64 0, i64 0 -// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_1_0]], i32 noundef 4) +// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_1_0]], i32 4) // CHECK: %[[S_1_1:.*]] = getelementptr inbounds %[[S]], %[[S]]* %[[S_1_0]], i64 1 -// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_1_1]], i32 noundef 5) +// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_1_1]], i32 5) // CHECK: %[[S_1_2:.*]] = getelementptr inbounds %[[S]], %[[S]]* %[[S_1_1]], i64 1 -// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_1_2]], i32 noundef 6) +// CHECK: call void @_ZN1SC1Ei(%[[S]]* {{[^,]*}} %[[S_1_2]], i32 6) // // And the rest. // @@ -113,7 +113,7 @@ void *r = new T[n][3]{ { 1, 2, 3 }, { 4, 5, 6 } }; // No cookie. // CHECK-NOT: @llvm.uadd.with.overflow // -// CHECK: %[[ALLOC:.*]] = call noalias noundef nonnull i8* @_Znam(i64 noundef %{{.*}}) +// CHECK: %[[ALLOC:.*]] = call noalias nonnull i8* @_Znam(i64 %{{.*}}) // // CHECK: %[[START_AS_T:.*]] = bitcast i8* %[[ALLOC]] to %[[T:.*]]* // diff --git a/clang/test/CodeGenCXX/cxx11-thread-local-reference.cpp b/clang/test/CodeGenCXX/cxx11-thread-local-reference.cpp index af783716bdf0d18ea426f4e45b495f0f519c57ab..b1e0cdb0d91ffbd5e2bb8d63605d9a09d5059476 100644 --- a/clang/test/CodeGenCXX/cxx11-thread-local-reference.cpp +++ b/clang/test/CodeGenCXX/cxx11-thread-local-reference.cpp @@ -14,7 +14,7 @@ thread_local int &r = f(); int &g() { return r; } // CHECK: define {{.*}} @[[R_INIT:.*]]() -// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_Z1fv() +// CHECK: call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_Z1fv() // CHECK: store i32* %{{.*}}, i32** @r, align 8 // CHECK-LABEL: define{{.*}} nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_Z1gv() @@ -22,8 +22,8 @@ int &g() { return r; } // DARWIN: call cxx_fast_tlscc i32* @_ZTW1r() // CHECK: ret i32* %{{.*}} -// LINUX_AIX: define weak_odr hidden noundef i32* @_ZTW1r() [[ATTR0:#[0-9]+]]{{( comdat)?}} { -// DARWIN: define cxx_fast_tlscc noundef i32* @_ZTW1r() [[ATTR1:#[0-9]+]] { +// LINUX_AIX: define weak_odr hidden i32* @_ZTW1r() [[ATTR0:#[0-9]+]]{{( comdat)?}} { +// DARWIN: define cxx_fast_tlscc i32* @_ZTW1r() [[ATTR1:#[0-9]+]] { // LINUX_AIX: call void @_ZTH1r() // DARWIN: call cxx_fast_tlscc void @_ZTH1r() // CHECK: load i32*, i32** @r, align 8 diff --git a/clang/test/CodeGenCXX/cxx11-thread-local-visibility.cpp b/clang/test/CodeGenCXX/cxx11-thread-local-visibility.cpp index d6e0cc87489ad4345c6dcea4d42c80adfe01b86e..992a25dadc31b01642e7eee512205e533b596970 100644 --- a/clang/test/CodeGenCXX/cxx11-thread-local-visibility.cpp +++ b/clang/test/CodeGenCXX/cxx11-thread-local-visibility.cpp @@ -6,13 +6,13 @@ // LINUX_AIX: @default_tls ={{.*}} thread_local global i32 // LINUX_AIX: @hidden_tls ={{( hidden)?}} thread_local global i32 -// LINUX_AIX: define weak_odr hidden noundef i32* @_ZTW11default_tls() -// LINUX_AIX: define weak_odr hidden noundef i32* @_ZTW10hidden_tls() +// LINUX_AIX: define weak_odr hidden i32* @_ZTW11default_tls() +// LINUX_AIX: define weak_odr hidden i32* @_ZTW10hidden_tls() // // DARWIN: @default_tls = internal thread_local global i32 // DARWIN: @hidden_tls = internal thread_local global i32 -// DARWIN: define cxx_fast_tlscc noundef i32* @_ZTW11default_tls() -// DARWIN: define hidden cxx_fast_tlscc noundef i32* @_ZTW10hidden_tls() +// DARWIN: define cxx_fast_tlscc i32* @_ZTW11default_tls() +// DARWIN: define hidden cxx_fast_tlscc i32* @_ZTW10hidden_tls() __attribute__((visibility("default"))) thread_local int default_tls; __attribute__((visibility("hidden"))) thread_local int hidden_tls; diff --git a/clang/test/CodeGenCXX/cxx11-thread-local.cpp b/clang/test/CodeGenCXX/cxx11-thread-local.cpp index 8183929d3b0c663629c65b0dc49fd0005ed0bd5e..e63762ee7bfa015c8f5c57f2714a6fa46d19d24b 100644 --- a/clang/test/CodeGenCXX/cxx11-thread-local.cpp +++ b/clang/test/CodeGenCXX/cxx11-thread-local.cpp @@ -132,7 +132,7 @@ int f() { // CHECK-NEXT: load i32, i32* %{{.*}}, align 4 // CHECK-NEXT: store i32 %{{.*}}, i32* @c, align 4 -// LINUX_AIX-LABEL: define linkonce_odr hidden noundef i32* @_ZTW1b() +// LINUX_AIX-LABEL: define linkonce_odr hidden i32* @_ZTW1b() // LINUX: br i1 icmp ne (void ()* @_ZTH1b, void ()* null), // AIX-NOT: br i1 icmp ne (void ()* @_ZTH1b, void ()* null), // not null: @@ -141,7 +141,7 @@ int f() { // AIX-NOT: br label // finally: // LINUX_AIX: ret i32* @b -// DARWIN-LABEL: declare cxx_fast_tlscc noundef i32* @_ZTW1b() +// DARWIN-LABEL: declare cxx_fast_tlscc i32* @_ZTW1b() // There is no definition of the thread wrapper on Darwin for external TLV. // CHECK: define {{.*}} @[[D_INIT:.*]]() @@ -160,14 +160,14 @@ int f() { // DARWIN: call cxx_fast_tlscc {{.*}}* @_ZTWN1XIiE1mE() // CHECK: store {{.*}} @e -// LINUX_AIX-LABEL: define weak_odr hidden noundef i32* @_ZTWN1VIiE1mE() -// DARWIN-LABEL: define weak_odr hidden cxx_fast_tlscc noundef i32* @_ZTWN1VIiE1mE() +// LINUX_AIX-LABEL: define weak_odr hidden i32* @_ZTWN1VIiE1mE() +// DARWIN-LABEL: define weak_odr hidden cxx_fast_tlscc i32* @_ZTWN1VIiE1mE() // LINUX_AIX: call void @_ZTHN1VIiE1mE() // DARWIN: call cxx_fast_tlscc void @_ZTHN1VIiE1mE() // CHECK: ret i32* @_ZN1VIiE1mE -// LINUX_AIX-LABEL: define weak_odr hidden noundef i32* @_ZTWN1WIiE1mE() -// DARWIN-LABEL: define weak_odr hidden cxx_fast_tlscc noundef i32* @_ZTWN1WIiE1mE() +// LINUX_AIX-LABEL: define weak_odr hidden i32* @_ZTWN1WIiE1mE() +// DARWIN-LABEL: define weak_odr hidden cxx_fast_tlscc i32* @_ZTWN1WIiE1mE() // CHECK-NOT: call // CHECK: ret i32* @_ZN1WIiE1mE @@ -207,15 +207,15 @@ int f() { // AIX: declare i32 @__pt_atexit_np(i32, i32 (i32, ...)*, ...) // DARWIN: declare i32 @_tlv_atexit(void (i8*)*, i8*, i8*) -// DARWIN: declare cxx_fast_tlscc noundef i32* @_ZTWN1VIcE1mE() -// LINUX_AIX: define linkonce_odr hidden noundef i32* @_ZTWN1VIcE1mE() {{#[0-9]+}}{{( comdat)?}} { +// DARWIN: declare cxx_fast_tlscc i32* @_ZTWN1VIcE1mE() +// LINUX_AIX: define linkonce_odr hidden i32* @_ZTWN1VIcE1mE() {{#[0-9]+}}{{( comdat)?}} { // LINUX: br i1 icmp ne (void ()* @_ZTHN1VIcE1mE, // AIX-NOT: br i1 icmp ne (void ()* @_ZTHN1VIcE1mE // LINUX_AIX: call void @_ZTHN1VIcE1mE() // LINUX_AIX: ret i32* @_ZN1VIcE1mE -// DARWIN: declare cxx_fast_tlscc noundef i32* @_ZTWN1WIcE1mE() -// LINUX_AIX: define linkonce_odr hidden noundef i32* @_ZTWN1WIcE1mE() {{#[0-9]+}}{{( comdat)?}} { +// DARWIN: declare cxx_fast_tlscc i32* @_ZTWN1WIcE1mE() +// LINUX_AIX: define linkonce_odr hidden i32* @_ZTWN1WIcE1mE() {{#[0-9]+}}{{( comdat)?}} { // LINUX: br i1 icmp ne (void ()* @_ZTHN1WIcE1mE, // AIX-NOT: br i1 icmp ne (void ()* @_ZTHN1WIcE1mE, // LINUX_AIX: call void @_ZTHN1WIcE1mE() @@ -258,7 +258,7 @@ void tls_dtor() { static thread_local const S &u = S(); } -// AIX: define {{.*}}@__dtor__ZZ8tls_dtorvE1s(i32 noundef signext %0, ...){{.*}}{ +// AIX: define {{.*}}@__dtor__ZZ8tls_dtorvE1s(i32 signext %0, ...){{.*}}{ // AIX: entry: // AIX: %.addr = alloca i32, align 4 // AIX: store i32 %0, i32* %.addr, align 4 @@ -266,7 +266,7 @@ void tls_dtor() { // AIX: ret i32 0 // AIX: } -// AIX: define {{.*}}@__dtor__ZZ8tls_dtorvE1t(i32 noundef signext %0, ...){{.*}}{ +// AIX: define {{.*}}@__dtor__ZZ8tls_dtorvE1t(i32 signext %0, ...){{.*}}{ // AIX: entry: // AIX: %.addr = alloca i32, align 4 // AIX: store i32 %0, i32* %.addr, align 4 @@ -274,7 +274,7 @@ void tls_dtor() { // AIX: ret i32 0 // AIX: } -// AIX: define {{.*}}@__dtor__ZZ8tls_dtorvE1u(i32 noundef signext %0, ...){{.*}}{ +// AIX: define {{.*}}@__dtor__ZZ8tls_dtorvE1u(i32 signext %0, ...){{.*}}{ // AIX: entry: // AIX: %.addr = alloca i32, align 4 // AIX: store i32 %0, i32* %.addr, align 4 @@ -306,8 +306,8 @@ thread_local int anon_i{f()}; void set_anon_i() { anon_i = 2; } -// LINUX_AIX-LABEL: define internal noundef i32* @_ZTWN12_GLOBAL__N_16anon_iE() -// DARWIN-LABEL: define internal cxx_fast_tlscc noundef i32* @_ZTWN12_GLOBAL__N_16anon_iE() +// LINUX_AIX-LABEL: define internal i32* @_ZTWN12_GLOBAL__N_16anon_iE() +// DARWIN-LABEL: define internal cxx_fast_tlscc i32* @_ZTWN12_GLOBAL__N_16anon_iE() // LINUX_AIX: define internal void @[[V_M_INIT]]() // DARWIN: define internal cxx_fast_tlscc void @[[V_M_INIT]]() @@ -355,8 +355,8 @@ void set_anon_i() { // CHECK-NOT: call void @[[V_M_INIT]]() -// LINUX_AIX: define weak_odr hidden noundef i32* @_ZTW1a() -// DARWIN: define cxx_fast_tlscc noundef i32* @_ZTW1a() +// LINUX_AIX: define weak_odr hidden i32* @_ZTW1a() +// DARWIN: define cxx_fast_tlscc i32* @_ZTW1a() // LINUX_AIX: call void @_ZTH1a() // DARWIN: call cxx_fast_tlscc void @_ZTH1a() // CHECK: ret i32* @a @@ -368,8 +368,8 @@ void set_anon_i() { // thread-local variables in this TU. // CHECK-NOT: define {{.*}} @_ZTWL1d() -// LINUX_AIX-LABEL: define weak_odr hidden noundef i32* @_ZTWN1U1mE() -// DARWIN-LABEL: define cxx_fast_tlscc noundef i32* @_ZTWN1U1mE() +// LINUX_AIX-LABEL: define weak_odr hidden i32* @_ZTWN1U1mE() +// DARWIN-LABEL: define cxx_fast_tlscc i32* @_ZTWN1U1mE() // LINUX_AIX: call void @_ZTHN1U1mE() // DARWIN: call cxx_fast_tlscc void @_ZTHN1U1mE() // CHECK: ret i32* @_ZN1U1mE diff --git a/clang/test/CodeGenCXX/cxx11-user-defined-literal.cpp b/clang/test/CodeGenCXX/cxx11-user-defined-literal.cpp index df26f82caf30234df1814e2c3ba081f183e39294..c1eab634b1205590beb5af87f05132ce0cdb7e5d 100644 --- a/clang/test/CodeGenCXX/cxx11-user-defined-literal.cpp +++ b/clang/test/CodeGenCXX/cxx11-user-defined-literal.cpp @@ -16,11 +16,11 @@ template S operator"" _t() { return S(); } // CHECK: @[[s_0xffffeeee:.*]] = {{.*}} constant [11 x i8] c"0xffffeeee\00" void f() { - // CHECK: call void @_Zli2_xPKcm({{.*}}, i8* noundef getelementptr inbounds ([4 x i8], [4 x i8]* @[[s_foo]], i64 0, i64 0), i64 noundef 3) - // CHECK: call void @_Zli2_xPKcm({{.*}}, i8* noundef getelementptr inbounds ([4 x i8], [4 x i8]* @[[s_bar]], i64 0, i64 0), i64 noundef 3) + // CHECK: call void @_Zli2_xPKcm({{.*}}, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @[[s_foo]], i64 0, i64 0), i64 3) + // CHECK: call void @_Zli2_xPKcm({{.*}}, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @[[s_bar]], i64 0, i64 0), i64 3) // CHECK: call void @_Zli2_yw({{.*}} 97) // CHECK: call void @_Zli2_zy({{.*}} 42) - // CHECK: call void @_Zli2_fe({{.*}} x86_fp80 noundef 0xK3FFF8000000000000000) + // CHECK: call void @_Zli2_fe({{.*}} x86_fp80 0xK3FFF8000000000000000) // CHECK: call void @_ZN1SD1Ev({{.*}}) // CHECK: call void @_ZN1SD1Ev({{.*}}) // CHECK: call void @_ZN1SD1Ev({{.*}}) @@ -28,9 +28,9 @@ void f() { // CHECK: call void @_ZN1SD1Ev({{.*}}) "foo"_x, "bar"_x, L'a'_y, 42_z, 1.0_f; - // CHECK: call void @_Zli2_rPKc({{.*}}, i8* noundef getelementptr inbounds ([4 x i8], [4 x i8]* @[[s_123]], i64 0, i64 0)) - // CHECK: call void @_Zli2_rPKc({{.*}}, i8* noundef getelementptr inbounds ([4 x i8], [4 x i8]* @[[s_4_9]], i64 0, i64 0)) - // CHECK: call void @_Zli2_rPKc({{.*}}, i8* noundef getelementptr inbounds ([11 x i8], [11 x i8]* @[[s_0xffffeeee]], i64 0, i64 0)) + // CHECK: call void @_Zli2_rPKc({{.*}}, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @[[s_123]], i64 0, i64 0)) + // CHECK: call void @_Zli2_rPKc({{.*}}, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @[[s_4_9]], i64 0, i64 0)) + // CHECK: call void @_Zli2_rPKc({{.*}}, i8* getelementptr inbounds ([11 x i8], [11 x i8]* @[[s_0xffffeeee]], i64 0, i64 0)) // CHECK: call void @_ZN1SD1Ev({{.*}}) // CHECK: call void @_ZN1SD1Ev({{.*}}) // CHECK: call void @_ZN1SD1Ev({{.*}}) @@ -55,15 +55,15 @@ void h() { } // CHECK: define {{.*}} @_Z1hv() -// CHECK: call void @_Z1gIiEDTclclL_Zli2_xPKcmELA4_S0_ELm3EEfp_EET_(i32 noundef 42) -// CHECK: call void @_Z1iIiEDTclclL_Zli2_xPKcmELA4_S0_ELi3EEfp_EET_(i32 noundef 42) +// CHECK: call void @_Z1gIiEDTclclL_Zli2_xPKcmELA4_S0_ELm3EEfp_EET_(i32 42) +// CHECK: call void @_Z1iIiEDTclclL_Zli2_xPKcmELA4_S0_ELi3EEfp_EET_(i32 42) // CHECK: define {{.*}} @_Z1gIiEDTclclL_Zli2_xPKcmELA4_S0_ELm3EEfp_EET_(i32 -// CHECK: call void @_Zli2_xPKcm({{.*}}, i8* noundef getelementptr inbounds ([4 x i8], [4 x i8]* @{{.*}}, i64 0, i64 0), i64 noundef 3) +// CHECK: call void @_Zli2_xPKcm({{.*}}, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @{{.*}}, i64 0, i64 0), i64 3) // CHECK: call void @_ZN1SclEi // CHECK: call void @_ZN1SD1Ev // CHECK: define {{.*}} @_Z1iIiEDTclclL_Zli2_xPKcmELA4_S0_ELi3EEfp_EET_(i32 -// CHECK: call void @_Zli2_xPKcm({{.*}}, i8* noundef getelementptr inbounds ([4 x i8], [4 x i8]* @{{.*}}, i64 0, i64 0), i64 noundef 3) +// CHECK: call void @_Zli2_xPKcm({{.*}}, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @{{.*}}, i64 0, i64 0), i64 3) // CHECK: call void @_ZN1SclEi // CHECK: call void @_ZN1SD1Ev diff --git a/clang/test/CodeGenCXX/cxx1y-init-captures.cpp b/clang/test/CodeGenCXX/cxx1y-init-captures.cpp index 83d07103720a0035629ab93144823253337cc7a2..0a9fe4d3fdac8a4e8371746f96646b1bdc2a3872 100644 --- a/clang/test/CodeGenCXX/cxx1y-init-captures.cpp +++ b/clang/test/CodeGenCXX/cxx1y-init-captures.cpp @@ -28,9 +28,9 @@ void g() { // CHECK: store i32 1, i32* // CHECK: getelementptr inbounds {{.*}}, i32 0, i32 1 // CHECK: store i32 2, i32* -// CHECK: call noundef i32 @"_ZZ1gvENK3$_1clEv"( +// CHECK: call i32 @"_ZZ1gvENK3$_1clEv"( -// CHECK-LABEL: define internal noundef i32 @"_ZZ1gvENK3$_1clEv"( +// CHECK-LABEL: define internal i32 @"_ZZ1gvENK3$_1clEv"( // CHECK: getelementptr inbounds {{.*}}, i32 0, i32 0 // CHECK: load i32, i32* // CHECK: getelementptr inbounds {{.*}}, i32 0, i32 1 @@ -66,9 +66,9 @@ int h(int a) { // CHECK: load i32, i32* %[[A_ADDR]], // CHECK: store i32 // - // CHECK: call noundef i32 @"_ZZ1hiENK3$_2clEv"({{.*}}* {{[^,]*}} %[[OUTER]]) + // CHECK: call i32 @"_ZZ1hiENK3$_2clEv"({{.*}}* {{[^,]*}} %[[OUTER]]) return [&b(a), c(a)] { - // CHECK-LABEL: define internal noundef i32 @"_ZZ1hiENK3$_2clEv"( + // CHECK-LABEL: define internal i32 @"_ZZ1hiENK3$_2clEv"( // CHECK: %[[OUTER_ADDR:.*]] = alloca // CHECK: %[[INNER:.*]] = alloca // CHECK: store {{.*}}, {{.*}}** %[[OUTER_ADDR]], @@ -86,12 +86,12 @@ int h(int a) { // CHECK-NEXT: load i32, i32* % // CHECK-NEXT: store i32 // - // CHECK: call noundef i32 @"_ZZZ1hiENK3$_2clEvENKUlvE_clEv"({{.*}}* {{[^,]*}} %[[INNER]]) + // CHECK: call i32 @"_ZZZ1hiENK3$_2clEvENKUlvE_clEv"({{.*}}* {{[^,]*}} %[[INNER]]) return [=, &c] { // CHECK-LABEL: define internal void @"_ZZ1fvEN3$_0D2Ev"( // CHECK: call void @_ZN1SD1Ev( - // CHECK-LABEL: define internal noundef i32 @"_ZZZ1hiENK3$_2clEvENKUlvE_clEv"( + // CHECK-LABEL: define internal i32 @"_ZZZ1hiENK3$_2clEvENKUlvE_clEv"( // CHECK: %[[INNER_ADDR:.*]] = alloca // CHECK: store {{.*}}, {{.*}}** %[[INNER_ADDR]], // CHECK: %[[INNER:.*]] = load {{.*}}*, {{.*}}** %[[INNER_ADDR]] diff --git a/clang/test/CodeGenCXX/cxx1y-initializer-aggregate.cpp b/clang/test/CodeGenCXX/cxx1y-initializer-aggregate.cpp index f9941ebbe3d1891eec1c669661166be12c88268a..a3af8d2b19077cfbd8dabb1a05d14ada5a28b3ce 100644 --- a/clang/test/CodeGenCXX/cxx1y-initializer-aggregate.cpp +++ b/clang/test/CodeGenCXX/cxx1y-initializer-aggregate.cpp @@ -55,7 +55,7 @@ C n{}; // CHECK: load i32, i32* getelementptr inbounds ({{.*}} @a, i32 0, i32 0) // CHECK: getelementptr inbounds i8, i8* %{{.*}}, {{.*}} %{{.*}} // CHECK: store i8 %{{.*}}, i8* getelementptr inbounds ({{.*}} @a, i32 0, i32 2) -// CHECK: call noundef i32 @_ZN1A1fEv({{.*}} @a) +// CHECK: call i32 @_ZN1A1fEv({{.*}} @a) // CHECK: store i32 %{{.*}}, i32* getelementptr inbounds ({{.*}}, {{.*}}* @a, i32 0, i32 3) // CHECK: store double 1.000000e+00, double* getelementptr inbounds ({{.*}} @a, i32 0, i32 4, i32 0) @@ -69,12 +69,12 @@ C n{}; // CHECK: store i8* null, i8** getelementptr inbounds ({{.*}} @c, i32 0, i32 1) // CHECK-NOT: load // CHECK: store i8 65, i8* getelementptr inbounds ({{.*}} @c, i32 0, i32 2) -// CHECK: call noundef i32 @_Z1fv() +// CHECK: call i32 @_Z1fv() // CHECK: store i32 %{{.*}}, i32* getelementptr inbounds ({{.*}}, {{.*}}* @c, i32 0, i32 3) // CHECK-NOT: C1Ev // CHECK: store i8 3, i8* {{.*}} @c, i32 0, i32 4) // CHECK: call void @_ZN1BC1Ev({{.*}} @x) -// CHECK: call noundef i32 @_ZN1B1fEv({{.*}} @y) +// CHECK: call i32 @_ZN1B1fEv({{.*}} @y) // CHECK: store i32 %{{.*}}, i32* getelementptr inbounds ({{.*}} @y, i32 0, i32 0) diff --git a/clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp b/clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp index 0ba4cea9405bb5646ec59a6d941da5753792d57f..03aa93f32e0683e74307a96b16172cbcb0c2d5c6 100644 --- a/clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp +++ b/clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp @@ -50,65 +50,65 @@ template void del(); D::D() {} // CHECK-LABEL: define weak_odr void @_Z3delIiEvv() -// CHECK: call void @_ZdlPvm(i8* noundef %{{[^ ]*}}, i64 noundef 4) -// CHECK: call void @_ZdaPv(i8* noundef %{{[^ ]*}}) +// CHECK: call void @_ZdlPvm(i8* %{{[^ ]*}}, i64 4) +// CHECK: call void @_ZdaPv(i8* %{{[^ ]*}}) // -// CHECK: call void @_ZdlPvm(i8* noundef %{{[^ ]*}}, i64 noundef 4) -// CHECK: call void @_ZdaPv(i8* noundef %{{[^ ]*}}) +// CHECK: call void @_ZdlPvm(i8* %{{[^ ]*}}, i64 4) +// CHECK: call void @_ZdaPv(i8* %{{[^ ]*}}) // CHECK-LABEL: declare void @_ZdlPvm(i8* // CHECK-LABEL: define weak_odr void @_Z3delI1BEvv() -// CHECK: call void @_ZdlPvm(i8* noundef %{{[^ ]*}}, i64 noundef 4) -// CHECK: call void @_ZdaPv(i8* noundef %{{[^ ]*}}) +// CHECK: call void @_ZdlPvm(i8* %{{[^ ]*}}, i64 4) +// CHECK: call void @_ZdaPv(i8* %{{[^ ]*}}) // -// CHECK: call void @_ZdlPvm(i8* noundef %{{[^ ]*}}, i64 noundef 4) -// CHECK: call void @_ZdaPv(i8* noundef %{{[^ ]*}}) +// CHECK: call void @_ZdlPvm(i8* %{{[^ ]*}}, i64 4) +// CHECK: call void @_ZdaPv(i8* %{{[^ ]*}}) // CHECK-LABEL: define weak_odr void @_Z3delI1CEvv() -// CHECK: call void @_ZdlPvm(i8* noundef %{{[^ ]*}}, i64 noundef 1) +// CHECK: call void @_ZdlPvm(i8* %{{[^ ]*}}, i64 1) // CHECK: mul i64 1, %{{[^ ]*}} // CHECK: add i64 %{{[^ ]*}}, 8 -// CHECK: call void @_ZdaPvm(i8* noundef %{{[^ ]*}}, i64 noundef %{{[^ ]*}}) +// CHECK: call void @_ZdaPvm(i8* %{{[^ ]*}}, i64 %{{[^ ]*}}) // -// CHECK: call void @_ZdlPvm(i8* noundef %{{[^ ]*}}, i64 noundef 1) +// CHECK: call void @_ZdlPvm(i8* %{{[^ ]*}}, i64 1) // CHECK: mul i64 1, %{{[^ ]*}} // CHECK: add i64 %{{[^ ]*}}, 8 -// CHECK: call void @_ZdaPvm(i8* noundef %{{[^ ]*}}, i64 noundef %{{[^ ]*}}) +// CHECK: call void @_ZdaPvm(i8* %{{[^ ]*}}, i64 %{{[^ ]*}}) // CHECK-LABEL: declare void @_ZdaPvm(i8* // CHECK-LABEL: define weak_odr void @_Z3delI1DEvv() -// CHECK: call void @_ZdlPvm(i8* noundef %{{[^ ]*}}, i64 noundef 8) +// CHECK: call void @_ZdlPvm(i8* %{{[^ ]*}}, i64 8) // CHECK: mul i64 8, %{{[^ ]*}} // CHECK: add i64 %{{[^ ]*}}, 8 -// CHECK: call void @_ZdaPvm(i8* noundef %{{[^ ]*}}, i64 noundef %{{[^ ]*}}) +// CHECK: call void @_ZdaPvm(i8* %{{[^ ]*}}, i64 %{{[^ ]*}}) // // CHECK-NOT: Zdl // CHECK: call void %{{.*}} // CHECK-NOT: Zdl // CHECK: mul i64 8, %{{[^ ]*}} // CHECK: add i64 %{{[^ ]*}}, 8 -// CHECK: call void @_ZdaPvm(i8* noundef %{{[^ ]*}}, i64 noundef %{{[^ ]*}}) +// CHECK: call void @_ZdaPvm(i8* %{{[^ ]*}}, i64 %{{[^ ]*}}) // CHECK-LABEL: define weak_odr void @_Z3delI1EEvv() -// CHECK: call void @_ZdlPvm(i8* noundef %{{[^ ]*}}, i64 noundef 1) -// CHECK: call void @_ZdaPv(i8* noundef %{{[^ ]*}}) +// CHECK: call void @_ZdlPvm(i8* %{{[^ ]*}}, i64 1) +// CHECK: call void @_ZdaPv(i8* %{{[^ ]*}}) // -// CHECK: call void @_ZN1EdlEPv(i8* noundef %{{[^ ]*}}) -// CHECK: call void @_ZN1EdaEPv(i8* noundef %{{[^ ]*}}) +// CHECK: call void @_ZN1EdlEPv(i8* %{{[^ ]*}}) +// CHECK: call void @_ZN1EdaEPv(i8* %{{[^ ]*}}) // CHECK-LABEL: define weak_odr void @_Z3delI1FEvv() -// CHECK: call void @_ZdlPvm(i8* noundef %{{[^ ]*}}, i64 noundef 1) +// CHECK: call void @_ZdlPvm(i8* %{{[^ ]*}}, i64 1) // CHECK: mul i64 1, %{{[^ ]*}} // CHECK: add i64 %{{[^ ]*}}, 8 -// CHECK: call void @_ZdaPvm(i8* noundef %{{[^ ]*}}, i64 noundef %{{[^ ]*}}) +// CHECK: call void @_ZdaPvm(i8* %{{[^ ]*}}, i64 %{{[^ ]*}}) // -// CHECK: call void @_ZN1FdlEPvm(i8* noundef %{{[^ ]*}}, i64 noundef 1) +// CHECK: call void @_ZN1FdlEPvm(i8* %{{[^ ]*}}, i64 1) // CHECK: mul i64 1, %{{[^ ]*}} // CHECK: add i64 %{{[^ ]*}}, 8 -// CHECK: call void @_ZN1FdaEPvm(i8* noundef %{{[^ ]*}}, i64 noundef %{{[^ ]*}}) +// CHECK: call void @_ZN1FdaEPvm(i8* %{{[^ ]*}}, i64 %{{[^ ]*}}) // CHECK-LABEL: define linkonce_odr void @_ZN1DD0Ev(%{{[^ ]*}}* {{[^,]*}} %this) -// CHECK: call void @_ZdlPvm(i8* noundef %{{[^ ]*}}, i64 noundef 8) +// CHECK: call void @_ZdlPvm(i8* %{{[^ ]*}}, i64 8) diff --git a/clang/test/CodeGenCXX/cxx1y-variable-template-linkage.cpp b/clang/test/CodeGenCXX/cxx1y-variable-template-linkage.cpp index a05375006763a5e2a12a93e1877502380041910f..fc23d90a306e66dbc8febc6a3b856065684a171b 100644 --- a/clang/test/CodeGenCXX/cxx1y-variable-template-linkage.cpp +++ b/clang/test/CodeGenCXX/cxx1y-variable-template-linkage.cpp @@ -25,7 +25,7 @@ template T t = 42; int mode; -// CHECK-DAG: define internal noundef nonnull align 4 dereferenceable(4) i32* @_ZL3foov( +// CHECK-DAG: define internal nonnull align 4 dereferenceable(4) i32* @_ZL3foov( static const int &foo() { struct Foo { }; @@ -61,18 +61,18 @@ static const int &foo() { #if !__has_feature(cxx_exceptions) // File A // CHECKA-DAG: define{{.*}} nonnull align 4 dereferenceable(4) i32* @_Z3barv( const int &bar() { - // CHECKA-DAG: call noundef nonnull align 4 dereferenceable(4) i32* @_ZL3foov() + // CHECKA-DAG: call nonnull align 4 dereferenceable(4) i32* @_ZL3foov() return foo(); } #else // File B -// CHECKB-DAG: declare noundef nonnull align 4 dereferenceable(4) i32* @_Z3barv( +// CHECKB-DAG: declare nonnull align 4 dereferenceable(4) i32* @_Z3barv( const int &bar(); int main() { - // CHECKB-DAG: call noundef nonnull align 4 dereferenceable(4) i32* @_Z3barv() - // CHECKB-DAG: call noundef nonnull align 4 dereferenceable(4) i32* @_ZL3foov() + // CHECKB-DAG: call nonnull align 4 dereferenceable(4) i32* @_Z3barv() + // CHECKB-DAG: call nonnull align 4 dereferenceable(4) i32* @_ZL3foov() &bar() == &foo() ? throw 0 : (void)0; // Should not throw exception at runtime. } diff --git a/clang/test/CodeGenCXX/cxx1y-variable-template.cpp b/clang/test/CodeGenCXX/cxx1y-variable-template.cpp index 2c79b731c8b59b7d0787833bee0e211bc9fb6cc6..51d1b54b37a7fcb7d60753e3878daae16ae6194f 100644 --- a/clang/test/CodeGenCXX/cxx1y-variable-template.cpp +++ b/clang/test/CodeGenCXX/cxx1y-variable-template.cpp @@ -40,7 +40,7 @@ namespace PR42111 { // CHECK: load {{.*}} @_ZGVN7PR4211112_GLOBAL__N_11nILi0EEE // CHECK: icmp eq i8 {{.*}}, 0 // CHECK: br i1 - // CHECK: call noundef i32 @_ZN7PR421111fEv( + // CHECK: call i32 @_ZN7PR421111fEv( // CHECK: store i32 {{.*}}, i32* @_ZN7PR4211112_GLOBAL__N_11nILi0EEE // CHECK: store i8 1, i8* @_ZGVN7PR4211112_GLOBAL__N_11nILi0EEE int g() { return n<> + n<>; } diff --git a/clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp b/clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp index 44bc319a65be8ca9eb4470690f27e278477461a5..d2b5b64d644ca5d3b3ff4e418c870dffd0e116b8 100644 --- a/clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp +++ b/clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp @@ -27,38 +27,38 @@ namespace std { enum class align_val_t : size_t {}; } struct OVERALIGNED A { A(); int n[128]; }; // CHECK-LABEL: define {{.*}} @_Z2a0v() -// CHECK: %[[ALLOC:.*]] = call noalias noundef nonnull align 32 i8* @_ZnwmSt11align_val_t(i64 noundef 512, i64 noundef 32) -// CHECK: call void @_ZdlPvSt11align_val_t(i8* noundef %[[ALLOC]], i64 noundef 32) +// CHECK: %[[ALLOC:.*]] = call noalias nonnull align 32 i8* @_ZnwmSt11align_val_t(i64 512, i64 32) +// CHECK: call void @_ZdlPvSt11align_val_t(i8* %[[ALLOC]], i64 32) // CHECK-MS-LABEL: define {{.*}} @"?a0@@YAPEAXXZ"() -// CHECK-MS: %[[ALLOC:.*]] = call noalias noundef nonnull align 32 i8* @"??2@YAPEAX_KW4align_val_t@std@@@Z"(i64 noundef 512, i64 noundef 32) +// CHECK-MS: %[[ALLOC:.*]] = call noalias nonnull align 32 i8* @"??2@YAPEAX_KW4align_val_t@std@@@Z"(i64 512, i64 32) // CHECK-MS: cleanuppad -// CHECK-MS: call void @"??3@YAXPEAXW4align_val_t@std@@@Z"(i8* noundef %[[ALLOC]], i64 noundef 32) +// CHECK-MS: call void @"??3@YAXPEAXW4align_val_t@std@@@Z"(i8* %[[ALLOC]], i64 32) void *a0() { return new A; } // FIXME: Why don't we call the sized array deallocation overload in this case? // The size is known. // // CHECK-LABEL: define {{.*}} @_Z2a1l( -// CHECK: %[[ALLOC:.*]] = call noalias noundef nonnull align 32 i8* @_ZnamSt11align_val_t(i64 noundef %{{.*}}, i64 noundef 32) +// CHECK: %[[ALLOC:.*]] = call noalias nonnull align 32 i8* @_ZnamSt11align_val_t(i64 %{{.*}}, i64 32) // No array cookie. // CHECK-NOT: store // CHECK: invoke void @_ZN1AC1Ev( -// CHECK: call void @_ZdaPvSt11align_val_t(i8* noundef %[[ALLOC]], i64 noundef 32) +// CHECK: call void @_ZdaPvSt11align_val_t(i8* %[[ALLOC]], i64 32) // CHECK-MS-LABEL: define {{.*}} @"?a1@@YAPEAXJ@Z"( -// CHECK-MS: %[[ALLOC:.*]] = call noalias noundef nonnull align 32 i8* @"??_U@YAPEAX_KW4align_val_t@std@@@Z"(i64 noundef %{{.*}}, i64 noundef 32) +// CHECK-MS: %[[ALLOC:.*]] = call noalias nonnull align 32 i8* @"??_U@YAPEAX_KW4align_val_t@std@@@Z"(i64 %{{.*}}, i64 32) // No array cookie. // CHECK-MS-NOT: store -// CHECK-MS: invoke noundef %struct.A* @"??0A@@QEAA@XZ"( +// CHECK-MS: invoke %struct.A* @"??0A@@QEAA@XZ"( // CHECK-MS: cleanuppad -// CHECK-MS: call void @"??_V@YAXPEAXW4align_val_t@std@@@Z"(i8* noundef %[[ALLOC]], i64 noundef 32) +// CHECK-MS: call void @"??_V@YAXPEAXW4align_val_t@std@@@Z"(i8* %[[ALLOC]], i64 32) void *a1(long n) { return new A[n]; } // CHECK-LABEL: define {{.*}} @_Z2a2P1A( -// CHECK: call void @_ZdlPvmSt11align_val_t(i8* noundef %{{.*}}, i64 noundef 512, i64 noundef 32) #9 +// CHECK: call void @_ZdlPvmSt11align_val_t(i8* %{{.*}}, i64 512, i64 32) #9 void a2(A *p) { delete p; } // CHECK-LABEL: define {{.*}} @_Z2a3P1A( -// CHECK: call void @_ZdaPvSt11align_val_t(i8* noundef %{{.*}}, i64 noundef 32) #9 +// CHECK: call void @_ZdaPvSt11align_val_t(i8* %{{.*}}, i64 32) #9 void a3(A *p) { delete[] p; } @@ -79,24 +79,24 @@ struct OVERALIGNED B { }; // CHECK-LABEL: define {{.*}} @_Z2b0v() -// CHECK: %[[ALLOC:.*]] = call noundef i8* @_ZN1BnwEmSt11align_val_t(i64 noundef 512, i64 noundef 32) -// CHECK: call void @_ZN1BdlEPvSt11align_val_t(i8* noundef %[[ALLOC]], i64 noundef 32) +// CHECK: %[[ALLOC:.*]] = call i8* @_ZN1BnwEmSt11align_val_t(i64 512, i64 32) +// CHECK: call void @_ZN1BdlEPvSt11align_val_t(i8* %[[ALLOC]], i64 32) void *b0() { return new B; } // CHECK-LABEL: define {{.*}} @_Z2b1l( -// CHECK: %[[ALLOC:.*]] = call noalias noundef nonnull align 32 i8* @_ZnamSt11align_val_t(i64 noundef %{{.*}}, i64 noundef 32) +// CHECK: %[[ALLOC:.*]] = call noalias nonnull align 32 i8* @_ZnamSt11align_val_t(i64 %{{.*}}, i64 32) // No array cookie. // CHECK-NOT: store // CHECK: invoke void @_ZN1BC1Ev( -// CHECK: call void @_ZN1BdaEPvSt11align_val_t(i8* noundef %[[ALLOC]], i64 noundef 32) +// CHECK: call void @_ZN1BdaEPvSt11align_val_t(i8* %[[ALLOC]], i64 32) void *b1(long n) { return new B[n]; } // CHECK-LABEL: define {{.*}} @_Z2b2P1B( -// CHECK: call void @_ZN1BdlEPvSt11align_val_t(i8* noundef %{{.*}}, i64 noundef 32) +// CHECK: call void @_ZN1BdlEPvSt11align_val_t(i8* %{{.*}}, i64 32) void b2(B *p) { delete p; } // CHECK-LABEL: define {{.*}} @_Z2b3P1B( -// CHECK: call void @_ZN1BdaEPvSt11align_val_t(i8* noundef %{{.*}}, i64 noundef 32) +// CHECK: call void @_ZN1BdaEPvSt11align_val_t(i8* %{{.*}}, i64 32) void b3(B *p) { delete[] p; } struct OVERALIGNED C { @@ -113,7 +113,7 @@ struct OVERALIGNED C { // CHECK-LABEL: define {{.*}} @_Z2b4l( // CHECK: call {{.*}} @llvm.umul.with.overflow{{.*}}i64 32 // CHECK: call {{.*}} @llvm.uadd.with.overflow{{.*}}i64 32 -// CHECK: %[[ALLOC:.*]] = call noundef i8* @_ZN1CnaEmSt11align_val_t(i64 noundef %{{.*}}, i64 noundef 32) +// CHECK: %[[ALLOC:.*]] = call i8* @_ZN1CnaEmSt11align_val_t(i64 %{{.*}}, i64 32) // CHECK: store // CHECK: call void @_ZN1CC1Ev( // @@ -142,8 +142,8 @@ void operator delete(void*, Q); void operator delete(void*, std::align_val_t, Q); // CHECK-LABEL: define {{.*}} @_Z2c0v( -// CHECK: %[[ALLOC:.*]] = call noundef i8* @_ZnwmSt11align_val_t1Q(i64 noundef 512, i64 noundef 32, i32 % -// CHECK: call void @_ZdlPvSt11align_val_t1Q(i8* noundef %[[ALLOC]], i64 noundef 32, i32 % +// CHECK: %[[ALLOC:.*]] = call i8* @_ZnwmSt11align_val_t1Q(i64 512, i64 32, i32 % +// CHECK: call void @_ZdlPvSt11align_val_t1Q(i8* %[[ALLOC]], i64 32, i32 % void *c0() { return new (q) A; } @@ -159,8 +159,8 @@ struct OVERALIGNED D { }; // CHECK-LABEL: define {{.*}} @_Z2d0v( -// CHECK: %[[ALLOC:.*]] = call noundef i8* @_ZN1DnwEmSt11align_val_t1Q(i64 noundef 32, i64 noundef 32, i32 % -// CHECK: call void @_ZN1DdlEPvSt11align_val_t1Q(i8* noundef %[[ALLOC]], i64 noundef 32, i32 % +// CHECK: %[[ALLOC:.*]] = call i8* @_ZN1DnwEmSt11align_val_t1Q(i64 32, i64 32, i32 % +// CHECK: call void @_ZN1DdlEPvSt11align_val_t1Q(i8* %[[ALLOC]], i64 32, i32 % void *d0() { return new (q) D; } @@ -169,13 +169,13 @@ void *d0() { return new (q) D; } #ifndef UNALIGNED // CHECK-LABEL: define {{.*}} @_Z2e0v( -// CHECK: %[[ALLOC:.*]] = call noalias noundef nonnull align 4 i8* @_ZnwmSt11align_val_t(i64 noundef 512, i64 noundef 4) -// CHECK: call void @_ZdlPvSt11align_val_t(i8* noundef %[[ALLOC]], i64 noundef 4) +// CHECK: %[[ALLOC:.*]] = call noalias nonnull align 4 i8* @_ZnwmSt11align_val_t(i64 512, i64 4) +// CHECK: call void @_ZdlPvSt11align_val_t(i8* %[[ALLOC]], i64 4) void *e0() { return new (std::align_val_t(4)) A; } // CHECK-LABEL: define {{.*}} @_Z2e1v( -// CHECK: %[[ALLOC:.*]] = call noundef i8* @_ZN1BnwEmSt11align_val_t(i64 noundef 512, i64 noundef 4) -// CHECK: call void @_ZN1BdlEPvSt11align_val_t(i8* noundef %[[ALLOC]], i64 noundef 4) +// CHECK: %[[ALLOC:.*]] = call i8* @_ZN1BnwEmSt11align_val_t(i64 512, i64 4) +// CHECK: call void @_ZN1BdlEPvSt11align_val_t(i8* %[[ALLOC]], i64 4) void *e1() { return new (std::align_val_t(4)) B; } #endif @@ -190,17 +190,17 @@ struct OVERALIGNED F { }; // CHECK-LABEL: define {{.*}} @_Z2f0v( -// CHECK: %[[ALLOC:.*]] = call noundef i8* (i64, ...) @_ZN1FnwEmz(i64 noundef 512, i64 noundef 32) +// CHECK: %[[ALLOC:.*]] = call i8* (i64, ...) @_ZN1FnwEmz(i64 512, i64 32) // Non-placement allocation function, uses normal deallocation lookup which // cares about whether a parameter has type std::align_val_t. -// CHECK: call void (i8*, ...) @_ZN1FdlEPvz(i8* noundef %[[ALLOC]]) +// CHECK: call void (i8*, ...) @_ZN1FdlEPvz(i8* %[[ALLOC]]) void *f0() { return new F; } // CHECK-LABEL: define {{.*}} @_Z2f1v( -// CHECK: %[[ALLOC:.*]] = call noundef i8* (i64, ...) @_ZN1FnwEmz(i64 noundef 512, i64 noundef 32, i32 % +// CHECK: %[[ALLOC:.*]] = call i8* (i64, ...) @_ZN1FnwEmz(i64 512, i64 32, i32 % // Placement allocation function, uses placement deallocation matching, which // passes same arguments and therefore includes alignment. -// CHECK: call void (i8*, ...) @_ZN1FdlEPvz(i8* noundef %[[ALLOC]], i64 noundef 32, i32 % +// CHECK: call void (i8*, ...) @_ZN1FdlEPvz(i8* %[[ALLOC]], i64 32, i32 % void *f1() { return new (q) F; } struct OVERALIGNED G { @@ -211,12 +211,12 @@ struct OVERALIGNED G { }; #ifndef UNALIGNED // CHECK-LABEL: define {{.*}} @_Z2g0v -// CHECK: %[[ALLOC:.*]] = call noundef i8* (i64, i64, ...) @_ZN1GnwEmSt11align_val_tz(i64 noundef 512, i64 noundef 32) -// CHECK: call void (i8*, i64, ...) @_ZN1GdlEPvSt11align_val_tz(i8* noundef %[[ALLOC]], i64 noundef 32) +// CHECK: %[[ALLOC:.*]] = call i8* (i64, i64, ...) @_ZN1GnwEmSt11align_val_tz(i64 512, i64 32) +// CHECK: call void (i8*, i64, ...) @_ZN1GdlEPvSt11align_val_tz(i8* %[[ALLOC]], i64 32) void *g0() { return new G; } // CHECK-LABEL: define {{.*}} @_Z2g1v -// CHECK: %[[ALLOC:.*]] = call noundef i8* (i64, i64, ...) @_ZN1GnwEmSt11align_val_tz(i64 noundef 512, i64 noundef 32, i32 % -// CHECK: call void (i8*, i64, ...) @_ZN1GdlEPvSt11align_val_tz(i8* noundef %[[ALLOC]], i64 noundef 32, i32 % +// CHECK: %[[ALLOC:.*]] = call i8* (i64, i64, ...) @_ZN1GnwEmSt11align_val_tz(i64 512, i64 32, i32 % +// CHECK: call void (i8*, i64, ...) @_ZN1GdlEPvSt11align_val_tz(i8* %[[ALLOC]], i64 32, i32 % void *g1() { return new (q) G; } #endif diff --git a/clang/test/CodeGenCXX/cxx1z-copy-omission.cpp b/clang/test/CodeGenCXX/cxx1z-copy-omission.cpp index 197575133f64c6c00695119230b41300097732a7..6a589ec352d69d9fe512f78574d4449ff395715b 100644 --- a/clang/test/CodeGenCXX/cxx1z-copy-omission.cpp +++ b/clang/test/CodeGenCXX/cxx1z-copy-omission.cpp @@ -42,7 +42,7 @@ void h() { // CHECK: call {{.*}} @_Z1fv({{.*}}* sret({{.*}}) align 4 %[[A]]) // CHECK-NOT: call - // CHECK: call {{.*}} @_Z1f1A({{.*}}* noundef %[[A]]) + // CHECK: call {{.*}} @_Z1f1A({{.*}}* %[[A]]) f(f()); // CHECK-NOT: call // CHECK: call void @_ZN1AD1Ev({{.*}}* {{[^,]*}} %[[A]]) @@ -87,14 +87,14 @@ void j() { // CHECK: alloca %{{.*}}* // CHECK: %[[OUTERTEMP:.*]] = alloca %{{.*}} // CHECK: %[[INNERTEMP:.*]] = alloca %{{.*}} - // CHECK: call void @_ZN1AC1Ei(%{{.*}} %[[INNERTEMP]], i32 noundef 1) - // CHECK: call noundef zeroext i1 @_ZN1AcvbEv(%{{.*}} %[[INNERTEMP]]) + // CHECK: call void @_ZN1AC1Ei(%{{.*}} %[[INNERTEMP]], i32 1) + // CHECK: call zeroext i1 @_ZN1AcvbEv(%{{.*}} %[[INNERTEMP]]) // CHECK: br i1 // // CHECK: call void @_ZN1AC1EOS_(%{{.*}} %[[OUTERTEMP]], %{{.*}} %[[INNERTEMP]]) // CHECK: br label // - // CHECK: call void @_ZN1AC1Ei(%{{.*}} %[[OUTERTEMP]], i32 noundef 2) + // CHECK: call void @_ZN1AC1Ei(%{{.*}} %[[OUTERTEMP]], i32 2) // CHECK: br label // // CHECK: call void @_ZN1AD1Ev(%{{.*}} %[[INNERTEMP]]) diff --git a/clang/test/CodeGenCXX/cxx1z-decomposition.cpp b/clang/test/CodeGenCXX/cxx1z-decomposition.cpp index 06ac6ce3bdc9d19ece93959d07cb2ef18022950e..d4b8203a634bd836dfdfd3ed8c947efbf1cb8c70 100644 --- a/clang/test/CodeGenCXX/cxx1z-decomposition.cpp +++ b/clang/test/CodeGenCXX/cxx1z-decomposition.cpp @@ -54,7 +54,7 @@ auto [e1, e2] = make(); // CHECK: call i32 @__cxa_atexit({{.*}}@_ZN1XD1Ev{{.*}}@_ZGR2b1_ // CHECK: store {{.*}}* @_ZGR2b1_, // -// CHECK: call noundef double @_Z3getILi1EEDa1B() +// CHECK: call double @_Z3getILi1EEDa1B() // CHECK: fptosi double %{{.*}} to i32 // CHECK: store i32 %{{.*}}, i32* @_ZGR2b2_ // CHECK: store i32* @_ZGR2b2_, i32** @b2 @@ -95,7 +95,7 @@ int test_locals() { // CHECK: call i32 @_Z3getILi0EEDa1B() // CHECK: call void @_ZN1XC1E1Y({{.*}}* {{[^,]*}} %[[b1:.*]], i32 // - // CHECK: call noundef double @_Z3getILi1EEDa1B() + // CHECK: call double @_Z3getILi1EEDa1B() // CHECK: %[[cvt:.*]] = fptosi double %{{.*}} to i32 // CHECK: store i32 %[[cvt]], i32* %[[b2:.*]], // CHECK: store i32* %[[b2]], i32** %[[b2ref:.*]], diff --git a/clang/test/CodeGenCXX/cxx1z-init-statement.cpp b/clang/test/CodeGenCXX/cxx1z-init-statement.cpp index 0c9ed03d7f6cb759663c1d9bdc21954ff9832f46..522ae56d504ff6e2c4479ff2e395d65e76ab648f 100644 --- a/clang/test/CodeGenCXX/cxx1z-init-statement.cpp +++ b/clang/test/CodeGenCXX/cxx1z-init-statement.cpp @@ -22,7 +22,7 @@ void f1() { int f2() { // CHECK: %[[A:.*]] = alloca i32, align 4 - // CHECK-NEXT: %[[B:.*]] = call noundef i32 @_Z2f2v() + // CHECK-NEXT: %[[B:.*]] = call i32 @_Z2f2v() // CHECK-NEXT: store i32 7, i32* %[[A]], align 4 // CHECK-NEXT: %[[C:.*]] = load i32, i32* %[[A]], align 4 // CHECK-NEXT: %[[D:.*]] = icmp ne i32 %[[C]], 0 @@ -58,7 +58,7 @@ void g1() { int g2() { // CHECK: %[[A:.*]] = alloca i32, align 4 - // CHECK-NEXT: %[[B:.*]] = call noundef i32 @_Z2f2v() + // CHECK-NEXT: %[[B:.*]] = call i32 @_Z2f2v() // CHECK-NEXT: store i32 7, i32* %[[A]], align 4 // CHECK-NEXT: %[[C:.*]] = load i32, i32* %[[A]], align 4 // CHECK-NEXT: switch i32 %[[C]], label %[[E:.*]] [ diff --git a/clang/test/CodeGenCXX/cxx1z-initializer-aggregate.cpp b/clang/test/CodeGenCXX/cxx1z-initializer-aggregate.cpp index 07d65e71f28bd3857bba67e0689a520bb6a67336..35ea72df150dcc8d31e4f07cc3e9cd8d7206001c 100644 --- a/clang/test/CodeGenCXX/cxx1z-initializer-aggregate.cpp +++ b/clang/test/CodeGenCXX/cxx1z-initializer-aggregate.cpp @@ -65,9 +65,9 @@ namespace Dynamic { // CHECK-LABEL: define {{.*}}global_var_init // CHECK: call void @_ZN7Dynamic1AC2Ev({{.*}} @_ZN7Dynamic2d1E // CHECK: store i32 5, {{.*}}i8* getelementptr inbounds {{.*}} @_ZN7Dynamic2d1E{{.*}}, i64 8 - // CHECK: invoke void @_ZN7Dynamic1CC2Eb({{.*}} @_ZN7Dynamic2d1E{{.*}}, i1 noundef zeroext true) + // CHECK: invoke void @_ZN7Dynamic1CC2Eb({{.*}} @_ZN7Dynamic2d1E{{.*}}, i1 zeroext true) // CHECK: unwind label %[[UNWIND:.*]] - // CHECK: invoke noundef i32 @_ZN7Dynamic1fEv() + // CHECK: invoke i32 @_ZN7Dynamic1fEv() // CHECK: unwind label %[[UNWIND:.*]] // CHECK: store i32 {{.*}}, i32* getelementptr {{.*}} @_ZN7Dynamic2d1E, i32 0, i32 2 // CHECK: call {{.*}} @__cxa_atexit({{.*}} @_ZN7Dynamic1DD1Ev {{.*}} @_ZN7Dynamic2d1E @@ -79,24 +79,24 @@ namespace Dynamic { D d2 = {1, 2, false}; // CHECK-LABEL: define {{.*}}global_var_init - // CHECK: call void @_ZN7Dynamic1AC1Ei({{.*}} @_ZN7Dynamic2d2E{{.*}}, i32 noundef 1) + // CHECK: call void @_ZN7Dynamic1AC1Ei({{.*}} @_ZN7Dynamic2d2E{{.*}}, i32 1) // CHECK: store i32 2, {{.*}}i8* getelementptr inbounds {{.*}}@_ZN7Dynamic2d2E{{.*}}, i64 8 - // CHECK: invoke void @_ZN7Dynamic1CC1Eb({{.*}} @_ZN7Dynamic2d2E{{.*}}, i1 noundef zeroext false) - // CHECK: invoke noundef i32 @_ZN7Dynamic1fEv() + // CHECK: invoke void @_ZN7Dynamic1CC1Eb({{.*}} @_ZN7Dynamic2d2E{{.*}}, i1 zeroext false) + // CHECK: invoke i32 @_ZN7Dynamic1fEv() // CHECK: store i32 {{.*}}, i32* getelementptr {{.*}} @_ZN7Dynamic2d2E, i32 0, i32 2 // CHECK: call {{.*}} @__cxa_atexit({{.*}} @_ZN7Dynamic1DD1Ev {{.*}} @_ZN7Dynamic2d2E // CHECK: ret void D d3 = {g(), h(), {}, i()}; // CHECK-LABEL: define {{.*}}global_var_init - // CHECK: %[[G_CALL:.*]] = call noundef i32 @_ZN7Dynamic1gEv() - // CHECK: call void @_ZN7Dynamic1AC1Ei({{.*}} @_ZN7Dynamic2d3E{{.*}}, i32 noundef %[[G_CALL]]) - // CHECK: %[[H_CALL:.*]] = invoke noundef i32 @_ZN7Dynamic1hEv() + // CHECK: %[[G_CALL:.*]] = call i32 @_ZN7Dynamic1gEv() + // CHECK: call void @_ZN7Dynamic1AC1Ei({{.*}} @_ZN7Dynamic2d3E{{.*}}, i32 %[[G_CALL]]) + // CHECK: %[[H_CALL:.*]] = invoke i32 @_ZN7Dynamic1hEv() // CHECK: unwind label %[[DESTROY_A_LPAD:.*]] // CHECK: store i32 %[[H_CALL]], {{.*}}i8* getelementptr inbounds {{.*}} @_ZN7Dynamic2d3E{{.*}}, i64 8 - // CHECK: invoke void @_ZN7Dynamic1CC2Eb({{.*}} @_ZN7Dynamic2d3E{{.*}}, i1 noundef zeroext true) + // CHECK: invoke void @_ZN7Dynamic1CC2Eb({{.*}} @_ZN7Dynamic2d3E{{.*}}, i1 zeroext true) // CHECK: unwind label %[[DESTROY_AB_LPAD:.*]] - // CHECK: %[[I_CALL:.*]] = invoke noundef i32 @_ZN7Dynamic1iEv() + // CHECK: %[[I_CALL:.*]] = invoke i32 @_ZN7Dynamic1iEv() // CHECK: unwind label %[[DESTROY_AB_LPAD:.*]] // CHECK: store i32 %[[I_CALL]], i32* getelementptr {{.*}} @_ZN7Dynamic2d3E, i32 0, i32 2 // CHECK: call {{.*}} @__cxa_atexit({{.*}} @_ZN7Dynamic1DD1Ev {{.*}} @_ZN7Dynamic2d3E to i8* diff --git a/clang/test/CodeGenCXX/cxx1z-inline-variables.cpp b/clang/test/CodeGenCXX/cxx1z-inline-variables.cpp index b6e6aa0d7e67bdba9377fa139c35a3ee79bc5fa5..896db4acc13187bd1801a4212a1088a41d5426d6 100644 --- a/clang/test/CodeGenCXX/cxx1z-inline-variables.cpp +++ b/clang/test/CodeGenCXX/cxx1z-inline-variables.cpp @@ -88,18 +88,18 @@ const int &yib = Y::b; // CHECK-NOT: @_ZN1YIiE1cE // CHECK-LABEL: define {{.*}}global_var_init -// CHECK: call noundef i32 @_Z1fv +// CHECK: call i32 @_Z1fv // CHECK-LABEL: define {{.*}}global_var_init{{.*}} comdat($b) // CHECK: load atomic {{.*}} acquire, align // CHECK: br // CHECK: __cxa_guard_acquire(i64* @_ZGV1b) // CHECK: br -// CHECK: call noundef i32 @_Z1fv +// CHECK: call i32 @_Z1fv // CHECK: __cxa_guard_release(i64* @_ZGV1b) // CHECK-LABEL: define {{.*}}global_var_init -// CHECK: call noundef i32 @_Z1fv +// CHECK: call i32 @_Z1fv template inline int d = f(); int e = d; @@ -107,7 +107,7 @@ int e = d; // CHECK-LABEL: define {{.*}}global_var_init{{.*}}comdat // CHECK: _ZGV1dIiE // CHECK-NOT: __cxa_guard_acquire(i64* @_ZGV1b) -// CHECK: call noundef i32 @_Z1fv +// CHECK: call i32 @_Z1fv // CHECK-NOT: __cxa_guard_release(i64* @_ZGV1b) namespace PR35599 { diff --git a/clang/test/CodeGenCXX/cxx2a-consteval.cpp b/clang/test/CodeGenCXX/cxx2a-consteval.cpp index 0a962d82113cc8361bf3a1028b4df786f82975e6..b10ac8fa68259070459128784f1c9ad1c968209e 100644 --- a/clang/test/CodeGenCXX/cxx2a-consteval.cpp +++ b/clang/test/CodeGenCXX/cxx2a-consteval.cpp @@ -224,19 +224,12 @@ int test_UserConv() { return UserConv(); } -// EVAL-FN-LABEL: @_Z28test_UserConvOverload_helperi( -// EVAL-FN-NEXT: entry: -// EVAL-FN-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// EVAL-FN-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 -// EVAL-FN-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// EVAL-FN-NEXT: ret i32 [[TMP0]] -// int test_UserConvOverload_helper(int a) { return a; } // EVAL-FN-LABEL: @_Z21test_UserConvOverloadv( // EVAL-FN-NEXT: entry: -// EVAL-FN-NEXT: [[CALL:%.*]] = call noundef i32 @_Z28test_UserConvOverload_helperi(i32 noundef 42) -// EVAL-FN-NEXT: ret i32 [[CALL]] +// EVAL-FN-NEXT: %call = call i32 @_Z28test_UserConvOverload_helperi(i32 42) +// EVAL-FN-NEXT: ret i32 %call // int test_UserConvOverload() { return test_UserConvOverload_helper(UserConv()); diff --git a/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp b/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp index 3e21c8ba9d2006339d08b05df9d39dfbb4a282f1..2fe489efdd90cd14f3ea5cc39518b459876a7ccc 100644 --- a/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp +++ b/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp @@ -26,9 +26,9 @@ void delete_A(A *a) { delete a; } // // Ensure that we call the destroying delete and not the destructor. // CHECK-NOT: call -// CHECK-ITANIUM: call void @_ZN1AdlEPS_St19destroying_delete_t(%{{.*}}* noundef %[[a]]) -// CHECK-MSABI64: call void @"??3A@@SAXPEAU0@Udestroying_delete_t@std@@@Z"(%{{.*}}* noundef %[[a]], i8 -// CHECK-MSABI32: call void @"??3A@@SAXPAU0@Udestroying_delete_t@std@@@Z"(%{{.*}}* noundef %[[a]], %{{.*}}* noundef byval(%{{.*}}) align 4 %{{.*}}) +// CHECK-ITANIUM: call void @_ZN1AdlEPS_St19destroying_delete_t(%{{.*}}* %[[a]]) +// CHECK-MSABI64: call void @"??3A@@SAXPEAU0@Udestroying_delete_t@std@@@Z"(%{{.*}}* %[[a]], i8 +// CHECK-MSABI32: call void @"??3A@@SAXPAU0@Udestroying_delete_t@std@@@Z"(%{{.*}}* %[[a]], %{{.*}}* byval(%{{.*}}) align 4 %{{.*}}) // CHECK-NOT: call // CHECK: } @@ -46,8 +46,8 @@ void delete_B(B *b) { delete b; } // CHECK-NOT: call // CHECK: %[[VTABLE:.*]] = load // CHECK: %[[DTOR:.*]] = load -// CHECK: call {{void|noundef i8\*|x86_thiscallcc noundef i8\*}} %[[DTOR]](%{{.*}}* {{[^,]*}} %[[b]] -// CHECK-MSABI-SAME: , i32 noundef 1) +// CHECK: call {{void|i8\*|x86_thiscallcc i8\*}} %[[DTOR]](%{{.*}}* {{[^,]*}} %[[b]] +// CHECK-MSABI-SAME: , i32 1) // CHECK-NOT: call // CHECK: } @@ -72,9 +72,9 @@ void delete_C(C *c) { delete c; } // CHECK: br i1 // // CHECK-NOT: call -// CHECK-ITANIUM: call void @_ZN1AdlEPS_St19destroying_delete_t(%{{.*}}* noundef %[[a]]) -// CHECK-MSABI64: call void @"??3A@@SAXPEAU0@Udestroying_delete_t@std@@@Z"(%{{.*}}* noundef %[[a]], i8 -// CHECK-MSABI32: call void @"??3A@@SAXPAU0@Udestroying_delete_t@std@@@Z"(%{{.*}}* noundef %[[a]], %{{.*}}* noundef byval(%{{.*}}) align 4 %{{.*}}) +// CHECK-ITANIUM: call void @_ZN1AdlEPS_St19destroying_delete_t(%{{.*}}* %[[a]]) +// CHECK-MSABI64: call void @"??3A@@SAXPEAU0@Udestroying_delete_t@std@@@Z"(%{{.*}}* %[[a]], i8 +// CHECK-MSABI32: call void @"??3A@@SAXPAU0@Udestroying_delete_t@std@@@Z"(%{{.*}}* %[[a]], %{{.*}}* byval(%{{.*}}) align 4 %{{.*}}) // CHECK-NOT: call // CHECK: } @@ -97,8 +97,8 @@ void delete_D(D *d) { delete d; } // CHECK: %[[VTABLE:.*]] = load // CHECK: %[[DTOR:.*]] = load // -// CHECK: call {{void|noundef i8\*|x86_thiscallcc noundef i8\*}} %[[DTOR]](%{{.*}}* {{[^,]*}} %[[d]] -// CHECK-MSABI-SAME: , i32 noundef 1) +// CHECK: call {{void|i8\*|x86_thiscallcc i8\*}} %[[DTOR]](%{{.*}}* {{[^,]*}} %[[d]] +// CHECK-MSABI-SAME: , i32 1) // CHECK-NOT: call // CHECK: } @@ -144,9 +144,9 @@ struct alignas(16) G : E, F { void *data; }; void delete_G(G *g) { delete g; } // CHECK-LABEL: define {{.*}}delete_G // CHECK-NOT: call -// CHECK-ITANIUM: call void @_ZN1FdlEPS_St19destroying_delete_tmSt11align_val_t(%{{.*}}* noundef %[[a]], i64 noundef 32, i64 noundef 16) -// CHECK-MSABI64: call void @"??3F@@SAXPEAU0@Udestroying_delete_t@std@@_KW4align_val_t@2@@Z"(%{{.*}}* noundef %[[a]], i8 {{[^,]*}}, i64 noundef 32, i64 noundef 16) -// CHECK-MSABI32: call void @"??3F@@SAXPAU0@Udestroying_delete_t@std@@IW4align_val_t@2@@Z"(%{{.*}}* noundef %[[a]], %{{.*}}* noundef byval(%{{.*}}) align 4 %{{.*}}, i32 noundef 16, i32 noundef 16) +// CHECK-ITANIUM: call void @_ZN1FdlEPS_St19destroying_delete_tmSt11align_val_t(%{{.*}}* %[[a]], i64 32, i64 16) +// CHECK-MSABI64: call void @"??3F@@SAXPEAU0@Udestroying_delete_t@std@@_KW4align_val_t@2@@Z"(%{{.*}}* %[[a]], i8 {{[^,]*}}, i64 32, i64 16) +// CHECK-MSABI32: call void @"??3F@@SAXPAU0@Udestroying_delete_t@std@@IW4align_val_t@2@@Z"(%{{.*}}* %[[a]], %{{.*}}* byval(%{{.*}}) align 4 %{{.*}}, i32 16, i32 16) // CHECK-NOT: call // CHECK: } @@ -158,7 +158,7 @@ H::~H() { call_in_dtor(); } // CHECK-ITANIUM-NOT: call // CHECK-ITANIUM: getelementptr {{.*}}, i64 24 // CHECK-ITANIUM-NOT: call -// CHECK-ITANIUM: call void @_ZN1FdlEPS_St19destroying_delete_tmSt11align_val_t({{.*}}, i64 noundef 48, i64 noundef 16) +// CHECK-ITANIUM: call void @_ZN1FdlEPS_St19destroying_delete_tmSt11align_val_t({{.*}}, i64 48, i64 16) // CHECK-ITANIUM-NOT: call // CHECK-ITANIUM: } @@ -173,8 +173,8 @@ H::~H() { call_in_dtor(); } // CHECK-MSABI64: getelementptr {{.*}}, i64 24 // CHECK-MSABI32: getelementptr {{.*}}, i32 20 // CHECK-MSABI-NOT: call{{ }} -// CHECK-MSABI64: call void @"??3F@@SAXPEAU0@Udestroying_delete_t@std@@_KW4align_val_t@2@@Z"({{.*}}, i64 noundef 48, i64 noundef 16) -// CHECK-MSABI32: call void @"??3F@@SAXPAU0@Udestroying_delete_t@std@@IW4align_val_t@2@@Z"({{.*}}, i32 noundef 32, i32 noundef 16) +// CHECK-MSABI64: call void @"??3F@@SAXPEAU0@Udestroying_delete_t@std@@_KW4align_val_t@2@@Z"({{.*}}, i64 48, i64 16) +// CHECK-MSABI32: call void @"??3F@@SAXPAU0@Udestroying_delete_t@std@@IW4align_val_t@2@@Z"({{.*}}, i32 32, i32 16) // CHECK-MSABI: br label %[[RETURN:.*]] // // CHECK-MSABI64: call void @"??1H@@UEAA@XZ"( @@ -189,7 +189,7 @@ I::~I() { call_in_dtor(); } // CHECK-ITANIUM-NOT: call // CHECK-ITANIUM: getelementptr {{.*}}, i64 24 // CHECK-ITANIUM-NOT: call -// CHECK-ITANIUM: call void @_ZN1FdlEPS_St19destroying_delete_tmSt11align_val_t({{.*}}, i64 noundef 96, i64 noundef 32) +// CHECK-ITANIUM: call void @_ZN1FdlEPS_St19destroying_delete_tmSt11align_val_t({{.*}}, i64 96, i64 32) // CHECK-ITANIUM-NOT: call // CHECK-ITANIUM: } @@ -204,8 +204,8 @@ I::~I() { call_in_dtor(); } // CHECK-MSABI64: getelementptr {{.*}}, i64 24 // CHECK-MSABI32: getelementptr {{.*}}, i32 20 // CHECK-MSABI-NOT: call{{ }} -// CHECK-MSABI64: call void @"??3F@@SAXPEAU0@Udestroying_delete_t@std@@_KW4align_val_t@2@@Z"({{.*}}, i64 noundef 96, i64 noundef 32) -// CHECK-MSABI32: call void @"??3F@@SAXPAU0@Udestroying_delete_t@std@@IW4align_val_t@2@@Z"({{.*}}, i32 noundef 64, i32 noundef 32) +// CHECK-MSABI64: call void @"??3F@@SAXPEAU0@Udestroying_delete_t@std@@_KW4align_val_t@2@@Z"({{.*}}, i64 96, i64 32) +// CHECK-MSABI32: call void @"??3F@@SAXPAU0@Udestroying_delete_t@std@@IW4align_val_t@2@@Z"({{.*}}, i32 64, i32 32) // CHECK-MSABI: br label %[[RETURN:.*]] // // CHECK-MSABI64: call void @"??1I@@UEAA@XZ"( diff --git a/clang/test/CodeGenCXX/debug-info-codeview-heapallocsite.cpp b/clang/test/CodeGenCXX/debug-info-codeview-heapallocsite.cpp index 792189c6829dce8a0d74eb4c1b2d0c3cfee110dd..33e60380c6983cb19e45dac82792c1b1e87947b9 100644 --- a/clang/test/CodeGenCXX/debug-info-codeview-heapallocsite.cpp +++ b/clang/test/CodeGenCXX/debug-info-codeview-heapallocsite.cpp @@ -14,8 +14,8 @@ extern "C" void doit() { } // CHECK-LABEL: define {{.*}}void @doit -// CHECK: call {{.*}} i8* {{.*}}@"??2@YAPEAX_K@Z"(i64 noundef 4) {{.*}} !heapallocsite [[DBG_FOO:!.*]] -// CHECK: call {{.*}} i8* {{.*}}@"??2@YAPEAX_K@Z"(i64 noundef 4) {{.*}} !heapallocsite [[DBG_BAR:!.*]] +// CHECK: call {{.*}} i8* {{.*}}@"??2@YAPEAX_K@Z"(i64 4) {{.*}} !heapallocsite [[DBG_FOO:!.*]] +// CHECK: call {{.*}} i8* {{.*}}@"??2@YAPEAX_K@Z"(i64 4) {{.*}} !heapallocsite [[DBG_BAR:!.*]] extern "C" void useinvoke() { struct HasDtor { @@ -25,7 +25,7 @@ extern "C" void useinvoke() { } // CHECK-LABEL: define {{.*}}void @useinvoke -// CHECK: invoke {{.*}} i8* {{.*}}@"??2@YAPEAX_K@Z"(i64 noundef 4) +// CHECK: invoke {{.*}} i8* {{.*}}@"??2@YAPEAX_K@Z"(i64 4) // CHECK-NEXT: to label {{.*}} unwind label {{.*}} !heapallocsite [[DBG_FOO]] // CHECK: [[DBG_FOO]] = distinct !DICompositeType(tag: DW_TAG_structure_type, diff --git a/clang/test/CodeGenCXX/debug-info-destroy-helper.cpp b/clang/test/CodeGenCXX/debug-info-destroy-helper.cpp index 3a64c48484988faa1f1fa8a477305eee0605f01b..4146a645030f6895b7561cdcf5685b37b6eb3491 100644 --- a/clang/test/CodeGenCXX/debug-info-destroy-helper.cpp +++ b/clang/test/CodeGenCXX/debug-info-destroy-helper.cpp @@ -1,24 +1,24 @@ -// RUN: %clang_cc1 -emit-llvm %s -triple x86_64-windows-msvc -gcodeview -debug-info-kind=limited -o - | FileCheck %s - -struct b { - b(char *); - ~b(); -}; -struct a { - ~a(); -}; -struct { - b c; - const a &d; -} e[]{nullptr, {}}; - -// CHECK: define internal void @__cxx_global_array_dtor(i8* noundef %0) -// CHECK-SAME: !dbg ![[SUBPROGRAM:[0-9]+]] { -// CHECK: arraydestroy.body -// CHECK: %arraydestroy.elementPast = -// CHECK-SAME: !dbg ![[LOCATION:[0-9]+]] -// CHECK: call void @"??1@@QEAA@XZ"(%struct.anon* {{[^,]*}} %arraydestroy.element) -// CHECK-SAME: !dbg ![[LOCATION]] -// CHECK: ![[SUBPROGRAM]] = distinct !DISubprogram(name: "__cxx_global_array_dtor" -// CHECK-SAME: flags: DIFlagArtificial -// CHECK: ![[LOCATION]] = !DILocation(line: 0, +// RUN: %clang_cc1 -emit-llvm %s -triple x86_64-windows-msvc -gcodeview -debug-info-kind=limited -o - | FileCheck %s + +struct b { + b(char *); + ~b(); +}; +struct a { + ~a(); +}; +struct { + b c; + const a &d; +} e[]{nullptr, {}}; + +// CHECK: define internal void @__cxx_global_array_dtor(i8* %0) +// CHECK-SAME: !dbg ![[SUBPROGRAM:[0-9]+]] { +// CHECK: arraydestroy.body +// CHECK: %arraydestroy.elementPast = +// CHECK-SAME: !dbg ![[LOCATION:[0-9]+]] +// CHECK: call void @"??1@@QEAA@XZ"(%struct.anon* {{[^,]*}} %arraydestroy.element) +// CHECK-SAME: !dbg ![[LOCATION]] +// CHECK: ![[SUBPROGRAM]] = distinct !DISubprogram(name: "__cxx_global_array_dtor" +// CHECK-SAME: flags: DIFlagArtificial +// CHECK: ![[LOCATION]] = !DILocation(line: 0, diff --git a/clang/test/CodeGenCXX/debug-info-globalinit.cpp b/clang/test/CodeGenCXX/debug-info-globalinit.cpp index 0e3558f954f9b26d917b0159adf4f74ff89e8d6f..09c7d59bffed02c58b0f5c69d562f7aeaf8c06d9 100644 --- a/clang/test/CodeGenCXX/debug-info-globalinit.cpp +++ b/clang/test/CodeGenCXX/debug-info-globalinit.cpp @@ -18,19 +18,19 @@ int main(void) {} // CHECK-LABEL: define internal void @__cxx_global_var_init() // CHECK-NOT: __cxx_global_var_init -// CHECK: %[[C0:.+]] = call noundef i32 @_Z4testv(), !dbg ![[LINE:.*]] +// CHECK: %[[C0:.+]] = call i32 @_Z4testv(), !dbg ![[LINE:.*]] // CHECK-NOT: __cxx_global_var_init // CHECK: store i32 %[[C0]], i32* @_ZL1i, align 4, !dbg // // CHECK-LABEL: define internal void @__cxx_global_var_init.1() // CHECK-NOT: dbg -// CHECK: %[[C1:.+]] = call noundef i32 @_Z4testv() +// CHECK: %[[C1:.+]] = call i32 @_Z4testv() // CHECK-NOT: dbg // CHECK: store i32 %[[C1]], i32* @_ZL1j, align 4 // // CHECK-LABEL: define internal void @__cxx_global_var_init.2() // CHECK-NOT: __cxx_global_var_init -// CHECK: %[[C2:.+]] = call noundef i32 @_Z4testv(), !dbg ![[LINE2:.*]] +// CHECK: %[[C2:.+]] = call i32 @_Z4testv(), !dbg ![[LINE2:.*]] // CHECK-NOT: __cxx_global_var_init // CHECK: store i32 %[[C2]], i32* @_ZL1k, align 4, !dbg // diff --git a/clang/test/CodeGenCXX/debug-info-line.cpp b/clang/test/CodeGenCXX/debug-info-line.cpp index ebae9d944a7869a2baa848c776dbc2033dfe3caa..2581ea0712af3687da18235d5b7fc07dd04a5aab 100644 --- a/clang/test/CodeGenCXX/debug-info-line.cpp +++ b/clang/test/CodeGenCXX/debug-info-line.cpp @@ -158,7 +158,7 @@ __complex double f11() { void f12() { int f12_1(); void f12_2(int = f12_1()); -// CHECK: call {{.*}}{{(signext )?}}i32 noundef {{.*}} !dbg [[DBG_F12:!.*]] +// CHECK: call {{.*}}{{(signext )?}}i32 {{.*}} !dbg [[DBG_F12:!.*]] #line 1400 f12_2(); } @@ -296,7 +296,7 @@ void f24() { // CHECK-LABEL: define void f25_a(int x = __builtin_LINE()) {} void f25() { - // CHECK: call void @_Z5f25_ai(i32 noundef {{(signext )?}}2700) + // CHECK: call void @_Z5f25_ai(i32 {{(signext )?}}2700) #line 2700 f25_a(); } diff --git a/clang/test/CodeGenCXX/debug-info-nested-exprs.cpp b/clang/test/CodeGenCXX/debug-info-nested-exprs.cpp index b9fb02e87f07315a143108307af3cab94fdf9d44..fa934bf2aa008b4f45403acd0006ff397b1debec 100644 --- a/clang/test/CodeGenCXX/debug-info-nested-exprs.cpp +++ b/clang/test/CodeGenCXX/debug-info-nested-exprs.cpp @@ -30,17 +30,17 @@ int foo(int x, int y, int z) { int a = bar(x, y) + baz(x, z) + qux(y, z); - // NONEST: call noundef i32 @{{.*}}bar{{.*}}, !dbg ![[LOC:[0-9]+]] - // NONEST: call noundef i32 @{{.*}}baz{{.*}}, !dbg ![[LOC]] - // NONEST: call noundef i32 @{{.*}}qux{{.*}}, !dbg ![[LOC]] + // NONEST: call i32 @{{.*}}bar{{.*}}, !dbg ![[LOC:[0-9]+]] + // NONEST: call i32 @{{.*}}baz{{.*}}, !dbg ![[LOC]] + // NONEST: call i32 @{{.*}}qux{{.*}}, !dbg ![[LOC]] // NONEST: store i32 {{.*}}, i32* %a,{{.*}} !dbg ![[LOC]] - // NESTED: call noundef i32 @{{.*}}bar{{.*}}, !dbg ![[BAR:[0-9]+]] - // NESTED: call noundef i32 @{{.*}}baz{{.*}}, !dbg ![[BAZ:[0-9]+]] - // NESTED: call noundef i32 @{{.*}}qux{{.*}}, !dbg ![[QUX:[0-9]+]] + // NESTED: call i32 @{{.*}}bar{{.*}}, !dbg ![[BAR:[0-9]+]] + // NESTED: call i32 @{{.*}}baz{{.*}}, !dbg ![[BAZ:[0-9]+]] + // NESTED: call i32 @{{.*}}qux{{.*}}, !dbg ![[QUX:[0-9]+]] // NESTED: store i32 {{.*}}, i32* %a,{{.*}} !dbg ![[BAR]] - // COLUMNS: call noundef i32 @{{.*}}bar{{.*}}, !dbg ![[BAR:[0-9]+]] - // COLUMNS: call noundef i32 @{{.*}}baz{{.*}}, !dbg ![[BAZ:[0-9]+]] - // COLUMNS: call noundef i32 @{{.*}}qux{{.*}}, !dbg ![[QUX:[0-9]+]] + // COLUMNS: call i32 @{{.*}}bar{{.*}}, !dbg ![[BAR:[0-9]+]] + // COLUMNS: call i32 @{{.*}}baz{{.*}}, !dbg ![[BAZ:[0-9]+]] + // COLUMNS: call i32 @{{.*}}qux{{.*}}, !dbg ![[QUX:[0-9]+]] // COLUMNS: store i32 {{.*}}, i32* %a,{{.*}} !dbg ![[DECLA:[0-9]+]] int i = 1, b = 0, c = 0; @@ -58,23 +58,23 @@ int foo(int x, int y, int z) { b = bar(a, b); --i; } - // NONEST: call noundef i32 @{{.*}}bar{{.*}}, !dbg ![[WHILE1:[0-9]+]] + // NONEST: call i32 @{{.*}}bar{{.*}}, !dbg ![[WHILE1:[0-9]+]] // NONEST: store i32 %{{[^,]+}}, i32* %i,{{.*}} !dbg ![[WHILE2:[0-9]+]] - // NESTED: call noundef i32 @{{.*}}bar{{.*}}, !dbg ![[WHILE1:[0-9]+]] + // NESTED: call i32 @{{.*}}bar{{.*}}, !dbg ![[WHILE1:[0-9]+]] // NESTED: store i32 %{{[^,]+}}, i32* %i,{{.*}} !dbg ![[WHILE2:[0-9]+]] - // COLUMNS: call noundef i32 @{{.*}}bar{{.*}}, !dbg ![[WHILE1:[0-9]+]] + // COLUMNS: call i32 @{{.*}}bar{{.*}}, !dbg ![[WHILE1:[0-9]+]] // COLUMNS: store i32 %{{[^,]+}}, i32* %i,{{.*}} !dbg ![[WHILE2:[0-9]+]] for (i = 0; i < 1; i++) { b = bar(a, b); c = qux(a, c); } - // NONEST: call noundef i32 @{{.*}}bar{{.*}}, !dbg ![[FOR1:[0-9]+]] - // NONEST: call noundef i32 @{{.*}}qux{{.*}}, !dbg ![[FOR2:[0-9]+]] - // NESTED: call noundef i32 @{{.*}}bar{{.*}}, !dbg ![[FOR1:[0-9]+]] - // NESTED: call noundef i32 @{{.*}}qux{{.*}}, !dbg ![[FOR2:[0-9]+]] - // COLUMNS: call noundef i32 @{{.*}}bar{{.*}}, !dbg ![[FOR1:[0-9]+]] - // COLUMNS: call noundef i32 @{{.*}}qux{{.*}}, !dbg ![[FOR2:[0-9]+]] + // NONEST: call i32 @{{.*}}bar{{.*}}, !dbg ![[FOR1:[0-9]+]] + // NONEST: call i32 @{{.*}}qux{{.*}}, !dbg ![[FOR2:[0-9]+]] + // NESTED: call i32 @{{.*}}bar{{.*}}, !dbg ![[FOR1:[0-9]+]] + // NESTED: call i32 @{{.*}}qux{{.*}}, !dbg ![[FOR2:[0-9]+]] + // COLUMNS: call i32 @{{.*}}bar{{.*}}, !dbg ![[FOR1:[0-9]+]] + // COLUMNS: call i32 @{{.*}}qux{{.*}}, !dbg ![[FOR2:[0-9]+]] if (a < b) { int t = a; @@ -93,51 +93,51 @@ int foo(int x, int y, int z) { int d = onearg( noargs()); - // NONEST: call noundef i32 @{{.*}}noargs{{.*}}, !dbg ![[DECLD:[0-9]+]] - // NONEST: call noundef i32 @{{.*}}onearg{{.*}}, !dbg ![[DECLD]] + // NONEST: call i32 @{{.*}}noargs{{.*}}, !dbg ![[DECLD:[0-9]+]] + // NONEST: call i32 @{{.*}}onearg{{.*}}, !dbg ![[DECLD]] // NONEST: store i32 %{{[^,]+}}, i32* %d,{{.*}} !dbg ![[DECLD]] - // NESTED: call noundef i32 @{{.*}}noargs{{.*}}, !dbg ![[DNOARGS:[0-9]+]] - // NESTED: call noundef i32 @{{.*}}onearg{{.*}}, !dbg ![[DECLD:[0-9]+]] + // NESTED: call i32 @{{.*}}noargs{{.*}}, !dbg ![[DNOARGS:[0-9]+]] + // NESTED: call i32 @{{.*}}onearg{{.*}}, !dbg ![[DECLD:[0-9]+]] // NESTED: store i32 %{{[^,]+}}, i32* %d,{{.*}} !dbg ![[DECLD]] - // COLUMNS: call noundef i32 @{{.*}}noargs{{.*}}, !dbg ![[DNOARGS:[0-9]+]] - // COLUMNS: call noundef i32 @{{.*}}onearg{{.*}}, !dbg ![[DONEARG:[0-9]+]] + // COLUMNS: call i32 @{{.*}}noargs{{.*}}, !dbg ![[DNOARGS:[0-9]+]] + // COLUMNS: call i32 @{{.*}}onearg{{.*}}, !dbg ![[DONEARG:[0-9]+]] // COLUMNS: store i32 %{{[^,]+}}, i32* %d,{{.*}} !dbg ![[DECLD:[0-9]+]] d = onearg(noargs()); - // NONEST: call noundef i32 @{{.*}}noargs{{.*}}, !dbg ![[SETD:[0-9]+]] - // NONEST: call noundef i32 @{{.*}}onearg{{.*}}, !dbg ![[SETD]] + // NONEST: call i32 @{{.*}}noargs{{.*}}, !dbg ![[SETD:[0-9]+]] + // NONEST: call i32 @{{.*}}onearg{{.*}}, !dbg ![[SETD]] // NONEST: store i32 %{{[^,]+}}, i32* %d,{{.*}} !dbg ![[SETD]] - // NESTED: call noundef i32 @{{.*}}noargs{{.*}}, !dbg ![[SETD:[0-9]+]] - // NESTED: call noundef i32 @{{.*}}onearg{{.*}}, !dbg ![[SETD]] + // NESTED: call i32 @{{.*}}noargs{{.*}}, !dbg ![[SETD:[0-9]+]] + // NESTED: call i32 @{{.*}}onearg{{.*}}, !dbg ![[SETD]] // NESTED: store i32 %{{[^,]+}}, i32* %d,{{.*}} !dbg ![[SETD]] - // COLUMNS: call noundef i32 @{{.*}}noargs{{.*}}, !dbg ![[SETDNOARGS:[0-9]+]] - // COLUMNS: call noundef i32 @{{.*}}onearg{{.*}}, !dbg ![[SETDONEARG:[0-9]+]] + // COLUMNS: call i32 @{{.*}}noargs{{.*}}, !dbg ![[SETDNOARGS:[0-9]+]] + // COLUMNS: call i32 @{{.*}}onearg{{.*}}, !dbg ![[SETDONEARG:[0-9]+]] // COLUMNS: store i32 %{{[^,]+}}, i32* %d,{{.*}} !dbg ![[SETD:[0-9]+]] for (const auto x : range(noargs())) noargs1(); - // NONEST: call noundef i32 @{{.*}}noargs{{.*}}, !dbg ![[RANGEFOR:[0-9]+]] + // NONEST: call i32 @{{.*}}noargs{{.*}}, !dbg ![[RANGEFOR:[0-9]+]] // NONEST: call {{.+}} @{{.*}}range{{.*}}, !dbg ![[RANGEFOR]] - // NONEST: call noundef i32 @{{.*}}noargs1{{.*}}, !dbg ![[RANGEFOR_BODY:[0-9]+]] - // NESTED: call noundef i32 @{{.*}}noargs{{.*}}, !dbg ![[RANGEFOR:[0-9]+]] + // NONEST: call i32 @{{.*}}noargs1{{.*}}, !dbg ![[RANGEFOR_BODY:[0-9]+]] + // NESTED: call i32 @{{.*}}noargs{{.*}}, !dbg ![[RANGEFOR:[0-9]+]] // NESTED: call {{.+}} @{{.*}}range{{.*}}, !dbg ![[RANGEFOR]] - // NESTED: call noundef i32 @{{.*}}noargs1{{.*}}, !dbg ![[RANGEFOR_BODY:[0-9]+]] - // COLUMNS: call noundef i32 @{{.*}}noargs{{.*}}, !dbg ![[RANGEFOR_NOARGS:[0-9]+]] + // NESTED: call i32 @{{.*}}noargs1{{.*}}, !dbg ![[RANGEFOR_BODY:[0-9]+]] + // COLUMNS: call i32 @{{.*}}noargs{{.*}}, !dbg ![[RANGEFOR_NOARGS:[0-9]+]] // COLUMNS: call {{.+}} @{{.*}}range{{.*}}, !dbg ![[RANGEFOR_RANGE:[0-9]+]] - // COLUMNS: call noundef i32 @{{.*}}noargs1{{.*}}, !dbg ![[RANGEFOR_BODY:[0-9]+]] + // COLUMNS: call i32 @{{.*}}noargs1{{.*}}, !dbg ![[RANGEFOR_BODY:[0-9]+]] if (noargs() && noargs1()) { Foo::create().func(); } - // NONEST: call noundef i32 @{{.*}}noargs{{.*}}, !dbg ![[AND:[0-9]+]] - // NONEST: call noundef i32 @{{.*}}noargs1{{.*}}, !dbg ![[AND]] + // NONEST: call i32 @{{.*}}noargs{{.*}}, !dbg ![[AND:[0-9]+]] + // NONEST: call i32 @{{.*}}noargs1{{.*}}, !dbg ![[AND]] // NONEST: call {{.+}} @{{.*}}create{{.*}}, !dbg ![[AND_BODY:[0-9]+]] // NONEST: call void @{{.*}}func{{.*}}, !dbg ![[AND_BODY]] - // NESTED: call noundef i32 @{{.*}}noargs{{.*}}, !dbg ![[AND:[0-9]+]] - // NESTED: call noundef i32 @{{.*}}noargs1{{.*}}, !dbg ![[AND]] + // NESTED: call i32 @{{.*}}noargs{{.*}}, !dbg ![[AND:[0-9]+]] + // NESTED: call i32 @{{.*}}noargs1{{.*}}, !dbg ![[AND]] // NESTED: call {{.+}} @{{.*}}create{{.*}}, !dbg ![[AND_BODY:[0-9]+]] // NESTED: call void @{{.*}}func{{.*}}, !dbg ![[AND_BODY]] - // COLUMNS: call noundef i32 @{{.*}}noargs{{.*}}, !dbg ![[ANDLHS:[0-9]+]] - // COLUMNS: call noundef i32 @{{.*}}noargs1{{.*}}, !dbg ![[ANDRHS:[0-9]+]] + // COLUMNS: call i32 @{{.*}}noargs{{.*}}, !dbg ![[ANDLHS:[0-9]+]] + // COLUMNS: call i32 @{{.*}}noargs1{{.*}}, !dbg ![[ANDRHS:[0-9]+]] // COLUMNS: call {{.+}} @{{.*}}create{{.*}}, !dbg ![[AND_CREATE:[0-9]+]] // COLUMNS: call void @{{.*}}func{{.*}}, !dbg ![[AND_FUNC:[0-9]+]] diff --git a/clang/test/CodeGenCXX/debug-info-static-fns.cpp b/clang/test/CodeGenCXX/debug-info-static-fns.cpp index 0ce3cb7f325d94d545bf9ed0b36942564d378a50..2c8ed8f26c5656bdb886b7d0a973f1d9c96d18a9 100644 --- a/clang/test/CodeGenCXX/debug-info-static-fns.cpp +++ b/clang/test/CodeGenCXX/debug-info-static-fns.cpp @@ -7,7 +7,7 @@ namespace A { } // Verify that a is present and mangled. -// CHECK: define internal noundef i32 @_ZN1AL1aEi({{.*}} !dbg [[DBG:![0-9]+]] +// CHECK: define internal i32 @_ZN1AL1aEi({{.*}} !dbg [[DBG:![0-9]+]] // CHECK: [[DBG]] = distinct !DISubprogram(name: "a", linkageName: "_ZN1AL1aEi", // CHECK-SAME: line: 4 // CHECK-SAME: DISPFlagDefinition diff --git a/clang/test/CodeGenCXX/debug-info-thunk-msabi.cpp b/clang/test/CodeGenCXX/debug-info-thunk-msabi.cpp index 0b8333b25a34af8265345433c58fd1b014d09699..3dbabafdd87d5ed7be95d519d34ece2600bdcde7 100644 --- a/clang/test/CodeGenCXX/debug-info-thunk-msabi.cpp +++ b/clang/test/CodeGenCXX/debug-info-thunk-msabi.cpp @@ -6,7 +6,7 @@ class __declspec(dllexport) A { // CHECK: define {{.*}}void @"??_FA@@AAEXXZ" // CHECK-SAME: !dbg ![[SP:[0-9]+]] // CHECK-NOT: {{ret }} -// CHECK: call x86_thiscallcc noundef %class.A* @"??0A@@AAE@PAH@Z" +// CHECK: call x86_thiscallcc %class.A* @"??0A@@AAE@PAH@Z" // CHECK-SAME: !dbg ![[DBG:[0-9]+]] // CHECK: ret void, !dbg // diff --git a/clang/test/CodeGenCXX/decl-ref-init.cpp b/clang/test/CodeGenCXX/decl-ref-init.cpp index 6c46185eb7917712a7c0edaf139449b754686495..5497f767ba4906065e710d9edd6398059ecbe11a 100644 --- a/clang/test/CodeGenCXX/decl-ref-init.cpp +++ b/clang/test/CodeGenCXX/decl-ref-init.cpp @@ -23,5 +23,5 @@ int main() { const A& rca2 = d(); } -// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.A* @_ZN1BcvR1AEv -// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.A* @_ZN1BcvR1AEv +// CHECK: call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.A* @_ZN1BcvR1AEv +// CHECK: call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.A* @_ZN1BcvR1AEv diff --git a/clang/test/CodeGenCXX/default-arg-temps.cpp b/clang/test/CodeGenCXX/default-arg-temps.cpp index e796043d0477fd8b44d4851cf16ffab46f0ddaa2..8ef23837d964bf7b016f25ee04c3ffe9315a7e21 100644 --- a/clang/test/CodeGenCXX/default-arg-temps.cpp +++ b/clang/test/CodeGenCXX/default-arg-temps.cpp @@ -16,12 +16,12 @@ public: // CHECK-LABEL: define{{.*}} void @_Z1gv() void g() { // CHECK: call void @_ZN1TC1Ev([[T:%.*]]* {{[^,]*}} [[AGG1:%.*]]) - // CHECK-NEXT: call void @_Z1fRK1T([[T]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[AGG1]]) + // CHECK-NEXT: call void @_Z1fRK1T([[T]]* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[AGG1]]) // CHECK-NEXT: call void @_ZN1TD1Ev([[T]]* {{[^,]*}} [[AGG1]]) f(); // CHECK-NEXT: call void @_ZN1TC1Ev([[T:%.*]]* {{[^,]*}} [[AGG2:%.*]]) - // CHECK-NEXT: call void @_Z1fRK1T([[T]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[AGG2]]) + // CHECK-NEXT: call void @_Z1fRK1T([[T]]* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[AGG2]]) // CHECK-NEXT: call void @_ZN1TD1Ev([[T]]* {{[^,]*}} [[AGG2]]) f(); diff --git a/clang/test/CodeGenCXX/default-arguments.cpp b/clang/test/CodeGenCXX/default-arguments.cpp index 6c8758a0a6d111eb8a6cf0703c2c5dec516117ec..106d13eb2692bcf0b597423c9fc28cefaab554ba 100644 --- a/clang/test/CodeGenCXX/default-arguments.cpp +++ b/clang/test/CodeGenCXX/default-arguments.cpp @@ -71,6 +71,6 @@ void f4() { } void g4(int a = 5, int b); - // CHECK: call void @_Z2g4ii(i32 noundef 5, i32 noundef 7) + // CHECK: call void @_Z2g4ii(i32 5, i32 7) g4(); } diff --git a/clang/test/CodeGenCXX/default_calling_conv.cpp b/clang/test/CodeGenCXX/default_calling_conv.cpp index 0991f862b881d5c296ff358ffbc5d7ff855b85f7..83d1200e0ab109f9540b1e6ca4154e99188dedbf 100644 --- a/clang/test/CodeGenCXX/default_calling_conv.cpp +++ b/clang/test/CodeGenCXX/default_calling_conv.cpp @@ -55,42 +55,42 @@ int main() { } #ifdef WINDOWS -// WIN32: define dso_local noundef i32 @wmain -// WIN64: define dso_local noundef i32 @wmain +// WIN32: define dso_local i32 @wmain +// WIN64: define dso_local i32 @wmain int wmain() { return 1; } -// WIN32: define dso_local x86_stdcallcc noundef i32 @WinMain -// WIN64: define dso_local noundef i32 @WinMain +// WIN32: define dso_local x86_stdcallcc i32 @WinMain +// WIN64: define dso_local i32 @WinMain int WinMain() { return 1; } -// WIN32: define dso_local x86_stdcallcc noundef i32 @wWinMain -// WIN64: define dso_local noundef i32 @wWinMain +// WIN32: define dso_local x86_stdcallcc i32 @wWinMain +// WIN64: define dso_local i32 @wWinMain int wWinMain() { return 1; } -// WIN32: define dso_local x86_stdcallcc noundef i32 @DllMain -// WIN64: define dso_local noundef i32 @DllMain +// WIN32: define dso_local x86_stdcallcc i32 @DllMain +// WIN64: define dso_local i32 @DllMain int DllMain() { return 1; } #endif // Windows #ifdef EXPLICITCC -// EXPLICITCC: define dso_local x86_fastcallcc noundef i32 @wmain +// EXPLICITCC: define dso_local x86_fastcallcc i32 @wmain int __fastcall wmain() { return 1; } -// EXPLICITCC: define dso_local x86_fastcallcc noundef i32 @WinMain +// EXPLICITCC: define dso_local x86_fastcallcc i32 @WinMain int __fastcall WinMain() { return 1; } -// EXPLICITCC: define dso_local x86_fastcallcc noundef i32 @wWinMain +// EXPLICITCC: define dso_local x86_fastcallcc i32 @wWinMain int __fastcall wWinMain() { return 1; } -// EXPLICITCC: define dso_local x86_fastcallcc noundef i32 @DllMain +// EXPLICITCC: define dso_local x86_fastcallcc i32 @DllMain int __fastcall DllMain() { return 1; } diff --git a/clang/test/CodeGenCXX/delete-two-arg.cpp b/clang/test/CodeGenCXX/delete-two-arg.cpp index ecccbad5e8acc2ccb601d52b4f95609748144384..5870eebd8f92e4d2f0cfbbabe30b3be288da5a29 100644 --- a/clang/test/CodeGenCXX/delete-two-arg.cpp +++ b/clang/test/CodeGenCXX/delete-two-arg.cpp @@ -11,7 +11,7 @@ namespace test1 { // CHECK: load // CHECK-NEXT: icmp eq {{.*}}, null // CHECK-NEXT: br i1 - // CHECK: call void @_ZN5test11AdlEPvj(i8* noundef %{{.*}}, i32 noundef 4) + // CHECK: call void @_ZN5test11AdlEPvj(i8* %{{.*}}, i32 4) delete x; } } @@ -27,7 +27,7 @@ namespace test2 { // CHECK: define{{.*}} [[A:%.*]]* @_ZN5test24testEv() A *test() { - // CHECK: [[NEW:%.*]] = call noalias noundef nonnull i8* @_Znaj(i32 noundef 44) + // CHECK: [[NEW:%.*]] = call noalias nonnull i8* @_Znaj(i32 44) // CHECK-NEXT: [[T0:%.*]] = bitcast i8* [[NEW]] to i32* // CHECK-NEXT: store i32 10, i32* [[T0]] // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds i8, i8* [[NEW]], i32 4 @@ -47,7 +47,7 @@ namespace test2 { // CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds i8, i8* [[T2]], i32 -4 // CHECK-NEXT: [[T4:%.*]] = bitcast i8* [[T3]] to i32* // CHECK-NEXT: [[T5:%.*]] = load i32, i32* [[T4]] - // CHECK-NEXT: call void @_ZdaPv(i8* noundef [[T3]]) + // CHECK-NEXT: call void @_ZdaPv(i8* [[T3]]) // CHECK-NEXT: br label ::delete[] p; } @@ -63,7 +63,7 @@ namespace test3 { // CHECK-LABEL: define{{.*}} void @_ZN5test34testEv() void test() { - // CHECK: [[CALL:%.*]] = call noalias noundef nonnull i8* @_Znaj(i32 noundef 24) + // CHECK: [[CALL:%.*]] = call noalias nonnull i8* @_Znaj(i32 24) // CHECK-NEXT: bitcast i8* [[CALL]] to i32* // CHECK-NEXT: store i32 5 (void) new B[5]; diff --git a/clang/test/CodeGenCXX/delete.cpp b/clang/test/CodeGenCXX/delete.cpp index 5f5b6a44a2f6eb41d62fbb56d7cd4686b4799460..3e837c5c307260fcbf9f6d1a0a51f346dbcd4252 100644 --- a/clang/test/CodeGenCXX/delete.cpp +++ b/clang/test/CodeGenCXX/delete.cpp @@ -100,7 +100,7 @@ namespace test1 { // CHECK-NEXT: call void @_ZN5test11AD1Ev([[A]]* {{[^,]*}} [[CUR]]) // CHECK-NEXT: [[ISDONE:%.*]] = icmp eq [[A]]* [[CUR]], [[BEGIN]] // CHECK-NEXT: br i1 [[ISDONE]] - // CHECK: call void @_ZdaPv(i8* noundef [[ALLOC]]) + // CHECK: call void @_ZdaPv(i8* [[ALLOC]]) } } @@ -139,14 +139,14 @@ namespace test4 { // CHECK-NEXT: [[T0:%.*]] = bitcast [[X]]* [[XP]] to i8* // CHECK-NEXT: [[ALLOCATED:%.*]] = getelementptr inbounds i8, i8* [[T0]], i64 [[OFFSET]] // Load the complete-object destructor (not the deleting destructor) - // and call noundef it. + // and call it. // CHECK-NEXT: [[T0:%.*]] = bitcast [[X:%.*]]* [[XP:%.*]] to void ([[X]]*)*** // CHECK-NEXT: [[VTABLE:%.*]] = load void ([[X]]*)**, void ([[X]]*)*** [[T0]] // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds void ([[X]]*)*, void ([[X]]*)** [[VTABLE]], i64 0 // CHECK-NEXT: [[DTOR:%.*]] = load void ([[X]]*)*, void ([[X]]*)** [[T0]] // CHECK-NEXT: call void [[DTOR]]([[X]]* {{[^,]*}} [[OBJ:%.*]]) // Call the global operator delete. - // CHECK-NEXT: call void @_ZdlPv(i8* noundef [[ALLOCATED]]) [[NUW:#[0-9]+]] + // CHECK-NEXT: call void @_ZdlPv(i8* [[ALLOCATED]]) [[NUW:#[0-9]+]] ::delete xp; } } diff --git a/clang/test/CodeGenCXX/derived-to-base-conv.cpp b/clang/test/CodeGenCXX/derived-to-base-conv.cpp index 916401174d21cd113b03fdb7ea96276007d77572..1d99e3e513910a95715497a472413eb21e778628 100644 --- a/clang/test/CodeGenCXX/derived-to-base-conv.cpp +++ b/clang/test/CodeGenCXX/derived-to-base-conv.cpp @@ -33,10 +33,10 @@ void test0(X x) { test0_helper(x); // CHECK-LABEL: define{{.*}} void @_Z5test01X( // CHECK: [[TMP:%.*]] = alloca [[A:%.*]], align - // CHECK-NEXT: [[T0:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[B:%.*]]* @_ZN1XcvR1BEv( + // CHECK-NEXT: [[T0:%.*]] = call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[B:%.*]]* @_ZN1XcvR1BEv( // CHECK-NEXT: [[T1:%.*]] = bitcast [[B]]* [[T0]] to [[A]]* - // CHECK-NEXT: call void @_ZN1AC1ERKS_([[A]]* {{[^,]*}} [[TMP]], [[A]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[T1]]) - // CHECK-NEXT: call void @_Z12test0_helper1A([[A]]* noundef [[TMP]]) + // CHECK-NEXT: call void @_ZN1AC1ERKS_([[A]]* {{[^,]*}} [[TMP]], [[A]]* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[T1]]) + // CHECK-NEXT: call void @_Z12test0_helper1A([[A]]* [[TMP]]) // CHECK-NEXT: call void @_ZN1AD1Ev([[A]]* {{[^,]*}} [[TMP]]) // CHECK-NEXT: ret void } diff --git a/clang/test/CodeGenCXX/derived-to-base.cpp b/clang/test/CodeGenCXX/derived-to-base.cpp index d91612002677be48667c94bb0f405433748c0734..19aed059c55f3f0fb18d23db3b4f5033fdbb02c9 100644 --- a/clang/test/CodeGenCXX/derived-to-base.cpp +++ b/clang/test/CodeGenCXX/derived-to-base.cpp @@ -15,7 +15,7 @@ void f() { b.f(); } -// CHECK: define{{.*}} %struct.B* @_Z1fP1A(%struct.A* noundef %a) [[NUW:#[0-9]+]] +// CHECK: define{{.*}} %struct.B* @_Z1fP1A(%struct.A* %a) [[NUW:#[0-9]+]] B *f(A *a) { // CHECK-NOT: br label // CHECK: ret %struct.B* @@ -25,7 +25,7 @@ B *f(A *a) { // PR5965 namespace PR5965 { -// CHECK: define{{.*}} %struct.A* @_ZN6PR59651fEP1B(%struct.B* noundef %b) [[NUW]] +// CHECK: define{{.*}} %struct.A* @_ZN6PR59651fEP1B(%struct.B* %b) [[NUW]] A *f(B* b) { // CHECK-NOT: br label // CHECK: ret %struct.A* diff --git a/clang/test/CodeGenCXX/destructors.cpp b/clang/test/CodeGenCXX/destructors.cpp index 190b8df6f6a06fbf5b9db37c8e371365736df217..d2f1a47a56910d84d55ea459e6ca3d138d5ccc6c 100644 --- a/clang/test/CodeGenCXX/destructors.cpp +++ b/clang/test/CodeGenCXX/destructors.cpp @@ -116,13 +116,13 @@ namespace test0 { B::~B() try { } catch (int i) {} // It will suppress the delegation optimization here, though. -// CHECK2-LABEL: define{{.*}} void @_ZN5test01BD2Ev(%"struct.test0::B"* {{[^,]*}} %this, i8** noundef %vtt) unnamed_addr +// CHECK2-LABEL: define{{.*}} void @_ZN5test01BD2Ev(%"struct.test0::B"* {{[^,]*}} %this, i8** %vtt) unnamed_addr // CHECK2: invoke void @_ZN5test06MemberD1Ev // CHECK2: unwind label [[MEM_UNWIND:%[a-zA-Z0-9.]+]] // CHECK2: invoke void @_ZN5test04BaseD2Ev // CHECK2: unwind label [[BASE_UNWIND:%[a-zA-Z0-9.]+]] -// CHECK2v11-LABEL: define{{.*}} void @_ZN5test01BD2Ev(%"struct.test0::B"* {{[^,]*}} %this, i8** noundef %vtt) unnamed_addr +// CHECK2v11-LABEL: define{{.*}} void @_ZN5test01BD2Ev(%"struct.test0::B"* {{[^,]*}} %this, i8** %vtt) unnamed_addr // CHECK2v11: call void @_ZN5test06MemberD1Ev // CHECK2v11: call void @_ZN5test04BaseD2Ev @@ -182,7 +182,7 @@ namespace test1 { // The VTT parameter prevents this. We could still make this work // for calling conventions that are safe against extra parameters. struct U : A, virtual B { ~U(); }; - U::~U() {} // CHECK4-LABEL: define{{.*}} void @_ZN5test11UD2Ev(%"struct.test1::U"* {{[^,]*}} %this, i8** noundef %vtt) unnamed_addr + U::~U() {} // CHECK4-LABEL: define{{.*}} void @_ZN5test11UD2Ev(%"struct.test1::U"* {{[^,]*}} %this, i8** %vtt) unnamed_addr } // PR6471 @@ -359,7 +359,7 @@ namespace test6 { // FIXME: way too much EH cleanup code follows C::~C() { opaque(); } - // CHECK5-LABEL: define{{.*}} void @_ZN5test61CD2Ev(%"struct.test6::C"* {{[^,]*}} %this, i8** noundef %vtt) unnamed_addr + // CHECK5-LABEL: define{{.*}} void @_ZN5test61CD2Ev(%"struct.test6::C"* {{[^,]*}} %this, i8** %vtt) unnamed_addr // CHECK5: invoke void @_ZN5test66opaqueEv // CHECK5v03: invoke void @_ZN5test61AD1Ev // CHECK5v03: invoke void @_ZN5test61AD1Ev diff --git a/clang/test/CodeGenCXX/devirtualize-ms-dtor.cpp b/clang/test/CodeGenCXX/devirtualize-ms-dtor.cpp index 35c1016f01527424d9da27a86e3f099b2b8d4aa6..d999b0c2dc405b98b25b65c040802522f6551e8e 100644 --- a/clang/test/CodeGenCXX/devirtualize-ms-dtor.cpp +++ b/clang/test/CodeGenCXX/devirtualize-ms-dtor.cpp @@ -11,6 +11,6 @@ void f(Foo *p) { p->~Foo(); } -// CHECK-LABEL: define{{.*}} void @"?f@@YAXPEAUFoo@@@Z"(%struct.Foo* noundef %p) +// CHECK-LABEL: define{{.*}} void @"?f@@YAXPEAUFoo@@@Z"(%struct.Foo* %p) // CHECK: call void @"??1Foo@@UEAA@XZ" // CHECK: ret void diff --git a/clang/test/CodeGenCXX/devirtualize-virtual-function-calls-final.cpp b/clang/test/CodeGenCXX/devirtualize-virtual-function-calls-final.cpp index 3af046ca7701c06b48048b16615f6fc16df26d49..963a88d0270fd56700c4a9fdb4a031e89ef2a762 100644 --- a/clang/test/CodeGenCXX/devirtualize-virtual-function-calls-final.cpp +++ b/clang/test/CodeGenCXX/devirtualize-virtual-function-calls-final.cpp @@ -7,7 +7,7 @@ namespace Test1 { // CHECK-LABEL: define{{.*}} i32 @_ZN5Test11fEPNS_1AE int f(A *a) { - // CHECK: call noundef i32 @_ZN5Test11A1fEv + // CHECK: call i32 @_ZN5Test11A1fEv return a->f(); } } @@ -19,7 +19,7 @@ namespace Test2 { // CHECK-LABEL: define{{.*}} i32 @_ZN5Test21fEPNS_1AE int f(A *a) { - // CHECK: call noundef i32 @_ZN5Test21A1fEv + // CHECK: call i32 @_ZN5Test21A1fEv return a->f(); } } @@ -32,7 +32,7 @@ namespace Test2a { // CHECK-LABEL: define{{.*}} i32 @_ZN6Test2a1fEPNS_1AE int f(A *a) { - // CHECK: call noundef i32 @_ZN6Test2a1A1fEv + // CHECK: call i32 @_ZN6Test2a1A1fEv return a->f(); } } @@ -46,19 +46,19 @@ namespace Test3 { // CHECK-LABEL: define{{.*}} i32 @_ZN5Test31fEPNS_1BE int f(B *b) { - // CHECK: call noundef i32 @_ZN5Test31A1fEv + // CHECK: call i32 @_ZN5Test31A1fEv return b->f(); } // CHECK-LABEL: define{{.*}} i32 @_ZN5Test31fERNS_1BE int f(B &b) { - // CHECK: call noundef i32 @_ZN5Test31A1fEv + // CHECK: call i32 @_ZN5Test31A1fEv return b.f(); } // CHECK-LABEL: define{{.*}} i32 @_ZN5Test31fEPv int f(void *v) { - // CHECK: call noundef i32 @_ZN5Test31A1fEv + // CHECK: call i32 @_ZN5Test31A1fEv return static_cast(v)->f(); } } @@ -78,7 +78,7 @@ namespace Test4 { void f(B* d) { // CHECK: call void @_ZN5Test41B1fEv static_cast(d)->f(); - // CHECK: call noundef i32 @_ZN5Test41BngEv + // CHECK: call i32 @_ZN5Test41BngEv -static_cast(*d); } } @@ -112,7 +112,7 @@ namespace Test5 { // not implemented yet. // CHECK: getelementptr // CHECK-NEXT: %[[FUNC:.*]] = load - // CHECK-NEXT: call noundef i32 %[[FUNC]] + // CHECK-NEXT: call i32 %[[FUNC]] -static_cast(*d); } } @@ -159,7 +159,7 @@ namespace Test7 { // CHECK: alloca // CHECK-NEXT: store // CHECK-NEXT: load - // CHECK-NEXT: call noundef i32 @_ZN5Test73zed1fEv + // CHECK-NEXT: call i32 @_ZN5Test73zed1fEv // CHECK-NEXT: ret return static_cast(z)->f(); } @@ -175,7 +175,7 @@ namespace Test8 { // CHECK-LABEL: define{{.*}} i32 @_ZN5Test84testEPNS_1CE int test(C *c) { // CHECK: %[[THIS:.*]] = phi - // CHECK-NEXT: call noundef i32 @_ZN5Test81B3fooEv(%"struct.Test8::B"* {{[^,]*}} %[[THIS]]) + // CHECK-NEXT: call i32 @_ZN5Test81B3fooEv(%"struct.Test8::B"* {{[^,]*}} %[[THIS]]) return static_cast(c)->foo(); } } @@ -250,7 +250,7 @@ namespace Test10 { // CHECK-LABEL: define{{.*}} i32 @_ZN6Test101fEPNS_1BE int f(B *b) { - // CHECK: call noundef i32 @_ZN6Test101B1fEv + // CHECK: call i32 @_ZN6Test101B1fEv return static_cast(b)->f(); } } @@ -303,13 +303,13 @@ namespace Test11 { // CHECK-LABEL: define linkonce_odr void @_ZN6Test111SIiE4foo1Ev( // CHECK: call void @_ZN6Test111SIiE7DerivedclEv( - // CHECK: call noundef zeroext i1 @_ZN6Test111SIiE7DerivedeqERKNS_4BaseE( - // CHECK: call noundef zeroext i1 @_ZN6Test111SIiE7DerivedntEv( - // CHECK: call noundef nonnull align 4 dereferenceable(4) %"class.Test11::Base"* @_ZN6Test111SIiE7DerivedixEi( + // CHECK: call zeroext i1 @_ZN6Test111SIiE7DerivedeqERKNS_4BaseE( + // CHECK: call zeroext i1 @_ZN6Test111SIiE7DerivedntEv( + // CHECK: call nonnull align 4 dereferenceable(4) %"class.Test11::Base"* @_ZN6Test111SIiE7DerivedixEi( // CHECK: define linkonce_odr void @_ZN6Test111SIiE7DerivedclEv( - // CHECK: define linkonce_odr noundef zeroext i1 @_ZN6Test111SIiE7DerivedeqERKNS_4BaseE( - // CHECK: define linkonce_odr noundef zeroext i1 @_ZN6Test111SIiE7DerivedntEv( - // CHECK: define linkonce_odr noundef nonnull align 4 dereferenceable(4) %"class.Test11::Base"* @_ZN6Test111SIiE7DerivedixEi( + // CHECK: define linkonce_odr zeroext i1 @_ZN6Test111SIiE7DerivedeqERKNS_4BaseE( + // CHECK: define linkonce_odr zeroext i1 @_ZN6Test111SIiE7DerivedntEv( + // CHECK: define linkonce_odr nonnull align 4 dereferenceable(4) %"class.Test11::Base"* @_ZN6Test111SIiE7DerivedixEi( class Base { public: virtual void operator()() {} diff --git a/clang/test/CodeGenCXX/devirtualize-virtual-function-calls.cpp b/clang/test/CodeGenCXX/devirtualize-virtual-function-calls.cpp index 39f7a74254e173b4e16b8db2288ca7022a6a7959..ea4869299e5a881175cecd12efa5c12fc490af1e 100644 --- a/clang/test/CodeGenCXX/devirtualize-virtual-function-calls.cpp +++ b/clang/test/CodeGenCXX/devirtualize-virtual-function-calls.cpp @@ -127,7 +127,7 @@ namespace test2 { void f(bar *b) { // CHECK: call void @_ZN5test23foo1fEv - // CHECK: call noundef %"struct.test2::foo"* @_ZN5test23fooD1Ev + // CHECK: call %"struct.test2::foo"* @_ZN5test23fooD1Ev b->foo::f(); b->foo::~foo(); } diff --git a/clang/test/CodeGenCXX/dllexport-ctor-closure.cpp b/clang/test/CodeGenCXX/dllexport-ctor-closure.cpp index 9d8135122b91d49f12ae4369f30b5b99aa7db407..42401e5ecd5d87e6fdbf71d64937d70bb4d8e633 100644 --- a/clang/test/CodeGenCXX/dllexport-ctor-closure.cpp +++ b/clang/test/CodeGenCXX/dllexport-ctor-closure.cpp @@ -9,7 +9,7 @@ struct CtorWithClosure { // CHECK: %[[this_addr:.*]] = alloca %struct.CtorWithClosure*, align 4 // CHECK: store %struct.CtorWithClosure* %this, %struct.CtorWithClosure** %[[this_addr]], align 4 // CHECK: %[[this:.*]] = load %struct.CtorWithClosure*, %struct.CtorWithClosure** %[[this_addr]] -// CHECK: call noundef %struct.CtorWithClosure* (%struct.CtorWithClosure*, ...) @"??0CtorWithClosure@@QAA@ZZ"(%struct.CtorWithClosure* {{[^,]*}} %[[this]]) +// CHECK: call %struct.CtorWithClosure* (%struct.CtorWithClosure*, ...) @"??0CtorWithClosure@@QAA@ZZ"(%struct.CtorWithClosure* {{[^,]*}} %[[this]]) // CHECK: ret void }; @@ -32,7 +32,7 @@ struct __declspec(dllexport) ClassWithClosure { // CHECK: %[[this_addr:.*]] = alloca %struct.ClassWithClosure*, align 4 // CHECK: store %struct.ClassWithClosure* %this, %struct.ClassWithClosure** %[[this_addr]], align 4 // CHECK: %[[this:.*]] = load %struct.ClassWithClosure*, %struct.ClassWithClosure** %[[this_addr]] -// CHECK: call noundef %struct.ClassWithClosure* (%struct.ClassWithClosure*, ...) @"??0ClassWithClosure@@QAA@ZZ"(%struct.ClassWithClosure* {{[^,]*}} %[[this]]) +// CHECK: call %struct.ClassWithClosure* (%struct.ClassWithClosure*, ...) @"??0ClassWithClosure@@QAA@ZZ"(%struct.ClassWithClosure* {{[^,]*}} %[[this]]) // CHECK: ret void }; @@ -45,10 +45,10 @@ extern template struct TemplateWithClosure; template struct __declspec(dllexport) TemplateWithClosure; // CHECK-LABEL: define weak_odr dso_local dllexport x86_thiscallcc void @"??_F?$TemplateWithClosure@D@@QAEXXZ"({{.*}}) {{#[0-9]+}} comdat -// CHECK: call {{.*}} @"??0?$TemplateWithClosure@D@@QAE@H@Z"({{.*}}, i32 noundef 1) +// CHECK: call {{.*}} @"??0?$TemplateWithClosure@D@@QAE@H@Z"({{.*}}, i32 1) // CHECK-LABEL: define weak_odr dso_local dllexport x86_thiscallcc void @"??_F?$TemplateWithClosure@H@@QAEXXZ"({{.*}}) {{#[0-9]+}} comdat -// CHECK: call {{.*}} @"??0?$TemplateWithClosure@H@@QAE@H@Z"({{.*}}, i32 noundef 4) +// CHECK: call {{.*}} @"??0?$TemplateWithClosure@H@@QAE@H@Z"({{.*}}, i32 4) template struct __declspec(dllexport) ExportedTemplateWithClosure { ExportedTemplateWithClosure(int x = sizeof(T)) {} @@ -56,7 +56,7 @@ template struct __declspec(dllexport) ExportedTemplateWithClosure { template <> ExportedTemplateWithClosure::ExportedTemplateWithClosure(int); // Don't try to emit the closure for a declaration. template <> ExportedTemplateWithClosure::ExportedTemplateWithClosure(int) {}; // CHECK-LABEL: define weak_odr dso_local dllexport x86_thiscallcc void @"??_F?$ExportedTemplateWithClosure@H@@QAEXXZ"({{.*}}) {{#[0-9]+}} comdat -// CHECK: call {{.*}} @"??0?$ExportedTemplateWithClosure@H@@QAE@H@Z"({{.*}}, i32 noundef 4) +// CHECK: call {{.*}} @"??0?$ExportedTemplateWithClosure@H@@QAE@H@Z"({{.*}}, i32 4) struct __declspec(dllexport) NestedOuter { DELETE_IMPLICIT_MEMBERS(NestedOuter); diff --git a/clang/test/CodeGenCXX/dllexport-dtor-thunks.cpp b/clang/test/CodeGenCXX/dllexport-dtor-thunks.cpp index 33a2cfab626cdb193f979a5458964d3b84bf0562..d2aa195e8cc3a96e258743018081d50f21f7003f 100644 --- a/clang/test/CodeGenCXX/dllexport-dtor-thunks.cpp +++ b/clang/test/CodeGenCXX/dllexport-dtor-thunks.cpp @@ -14,4 +14,4 @@ C::~C() {} // CHECK: define dso_local dllexport void @"??1C@@UEAA@XZ" // This thunk should *not* be dllexport. -// CHECK: define linkonce_odr dso_local noundef i8* @"??_EC@@W7EAAPEAXI@Z" +// CHECK: define linkonce_odr dso_local i8* @"??_EC@@W7EAAPEAXI@Z" diff --git a/clang/test/CodeGenCXX/dllexport-members.cpp b/clang/test/CodeGenCXX/dllexport-members.cpp index 0dab20a59ae87aadbb43e5bf04ffe67611042a52..99312751b2b7a846a17ac12d5130adb4bdf78e6f 100644 --- a/clang/test/CodeGenCXX/dllexport-members.cpp +++ b/clang/test/CodeGenCXX/dllexport-members.cpp @@ -1,9 +1,9 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-msvc -fms-compatibility -fms-compatibility-version=18 -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=MSC --check-prefix=M32 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-windows-msvc -fms-compatibility -fms-compatibility-version=18 -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=MSC --check-prefix=M64 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-msvc -fms-compatibility -fms-compatibility-version=19 -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=M32VS2015 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-windows-msvc -fms-compatibility -fms-compatibility-version=19 -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=M64VS2015 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-gnu -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=GNU --check-prefix=G32 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-windows-gnu -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=GNU --check-prefix=G64 %s +// RUN: %clang_cc1 -triple i686-windows-msvc -fms-compatibility -fms-compatibility-version=18 -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=MSC --check-prefix=M32 %s +// RUN: %clang_cc1 -triple x86_64-windows-msvc -fms-compatibility -fms-compatibility-version=18 -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=MSC --check-prefix=M64 %s +// RUN: %clang_cc1 -triple i686-windows-msvc -fms-compatibility -fms-compatibility-version=19 -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=M32VS2015 %s +// RUN: %clang_cc1 -triple x86_64-windows-msvc -fms-compatibility -fms-compatibility-version=19 -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=M64VS2015 %s +// RUN: %clang_cc1 -triple i686-windows-gnu -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=GNU --check-prefix=G32 %s +// RUN: %clang_cc1 -triple x86_64-windows-gnu -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=GNU --check-prefix=G64 %s // Helper structs to make templates more expressive. struct ImplicitInst_Exported {}; diff --git a/clang/test/CodeGenCXX/dllexport-no-dllexport-inlines.cpp b/clang/test/CodeGenCXX/dllexport-no-dllexport-inlines.cpp index a7871560c411614324edcba0e989e3a1af48fd0b..02cab5e2b4e05aa9fe90cf726b2a8d663c191dce 100644 --- a/clang/test/CodeGenCXX/dllexport-no-dllexport-inlines.cpp +++ b/clang/test/CodeGenCXX/dllexport-no-dllexport-inlines.cpp @@ -15,7 +15,7 @@ struct __declspec(dllexport) ExportedClass { // EXPORTINLINE-DAG: define weak_odr dso_local dllexport void @"?InclassDefFunc@ExportedClass@@ void InclassDefFunc() {} - // CHECK-DAG: define weak_odr dso_local dllexport noundef i32 @"?InclassDefFuncWithStaticVariable@ExportedClass@@QEAAHXZ" + // CHECK-DAG: define weak_odr dso_local dllexport i32 @"?InclassDefFuncWithStaticVariable@ExportedClass@@QEAAHXZ" int InclassDefFuncWithStaticVariable() { // CHECK-DAG: @"?static_variable@?1??InclassDefFuncWithStaticVariable@ExportedClass@@QEAAHXZ@4HA" = weak_odr dso_local dllexport global i32 0, comdat, align 4 static int static_variable = 0; @@ -23,7 +23,7 @@ struct __declspec(dllexport) ExportedClass { return static_variable; } - // CHECK-DAG: define weak_odr dso_local dllexport noundef i32 @"?InclassDefFunctWithLambdaStaticVariable@ExportedClass@@QEAAHXZ" + // CHECK-DAG: define weak_odr dso_local dllexport i32 @"?InclassDefFunctWithLambdaStaticVariable@ExportedClass@@QEAAHXZ" int InclassDefFunctWithLambdaStaticVariable() { // CHECK-DAG: @"?static_x@?2???R@?0??InclassDefFunctWithLambdaStaticVariable@ExportedClass@@QEAAHXZ@QEBA?A?@@XZ@4HA" = weak_odr dso_local dllexport global i32 0, comdat, align 4 return ([]() { static int static_x; return ++static_x; })(); @@ -33,7 +33,7 @@ struct __declspec(dllexport) ExportedClass { // EXPORTINLINE-DAG: define weak_odr dso_local dllexport void @"?InlineOutclassDefFunc@ExportedClass@@QEAAXXZ inline void InlineOutclassDefFunc(); - // CHECK-DAG: define weak_odr dso_local dllexport noundef i32 @"?InlineOutclassDefFuncWithStaticVariable@ExportedClass@@QEAAHXZ" + // CHECK-DAG: define weak_odr dso_local dllexport i32 @"?InlineOutclassDefFuncWithStaticVariable@ExportedClass@@QEAAHXZ" inline int InlineOutclassDefFuncWithStaticVariable(); // CHECK-DAG: define dso_local dllexport void @"?OutoflineDefFunc@ExportedClass@@QEAAXXZ" @@ -69,13 +69,13 @@ class A11{}; class B22{}; // CHECK-DAG: define weak_odr dso_local dllexport void @"?InclassDefFunc@?$TemplateExportedClass@VA11@@@@QEAAXXZ" -// CHECK-DAG: define weak_odr dso_local dllexport noundef i32 @"?InclassDefFuncWithStaticVariable@?$TemplateExportedClass@VA11@@@@QEAAHXZ" +// CHECK-DAG: define weak_odr dso_local dllexport i32 @"?InclassDefFuncWithStaticVariable@?$TemplateExportedClass@VA11@@@@QEAAHXZ" // CHECK-DAG: @"?static_x@?2??InclassDefFuncWithStaticVariable@?$TemplateExportedClass@VA11@@@@QEAAHXZ@4HA" = weak_odr dso_local dllexport global i32 0, comdat, align 4 template class TemplateExportedClass; // NOEXPORTINLINE-DAG: define linkonce_odr dso_local void @"?InclassDefFunc@?$TemplateExportedClass@VB22@@@@QEAAXXZ" // EXPORTINLINE-DAG: define weak_odr dso_local dllexport void @"?InclassDefFunc@?$TemplateExportedClass@VB22@@@@QEAAXXZ -// CHECK-DAG: define weak_odr dso_local dllexport noundef i32 @"?InclassDefFuncWithStaticVariable@?$TemplateExportedClass@VB22@@@@QEAAHXZ" +// CHECK-DAG: define weak_odr dso_local dllexport i32 @"?InclassDefFuncWithStaticVariable@?$TemplateExportedClass@VB22@@@@QEAAHXZ" // CHECK-DAG: @"?static_x@?2??InclassDefFuncWithStaticVariable@?$TemplateExportedClass@VB22@@@@QEAAHXZ@4HA" = weak_odr dso_local dllexport global i32 0, comdat, align 4 TemplateExportedClass b22; @@ -95,12 +95,12 @@ struct TemplateNoAttributeClass { }; // CHECK-DAG: define weak_odr dso_local dllexport void @"?InclassDefFunc@?$TemplateNoAttributeClass@VA11@@@@QEAAXXZ" -// CHECK-DAG: define weak_odr dso_local dllexport noundef i32 @"?InclassDefFuncWithStaticLocal@?$TemplateNoAttributeClass@VA11 +// CHECK-DAG: define weak_odr dso_local dllexport i32 @"?InclassDefFuncWithStaticLocal@?$TemplateNoAttributeClass@VA11 // CHECK-DAG: @"?static_x@?2??InclassDefFuncWithStaticLocal@?$TemplateNoAttributeClass@VA11@@@@QEAAHXZ@4HA" = weak_odr dso_local dllexport global i32 0, comdat, align 4 template class __declspec(dllexport) TemplateNoAttributeClass; // CHECK-DAG: define available_externally dllimport void @"?InclassDefFunc@?$TemplateNoAttributeClass@VB22@@@@QEAAXXZ" -// CHECK-DAG: define available_externally dllimport noundef i32 @"?InclassDefFuncWithStaticLocal@?$TemplateNoAttributeClass@VB22@@@@QEAAHXZ" +// CHECK-DAG: define available_externally dllimport i32 @"?InclassDefFuncWithStaticLocal@?$TemplateNoAttributeClass@VB22@@@@QEAAHXZ" // CHECK-DAG: @"?static_x@?2??InclassDefFuncWithStaticLocal@?$TemplateNoAttributeClass@VB22@@@@QEAAHXZ@4HA" = available_externally dllimport global i32 0, align 4 extern template class __declspec(dllimport) TemplateNoAttributeClass; @@ -115,8 +115,8 @@ struct __declspec(dllimport) ImportedClass { // EXPORTINLINE-DAG: define available_externally dllimport void @"?InClassDefFunc@ImportedClass@@QEAAXXZ" void InClassDefFunc() {} - // EXPORTINLINE-DAG: define available_externally dllimport noundef i32 @"?InClassDefFuncWithStaticVariable@ImportedClass@@QEAAHXZ" - // NOEXPORTINLINE-DAG: define linkonce_odr dso_local noundef i32 @"?InClassDefFuncWithStaticVariable@ImportedClass@@QEAAHXZ" + // EXPORTINLINE-DAG: define available_externally dllimport i32 @"?InClassDefFuncWithStaticVariable@ImportedClass@@QEAAHXZ" + // NOEXPORTINLINE-DAG: define linkonce_odr dso_local i32 @"?InClassDefFuncWithStaticVariable@ImportedClass@@QEAAHXZ" int InClassDefFuncWithStaticVariable() { // CHECK-DAG: @"?static_variable@?1??InClassDefFuncWithStaticVariable@ImportedClass@@QEAAHXZ@4HA" = available_externally dllimport global i32 0, align 4 static int static_variable = 0; diff --git a/clang/test/CodeGenCXX/dllexport.cpp b/clang/test/CodeGenCXX/dllexport.cpp index fb3d0f9484783e32c7df94a19ae702a3763033d8..a0f53c8e2e9ff137c6d08e9a54ab964c08a60f48 100644 --- a/clang/test/CodeGenCXX/dllexport.cpp +++ b/clang/test/CodeGenCXX/dllexport.cpp @@ -1,11 +1,11 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-msvc -emit-llvm -std=c++1y -fno-threadsafe-statics -fms-extensions -O1 -mconstructor-aliases -disable-llvm-passes -o - %s -w -fms-compatibility-version=19.00 | FileCheck -allow-deprecated-dag-overlap --check-prefix=MSC --check-prefix=M32 -check-prefix=MSVC2015 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-msvc -emit-llvm -std=c++1y -fno-threadsafe-statics -fms-extensions -O1 -mconstructor-aliases -disable-llvm-passes -o - %s -w -fms-compatibility-version=18.00 | FileCheck -allow-deprecated-dag-overlap --check-prefix=MSC --check-prefix=M32 -check-prefix=MSVC2013 -check-prefix=M32MSVC2013 %s +// RUN: %clang_cc1 -triple i686-windows-msvc -emit-llvm -std=c++1y -fno-threadsafe-statics -fms-extensions -O1 -mconstructor-aliases -disable-llvm-passes -o - %s -w -fms-compatibility-version=19.00 | FileCheck -allow-deprecated-dag-overlap --check-prefix=MSC --check-prefix=M32 -check-prefix=MSVC2015 %s +// RUN: %clang_cc1 -triple i686-windows-msvc -emit-llvm -std=c++1y -fno-threadsafe-statics -fms-extensions -O1 -mconstructor-aliases -disable-llvm-passes -o - %s -w -fms-compatibility-version=18.00 | FileCheck -allow-deprecated-dag-overlap --check-prefix=MSC --check-prefix=M32 -check-prefix=MSVC2013 -check-prefix=M32MSVC2013 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-windows-msvc -emit-llvm -std=c++1y -fno-threadsafe-statics -fms-extensions -O0 -o - %s -w -fms-compatibility-version=19.00 | FileCheck -allow-deprecated-dag-overlap --check-prefix=MSC --check-prefix=M64 -check-prefix=MSVC2015 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-windows-msvc -emit-llvm -std=c++1y -fno-threadsafe-statics -fms-extensions -O0 -o - %s -w -fms-compatibility-version=18.00 | FileCheck -allow-deprecated-dag-overlap --check-prefix=MSC --check-prefix=M64 -check-prefix=MSVC2013 %s +// RUN: %clang_cc1 -triple x86_64-windows-msvc -emit-llvm -std=c++1y -fno-threadsafe-statics -fms-extensions -O0 -o - %s -w -fms-compatibility-version=19.00 | FileCheck -allow-deprecated-dag-overlap --check-prefix=MSC --check-prefix=M64 -check-prefix=MSVC2015 %s +// RUN: %clang_cc1 -triple x86_64-windows-msvc -emit-llvm -std=c++1y -fno-threadsafe-statics -fms-extensions -O0 -o - %s -w -fms-compatibility-version=18.00 | FileCheck -allow-deprecated-dag-overlap --check-prefix=MSC --check-prefix=M64 -check-prefix=MSVC2013 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-gnu -emit-llvm -std=c++1y -fno-threadsafe-statics -fms-extensions -O0 -o - %s -w | FileCheck -allow-deprecated-dag-overlap --check-prefix=GNU --check-prefix=G32 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-windows-gnu -emit-llvm -std=c++1y -fno-threadsafe-statics -fms-extensions -O0 -o - %s -w | FileCheck -allow-deprecated-dag-overlap --check-prefix=GNU %s +// RUN: %clang_cc1 -triple i686-windows-gnu -emit-llvm -std=c++1y -fno-threadsafe-statics -fms-extensions -O0 -o - %s -w | FileCheck -allow-deprecated-dag-overlap --check-prefix=GNU --check-prefix=G32 %s +// RUN: %clang_cc1 -triple x86_64-windows-gnu -emit-llvm -std=c++1y -fno-threadsafe-statics -fms-extensions -O0 -o - %s -w | FileCheck -allow-deprecated-dag-overlap --check-prefix=GNU %s // Helper structs to make templates more expressive. struct ImplicitInst_Exported {}; diff --git a/clang/test/CodeGenCXX/dllimport-members.cpp b/clang/test/CodeGenCXX/dllimport-members.cpp index 795dfa6c21186fbd506ccae26c6aad10e1e7757d..37eda806463b2d73500072622ad153ffe76196a9 100644 --- a/clang/test/CodeGenCXX/dllimport-members.cpp +++ b/clang/test/CodeGenCXX/dllimport-members.cpp @@ -1,9 +1,9 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-msvc -fms-compatibility -emit-llvm -std=c++1y -O0 -o - %s -DMSABI | FileCheck --check-prefix=MSC --check-prefix=M32 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-windows-msvc -fms-compatibility -emit-llvm -std=c++1y -O0 -o - %s -DMSABI | FileCheck --check-prefix=MSC --check-prefix=M64 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-gnu -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=GNU --check-prefix=G32 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-windows-gnu -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=GNU --check-prefix=G64 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-msvc -fms-compatibility -emit-llvm -std=c++1y -O1 -fno-experimental-new-pass-manager -o - %s -DMSABI | FileCheck --check-prefix=MO1 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-gnu -emit-llvm -std=c++1y -O1 -fno-experimental-new-pass-manager -o - %s | FileCheck --check-prefix=GO1 %s +// RUN: %clang_cc1 -triple i686-windows-msvc -fms-compatibility -emit-llvm -std=c++1y -O0 -o - %s -DMSABI | FileCheck --check-prefix=MSC --check-prefix=M32 %s +// RUN: %clang_cc1 -triple x86_64-windows-msvc -fms-compatibility -emit-llvm -std=c++1y -O0 -o - %s -DMSABI | FileCheck --check-prefix=MSC --check-prefix=M64 %s +// RUN: %clang_cc1 -triple i686-windows-gnu -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=GNU --check-prefix=G32 %s +// RUN: %clang_cc1 -triple x86_64-windows-gnu -emit-llvm -std=c++1y -O0 -o - %s | FileCheck --check-prefix=GNU --check-prefix=G64 %s +// RUN: %clang_cc1 -triple i686-windows-msvc -fms-compatibility -emit-llvm -std=c++1y -O1 -fno-experimental-new-pass-manager -o - %s -DMSABI | FileCheck --check-prefix=MO1 %s +// RUN: %clang_cc1 -triple i686-windows-gnu -emit-llvm -std=c++1y -O1 -fno-experimental-new-pass-manager -o - %s | FileCheck --check-prefix=GO1 %s // Helper structs to make templates more expressive. struct ImplicitInst_Imported {}; diff --git a/clang/test/CodeGenCXX/dllimport-runtime-fns.cpp b/clang/test/CodeGenCXX/dllimport-runtime-fns.cpp index e2ae9cd3e8243aebbc8023bd86e92aea810de232..78ab280c9b063659555021134c3703689b37bbf0 100644 --- a/clang/test/CodeGenCXX/dllimport-runtime-fns.cpp +++ b/clang/test/CodeGenCXX/dllimport-runtime-fns.cpp @@ -48,16 +48,16 @@ struct C : A, virtual B {}; struct T {}; T *foo3() { return dynamic_cast((C *)0); } // __RTDynamicCast should not be marked dllimport. -// MSVC-LABEL: define dso_local noundef %struct.T* @"?foo3@@YAPEAUT@@XZ" +// MSVC-LABEL: define dso_local %struct.T* @"?foo3@@YAPEAUT@@XZ" // MSVC: call i8* @__RTDynamicCast({{.*}}) // MSVC: declare dso_local i8* @__RTDynamicCast(i8*, i32, i8*, i8*, i32) // Again, imported -// ITANIUM-LABEL: define dso_local noundef %struct.T* @_Z4foo3v() +// ITANIUM-LABEL: define dso_local %struct.T* @_Z4foo3v() // ITANIUM: call i8* @__dynamic_cast({{.*}}) // ITANIUM: declare dllimport i8* @__dynamic_cast({{.*}}) // Not imported -// GNU-LABEL: define dso_local noundef %struct.T* @_Z4foo3v() +// GNU-LABEL: define dso_local %struct.T* @_Z4foo3v() // GNU: call i8* @__dynamic_cast({{.*}}) // GNU: declare dso_local i8* @__dynamic_cast({{.*}}) diff --git a/clang/test/CodeGenCXX/dllimport.cpp b/clang/test/CodeGenCXX/dllimport.cpp index c354325ec45aaef442cb82ac672c7392b3cf429b..6113b28ed5c77bd9585d0f0bccaf4162117d0dd6 100644 --- a/clang/test/CodeGenCXX/dllimport.cpp +++ b/clang/test/CodeGenCXX/dllimport.cpp @@ -1,14 +1,14 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-msvc -fno-rtti -fno-threadsafe-statics -fms-extensions -emit-llvm -std=c++1y -O0 -o - %s -DMSABI -w | FileCheck --check-prefix=MSC --check-prefix=M32 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-windows-msvc -fno-rtti -fno-threadsafe-statics -fms-extensions -emit-llvm -std=c++1y -O0 -o - %s -DMSABI -w | FileCheck --check-prefix=MSC --check-prefix=M64 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-gnu -fno-rtti -fno-threadsafe-statics -fms-extensions -emit-llvm -std=c++1y -O0 -o - %s -w | FileCheck --check-prefix=GNU --check-prefix=G32 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-windows-gnu -fno-rtti -fno-threadsafe-statics -fms-extensions -emit-llvm -std=c++1y -O0 -o - %s -w | FileCheck --check-prefix=GNU %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-msvc -fno-rtti -fno-threadsafe-statics -fms-extensions -fms-compatibility-version=18.00 -emit-llvm -std=c++1y -O1 -disable-llvm-passes -o - %s -DMSABI -w | FileCheck --check-prefix=MO1 --check-prefix=M18 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-msvc -fno-rtti -fno-threadsafe-statics -fms-extensions -fms-compatibility-version=19.00 -emit-llvm -std=c++1y -O1 -disable-llvm-passes -o - %s -DMSABI -w | FileCheck --check-prefix=MO1 --check-prefix=M19 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-gnu -fno-rtti -fno-threadsafe-statics -fms-extensions -emit-llvm -std=c++1y -O1 -fno-experimental-new-pass-manager -o - %s -w | FileCheck --check-prefix=GO1 %s +// RUN: %clang_cc1 -triple i686-windows-msvc -fno-rtti -fno-threadsafe-statics -fms-extensions -emit-llvm -std=c++1y -O0 -o - %s -DMSABI -w | FileCheck --check-prefix=MSC --check-prefix=M32 %s +// RUN: %clang_cc1 -triple x86_64-windows-msvc -fno-rtti -fno-threadsafe-statics -fms-extensions -emit-llvm -std=c++1y -O0 -o - %s -DMSABI -w | FileCheck --check-prefix=MSC --check-prefix=M64 %s +// RUN: %clang_cc1 -triple i686-windows-gnu -fno-rtti -fno-threadsafe-statics -fms-extensions -emit-llvm -std=c++1y -O0 -o - %s -w | FileCheck --check-prefix=GNU --check-prefix=G32 %s +// RUN: %clang_cc1 -triple x86_64-windows-gnu -fno-rtti -fno-threadsafe-statics -fms-extensions -emit-llvm -std=c++1y -O0 -o - %s -w | FileCheck --check-prefix=GNU %s +// RUN: %clang_cc1 -triple i686-windows-msvc -fno-rtti -fno-threadsafe-statics -fms-extensions -fms-compatibility-version=18.00 -emit-llvm -std=c++1y -O1 -disable-llvm-passes -o - %s -DMSABI -w | FileCheck --check-prefix=MO1 --check-prefix=M18 %s +// RUN: %clang_cc1 -triple i686-windows-msvc -fno-rtti -fno-threadsafe-statics -fms-extensions -fms-compatibility-version=19.00 -emit-llvm -std=c++1y -O1 -disable-llvm-passes -o - %s -DMSABI -w | FileCheck --check-prefix=MO1 --check-prefix=M19 %s +// RUN: %clang_cc1 -triple i686-windows-gnu -fno-rtti -fno-threadsafe-statics -fms-extensions -emit-llvm -std=c++1y -O1 -fno-experimental-new-pass-manager -o - %s -w | FileCheck --check-prefix=GO1 %s // CHECK-NOT doesn't play nice with CHECK-DAG, so use separate run lines. -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-msvc -fno-rtti -fno-threadsafe-statics -fms-extensions -emit-llvm -std=c++1y -O0 -o - %s -DMSABI -w | FileCheck --check-prefix=MSC2 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple i686-windows-gnu -fno-rtti -fno-threadsafe-statics -fms-extensions -emit-llvm -std=c++1y -O0 -o - %s -w | FileCheck --check-prefix=GNU2 %s +// RUN: %clang_cc1 -triple i686-windows-msvc -fno-rtti -fno-threadsafe-statics -fms-extensions -emit-llvm -std=c++1y -O0 -o - %s -DMSABI -w | FileCheck --check-prefix=MSC2 %s +// RUN: %clang_cc1 -triple i686-windows-gnu -fno-rtti -fno-threadsafe-statics -fms-extensions -emit-llvm -std=c++1y -O0 -o - %s -w | FileCheck --check-prefix=GNU2 %s // Helper structs to make templates more expressive. struct ImplicitInst_Imported {}; diff --git a/clang/test/CodeGenCXX/eh.cpp b/clang/test/CodeGenCXX/eh.cpp index d96d32dbed5e65e4c6f3b8364cc5f4a25d86a330..a8592ad9fc4e7ea04ac61254d266239d8a974f7d 100644 --- a/clang/test/CodeGenCXX/eh.cpp +++ b/clang/test/CodeGenCXX/eh.cpp @@ -35,7 +35,7 @@ void test2() { // CHECK-NEXT: [[SELECTORVAR:%.*]] = alloca i32 // CHECK-NEXT: [[EXNOBJ:%.*]] = call i8* @__cxa_allocate_exception(i64 16) // CHECK-NEXT: [[EXN:%.*]] = bitcast i8* [[EXNOBJ]] to [[DSTAR:%[^*]*\*]] -// CHECK-NEXT: invoke void @_ZN7test2_DC1ERKS_([[DSTAR]] {{[^,]*}} [[EXN]], [[DSTAR]] noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) @d2) +// CHECK-NEXT: invoke void @_ZN7test2_DC1ERKS_([[DSTAR]] {{[^,]*}} [[EXN]], [[DSTAR]] nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) @d2) // CHECK-NEXT: to label %[[CONT:.*]] unwind label %{{.*}} // : [[CONT]]: (can't check this in Release-Asserts builds) // CHECK: call void @__cxa_throw(i8* [[EXNOBJ]], i8* bitcast ({{.*}}* @_ZTI7test2_D to i8*), i8* null) [[NR]] @@ -299,7 +299,7 @@ namespace test12 { // CHECK: [[CLEANUPDEST:%.*]] = alloca i32 A x; - // CHECK: invoke noundef zeroext i1 @_ZN6test126opaqueERKNS_1AE( + // CHECK: invoke zeroext i1 @_ZN6test126opaqueERKNS_1AE( if (opaque(x)) { A y; A z; @@ -388,7 +388,7 @@ namespace test15 { while (true) { // CHECK: load i32, i32* [[X]] - // CHECK-NEXT: [[COND:%.*]] = invoke noundef zeroext i1 @_ZN6test156opaqueEi + // CHECK-NEXT: [[COND:%.*]] = invoke zeroext i1 @_ZN6test156opaqueEi // CHECK: br i1 [[COND]] if (opaque(x)) // CHECK: br label @@ -420,7 +420,7 @@ namespace test16 { cond() ? throw B(A()) : foo(); - // CHECK-NEXT: [[COND:%.*]] = call noundef zeroext i1 @_ZN6test164condEv() + // CHECK-NEXT: [[COND:%.*]] = call zeroext i1 @_ZN6test164condEv() // CHECK-NEXT: store i1 false, i1* [[EXN_ACTIVE]] // CHECK-NEXT: store i1 false, i1* [[TEMP_ACTIVE]] // CHECK-NEXT: br i1 [[COND]], @@ -431,7 +431,7 @@ namespace test16 { // CHECK-NEXT: [[T0:%.*]] = bitcast i8* [[EXN]] to [[B:%.*]]* // CHECK-NEXT: invoke void @_ZN6test161AC1Ev([[A]]* {{[^,]*}} [[TEMP]]) // CHECK: store i1 true, i1* [[TEMP_ACTIVE]] - // CHECK-NEXT: invoke void @_ZN6test161BC1ERKNS_1AE([[B]]* {{[^,]*}} [[T0]], [[A]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[TEMP]]) + // CHECK-NEXT: invoke void @_ZN6test161BC1ERKNS_1AE([[B]]* {{[^,]*}} [[T0]], [[A]]* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[TEMP]]) // CHECK: store i1 false, i1* [[EXN_ACTIVE]] // CHECK-NEXT: invoke void @__cxa_throw(i8* [[EXN]], diff --git a/clang/test/CodeGenCXX/empty-nontrivially-copyable.cpp b/clang/test/CodeGenCXX/empty-nontrivially-copyable.cpp index 507c09a1952494f8ab3ce53631f4349e40d5c382..17dc2743500e0466509b85ce931b9f01beaf59e8 100644 --- a/clang/test/CodeGenCXX/empty-nontrivially-copyable.cpp +++ b/clang/test/CodeGenCXX/empty-nontrivially-copyable.cpp @@ -13,14 +13,14 @@ struct Empty { }; bool foo(Empty e) { -// CHECK: @_Z3foo5Empty(%struct.Empty* noundef %e) +// CHECK: @_Z3foo5Empty(%struct.Empty* %e) // CHECK: call {{.*}} @_ZN5Empty5checkEv(%struct.Empty* {{[^,]*}} %e) return e.check(); } void caller(Empty &e) { -// CHECK: @_Z6callerR5Empty(%struct.Empty* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %e) +// CHECK: @_Z6callerR5Empty(%struct.Empty* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %e) // CHECK: call {{.*}} @_ZN5EmptyC1ERKS_(%struct.Empty* {{[^,]*}} [[NEWTMP:%.*]], %struct.Empty* -// CHECK: call {{.*}} @_Z3foo5Empty(%struct.Empty* noundef [[NEWTMP]]) +// CHECK: call {{.*}} @_Z3foo5Empty(%struct.Empty* [[NEWTMP]]) foo(e); } diff --git a/clang/test/CodeGenCXX/exceptions-cxx-new.cpp b/clang/test/CodeGenCXX/exceptions-cxx-new.cpp index 47e5d580ae5e737bac66162f91b9036782a66600..4906a7b19098c80b6022c56c00d5446c8ba14134 100644 --- a/clang/test/CodeGenCXX/exceptions-cxx-new.cpp +++ b/clang/test/CodeGenCXX/exceptions-cxx-new.cpp @@ -13,7 +13,7 @@ void test_catch() { } // CHECK-LABEL: define dso_local void @"?test_catch@@YAXXZ"( -// CHECK: invoke noundef i32 @"?f@@YAHH@Z"(i32 noundef 1) +// CHECK: invoke i32 @"?f@@YAHH@Z"(i32 1) // CHECK: to label %[[NORMAL:.*]] unwind label %[[CATCHSWITCH:.*]] // CHECK: [[CATCHSWITCH]] @@ -21,7 +21,7 @@ void test_catch() { // CHECK: [[CATCH_INT]] // CHECK: %[[CATCHPAD_INT:.*]] = catchpad within %[[CATCHSWITCHPAD]] [%rtti.TypeDescriptor2* @"??_R0H@8", i32 0, i8* null] -// CHECK: call noundef i32 @"?f@@YAHH@Z"(i32 noundef 2) +// CHECK: call i32 @"?f@@YAHH@Z"(i32 2) // CHECK: catchret from %[[CATCHPAD_INT]] to label %[[LEAVE_INT_CATCH:.*]] // CHECK: [[LEAVE_INT_CATCH]] @@ -32,7 +32,7 @@ void test_catch() { // CHECK: [[CATCH_DOUBLE]] // CHECK: %[[CATCHPAD_DOUBLE:.*]] = catchpad within %[[CATCHSWITCHPAD]] [%rtti.TypeDescriptor2* @"??_R0N@8", i32 0, i8* null] -// CHECK: call noundef i32 @"?f@@YAHH@Z"(i32 noundef 3) +// CHECK: call i32 @"?f@@YAHH@Z"(i32 3) // CHECK: catchret from %[[CATCHPAD_DOUBLE]] to label %[[LEAVE_DOUBLE_CATCH:.*]] // CHECK: [[LEAVE_DOUBLE_CATCH]] @@ -51,7 +51,7 @@ void test_cleanup() { } // CHECK-LABEL: define dso_local {{.*}} @"?test_cleanup@@YAXXZ"( -// CHECK: invoke noundef i32 @"?f@@YAHH@Z"(i32 noundef 1) +// CHECK: invoke i32 @"?f@@YAHH@Z"(i32 1) // CHECK: to label %[[LEAVE_FUNC:.*]] unwind label %[[CLEANUP:.*]] // CHECK: [[LEAVE_FUNC]] @@ -65,7 +65,7 @@ void test_cleanup() { // CHECK-LABEL: define {{.*}} void @"??1Cleanup@@QAE@XZ"( -// CHECK: invoke noundef i32 @"?f@@YAHH@Z"(i32 noundef -1) +// CHECK: invoke i32 @"?f@@YAHH@Z"(i32 -1) // CHECK: to label %[[LEAVE_FUNC:.*]] unwind label %[[TERMINATE:.*]] // CHECK: [[LEAVE_FUNC]] diff --git a/clang/test/CodeGenCXX/exceptions-seh-filter-captures.cpp b/clang/test/CodeGenCXX/exceptions-seh-filter-captures.cpp index c16d92d390c35efb5905330dfd8dd599d92fd510..6b5c27097cbd0a2accd92856b3d2f051cf126705 100644 --- a/clang/test/CodeGenCXX/exceptions-seh-filter-captures.cpp +++ b/clang/test/CodeGenCXX/exceptions-seh-filter-captures.cpp @@ -13,13 +13,13 @@ extern "C" void test_freefunc(int p1) { } } -// CHECK-LABEL: define dso_local void @test_freefunc(i32 noundef %p1) +// CHECK-LABEL: define dso_local void @test_freefunc(i32 %p1) // CHECK: @llvm.localescape(i32* %[[p1_ptr:[^, ]*]], i32* %[[l1_ptr:[^, ]*]]) // CHECK: store i32 %p1, i32* %[[p1_ptr]], align 4 // CHECK: store i32 13, i32* %[[l1_ptr]], align 4 // CHECK: invoke void @might_crash() -// CHECK-LABEL: define internal noundef i32 @"?filt$0@0@test_freefunc@@"(i8* noundef %exception_pointers, i8* noundef %frame_pointer) +// CHECK-LABEL: define internal i32 @"?filt$0@0@test_freefunc@@"(i8* %exception_pointers, i8* %frame_pointer) // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.eh.recoverfp(i8* bitcast (void (i32)* @test_freefunc to i8*), i8* %frame_pointer) // CHECK: %[[p1_i8:[^ ]*]] = call i8* @llvm.localrecover(i8* bitcast (void (i32)* @test_freefunc to i8*), i8* %[[fp]], i32 0) // CHECK: %[[p1_ptr:[^ ]*]] = bitcast i8* %[[p1_i8]] to i32* @@ -28,7 +28,7 @@ extern "C" void test_freefunc(int p1) { // CHECK: %[[s1:[^ ]*]] = load i32, i32* @"?s1@?1??test_freefunc@@9@4HA", align 4 // CHECK: %[[l1:[^ ]*]] = load i32, i32* %[[l1_ptr]] // CHECK: %[[p1:[^ ]*]] = load i32, i32* %[[p1_ptr]] -// CHECK: call i32 (i32, ...) @basic_filter(i32 noundef %[[p1]], i32 noundef %[[l1]], i32 noundef %[[s1]]) +// CHECK: call i32 (i32, ...) @basic_filter(i32 %[[p1]], i32 %[[l1]], i32 %[[s1]]) struct S { int m1; @@ -49,7 +49,7 @@ void S::test_method() { // CHECK: store i32 13, i32* %[[l1_addr]], align 4 // CHECK: invoke void @might_crash() -// CHECK-LABEL: define internal noundef i32 @"?filt$0@0@test_method@S@@"(i8* noundef %exception_pointers, i8* noundef %frame_pointer) +// CHECK-LABEL: define internal i32 @"?filt$0@0@test_method@S@@"(i8* %exception_pointers, i8* %frame_pointer) // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.eh.recoverfp(i8* bitcast (void (%struct.S*)* @"?test_method@S@@QEAAXXZ" to i8*), i8* %frame_pointer) // CHECK: %[[l1_i8:[^ ]*]] = call i8* @llvm.localrecover(i8* bitcast (void (%struct.S*)* @"?test_method@S@@QEAAXXZ" to i8*), i8* %[[fp]], i32 0) // CHECK: %[[l1_ptr:[^ ]*]] = bitcast i8* %[[l1_i8]] to i32* @@ -59,7 +59,7 @@ void S::test_method() { // CHECK: %[[m1_ptr:[^ ]*]] = getelementptr inbounds %struct.S, %struct.S* %[[this]], i32 0, i32 0 // CHECK: %[[m1:[^ ]*]] = load i32, i32* %[[m1_ptr]] // CHECK: %[[l1:[^ ]*]] = load i32, i32* %[[l1_ptr]] -// CHECK: call i32 (i32, ...) @basic_filter(i32 noundef %[[l1]], i32 noundef %[[m1]]) +// CHECK: call i32 (i32, ...) @basic_filter(i32 %[[l1]], i32 %[[m1]]) struct V { void test_virtual(int p1); @@ -74,13 +74,13 @@ void V::test_virtual(int p1) { } } -// CHECK-LABEL: define dso_local void @"?test_virtual@V@@QEAAXH@Z"(%struct.V* {{[^,]*}} %this, i32 noundef %p1) +// CHECK-LABEL: define dso_local void @"?test_virtual@V@@QEAAXH@Z"(%struct.V* {{[^,]*}} %this, i32 %p1) // CHECK: @llvm.localescape(%struct.V** %[[this_addr:[^, ]*]], i32* %[[p1_addr:[^, ]*]]) // CHECK: store i32 %p1, i32* %[[p1_addr]], align 4 // CHECK: store %struct.V* %this, %struct.V** %[[this_addr]], align 8 // CHECK: invoke void @might_crash() -// CHECK-LABEL: define internal void @"?fin$0@0@test_virtual@V@@"(i8 noundef %abnormal_termination, i8* noundef %frame_pointer) +// CHECK-LABEL: define internal void @"?fin$0@0@test_virtual@V@@"(i8 %abnormal_termination, i8* %frame_pointer) // CHECK: %[[this_i8:[^ ]*]] = call i8* @llvm.localrecover(i8* bitcast (void (%struct.V*, i32)* @"?test_virtual@V@@QEAAXH@Z" to i8*), i8* %frame_pointer, i32 0) // CHECK: %[[this_ptr:[^ ]*]] = bitcast i8* %[[this_i8]] to %struct.V** // CHECK: %[[this:[^ ]*]] = load %struct.V*, %struct.V** %[[this_ptr]], align 8 @@ -91,7 +91,7 @@ void V::test_virtual(int p1) { // CHECK: %[[vtable:[^ ]*]] = load void (%struct.V*, i32)**, void (%struct.V*, i32)*** %[[this_2]], align 8 // CHECK: %[[vfn:[^ ]*]] = getelementptr inbounds void (%struct.V*, i32)*, void (%struct.V*, i32)** %[[vtable]], i64 0 // CHECK: %[[virt:[^ ]*]] = load void (%struct.V*, i32)*, void (%struct.V*, i32)** %[[vfn]], align 8 -// CHECK: call void %[[virt]](%struct.V* {{[^,]*}} %[[this]], i32 noundef %[[p1]]) +// CHECK: call void %[[virt]](%struct.V* {{[^,]*}} %[[this]], i32 %[[p1]]) void test_lambda() { int l1 = 13; @@ -111,7 +111,7 @@ void test_lambda() { // CHECK: store i32 42, i32* %[[l2_addr]], align 4 // CHECK: invoke void @might_crash() -// CHECK-LABEL: define internal noundef i32 @"?filt$0@0@?R@?0??test_lambda@@YAXXZ@"(i8* noundef %exception_pointers, i8* noundef %frame_pointer) +// CHECK-LABEL: define internal i32 @"?filt$0@0@?R@?0??test_lambda@@YAXXZ@"(i8* %exception_pointers, i8* %frame_pointer) // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.eh.recoverfp(i8* bitcast (void (%class.anon*)* @"??R@?0??test_lambda@@YAXXZ@QEBA@XZ" to i8*), i8* %frame_pointer) // CHECK: %[[this_i8:[^ ]*]] = call i8* @llvm.localrecover(i8* bitcast (void (%class.anon*)* @"??R@?0??test_lambda@@YAXXZ@QEBA@XZ" to i8*), i8* %[[fp]], i32 0) // CHECK: %[[this_ptr:[^ ]*]] = bitcast i8* %[[this_i8]] to %class.anon** @@ -122,7 +122,7 @@ void test_lambda() { // CHECK: %[[l1_ref_ptr:[^ ]*]] = getelementptr inbounds %class.anon, %class.anon* %[[this]], i32 0, i32 0 // CHECK: %[[l1_ref:[^ ]*]] = load i32*, i32** %[[l1_ref_ptr]] // CHECK: %[[l1:[^ ]*]] = load i32, i32* %[[l1_ref]] -// CHECK: call i32 (i32, ...) @basic_filter(i32 noundef %[[l1]], i32 noundef %[[l2]]) +// CHECK: call i32 (i32, ...) @basic_filter(i32 %[[l1]], i32 %[[l2]]) struct U { void this_in_lambda(); @@ -138,10 +138,10 @@ void U::this_in_lambda() { lambda(); } -// CHECK-LABEL: define internal noundef i32 @"?filt$0@0@?R@?0??this_in_lambda@U@@QEAAXXZ@"(i8* noundef %exception_pointers, i8* noundef %frame_pointer) +// CHECK-LABEL: define internal i32 @"?filt$0@0@?R@?0??this_in_lambda@U@@QEAAXXZ@"(i8* %exception_pointers, i8* %frame_pointer) // CHECK: %[[this_i8:[^ ]*]] = call i8* @llvm.localrecover(i8* bitcast (void (%class.anon.0*)* @"??R@?0??this_in_lambda@U@@QEAAXXZ@QEBA@XZ" to i8*), i8* %[[fp:[^ ]*]], i32 0) // CHECK: %[[this_ptr:[^ ]*]] = bitcast i8* %[[this_i8]] to %class.anon.0** // CHECK: %[[this:[^ ]*]] = load %class.anon.0*, %class.anon.0** %[[this_ptr]], align 8 // CHECK: %[[actual_this_ptr:[^ ]*]] = getelementptr inbounds %class.anon.0, %class.anon.0* %[[this]], i32 0, i32 0 // CHECK: %[[actual_this:[^ ]*]] = load %struct.U*, %struct.U** %[[actual_this_ptr]], align 8 -// CHECK: call i32 (i32, ...) @basic_filter(i32 noundef 0, %struct.U* noundef %[[actual_this]]) +// CHECK: call i32 (i32, ...) @basic_filter(i32 0, %struct.U* %[[actual_this]]) diff --git a/clang/test/CodeGenCXX/exceptions-seh-filter-uwtable.cpp b/clang/test/CodeGenCXX/exceptions-seh-filter-uwtable.cpp index 55ee1dfd3750718ddcb9bb2a00c7a2195fe1f06d..17fd01285d3c80eb618b894a4385a2412094c709 100644 --- a/clang/test/CodeGenCXX/exceptions-seh-filter-uwtable.cpp +++ b/clang/test/CodeGenCXX/exceptions-seh-filter-uwtable.cpp @@ -34,7 +34,7 @@ g aq(h j, g k, int, int) { } // Check for the uwtable attribute on the filter funclet. -// CHECK: define internal noundef i32 @"?filt$0@0@at@@"(i8* noundef %exception_pointers, i8* noundef %frame_pointer) #[[MD:[0-9]+]] +// CHECK: define internal i32 @"?filt$0@0@at@@"(i8* %exception_pointers, i8* %frame_pointer) #[[MD:[0-9]+]] // CHECK: attributes #[[MD]] = { nounwind uwtable void at() { diff --git a/clang/test/CodeGenCXX/exceptions-seh.cpp b/clang/test/CodeGenCXX/exceptions-seh.cpp index 3af157ec2c7c6073c22ac8920f07ad4538ac8ff0..42b76b1dcc5a9cd804f62a1bc3945f77ff3ed093 100644 --- a/clang/test/CodeGenCXX/exceptions-seh.cpp +++ b/clang/test/CodeGenCXX/exceptions-seh.cpp @@ -23,7 +23,7 @@ extern "C" void use_cxx() { // CXXEH-LABEL: define dso_local void @use_cxx() // CXXEH-SAME: personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) -// CXXEH: call noundef %struct.HasCleanup* @"??0HasCleanup@@QEAA@XZ"(%struct.HasCleanup* {{[^,]*}} %{{.*}}) +// CXXEH: call %struct.HasCleanup* @"??0HasCleanup@@QEAA@XZ"(%struct.HasCleanup* {{[^,]*}} %{{.*}}) // CXXEH: invoke void @might_throw() // CXXEH: to label %[[cont:[^ ]*]] unwind label %[[lpad:[^ ]*]] // @@ -38,7 +38,7 @@ extern "C" void use_cxx() { // NOCXX-LABEL: define dso_local void @use_cxx() // NOCXX-NOT: invoke -// NOCXX: call noundef %struct.HasCleanup* @"??0HasCleanup@@QEAA@XZ"(%struct.HasCleanup* {{[^,]*}} %{{.*}}) +// NOCXX: call %struct.HasCleanup* @"??0HasCleanup@@QEAA@XZ"(%struct.HasCleanup* {{[^,]*}} %{{.*}}) // NOCXX-NOT: invoke // NOCXX: call void @might_throw() // NOCXX-NOT: invoke @@ -90,12 +90,12 @@ extern "C" void nested_finally() { // CHECK-LABEL: define dso_local void @nested_finally() #{{[0-9]+}} // CHECK-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) // CHECK: invoke void @might_throw() -// CHECK: call void @"?fin$0@0@nested_finally@@"(i8 noundef 1, i8* {{.*}}) +// CHECK: call void @"?fin$0@0@nested_finally@@"(i8 1, i8* {{.*}}) // CHECK-LABEL: define internal void @"?fin$0@0@nested_finally@@" // CHECK-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) // CHECK: invoke void @might_throw() -// CHECK: call void @"?fin$1@0@nested_finally@@"(i8 noundef 1, i8* {{.*}}) +// CHECK: call void @"?fin$1@0@nested_finally@@"(i8 1, i8* {{.*}}) void use_seh_in_lambda() { ([]() { @@ -148,19 +148,19 @@ void use_inline() { // CHECK: invoke void @might_throw() // // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK: call void @"?fin$0@0@use_seh_in_inline_func@@"(i8 noundef 0, i8* noundef %[[fp]]) +// CHECK: call void @"?fin$0@0@use_seh_in_inline_func@@"(i8 0, i8* %[[fp]]) // CHECK: ret void // // CHECK: cleanuppad // CHECK: %[[fp:[^ ]*]] = call i8* @llvm.localaddress() -// CHECK: call void @"?fin$0@0@use_seh_in_inline_func@@"(i8 noundef 1, i8* noundef %[[fp]]) +// CHECK: call void @"?fin$0@0@use_seh_in_inline_func@@"(i8 1, i8* %[[fp]]) -// CHECK-LABEL: define internal noundef i32 @"?filt$0@0@use_seh_in_inline_func@@"(i8* noundef %exception_pointers, i8* noundef %frame_pointer) #{{[0-9]+}} +// CHECK-LABEL: define internal i32 @"?filt$0@0@use_seh_in_inline_func@@"(i8* %exception_pointers, i8* %frame_pointer) #{{[0-9]+}} // CHECK: icmp eq i32 %{{.*}}, 424242 // CHECK: zext i1 %{{.*}} to i32 // CHECK: ret i32 -// CHECK-LABEL: define internal void @"?fin$0@0@use_seh_in_inline_func@@"(i8 noundef %abnormal_termination, i8* noundef %frame_pointer) #{{[0-9]+}} +// CHECK-LABEL: define internal void @"?fin$0@0@use_seh_in_inline_func@@"(i8 %abnormal_termination, i8* %frame_pointer) #{{[0-9]+}} // CHECK: store i32 1234, i32* @my_unique_global // CHECK: attributes #[[NOINLINE]] = { {{.*noinline.*}} } diff --git a/clang/test/CodeGenCXX/exceptions.cpp b/clang/test/CodeGenCXX/exceptions.cpp index 256a7913985094c0d3a52f8c4f793a393491358d..c37fb5770c7e66352bfaa2add84be955be2d1c2b 100644 --- a/clang/test/CodeGenCXX/exceptions.cpp +++ b/clang/test/CodeGenCXX/exceptions.cpp @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -disable-noundef-analysis %s -triple=x86_64-linux-gnu -emit-llvm -std=c++98 -o - -fcxx-exceptions -fexceptions | FileCheck -check-prefix=CHECK -check-prefix=CHECK98 %s -// RUN: %clang_cc1 -disable-noundef-analysis %s -triple=x86_64-linux-gnu -emit-llvm -std=c++11 -o - -fcxx-exceptions -fexceptions | FileCheck -check-prefix=CHECK -check-prefix=CHECK11 %s +// RUN: %clang_cc1 %s -triple=x86_64-linux-gnu -emit-llvm -std=c++98 -o - -fcxx-exceptions -fexceptions | FileCheck -check-prefix=CHECK -check-prefix=CHECK98 %s +// RUN: %clang_cc1 %s -triple=x86_64-linux-gnu -emit-llvm -std=c++11 -o - -fcxx-exceptions -fexceptions | FileCheck -check-prefix=CHECK -check-prefix=CHECK11 %s // CHECK: %[[STRUCT_TEST13_A:.*]] = type { i32, i32 } diff --git a/clang/test/CodeGenCXX/explicit-instantiation.cpp b/clang/test/CodeGenCXX/explicit-instantiation.cpp index b7fe82f4db921f65e550826ec35cd311a074a785..07c5f7265acd608edcbb4b63bb514f3681f5552c 100644 --- a/clang/test/CodeGenCXX/explicit-instantiation.cpp +++ b/clang/test/CodeGenCXX/explicit-instantiation.cpp @@ -18,7 +18,7 @@ Result plus::operator()(const T& t, const U& u) const { return t + u; } -// CHECK-LABEL: define weak_odr noundef i32 @_ZNK4plusIillEclERKiRKl +// CHECK-LABEL: define weak_odr i32 @_ZNK4plusIillEclERKiRKl template struct plus; namespace EarlyInstantiation { @@ -38,10 +38,10 @@ namespace EarlyInstantiation { constexpr int c = S().constexpr_function(); int d = S().deduced_return_type(); - // CHECK: define weak_odr noundef i32 @_ZN18EarlyInstantiation1SIcE18constexpr_functionEv( - // CHECK: define weak_odr noundef i32 @_ZN18EarlyInstantiation1SIcE19deduced_return_typeEv( - // CHECK: define weak_odr noundef i32 @_ZN18EarlyInstantiation1SIiE18constexpr_functionEv( - // CHECK: define weak_odr noundef i32 @_ZN18EarlyInstantiation1SIiE19deduced_return_typeEv( + // CHECK: define weak_odr i32 @_ZN18EarlyInstantiation1SIcE18constexpr_functionEv( + // CHECK: define weak_odr i32 @_ZN18EarlyInstantiation1SIcE19deduced_return_typeEv( + // CHECK: define weak_odr i32 @_ZN18EarlyInstantiation1SIiE18constexpr_functionEv( + // CHECK: define weak_odr i32 @_ZN18EarlyInstantiation1SIiE19deduced_return_typeEv( template struct S; template struct S; @@ -59,10 +59,10 @@ namespace EarlyInstantiation { int h = deduced_return_type(); // The FIXMEs below are for PR19551. - // CHECK: define weak_odr noundef i32 @_ZN18EarlyInstantiation18constexpr_functionIcEEiv( - // FIXME: define weak_odr noundef i32 @_ZN18EarlyInstantiation19deduced_return_typeIcEEiv( - // CHECK: define weak_odr noundef i32 @_ZN18EarlyInstantiation18constexpr_functionIiEEiv( - // FIXME: define weak_odr noundef i32 @_ZN18EarlyInstantiation19deduced_return_typeIiEEiv( + // CHECK: define weak_odr i32 @_ZN18EarlyInstantiation18constexpr_functionIcEEiv( + // FIXME: define weak_odr i32 @_ZN18EarlyInstantiation19deduced_return_typeIcEEiv( + // CHECK: define weak_odr i32 @_ZN18EarlyInstantiation18constexpr_functionIiEEiv( + // FIXME: define weak_odr i32 @_ZN18EarlyInstantiation19deduced_return_typeIiEEiv( template int constexpr_function(); // FIXME template auto deduced_return_type(); template int constexpr_function(); @@ -86,12 +86,12 @@ namespace LateInstantiation { // Check that we declare, define, or provide an available-externally // definition as appropriate. - // CHECK: define linkonce_odr noundef i32 @_ZN17LateInstantiation1SIcE1fEv( - // CHECK: define linkonce_odr noundef i32 @_ZN17LateInstantiation1fIcEEiv( - // CHECK-NO-OPT: declare noundef i32 @_ZN17LateInstantiation1SIiE1fEv( - // CHECK-NO-OPT: declare noundef i32 @_ZN17LateInstantiation1fIiEEiv( - // CHECK-OPT: define available_externally noundef i32 @_ZN17LateInstantiation1SIiE1fEv( - // CHECK-OPT: define available_externally noundef i32 @_ZN17LateInstantiation1fIiEEiv( + // CHECK: define linkonce_odr i32 @_ZN17LateInstantiation1SIcE1fEv( + // CHECK: define linkonce_odr i32 @_ZN17LateInstantiation1fIcEEiv( + // CHECK-NO-OPT: declare i32 @_ZN17LateInstantiation1SIiE1fEv( + // CHECK-NO-OPT: declare i32 @_ZN17LateInstantiation1fIiEEiv( + // CHECK-OPT: define available_externally i32 @_ZN17LateInstantiation1SIiE1fEv( + // CHECK-OPT: define available_externally i32 @_ZN17LateInstantiation1fIiEEiv( } namespace PR21718 { @@ -100,7 +100,7 @@ namespace PR21718 { // same function twice. template struct S { -// CHECK-LABEL: define weak_odr noundef i32 @_ZN7PR217181SIiE1fEv +// CHECK-LABEL: define weak_odr i32 @_ZN7PR217181SIiE1fEv __attribute__((used)) constexpr int f() { return 0; } }; int g() { return S().f(); } diff --git a/clang/test/CodeGenCXX/ext-int.cpp b/clang/test/CodeGenCXX/ext-int.cpp index 6880c86731655ab2fd07e8915235222cba45f425..3cbcf1331eaff1e3e51c04253a1b9f795f333131 100644 --- a/clang/test/CodeGenCXX/ext-int.cpp +++ b/clang/test/CodeGenCXX/ext-int.cpp @@ -1,8 +1,8 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-gnu-linux -O3 -disable-llvm-passes -I%S -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,LIN,NoNewStructPathTBAA -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-gnu-linux -O3 -disable-llvm-passes -I%S -new-struct-path-tbaa -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,LIN,NewStructPathTBAA +// RUN: %clang_cc1 -triple x86_64-gnu-linux -O3 -disable-llvm-passes -I%S -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,LIN,NoNewStructPathTBAA +// RUN: %clang_cc1 -triple x86_64-gnu-linux -O3 -disable-llvm-passes -I%S -new-struct-path-tbaa -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,LIN,NewStructPathTBAA -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-windows-pc -O3 -disable-llvm-passes -I%S -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,WIN,NoNewStructPathTBAA -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-windows-pc -O3 -disable-llvm-passes -I%S -new-struct-path-tbaa -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,WIN,NewStructPathTBAA +// RUN: %clang_cc1 -triple x86_64-windows-pc -O3 -disable-llvm-passes -I%S -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,WIN,NoNewStructPathTBAA +// RUN: %clang_cc1 -triple x86_64-windows-pc -O3 -disable-llvm-passes -I%S -new-struct-path-tbaa -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,WIN,NewStructPathTBAA #include diff --git a/clang/test/CodeGenCXX/fastcall.cpp b/clang/test/CodeGenCXX/fastcall.cpp index 4a30c67893597b8374777690bd40a0a1e69e0aa7..bd3bba1da16283654f497c81eedde85793210bb6 100644 --- a/clang/test/CodeGenCXX/fastcall.cpp +++ b/clang/test/CodeGenCXX/fastcall.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple i386-unknown-unknown -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple i386-unknown-unknown -emit-llvm -o - %s | FileCheck %s void __attribute__((fastcall)) foo1(int &y); void bar1(int &y) { diff --git a/clang/test/CodeGenCXX/float128-declarations.cpp b/clang/test/CodeGenCXX/float128-declarations.cpp index ba8c346541fc0888af8a37dc1c0f6f1798fdda5b..8d8c465a63a100dd2fc0cfdeaf00e84564c73109 100644 --- a/clang/test/CodeGenCXX/float128-declarations.cpp +++ b/clang/test/CodeGenCXX/float128-declarations.cpp @@ -84,15 +84,15 @@ int main(void) { // CHECK-DAG: @_ZN12_GLOBAL__N_13f2nE = internal global fp128 0xL00000000000000004004080000000000 // CHECK-DAG: @_ZN12_GLOBAL__N_15arr1nE = internal global [10 x fp128] // CHECK-DAG: @_ZN12_GLOBAL__N_15arr2nE = internal global [3 x fp128] [fp128 0xL33333333333333333FFF333333333333, fp128 0xL00000000000000004000800000000000, fp128 0xL00000000000000004025176592E00000] -// CHECK-DAG: define internal noundef fp128 @_ZN12_GLOBAL__N_16func1nERKu9__ieee128(fp128* +// CHECK-DAG: define internal fp128 @_ZN12_GLOBAL__N_16func1nERKu9__ieee128(fp128* // CHECK-DAG: @f1f ={{.*}} global fp128 0xL00000000000000000000000000000000 // CHECK-DAG: @f2f ={{.*}} global fp128 0xL33333333333333334004033333333333 // CHECK-DAG: @arr1f ={{.*}} global [10 x fp128] // CHECK-DAG: @arr2f ={{.*}} global [3 x fp128] [fp128 0xL3333333333333333BFFF333333333333, fp128 0xL0000000000000000C000800000000000, fp128 0xL0000000000000000C025176592E00000] -// CHECK-DAG: declare noundef fp128 @_Z6func1fu9__ieee128(fp128 noundef) -// CHECK-DAG: define linkonce_odr void @_ZN2C1C2Eu9__ieee128(%class.C1* {{[^,]*}} %this, fp128 noundef %arg) -// CHECK-DAG: define linkonce_odr noundef fp128 @_ZN2C16func2cEu9__ieee128(fp128 noundef %arg) -// CHECK-DAG: define linkonce_odr noundef fp128 @_Z6func1tIu9__ieee128ET_S0_(fp128 noundef %arg) +// CHECK-DAG: declare fp128 @_Z6func1fu9__ieee128(fp128) +// CHECK-DAG: define linkonce_odr void @_ZN2C1C2Eu9__ieee128(%class.C1* {{[^,]*}} %this, fp128 %arg) +// CHECK-DAG: define linkonce_odr fp128 @_ZN2C16func2cEu9__ieee128(fp128 %arg) +// CHECK-DAG: define linkonce_odr fp128 @_Z6func1tIu9__ieee128ET_S0_(fp128 %arg) // CHECK-DAG: @__const.main.s1 = private unnamed_addr constant %struct.S1 { fp128 0xL00000000000000004006080000000000 } // CHECK-DAG: store fp128 0xLF0AFD0EBFF292DCE42E0B38CDD83F26F, fp128* %f1l, align 16 // CHECK-DAG: store fp128 0xL00000000000000008000000000000000, fp128* %f2l, align 16 @@ -106,15 +106,15 @@ int main(void) { // CHECK-X86-DAG: @_ZN12_GLOBAL__N_13f2nE = internal global fp128 0xL00000000000000004004080000000000 // CHECK-X86-DAG: @_ZN12_GLOBAL__N_15arr1nE = internal global [10 x fp128] // CHECK-X86-DAG: @_ZN12_GLOBAL__N_15arr2nE = internal global [3 x fp128] [fp128 0xL33333333333333333FFF333333333333, fp128 0xL00000000000000004000800000000000, fp128 0xL00000000000000004025176592E00000] -// CHECK-X86-DAG: define internal noundef fp128 @_ZN12_GLOBAL__N_16func1nERKg(fp128* +// CHECK-X86-DAG: define internal fp128 @_ZN12_GLOBAL__N_16func1nERKg(fp128* // CHECK-X86-DAG: @f1f ={{.*}} global fp128 0xL00000000000000000000000000000000 // CHECK-X86-DAG: @f2f ={{.*}} global fp128 0xL33333333333333334004033333333333 // CHECK-X86-DAG: @arr1f ={{.*}} global [10 x fp128] // CHECK-X86-DAG: @arr2f ={{.*}} global [3 x fp128] [fp128 0xL3333333333333333BFFF333333333333, fp128 0xL0000000000000000C000800000000000, fp128 0xL0000000000000000C025176592E00000] -// CHECK-X86-DAG: declare noundef fp128 @_Z6func1fg(fp128 noundef) -// CHECK-X86-DAG: define linkonce_odr void @_ZN2C1C2Eg(%class.C1* {{[^,]*}} %this, fp128 noundef %arg) -// CHECK-X86-DAG: define linkonce_odr noundef fp128 @_ZN2C16func2cEg(fp128 noundef %arg) -// CHECK-X86-DAG: define linkonce_odr noundef fp128 @_Z6func1tIgET_S0_(fp128 noundef %arg) +// CHECK-X86-DAG: declare fp128 @_Z6func1fg(fp128) +// CHECK-X86-DAG: define linkonce_odr void @_ZN2C1C2Eg(%class.C1* {{[^,]*}} %this, fp128 %arg) +// CHECK-X86-DAG: define linkonce_odr fp128 @_ZN2C16func2cEg(fp128 %arg) +// CHECK-X86-DAG: define linkonce_odr fp128 @_Z6func1tIgET_S0_(fp128 %arg) // CHECK-X86-DAG: @__const.main.s1 = private unnamed_addr constant %struct.S1 { fp128 0xL00000000000000004006080000000000 } // CHECK-X86-DAG: store fp128 0xLF0AFD0EBFF292DCE42E0B38CDD83F26F, fp128* %f1l, align 16 // CHECK-X86-DAG: store fp128 0xL00000000000000008000000000000000, fp128* %f2l, align 16 diff --git a/clang/test/CodeGenCXX/float16-declarations.cpp b/clang/test/CodeGenCXX/float16-declarations.cpp index ca9e518b47bc73eabd55fa3c7d27cb697663b4a2..ce899724eafd94f5a5c2d00697a8b4d7b6863ed1 100644 --- a/clang/test/CodeGenCXX/float16-declarations.cpp +++ b/clang/test/CodeGenCXX/float16-declarations.cpp @@ -59,12 +59,12 @@ public: _Float16 func1c(_Float16 arg ) { return f1c + arg; } -// CHECK-DAG: define linkonce_odr dso_local noundef half @_ZN2C16func1cEDF16_(%class.C1*{{.*}}, half{{.*}}) +// CHECK-DAG: define linkonce_odr dso_local half @_ZN2C16func1cEDF16_(%class.C1*{{.*}}, half{{.*}}) static _Float16 func2c(_Float16 arg) { return arg * C1::f2c; } -// CHECK-DAG: define linkonce_odr dso_local noundef half @_ZN2C16func2cEDF16_(half{{.*}}) +// CHECK-DAG: define linkonce_odr dso_local half @_ZN2C16func2cEDF16_(half{{.*}}) }; /* Template */ @@ -72,7 +72,7 @@ public: template C func1t(C arg) { return arg * 2.f16; } -// CHECK-DAG: define linkonce_odr dso_local noundef half @_Z6func1tIDF16_ET_S0_(half{{.*}}) +// CHECK-DAG: define linkonce_odr dso_local half @_Z6func1tIDF16_ET_S0_(half{{.*}}) template struct S1 { C mem1; @@ -99,7 +99,7 @@ int main(void) { C1 c1(f1l); // CHECK-DAG: [[F1L:%[a-z0-9]+]] = load half, half* %{{.*}}, align 2 -// CHECK-DAG: call void @_ZN2C1C2EDF16_(%class.C1* {{[^,]*}} %{{.*}}, half noundef %{{.*}}) +// CHECK-DAG: call void @_ZN2C1C2EDF16_(%class.C1* {{[^,]*}} %{{.*}}, half %{{.*}}) S1<_Float16> s1 = { 132.f16 }; // CHECK-DAG: @__const.main.s1 = private unnamed_addr constant %struct.S1 { half 0xH5820 }, align 2 diff --git a/clang/test/CodeGenCXX/for-cond-var.cpp b/clang/test/CodeGenCXX/for-cond-var.cpp index 25279181903a206f11116d192bfe14c85b330d95..60e54d4141f729d5a44f29379378ed3aa43339a0 100644 --- a/clang/test/CodeGenCXX/for-cond-var.cpp +++ b/clang/test/CodeGenCXX/for-cond-var.cpp @@ -18,7 +18,7 @@ void f(int); // CHECK: define {{.*}} void @_Z7PR49585v( void PR49585() { for ( - // CHECK: call void @_Z1fi(i32 noundef 1) + // CHECK: call void @_Z1fi(i32 1) // CHECK: br label %[[for_cond:.*]] f(1); @@ -38,20 +38,20 @@ void PR49585() { // CHECK: br i1 {{.*}}, label %[[if_then:.*]], label %[[if_end:.*]] if (cond()) { // CHECK: [[if_then]]: - // CHECK: call {{.*}} @_Z1fi(i32 noundef 3) + // CHECK: call {{.*}} @_Z1fi(i32 3) // CHECK: br label %[[for_inc:.*]] f(3); continue; } // CHECK: [[if_end]]: - // CHECK: call {{.*}} @_Z1fi(i32 noundef 4) + // CHECK: call {{.*}} @_Z1fi(i32 4) // CHECK: br label %[[for_inc]] f(4); } // CHECK: [[for_inc]]: - // CHECK: call void @_Z1fi(i32 noundef 2) + // CHECK: call void @_Z1fi(i32 2) // CHECK: store // CHECK: br label %[[cleanup]] @@ -72,7 +72,7 @@ void PR49585() { // CHECK: define {{.*}} void @_Z13PR49585_breakv( void PR49585_break() { for ( - // CHECK: call void @_Z1fi(i32 noundef 1) + // CHECK: call void @_Z1fi(i32 1) // CHECK: br label %[[for_cond:.*]] f(1); @@ -92,7 +92,7 @@ void PR49585_break() { // CHECK: br i1 {{.*}}, label %[[if_then:.*]], label %[[if_end:.*]] if (cond()) { // CHECK: [[if_then]]: - // CHECK: call {{.*}} @_Z1fi(i32 noundef 3) + // CHECK: call {{.*}} @_Z1fi(i32 3) // CHECK: store // CHECK: br label %[[cleanup:.*]] f(3); @@ -100,13 +100,13 @@ void PR49585_break() { } // CHECK: [[if_end]]: - // CHECK: call {{.*}} @_Z1fi(i32 noundef 4) + // CHECK: call {{.*}} @_Z1fi(i32 4) // CHECK: br label %[[for_inc]] f(4); } // CHECK: [[for_inc]]: - // CHECK: call void @_Z1fi(i32 noundef 2) + // CHECK: call void @_Z1fi(i32 2) // CHECK: store // CHECK: br label %[[cleanup]] diff --git a/clang/test/CodeGenCXX/for-range-temporaries.cpp b/clang/test/CodeGenCXX/for-range-temporaries.cpp index 5a42854eca40fb3517031e5b6310513f55725656..a03bb0a8152727af21b1236e4e451ca0a8d6aaff 100644 --- a/clang/test/CodeGenCXX/for-range-temporaries.cpp +++ b/clang/test/CodeGenCXX/for-range-temporaries.cpp @@ -115,7 +115,7 @@ template void for_temps(); // CHECK: [[COND]]: // CHECK: call void @_ZN1EneERKS_( -// CHECK: %[[CMP:.*]] = call noundef zeroext i1 @_ZN1HcvbEv( +// CHECK: %[[CMP:.*]] = call zeroext i1 @_ZN1HcvbEv( // CHECK: call void @_ZN1HD1Ev( // CHECK: br i1 %[[CMP]], label %[[BODY:.*]], label %[[CLEANUP:.*]] diff --git a/clang/test/CodeGenCXX/for-range.cpp b/clang/test/CodeGenCXX/for-range.cpp index e1f384a24ddd65d62f665f91949372693c8d9711..98265074adf71918ee02b5f1ce0ce27dc457325d 100644 --- a/clang/test/CodeGenCXX/for-range.cpp +++ b/clang/test/CodeGenCXX/for-range.cpp @@ -34,7 +34,7 @@ extern B array[5]; // CHECK-LABEL: define{{.*}} void @_Z9for_arrayv( void for_array() { - // CHECK: call void @_ZN1AC1Ev(%struct.A* noundef [[A:.*]]) + // CHECK: call void @_ZN1AC1Ev(%struct.A* [[A:.*]]) A a; for (B b : array) { // CHECK-NOT: 5begin @@ -57,18 +57,18 @@ void for_array() { // CHECK: br label %[[COND]] } // CHECK: [[END]]: - // CHECK: call void @_ZN1AD1Ev(%struct.A* noundef [[A]]) + // CHECK: call void @_ZN1AD1Ev(%struct.A* [[A]]) // CHECK: ret void } // CHECK-LABEL: define{{.*}} void @_Z9for_rangev( void for_range() { - // CHECK: call void @_ZN1AC1Ev(%struct.A* noundef [[A:.*]]) + // CHECK: call void @_ZN1AC1Ev(%struct.A* [[A:.*]]) A a; for (B b : C()) { // CHECK: call void @_ZN1CC1Ev( - // CHECK: = call noundef %struct.B* @_Z5beginR1C( - // CHECK: = call noundef %struct.B* @_Z3endR1C( + // CHECK: = call %struct.B* @_Z5beginR1C( + // CHECK: = call %struct.B* @_Z3endR1C( // CHECK: br label %[[COND:.*]] // CHECK: [[COND]]: @@ -89,18 +89,18 @@ void for_range() { // CHECK: br label %[[COND]] } // CHECK: [[END]]: - // CHECK: call void @_ZN1AD1Ev(%struct.A* noundef [[A]]) + // CHECK: call void @_ZN1AD1Ev(%struct.A* [[A]]) // CHECK: ret void } // CHECK-LABEL: define{{.*}} void @_Z16for_member_rangev( void for_member_range() { - // CHECK: call void @_ZN1AC1Ev(%struct.A* noundef [[A:.*]]) + // CHECK: call void @_ZN1AC1Ev(%struct.A* [[A:.*]]) A a; for (B b : D()) { // CHECK: call void @_ZN1DC1Ev( - // CHECK: = call noundef %struct.B* @_ZN1D5beginEv( - // CHECK: = call noundef %struct.B* @_ZN1D3endEv( + // CHECK: = call %struct.B* @_ZN1D5beginEv( + // CHECK: = call %struct.B* @_ZN1D3endEv( // CHECK: br label %[[COND:.*]] // CHECK: [[COND]]: @@ -121,6 +121,6 @@ void for_member_range() { // CHECK: br label %[[COND]] } // CHECK: [[END]]: - // CHECK: call void @_ZN1AD1Ev(%struct.A* noundef [[A]]) + // CHECK: call void @_ZN1AD1Ev(%struct.A* [[A]]) // CHECK: ret void } diff --git a/clang/test/CodeGenCXX/forward-enum.cpp b/clang/test/CodeGenCXX/forward-enum.cpp index 9d6a6186e255d30c154c0628e9dec4aa4590078c..0d2ff8e7d11f9ef3da3233a3d5aa2ceb536bd3f6 100644 --- a/clang/test/CodeGenCXX/forward-enum.cpp +++ b/clang/test/CodeGenCXX/forward-enum.cpp @@ -6,6 +6,6 @@ void bar(MyEnum value) { } // CHECK-LABEL: define{{.*}} void @_Z3foo6MyEnum void foo(MyEnum value) { - // CHECK: call void @_Z3bar6MyEnum(i8 noundef signext + // CHECK: call void @_Z3bar6MyEnum(i8 signext bar(value); } diff --git a/clang/test/CodeGenCXX/fp16-mangle-arg-return.cpp b/clang/test/CodeGenCXX/fp16-mangle-arg-return.cpp index fe0ebb2f8aa9f3feb4ffa419c759d710e2bea1c7..15214e13ad8a795e15777e99ef3383690470339a 100644 --- a/clang/test/CodeGenCXX/fp16-mangle-arg-return.cpp +++ b/clang/test/CodeGenCXX/fp16-mangle-arg-return.cpp @@ -4,7 +4,7 @@ // Test name-mangling of __fp16 passed directly as a function argument // (when that is permitted). -// CHECK: define {{.*}}void @_Z13fp16_argumentDh(half noundef %{{.*}}) +// CHECK: define {{.*}}void @_Z13fp16_argumentDh(half %{{.*}}) void fp16_argument(__fp16 arg) {} // Test name-mangling of __fp16 as a return type. The return type of @@ -12,5 +12,5 @@ void fp16_argument(__fp16 arg) {} // this, we have to pass it a function pointer and make __fp16 the // return type of that. -// CHECK: define {{.*}}void @_Z11fp16_returnPFDhvE(half ()* noundef %{{.*}}) +// CHECK: define {{.*}}void @_Z11fp16_returnPFDhvE(half ()* %{{.*}}) void fp16_return(__fp16 (*func)(void)) {} diff --git a/clang/test/CodeGenCXX/fp16-mangle.cpp b/clang/test/CodeGenCXX/fp16-mangle.cpp index 4ca953b35e2dbf5dce79aef8e867d8a0143e473e..4157733df77a81d5e7577d79ba298ceea47b5778 100644 --- a/clang/test/CodeGenCXX/fp16-mangle.cpp +++ b/clang/test/CodeGenCXX/fp16-mangle.cpp @@ -4,9 +4,9 @@ template struct S { static int i; }; template <> int S<__fp16, __fp16>::i = 3; -// CHECK-LABEL: define{{.*}} void @_Z1fPDh(half* noundef %x) +// CHECK-LABEL: define{{.*}} void @_Z1fPDh(half* %x) void f (__fp16 *x) { } -// CHECK-LABEL: define{{.*}} void @_Z1gPDhS_(half* noundef %x, half* noundef %y) +// CHECK-LABEL: define{{.*}} void @_Z1gPDhS_(half* %x, half* %y) void g (__fp16 *x, __fp16 *y) { } diff --git a/clang/test/CodeGenCXX/fp16-overload.cpp b/clang/test/CodeGenCXX/fp16-overload.cpp index 935ea79c86bbcb4ea5b5f137c846a05a9c5d13d9..75622109c175914da29f198cc10113a9110aaa35 100644 --- a/clang/test/CodeGenCXX/fp16-overload.cpp +++ b/clang/test/CodeGenCXX/fp16-overload.cpp @@ -5,6 +5,6 @@ extern int foo(double x); __fp16 a; -// CHECK: call noundef i32 @_Z3foof -// CHECK-NOT: call noundef i32 @_Z3food +// CHECK: call i32 @_Z3foof +// CHECK-NOT: call i32 @_Z3food int bar (void) { return foo(a); } diff --git a/clang/test/CodeGenCXX/global-init.cpp b/clang/test/CodeGenCXX/global-init.cpp index b95fde03aec9b6b820aa1f200fc0583b67e08f89..f84ca3976324eb5bdad578737da4b5bae40896ab 100644 --- a/clang/test/CodeGenCXX/global-init.cpp +++ b/clang/test/CodeGenCXX/global-init.cpp @@ -79,7 +79,7 @@ namespace test4 { // This needs an initialization function and guard variables. // CHECK: load i8, i8* bitcast (i64* @_ZGVN5test41xE to i8*) - // CHECK: [[CALL:%.*]] = call noundef i32 @_ZN5test43fooEv + // CHECK: [[CALL:%.*]] = call i32 @_ZN5test43fooEv // CHECK-NEXT: store i32 [[CALL]], i32* @_ZN5test41xE // CHECK-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN5test41xE to i8*) __attribute__((weak)) int x = foo(); diff --git a/clang/test/CodeGenCXX/goto.cpp b/clang/test/CodeGenCXX/goto.cpp index 6a7844ef1f45b0a07f687b1951bea3bd5eb63140..33f20a48060234303545c4c9efebe7f93f281e1b 100644 --- a/clang/test/CodeGenCXX/goto.cpp +++ b/clang/test/CodeGenCXX/goto.cpp @@ -6,7 +6,7 @@ namespace test0 { struct A { A(); ~A(); }; struct V { V(const A &a = A()); ~V(); }; - // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN5test04testILi0EEEii + // CHECK-LABEL: define linkonce_odr i32 @_ZN5test04testILi0EEEii template int test(int x) { // CHECK: [[RET:%.*]] = alloca i32 // CHECK-NEXT: [[X:%.*]] = alloca i32 @@ -19,11 +19,11 @@ namespace test0 { // CHECK-NEXT: [[CLEANUPACTIVE:%.*]] = alloca i1 // CHECK: call void @_ZN5test01AC1Ev([[A]]* {{[^,]*}} [[Y]]) // CHECK-NEXT: invoke void @_ZN5test01AC1Ev([[A]]* {{[^,]*}} [[Z]]) - // CHECK: [[NEW:%.*]] = invoke noalias noundef nonnull i8* @_Znwm(i64 noundef 1) + // CHECK: [[NEW:%.*]] = invoke noalias nonnull i8* @_Znwm(i64 1) // CHECK: store i1 true, i1* [[CLEANUPACTIVE]] // CHECK: [[NEWCAST:%.*]] = bitcast i8* [[NEW]] to [[V]]* // CHECK-NEXT: invoke void @_ZN5test01AC1Ev([[A]]* {{[^,]*}} [[TMP]]) - // CHECK: invoke void @_ZN5test01VC1ERKNS_1AE([[V]]* {{[^,]*}} [[NEWCAST]], [[A]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[TMP]]) + // CHECK: invoke void @_ZN5test01VC1ERKNS_1AE([[V]]* {{[^,]*}} [[NEWCAST]], [[A]]* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[TMP]]) // CHECK: store i1 false, i1* [[CLEANUPACTIVE]] // CHECK98-NEXT: invoke void @_ZN5test01AD1Ev([[A]]* {{[^,]*}} [[TMP]]) diff --git a/clang/test/CodeGenCXX/homogeneous-aggregates.cpp b/clang/test/CodeGenCXX/homogeneous-aggregates.cpp index 4dac989f70ae1680cd7b29c44334d7a952c3eac3..0fa30b2663bfc4a8f21d4360e349f2c48b090dbf 100644 --- a/clang/test/CodeGenCXX/homogeneous-aggregates.cpp +++ b/clang/test/CodeGenCXX/homogeneous-aggregates.cpp @@ -41,8 +41,8 @@ struct D5 : I1, I2, I3 {}; // homogeneous aggregate // PPC: define{{.*}} void @_Z7func_D12D1(%struct.D1* noalias sret(%struct.D1) align 8 %agg.result, [3 x i64] %x.coerce) // ARM32: define{{.*}} arm_aapcs_vfpcc void @_Z7func_D12D1(%struct.D1* noalias sret(%struct.D1) align 8 %agg.result, [3 x i64] %x.coerce) -// ARM64: define{{.*}} void @_Z7func_D12D1(%struct.D1* noalias sret(%struct.D1) align 8 %agg.result, %struct.D1* noundef %x) -// X64: define dso_local x86_vectorcallcc void @"\01_Z7func_D12D1@@24"(%struct.D1* noalias sret(%struct.D1) align 8 %agg.result, %struct.D1* noundef %x) +// ARM64: define{{.*}} void @_Z7func_D12D1(%struct.D1* noalias sret(%struct.D1) align 8 %agg.result, %struct.D1* %x) +// X64: define dso_local x86_vectorcallcc void @"\01_Z7func_D12D1@@24"(%struct.D1* noalias sret(%struct.D1) align 8 %agg.result, %struct.D1* %x) D1 CC func_D1(D1 x) { return x; } // PPC: define{{.*}} [3 x double] @_Z7func_D22D2([3 x double] %x.coerce) @@ -53,7 +53,7 @@ D2 CC func_D2(D2 x) { return x; } // PPC: define{{.*}} void @_Z7func_D32D3(%struct.D3* noalias sret(%struct.D3) align 8 %agg.result, [4 x i64] %x.coerce) // ARM32: define{{.*}} arm_aapcs_vfpcc void @_Z7func_D32D3(%struct.D3* noalias sret(%struct.D3) align 8 %agg.result, [4 x i64] %x.coerce) -// ARM64: define{{.*}} void @_Z7func_D32D3(%struct.D3* noalias sret(%struct.D3) align 8 %agg.result, %struct.D3* noundef %x) +// ARM64: define{{.*}} void @_Z7func_D32D3(%struct.D3* noalias sret(%struct.D3) align 8 %agg.result, %struct.D3* %x) D3 CC func_D3(D3 x) { return x; } // PPC: define{{.*}} [4 x double] @_Z7func_D42D4([4 x double] %x.coerce) @@ -78,7 +78,7 @@ void call_D5(D5 *p) { // Check the call site. // -// ARM64-LABEL: define{{.*}} void @_Z7call_D5P2D5(%struct.D5* noundef %p) +// ARM64-LABEL: define{{.*}} void @_Z7call_D5P2D5(%struct.D5* %p) // ARM64: load [3 x double], [3 x double]* // ARM64: call %struct.D5 @_Z7func_D52D5([3 x double] %{{.*}}) @@ -132,44 +132,44 @@ struct HasEmptyBase : public Empty { double b[2]; }; struct HasPodBase : public Pod {}; -// WOA64-LABEL: define dso_local %"struct.pr47611::Pod" @"?copy@pr47611@@YA?AUPod@1@PEAU21@@Z"(%"struct.pr47611::Pod"* noundef %x) +// WOA64-LABEL: define dso_local %"struct.pr47611::Pod" @"?copy@pr47611@@YA?AUPod@1@PEAU21@@Z"(%"struct.pr47611::Pod"* %x) Pod copy(Pod *x) { return *x; } // MSVC: ldp d0,d1,[x0], Clang: ldp d0,d1,[x0] -// WOA64-LABEL: define dso_local void @"?copy@pr47611@@YA?AUNotCXX14Aggregate@1@PEAU21@@Z"(%"struct.pr47611::NotCXX14Aggregate"* inreg noalias sret(%"struct.pr47611::NotCXX14Aggregate") align 8 %agg.result, %"struct.pr47611::NotCXX14Aggregate"* noundef %x) +// WOA64-LABEL: define dso_local void @"?copy@pr47611@@YA?AUNotCXX14Aggregate@1@PEAU21@@Z"(%"struct.pr47611::NotCXX14Aggregate"* inreg noalias sret(%"struct.pr47611::NotCXX14Aggregate") align 8 %agg.result, %"struct.pr47611::NotCXX14Aggregate"* %x) NotCXX14Aggregate copy(NotCXX14Aggregate *x) { return *x; } // MSVC: stp x8,x9,[x0], Clang: str q0,[x0] -// WOA64-LABEL: define dso_local [2 x i64] @"?copy@pr47611@@YA?AUNotPod@1@PEAU21@@Z"(%"struct.pr47611::NotPod"* noundef %x) +// WOA64-LABEL: define dso_local [2 x i64] @"?copy@pr47611@@YA?AUNotPod@1@PEAU21@@Z"(%"struct.pr47611::NotPod"* %x) NotPod copy(NotPod *x) { return *x; } -// WOA64-LABEL: define dso_local void @"?copy@pr47611@@YA?AUHasEmptyBase@1@PEAU21@@Z"(%"struct.pr47611::HasEmptyBase"* inreg noalias sret(%"struct.pr47611::HasEmptyBase") align 8 %agg.result, %"struct.pr47611::HasEmptyBase"* noundef %x) +// WOA64-LABEL: define dso_local void @"?copy@pr47611@@YA?AUHasEmptyBase@1@PEAU21@@Z"(%"struct.pr47611::HasEmptyBase"* inreg noalias sret(%"struct.pr47611::HasEmptyBase") align 8 %agg.result, %"struct.pr47611::HasEmptyBase"* %x) HasEmptyBase copy(HasEmptyBase *x) { return *x; } -// WOA64-LABEL: define dso_local void @"?copy@pr47611@@YA?AUHasPodBase@1@PEAU21@@Z"(%"struct.pr47611::HasPodBase"* inreg noalias sret(%"struct.pr47611::HasPodBase") align 8 %agg.result, %"struct.pr47611::HasPodBase"* noundef %x) +// WOA64-LABEL: define dso_local void @"?copy@pr47611@@YA?AUHasPodBase@1@PEAU21@@Z"(%"struct.pr47611::HasPodBase"* inreg noalias sret(%"struct.pr47611::HasPodBase") align 8 %agg.result, %"struct.pr47611::HasPodBase"* %x) HasPodBase copy(HasPodBase *x) { return *x; } void call_copy_pod(Pod *pod) { *pod = copy(pod); // WOA64-LABEL: define dso_local void @"?call_copy_pod@pr47611@@YAXPEAUPod@1@@Z" - // WOA64: %{{.*}} = call %"struct.pr47611::Pod" @"?copy@pr47611@@YA?AUPod@1@PEAU21@@Z"(%"struct.pr47611::Pod"* noundef %{{.*}}) + // WOA64: %{{.*}} = call %"struct.pr47611::Pod" @"?copy@pr47611@@YA?AUPod@1@PEAU21@@Z"(%"struct.pr47611::Pod"* %{{.*}}) } void call_copy_notcxx14aggregate(NotCXX14Aggregate *notcxx14aggregate) { *notcxx14aggregate = copy(notcxx14aggregate); // WOA64-LABEL: define dso_local void @"?call_copy_notcxx14aggregate@pr47611@@YAXPEAUNotCXX14Aggregate@1@@Z" - // WOA64: call void @"?copy@pr47611@@YA?AUNotCXX14Aggregate@1@PEAU21@@Z"(%"struct.pr47611::NotCXX14Aggregate"* inreg sret(%"struct.pr47611::NotCXX14Aggregate") align 8 %{{.*}}, %"struct.pr47611::NotCXX14Aggregate"* noundef %{{.*}}) + // WOA64: call void @"?copy@pr47611@@YA?AUNotCXX14Aggregate@1@PEAU21@@Z"(%"struct.pr47611::NotCXX14Aggregate"* inreg sret(%"struct.pr47611::NotCXX14Aggregate") align 8 %{{.*}}, %"struct.pr47611::NotCXX14Aggregate"* %{{.*}}) } void call_copy_notpod(NotPod *notPod) { *notPod = copy(notPod); // WOA64-LABEL: define dso_local void @"?call_copy_notpod@pr47611@@YAXPEAUNotPod@1@@Z" - // WOA64: %{{.*}} = call [2 x i64] @"?copy@pr47611@@YA?AUNotPod@1@PEAU21@@Z"(%"struct.pr47611::NotPod"* noundef %{{.*}}) + // WOA64: %{{.*}} = call [2 x i64] @"?copy@pr47611@@YA?AUNotPod@1@PEAU21@@Z"(%"struct.pr47611::NotPod"* %{{.*}}) } void call_copy_hasemptybase(HasEmptyBase *hasEmptyBase) { *hasEmptyBase = copy(hasEmptyBase); // WOA64-LABEL: define dso_local void @"?call_copy_hasemptybase@pr47611@@YAXPEAUHasEmptyBase@1@@Z" - // WOA64: call void @"?copy@pr47611@@YA?AUHasEmptyBase@1@PEAU21@@Z"(%"struct.pr47611::HasEmptyBase"* inreg sret(%"struct.pr47611::HasEmptyBase") align 8 %{{.*}}, %"struct.pr47611::HasEmptyBase"* noundef %{{.*}}) + // WOA64: call void @"?copy@pr47611@@YA?AUHasEmptyBase@1@PEAU21@@Z"(%"struct.pr47611::HasEmptyBase"* inreg sret(%"struct.pr47611::HasEmptyBase") align 8 %{{.*}}, %"struct.pr47611::HasEmptyBase"* %{{.*}}) } void call_copy_haspodbase(HasPodBase *hasPodBase) { *hasPodBase = copy(hasPodBase); // WOA64-LABEL: define dso_local void @"?call_copy_haspodbase@pr47611@@YAXPEAUHasPodBase@1@@Z" - // WOA64: call void @"?copy@pr47611@@YA?AUHasPodBase@1@PEAU21@@Z"(%"struct.pr47611::HasPodBase"* inreg sret(%"struct.pr47611::HasPodBase") align 8 %{{.*}}, %"struct.pr47611::HasPodBase"* noundef %{{.*}}) + // WOA64: call void @"?copy@pr47611@@YA?AUHasPodBase@1@PEAU21@@Z"(%"struct.pr47611::HasPodBase"* inreg sret(%"struct.pr47611::HasPodBase") align 8 %{{.*}}, %"struct.pr47611::HasPodBase"* %{{.*}}) } }; // namespace pr47611 diff --git a/clang/test/CodeGenCXX/ibm128-declarations.cpp b/clang/test/CodeGenCXX/ibm128-declarations.cpp index 72e2e6859df19a0344a5e474e767647c7ab83bf5..6d2c6d25448799e1d9acc1161770834ab0c27ed7 100644 --- a/clang/test/CodeGenCXX/ibm128-declarations.cpp +++ b/clang/test/CodeGenCXX/ibm128-declarations.cpp @@ -79,7 +79,7 @@ int main(void) { // CHECK: @gf = global ppc_fp128 0xM40080000000000000000000000000000, align 16 // CHECK: @_ZN5CTest3scfE = external constant ppc_fp128, align 16 -// CHECK: define dso_local noundef ppc_fp128 @_Z10func_arithggg(ppc_fp128 noundef %a, ppc_fp128 noundef %b, ppc_fp128 noundef %c) +// CHECK: define dso_local ppc_fp128 @_Z10func_arithggg(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c) // CHECK: entry: // CHECK: store ppc_fp128 %a, ppc_fp128* %a.addr, align 16 // CHECK: store ppc_fp128 %b, ppc_fp128* %b.addr, align 16 @@ -104,7 +104,7 @@ int main(void) { // CHECK: ret ppc_fp128 %8 // CHECK: } -// CHECK: define dso_local noundef ppc_fp128 @_Z10func_vaargiz(i32 noundef signext %n, ...) +// CHECK: define dso_local ppc_fp128 @_Z10func_vaargiz(i32 signext %n, ...) // CHECK: entry: // CHECK: store i32 %n, i32* %n.addr, align 4 // CHECK: %ap1 = bitcast i8** %ap to i8* @@ -121,36 +121,36 @@ int main(void) { // CHECK: ret ppc_fp128 %2 // CHECK: } -// CHECK: define dso_local noundef ppc_fp128 @_Z11icmode_selfg(ppc_fp128 noundef %x) -// CHECK: define dso_local noundef { ppc_fp128, ppc_fp128 } @_Z19icmode_self_complexCg(ppc_fp128 noundef %x.coerce0, ppc_fp128 noundef %x.coerce1) +// CHECK: define dso_local ppc_fp128 @_Z11icmode_selfg(ppc_fp128 %x) +// CHECK: define dso_local { ppc_fp128, ppc_fp128 } @_Z19icmode_self_complexCg(ppc_fp128 %x.coerce0, ppc_fp128 %x.coerce1) -// CHECK: define dso_local noundef signext i32 @main() +// CHECK: define dso_local signext i32 @main() // CHECK: entry: // CHECK: %0 = load ppc_fp128, ppc_fp128* %lf, align 16 -// CHECK: call void @_ZN5CTestC1Eg(%class.CTest* noundef %ct, ppc_fp128 noundef %0) +// CHECK: call void @_ZN5CTestC1Eg(%class.CTest* nonnull align 16 dereferenceable(32) %ct, ppc_fp128 %0) // CHECK: %mem2 = getelementptr inbounds %struct.T1, %struct.T1* %tf, i32 0, i32 0 // CHECK: %1 = load ppc_fp128, ppc_fp128* %mem2, align 16 // CHECK: %2 = load ppc_fp128, ppc_fp128* %lf, align 16 -// CHECK: %call = call noundef ppc_fp128 @_Z5func1g(ppc_fp128 noundef %2) +// CHECK: %call = call ppc_fp128 @_Z5func1g(ppc_fp128 %2) // CHECK: %add = fadd ppc_fp128 %1, %call // CHECK: %3 = load ppc_fp128, ppc_fp128* %lf, align 16 -// CHECK: %call1 = call noundef ppc_fp128 @_ZN5CTest5func3Eg(ppc_fp128 noundef %3) +// CHECK: %call1 = call ppc_fp128 @_ZN5CTest5func3Eg(ppc_fp128 %3) // CHECK: %sub = fsub ppc_fp128 %add, %call1 // CHECK: store ppc_fp128 %sub, ppc_fp128* %lfi, align 16 // CHECK: ret i32 0 // CHECK: } -// CHECK: define linkonce_odr void @_ZN5CTestC1Eg(%class.CTest* noundef %this, ppc_fp128 noundef %arg) +// CHECK: define linkonce_odr void @_ZN5CTestC1Eg(%class.CTest* nonnull align 16 dereferenceable(32) %this, ppc_fp128 %arg) // CHECK: entry: // CHECK: store %class.CTest* %this, %class.CTest** %this.addr, align 8 // CHECK: store ppc_fp128 %arg, ppc_fp128* %arg.addr, align 16 // CHECK: %this1 = load %class.CTest*, %class.CTest** %this.addr, align 8 // CHECK: %0 = load ppc_fp128, ppc_fp128* %arg.addr, align 16 -// CHECK: call void @_ZN5CTestC2Eg(%class.CTest* noundef %this1, ppc_fp128 noundef %0) +// CHECK: call void @_ZN5CTestC2Eg(%class.CTest* nonnull align 16 dereferenceable(32) %this1, ppc_fp128 %0) // CHECK: ret void // CHECK: } -// CHECK: define linkonce_odr noundef ppc_fp128 @_ZN5CTest5func3Eg(ppc_fp128 noundef %arg) +// CHECK: define linkonce_odr ppc_fp128 @_ZN5CTest5func3Eg(ppc_fp128 %arg) // CHECK: entry: // CHECK: %arg.addr = alloca ppc_fp128, align 16 // CHECK: store ppc_fp128 %arg, ppc_fp128* %arg.addr, align 16 @@ -160,7 +160,7 @@ int main(void) { // CHECK: ret ppc_fp128 %mul // CHECK: } -// CHECK: define linkonce_odr void @_ZN5CTestC2Eg(%class.CTest* noundef %this, ppc_fp128 noundef %arg) +// CHECK: define linkonce_odr void @_ZN5CTestC2Eg(%class.CTest* nonnull align 16 dereferenceable(32) %this, ppc_fp128 %arg) // CHECK: entry: // CHECK: store %class.CTest* %this, %class.CTest** %this.addr, align 8 // CHECK: store ppc_fp128 %arg, ppc_fp128* %arg.addr, align 16 diff --git a/clang/test/CodeGenCXX/implicit-copy-assign-operator.cpp b/clang/test/CodeGenCXX/implicit-copy-assign-operator.cpp index 10d0be837dddeb527e5d309c42f8e93a6ec4c4fc..b4f246f74c19f9c6b4b3e5d75aba140ce2032d17 100644 --- a/clang/test/CodeGenCXX/implicit-copy-assign-operator.cpp +++ b/clang/test/CodeGenCXX/implicit-copy-assign-operator.cpp @@ -40,7 +40,7 @@ void test_D(D d1, D d2) { d1 = d2; } -// CHECK-LABEL: define linkonce_odr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.D* @_ZN1DaSERS_ +// CHECK-LABEL: define linkonce_odr nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.D* @_ZN1DaSERS_ // CHECK: {{call.*_ZN1AaSERS_}} // CHECK: {{call.*_ZN1BaSERS_}} // CHECK: {{call.*_ZN1CaSERKS_}} diff --git a/clang/test/CodeGenCXX/implicit-copy-constructor.cpp b/clang/test/CodeGenCXX/implicit-copy-constructor.cpp index f56ccdddd910d3d5a49e28c6529cfda34ebe84e0..ecd1d2b742019844611c3942ee704db68599ee29 100644 --- a/clang/test/CodeGenCXX/implicit-copy-constructor.cpp +++ b/clang/test/CodeGenCXX/implicit-copy-constructor.cpp @@ -40,7 +40,7 @@ void f(D d) { D d2(d); } -// CHECK-LABEL: define linkonce_odr void @_ZN1DC1ERS_(%struct.D* {{[^,]*}} %this, %struct.D* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr +// CHECK-LABEL: define linkonce_odr void @_ZN1DC1ERS_(%struct.D* {{[^,]*}} %this, %struct.D* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr // CHECK: call void @_ZN1AC1Ev // CHECK: call void @_ZN1CC2ERS_1A // CHECK: call void @_ZN1AD1Ev diff --git a/clang/test/CodeGenCXX/inalloca-overaligned.cpp b/clang/test/CodeGenCXX/inalloca-overaligned.cpp index 7de903c93d84be90b5391839d8b454041923d3ce..0a51875bb592234db45a051ef483f869100ec853 100644 --- a/clang/test/CodeGenCXX/inalloca-overaligned.cpp +++ b/clang/test/CodeGenCXX/inalloca-overaligned.cpp @@ -27,7 +27,7 @@ int receive_inalloca_overaligned(NonTrivial nt, OverAligned o) { return nt.x + o.buf[0]; } -// CHECK-LABEL: define dso_local noundef i32 @"?receive_inalloca_overaligned@@Y{{.*}}" +// CHECK-LABEL: define dso_local i32 @"?receive_inalloca_overaligned@@Y{{.*}}" // CHECK-SAME: (<{ %struct.NonTrivial, %struct.OverAligned* }>* inalloca(<{ %struct.NonTrivial, %struct.OverAligned* }>) %0) int pass_inalloca_overaligned() { @@ -35,45 +35,45 @@ int pass_inalloca_overaligned() { return gvi32; } -// CHECK-LABEL: define dso_local noundef i32 @"?pass_inalloca_overaligned@@Y{{.*}}" +// CHECK-LABEL: define dso_local i32 @"?pass_inalloca_overaligned@@Y{{.*}}" // CHECK: [[TMP:%[^ ]*]] = alloca %struct.OverAligned, align 64 // CHECK: call i8* @llvm.stacksave() // CHECK: alloca inalloca <{ %struct.NonTrivial, %struct.OverAligned* }> // Construct OverAligned into TMP. -// CHECK: call x86_thiscallcc noundef %struct.OverAligned* @"??0OverAligned@@QAE@XZ"(%struct.OverAligned* {{[^,]*}} [[TMP]]) +// CHECK: call x86_thiscallcc %struct.OverAligned* @"??0OverAligned@@QAE@XZ"(%struct.OverAligned* {{[^,]*}} [[TMP]]) // Construct NonTrivial into the GEP. // CHECK: [[GEP:%[^ ]*]] = getelementptr inbounds <{ %struct.NonTrivial, %struct.OverAligned* }>, <{ %struct.NonTrivial, %struct.OverAligned* }>* %{{.*}}, i32 0, i32 0 -// CHECK: call x86_thiscallcc noundef %struct.NonTrivial* @"??0NonTrivial@@QAE@XZ"(%struct.NonTrivial* {{[^,]*}} [[GEP]]) +// CHECK: call x86_thiscallcc %struct.NonTrivial* @"??0NonTrivial@@QAE@XZ"(%struct.NonTrivial* {{[^,]*}} [[GEP]]) // Store the address of an OverAligned temporary into the struct. // CHECK: getelementptr inbounds <{ %struct.NonTrivial, %struct.OverAligned* }>, <{ %struct.NonTrivial, %struct.OverAligned* }>* %{{.*}}, i32 0, i32 1 // CHECK: store %struct.OverAligned* [[TMP]], %struct.OverAligned** %{{.*}}, align 4 -// CHECK: call noundef i32 @"?receive_inalloca_overaligned@@Y{{.*}}"(<{ %struct.NonTrivial, %struct.OverAligned* }>* inalloca(<{ %struct.NonTrivial, %struct.OverAligned* }>) %argmem) +// CHECK: call i32 @"?receive_inalloca_overaligned@@Y{{.*}}"(<{ %struct.NonTrivial, %struct.OverAligned* }>* inalloca(<{ %struct.NonTrivial, %struct.OverAligned* }>) %argmem) int receive_both(Both o) { return o.x + o.y; } -// CHECK-LABEL: define dso_local noundef i32 @"?receive_both@@Y{{.*}}" -// CHECK-SAME: (%struct.Both* noundef %o) +// CHECK-LABEL: define dso_local i32 @"?receive_both@@Y{{.*}}" +// CHECK-SAME: (%struct.Both* %o) int pass_both() { gvi32 = receive_both(Both()); return gvi32; } -// CHECK-LABEL: define dso_local noundef i32 @"?pass_both@@Y{{.*}}" +// CHECK-LABEL: define dso_local i32 @"?pass_both@@Y{{.*}}" // CHECK: [[TMP:%[^ ]*]] = alloca %struct.Both, align 8 -// CHECK: call x86_thiscallcc noundef %struct.Both* @"??0Both@@QAE@XZ"(%struct.Both* {{[^,]*}} [[TMP]]) -// CHECK: call noundef i32 @"?receive_both@@Y{{.*}}"(%struct.Both* noundef [[TMP]]) +// CHECK: call x86_thiscallcc %struct.Both* @"??0Both@@QAE@XZ"(%struct.Both* {{[^,]*}} [[TMP]]) +// CHECK: call i32 @"?receive_both@@Y{{.*}}"(%struct.Both* [[TMP]]) int receive_inalloca_both(NonTrivial nt, Both o) { return nt.x + o.x + o.y; } -// CHECK-LABEL: define dso_local noundef i32 @"?receive_inalloca_both@@Y{{.*}}" +// CHECK-LABEL: define dso_local i32 @"?receive_inalloca_both@@Y{{.*}}" // CHECK-SAME: (<{ %struct.NonTrivial, %struct.Both* }>* inalloca(<{ %struct.NonTrivial, %struct.Both* }>) %0) int pass_inalloca_both() { @@ -81,10 +81,10 @@ int pass_inalloca_both() { return gvi32; } -// CHECK-LABEL: define dso_local noundef i32 @"?pass_inalloca_both@@Y{{.*}}" +// CHECK-LABEL: define dso_local i32 @"?pass_inalloca_both@@Y{{.*}}" // CHECK: [[TMP:%[^ ]*]] = alloca %struct.Both, align 8 -// CHECK: call x86_thiscallcc noundef %struct.Both* @"??0Both@@QAE@XZ"(%struct.Both* {{[^,]*}} [[TMP]]) -// CHECK: call noundef i32 @"?receive_inalloca_both@@Y{{.*}}"(<{ %struct.NonTrivial, %struct.Both* }>* inalloca(<{ %struct.NonTrivial, %struct.Both* }>) %argmem) +// CHECK: call x86_thiscallcc %struct.Both* @"??0Both@@QAE@XZ"(%struct.Both* {{[^,]*}} [[TMP]]) +// CHECK: call i32 @"?receive_inalloca_both@@Y{{.*}}"(<{ %struct.NonTrivial, %struct.Both* }>* inalloca(<{ %struct.NonTrivial, %struct.Both* }>) %argmem) // Here we have a type that is: // - overaligned @@ -100,12 +100,12 @@ struct [[trivial_abi]] alignas(8) MyPtr { int receiveMyPtr(MyPtr o) { return *o.ptr; } -// CHECK-LABEL: define dso_local noundef i32 @"?receiveMyPtr@@Y{{.*}}" -// CHECK-SAME: (%struct.MyPtr* noundef %o) +// CHECK-LABEL: define dso_local i32 @"?receiveMyPtr@@Y{{.*}}" +// CHECK-SAME: (%struct.MyPtr* %o) int passMyPtr() { return receiveMyPtr(MyPtr()); } -// CHECK-LABEL: define dso_local noundef i32 @"?passMyPtr@@Y{{.*}}" +// CHECK-LABEL: define dso_local i32 @"?passMyPtr@@Y{{.*}}" // CHECK: [[TMP:%[^ ]*]] = alloca %struct.MyPtr, align 8 -// CHECK: call x86_thiscallcc noundef %struct.MyPtr* @"??0MyPtr@@QAE@XZ"(%struct.MyPtr* {{[^,]*}} [[TMP]]) -// CHECK: call noundef i32 @"?receiveMyPtr@@Y{{.*}}"(%struct.MyPtr* noundef [[TMP]]) +// CHECK: call x86_thiscallcc %struct.MyPtr* @"??0MyPtr@@QAE@XZ"(%struct.MyPtr* {{[^,]*}} [[TMP]]) +// CHECK: call i32 @"?receiveMyPtr@@Y{{.*}}"(%struct.MyPtr* [[TMP]]) diff --git a/clang/test/CodeGenCXX/inalloca-stmtexpr.cpp b/clang/test/CodeGenCXX/inalloca-stmtexpr.cpp index 8113970ceabf835f1b1f8363fe5e35a761b63eae..090953ae3b1d9656ebe5ce28b3b732942a15d698 100644 --- a/clang/test/CodeGenCXX/inalloca-stmtexpr.cpp +++ b/clang/test/CodeGenCXX/inalloca-stmtexpr.cpp @@ -43,7 +43,7 @@ out:; // that goto branches through. // CHECK-LABEL: define dso_local void @seqAbort() // CHECK: alloca inalloca <{ %struct.Foo, %struct.Foo }> -// CHECK: call noundef zeroext i1 @"?cond@@YA_NXZ"() +// CHECK: call zeroext i1 @"?cond@@YA_NXZ"() // CHECK: br i1 // CHECK: br label %out // CHECK: call void @"?inalloca@@YAXUFoo@@0@Z"(<{ %struct.Foo, %struct.Foo }>* inalloca(<{ %struct.Foo, %struct.Foo }>) %{{.*}}) diff --git a/clang/test/CodeGenCXX/inalloca-vector.cpp b/clang/test/CodeGenCXX/inalloca-vector.cpp index 77033970354f38a901ac4ad748a6485a946d39b3..e052d2e6728d677397f2283ee43e9124c3e466fd 100644 --- a/clang/test/CodeGenCXX/inalloca-vector.cpp +++ b/clang/test/CodeGenCXX/inalloca-vector.cpp @@ -18,9 +18,9 @@ void receive_vec_128(NonTrivial nt, __m128 x, __m128 y, __m128 z, __m128 w, __m1 gv128 = x + y + z + w + q; } // CHECK-LABEL: define dso_local void @"?receive_vec_128@@YAXUNonTrivial@@T__m128@@1111@Z" -// CHECK-SAME: (<4 x float> inreg noundef %x, -// CHECK-SAME: <4 x float> inreg noundef %y, -// CHECK-SAME: <4 x float> inreg noundef %z, +// CHECK-SAME: (<4 x float> inreg %x, +// CHECK-SAME: <4 x float> inreg %y, +// CHECK-SAME: <4 x float> inreg %z, // CHECK-SAME: <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>* inalloca(<{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>) %0) void pass_vec_128() { @@ -29,7 +29,7 @@ void pass_vec_128() { } // CHECK-LABEL: define dso_local void @"?pass_vec_128@@YAXXZ"() // CHECK: getelementptr inbounds <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>, <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>* %{{[^,]*}}, i32 0, i32 0 -// CHECK: call x86_thiscallcc noundef %struct.NonTrivial* @"??0NonTrivial@@QAE@XZ"(%struct.NonTrivial* {{[^,]*}} %{{.*}}) +// CHECK: call x86_thiscallcc %struct.NonTrivial* @"??0NonTrivial@@QAE@XZ"(%struct.NonTrivial* {{[^,]*}} %{{.*}}) // Store q, store temp alloca. // CHECK: store <4 x float> %{{[^,]*}}, <4 x float>* %{{[^,]*}}, align 16 @@ -42,9 +42,9 @@ void pass_vec_128() { // CHECK: store <4 x float>* %{{[^,]*}}, <4 x float>** %{{[^,]*}}, align 4 // CHECK: call void @"?receive_vec_128@@YAXUNonTrivial@@T__m128@@1111@Z" -// CHECK-SAME: (<4 x float> inreg noundef %{{[^,]*}}, -// CHECK-SAME: <4 x float> inreg noundef %{{[^,]*}}, -// CHECK-SAME: <4 x float> inreg noundef %{{[^,]*}}, +// CHECK-SAME: (<4 x float> inreg %{{[^,]*}}, +// CHECK-SAME: <4 x float> inreg %{{[^,]*}}, +// CHECK-SAME: <4 x float> inreg %{{[^,]*}}, // CHECK-SAME: <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>* inalloca(<{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>) %{{[^,]*}}) // w will be passed indirectly by register, and q will be passed indirectly, but @@ -53,11 +53,11 @@ void __fastcall fastcall_receive_vec(__m128 x, __m128 y, __m128 z, __m128 w, int gv128 = x + y + z + w + q; } // CHECK-LABEL: define dso_local x86_fastcallcc void @"?fastcall_receive_vec@@Y{{[^"]*}}" -// CHECK-SAME: (<4 x float> inreg noundef %x, -// CHECK-SAME: <4 x float> inreg noundef %y, -// CHECK-SAME: <4 x float> inreg noundef %z, -// CHECK-SAME: <4 x float>* inreg noundef %0, -// CHECK-SAME: i32 inreg noundef %edx, +// CHECK-SAME: (<4 x float> inreg %x, +// CHECK-SAME: <4 x float> inreg %y, +// CHECK-SAME: <4 x float> inreg %z, +// CHECK-SAME: <4 x float>* inreg %0, +// CHECK-SAME: i32 inreg %edx, // CHECK-SAME: <{ <4 x float>*, %struct.NonTrivial }>* inalloca(<{ <4 x float>*, %struct.NonTrivial }>) %1) @@ -67,12 +67,12 @@ void __vectorcall vectorcall_receive_vec(double xmm0, double xmm1, double xmm2, gv128 = x + y + z + w + q; } // CHECK-LABEL: define dso_local x86_vectorcallcc void @"?vectorcall_receive_vec@@Y{{[^"]*}}" -// CHECK-SAME: (double inreg noundef %xmm0, -// CHECK-SAME: double inreg noundef %xmm1, -// CHECK-SAME: double inreg noundef %xmm2, -// CHECK-SAME: <4 x float> inreg noundef %x, -// CHECK-SAME: <4 x float> inreg noundef %y, -// CHECK-SAME: <4 x float> inreg noundef %z, -// CHECK-SAME: <4 x float>* inreg noundef %0, -// CHECK-SAME: i32 inreg noundef %edx, +// CHECK-SAME: (double inreg %xmm0, +// CHECK-SAME: double inreg %xmm1, +// CHECK-SAME: double inreg %xmm2, +// CHECK-SAME: <4 x float> inreg %x, +// CHECK-SAME: <4 x float> inreg %y, +// CHECK-SAME: <4 x float> inreg %z, +// CHECK-SAME: <4 x float>* inreg %0, +// CHECK-SAME: i32 inreg %edx, // CHECK-SAME: <{ <4 x float>*, %struct.NonTrivial }>* inalloca(<{ <4 x float>*, %struct.NonTrivial }>) %1) diff --git a/clang/test/CodeGenCXX/inheriting-constructor-cleanup.cpp b/clang/test/CodeGenCXX/inheriting-constructor-cleanup.cpp index d6f05d1ab7d7f16bf6b2ce88b506d9c4835fff52..6b33ba3bf3620b6f2b6b4109a8da7afdcc0322bc 100644 --- a/clang/test/CodeGenCXX/inheriting-constructor-cleanup.cpp +++ b/clang/test/CodeGenCXX/inheriting-constructor-cleanup.cpp @@ -29,7 +29,7 @@ void f() { // CHECK-LABEL: define{{.*}} void @_Z1fv // CHECK: %[[TMP1:.*]] = alloca %struct.S1 // CHECK: %[[TMP2:.*]] = alloca %struct.S2 - // CHECK: call void (%struct.Base*, %struct.S1*, %struct.S2*, i8*, ...) @_ZN4BaseC2ERK2S1RK2S2PKcz(%struct.Base* {{.*}}, %struct.S1* noundef nonnull align 1 dereferenceable(1) %[[TMP1]], %struct.S2* noundef nonnull align 1 dereferenceable(1) %[[TMP2]], i8* {{.*}}) + // CHECK: call void (%struct.Base*, %struct.S1*, %struct.S2*, i8*, ...) @_ZN4BaseC2ERK2S1RK2S2PKcz(%struct.Base* {{.*}}, %struct.S1* nonnull align 1 dereferenceable(1) %[[TMP1]], %struct.S2* nonnull align 1 dereferenceable(1) %[[TMP2]], i8* {{.*}}) // CHECK-NEXT: call void @_ZN9InheritorD1Ev(%struct.Inheritor* {{.*}}) // CHECK-NEXT: call void @_ZN2S2D1Ev(%struct.S2* {{[^,]*}} %[[TMP2]]) // CHECK-NEXT: call void @_ZN2S1D1Ev(%struct.S1* {{[^,]*}} %[[TMP1]]) @@ -37,7 +37,7 @@ void f() { // EXCEPTIONS-LABEL: define{{.*}} void @_Z1fv // EXCEPTIONS: %[[TMP1:.*]] = alloca %struct.S1 // EXCEPTIONS: %[[TMP2:.*]] = alloca %struct.S2 - // EXCEPTIONS: invoke void (%struct.Base*, %struct.S1*, %struct.S2*, i8*, ...) @_ZN4BaseC2ERK2S1RK2S2PKcz(%struct.Base* {{.*}}, %struct.S1* noundef nonnull align 1 dereferenceable(1) %[[TMP1]], %struct.S2* noundef nonnull align 1 dereferenceable(1) %[[TMP2]], i8* {{.*}}) + // EXCEPTIONS: invoke void (%struct.Base*, %struct.S1*, %struct.S2*, i8*, ...) @_ZN4BaseC2ERK2S1RK2S2PKcz(%struct.Base* {{.*}}, %struct.S1* nonnull align 1 dereferenceable(1) %[[TMP1]], %struct.S2* nonnull align 1 dereferenceable(1) %[[TMP2]], i8* {{.*}}) // EXCEPTIONS-NEXT: to label %[[CONT:.*]] unwind label %[[LPAD:.*]] // EXCEPTIONS: [[CONT]]: diff --git a/clang/test/CodeGenCXX/inheriting-constructor.cpp b/clang/test/CodeGenCXX/inheriting-constructor.cpp index 62df84b9464d23b0b9fcafa256cfe4528d2d5fd6..c338edcc76ae433231659a6d9648d2cccdb36fc2 100644 --- a/clang/test/CodeGenCXX/inheriting-constructor.cpp +++ b/clang/test/CodeGenCXX/inheriting-constructor.cpp @@ -1,8 +1,8 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -std=c++11 -triple i386-linux -emit-llvm -o - %s | FileCheck %s --check-prefix=ITANIUM -// RUN: %clang_cc1 -disable-noundef-analysis -std=c++11 -triple x86_64-darwin -emit-llvm -o - %s | FileCheck %s --check-prefix=ITANIUM -// RUN: %clang_cc1 -disable-noundef-analysis -std=c++11 -triple arm64-ehabi -emit-llvm -o - %s | FileCheck %s --check-prefix=ITANIUM -// RUN: %clang_cc1 -disable-noundef-analysis -std=c++11 -triple i386-windows -emit-llvm -o - %s | FileCheck %s --check-prefix=MSABI --check-prefix=WIN32 -// RUN: %clang_cc1 -disable-noundef-analysis -std=c++11 -triple x86_64-windows -emit-llvm -o - %s | FileCheck %s --check-prefix=MSABI --check-prefix=WIN64 +// RUN: %clang_cc1 -std=c++11 -triple i386-linux -emit-llvm -o - %s | FileCheck %s --check-prefix=ITANIUM +// RUN: %clang_cc1 -std=c++11 -triple x86_64-darwin -emit-llvm -o - %s | FileCheck %s --check-prefix=ITANIUM +// RUN: %clang_cc1 -std=c++11 -triple arm64-ehabi -emit-llvm -o - %s | FileCheck %s --check-prefix=ITANIUM +// RUN: %clang_cc1 -std=c++11 -triple i386-windows -emit-llvm -o - %s | FileCheck %s --check-prefix=MSABI --check-prefix=WIN32 +// RUN: %clang_cc1 -std=c++11 -triple x86_64-windows -emit-llvm -o - %s | FileCheck %s --check-prefix=MSABI --check-prefix=WIN64 // PR12219 struct A { A(int); virtual ~A(); }; diff --git a/clang/test/CodeGenCXX/init-invariant.cpp b/clang/test/CodeGenCXX/init-invariant.cpp index eec3f839327be55d176bd54348162f5c86404599..2126d7f9ee56eac1122789723a0122a4ff351df9 100644 --- a/clang/test/CodeGenCXX/init-invariant.cpp +++ b/clang/test/CodeGenCXX/init-invariant.cpp @@ -41,20 +41,20 @@ void e() { static const A a = A(); } -// CHECK: call void @_ZN1AC1Ev({{.*}}* noundef {{[^,]*}} @a) +// CHECK: call void @_ZN1AC1Ev({{.*}}* nonnull {{[^,]*}} @a) // CHECK: call {{.*}}@llvm.invariant.start.p0i8(i64 4, i8* bitcast ({{.*}} @a to i8*)) -// CHECK: call void @_ZN1BC1Ev({{.*}}* noundef {{[^,]*}} @b) -// CHECK-NOT: call {{.*}}@llvm.invariant.start.p0i8(i64 noundef 4, i8* bitcast ({{.*}} @b to i8*)) +// CHECK: call void @_ZN1BC1Ev({{.*}}* nonnull {{[^,]*}} @b) +// CHECK-NOT: call {{.*}}@llvm.invariant.start.p0i8(i64 4, i8* bitcast ({{.*}} @b to i8*)) -// CHECK: call void @_ZN1CC1Ev({{.*}}* noundef {{[^,]*}} @c) -// CHECK-NOT: call {{.*}}@llvm.invariant.start.p0i8(i64 noundef 4, i8* bitcast ({{.*}} @c to i8*)) +// CHECK: call void @_ZN1CC1Ev({{.*}}* nonnull {{[^,]*}} @c) +// CHECK-NOT: call {{.*}}@llvm.invariant.start.p0i8(i64 4, i8* bitcast ({{.*}} @c to i8*)) -// CHECK: call noundef i32 @_Z1fv( +// CHECK: call i32 @_Z1fv( // CHECK: store {{.*}}, i32* @d // CHECK: call {{.*}}@llvm.invariant.start.p0i8(i64 4, i8* bitcast ({{.*}} @d to i8*)) // CHECK-LABEL: define{{.*}} void @_Z1ev( -// CHECK: call void @_ZN1AC1Ev(%struct.A* noundef {{[^,]*}} @_ZZ1evE1a) +// CHECK: call void @_ZN1AC1Ev(%struct.A* nonnull {{[^,]*}} @_ZZ1evE1a) // CHECK: call {{.*}}@llvm.invariant.start.p0i8(i64 4, i8* {{.*}}bitcast ({{.*}} @_ZZ1evE1a to i8*)) // CHECK-NOT: llvm.invariant.end diff --git a/clang/test/CodeGenCXX/init-priority-attr.cpp b/clang/test/CodeGenCXX/init-priority-attr.cpp index faace8ae3cabd5a2653e542381508ae39e4262a7..ff155d07ca2eeed76852bd47419b2f58f231f51c 100644 --- a/clang/test/CodeGenCXX/init-priority-attr.cpp +++ b/clang/test/CodeGenCXX/init-priority-attr.cpp @@ -33,17 +33,17 @@ A C::a = A(); // CHECK: { i32, void ()*, i8* } { i32 65535, void ()* @_GLOBAL__sub_I_init_priority_attr.cpp, i8* null }] // CHECK: _GLOBAL__I_000200() -// CHECK: _Z3fooi(i32 noundef 3) +// CHECK: _Z3fooi(i32 3) // CHECK-NEXT: ret void // CHECK: _GLOBAL__I_000300() -// CHECK: _Z3fooi(i32 noundef 2) -// CHECK-NEXT: _Z3fooi(i32 noundef 1) +// CHECK: _Z3fooi(i32 2) +// CHECK-NEXT: _Z3fooi(i32 1) // CHECK-NEXT: ret void // CHECK: _GLOBAL__sub_I_init_priority_attr.cpp() -// CHECK: _Z3fooi(i32 noundef 1) -// CHECK-NEXT: _Z3fooi(i32 noundef 4) +// CHECK: _Z3fooi(i32 1) +// CHECK-NEXT: _Z3fooi(i32 4) // CHECK-NEXT: ret void C c; diff --git a/clang/test/CodeGenCXX/initializer-list-ctor-order.cpp b/clang/test/CodeGenCXX/initializer-list-ctor-order.cpp index 63f8f96230d2608caaf03126b52e7ce8bf6d99e7..3644da0e23af1064003a0b668119a017a315f11b 100644 --- a/clang/test/CodeGenCXX/initializer-list-ctor-order.cpp +++ b/clang/test/CodeGenCXX/initializer-list-ctor-order.cpp @@ -24,6 +24,6 @@ struct B : A { }; B::B() : A{f(), g()} {} // CHECK-ITANIUM-LABEL: define{{.*}} void @_ZN1BC2Ev -// CHECK-MS-LABEL: define dso_local x86_thiscallcc noundef %struct.B* @"??0B@@QAE@XZ" +// CHECK-MS-LABEL: define dso_local x86_thiscallcc %struct.B* @"??0B@@QAE@XZ" // CHECK: call i32 @f() // CHECK: call i32 @g() diff --git a/clang/test/CodeGenCXX/inline-functions.cpp b/clang/test/CodeGenCXX/inline-functions.cpp index 549682ed094bd25cc0b60a41574d90f91da94eb5..17f0fad27909400cc3c29bd341a0bad3bb13a93e 100644 --- a/clang/test/CodeGenCXX/inline-functions.cpp +++ b/clang/test/CodeGenCXX/inline-functions.cpp @@ -101,7 +101,7 @@ extern void InlineThenExternThenDefFn(); void InlineThenExternThenDefFn() {} // NORMAL-NOT: _Z17ExternAndConstexprFnv -// MSVCCOMPAT-LABEL: define weak_odr dso_local noundef i32 @"?ExternAndConstexprFn@@YAHXZ" +// MSVCCOMPAT-LABEL: define weak_odr dso_local i32 @"?ExternAndConstexprFn@@YAHXZ" extern constexpr int ExternAndConstexprFn() { return 0; } // NORMAL-NOT: _Z11ConstexprFnv diff --git a/clang/test/CodeGenCXX/lambda-conversion-op-cc.cpp b/clang/test/CodeGenCXX/lambda-conversion-op-cc.cpp index 47e2421684fe188239cbf77f5fbed6f782c5c548..f6487615840936c6448efbd0df0ac5ae9a9899b4 100644 --- a/clang/test/CodeGenCXX/lambda-conversion-op-cc.cpp +++ b/clang/test/CodeGenCXX/lambda-conversion-op-cc.cpp @@ -31,42 +31,42 @@ void usage() { // LIN64: define{{.*}} void @_Z5usagev() // VECCALL: define{{.*}} void @_Z5usagev() // WIN32: define dso_local void @"?usage@@YAXXZ"() -// CHECK: call noundef double (i32, float, double)* @"_ZZ5usagevENK3$_0cvPFdifdEEv" -// WIN32: call x86_thiscallcc noundef double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6A?A?@@HMN@ZXZ" -// WIN32: call x86_thiscallcc noundef double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6E?A?@@HMN@ZXZ" -// WIN32: call x86_thiscallcc noundef double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6G?A?@@HMN@ZXZ" -// WIN32: call x86_thiscallcc noundef double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6I?A?@@HMN@ZXZ" -// WIN32: call x86_thiscallcc noundef double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6Q?A?@@HMN@ZXZ" +// CHECK: call double (i32, float, double)* @"_ZZ5usagevENK3$_0cvPFdifdEEv" +// WIN32: call x86_thiscallcc double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6A?A?@@HMN@ZXZ" +// WIN32: call x86_thiscallcc double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6E?A?@@HMN@ZXZ" +// WIN32: call x86_thiscallcc double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6G?A?@@HMN@ZXZ" +// WIN32: call x86_thiscallcc double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6I?A?@@HMN@ZXZ" +// WIN32: call x86_thiscallcc double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6Q?A?@@HMN@ZXZ" // Operator+ calls 'default' calling convention. -// CHECK: call noundef double (i32, float, double)* @"_ZZ5usagevENK3$_0cvPFdifdEEv" -// WIN32: call x86_thiscallcc noundef double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6A?A?@@HMN@ZXZ" +// CHECK: call double (i32, float, double)* @"_ZZ5usagevENK3$_0cvPFdifdEEv" +// WIN32: call x86_thiscallcc double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6A?A?@@HMN@ZXZ" // // Conversion operator, returns __invoke. -// CHECK: define internal noundef double (i32, float, double)* @"_ZZ5usagevENK3$_0cvPFdifdEEv" +// CHECK: define internal double (i32, float, double)* @"_ZZ5usagevENK3$_0cvPFdifdEEv" // CHECK: ret double (i32, float, double)* @"_ZZ5usagevEN3$_08__invokeEifd" -// WIN32: define internal x86_thiscallcc noundef double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6A?A?@@HMN@ZXZ" +// WIN32: define internal x86_thiscallcc double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6A?A?@@HMN@ZXZ" // WIN32: ret double (i32, float, double)* @"?__invoke@@?0??usage@@YAXXZ@CA?A?@@HMN@Z" -// WIN32: define internal x86_thiscallcc noundef double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6E?A?@@HMN@ZXZ" +// WIN32: define internal x86_thiscallcc double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6E?A?@@HMN@ZXZ" // WIN32: ret double (i32, float, double)* @"?__invoke@@?0??usage@@YAXXZ@CE?A?@@HMN@Z" -// WIN32: define internal x86_thiscallcc noundef double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6G?A?@@HMN@ZXZ" +// WIN32: define internal x86_thiscallcc double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6G?A?@@HMN@ZXZ" // WIN32: ret double (i32, float, double)* @"?__invoke@@?0??usage@@YAXXZ@CG?A?@@HMN@Z" -// WIN32: define internal x86_thiscallcc noundef double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6I?A?@@HMN@ZXZ" +// WIN32: define internal x86_thiscallcc double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6I?A?@@HMN@ZXZ" // WIN32: ret double (i32, float, double)* @"?__invoke@@?0??usage@@YAXXZ@CI?A?@@HMN@Z" -// WIN32: define internal x86_thiscallcc noundef double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6Q?A?@@HMN@ZXZ" +// WIN32: define internal x86_thiscallcc double (i32, float, double)* @"??B@?0??usage@@YAXXZ@QBEP6Q?A?@@HMN@ZXZ" // WIN32: ret double (i32, float, double)* @"?__invoke@@?0??usage@@YAXXZ@CQ?A?@@HMN@Z" // // __invoke function, calls operator(). Win32 should call both. -// LIN64: define internal noundef double @"_ZZ5usagevEN3$_08__invokeEifd" -// LIN64: call noundef double @"_ZZ5usagevENK3$_0clEifd" -// VECCALL: define internal x86_vectorcallcc noundef double @"_ZZ5usagevEN3$_08__invokeEifd" -// VECCALL: call x86_vectorcallcc noundef double @"_ZZ5usagevENK3$_0clEifd" -// WIN32: define internal noundef double @"?__invoke@@?0??usage@@YAXXZ@CA?A?@@HMN@Z" -// WIN32: call x86_thiscallcc noundef double @"??R@?0??usage@@YAXXZ@QBE?A?@@HMN@Z" -// WIN32: define internal x86_thiscallcc noundef double @"?__invoke@@?0??usage@@YAXXZ@CE?A?@@HMN@Z" -// WIN32: call x86_thiscallcc noundef double @"??R@?0??usage@@YAXXZ@QBE?A?@@HMN@Z" -// WIN32: define internal x86_stdcallcc noundef double @"?__invoke@@?0??usage@@YAXXZ@CG?A?@@HMN@Z" -// WIN32: call x86_thiscallcc noundef double @"??R@?0??usage@@YAXXZ@QBE?A?@@HMN@Z" -// WIN32: define internal x86_fastcallcc noundef double @"?__invoke@@?0??usage@@YAXXZ@CI?A?@@HMN@Z" -// WIN32: call x86_thiscallcc noundef double @"??R@?0??usage@@YAXXZ@QBE?A?@@HMN@Z" -// WIN32: define internal x86_vectorcallcc noundef double @"?__invoke@@?0??usage@@YAXXZ@CQ?A?@@HMN@Z" -// WIN32: call x86_thiscallcc noundef double @"??R@?0??usage@@YAXXZ@QBE?A?@@HMN@Z" +// LIN64: define internal double @"_ZZ5usagevEN3$_08__invokeEifd" +// LIN64: call double @"_ZZ5usagevENK3$_0clEifd" +// VECCALL: define internal x86_vectorcallcc double @"_ZZ5usagevEN3$_08__invokeEifd" +// VECCALL: call x86_vectorcallcc double @"_ZZ5usagevENK3$_0clEifd" +// WIN32: define internal double @"?__invoke@@?0??usage@@YAXXZ@CA?A?@@HMN@Z" +// WIN32: call x86_thiscallcc double @"??R@?0??usage@@YAXXZ@QBE?A?@@HMN@Z" +// WIN32: define internal x86_thiscallcc double @"?__invoke@@?0??usage@@YAXXZ@CE?A?@@HMN@Z" +// WIN32: call x86_thiscallcc double @"??R@?0??usage@@YAXXZ@QBE?A?@@HMN@Z" +// WIN32: define internal x86_stdcallcc double @"?__invoke@@?0??usage@@YAXXZ@CG?A?@@HMN@Z" +// WIN32: call x86_thiscallcc double @"??R@?0??usage@@YAXXZ@QBE?A?@@HMN@Z" +// WIN32: define internal x86_fastcallcc double @"?__invoke@@?0??usage@@YAXXZ@CI?A?@@HMN@Z" +// WIN32: call x86_thiscallcc double @"??R@?0??usage@@YAXXZ@QBE?A?@@HMN@Z" +// WIN32: define internal x86_vectorcallcc double @"?__invoke@@?0??usage@@YAXXZ@CQ?A?@@HMN@Z" +// WIN32: call x86_thiscallcc double @"??R@?0??usage@@YAXXZ@QBE?A?@@HMN@Z" diff --git a/clang/test/CodeGenCXX/lambda-expressions-inside-auto-functions.cpp b/clang/test/CodeGenCXX/lambda-expressions-inside-auto-functions.cpp index 58e1e376ab6e4a967b34ad6c479476b9488e6d99..59acba7be26e02cbc88598629475ac90f0186b7d 100644 --- a/clang/test/CodeGenCXX/lambda-expressions-inside-auto-functions.cpp +++ b/clang/test/CodeGenCXX/lambda-expressions-inside-auto-functions.cpp @@ -53,12 +53,12 @@ struct A { template auto foo() { return [](const T&) { return 42; }; } }; -//CHECK_ABIV6: define linkonce_odr noundef i32 @_ZZN22inline_member_function1AIdE14default_lambdaIdEEDavENKUlRKdE_clES5_(%class.anon -//CHECK_ABI_LATEST: define linkonce_odr noundef i32 @_ZZN22inline_member_function1AIdE14default_lambdaIdEEDavENKUlRKdE_clES4_(%class.anon +//CHECK_ABIV6: define linkonce_odr i32 @_ZZN22inline_member_function1AIdE14default_lambdaIdEEDavENKUlRKdE_clES5_(%class.anon +//CHECK_ABI_LATEST: define linkonce_odr i32 @_ZZN22inline_member_function1AIdE14default_lambdaIdEEDavENKUlRKdE_clES4_(%class.anon int run2 = A{}.func()(3.14); -//CHECK_ABIV6: define linkonce_odr noundef i32 @_ZZN22inline_member_function1AIcE14default_lambdaIcEEDavENKUlRKcE_clES5_(%class.anon -//CHECK_ABI_LATEST: define linkonce_odr noundef i32 @_ZZN22inline_member_function1AIcE14default_lambdaIcEEDavENKUlRKcE_clES4_(%class.anon +//CHECK_ABIV6: define linkonce_odr i32 @_ZZN22inline_member_function1AIcE14default_lambdaIcEEDavENKUlRKcE_clES5_(%class.anon +//CHECK_ABI_LATEST: define linkonce_odr i32 @_ZZN22inline_member_function1AIcE14default_lambdaIcEEDavENKUlRKcE_clES4_(%class.anon int run3 = A{}.func()('a'); } // end inline_member_function diff --git a/clang/test/CodeGenCXX/lambda-expressions-nested-linkage.cpp b/clang/test/CodeGenCXX/lambda-expressions-nested-linkage.cpp index 28443b79bcc4871c7bd2085b975c9faca487a977..228e42999b417bbeb311519b2b9a61637c225eee 100644 --- a/clang/test/CodeGenCXX/lambda-expressions-nested-linkage.cpp +++ b/clang/test/CodeGenCXX/lambda-expressions-nested-linkage.cpp @@ -3,7 +3,7 @@ // CHECK-LABEL: define{{.*}} void @_ZN19non_inline_function3fooEv() // CHECK-LABEL: define internal void @"_ZZN19non_inline_function3fooEvENK3$_0clEi"(%class.anon -// CHECK-LABEL: define internal noundef signext i8 @"_ZZZN19non_inline_function3fooEvENK3$_0clEiENKUlcE_clEc"(%class.anon +// CHECK-LABEL: define internal signext i8 @"_ZZZN19non_inline_function3fooEvENK3$_0clEiENKUlcE_clEc"(%class.anon namespace non_inline_function { void foo() { auto L = [](int a) { @@ -37,17 +37,17 @@ struct L { L l; } -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZN15inline_function3fooEv +// CHECK-LABEL: define linkonce_odr i32 @_ZN15inline_function3fooEv // CHECK-LABEL: define linkonce_odr void @_ZNK12non_template1L1tMUliE_clEi(%class.anon -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZZNK12non_template1L1tMUliE_clEiENKUliE_clEi(%class.anon +// CHECK-LABEL: define linkonce_odr i32 @_ZZNK12non_template1L1tMUliE_clEiENKUliE_clEi(%class.anon // CHECK-LABEL: define linkonce_odr void @_ZNK32lambdas_in_NSDMIs_template_class1LIiEUliE_clEi(%class.anon -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZZNK32lambdas_in_NSDMIs_template_class1LIiEUliE_clEiENKUliE_clEi(%class.anon +// CHECK-LABEL: define linkonce_odr i32 @_ZZNK32lambdas_in_NSDMIs_template_class1LIiEUliE_clEiENKUliE_clEi(%class.anon // CHECK-LABEL: define linkonce_odr void @_ZZN15inline_function3fooEvENKUliE_clEi -// CHECK-LABEL: define linkonce_odr noundef signext i8 @_ZZZN15inline_function3fooEvENKUliE_clEiENKUlcE_clEc +// CHECK-LABEL: define linkonce_odr signext i8 @_ZZZN15inline_function3fooEvENKUliE_clEiENKUlcE_clEc namespace inline_function { inline int foo() { auto L = [](int a) { diff --git a/clang/test/CodeGenCXX/lambda-expressions.cpp b/clang/test/CodeGenCXX/lambda-expressions.cpp index 86a4a9c6a373ca2ca09ea6aa71536da89859d3da..1adc5cfd07aebf91de5c7f47870c95644abe70ee 100644 --- a/clang/test/CodeGenCXX/lambda-expressions.cpp +++ b/clang/test/CodeGenCXX/lambda-expressions.cpp @@ -25,12 +25,12 @@ int ARBSizeOf(int n) { }(); } -// CHECK-LABEL: define internal noundef i32 @"_ZZ9ARBSizeOfiENK3$_0clEv" +// CHECK-LABEL: define internal i32 @"_ZZ9ARBSizeOfiENK3$_0clEv" int a() { return []{ return 1; }(); } // CHECK-LABEL: define{{.*}} i32 @_Z1av -// CHECK: call noundef i32 @"_ZZ1avENK3$_1clEv" -// CHECK-LABEL: define internal noundef i32 @"_ZZ1avENK3$_1clEv" +// CHECK: call i32 @"_ZZ1avENK3$_1clEv" +// CHECK-LABEL: define internal i32 @"_ZZ1avENK3$_1clEv" // CHECK: ret i32 1 int b(int x) { return [x]{return x;}(); } @@ -38,8 +38,8 @@ int b(int x) { return [x]{return x;}(); } // CHECK: store i32 // CHECK: load i32, i32* // CHECK: store i32 -// CHECK: call noundef i32 @"_ZZ1biENK3$_2clEv" -// CHECK-LABEL: define internal noundef i32 @"_ZZ1biENK3$_2clEv" +// CHECK: call i32 @"_ZZ1biENK3$_2clEv" +// CHECK-LABEL: define internal i32 @"_ZZ1biENK3$_2clEv" // CHECK: load i32, i32* // CHECK: ret i32 @@ -47,8 +47,8 @@ int c(int x) { return [&x]{return x;}(); } // CHECK-LABEL: define{{.*}} i32 @_Z1ci // CHECK: store i32 // CHECK: store i32* -// CHECK: call noundef i32 @"_ZZ1ciENK3$_3clEv" -// CHECK-LABEL: define internal noundef i32 @"_ZZ1ciENK3$_3clEv" +// CHECK: call i32 @"_ZZ1ciENK3$_3clEv" +// CHECK-LABEL: define internal i32 @"_ZZ1ciENK3$_3clEv" // CHECK: load i32*, i32** // CHECK: load i32, i32* // CHECK: ret i32 @@ -62,8 +62,8 @@ int d(int x) { D y[10]; return [x,y] { return y[x].x; }(); } // CHECK: call void @_ZN1DC1ERKS_ // CHECK: icmp eq i64 %{{.*}}, 10 // CHECK: br i1 -// CHECK: call noundef i32 @"_ZZ1diENK3$_4clEv" -// CHECK-LABEL: define internal noundef i32 @"_ZZ1diENK3$_4clEv" +// CHECK: call i32 @"_ZZ1diENK3$_4clEv" +// CHECK-LABEL: define internal i32 @"_ZZ1diENK3$_4clEv" // CHECK: load i32, i32* // CHECK: load i32, i32* // CHECK: ret i32 @@ -73,11 +73,11 @@ int e(E a, E b, bool cond) { return [a,b,cond](){ return (cond ? a : b).x; }(); // CHECK-LABEL: define{{.*}} i32 @_Z1e1ES_b // CHECK: call void @_ZN1EC1ERKS_ // CHECK: invoke void @_ZN1EC1ERKS_ -// CHECK: invoke noundef i32 @"_ZZ1e1ES_bENK3$_5clEv" +// CHECK: invoke i32 @"_ZZ1e1ES_bENK3$_5clEv" // CHECK: call void @"_ZZ1e1ES_bEN3$_5D1Ev" // CHECK: call void @"_ZZ1e1ES_bEN3$_5D1Ev" -// CHECK-LABEL: define internal noundef i32 @"_ZZ1e1ES_bENK3$_5clEv" +// CHECK-LABEL: define internal i32 @"_ZZ1e1ES_bENK3$_5clEv" // CHECK: trunc i8 // CHECK: load i32, i32* // CHECK: ret i32 @@ -93,7 +93,7 @@ void f() { static int k; int g() { int &r = k; - // CHECK-LABEL: define internal noundef i32 @"_ZZ1gvENK3$_7clEv"( + // CHECK-LABEL: define internal i32 @"_ZZ1gvENK3$_7clEv"( // CHECK-NOT: } // CHECK: load i32, i32* @_ZL1k, return [] { return r; } (); @@ -110,7 +110,7 @@ void staticarrayref(){ }(); } -// CHECK-LABEL: define internal noundef i32* @"_ZZ11PR22071_funvENK3$_9clEv" +// CHECK-LABEL: define internal i32* @"_ZZ11PR22071_funvENK3$_9clEv" // CHECK: ret i32* @PR22071_var int PR22071_var; int *PR22071_fun() { @@ -186,12 +186,12 @@ namespace pr28595 { // CHECK-LABEL: define internal void @"_ZZ1e1ES_bEN3$_5D2Ev" -// CHECK-LABEL: define internal noundef i32 @"_ZZ1fvEN3$_68__invokeEii" +// CHECK-LABEL: define internal i32 @"_ZZ1fvEN3$_68__invokeEii" // CHECK: store i32 // CHECK-NEXT: store i32 // CHECK-NEXT: load i32, i32* // CHECK-NEXT: load i32, i32* -// CHECK-NEXT: call noundef i32 @"_ZZ1fvENK3$_6clEii" +// CHECK-NEXT: call i32 @"_ZZ1fvENK3$_6clEii" // CHECK-NEXT: ret i32 // CHECK-LABEL: define internal void @"_ZZ1hvEN4$_118__invokeEv"(%struct.A* noalias sret(%struct.A) align 1 %agg.result) {{.*}} { diff --git a/clang/test/CodeGenCXX/lifetime-sanitizer.cpp b/clang/test/CodeGenCXX/lifetime-sanitizer.cpp index 3cce664689598203272c011f0171f7c1b2f9057e..655028bdd0882f56626f0df98289a7020fa5e8ef 100644 --- a/clang/test/CodeGenCXX/lifetime-sanitizer.cpp +++ b/clang/test/CodeGenCXX/lifetime-sanitizer.cpp @@ -24,7 +24,7 @@ struct Y { extern "C" void a(), b(), c(), d(); -// CHECK: define dso_local void @_Z3fooi(i32 noundef %[[N:[^)]+]]) +// CHECK: define dso_local void @_Z3fooi(i32 %[[N:[^)]+]]) void foo(int n) { // CHECK: store i32 %[[N]], i32* %[[NADDR:[^,]+]] // CHECK-LABEL: call void @a() diff --git a/clang/test/CodeGenCXX/linkage.cpp b/clang/test/CodeGenCXX/linkage.cpp index 632335f4d658a89b610e164ad11f110abe10f2e7..69b426269ccdd88cc2e6adcd95f62c73499150f8 100644 --- a/clang/test/CodeGenCXX/linkage.cpp +++ b/clang/test/CodeGenCXX/linkage.cpp @@ -212,7 +212,7 @@ namespace test16 { namespace test17 { // CHECK-DAG: @_ZZN6test173fooILi42EEEPivE3bar = linkonce_odr - // CHECK-DAG: define weak_odr noundef i32* @_ZN6test173fooILi42EEEPiv( + // CHECK-DAG: define weak_odr i32* @_ZN6test173fooILi42EEEPiv( template int *foo() { static int bar; diff --git a/clang/test/CodeGenCXX/mangle-abi-tag.cpp b/clang/test/CodeGenCXX/mangle-abi-tag.cpp index 5399d829f37b0aafabf815950d7f9e4f9d9a33b0..9e26604a2c448aaf553ba85bea70db4e402f219a 100644 --- a/clang/test/CodeGenCXX/mangle-abi-tag.cpp +++ b/clang/test/CodeGenCXX/mangle-abi-tag.cpp @@ -145,7 +145,7 @@ void f13_test() { f13(); } // f13()::L::foo[abi:C][abi:D]() -// CHECK-DAG: define linkonce_odr {{(dso_local )?}}{{(noundef )?}}%struct.E* @_ZZ3f13vEN1L3fooB1CB1DEv( +// CHECK-DAG: define linkonce_odr {{(dso_local )?}}%struct.E* @_ZZ3f13vEN1L3fooB1CB1DEv( // f13()::L::foo[abi:C][abi:D]()::a[abi:A][abi:B] // CHECK-DAG: @_ZZZ3f13vEN1L3fooB1CB1DEvE1aB1AB1B = diff --git a/clang/test/CodeGenCXX/mangle-exprs.cpp b/clang/test/CodeGenCXX/mangle-exprs.cpp index 311685abd87aa07f7e8cc7e6c38c9ed37e68a578..2b099aef749947e94c168de2df27c018c187fbdb 100644 --- a/clang/test/CodeGenCXX/mangle-exprs.cpp +++ b/clang/test/CodeGenCXX/mangle-exprs.cpp @@ -112,10 +112,10 @@ namespace test1 { short foo(short); int foo(int); - // CHECK-LABEL: define linkonce_odr noundef signext i16 @_ZN5test11aIsEEDTcl3foocvT__EEES1_( + // CHECK-LABEL: define linkonce_odr signext i16 @_ZN5test11aIsEEDTcl3foocvT__EEES1_( template auto a(T t) -> decltype(foo(T())) { return foo(t); } - // CHECK-LABEL: define linkonce_odr noundef signext i16 @_ZN5test11bIsEEDTcp3foocvT__EEES1_( + // CHECK-LABEL: define linkonce_odr signext i16 @_ZN5test11bIsEEDTcp3foocvT__EEES1_( template auto b(T t) -> decltype((foo)(T())) { return (foo)(t); } void test(short s) { @@ -147,7 +147,7 @@ namespace test2 { void instantiate() { // CHECK: call void @_ZN5test21aIPFfvEEEvT_DTclfL0p_EE( a(foo, 0.0f); - // CHECK: call noundef float @_ZN5test21bIPFfvEEEDTclfp_EET_( + // CHECK: call float @_ZN5test21bIPFfvEEEDTclfp_EET_( (void) b(foo); // CHECK: call void @_ZN5test21cIPFfvEEEvT_PFvDTclfL1p_EEE( c(foo, bar); @@ -363,7 +363,7 @@ namespace test8 { template auto bar() const -> decltype(foo()) { return 0; } }; - // CHECK-LABEL: define weak_odr noundef i32 @_ZNK5test81XIiE3barIiEEDTcl3fooIT_EEEv + // CHECK-LABEL: define weak_odr i32 @_ZNK5test81XIiE3barIiEEDTcl3fooIT_EEEv template int X::bar() const; } diff --git a/clang/test/CodeGenCXX/mangle-extern-local.cpp b/clang/test/CodeGenCXX/mangle-extern-local.cpp index 111a3ec98e905a2aa319d7536c0f4c4be2849ef1..1394c8f2a1329bf56d7e794ded1798a6fc4ed579 100644 --- a/clang/test/CodeGenCXX/mangle-extern-local.cpp +++ b/clang/test/CodeGenCXX/mangle-extern-local.cpp @@ -6,10 +6,10 @@ // CHECK: @_ZN1N4var3E = external global i32 // CHECK: @_ZN1N4var4E = external global i32 -// CHECK: declare noundef i32 @_Z5func1v() -// CHECK: declare noundef i32 @_ZN1N5func2Ev() +// CHECK: declare i32 @_Z5func1v() +// CHECK: declare i32 @_ZN1N5func2Ev() // CHECK: declare i32 @func4() -// CHECK: declare noundef i32 @_ZN1N5func3Ev() +// CHECK: declare i32 @_ZN1N5func3Ev() int f1() { extern int var1, func1(); diff --git a/clang/test/CodeGenCXX/mangle-lambdas.cpp b/clang/test/CodeGenCXX/mangle-lambdas.cpp index 5b48cbf50841f5322d0d98e21e0d83979884f1ac..66ce8a856851e20693e1db26843a7ecc0d5e3509 100644 --- a/clang/test/CodeGenCXX/mangle-lambdas.cpp +++ b/clang/test/CodeGenCXX/mangle-lambdas.cpp @@ -2,21 +2,21 @@ // CHECK-LABEL: define linkonce_odr void @_Z11inline_funci inline void inline_func(int n) { - // CHECK: call noundef i32 @_ZZ11inline_funciENKUlvE_clEv + // CHECK: call i32 @_ZZ11inline_funciENKUlvE_clEv int i = []{ return 1; }(); - // CHECK: call noundef i32 @_ZZ11inline_funciENKUlvE0_clEv + // CHECK: call i32 @_ZZ11inline_funciENKUlvE0_clEv int j = [=] { return n + i; }(); - // CHECK: call noundef double @_ZZ11inline_funciENKUlvE1_clEv + // CHECK: call double @_ZZ11inline_funciENKUlvE1_clEv int k = [=] () -> double { return n + i; }(); - // CHECK: call noundef i32 @_ZZ11inline_funciENKUliE_clEi + // CHECK: call i32 @_ZZ11inline_funciENKUliE_clEi int l = [=] (int x) -> int { return x + i; }(n); int inner(int i = []{ return 17; }()); - // CHECK: call noundef i32 @_ZZ11inline_funciENKUlvE2_clEv - // CHECK-NEXT: call noundef i32 @_Z5inneri + // CHECK: call i32 @_ZZ11inline_funciENKUlvE2_clEv + // CHECK-NEXT: call i32 @_Z5inneri inner(); // CHECK-NEXT: ret void @@ -26,7 +26,7 @@ void call_inline_func() { inline_func(17); } -// CHECK-LABEL: define linkonce_odr noundef i32* @_ZNK10inline_varMUlvE_clEv( +// CHECK-LABEL: define linkonce_odr i32* @_ZNK10inline_varMUlvE_clEv( // CHECK: @_ZZNK10inline_varMUlvE_clEvE1n inline auto inline_var = [] { static int n = 5; @@ -35,7 +35,7 @@ inline auto inline_var = [] { int *use_inline_var = inline_var(); -// CHECK-LABEL: define linkonce_odr noundef i32* @_ZNK12var_templateIiEMUlvE_clEv( +// CHECK-LABEL: define linkonce_odr i32* @_ZNK12var_templateIiEMUlvE_clEv( // CHECK: @_ZZNK12var_templateIiEMUlvE_clEvE1n template auto var_template = [] { static int n = 9; @@ -59,10 +59,10 @@ void S::g(int i = []{return 1;}(), // CHECK-LABEL: define{{.*}} void @_Z6test_S1S void test_S(S s) { - // CHECK: call noundef i32 @_ZZN1S1fEiiEd0_NKUlvE_clEv - // CHECK-NEXT: call noundef i32 @_ZZN1S1fEiiEd0_NKUlvE0_clEv + // CHECK: call i32 @_ZZN1S1fEiiEd0_NKUlvE_clEv + // CHECK-NEXT: call i32 @_ZZN1S1fEiiEd0_NKUlvE0_clEv // CHECK-NEXT: add nsw i32 - // CHECK-NEXT: call noundef i32 @_ZZN1S1fEiiEd_NKUlvE_clEv + // CHECK-NEXT: call i32 @_ZZN1S1fEiiEd_NKUlvE_clEv // CHECK-NEXT: call void @_ZN1S1fEii s.f(); @@ -70,8 +70,8 @@ void test_S(S s) { // the lambdas in the default arguments of g() won't be seen by // multiple translation units. We check them mainly to ensure that they don't // get the special mangling for lambdas in in-class default arguments. - // CHECK: call noundef i32 @"_ZNK1S3$_0clEv" - // CHECK-NEXT: call noundef i32 @"_ZNK1S3$_1clEv" + // CHECK: call i32 @"_ZNK1S3$_0clEv" + // CHECK-NEXT: call i32 @"_ZNK1S3$_1clEv" // CHECK-NEXT: call void @_ZN1S1gEi s.g(); @@ -79,15 +79,15 @@ void test_S(S s) { } // Check the linkage of the lambda call operators used in test_S. -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZZN1S1fEiiEd0_NKUlvE_clEv +// CHECK-LABEL: define linkonce_odr i32 @_ZZN1S1fEiiEd0_NKUlvE_clEv // CHECK: ret i32 1 -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZZN1S1fEiiEd0_NKUlvE0_clEv +// CHECK-LABEL: define linkonce_odr i32 @_ZZN1S1fEiiEd0_NKUlvE0_clEv // CHECK: ret i32 2 -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZZN1S1fEiiEd_NKUlvE_clEv +// CHECK-LABEL: define linkonce_odr i32 @_ZZN1S1fEiiEd_NKUlvE_clEv // CHECK: ret i32 3 -// CHECK-LABEL: define internal noundef i32 @"_ZNK1S3$_0clEv" +// CHECK-LABEL: define internal i32 @"_ZNK1S3$_0clEv" // CHECK: ret i32 1 -// CHECK-LABEL: define internal noundef i32 @"_ZNK1S3$_1clEv" +// CHECK-LABEL: define internal i32 @"_ZNK1S3$_1clEv" // CHECK: ret i32 2 template @@ -99,10 +99,10 @@ struct ST { // CHECK-LABEL: define{{.*}} void @_Z7test_ST2STIdE void test_ST(ST st) { - // CHECK: call noundef double @_ZZN2STIdE1fEddEd0_NKUlvE_clEv - // CHECK-NEXT: call noundef double @_ZZN2STIdE1fEddEd0_NKUlvE0_clEv + // CHECK: call double @_ZZN2STIdE1fEddEd0_NKUlvE_clEv + // CHECK-NEXT: call double @_ZZN2STIdE1fEddEd0_NKUlvE0_clEv // CHECK-NEXT: fadd double - // CHECK-NEXT: call noundef double @_ZZN2STIdE1fEddEd_NKUlvE_clEv + // CHECK-NEXT: call double @_ZZN2STIdE1fEddEd_NKUlvE_clEv // CHECK-NEXT: call void @_ZN2STIdE1fEdd st.f(); @@ -110,11 +110,11 @@ void test_ST(ST st) { } // Check the linkage of the lambda call operators used in test_ST. -// CHECK-LABEL: define linkonce_odr noundef double @_ZZN2STIdE1fEddEd0_NKUlvE_clEv +// CHECK-LABEL: define linkonce_odr double @_ZZN2STIdE1fEddEd0_NKUlvE_clEv // CHECK: ret double 1 -// CHECK-LABEL: define linkonce_odr noundef double @_ZZN2STIdE1fEddEd0_NKUlvE0_clEv +// CHECK-LABEL: define linkonce_odr double @_ZZN2STIdE1fEddEd0_NKUlvE0_clEv // CHECK: ret double 2 -// CHECK-LABEL: define linkonce_odr noundef double @_ZZN2STIdE1fEddEd_NKUlvE_clEv +// CHECK-LABEL: define linkonce_odr double @_ZZN2STIdE1fEddEd_NKUlvE_clEv // CHECK: ret double 3 template @@ -140,34 +140,34 @@ template int (*StaticMembers::f)() = []{return 5;}; // CHECK-LABEL: define internal void @__cxx_global_var_init -// CHECK: call noundef i32 @_ZNK13StaticMembersIfE1xMUlvE_clEv -// CHECK-NEXT: call noundef i32 @_ZNK13StaticMembersIfE1xMUlvE0_clEv +// CHECK: call i32 @_ZNK13StaticMembersIfE1xMUlvE_clEv +// CHECK-NEXT: call i32 @_ZNK13StaticMembersIfE1xMUlvE0_clEv // CHECK-NEXT: add nsw -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZNK13StaticMembersIfE1xMUlvE_clEv +// CHECK-LABEL: define linkonce_odr i32 @_ZNK13StaticMembersIfE1xMUlvE_clEv // CHECK: ret i32 1 -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZNK13StaticMembersIfE1xMUlvE0_clEv +// CHECK-LABEL: define linkonce_odr i32 @_ZNK13StaticMembersIfE1xMUlvE0_clEv // CHECK: ret i32 2 template float StaticMembers::x; // CHECK-LABEL: define internal void @__cxx_global_var_init -// CHECK: call noundef i32 @_ZNK13StaticMembersIfE1yMUlvE_clEv -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZNK13StaticMembersIfE1yMUlvE_clEv +// CHECK: call i32 @_ZNK13StaticMembersIfE1yMUlvE_clEv +// CHECK-LABEL: define linkonce_odr i32 @_ZNK13StaticMembersIfE1yMUlvE_clEv // CHECK: ret i32 3 template float StaticMembers::y; // CHECK-LABEL: define internal void @__cxx_global_var_init -// CHECK: call noundef i32 @_Z13accept_lambdaIN13StaticMembersIfE1zMUlvE_EEiT_ -// CHECK: declare noundef i32 @_Z13accept_lambdaIN13StaticMembersIfE1zMUlvE_EEiT_() +// CHECK: call i32 @_Z13accept_lambdaIN13StaticMembersIfE1zMUlvE_EEiT_ +// CHECK: declare i32 @_Z13accept_lambdaIN13StaticMembersIfE1zMUlvE_EEiT_() template float StaticMembers::z; // CHECK-LABEL: define internal void @__cxx_global_var_init // CHECK: call {{.*}} @_ZNK13StaticMembersIfE1fMUlvE_cvPFivEEv -// CHECK-LABEL: define linkonce_odr noundef i32 ()* @_ZNK13StaticMembersIfE1fMUlvE_cvPFivEEv +// CHECK-LABEL: define linkonce_odr i32 ()* @_ZNK13StaticMembersIfE1fMUlvE_cvPFivEEv template int (*StaticMembers::f)(); // CHECK-LABEL: define internal void @__cxx_global_var_init -// CHECK: call noundef i32 @"_ZNK13StaticMembersIdE3$_2clEv" -// CHECK-LABEL: define internal noundef i32 @"_ZNK13StaticMembersIdE3$_2clEv" +// CHECK: call i32 @"_ZNK13StaticMembersIdE3$_2clEv" +// CHECK-LABEL: define internal i32 @"_ZNK13StaticMembersIdE3$_2clEv" // CHECK: ret i32 42 template<> double StaticMembers::z = []{return 42; }(); @@ -176,7 +176,7 @@ void func_template(T = []{ return T(); }()); // CHECK-LABEL: define{{.*}} void @_Z17use_func_templatev() void use_func_template() { - // CHECK: call noundef i32 @"_ZZ13func_templateIiEvT_ENK3$_3clEv" + // CHECK: call i32 @"_ZZ13func_templateIiEvT_ENK3$_3clEv" func_template(); } @@ -196,9 +196,9 @@ namespace PR12123 { void B::h() { f(); j(); } } -// CHECK-LABEL: define linkonce_odr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %"struct.PR12123::A"* @_ZZN7PR121231B1fERKSt9type_infoEd_NKUlvE_clEv -// CHECK-LABEL: define linkonce_odr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %"struct.PR12123::A"* @_ZZN7PR121231B1jEbEd_NKUlvE_clEv -// CHECK-LABEL: define linkonce_odr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %"struct.PR12123::C"* @_ZZN7PR121231B1jEbEd_NKUlvE0_clEv +// CHECK-LABEL: define linkonce_odr nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %"struct.PR12123::A"* @_ZZN7PR121231B1fERKSt9type_infoEd_NKUlvE_clEv +// CHECK-LABEL: define linkonce_odr nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %"struct.PR12123::A"* @_ZZN7PR121231B1jEbEd_NKUlvE_clEv +// CHECK-LABEL: define linkonce_odr nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %"struct.PR12123::C"* @_ZZN7PR121231B1jEbEd_NKUlvE0_clEv // CHECK-LABEL: define {{.*}} @_Z{{[0-9]*}}testVarargsLambdaNumberingv( inline int testVarargsLambdaNumbering() { @@ -211,31 +211,31 @@ inline int testVarargsLambdaNumbering() { int k = testVarargsLambdaNumbering(); // Check linkage of the various lambdas. -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZZ11inline_funciENKUlvE_clEv +// CHECK-LABEL: define linkonce_odr i32 @_ZZ11inline_funciENKUlvE_clEv // CHECK: ret i32 1 -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZZ11inline_funciENKUlvE0_clEv +// CHECK-LABEL: define linkonce_odr i32 @_ZZ11inline_funciENKUlvE0_clEv // CHECK: ret i32 -// CHECK-LABEL: define linkonce_odr noundef double @_ZZ11inline_funciENKUlvE1_clEv +// CHECK-LABEL: define linkonce_odr double @_ZZ11inline_funciENKUlvE1_clEv // CHECK: ret double -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZZ11inline_funciENKUliE_clEi +// CHECK-LABEL: define linkonce_odr i32 @_ZZ11inline_funciENKUliE_clEi // CHECK: ret i32 -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZZ11inline_funciENKUlvE2_clEv +// CHECK-LABEL: define linkonce_odr i32 @_ZZ11inline_funciENKUlvE2_clEv // CHECK: ret i32 17 // CHECK-LABEL: define linkonce_odr void @_ZN7MembersC2Ev -// CHECK: call noundef i32 @_ZNK7Members1xMUlvE_clEv -// CHECK-NEXT: call noundef i32 @_ZNK7Members1xMUlvE0_clE +// CHECK: call i32 @_ZNK7Members1xMUlvE_clEv +// CHECK-NEXT: call i32 @_ZNK7Members1xMUlvE0_clE // CHECK-NEXT: add nsw i32 -// CHECK: call noundef i32 @_ZNK7Members1yMUlvE_clEv +// CHECK: call i32 @_ZNK7Members1yMUlvE_clEv // CHECK: ret void // Check the linkage of the lambdas used in test_Members. -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZNK7Members1xMUlvE_clEv +// CHECK-LABEL: define linkonce_odr i32 @_ZNK7Members1xMUlvE_clEv // CHECK: ret i32 1 -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZNK7Members1xMUlvE0_clEv +// CHECK-LABEL: define linkonce_odr i32 @_ZNK7Members1xMUlvE0_clEv // CHECK: ret i32 2 -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZNK7Members1yMUlvE_clEv +// CHECK-LABEL: define linkonce_odr i32 @_ZNK7Members1yMUlvE_clEv // CHECK: ret i32 3 // CHECK-LABEL: define linkonce_odr void @_Z1fIZZNK23TestNestedInstantiationclEvENKUlvE_clEvEUlvE_EvT_ @@ -253,7 +253,7 @@ namespace PR12808 { b(1); } // CHECK-LABEL: define linkonce_odr void @_ZZN7PR128081bIiEEviENKUlvE_clEv - // CHECK-LABEL: define linkonce_odr noundef i32 @_ZZZN7PR128081bIiEEviENKUlvE_clEvENKUlvE_clEv + // CHECK-LABEL: define linkonce_odr i32 @_ZZZN7PR128081bIiEEviENKUlvE_clEvENKUlvE_clEv } diff --git a/clang/test/CodeGenCXX/mangle-ms-cxx11.cpp b/clang/test/CodeGenCXX/mangle-ms-cxx11.cpp index c811e52f7573a869c4917863ea93f5b8cf82099e..1e3b7ceca7175fb2c600558ad3447bf4e80afa8f 100644 --- a/clang/test/CodeGenCXX/mangle-ms-cxx11.cpp +++ b/clang/test/CodeGenCXX/mangle-ms-cxx11.cpp @@ -323,13 +323,13 @@ void unaligned_foo8_S::unaligned_foo8() volatile __unaligned {} namespace PR31197 { struct A { - // CHECK-DAG: define linkonce_odr dso_local x86_thiscallcc noundef i32* @"??R@x@A@PR31197@@QBE@XZ"( + // CHECK-DAG: define linkonce_odr dso_local x86_thiscallcc i32* @"??R@x@A@PR31197@@QBE@XZ"( int *x = []() { static int white; // CHECK-DAG: @"?white@?1???R@x@A@PR31197@@QBE@XZ@4HA" return &white; }(); - // CHECK-DAG: define linkonce_odr dso_local x86_thiscallcc noundef i32* @"??R@y@A@PR31197@@QBE@XZ"( + // CHECK-DAG: define linkonce_odr dso_local x86_thiscallcc i32* @"??R@y@A@PR31197@@QBE@XZ"( int *y = []() { static int black; // CHECK-DAG: @"?black@?1???R@y@A@PR31197@@QBE@XZ@4HA" diff --git a/clang/test/CodeGenCXX/mangle-ms-templates-memptrs-2.cpp b/clang/test/CodeGenCXX/mangle-ms-templates-memptrs-2.cpp index 8d8b82eccf13e5a893e49deb1e793f012fd8d5cf..e4a608aa6c25fcd2108058419b8bb926462703b7 100644 --- a/clang/test/CodeGenCXX/mangle-ms-templates-memptrs-2.cpp +++ b/clang/test/CodeGenCXX/mangle-ms-templates-memptrs-2.cpp @@ -57,4 +57,4 @@ template struct ClassTemplate<&MostGeneral::h>; // Test that we mangle in the vbptr offset, which is 12 here. // -// CHECK: define weak_odr dso_local x86_thiscallcc noundef %struct.ClassTemplate* @"??0?$ClassTemplate@$J??_9MostGeneral@@$BA@AEA@M@3@@QAE@XZ" +// CHECK: define weak_odr dso_local x86_thiscallcc %struct.ClassTemplate* @"??0?$ClassTemplate@$J??_9MostGeneral@@$BA@AEA@M@3@@QAE@XZ" diff --git a/clang/test/CodeGenCXX/mangle-ms-vector-types.cpp b/clang/test/CodeGenCXX/mangle-ms-vector-types.cpp index 6699c99deaec0039af24ebd0d9c898b70033c50f..c2461a30700fdfb77d026617cdb725435849bddd 100644 --- a/clang/test/CodeGenCXX/mangle-ms-vector-types.cpp +++ b/clang/test/CodeGenCXX/mangle-ms-vector-types.cpp @@ -48,43 +48,43 @@ void foo64(__m64) {} // CHECK: define dso_local void @"?foo64@@YAXT__m64@@@Z" __m64 rfoo64() { return __m64(); } -// CHECK: define dso_local noundef <1 x i64> @"?rfoo64@@YA?AT__m64@@XZ" +// CHECK: define dso_local <1 x i64> @"?rfoo64@@YA?AT__m64@@XZ" void foo128(__m128) {} // CHECK: define dso_local void @"?foo128@@YAXT__m128@@@Z" const __m128 rfoo128() { return __m128(); } -// CHECK: define dso_local noundef <4 x float> @"?rfoo128@@YA?BT__m128@@XZ" +// CHECK: define dso_local <4 x float> @"?rfoo128@@YA?BT__m128@@XZ" void foo128d(__m128d) {} // CHECK: define dso_local void @"?foo128d@@YAXU__m128d@@@Z" volatile __m128d rfoo128d() { return __m128d(); } -// CHECK: define dso_local noundef <2 x double> @"?rfoo128d@@YA?CU__m128d@@XZ" +// CHECK: define dso_local <2 x double> @"?rfoo128d@@YA?CU__m128d@@XZ" void foo128i(__m128i) {} // CHECK: define dso_local void @"?foo128i@@YAXT__m128i@@@Z" const volatile __m128i rfoo128i() { return __m128i(); } -// CHECK: define dso_local noundef <2 x i64> @"?rfoo128i@@YA?DT__m128i@@XZ" +// CHECK: define dso_local <2 x i64> @"?rfoo128i@@YA?DT__m128i@@XZ" void foo256(__m256) {} // CHECK: define dso_local void @"?foo256@@YAXT__m256@@@Z" __m256 rfoo256() { return __m256(); } -// CHECK: define dso_local noundef <8 x float> @"?rfoo256@@YA?AT__m256@@XZ" +// CHECK: define dso_local <8 x float> @"?rfoo256@@YA?AT__m256@@XZ" void foo256d(__m256d) {} // CHECK: define dso_local void @"?foo256d@@YAXU__m256d@@@Z" __m256d rfoo256d() { return __m256d(); } -// CHECK: define dso_local noundef <4 x double> @"?rfoo256d@@YA?AU__m256d@@XZ" +// CHECK: define dso_local <4 x double> @"?rfoo256d@@YA?AU__m256d@@XZ" void foo256i(__m256i) {} // CHECK: define dso_local void @"?foo256i@@YAXT__m256i@@@Z" __m256i rfoo256i() { return __m256i(); } -// CHECK: define dso_local noundef <4 x i64> @"?rfoo256i@@YA?AT__m256i@@XZ" +// CHECK: define dso_local <4 x i64> @"?rfoo256i@@YA?AT__m256i@@XZ" // We have a custom mangling for vector types not standardized by Intel. void foov8hi(__v8hi) {} diff --git a/clang/test/CodeGenCXX/mangle-ms.cpp b/clang/test/CodeGenCXX/mangle-ms.cpp index 144f8e38cb191e595cfc6ea8bb2c2af3551caa63..4bb376df428aace56c61379331d91bc4bc0ea058 100644 --- a/clang/test/CodeGenCXX/mangle-ms.cpp +++ b/clang/test/CodeGenCXX/mangle-ms.cpp @@ -453,15 +453,15 @@ namespace PassObjectSize { // void foo(void *const, __clang::__pass_object_size0); // where __clang is a top-level namespace. -// CHECK-DAG: define dso_local noundef i32 @"?foo@PassObjectSize@@YAHQAHW4__pass_object_size0@__clang@@@Z" +// CHECK-DAG: define dso_local i32 @"?foo@PassObjectSize@@YAHQAHW4__pass_object_size0@__clang@@@Z" int foo(int *const i __attribute__((pass_object_size(0)))) { return 0; } -// CHECK-DAG: define dso_local noundef i32 @"?bar@PassObjectSize@@YAHQAHW4__pass_object_size1@__clang@@@Z" +// CHECK-DAG: define dso_local i32 @"?bar@PassObjectSize@@YAHQAHW4__pass_object_size1@__clang@@@Z" int bar(int *const i __attribute__((pass_object_size(1)))) { return 0; } -// CHECK-DAG: define dso_local noundef i32 @"?qux@PassObjectSize@@YAHQAHW4__pass_object_size1@__clang@@0W4__pass_object_size0@3@@Z" +// CHECK-DAG: define dso_local i32 @"?qux@PassObjectSize@@YAHQAHW4__pass_object_size1@__clang@@0W4__pass_object_size0@3@@Z" int qux(int *const i __attribute__((pass_object_size(1))), int *const j __attribute__((pass_object_size(0)))) { return 0; } -// CHECK-DAG: define dso_local noundef i32 @"?zot@PassObjectSize@@YAHQAHW4__pass_object_size1@__clang@@01@Z" +// CHECK-DAG: define dso_local i32 @"?zot@PassObjectSize@@YAHQAHW4__pass_object_size1@__clang@@01@Z" int zot(int *const i __attribute__((pass_object_size(1))), int *const j __attribute__((pass_object_size(1)))) { return 0; } -// CHECK-DAG: define dso_local noundef i32 @"?silly_word@PassObjectSize@@YAHQAHW4__pass_dynamic_object_size1@__clang@@@Z" +// CHECK-DAG: define dso_local i32 @"?silly_word@PassObjectSize@@YAHQAHW4__pass_dynamic_object_size1@__clang@@@Z" int silly_word(int *const i __attribute__((pass_dynamic_object_size(1)))) { return 0; } } diff --git a/clang/test/CodeGenCXX/mangle-this-cxx11.cpp b/clang/test/CodeGenCXX/mangle-this-cxx11.cpp index dcc487c0e5c52336ec81d9cffc58a69b0bc47b00..f9e94797b1596f350bc09edd018a07524cc50a00 100644 --- a/clang/test/CodeGenCXX/mangle-this-cxx11.cpp +++ b/clang/test/CodeGenCXX/mangle-this-cxx11.cpp @@ -13,8 +13,8 @@ struct A { int main() { A a; - // CHECK: call noundef i32 @_ZN1A1fIiEEDTcldtdtdefpT1b1fIT_EEEv + // CHECK: call i32 @_ZN1A1fIiEEDTcldtdtdefpT1b1fIT_EEEv a.f(); - // CHECK: call noundef i32 @_ZN1A1gIiEEDTcldtptfpT1b1fIT_EEEv + // CHECK: call i32 @_ZN1A1gIiEEDTcldtptfpT1b1fIT_EEEv a.g(); } diff --git a/clang/test/CodeGenCXX/mangle-win-ccs.cpp b/clang/test/CodeGenCXX/mangle-win-ccs.cpp index 703d6450d5c91a39d9192d89c2a000c0531d97cf..c8921687d869368a6b88705f5c7ce5b627077ced 100644 --- a/clang/test/CodeGenCXX/mangle-win-ccs.cpp +++ b/clang/test/CodeGenCXX/mangle-win-ccs.cpp @@ -18,14 +18,14 @@ int as_cdecl() { return func_as_ptr(f_cdecl); } int as_stdcall() { return func_as_ptr(f_stdcall); } int as_fastcall() { return func_as_ptr(f_fastcall); } -// CHECK: define dso_local noundef i32 @_Z8as_cdeclv() -// CHECK: call noundef i32 @_ZL11func_as_ptrIPFviiEEiT_(void (i32, i32)* noundef @_Z7f_cdeclii) +// CHECK: define dso_local i32 @_Z8as_cdeclv() +// CHECK: call i32 @_ZL11func_as_ptrIPFviiEEiT_(void (i32, i32)* @_Z7f_cdeclii) -// CHECK: define dso_local noundef i32 @_Z10as_stdcallv() -// CHECK: call noundef i32 @_ZL11func_as_ptrIPU7stdcallFviiEEiT_(void (i32, i32)* noundef @"\01__Z9f_stdcallii@8") +// CHECK: define dso_local i32 @_Z10as_stdcallv() +// CHECK: call i32 @_ZL11func_as_ptrIPU7stdcallFviiEEiT_(void (i32, i32)* @"\01__Z9f_stdcallii@8") -// CHECK: define dso_local noundef i32 @_Z11as_fastcallv() -// CHECK: call noundef i32 @_ZL11func_as_ptrIPU8fastcallFviiEEiT_(void (i32, i32)* noundef @"\01@_Z10f_fastcallii@8") +// CHECK: define dso_local i32 @_Z11as_fastcallv() +// CHECK: call i32 @_ZL11func_as_ptrIPU8fastcallFviiEEiT_(void (i32, i32)* @"\01@_Z10f_fastcallii@8") // PR40107: We should mangle thiscall here but we don't because we can't // disambiguate it from the member pointer case below where it shouldn't be @@ -34,7 +34,7 @@ int as_fastcall() { return func_as_ptr(f_fastcall); } // CHECKX: define dso_local i32 @_Z11as_thiscallv() // CHECKX: call i32 @_ZL11func_as_ptrIPU8thiscallFviiEEiT_(void (i32, i32)* @_Z10f_thiscallii) -// CHECK: define dso_local void @_Z11funcRefTypeRU8fastcallFviiE(void (i32, i32)* noundef nonnull %fr) +// CHECK: define dso_local void @_Z11funcRefTypeRU8fastcallFviiE(void (i32, i32)* nonnull %fr) void funcRefType(void(__attribute__((fastcall)) & fr)(int, int)) { fr(1, 2); } @@ -46,13 +46,13 @@ struct Foo { void bar(int, int); }; // CHECK: define dso_local void @_Z15memptr_thiscallP3FooMS_FvvE(%struct.Foo* {{.*}}) void memptr_thiscall(Foo *o, void (Foo::*mp)()) { (o->*mp)(); } -// CHECK: define dso_local void @_Z12memptrCCTypeR3FooMS_U8fastcallFviiE(%struct.Foo* {{.*}}, { i32, i32 }* noundef byval{{.*}}) +// CHECK: define dso_local void @_Z12memptrCCTypeR3FooMS_U8fastcallFviiE(%struct.Foo* {{.*}}, { i32, i32 }* byval{{.*}}) void memptrCCType(Foo &o, void (__attribute__((fastcall)) Foo::*mp)(int, int)) { (o.*mp)(1, 2); } -// CHECK: define dso_local noundef i32 @_Z17useTemplateFnTypev() -// CHECK: call noundef i32 @_ZL14templateFnTypeIU8fastcallFviiEElPT_(void (i32, i32)* noundef @"\01@_Z10f_fastcallii@8") +// CHECK: define dso_local i32 @_Z17useTemplateFnTypev() +// CHECK: call i32 @_ZL14templateFnTypeIU8fastcallFviiEElPT_(void (i32, i32)* @"\01@_Z10f_fastcallii@8") template static long templateFnType(Fn *fn) { return long(fn); } long useTemplateFnType() { return templateFnType(f_fastcall); } @@ -62,8 +62,8 @@ template void __attribute__((fastcall)) fnTemplate() {} template void __attribute__((fastcall)) fnTemplate(); template <> void __attribute__((fastcall)) fnTemplate() {} -// CHECK: define weak_odr dso_local x86_fastcallcc noundef void (i32, i32)* @"\01@_Z12fnTempReturnIsEPU8fastcallFviiEv@0"() -// CHECK: define dso_local x86_fastcallcc noundef void (i32, i32)* @"\01@_Z12fnTempReturnIiEPU8fastcallFviiEv@0"() +// CHECK: define weak_odr dso_local x86_fastcallcc void (i32, i32)* @"\01@_Z12fnTempReturnIsEPU8fastcallFviiEv@0"() +// CHECK: define dso_local x86_fastcallcc void (i32, i32)* @"\01@_Z12fnTempReturnIiEPU8fastcallFviiEv@0"() typedef void (__attribute__((fastcall)) *fp_cc_t)(int, int); template fp_cc_t __attribute__((fastcall)) fnTempReturn() { return nullptr; } template fp_cc_t __attribute__((fastcall)) fnTempReturn(); diff --git a/clang/test/CodeGenCXX/mangle-win64-ccs.cpp b/clang/test/CodeGenCXX/mangle-win64-ccs.cpp index 771b9d4a0de8b00ac409244d826e38eecb3bd3f2..f2076c976891eebf4d4f3dda970e4dd545151759 100644 --- a/clang/test/CodeGenCXX/mangle-win64-ccs.cpp +++ b/clang/test/CodeGenCXX/mangle-win64-ccs.cpp @@ -15,12 +15,12 @@ ptrdiff_t useThem() { return rv; } -// CHECK-WIN: define dso_local noundef i64 @_Z7useThemv() -// CHECK-WIN: call noundef i64 @_Z11func_as_intIFiiEExPT_(i32 (i32)* noundef @_Z7f_plaini) -// CHECK-WIN: call noundef i64 @_Z11func_as_intIU8sysv_abiFiiEExPT_(i32 (i32)* noundef @_Z9f_sysvabii) -// CHECK-WIN: call noundef i64 @_Z11func_as_intIFiiEExPT_(i32 (i32)* noundef @_Z7f_msabii) +// CHECK-WIN: define dso_local i64 @_Z7useThemv() +// CHECK-WIN: call i64 @_Z11func_as_intIFiiEExPT_(i32 (i32)* @_Z7f_plaini) +// CHECK-WIN: call i64 @_Z11func_as_intIU8sysv_abiFiiEExPT_(i32 (i32)* @_Z9f_sysvabii) +// CHECK-WIN: call i64 @_Z11func_as_intIFiiEExPT_(i32 (i32)* @_Z7f_msabii) // CHECK-LIN: define{{.*}} i64 @_Z7useThemv() -// CHECK-LIN: call noundef i64 @_Z11func_as_intIFiiEElPT_(i32 (i32)* noundef @_Z7f_plaini) -// CHECK-LIN: call noundef i64 @_Z11func_as_intIFiiEElPT_(i32 (i32)* noundef @_Z9f_sysvabii) -// CHECK-LIN: call noundef i64 @_Z11func_as_intIU6ms_abiFiiEElPT_(i32 (i32)* noundef @_Z7f_msabii) +// CHECK-LIN: call i64 @_Z11func_as_intIFiiEElPT_(i32 (i32)* @_Z7f_plaini) +// CHECK-LIN: call i64 @_Z11func_as_intIFiiEElPT_(i32 (i32)* @_Z9f_sysvabii) +// CHECK-LIN: call i64 @_Z11func_as_intIU6ms_abiFiiEElPT_(i32 (i32)* @_Z7f_msabii) diff --git a/clang/test/CodeGenCXX/mangle.cpp b/clang/test/CodeGenCXX/mangle.cpp index 5db6678fa4de36c42ade935944eb20120538a1f3..6cec33e3758e718106a5a0b7a49c0d5eeecc2fdd 100644 --- a/clang/test/CodeGenCXX/mangle.cpp +++ b/clang/test/CodeGenCXX/mangle.cpp @@ -302,7 +302,7 @@ template > class Alloc T *allocate(int, const void*) { return 0; } }; -// CHECK-LABEL: define weak_odr noundef i8* @_ZN6PR58615AllocIcNS_6PolicyINS_1PELb1EEEE8allocateEiPKv +// CHECK-LABEL: define weak_odr i8* @_ZN6PR58615AllocIcNS_6PolicyINS_1PELb1EEEE8allocateEiPKv template class Alloc; } @@ -392,7 +392,7 @@ namespace test2 { return read_member(obj); } - // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN5test211read_memberINS_1AEEEDtptcvPT_Li0E6memberERS2_( + // CHECK-LABEL: define linkonce_odr i32 @_ZN5test211read_memberINS_1AEEEDtptcvPT_Li0E6memberERS2_( } // rdar://problem/9280586 @@ -402,16 +402,16 @@ namespace test3 { struct Path2 : AmbiguousBase { double p; }; struct Derived : Path1, Path2 { }; - // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN5test38get_ab_1INS_7DerivedEEEDtptcvPT_Li0Esr5Path1E2abERS2_( + // CHECK-LABEL: define linkonce_odr i32 @_ZN5test38get_ab_1INS_7DerivedEEEDtptcvPT_Li0Esr5Path1E2abERS2_( template decltype(((T*) 0)->Path1::ab) get_ab_1(T &ref) { return ref.Path1::ab; } - // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN5test38get_ab_2INS_7DerivedEEEDtptcvPT_Li0Esr5Path2E2abERS2_( + // CHECK-LABEL: define linkonce_odr i32 @_ZN5test38get_ab_2INS_7DerivedEEEDtptcvPT_Li0Esr5Path2E2abERS2_( template decltype(((T*) 0)->Path2::ab) get_ab_2(T &ref) { return ref.Path2::ab; } - // CHECK-LABEL: define linkonce_odr noundef float @_ZN5test37get_p_1INS_7DerivedEEEDtptcvPT_Li0Esr5Path1E1pERS2_( + // CHECK-LABEL: define linkonce_odr float @_ZN5test37get_p_1INS_7DerivedEEEDtptcvPT_Li0Esr5Path1E1pERS2_( template decltype(((T*) 0)->Path1::p) get_p_1(T &ref) { return ref.Path1::p; } - // CHECK-LABEL: define linkonce_odr noundef double @_ZN5test37get_p_2INS_7DerivedEEEDtptcvPT_Li0Esr5Path2E1pERS2_( + // CHECK-LABEL: define linkonce_odr double @_ZN5test37get_p_2INS_7DerivedEEEDtptcvPT_Li0Esr5Path2E1pERS2_( template decltype(((T*) 0)->Path2::p) get_p_2(T &ref) { return ref.Path2::p; } Derived obj; @@ -648,13 +648,13 @@ namespace test23 { namespace test24 { void test0() { extern int foo(); - // CHECK: call noundef i32 @_ZN6test243fooEv() + // CHECK: call i32 @_ZN6test243fooEv() foo(); } static char bar() {} void test1() { - // CHECK: call noundef signext i8 @_ZN6test24L3barEv() + // CHECK: call signext i8 @_ZN6test24L3barEv() bar(); } } @@ -757,9 +757,9 @@ namespace test31 { // instantiation-dependent mangling of decltype void g(int); template auto f3(T p)->decltype(g(p)) {} - // CHECK-LABEL: define weak_odr noundef i32 @_ZN6test312f1IiEEiT_( + // CHECK-LABEL: define weak_odr i32 @_ZN6test312f1IiEEiT_( template int f1(int); - // CHECK-LABEL: define weak_odr noundef i32 @_ZN6test312f2IiEEDtfp_ET_ + // CHECK-LABEL: define weak_odr i32 @_ZN6test312f2IiEEDtfp_ET_ template int f2(int); // CHECK-LABEL: define weak_odr void @_ZN6test312f3IiEEDTcl1gfp_EET_ template void f3(int); @@ -775,7 +775,7 @@ namespace test32 { template typename A::type foo() { return 0; } void test() { foo(); - // CHECK: call noundef i32 @_ZN6test323fooINS_1BEEENS_1AIT_XsrS3_5valueEE4typeEv() + // CHECK: call i32 @_ZN6test323fooINS_1BEEENS_1AIT_XsrS3_5valueEE4typeEv() } } @@ -793,7 +793,7 @@ namespace test33 { void test() { foo(); - // CHECK: call noundef i32 @_ZN6test333fooINS_1BEEENS_1AIT_Xsr1XIS3_EE5valueEE4typeEv() + // CHECK: call i32 @_ZN6test333fooINS_1BEEENS_1AIT_Xsr1XIS3_EE5valueEE4typeEv() } } @@ -960,7 +960,7 @@ namespace test45 { template void f(enum T::e *) {} template void f(S::e *); - // CHECK-LABEL: define weak_odr void @_ZN6test451fINS_1SEEEvPTeNT_1eE(i32* noundef %0) + // CHECK-LABEL: define weak_odr void @_ZN6test451fINS_1SEEEvPTeNT_1eE(i32* %0) } namespace test46 { @@ -970,7 +970,7 @@ namespace test46 { template void f(struct T::s *) {} template void f(S::s *); - // CHECK-LABEL: define weak_odr void @_ZN6test461fINS_1SEEEvPTsNT_1sE(%"struct.test46::S::s"* noundef %0) + // CHECK-LABEL: define weak_odr void @_ZN6test461fINS_1SEEEvPTsNT_1sE(%"struct.test46::S::s"* %0) } namespace test47 { @@ -980,7 +980,7 @@ namespace test47 { template void f(class T::c *) {} template void f(S::c *); - // CHECK-LABEL: define weak_odr void @_ZN6test471fINS_1SEEEvPTsNT_1cE(%"class.test47::S::c"* noundef %0) + // CHECK-LABEL: define weak_odr void @_ZN6test471fINS_1SEEEvPTsNT_1cE(%"class.test47::S::c"* %0) } namespace test48 { @@ -990,7 +990,7 @@ namespace test48 { template void f(union T::u *) {} template void f(S::u *); - // CHECK-LABEL: define weak_odr void @_ZN6test481fINS_1SEEEvPTuNT_1uE(%"union.test48::S::u"* noundef %0) + // CHECK-LABEL: define weak_odr void @_ZN6test481fINS_1SEEEvPTuNT_1uE(%"union.test48::S::u"* %0) } namespace test49 { diff --git a/clang/test/CodeGenCXX/matrix-casts.cpp b/clang/test/CodeGenCXX/matrix-casts.cpp index b695e5fd9dc9d7bb7443797e05ff1884e9341172..1bf751ee81b033372a7e7dd8be43cb0430ed7b28 100644 --- a/clang/test/CodeGenCXX/matrix-casts.cpp +++ b/clang/test/CodeGenCXX/matrix-casts.cpp @@ -350,9 +350,9 @@ public: }; Foo class_constructor_matrix_ty(matrix_5_5 m) { - // CHECK-LABEL: define void @_Z27class_constructor_matrix_tyu11matrix_typeILm5ELm5EiE(%class.Foo* noalias sret(%class.Foo) align 4 %agg.result, <25 x i32> noundef %m) + // CHECK-LABEL: define void @_Z27class_constructor_matrix_tyu11matrix_typeILm5ELm5EiE(%class.Foo* noalias sret(%class.Foo) align 4 %agg.result, <25 x i32> %m) // CHECK: [[M:%.*]] = load <25 x i32>, <25 x i32>* {{.*}}, align 4 - // CHECK-NEXT: call void @_ZN3FooC1Eu11matrix_typeILm5ELm5EiE(%class.Foo* noundef %agg.result, <25 x i32> noundef [[M]]) + // CHECK-NEXT: call void @_ZN3FooC1Eu11matrix_typeILm5ELm5EiE(%class.Foo* nonnull align 4 dereferenceable(40) %agg.result, <25 x i32> [[M]]) // CHECK-NEXT: ret void return Foo(m); @@ -364,9 +364,9 @@ struct Bar { }; Bar struct_constructor_matrix_ty(matrix_4_4 m) { - // CHECK-LABEL: define void @_Z28struct_constructor_matrix_tyu11matrix_typeILm4ELm4EfE(%struct.Bar* noalias sret(%struct.Bar) align 4 %agg.result, <16 x float> noundef %m) + // CHECK-LABEL: define void @_Z28struct_constructor_matrix_tyu11matrix_typeILm4ELm4EfE(%struct.Bar* noalias sret(%struct.Bar) align 4 %agg.result, <16 x float> %m) // CHECK: [[M:%.*]] = load <16 x float>, <16 x float>* {{.*}}, align 4 - // CHECK-NEXT: call void @_ZN3BarC1Eu11matrix_typeILm4ELm4EfE(%struct.Bar* noundef %agg.result, <16 x float> noundef [[M]]) + // CHECK-NEXT: call void @_ZN3BarC1Eu11matrix_typeILm4ELm4EfE(%struct.Bar* nonnull align 4 dereferenceable(40) %agg.result, <16 x float> [[M]]) // CHECK-NEXT: ret void return Bar(m); diff --git a/clang/test/CodeGenCXX/matrix-type-builtins.cpp b/clang/test/CodeGenCXX/matrix-type-builtins.cpp index 9182ffe2dd4178b7ae91bdbd3d4d09a609b5d89b..d95774feb7c7524320911ecde4da45dc78132065 100644 --- a/clang/test/CodeGenCXX/matrix-type-builtins.cpp +++ b/clang/test/CodeGenCXX/matrix-type-builtins.cpp @@ -19,7 +19,7 @@ MyMatrix transpose(const MyMatrix &M) { void test_transpose_template1() { // CHECK-LABEL: define{{.*}} void @_Z24test_transpose_template1v() - // CHECK: call void @_Z9transposeIiLj4ELj10EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(%struct.MyMatrix.0* sret(%struct.MyMatrix.0) align 4 %M1_t, %struct.MyMatrix* noundef nonnull align 4 dereferenceable(160) %M1) + // CHECK: call void @_Z9transposeIiLj4ELj10EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(%struct.MyMatrix.0* sret(%struct.MyMatrix.0) align 4 %M1_t, %struct.MyMatrix* nonnull align 4 dereferenceable(160) %M1) // CHECK-LABEL: define linkonce_odr void @_Z9transposeIiLj4ELj10EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE( // CHECK: [[M:%.*]] = load <40 x i32>, <40 x i32>* {{.*}}, align 4 @@ -31,9 +31,9 @@ void test_transpose_template1() { void test_transpose_template2(MyMatrix &M) { // CHECK-LABEL: define{{.*}} void @_Z24test_transpose_template2R8MyMatrixIdLj7ELj6EE( - // CHECK: call void @_Z9transposeIdLj7ELj6EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(%struct.MyMatrix.2* sret(%struct.MyMatrix.2) align 8 %ref.tmp1, %struct.MyMatrix.1* noundef nonnull align 8 dereferenceable(336) %0) - // CHECK-NEXT: call void @_Z9transposeIdLj6ELj7EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(%struct.MyMatrix.1* sret(%struct.MyMatrix.1) align 8 %ref.tmp, %struct.MyMatrix.2* noundef nonnull align 8 dereferenceable(336) %ref.tmp1) - // CHECK-NEXT: call void @_Z9transposeIdLj7ELj6EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(%struct.MyMatrix.2* sret(%struct.MyMatrix.2) align 8 %M2_t, %struct.MyMatrix.1* noundef nonnull align 8 dereferenceable(336) %ref.tmp) + // CHECK: call void @_Z9transposeIdLj7ELj6EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(%struct.MyMatrix.2* sret(%struct.MyMatrix.2) align 8 %ref.tmp1, %struct.MyMatrix.1* nonnull align 8 dereferenceable(336) %0) + // CHECK-NEXT: call void @_Z9transposeIdLj6ELj7EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(%struct.MyMatrix.1* sret(%struct.MyMatrix.1) align 8 %ref.tmp, %struct.MyMatrix.2* nonnull align 8 dereferenceable(336) %ref.tmp1) + // CHECK-NEXT: call void @_Z9transposeIdLj7ELj6EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE(%struct.MyMatrix.2* sret(%struct.MyMatrix.2) align 8 %M2_t, %struct.MyMatrix.1* nonnull align 8 dereferenceable(336) %ref.tmp) // CHECK-LABEL: define linkonce_odr void @_Z9transposeIdLj7ELj6EE8MyMatrixIT_XT1_EXT0_EERKS0_IS1_XT0_EXT1_EE( // CHECK: [[M:%.*]] = load <42 x double>, <42 x double>* {{.*}}, align 8 @@ -58,7 +58,7 @@ void test_transpose_rvalue() { // CHECK-LABEL: define{{.*}} void @_Z21test_transpose_rvaluev() // CHECK-NEXT: entry: // CHECK-NEXT: [[M_T_ADDR:%.*]] = alloca [9 x float], align 4 - // CHECK-NEXT: [[CALL_RES:%.*]] = call noundef <9 x float> @_Z10get_matrixv() + // CHECK-NEXT: [[CALL_RES:%.*]] = call <9 x float> @_Z10get_matrixv() // CHECK-NEXT: [[ADD:%.*]] = fadd <9 x float> [[CALL_RES]], // CHECK-NEXT: [[M_T:%.*]] = call <9 x float> @llvm.matrix.transpose.v9f32(<9 x float> [[ADD]], i32 3, i32 3) // CHECK-NEXT: [[M_T_ADDR_CAST:%.*]] = bitcast [9 x float]* [[M_T_ADDR]] to <9 x float>* @@ -88,11 +88,11 @@ matrix_t column_major_load_with_stride(T *Ptr) { } void test_column_major_load_with_stride_template_double(double *Ptr) { - // CHECK-LABEL: define{{.*}} void @_Z50test_column_major_load_with_stride_template_doublePd(double* noundef %Ptr) + // CHECK-LABEL: define{{.*}} void @_Z50test_column_major_load_with_stride_template_doublePd(double* %Ptr) // CHECK: [[PTR:%.*]] = load double*, double** %Ptr.addr, align 8 - // CHECK-NEXT: call noundef <40 x double> @_Z29column_major_load_with_strideIdLj10ELj4ELj15EEu11matrix_typeIXT0_EXT1_ET_EPS0_(double* noundef [[PTR]]) + // CHECK-NEXT: call <40 x double> @_Z29column_major_load_with_strideIdLj10ELj4ELj15EEu11matrix_typeIXT0_EXT1_ET_EPS0_(double* [[PTR]]) - // CHECK-LABEL: define linkonce_odr noundef <40 x double> @_Z29column_major_load_with_strideIdLj10ELj4ELj15EEu11matrix_typeIXT0_EXT1_ET_EPS0_(double* noundef %Ptr) + // CHECK-LABEL: define linkonce_odr <40 x double> @_Z29column_major_load_with_strideIdLj10ELj4ELj15EEu11matrix_typeIXT0_EXT1_ET_EPS0_(double* %Ptr) // CHECK: [[PTR:%.*]] = load double*, double** %Ptr.addr, align 8 // CHECK-NEXT: call <40 x double> @llvm.matrix.column.major.load.v40f64.i64(double* align 8 [[PTR]], i64 15, i1 false, i32 10, i32 4) @@ -100,11 +100,11 @@ void test_column_major_load_with_stride_template_double(double *Ptr) { } void test_column_major_load_with_stride_template_int(int *Ptr) { - // CHECK-LABEL: define{{.*}} void @_Z47test_column_major_load_with_stride_template_intPi(i32* noundef %Ptr) #5 { + // CHECK-LABEL: define{{.*}} void @_Z47test_column_major_load_with_stride_template_intPi(i32* %Ptr) #5 { // CHECK: [[PTR:%.*]] = load i32*, i32** %Ptr.addr, align 8 - // CHECK-NEXT: call noundef <6 x i32> @_Z29column_major_load_with_strideIiLj3ELj2ELj12EEu11matrix_typeIXT0_EXT1_ET_EPS0_(i32* noundef [[PTR]]) + // CHECK-NEXT: call <6 x i32> @_Z29column_major_load_with_strideIiLj3ELj2ELj12EEu11matrix_typeIXT0_EXT1_ET_EPS0_(i32* [[PTR]]) - // CHECK-LABEL: define linkonce_odr noundef <6 x i32> @_Z29column_major_load_with_strideIiLj3ELj2ELj12EEu11matrix_typeIXT0_EXT1_ET_EPS0_(i32* noundef %Ptr) + // CHECK-LABEL: define linkonce_odr <6 x i32> @_Z29column_major_load_with_strideIiLj3ELj2ELj12EEu11matrix_typeIXT0_EXT1_ET_EPS0_(i32* %Ptr) // CHECK: [[PTR:%.*]] = load i32*, i32** %Ptr.addr, align 8 // CHECK-NEXT: call <6 x i32> @llvm.matrix.column.major.load.v6i32.i64(i32* align 4 [[PTR]], i64 12, i1 false, i32 3, i32 2) @@ -119,9 +119,9 @@ struct UnsignedWrapper { }; void test_column_major_load_stride_wrapper(int *Ptr, UnsignedWrapper &W) { - // CHECK-LABEL: define{{.*}} void @_Z37test_column_major_load_stride_wrapperPiR15UnsignedWrapper(i32* noundef %Ptr, %struct.UnsignedWrapper* noundef nonnull align 1 dereferenceable(1) %W) + // CHECK-LABEL: define{{.*}} void @_Z37test_column_major_load_stride_wrapperPiR15UnsignedWrapper(i32* %Ptr, %struct.UnsignedWrapper* nonnull align 1 dereferenceable(1) %W) // CHECK: [[W:%.*]] = load %struct.UnsignedWrapper*, %struct.UnsignedWrapper** %W.addr, align 8 - // CHECK-NEXT: [[STRIDE:%.*]] = call noundef i32 @_ZN15UnsignedWrappercvjEv(%struct.UnsignedWrapper* {{[^,]*}} [[W]]) + // CHECK-NEXT: [[STRIDE:%.*]] = call i32 @_ZN15UnsignedWrappercvjEv(%struct.UnsignedWrapper* {{[^,]*}} [[W]]) // CHECK-NEXT: [[STRIDE_EXT:%.*]] = zext i32 [[STRIDE]] to i64 // CHECK-NEXT: [[PTR:%.*]] = load i32*, i32** %Ptr.addr, align 8 // CHECK-NEXT: call <4 x i32> @llvm.matrix.column.major.load.v4i32.i64(i32* align 4 [[PTR]], i64 [[STRIDE_EXT]], i1 false, i32 2, i32 2) @@ -131,7 +131,7 @@ void test_column_major_load_stride_wrapper(int *Ptr, UnsignedWrapper &W) { constexpr int constexpr3() { return 3; } void test_column_major_load_constexpr_num_rows(int *Ptr) { - // CHECK-LABEL: define{{.*}} void @_Z41test_column_major_load_constexpr_num_rowsPi(i32* noundef %Ptr) + // CHECK-LABEL: define{{.*}} void @_Z41test_column_major_load_constexpr_num_rowsPi(i32* %Ptr) // CHECK: [[PTR:%.*]] = load i32*, i32** %Ptr.addr, align 8 // CHECK-NEXT: call <6 x i32> @llvm.matrix.column.major.load.v6i32.i64(i32* align 4 [[PTR]], i64 3, i1 false, i32 3, i32 2) @@ -141,7 +141,7 @@ void test_column_major_load_constexpr_num_rows(int *Ptr) { constexpr int constexpr1() { return 1; } void test_column_major_load_constexpr_num_columns(int *Ptr) { - // CHECK-LABEL: define{{.*}} void @_Z44test_column_major_load_constexpr_num_columnsPi(i32* noundef %Ptr) + // CHECK-LABEL: define{{.*}} void @_Z44test_column_major_load_constexpr_num_columnsPi(i32* %Ptr) // CHECK: [[PTR:%.*]] = load i32*, i32** %Ptr.addr, align 8 // CHECK-NEXT: call <2 x i32> @llvm.matrix.column.major.load.v2i32.i64(i32* align 4 [[PTR]], i64 3, i1 false, i32 2, i32 1) matrix_t M1 = __builtin_matrix_column_major_load(Ptr, 2, constexpr1(), 3); @@ -151,15 +151,15 @@ template constexpr int constexpr_plus1() { return N + 1; } void test_column_major_load_constexpr_num_columns_temp(int *Ptr) { - // CHECK-LABEL: define{{.*}} void @_Z49test_column_major_load_constexpr_num_columns_tempPi(i32* noundef %Ptr) + // CHECK-LABEL: define{{.*}} void @_Z49test_column_major_load_constexpr_num_columns_tempPi(i32* %Ptr) // CHECK: [[PTR:%.*]] = load i32*, i32** %Ptr.addr, align 8 // CHECK-NEXT: call <10 x i32> @llvm.matrix.column.major.load.v10i32.i64(i32* align 4 [[PTR]], i64 3, i1 false, i32 2, i32 5) matrix_t M1 = __builtin_matrix_column_major_load(Ptr, 2, constexpr_plus1<4>(), 3); } void test_column_major_load_constexpr_stride_constexpr(int *Ptr) { - // CHECK-LABEL: define{{.*}} void @_Z49test_column_major_load_constexpr_stride_constexprPi(i32* noundef %Ptr) - // CHECK: [[STRIDE:%.*]] = call noundef i32 @_Z10constexpr3v() + // CHECK-LABEL: define{{.*}} void @_Z49test_column_major_load_constexpr_stride_constexprPi(i32* %Ptr) + // CHECK: [[STRIDE:%.*]] = call i32 @_Z10constexpr3v() // CHECK-NEXT: [[STRIDE_EXT:%.*]] = sext i32 [[STRIDE]] to i64 // CHECK-NEXT: [[PTR:%.*]] = load i32*, i32** %Ptr.addr, align 8 // CHECK-NEXT: call <4 x i32> @llvm.matrix.column.major.load.v4i32.i64(i32* align 4 [[PTR]], i64 [[STRIDE_EXT]], i1 false, i32 2, i32 2) @@ -193,11 +193,11 @@ void column_major_store_with_stride(matrix_t &m, T *Ptr) { } void test_column_major_store_with_stride_template_double(double *Ptr) { - // CHECK-LABEL: define{{.*}} void @_Z51test_column_major_store_with_stride_template_doublePd(double* noundef %Ptr) + // CHECK-LABEL: define{{.*}} void @_Z51test_column_major_store_with_stride_template_doublePd(double* %Ptr) // CHECK: [[PTR:%.*]] = load double*, double** %Ptr.addr, align 8 - // CHECK-NEXT: call void @_Z30column_major_store_with_strideIdLj10ELj4ELj15EEvRu11matrix_typeIXT0_EXT1_ET_EPS0_([40 x double]* noundef nonnull align 8 dereferenceable(320) %M1, double* noundef [[PTR]]) + // CHECK-NEXT: call void @_Z30column_major_store_with_strideIdLj10ELj4ELj15EEvRu11matrix_typeIXT0_EXT1_ET_EPS0_([40 x double]* nonnull align 8 dereferenceable(320) %M1, double* [[PTR]]) - // CHECK-LABEL: define linkonce_odr void @_Z30column_major_store_with_strideIdLj10ELj4ELj15EEvRu11matrix_typeIXT0_EXT1_ET_EPS0_([40 x double]* noundef nonnull align 8 dereferenceable(320) %m, double* noundef %Ptr) + // CHECK-LABEL: define linkonce_odr void @_Z30column_major_store_with_strideIdLj10ELj4ELj15EEvRu11matrix_typeIXT0_EXT1_ET_EPS0_([40 x double]* nonnull align 8 dereferenceable(320) %m, double* %Ptr) // CHECK: [[M:%.*]] = load <40 x double>, <40 x double>* {{.*}}, align 8 // CHECK-NEXT: [[PTR:%.*]] = load double*, double** %Ptr.addr, align 8 // CHECK-NEXT: call void @llvm.matrix.column.major.store.v40f64.i64(<40 x double> [[M]], double* align 8 [[PTR]], i64 15, i1 false, i32 10, i32 4) @@ -207,11 +207,11 @@ void test_column_major_store_with_stride_template_double(double *Ptr) { } void test_column_major_store_with_stride_template_int(int *Ptr) { - // CHECK-LABEL: define{{.*}} void @_Z48test_column_major_store_with_stride_template_intPi(i32* noundef %Ptr) + // CHECK-LABEL: define{{.*}} void @_Z48test_column_major_store_with_stride_template_intPi(i32* %Ptr) // CHECK: [[PTR:%.*]] = load i32*, i32** %Ptr.addr, align 8 - // CHECK-NEXT: call void @_Z30column_major_store_with_strideIiLj3ELj2ELj3EEvRu11matrix_typeIXT0_EXT1_ET_EPS0_([6 x i32]* noundef nonnull align 4 dereferenceable(24) %M1, i32* noundef [[PTR]]) + // CHECK-NEXT: call void @_Z30column_major_store_with_strideIiLj3ELj2ELj3EEvRu11matrix_typeIXT0_EXT1_ET_EPS0_([6 x i32]* nonnull align 4 dereferenceable(24) %M1, i32* [[PTR]]) - // CHECK-LABEL: define linkonce_odr void @_Z30column_major_store_with_strideIiLj3ELj2ELj3EEvRu11matrix_typeIXT0_EXT1_ET_EPS0_([6 x i32]* noundef nonnull align 4 dereferenceable(24) %m, i32* noundef %Ptr) + // CHECK-LABEL: define linkonce_odr void @_Z30column_major_store_with_strideIiLj3ELj2ELj3EEvRu11matrix_typeIXT0_EXT1_ET_EPS0_([6 x i32]* nonnull align 4 dereferenceable(24) %m, i32* %Ptr) // CHECK: [[M:%.*]] = load <6 x i32>, <6 x i32>* {{.*}}, align 4 // CHECK-NEXT: [[PTR:%.*]] = load i32*, i32** %Ptr.addr, align 8 // CHECK-NEXT: call void @llvm.matrix.column.major.store.v6i32.i64(<6 x i32> [[M]], i32* align 4 [[PTR]], i64 3, i1 false, i32 3, i32 2) @@ -221,11 +221,11 @@ void test_column_major_store_with_stride_template_int(int *Ptr) { } void test_column_major_store_stride_wrapper(int *Ptr, UnsignedWrapper &W) { - // CHECK-LABEL: define{{.*}} void @_Z38test_column_major_store_stride_wrapperPiR15UnsignedWrapper(i32* noundef %Ptr, %struct.UnsignedWrapper* noundef nonnull align 1 dereferenceable(1) %W) + // CHECK-LABEL: define{{.*}} void @_Z38test_column_major_store_stride_wrapperPiR15UnsignedWrapper(i32* %Ptr, %struct.UnsignedWrapper* nonnull align 1 dereferenceable(1) %W) // CHECK: [[M:%.*]] = load <4 x i32>, <4 x i32>* {{.*}}, align 4 // CHECK-NEXT: [[PTR:%.*]] = load i32*, i32** %Ptr.addr, align 8 // CHECK-NEXT: [[W:%.*]] = load %struct.UnsignedWrapper*, %struct.UnsignedWrapper** %W.addr, align 8 - // CHECK-NEXT: [[IDX:%.*]] = call noundef i32 @_ZN15UnsignedWrappercvjEv(%struct.UnsignedWrapper* {{[^,]*}} [[W]]) + // CHECK-NEXT: [[IDX:%.*]] = call i32 @_ZN15UnsignedWrappercvjEv(%struct.UnsignedWrapper* {{[^,]*}} [[W]]) // CHECK-NEXT: [[IDX_EXT:%.*]] = zext i32 [[IDX]] to i64 // CHECK-NEXT: call void @llvm.matrix.column.major.store.v4i32.i64(<4 x i32> [[M]], i32* align 4 [[PTR]], i64 [[IDX_EXT]], i1 false, i32 2, i32 2) @@ -234,10 +234,10 @@ void test_column_major_store_stride_wrapper(int *Ptr, UnsignedWrapper &W) { } void test_column_major_store_constexpr_stride_constexpr(int *Ptr) { - // CHECK-LABEL: define{{.*}} void @_Z50test_column_major_store_constexpr_stride_constexprPi(i32* noundef %Ptr) + // CHECK-LABEL: define{{.*}} void @_Z50test_column_major_store_constexpr_stride_constexprPi(i32* %Ptr) // CHECK: [[M:%.*]] = load <4 x i32>, <4 x i32>* %0, align 4 // CHECK-NEXT: [[PTR:%.*]] = load i32*, i32** %Ptr.addr, align 8 - // CHECK-NEXT: [[IDX:%.*]] = call noundef i32 @_Z10constexpr3v() + // CHECK-NEXT: [[IDX:%.*]] = call i32 @_Z10constexpr3v() // CHECK-NEXT: [[IDX_EXT:%.*]] = sext i32 [[IDX]] to i64 // CHECK-NEXT: call void @llvm.matrix.column.major.store.v4i32.i64(<4 x i32> [[M]], i32* align 4 [[PTR]], i64 [[IDX_EXT]], i1 false, i32 2, i32 2) diff --git a/clang/test/CodeGenCXX/matrix-type-operators.cpp b/clang/test/CodeGenCXX/matrix-type-operators.cpp index 7e6245f0d581c2c0a765ece2ffa7166482d61959..a082b53f99c5fdf25c355b8b6d9379d2a4c0f159 100644 --- a/clang/test/CodeGenCXX/matrix-type-operators.cpp +++ b/clang/test/CodeGenCXX/matrix-type-operators.cpp @@ -18,9 +18,9 @@ typename MyMatrix::matrix_t add(MyMatrix &A, MyM void test_add_template() { // CHECK-LABEL: define{{.*}} void @_Z17test_add_templatev() - // CHECK: %call = call noundef <10 x float> @_Z3addIfLj2ELj5EEN8MyMatrixIT_XT0_EXT1_EE8matrix_tERS2_S4_(%struct.MyMatrix* noundef nonnull align 4 dereferenceable(40) %Mat1, %struct.MyMatrix* noundef nonnull align 4 dereferenceable(40) %Mat2) + // CHECK: %call = call <10 x float> @_Z3addIfLj2ELj5EEN8MyMatrixIT_XT0_EXT1_EE8matrix_tERS2_S4_(%struct.MyMatrix* nonnull align 4 dereferenceable(40) %Mat1, %struct.MyMatrix* nonnull align 4 dereferenceable(40) %Mat2) - // CHECK-LABEL: define linkonce_odr noundef <10 x float> @_Z3addIfLj2ELj5EEN8MyMatrixIT_XT0_EXT1_EE8matrix_tERS2_S4_( + // CHECK-LABEL: define linkonce_odr <10 x float> @_Z3addIfLj2ELj5EEN8MyMatrixIT_XT0_EXT1_EE8matrix_tERS2_S4_( // CHECK: [[MAT1:%.*]] = load <10 x float>, <10 x float>* {{.*}}, align 4 // CHECK: [[MAT2:%.*]] = load <10 x float>, <10 x float>* {{.*}}, align 4 // CHECK-NEXT: [[RES:%.*]] = fadd <10 x float> [[MAT1]], [[MAT2]] @@ -38,9 +38,9 @@ typename MyMatrix::matrix_t subtract(MyMatrix &A void test_subtract_template() { // CHECK-LABEL: define{{.*}} void @_Z22test_subtract_templatev() - // CHECK: %call = call noundef <10 x float> @_Z8subtractIfLj2ELj5EEN8MyMatrixIT_XT0_EXT1_EE8matrix_tERS2_S4_(%struct.MyMatrix* noundef nonnull align 4 dereferenceable(40) %Mat1, %struct.MyMatrix* noundef nonnull align 4 dereferenceable(40) %Mat2) + // CHECK: %call = call <10 x float> @_Z8subtractIfLj2ELj5EEN8MyMatrixIT_XT0_EXT1_EE8matrix_tERS2_S4_(%struct.MyMatrix* nonnull align 4 dereferenceable(40) %Mat1, %struct.MyMatrix* nonnull align 4 dereferenceable(40) %Mat2) - // CHECK-LABEL: define linkonce_odr noundef <10 x float> @_Z8subtractIfLj2ELj5EEN8MyMatrixIT_XT0_EXT1_EE8matrix_tERS2_S4_( + // CHECK-LABEL: define linkonce_odr <10 x float> @_Z8subtractIfLj2ELj5EEN8MyMatrixIT_XT0_EXT1_EE8matrix_tERS2_S4_( // CHECK: [[MAT1:%.*]] = load <10 x float>, <10 x float>* {{.*}}, align 4 // CHECK: [[MAT2:%.*]] = load <10 x float>, <10 x float>* {{.*}}, align 4 // CHECK-NEXT: [[RES:%.*]] = fsub <10 x float> [[MAT1]], [[MAT2]] @@ -61,7 +61,7 @@ struct DoubleWrapper1 { void test_DoubleWrapper1_Sub1(MyMatrix &m) { // CHECK-LABEL: define{{.*}} void @_Z24test_DoubleWrapper1_Sub1R8MyMatrixIdLj10ELj9EE( // CHECK: [[MATRIX:%.*]] = load <90 x double>, <90 x double>* {{.*}}, align 8 - // CHECK: [[SCALAR:%.*]] = call noundef double @_ZN14DoubleWrapper1cvdEv(%struct.DoubleWrapper1* {{[^,]*}} %w1) + // CHECK: [[SCALAR:%.*]] = call double @_ZN14DoubleWrapper1cvdEv(%struct.DoubleWrapper1* {{[^,]*}} %w1) // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <90 x double> poison, double [[SCALAR]], i32 0 // CHECK-NEXT: [[SCALAR_EMBED1:%.*]] = shufflevector <90 x double> [[SCALAR_EMBED]], <90 x double> poison, <90 x i32> zeroinitializer // CHECK-NEXT: [[RES:%.*]] = fsub <90 x double> [[MATRIX]], [[SCALAR_EMBED1]] @@ -74,7 +74,7 @@ void test_DoubleWrapper1_Sub1(MyMatrix &m) { void test_DoubleWrapper1_Sub2(MyMatrix &m) { // CHECK-LABEL: define{{.*}} void @_Z24test_DoubleWrapper1_Sub2R8MyMatrixIdLj10ELj9EE( - // CHECK: [[SCALAR:%.*]] = call noundef double @_ZN14DoubleWrapper1cvdEv(%struct.DoubleWrapper1* {{[^,]*}} %w1) + // CHECK: [[SCALAR:%.*]] = call double @_ZN14DoubleWrapper1cvdEv(%struct.DoubleWrapper1* {{[^,]*}} %w1) // CHECK: [[MATRIX:%.*]] = load <90 x double>, <90 x double>* {{.*}}, align 8 // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <90 x double> poison, double [[SCALAR]], i32 0 // CHECK-NEXT: [[SCALAR_EMBED1:%.*]] = shufflevector <90 x double> [[SCALAR_EMBED]], <90 x double> poison, <90 x i32> zeroinitializer @@ -96,7 +96,7 @@ struct DoubleWrapper2 { void test_DoubleWrapper2_Add1(MyMatrix &m) { // CHECK-LABEL: define{{.*}} void @_Z24test_DoubleWrapper2_Add1R8MyMatrixIdLj10ELj9EE( // CHECK: [[MATRIX:%.*]] = load <90 x double>, <90 x double>* {{.+}}, align 8 - // CHECK: [[SCALAR:%.*]] = call noundef double @_ZN14DoubleWrapper2cvdEv(%struct.DoubleWrapper2* {{[^,]*}} %w2) + // CHECK: [[SCALAR:%.*]] = call double @_ZN14DoubleWrapper2cvdEv(%struct.DoubleWrapper2* {{[^,]*}} %w2) // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <90 x double> poison, double [[SCALAR]], i32 0 // CHECK-NEXT: [[SCALAR_EMBED1:%.*]] = shufflevector <90 x double> [[SCALAR_EMBED]], <90 x double> poison, <90 x i32> zeroinitializer // CHECK-NEXT: [[RES:%.*]] = fadd <90 x double> [[MATRIX]], [[SCALAR_EMBED1]] @@ -109,7 +109,7 @@ void test_DoubleWrapper2_Add1(MyMatrix &m) { void test_DoubleWrapper2_Add2(MyMatrix &m) { // CHECK-LABEL: define{{.*}} void @_Z24test_DoubleWrapper2_Add2R8MyMatrixIdLj10ELj9EE( - // CHECK: [[SCALAR:%.*]] = call noundef double @_ZN14DoubleWrapper2cvdEv(%struct.DoubleWrapper2* {{[^,]*}} %w2) + // CHECK: [[SCALAR:%.*]] = call double @_ZN14DoubleWrapper2cvdEv(%struct.DoubleWrapper2* {{[^,]*}} %w2) // CHECK: [[MATRIX:%.*]] = load <90 x double>, <90 x double>* {{.*}}, align 8 // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <90 x double> poison, double [[SCALAR]], i32 0 // CHECK-NEXT: [[SCALAR_EMBED1:%.*]] = shufflevector <90 x double> [[SCALAR_EMBED]], <90 x double> poison, <90 x i32> zeroinitializer @@ -131,7 +131,7 @@ struct IntWrapper { void test_IntWrapper_Add(MyMatrix &m) { // CHECK-LABEL: define{{.*}} void @_Z19test_IntWrapper_AddR8MyMatrixIdLj10ELj9EE( // CHECK: [[MATRIX:%.*]] = load <90 x double>, <90 x double>* {{.*}}, align 8 - // CHECK: [[SCALAR:%.*]] = call noundef i32 @_ZN10IntWrappercviEv(%struct.IntWrapper* {{[^,]*}} %w3) + // CHECK: [[SCALAR:%.*]] = call i32 @_ZN10IntWrappercviEv(%struct.IntWrapper* {{[^,]*}} %w3) // CHECK: [[SCALAR_FP:%.*]] = sitofp i32 %call to double // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <90 x double> poison, double [[SCALAR_FP]], i32 0 // CHECK-NEXT: [[SCALAR_EMBED1:%.*]] = shufflevector <90 x double> [[SCALAR_EMBED]], <90 x double> poison, <90 x i32> zeroinitializer @@ -145,7 +145,7 @@ void test_IntWrapper_Add(MyMatrix &m) { void test_IntWrapper_Sub(MyMatrix &m) { // CHECK-LABEL: define{{.*}} void @_Z19test_IntWrapper_SubR8MyMatrixIdLj10ELj9EE( - // CHECK: [[SCALAR:%.*]] = call noundef i32 @_ZN10IntWrappercviEv(%struct.IntWrapper* {{[^,]*}} %w3) + // CHECK: [[SCALAR:%.*]] = call i32 @_ZN10IntWrappercviEv(%struct.IntWrapper* {{[^,]*}} %w3) // CHECK-NEXT: [[SCALAR_FP:%.*]] = sitofp i32 %call to double // CHECK: [[MATRIX:%.*]] = load <90 x double>, <90 x double>* {{.*}}, align 8 // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <90 x double> poison, double [[SCALAR_FP]], i32 0 @@ -167,13 +167,13 @@ MyMatrix test_multiply_template(MyMatrix Mat1, MyMatrix Mat2) { // CHECK-LABEL: define{{.*}} void @_Z22test_multiply_template8MyMatrixIfLj2ELj5EES_IfLj5ELj2EE( // CHECK-NEXT: entry: - // CHECK-NEXT: [[RES:%.*]] = call noundef <4 x float> @_Z8multiplyIfLj2ELj5ELj2EEN8MyMatrixIT_XT0_EXT2_EE8matrix_tERS0_IS1_XT0_EXT1_EERS0_IS1_XT1_EXT2_EE(%struct.MyMatrix* noundef nonnull align 4 dereferenceable(40) %Mat1, %struct.MyMatrix.2* noundef nonnull align 4 dereferenceable(40) %Mat2) + // CHECK-NEXT: [[RES:%.*]] = call <4 x float> @_Z8multiplyIfLj2ELj5ELj2EEN8MyMatrixIT_XT0_EXT2_EE8matrix_tERS0_IS1_XT0_EXT1_EERS0_IS1_XT1_EXT2_EE(%struct.MyMatrix* nonnull align 4 dereferenceable(40) %Mat1, %struct.MyMatrix.2* nonnull align 4 dereferenceable(40) %Mat2) // CHECK-NEXT: %value = getelementptr inbounds %struct.MyMatrix.1, %struct.MyMatrix.1* %agg.result, i32 0, i32 0 // CHECK-NEXT: [[VALUE_ADDR:%.*]] = bitcast [4 x float]* %value to <4 x float>* // CHECK-NEXT: store <4 x float> [[RES]], <4 x float>* [[VALUE_ADDR]], align 4 // CHECK-NEXT: ret void // - // CHECK-LABEL: define linkonce_odr noundef <4 x float> @_Z8multiplyIfLj2ELj5ELj2EEN8MyMatrixIT_XT0_EXT2_EE8matrix_tERS0_IS1_XT0_EXT1_EERS0_IS1_XT1_EXT2_EE( + // CHECK-LABEL: define linkonce_odr <4 x float> @_Z8multiplyIfLj2ELj5ELj2EEN8MyMatrixIT_XT0_EXT2_EE8matrix_tERS0_IS1_XT0_EXT1_EERS0_IS1_XT1_EXT2_EE( // CHECK: [[MAT1:%.*]] = load <10 x float>, <10 x float>* {{.*}}, align 4 // CHECK: [[MAT2:%.*]] = load <10 x float>, <10 x float>* {{.*}}, align 4 // CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.matrix.multiply.v4f32.v10f32.v10f32(<10 x float> [[MAT1]], <10 x float> [[MAT2]], i32 2, i32 5, i32 2) @@ -186,7 +186,7 @@ MyMatrix test_multiply_template(MyMatrix Mat1, void test_IntWrapper_Multiply(MyMatrix &m, IntWrapper &w3) { // CHECK-LABEL: define{{.*}} void @_Z24test_IntWrapper_MultiplyR8MyMatrixIdLj10ELj9EER10IntWrapper( - // CHECK: [[SCALAR:%.*]] = call noundef i32 @_ZN10IntWrappercviEv(%struct.IntWrapper* noundef {{.*}}) + // CHECK: [[SCALAR:%.*]] = call i32 @_ZN10IntWrappercviEv(%struct.IntWrapper* {{.*}}) // CHECK-NEXT: [[SCALAR_FP:%.*]] = sitofp i32 %call to double // CHECK: [[MATRIX:%.*]] = load <90 x double>, <90 x double>* {{.*}}, align 8 // CHECK-NEXT: [[SCALAR_EMBED:%.*]] = insertelement <90 x double> poison, double [[SCALAR_FP]], i32 0 @@ -208,7 +208,7 @@ void test_insert_template1(MyMatrix &Mat, unsigned e, unsigned i // CHECK-NEXT: [[E:%.*]] = load i32, i32* %e.addr, align 4 // CHECK-NEXT: [[I:%.*]] = load i32, i32* %i.addr, align 4 // CHECK-NEXT: [[J:%.*]] = load i32, i32* %j.addr, align 4 - // CHECK-NEXT: call void @_Z6insertIjLj2ELj2EEvR8MyMatrixIT_XT0_EXT1_EES1_jj(%struct.MyMatrix.3* noundef nonnull align 4 dereferenceable(16) [[MAT_ADDR]], i32 noundef [[E]], i32 noundef [[I]], i32 noundef [[J]]) + // CHECK-NEXT: call void @_Z6insertIjLj2ELj2EEvR8MyMatrixIT_XT0_EXT1_EES1_jj(%struct.MyMatrix.3* nonnull align 4 dereferenceable(16) [[MAT_ADDR]], i32 [[E]], i32 [[I]], i32 [[J]]) // CHECK-NEXT: ret void // // CHECK-LABEL: define linkonce_odr void @_Z6insertIjLj2ELj2EEvR8MyMatrixIT_XT0_EXT1_EES1_jj( @@ -234,7 +234,7 @@ void test_insert_template2(MyMatrix &Mat, float e) { // CHECK-LABEL: @_Z21test_insert_template2R8MyMatrixIfLj3ELj8EEf( // CHECK: [[MAT_ADDR:%.*]] = load %struct.MyMatrix.4*, %struct.MyMatrix.4** %Mat.addr, align 8 // CHECK-NEXT: [[E:%.*]] = load float, float* %e.addr, align 4 - // CHECK-NEXT: call void @_Z6insertIfLj3ELj8EEvR8MyMatrixIT_XT0_EXT1_EES1_jj(%struct.MyMatrix.4* noundef nonnull align 4 dereferenceable(96) [[MAT_ADDR]], float noundef [[E]], i32 noundef 2, i32 noundef 5) + // CHECK-NEXT: call void @_Z6insertIfLj3ELj8EEvR8MyMatrixIT_XT0_EXT1_EES1_jj(%struct.MyMatrix.4* nonnull align 4 dereferenceable(96) [[MAT_ADDR]], float [[E]], i32 2, i32 5) // CHECK-NEXT: ret void // // CHECK-LABEL: define linkonce_odr void @_Z6insertIfLj3ELj8EEvR8MyMatrixIT_XT0_EXT1_EES1_jj( @@ -264,10 +264,10 @@ EltTy extract(MyMatrix &Mat) { int test_extract_template(MyMatrix Mat1) { // CHECK-LABEL: @_Z21test_extract_template8MyMatrixIiLj2ELj2EE( // CHECK-NEXT: entry: - // CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_Z7extractIiLj2ELj2EET_R8MyMatrixIS0_XT0_EXT1_EE(%struct.MyMatrix.5* noundef nonnull align 4 dereferenceable(16) [[MAT1:%.*]]) + // CHECK-NEXT: [[CALL:%.*]] = call i32 @_Z7extractIiLj2ELj2EET_R8MyMatrixIS0_XT0_EXT1_EE(%struct.MyMatrix.5* nonnull align 4 dereferenceable(16) [[MAT1:%.*]]) // CHECK-NEXT: ret i32 [[CALL]] // - // CHECK-LABEL: define linkonce_odr noundef i32 @_Z7extractIiLj2ELj2EET_R8MyMatrixIS0_XT0_EXT1_EE( + // CHECK-LABEL: define linkonce_odr i32 @_Z7extractIiLj2ELj2EET_R8MyMatrixIS0_XT0_EXT1_EE( // CHECK: [[MAT:%.*]] = load <4 x i32>, <4 x i32>* {{.*}}, align 4 // CHECK-NEXT: [[MATEXT:%.*]] = extractelement <4 x i32> [[MAT]], i64 1 // CHECK-NEXT: ret i32 [[MATEXT]] @@ -283,7 +283,7 @@ auto matrix_subscript(double4x4 m, R r, C c) -> decltype(m[r][c]) {} double test_matrix_subscript(double4x4 m) { // CHECK-LABEL: @_Z21test_matrix_subscriptu11matrix_typeILm4ELm4EdE( // CHECK: [[MAT:%.*]] = load <16 x double>, <16 x double>* {{.*}}, align 8 - // CHECK-NEXT: [[CALL:%.*]] = call noundef nonnull align 8 dereferenceable(8) double* @_Z16matrix_subscriptIiiEDTixixfp_fp0_fp1_Eu11matrix_typeILm4ELm4EdET_T0_(<16 x double> noundef [[MAT]], i32 noundef 1, i32 noundef 2) + // CHECK-NEXT: [[CALL:%.*]] = call nonnull align 8 dereferenceable(8) double* @_Z16matrix_subscriptIiiEDTixixfp_fp0_fp1_Eu11matrix_typeILm4ELm4EdET_T0_(<16 x double> [[MAT]], i32 1, i32 2) // CHECK-NEXT: [[RES:%.*]] = load double, double* [[CALL]], align 8 // CHECK-NEXT: ret double [[RES]] @@ -314,10 +314,10 @@ struct UnsignedWrapper { double extract_IntWrapper_idx(double4x4 &m, IntWrapper i, UnsignedWrapper j) { // CHECK-LABEL: define{{.*}} double @_Z22extract_IntWrapper_idxRu11matrix_typeILm4ELm4EdE10IntWrapper15UnsignedWrapper( - // CHECK: [[I:%.*]] = call noundef i32 @_ZN10IntWrappercviEv(%struct.IntWrapper* {{[^,]*}} %i) + // CHECK: [[I:%.*]] = call i32 @_ZN10IntWrappercviEv(%struct.IntWrapper* {{[^,]*}} %i) // CHECK-NEXT: [[I_ADD:%.*]] = add nsw i32 [[I]], 1 // CHECK-NEXT: [[I_ADD_EXT:%.*]] = sext i32 [[I_ADD]] to i64 - // CHECK-NEXT: [[J:%.*]] = call noundef i32 @_ZN15UnsignedWrappercvjEv(%struct.UnsignedWrapper* {{[^,]*}} %j) + // CHECK-NEXT: [[J:%.*]] = call i32 @_ZN15UnsignedWrappercvjEv(%struct.UnsignedWrapper* {{[^,]*}} %j) // CHECK-NEXT: [[J_SUB:%.*]] = sub i32 [[J]], 1 // CHECK-NEXT: [[J_SUB_EXT:%.*]] = zext i32 [[J_SUB]] to i64 // CHECK-NEXT: [[IDX1:%.*]] = mul i64 [[J_SUB_EXT]], 4 @@ -349,14 +349,14 @@ constexpr identmatrix_t identmatrix; void test_constexpr1(matrix_type &m) { // CHECK-LABEL: define{{.*}} void @_Z15test_constexpr1Ru11matrix_typeILm4ELm4EfE( // CHECK: [[MAT:%.*]] = load <16 x float>, <16 x float>* {{.*}}, align 4 - // CHECK-NEXT: [[IM:%.*]] = call noundef <16 x float> @_ZNK13identmatrix_tcvu11matrix_typeIXT0_EXT0_ET_EIfLj4EEEv(%struct.identmatrix_t* {{[^,]*}} @_ZL11identmatrix) + // CHECK-NEXT: [[IM:%.*]] = call <16 x float> @_ZNK13identmatrix_tcvu11matrix_typeIXT0_EXT0_ET_EIfLj4EEEv(%struct.identmatrix_t* {{[^,]*}} @_ZL11identmatrix) // CHECK-NEXT: [[ADD:%.*]] = fadd <16 x float> [[MAT]], [[IM]] // CHECK-NEXT: [[MAT_ADDR:%.*]] = load [16 x float]*, [16 x float]** %m.addr, align 8 // CHECK-NEXT: [[MAT_ADDR2:%.*]] = bitcast [16 x float]* [[MAT_ADDR]] to <16 x float>* // CHECK-NEXT: store <16 x float> [[ADD]], <16 x float>* [[MAT_ADDR2]], align 4 // CHECK-NEXT: ret voi - // CHECK-LABEL: define linkonce_odr noundef <16 x float> @_ZNK13identmatrix_tcvu11matrix_typeIXT0_EXT0_ET_EIfLj4EEEv( + // CHECK-LABEL: define linkonce_odr <16 x float> @_ZNK13identmatrix_tcvu11matrix_typeIXT0_EXT0_ET_EIfLj4EEEv( // CHECK-LABEL: for.body: ; preds = %for.cond // CHECK-NEXT: [[I:%.*]] = load i32, i32* %i, align 4 // CHECK-NEXT: [[I_EXT:%.*]] = zext i32 [[I]] to i64 @@ -376,7 +376,7 @@ void test_constexpr1(matrix_type &m) { void test_constexpr2(matrix_type &m) { // CHECK-LABEL: define{{.*}} void @_Z15test_constexpr2Ru11matrix_typeILm5ELm5EiE( - // CHECK: [[IM:%.*]] = call noundef <25 x i32> @_ZNK13identmatrix_tcvu11matrix_typeIXT0_EXT0_ET_EIiLj5EEEv(%struct.identmatrix_t* {{[^,]*}} @_ZL11identmatrix) + // CHECK: [[IM:%.*]] = call <25 x i32> @_ZNK13identmatrix_tcvu11matrix_typeIXT0_EXT0_ET_EIiLj5EEEv(%struct.identmatrix_t* {{[^,]*}} @_ZL11identmatrix) // CHECK: [[MAT:%.*]] = load <25 x i32>, <25 x i32>* {{.*}}, align 4 // CHECK-NEXT: [[SUB:%.*]] = sub <25 x i32> [[IM]], [[MAT]] // CHECK-NEXT: [[SUB2:%.*]] = add <25 x i32> [[SUB]], @@ -386,7 +386,7 @@ void test_constexpr2(matrix_type &m) { // CHECK-NEXT: ret void // - // CHECK-LABEL: define linkonce_odr noundef <25 x i32> @_ZNK13identmatrix_tcvu11matrix_typeIXT0_EXT0_ET_EIiLj5EEEv( + // CHECK-LABEL: define linkonce_odr <25 x i32> @_ZNK13identmatrix_tcvu11matrix_typeIXT0_EXT0_ET_EIiLj5EEEv( // CHECK-LABEL: for.body: ; preds = %for.cond // CHECK-NEXT: [[I:%.*]] = load i32, i32* %i, align 4 // CHECK-NEXT: [[I_EXT:%.*]] = zext i32 [[I]] to i64 diff --git a/clang/test/CodeGenCXX/matrix-type.cpp b/clang/test/CodeGenCXX/matrix-type.cpp index 8be81e97567e8d7411923b798949867348ededa7..9e715e10ce1c6f7e7d09241db8031dcee8519649 100644 --- a/clang/test/CodeGenCXX/matrix-type.cpp +++ b/clang/test/CodeGenCXX/matrix-type.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -fenable-matrix -triple x86_64-apple-darwin %s -emit-llvm -disable-llvm-passes -o - -std=c++17 | FileCheck %s +// RUN: %clang_cc1 -fenable-matrix -triple x86_64-apple-darwin %s -emit-llvm -disable-llvm-passes -o - -std=c++17 | FileCheck %s typedef double dx5x5_t __attribute__((matrix_type(5, 5))); typedef float fx3x4_t __attribute__((matrix_type(3, 4))); diff --git a/clang/test/CodeGenCXX/member-expr-references-variable.cpp b/clang/test/CodeGenCXX/member-expr-references-variable.cpp index 4001efe2a6e58c96a2a0fca4aa50281061a63d14..32bf9320d0edd2df12c992da64c4709797af719a 100644 --- a/clang/test/CodeGenCXX/member-expr-references-variable.cpp +++ b/clang/test/CodeGenCXX/member-expr-references-variable.cpp @@ -21,22 +21,22 @@ Struct *getPtr(); void scalarStaticVariableInMemberExpr(Struct *ptr, Struct &ref) { use(1, Struct::name); -// CHECK: call void @_Z3useiPKc(i32 noundef 1, i8* noundef getelementptr inbounds ([4 x i8], [4 x i8]* @[[STR]], i32 0, i32 0)) +// CHECK: call void @_Z3useiPKc(i32 1, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @[[STR]], i32 0, i32 0)) Struct s; use(2, s.name); -// CHECK: call void @_Z3useiPKc(i32 noundef 2, i8* noundef getelementptr inbounds ([4 x i8], [4 x i8]* @[[STR]], i32 0, i32 0)) +// CHECK: call void @_Z3useiPKc(i32 2, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @[[STR]], i32 0, i32 0)) use(3, ptr->name); // CHECK: load %struct.Struct*, %struct.Struct** %{{.*}}, align 8 -// CHECK: call void @_Z3useiPKc(i32 noundef 3, i8* noundef getelementptr inbounds ([4 x i8], [4 x i8]* @[[STR]], i32 0, i32 0)) +// CHECK: call void @_Z3useiPKc(i32 3, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @[[STR]], i32 0, i32 0)) use(4, ref.name); // CHECK: load %struct.Struct*, %struct.Struct** %{{.*}}, align 8 -// CHECK: call void @_Z3useiPKc(i32 noundef 4, i8* noundef getelementptr inbounds ([4 x i8], [4 x i8]* @[[STR]], i32 0, i32 0)) +// CHECK: call void @_Z3useiPKc(i32 4, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @[[STR]], i32 0, i32 0)) use(5, Struct(2).name); -// CHECK: call void @_ZN6StructC1Ei(%struct.Struct* {{[^,]*}} %{{.*}}, i32 noundef 2) -// CHECK: call void @_Z3useiPKc(i32 noundef 5, i8* noundef getelementptr inbounds ([4 x i8], [4 x i8]* @[[STR]], i32 0, i32 0)) +// CHECK: call void @_ZN6StructC1Ei(%struct.Struct* {{[^,]*}} %{{.*}}, i32 2) +// CHECK: call void @_Z3useiPKc(i32 5, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @[[STR]], i32 0, i32 0)) use(6, getPtr()->name); -// CHECK: call noundef %struct.Struct* @_Z6getPtrv() -// CHECK: call void @_Z3useiPKc(i32 noundef 6, i8* noundef getelementptr inbounds ([4 x i8], [4 x i8]* @[[STR]], i32 0, i32 0)) +// CHECK: call %struct.Struct* @_Z6getPtrv() +// CHECK: call void @_Z3useiPKc(i32 6, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @[[STR]], i32 0, i32 0)) } void use(int n, __complex float v); @@ -47,58 +47,58 @@ void complexStaticVariableInMemberExpr(Struct *ptr, Struct &ref) { // CHECK: store float 0.000000e+00, float* %[[coerce0]].{{.*}}, align 4 // CHECK: %[[cast0:.*]] = bitcast { float, float }* %[[coerce0]] to <2 x float>* // CHECK: %[[vector0:.*]] = load <2 x float>, <2 x float>* %[[cast0]], align 4 -// CHECK: call void @_Z3useiCf(i32 noundef 1, <2 x float> noundef %[[vector0]]) +// CHECK: call void @_Z3useiCf(i32 1, <2 x float> %[[vector0]]) Struct s; use(2, s.complexValue); // CHECK: store float 4.200000e+01, float* %[[coerce1:.*]].{{.*}}, align 4 // CHECK: store float 0.000000e+00, float* %[[coerce1]].{{.*}}, align 4 // CHECK: %[[cast1:.*]] = bitcast { float, float }* %[[coerce1]] to <2 x float>* // CHECK: %[[vector1:.*]] = load <2 x float>, <2 x float>* %[[cast1]], align 4 -// CHECK: call void @_Z3useiCf(i32 noundef 2, <2 x float> noundef %[[vector1]]) +// CHECK: call void @_Z3useiCf(i32 2, <2 x float> %[[vector1]]) use(3, ptr->complexValue); // CHECK: load %struct.Struct*, %struct.Struct** %{{.*}}, align 8 // CHECK: store float 4.200000e+01, float* %[[coerce2:.*]].{{.*}}, align 4 // CHECK: store float 0.000000e+00, float* %[[coerce2]].{{.*}}, align 4 // CHECK: %[[cast2:.*]] = bitcast { float, float }* %[[coerce2]] to <2 x float>* // CHECK: %[[vector2:.*]] = load <2 x float>, <2 x float>* %[[cast2]], align 4 -// CHECK: call void @_Z3useiCf(i32 noundef 3, <2 x float> noundef %[[vector2]]) +// CHECK: call void @_Z3useiCf(i32 3, <2 x float> %[[vector2]]) use(4, ref.complexValue); // CHECK: load %struct.Struct*, %struct.Struct** %{{.*}}, align 8 // CHECK: store float 4.200000e+01, float* %[[coerce3:.*]].{{.*}}, align 4 // CHECK: store float 0.000000e+00, float* %[[coerce3]].{{.*}}, align 4 // CHECK: %[[cast3:.*]] = bitcast { float, float }* %[[coerce3]] to <2 x float>* // CHECK: %[[vector3:.*]] = load <2 x float>, <2 x float>* %[[cast3]], align 4 -// CHECK: call void @_Z3useiCf(i32 noundef 4, <2 x float> noundef %[[vector3]]) +// CHECK: call void @_Z3useiCf(i32 4, <2 x float> %[[vector3]]) use(5, Struct(2).complexValue); -// CHECK: call void @_ZN6StructC1Ei(%struct.Struct* {{[^,]*}} %{{.*}}, i32 noundef 2) +// CHECK: call void @_ZN6StructC1Ei(%struct.Struct* {{[^,]*}} %{{.*}}, i32 2) // CHECK: store float 4.200000e+01, float* %[[coerce4:.*]].{{.*}}, align 4 // CHECK: store float 0.000000e+00, float* %[[coerce4]].{{.*}}, align 4 // CHECK: %[[cast4:.*]] = bitcast { float, float }* %[[coerce4]] to <2 x float>* // CHECK: %[[vector4:.*]] = load <2 x float>, <2 x float>* %[[cast4]], align 4 -// CHECK: call void @_Z3useiCf(i32 noundef 5, <2 x float> noundef %[[vector4]]) +// CHECK: call void @_Z3useiCf(i32 5, <2 x float> %[[vector4]]) use(6, getPtr()->complexValue); -// CHECK: call noundef %struct.Struct* @_Z6getPtrv() +// CHECK: call %struct.Struct* @_Z6getPtrv() // CHECK: store float 4.200000e+01, float* %[[coerce5:.*]].{{.*}}, align 4 // CHECK: store float 0.000000e+00, float* %[[coerce5]].{{.*}}, align 4 // CHECK: %[[cast5:.*]] = bitcast { float, float }* %[[coerce5]] to <2 x float>* // CHECK: %[[vector5:.*]] = load <2 x float>, <2 x float>* %[[cast5]], align 4 -// CHECK: call void @_Z3useiCf(i32 noundef 6, <2 x float> noundef %[[vector5]]) +// CHECK: call void @_Z3useiCf(i32 6, <2 x float> %[[vector5]]) } void aggregateRefInMemberExpr(Struct *ptr, Struct &ref) { use(1, Struct::agg.x); // CHECK: %[[value0:.*]] = load i8*, i8** getelementptr inbounds (%struct.Agg, %struct.Agg* @_ZGRN6Struct3aggE_, i32 0, i32 0), align 8 -// CHECK: call void @_Z3useiPKc(i32 noundef 1, i8* noundef %[[value0]]) +// CHECK: call void @_Z3useiPKc(i32 1, i8* %[[value0]]) Struct s; use(2, s.agg.x); // CHECK: %[[value1:.*]] = load i8*, i8** getelementptr inbounds (%struct.Agg, %struct.Agg* @_ZGRN6Struct3aggE_, i32 0, i32 0), align 8 -// CHECK: call void @_Z3useiPKc(i32 noundef 2, i8* noundef %[[value1]]) +// CHECK: call void @_Z3useiPKc(i32 2, i8* %[[value1]]) use(3, ptr->agg.x); // CHECK: load %struct.Struct*, %struct.Struct** %{{.*}}, align 8 // CHECK: %[[value2:.*]] = load i8*, i8** getelementptr inbounds (%struct.Agg, %struct.Agg* @_ZGRN6Struct3aggE_, i32 0, i32 0), align 8 -// CHECK: call void @_Z3useiPKc(i32 noundef 3, i8* noundef %[[value2]]) +// CHECK: call void @_Z3useiPKc(i32 3, i8* %[[value2]]) use(4, ref.agg.x); // CHECK: load %struct.Struct*, %struct.Struct** %{{.*}}, align 8 // CHECK: %[[value3:.*]] = load i8*, i8** getelementptr inbounds (%struct.Agg, %struct.Agg* @_ZGRN6Struct3aggE_, i32 0, i32 0), align 8 -// CHECK: call void @_Z3useiPKc(i32 noundef 4, i8* noundef %[[value3]]) +// CHECK: call void @_Z3useiPKc(i32 4, i8* %[[value3]]) } diff --git a/clang/test/CodeGenCXX/member-expressions.cpp b/clang/test/CodeGenCXX/member-expressions.cpp index d80cfd9c75997c47746cab1345a090acccf458fd..05a49502abd9722d673741b365ff84e683673652 100644 --- a/clang/test/CodeGenCXX/member-expressions.cpp +++ b/clang/test/CodeGenCXX/member-expressions.cpp @@ -29,7 +29,7 @@ A *g(); void f(A *a) { A::E e1 = a->Foo; - // CHECK: call noundef %struct.A* @_Z1gv() + // CHECK: call %struct.A* @_Z1gv() A::E e2 = g()->Foo; // CHECK: call void @_ZN1AC1Ev( // CHECK: call void @_ZN1AD1Ev( diff --git a/clang/test/CodeGenCXX/member-function-pointer-calls.cpp b/clang/test/CodeGenCXX/member-function-pointer-calls.cpp index 0ddd037d92cb28cdff3a44fd921737c6d49f5dc7..361f7a5e81d8e2defcaa02420a1dcc267770c14c 100644 --- a/clang/test/CodeGenCXX/member-function-pointer-calls.cpp +++ b/clang/test/CodeGenCXX/member-function-pointer-calls.cpp @@ -1,10 +1,8 @@ -// RUN: %clang_cc1 %s -triple=x86_64-apple-darwin10 -emit-llvm -O3 -fno-experimental-new-pass-manager -o - | FileCheck %s -// RUN: %clang_cc1 %s -triple=x86_64-apple-darwin10 -emit-llvm -O3 -fexperimental-new-pass-manager -o - | FileCheck %s +// RUN: %clang_cc1 %s -triple=x86_64-apple-darwin10 -emit-llvm -O3 -o - | FileCheck %s /// Check that we pass the member pointers indirectly for MinGW64 // RUN: %clang_cc1 %s -triple=x86_64-windows-gnu -emit-llvm -o - | FileCheck %s -check-prefix MINGW64 /// We should be able to optimize calls via the indirectly passed member pointers -// RUN: %clang_cc1 %s -triple=x86_64-windows-gnu -emit-llvm -O3 -fno-experimental-new-pass-manager -o - | FileCheck %s -// RUN: %clang_cc1 %s -triple=x86_64-windows-gnu -emit-llvm -O3 -fexperimental-new-pass-manager -o - | FileCheck %s +// RUN: %clang_cc1 %s -triple=x86_64-windows-gnu -emit-llvm -O3 -o - | FileCheck %s struct A { virtual int vf1() { return 1; } virtual int vf2() { return 2; } @@ -17,8 +15,8 @@ int f(A* a, int (A::*fp)()) { // CHECK-LABEL: define{{.*}} i32 @_Z2g1v() // CHECK-NOT: } // CHECK: ret i32 1 -// MINGW64-LABEL: define dso_local noundef i32 @_Z2g1v() -// MINGW64: call noundef i32 @_Z1fP1AMS_FivE(%struct.A* noundef %{{.*}}, { i64, i64 }* noundef %{{.*}}) +// MINGW64-LABEL: define dso_local i32 @_Z2g1v() +// MINGW64: call i32 @_Z1fP1AMS_FivE(%struct.A* %{{.*}}, { i64, i64 }* %{{.*}}) int g1() { A a; return f(&a, &A::vf1); @@ -27,8 +25,8 @@ int g1() { // CHECK-LABEL: define{{.*}} i32 @_Z2g2v() // CHECK-NOT: } // CHECK: ret i32 2 -// MINGW64-LABEL: define dso_local noundef i32 @_Z2g2v() -// MINGW64: call noundef i32 @_Z1fP1AMS_FivE(%struct.A* noundef %{{.*}}, { i64, i64 }* noundef %{{.*}}) +// MINGW64-LABEL: define dso_local i32 @_Z2g2v() +// MINGW64: call i32 @_Z1fP1AMS_FivE(%struct.A* %{{.*}}, { i64, i64 }* %{{.*}}) int g2() { A a; return f(&a, &A::vf2); diff --git a/clang/test/CodeGenCXX/member-init-assignment.cpp b/clang/test/CodeGenCXX/member-init-assignment.cpp index 966d415ac97dc34e37997eeee96b897b1c5131da..288f860467643603ee14aac745500c4a4cd0afec 100644 --- a/clang/test/CodeGenCXX/member-init-assignment.cpp +++ b/clang/test/CodeGenCXX/member-init-assignment.cpp @@ -10,7 +10,7 @@ struct Foo { Foo::Foo(unsigned arg) : file_id(arg = 42) { } -// CHECK: define {{.*}} @_ZN3FooC2Ej(%struct.Foo* {{[^,]*}} %this, i32 noundef %arg) unnamed_addr +// CHECK: define {{.*}} @_ZN3FooC2Ej(%struct.Foo* {{[^,]*}} %this, i32 %arg) unnamed_addr // CHECK: [[ARG:%.*]] = alloca i32 // CHECK: store i32 42, i32* [[ARG]] // CHECK: store i32 42, i32* %{{.*}} diff --git a/clang/test/CodeGenCXX/member-templates.cpp b/clang/test/CodeGenCXX/member-templates.cpp index 9dfeeb57b45319a134ed9faaca2a2f8e74919f69..59514ed6fbe9feb82e9d7df4a336cd20887f7ffd 100644 --- a/clang/test/CodeGenCXX/member-templates.cpp +++ b/clang/test/CodeGenCXX/member-templates.cpp @@ -15,8 +15,8 @@ struct B { template B::B(T) {} -// CHECK-LABEL: define weak_odr void @_ZN1BC2IiEET_(%struct.B* {{[^,]*}} %this, i32 noundef %0) unnamed_addr -// CHECK-LABEL: define weak_odr void @_ZN1BC1IiEET_(%struct.B* {{[^,]*}} %this, i32 noundef %0) unnamed_addr +// CHECK-LABEL: define weak_odr void @_ZN1BC2IiEET_(%struct.B* {{[^,]*}} %this, i32 %0) unnamed_addr +// CHECK-LABEL: define weak_odr void @_ZN1BC1IiEET_(%struct.B* {{[^,]*}} %this, i32 %0) unnamed_addr template B::B(int); template diff --git a/clang/test/CodeGenCXX/merge-functions.cpp b/clang/test/CodeGenCXX/merge-functions.cpp index 42d57d7db811c6920012d84a30ddda79417b01cf..892234ceedd3767bb0f6fe2b822b7067abdded05 100644 --- a/clang/test/CodeGenCXX/merge-functions.cpp +++ b/clang/test/CodeGenCXX/merge-functions.cpp @@ -1,8 +1,6 @@ // REQUIRES: x86-registered-target -// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -O0 -fno-experimental-new-pass-manager -fmerge-functions -emit-llvm -o - -x c++ < %s | FileCheck %s -implicit-check-not=_ZN1A1gEiPi -// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -O1 -fno-experimental-new-pass-manager -fmerge-functions -emit-llvm -o - -x c++ < %s | FileCheck %s -implicit-check-not=_ZN1A1gEiPi -// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -O0 -fexperimental-new-pass-manager -fmerge-functions -emit-llvm -o - -x c++ < %s | FileCheck %s -implicit-check-not=_ZN1A1gEiPi -// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -O1 -fexperimental-new-pass-manager -fmerge-functions -emit-llvm -o - -x c++ < %s | FileCheck %s -implicit-check-not=_ZN1A1gEiPi +// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -O0 -fmerge-functions -emit-llvm -o - -x c++ < %s | FileCheck %s -implicit-check-not=_ZN1A1gEiPi +// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -O1 -fmerge-functions -emit-llvm -o - -x c++ < %s | FileCheck %s -implicit-check-not=_ZN1A1gEiPi // Basic functionality test. Function merging doesn't kick in on functions that // are too simple. diff --git a/clang/test/CodeGenCXX/microsoft-abi-arg-order.cpp b/clang/test/CodeGenCXX/microsoft-abi-arg-order.cpp index 607ac14d4133b6f5457c95eca75964e710d88712..215a39ec7d489ca16969157e7208caaa5ea1ebd8 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-arg-order.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-arg-order.cpp @@ -24,7 +24,7 @@ void foo(A a, A b, A c) { // X86: ret void // X64-LABEL: define dso_local void @"?foo@@YAXUA@@00@Z" -// X64: (%struct.A* noundef %[[a:[^,]*]], %struct.A* noundef %[[b:[^,]*]], %struct.A* noundef %[[c:[^)]*]]) +// X64: (%struct.A* %[[a:[^,]*]], %struct.A* %[[b:[^,]*]], %struct.A* %[[c:[^)]*]]) // X64: call void @"??1A@@QEAA@XZ"(%struct.A* {{[^,]*}} %[[a]]) // X64: call void @"??1A@@QEAA@XZ"(%struct.A* {{[^,]*}} %[[b]]) // X64: call void @"??1A@@QEAA@XZ"(%struct.A* {{[^,]*}} %[[c]]) @@ -42,11 +42,11 @@ void call_foo() { // X86: call i8* @llvm.stacksave() // X86: %[[argmem:[^ ]*]] = alloca inalloca [[argmem_ty]] // X86: %[[arg3:[^ ]*]] = getelementptr inbounds [[argmem_ty]], [[argmem_ty]]* %[[argmem]], i32 0, i32 2 -// X86: call x86_thiscallcc noundef %struct.A* @"??0A@@QAE@H@Z"(%struct.A* {{[^,]*}} %[[arg3]], i32 noundef 3) +// X86: call x86_thiscallcc %struct.A* @"??0A@@QAE@H@Z"(%struct.A* {{[^,]*}} %[[arg3]], i32 3) // X86: %[[arg2:[^ ]*]] = getelementptr inbounds [[argmem_ty]], [[argmem_ty]]* %[[argmem]], i32 0, i32 1 -// X86: invoke x86_thiscallcc noundef %struct.A* @"??0A@@QAE@H@Z"(%struct.A* {{[^,]*}} %[[arg2]], i32 noundef 2) +// X86: invoke x86_thiscallcc %struct.A* @"??0A@@QAE@H@Z"(%struct.A* {{[^,]*}} %[[arg2]], i32 2) // X86: %[[arg1:[^ ]*]] = getelementptr inbounds [[argmem_ty]], [[argmem_ty]]* %[[argmem]], i32 0, i32 0 -// X86: invoke x86_thiscallcc noundef %struct.A* @"??0A@@QAE@H@Z"(%struct.A* {{[^,]*}} %[[arg1]], i32 noundef 1) +// X86: invoke x86_thiscallcc %struct.A* @"??0A@@QAE@H@Z"(%struct.A* {{[^,]*}} %[[arg1]], i32 1) // X86: call void @"?foo@@YAXUA@@00@Z"([[argmem_ty]]* inalloca([[argmem_ty]]) %[[argmem]]) // X86: call void @llvm.stackrestore // X86: ret void @@ -60,11 +60,11 @@ void call_foo() { // X86: call x86_thiscallcc void @"??1A@@QAE@XZ"(%struct.A* {{[^,]*}} %[[arg3]]) // X64-LABEL: define dso_local void @"?call_foo@@YAXXZ"() -// X64: call noundef %struct.A* @"??0A@@QEAA@H@Z"(%struct.A* {{[^,]*}} %[[arg3:[^,]*]], i32 noundef 3) -// X64: invoke noundef %struct.A* @"??0A@@QEAA@H@Z"(%struct.A* {{[^,]*}} %[[arg2:[^,]*]], i32 noundef 2) -// X64: invoke noundef %struct.A* @"??0A@@QEAA@H@Z"(%struct.A* {{[^,]*}} %[[arg1:[^,]*]], i32 noundef 1) +// X64: call %struct.A* @"??0A@@QEAA@H@Z"(%struct.A* {{[^,]*}} %[[arg3:[^,]*]], i32 3) +// X64: invoke %struct.A* @"??0A@@QEAA@H@Z"(%struct.A* {{[^,]*}} %[[arg2:[^,]*]], i32 2) +// X64: invoke %struct.A* @"??0A@@QEAA@H@Z"(%struct.A* {{[^,]*}} %[[arg1:[^,]*]], i32 1) // X64: call void @"?foo@@YAXUA@@00@Z" -// X64: (%struct.A* noundef %[[arg1]], %struct.A* noundef %[[arg2]], %struct.A* noundef %[[arg3]]) +// X64: (%struct.A* %[[arg1]], %struct.A* %[[arg2]], %struct.A* %[[arg3]]) // X64: ret void // // lpad2: diff --git a/clang/test/CodeGenCXX/microsoft-abi-array-cookies.cpp b/clang/test/CodeGenCXX/microsoft-abi-array-cookies.cpp index f83eba4896568cb912333c5d00badab35bd7d8c6..c500a83a198cd85f9a7ff6ef4746804a6b41542a 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-array-cookies.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-array-cookies.cpp @@ -7,7 +7,7 @@ struct ClassWithoutDtor { void check_array_no_cookies() { // CHECK: define dso_local void @"?check_array_no_cookies@@YAXXZ"() [[NUW:#[0-9]+]] -// CHECK: call noalias noundef nonnull i8* @"??_U@YAPAXI@Z"(i32 noundef 42) +// CHECK: call noalias nonnull i8* @"??_U@YAPAXI@Z"(i32 42) ClassWithoutDtor *array = new ClassWithoutDtor[42]; // CHECK: call void @"??_V@YAXPAX@Z"( @@ -24,7 +24,7 @@ void check_array_cookies_simple() { // CHECK: define {{.*}} @"?check_array_cookies_simple@@YAXXZ"() ClassWithDtor *array = new ClassWithDtor[42]; -// CHECK: [[ALLOCATED:%.*]] = call noalias noundef nonnull i8* @"??_U@YAPAXI@Z"(i32 noundef 46) +// CHECK: [[ALLOCATED:%.*]] = call noalias nonnull i8* @"??_U@YAPAXI@Z"(i32 46) // 46 = 42 + size of cookie (4) // CHECK: [[COOKIE:%.*]] = bitcast i8* [[ALLOCATED]] to i32* // CHECK: store i32 42, i32* [[COOKIE]] @@ -46,7 +46,7 @@ struct __attribute__((aligned(8))) ClassWithAlignment { void check_array_cookies_aligned() { // CHECK: define {{.*}} @"?check_array_cookies_aligned@@YAXXZ"() ClassWithAlignment *array = new ClassWithAlignment[42]; -// CHECK: [[ALLOCATED:%.*]] = call noalias noundef nonnull i8* @"??_U@YAPAXI@Z"(i32 noundef 344) +// CHECK: [[ALLOCATED:%.*]] = call noalias nonnull i8* @"??_U@YAPAXI@Z"(i32 344) // 344 = 42*8 + size of cookie (8, due to alignment) // CHECK: [[COOKIE:%.*]] = bitcast i8* [[ALLOCATED]] to i32* // CHECK: store i32 42, i32* [[COOKIE]] @@ -63,7 +63,7 @@ struct S { char x[42]; void operator delete[](void *p, __SIZE_TYPE__); // CHECK-LABEL: define dso_local void @"?delete_s@PR23990@@YAXPAUS@1@@Z"( - // CHECK: call void @"??_VS@PR23990@@SAXPAXI@Z"(i8* noundef {{.*}}, i32 noundef 42) + // CHECK: call void @"??_VS@PR23990@@SAXPAXI@Z"(i8* {{.*}}, i32 42) }; void delete_s(S *s) { delete[] s; } } diff --git a/clang/test/CodeGenCXX/microsoft-abi-byval-sret.cpp b/clang/test/CodeGenCXX/microsoft-abi-byval-sret.cpp index 1e3e16814c6d666b4c7952245bfa79400aadd82d..adf3921f71156984b9f4c722202e6411e397ce92 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-byval-sret.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-byval-sret.cpp @@ -19,7 +19,7 @@ A B::foo(A x) { } // CHECK-LABEL: define dso_local x86_thiscallcc %struct.A* @"?foo@B@@QAE?AUA@@U2@@Z" -// CHECK: (%struct.B* noundef %this, <{ %struct.A*, %struct.A }>* inalloca(<{ %struct.A*, %struct.A }>) %0) +// CHECK: (%struct.B* %this, <{ %struct.A*, %struct.A }>* inalloca(<{ %struct.A*, %struct.A }>) %0) // CHECK: getelementptr inbounds <{ %struct.A*, %struct.A }>, <{ %struct.A*, %struct.A }>* %{{.*}}, i32 0, i32 0 // CHECK: load %struct.A*, %struct.A** // CHECK: ret %struct.A* @@ -49,7 +49,7 @@ A B::qux(A x) { } // CHECK-LABEL: define dso_local x86_fastcallcc void @"?qux@B@@QAI?AUA@@U2@@Z" -// CHECK: (%struct.B* inreg noundef %this, %struct.A* inreg noalias sret(%struct.A) align 4 %agg.result, <{ %struct.A }>* inalloca(<{ %struct.A }>) %0) +// CHECK: (%struct.B* inreg %this, %struct.A* inreg noalias sret(%struct.A) align 4 %agg.result, <{ %struct.A }>* inalloca(<{ %struct.A }>) %0) // CHECK: ret void int main() { @@ -61,10 +61,10 @@ int main() { } // CHECK: call x86_thiscallcc %struct.A* @"?foo@B@@QAE?AUA@@U2@@Z" -// CHECK: (%struct.B* noundef %{{[^,]*}}, <{ %struct.A*, %struct.A }>* inalloca(<{ %struct.A*, %struct.A }>) %{{[^,]*}}) +// CHECK: (%struct.B* %{{[^,]*}}, <{ %struct.A*, %struct.A }>* inalloca(<{ %struct.A*, %struct.A }>) %{{[^,]*}}) // CHECK: call %struct.A* @"?bar@B@@QAA?AUA@@U2@@Z" // CHECK: (<{ %struct.B*, %struct.A*, %struct.A }>* inalloca(<{ %struct.B*, %struct.A*, %struct.A }>) %{{[^,]*}}) // CHECK: call x86_stdcallcc %struct.A* @"?baz@B@@QAG?AUA@@U2@@Z" // CHECK: (<{ %struct.B*, %struct.A*, %struct.A }>* inalloca(<{ %struct.B*, %struct.A*, %struct.A }>) %{{[^,]*}}) // CHECK: call x86_fastcallcc void @"?qux@B@@QAI?AUA@@U2@@Z" -// CHECK: (%struct.B* inreg noundef %{{[^,]*}}, %struct.A* inreg sret(%struct.A) align 4 %{{.*}}, <{ %struct.A }>* inalloca(<{ %struct.A }>) %{{[^,]*}}) +// CHECK: (%struct.B* inreg %{{[^,]*}}, %struct.A* inreg sret(%struct.A) align 4 %{{.*}}, <{ %struct.A }>* inalloca(<{ %struct.A }>) %{{[^,]*}}) diff --git a/clang/test/CodeGenCXX/microsoft-abi-byval-thunks.cpp b/clang/test/CodeGenCXX/microsoft-abi-byval-thunks.cpp index 06c63de638222766cd230b82dbb91146c2bfa200..b329310dff51f69cea45b996f9ad06aa18e8d76d 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-byval-thunks.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-byval-thunks.cpp @@ -15,17 +15,17 @@ struct C : A, B { C(); virtual void foo(Agg x); }; C::C() {} // force emission // CHECK32-LABEL: define linkonce_odr dso_local x86_thiscallcc void @"?foo@C@byval_thunk@@W3AEXUAgg@2@@Z" -// CHECK32: (%"struct.byval_thunk::C"* noundef %this, <{ %"struct.byval_thunk::Agg" }>* inalloca(<{ %"struct.byval_thunk::Agg" }>) %0) +// CHECK32: (%"struct.byval_thunk::C"* %this, <{ %"struct.byval_thunk::Agg" }>* inalloca(<{ %"struct.byval_thunk::Agg" }>) %0) // CHECK32: getelementptr i8, i8* %{{.*}}, i32 -4 // CHECK32: musttail call x86_thiscallcc void @"?foo@C@byval_thunk@@UAEXUAgg@2@@Z" -// CHECK32: (%"struct.byval_thunk::C"* noundef %{{.*}}, <{ %"struct.byval_thunk::Agg" }>* inalloca(<{ %"struct.byval_thunk::Agg" }>) %0) +// CHECK32: (%"struct.byval_thunk::C"* %{{.*}}, <{ %"struct.byval_thunk::Agg" }>* inalloca(<{ %"struct.byval_thunk::Agg" }>) %0) // CHECK32-NEXT: ret void // CHECK64-LABEL: define linkonce_odr dso_local void @"?foo@C@byval_thunk@@W7EAAXUAgg@2@@Z" -// CHECK64: (%"struct.byval_thunk::C"* noundef %this, %"struct.byval_thunk::Agg"* noundef %x) +// CHECK64: (%"struct.byval_thunk::C"* %this, %"struct.byval_thunk::Agg"* %x) // CHECK64: getelementptr i8, i8* %{{.*}}, i32 -8 // CHECK64: call void @"?foo@C@byval_thunk@@UEAAXUAgg@2@@Z" -// CHECK64: (%"struct.byval_thunk::C"* {{[^,]*}} %{{.*}}, %"struct.byval_thunk::Agg"* noundef %x) +// CHECK64: (%"struct.byval_thunk::C"* {{[^,]*}} %{{.*}}, %"struct.byval_thunk::Agg"* %x) // CHECK64-NOT: call // CHECK64: ret void } @@ -54,10 +54,10 @@ C::C() {} // force emission // CHECK32-NEXT: ret void // CHECK64-LABEL: define linkonce_odr dso_local void @"?foo@C@stdcall_thunk@@W7EAAXUAgg@2@@Z" -// CHECK64: (%"struct.stdcall_thunk::C"* noundef %this, %"struct.stdcall_thunk::Agg"* noundef %x) +// CHECK64: (%"struct.stdcall_thunk::C"* %this, %"struct.stdcall_thunk::Agg"* %x) // CHECK64: getelementptr i8, i8* %{{.*}}, i32 -8 // CHECK64: call void @"?foo@C@stdcall_thunk@@UEAAXUAgg@2@@Z" -// CHECK64: (%"struct.stdcall_thunk::C"* {{[^,]*}} %{{.*}}, %"struct.stdcall_thunk::Agg"* noundef %x) +// CHECK64: (%"struct.stdcall_thunk::C"* {{[^,]*}} %{{.*}}, %"struct.stdcall_thunk::Agg"* %x) // CHECK64-NOT: call // CHECK64: ret void } @@ -86,10 +86,10 @@ C::C() {} // force emission // CHECK32-NEXT: ret %"struct.sret_thunk::Agg"* %[[rv]] // CHECK64-LABEL: define linkonce_odr dso_local void @"?foo@C@sret_thunk@@W7EAA?AUAgg@2@U32@@Z" -// CHECK64: (%"struct.sret_thunk::C"* noundef %this, %"struct.sret_thunk::Agg"* noalias sret(%"struct.sret_thunk::Agg") align 4 %agg.result, %"struct.sret_thunk::Agg"* noundef %x) +// CHECK64: (%"struct.sret_thunk::C"* %this, %"struct.sret_thunk::Agg"* noalias sret(%"struct.sret_thunk::Agg") align 4 %agg.result, %"struct.sret_thunk::Agg"* %x) // CHECK64: getelementptr i8, i8* %{{.*}}, i32 -8 // CHECK64: call void @"?foo@C@sret_thunk@@UEAA?AUAgg@2@U32@@Z" -// CHECK64: (%"struct.sret_thunk::C"* {{[^,]*}} %{{.*}}, %"struct.sret_thunk::Agg"* sret(%"struct.sret_thunk::Agg") align 4 %agg.result, %"struct.sret_thunk::Agg"* noundef %x) +// CHECK64: (%"struct.sret_thunk::C"* {{[^,]*}} %{{.*}}, %"struct.sret_thunk::Agg"* sret(%"struct.sret_thunk::Agg") align 4 %agg.result, %"struct.sret_thunk::Agg"* %x) // CHECK64-NOT: call // CHECK64: ret void } diff --git a/clang/test/CodeGenCXX/microsoft-abi-byval-vararg.cpp b/clang/test/CodeGenCXX/microsoft-abi-byval-vararg.cpp index 97c4193114e1e7fe899aea4d0ba03e506b4edd41..18333f36c239d4f5950ce5158e0d570d60d4ad80 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-byval-vararg.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-byval-vararg.cpp @@ -19,14 +19,14 @@ int foo(A a, ...) { return sum; } -// CHECK-LABEL: define dso_local noundef i32 @"?foo@@YAHUA@@ZZ"(<{ %struct.A }>* inalloca(<{ %struct.A }>) %0, ...) +// CHECK-LABEL: define dso_local i32 @"?foo@@YAHUA@@ZZ"(<{ %struct.A }>* inalloca(<{ %struct.A }>) %0, ...) int main() { return foo(A(3), 1, 2, 3); } -// CHECK-LABEL: define dso_local noundef i32 @main() +// CHECK-LABEL: define dso_local i32 @main() // CHECK: %[[argmem:[^ ]*]] = alloca inalloca <{ %struct.A, i32, i32, i32 }> -// CHECK: call noundef i32 {{.*bitcast.*}}@"?foo@@YAHUA@@ZZ"{{.*}}(<{ %struct.A, i32, i32, i32 }>* inalloca(<{ %struct.A, i32, i32, i32 }>) %[[argmem]]) +// CHECK: call i32 {{.*bitcast.*}}@"?foo@@YAHUA@@ZZ"{{.*}}(<{ %struct.A, i32, i32, i32 }>* inalloca(<{ %struct.A, i32, i32, i32 }>) %[[argmem]]) void varargs_zero(...); void varargs_one(int, ...); @@ -47,6 +47,6 @@ void call_var_args() { // CHECK: call void {{.*bitcast.*varargs_three.*}}(<{ i32, i32, i32, %struct.A }>* inalloca(<{ i32, i32, i32, %struct.A }>) %{{.*}}) // CHECK-LABEL: declare dso_local void @"?varargs_zero@@YAXZZ"(...) -// CHECK-LABEL: declare dso_local void @"?varargs_one@@YAXHZZ"(i32 noundef, ...) -// CHECK-LABEL: declare dso_local void @"?varargs_two@@YAXHHZZ"(i32 noundef, i32 noundef, ...) -// CHECK-LABEL: declare dso_local void @"?varargs_three@@YAXHHHZZ"(i32 noundef, i32 noundef, i32 noundef, ...) +// CHECK-LABEL: declare dso_local void @"?varargs_one@@YAXHZZ"(i32, ...) +// CHECK-LABEL: declare dso_local void @"?varargs_two@@YAXHHZZ"(i32, i32, ...) +// CHECK-LABEL: declare dso_local void @"?varargs_three@@YAXHHHZZ"(i32, i32, i32, ...) diff --git a/clang/test/CodeGenCXX/microsoft-abi-cdecl-method-sret.cpp b/clang/test/CodeGenCXX/microsoft-abi-cdecl-method-sret.cpp index b49f8834187ebbda34810c215adc6e40478d30e5..44c76e76ce17aa322fc171a368df306de65cced5 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-cdecl-method-sret.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-cdecl-method-sret.cpp @@ -19,9 +19,9 @@ S C::variadic_sret(const char *f, ...) { return S(); } S C::cdecl_sret() { return S(); } S C::byval_and_sret(S a) { return S(); } -// CHECK: define dso_local void @"?variadic_sret@C@@QAA?AUS@@PBDZZ"(%struct.C* {{[^,]*}} %this, %struct.S* noalias sret(%struct.S) align 4 %agg.result, i8* noundef %f, ...) +// CHECK: define dso_local void @"?variadic_sret@C@@QAA?AUS@@PBDZZ"(%struct.C* {{[^,]*}} %this, %struct.S* noalias sret(%struct.S) align 4 %agg.result, i8* %f, ...) // CHECK: define dso_local void @"?cdecl_sret@C@@QAA?AUS@@XZ"(%struct.C* {{[^,]*}} %this, %struct.S* noalias sret(%struct.S) align 4 %agg.result) -// CHECK: define dso_local void @"?byval_and_sret@C@@QAA?AUS@@U2@@Z"(%struct.C* {{[^,]*}} %this, %struct.S* noalias sret(%struct.S) align 4 %agg.result, %struct.S* noundef byval(%struct.S) align 4 %a) +// CHECK: define dso_local void @"?byval_and_sret@C@@QAA?AUS@@U2@@Z"(%struct.C* {{[^,]*}} %this, %struct.S* noalias sret(%struct.S) align 4 %agg.result, %struct.S* byval(%struct.S) align 4 %a) int main() { C c; @@ -29,7 +29,7 @@ int main() { c.cdecl_sret(); c.byval_and_sret(S()); } -// CHECK-LABEL: define dso_local noundef i32 @main() +// CHECK-LABEL: define dso_local i32 @main() // CHECK: call void {{.*}} @"?variadic_sret@C@@QAA?AUS@@PBDZZ" // CHECK: call void @"?cdecl_sret@C@@QAA?AUS@@XZ" // CHECK: call void @"?byval_and_sret@C@@QAA?AUS@@U2@@Z" @@ -41,4 +41,4 @@ struct A { S A::f(int x) { return S(); } -// CHECK-LABEL: define dso_local x86_fastcallcc void @"?f@A@@QAI?AUS@@H@Z"(%struct.A* inreg noundef %this, %struct.S* inreg noalias sret(%struct.S) align 4 %agg.result, i32 noundef %x) +// CHECK-LABEL: define dso_local x86_fastcallcc void @"?f@A@@QAI?AUS@@H@Z"(%struct.A* inreg %this, %struct.S* inreg noalias sret(%struct.S) align 4 %agg.result, i32 %x) diff --git a/clang/test/CodeGenCXX/microsoft-abi-dynamic-cast.cpp b/clang/test/CodeGenCXX/microsoft-abi-dynamic-cast.cpp index a7818a319e85872850d6335cb3dfbdf08ec531c3..a07114dce7d07fffd6f7801e8d7966d0c1151a39 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-dynamic-cast.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-dynamic-cast.cpp @@ -7,18 +7,18 @@ struct B : S, virtual V {}; struct T {}; T* test0() { return dynamic_cast((B*)0); } -// CHECK-LABEL: define dso_local noalias noundef %struct.T* @"?test0@@YAPAUT@@XZ"() +// CHECK-LABEL: define dso_local noalias %struct.T* @"?test0@@YAPAUT@@XZ"() // CHECK: ret %struct.T* null T* test1(V* x) { return &dynamic_cast(*x); } -// CHECK-LABEL: define dso_local noundef %struct.T* @"?test1@@YAPAUT@@PAUV@@@Z"(%struct.V* noundef %x) +// CHECK-LABEL: define dso_local %struct.T* @"?test1@@YAPAUT@@PAUV@@@Z"(%struct.V* %x) // CHECK: [[CAST:%.*]] = bitcast %struct.V* %x to i8* // CHECK-NEXT: [[CALL:%.*]] = call i8* @__RTDynamicCast(i8* [[CAST]], i32 0, i8* bitcast (%rtti.TypeDescriptor7* @"??_R0?AUV@@@8" to i8*), i8* bitcast (%rtti.TypeDescriptor7* @"??_R0?AUT@@@8" to i8*), i32 1) // CHECK-NEXT: [[RET:%.*]] = bitcast i8* [[CALL]] to %struct.T* // CHECK-NEXT: ret %struct.T* [[RET]] T* test2(A* x) { return &dynamic_cast(*x); } -// CHECK-LABEL: define dso_local noundef %struct.T* @"?test2@@YAPAUT@@PAUA@@@Z"(%struct.A* noundef %x) +// CHECK-LABEL: define dso_local %struct.T* @"?test2@@YAPAUT@@PAUA@@@Z"(%struct.A* %x) // CHECK: [[CAST:%.*]] = bitcast %struct.A* %x to i8* // CHECK-NEXT: [[VBPTRPTR:%.*]] = getelementptr %struct.A, %struct.A* %x, i32 0, i32 0 // CHECK-NEXT: [[VBTBL:%.*]] = load i32*, i32** [[VBPTRPTR]], align 4 @@ -30,7 +30,7 @@ T* test2(A* x) { return &dynamic_cast(*x); } // CHECK-NEXT: ret %struct.T* [[RET]] T* test3(B* x) { return &dynamic_cast(*x); } -// CHECK-LABEL: define dso_local noundef %struct.T* @"?test3@@YAPAUT@@PAUB@@@Z"(%struct.B* noundef %x) +// CHECK-LABEL: define dso_local %struct.T* @"?test3@@YAPAUT@@PAUB@@@Z"(%struct.B* %x) // CHECK: [[VOIDP:%.*]] = getelementptr %struct.B, %struct.B* %x, i32 0, i32 0, i32 0 // CHECK-NEXT: [[VBPTR:%.*]] = getelementptr inbounds i8, i8* [[VOIDP]], i32 4 // CHECK-NEXT: [[VBPTRPTR:%.*]] = bitcast i8* [[VBPTR:%.*]] to i32** @@ -44,14 +44,14 @@ T* test3(B* x) { return &dynamic_cast(*x); } // CHECK-NEXT: ret %struct.T* [[RET]] T* test4(V* x) { return dynamic_cast(x); } -// CHECK-LABEL: define dso_local noundef %struct.T* @"?test4@@YAPAUT@@PAUV@@@Z"(%struct.V* noundef %x) +// CHECK-LABEL: define dso_local %struct.T* @"?test4@@YAPAUT@@PAUV@@@Z"(%struct.V* %x) // CHECK: [[CAST:%.*]] = bitcast %struct.V* %x to i8* // CHECK-NEXT: [[CALL:%.*]] = call i8* @__RTDynamicCast(i8* [[CAST]], i32 0, i8* bitcast (%rtti.TypeDescriptor7* @"??_R0?AUV@@@8" to i8*), i8* bitcast (%rtti.TypeDescriptor7* @"??_R0?AUT@@@8" to i8*), i32 0) // CHECK-NEXT: [[RET:%.*]] = bitcast i8* [[CALL]] to %struct.T* // CHECK-NEXT: ret %struct.T* [[RET]] T* test5(A* x) { return dynamic_cast(x); } -// CHECK-LABEL: define dso_local noundef %struct.T* @"?test5@@YAPAUT@@PAUA@@@Z"(%struct.A* noundef %x) +// CHECK-LABEL: define dso_local %struct.T* @"?test5@@YAPAUT@@PAUA@@@Z"(%struct.A* %x) // CHECK: [[CHECK:%.*]] = icmp eq %struct.A* %x, null // CHECK-NEXT: br i1 [[CHECK]] // CHECK: [[VOIDP:%.*]] = bitcast %struct.A* %x to i8* @@ -67,7 +67,7 @@ T* test5(A* x) { return dynamic_cast(x); } // CHECK-NEXT: ret %struct.T* [[RET]] T* test6(B* x) { return dynamic_cast(x); } -// CHECK-LABEL: define dso_local noundef %struct.T* @"?test6@@YAPAUT@@PAUB@@@Z"(%struct.B* noundef %x) +// CHECK-LABEL: define dso_local %struct.T* @"?test6@@YAPAUT@@PAUB@@@Z"(%struct.B* %x) // CHECK: [[CHECK:%.*]] = icmp eq %struct.B* %x, null // CHECK-NEXT: br i1 [[CHECK]] // CHECK: [[CAST:%.*]] = getelementptr %struct.B, %struct.B* %x, i32 0, i32 0, i32 0 @@ -85,13 +85,13 @@ T* test6(B* x) { return dynamic_cast(x); } // CHECK-NEXT: ret %struct.T* [[RET]] void* test7(V* x) { return dynamic_cast(x); } -// CHECK-LABEL: define dso_local noundef i8* @"?test7@@YAPAXPAUV@@@Z"(%struct.V* noundef %x) +// CHECK-LABEL: define dso_local i8* @"?test7@@YAPAXPAUV@@@Z"(%struct.V* %x) // CHECK: [[CAST:%.*]] = bitcast %struct.V* %x to i8* // CHECK-NEXT: [[RET:%.*]] = call i8* @__RTCastToVoid(i8* [[CAST]]) // CHECK-NEXT: ret i8* [[RET]] void* test8(A* x) { return dynamic_cast(x); } -// CHECK-LABEL: define dso_local noundef i8* @"?test8@@YAPAXPAUA@@@Z"(%struct.A* noundef %x) +// CHECK-LABEL: define dso_local i8* @"?test8@@YAPAXPAUA@@@Z"(%struct.A* %x) // CHECK: [[CHECK:%.*]] = icmp eq %struct.A* %x, null // CHECK-NEXT: br i1 [[CHECK]] // CHECK: [[VOIDP:%.*]] = bitcast %struct.A* %x to i8* @@ -106,7 +106,7 @@ void* test8(A* x) { return dynamic_cast(x); } // CHECK-NEXT: ret i8* [[RET]] void* test9(B* x) { return dynamic_cast(x); } -// CHECK-LABEL: define dso_local noundef i8* @"?test9@@YAPAXPAUB@@@Z"(%struct.B* noundef %x) +// CHECK-LABEL: define dso_local i8* @"?test9@@YAPAXPAUB@@@Z"(%struct.B* %x) // CHECK: [[CHECK:%.*]] = icmp eq %struct.B* %x, null // CHECK-NEXT: br i1 [[CHECK]] // CHECK: [[CAST:%.*]] = getelementptr %struct.B, %struct.B* %x, i32 0, i32 0, i32 0 @@ -134,7 +134,7 @@ S3 *f(S2 &s) { Cleanup c; return dynamic_cast(&s); } -// CHECK-LABEL: define dso_local noundef %"struct.PR25606::S3"* @"?f@PR25606@@YAPAUS3@1@AAUS2@1@@Z"( +// CHECK-LABEL: define dso_local %"struct.PR25606::S3"* @"?f@PR25606@@YAPAUS3@1@AAUS2@1@@Z"( // CHECK: [[CALL:%.*]] = invoke i8* @__RTDynamicCast // CHECK: [[BC:%.*]] = bitcast i8* [[CALL]] to %"struct.PR25606::S3"* diff --git a/clang/test/CodeGenCXX/microsoft-abi-eh-catch.cpp b/clang/test/CodeGenCXX/microsoft-abi-eh-catch.cpp index b6c5b22b50cc0b68805e8b39ec85fc6c34d233d5..53f87177e700a9653aceca7dec8582882b32a92c 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-eh-catch.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-eh-catch.cpp @@ -57,7 +57,7 @@ extern "C" void catch_int() { // WIN64: %[[e_i8:[^ ]*]] = bitcast i32* %[[e_addr]] to i8* // WIN64-NOT: lifetime.start // WIN64: call void @handle_exception -// WIN64-SAME: (i8* noundef %[[e_i8]]) +// WIN64-SAME: (i8* %[[e_i8]]) // WIN64-NOT: lifetime.end // WIN64: catchret @@ -98,7 +98,7 @@ extern "C" void catch_a_byval() { // WIN64: %[[e_addr:[^ ]*]] = alloca %struct.A // WIN64: catchpad within %{{[^ ]*}} [%rtti.TypeDescriptor7* @"??_R0?AUA@@@8", i32 0, %struct.A* %[[e_addr]]] // WIN64: %[[e_i8:[^ ]*]] = bitcast %struct.A* %[[e_addr]] to i8* -// WIN64: call void @handle_exception(i8* noundef %[[e_i8]]) +// WIN64: call void @handle_exception(i8* %[[e_i8]]) // WIN64: catchret extern "C" void catch_a_ref() { @@ -114,7 +114,7 @@ extern "C" void catch_a_ref() { // WIN64: catchpad within %{{[^ ]*}} [%rtti.TypeDescriptor7* @"??_R0?AUA@@@8", i32 8, %struct.A** %[[e_addr]]] // WIN64: %[[eptr:[^ ]*]] = load %struct.A*, %struct.A** %[[e_addr]] // WIN64: %[[eptr_i8:[^ ]*]] = bitcast %struct.A* %[[eptr]] to i8* -// WIN64: call void @handle_exception(i8* noundef %[[eptr_i8]]) +// WIN64: call void @handle_exception(i8* %[[eptr_i8]]) // WIN64: catchret extern "C" void fn_with_exc_spec() throw(int) { diff --git a/clang/test/CodeGenCXX/microsoft-abi-eh-cleanups.cpp b/clang/test/CodeGenCXX/microsoft-abi-eh-cleanups.cpp index 5e4f8eabc0de6b62c6f41e04bcab428ab1937ebc..0b6b4385a35217ea1a84d39039c2bd9d3426ed32 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-eh-cleanups.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-eh-cleanups.cpp @@ -22,7 +22,7 @@ void HasEHCleanup() { // If this call throws, we have to cleanup the first temporary. // WIN32: invoke void @"?getA@@YA?AUA@@XZ"(%struct.A* sret(%struct.A) align 4 %{{.*}}) // If this call throws, we have to cleanup the stacksave. -// WIN32: call noundef i32 @"?TakesTwo@@YAHUA@@0@Z" +// WIN32: call i32 @"?TakesTwo@@YAHUA@@0@Z" // WIN32: call void @llvm.stackrestore // WIN32: ret void // @@ -37,24 +37,24 @@ int HasDeactivatedCleanups() { return TakesTwo((TakeRef(A()), A()), (TakeRef(A()), A())); } -// WIN32-LABEL: define dso_local noundef i32 @"?HasDeactivatedCleanups@@YAHXZ"() {{.*}} { +// WIN32-LABEL: define dso_local i32 @"?HasDeactivatedCleanups@@YAHXZ"() {{.*}} { // WIN32: %[[isactive:.*]] = alloca i1 // WIN32: call i8* @llvm.stacksave() // WIN32: %[[argmem:.*]] = alloca inalloca [[argmem_ty:<{ %struct.A, %struct.A }>]] // WIN32: %[[arg1:.*]] = getelementptr inbounds [[argmem_ty]], [[argmem_ty]]* %[[argmem]], i32 0, i32 1 -// WIN32: call x86_thiscallcc noundef %struct.A* @"??0A@@QAE@XZ" +// WIN32: call x86_thiscallcc %struct.A* @"??0A@@QAE@XZ" // WIN32: invoke void @"?TakeRef@@YAXABUA@@@Z" // -// WIN32: invoke x86_thiscallcc noundef %struct.A* @"??0A@@QAE@XZ"(%struct.A* {{[^,]*}} %[[arg1]]) +// WIN32: invoke x86_thiscallcc %struct.A* @"??0A@@QAE@XZ"(%struct.A* {{[^,]*}} %[[arg1]]) // WIN32: store i1 true, i1* %[[isactive]] // // WIN32: %[[arg0:.*]] = getelementptr inbounds [[argmem_ty]], [[argmem_ty]]* %[[argmem]], i32 0, i32 0 -// WIN32: invoke x86_thiscallcc noundef %struct.A* @"??0A@@QAE@XZ" +// WIN32: invoke x86_thiscallcc %struct.A* @"??0A@@QAE@XZ" // WIN32: invoke void @"?TakeRef@@YAXABUA@@@Z" -// WIN32: invoke x86_thiscallcc noundef %struct.A* @"??0A@@QAE@XZ" +// WIN32: invoke x86_thiscallcc %struct.A* @"??0A@@QAE@XZ" // WIN32: store i1 false, i1* %[[isactive]] // -// WIN32: invoke noundef i32 @"?TakesTwo@@YAHUA@@0@Z"([[argmem_ty]]* inalloca([[argmem_ty]]) %[[argmem]]) +// WIN32: invoke i32 @"?TakesTwo@@YAHUA@@0@Z"([[argmem_ty]]* inalloca([[argmem_ty]]) %[[argmem]]) // Destroy the two const ref temporaries. // WIN32: call x86_thiscallcc void @"??1A@@QAE@XZ"({{.*}}) // WIN32: call x86_thiscallcc void @"??1A@@QAE@XZ"({{.*}}) @@ -72,18 +72,18 @@ int HasConditionalCleanup(bool cond) { return (cond ? TakesTwo(A(), A()) : CouldThrow()); } -// WIN32-LABEL: define dso_local noundef i32 @"?HasConditionalCleanup@@YAH_N@Z"(i1 noundef zeroext %{{.*}}) {{.*}} { +// WIN32-LABEL: define dso_local i32 @"?HasConditionalCleanup@@YAH_N@Z"(i1 zeroext %{{.*}}) {{.*}} { // WIN32: store i1 false // WIN32: br i1 // WIN32: call i8* @llvm.stacksave() -// WIN32: call x86_thiscallcc noundef %struct.A* @"??0A@@QAE@XZ"(%struct.A* {{[^,]*}} %{{.*}}) +// WIN32: call x86_thiscallcc %struct.A* @"??0A@@QAE@XZ"(%struct.A* {{[^,]*}} %{{.*}}) // WIN32: store i1 true -// WIN32: invoke x86_thiscallcc noundef %struct.A* @"??0A@@QAE@XZ"(%struct.A* {{[^,]*}} %{{.*}}) -// WIN32: call noundef i32 @"?TakesTwo@@YAHUA@@0@Z" +// WIN32: invoke x86_thiscallcc %struct.A* @"??0A@@QAE@XZ"(%struct.A* {{[^,]*}} %{{.*}}) +// WIN32: call i32 @"?TakesTwo@@YAHUA@@0@Z" // // WIN32: call void @llvm.stackrestore // -// WIN32: call noundef i32 @"?CouldThrow@@YAHXZ"() +// WIN32: call i32 @"?CouldThrow@@YAHXZ"() // // Only one dtor in the invoke for arg1 // WIN32: call x86_thiscallcc void @"??1A@@QAE@XZ"({{.*}}) @@ -95,7 +95,7 @@ int HasConditionalDeactivatedCleanups(bool cond) { return (cond ? TakesTwo((TakeRef(A()), A()), (TakeRef(A()), A())) : CouldThrow()); } -// WIN32-O0-LABEL: define dso_local noundef i32 @"?HasConditionalDeactivatedCleanups@@YAH_N@Z"{{.*}} { +// WIN32-O0-LABEL: define dso_local i32 @"?HasConditionalDeactivatedCleanups@@YAH_N@Z"{{.*}} { // WIN32-O0: alloca i1 // WIN32-O0: %[[arg1_cond:.*]] = alloca i1 // Start all four cleanups as deactivated. @@ -105,20 +105,20 @@ int HasConditionalDeactivatedCleanups(bool cond) { // WIN32-O0: store i1 false // WIN32-O0: br i1 // True condition. -// WIN32-O0: call x86_thiscallcc noundef %struct.A* @"??0A@@QAE@XZ" +// WIN32-O0: call x86_thiscallcc %struct.A* @"??0A@@QAE@XZ" // WIN32-O0: store i1 true // WIN32-O0: invoke void @"?TakeRef@@YAXABUA@@@Z" -// WIN32-O0: invoke x86_thiscallcc noundef %struct.A* @"??0A@@QAE@XZ" +// WIN32-O0: invoke x86_thiscallcc %struct.A* @"??0A@@QAE@XZ" // WIN32-O0: store i1 true, i1* %[[arg1_cond]] -// WIN32-O0: invoke x86_thiscallcc noundef %struct.A* @"??0A@@QAE@XZ" +// WIN32-O0: invoke x86_thiscallcc %struct.A* @"??0A@@QAE@XZ" // WIN32-O0: store i1 true // WIN32-O0: invoke void @"?TakeRef@@YAXABUA@@@Z" -// WIN32-O0: invoke x86_thiscallcc noundef %struct.A* @"??0A@@QAE@XZ" +// WIN32-O0: invoke x86_thiscallcc %struct.A* @"??0A@@QAE@XZ" // WIN32-O0: store i1 true // WIN32-O0: store i1 false, i1* %[[arg1_cond]] -// WIN32-O0: invoke noundef i32 @"?TakesTwo@@YAHUA@@0@Z" +// WIN32-O0: invoke i32 @"?TakesTwo@@YAHUA@@0@Z" // False condition. -// WIN32-O0: invoke noundef i32 @"?CouldThrow@@YAHXZ"() +// WIN32-O0: invoke i32 @"?CouldThrow@@YAHXZ"() // Two normal cleanups for TakeRef args. // WIN32-O0: call x86_thiscallcc void @"??1A@@QAE@XZ"({{.*}}) // WIN32-O0-NOT: invoke x86_thiscallcc void @"??1A@@QAE@XZ" @@ -130,7 +130,7 @@ int HasConditionalDeactivatedCleanups(bool cond) { // WIN32-O0: call x86_thiscallcc void @"??1A@@QAE@XZ"({{.*}}) // WIN32-O0: } -// WIN32-O3-LABEL: define dso_local noundef i32 @"?HasConditionalDeactivatedCleanups@@YAH_N@Z"{{.*}} { +// WIN32-O3-LABEL: define dso_local i32 @"?HasConditionalDeactivatedCleanups@@YAH_N@Z"{{.*}} { // WIN32-O3: alloca i1 // WIN32-O3: alloca i1 // WIN32-O3: %[[arg1_cond:.*]] = alloca i1 @@ -143,20 +143,20 @@ int HasConditionalDeactivatedCleanups(bool cond) { // WIN32-O3: store i1 false // WIN32-O3: br i1 // True condition. -// WIN32-O3: call x86_thiscallcc noundef %struct.A* @"??0A@@QAE@XZ" +// WIN32-O3: call x86_thiscallcc %struct.A* @"??0A@@QAE@XZ" // WIN32-O3: store i1 true // WIN32-O3: invoke void @"?TakeRef@@YAXABUA@@@Z" -// WIN32-O3: invoke x86_thiscallcc noundef %struct.A* @"??0A@@QAE@XZ" +// WIN32-O3: invoke x86_thiscallcc %struct.A* @"??0A@@QAE@XZ" // WIN32-O3: store i1 true, i1* %[[arg1_cond]] -// WIN32-O3: invoke x86_thiscallcc noundef %struct.A* @"??0A@@QAE@XZ" +// WIN32-O3: invoke x86_thiscallcc %struct.A* @"??0A@@QAE@XZ" // WIN32-O3: store i1 true // WIN32-O3: invoke void @"?TakeRef@@YAXABUA@@@Z" -// WIN32-O3: invoke x86_thiscallcc noundef %struct.A* @"??0A@@QAE@XZ" +// WIN32-O3: invoke x86_thiscallcc %struct.A* @"??0A@@QAE@XZ" // WIN32-O3: store i1 true // WIN32-O3: store i1 false, i1* %[[arg1_cond]] -// WIN32-O3: invoke noundef i32 @"?TakesTwo@@YAHUA@@0@Z" +// WIN32-O3: invoke i32 @"?TakesTwo@@YAHUA@@0@Z" // False condition. -// WIN32-O3: invoke noundef i32 @"?CouldThrow@@YAHXZ"() +// WIN32-O3: invoke i32 @"?CouldThrow@@YAHXZ"() // Two normal cleanups for TakeRef args. // WIN32-O3: call x86_thiscallcc void @"??1A@@QAE@XZ"({{.*}}) // WIN32-O3-NOT: invoke x86_thiscallcc void @"??1A@@QAE@XZ" @@ -240,7 +240,7 @@ void f() { } // WIN32-LABEL: define dso_local void @"?f@noexcept_false_dtor@@YAXXZ"() -// WIN32: invoke noundef i32 @"?CouldThrow@@YAHXZ"() +// WIN32: invoke i32 @"?CouldThrow@@YAHXZ"() // WIN32: call x86_thiscallcc void @"??1D@noexcept_false_dtor@@QAE@XZ"(%"struct.noexcept_false_dtor::D"* {{[^,]*}} %{{.*}}) // WIN32: cleanuppad // WIN32: call x86_thiscallcc void @"??1D@noexcept_false_dtor@@QAE@XZ"(%"struct.noexcept_false_dtor::D"* {{[^,]*}} %{{.*}}) @@ -293,7 +293,7 @@ struct class_0 : class_1 { }; class_0::class_0() { - // WIN32: define dso_local x86_thiscallcc noundef %struct.class_0* @"??0class_0@@QAE@XZ"(%struct.class_0* {{[^,]*}} returned %this, i32 noundef %is_most_derived) + // WIN32: define dso_local x86_thiscallcc %struct.class_0* @"??0class_0@@QAE@XZ"(%struct.class_0* {{[^,]*}} returned {{[^,]*}} %this, i32 %is_most_derived) // WIN32: store i32 %is_most_derived, i32* %[[IS_MOST_DERIVED_VAR:.*]], align 4 // WIN32: %[[IS_MOST_DERIVED_VAL:.*]] = load i32, i32* %[[IS_MOST_DERIVED_VAR]] // WIN32: %[[SHOULD_CALL_VBASE_CTORS:.*]] = icmp ne i32 %[[IS_MOST_DERIVED_VAL]], 0 diff --git a/clang/test/CodeGenCXX/microsoft-abi-extern-template.cpp b/clang/test/CodeGenCXX/microsoft-abi-extern-template.cpp index 5f9adfdedea49992aec0380c17c6b2efd50f68c8..a971fd441e6b207839daa536efc77d9eb031f743 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-extern-template.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-extern-template.cpp @@ -7,13 +7,13 @@ // CHECK-SAME: i8* bitcast (i8* (%struct.Foo*, i32)* @"??_G?$Foo@H@@UEAAPEAXI@Z" to i8*) // CHECK-SAME: ] }, comdat -// CHECK-LABEL: define dso_local noundef %struct.Foo* @"?f@@YAPEAU?$Foo@H@@XZ"() -// CHECK: call noundef %struct.Foo* @"??0?$Foo@H@@QEAA@XZ"(%struct.Foo* {{[^,]*}} %{{.*}}) +// CHECK-LABEL: define dso_local %struct.Foo* @"?f@@YAPEAU?$Foo@H@@XZ"() +// CHECK: call %struct.Foo* @"??0?$Foo@H@@QEAA@XZ"(%struct.Foo* {{[^,]*}} %{{.*}}) -// CHECK: define available_externally dso_local noundef %struct.Foo* @"??0?$Foo@H@@QEAA@XZ"(%struct.Foo* {{[^,]*}} returned %this) +// CHECK: define available_externally dso_local %struct.Foo* @"??0?$Foo@H@@QEAA@XZ"(%struct.Foo* {{[^,]*}} returned {{[^,]*}} %this) // CHECK: store {{.*}} @"??_7?$Foo@H@@6B@" -// CHECK: define linkonce_odr dso_local noundef i8* @"??_G?$Foo@H@@UEAAPEAXI@Z"(%struct.Foo* {{[^,]*}} %this, i32 noundef %should_call_delete) +// CHECK: define linkonce_odr dso_local i8* @"??_G?$Foo@H@@UEAAPEAXI@Z"(%struct.Foo* {{[^,]*}} %this, i32 %should_call_delete) struct Base { virtual ~Base(); diff --git a/clang/test/CodeGenCXX/microsoft-abi-member-pointers.cpp b/clang/test/CodeGenCXX/microsoft-abi-member-pointers.cpp index 24f60ac3431723e2aa4cbcd9c16e011761b27e56..527363a6ff8fdc2184363bfd747596321d075c19 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-member-pointers.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-member-pointers.cpp @@ -410,7 +410,7 @@ void polymorphicMemPtrs() { bool nullTestDataUnspecified(int Unspecified::*mp) { return mp; -// CHECK: define dso_local noundef zeroext i1 @"?nullTestDataUnspecified@@YA_NPQUnspecified@@H@Z"{{.*}} { +// CHECK: define dso_local zeroext i1 @"?nullTestDataUnspecified@@YA_NPQUnspecified@@H@Z"{{.*}} { // CHECK: %{{.*}} = load { i32, i32, i32 }, { i32, i32, i32 }* %{{.*}}, align 4 // CHECK: store { i32, i32, i32 } {{.*}} align 4 // CHECK: %[[mp:.*]] = load { i32, i32, i32 }, { i32, i32, i32 }* %{{.*}}, align 4 @@ -426,13 +426,13 @@ bool nullTestDataUnspecified(int Unspecified::*mp) { // CHECK: } // Pass this large type indirectly. -// X64-LABEL: define dso_local noundef zeroext i1 @"?nullTestDataUnspecified@@ -// X64: ({ i32, i32, i32 }* noundef %0) +// X64-LABEL: define dso_local zeroext i1 @"?nullTestDataUnspecified@@ +// X64: ({ i32, i32, i32 }* %0) } bool nullTestFunctionUnspecified(void (Unspecified::*mp)()) { return mp; -// CHECK: define dso_local noundef zeroext i1 @"?nullTestFunctionUnspecified@@YA_NP8Unspecified@@AEXXZ@Z"{{.*}} { +// CHECK: define dso_local zeroext i1 @"?nullTestFunctionUnspecified@@YA_NP8Unspecified@@AEXXZ@Z"{{.*}} { // CHECK: %{{.*}} = load { i8*, i32, i32, i32 }, { i8*, i32, i32, i32 }* %{{.*}}, align 4 // CHECK: store { i8*, i32, i32, i32 } {{.*}} align 4 // CHECK: %[[mp:.*]] = load { i8*, i32, i32, i32 }, { i8*, i32, i32, i32 }* %{{.*}}, align 4 @@ -446,7 +446,7 @@ int loadDataMemberPointerVirtual(Virtual *o, int Virtual::*memptr) { return o->*memptr; // Test that we can unpack this aggregate member pointer and load the member // data pointer. -// CHECK: define dso_local noundef i32 @"?loadDataMemberPointerVirtual@@YAHPAUVirtual@@PQ1@H@Z"{{.*}} { +// CHECK: define dso_local i32 @"?loadDataMemberPointerVirtual@@YAHPAUVirtual@@PQ1@H@Z"{{.*}} { // CHECK: %[[o:.*]] = load %{{.*}}*, %{{.*}}** %{{.*}}, align 4 // CHECK: %[[memptr:.*]] = load { i32, i32 }, { i32, i32 }* %{{.*}}, align 4 // CHECK: %[[memptr0:.*]] = extractvalue { i32, i32 } %[[memptr:.*]], 0 @@ -467,15 +467,15 @@ int loadDataMemberPointerVirtual(Virtual *o, int Virtual::*memptr) { // A two-field data memptr on x64 gets coerced to i64 and is passed in a // register or memory. -// X64-LABEL: define dso_local noundef i32 @"?loadDataMemberPointerVirtual@@YAHPEAUVirtual@@PEQ1@H@Z" -// X64: (%struct.Virtual* noundef %o, i64 %memptr.coerce) +// X64-LABEL: define dso_local i32 @"?loadDataMemberPointerVirtual@@YAHPEAUVirtual@@PEQ1@H@Z" +// X64: (%struct.Virtual* %o, i64 %memptr.coerce) } int loadDataMemberPointerUnspecified(Unspecified *o, int Unspecified::*memptr) { return o->*memptr; // Test that we can unpack this aggregate member pointer and load the member // data pointer. -// CHECK: define dso_local noundef i32 @"?loadDataMemberPointerUnspecified@@YAHPAUUnspecified@@PQ1@H@Z"{{.*}} { +// CHECK: define dso_local i32 @"?loadDataMemberPointerUnspecified@@YAHPAUUnspecified@@PQ1@H@Z"{{.*}} { // CHECK: %[[o:.*]] = load %{{.*}}*, %{{.*}}** %{{.*}}, align 4 // CHECK: %[[memptr:.*]] = load { i32, i32, i32 }, { i32, i32, i32 }* %{{.*}}, align 4 // CHECK: %[[memptr0:.*]] = extractvalue { i32, i32, i32 } %[[memptr:.*]], 0 @@ -512,7 +512,7 @@ void callMemberPointerSingle(Single *o, void (Single::*memptr)()) { // CHECK: } // X64-LABEL: define dso_local void @"?callMemberPointerSingle@@ -// X64: (%struct.Single* noundef %o, i8* %memptr) +// X64: (%struct.Single* %o, i8* %memptr) // X64: bitcast i8* %{{[^ ]*}} to void (%struct.Single*)* // X64: ret void } @@ -555,21 +555,21 @@ void callMemberPointerVirtualBase(Virtual *o, void (Virtual::*memptr)()) { bool compareSingleFunctionMemptr(void (Single::*l)(), void (Single::*r)()) { return l == r; // Should only be one comparison here. -// CHECK: define dso_local noundef zeroext i1 @"?compareSingleFunctionMemptr@@YA_NP8Single@@AEXXZ0@Z"{{.*}} { +// CHECK: define dso_local zeroext i1 @"?compareSingleFunctionMemptr@@YA_NP8Single@@AEXXZ0@Z"{{.*}} { // CHECK-NOT: icmp // CHECK: %[[r:.*]] = icmp eq // CHECK-NOT: icmp // CHECK: ret i1 %[[r]] // CHECK: } -// X64-LABEL: define dso_local noundef zeroext i1 @"?compareSingleFunctionMemptr@@ +// X64-LABEL: define dso_local zeroext i1 @"?compareSingleFunctionMemptr@@ // X64: (i8* %{{[^,]*}}, i8* %{{[^)]*}}) } bool compareNeqSingleFunctionMemptr(void (Single::*l)(), void (Single::*r)()) { return l != r; // Should only be one comparison here. -// CHECK: define dso_local noundef zeroext i1 @"?compareNeqSingleFunctionMemptr@@YA_NP8Single@@AEXXZ0@Z"{{.*}} { +// CHECK: define dso_local zeroext i1 @"?compareNeqSingleFunctionMemptr@@YA_NP8Single@@AEXXZ0@Z"{{.*}} { // CHECK-NOT: icmp // CHECK: %[[r:.*]] = icmp ne // CHECK-NOT: icmp @@ -579,7 +579,7 @@ bool compareNeqSingleFunctionMemptr(void (Single::*l)(), void (Single::*r)()) { bool unspecFuncMemptrEq(void (Unspecified::*l)(), void (Unspecified::*r)()) { return l == r; -// CHECK: define dso_local noundef zeroext i1 @"?unspecFuncMemptrEq@@YA_NP8Unspecified@@AEXXZ0@Z"{{.*}} { +// CHECK: define dso_local zeroext i1 @"?unspecFuncMemptrEq@@YA_NP8Unspecified@@AEXXZ0@Z"{{.*}} { // CHECK: %[[lhs0:.*]] = extractvalue { i8*, i32, i32, i32 } %[[l:.*]], 0 // CHECK: %{{.*}} = extractvalue { i8*, i32, i32, i32 } %[[r:.*]], 0 // CHECK: %[[cmp0:.*]] = icmp eq i8* %[[lhs0]], %{{.*}} @@ -600,13 +600,13 @@ bool unspecFuncMemptrEq(void (Unspecified::*l)(), void (Unspecified::*r)()) { // CHECK: ret i1 %{{.*}} // CHECK: } -// X64-LABEL: define dso_local noundef zeroext i1 @"?unspecFuncMemptrEq@@ -// X64: ({ i8*, i32, i32, i32 }* noundef %0, { i8*, i32, i32, i32 }* noundef %1) +// X64-LABEL: define dso_local zeroext i1 @"?unspecFuncMemptrEq@@ +// X64: ({ i8*, i32, i32, i32 }* %0, { i8*, i32, i32, i32 }* %1) } bool unspecFuncMemptrNeq(void (Unspecified::*l)(), void (Unspecified::*r)()) { return l != r; -// CHECK: define dso_local noundef zeroext i1 @"?unspecFuncMemptrNeq@@YA_NP8Unspecified@@AEXXZ0@Z"{{.*}} { +// CHECK: define dso_local zeroext i1 @"?unspecFuncMemptrNeq@@YA_NP8Unspecified@@AEXXZ0@Z"{{.*}} { // CHECK: %[[lhs0:.*]] = extractvalue { i8*, i32, i32, i32 } %[[l:.*]], 0 // CHECK: %{{.*}} = extractvalue { i8*, i32, i32, i32 } %[[r:.*]], 0 // CHECK: %[[cmp0:.*]] = icmp ne i8* %[[lhs0]], %{{.*}} @@ -630,7 +630,7 @@ bool unspecFuncMemptrNeq(void (Unspecified::*l)(), void (Unspecified::*r)()) { bool unspecDataMemptrEq(int Unspecified::*l, int Unspecified::*r) { return l == r; -// CHECK: define dso_local noundef zeroext i1 @"?unspecDataMemptrEq@@YA_NPQUnspecified@@H0@Z"{{.*}} { +// CHECK: define dso_local zeroext i1 @"?unspecDataMemptrEq@@YA_NPQUnspecified@@H0@Z"{{.*}} { // CHECK: extractvalue { i32, i32, i32 } %{{.*}}, 0 // CHECK: extractvalue { i32, i32, i32 } %{{.*}}, 0 // CHECK: icmp eq i32 @@ -645,8 +645,8 @@ bool unspecDataMemptrEq(int Unspecified::*l, int Unspecified::*r) { // CHECK: ret i1 // CHECK: } -// X64-LABEL: define dso_local noundef zeroext i1 @"?unspecDataMemptrEq@@ -// X64: ({ i32, i32, i32 }* noundef %0, { i32, i32, i32 }* noundef %1) +// X64-LABEL: define dso_local zeroext i1 @"?unspecDataMemptrEq@@ +// X64: ({ i32, i32, i32 }* %0, { i32, i32, i32 }* %1) } void (Multiple::*convertB2FuncToMultiple(void (B2::*mp)()))() { @@ -767,7 +767,7 @@ struct A { int *load_data(A *a, int A::*mp) { return &(a->*mp); -// CHECK-LABEL: define dso_local noundef i32* @"?load_data@Test3@@YAPAHPAUA@1@PQ21@H@Z"{{.*}} { +// CHECK-LABEL: define dso_local i32* @"?load_data@Test3@@YAPAHPAUA@1@PQ21@H@Z"{{.*}} { // CHECK: %[[a:.*]] = load %"struct.Test3::A"*, %"struct.Test3::A"** %{{.*}}, align 4 // CHECK: %[[mp:.*]] = load i32, i32* %{{.*}}, align 4 // CHECK: %[[a_i8:.*]] = bitcast %"struct.Test3::A"* %[[a]] to i8* @@ -790,7 +790,7 @@ void (C::*getmp())() { // CHECK: store { i8*, i32 } { i8* bitcast (void (%"struct.Test4::C"*, ...)* @"??_9C@Test4@@$BA@AE" to i8*), i32 4 }, { i8*, i32 }* %{{.*}} // -// CHECK-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@Test4@@$BA@AE"(%"struct.Test4::C"* noundef %this, ...) {{.*}} comdat +// CHECK-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@Test4@@$BA@AE"(%"struct.Test4::C"* %this, ...) {{.*}} comdat // CHECK-NOT: getelementptr // CHECK: load void (%"struct.Test4::C"*, ...)**, void (%"struct.Test4::C"*, ...)*** %{{.*}} // CHECK: getelementptr inbounds void (%"struct.Test4::C"*, ...)*, void (%"struct.Test4::C"*, ...)** %{{.*}}, i64 0 diff --git a/clang/test/CodeGenCXX/microsoft-abi-methods.cpp b/clang/test/CodeGenCXX/microsoft-abi-methods.cpp index 863b3eca8ed3ab6e47ebcad03206975289d5d0f9..f4186a20ec5293a92657cf8f1163e7324b8e7511 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-methods.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-methods.cpp @@ -69,20 +69,20 @@ class Child: public Base { }; void constructors() { Child c; -// Make sure that the Base constructor call noundef in the Child constructor uses +// Make sure that the Base constructor call in the Child constructor uses // the right calling convention: -// CHECK: define linkonce_odr dso_local x86_thiscallcc noundef %class.Child* @"??0Child@@QAE@XZ" -// CHECK: %{{[.0-9A-Z_a-z]+}} = call x86_thiscallcc noundef %class.Base* @"??0Base@@QAE@XZ" +// CHECK: define linkonce_odr dso_local x86_thiscallcc %class.Child* @"??0Child@@QAE@XZ" +// CHECK: %{{[.0-9A-Z_a-z]+}} = call x86_thiscallcc %class.Base* @"??0Base@@QAE@XZ" // CHECK: ret -// Make sure that the Base destructor call noundef in the Child denstructor uses +// Make sure that the Base destructor call in the Child denstructor uses // the right calling convention: // CHECK: define linkonce_odr dso_local x86_thiscallcc void @"??1Child@@QAE@XZ" // CHECK: call x86_thiscallcc void @"??1Base@@QAE@XZ" // CHECK: ret // Make sure that the Base constructor definition uses the right CC: -// CHECK: define linkonce_odr dso_local x86_thiscallcc noundef %class.Base* @"??0Base@@QAE@XZ" +// CHECK: define linkonce_odr dso_local x86_thiscallcc %class.Base* @"??0Base@@QAE@XZ" // Make sure that the Base destructor definition uses the right CC: // CHECK: define linkonce_odr dso_local x86_thiscallcc void @"??1Base@@QAE@XZ" diff --git a/clang/test/CodeGenCXX/microsoft-abi-multiple-nonvirtual-inheritance.cpp b/clang/test/CodeGenCXX/microsoft-abi-multiple-nonvirtual-inheritance.cpp index 7941a14689dfc80f66d96ca34c9fae641398d275..977bb5d6da2552b2b7b86b6e80683d5cf1f5062b 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-multiple-nonvirtual-inheritance.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-multiple-nonvirtual-inheritance.cpp @@ -44,7 +44,7 @@ void ChildOverride::left() { foo(this); // CHECK: %[[THIS:.*]] = load %struct.ChildOverride*, %struct.ChildOverride** %[[THIS_ADDR]] // CHECK: %[[THIS_i8:.*]] = bitcast %struct.ChildOverride* %[[THIS]] to i8* -// CHECK: call void @foo(i8* noundef %[[THIS_i8]]) +// CHECK: call void @foo(i8* %[[THIS_i8]]) // CHECK: ret } @@ -101,7 +101,7 @@ void ChildOverride::right() { foo(this); // CHECK: %[[THIS_PARAM:.*]] = bitcast %struct.ChildOverride* %[[THIS]] to i8* -// CHECK: call void @foo(i8* noundef %[[THIS_PARAM]]) +// CHECK: call void @foo(i8* %[[THIS_PARAM]]) // CHECK: ret } @@ -123,7 +123,7 @@ void call_right_override(ChildOverride *child) { // CHECK: %[[VFUN:.*]] = getelementptr inbounds void (i8*)*, void (i8*)** %[[VFTABLE]], i64 0 // CHECK: %[[VFUN_VALUE:.*]] = load void (i8*)*, void (i8*)** %[[VFUN]] // -// CHECK: call x86_thiscallcc void %[[VFUN_VALUE]](i8* noundef %[[RIGHT]]) +// CHECK: call x86_thiscallcc void %[[VFUN_VALUE]](i8* %[[RIGHT]]) // CHECK: ret } @@ -147,7 +147,7 @@ void GrandchildOverride::right() { foo(this); // CHECK: %[[THIS_PARAM:.*]] = bitcast %struct.GrandchildOverride* %[[THIS]] to i8* -// CHECK: call void @foo(i8* noundef %[[THIS_PARAM]]) +// CHECK: call void @foo(i8* %[[THIS_PARAM]]) // CHECK: ret } @@ -204,7 +204,7 @@ struct AsymmetricChild : LeftWithNonVirtualDtor, Right { void call_asymmetric_child_complete_dtor() { // CHECK-LABEL: define dso_local void @"?call_asymmetric_child_complete_dtor@@YAXXZ" AsymmetricChild obj; - // CHECK: call x86_thiscallcc noundef %struct.AsymmetricChild* @"??0AsymmetricChild@@QAE@XZ"(%struct.AsymmetricChild* {{[^,]*}} %[[OBJ:.*]]) + // CHECK: call x86_thiscallcc %struct.AsymmetricChild* @"??0AsymmetricChild@@QAE@XZ"(%struct.AsymmetricChild* {{[^,]*}} %[[OBJ:.*]]) // CHECK-NOT: getelementptr // CHECK: call x86_thiscallcc void @"??1AsymmetricChild@@UAE@XZ"(%struct.AsymmetricChild* {{[^,]*}} %[[OBJ]]) // CHECK: ret diff --git a/clang/test/CodeGenCXX/microsoft-abi-sret-and-byval.cpp b/clang/test/CodeGenCXX/microsoft-abi-sret-and-byval.cpp index 79dd08386d1685f21cca9b763b23bbf2b752a831..94d59eb8703f0060ca6b583864b1c4211d8d67e2 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-sret-and-byval.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-sret-and-byval.cpp @@ -151,28 +151,28 @@ void medium_arg(Medium s) {} // WOA: define dso_local arm_aapcs_vfpcc void @"?medium_arg@@YAXUMedium@@@Z"([2 x i32] %s.coerce) void base_no_byval_arg(BaseNoByval s) {} -// LINUX-LABEL: define{{.*}} void @_Z17base_no_byval_arg11BaseNoByval(%struct.BaseNoByval* noundef byval(%struct.BaseNoByval) align 4 %s) +// LINUX-LABEL: define{{.*}} void @_Z17base_no_byval_arg11BaseNoByval(%struct.BaseNoByval* byval(%struct.BaseNoByval) align 4 %s) // WIN32: define dso_local void @"?base_no_byval_arg@@YAXUBaseNoByval@@@Z"(i32 %s.0, i32 %s.1) // WIN64: define dso_local void @"?base_no_byval_arg@@YAXUBaseNoByval@@@Z"(i64 %s.coerce) // WOA: define dso_local arm_aapcs_vfpcc void @"?base_no_byval_arg@@YAXUBaseNoByval@@@Z"([2 x i32] %s.coerce) void small_arg_with_ctor(SmallWithCtor s) {} -// LINUX-LABEL: define{{.*}} void @_Z19small_arg_with_ctor13SmallWithCtor(%struct.SmallWithCtor* noundef byval(%struct.SmallWithCtor) align 4 %s) +// LINUX-LABEL: define{{.*}} void @_Z19small_arg_with_ctor13SmallWithCtor(%struct.SmallWithCtor* byval(%struct.SmallWithCtor) align 4 %s) // WIN32: define dso_local void @"?small_arg_with_ctor@@YAXUSmallWithCtor@@@Z"(i32 %s.0) // WIN64: define dso_local void @"?small_arg_with_ctor@@YAXUSmallWithCtor@@@Z"(i32 %s.coerce) // WOA: define dso_local arm_aapcs_vfpcc void @"?small_arg_with_ctor@@YAXUSmallWithCtor@@@Z"([1 x i32] %s.coerce) // FIXME: We could coerce to a series of i32s here if we wanted to. void multibyte_arg(Multibyte s) {} -// LINUX-LABEL: define{{.*}} void @_Z13multibyte_arg9Multibyte(%struct.Multibyte* noundef byval(%struct.Multibyte) align 4 %s) -// WIN32: define dso_local void @"?multibyte_arg@@YAXUMultibyte@@@Z"(%struct.Multibyte* noundef byval(%struct.Multibyte) align 4 %s) +// LINUX-LABEL: define{{.*}} void @_Z13multibyte_arg9Multibyte(%struct.Multibyte* byval(%struct.Multibyte) align 4 %s) +// WIN32: define dso_local void @"?multibyte_arg@@YAXUMultibyte@@@Z"(%struct.Multibyte* byval(%struct.Multibyte) align 4 %s) // WIN64: define dso_local void @"?multibyte_arg@@YAXUMultibyte@@@Z"(i32 %s.coerce) // WOA: define dso_local arm_aapcs_vfpcc void @"?multibyte_arg@@YAXUMultibyte@@@Z"([1 x i32] %s.coerce) void packed_arg(Packed s) {} -// LINUX-LABEL: define{{.*}} void @_Z10packed_arg6Packed(%struct.Packed* noundef byval(%struct.Packed) align 4 %s) -// WIN32: define dso_local void @"?packed_arg@@YAXUPacked@@@Z"(%struct.Packed* noundef byval(%struct.Packed) align 4 %s) -// WIN64: define dso_local void @"?packed_arg@@YAXUPacked@@@Z"(%struct.Packed* noundef %s) +// LINUX-LABEL: define{{.*}} void @_Z10packed_arg6Packed(%struct.Packed* byval(%struct.Packed) align 4 %s) +// WIN32: define dso_local void @"?packed_arg@@YAXUPacked@@@Z"(%struct.Packed* byval(%struct.Packed) align 4 %s) +// WIN64: define dso_local void @"?packed_arg@@YAXUPacked@@@Z"(%struct.Packed* %s) // Test that dtors are invoked in the callee. void small_arg_with_dtor(SmallWithDtor s) {} @@ -187,7 +187,7 @@ void small_arg_with_dtor(SmallWithDtor s) {} // WOA64: } // FIXME: MSVC incompatible! -// WOA: define dso_local arm_aapcs_vfpcc void @"?small_arg_with_dtor@@YAXUSmallWithDtor@@@Z"(%struct.SmallWithDtor* noundef %s) {{.*}} { +// WOA: define dso_local arm_aapcs_vfpcc void @"?small_arg_with_dtor@@YAXUSmallWithDtor@@@Z"(%struct.SmallWithDtor* %s) {{.*}} { // WOA: call arm_aapcs_vfpcc void @"??1SmallWithDtor@@QAA@XZ"(%struct.SmallWithDtor* {{[^,]*}} %s) // WOA: } @@ -201,19 +201,19 @@ void call_small_arg_with_dtor() { small_arg_with_dtor(SmallWithDtor()); } // WIN64-LABEL: define dso_local void @"?call_small_arg_with_dtor@@YAXXZ"() -// WIN64: call noundef %struct.SmallWithDtor* @"??0SmallWithDtor@@QEAA@XZ" +// WIN64: call %struct.SmallWithDtor* @"??0SmallWithDtor@@QEAA@XZ" // WIN64: call void @"?small_arg_with_dtor@@YAXUSmallWithDtor@@@Z"(i32 %{{.*}}) // WIN64: ret void // Test that references aren't destroyed in the callee. void ref_small_arg_with_dtor(const SmallWithDtor &s) { } -// WIN32: define dso_local void @"?ref_small_arg_with_dtor@@YAXABUSmallWithDtor@@@Z"(%struct.SmallWithDtor* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %s) {{.*}} { +// WIN32: define dso_local void @"?ref_small_arg_with_dtor@@YAXABUSmallWithDtor@@@Z"(%struct.SmallWithDtor* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %s) {{.*}} { // WIN32-NOT: call x86_thiscallcc void @"??1SmallWithDtor@@QAE@XZ" // WIN32: } -// WIN64-LABEL: define dso_local void @"?ref_small_arg_with_dtor@@YAXAEBUSmallWithDtor@@@Z"(%struct.SmallWithDtor* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %s) +// WIN64-LABEL: define dso_local void @"?ref_small_arg_with_dtor@@YAXAEBUSmallWithDtor@@@Z"(%struct.SmallWithDtor* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %s) void big_arg_with_dtor(BigWithDtor s) {} -// WIN64-LABEL: define dso_local void @"?big_arg_with_dtor@@YAXUBigWithDtor@@@Z"(%struct.BigWithDtor* noundef %s) +// WIN64-LABEL: define dso_local void @"?big_arg_with_dtor@@YAXUBigWithDtor@@@Z"(%struct.BigWithDtor* %s) // WIN64: call void @"??1BigWithDtor@@QEAA@XZ" // WIN64: } @@ -223,8 +223,8 @@ void call_big_arg_with_dtor() { // We can elide the copy of the temporary in the caller, because this object is // larger than 8 bytes and is passed indirectly. // WIN64-LABEL: define dso_local void @"?call_big_arg_with_dtor@@YAXXZ"() -// WIN64: call noundef %struct.BigWithDtor* @"??0BigWithDtor@@QEAA@XZ" -// WIN64: call void @"?big_arg_with_dtor@@YAXUBigWithDtor@@@Z"(%struct.BigWithDtor* noundef %{{.*}}) +// WIN64: call %struct.BigWithDtor* @"??0BigWithDtor@@QEAA@XZ" +// WIN64: call void @"?big_arg_with_dtor@@YAXUBigWithDtor@@@Z"(%struct.BigWithDtor* %{{.*}}) // WIN64-NOT: call void @"??1BigWithDtor@@QEAA@XZ" // WIN64: ret void @@ -233,7 +233,7 @@ void temporary_ref_with_dtor() { ref_small_arg_with_dtor(SmallWithDtor()); } // WIN32: define dso_local void @"?temporary_ref_with_dtor@@YAXXZ"() {{.*}} { -// WIN32: call x86_thiscallcc noundef %struct.SmallWithDtor* @"??0SmallWithDtor@@QAE@XZ" +// WIN32: call x86_thiscallcc %struct.SmallWithDtor* @"??0SmallWithDtor@@QAE@XZ" // WIN32: call void @"?ref_small_arg_with_dtor@@YAXABUSmallWithDtor@@@Z" // WIN32: call x86_thiscallcc void @"??1SmallWithDtor@@QAE@XZ" // WIN32: } @@ -245,29 +245,29 @@ void eh_cleanup_arg_with_dtor() { // When exceptions are off, we don't have any cleanups. See // microsoft-abi-exceptions.cpp for these cleanups. // WIN32: define dso_local void @"?eh_cleanup_arg_with_dtor@@YAXXZ"() {{.*}} { -// WIN32: call x86_thiscallcc noundef %struct.SmallWithDtor* @"??0SmallWithDtor@@QAE@XZ" -// WIN32: call x86_thiscallcc noundef %struct.SmallWithDtor* @"??0SmallWithDtor@@QAE@XZ" +// WIN32: call x86_thiscallcc %struct.SmallWithDtor* @"??0SmallWithDtor@@QAE@XZ" +// WIN32: call x86_thiscallcc %struct.SmallWithDtor* @"??0SmallWithDtor@@QAE@XZ" // WIN32: call void @"?takes_two_by_val_with_dtor@@YAXUSmallWithDtor@@0@Z" // WIN32-NOT: call x86_thiscallcc void @"??1SmallWithDtor@@QAE@XZ" // WIN32: } void small_arg_with_vftable(SmallWithVftable s) {} -// LINUX-LABEL: define{{.*}} void @_Z22small_arg_with_vftable16SmallWithVftable(%struct.SmallWithVftable* noundef %s) +// LINUX-LABEL: define{{.*}} void @_Z22small_arg_with_vftable16SmallWithVftable(%struct.SmallWithVftable* %s) // WIN32: define dso_local void @"?small_arg_with_vftable@@YAXUSmallWithVftable@@@Z"(<{ %struct.SmallWithVftable }>* inalloca(<{ %struct.SmallWithVftable }>) %0) -// WIN64: define dso_local void @"?small_arg_with_vftable@@YAXUSmallWithVftable@@@Z"(%struct.SmallWithVftable* noundef %s) -// WOA64: define dso_local void @"?small_arg_with_vftable@@YAXUSmallWithVftable@@@Z"(%struct.SmallWithVftable* noundef %s) +// WIN64: define dso_local void @"?small_arg_with_vftable@@YAXUSmallWithVftable@@@Z"(%struct.SmallWithVftable* %s) +// WOA64: define dso_local void @"?small_arg_with_vftable@@YAXUSmallWithVftable@@@Z"(%struct.SmallWithVftable* %s) void medium_arg_with_copy_ctor(MediumWithCopyCtor s) {} -// LINUX-LABEL: define{{.*}} void @_Z25medium_arg_with_copy_ctor18MediumWithCopyCtor(%struct.MediumWithCopyCtor* noundef %s) +// LINUX-LABEL: define{{.*}} void @_Z25medium_arg_with_copy_ctor18MediumWithCopyCtor(%struct.MediumWithCopyCtor* %s) // WIN32: define dso_local void @"?medium_arg_with_copy_ctor@@YAXUMediumWithCopyCtor@@@Z"(<{ %struct.MediumWithCopyCtor }>* inalloca(<{ %struct.MediumWithCopyCtor }>) %0) -// WIN64: define dso_local void @"?medium_arg_with_copy_ctor@@YAXUMediumWithCopyCtor@@@Z"(%struct.MediumWithCopyCtor* noundef %s) -// WOA: define dso_local arm_aapcs_vfpcc void @"?medium_arg_with_copy_ctor@@YAXUMediumWithCopyCtor@@@Z"(%struct.MediumWithCopyCtor* noundef %s) -// WOA64: define dso_local void @"?medium_arg_with_copy_ctor@@YAXUMediumWithCopyCtor@@@Z"(%struct.MediumWithCopyCtor* noundef %s) +// WIN64: define dso_local void @"?medium_arg_with_copy_ctor@@YAXUMediumWithCopyCtor@@@Z"(%struct.MediumWithCopyCtor* %s) +// WOA: define dso_local arm_aapcs_vfpcc void @"?medium_arg_with_copy_ctor@@YAXUMediumWithCopyCtor@@@Z"(%struct.MediumWithCopyCtor* %s) +// WOA64: define dso_local void @"?medium_arg_with_copy_ctor@@YAXUMediumWithCopyCtor@@@Z"(%struct.MediumWithCopyCtor* %s) void big_arg(Big s) {} -// LINUX-LABEL: define{{.*}} void @_Z7big_arg3Big(%struct.Big* noundef byval(%struct.Big) align 4 %s) -// WIN32: define dso_local void @"?big_arg@@YAXUBig@@@Z"(%struct.Big* noundef byval(%struct.Big) align 4 %s) -// WIN64: define dso_local void @"?big_arg@@YAXUBig@@@Z"(%struct.Big* noundef %s) +// LINUX-LABEL: define{{.*}} void @_Z7big_arg3Big(%struct.Big* byval(%struct.Big) align 4 %s) +// WIN32: define dso_local void @"?big_arg@@YAXUBig@@@Z"(%struct.Big* byval(%struct.Big) align 4 %s) +// WIN64: define dso_local void @"?big_arg@@YAXUBig@@@Z"(%struct.Big* %s) // PR27607: We would attempt to load i32 value out of the reference instead of // just loading the pointer from the struct during argument expansion. @@ -276,7 +276,7 @@ struct RefField { int &x; }; void takes_ref_field(RefField s) {} -// LINUX-LABEL: define{{.*}} void @_Z15takes_ref_field8RefField(%struct.RefField* noundef byval(%struct.RefField) align 4 %s) +// LINUX-LABEL: define{{.*}} void @_Z15takes_ref_field8RefField(%struct.RefField* byval(%struct.RefField) align 4 %s) // WIN32: define dso_local void @"?takes_ref_field@@YAXURefField@@@Z"(i32* %s.0) // WIN64: define dso_local void @"?takes_ref_field@@YAXURefField@@@Z"(i64 %s.coerce) @@ -285,7 +285,7 @@ void pass_ref_field() { takes_ref_field(RefField(x)); } // LINUX-LABEL: define{{.*}} void @_Z14pass_ref_fieldv() -// LINUX: call void @_Z15takes_ref_field8RefField(%struct.RefField* noundef byval(%struct.RefField) align 4 %{{.*}}) +// LINUX: call void @_Z15takes_ref_field8RefField(%struct.RefField* byval(%struct.RefField) align 4 %{{.*}}) // WIN32-LABEL: define dso_local void @"?pass_ref_field@@YAXXZ"() // WIN32: call void @"?takes_ref_field@@YAXURefField@@@Z"(i32* %{{.*}}) // WIN64-LABEL: define dso_local void @"?pass_ref_field@@YAXXZ"() @@ -318,12 +318,12 @@ class Class { void thiscall_method_arg(Empty s) {} // LINUX: define {{.*}} void @_ZN5Class19thiscall_method_argE5Empty(%class.Class* {{[^,]*}} %this) - // WIN32: define {{.*}} void @"?thiscall_method_arg@Class@@QAEXUEmpty@@@Z"(%class.Class* {{[^,]*}} %this, %struct.Empty* noundef byval(%struct.Empty) align 4 %s) + // WIN32: define {{.*}} void @"?thiscall_method_arg@Class@@QAEXUEmpty@@@Z"(%class.Class* {{[^,]*}} %this, %struct.Empty* byval(%struct.Empty) align 4 %s) // WIN64: define linkonce_odr dso_local void @"?thiscall_method_arg@Class@@QEAAXUEmpty@@@Z"(%class.Class* {{[^,]*}} %this, i8 %s.coerce) void thiscall_method_arg(EmptyWithCtor s) {} // LINUX: define {{.*}} void @_ZN5Class19thiscall_method_argE13EmptyWithCtor(%class.Class* {{[^,]*}} %this) - // WIN32: define {{.*}} void @"?thiscall_method_arg@Class@@QAEXUEmptyWithCtor@@@Z"(%class.Class* {{[^,]*}} %this, %struct.EmptyWithCtor* noundef byval(%struct.EmptyWithCtor) align 4 %s) + // WIN32: define {{.*}} void @"?thiscall_method_arg@Class@@QAEXUEmptyWithCtor@@@Z"(%class.Class* {{[^,]*}} %this, %struct.EmptyWithCtor* byval(%struct.EmptyWithCtor) align 4 %s) // WIN64: define linkonce_odr dso_local void @"?thiscall_method_arg@Class@@QEAAXUEmptyWithCtor@@@Z"(%class.Class* {{[^,]*}} %this, i8 %s.coerce) void thiscall_method_arg(Small s) {} @@ -332,14 +332,14 @@ class Class { // WIN64: define linkonce_odr dso_local void @"?thiscall_method_arg@Class@@QEAAXUSmall@@@Z"(%class.Class* {{[^,]*}} %this, i32 %s.coerce) void thiscall_method_arg(SmallWithCtor s) {} - // LINUX: define {{.*}} void @_ZN5Class19thiscall_method_argE13SmallWithCtor(%class.Class* {{[^,]*}} %this, %struct.SmallWithCtor* noundef byval(%struct.SmallWithCtor) align 4 %s) + // LINUX: define {{.*}} void @_ZN5Class19thiscall_method_argE13SmallWithCtor(%class.Class* {{[^,]*}} %this, %struct.SmallWithCtor* byval(%struct.SmallWithCtor) align 4 %s) // WIN32: define {{.*}} void @"?thiscall_method_arg@Class@@QAEXUSmallWithCtor@@@Z"(%class.Class* {{[^,]*}} %this, i32 %s.0) // WIN64: define linkonce_odr dso_local void @"?thiscall_method_arg@Class@@QEAAXUSmallWithCtor@@@Z"(%class.Class* {{[^,]*}} %this, i32 %s.coerce) void thiscall_method_arg(Big s) {} - // LINUX: define {{.*}} void @_ZN5Class19thiscall_method_argE3Big(%class.Class* {{[^,]*}} %this, %struct.Big* noundef byval(%struct.Big) align 4 %s) - // WIN32: define {{.*}} void @"?thiscall_method_arg@Class@@QAEXUBig@@@Z"(%class.Class* {{[^,]*}} %this, %struct.Big* noundef byval(%struct.Big) align 4 %s) - // WIN64: define linkonce_odr dso_local void @"?thiscall_method_arg@Class@@QEAAXUBig@@@Z"(%class.Class* {{[^,]*}} %this, %struct.Big* noundef %s) + // LINUX: define {{.*}} void @_ZN5Class19thiscall_method_argE3Big(%class.Class* {{[^,]*}} %this, %struct.Big* byval(%struct.Big) align 4 %s) + // WIN32: define {{.*}} void @"?thiscall_method_arg@Class@@QAEXUBig@@@Z"(%class.Class* {{[^,]*}} %this, %struct.Big* byval(%struct.Big) align 4 %s) + // WIN64: define linkonce_odr dso_local void @"?thiscall_method_arg@Class@@QEAAXUBig@@@Z"(%class.Class* {{[^,]*}} %this, %struct.Big* %s) }; void use_class() { @@ -397,8 +397,8 @@ void bar() { // WIN32: getelementptr inbounds [[argmem_ty]], [[argmem_ty]]* %[[argmem]], i32 0, i32 1 // WIN32: call void @llvm.memcpy // WIN32: getelementptr inbounds [[argmem_ty]], [[argmem_ty]]* %[[argmem]], i32 0, i32 0 -// WIN32: call x86_thiscallcc noundef %"struct.test2::NonTrivial"* @"??0NonTrivial@test2@@QAE@XZ" -// WIN32: call noundef i32 @"?foo@test2@@YAHUNonTrivial@1@UPOD@1@@Z"([[argmem_ty]]* inalloca([[argmem_ty]]) %argmem) +// WIN32: call x86_thiscallcc %"struct.test2::NonTrivial"* @"??0NonTrivial@test2@@QAE@XZ" +// WIN32: call i32 @"?foo@test2@@YAHUNonTrivial@1@UPOD@1@@Z"([[argmem_ty]]* inalloca([[argmem_ty]]) %argmem) // WIN32: ret void // WIN32: } @@ -461,10 +461,10 @@ struct C final : A, B { void C::g() { return h(SmallWithDtor()); } // WIN32-LABEL: define dso_local x86_thiscallcc void @"?g@C@pr30293@@QAEXXZ"(%"struct.pr30293::C"* {{[^,]*}} %this) -// WIN32: call x86_thiscallcc noundef %struct.SmallWithDtor* @"??0SmallWithDtor@@QAE@XZ" +// WIN32: call x86_thiscallcc %struct.SmallWithDtor* @"??0SmallWithDtor@@QAE@XZ" // WIN32: call void @"?h@C@pr30293@@UAAXUSmallWithDtor@@@Z"(<{ i8*, %struct.SmallWithDtor }>* inalloca(<{ i8*, %struct.SmallWithDtor }>) %{{[^,)]*}}) // WIN32: declare dso_local void @"?h@C@pr30293@@UAAXUSmallWithDtor@@@Z"(<{ i8*, %struct.SmallWithDtor }>* inalloca(<{ i8*, %struct.SmallWithDtor }>)) // WIN64-LABEL: define dso_local void @"?g@C@pr30293@@QEAAXXZ"(%"struct.pr30293::C"* {{[^,]*}} %this) -// WIN64: declare dso_local void @"?h@C@pr30293@@UEAAXUSmallWithDtor@@@Z"(i8* noundef, i32) +// WIN64: declare dso_local void @"?h@C@pr30293@@UEAAXUSmallWithDtor@@@Z"(i8*, i32) } diff --git a/clang/test/CodeGenCXX/microsoft-abi-static-initializers.cpp b/clang/test/CodeGenCXX/microsoft-abi-static-initializers.cpp index 1d98fa007ae3b21c539d9cc2198017b3c1db6788..dbc22d3fe3d2b24017dad7183982c8c20fa24ffc 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-static-initializers.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-static-initializers.cpp @@ -16,7 +16,7 @@ struct S { S s; // CHECK: define internal void @"??__Es@@YAXXZ"() -// CHECK: call x86_thiscallcc noundef %struct.S* @"??0S@@QAE@XZ" +// CHECK: call x86_thiscallcc %struct.S* @"??0S@@QAE@XZ" // CHECK: call i32 @atexit(void ()* @"??__Fs@@YAXXZ") // CHECK: ret void @@ -30,11 +30,11 @@ __declspec(selectany) S selectany1; __declspec(selectany) S selectany2; // CHECK: define linkonce_odr dso_local void @"??__Eselectany1@@YAXXZ"() {{.*}} comdat // CHECK-NOT: @"??_Bselectany1 -// CHECK: call x86_thiscallcc noundef %struct.S* @"??0S@@QAE@XZ" +// CHECK: call x86_thiscallcc %struct.S* @"??0S@@QAE@XZ" // CHECK: ret void // CHECK: define linkonce_odr dso_local void @"??__Eselectany2@@YAXXZ"() {{.*}} comdat // CHECK-NOT: @"??_Bselectany2 -// CHECK: call x86_thiscallcc noundef %struct.S* @"??0S@@QAE@XZ" +// CHECK: call x86_thiscallcc %struct.S* @"??0S@@QAE@XZ" // CHECK: ret void // The implicitly instantiated static data member should have initializer @@ -133,7 +133,7 @@ inline S &UnreachableStatic() { return s; } -// CHECK-LABEL: define linkonce_odr dso_local noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.S* @"?UnreachableStatic@@YAAAUS@@XZ"() {{.*}} comdat +// CHECK-LABEL: define linkonce_odr dso_local nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.S* @"?UnreachableStatic@@YAAAUS@@XZ"() {{.*}} comdat // CHECK: and i32 {{.*}}, 2 // CHECK: or i32 {{.*}}, 2 // CHECK: ret @@ -143,7 +143,7 @@ inline S &getS() { return TheS; } -// CHECK-LABEL: define linkonce_odr dso_local noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.S* @"?getS@@YAAAUS@@XZ"() {{.*}} comdat +// CHECK-LABEL: define linkonce_odr dso_local nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.S* @"?getS@@YAAAUS@@XZ"() {{.*}} comdat // CHECK: load i32, i32* @"??_B?1??getS@@YAAAUS@@XZ@51" // CHECK: and i32 {{.*}}, 1 // CHECK: icmp eq i32 {{.*}}, 0 @@ -151,14 +151,14 @@ inline S &getS() { // init: // CHECK: or i32 {{.*}}, 1 // CHECK: store i32 {{.*}}, i32* @"??_B?1??getS@@YAAAUS@@XZ@51" -// CHECK: call x86_thiscallcc noundef %struct.S* @"??0S@@QAE@XZ"(%struct.S* {{[^,]*}} @"?TheS@?1??getS@@YAAAUS@@XZ@4U2@A") +// CHECK: call x86_thiscallcc %struct.S* @"??0S@@QAE@XZ"(%struct.S* {{[^,]*}} @"?TheS@?1??getS@@YAAAUS@@XZ@4U2@A") // CHECK: call i32 @atexit(void ()* @"??__FTheS@?1??getS@@YAAAUS@@XZ@YAXXZ") // CHECK: br label // init.end: // CHECK: ret %struct.S* @"?TheS@?1??getS@@YAAAUS@@XZ@4U2@A" inline int enum_in_function() { - // CHECK-LABEL: define linkonce_odr dso_local noundef i32 @"?enum_in_function@@YAHXZ"() {{.*}} comdat + // CHECK-LABEL: define linkonce_odr dso_local i32 @"?enum_in_function@@YAHXZ"() {{.*}} comdat static enum e { foo, bar, baz } x; // CHECK: @"?x@?1??enum_in_function@@YAHXZ@4W4e@?1??1@YAHXZ@A" static int y; @@ -169,7 +169,7 @@ inline int enum_in_function() { struct T { enum e { foo, bar, baz }; int enum_in_struct() { - // CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc noundef i32 @"?enum_in_struct@T@@QAEHXZ"({{.*}}) {{.*}} comdat + // CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc i32 @"?enum_in_struct@T@@QAEHXZ"({{.*}}) {{.*}} comdat static int x; // CHECK: @"?x@?1??enum_in_struct@T@@QAEHXZ@4HA" return x++; @@ -177,7 +177,7 @@ struct T { }; inline int switch_test(int x) { - // CHECK-LABEL: define linkonce_odr dso_local noundef i32 @"?switch_test@@YAHH@Z"(i32 noundef %x) {{.*}} comdat + // CHECK-LABEL: define linkonce_odr dso_local i32 @"?switch_test@@YAHH@Z"(i32 %x) {{.*}} comdat switch (x) { static int a; // CHECK: @"?a@?3??switch_test@@YAHH@Z@4HA" @@ -213,7 +213,7 @@ namespace DynamicDLLImportInitVSMangling { template struct __declspec(dllimport) A; inline int switch_test3() { - // CHECK-LABEL: define linkonce_odr dso_local noundef i32 @"?switch_test3@DynamicDLLImportInitVSMangling@@YAHXZ"() {{.*}} comdat + // CHECK-LABEL: define linkonce_odr dso_local i32 @"?switch_test3@DynamicDLLImportInitVSMangling@@YAHXZ"() {{.*}} comdat static int local; // CHECK: @"?local@?1??switch_test3@DynamicDLLImportInitVSMangling@@YAHXZ@4HA" return local++; @@ -234,11 +234,11 @@ void force_usage() { // CHECK: define linkonce_odr dso_local void @"??__E?foo@?$B@H@@2VA@@A@@YAXXZ"() {{.*}} comdat // CHECK-NOT: and // CHECK-NOT: ?_Bfoo@ -// CHECK: call x86_thiscallcc noundef %class.A* @"??0A@@QAE@XZ" +// CHECK: call x86_thiscallcc %class.A* @"??0A@@QAE@XZ" // CHECK: call i32 @atexit(void ()* @"??__F?foo@?$B@H@@2VA@@A@@YAXXZ") // CHECK: ret void -// CHECK: define linkonce_odr dso_local x86_thiscallcc noundef %class.A* @"??0A@@QAE@XZ"({{.*}}) {{.*}} comdat +// CHECK: define linkonce_odr dso_local x86_thiscallcc %class.A* @"??0A@@QAE@XZ"({{.*}}) {{.*}} comdat // CHECK: define linkonce_odr dso_local x86_thiscallcc void @"??1A@@QAE@XZ"({{.*}}) {{.*}} comdat diff --git a/clang/test/CodeGenCXX/microsoft-abi-structors.cpp b/clang/test/CodeGenCXX/microsoft-abi-structors.cpp index ce99b9cd737c5d94869f578819e51a593192207e..1307afb7acb742be844b24f2c68d5b38d06a910e 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-structors.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-structors.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -emit-llvm -fno-rtti %s -std=c++11 -o - -mconstructor-aliases -triple=i386-pc-win32 -fno-rtti > %t +// RUN: %clang_cc1 -emit-llvm -fno-rtti %s -std=c++11 -o - -mconstructor-aliases -triple=i386-pc-win32 -fno-rtti > %t // RUN: FileCheck %s < %t // vftables are emitted very late, so do another pass to try to keep the checks // in source order. diff --git a/clang/test/CodeGenCXX/microsoft-abi-this-nullable.cpp b/clang/test/CodeGenCXX/microsoft-abi-this-nullable.cpp index c37cd4b419c3eaec5dd9641af02bf421c5e6a333..d038a4208ecddc134de863b13cf8057cfb6ff851 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-this-nullable.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-this-nullable.cpp @@ -49,5 +49,5 @@ void call_right_override(ChildOverride *child) { // // CHECK: %[[RIGHT:.*]] = getelementptr inbounds i8, i8* %[[CHILD_i8]], i32 4 // CHECK: %[[VFUN_VALUE:.*]] = load void (i8*)*, void (i8*)** %[[VFUN]] - // CHECK: call x86_thiscallcc void %[[VFUN_VALUE]](i8* noundef %[[RIGHT]]) + // CHECK: call x86_thiscallcc void %[[VFUN_VALUE]](i8* %[[RIGHT]]) } diff --git a/clang/test/CodeGenCXX/microsoft-abi-thread-safe-statics.cpp b/clang/test/CodeGenCXX/microsoft-abi-thread-safe-statics.cpp index 4923700ad340f7e8e1b32d60d54e0f3e4016421f..980b45bf1fa96376c38432a4c660020fbfb2b0d0 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-thread-safe-statics.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-thread-safe-statics.cpp @@ -89,7 +89,7 @@ extern inline S&h(bool b) { return b ? j : i; } -// CHECK-LABEL: define dso_local noundef i32 @"?g1@@YAHXZ"() +// CHECK-LABEL: define dso_local i32 @"?g1@@YAHXZ"() int f1(); int g1() { static int i = f1(); diff --git a/clang/test/CodeGenCXX/microsoft-abi-throw.cpp b/clang/test/CodeGenCXX/microsoft-abi-throw.cpp index 2ff067e0e2912e4bcbab6a005f32e1304b6222c6..7bf65c79a46389225d61482ce2c06db11ee2cca2 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-throw.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-throw.cpp @@ -37,7 +37,7 @@ struct Y : Z, W, virtual V {}; void f(const Y &y) { // CHECK-LABEL: @"?f@@YAXABUY@@@Z" - // CHECK: call x86_thiscallcc noundef %struct.Y* @"??0Y@@QAE@ABU0@@Z"(%struct.Y* {{[^,]*}} %[[mem:.*]], %struct.Y* + // CHECK: call x86_thiscallcc %struct.Y* @"??0Y@@QAE@ABU0@@Z"(%struct.Y* {{[^,]*}} %[[mem:.*]], %struct.Y* // CHECK: %[[cast:.*]] = bitcast %struct.Y* %[[mem]] to i8* // CHECK: call void @_CxxThrowException(i8* %[[cast]], %eh.ThrowInfo* @"_TI5?AUY@@") throw y; @@ -66,7 +66,7 @@ struct Default { // CHECK: store {{.*}} %this, {{.*}} %[[this_addr]], align 4 // CHECK: %[[this:.*]] = load {{.*}} %[[this_addr]] // CHECK: %[[src:.*]] = load {{.*}} %[[src_addr]] -// CHECK: call x86_thiscallcc {{.*}} @"??0Default@@QAE@AAU0@H@Z"({{.*}} %[[this]], {{.*}} %[[src]], i32 noundef 42) +// CHECK: call x86_thiscallcc {{.*}} @"??0Default@@QAE@AAU0@H@Z"({{.*}} %[[this]], {{.*}} %[[src]], i32 42) // CHECK: ret void void h(Default &d) { diff --git a/clang/test/CodeGenCXX/microsoft-abi-thunks.cpp b/clang/test/CodeGenCXX/microsoft-abi-thunks.cpp index 1d31e1ae3a729286b5c1e1bfff06c6d92d05e48c..2b0231ffe74e4599d0b9e1c494d76496f938d5fe 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-thunks.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-thunks.cpp @@ -61,10 +61,10 @@ struct C : A, B { C::C() {} // Emits vftable and forces thunk generation. -// CODEGEN-LABEL: define linkonce_odr dso_local x86_thiscallcc noundef i8* @"??_EC@@W3AEPAXI@Z"(%struct.C* noundef %this, i32 noundef %should_call_delete) {{.*}} comdat +// CODEGEN-LABEL: define linkonce_odr dso_local x86_thiscallcc i8* @"??_EC@@W3AEPAXI@Z"(%struct.C* %this, i32 %should_call_delete) {{.*}} comdat // CODEGEN: getelementptr i8, i8* {{.*}}, i32 -4 // FIXME: should actually call _EC, not _GC. -// CODEGEN: call x86_thiscallcc noundef i8* @"??_GC@@UAEPAXI@Z" +// CODEGEN: call x86_thiscallcc i8* @"??_GC@@UAEPAXI@Z" // CODEGEN: ret // CODEGEN-LABEL: define linkonce_odr dso_local x86_thiscallcc void @"?public_f@C@@W3AEXXZ"(%struct.C* @@ -91,8 +91,8 @@ struct E : D { E::E() {} // Emits vftable and forces thunk generation. -// CODEGEN-LABEL: define weak_odr dso_local x86_thiscallcc noundef %struct.C* @"?goo@E@@QAEPAUB@@XZ"{{.*}} comdat -// CODEGEN: call x86_thiscallcc noundef %struct.C* @"?goo@E@@UAEPAUC@@XZ" +// CODEGEN-LABEL: define weak_odr dso_local x86_thiscallcc %struct.C* @"?goo@E@@QAEPAUB@@XZ"{{.*}} comdat +// CODEGEN: call x86_thiscallcc %struct.C* @"?goo@E@@UAEPAUC@@XZ" // CODEGEN: getelementptr inbounds i8, i8* {{.*}}, i32 4 // CODEGEN: ret @@ -124,8 +124,8 @@ struct I : D { I::I() {} // Emits vftable and forces thunk generation. -// CODEGEN-LABEL: define weak_odr dso_local x86_thiscallcc noundef %struct.{{[BF]}}* @"?goo@I@@QAEPAUB@@XZ"{{.*}} comdat -// CODEGEN: %[[ORIG_RET:.*]] = call x86_thiscallcc noundef %struct.F* @"?goo@I@@UAEPAUF@@XZ" +// CODEGEN-LABEL: define weak_odr dso_local x86_thiscallcc %struct.{{[BF]}}* @"?goo@I@@QAEPAUB@@XZ"{{.*}} comdat +// CODEGEN: %[[ORIG_RET:.*]] = call x86_thiscallcc %struct.F* @"?goo@I@@UAEPAUF@@XZ" // CODEGEN: %[[ORIG_RET_i8:.*]] = bitcast %struct.F* %[[ORIG_RET]] to i8* // CODEGEN: %[[VBPTR_i8:.*]] = getelementptr inbounds i8, i8* %[[ORIG_RET_i8]], i32 4 // CODEGEN: %[[VBPTR:.*]] = bitcast i8* %[[VBPTR_i8]] to i32** @@ -160,5 +160,5 @@ struct E : D { E::E() {} E e; // Class with internal linkage has internal linkage thunks. -// CODEGEN: define internal x86_thiscallcc noundef %struct.C* @"?goo@E@?A0x{{[^@]*}}@@QAEPAUB@@XZ" +// CODEGEN: define internal x86_thiscallcc %struct.C* @"?goo@E@?A0x{{[^@]*}}@@QAEPAUB@@XZ" } diff --git a/clang/test/CodeGenCXX/microsoft-abi-typeid.cpp b/clang/test/CodeGenCXX/microsoft-abi-typeid.cpp index 45c7dd9a6f1aca0db478ec1520c9091d990dc466..8598396f06441ce3bd4341a4c6d3024265f96c38 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-typeid.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-typeid.cpp @@ -12,20 +12,20 @@ extern int b; A* fn(); const std::type_info* test0_typeid() { return &typeid(int); } -// CHECK-LABEL: define dso_local noundef %struct.type_info* @"?test0_typeid@@YAPBUtype_info@@XZ"() +// CHECK-LABEL: define dso_local %struct.type_info* @"?test0_typeid@@YAPBUtype_info@@XZ"() // CHECK: ret %struct.type_info* bitcast (%rtti.TypeDescriptor2* @"??_R0H@8" to %struct.type_info*) const std::type_info* test1_typeid() { return &typeid(A); } -// CHECK-LABEL: define dso_local noundef %struct.type_info* @"?test1_typeid@@YAPBUtype_info@@XZ"() +// CHECK-LABEL: define dso_local %struct.type_info* @"?test1_typeid@@YAPBUtype_info@@XZ"() // CHECK: ret %struct.type_info* bitcast (%rtti.TypeDescriptor7* @"??_R0?AUA@@@8" to %struct.type_info*) const std::type_info* test2_typeid() { return &typeid(&a); } -// CHECK-LABEL: define dso_local noundef %struct.type_info* @"?test2_typeid@@YAPBUtype_info@@XZ"() +// CHECK-LABEL: define dso_local %struct.type_info* @"?test2_typeid@@YAPBUtype_info@@XZ"() // CHECK: ret %struct.type_info* bitcast (%rtti.TypeDescriptor7* @"??_R0PAUA@@@8" to %struct.type_info*) const std::type_info* test3_typeid() { return &typeid(*fn()); } -// CHECK-LABEL: define dso_local noundef %struct.type_info* @"?test3_typeid@@YAPBUtype_info@@XZ"() -// CHECK: [[CALL:%.*]] = call noundef %struct.A* @"?fn@@YAPAUA@@XZ"() +// CHECK-LABEL: define dso_local %struct.type_info* @"?test3_typeid@@YAPBUtype_info@@XZ"() +// CHECK: [[CALL:%.*]] = call %struct.A* @"?fn@@YAPAUA@@XZ"() // CHECK-NEXT: [[CMP:%.*]] = icmp eq %struct.A* [[CALL]], null // CHECK-NEXT: br i1 [[CMP]] // CHECK: call i8* @__RTtypeid(i8* null) @@ -41,15 +41,15 @@ const std::type_info* test3_typeid() { return &typeid(*fn()); } // CHECK-NEXT: ret %struct.type_info* [[RET]] const std::type_info* test4_typeid() { return &typeid(b); } -// CHECK: define dso_local noundef %struct.type_info* @"?test4_typeid@@YAPBUtype_info@@XZ"() +// CHECK: define dso_local %struct.type_info* @"?test4_typeid@@YAPBUtype_info@@XZ"() // CHECK: ret %struct.type_info* bitcast (%rtti.TypeDescriptor2* @"??_R0H@8" to %struct.type_info*) const std::type_info* test5_typeid() { return &typeid(v); } -// CHECK: define dso_local noundef %struct.type_info* @"?test5_typeid@@YAPBUtype_info@@XZ"() +// CHECK: define dso_local %struct.type_info* @"?test5_typeid@@YAPBUtype_info@@XZ"() // CHECK: ret %struct.type_info* bitcast (%rtti.TypeDescriptor7* @"??_R0?AUV@@@8" to %struct.type_info*) const std::type_info *test6_typeid() { return &typeid((V &)v); } -// CHECK: define dso_local noundef %struct.type_info* @"?test6_typeid@@YAPBUtype_info@@XZ"() +// CHECK: define dso_local %struct.type_info* @"?test6_typeid@@YAPBUtype_info@@XZ"() // CHECK: ret %struct.type_info* bitcast (%rtti.TypeDescriptor7* @"??_R0?AUV@@@8" to %struct.type_info*) namespace PR26329 { diff --git a/clang/test/CodeGenCXX/microsoft-abi-unknown-arch.cpp b/clang/test/CodeGenCXX/microsoft-abi-unknown-arch.cpp index 15ce523ada52f63f85f705f872e0284b946b7b7c..195ab40a6acd615e2a2fab4a006d2d224b81aa7e 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-unknown-arch.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-unknown-arch.cpp @@ -18,4 +18,4 @@ A B::foo(A x) { return x; } -// CHECK-LABEL: define{{.*}} void @"?foo@B@@QEAA?AUA@@U2@@Z"(%struct.B* {{[^,]*}} %this, %struct.A* noalias sret(%struct.A) align 4 %agg.result, %struct.A* noundef %x) +// CHECK-LABEL: define{{.*}} void @"?foo@B@@QEAA?AUA@@U2@@Z"(%struct.B* {{[^,]*}} %this, %struct.A* noalias sret(%struct.A) align 4 %agg.result, %struct.A* %x) diff --git a/clang/test/CodeGenCXX/microsoft-abi-vbase-dtor.cpp b/clang/test/CodeGenCXX/microsoft-abi-vbase-dtor.cpp index 4f938b5f7b94b979f91a5226eeae674a05fcbc64..f08eefe664c413acec795f8388a028dcf299c2d3 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-vbase-dtor.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-vbase-dtor.cpp @@ -13,7 +13,7 @@ struct HasCompleteDtor : virtual DefaultedDtor { }; void useCompleteDtor(HasCompleteDtor *p) { delete p; } -// CHECK-LABEL: define dso_local void @"?useCompleteDtor@@YAXPEAUHasCompleteDtor@@@Z"(%struct.HasCompleteDtor* noundef %p) +// CHECK-LABEL: define dso_local void @"?useCompleteDtor@@YAXPEAUHasCompleteDtor@@@Z"(%struct.HasCompleteDtor* %p) // CHECK: call void @"??_DHasCompleteDtor@@QEAAXXZ"({{.*}}) // CHECK-LABEL: define linkonce_odr dso_local void @"??_DHasCompleteDtor@@QEAAXXZ"(%struct.HasCompleteDtor* {{[^,]*}} %this) diff --git a/clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance-vtordisps.cpp b/clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance-vtordisps.cpp index 44583aaae5a50fafb9d2676f0bcdf91112b4ef4f..0120299a7da44111565a1430c035fc37afccb91e 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance-vtordisps.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance-vtordisps.cpp @@ -33,7 +33,7 @@ D::D() {} // Forces vftable emission. // CHECK: %[[VTORDISP:.*]] = load i32, i32* %[[VTORDISP_PTR]] // CHECK: %[[VTORDISP_NEG:.*]] = sub i32 0, %[[VTORDISP]] // CHECK: %[[ADJUSTED_i8:.*]] = getelementptr i8, i8* %[[ECX_i8]], i32 %[[VTORDISP_NEG]] -// CHECK: call x86_thiscallcc void @"?f@D@@UAEXXZ"(i8* noundef %[[ADJUSTED_i8]]) +// CHECK: call x86_thiscallcc void @"?f@D@@UAEXXZ"(i8* %[[ADJUSTED_i8]]) // CHECK: ret void // CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc void @"?f@D@@$4PPPPPPPI@3AEXXZ" @@ -46,7 +46,7 @@ D::D() {} // Forces vftable emission. // CHECK: %[[VTORDISP_NEG:.*]] = sub i32 0, %[[VTORDISP]] // CHECK: %[[VTORDISP_ADJUSTED_i8:.*]] = getelementptr i8, i8* %[[ECX_i8]], i32 %[[VTORDISP_NEG]] // CHECK: %[[ADJUSTED_i8:.*]] = getelementptr i8, i8* %[[VTORDISP_ADJUSTED_i8]], i32 -4 -// CHECK: call x86_thiscallcc void @"?f@D@@UAEXXZ"(i8* noundef %[[ADJUSTED_i8]]) +// CHECK: call x86_thiscallcc void @"?f@D@@UAEXXZ"(i8* %[[ADJUSTED_i8]]) // CHECK: ret void struct E : virtual A { @@ -82,5 +82,5 @@ G::G() {} // Forces vftable emission. // CHECK: %[[VBASE_OFFSET:.*]] = load i32, i32* %[[VBOFFSET_PTR]] // CHECK: %[[VBASE:.*]] = getelementptr inbounds i8, i8* %[[VBPTR_i8]], i32 %[[VBASE_OFFSET]] // CHECK: %[[ARG_i8:.*]] = getelementptr i8, i8* %[[VBASE]], i32 8 -// CHECK: call x86_thiscallcc void @"?f@E@@UAEXXZ"(i8* noundef %[[ARG_i8]]) +// CHECK: call x86_thiscallcc void @"?f@E@@UAEXXZ"(i8* %[[ARG_i8]]) // CHECK: ret void diff --git a/clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance.cpp b/clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance.cpp index 94ae67a451a91a3131554856d293094066fb18fb..69f5728c4855555ee1462bb7f2d8a4cae2b2d3c0 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-virtual-inheritance.cpp @@ -20,7 +20,7 @@ struct B : virtual VBase { }; B::B() { - // CHECK-LABEL: define dso_local x86_thiscallcc noundef %struct.B* @"??0B@@QAE@XZ" + // CHECK-LABEL: define dso_local x86_thiscallcc %struct.B* @"??0B@@QAE@XZ" // CHECK: %[[THIS:.*]] = load %struct.B*, %struct.B** // CHECK: br i1 %{{.*}}, label %[[INIT_VBASES:.*]], label %[[SKIP_VBASES:.*]] @@ -98,7 +98,7 @@ B::~B() { // CHECK2: call x86_thiscallcc void @"??1VBase@@UAE@XZ"(%struct.VBase* {{[^,]*}} %[[VBASE]]) // CHECK2: ret - // CHECK2-LABEL: define linkonce_odr dso_local x86_thiscallcc noundef i8* @"??_GB@@UAEPAXI@Z" + // CHECK2-LABEL: define linkonce_odr dso_local x86_thiscallcc i8* @"??_GB@@UAEPAXI@Z" // CHECK2: store %struct.B* %{{.*}}, %struct.B** %[[THIS_ADDR:.*]], align 4 // CHECK2: %[[THIS:.*]] = load %struct.B*, %struct.B** %[[THIS_ADDR]] // CHECK2: %[[THIS_PARAM_i8:.*]] = bitcast %struct.B* %[[THIS]] to i8* @@ -149,7 +149,7 @@ void B::foo() { } void call_vbase_bar(B *obj) { -// CHECK-LABEL: define dso_local void @"?call_vbase_bar@@YAXPAUB@@@Z"(%struct.B* noundef %obj) +// CHECK-LABEL: define dso_local void @"?call_vbase_bar@@YAXPAUB@@@Z"(%struct.B* %obj) // CHECK: %[[OBJ:.*]] = load %struct.B obj->bar(); @@ -178,13 +178,13 @@ void call_vbase_bar(B *obj) { // CHECK: %[[VFUN:.*]] = getelementptr inbounds void (i8*)*, void (i8*)** %[[VFTABLE]], i64 2 // CHECK: %[[VFUN_VALUE:.*]] = load void (i8*)*, void (i8*)** %[[VFUN]] // -// CHECK: call x86_thiscallcc void %[[VFUN_VALUE]](i8* noundef %[[VBASE]]) +// CHECK: call x86_thiscallcc void %[[VFUN_VALUE]](i8* %[[VBASE]]) // // CHECK: ret void } void delete_B(B *obj) { -// CHECK-LABEL: define dso_local void @"?delete_B@@YAXPAUB@@@Z"(%struct.B* noundef %obj) +// CHECK-LABEL: define dso_local void @"?delete_B@@YAXPAUB@@@Z"(%struct.B* %obj) // CHECK: %[[OBJ:.*]] = load %struct.B delete obj; @@ -211,14 +211,14 @@ void delete_B(B *obj) { // CHECK: %[[VFUN:.*]] = getelementptr inbounds i8* (%struct.B*, i32)*, i8* (%struct.B*, i32)** %[[VFTABLE]], i64 0 // CHECK: %[[VFUN_VALUE:.*]] = load i8* (%struct.B*, i32)*, i8* (%struct.B*, i32)** %[[VFUN]] // -// CHECK: call x86_thiscallcc noundef i8* %[[VFUN_VALUE]](%struct.B* {{[^,]*}} %[[VBASE]], i32 noundef 1) +// CHECK: call x86_thiscallcc i8* %[[VFUN_VALUE]](%struct.B* {{[^,]*}} %[[VBASE]], i32 1) // CHECK: ret void } void call_complete_dtor() { // CHECK-LABEL: define dso_local void @"?call_complete_dtor@@YAXXZ" B b; - // CHECK: call x86_thiscallcc noundef %struct.B* @"??0B@@QAE@XZ"(%struct.B* {{[^,]*}} %[[B:.*]], i32 noundef 1) + // CHECK: call x86_thiscallcc %struct.B* @"??0B@@QAE@XZ"(%struct.B* {{[^,]*}} %[[B:.*]], i32 1) // CHECK-NOT: getelementptr // CHECK: call x86_thiscallcc void @"??_DB@@QAEXXZ"(%struct.B* {{[^,]*}} %[[B]]) // CHECK: ret @@ -231,7 +231,7 @@ struct C : B { // Used to crash on an assertion. C::C() { -// CHECK-LABEL: define dso_local x86_thiscallcc noundef %struct.C* @"??0C@@QAE@XZ" +// CHECK-LABEL: define dso_local x86_thiscallcc %struct.C* @"??0C@@QAE@XZ" } namespace multiple_vbases { @@ -255,7 +255,7 @@ struct D : virtual A, virtual B, virtual C { }; D::D() { - // CHECK-LABEL: define dso_local x86_thiscallcc noundef %"struct.multiple_vbases::D"* @"??0D@multiple_vbases@@QAE@XZ" + // CHECK-LABEL: define dso_local x86_thiscallcc %"struct.multiple_vbases::D"* @"??0D@multiple_vbases@@QAE@XZ" // Just make sure we emit 3 vtordisps after initializing vfptrs. // CHECK: store i32 (...)** bitcast ({ [1 x i8*] }* @"??_7D@multiple_vbases@@6BA@1@@" to i32 (...)**), i32 (...)*** %{{.*}} // CHECK: store i32 (...)** bitcast ({ [1 x i8*] }* @"??_7D@multiple_vbases@@6BB@1@@" to i32 (...)**), i32 (...)*** %{{.*}} @@ -334,20 +334,20 @@ struct C : B, A { C() {} }; // call to B() from C(). void callC() { C x; } -// CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc noundef %"struct.test2::C"* @"??0C@test2@@QAE@XZ" -// CHECK: (%"struct.test2::C"* {{[^,]*}} returned %this, i32 noundef %is_most_derived) +// CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc %"struct.test2::C"* @"??0C@test2@@QAE@XZ" +// CHECK: (%"struct.test2::C"* {{[^,]*}} returned {{[^,]*}} %this, i32 %is_most_derived) // CHECK: br i1 // Virtual bases -// CHECK: call x86_thiscallcc noundef %"struct.test2::A"* @"??0A@test2@@QAE@XZ"(%"struct.test2::A"* {{[^,]*}} %{{.*}}) +// CHECK: call x86_thiscallcc %"struct.test2::A"* @"??0A@test2@@QAE@XZ"(%"struct.test2::A"* {{[^,]*}} %{{.*}}) // CHECK: br label // Non-virtual bases -// CHECK: call x86_thiscallcc noundef %"struct.test2::B"* @"??0B@test2@@QAE@XZ"(%"struct.test2::B"* {{[^,]*}} %{{.*}}, i32 noundef 0) -// CHECK: call x86_thiscallcc noundef %"struct.test2::A"* @"??0A@test2@@QAE@XZ"(%"struct.test2::A"* {{[^,]*}} %{{.*}}) +// CHECK: call x86_thiscallcc %"struct.test2::B"* @"??0B@test2@@QAE@XZ"(%"struct.test2::B"* {{[^,]*}} %{{.*}}, i32 0) +// CHECK: call x86_thiscallcc %"struct.test2::A"* @"??0A@test2@@QAE@XZ"(%"struct.test2::A"* {{[^,]*}} %{{.*}}) // CHECK: ret -// CHECK2-LABEL: define linkonce_odr dso_local x86_thiscallcc noundef %"struct.test2::B"* @"??0B@test2@@QAE@XZ" -// CHECK2: (%"struct.test2::B"* {{[^,]*}} returned %this, i32 noundef %is_most_derived) -// CHECK2: call x86_thiscallcc noundef %"struct.test2::A"* @"??0A@test2@@QAE@XZ"(%"struct.test2::A"* {{[^,]*}} %{{.*}}) +// CHECK2-LABEL: define linkonce_odr dso_local x86_thiscallcc %"struct.test2::B"* @"??0B@test2@@QAE@XZ" +// CHECK2: (%"struct.test2::B"* {{[^,]*}} returned {{[^,]*}} %this, i32 %is_most_derived) +// CHECK2: call x86_thiscallcc %"struct.test2::A"* @"??0A@test2@@QAE@XZ"(%"struct.test2::A"* {{[^,]*}} %{{.*}}) // CHECK2: ret } @@ -385,7 +385,7 @@ void D::bar() { // CHECK: %[[C:.*]] = bitcast i8* %[[C_i8]] to %"struct.test3::C"* // CHECK: %[[C_i8:.*]] = bitcast %"struct.test3::C"* %[[C]] to i8* // CHECK: %[[ARG:.*]] = getelementptr i8, i8* %[[C_i8]], i32 4 - // CHECK: call x86_thiscallcc void @"?foo@C@test3@@UAEXXZ"(i8* noundef %[[ARG]]) + // CHECK: call x86_thiscallcc void @"?foo@C@test3@@UAEXXZ"(i8* %[[ARG]]) // CHECK: ret } } @@ -421,14 +421,14 @@ C::~C() { } void destroy(C *obj) { - // CHECK-LABEL: define dso_local void @"?destroy@test4@@YAXPAUC@1@@Z"(%"struct.test4::C"* noundef %obj) + // CHECK-LABEL: define dso_local void @"?destroy@test4@@YAXPAUC@1@@Z"(%"struct.test4::C"* %obj) delete obj; // CHECK: %[[VPTR:.*]] = bitcast %"struct.test4::C"* %[[OBJ:.*]] to i8* (%"struct.test4::C"*, i32)*** // CHECK: %[[VFTABLE:.*]] = load i8* (%"struct.test4::C"*, i32)**, i8* (%"struct.test4::C"*, i32)*** %[[VPTR]] // CHECK: %[[VFTENTRY:.*]] = getelementptr inbounds i8* (%"struct.test4::C"*, i32)*, i8* (%"struct.test4::C"*, i32)** %[[VFTABLE]], i64 0 // CHECK: %[[VFUN:.*]] = load i8* (%"struct.test4::C"*, i32)*, i8* (%"struct.test4::C"*, i32)** %[[VFTENTRY]] - // CHECK: call x86_thiscallcc noundef i8* %[[VFUN]](%"struct.test4::C"* {{[^,]*}} %[[OBJ]], i32 noundef 1) + // CHECK: call x86_thiscallcc i8* %[[VFUN]](%"struct.test4::C"* {{[^,]*}} %[[OBJ]], i32 1) // CHECK: ret } @@ -454,7 +454,7 @@ E::~E() { } void destroy(E *obj) { - // CHECK-LABEL: define dso_local void @"?destroy@test4@@YAXPAUE@1@@Z"(%"struct.test4::E"* noundef %obj) + // CHECK-LABEL: define dso_local void @"?destroy@test4@@YAXPAUE@1@@Z"(%"struct.test4::E"* %obj) // CHECK-NOT: getelementptr // CHECK: %[[OBJ_i8:.*]] = bitcast %"struct.test4::E"* %[[OBJ]] to i8* @@ -467,7 +467,7 @@ void destroy(E *obj) { // CHECK: %[[VFTABLE:.*]] = load i8* (%"struct.test4::E"*, i32)**, i8* (%"struct.test4::E"*, i32)*** %[[VPTR]] // CHECK: %[[VFTENTRY:.*]] = getelementptr inbounds i8* (%"struct.test4::E"*, i32)*, i8* (%"struct.test4::E"*, i32)** %[[VFTABLE]], i64 0 // CHECK: %[[VFUN:.*]] = load i8* (%"struct.test4::E"*, i32)*, i8* (%"struct.test4::E"*, i32)** %[[VFTENTRY]] - // CHECK: call x86_thiscallcc noundef i8* %[[VFUN]](%"struct.test4::E"* {{[^,]*}} %[[B_as_E]], i32 noundef 1) + // CHECK: call x86_thiscallcc i8* %[[VFUN]](%"struct.test4::E"* {{[^,]*}} %[[B_as_E]], i32 1) delete obj; } @@ -488,7 +488,7 @@ struct C : B { }; C::C() : B() {} -// CHECK-LABEL: define dso_local x86_thiscallcc noundef %"struct.test5::C"* @"??0C@test5@@QAE@XZ"( +// CHECK-LABEL: define dso_local x86_thiscallcc %"struct.test5::C"* @"??0C@test5@@QAE@XZ"( // CHECK: %[[THIS:.*]] = load %"struct.test5::C"*, %"struct.test5::C"** // CHECK: br i1 %{{.*}}, label %[[INIT_VBASES:.*]], label %[[SKIP_VBASES:.*]] @@ -512,9 +512,9 @@ struct C final : A, B { void callit(C *p) { static_cast(p)->g(); } -// CHECK-LABEL: define dso_local void @"?callit@pr27621@@YAXPAUC@1@@Z"(%"struct.pr27621::C"* noundef %{{.*}}) +// CHECK-LABEL: define dso_local void @"?callit@pr27621@@YAXPAUC@1@@Z"(%"struct.pr27621::C"* %{{.*}}) // CHECK: %[[B_i8:.*]] = getelementptr i8, i8* %{{.*}}, i32 4 -// CHECK: call x86_thiscallcc void @"?g@C@pr27621@@UAEXXZ"(i8* noundef %[[B_i8]]) +// CHECK: call x86_thiscallcc void @"?g@C@pr27621@@UAEXXZ"(i8* %[[B_i8]]) } namespace test6 { @@ -528,7 +528,7 @@ class D : C { D(); }; D::D() : C() {} -// CHECK-LABEL: define dso_local x86_thiscallcc noundef %"class.test6::D"* @"??0D@test6@@AAE@XZ"( +// CHECK-LABEL: define dso_local x86_thiscallcc %"class.test6::D"* @"??0D@test6@@AAE@XZ"( // CHECK: %[[THIS:.*]] = load %"class.test6::D"*, %"class.test6::D"** // CHECK: br i1 %{{.*}}, label %[[INIT_VBASES:.*]], label %[[SKIP_VBASES:.*]] @@ -549,7 +549,7 @@ struct B { struct C : virtual B {}; struct D : virtual A, C {}; D d; -// CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc noundef i8* @"??_GD@pr36921@@UAEPAXI@Z"( +// CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc i8* @"??_GD@pr36921@@UAEPAXI@Z"( // CHECK: %[[THIS:.*]] = load %"struct.pr36921::D"*, %"struct.pr36921::D"** // CHECK: %[[THIS_UNADJ_i8:.*]] = bitcast %"struct.pr36921::D"* %[[THIS_RELOAD]] to i8* // CHECK: %[[THIS_ADJ_i8:.*]] = getelementptr inbounds i8, i8* %[[THIS_UNADJ_i8]], i32 -4 diff --git a/clang/test/CodeGenCXX/microsoft-abi-virtual-member-pointers.cpp b/clang/test/CodeGenCXX/microsoft-abi-virtual-member-pointers.cpp index e2acef69558757a7e1fa6a9c274bcb1719accfc3..5ebe612e00acddfc79c2513160b95e1f45f52797 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-virtual-member-pointers.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-virtual-member-pointers.cpp @@ -70,119 +70,119 @@ void f() { // Thunk for calling the 1st virtual function in C with no parameters. -// CHECK32-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@@$BA@AE"(%struct.C* noundef %this, ...) +// CHECK32-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@@$BA@AE"(%struct.C* %this, ...) // CHECK32: #[[ATTR:[0-9]+]] // CHECK32-NOT: unnamed_addr // CHECK32: comdat // CHECK32: [[VPTR:%.*]] = getelementptr inbounds void (%struct.C*, ...)*, void (%struct.C*, ...)** %{{.*}}, i64 0 // CHECK32: [[CALLEE:%.*]] = load void (%struct.C*, ...)*, void (%struct.C*, ...)** [[VPTR]] -// CHECK32: musttail call x86_thiscallcc void (%struct.C*, ...) [[CALLEE]](%struct.C* noundef %{{.*}}, ...) +// CHECK32: musttail call x86_thiscallcc void (%struct.C*, ...) [[CALLEE]](%struct.C* %{{.*}}, ...) // CHECK32-NEXT: ret void // CHECK32: } // -// CHECK64-LABEL: define linkonce_odr void @"??_9C@@$BA@AA"(%struct.C* noundef %this, ...) +// CHECK64-LABEL: define linkonce_odr void @"??_9C@@$BA@AA"(%struct.C* %this, ...) // CHECK64: #[[ATTR:[0-9]+]] // CHECK64-NOT: unnamed_addr // CHECK64: comdat // CHECK64: [[VPTR:%.*]] = getelementptr inbounds void (%struct.C*, ...)*, void (%struct.C*, ...)** %{{.*}}, i64 0 // CHECK64: [[CALLEE:%.*]] = load void (%struct.C*, ...)*, void (%struct.C*, ...)** [[VPTR]] -// CHECK64: musttail call void (%struct.C*, ...) [[CALLEE]](%struct.C* noundef %{{.*}}, ...) +// CHECK64: musttail call void (%struct.C*, ...) [[CALLEE]](%struct.C* %{{.*}}, ...) // CHECK64-NEXT: ret void // CHECK64: } // Thunk for calling the 2nd virtual function in C, taking int and double as parameters, returning int. -// CHECK32-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@@$B3AE"(%struct.C* noundef %this, ...) +// CHECK32-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@@$B3AE"(%struct.C* %this, ...) // CHECK32: #[[ATTR]] comdat // CHECK32: [[VPTR:%.*]] = getelementptr inbounds void (%struct.C*, ...)*, void (%struct.C*, ...)** %{{.*}}, i64 1 // CHECK32: [[CALLEE:%.*]] = load void (%struct.C*, ...)*, void (%struct.C*, ...)** [[VPTR]] -// CHECK32: musttail call x86_thiscallcc void (%struct.C*, ...) [[CALLEE]](%struct.C* noundef %{{.*}}, ...) +// CHECK32: musttail call x86_thiscallcc void (%struct.C*, ...) [[CALLEE]](%struct.C* %{{.*}}, ...) // CHECK32-NEXT: ret void // CHECK32: } // -// CHECK64-LABEL: define linkonce_odr void @"??_9C@@$B7AA"(%struct.C* noundef %this, ...) +// CHECK64-LABEL: define linkonce_odr void @"??_9C@@$B7AA"(%struct.C* %this, ...) // CHECK64: #[[ATTR]] comdat // CHECK64: [[VPTR:%.*]] = getelementptr inbounds void (%struct.C*, ...)*, void (%struct.C*, ...)** %{{.*}}, i64 1 // CHECK64: [[CALLEE:%.*]] = load void (%struct.C*, ...)*, void (%struct.C*, ...)** [[VPTR]] -// CHECK64: musttail call void (%struct.C*, ...) [[CALLEE]](%struct.C* noundef %{{.*}}, ...) +// CHECK64: musttail call void (%struct.C*, ...) [[CALLEE]](%struct.C* %{{.*}}, ...) // CHECK64-NEXT: ret void // CHECK64: } // Thunk for calling the 3rd virtual function in C, taking an int parameter, returning a struct. -// CHECK32-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@@$B7AE"(%struct.C* noundef %this, ...) +// CHECK32-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@@$B7AE"(%struct.C* %this, ...) // CHECK32: #[[ATTR]] comdat // CHECK32: [[VPTR:%.*]] = getelementptr inbounds void (%struct.C*, ...)*, void (%struct.C*, ...)** %{{.*}}, i64 2 // CHECK32: [[CALLEE:%.*]] = load void (%struct.C*, ...)*, void (%struct.C*, ...)** [[VPTR]] -// CHECK32: musttail call x86_thiscallcc void (%struct.C*, ...) [[CALLEE]](%struct.C* noundef %{{.*}}, ...) +// CHECK32: musttail call x86_thiscallcc void (%struct.C*, ...) [[CALLEE]](%struct.C* %{{.*}}, ...) // CHECK32-NEXT: ret void // CHECK32: } // -// CHECK64-LABEL: define linkonce_odr void @"??_9C@@$BBA@AA"(%struct.C* noundef %this, ...) +// CHECK64-LABEL: define linkonce_odr void @"??_9C@@$BBA@AA"(%struct.C* %this, ...) // CHECK64: #[[ATTR]] comdat // CHECK64: [[VPTR:%.*]] = getelementptr inbounds void (%struct.C*, ...)*, void (%struct.C*, ...)** %{{.*}}, i64 2 // CHECK64: [[CALLEE:%.*]] = load void (%struct.C*, ...)*, void (%struct.C*, ...)** [[VPTR]] -// CHECK64: musttail call void (%struct.C*, ...) [[CALLEE]](%struct.C* noundef %{{.*}}, ...) +// CHECK64: musttail call void (%struct.C*, ...) [[CALLEE]](%struct.C* %{{.*}}, ...) // CHECK64-NEXT: ret void // CHECK64: } // Thunk for calling the virtual function in internal class D. -// CHECK32-LABEL: define internal x86_thiscallcc void @"??_9D@?A0x{{[^@]*}}@@$BA@AE"(%"struct.(anonymous namespace)::D"* noundef %this, ...) +// CHECK32-LABEL: define internal x86_thiscallcc void @"??_9D@?A0x{{[^@]*}}@@$BA@AE"(%"struct.(anonymous namespace)::D"* %this, ...) // CHECK32: #[[ATTR]] // CHECK32: [[VPTR:%.*]] = getelementptr inbounds void (%"struct.(anonymous namespace)::D"*, ...)*, void (%"struct.(anonymous namespace)::D"*, ...)** %{{.*}}, i64 0 // CHECK32: [[CALLEE:%.*]] = load void (%"struct.(anonymous namespace)::D"*, ...)*, void (%"struct.(anonymous namespace)::D"*, ...)** [[VPTR]] -// CHECK32: musttail call x86_thiscallcc void (%"struct.(anonymous namespace)::D"*, ...) [[CALLEE]](%"struct.(anonymous namespace)::D"* noundef %{{.*}}, ...) +// CHECK32: musttail call x86_thiscallcc void (%"struct.(anonymous namespace)::D"*, ...) [[CALLEE]](%"struct.(anonymous namespace)::D"* %{{.*}}, ...) // CHECK32-NEXT: ret void // CHECK32: } // -// CHECK64-LABEL: define internal void @"??_9D@?A0x{{[^@]*}}@@$BA@AA"(%"struct.(anonymous namespace)::D"* noundef %this, ...) +// CHECK64-LABEL: define internal void @"??_9D@?A0x{{[^@]*}}@@$BA@AA"(%"struct.(anonymous namespace)::D"* %this, ...) // CHECK64: #[[ATTR]] // CHECK64: [[VPTR:%.*]] = getelementptr inbounds void (%"struct.(anonymous namespace)::D"*, ...)*, void (%"struct.(anonymous namespace)::D"*, ...)** %{{.*}}, i64 0 // CHECK64: [[CALLEE:%.*]] = load void (%"struct.(anonymous namespace)::D"*, ...)*, void (%"struct.(anonymous namespace)::D"*, ...)** [[VPTR]] -// CHECK64: musttail call void (%"struct.(anonymous namespace)::D"*, ...) [[CALLEE]](%"struct.(anonymous namespace)::D"* noundef %{{.*}}, ...) +// CHECK64: musttail call void (%"struct.(anonymous namespace)::D"*, ...) [[CALLEE]](%"struct.(anonymous namespace)::D"* %{{.*}}, ...) // CHECK64-NEXT: ret void // CHECK64: } // Thunk for calling the fourth virtual function in C, taking a struct parameter // and returning a struct. -// CHECK32-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@@$BM@AE"(%struct.C* noundef %this, ...) {{.*}} comdat +// CHECK32-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@@$BM@AE"(%struct.C* %this, ...) {{.*}} comdat // CHECK32: [[VPTR:%.*]] = getelementptr inbounds void (%struct.C*, ...)*, void (%struct.C*, ...)** %{{.*}}, i64 3 // CHECK32: [[CALLEE:%.*]] = load void (%struct.C*, ...)*, void (%struct.C*, ...)** [[VPTR]] -// CHECK32: musttail call x86_thiscallcc void (%struct.C*, ...) [[CALLEE]](%struct.C* noundef %{{.*}}, ...) +// CHECK32: musttail call x86_thiscallcc void (%struct.C*, ...) [[CALLEE]](%struct.C* %{{.*}}, ...) // CHECK32-NEXT: ret void // CHECK32: } // -// CHECK64-LABEL: define linkonce_odr void @"??_9C@@$BBI@AA"(%struct.C* noundef %this, ...) {{.*}} comdat +// CHECK64-LABEL: define linkonce_odr void @"??_9C@@$BBI@AA"(%struct.C* %this, ...) {{.*}} comdat // CHECK64: [[VPTR:%.*]] = getelementptr inbounds void (%struct.C*, ...)*, void (%struct.C*, ...)** %{{.*}}, i64 3 // CHECK64: [[CALLEE:%.*]] = load void (%struct.C*, ...)*, void (%struct.C*, ...)** [[VPTR]] -// CHECK64: musttail call void (%struct.C*, ...) [[CALLEE]](%struct.C* noundef %{{.*}}, ...) +// CHECK64: musttail call void (%struct.C*, ...) [[CALLEE]](%struct.C* %{{.*}}, ...) // CHECK64: ret void // CHECK64: } // Thunk for calling the fifth virtual function in C which uses the __cdecl calling convention. -// CHECK32-LABEL: define linkonce_odr void @"??_9C@@$BBA@AA"(%struct.C* noundef %this, ...) {{.*}} comdat align 2 { +// CHECK32-LABEL: define linkonce_odr void @"??_9C@@$BBA@AA"(%struct.C* %this, ...) {{.*}} comdat align 2 { // CHECK32: [[VPTR:%.*]] = getelementptr inbounds void (%struct.C*, ...)*, void (%struct.C*, ...)** %{{.*}}, i64 4 // CHECK32: [[CALLEE:%.*]] = load void (%struct.C*, ...)*, void (%struct.C*, ...)** [[VPTR]] -// CHECK32: musttail call void (%struct.C*, ...) [[CALLEE]](%struct.C* noundef %{{.*}}, ...) +// CHECK32: musttail call void (%struct.C*, ...) [[CALLEE]](%struct.C* %{{.*}}, ...) // CHECK32: ret void // CHECK32: } // -// CHECK64-LABEL: define linkonce_odr void @"??_9C@@$BCA@AA"(%struct.C* noundef %this, ...) {{.*}} comdat align 2 { +// CHECK64-LABEL: define linkonce_odr void @"??_9C@@$BCA@AA"(%struct.C* %this, ...) {{.*}} comdat align 2 { // CHECK64: [[VPTR:%.*]] = getelementptr inbounds void (%struct.C*, ...)*, void (%struct.C*, ...)** %{{.*}}, i64 4 // CHECK64: [[CALLEE:%.*]] = load void (%struct.C*, ...)*, void (%struct.C*, ...)** [[VPTR]] -// CHECK64: musttail call void (%struct.C*, ...) [[CALLEE]](%struct.C* noundef %{{.*}}, ...) +// CHECK64: musttail call void (%struct.C*, ...) [[CALLEE]](%struct.C* %{{.*}}, ...) // CHECK64: ret void // CHECK64: } -// CHECK32: define linkonce_odr x86_thiscallcc void @"??_9C@@$BBE@AE"(%struct.C* noundef %this, ...) {{.*}} comdat align 2 { +// CHECK32: define linkonce_odr x86_thiscallcc void @"??_9C@@$BBE@AE"(%struct.C* %this, ...) {{.*}} comdat align 2 { // CHECK32: [[VPTR:%.*]] = getelementptr inbounds void (%struct.C*, ...)*, void (%struct.C*, ...)** %{{.*}}, i64 5 // CHECK32: [[CALLEE:%.*]] = load void (%struct.C*, ...)*, void (%struct.C*, ...)** [[VPTR]] -// CHECK32: musttail call x86_thiscallcc void (%struct.C*, ...) [[CALLEE]](%struct.C* noundef %{{.*}}, ...) +// CHECK32: musttail call x86_thiscallcc void (%struct.C*, ...) [[CALLEE]](%struct.C* %{{.*}}, ...) // CHECK32: ret void // CHECK32: } -// CHECK64: define linkonce_odr void @"??_9C@@$BCI@AA"(%struct.C* noundef %this, ...) {{.*}} comdat align 2 { +// CHECK64: define linkonce_odr void @"??_9C@@$BCI@AA"(%struct.C* %this, ...) {{.*}} comdat align 2 { // CHECK64: [[VPTR:%.*]] = getelementptr inbounds void (%struct.C*, ...)*, void (%struct.C*, ...)** %{{.*}}, i64 5 // CHECK64: [[CALLEE:%.*]] = load void (%struct.C*, ...)*, void (%struct.C*, ...)** [[VPTR]] -// CHECK64: musttail call void (%struct.C*, ...) [[CALLEE]](%struct.C* noundef %{{.*}}, ...) +// CHECK64: musttail call void (%struct.C*, ...) [[CALLEE]](%struct.C* %{{.*}}, ...) // CHECK64: ret void // CHECK64: } diff --git a/clang/test/CodeGenCXX/microsoft-abi-vmemptr-conflicts.cpp b/clang/test/CodeGenCXX/microsoft-abi-vmemptr-conflicts.cpp index 6cf546f92280a143c47204e964e6e46a2802f307..e71d6238c53add791bc6332c0552a2a5c348990b 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-vmemptr-conflicts.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-vmemptr-conflicts.cpp @@ -19,12 +19,12 @@ void f(C *c) { } } -// CHECK-LABEL: define dso_local void @"?f@num_params@@YAXPAUC@1@@Z"(%"struct.num_params::C"* noundef %c) -// CHECK: call x86_thiscallcc void bitcast (void (%"struct.num_params::C"*, ...)* @"??_9C@num_params@@$BA@AE" to void (%"struct.num_params::C"*, i32)*)(%"struct.num_params::C"* {{[^,]*}} %{{.*}}, i32 noundef 0) -// CHECK: call x86_thiscallcc void bitcast (void (%"struct.num_params::C"*, ...)* @"??_9C@num_params@@$BA@AE" to void (%"struct.num_params::C"*, i32, i32)*)(%"struct.num_params::C"* {{[^,]*}} %{{.*}}, i32 noundef 0, i32 noundef 0) +// CHECK-LABEL: define dso_local void @"?f@num_params@@YAXPAUC@1@@Z"(%"struct.num_params::C"* %c) +// CHECK: call x86_thiscallcc void bitcast (void (%"struct.num_params::C"*, ...)* @"??_9C@num_params@@$BA@AE" to void (%"struct.num_params::C"*, i32)*)(%"struct.num_params::C"* {{[^,]*}} %{{.*}}, i32 0) +// CHECK: call x86_thiscallcc void bitcast (void (%"struct.num_params::C"*, ...)* @"??_9C@num_params@@$BA@AE" to void (%"struct.num_params::C"*, i32, i32)*)(%"struct.num_params::C"* {{[^,]*}} %{{.*}}, i32 0, i32 0) -// CHECK-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@num_params@@$BA@AE"(%"struct.num_params::C"* noundef %this, ...) {{.*}} comdat -// CHECK: musttail call x86_thiscallcc void (%"struct.num_params::C"*, ...) %{{.*}}(%"struct.num_params::C"* noundef %{{.*}}, ...) +// CHECK-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@num_params@@$BA@AE"(%"struct.num_params::C"* %this, ...) {{.*}} comdat +// CHECK: musttail call x86_thiscallcc void (%"struct.num_params::C"*, ...) %{{.*}}(%"struct.num_params::C"* %{{.*}}, ...) // CHECK-NEXT: ret void namespace i64_return { @@ -41,12 +41,12 @@ long long f(C *c) { } } -// CHECK-LABEL: define dso_local noundef i64 @"?f@i64_return@@YA_JPAUC@1@@Z"(%"struct.i64_return::C"* noundef %c) -// CHECK: call x86_thiscallcc noundef i32 bitcast (void (%"struct.i64_return::C"*, ...)* @"??_9C@i64_return@@$BA@AE" to i32 (%"struct.i64_return::C"*)*)(%"struct.i64_return::C"* {{[^,]*}} %{{.*}}) -// CHECK: call x86_thiscallcc noundef i64 bitcast (void (%"struct.i64_return::C"*, ...)* @"??_9C@i64_return@@$BA@AE" to i64 (%"struct.i64_return::C"*)*)(%"struct.i64_return::C"* {{[^,]*}} %{{.*}}) +// CHECK-LABEL: define dso_local i64 @"?f@i64_return@@YA_JPAUC@1@@Z"(%"struct.i64_return::C"* %c) +// CHECK: call x86_thiscallcc i32 bitcast (void (%"struct.i64_return::C"*, ...)* @"??_9C@i64_return@@$BA@AE" to i32 (%"struct.i64_return::C"*)*)(%"struct.i64_return::C"* {{[^,]*}} %{{.*}}) +// CHECK: call x86_thiscallcc i64 bitcast (void (%"struct.i64_return::C"*, ...)* @"??_9C@i64_return@@$BA@AE" to i64 (%"struct.i64_return::C"*)*)(%"struct.i64_return::C"* {{[^,]*}} %{{.*}}) -// CHECK-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@i64_return@@$BA@AE"(%"struct.i64_return::C"* noundef %this, ...) {{.*}} comdat -// CHECK: musttail call x86_thiscallcc void (%"struct.i64_return::C"*, ...) %{{.*}}(%"struct.i64_return::C"* noundef %{{.*}}, ...) +// CHECK-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@i64_return@@$BA@AE"(%"struct.i64_return::C"* %this, ...) {{.*}} comdat +// CHECK: musttail call x86_thiscallcc void (%"struct.i64_return::C"*, ...) %{{.*}}(%"struct.i64_return::C"* %{{.*}}, ...) // CHECK-NEXT: ret void namespace sret { @@ -63,12 +63,12 @@ void f(C *c) { } } -// CHECK-LABEL: define dso_local void @"?f@sret@@YAXPAUC@1@@Z"(%"struct.sret::C"* noundef %c) -// CHECK: call x86_thiscallcc noundef i32 bitcast (void (%"struct.sret::C"*, ...)* @"??_9C@sret@@$BA@AE" to i32 (%"struct.sret::C"*)*)(%"struct.sret::C"* {{[^,]*}} %{{.*}}) +// CHECK-LABEL: define dso_local void @"?f@sret@@YAXPAUC@1@@Z"(%"struct.sret::C"* %c) +// CHECK: call x86_thiscallcc i32 bitcast (void (%"struct.sret::C"*, ...)* @"??_9C@sret@@$BA@AE" to i32 (%"struct.sret::C"*)*)(%"struct.sret::C"* {{[^,]*}} %{{.*}}) // CHECK: call x86_thiscallcc void bitcast (void (%"struct.sret::C"*, ...)* @"??_9C@sret@@$BA@AE" to void (%"struct.sret::C"*, %"struct.sret::Big"*)*)(%"struct.sret::C"* {{[^,]*}} %{{.*}}, %"struct.sret::Big"* sret(%"struct.sret::Big") align 4 %{{.*}}) -// CHECK-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@sret@@$BA@AE"(%"struct.sret::C"* noundef %this, ...) {{.*}} comdat -// CHECK: musttail call x86_thiscallcc void (%"struct.sret::C"*, ...) %{{.*}}(%"struct.sret::C"* noundef %{{.*}}, ...) +// CHECK-LABEL: define linkonce_odr x86_thiscallcc void @"??_9C@sret@@$BA@AE"(%"struct.sret::C"* %this, ...) {{.*}} comdat +// CHECK: musttail call x86_thiscallcc void (%"struct.sret::C"*, ...) %{{.*}}(%"struct.sret::C"* %{{.*}}, ...) // CHECK-NEXT: ret void namespace cdecl_inalloca { @@ -92,10 +92,10 @@ void f(C *c) { } } -// CHECK-LABEL: define dso_local void @"?f@cdecl_inalloca@@YAXPAUC@1@@Z"(%"struct.cdecl_inalloca::C"* noundef %c) +// CHECK-LABEL: define dso_local void @"?f@cdecl_inalloca@@YAXPAUC@1@@Z"(%"struct.cdecl_inalloca::C"* %c) // CHECK: call void bitcast (void (%"struct.cdecl_inalloca::C"*, ...)* @"??_9C@cdecl_inalloca@@$BA@AA" to void (%"struct.cdecl_inalloca::C"*)*)(%"struct.cdecl_inalloca::C"* {{[^,]*}} %{{.*}}) // CHECK: call void bitcast (void (%"struct.cdecl_inalloca::C"*, ...)* @"??_9C@cdecl_inalloca@@$BA@AA" to void (<{ %"struct.cdecl_inalloca::C"*, %"struct.cdecl_inalloca::Big" }>*)*)(<{ %"struct.cdecl_inalloca::C"*, %"struct.cdecl_inalloca::Big" }>* inalloca(<{ %"struct.cdecl_inalloca::C"*, %"struct.cdecl_inalloca::Big" }>) %{{.*}}) -// CHECK-LABEL: define linkonce_odr void @"??_9C@cdecl_inalloca@@$BA@AA"(%"struct.cdecl_inalloca::C"* noundef %this, ...) {{.*}} comdat -// CHECK: musttail call void (%"struct.cdecl_inalloca::C"*, ...) %{{.*}}(%"struct.cdecl_inalloca::C"* noundef %{{.*}}, ...) +// CHECK-LABEL: define linkonce_odr void @"??_9C@cdecl_inalloca@@$BA@AA"(%"struct.cdecl_inalloca::C"* %this, ...) {{.*}} comdat +// CHECK: musttail call void (%"struct.cdecl_inalloca::C"*, ...) %{{.*}}(%"struct.cdecl_inalloca::C"* %{{.*}}, ...) // CHECK-NEXT: ret void diff --git a/clang/test/CodeGenCXX/microsoft-abi-vmemptr-fastcall.cpp b/clang/test/CodeGenCXX/microsoft-abi-vmemptr-fastcall.cpp index aeaf729b9071a2f2d52018e87e21ea4e3943abdc..59e8b0b8c2c89d0f01ded1a0e71bec7c2e1512dd 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-vmemptr-fastcall.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-vmemptr-fastcall.cpp @@ -7,9 +7,9 @@ void (__fastcall A::*doit())(int, int) { return &A::f; } -// CHECK: define linkonce_odr x86_fastcallcc void @"??_9A@@$BA@AI"(%struct.A* inreg noundef %this, ...) {{.*}} comdat align 2 { +// CHECK: define linkonce_odr x86_fastcallcc void @"??_9A@@$BA@AI"(%struct.A* inreg %this, ...) {{.*}} comdat align 2 { // CHECK: [[VPTR:%.*]] = getelementptr inbounds void (%struct.A*, ...)*, void (%struct.A*, ...)** %{{.*}}, i64 0 // CHECK: [[CALLEE:%.*]] = load void (%struct.A*, ...)*, void (%struct.A*, ...)** [[VPTR]] -// CHECK: musttail call x86_fastcallcc void (%struct.A*, ...) [[CALLEE]](%struct.A* inreg noundef %{{.*}}, ...) +// CHECK: musttail call x86_fastcallcc void (%struct.A*, ...) [[CALLEE]](%struct.A* inreg %{{.*}}, ...) // CHECK: ret void // CHECK: } diff --git a/clang/test/CodeGenCXX/microsoft-abi-vtables-multiple-nonvirtual-inheritance-this-adjustment.cpp b/clang/test/CodeGenCXX/microsoft-abi-vtables-multiple-nonvirtual-inheritance-this-adjustment.cpp index 9b8cd1d9bb55b573c4451fc8ae15ac87da80d3a8..5cced42834e1b177f2ea1b645063550cc3f9f9ec 100644 --- a/clang/test/CodeGenCXX/microsoft-abi-vtables-multiple-nonvirtual-inheritance-this-adjustment.cpp +++ b/clang/test/CodeGenCXX/microsoft-abi-vtables-multiple-nonvirtual-inheritance-this-adjustment.cpp @@ -158,7 +158,7 @@ struct C : public A, public B { void ffun(C &c) { // BITCODE: [[THIS1:%.+]] = bitcast %"struct.test4::C"* {{.*}} to i8* // BITCODE: [[THIS2:%.+]] = getelementptr inbounds i8, i8* [[THIS1]], i32 4 - // BITCODE: call x86_thiscallcc {{.*}}(i8* noundef [[THIS2]]) + // BITCODE: call x86_thiscallcc {{.*}}(i8* [[THIS2]]) c.bar(); } @@ -166,7 +166,7 @@ void ffun(C &c) { void fop(C &c) { // BITCODE: [[THIS1:%.+]] = bitcast %"struct.test4::C"* {{.*}} to i8* // BITCODE: [[THIS2:%.+]] = getelementptr inbounds i8, i8* [[THIS1]], i32 4 - // BITCODE: call x86_thiscallcc {{.*}}(i8* noundef [[THIS2]]) + // BITCODE: call x86_thiscallcc {{.*}}(i8* [[THIS2]]) -c; } diff --git a/clang/test/CodeGenCXX/microsoft-compatibility.cpp b/clang/test/CodeGenCXX/microsoft-compatibility.cpp index 5791cd21ef1d9ba17be61a509f443a3f63bddb55..64d10a54c006224bec7b36df0c04ff126704ce6d 100644 --- a/clang/test/CodeGenCXX/microsoft-compatibility.cpp +++ b/clang/test/CodeGenCXX/microsoft-compatibility.cpp @@ -24,7 +24,7 @@ extern "C" void f() { // CHECK: call void @"??$destroy@X@@YAXPAX@Z" // CHECK: ret void -// CHECK-LABEL: define linkonce_odr dso_local void @"??$destroy@X@@YAXPAX@Z"(i8* noundef %p) +// CHECK-LABEL: define linkonce_odr dso_local void @"??$destroy@X@@YAXPAX@Z"(i8* %p) // The pseudo-dtor expr should not generate calls to anything. // CHECK-NOT: call // CHECK-NOT: invoke diff --git a/clang/test/CodeGenCXX/microsoft-inaccessible-base.cpp b/clang/test/CodeGenCXX/microsoft-inaccessible-base.cpp index 4a519b2c369a5cb0b9666fad9ddfd99010ac4456..d8af8ef9eaf7f7e2e2033ff0c7a6eb351532183b 100644 --- a/clang/test/CodeGenCXX/microsoft-inaccessible-base.cpp +++ b/clang/test/CodeGenCXX/microsoft-inaccessible-base.cpp @@ -10,11 +10,11 @@ struct B : A { int b; }; struct C : A, B { }; extern "C" A *a_from_c(C *p) { return p; } -// CHECK-LABEL: define dso_local %struct.A* @a_from_c(%struct.C* noundef %{{.*}}) +// CHECK-LABEL: define dso_local %struct.A* @a_from_c(%struct.C* %{{.*}}) // CHECK: bitcast %struct.C* %{{.*}} to %struct.A* struct D : B, A { }; extern "C" A *a_from_d(D *p) { return p; } -// CHECK-LABEL: define dso_local %struct.A* @a_from_d(%struct.D* noundef %{{.*}}) +// CHECK-LABEL: define dso_local %struct.A* @a_from_d(%struct.D* %{{.*}}) // CHECK: %[[p_i8:[^ ]*]] = bitcast %struct.D* %{{.*}} to i8* // CHECK: getelementptr inbounds i8, i8* %[[p_i8]], i64 8 diff --git a/clang/test/CodeGenCXX/microsoft-interface.cpp b/clang/test/CodeGenCXX/microsoft-interface.cpp index 9267fcae0247e25028f71808b621fff174173e61..bfc4b5acffc4ab3003ed6449bf28082f179b0021 100644 --- a/clang/test/CodeGenCXX/microsoft-interface.cpp +++ b/clang/test/CodeGenCXX/microsoft-interface.cpp @@ -19,15 +19,15 @@ int fn() { // CHECK: @_ZTV1S = linkonce_odr dso_local unnamed_addr constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* bitcast ({ i8*, i8*, i8* }* @_ZTI1S to i8*), i8* bitcast (i32 (%struct.S*)* @_ZN1S4testEv to i8*)] } -// CHECK-LABEL: define dso_local noundef i32 @_Z2fnv() +// CHECK-LABEL: define dso_local i32 @_Z2fnv() // CHECK: call x86_thiscallcc void @_ZN1SC1Ev(%struct.S* {{[^,]*}} %s) -// CHECK: %{{[.0-9A-Z_a-z]+}} = call x86_thiscallcc noundef i32 @_ZN1S4testEv(%struct.S* {{[^,]*}} %s) +// CHECK: %{{[.0-9A-Z_a-z]+}} = call x86_thiscallcc i32 @_ZN1S4testEv(%struct.S* {{[^,]*}} %s) // CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc void @_ZN1SC1Ev(%struct.S* {{[^,]*}} %this) // CHECK: call x86_thiscallcc void @_ZN1SC2Ev(%struct.S* {{[^,]*}} %{{[.0-9A-Z_a-z]+}}) -// CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc noundef i32 @_ZN1S4testEv(%struct.S* {{[^,]*}} %this) -// CHECK: %{{[.0-9A-Z_a-z]+}} = call x86_thiscallcc noundef i32 @_ZN1I4testEv(%__interface.I* {{[^,]*}} %{{[.0-9A-Z_a-z]+}}) +// CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc i32 @_ZN1S4testEv(%struct.S* {{[^,]*}} %this) +// CHECK: %{{[.0-9A-Z_a-z]+}} = call x86_thiscallcc i32 @_ZN1I4testEv(%__interface.I* {{[^,]*}} %{{[.0-9A-Z_a-z]+}}) // CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc void @_ZN1SC2Ev(%struct.S* {{[^,]*}} %this) // CHECK: call x86_thiscallcc void @_ZN1IC2Ev(%__interface.I* {{[^,]*}} %{{[.0-9A-Z_a-z]+}}) @@ -36,5 +36,5 @@ int fn() { // CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc void @_ZN1IC2Ev(%__interface.I* {{[^,]*}} %this) // CHECK: store i32 (...)** bitcast (i8** getelementptr inbounds ({ [3 x i8*] }, { [3 x i8*] }* @_ZTV1I, i32 0, inrange i32 0, i32 2) to i32 (...)**), i32 (...)*** %{{[.0-9A-Z_a-z]+}} -// CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc noundef i32 @_ZN1I4testEv(%__interface.I* {{[^,]*}} %this) +// CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc i32 @_ZN1I4testEv(%__interface.I* {{[^,]*}} %this) // CHECK: ret i32 1 diff --git a/clang/test/CodeGenCXX/microsoft-new.cpp b/clang/test/CodeGenCXX/microsoft-new.cpp index 6a7e34463c689692f5d6f46dd043817164472dec..01b0960968be7233320d991292036f0be0a4e18e 100644 --- a/clang/test/CodeGenCXX/microsoft-new.cpp +++ b/clang/test/CodeGenCXX/microsoft-new.cpp @@ -13,7 +13,7 @@ namespace PR13164 { // MSVC will fall back on the non-array operator new. void *a; int *p = new(arbitrary) int[4]; - // CHECK: call noundef i8* @"??2@YAPAXIUarbitrary_t@@@Z"(i32 noundef 16, %struct.arbitrary_t* + // CHECK: call i8* @"??2@YAPAXIUarbitrary_t@@@Z"(i32 16, %struct.arbitrary_t* } struct S { @@ -22,9 +22,9 @@ namespace PR13164 { void g() { S *s = new(arbitrary) S[2]; - // CHECK: call noundef i8* @"??_US@PR13164@@SAPAXIUarbitrary_t@@@Z"(i32 noundef 2, %struct.arbitrary_t* + // CHECK: call i8* @"??_US@PR13164@@SAPAXIUarbitrary_t@@@Z"(i32 2, %struct.arbitrary_t* S *s1 = new(arbitrary) S; - // CHECK: call noundef i8* @"??2@YAPAXIUarbitrary_t@@@Z"(i32 noundef 1, %struct.arbitrary_t* + // CHECK: call i8* @"??2@YAPAXIUarbitrary_t@@@Z"(i32 1, %struct.arbitrary_t* } struct T { @@ -34,6 +34,6 @@ namespace PR13164 { void h() { // This should still call the global operator new[]. T *t = new(arbitrary2) T[2]; - // CHECK: call noundef i8* @"??_U@YAPAXIUarbitrary2_t@@@Z"(i32 noundef 2, %struct.arbitrary2_t* + // CHECK: call i8* @"??_U@YAPAXIUarbitrary2_t@@@Z"(i32 2, %struct.arbitrary2_t* } } diff --git a/clang/test/CodeGenCXX/mips-size_t-ptrdiff_t.cpp b/clang/test/CodeGenCXX/mips-size_t-ptrdiff_t.cpp index 243b6ec298d94e21ce3dd074b771be1de0bb7526..42768ac90f7d0bf577adf141bec1c51392d48485 100644 --- a/clang/test/CodeGenCXX/mips-size_t-ptrdiff_t.cpp +++ b/clang/test/CodeGenCXX/mips-size_t-ptrdiff_t.cpp @@ -10,13 +10,13 @@ long *alloc_long() { return rv; } // O32-LABEL: define{{.*}} i32* @_Z10alloc_longv() -// O32: call noalias noundef nonnull i8* @_Znwj(i32 noundef signext 4) +// O32: call noalias nonnull i8* @_Znwj(i32 signext 4) // N32-LABEL: define{{.*}} i32* @_Z10alloc_longv() -// N32: call noalias noundef nonnull i8* @_Znwj(i32 noundef signext 4) +// N32: call noalias nonnull i8* @_Znwj(i32 signext 4) // N64-LABEL: define{{.*}} i64* @_Z10alloc_longv() -// N64: call noalias noundef nonnull i8* @_Znwm(i64 noundef zeroext 8) +// N64: call noalias nonnull i8* @_Znwm(i64 zeroext 8) long *alloc_long_array() { long *rv = new long[2]; @@ -24,13 +24,13 @@ long *alloc_long_array() { } // O32-LABEL: define{{.*}} i32* @_Z16alloc_long_arrayv() -// O32: call noalias noundef nonnull i8* @_Znaj(i32 noundef signext 8) +// O32: call noalias nonnull i8* @_Znaj(i32 signext 8) // N32-LABEL: define{{.*}} i32* @_Z16alloc_long_arrayv() -// N32: call noalias noundef nonnull i8* @_Znaj(i32 noundef signext 8) +// N32: call noalias nonnull i8* @_Znaj(i32 signext 8) // N64-LABEL: define{{.*}} i64* @_Z16alloc_long_arrayv() -// N64: call noalias noundef nonnull i8* @_Znam(i64 noundef zeroext 16) +// N64: call noalias nonnull i8* @_Znam(i64 zeroext 16) #include diff --git a/clang/test/CodeGenCXX/ms-inline-asm-fields.cpp b/clang/test/CodeGenCXX/ms-inline-asm-fields.cpp index f57e72221075b8a68477952006f15cc62bce20e8..0817f3e4ecc89bb3a3010e47d36502a1a15bafdf 100644 --- a/clang/test/CodeGenCXX/ms-inline-asm-fields.cpp +++ b/clang/test/CodeGenCXX/ms-inline-asm-fields.cpp @@ -15,7 +15,7 @@ A a_global; } extern "C" int test_param_field(A p) { -// CHECK: define{{.*}} i32 @test_param_field(%struct.A* noundef byval(%struct.A) align 4 %p) +// CHECK: define{{.*}} i32 @test_param_field(%struct.A* byval(%struct.A) align 4 %p) // CHECK: getelementptr inbounds %struct.A, %struct.A* %p, i32 0, i32 0 // CHECK: call i32 asm sideeffect inteldialect "mov eax, $1" // CHECK: ret i32 diff --git a/clang/test/CodeGenCXX/ms-inline-asm-return.cpp b/clang/test/CodeGenCXX/ms-inline-asm-return.cpp index 3c25fdc158a91376af0272225316de50cc0ad2b4..c01358c95b588203228d204763620db539f5a1f4 100644 --- a/clang/test/CodeGenCXX/ms-inline-asm-return.cpp +++ b/clang/test/CodeGenCXX/ms-inline-asm-return.cpp @@ -124,6 +124,6 @@ EightChars f_s8() { int main() { __asm xor eax, eax } -// CHECK-LABEL: define dso_local noundef i32 @main() +// CHECK-LABEL: define dso_local i32 @main() // CHECK: %[[r:[^ ]*]] = call i32 asm sideeffect inteldialect "xor eax, eax", "=&{eax},{{.*}}" // CHECK: ret i32 %[[r]] diff --git a/clang/test/CodeGenCXX/ms-property.cpp b/clang/test/CodeGenCXX/ms-property.cpp index fc4859db0a617d4af82696bd143b652032c7e52d..fb50edace205a740672b045cd4ad62cbb1e5e570 100644 --- a/clang/test/CodeGenCXX/ms-property.cpp +++ b/clang/test/CodeGenCXX/ms-property.cpp @@ -53,61 +53,61 @@ int main(int argc, char **argv) { Test1 t(argc); S *p1 = 0; St *p2 = 0; - // CHECK: call noundef i32 @"?GetX@S@@QEAAHHH@Z"(%class.S* {{[^,]*}} %{{.+}}, i32 noundef 223, i32 noundef 11) + // CHECK: call i32 @"?GetX@S@@QEAAHHH@Z"(%class.S* {{[^,]*}} %{{.+}}, i32 223, i32 11) int j = p1->x[223][11]; // CHECK: [[J:%.+]] = load i32, i32* % - // CHECK-NEXT: call void @"?PutX@S@@QEAAXHHH@Z"(%class.S* {{[^,]*}} %{{.+}}, i32 noundef 23, i32 noundef 1, i32 noundef [[J]]) + // CHECK-NEXT: call void @"?PutX@S@@QEAAXHHH@Z"(%class.S* {{[^,]*}} %{{.+}}, i32 23, i32 1, i32 [[J]]) p1->x[23][1] = j; - // CHECK: call noundef float @"?GetX@?$St@M@@QEAAMMM@Z"(%class.St* {{[^,]*}} %{{.+}}, float noundef 2.230000e+02, float noundef 1.100000e+01) + // CHECK: call float @"?GetX@?$St@M@@QEAAMMM@Z"(%class.St* {{[^,]*}} %{{.+}}, float 2.230000e+02, float 1.100000e+01) float j1 = p2->x[223][11]; // CHECK: [[J1:%.+]] = load float, float* % - // CHECK-NEXT: [[CALL:%.+]] = call noundef float @"?PutX@?$St@M@@QEAAMMMM@Z"(%class.St* {{[^,]*}} %{{.+}}, float noundef 2.300000e+01, float noundef 1.000000e+00, float noundef [[J1]]) + // CHECK-NEXT: [[CALL:%.+]] = call float @"?PutX@?$St@M@@QEAAMMMM@Z"(%class.St* {{[^,]*}} %{{.+}}, float 2.300000e+01, float 1.000000e+00, float [[J1]]) // CHECK-NEXT: [[CONV:%.+]] = fptosi float [[CALL]] to i32 // CHECK-NEXT: store i32 [[CONV]], i32* argc = p2->x[23][1] = j1; - // CHECK: [[IDX:%.+]] = call noundef i32 @"?idx@@YAHXZ"() + // CHECK: [[IDX:%.+]] = call i32 @"?idx@@YAHXZ"() // CHECK-NEXT: [[CONV:%.+]] = sitofp i32 [[IDX]] to float - // CHECK-NEXT: [[GET:%.+]] = call noundef float @"?GetX@?$St@M@@QEAAMMM@Z"(%class.St* {{[^,]*}} %{{.+}}, float noundef [[CONV]], float noundef 1.000000e+00) + // CHECK-NEXT: [[GET:%.+]] = call float @"?GetX@?$St@M@@QEAAMMM@Z"(%class.St* {{[^,]*}} %{{.+}}, float [[CONV]], float 1.000000e+00) // CHECK-NEXT: [[INC:%.+]] = fadd float [[GET]], 1.000000e+00 // CHECK-NEXT: [[CONV:%.+]] = sitofp i32 [[IDX]] to float - // CHECK-NEXT: call noundef float @"?PutX@?$St@M@@QEAAMMMM@Z"(%class.St* {{[^,]*}} %{{.+}}, float noundef [[CONV]], float noundef 1.000000e+00, float noundef [[INC]]) + // CHECK-NEXT: call float @"?PutX@?$St@M@@QEAAMMMM@Z"(%class.St* {{[^,]*}} %{{.+}}, float [[CONV]], float 1.000000e+00, float [[INC]]) ++p2->x[idx()][1]; - // CHECK: call void @"??$foo@H@@YAXHH@Z"(i32 noundef %{{.+}}, i32 noundef %{{.+}}) + // CHECK: call void @"??$foo@H@@YAXHH@Z"(i32 %{{.+}}, i32 %{{.+}}) foo(argc, (int)argv[0][0]); // CHECK: [[P2:%.+]] = load %class.St*, %class.St** % // CHECK: [[P1:%.+]] = load %class.S*, %class.S** % - // CHECK: [[P1_X_22_33:%.+]] = call noundef i32 @"?GetX@S@@QEAAHHH@Z"(%class.S* {{[^,]*}} [[P1]], i32 noundef 22, i32 noundef 33) + // CHECK: [[P1_X_22_33:%.+]] = call i32 @"?GetX@S@@QEAAHHH@Z"(%class.S* {{[^,]*}} [[P1]], i32 22, i32 33) // CHECK: [[CAST:%.+]] = sitofp i32 [[P1_X_22_33]] to double // CHECK: [[ARGC:%.+]] = load i32, i32* % - // CHECK: [[T_X:%.+]] = call noundef i32 @"?get_x@Test1@@QEBAHXZ"(%class.Test1* {{[^,]*}} %{{.+}}) + // CHECK: [[T_X:%.+]] = call i32 @"?get_x@Test1@@QEBAHXZ"(%class.Test1* {{[^,]*}} %{{.+}}) // CHECK: [[CAST2:%.+]] = trunc i32 [[T_X]] to i8 - // CHECK: call void @"?PutY@?$St@M@@QEAAXDHN@Z"(%class.St* {{[^,]*}} [[P2]], i8 noundef [[CAST2]], i32 noundef [[ARGC]], double noundef [[CAST]]) + // CHECK: call void @"?PutY@?$St@M@@QEAAXDHN@Z"(%class.St* {{[^,]*}} [[P2]], i8 [[CAST2]], i32 [[ARGC]], double [[CAST]]) p2->y[t.X][argc] = p1->x[22][33]; // CHECK: [[P2_1:%.+]] = load %class.St*, %class.St** // CHECK: [[P2_2:%.+]] = load %class.St*, %class.St** // CHECK: [[P1:%.+]] = load %class.S*, %class.S** // CHECK: [[ARGC:%.+]] = load i32, i32* % - // CHECK: [[P1_X_ARGC_0:%.+]] = call noundef i32 @"?GetX@S@@QEAAHHH@Z"(%class.S* {{[^,]*}} [[P1]], i32 noundef [[ARGC]], i32 noundef 0) + // CHECK: [[P1_X_ARGC_0:%.+]] = call i32 @"?GetX@S@@QEAAHHH@Z"(%class.S* {{[^,]*}} [[P1]], i32 [[ARGC]], i32 0) // CHECK: [[CAST:%.+]] = trunc i32 [[P1_X_ARGC_0]] to i8 - // CHECK: [[P2_Y_p1_X_ARGC_0_T:%.+]] = call noundef i8 @"?GetY@?$St@M@@QEAADDVTest1@@@Z"(%class.St* {{[^,]*}} [[P2_2]], i8 noundef [[CAST]], %class.Test1* noundef %{{.+}}) + // CHECK: [[P2_Y_p1_X_ARGC_0_T:%.+]] = call i8 @"?GetY@?$St@M@@QEAADDVTest1@@@Z"(%class.St* {{[^,]*}} [[P2_2]], i8 [[CAST]], %class.Test1* %{{.+}}) // CHECK: [[CAST:%.+]] = sitofp i8 [[P2_Y_p1_X_ARGC_0_T]] to float // CHECK: [[J:%.+]] = load i32, i32* % // CHECK: [[CAST1:%.+]] = sitofp i32 [[J]] to float // CHECK: [[J:%.+]] = load i32, i32* % // CHECK: [[CAST2:%.+]] = sitofp i32 [[J]] to float - // CHECK: call noundef float @"?PutX@?$St@M@@QEAAMMMM@Z"(%class.St* {{[^,]*}} [[P2_1]], float noundef [[CAST2]], float noundef [[CAST1]], float noundef [[CAST]]) + // CHECK: call float @"?PutX@?$St@M@@QEAAMMMM@Z"(%class.St* {{[^,]*}} [[P2_1]], float [[CAST2]], float [[CAST1]], float [[CAST]]) p2->x[j][j] = p2->y[p1->x[argc][0]][t]; - // CHECK: [[CALL:%.+]] = call noundef %class.Test1* @"?GetTest1@Test1@@SAPEAV1@XZ"() - // CHECK-NEXT: call noundef i32 @"?get_x@Test1@@QEBAHXZ"(%class.Test1* {{[^,]*}} [[CALL]]) + // CHECK: [[CALL:%.+]] = call %class.Test1* @"?GetTest1@Test1@@SAPEAV1@XZ"() + // CHECK-NEXT: call i32 @"?get_x@Test1@@QEBAHXZ"(%class.Test1* {{[^,]*}} [[CALL]]) return Test1::GetTest1()->X; } -// CHECK: define linkonce_odr dso_local void @"??$foo@H@@YAXHH@Z"(i32 noundef %{{.+}}, i32 noundef %{{.+}}) -// CHECK: call noundef i32 @"?GetX@?$St@H@@QEAAHHH@Z"(%class.St{{.+}}* {{[^,]*}} [[BAR:%.+]], i32 noundef %{{.+}} i32 noundef %{{.+}}) -// CHECK: call noundef i32 @"?PutX@?$St@H@@QEAAHHHH@Z"(%class.St{{.+}}* {{[^,]*}} [[BAR]], i32 noundef %{{.+}}, i32 noundef %{{.+}}, i32 noundef %{{.+}}) -// CHECK: call noundef i32 @"?GetX@?$St@H@@QEAAHHH@Z"(%class.St{{.+}}* {{[^,]*}} [[BAR]], i32 noundef %{{.+}} i32 noundef %{{.+}}) -// CHECK: call void @"?PutY@?$St@H@@QEAAXDHN@Z"(%class.St{{.+}}* {{[^,]*}} [[BAR]], i8 noundef %{{.+}}, i32 noundef %{{.+}}, double noundef %{{.+}} -// CHECK: call noundef i32 @"?GetX@?$St@H@@QEAAHHH@Z"(%class.St{{.+}}* {{[^,]*}} [[BAR]], i32 noundef %{{.+}} i32 noundef %{{.+}}) -// CHECK: call noundef i8 @"?GetY@?$St@H@@QEAADDVTest1@@@Z"(%class.St{{.+}}* {{[^,]*}} [[BAR]], i8 noundef %{{.+}}, %class.Test1* noundef %{{.+}}) -// CHECK: call noundef i32 @"?PutX@?$St@H@@QEAAHHHH@Z"(%class.St{{.+}}* {{[^,]*}} [[BAR]], i32 noundef %{{.+}}, i32 noundef %{{.+}}, i32 noundef %{{.+}}) +// CHECK: define linkonce_odr dso_local void @"??$foo@H@@YAXHH@Z"(i32 %{{.+}}, i32 %{{.+}}) +// CHECK: call i32 @"?GetX@?$St@H@@QEAAHHH@Z"(%class.St{{.+}}* {{[^,]*}} [[BAR:%.+]], i32 %{{.+}} i32 %{{.+}}) +// CHECK: call i32 @"?PutX@?$St@H@@QEAAHHHH@Z"(%class.St{{.+}}* {{[^,]*}} [[BAR]], i32 %{{.+}}, i32 %{{.+}}, i32 %{{.+}}) +// CHECK: call i32 @"?GetX@?$St@H@@QEAAHHH@Z"(%class.St{{.+}}* {{[^,]*}} [[BAR]], i32 %{{.+}} i32 %{{.+}}) +// CHECK: call void @"?PutY@?$St@H@@QEAAXDHN@Z"(%class.St{{.+}}* {{[^,]*}} [[BAR]], i8 %{{.+}}, i32 %{{.+}}, double %{{.+}} +// CHECK: call i32 @"?GetX@?$St@H@@QEAAHHH@Z"(%class.St{{.+}}* {{[^,]*}} [[BAR]], i32 %{{.+}} i32 %{{.+}}) +// CHECK: call i8 @"?GetY@?$St@H@@QEAADDVTest1@@@Z"(%class.St{{.+}}* {{[^,]*}} [[BAR]], i8 %{{.+}}, %class.Test1* %{{.+}}) +// CHECK: call i32 @"?PutX@?$St@H@@QEAAHHHH@Z"(%class.St{{.+}}* {{[^,]*}} [[BAR]], i32 %{{.+}}, i32 %{{.+}}, i32 %{{.+}}) #endif //HEADER diff --git a/clang/test/CodeGenCXX/ms-thunks-ehspec.cpp b/clang/test/CodeGenCXX/ms-thunks-ehspec.cpp index 915433764f9a5c65421984ed1c6a20e67b1940e9..b8ebe2dd9f39996f2f54e4dbe9a94075e456b572 100644 --- a/clang/test/CodeGenCXX/ms-thunks-ehspec.cpp +++ b/clang/test/CodeGenCXX/ms-thunks-ehspec.cpp @@ -20,8 +20,8 @@ class C : A, B { }; C c; -// CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc void @"?f@C@@G3AEXUNonTrivial@@@Z"(%class.C* noundef %this, <{ %struct.NonTrivial }>* inalloca(<{ %struct.NonTrivial }>) %0) +// CHECK-LABEL: define linkonce_odr dso_local x86_thiscallcc void @"?f@C@@G3AEXUNonTrivial@@@Z"(%class.C* %this, <{ %struct.NonTrivial }>* inalloca(<{ %struct.NonTrivial }>) %0) // CHECK-NOT: invoke -// CHECK: musttail call x86_thiscallcc void @"?f@C@@EAEXUNonTrivial@@@Z"(%class.C* noundef %{{.*}}, <{ %struct.NonTrivial }>* inalloca(<{ %struct.NonTrivial }>) %0) +// CHECK: musttail call x86_thiscallcc void @"?f@C@@EAEXUNonTrivial@@@Z"(%class.C* %{{.*}}, <{ %struct.NonTrivial }>* inalloca(<{ %struct.NonTrivial }>) %0) // CHECK-NEXT: ret void diff --git a/clang/test/CodeGenCXX/ms-thunks-unprototyped.cpp b/clang/test/CodeGenCXX/ms-thunks-unprototyped.cpp index d45797bb31909dc58a1a1ee3ab3327f6baaa3db1..0a232b98518e11efcec01d30b8a5aa6b69dfd0f7 100644 --- a/clang/test/CodeGenCXX/ms-thunks-unprototyped.cpp +++ b/clang/test/CodeGenCXX/ms-thunks-unprototyped.cpp @@ -39,35 +39,35 @@ S s; // CHECK-SAME: i32 (i8*, i32)* @"?baz@B@@W7EAAHU?$InstantiateLater@H@@@Z" -// CHECK-LABEL: define linkonce_odr dso_local void @"?f@S@@W7EAA?AU?$DoNotInstantiate@X@@XZ"(%struct.S* noundef %this, ...) +// CHECK-LABEL: define linkonce_odr dso_local void @"?f@S@@W7EAA?AU?$DoNotInstantiate@X@@XZ"(%struct.S* %this, ...) // CHECK: %[[THIS_ADJ_i8:[^ ]*]] = getelementptr i8, i8* {{.*}}, i32 -8 // CHECK: %[[THIS_ADJ:[^ ]*]] = bitcast i8* %[[THIS_ADJ_i8]] to %struct.S* // CHECK: musttail call void (%struct.S*, ...) {{.*}}@"?f@S@@UEAA?AU?$DoNotInstantiate@X@@XZ" -// CHECK-SAME: (%struct.S* noundef %[[THIS_ADJ]], ...) +// CHECK-SAME: (%struct.S* %[[THIS_ADJ]], ...) // CHECK: ret void // The thunks should have a -8 adjustment. -// CHECK-LABEL: define linkonce_odr dso_local void @"?foo@B@@W7EAAXUIncomplete@@@Z"(%struct.B* noundef %this, ...) +// CHECK-LABEL: define linkonce_odr dso_local void @"?foo@B@@W7EAAXUIncomplete@@@Z"(%struct.B* %this, ...) // CHECK: %[[THIS_ADJ_i8:[^ ]*]] = getelementptr i8, i8* {{.*}}, i32 -8 // CHECK: %[[THIS_ADJ:[^ ]*]] = bitcast i8* %[[THIS_ADJ_i8]] to %struct.B* // CHECK: musttail call void (%struct.B*, ...) {{.*}}@"?foo@B@@UEAAXUIncomplete@@@Z" -// CHECK-SAME: (%struct.B* noundef %[[THIS_ADJ]], ...) +// CHECK-SAME: (%struct.B* %[[THIS_ADJ]], ...) // CHECK-NEXT: ret void -// CHECK-LABEL: define linkonce_odr dso_local void @"?bar@B@@W7EAAXU?$DoNotInstantiate@H@@@Z"(%struct.B* noundef %this, ...) +// CHECK-LABEL: define linkonce_odr dso_local void @"?bar@B@@W7EAAXU?$DoNotInstantiate@H@@@Z"(%struct.B* %this, ...) // CHECK: %[[THIS_ADJ_i8:[^ ]*]] = getelementptr i8, i8* {{.*}}, i32 -8 // CHECK: %[[THIS_ADJ:[^ ]*]] = bitcast i8* %[[THIS_ADJ_i8]] to %struct.B* // CHECK: musttail call void (%struct.B*, ...) {{.*}}@"?bar@B@@UEAAXU?$DoNotInstantiate@H@@@Z" -// CHECK-SAME: (%struct.B* noundef %[[THIS_ADJ]], ...) +// CHECK-SAME: (%struct.B* %[[THIS_ADJ]], ...) // CHECK-NEXT: ret void // If we complete the definition later, things work out. template struct InstantiateLater { T x; }; inline int B::baz(InstantiateLater p) { return p.x; } -// CHECK-LABEL: define linkonce_odr dso_local noundef i32 @"?baz@B@@W7EAAHU?$InstantiateLater@H@@@Z"(i8* noundef %this.coerce, i32 %p.coerce) +// CHECK-LABEL: define linkonce_odr dso_local i32 @"?baz@B@@W7EAAHU?$InstantiateLater@H@@@Z"(i8* %this.coerce, i32 %p.coerce) // CHECK: = getelementptr i8, i8* {{.*}}, i32 -8 -// CHECK: tail call noundef i32 @"?baz@B@@UEAAHU?$InstantiateLater@H@@@Z"(i8* {{[^,]*}}, i32 {{.*}}) +// CHECK: tail call i32 @"?baz@B@@UEAAHU?$InstantiateLater@H@@@Z"(i8* {{[^,]*}}, i32 {{.*}}) -// CHECK-LABEL: define linkonce_odr dso_local noundef i32 @"?baz@B@@UEAAHU?$InstantiateLater@H@@@Z"(i8* noundef %this.coerce, i32 %p.coerce) +// CHECK-LABEL: define linkonce_odr dso_local i32 @"?baz@B@@UEAAHU?$InstantiateLater@H@@@Z"(i8* %this.coerce, i32 %p.coerce) diff --git a/clang/test/CodeGenCXX/ms-union-member-ref.cpp b/clang/test/CodeGenCXX/ms-union-member-ref.cpp index 6aeb6fcbdd3a5536a8edebc9d72b1d8c34754d98..59cdda599c2a5a027fca25de51b89c1ae372217e 100644 --- a/clang/test/CodeGenCXX/ms-union-member-ref.cpp +++ b/clang/test/CodeGenCXX/ms-union-member-ref.cpp @@ -8,7 +8,7 @@ union A { int *f1(A *a) { return a->ref; } -// CHECK-LABEL: define {{.*}}i32* @"?f1@@YAPAHPATA@@@Z"(%union.A* noundef %a) +// CHECK-LABEL: define {{.*}}i32* @"?f1@@YAPAHPATA@@@Z"(%union.A* %a) // CHECK: [[REF:%[^[:space:]]+]] = bitcast %union.A* %{{.*}} to i32*** // CHECK: [[IPP:%[^[:space:]]+]] = load i32**, i32*** [[REF]] // CHECK: [[IP:%[^[:space:]]+]] = load i32*, i32** [[IPP]] @@ -17,7 +17,7 @@ int *f1(A *a) { void f2(A *a) { *a->ref = 1; } -// CHECK-LABEL: define {{.*}}void @"?f2@@YAXPATA@@@Z"(%union.A* noundef %a) +// CHECK-LABEL: define {{.*}}void @"?f2@@YAXPATA@@@Z"(%union.A* %a) // CHECK: [[REF:%[^[:space:]]+]] = bitcast %union.A* %{{.*}} to i32*** // CHECK: [[IPP:%[^[:space:]]+]] = load i32**, i32*** [[REF]] // CHECK: [[IP:%[^[:space:]]+]] = load i32*, i32** [[IPP]] @@ -26,7 +26,7 @@ void f2(A *a) { bool f3(A *a, int *b) { return a->ref != b; } -// CHECK-LABEL: define {{.*}}i1 @"?f3@@YA_NPATA@@PAH@Z"(%union.A* noundef %a, i32* noundef %b) +// CHECK-LABEL: define {{.*}}i1 @"?f3@@YA_NPATA@@PAH@Z"(%union.A* %a, i32* %b) // CHECK: [[REF:%[^[:space:]]+]] = bitcast %union.A* %{{.*}} to i32*** // CHECK: [[IPP:%[^[:space:]]+]] = load i32**, i32*** [[REF]] // CHECK: [[IP:%[^[:space:]]+]] = load i32*, i32** [[IPP]] diff --git a/clang/test/CodeGenCXX/msabi-ctor-abstract-vbase.cpp b/clang/test/CodeGenCXX/msabi-ctor-abstract-vbase.cpp index 7b1cc05e937bdd526e81e345d6648baa291e9fd2..7632581db254c6a773c0a327efc13d67dbe67245 100644 --- a/clang/test/CodeGenCXX/msabi-ctor-abstract-vbase.cpp +++ b/clang/test/CodeGenCXX/msabi-ctor-abstract-vbase.cpp @@ -52,7 +52,7 @@ C::C(int n) : B(n) { may_throw(); } // No branches, no constructor calls before may_throw(); // -// CHECK-LABEL: define dso_local noundef %struct.C* @"??0C@@QEAA@H@Z"(%struct.C* {{[^,]*}} returned %this, i32 noundef %n, i32 noundef %is_most_derived) +// CHECK-LABEL: define dso_local %struct.C* @"??0C@@QEAA@H@Z"(%struct.C* {{[^,]*}} returned {{[^,]*}} %this, i32 %n, i32 %is_most_derived) // CHECK-NOT: br i1 // CHECK-NOT: {{call.*@"\?0}} // CHECK: call void @"?may_throw@@YAXXZ"() @@ -63,12 +63,12 @@ D::D(int n) : C(n), B(n) { may_throw(); } // Conditionally construct (and destroy) vbase B, unconditionally C. // -// CHECK-LABEL: define dso_local noundef %struct.D* @"??0D@@QEAA@H@Z"(%struct.D* {{[^,]*}} returned %this, i32 noundef %n, i32 noundef %is_most_derived) +// CHECK-LABEL: define dso_local %struct.D* @"??0D@@QEAA@H@Z"(%struct.D* {{[^,]*}} returned {{[^,]*}} %this, i32 %n, i32 %is_most_derived) // CHECK: icmp ne i32 {{.*}}, 0 // CHECK: br i1 -// CHECK: call noundef %struct.B* @"??0B@@QEAA@H@Z" +// CHECK: call %struct.B* @"??0B@@QEAA@H@Z" // CHECK: br label -// CHECK: invoke noundef %struct.C* @"??0C@@QEAA@H@Z" +// CHECK: invoke %struct.C* @"??0C@@QEAA@H@Z" // CHECK: invoke void @"?may_throw@@YAXXZ"() // CHECK: cleanuppad // CHECK: call void @"??1C@@UEAA@XZ" diff --git a/clang/test/CodeGenCXX/multi-dim-operator-new.cpp b/clang/test/CodeGenCXX/multi-dim-operator-new.cpp index f095e8e1516bb3cd4657f25bd04484a02c6c1721..5cd73833ba12be01b3e80d6ff7604aa0bafdd311 100644 --- a/clang/test/CodeGenCXX/multi-dim-operator-new.cpp +++ b/clang/test/CodeGenCXX/multi-dim-operator-new.cpp @@ -43,6 +43,6 @@ int main() { return 0; } -// CHECK: call noalias noundef nonnull i8* @_Znam -// CHECK: call noalias noundef nonnull i8* @_Znam -// CHECK: call noalias noundef nonnull i8* @_Znam +// CHECK: call noalias nonnull i8* @_Znam +// CHECK: call noalias nonnull i8* @_Znam +// CHECK: call noalias nonnull i8* @_Znam diff --git a/clang/test/CodeGenCXX/new-alias.cpp b/clang/test/CodeGenCXX/new-alias.cpp index 9a4bb590e4c6d31c195cd06fcb7ee216fe6d8893..3644a5d7745d7b055cf42d93fd7a8958c51c2a87 100644 --- a/clang/test/CodeGenCXX/new-alias.cpp +++ b/clang/test/CodeGenCXX/new-alias.cpp @@ -9,5 +9,5 @@ extern "C" char *something(long long x) { void *operator new(size_t) __attribute__((alias("something"))); // PR16715: don't assert here. -// CHECK: call noalias noundef nonnull i8* @_Znwm(i64 noundef 4) #3{{$}} +// CHECK: call noalias nonnull i8* @_Znwm(i64 4) #3{{$}} int *pr16715 = new int; diff --git a/clang/test/CodeGenCXX/new-array-init.cpp b/clang/test/CodeGenCXX/new-array-init.cpp index 274c3d155569879d69e8dd2952e29e6c279fe4fb..661f5fe64a0a3aabd2500b2edbb5c320d1b7aae3 100644 --- a/clang/test/CodeGenCXX/new-array-init.cpp +++ b/clang/test/CodeGenCXX/new-array-init.cpp @@ -34,7 +34,7 @@ void check_array_value_init() { struct S; new (int S::*[3][4][5]) (); - // CHECK: call noalias noundef nonnull i8* @_Zna{{.}}(i{{32 noundef 240|64 noundef 480}}) + // CHECK: call noalias nonnull i8* @_Zna{{.}}(i{{32 240|64 480}}) // CHECK: getelementptr inbounds i{{32|64}}, i{{32|64}}* {{.*}}, i{{32|64}} 60 // CHECK: phi @@ -49,7 +49,7 @@ void string_nonconst(int n) { // CHECK: icmp slt i{{32|64}} %{{[^ ]+}}, 4 // FIXME: Conditionally throw an exception rather than passing -1 to alloc function // CHECK: select - // CHECK: %[[PTR:.*]] = call noalias noundef nonnull i8* @_Zna{{.}}(i{{32|64}} + // CHECK: %[[PTR:.*]] = call noalias nonnull i8* @_Zna{{.}}(i{{32|64}} // CHECK: call void @llvm.memcpy{{.*}}(i8* align {{[0-9]+}} %[[PTR]], i8* align {{[0-9]+}} getelementptr inbounds ([4 x i8], [4 x i8]* @[[ABC4]], i32 0, i32 0), i32 4, // CHECK: %[[REST:.*]] = getelementptr inbounds i8, i8* %[[PTR]], i32 4 // CHECK: %[[RESTSIZE:.*]] = sub {{.*}}, 4 @@ -60,7 +60,7 @@ void string_nonconst(int n) { // CHECK-LABEL: define{{.*}} void @_Z12string_exactv void string_exact() { // CHECK-NOT: icmp - // CHECK: %[[PTR:.*]] = call noalias noundef nonnull i8* @_Zna{{.}}(i{{32|64}} noundef 4) + // CHECK: %[[PTR:.*]] = call noalias nonnull i8* @_Zna{{.}}(i{{32|64}} 4) // CHECK: call void @llvm.memcpy{{.*}}(i8* align {{[0-9]+}} %[[PTR]], i8* align {{[0-9]+}} getelementptr inbounds ([4 x i8], [4 x i8]* @[[ABC4]], i32 0, i32 0), i32 4, // CHECK-NOT: memset new char[4] { "abc" }; @@ -69,7 +69,7 @@ void string_exact() { // CHECK-LABEL: define{{.*}} void @_Z17string_sufficientv void string_sufficient() { // CHECK-NOT: icmp - // CHECK: %[[PTR:.*]] = call noalias noundef nonnull i8* @_Zna{{.}}(i{{32|64}} noundef 15) + // CHECK: %[[PTR:.*]] = call noalias nonnull i8* @_Zna{{.}}(i{{32|64}} 15) // FIXME: For very large arrays, it would be preferable to emit a small copy and a memset. // CHECK: call void @llvm.memcpy{{.*}}(i8* align {{[0-9]+}} %[[PTR]], i8* align {{[0-9]+}} getelementptr inbounds ([15 x i8], [15 x i8]* @[[ABC15]], i32 0, i32 0), i32 15, // CHECK-NOT: memset @@ -79,7 +79,7 @@ void string_sufficient() { // CHECK-LABEL: define{{.*}} void @_Z10aggr_exactv void aggr_exact() { // CHECK-NOT: icmp - // CHECK: %[[MEM:.*]] = call noalias noundef nonnull i8* @_Zna{{.}}(i{{32|64}} noundef 16) + // CHECK: %[[MEM:.*]] = call noalias nonnull i8* @_Zna{{.}}(i{{32|64}} 16) // CHECK: %[[PTR0:.*]] = bitcast i8* %[[MEM]] to %[[AGGR:.*]]* // CHECK: %[[FIELD:.*]] = getelementptr inbounds %[[AGGR]], %[[AGGR]]* %[[PTR0]], i32 0, i32 0{{$}} // CHECK: store i32 1, i32* %[[FIELD]] @@ -99,7 +99,7 @@ void aggr_exact() { // CHECK-LABEL: define{{.*}} void @_Z15aggr_sufficienti void aggr_sufficient(int n) { // CHECK: icmp ult i32 %{{.*}}, 2 - // CHECK: %[[MEM:.*]] = call noalias noundef nonnull i8* @_Zna{{.}}( + // CHECK: %[[MEM:.*]] = call noalias nonnull i8* @_Zna{{.}}( // CHECK: %[[PTR0:.*]] = bitcast i8* %[[MEM]] to %[[AGGR:.*]]* // CHECK: %[[FIELD:.*]] = getelementptr inbounds %[[AGGR]], %[[AGGR]]* %[[PTR0]], i32 0, i32 0{{$}} // CHECK: store i32 1, i32* %[[FIELD]] @@ -120,7 +120,7 @@ void aggr_sufficient(int n) { // SIO-LABEL: define{{.*}} void @_Z14constexpr_testv void constexpr_test() { - // SIO: call noalias noundef nonnull i8* @_Zna{{.}}(i32 noundef 4) + // SIO: call noalias nonnull i8* @_Zna{{.}}(i32 4) new int[0+1]{0}; } @@ -128,7 +128,7 @@ void constexpr_test() { void unknown_bound() { struct Aggr { int x, y, z; }; new Aggr[]{1, 2, 3, 4}; - // CHECK: call {{.*}}_Znaj(i32 noundef 24) + // CHECK: call {{.*}}_Znaj(i32 24) // CHECK: store i32 1 // CHECK: store i32 2 // CHECK: store i32 3 @@ -142,6 +142,6 @@ void unknown_bound() { // CHECK-LABEL: define{{.*}} void @_Z20unknown_bound_stringv void unknown_bound_string() { new char[]{"hello"}; - // CHECK: call {{.*}}_Znaj(i32 noundef 6) + // CHECK: call {{.*}}_Znaj(i32 6) // CHECK: memcpy{{.*}} i32 6, } diff --git a/clang/test/CodeGenCXX/new-infallible.cpp b/clang/test/CodeGenCXX/new-infallible.cpp index c7dc2f3f6cde4ddc0d085495a56c7707b0f39f35..94bcc886d39661d9842fe631da391192e3c16528 100644 --- a/clang/test/CodeGenCXX/new-infallible.cpp +++ b/clang/test/CodeGenCXX/new-infallible.cpp @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -emit-llvm -triple x86_64-linux-gnu -fnew-infallible -o - %s | FileCheck %s -// CHECK: call noalias noundef nonnull i8* @_Znwm(i64 noundef 4) +// CHECK: call noalias nonnull i8* @_Znwm(i64 4) // CHECK: ; Function Attrs: nobuiltin nounwind allocsize(0) -// CHECK-NEXT: declare noundef nonnull i8* @_Znwm(i64 noundef) +// CHECK-NEXT: declare nonnull i8* @_Znwm(i64) int *new_infallible = new int; diff --git a/clang/test/CodeGenCXX/new-overflow.cpp b/clang/test/CodeGenCXX/new-overflow.cpp index 6590ee4121f65e25d4708f3c6998728ed59f3761..7c459cb91c76db141cadcab805225d07161f49b7 100644 --- a/clang/test/CodeGenCXX/new-overflow.cpp +++ b/clang/test/CodeGenCXX/new-overflow.cpp @@ -11,13 +11,13 @@ namespace test0 { typedef A elt; - // CHECK: define{{.*}} [[A:%.*]]* @_ZN5test04testEs(i16 noundef signext + // CHECK: define{{.*}} [[A:%.*]]* @_ZN5test04testEs(i16 signext // CHECK: [[N:%.*]] = sext i16 {{%.*}} to i32 // CHECK-NEXT: [[T0:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[N]], i32 4) // CHECK-NEXT: [[T1:%.*]] = extractvalue { i32, i1 } [[T0]], 1 // CHECK-NEXT: [[T2:%.*]] = extractvalue { i32, i1 } [[T0]], 0 // CHECK-NEXT: [[T3:%.*]] = select i1 [[T1]], i32 -1, i32 [[T2]] - // CHECK-NEXT: call noalias noundef nonnull i8* @_Znaj(i32 noundef [[T3]]) + // CHECK-NEXT: call noalias nonnull i8* @_Znaj(i32 [[T3]]) // CHECK: getelementptr inbounds {{.*}}, i32 [[N]] elt *test(short s) { return new elt[s]; @@ -33,14 +33,14 @@ namespace test1 { typedef A elt[100]; - // CHECK: define{{.*}} [100 x [[A:%.*]]]* @_ZN5test14testEs(i16 noundef signext + // CHECK: define{{.*}} [100 x [[A:%.*]]]* @_ZN5test14testEs(i16 signext // CHECK: [[N:%.*]] = sext i16 {{%.*}} to i32 // CHECK-NEXT: [[T0:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[N]], i32 400) // CHECK-NEXT: [[T1:%.*]] = extractvalue { i32, i1 } [[T0]], 1 // CHECK-NEXT: [[T2:%.*]] = extractvalue { i32, i1 } [[T0]], 0 // CHECK-NEXT: [[T3:%.*]] = mul i32 [[N]], 100 // CHECK-NEXT: [[T4:%.*]] = select i1 [[T1]], i32 -1, i32 [[T2]] - // CHECK-NEXT: call noalias noundef nonnull i8* @_Znaj(i32 noundef [[T4]]) + // CHECK-NEXT: call noalias nonnull i8* @_Znaj(i32 [[T4]]) // CHECK: getelementptr inbounds {{.*}}, i32 [[T3]] elt *test(short s) { return new elt[s]; @@ -57,7 +57,7 @@ namespace test2 { typedef A elt[100]; - // CHECK: define{{.*}} [100 x [[A:%.*]]]* @_ZN5test24testEs(i16 noundef signext + // CHECK: define{{.*}} [100 x [[A:%.*]]]* @_ZN5test24testEs(i16 signext // CHECK: [[N:%.*]] = sext i16 {{%.*}} to i32 // CHECK-NEXT: [[T0:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[N]], i32 400) // CHECK-NEXT: [[T1:%.*]] = extractvalue { i32, i1 } [[T0]], 1 @@ -68,7 +68,7 @@ namespace test2 { // CHECK-NEXT: [[T6:%.*]] = or i1 [[T1]], [[T5]] // CHECK-NEXT: [[T7:%.*]] = extractvalue { i32, i1 } [[T4]], 0 // CHECK-NEXT: [[T8:%.*]] = select i1 [[T6]], i32 -1, i32 [[T7]] - // CHECK-NEXT: call noalias noundef nonnull i8* @_Znaj(i32 noundef [[T8]]) + // CHECK-NEXT: call noalias nonnull i8* @_Znaj(i32 [[T8]]) // CHECK: getelementptr inbounds {{.*}}, i32 [[T3]] elt *test(short s) { return new elt[s]; @@ -83,9 +83,9 @@ namespace test4 { typedef A elt; - // CHECK: define{{.*}} [[A:%.*]]* @_ZN5test44testEs(i16 noundef signext + // CHECK: define{{.*}} [[A:%.*]]* @_ZN5test44testEs(i16 signext // CHECK: [[N:%.*]] = sext i16 {{%.*}} to i32 - // CHECK-NEXT: call noalias noundef nonnull i8* @_Znaj(i32 noundef [[N]]) + // CHECK-NEXT: call noalias nonnull i8* @_Znaj(i32 [[N]]) // CHECK: getelementptr inbounds {{.*}}, i32 [[N]] elt *test(short s) { return new elt[s]; @@ -102,7 +102,7 @@ namespace test5 { // CHECK: define{{.*}} [[A:%.*]]* @_ZN5test54testEi(i32 // CHECK: [[N:%.*]] = load i32, i32* - // CHECK-NEXT: call noalias noundef nonnull i8* @_Znaj(i32 noundef [[N]]) + // CHECK-NEXT: call noalias nonnull i8* @_Znaj(i32 [[N]]) // CHECK: getelementptr inbounds {{.*}}, i32 [[N]] elt *test(int s) { return new elt[s]; @@ -118,13 +118,13 @@ namespace test6 { typedef A elt; - // CHECK: define{{.*}} [[A:%.*]]* @_ZN5test64testEt(i16 noundef zeroext + // CHECK: define{{.*}} [[A:%.*]]* @_ZN5test64testEt(i16 zeroext // CHECK: [[N:%.*]] = zext i16 {{%.*}} to i32 // CHECK-NEXT: [[T0:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[N]], i32 4) // CHECK-NEXT: [[T1:%.*]] = extractvalue { i32, i1 } [[T0]], 1 // CHECK-NEXT: [[T2:%.*]] = extractvalue { i32, i1 } [[T0]], 0 // CHECK-NEXT: [[T3:%.*]] = select i1 [[T1]], i32 -1, i32 [[T2]] - // CHECK-NEXT: call noalias noundef nonnull i8* @_Znaj(i32 noundef [[T3]]) + // CHECK-NEXT: call noalias nonnull i8* @_Znaj(i32 [[T3]]) // CHECK: getelementptr inbounds {{.*}}, i32 [[N]] elt *test(unsigned short s) { return new elt[s]; @@ -140,14 +140,14 @@ namespace test7 { typedef A elt[100]; - // CHECK: define{{.*}} [100 x [[A:%.*]]]* @_ZN5test74testEt(i16 noundef zeroext + // CHECK: define{{.*}} [100 x [[A:%.*]]]* @_ZN5test74testEt(i16 zeroext // CHECK: [[N:%.*]] = zext i16 {{%.*}} to i32 // CHECK-NEXT: [[T0:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[N]], i32 400) // CHECK-NEXT: [[T1:%.*]] = extractvalue { i32, i1 } [[T0]], 1 // CHECK-NEXT: [[T2:%.*]] = extractvalue { i32, i1 } [[T0]], 0 // CHECK-NEXT: [[T3:%.*]] = mul i32 [[N]], 100 // CHECK-NEXT: [[T4:%.*]] = select i1 [[T1]], i32 -1, i32 [[T2]] - // CHECK-NEXT: call noalias noundef nonnull i8* @_Znaj(i32 noundef [[T4]]) + // CHECK-NEXT: call noalias nonnull i8* @_Znaj(i32 [[T4]]) // CHECK: getelementptr inbounds {{.*}}, i32 [[T3]] elt *test(unsigned short s) { return new elt[s]; @@ -170,7 +170,7 @@ namespace test8 { // CHECK-NEXT: [[T3:%.*]] = extractvalue { i32, i1 } [[T2]], 1 // CHECK-NEXT: [[T5:%.*]] = extractvalue { i32, i1 } [[T2]], 0 // CHECK-NEXT: [[T6:%.*]] = select i1 [[T3]], i32 -1, i32 [[T5]] - // CHECK-NEXT: call noalias noundef nonnull i8* @_Znaj(i32 noundef [[T6]]) + // CHECK-NEXT: call noalias nonnull i8* @_Znaj(i32 [[T6]]) // CHECK: getelementptr inbounds {{.*}}, i32 [[T1]] elt *test(long long s) { return new elt[s]; @@ -193,7 +193,7 @@ namespace test9 { // CHECK-NEXT: [[T3:%.*]] = extractvalue { i32, i1 } [[T2]], 1 // CHECK-NEXT: [[T5:%.*]] = extractvalue { i32, i1 } [[T2]], 0 // CHECK-NEXT: [[T6:%.*]] = select i1 [[T3]], i32 -1, i32 [[T5]] - // CHECK-NEXT: call noalias noundef nonnull i8* @_Znaj(i32 noundef [[T6]]) + // CHECK-NEXT: call noalias nonnull i8* @_Znaj(i32 [[T6]]) // CHECK: getelementptr inbounds {{.*}}, i32 [[T1]] elt *test(unsigned long long s) { return new elt[s]; diff --git a/clang/test/CodeGenCXX/new.cpp b/clang/test/CodeGenCXX/new.cpp index ec0147f3f0db775976010177336f4d549edd567f..3142dba4bf683b5cbd93803fd613299f15243080 100644 --- a/clang/test/CodeGenCXX/new.cpp +++ b/clang/test/CodeGenCXX/new.cpp @@ -14,10 +14,10 @@ void t1() { delete [] new int [3]; } -// CHECK: declare noundef nonnull i8* @_Znwm(i64 noundef) [[ATTR_NOBUILTIN:#[^ ]*]] -// CHECK: declare void @_ZdlPv(i8* noundef) [[ATTR_NOBUILTIN_NOUNWIND:#[^ ]*]] -// CHECK: declare noundef nonnull i8* @_Znam(i64 noundef) [[ATTR_NOBUILTIN]] -// CHECK: declare void @_ZdaPv(i8* noundef) [[ATTR_NOBUILTIN_NOUNWIND]] +// CHECK: declare nonnull i8* @_Znwm(i64) [[ATTR_NOBUILTIN:#[^ ]*]] +// CHECK: declare void @_ZdlPv(i8*) [[ATTR_NOBUILTIN_NOUNWIND:#[^ ]*]] +// CHECK: declare nonnull i8* @_Znam(i64) [[ATTR_NOBUILTIN]] +// CHECK: declare void @_ZdaPv(i8*) [[ATTR_NOBUILTIN_NOUNWIND]] namespace std { struct nothrow_t {}; @@ -127,15 +127,15 @@ struct B { int a; }; struct Bmemptr { int Bmemptr::* memptr; int a; }; void t11(int n) { - // CHECK: call noalias noundef nonnull i8* @_Znwm + // CHECK: call noalias nonnull i8* @_Znwm // CHECK: call void @llvm.memset.p0i8.i64( B* b = new B(); - // CHECK: call noalias noundef nonnull i8* @_Znam + // CHECK: call noalias nonnull i8* @_Znam // CHECK: {{call void.*llvm.memset.p0i8.i64.*i8 0, i64 %}} B *b2 = new B[n](); - // CHECK: call noalias noundef nonnull i8* @_Znam + // CHECK: call noalias nonnull i8* @_Znam // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64 // CHECK: br Bmemptr *b_memptr = new Bmemptr[n](); @@ -148,11 +148,11 @@ struct Empty { }; // We don't need to initialize an empty class. // CHECK-LABEL: define{{.*}} void @_Z3t12v void t12() { - // CHECK: call noalias noundef nonnull i8* @_Znam + // CHECK: call noalias nonnull i8* @_Znam // CHECK-NOT: br (void)new Empty[10]; - // CHECK: call noalias noundef nonnull i8* @_Znam + // CHECK: call noalias nonnull i8* @_Znam // CHECK-NOT: br (void)new Empty[10](); @@ -162,11 +162,11 @@ void t12() { // Zero-initialization // CHECK-LABEL: define{{.*}} void @_Z3t13i void t13(int n) { - // CHECK: call noalias noundef nonnull i8* @_Znwm + // CHECK: call noalias nonnull i8* @_Znwm // CHECK: store i32 0, i32* (void)new int(); - // CHECK: call noalias noundef nonnull i8* @_Znam + // CHECK: call noalias nonnull i8* @_Znam // CHECK: {{call void.*llvm.memset.p0i8.i64.*i8 0, i64 %}} (void)new int[n](); @@ -182,16 +182,16 @@ struct Alloc{ }; void f() { - // CHECK: call noundef i8* @_ZN5AllocnaEm(i64 noundef 808) + // CHECK: call i8* @_ZN5AllocnaEm(i64 808) // CHECK: store i64 200 // CHECK: call void @_ZN5AllocD1Ev( // CHECK: call void @_ZN5AllocdaEPv(i8* delete[] new Alloc[10][20]; - // CHECK: [[P:%.*]] = call noundef nonnull i8* @_ZN5AllocnaEmRKSt9nothrow_t(i64 noundef 808, {{.*}}) [[ATTR_NOUNWIND:#[^ ]*]] + // CHECK: [[P:%.*]] = call nonnull i8* @_ZN5AllocnaEmRKSt9nothrow_t(i64 808, {{.*}}) [[ATTR_NOUNWIND:#[^ ]*]] // CHECK-NOT: icmp eq i8* [[P]], null // CHECK: store i64 200 delete[] new (nothrow) Alloc[10][20]; - // CHECK: call noalias noundef nonnull i8* @_Znwm + // CHECK: call noalias nonnull i8* @_Znwm // CHECK: call void @_ZdlPv(i8* delete new bool; // CHECK: ret void @@ -212,7 +212,7 @@ namespace test15 { // CHECK-LABEL: define{{.*}} void @_ZN6test156test0bEPv( // CHECK: [[P0:%.*]] = load i8*, i8** - // CHECK: [[P:%.*]] = call noundef i8* @_ZnwmPvb(i64 noundef 1, i8* noundef [[P0]] + // CHECK: [[P:%.*]] = call i8* @_ZnwmPvb(i64 1, i8* [[P0]] // CHECK-NEXT: icmp eq i8* [[P]], null // CHECK-NEXT: br i1 // CHECK: [[T0:%.*]] = bitcast i8* [[P]] to [[A:%.*]]* @@ -239,7 +239,7 @@ namespace test15 { // CHECK-LABEL: define{{.*}} void @_ZN6test156test1bEPv( // CHECK: [[P0:%.*]] = load i8*, i8** - // CHECK: [[P:%.*]] = call noundef i8* @_ZnamPvb(i64 noundef 13, i8* noundef [[P0]] + // CHECK: [[P:%.*]] = call i8* @_ZnamPvb(i64 13, i8* [[P0]] // CHECK-NEXT: icmp eq i8* [[P]], null // CHECK-NEXT: br i1 // CHECK: [[AFTER_COOKIE:%.*]] = getelementptr inbounds i8, i8* [[P]], i64 8 @@ -277,7 +277,7 @@ namespace PR10197 { // CHECK-LABEL: define weak_odr void @_ZN7PR101971fIiEEvv() template void f() { - // CHECK: [[CALL:%.*]] = call noalias noundef nonnull i8* @_Znwm + // CHECK: [[CALL:%.*]] = call noalias nonnull i8* @_Znwm // CHECK-NEXT: [[CASTED:%.*]] = bitcast i8* [[CALL]] to new T; // CHECK-NEXT: ret void @@ -299,7 +299,7 @@ namespace PR11757 { struct X { X(); X(const X&); }; X* a(X* x) { return new X(X()); } // CHECK: define {{.*}} @_ZN7PR117571aEPNS_1XE - // CHECK: [[CALL:%.*]] = call noalias noundef nonnull i8* @_Znwm + // CHECK: [[CALL:%.*]] = call noalias nonnull i8* @_Znwm // CHECK-NEXT: [[CASTED:%.*]] = bitcast i8* [[CALL]] to // CHECK-NEXT: call void @_ZN7PR117571XC1Ev({{.*}}* {{[^,]*}} [[CASTED]]) // CHECK-NEXT: ret {{.*}} [[CASTED]] @@ -309,7 +309,7 @@ namespace PR13380 { struct A { A() {} }; struct B : public A { int x; }; // CHECK-LABEL: define{{.*}} i8* @_ZN7PR133801fEv - // CHECK: call noalias noundef nonnull i8* @_Znam( + // CHECK: call noalias nonnull i8* @_Znam( // CHECK: call void @llvm.memset.p0i8 // CHECK-NEXT: call void @_ZN7PR133801BC1Ev void* f() { return new B[2](); } @@ -323,40 +323,40 @@ namespace N3664 { // CHECK-LABEL: define{{.*}} void @_ZN5N36641fEv void f() { - // CHECK: call noalias noundef nonnull i8* @_Znwm(i64 noundef 4) [[ATTR_BUILTIN_NEW:#[^ ]*]] + // CHECK: call noalias nonnull i8* @_Znwm(i64 4) [[ATTR_BUILTIN_NEW:#[^ ]*]] int *p = new int; // expected-note {{allocated with 'new' here}} // CHECK: call void @_ZdlPv({{.*}}) [[ATTR_BUILTIN_DELETE:#[^ ]*]] delete p; - // CHECK: call noalias noundef nonnull i8* @_Znam(i64 noundef 12) [[ATTR_BUILTIN_NEW]] + // CHECK: call noalias nonnull i8* @_Znam(i64 12) [[ATTR_BUILTIN_NEW]] int *q = new int[3]; // CHECK: call void @_ZdaPv({{.*}}) [[ATTR_BUILTIN_DELETE]] delete[] p; // expected-warning {{'delete[]' applied to a pointer that was allocated with 'new'; did you mean 'delete'?}} - // CHECK: call noalias noundef i8* @_ZnamRKSt9nothrow_t(i64 noundef 3, {{.*}}) [[ATTR_NOBUILTIN_NOUNWIND_ALLOCSIZE:#[^ ]*]] + // CHECK: call noalias i8* @_ZnamRKSt9nothrow_t(i64 3, {{.*}}) [[ATTR_NOBUILTIN_NOUNWIND_ALLOCSIZE:#[^ ]*]] (void) new (nothrow) S[3]; - // CHECK: call noundef i8* @_Znwm15MyPlacementType(i64 noundef 4){{$}} + // CHECK: call i8* @_Znwm15MyPlacementType(i64 4){{$}} (void) new (mpt) int; } - // CHECK: declare noundef i8* @_ZnamRKSt9nothrow_t(i64 noundef, {{.*}}) [[ATTR_NOBUILTIN_NOUNWIND_ALLOCSIZE:#[^ ]*]] + // CHECK: declare i8* @_ZnamRKSt9nothrow_t(i64, {{.*}}) [[ATTR_NOBUILTIN_NOUNWIND_ALLOCSIZE:#[^ ]*]] // CHECK-LABEL: define{{.*}} void @_ZN5N36641gEv void g() { // It's OK for there to be attributes here, so long as we don't have a // 'builtin' attribute. - // CHECK: call noalias noundef nonnull i8* @_Znwm(i64 noundef 4) {{#[^ ]*}}{{$}} + // CHECK: call noalias nonnull i8* @_Znwm(i64 4) {{#[^ ]*}}{{$}} int *p = (int*)operator new(4); // CHECK: call void @_ZdlPv({{.*}}) [[ATTR_NOUNWIND:#[^ ]*]] operator delete(p); - // CHECK: call noalias noundef nonnull i8* @_Znam(i64 noundef 12) {{#[^ ]*}}{{$}} + // CHECK: call noalias nonnull i8* @_Znam(i64 12) {{#[^ ]*}}{{$}} int *q = (int*)operator new[](12); // CHECK: call void @_ZdaPv({{.*}}) [[ATTR_NOUNWIND]] operator delete [](p); - // CHECK: call noalias noundef i8* @_ZnamRKSt9nothrow_t(i64 noundef 3, {{.*}}) [[ATTR_NOUNWIND_ALLOCSIZE:#[^ ]*]] + // CHECK: call noalias i8* @_ZnamRKSt9nothrow_t(i64 3, {{.*}}) [[ATTR_NOUNWIND_ALLOCSIZE:#[^ ]*]] (void) operator new[](3, nothrow); } } @@ -364,7 +364,7 @@ namespace N3664 { namespace builtins { // CHECK-LABEL: define{{.*}} void @_ZN8builtins1fEv void f() { - // CHECK: call noalias noundef nonnull i8* @_Znwm(i64 noundef 4) [[ATTR_BUILTIN_NEW]] + // CHECK: call noalias nonnull i8* @_Znwm(i64 4) [[ATTR_BUILTIN_NEW]] // CHECK: call void @_ZdlPv({{.*}}) [[ATTR_BUILTIN_DELETE]] __builtin_operator_delete(__builtin_operator_new(4)); } diff --git a/clang/test/CodeGenCXX/noescape.cpp b/clang/test/CodeGenCXX/noescape.cpp index 866218b20175d63f7d83833a2b843ea199fa8192..d1ed879e09801403a0e17d6759c5a7e063857e55 100644 --- a/clang/test/CodeGenCXX/noescape.cpp +++ b/clang/test/CodeGenCXX/noescape.cpp @@ -8,26 +8,26 @@ struct S { virtual void vm1(int *, int * __attribute__((noescape))); }; -// CHECK: define{{.*}} void @_ZN1SC2EPiS0_(%struct.S* {{.*}}, {{.*}}, {{.*}} nocapture noundef {{%.*}}) -// CHECK: define{{.*}} void @_ZN1SC1EPiS0_(%struct.S* {{.*}}, {{.*}}, {{.*}} nocapture noundef {{%.*}}) {{.*}} { +// CHECK: define{{.*}} void @_ZN1SC2EPiS0_(%struct.S* {{.*}}, {{.*}}, {{.*}} nocapture {{%.*}}) +// CHECK: define{{.*}} void @_ZN1SC1EPiS0_(%struct.S* {{.*}}, {{.*}}, {{.*}} nocapture {{%.*}}) {{.*}} { // CHECK: call void @_ZN1SC2EPiS0_(%struct.S* {{.*}}, {{.*}}, {{.*}} nocapture {{.*}}) S::S(int *, int * __attribute__((noescape))) {} -// CHECK: define {{.*}} %struct.S* @_ZN1SaSEPi(%struct.S* {{.*}}, {{.*}} nocapture noundef {{%.*}}) +// CHECK: define {{.*}} %struct.S* @_ZN1SaSEPi(%struct.S* {{.*}}, {{.*}} nocapture {{%.*}}) S &S::operator=(int * __attribute__((noescape))) { return *this; } -// CHECK: define{{.*}} void @_ZN1S2m0EPiS0_(%struct.S* {{.*}}, {{.*}} nocapture noundef {{%.*}}) +// CHECK: define{{.*}} void @_ZN1S2m0EPiS0_(%struct.S* {{.*}}, {{.*}} nocapture {{%.*}}) void S::m0(int *, int * __attribute__((noescape))) {} -// CHECK: define{{.*}} void @_ZN1S3vm1EPiS0_(%struct.S* {{.*}}, {{.*}} nocapture noundef {{%.*}}) +// CHECK: define{{.*}} void @_ZN1S3vm1EPiS0_(%struct.S* {{.*}}, {{.*}} nocapture {{%.*}}) void S::vm1(int *, int * __attribute__((noescape))) {} // CHECK-LABEL: define{{.*}} void @_Z5test0P1SPiS1_( -// CHECK: call void @_ZN1SC1EPiS0_(%struct.S* {{.*}}, {{.*}}, {{.*}} nocapture noundef {{.*}}) -// CHECK: call {{.*}} %struct.S* @_ZN1SaSEPi(%struct.S* {{.*}}, {{.*}} nocapture noundef {{.*}}) -// CHECK: call void @_ZN1S2m0EPiS0_(%struct.S* {{.*}}, {{.*}}, {{.*}} nocapture noundef {{.*}}) -// CHECK: call void {{.*}}(%struct.S* {{.*}}, {{.*}}, {{.*}} nocapture noundef {{.*}}) +// CHECK: call void @_ZN1SC1EPiS0_(%struct.S* {{.*}}, {{.*}}, {{.*}} nocapture {{.*}}) +// CHECK: call {{.*}} %struct.S* @_ZN1SaSEPi(%struct.S* {{.*}}, {{.*}} nocapture {{.*}}) +// CHECK: call void @_ZN1S2m0EPiS0_(%struct.S* {{.*}}, {{.*}}, {{.*}} nocapture {{.*}}) +// CHECK: call void {{.*}}(%struct.S* {{.*}}, {{.*}}, {{.*}} nocapture {{.*}}) void test0(S *s, int *p0, int *p1) { S t(p0, p1); t = p1; @@ -52,14 +52,14 @@ void *test1(void *p0) { // CHECK-LABEL: define{{.*}} void @_Z5test2PiS_( // CHECK: call void @"_ZZ5test2PiS_ENK3$_0clES_S_"({{.*}}, {{.*}}, {{.*}} nocapture {{.*}}) -// CHECK: define internal void @"_ZZ5test2PiS_ENK3$_0clES_S_"({{.*}}, {{.*}}, {{.*}} nocapture noundef {{%.*}}) +// CHECK: define internal void @"_ZZ5test2PiS_ENK3$_0clES_S_"({{.*}}, {{.*}}, {{.*}} nocapture {{%.*}}) void test2(int *p0, int *p1) { auto t = [](int *, int * __attribute__((noescape))){}; t(p0, p1); } // CHECK-LABEL: define{{.*}} void @_Z5test3PFvU8noescapePiES_( -// CHECK: call void {{.*}}(i32* nocapture noundef {{.*}}) +// CHECK: call void {{.*}}(i32* nocapture {{.*}}) typedef void (*NoEscapeFunc)(__attribute__((noescape)) int *); void test3(NoEscapeFunc f, int *p) { diff --git a/clang/test/CodeGenCXX/nonconst-init.cpp b/clang/test/CodeGenCXX/nonconst-init.cpp index 9b103f03711b63f1b437f1179015b3c1d6e48ba9..21129b9b2a63fa1d95c801a16cfac07926e1589a 100644 --- a/clang/test/CodeGenCXX/nonconst-init.cpp +++ b/clang/test/CodeGenCXX/nonconst-init.cpp @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | FileCheck %s int a(); -// CHECK: call noundef i32 @_Z1av() +// CHECK: call i32 @_Z1av() struct x {int x, y : 10;} x = {1, a()}; diff --git a/clang/test/CodeGenCXX/nrvo.cpp b/clang/test/CodeGenCXX/nrvo.cpp index 36c5e5ba992282af1384166a5c41be4cdac8afd8..e01937fccdc1c849920129b64ab95a7b01b7ddf2 100644 --- a/clang/test/CodeGenCXX/nrvo.cpp +++ b/clang/test/CodeGenCXX/nrvo.cpp @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -triple i386-unknown-unknown -emit-llvm -O1 -fno-experimental-new-pass-manager -o - %s | FileCheck %s -// RUN: %clang_cc1 -triple i386-unknown-unknown -emit-llvm -O1 -fno-experimental-new-pass-manager -fcxx-exceptions -fexceptions -std=c++03 -o - %s | FileCheck --check-prefixes=CHECK-EH,CHECK-EH-03 %s -// RUN: %clang_cc1 -triple i386-unknown-unknown -emit-llvm -O1 -fno-experimental-new-pass-manager -fcxx-exceptions -fexceptions -std=c++11 -o - %s | FileCheck --check-prefixes=CHECK-EH,CHECK-EH-11 %s +// RUN: %clang_cc1 -triple i386-unknown-unknown -emit-llvm -O1 -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple i386-unknown-unknown -emit-llvm -O1 -fcxx-exceptions -fexceptions -std=c++03 -o - %s | FileCheck --check-prefixes=CHECK-EH,CHECK-EH-03 %s +// RUN: %clang_cc1 -triple i386-unknown-unknown -emit-llvm -O1 -fcxx-exceptions -fexceptions -std=c++11 -o - %s | FileCheck --check-prefixes=CHECK-EH,CHECK-EH-11 %s // Test code generation for the named return value optimization. class X { @@ -153,7 +153,7 @@ X test4(bool B) { return x; } // CHECK: call {{.*}} @_ZN1XD1Ev - // CHECK: call void @exit(i32 noundef 1) + // CHECK: call void @exit(i32 1) exit(1); } @@ -181,7 +181,7 @@ X test6() { // CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds %class.X, %class.X* [[A]], i32 0, i32 0 // CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull [[PTR]]) // CHECK-NEXT: call {{.*}} @_ZN1XC1Ev([[X]]* {{[^,]*}} [[A]]) - // CHECK-NEXT: call {{.*}} @_ZN1XC1ERKS_([[X]]* {{[^,]*}} {{%.*}}, [[X]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[A]]) + // CHECK-NEXT: call {{.*}} @_ZN1XC1ERKS_([[X]]* {{[^,]*}} {{%.*}}, [[X]]* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[A]]) // CHECK-NEXT: call {{.*}} @_ZN1XD1Ev([[X]]* {{[^,]*}} [[A]]) // CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull [[PTR]]) // CHECK-NEXT: ret void diff --git a/clang/test/CodeGenCXX/observe-noexcept.cpp b/clang/test/CodeGenCXX/observe-noexcept.cpp index 7995b2d57f08989178f66aed787aa35a7633231d..76046a6168a9c2734a3332ad0f01284d6f3a3d38 100644 --- a/clang/test/CodeGenCXX/observe-noexcept.cpp +++ b/clang/test/CodeGenCXX/observe-noexcept.cpp @@ -7,7 +7,7 @@ void ffcomplex (int a) { double _Complex dc = (double)a; - // CHECK: call noundef { double, double } @__muldc3(double noundef %{{.+}}, double noundef %{{.+}}, double noundef %{{.+}}, double noundef %{{.+}}) + // CHECK: call { double, double } @__muldc3(double %{{.+}}, double %{{.+}}, double %{{.+}}, double %{{.+}}) dc *= dc; // CHECK: call {{.+}} @__kmpc_fork_call({{.+}} [[REGNAME1:@.*]] to void (i32*, i32*, ...)*), { double, double }* %{{.+}}) #pragma omp parallel @@ -19,7 +19,7 @@ void ffcomplex (int a) { // CHECK: define internal {{.+}}[[REGNAME1]]( // CHECK-NOT: invoke -// CHECK: call noundef { double, double } @__muldc3(double noundef %{{.+}}, double noundef %{{.+}}, double noundef %{{.+}}, double noundef %{{.+}}) +// CHECK: call { double, double } @__muldc3(double %{{.+}}, double %{{.+}}, double %{{.+}}, double %{{.+}}) // CHECK-NOT: invoke // CHECK: ret void diff --git a/clang/test/CodeGenCXX/operator-new.cpp b/clang/test/CodeGenCXX/operator-new.cpp index 89bd303e479ab2a4426cd0ba8a72bdb56f63b39f..d3679be10a9c66e7a4cf3a31b7d34a18a732bf8f 100644 --- a/clang/test/CodeGenCXX/operator-new.cpp +++ b/clang/test/CodeGenCXX/operator-new.cpp @@ -10,7 +10,7 @@ public: }; void f1() { - // ALL: declare noundef nonnull i8* @_Znwj( + // ALL: declare nonnull i8* @_Znwj( new teste(); } @@ -22,8 +22,8 @@ void *f2(long N) { // ALL-NEXT: [[OVER:%.*]] = extractvalue {{.*}} [[UWO]], 1 // ALL-NEXT: [[SUM:%.*]] = extractvalue {{.*}} [[UWO]], 0 // ALL-NEXT: [[RESULT:%.*]] = select i1 [[OVER]], i32 -1, i32 [[SUM]] - // SANE-NEXT: call noalias noundef nonnull i8* @_Znaj(i32 noundef [[RESULT]]) - // SANENOT-NEXT: call noundef nonnull i8* @_Znaj(i32 noundef [[RESULT]]) + // SANE-NEXT: call noalias nonnull i8* @_Znaj(i32 [[RESULT]]) + // SANENOT-NEXT: call nonnull i8* @_Znaj(i32 [[RESULT]]) } -// ALL: declare noundef nonnull i8* @_Znaj( +// ALL: declare nonnull i8* @_Znaj( diff --git a/clang/test/CodeGenCXX/partial-destruction.cpp b/clang/test/CodeGenCXX/partial-destruction.cpp index 9592b511fd437a4805a3c8eba5afc248279d14ae..46ea251468f0505c411749260a65a6e644dd60e8 100644 --- a/clang/test/CodeGenCXX/partial-destruction.cpp +++ b/clang/test/CodeGenCXX/partial-destruction.cpp @@ -22,10 +22,10 @@ namespace test0 { // Initialize. // CHECK-NEXT: [[E_BEGIN:%.*]] = getelementptr inbounds [10 x [[A]]], [10 x [[A]]]* [[AS]], i64 0, i64 0 // CHECK-NEXT: store [[A]]* [[E_BEGIN]], [[A]]** [[ENDVAR]] - // CHECK-NEXT: invoke void @_ZN5test01AC1Ei([[A]]* {{[^,]*}} [[E_BEGIN]], i32 noundef 5) + // CHECK-NEXT: invoke void @_ZN5test01AC1Ei([[A]]* {{[^,]*}} [[E_BEGIN]], i32 5) // CHECK: [[E1:%.*]] = getelementptr inbounds [[A]], [[A]]* [[E_BEGIN]], i64 1 // CHECK-NEXT: store [[A]]* [[E1]], [[A]]** [[ENDVAR]] - // CHECK-NEXT: invoke void @_ZN5test01AC1Ei([[A]]* {{[^,]*}} [[E1]], i32 noundef 7) + // CHECK-NEXT: invoke void @_ZN5test01AC1Ei([[A]]* {{[^,]*}} [[E1]], i32 7) // CHECK: [[E2:%.*]] = getelementptr inbounds [[A]], [[A]]* [[E1]], i64 1 // CHECK-NEXT: store [[A]]* [[E2]], [[A]]** [[ENDVAR]] // CHECK-NEXT: [[E_END:%.*]] = getelementptr inbounds [[A]], [[A]]* [[E_BEGIN]], i64 10 @@ -109,11 +109,11 @@ namespace test1 { // CHECK-NEXT: alloca i8* // CHECK-NEXT: alloca i32 // CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[B]], [[B]]* [[V]], i32 0, i32 0 - // CHECK-NEXT: call void @_ZN5test11AC1Ei([[A:%.*]]* {{[^,]*}} [[X]], i32 noundef 5) + // CHECK-NEXT: call void @_ZN5test11AC1Ei([[A:%.*]]* {{[^,]*}} [[X]], i32 5) // CHECK-NEXT: [[Y:%.*]] = getelementptr inbounds [[B]], [[B]]* [[V]], i32 0, i32 1 - // CHECK-NEXT: invoke void @_ZN5test11AC1Ei([[A]]* {{[^,]*}} [[Y]], i32 noundef 6) + // CHECK-NEXT: invoke void @_ZN5test11AC1Ei([[A]]* {{[^,]*}} [[Y]], i32 6) // CHECK: [[Z:%.*]] = getelementptr inbounds [[B]], [[B]]* [[V]], i32 0, i32 2 - // CHECK-NEXT: invoke void @_ZN5test11AC1Ei([[A]]* {{[^,]*}} [[Z]], i32 noundef 7) + // CHECK-NEXT: invoke void @_ZN5test11AC1Ei([[A]]* {{[^,]*}} [[Z]], i32 7) // CHECK: [[W:%.*]] = getelementptr inbounds [[B]], [[B]]* [[V]], i32 0, i32 3 // CHECK-NEXT: store i32 8, i32* [[W]], align 4 // CHECK-NEXT: call void @_ZN5test11BD1Ev([[B]]* {{[^,]*}} [[V]]) @@ -193,21 +193,21 @@ namespace test4 { // CHECK-NEXT: store [3 x [[A]]]* [[A0]], // CHECK-NEXT: [[A00:%.*]] = getelementptr inbounds [3 x [[A]]], [3 x [[A]]]* [[A0]], i64 0, i64 0 // CHECK-NEXT: store [[A]]* [[A00]], -// CHECK-NEXT: invoke void @_ZN5test41AC1Ej([[A]]* {{[^,]*}} [[A00]], i32 noundef 0) +// CHECK-NEXT: invoke void @_ZN5test41AC1Ej([[A]]* {{[^,]*}} [[A00]], i32 0) // CHECK: [[A01:%.*]] = getelementptr inbounds [[A]], [[A]]* [[A00]], i64 1 // CHECK-NEXT: store [[A]]* [[A01]], -// CHECK-NEXT: invoke void @_ZN5test41AC1Ej([[A]]* {{[^,]*}} [[A01]], i32 noundef 1) +// CHECK-NEXT: invoke void @_ZN5test41AC1Ej([[A]]* {{[^,]*}} [[A01]], i32 1) // CHECK: [[A02:%.*]] = getelementptr inbounds [[A]], [[A]]* [[A01]], i64 1 // CHECK-NEXT: store [[A]]* [[A02]], -// CHECK-NEXT: invoke void @_ZN5test41AC1Ej([[A]]* {{[^,]*}} [[A02]], i32 noundef 2) +// CHECK-NEXT: invoke void @_ZN5test41AC1Ej([[A]]* {{[^,]*}} [[A02]], i32 2) // CHECK: [[A1:%.*]] = getelementptr inbounds [3 x [[A]]], [3 x [[A]]]* [[A0]], i64 1 // CHECK-NEXT: store [3 x [[A]]]* [[A1]], // CHECK-NEXT: [[A10:%.*]] = getelementptr inbounds [3 x [[A]]], [3 x [[A]]]* [[A1]], i64 0, i64 0 // CHECK-NEXT: store [[A]]* [[A10]], -// CHECK-NEXT: invoke void @_ZN5test41AC1Ej([[A]]* {{[^,]*}} [[A10]], i32 noundef 3) +// CHECK-NEXT: invoke void @_ZN5test41AC1Ej([[A]]* {{[^,]*}} [[A10]], i32 3) // CHECK: [[A11:%.*]] = getelementptr inbounds [[A]], [[A]]* [[A10]], i64 1 // CHECK-NEXT: store [[A]]* [[A11]], -// CHECK-NEXT: invoke void @_ZN5test41AC1Ej([[A]]* {{[^,]*}} [[A11]], i32 noundef 4) +// CHECK-NEXT: invoke void @_ZN5test41AC1Ej([[A]]* {{[^,]*}} [[A11]], i32 4) // CHECK: [[A12:%.*]] = getelementptr inbounds [[A]], [[A]]* [[A11]], i64 1 // CHECK-NEXT: store [[A]]* [[A12]], -// CHECK-NEXT: invoke void @_ZN5test41AC1Ej([[A]]* {{[^,]*}} [[A12]], i32 noundef 5) +// CHECK-NEXT: invoke void @_ZN5test41AC1Ej([[A]]* {{[^,]*}} [[A12]], i32 5) diff --git a/clang/test/CodeGenCXX/pass-by-value-noalias.cpp b/clang/test/CodeGenCXX/pass-by-value-noalias.cpp index 7f9c2e2baa15add83b6db4757ec3e1b8441c1344..eb0e871b5cc32ab36a4baf3e5ec51778c3dbdf16 100644 --- a/clang/test/CodeGenCXX/pass-by-value-noalias.cpp +++ b/clang/test/CodeGenCXX/pass-by-value-noalias.cpp @@ -14,8 +14,8 @@ struct Foo { // Make sure noalias is added to indirect arguments with trivially copyable types // if -fpass-by-value-is-noalias is provided. -// WITH_NOALIAS: define{{.*}} void @_Z4take3Foo(%struct.Foo* noalias noundef %arg) -// NO_NOALIAS: define{{.*}} void @_Z4take3Foo(%struct.Foo* noundef %arg) +// WITH_NOALIAS: define{{.*}} void @_Z4take3Foo(%struct.Foo* noalias %arg) +// NO_NOALIAS: define{{.*}} void @_Z4take3Foo(%struct.Foo* %arg) void take(Foo arg) {} int G; @@ -38,8 +38,8 @@ struct NonTrivial { // Make sure noalias is not added to indirect arguments that are not trivially // copyable even if -fpass-by-value-is-noalias is provided. -// WITH_NOALIAS: define{{.*}} void @_Z4take10NonTrivial(%struct.NonTrivial* noundef %arg) -// NO_NOALIAS: define{{.*}} void @_Z4take10NonTrivial(%struct.NonTrivial* noundef %arg) +// WITH_NOALIAS: define{{.*}} void @_Z4take10NonTrivial(%struct.NonTrivial* %arg) +// NO_NOALIAS: define{{.*}} void @_Z4take10NonTrivial(%struct.NonTrivial* %arg) void take(NonTrivial arg) {} // Escape examples. Pointers to the objects passed to take() may escape, depending on whether a temporary copy is created or not (e.g. due to NRVO). @@ -54,12 +54,12 @@ struct A { }; A *p; -// WITH_NOALIAS: define{{.*}} void @_Z4take1A(%struct.A* noalias noundef %arg) -// NO_NOALIAS: define{{.*}} void @_Z4take1A(%struct.A* noundef %arg) +// WITH_NOALIAS: define{{.*}} void @_Z4take1A(%struct.A* noalias %arg) +// NO_NOALIAS: define{{.*}} void @_Z4take1A(%struct.A* %arg) void take(A arg) {} -// WITH_NOALIAS: define{{.*}} void @_Z7CreateAPP1A(%struct.A* noalias sret(%struct.A) align 1 %agg.result, %struct.A** noundef %where) -// NO_NOALIAS: define{{.*}} void @_Z7CreateAPP1A(%struct.A* noalias sret(%struct.A) align 1 %agg.result, %struct.A** noundef %where) +// WITH_NOALIAS: define{{.*}} void @_Z7CreateAPP1A(%struct.A* noalias sret(%struct.A) align 1 %agg.result, %struct.A** %where) +// NO_NOALIAS: define{{.*}} void @_Z7CreateAPP1A(%struct.A* noalias sret(%struct.A) align 1 %agg.result, %struct.A** %where) A CreateA(A **where) { A justlikethis; *where = &justlikethis; //Escaped pointer 2 (should also be UB, then) diff --git a/clang/test/CodeGenCXX/pass-object-size.cpp b/clang/test/CodeGenCXX/pass-object-size.cpp index a62924792f579d9c3042fa42bd25c7dec8e8e30b..f993c054e2f2e6f2b42bfc9eabbf41c6de09bb76 100644 --- a/clang/test/CodeGenCXX/pass-object-size.cpp +++ b/clang/test/CodeGenCXX/pass-object-size.cpp @@ -20,10 +20,10 @@ void Lambdas(char *ptr) { gi = L2(ptr); } -// CHECK-DAG: define internal noundef i64 @"_ZZN7lambdas7LambdasEPcENK3$_0clEPvU17pass_object_size0" -// CHECK-NOT: call noundef i64 @llvm.objectsize -// CHECK-DAG: define internal noundef i64 @"_ZZN7lambdas7LambdasEPcENK3$_1clEPvU17pass_object_size0" -// CHECK-NOT: call noundef i64 @llvm.objectsize +// CHECK-DAG: define internal i64 @"_ZZN7lambdas7LambdasEPcENK3$_0clEPvU17pass_object_size0" +// CHECK-NOT: call i64 @llvm.objectsize +// CHECK-DAG: define internal i64 @"_ZZN7lambdas7LambdasEPcENK3$_1clEPvU17pass_object_size0" +// CHECK-NOT: call i64 @llvm.objectsize } // This is here instead of in Sema/ because we need to check to make sure the diff --git a/clang/test/CodeGenCXX/pod-member-memcpys.cpp b/clang/test/CodeGenCXX/pod-member-memcpys.cpp index 83a732630b72aa6159391802ff0a61938de55c70..8c66857921db7755d3eb3151bd4542ed93d7e1ea 100644 --- a/clang/test/CodeGenCXX/pod-member-memcpys.cpp +++ b/clang/test/CodeGenCXX/pod-member-memcpys.cpp @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-apple-darwin10 -emit-llvm -std=c++03 -fexceptions -fcxx-exceptions -o - %s | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple i386-apple-darwin10 -emit-llvm -std=c++03 -o - %s | FileCheck --check-prefix=CHECK-2 %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -emit-llvm -std=c++03 -fexceptions -fcxx-exceptions -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple i386-apple-darwin10 -emit-llvm -std=c++03 -o - %s | FileCheck --check-prefix=CHECK-2 %s struct POD { int w, x, y, z; diff --git a/clang/test/CodeGenCXX/powerpc-byval.cpp b/clang/test/CodeGenCXX/powerpc-byval.cpp index d49cbfcb0fbdd4ec449de511037a5d980973b88e..a705bf6f7cabfabf82cb714257a1dd028eeec891 100644 --- a/clang/test/CodeGenCXX/powerpc-byval.cpp +++ b/clang/test/CodeGenCXX/powerpc-byval.cpp @@ -9,4 +9,4 @@ void byval(S one, S two) { one = two; } -// CHECK: define{{.*}} void @_Z5byval1SS_(%struct.S* noundef %one, %struct.S* noundef %two) +// CHECK: define{{.*}} void @_Z5byval1SS_(%struct.S* %one, %struct.S* %two) diff --git a/clang/test/CodeGenCXX/pr13396.cpp b/clang/test/CodeGenCXX/pr13396.cpp index bb149666c48f70c36cc492569d95b3eb1e8ef4b6..2ce5999aa8311b5f3491e320d46e781390878da3 100644 --- a/clang/test/CodeGenCXX/pr13396.cpp +++ b/clang/test/CodeGenCXX/pr13396.cpp @@ -7,13 +7,13 @@ struct foo { }; foo::foo() { - // CHECK-LABEL: define{{.*}} void @_ZN3fooC2Ev(%struct.foo* inreg noundef %this) - // CHECK-LABEL: define{{.*}} void @_ZN3fooC1Ev(%struct.foo* inreg noundef %this) + // CHECK-LABEL: define{{.*}} void @_ZN3fooC2Ev(%struct.foo* inreg %this) + // CHECK-LABEL: define{{.*}} void @_ZN3fooC1Ev(%struct.foo* inreg %this) } foo::~foo() { - // CHECK-LABEL: define{{.*}} void @_ZN3fooD2Ev(%struct.foo* inreg noundef %this) - // CHECK-LABEL: define{{.*}} void @_ZN3fooD1Ev(%struct.foo* inreg noundef %this) + // CHECK-LABEL: define{{.*}} void @_ZN3fooD2Ev(%struct.foo* inreg %this) + // CHECK-LABEL: define{{.*}} void @_ZN3fooD1Ev(%struct.foo* inreg %this) } void dummy() { @@ -21,6 +21,6 @@ void dummy() { // older clangs accept: // template foo::foo(int x); foo x(10); - // CHECK-LABEL: define linkonce_odr void @_ZN3fooC1IiEET_(%struct.foo* inreg noundef %this, i32 inreg noundef %x) - // CHECK-LABEL: define linkonce_odr void @_ZN3fooC2IiEET_(%struct.foo* inreg noundef %this, i32 inreg noundef %x) + // CHECK-LABEL: define linkonce_odr void @_ZN3fooC1IiEET_(%struct.foo* inreg %this, i32 inreg %x) + // CHECK-LABEL: define linkonce_odr void @_ZN3fooC2IiEET_(%struct.foo* inreg %this, i32 inreg %x) } diff --git a/clang/test/CodeGenCXX/pr20897.cpp b/clang/test/CodeGenCXX/pr20897.cpp index 4d23d95671c7c2731d3aa0614993d570ae611f08..73995fc2715573b999b9fa314948347706963c93 100644 --- a/clang/test/CodeGenCXX/pr20897.cpp +++ b/clang/test/CodeGenCXX/pr20897.cpp @@ -3,7 +3,7 @@ struct Base {}; // __declspec(dllexport) causes us to export the implicit constructor. struct __declspec(dllexport) Derived : virtual Base { -// CHECK-LABEL: define weak_odr dso_local dllexport x86_thiscallcc noundef %struct.Derived* @"??0Derived@@QAE@ABU0@@Z" +// CHECK-LABEL: define weak_odr dso_local dllexport x86_thiscallcc %struct.Derived* @"??0Derived@@QAE@ABU0@@Z" // CHECK: %[[this:.*]] = load %struct.Derived*, %struct.Derived** {{.*}} // CHECK-NEXT: store %struct.Derived* %[[this]], %struct.Derived** %[[retval:.*]] // CHECK: %[[dest_a_gep:.*]] = getelementptr inbounds %struct.Derived, %struct.Derived* %[[this]], i32 0, i32 1 @@ -18,7 +18,7 @@ struct __declspec(dllexport) Derived : virtual Base { // __declspec(dllexport) causes us to export the implicit copy constructor. struct __declspec(dllexport) Derived2 : virtual Base { -// CHECK-LABEL: define weak_odr dso_local dllexport x86_thiscallcc noundef %struct.Derived2* @"??0Derived2@@QAE@ABU0@@Z" +// CHECK-LABEL: define weak_odr dso_local dllexport x86_thiscallcc %struct.Derived2* @"??0Derived2@@QAE@ABU0@@Z" // CHECK: %[[this:.*]] = load %struct.Derived2*, %struct.Derived2** {{.*}} // CHECK-NEXT: store %struct.Derived2* %[[this]], %struct.Derived2** %[[retval:.*]] // CHECK: %[[dest_a_gep:.*]] = getelementptr inbounds %struct.Derived2, %struct.Derived2* %[[this]], i32 0, i32 1 diff --git a/clang/test/CodeGenCXX/pr24097.cpp b/clang/test/CodeGenCXX/pr24097.cpp index 4556b760d779b658c5a47a543a9b4e8ece417f34..cdf78d20cbda8057c124884b0d7fb37f4a2bc7cc 100644 --- a/clang/test/CodeGenCXX/pr24097.cpp +++ b/clang/test/CodeGenCXX/pr24097.cpp @@ -17,4 +17,4 @@ void bar() { } // Test that it is not hidden -// CHECK: define available_externally noundef zeroext i1 @_ZThn8_N17SyncMessageFilter4SendEv +// CHECK: define available_externally zeroext i1 @_ZThn8_N17SyncMessageFilter4SendEv diff --git a/clang/test/CodeGenCXX/pr28360.cpp b/clang/test/CodeGenCXX/pr28360.cpp index cabf5a3fd11aec1935bb3b064b24af00be26ce4f..bff7343acd4541273d6a58a2c60c86ca2342dd29 100644 --- a/clang/test/CodeGenCXX/pr28360.cpp +++ b/clang/test/CodeGenCXX/pr28360.cpp @@ -13,4 +13,4 @@ void Baz() { Bar(&A::Foo); } // CHECK-LABEL: define dso_local void @"?Baz@@YAXXZ"( // CHECK: %[[ref_tmp:.*]] = alloca i8*, align 4 // CHECK: store i8* bitcast (void (%struct.A*)* @"?Foo@A@@QAEXXZ" to i8*), i8** %[[ref_tmp]], align 4 -// CHECK: call void @"?Bar@@YAXABQ8A@@AEXXZ@Z"(i8** noundef nonnull align 4 dereferenceable(4) %[[ref_tmp]]) +// CHECK: call void @"?Bar@@YAXABQ8A@@AEXXZ@Z"(i8** nonnull align 4 dereferenceable(4) %[[ref_tmp]]) diff --git a/clang/test/CodeGenCXX/pr9130.cpp b/clang/test/CodeGenCXX/pr9130.cpp index 1a74aa559e875017283037b752f895c4a10fb1ba..e726e5a80b0ab2a48d26258465553d56601981a3 100644 --- a/clang/test/CodeGenCXX/pr9130.cpp +++ b/clang/test/CodeGenCXX/pr9130.cpp @@ -11,4 +11,4 @@ class nsVorbisState : public nsOggCodecState { nsVorbisState::~nsVorbisState() { } -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZN15nsOggCodecState9StartTimeEv +// CHECK-LABEL: define linkonce_odr i32 @_ZN15nsOggCodecState9StartTimeEv diff --git a/clang/test/CodeGenCXX/pragma-visibility.cpp b/clang/test/CodeGenCXX/pragma-visibility.cpp index 2300d0a3c5dae7947953753d746041c2da611687..0e9050588a60e9fc5057ab98d58feefd1253d97a 100644 --- a/clang/test/CodeGenCXX/pragma-visibility.cpp +++ b/clang/test/CodeGenCXX/pragma-visibility.cpp @@ -29,7 +29,7 @@ template int f() { return x; } extern "C" int g() { return f<3>(); } #pragma GCC visibility pop // CHECK-LABEL: define hidden i32 @g() -// CHECK-LABEL: define linkonce_odr hidden noundef i32 @_Z1fILi3EEiv() +// CHECK-LABEL: define linkonce_odr hidden i32 @_Z1fILi3EEiv() #pragma GCC visibility push(hidden) template struct x5 { diff --git a/clang/test/CodeGenCXX/redefine_extname.cpp b/clang/test/CodeGenCXX/redefine_extname.cpp index 079cc5f903126fb0fe35c357d257c20b8d63a680..26cb376350498aff9891780437f4833550a60a7d 100644 --- a/clang/test/CodeGenCXX/redefine_extname.cpp +++ b/clang/test/CodeGenCXX/redefine_extname.cpp @@ -13,7 +13,7 @@ void some_func() { statvfs64(&st); // Check that even if there is a structure with redefined name before the // pragma, subsequent function name redefined properly. PR5172, Comment 11. -// CHECK: call i32 @statvfs(%struct.statvfs64* noundef %st) +// CHECK: call i32 @statvfs(%struct.statvfs64* %st) } // This is a case when redefenition is deferred *and* we have a local of the diff --git a/clang/test/CodeGenCXX/reference-cast.cpp b/clang/test/CodeGenCXX/reference-cast.cpp index 6f0d77f22cd39252207701bd54746afb4cf0df0c..4f27ecd1cb71c6a135ca2cb4186af73b73d21aaf 100644 --- a/clang/test/CodeGenCXX/reference-cast.cpp +++ b/clang/test/CodeGenCXX/reference-cast.cpp @@ -68,14 +68,14 @@ int get_int(); // CHECK-LABEL: define{{.*}} nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i8* @_Z24lvalue_integer_bool_castv() const bool &lvalue_integer_bool_cast() { if (i == 0) - // CHECK: call noundef i32 @_Z7get_intv() + // CHECK: call i32 @_Z7get_intv() // CHECK: store i8 return (const bool&)get_int(); else if (i == 1) - // CHECK: call noundef i32 @_Z7get_intv() + // CHECK: call i32 @_Z7get_intv() // CHECK: store i8 return static_cast(get_int()); - // CHECK: call noundef i32 @_Z7get_intv() + // CHECK: call i32 @_Z7get_intv() // CHECK: store i8 return get_int(); } @@ -85,16 +85,16 @@ float get_float(); // CHECK-LABEL: define{{.*}} nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i8* @_Z25lvalue_floating_bool_castv() const bool &lvalue_floating_bool_cast() { if (i == 0) - // CHECK: call noundef float @_Z9get_floatv() + // CHECK: call float @_Z9get_floatv() // CHECK: fcmp une float // CHECK: store i8 return (const bool&)get_float(); else if (i == 1) - // CHECK: call noundef float @_Z9get_floatv() + // CHECK: call float @_Z9get_floatv() // CHECK: fcmp une float // CHECK: store i8 return static_cast(get_float()); - // CHECK: call noundef float @_Z9get_floatv() + // CHECK: call float @_Z9get_floatv() // CHECK: fcmp une float // CHECK: store i8 return get_float(); diff --git a/clang/test/CodeGenCXX/references.cpp b/clang/test/CodeGenCXX/references.cpp index 552aecea0dd58c67a910f8c68b3aecff59c9eca4..9c560c95fe9a97dacab5db1ccc31ce201aebb821 100644 --- a/clang/test/CodeGenCXX/references.cpp +++ b/clang/test/CodeGenCXX/references.cpp @@ -241,7 +241,7 @@ struct A { }; // CHECK-LABEL: define internal void @__cxx_global_var_init -// CHECK: call void @_ZN2N31AC1Ei(%"struct.N3::A"* {{[^,]*}} @_ZGRN2N35sA123E_, i32 noundef 123) +// CHECK: call void @_ZN2N31AC1Ei(%"struct.N3::A"* {{[^,]*}} @_ZGRN2N35sA123E_, i32 123) // CHECK: call i32 @__cxa_atexit // CHECK: ret void const A &sA123 = A(123); diff --git a/clang/test/CodeGenCXX/regcall.cpp b/clang/test/CodeGenCXX/regcall.cpp index 1ad420a2a7fb934999f4605d7eacda899e8ae4d0..465af3b288d4f4b462ee9ef904d7c9add8a567da 100644 --- a/clang/test/CodeGenCXX/regcall.cpp +++ b/clang/test/CodeGenCXX/regcall.cpp @@ -21,9 +21,9 @@ int main() int __regcall foo (int i){ return i; } -// CHECK-LIN: define{{.*}} x86_regcallcc noundef {{.+}}@_Z15__regcall3__foo -// CHECK-WIN64: define dso_local x86_regcallcc noundef {{.+}}@"?foo@@YwHH@Z" -// CHECK-WIN32: define dso_local x86_regcallcc noundef {{.+}}@"?foo@@YwHH@Z" +// CHECK-LIN: define{{.*}} x86_regcallcc {{.+}}@_Z15__regcall3__foo +// CHECK-WIN64: define dso_local x86_regcallcc {{.+}}@"?foo@@YwHH@Z" +// CHECK-WIN32: define dso_local x86_regcallcc {{.+}}@"?foo@@YwHH@Z" // used to give a body to test_class functions static int x = 0; @@ -37,8 +37,8 @@ public: // CHECK-LIN-DAG: define linkonce_odr x86_regcallcc void @_ZN10test_classC1Ev // CHECK-LIN-DAG: define linkonce_odr x86_regcallcc void @_ZN10test_classC2Ev // Windows ignores calling convention on constructor/destructors. - // CHECK-WIN64-DAG: define linkonce_odr dso_local noundef %class.test_class* @"??0test_class@@QEAA@XZ" - // CHECK-WIN32-DAG: define linkonce_odr dso_local x86_thiscallcc noundef %class.test_class* @"??0test_class@@QAE@XZ" + // CHECK-WIN64-DAG: define linkonce_odr dso_local %class.test_class* @"??0test_class@@QEAA@XZ" + // CHECK-WIN32-DAG: define linkonce_odr dso_local x86_thiscallcc %class.test_class* @"??0test_class@@QAE@XZ" #ifndef WIN_TEST __regcall @@ -53,9 +53,9 @@ public: test_class& __regcall operator+=(const test_class&){ return *this; } - // CHECK-LIN-DAG: define linkonce_odr x86_regcallcc noundef nonnull align 4 dereferenceable(4) %class.test_class* @_ZN10test_classpLERKS_ - // CHECK-WIN64-DAG: define linkonce_odr dso_local x86_regcallcc noundef nonnull align 4 dereferenceable(4) %class.test_class* @"??Ytest_class@@QEAwAEAV0@AEBV0@@Z" - // CHECK-WIN32-DAG: define linkonce_odr dso_local x86_regcallcc noundef nonnull align 4 dereferenceable(4) %class.test_class* @"??Ytest_class@@QAwAAV0@ABV0@@Z" + // CHECK-LIN-DAG: define linkonce_odr x86_regcallcc nonnull align 4 dereferenceable(4) %class.test_class* @_ZN10test_classpLERKS_ + // CHECK-WIN64-DAG: define linkonce_odr dso_local x86_regcallcc nonnull align 4 dereferenceable(4) %class.test_class* @"??Ytest_class@@QEAwAEAV0@AEBV0@@Z" + // CHECK-WIN32-DAG: define linkonce_odr dso_local x86_regcallcc nonnull align 4 dereferenceable(4) %class.test_class* @"??Ytest_class@@QAwAAV0@ABV0@@Z" void __regcall do_thing(){} // CHECK-LIN-DAG: define linkonce_odr x86_regcallcc void @_ZN10test_class20__regcall3__do_thingEv // CHECK-WIN64-DAG: define linkonce_odr dso_local x86_regcallcc void @"?do_thing@test_class@@QEAwXXZ" @@ -69,13 +69,13 @@ public: }; bool __regcall operator ==(const test_class&, const test_class&){ --x; return false;} -// CHECK-LIN-DAG: define{{.*}} x86_regcallcc noundef zeroext i1 @_ZeqRK10test_classS1_ -// CHECK-WIN64-DAG: define dso_local x86_regcallcc noundef zeroext i1 @"??8@Yw_NAEBVtest_class@@0@Z" -// CHECK-WIN32-DAG: define dso_local x86_regcallcc noundef zeroext i1 @"??8@Yw_NABVtest_class@@0@Z" +// CHECK-LIN-DAG: define{{.*}} x86_regcallcc zeroext i1 @_ZeqRK10test_classS1_ +// CHECK-WIN64-DAG: define dso_local x86_regcallcc zeroext i1 @"??8@Yw_NAEBVtest_class@@0@Z" +// CHECK-WIN32-DAG: define dso_local x86_regcallcc zeroext i1 @"??8@Yw_NABVtest_class@@0@Z" test_class __regcall operator""_test_class (unsigned long long) { ++x; return test_class{};} -// CHECK-LIN64-DAG: define{{.*}} x86_regcallcc void @_Zli11_test_classy(%class.test_class* noalias sret(%class.test_class) align 4 %agg.result, i64 noundef %0) -// CHECK-LIN32-DAG: define{{.*}} x86_regcallcc void @_Zli11_test_classy(%class.test_class* inreg noalias sret(%class.test_class) align 4 %agg.result, i64 noundef %0) +// CHECK-LIN64-DAG: define{{.*}} x86_regcallcc void @_Zli11_test_classy(%class.test_class* noalias sret(%class.test_class) align 4 %agg.result, i64 %0) +// CHECK-LIN32-DAG: define{{.*}} x86_regcallcc void @_Zli11_test_classy(%class.test_class* inreg noalias sret(%class.test_class) align 4 %agg.result, i64 %0) // CHECK-WIN64-DAG: ??__K_test_class@@Yw?AVtest_class@@_K@Z" // CHECK-WIN32-DAG: ??__K_test_class@@Yw?AVtest_class@@_K@Z" @@ -99,18 +99,18 @@ void force_gen() { long double _Complex __regcall foo(long double _Complex f) { return f; } -// CHECK-LIN64-DAG: define{{.*}} x86_regcallcc void @_Z15__regcall3__fooCe({ x86_fp80, x86_fp80 }* noalias sret({ x86_fp80, x86_fp80 }) align 16 %agg.result, { x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 16 %f) -// CHECK-LIN32-DAG: define{{.*}} x86_regcallcc void @_Z15__regcall3__fooCe({ x86_fp80, x86_fp80 }* inreg noalias sret({ x86_fp80, x86_fp80 }) align 4 %agg.result, { x86_fp80, x86_fp80 }* noundef byval({ x86_fp80, x86_fp80 }) align 4 %f) -// CHECK-WIN64-DAG: define dso_local x86_regcallcc noundef { double, double } @"?foo@@YwU?$_Complex@O@__clang@@U12@@Z"(double noundef %f.0, double noundef %f.1) -// CHECK-WIN32-DAG: define dso_local x86_regcallcc noundef { double, double } @"?foo@@YwU?$_Complex@O@__clang@@U12@@Z"(double noundef %f.0, double noundef %f.1) +// CHECK-LIN64-DAG: define{{.*}} x86_regcallcc void @_Z15__regcall3__fooCe({ x86_fp80, x86_fp80 }* noalias sret({ x86_fp80, x86_fp80 }) align 16 %agg.result, { x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 16 %f) +// CHECK-LIN32-DAG: define{{.*}} x86_regcallcc void @_Z15__regcall3__fooCe({ x86_fp80, x86_fp80 }* inreg noalias sret({ x86_fp80, x86_fp80 }) align 4 %agg.result, { x86_fp80, x86_fp80 }* byval({ x86_fp80, x86_fp80 }) align 4 %f) +// CHECK-WIN64-DAG: define dso_local x86_regcallcc { double, double } @"?foo@@YwU?$_Complex@O@__clang@@U12@@Z"(double %f.0, double %f.1) +// CHECK-WIN32-DAG: define dso_local x86_regcallcc { double, double } @"?foo@@YwU?$_Complex@O@__clang@@U12@@Z"(double %f.0, double %f.1) // The following caused us to dereference uninitialized memory. The long name // seems necessary, as does the return types. float _Complex __regcall callee(float _Complex f); -// CHECK-LIN64-DAG: declare x86_regcallcc noundef <2 x float> @_Z18__regcall3__calleeCf(<2 x float> noundef) -// CHECK-LIN32-DAG: declare x86_regcallcc noundef { float, float } @_Z18__regcall3__calleeCf(float noundef, float noundef) -// CHECK-WIN64-DAG: declare dso_local x86_regcallcc noundef { float, float } @"?callee@@YwU?$_Complex@M@__clang@@U12@@Z"(float noundef, float noundef) -// CHECK-WIN32-DAG: declare dso_local x86_regcallcc noundef { float, float } @"?callee@@YwU?$_Complex@M@__clang@@U12@@Z"(float noundef, float noundef) +// CHECK-LIN64-DAG: declare x86_regcallcc <2 x float> @_Z18__regcall3__calleeCf(<2 x float>) +// CHECK-LIN32-DAG: declare x86_regcallcc { float, float } @_Z18__regcall3__calleeCf(float, float) +// CHECK-WIN64-DAG: declare dso_local x86_regcallcc { float, float } @"?callee@@YwU?$_Complex@M@__clang@@U12@@Z"(float, float) +// CHECK-WIN32-DAG: declare dso_local x86_regcallcc { float, float } @"?callee@@YwU?$_Complex@M@__clang@@U12@@Z"(float, float) __regcall int some_really_long_name_that_manages_to_hit_the_right_spot_of_mem(int a) { diff --git a/clang/test/CodeGenCXX/regparm.cpp b/clang/test/CodeGenCXX/regparm.cpp index beb9cf82423a01990fdb35e9a2065021be5a4367..eb354465e81005e51be0ba85d9fb03576dd8066c 100644 --- a/clang/test/CodeGenCXX/regparm.cpp +++ b/clang/test/CodeGenCXX/regparm.cpp @@ -11,7 +11,7 @@ struct S1 { }; void __attribute__((regparm(3))) foo2(S1 a, int b); -// CHECK: declare void @_Z4foo22S1i(%struct.S1* inreg noundef, i32 inreg noundef) +// CHECK: declare void @_Z4foo22S1i(%struct.S1* inreg, i32 inreg) void bar2(S1 a, int b) { foo2(a, b); } @@ -21,7 +21,7 @@ struct S2 { }; void __attribute__((regparm(3))) foo3(struct S2 a, int b); -// CHECK: declare void @_Z4foo32S2i(i32 inreg, i32 inreg noundef) +// CHECK: declare void @_Z4foo32S2i(i32 inreg, i32 inreg) void bar3(struct S2 a, int b) { foo3(a, b); } @@ -32,7 +32,7 @@ struct S3 { } a; }; __attribute((regparm(2))) void foo4(S3 a, int b); -// CHECK: declare void @_Z4foo42S3i(%struct.S3* noundef byval(%struct.S3) align 4, i32 inreg noundef) +// CHECK: declare void @_Z4foo42S3i(%struct.S3* byval(%struct.S3) align 4, i32 inreg) void bar3(S3 a, int b) { foo4(a, b); } diff --git a/clang/test/CodeGenCXX/runtime-dllstorage.cpp b/clang/test/CodeGenCXX/runtime-dllstorage.cpp index 7b389c621a49d0357371c7132692fc898a8e608c..f972b54e42409afb32668b4a1fd8beb81113c854 100644 --- a/clang/test/CodeGenCXX/runtime-dllstorage.cpp +++ b/clang/test/CodeGenCXX/runtime-dllstorage.cpp @@ -110,7 +110,7 @@ void l() { // CHECK-MS-DAG: declare dso_local i32 @atexit(void ()*) // CHECK-MS-DYNAMIC-DAG: declare {{.*}} void @_CxxThrowException // CHECK-MS-STATIC-DAG: declare {{.*}} void @_CxxThrowException -// CHECK-MS-DAG: declare dso_local noundef nonnull i8* @"??2@YAPAXI@Z" +// CHECK-MS-DAG: declare dso_local nonnull i8* @"??2@YAPAXI@Z" // CHECK-MS-DAG: declare dso_local void @_Init_thread_header(i32*) // CHECK-MS-DAG: declare dso_local void @_Init_thread_footer(i32*) @@ -120,16 +120,16 @@ void l() { // CHECK-DYNAMIC-IA-DAG: declare dllimport i32 @__cxa_thread_atexit(void (i8*)*, i8*, i8*) // CHECK-DYNAMIC-IA-DAG: declare dllimport i32 @__cxa_atexit(void (i8*)*, i8*, i8*) -// CHECK-DYNAMIC-IA-DECL-DAG: declare i8* @__cxa_allocate_exception(i32 noundef) -// CHECK-DYNAMIC-IA-NODECL-DAG: declare dllimport i8* @__cxa_allocate_exception(i32 noundef) -// CHECK-DYNAMIC-IA-IMPORT-DAG: declare dllimport i8* @__cxa_allocate_exception(i32 noundef) -// CHECK-DYNAMIC-IA-EXPORT-DAG: declare dllimport i8* @__cxa_allocate_exception(i32 noundef) +// CHECK-DYNAMIC-IA-DECL-DAG: declare i8* @__cxa_allocate_exception(i32) +// CHECK-DYNAMIC-IA-NODECL-DAG: declare dllimport i8* @__cxa_allocate_exception(i32) +// CHECK-DYNAMIC-IA-IMPORT-DAG: declare dllimport i8* @__cxa_allocate_exception(i32) +// CHECK-DYNAMIC-IA-EXPORT-DAG: declare dllimport i8* @__cxa_allocate_exception(i32) // CHECK-DYNAMIC-IA-DAG: declare dllimport void @__cxa_throw(i8*, i8*, i8*) // CHECK-DYNAMIC-DECL-IA-DAG: declare dllimport i32 @__cxa_guard_acquire(i64*) // CHECK-DYNAMIC-NODECL-IA-DAG: declare dllimport i32 @__cxa_guard_acquire(i64*) // CHECK-DYNAMIC-IMPORT-IA-DAG: declare dllimport i32 @__cxa_guard_acquire(i64*) // CHECK-DYNAMIC-EXPORT-IA-DAG: declare dllexport i32 @__cxa_guard_acquire(i64*) -// CHECK-IA-DAG: declare dso_local noundef nonnull i8* @_Znwj(i32 noundef) +// CHECK-IA-DAG: declare dso_local nonnull i8* @_Znwj(i32) // CHECK-DYNAMIC-DECL-IA-DAG: declare dllimport void @__cxa_guard_release(i64*) // CHECK-DYNAMIC-NODECL-IA-DAG: declare dllimport void @__cxa_guard_release(i64*) // CHECK-DYNAMIC-IMPORT-IA-DAG: declare dllimport void @__cxa_guard_release(i64*) @@ -147,7 +147,7 @@ void l() { // CHECK-STATIC-NODECL-IA-DAG: declare dso_local i32 @__cxa_guard_acquire(i64*) // CHECK-STATIC-IMPORT-IA-DAG: declare dso_local i32 @__cxa_guard_acquire(i64*) // CHECK-STATIC-EXPORT-IA-DAG: declare dso_local i32 @__cxa_guard_acquire(i64*) -// CHECK-IA-DAG: declare dso_local noundef nonnull i8* @_Znwj(i32 noundef) +// CHECK-IA-DAG: declare dso_local nonnull i8* @_Znwj(i32) // CHECK-STATIC-DECL-IA-DAG: declare dso_local void @__cxa_guard_release(i64*) // CHECK-STATIC-NODECL-IA-DAG: declare dso_local void @__cxa_guard_release(i64*) // CHECK-STATIC-IMPORT-IA-DAG: declare dso_local void @__cxa_guard_release(i64*) diff --git a/clang/test/CodeGenCXX/runtimecc.cpp b/clang/test/CodeGenCXX/runtimecc.cpp index 28b2752b94966fb9102e724ea01ae5d9b1b9b549..8f43e168d2011a4f5e87e203906fa27aa6150086 100644 --- a/clang/test/CodeGenCXX/runtimecc.cpp +++ b/clang/test/CodeGenCXX/runtimecc.cpp @@ -21,7 +21,7 @@ namespace test0 { A global; // CHECK-LABEL: define internal void @__cxx_global_var_init() -// CHECK: call noundef [[A]]* @_ZN5test01AC1Ev([[A]]* {{[^,]*}} @_ZN5test06globalE) +// CHECK: call [[A]]* @_ZN5test01AC1Ev([[A]]* {{[^,]*}} @_ZN5test06globalE) // CHECK-NEXT: call i32 @__cxa_atexit(void (i8*)* bitcast ([[A]]* ([[A]]*)* @_ZN5test01AD1Ev to void (i8*)*), i8* bitcast ([[A]]* @_ZN5test06globalE to i8*), i8* @__dso_handle) [[NOUNWIND:#[0-9]+]] // CHECK-NEXT: ret void } diff --git a/clang/test/CodeGenCXX/rvalue-references.cpp b/clang/test/CodeGenCXX/rvalue-references.cpp index 0ffad8671f769efbf4c54725dce39fcb6cc2cdd0..5b7981a13332a3bd0ccec5487cf3aaf397e78042 100644 --- a/clang/test/CodeGenCXX/rvalue-references.cpp +++ b/clang/test/CodeGenCXX/rvalue-references.cpp @@ -8,7 +8,7 @@ struct B : Spacer, A { }; B &getB(); // CHECK-LABEL: define{{.*}} nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.A* @_Z4getAv() -// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.B* @_Z4getBv() +// CHECK: call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.B* @_Z4getBv() // CHECK-NEXT: bitcast %struct.B* // CHECK-NEXT: getelementptr inbounds i8, i8* // CHECK-NEXT: bitcast i8* {{.*}} to %struct.A* @@ -20,17 +20,17 @@ int &&getIntXValue(); int getIntPRValue(); // CHECK-LABEL: define{{.*}} nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_Z2f0v() -// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_Z12getIntLValuev() +// CHECK: call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_Z12getIntLValuev() // CHECK-NEXT: ret i32* int &&f0() { return static_cast(getIntLValue()); } // CHECK-LABEL: define{{.*}} nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_Z2f1v() -// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_Z12getIntXValuev() +// CHECK: call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_Z12getIntXValuev() // CHECK-NEXT: ret i32* int &&f1() { return static_cast(getIntXValue()); } // CHECK-LABEL: define{{.*}} nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_Z2f2v -// CHECK: call noundef i32 @_Z13getIntPRValuev() +// CHECK: call i32 @_Z13getIntPRValuev() // CHECK-NEXT: store i32 {{.*}}, i32* // CHECK-NEXT: ret i32* int &&f2() { return static_cast(getIntPRValue()); } @@ -95,9 +95,9 @@ namespace test1 { }; // CHECK-LABEL: define{{.*}} void @_ZN5test11BC2Ei( - // CHECK: [[T0:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_ZN5test14moveERi( + // CHECK: [[T0:%.*]] = call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_ZN5test14moveERi( // CHECK-NEXT: [[T1:%.*]] = load i32, i32* [[T0]] - // CHECK-NEXT: call void @_ZN5test11AC1Ei({{.*}}, i32 noundef [[T1]]) + // CHECK-NEXT: call void @_ZN5test11AC1Ei({{.*}}, i32 [[T1]]) // CHECK-NEXT: ret void B::B(int i) : a(move(i)) {} } diff --git a/clang/test/CodeGenCXX/split-stacks.cpp b/clang/test/CodeGenCXX/split-stacks.cpp index 57e23dcf979949e63e077a7451b46956eb747ac9..5f6a65557f4d79ef5a403c22a13ffc61babd89de 100644 --- a/clang/test/CodeGenCXX/split-stacks.cpp +++ b/clang/test/CodeGenCXX/split-stacks.cpp @@ -16,17 +16,17 @@ int nosplit() { return tnosplit(); } -// CHECK-SEGSTK: define dso_local noundef i32 @_Z3foov() [[SS:#[0-9]+]] { -// CHECK-SEGSTK: define dso_local noundef i32 @_Z7nosplitv() [[NSS1:#[0-9]+]] { -// CHECK-SEGSTK: define linkonce_odr dso_local noundef i32 @_Z8tnosplitIiEiv() [[NSS2:#[0-9]+]] comdat { +// CHECK-SEGSTK: define dso_local i32 @_Z3foov() [[SS:#[0-9]+]] { +// CHECK-SEGSTK: define dso_local i32 @_Z7nosplitv() [[NSS1:#[0-9]+]] { +// CHECK-SEGSTK: define linkonce_odr dso_local i32 @_Z8tnosplitIiEiv() [[NSS2:#[0-9]+]] comdat { // CHECK-SEGSTK-NOT: [[NSS1]] = { {{.*}} "split-stack" {{.*}} } // CHECK-SEGSTK-NOT: [[NSS2]] = { {{.*}} "split-stack" {{.*}} } // CHECK-SEGSTK: [[SS]] = { {{.*}} "split-stack" {{.*}} } // CHECK-SEGSTK-NOT: [[NSS1]] = { {{.*}} "split-stack" {{.*}} } // CHECK-SEGSTK-NOT: [[NSS2]] = { {{.*}} "split-stack" {{.*}} } -// CHECK-NOSEGSTK: define dso_local noundef i32 @_Z3foov() [[NSS0:#[0-9]+]] { -// CHECK-NOSEGSTK: define dso_local noundef i32 @_Z7nosplitv() [[NSS1:#[0-9]+]] { -// CHECK-NOSEGSTK: define linkonce_odr dso_local noundef i32 @_Z8tnosplitIiEiv() [[NSS0]] comdat { +// CHECK-NOSEGSTK: define dso_local i32 @_Z3foov() [[NSS0:#[0-9]+]] { +// CHECK-NOSEGSTK: define dso_local i32 @_Z7nosplitv() [[NSS1:#[0-9]+]] { +// CHECK-NOSEGSTK: define linkonce_odr dso_local i32 @_Z8tnosplitIiEiv() [[NSS0]] comdat { // CHECK-NOSEGSTK-NOT: [[NSS0]] = { {{.*}} "split-stack" {{.*}} } // CHECK-NOSEGSTK-NOT: [[NSS1]] = { {{.*}} "split-stack" {{.*}} } diff --git a/clang/test/CodeGenCXX/stack-reuse-miscompile.cpp b/clang/test/CodeGenCXX/stack-reuse-miscompile.cpp index 819863d4285a1e10d2dac782b6c69d143e12d118..516dde9334f5d8d494c91b7a3d9be3823c7db503 100644 --- a/clang/test/CodeGenCXX/stack-reuse-miscompile.cpp +++ b/clang/test/CodeGenCXX/stack-reuse-miscompile.cpp @@ -33,14 +33,14 @@ const char * f(S s) // // CHECK: [[T2i8:%.*]] = bitcast %class.T* [[T2]] to i8* // CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[T2i8]]) -// CHECK: [[T4:%.*]] = call noundef %class.T* @_ZN1TC1EPKc(%class.T* {{[^,]*}} [[T2]], i8* noundef getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i32 0, i32 0)) +// CHECK: [[T4:%.*]] = call %class.T* @_ZN1TC1EPKc(%class.T* {{[^,]*}} [[T2]], i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i32 0, i32 0)) // // CHECK: [[T3i8:%.*]] = bitcast %class.T* [[T3]] to i8* // CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[T3i8]]) -// CHECK: [[T5:%.*]] = call noundef %class.T* @_ZN1TC1E1S(%class.T* {{[^,]*}} [[T3]], [2 x i32] %{{.*}}) +// CHECK: [[T5:%.*]] = call %class.T* @_ZN1TC1E1S(%class.T* {{[^,]*}} [[T3]], [2 x i32] %{{.*}}) // -// CHECK: call void @_ZNK1T6concatERKS_(%class.T* sret(%class.T) align 4 [[T1]], %class.T* {{[^,]*}} [[T2]], %class.T* noundef nonnull align 4 dereferenceable(16) [[T3]]) -// CHECK: [[T6:%.*]] = call noundef i8* @_ZNK1T3strEv(%class.T* {{[^,]*}} [[T1]]) +// CHECK: call void @_ZNK1T6concatERKS_(%class.T* sret(%class.T) align 4 [[T1]], %class.T* {{[^,]*}} [[T2]], %class.T* nonnull align 4 dereferenceable(16) [[T3]]) +// CHECK: [[T6:%.*]] = call i8* @_ZNK1T3strEv(%class.T* {{[^,]*}} [[T1]]) // // CHECK: call void @llvm.lifetime.end.p0i8( // CHECK: call void @llvm.lifetime.end.p0i8( diff --git a/clang/test/CodeGenCXX/stack-reuse.cpp b/clang/test/CodeGenCXX/stack-reuse.cpp index bd8576c6ff42a51443598a639baddedd981ac2d5..9a67a36374f90fab0e91531e54d9e7e063a7a5d2 100644 --- a/clang/test/CodeGenCXX/stack-reuse.cpp +++ b/clang/test/CodeGenCXX/stack-reuse.cpp @@ -134,7 +134,7 @@ int large_combiner_test(S_large s) { // CHECK-LABEL: define{{.*}} i32 @large_combiner_test // CHECK: [[T2:%.*]] = alloca %struct.Combiner // CHECK: [[T1:%.*]] = alloca %struct.Combiner -// CHECK: [[T3:%.*]] = call noundef %struct.Combiner* @_ZN8CombinerC1E7S_large(%struct.Combiner* {{[^,]*}} [[T1]], [9 x i32] %s.coerce) +// CHECK: [[T3:%.*]] = call %struct.Combiner* @_ZN8CombinerC1E7S_large(%struct.Combiner* {{[^,]*}} [[T1]], [9 x i32] %s.coerce) // CHECK: call void @_ZN8Combiner1fEv(%struct.Combiner* nonnull sret(%struct.Combiner) align 4 [[T2]], %struct.Combiner* {{[^,]*}} [[T1]]) // CHECK: [[T4:%.*]] = getelementptr inbounds %struct.Combiner, %struct.Combiner* [[T2]], i32 0, i32 0, i32 0, i32 0 // CHECK: [[T5:%.*]] = load i32, i32* [[T4]] diff --git a/clang/test/CodeGenCXX/static-data-member.cpp b/clang/test/CodeGenCXX/static-data-member.cpp index 444307e9fc780c846b5543629eca5f1cc6cfeecf..898fa21270c070faae68debddfa656218d96368a 100644 --- a/clang/test/CodeGenCXX/static-data-member.cpp +++ b/clang/test/CodeGenCXX/static-data-member.cpp @@ -47,7 +47,7 @@ namespace test2 { } // CHECK-LABEL: define internal void @__cxx_global_var_init() - // CHECK: [[TMP:%.*]] = call noundef i32 @_ZN5test23fooEv() + // CHECK: [[TMP:%.*]] = call i32 @_ZN5test23fooEv() // CHECK-NEXT: store i32 [[TMP]], i32* @_ZN5test212_GLOBAL__N_11AIiE1xE, align 4 // CHECK-NEXT: ret void } @@ -70,7 +70,7 @@ namespace test3 { // CHECK: [[GUARDBYTE:%.*]] = load i8, i8* bitcast (i64* @_ZGVN5test31AIiE1xE to i8*) // CHECK-NEXT: [[UNINITIALIZED:%.*]] = icmp eq i8 [[GUARDBYTE]], 0 // CHECK-NEXT: br i1 [[UNINITIALIZED]] - // CHECK: [[TMP:%.*]] = call noundef i32 @_ZN5test33fooEv() + // CHECK: [[TMP:%.*]] = call i32 @_ZN5test33fooEv() // CHECK-NEXT: store i32 [[TMP]], i32* @_ZN5test31AIiE1xE, align 4 // CHECK-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN5test31AIiE1xE to i8*) // CHECK-NEXT: br label diff --git a/clang/test/CodeGenCXX/static-destructor.cpp b/clang/test/CodeGenCXX/static-destructor.cpp index 2e74099aec30ccc679989ceb57b0ff45bfd9caff..fd15895159296082d493456e815cf18959f5e61e 100644 --- a/clang/test/CodeGenCXX/static-destructor.cpp +++ b/clang/test/CodeGenCXX/static-destructor.cpp @@ -29,5 +29,5 @@ Foo global; // WASM: define internal void @__cxx_global_var_init() // WASM: call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) -// WASM: define internal void @__cxx_global_array_dtor(i8* noundef %0) -// WASM: %call = call noundef %class.Foo* @_ZN3FooD1Ev(%class.Foo* {{[^,]*}} @global) +// WASM: define internal void @__cxx_global_array_dtor(i8* %0) +// WASM: %call = call %class.Foo* @_ZN3FooD1Ev(%class.Foo* {{[^,]*}} @global) diff --git a/clang/test/CodeGenCXX/static-init-1.cpp b/clang/test/CodeGenCXX/static-init-1.cpp index 811ea01072556c8c6a3b867bcf76f33c141ba91a..09bf7bfd5ca6c64ca6a7c20ac1f4a657ca595777 100644 --- a/clang/test/CodeGenCXX/static-init-1.cpp +++ b/clang/test/CodeGenCXX/static-init-1.cpp @@ -8,18 +8,18 @@ int func2(int c) { return printf("loading the func2(%d)\n", c); }; int func1(int c) { return printf("loading the func1(%d)\n", c); } static int loader_1 = func1(++count); -// CHECK: call noundef i32 @_Z5func1i +// CHECK: call i32 @_Z5func1i int loader_2 = func2(++count); static int loader_3 = func1(++count); -// CHECK: call noundef i32 @_Z5func1i +// CHECK: call i32 @_Z5func1i int main() {} int loader_4 = func2(++count); static int loader_5 = func1(++count); int loader_6 = func2(++count); -// CHECK: call noundef i32 @_Z5func1i +// CHECK: call i32 @_Z5func1i -// CHECK-NOT: call noundef i32 @_Z5func1i +// CHECK-NOT: call i32 @_Z5func1i diff --git a/clang/test/CodeGenCXX/static-init-wasm.cpp b/clang/test/CodeGenCXX/static-init-wasm.cpp index 647a61b84721eb5e41c3f6455ed147a631a7661e..c9cdff757fb0bce3b519a069984ca2ef6efe5d86 100644 --- a/clang/test/CodeGenCXX/static-init-wasm.cpp +++ b/clang/test/CodeGenCXX/static-init-wasm.cpp @@ -44,11 +44,11 @@ struct A { A theA; // WEBASSEMBLY32: define internal void @__cxx_global_var_init() #3 { -// WEBASSEMBLY32: call noundef %struct.A* @_ZN1AC1Ev(%struct.A* {{[^,]*}} @theA) +// WEBASSEMBLY32: call %struct.A* @_ZN1AC1Ev(%struct.A* {{[^,]*}} @theA) // WEBASSEMBLY32: define internal void @_GLOBAL__sub_I_static_init_wasm.cpp() #3 { // WEBASSEMBLY32: call void @__cxx_global_var_init() // // WEBASSEMBLY64: define internal void @__cxx_global_var_init() #3 { -// WEBASSEMBLY64: call noundef %struct.A* @_ZN1AC1Ev(%struct.A* {{[^,]*}} @theA) +// WEBASSEMBLY64: call %struct.A* @_ZN1AC1Ev(%struct.A* {{[^,]*}} @theA) // WEBASSEMBLY64: define internal void @_GLOBAL__sub_I_static_init_wasm.cpp() #3 { // WEBASSEMBLY64: call void @__cxx_global_var_init() diff --git a/clang/test/CodeGenCXX/static-init.cpp b/clang/test/CodeGenCXX/static-init.cpp index cf7ec8fab1d76069652a83b196c3b75f2099ff36..0711539cde2ae5241cec4d9fd197f5961da3d3f3 100644 --- a/clang/test/CodeGenCXX/static-init.cpp +++ b/clang/test/CodeGenCXX/static-init.cpp @@ -28,7 +28,7 @@ void f() { } void g() { - // CHECK: call noalias noundef nonnull i8* @_Znwm(i64 noundef 1) + // CHECK: call noalias nonnull i8* @_Znwm(i64 1) // CHECK: call void @_ZN1AC1Ev( static A& a = *new A; } @@ -59,7 +59,7 @@ namespace test0 { } namespace test1 { - // CHECK-LABEL: define internal noundef i32 @_ZN5test1L6getvarEi( + // CHECK-LABEL: define internal i32 @_ZN5test1L6getvarEi( static inline int getvar(int index) { static const int var[] = { 1, 0, 2, 4 }; return var[index]; @@ -74,7 +74,7 @@ unsigned char base_req_uchar[] = { "bar" }; namespace union_static_local { // CHECK-LABEL: define internal void @_ZZN18union_static_local4testEvEN1c4mainEv - // CHECK: call void @_ZN18union_static_local1fEPNS_1xE(%"union.union_static_local::x"* noundef bitcast ({ [2 x i8*] }* @_ZZN18union_static_local4testEvE3foo to %"union.union_static_local::x"*)) + // CHECK: call void @_ZN18union_static_local1fEPNS_1xE(%"union.union_static_local::x"* bitcast ({ [2 x i8*] }* @_ZZN18union_static_local4testEvE3foo to %"union.union_static_local::x"*)) union x { long double y; const char *x[2]; }; void f(union x*); void test() { @@ -111,14 +111,14 @@ namespace test2 { // CHECK-LABEL: define{{.*}} void @_ZN5test21BC2Ev // CHECK: load atomic i8, i8* bitcast (i64* @_ZGVZN5test21BC1EvE1x to i8*) acquire, align 8 // CHECK: call i32 @__cxa_guard_acquire(i64* @_ZGVZN5test21BC1EvE1x) - // CHECK: [[T0:%.*]] = call noundef i32 @_ZN5test23fooEv() + // CHECK: [[T0:%.*]] = call i32 @_ZN5test23fooEv() // CHECK: store i32 [[T0]], i32* @_ZZN5test21BC1EvE1x, // CHECK: call void @__cxa_guard_release(i64* @_ZGVZN5test21BC1EvE1x) // CHECK-LABEL: define{{.*}} void @_ZN5test21BC1Ev // CHECK: load atomic i8, i8* bitcast (i64* @_ZGVZN5test21BC1EvE1x to i8*) acquire, align 8 // CHECK: call i32 @__cxa_guard_acquire(i64* @_ZGVZN5test21BC1EvE1x) - // CHECK: [[T0:%.*]] = call noundef i32 @_ZN5test23fooEv() + // CHECK: [[T0:%.*]] = call i32 @_ZN5test23fooEv() // CHECK: store i32 [[T0]], i32* @_ZZN5test21BC1EvE1x, // CHECK: call void @__cxa_guard_release(i64* @_ZGVZN5test21BC1EvE1x) @@ -130,7 +130,7 @@ namespace test2 { // CHECK-LABEL: define{{.*}} void @_ZN5test21BD2Ev( // CHECK: load atomic i8, i8* bitcast (i64* @_ZGVZN5test21BD1EvE1y to i8*) acquire, align 8 // CHECK: call i32 @__cxa_guard_acquire(i64* @_ZGVZN5test21BD1EvE1y) - // CHECK: [[T0:%.*]] = call noundef i32 @_ZN5test23fooEv() + // CHECK: [[T0:%.*]] = call i32 @_ZN5test23fooEv() // CHECK: store i32 [[T0]], i32* @_ZZN5test21BD1EvE1y, // CHECK: call void @__cxa_guard_release(i64* @_ZGVZN5test21BD1EvE1y) @@ -170,6 +170,6 @@ inline HasVTable &useStaticLocal() { void useit() { useStaticLocal(); } -// CHECK: define linkonce_odr noundef nonnull align 8 dereferenceable(8) %"struct.test4::HasVTable"* @_ZN5test414useStaticLocalEv() +// CHECK: define linkonce_odr nonnull align 8 dereferenceable(8) %"struct.test4::HasVTable"* @_ZN5test414useStaticLocalEv() // CHECK: ret %"struct.test4::HasVTable"*{{.*}} @_ZZN5test414useStaticLocalEvE3obj } diff --git a/clang/test/CodeGenCXX/static-local-in-local-class.cpp b/clang/test/CodeGenCXX/static-local-in-local-class.cpp index d793daedbb3009e0e23d789c2ba3ce0e1552aac8..ff8981299db15d73f404a7d188a3ca8d79ba8ad8 100644 --- a/clang/test/CodeGenCXX/static-local-in-local-class.cpp +++ b/clang/test/CodeGenCXX/static-local-in-local-class.cpp @@ -55,7 +55,7 @@ auto x = []() { int f() { return x()(); } } -// CHECK-LABEL: define internal noundef i32 @"_ZZNK14pr18020_lambda3$_0clEvENKUlvE_clEv" +// CHECK-LABEL: define internal i32 @"_ZZNK14pr18020_lambda3$_0clEvENKUlvE_clEv" // CHECK: load i32, i32* @"_ZZNK14pr18020_lambda3$_0clEvE2l1" namespace pr18020_constexpr { @@ -70,7 +70,7 @@ auto x = []() { int f() { return x()(); } } -// CHECK-LABEL: define internal noundef i32 @"_ZZNK17pr18020_constexpr3$_1clEvENKUlvE_clEv" +// CHECK-LABEL: define internal i32 @"_ZZNK17pr18020_constexpr3$_1clEvENKUlvE_clEv" // CHECK: load i32*, i32** @"_ZZZNK17pr18020_constexpr3$_1clEvENKUlvE_clEvE2l2" // Lambda-less reduction that references l1 before emitting it. This didn't @@ -87,7 +87,7 @@ struct pr18020_class { static pr18020_class x; int pr18020_f() { return x()(); } -// CHECK-LABEL: define linkonce_odr noundef i32 @_ZZN13pr18020_classclEvEN1UclEv +// CHECK-LABEL: define linkonce_odr i32 @_ZZN13pr18020_classclEvEN1UclEv // CHECK: load i32, i32* @_ZZN13pr18020_classclEvE2l1 // In this test case, the function containing the static local will not be @@ -103,11 +103,11 @@ extern "C" int call_deduced_return_operator() { } // CHECK-LABEL: define{{.*}} i32 @call_deduced_return_operator() -// CHECK: call noundef i32* @_ZZL14deduced_returnvEN1SclEv( +// CHECK: call i32* @_ZZL14deduced_returnvEN1SclEv( // CHECK: load i32, i32* % // CHECK: ret i32 % -// CHECK-LABEL: define internal noundef i32* @_ZZL14deduced_returnvEN1SclEv(%struct.S* {{[^,]*}} %this) +// CHECK-LABEL: define internal i32* @_ZZL14deduced_returnvEN1SclEv(%struct.S* {{[^,]*}} %this) // CHECK: ret i32* @_ZZL14deduced_returnvE1n static auto block_deduced_return() { @@ -123,11 +123,11 @@ extern "C" int call_block_deduced_return() { } // CHECK-LABEL: define{{.*}} i32 @call_block_deduced_return() -// CHECK: call noundef i32* @_ZZZL20block_deduced_returnvEUb_EN1SclEv( +// CHECK: call i32* @_ZZZL20block_deduced_returnvEUb_EN1SclEv( // CHECK: load i32, i32* % // CHECK: ret i32 % -// CHECK-LABEL: define internal noundef i32* @_ZZZL20block_deduced_returnvEUb_EN1SclEv(%struct.S.6* {{[^,]*}} %this) #1 align 2 { +// CHECK-LABEL: define internal i32* @_ZZZL20block_deduced_returnvEUb_EN1SclEv(%struct.S.6* {{[^,]*}} %this) #1 align 2 { // CHECK: ret i32* @_ZZZL20block_deduced_returnvEUb_E1n inline auto static_local_label(void *p) { @@ -141,7 +141,7 @@ label: } void *global_label = decltype(static_local_label(0))::get(); -// CHECK-LABEL: define linkonce_odr noundef i8* @_ZZ18static_local_labelPvEN1S3getEv() +// CHECK-LABEL: define linkonce_odr i8* @_ZZ18static_local_labelPvEN1S3getEv() // CHECK: %[[lbl:[^ ]*]] = load i8*, i8** @_ZZ18static_local_labelPvE1q // CHECK: ret i8* %[[lbl]] @@ -154,7 +154,7 @@ extern "C" int use_global_lambda() { return *decltype(global_lambda())::get(); } // CHECK-LABEL: define{{.*}} i32 @use_global_lambda() -// CHECK: call noundef i32* @"_ZZNK3$_2clEvEN1S3getEv"() +// CHECK: call i32* @"_ZZNK3$_2clEvEN1S3getEv"() -// CHECK-LABEL: define internal noundef i32* @"_ZZNK3$_2clEvEN1S3getEv"() +// CHECK-LABEL: define internal i32* @"_ZZNK3$_2clEvEN1S3getEv"() // CHECK: ret i32* @"_ZZNK3$_2clEvE1x" diff --git a/clang/test/CodeGenCXX/stmtexpr.cpp b/clang/test/CodeGenCXX/stmtexpr.cpp index 23f101c64348c43f0e2402a9b513dea5dddf847e..c63c14310f79c9ec916b2e2c2fdf738aa1ceb0a8 100644 --- a/clang/test/CodeGenCXX/stmtexpr.cpp +++ b/clang/test/CodeGenCXX/stmtexpr.cpp @@ -130,7 +130,7 @@ extern "C" int cleanup_exit_lvalue(bool cond) { // CHECK-LABEL: define{{.*}} i32 @cleanup_exit_lvalue({{.*}}) // CHECK: call {{.*}} @_ZN1AC1Ei // Spill after bar. -// CHECK: %[[v:[^ ]*]] = call noundef nonnull align 4 dereferenceable(4) i32* @_Z6getrefv({{.*}}) +// CHECK: %[[v:[^ ]*]] = call nonnull align 4 dereferenceable(4) i32* @_Z6getrefv({{.*}}) // CHECK-NEXT: store i32* %[[v]], i32** %[[tmp:[^, ]*]] // Do cleanup. // CHECK: call {{.*}} @_ZN1AD1Ev @@ -146,7 +146,7 @@ extern "C" int cleanup_exit_lvalue_byval(bool cond, ByVal arg) { ByVal &r = (A(1), ({ if (cond) return 0; (void)ByVal(); }), arg); return r.x[0]; } -// CHECK-LABEL: define{{.*}} i32 @cleanup_exit_lvalue_byval({{.*}}, %struct.ByVal* noundef byval(%struct.ByVal) align 4 %arg) +// CHECK-LABEL: define{{.*}} i32 @cleanup_exit_lvalue_byval({{.*}}, %struct.ByVal* byval(%struct.ByVal) align 4 %arg) // CHECK: call {{.*}} @_ZN1AC1Ei // CHECK: call {{.*}} @_ZN1AD1Ev // CHECK: switch @@ -202,7 +202,7 @@ void volatile_load() { // CHECK-NOT: load volatile ({n;}); - // CHECK-LABEL: @then(i32 noundef 1) + // CHECK-LABEL: @then(i32 1) then(1); // CHECK-NOT: load volatile @@ -210,7 +210,7 @@ void volatile_load() { // CHECK-NOT: load volatile ({goto lab; lab: n;}); - // CHECK-LABEL: @then(i32 noundef 2) + // CHECK-LABEL: @then(i32 2) then(2); // CHECK-NOT: load volatile @@ -218,7 +218,7 @@ void volatile_load() { // CHECK-NOT: load volatile ({[[gsl::suppress("foo")]] n;}); - // CHECK-LABEL: @then(i32 noundef 3) + // CHECK-LABEL: @then(i32 3) then(3); // CHECK-NOT: load volatile @@ -239,7 +239,7 @@ void volatile_load_template() { // CHECK-NOT: load volatile ({n;}); - // CHECK-LABEL: @then(i32 noundef 1) + // CHECK-LABEL: @then(i32 1) then(1); // CHECK-NOT: load volatile @@ -247,7 +247,7 @@ void volatile_load_template() { // CHECK-NOT: load volatile ({goto lab; lab: n;}); - // CHECK-LABEL: @then(i32 noundef 2) + // CHECK-LABEL: @then(i32 2) then(2); // CHECK-NOT: load volatile @@ -255,7 +255,7 @@ void volatile_load_template() { // CHECK-NOT: load volatile ({[[gsl::suppress("foo")]] n;}); - // CHECK-LABEL: @then(i32 noundef 3) + // CHECK-LABEL: @then(i32 3) then(3); // CHECK-NOT: load volatile diff --git a/clang/test/CodeGenCXX/switch-case-folding-2.cpp b/clang/test/CodeGenCXX/switch-case-folding-2.cpp index db506ae890ce537849a491c4bbc30b1c41acd40b..cfb8447ee32666c25a7e5bf4b985f486ccd90893 100644 --- a/clang/test/CodeGenCXX/switch-case-folding-2.cpp +++ b/clang/test/CodeGenCXX/switch-case-folding-2.cpp @@ -8,7 +8,7 @@ int test(int val){ case 4: do { switch (6) { - // CHECK: call noundef i32 (i8*, ...) @_Z6printfPKcz + // CHECK: call i32 (i8*, ...) @_Z6printfPKcz case 6: do { case 5: printf("bad\n"); } while (0); }; } while (0); diff --git a/clang/test/CodeGenCXX/temp-order.cpp b/clang/test/CodeGenCXX/temp-order.cpp index 9c61298e451308f031be93ca04bebcef5015976c..67cd4b7c3a69923186b2e6c7e07afd9a578a7a0d 100644 --- a/clang/test/CodeGenCXX/temp-order.cpp +++ b/clang/test/CodeGenCXX/temp-order.cpp @@ -157,47 +157,47 @@ extern "C" void print(const char *Name, unsigned N); #define ORDER5(a, b, c, d, e) (ORDER4(a, b, c, d) * pow(e, 5)) #define ORDER6(a, b, c, d, e, f) (ORDER5(a, b, c, d, e) * pow(f, 6)) void test() { -// CHECK: call void @print(i8* noundef {{.*}}, i32 noundef 1176) +// CHECK: call void @print(i8* {{.*}}, i32 1176) print("f0", f0()); if (f0() != ORDER3(3, 7, 2)) error(); -// CHECK: call void @print(i8* noundef {{.*}}, i32 noundef 411600) +// CHECK: call void @print(i8* {{.*}}, i32 411600) print("f1", f1()); if (f1() != ORDER4(3, 5, 7, 2)) error(); -// CHECK: call void @print(i8* noundef {{.*}}, i32 noundef 246960) +// CHECK: call void @print(i8* {{.*}}, i32 246960) print("f2", f2()); if (f2() != ORDER4(5, 3, 7, 2)) error(); -// CHECK: call void @print(i8* noundef {{.*}}, i32 noundef 1341648) +// CHECK: call void @print(i8* {{.*}}, i32 1341648) print("f3", f3()); if (f3() != ORDER4(7, 3, 11, 2)) error(); -// CHECK: call void @print(i8* noundef {{.*}}, i32 noundef 1176) +// CHECK: call void @print(i8* {{.*}}, i32 1176) print("f4", f4()); if (f4() != ORDER3(3, 7, 2)) error(); -// CHECK: call void @print(i8* noundef {{.*}}, i32 noundef 246960) +// CHECK: call void @print(i8* {{.*}}, i32 246960) print("f5", f5()); if (f5() != ORDER4(5, 3, 7, 2)) error(); -// CHECK: call void @print(i8* noundef {{.*}}, i32 noundef 1251552576) +// CHECK: call void @print(i8* {{.*}}, i32 1251552576) print("f6", f6()); if (f6() != ORDER6(3, 7, 11, 5, 13, 2)) error(); -// CHECK: call void @print(i8* noundef {{.*}}, i32 noundef 20) +// CHECK: call void @print(i8* {{.*}}, i32 20) print("f7", f7()); if (f7() != ORDER2(5, 2)) error(); -// CHECK: call void @print(i8* noundef {{.*}}, i32 noundef 20) +// CHECK: call void @print(i8* {{.*}}, i32 20) print("f8", f8()); if (f8() != ORDER2(5, 2)) error(); diff --git a/clang/test/CodeGenCXX/template-anonymous-types.cpp b/clang/test/CodeGenCXX/template-anonymous-types.cpp index ecdb76fd2aea0e02556dc1eab1c45eddf4700bee..ac8a2422e0919c60151676fe2f2de1005895a3d2 100644 --- a/clang/test/CodeGenCXX/template-anonymous-types.cpp +++ b/clang/test/CodeGenCXX/template-anonymous-types.cpp @@ -19,18 +19,18 @@ template int f(T t) { void test() { // Look for two instantiations, one for FOO's // type and one for BAR's. - // CHECK-LABEL: define linkonce_odr noundef i32 @_Z1fIN1SUt_EEiT_(i32 noundef %t) + // CHECK-LABEL: define linkonce_odr i32 @_Z1fIN1SUt_EEiT_(i32 %t) (void)f(S::FOO); - // CHECK-LABEL: define linkonce_odr noundef i32 @_Z1fIN1SUt0_EEiT_(i32 noundef %t) + // CHECK-LABEL: define linkonce_odr i32 @_Z1fIN1SUt0_EEiT_(i32 %t) (void)f(S::BAR); // Now check for the class template instantiations. // // BAR's instantiation of X: - // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN1XIN1SUt_EE1fEv(%struct.X* {{[^,]*}} %this) - // CHECK-LABEL: define linkonce_odr void @_ZN1XIN1SUt_EEC2ES1_(%struct.X* {{[^,]*}} %this, i32 noundef %t) unnamed_addr + // CHECK-LABEL: define linkonce_odr i32 @_ZN1XIN1SUt_EE1fEv(%struct.X* {{[^,]*}} %this) + // CHECK-LABEL: define linkonce_odr void @_ZN1XIN1SUt_EEC2ES1_(%struct.X* {{[^,]*}} %this, i32 %t) unnamed_addr // // FOO's instantiation of X: - // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN1XIN1SUt0_EE1fEv(%struct.X.0* {{[^,]*}} %this) - // CHECK-LABEL: define linkonce_odr void @_ZN1XIN1SUt0_EEC2ES1_(%struct.X.0* {{[^,]*}} %this, i32 noundef %t) unnamed_addr + // CHECK-LABEL: define linkonce_odr i32 @_ZN1XIN1SUt0_EE1fEv(%struct.X.0* {{[^,]*}} %this) + // CHECK-LABEL: define linkonce_odr void @_ZN1XIN1SUt0_EEC2ES1_(%struct.X.0* {{[^,]*}} %this, i32 %t) unnamed_addr } diff --git a/clang/test/CodeGenCXX/temporaries.cpp b/clang/test/CodeGenCXX/temporaries.cpp index 8a71ad68f7975aeaab71ad6e6137f3cb33b1e6d2..b769411c9518748e626cf09dbbc13f76c45acb6f 100644 --- a/clang/test/CodeGenCXX/temporaries.cpp +++ b/clang/test/CodeGenCXX/temporaries.cpp @@ -201,11 +201,11 @@ struct B { B::B() // CHECK: call void @_ZN6PR50771AC1Ev - // CHECK: call noundef i32 @_ZN6PR50771A1fEv + // CHECK: call i32 @_ZN6PR50771A1fEv // CHECK: call void @_ZN6PR50771AD1Ev : a1(A().f()) // CHECK: call void @_ZN6PR50771AC1Ev - // CHECK: call noundef i32 @_ZN6PR50771gERKNS_1AE + // CHECK: call i32 @_ZN6PR50771gERKNS_1AE // CHECK: call void @_ZN6PR50771AD1Ev , a2(g(A())) { @@ -332,8 +332,8 @@ int& f(int); // CHECK-LABEL: define{{.*}} void @_ZN3T121gEv void g() { // CHECK: call void @_ZN3T121AC1Ev - // CHECK-NEXT: call noundef i32 @_ZN3T121A1fEv( - // CHECK-NEXT: call noundef {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_ZN3T121fEi( + // CHECK-NEXT: call i32 @_ZN3T121A1fEv( + // CHECK-NEXT: call {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_ZN3T121fEi( // CHECK-NEXT: call void @_ZN3T121AD1Ev( int& i = f(A().f()); } @@ -348,8 +348,8 @@ namespace PR6648 { struct D; D& zed(B); void foobar() { - // NULL-INVALID: call noundef nonnull align 1 %"struct.PR6648::D"* @_ZN6PR66483zedENS_1BE - // NULL-VALID: call noundef align 1 %"struct.PR6648::D"* @_ZN6PR66483zedENS_1BE + // NULL-INVALID: call nonnull align 1 %"struct.PR6648::D"* @_ZN6PR66483zedENS_1BE + // NULL-VALID: call align 1 %"struct.PR6648::D"* @_ZN6PR66483zedENS_1BE zed(foo); } } @@ -436,10 +436,10 @@ namespace Elision { // CHECK-NEXT: [[J:%.*]] = alloca [[A]], align 8 // CHECK: call void @_ZN7Elision1AC1Ev([[A]]* {{[^,]*}} [[I]]) - // CHECK: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[I]], [[A]]* noundef {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[X:%.*]]) + // CHECK: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[I]], [[A]]* {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[X:%.*]]) A i = (c ? A() : x); - // CHECK: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[J]], [[A]]* noundef {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[X]]) + // CHECK: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[J]], [[A]]* {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[X]]) // CHECK: call void @_ZN7Elision1AC1Ev([[A]]* {{[^,]*}} [[J]]) A j = (c ? x : A()); @@ -459,10 +459,10 @@ namespace Elision { A test3(int v, A x) { if (v < 5) // CHECK: call void @_ZN7Elision1AC1Ev([[A]]* {{[^,]*}} [[RET:%.*]]) - // CHECK: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[RET]], [[A]]* noundef {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[X:%.*]]) + // CHECK: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[RET]], [[A]]* {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[X:%.*]]) return (v < 0 ? A() : x); else - // CHECK: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[RET]], [[A]]* noundef {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[X]]) + // CHECK: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[RET]], [[A]]* {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[X]]) // CHECK: call void @_ZN7Elision1AC1Ev([[A]]* {{[^,]*}} [[RET]]) return (v > 10 ? x : A()); @@ -480,7 +480,7 @@ namespace Elision { // CHECK-NEXT: [[XS0:%.*]] = getelementptr inbounds [2 x [[A]]], [2 x [[A]]]* [[XS]], i64 0, i64 0 // CHECK-NEXT: call void @_ZN7Elision1AC1Ev([[A]]* {{[^,]*}} [[XS0]]) // CHECK-NEXT: [[XS1:%.*]] = getelementptr inbounds [[A]], [[A]]* [[XS0]], i64 1 - // CHECK-NEXT: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[XS1]], [[A]]* noundef {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[X]]) + // CHECK-NEXT: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[XS1]], [[A]]* {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[X]]) A xs[] = { A(), x }; // CHECK-NEXT: [[BEGIN:%.*]] = getelementptr inbounds [2 x [[A]]], [2 x [[A]]]* [[XS]], i32 0, i32 0 @@ -507,21 +507,21 @@ namespace Elision { // CHECK: call void @_ZN7Elision1BC1Ev([[B]]* {{[^,]*}} [[BT0]]) // CHECK-NEXT: [[AM:%.*]] = getelementptr inbounds [[B]], [[B]]* [[BT0]], i32 0, i32 0 - // CHECK-NEXT: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[AT0]], [[A]]* noundef {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[AM]]) - // CHECK-NEXT: call void @_ZN7Elision5takeAENS_1AE([[A]]* noundef [[AT0]]) + // CHECK-NEXT: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[AT0]], [[A]]* {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[AM]]) + // CHECK-NEXT: call void @_ZN7Elision5takeAENS_1AE([[A]]* [[AT0]]) // CHECK-NEXT: call void @_ZN7Elision1AD1Ev([[A]]* {{[^,]*}} [[AT0]]) // CHECK-NEXT: call void @_ZN7Elision1BD1Ev([[B]]* {{[^,]*}} [[BT0]]) takeA(B().a); // CHECK-NEXT: call void @_ZN7Elision1BC1Ev([[B]]* {{[^,]*}} [[BT1]]) // CHECK-NEXT: [[AM:%.*]] = getelementptr inbounds [[B]], [[B]]* [[BT1]], i32 0, i32 0 - // CHECK-NEXT: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[X]], [[A]]* noundef {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[AM]]) + // CHECK-NEXT: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[X]], [[A]]* {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[AM]]) // CHECK-NEXT: call void @_ZN7Elision1BD1Ev([[B]]* {{[^,]*}} [[BT1]]) A x = B().a; // CHECK-NEXT: call void @_ZN7Elision1BC1Ev([[B]]* {{[^,]*}} [[BT2]]) // CHECK-NEXT: [[AM:%.*]] = getelementptr inbounds [[B]], [[B]]* [[BT2]], i32 0, i32 0 - // CHECK-NEXT: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[RET:%.*]], [[A]]* noundef {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[AM]]) + // CHECK-NEXT: call void @_ZN7Elision1AC1ERKS0_([[A]]* {{[^,]*}} [[RET:%.*]], [[A]]* {{(nonnull )?}}align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[AM]]) // CHECK-NEXT: call void @_ZN7Elision1BD1Ev([[B]]* {{[^,]*}} [[BT2]]) return B().a; @@ -553,10 +553,10 @@ namespace PR8623 { // CHECK: store i1 false, i1* [[LCONS]] // CHECK-NEXT: store i1 false, i1* [[RCONS]] // CHECK-NEXT: br i1 - // CHECK: call void @_ZN6PR86231AC1Ei([[A]]* {{[^,]*}} [[TMP]], i32 noundef 2) + // CHECK: call void @_ZN6PR86231AC1Ei([[A]]* {{[^,]*}} [[TMP]], i32 2) // CHECK-NEXT: store i1 true, i1* [[LCONS]] // CHECK-NEXT: br label - // CHECK: call void @_ZN6PR86231AC1Ei([[A]]* {{[^,]*}} [[TMP]], i32 noundef 3) + // CHECK: call void @_ZN6PR86231AC1Ei([[A]]* {{[^,]*}} [[TMP]], i32 3) // CHECK-NEXT: store i1 true, i1* [[RCONS]] // CHECK-NEXT: br label // CHECK: load i1, i1* [[RCONS]] @@ -787,19 +787,19 @@ namespace ArrayAccess { void f() { using T = A[3]; - // CHECK: call void @_ZN11ArrayAccess1AC1Ei({{.*}}, i32 noundef 1 + // CHECK: call void @_ZN11ArrayAccess1AC1Ei({{.*}}, i32 1 // CHECK-NOT: @_ZN11ArrayAccess1AD - // CHECK: call void @_ZN11ArrayAccess1AC1Ei({{.*}}, i32 noundef 2 + // CHECK: call void @_ZN11ArrayAccess1AC1Ei({{.*}}, i32 2 // CHECK-NOT: @_ZN11ArrayAccess1AD - // CHECK: call void @_ZN11ArrayAccess1AC1Ei({{.*}}, i32 noundef 3 + // CHECK: call void @_ZN11ArrayAccess1AC1Ei({{.*}}, i32 3 // CHECK-NOT: @_ZN11ArrayAccess1AD A &&a = T{1, 2, 3}[1]; - // CHECK: call void @_ZN11ArrayAccess1AC1Ei({{.*}}, i32 noundef 4 + // CHECK: call void @_ZN11ArrayAccess1AC1Ei({{.*}}, i32 4 // CHECK-NOT: @_ZN11ArrayAccess1AD - // CHECK: call void @_ZN11ArrayAccess1AC1Ei({{.*}}, i32 noundef 5 + // CHECK: call void @_ZN11ArrayAccess1AC1Ei({{.*}}, i32 5 // CHECK-NOT: @_ZN11ArrayAccess1AD - // CHECK: call void @_ZN11ArrayAccess1AC1Ei({{.*}}, i32 noundef 6 + // CHECK: call void @_ZN11ArrayAccess1AC1Ei({{.*}}, i32 6 // CHECK-NOT: @_ZN11ArrayAccess1AD A &&b = 2[T{4, 5, 6}]; @@ -815,7 +815,7 @@ namespace PR14130 { struct S { S(int); }; struct U { S &&s; }; U v { { 0 } }; - // CHECK: call void @_ZN7PR141301SC1Ei({{.*}} @_ZGRN7PR141301vE_, i32 noundef 0) + // CHECK: call void @_ZN7PR141301SC1Ei({{.*}} @_ZGRN7PR141301vE_, i32 0) // CHECK: store {{.*}} @_ZGRN7PR141301vE_, {{.*}} @_ZN7PR141301vE } diff --git a/clang/test/CodeGenCXX/this-nonnull.cpp b/clang/test/CodeGenCXX/this-nonnull.cpp index 1030f2d8aae97627157c4c0beb1c0003c0c6a125..7f146b6613991a3af13e6a4ceeb9c2947fc4207e 100644 --- a/clang/test/CodeGenCXX/this-nonnull.cpp +++ b/clang/test/CodeGenCXX/this-nonnull.cpp @@ -11,10 +11,10 @@ struct Struct { void TestReturnsVoid(Struct &s) { s.ReturnsVoid(); - // CHECK-YES: call void @_ZN6Struct11ReturnsVoidEv(%struct.Struct* noundef %0) + // CHECK-YES: call void @_ZN6Struct11ReturnsVoidEv(%struct.Struct* nonnull align 4 dereferenceable(12) %0) /// FIXME Use dereferenceable after dereferenceable respects NullPointerIsValid. - // CHECK-NO: call void @_ZN6Struct11ReturnsVoidEv(%struct.Struct* noundef %0) + // CHECK-NO: call void @_ZN6Struct11ReturnsVoidEv(%struct.Struct* align 4 dereferenceable_or_null(12) %0) } -// CHECK-YES: declare void @_ZN6Struct11ReturnsVoidEv(%struct.Struct* noundef) -// CHECK-NO: declare void @_ZN6Struct11ReturnsVoidEv(%struct.Struct* noundef) +// CHECK-YES: declare void @_ZN6Struct11ReturnsVoidEv(%struct.Struct* nonnull align 4 dereferenceable(12)) +// CHECK-NO: declare void @_ZN6Struct11ReturnsVoidEv(%struct.Struct* align 4 dereferenceable_or_null(12)) diff --git a/clang/test/CodeGenCXX/thunk-linkonce-odr.cpp b/clang/test/CodeGenCXX/thunk-linkonce-odr.cpp index e48284197e20128602d1ae50c3869baced20aa9c..82f2148e0b557acf7788dfb0615aba840e52632e 100644 --- a/clang/test/CodeGenCXX/thunk-linkonce-odr.cpp +++ b/clang/test/CodeGenCXX/thunk-linkonce-odr.cpp @@ -29,5 +29,5 @@ int g() { // Thunks should be marked as "linkonce ODR" not "weak". // -// CHECK: define linkonce_odr noundef i32 @_ZThn{{[48]}}_N1D1fEv -// CHECK: define linkonce_odr noundef i32 @_ZThn{{[48]}}_N1C1fEv +// CHECK: define linkonce_odr i32 @_ZThn{{[48]}}_N1D1fEv +// CHECK: define linkonce_odr i32 @_ZThn{{[48]}}_N1C1fEv diff --git a/clang/test/CodeGenCXX/thunk-returning-memptr.cpp b/clang/test/CodeGenCXX/thunk-returning-memptr.cpp index 77856abefa32c6384b735cd450ecee2481befcd1..5ec52eece58e6a65fc94e39e451b5045c1697a12 100644 --- a/clang/test/CodeGenCXX/thunk-returning-memptr.cpp +++ b/clang/test/CodeGenCXX/thunk-returning-memptr.cpp @@ -23,5 +23,5 @@ C::C() {} // Because of the tail call, the return value cannot be copied into a local // alloca. (PR39901) -// CHECK-LABEL: define linkonce_odr void @_ZThn4_N1C1fEv({ i32, i32 }* noalias sret({ i32, i32 }) align 4 %agg.result, %struct.C* noundef %this) +// CHECK-LABEL: define linkonce_odr void @_ZThn4_N1C1fEv({ i32, i32 }* noalias sret({ i32, i32 }) align 4 %agg.result, %struct.C* %this) // CHECK: tail call void @_ZN1C1fEv({ i32, i32 }* sret({ i32, i32 }) align 4 %agg.result diff --git a/clang/test/CodeGenCXX/thunks-ehspec.cpp b/clang/test/CodeGenCXX/thunks-ehspec.cpp index cfa67837b0bc70484e43e6b175a6826a32b114e4..41b2294b8eaf985547492a888f4ed8b112d0e888 100644 --- a/clang/test/CodeGenCXX/thunks-ehspec.cpp +++ b/clang/test/CodeGenCXX/thunks-ehspec.cpp @@ -17,13 +17,13 @@ class C : A, B { }; void C::primary_key() {} -// CHECK-LABEL: define available_externally void @_ZThn8_N1C9secondaryEv(%class.C* noundef %this) {{.*}} #2 +// CHECK-LABEL: define available_externally void @_ZThn8_N1C9secondaryEv(%class.C* %this) {{.*}} #2 // CHECK-NOT: invoke // CHECK: tail call void @_ZN1C9secondaryEv(%class.C* {{[^,]*}} %{{.*}}) // CHECK-NOT: invoke // CHECK: ret void -// CHECK-LABEL: define available_externally void @_ZThn8_N1C16secondary_varargEiz(%class.C* noundef %this, i32 noundef %0, ...) {{.*}} #2 +// CHECK-LABEL: define available_externally void @_ZThn8_N1C16secondary_varargEiz(%class.C* %this, i32 %0, ...) {{.*}} #2 // CHECK-NOT: invoke -// CHECK: musttail call void (%class.C*, i32, ...) @_ZN1C16secondary_varargEiz(%class.C* {{[^,]*}} %{{.*}}, i32 noundef %{{.*}}, ...) #3 +// CHECK: musttail call void (%class.C*, i32, ...) @_ZN1C16secondary_varargEiz(%class.C* {{[^,]*}} %{{.*}}, i32 %{{.*}}, ...) #3 // CHECK-NEXT: ret void diff --git a/clang/test/CodeGenCXX/thunks.cpp b/clang/test/CodeGenCXX/thunks.cpp index b5dde83f520189be8a7dfbf827086b7cf0432db0..c4109526d28c2ba156ed63f5223e69fe0f8ad071 100644 --- a/clang/test/CodeGenCXX/thunks.cpp +++ b/clang/test/CodeGenCXX/thunks.cpp @@ -88,7 +88,7 @@ struct B : A { }; // CHECK: define{{.*}} %{{.*}}* @_ZTch0_v0_n24_N5Test31B1fEv( -// WIN64: define weak_odr dso_local noundef %{{.*}} @"?f@B@Test3@@QEAAPEAUV1@2@XZ"( +// WIN64: define weak_odr dso_local %{{.*}} @"?f@B@Test3@@QEAAPEAUV1@2@XZ"( V2 *B::f() { return 0; } } @@ -327,10 +327,10 @@ namespace Test11 { // CHECK-DBG-NOT: dbg.declare // CHECK: ret - // WIN64-LABEL: define dso_local noundef %{{.*}}* @"?f@C@Test11@@UEAAPEAU12@XZ"(i8* + // WIN64-LABEL: define dso_local %{{.*}}* @"?f@C@Test11@@UEAAPEAU12@XZ"(i8* - // WIN64-LABEL: define weak_odr dso_local noundef %{{.*}}* @"?f@C@Test11@@QEAAPEAUA@2@XZ"(i8* - // WIN64: call noundef %{{.*}}* @"?f@C@Test11@@UEAAPEAU12@XZ"(i8* noundef %{{.*}}) + // WIN64-LABEL: define weak_odr dso_local %{{.*}}* @"?f@C@Test11@@QEAAPEAUA@2@XZ"(i8* + // WIN64: call %{{.*}}* @"?f@C@Test11@@UEAAPEAU12@XZ"(i8* %{{.*}}) // // Match the vbtable return adjustment. // WIN64: load i32*, i32** %{{[^,]*}}, align 8 @@ -372,15 +372,15 @@ namespace Test12 { // FIXME: The weak_odr linkage is probably not necessary and just an artifact // of Itanium ABI details. // WIN64-LABEL: define dso_local {{.*}} @"?f@C@Test12@@UEAAPEAU12@HZZ"( - // WIN64: call noundef %{{.*}}* @"?makeC@Test12@@YAPEAUC@1@XZ"() + // WIN64: call %{{.*}}* @"?makeC@Test12@@YAPEAUC@1@XZ"() // // This thunk needs return adjustment, clone. // WIN64-LABEL: define weak_odr dso_local {{.*}} @"?f@C@Test12@@W7EAAPEAUB@2@HZZ"( - // WIN64: call noundef %{{.*}}* @"?makeC@Test12@@YAPEAUC@1@XZ"() + // WIN64: call %{{.*}}* @"?makeC@Test12@@YAPEAUC@1@XZ"() // WIN64: getelementptr inbounds i8, i8* %{{.*}}, i32 8 // // Musttail call back to the A implementation after this adjustment from B to A. - // WIN64-LABEL: define linkonce_odr dso_local noundef %{{.*}}* @"?f@C@Test12@@W7EAAPEAU12@HZZ"( + // WIN64-LABEL: define linkonce_odr dso_local %{{.*}}* @"?f@C@Test12@@W7EAAPEAU12@HZZ"( // WIN64: getelementptr i8, i8* %{{[^,]*}}, i32 -8 // WIN64: musttail call {{.*}} @"?f@C@Test12@@UEAAPEAU12@HZZ"( C c; @@ -412,7 +412,7 @@ namespace Test13 { // CHECK: getelementptr inbounds i8, i8* {{.*}}, i64 8 // CHECK: ret %"struct.Test13::D"* - // WIN64-LABEL: define weak_odr dso_local noundef %"struct.Test13::D"* @"?foo1@D@Test13@@$4PPPPPPPE@A@EAAAEAUB1@2@XZ"( + // WIN64-LABEL: define weak_odr dso_local %"struct.Test13::D"* @"?foo1@D@Test13@@$4PPPPPPPE@A@EAAAEAUB1@2@XZ"( // This adjustment. // WIN64: getelementptr inbounds i8, i8* {{.*}}, i64 -12 // Call implementation. @@ -512,7 +512,7 @@ C c; // MSVC-LABEL: define linkonce_odr dso_local void @"?f@C@Test17@@G7EAAXPEBDZZ" // MSVC-SAME: (%"class.Test17::C"* %this, i8* %[[ARG:[^,]+]], ...) // MSVC: getelementptr i8, i8* %{{.*}}, i32 -8 -// MSVC: musttail call void (%"class.Test17::C"*, i8*, ...) @"?f@C@Test17@@EEAAXPEBDZZ"(%"class.Test17::C"* %{{.*}}, i8* noundef %[[ARG]], ...) +// MSVC: musttail call void (%"class.Test17::C"*, i8*, ...) @"?f@C@Test17@@EEAAXPEBDZZ"(%"class.Test17::C"* %{{.*}}, i8* %[[ARG]], ...) } /**** The following has to go at the end of the file ****/ @@ -529,7 +529,7 @@ C c; // CHECK-NONOPT-LABEL: define linkonce_odr void @_ZThn8_N6Test101C3fooEv // Checking with opt -// CHECK-OPT-LABEL: define internal void @_ZThn8_N6Test4B12_GLOBAL__N_11C1fEv(%"struct.Test4B::(anonymous namespace)::C"* noundef %this) unnamed_addr #1 align 2 +// CHECK-OPT-LABEL: define internal void @_ZThn8_N6Test4B12_GLOBAL__N_11C1fEv(%"struct.Test4B::(anonymous namespace)::C"* %this) unnamed_addr #1 align 2 // This is from Test5: // CHECK-OPT-LABEL: define linkonce_odr void @_ZTv0_n24_N5Test51B1fEv diff --git a/clang/test/CodeGenCXX/tls-init-funcs.cpp b/clang/test/CodeGenCXX/tls-init-funcs.cpp index d22d491b782494bdb76a4e972d2a36171256dcc7..e7e6540ba9a6432e87e59c17180af6304a1038a7 100644 --- a/clang/test/CodeGenCXX/tls-init-funcs.cpp +++ b/clang/test/CodeGenCXX/tls-init-funcs.cpp @@ -6,13 +6,13 @@ // CHECK: @_ZZ3inlvE3loc = linkonce_odr thread_local global i32 0 // CHECK: @_tlv_atexit({{.*}}@_ZN1AD1Ev // CHECK: call cxx_fast_tlscc i32* @_ZTW3ext() -// CHECK: declare cxx_fast_tlscc noundef i32* @_ZTW3ext() -// CHECK-DAG: define weak_odr hidden cxx_fast_tlscc noundef i32* @_ZTW2vtIiE() -// CHECK-DAG: define weak_odr hidden cxx_fast_tlscc noundef i32* @_ZTW2vtIvE() +// CHECK: declare cxx_fast_tlscc i32* @_ZTW3ext() +// CHECK-DAG: define weak_odr hidden cxx_fast_tlscc i32* @_ZTW2vtIiE() +// CHECK-DAG: define weak_odr hidden cxx_fast_tlscc i32* @_ZTW2vtIvE() // CHECK-DAG: define {{.*}} @_ZTW1a -// MINGW-DAG: define weak_odr hidden noundef i32* @_ZTW2vtIiE() {{.*}} comdat -// MINGW-DAG: define weak_odr hidden noundef i32* @_ZTW2vtIvE() {{.*}} comdat +// MINGW-DAG: define weak_odr hidden i32* @_ZTW2vtIiE() {{.*}} comdat +// MINGW-DAG: define weak_odr hidden i32* @_ZTW2vtIvE() {{.*}} comdat struct A { ~A(); diff --git a/clang/test/CodeGenCXX/trivial_abi.cpp b/clang/test/CodeGenCXX/trivial_abi.cpp index a77d6165cd48e3e9176103518ad5ee0d06b29a22..07efa5f7a363b8fe8f664be4752a3c94a1ea9d4c 100644 --- a/clang/test/CodeGenCXX/trivial_abi.cpp +++ b/clang/test/CodeGenCXX/trivial_abi.cpp @@ -73,7 +73,7 @@ Small D0::m0() { return {}; } // CHECK: %[[COERCE_DIVE:.*]] = getelementptr inbounds %[[STRUCT_SMALL]], %[[STRUCT_SMALL]]* %[[A]], i32 0, i32 0 // CHECK: %[[COERCE_VAL_IP:.*]] = inttoptr i64 %[[A_COERCE]] to i32* // CHECK: store i32* %[[COERCE_VAL_IP]], i32** %[[COERCE_DIVE]], align 8 -// CHECK: %[[CALL:.*]] = call noundef %[[STRUCT_SMALL]]* @_ZN5SmallD1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[A]]) +// CHECK: %[[CALL:.*]] = call %[[STRUCT_SMALL]]* @_ZN5SmallD1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[A]]) // CHECK: ret void // CHECK: } @@ -82,7 +82,7 @@ void testParamSmall(Small a) noexcept { // CHECK: define{{.*}} i64 @_Z15testReturnSmallv() // CHECK: %[[RETVAL:.*]] = alloca %[[STRUCT_SMALL:.*]], align 8 -// CHECK: %[[CALL:.*]] = call noundef %[[STRUCT_SMALL]]* @_ZN5SmallC1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[RETVAL]]) +// CHECK: %[[CALL:.*]] = call %[[STRUCT_SMALL]]* @_ZN5SmallC1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[RETVAL]]) // CHECK: %[[COERCE_DIVE:.*]] = getelementptr inbounds %[[STRUCT_SMALL]], %[[STRUCT_SMALL]]* %[[RETVAL]], i32 0, i32 0 // CHECK: %[[V0:.*]] = load i32*, i32** %[[COERCE_DIVE]], align 8 // CHECK: %[[COERCE_VAL_PI:.*]] = ptrtoint i32* %[[V0]] to i64 @@ -97,13 +97,13 @@ Small testReturnSmall() { // CHECK: define{{.*}} void @_Z14testCallSmall0v() // CHECK: %[[T:.*]] = alloca %[[STRUCT_SMALL:.*]], align 8 // CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_SMALL]], align 8 -// CHECK: %[[CALL:.*]] = call noundef %[[STRUCT_SMALL]]* @_ZN5SmallC1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[T]]) -// CHECK: %[[CALL1:.*]] = call noundef %[[STRUCT_SMALL]]* @_ZN5SmallC1ERKS_(%[[STRUCT_SMALL]]* {{[^,]*}} %[[AGG_TMP]], %[[STRUCT_SMALL]]* noundef nonnull align 8 dereferenceable(8) %[[T]]) +// CHECK: %[[CALL:.*]] = call %[[STRUCT_SMALL]]* @_ZN5SmallC1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[T]]) +// CHECK: %[[CALL1:.*]] = call %[[STRUCT_SMALL]]* @_ZN5SmallC1ERKS_(%[[STRUCT_SMALL]]* {{[^,]*}} %[[AGG_TMP]], %[[STRUCT_SMALL]]* nonnull align 8 dereferenceable(8) %[[T]]) // CHECK: %[[COERCE_DIVE:.*]] = getelementptr inbounds %[[STRUCT_SMALL]], %[[STRUCT_SMALL]]* %[[AGG_TMP]], i32 0, i32 0 // CHECK: %[[V0:.*]] = load i32*, i32** %[[COERCE_DIVE]], align 8 // CHECK: %[[COERCE_VAL_PI:.*]] = ptrtoint i32* %[[V0]] to i64 // CHECK: call void @_Z14testParamSmall5Small(i64 %[[COERCE_VAL_PI]]) -// CHECK: %[[CALL2:.*]] = call noundef %[[STRUCT_SMALL]]* @_ZN5SmallD1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[T]]) +// CHECK: %[[CALL2:.*]] = call %[[STRUCT_SMALL]]* @_ZN5SmallD1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[T]]) // CHECK: ret void // CHECK: } @@ -135,7 +135,7 @@ void testCallSmall1() { // CHECK: %[[COERCE_DIVE:.*]] = getelementptr inbounds %[[STRUCT_SMALL]], %[[STRUCT_SMALL]]* %[[AGG_TMP_ENSURED]], i32 0, i32 0 // CHECK: %[[COERCE_VAL_IP:.*]] = inttoptr i64 %[[CALL]] to i32* // CHECK: store i32* %[[COERCE_VAL_IP]], i32** %[[COERCE_DIVE]], align 8 -// CHECK: %[[CALL1:.*]] = call noundef %[[STRUCT_SMALL]]* @_ZN5SmallD1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[AGG_TMP_ENSURED]]) +// CHECK: %[[CALL1:.*]] = call %[[STRUCT_SMALL]]* @_ZN5SmallD1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[AGG_TMP_ENSURED]]) // CHECK: ret void // CHECK: } @@ -143,8 +143,8 @@ void testIgnoredSmall() { testReturnSmall(); } -// CHECK: define{{.*}} void @_Z14testParamLarge5Large(%[[STRUCT_LARGE:.*]]* noundef %[[A:.*]]) -// CHECK: %[[CALL:.*]] = call noundef %[[STRUCT_LARGE]]* @_ZN5LargeD1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[A]]) +// CHECK: define{{.*}} void @_Z14testParamLarge5Large(%[[STRUCT_LARGE:.*]]* %[[A:.*]]) +// CHECK: %[[CALL:.*]] = call %[[STRUCT_LARGE]]* @_ZN5LargeD1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[A]]) // CHECK: ret void // CHECK: } @@ -152,7 +152,7 @@ void testParamLarge(Large a) noexcept { } // CHECK: define{{.*}} void @_Z15testReturnLargev(%[[STRUCT_LARGE:.*]]* noalias sret(%[[STRUCT_LARGE]]) align 8 %[[AGG_RESULT:.*]]) -// CHECK: %[[CALL:.*]] = call noundef %[[STRUCT_LARGE]]* @_ZN5LargeC1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[AGG_RESULT]]) +// CHECK: %[[CALL:.*]] = call %[[STRUCT_LARGE]]* @_ZN5LargeC1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[AGG_RESULT]]) // CHECK: ret void // CHECK: } @@ -164,10 +164,10 @@ Large testReturnLarge() { // CHECK: define{{.*}} void @_Z14testCallLarge0v() // CHECK: %[[T:.*]] = alloca %[[STRUCT_LARGE:.*]], align 8 // CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_LARGE]], align 8 -// CHECK: %[[CALL:.*]] = call noundef %[[STRUCT_LARGE]]* @_ZN5LargeC1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[T]]) -// CHECK: %[[CALL1:.*]] = call noundef %[[STRUCT_LARGE]]* @_ZN5LargeC1ERKS_(%[[STRUCT_LARGE]]* {{[^,]*}} %[[AGG_TMP]], %[[STRUCT_LARGE]]* noundef nonnull align 8 dereferenceable(520) %[[T]]) -// CHECK: call void @_Z14testParamLarge5Large(%[[STRUCT_LARGE]]* noundef %[[AGG_TMP]]) -// CHECK: %[[CALL2:.*]] = call noundef %[[STRUCT_LARGE]]* @_ZN5LargeD1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[T]]) +// CHECK: %[[CALL:.*]] = call %[[STRUCT_LARGE]]* @_ZN5LargeC1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[T]]) +// CHECK: %[[CALL1:.*]] = call %[[STRUCT_LARGE]]* @_ZN5LargeC1ERKS_(%[[STRUCT_LARGE]]* {{[^,]*}} %[[AGG_TMP]], %[[STRUCT_LARGE]]* nonnull align 8 dereferenceable(520) %[[T]]) +// CHECK: call void @_Z14testParamLarge5Large(%[[STRUCT_LARGE]]* %[[AGG_TMP]]) +// CHECK: %[[CALL2:.*]] = call %[[STRUCT_LARGE]]* @_ZN5LargeD1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[T]]) // CHECK: ret void // CHECK: } @@ -179,7 +179,7 @@ void testCallLarge0() { // CHECK: define{{.*}} void @_Z14testCallLarge1v() // CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_LARGE:.*]], align 8 // CHECK: call void @_Z15testReturnLargev(%[[STRUCT_LARGE]]* sret(%[[STRUCT_LARGE]]) align 8 %[[AGG_TMP]]) -// CHECK: call void @_Z14testParamLarge5Large(%[[STRUCT_LARGE]]* noundef %[[AGG_TMP]]) +// CHECK: call void @_Z14testParamLarge5Large(%[[STRUCT_LARGE]]* %[[AGG_TMP]]) // CHECK: ret void // CHECK: } @@ -190,7 +190,7 @@ void testCallLarge1() { // CHECK: define{{.*}} void @_Z16testIgnoredLargev() // CHECK: %[[AGG_TMP_ENSURED:.*]] = alloca %[[STRUCT_LARGE:.*]], align 8 // CHECK: call void @_Z15testReturnLargev(%[[STRUCT_LARGE]]* sret(%[[STRUCT_LARGE]]) align 8 %[[AGG_TMP_ENSURED]]) -// CHECK: %[[CALL:.*]] = call noundef %[[STRUCT_LARGE]]* @_ZN5LargeD1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[AGG_TMP_ENSURED]]) +// CHECK: %[[CALL:.*]] = call %[[STRUCT_LARGE]]* @_ZN5LargeD1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[AGG_TMP_ENSURED]]) // CHECK: ret void // CHECK: } @@ -211,7 +211,7 @@ Trivial testReturnHasTrivial() { } // CHECK: define{{.*}} void @_Z23testReturnHasNonTrivialv(%[[STRUCT_NONTRIVIAL:.*]]* noalias sret(%[[STRUCT_NONTRIVIAL]]) align 4 %[[AGG_RESULT:.*]]) -// CHECK: %[[CALL:.*]] = call noundef %[[STRUCT_NONTRIVIAL]]* @_ZN10NonTrivialC1Ev(%[[STRUCT_NONTRIVIAL]]* {{[^,]*}} %[[AGG_RESULT]]) +// CHECK: %[[CALL:.*]] = call %[[STRUCT_NONTRIVIAL]]* @_ZN10NonTrivialC1Ev(%[[STRUCT_NONTRIVIAL]]* {{[^,]*}} %[[AGG_RESULT]]) // CHECK: ret void // CHECK: } @@ -223,14 +223,14 @@ NonTrivial testReturnHasNonTrivial() { // CHECK: define{{.*}} void @_Z18testExceptionSmallv() // CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_SMALL]], align 8 // CHECK: %[[AGG_TMP1:.*]] = alloca %[[STRUCT_SMALL]], align 8 -// CHECK: call noundef %[[STRUCT_SMALL]]* @_ZN5SmallC1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[AGG_TMP]]) -// CHECK: invoke noundef %[[STRUCT_SMALL]]* @_ZN5SmallC1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[AGG_TMP1]]) +// CHECK: call %[[STRUCT_SMALL]]* @_ZN5SmallC1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[AGG_TMP]]) +// CHECK: invoke %[[STRUCT_SMALL]]* @_ZN5SmallC1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[AGG_TMP1]]) // CHECK: call void @_Z20calleeExceptionSmall5SmallS_(i64 %{{.*}}, i64 %{{.*}}) // CHECK-NEXT: ret void // CHECK: landingpad { i8*, i32 } -// CHECK: call noundef %[[STRUCT_SMALL]]* @_ZN5SmallD1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[AGG_TMP]]) +// CHECK: call %[[STRUCT_SMALL]]* @_ZN5SmallD1Ev(%[[STRUCT_SMALL]]* {{[^,]*}} %[[AGG_TMP]]) // CHECK: br // CHECK: resume { i8*, i32 } @@ -244,14 +244,14 @@ void testExceptionSmall() { // CHECK: define{{.*}} void @_Z18testExceptionLargev() // CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_LARGE]], align 8 // CHECK: %[[AGG_TMP1:.*]] = alloca %[[STRUCT_LARGE]], align 8 -// CHECK: call noundef %[[STRUCT_LARGE]]* @_ZN5LargeC1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[AGG_TMP]]) -// CHECK: invoke noundef %[[STRUCT_LARGE]]* @_ZN5LargeC1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[AGG_TMP1]]) +// CHECK: call %[[STRUCT_LARGE]]* @_ZN5LargeC1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[AGG_TMP]]) +// CHECK: invoke %[[STRUCT_LARGE]]* @_ZN5LargeC1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[AGG_TMP1]]) -// CHECK: call void @_Z20calleeExceptionLarge5LargeS_(%[[STRUCT_LARGE]]* noundef %[[AGG_TMP]], %[[STRUCT_LARGE]]* noundef %[[AGG_TMP1]]) +// CHECK: call void @_Z20calleeExceptionLarge5LargeS_(%[[STRUCT_LARGE]]* %[[AGG_TMP]], %[[STRUCT_LARGE]]* %[[AGG_TMP1]]) // CHECK-NEXT: ret void // CHECK: landingpad { i8*, i32 } -// CHECK: call noundef %[[STRUCT_LARGE]]* @_ZN5LargeD1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[AGG_TMP]]) +// CHECK: call %[[STRUCT_LARGE]]* @_ZN5LargeD1Ev(%[[STRUCT_LARGE]]* {{[^,]*}} %[[AGG_TMP]]) // CHECK: br // CHECK: resume { i8*, i32 } diff --git a/clang/test/CodeGenCXX/ubsan-coroutines.cpp b/clang/test/CodeGenCXX/ubsan-coroutines.cpp index dacc229ce519e8d6acdb9fb5e8980b2ec6bb58d8..8ce15ee6ae7347f3a8972388c6d3d14e09f2b32f 100644 --- a/clang/test/CodeGenCXX/ubsan-coroutines.cpp +++ b/clang/test/CodeGenCXX/ubsan-coroutines.cpp @@ -1,8 +1,6 @@ // This test merely verifies that emitting the object file does not cause a // crash when the LLVM coroutines passes are run. -// PR42867: Disable this test for the new PM since the passes that lower the -// llvm.coro.* intrinsics have not yet been ported. -// RUN: %clang_cc1 -fno-experimental-new-pass-manager -emit-obj -std=c++2a -fsanitize=null %s -o %t.o +// RUN: %clang_cc1 -emit-obj -std=c++2a -fsanitize=null %s -o %t.o namespace std::experimental { template struct coroutine_traits { diff --git a/clang/test/CodeGenCXX/ubsan-suppress-checks.cpp b/clang/test/CodeGenCXX/ubsan-suppress-checks.cpp index 6033ac6baa97764216a87ec26d9a51e615da1dbe..1dc39cf58e13f331a956c172f44b30a394c510c3 100644 --- a/clang/test/CodeGenCXX/ubsan-suppress-checks.cpp +++ b/clang/test/CodeGenCXX/ubsan-suppress-checks.cpp @@ -67,7 +67,7 @@ struct A { // LAMBDA: ret void #endif - // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN1A11load_memberEv + // CHECK-LABEL: define linkonce_odr i32 @_ZN1A11load_memberEv int load_member() { // ALIGN: %[[THISINT3:[0-9]+]] = ptrtoint %struct.A* %{{.*}} to i64, !nosanitize // ALIGN: and i64 %[[THISINT3]], 3, !nosanitize @@ -79,7 +79,7 @@ struct A { // CHECK: ret i32 } - // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN1A11call_methodEv + // CHECK-LABEL: define linkonce_odr i32 @_ZN1A11call_methodEv int call_method() { // ALIGN: %[[THISINT4:[0-9]+]] = ptrtoint %struct.A* %{{.*}} to i64, !nosanitize // ALIGN: and i64 %[[THISINT4]], 3, !nosanitize @@ -127,7 +127,7 @@ struct A { // CHECK: ret void } - // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN1A22call_through_referenceERS_ + // CHECK-LABEL: define linkonce_odr i32 @_ZN1A22call_through_referenceERS_ static int call_through_reference(A &a) { // ALIGN: %[[OBJINT:[0-9]+]] = ptrtoint %struct.A* %{{.*}} to i64, !nosanitize // ALIGN: and i64 %[[OBJINT]], 3, !nosanitize @@ -137,7 +137,7 @@ struct A { // CHECK: ret i32 } - // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN1A20call_through_pointerEPS_ + // CHECK-LABEL: define linkonce_odr i32 @_ZN1A20call_through_pointerEPS_ static int call_through_pointer(A *a) { // CHECK: call void @__ubsan_handle_type_mismatch return a->load_member(); @@ -148,7 +148,7 @@ struct A { struct B { operator A*() const { return nullptr; } - // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN1B11load_memberEPS_ + // CHECK-LABEL: define linkonce_odr i32 @_ZN1B11load_memberEPS_ static int load_member(B *bp) { // Check &b before converting it to an A*. // CHECK: call void @__ubsan_handle_type_mismatch @@ -171,7 +171,7 @@ struct Base { struct Derived : public Base { int bar; - // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7Derived13load_member_2Ev + // CHECK-LABEL: define linkonce_odr i32 @_ZN7Derived13load_member_2Ev int load_member_2() { // ALIGN: %[[THISINT8:[0-9]+]] = ptrtoint %struct.Derived* %{{.*}} to i64, !nosanitize // ALIGN: and i64 %[[THISINT8]], 7, !nosanitize @@ -188,7 +188,7 @@ struct Derived : public Base { // CHECK: ret i32 } - // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7Derived13load_member_3Ev + // CHECK-LABEL: define linkonce_odr i32 @_ZN7Derived13load_member_3Ev int load_member_3() { // ALIGN: %[[THISINT9:[0-9]+]] = ptrtoint %struct.Derived* %{{.*}} to i64, !nosanitize // ALIGN: and i64 %[[THISINT9]], 7, !nosanitize @@ -202,7 +202,7 @@ struct Derived : public Base { // CHECK: ret i32 } - // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN7Derived13load_member_1Ev + // CHECK-LABEL: define linkonce_odr i32 @_ZN7Derived13load_member_1Ev int load_member_1() override { // ALIGN: %[[THISINT10:[0-9]+]] = ptrtoint %struct.Derived* %{{.*}} to i64, !nosanitize // ALIGN: and i64 %[[THISINT10]], 7, !nosanitize diff --git a/clang/test/CodeGenCXX/ubsan-vtable-checks.cpp b/clang/test/CodeGenCXX/ubsan-vtable-checks.cpp index 536536055fc6bcdeada4d9a9743d0a6fc3a9c387..889d09ed1471993f0c2561dd8b91c4c925153401 100644 --- a/clang/test/CodeGenCXX/ubsan-vtable-checks.cpp +++ b/clang/test/CodeGenCXX/ubsan-vtable-checks.cpp @@ -17,7 +17,7 @@ U::~U() {} // CHECK-VPTR-MS: @__ubsan_vptr_type_cache = external dso_local // ITANIUM: define{{.*}} i32 @_Z5get_vP1T -// MSABI: define dso_local noundef i32 @"?get_v +// MSABI: define dso_local i32 @"?get_v int get_v(T* t) { // First, we check that vtable is not loaded before a type check. // CHECK-NULL-NOT: load {{.*}} (%struct.T*{{.*}})**, {{.*}} (%struct.T*{{.*}})*** @@ -42,7 +42,7 @@ void delete_it(T *t) { } // ITANIUM: define{{.*}} %struct.U* @_Z7dyncastP1T -// MSABI: define dso_local noundef %struct.U* @"?dyncast +// MSABI: define dso_local %struct.U* @"?dyncast U* dyncast(T *t) { // First, we check that dynamic_cast is not called before a type check. // CHECK-VPTR-NOT: call i8* @__{{dynamic_cast|RTDynamicCast}} diff --git a/clang/test/CodeGenCXX/uncopyable-args.cpp b/clang/test/CodeGenCXX/uncopyable-args.cpp index d53f0cfe1c007b69fe2876e623397ece3a1cbea1..3b55cf760106c412c3715ad8fff637d184834355 100644 --- a/clang/test/CodeGenCXX/uncopyable-args.cpp +++ b/clang/test/CodeGenCXX/uncopyable-args.cpp @@ -58,12 +58,12 @@ void bar() { // CHECK-LABEL: define{{.*}} void @_ZN9move_ctor3barEv() // CHECK: call void @_Z{{.*}}C1Ev( // CHECK-NOT: call -// NEWABI: call void @_ZN9move_ctor3fooENS_1AE(%"struct.move_ctor::A"* noundef %{{.*}}) +// NEWABI: call void @_ZN9move_ctor3fooENS_1AE(%"struct.move_ctor::A"* %{{.*}}) // OLDABI: call void @_ZN9move_ctor3fooENS_1AE(i8* %{{.*}}) -// NEWABI-LABEL: declare void @_ZN9move_ctor3fooENS_1AE(%"struct.move_ctor::A"* noundef) +// NEWABI-LABEL: declare void @_ZN9move_ctor3fooENS_1AE(%"struct.move_ctor::A"*) // OLDABI-LABEL: declare void @_ZN9move_ctor3fooENS_1AE(i8*) -// WIN64-LABEL: declare dso_local void @"?foo@move_ctor@@YAXUA@1@@Z"(%"struct.move_ctor::A"* noundef) +// WIN64-LABEL: declare dso_local void @"?foo@move_ctor@@YAXUA@1@@Z"(%"struct.move_ctor::A"*) } namespace all_deleted { @@ -80,12 +80,12 @@ void bar() { // CHECK-LABEL: define{{.*}} void @_ZN11all_deleted3barEv() // CHECK: call void @_Z{{.*}}C1Ev( // CHECK-NOT: call -// NEWABI: call void @_ZN11all_deleted3fooENS_1AE(%"struct.all_deleted::A"* noundef %{{.*}}) +// NEWABI: call void @_ZN11all_deleted3fooENS_1AE(%"struct.all_deleted::A"* %{{.*}}) // OLDABI: call void @_ZN11all_deleted3fooENS_1AE(i8* %{{.*}}) -// NEWABI-LABEL: declare void @_ZN11all_deleted3fooENS_1AE(%"struct.all_deleted::A"* noundef) +// NEWABI-LABEL: declare void @_ZN11all_deleted3fooENS_1AE(%"struct.all_deleted::A"*) // OLDABI-LABEL: declare void @_ZN11all_deleted3fooENS_1AE(i8*) -// WIN64-LABEL: declare dso_local void @"?foo@all_deleted@@YAXUA@1@@Z"(%"struct.all_deleted::A"* noundef) +// WIN64-LABEL: declare dso_local void @"?foo@all_deleted@@YAXUA@1@@Z"(%"struct.all_deleted::A"*) } namespace implicitly_deleted { @@ -101,14 +101,14 @@ void bar() { // CHECK-LABEL: define{{.*}} void @_ZN18implicitly_deleted3barEv() // CHECK: call void @_Z{{.*}}C1Ev( // CHECK-NOT: call -// NEWABI: call void @_ZN18implicitly_deleted3fooENS_1AE(%"struct.implicitly_deleted::A"* noundef %{{.*}}) +// NEWABI: call void @_ZN18implicitly_deleted3fooENS_1AE(%"struct.implicitly_deleted::A"* %{{.*}}) // OLDABI: call void @_ZN18implicitly_deleted3fooENS_1AE(i8* %{{.*}}) -// NEWABI-LABEL: declare void @_ZN18implicitly_deleted3fooENS_1AE(%"struct.implicitly_deleted::A"* noundef) +// NEWABI-LABEL: declare void @_ZN18implicitly_deleted3fooENS_1AE(%"struct.implicitly_deleted::A"*) // OLDABI-LABEL: declare void @_ZN18implicitly_deleted3fooENS_1AE(i8*) // In MSVC 2013, the copy ctor is not deleted by a move assignment. In MSVC 2015, it is. // WIN64-18-LABEL: declare dso_local void @"?foo@implicitly_deleted@@YAXUA@1@@Z"(i64 -// WIN64-19-LABEL: declare dso_local void @"?foo@implicitly_deleted@@YAXUA@1@@Z"(%"struct.implicitly_deleted::A"* noundef) +// WIN64-19-LABEL: declare dso_local void @"?foo@implicitly_deleted@@YAXUA@1@@Z"(%"struct.implicitly_deleted::A"*) } namespace one_deleted { @@ -124,12 +124,12 @@ void bar() { // CHECK-LABEL: define{{.*}} void @_ZN11one_deleted3barEv() // CHECK: call void @_Z{{.*}}C1Ev( // CHECK-NOT: call -// NEWABI: call void @_ZN11one_deleted3fooENS_1AE(%"struct.one_deleted::A"* noundef %{{.*}}) +// NEWABI: call void @_ZN11one_deleted3fooENS_1AE(%"struct.one_deleted::A"* %{{.*}}) // OLDABI: call void @_ZN11one_deleted3fooENS_1AE(i8* %{{.*}}) -// NEWABI-LABEL: declare void @_ZN11one_deleted3fooENS_1AE(%"struct.one_deleted::A"* noundef) +// NEWABI-LABEL: declare void @_ZN11one_deleted3fooENS_1AE(%"struct.one_deleted::A"*) // OLDABI-LABEL: declare void @_ZN11one_deleted3fooENS_1AE(i8*) -// WIN64-LABEL: declare dso_local void @"?foo@one_deleted@@YAXUA@1@@Z"(%"struct.one_deleted::A"* noundef) +// WIN64-LABEL: declare dso_local void @"?foo@one_deleted@@YAXUA@1@@Z"(%"struct.one_deleted::A"*) } namespace copy_defaulted { @@ -169,7 +169,7 @@ void bar() { // CHECK: call void @_ZN14move_defaulted3fooENS_1AE(i8* %{{.*}}) // CHECK-LABEL: declare void @_ZN14move_defaulted3fooENS_1AE(i8*) -// WIN64-LABEL: declare dso_local void @"?foo@move_defaulted@@YAXUA@1@@Z"(%"struct.move_defaulted::A"* noundef) +// WIN64-LABEL: declare dso_local void @"?foo@move_defaulted@@YAXUA@1@@Z"(%"struct.move_defaulted::A"*) } namespace trivial_defaulted { @@ -206,12 +206,12 @@ void bar() { } // CHECK-LABEL: define{{.*}} void @_ZN14two_copy_ctors3barEv() // CHECK: call void @_Z{{.*}}C1Ev( -// NEWABI: call void @_ZN14two_copy_ctors3fooENS_1BE(%"struct.two_copy_ctors::B"* noundef %{{.*}}) -// OLDABI: call void @_ZN14two_copy_ctors3fooENS_1BE(%"struct.two_copy_ctors::B"* noundef byval -// NEWABI-LABEL: declare void @_ZN14two_copy_ctors3fooENS_1BE(%"struct.two_copy_ctors::B"* noundef) -// OLDABI-LABEL: declare void @_ZN14two_copy_ctors3fooENS_1BE(%"struct.two_copy_ctors::B"* noundef byval +// NEWABI: call void @_ZN14two_copy_ctors3fooENS_1BE(%"struct.two_copy_ctors::B"* %{{.*}}) +// OLDABI: call void @_ZN14two_copy_ctors3fooENS_1BE(%"struct.two_copy_ctors::B"* byval +// NEWABI-LABEL: declare void @_ZN14two_copy_ctors3fooENS_1BE(%"struct.two_copy_ctors::B"*) +// OLDABI-LABEL: declare void @_ZN14two_copy_ctors3fooENS_1BE(%"struct.two_copy_ctors::B"* byval -// WIN64-LABEL: declare dso_local void @"?foo@two_copy_ctors@@YAXUB@1@@Z"(%"struct.two_copy_ctors::B"* noundef) +// WIN64-LABEL: declare dso_local void @"?foo@two_copy_ctors@@YAXUB@1@@Z"(%"struct.two_copy_ctors::B"*) } namespace definition_only { @@ -223,7 +223,7 @@ struct A { void *foo(A a) { return a.p; } // NEWABI-LABEL: define{{.*}} i8* @_ZN15definition_only3fooENS_1AE(%"struct.definition_only::A"* // OLDABI-LABEL: define{{.*}} i8* @_ZN15definition_only3fooENS_1AE(i8* -// WIN64-LABEL: define dso_local noundef i8* @"?foo@definition_only@@YAPEAXUA@1@@Z"(%"struct.definition_only::A"* +// WIN64-LABEL: define dso_local i8* @"?foo@definition_only@@YAPEAXUA@1@@Z"(%"struct.definition_only::A"* } namespace deleted_by_member { @@ -239,7 +239,7 @@ struct A { void *foo(A a) { return a.b.p; } // NEWABI-LABEL: define{{.*}} i8* @_ZN17deleted_by_member3fooENS_1AE(%"struct.deleted_by_member::A"* // OLDABI-LABEL: define{{.*}} i8* @_ZN17deleted_by_member3fooENS_1AE(i8* -// WIN64-LABEL: define dso_local noundef i8* @"?foo@deleted_by_member@@YAPEAXUA@1@@Z"(%"struct.deleted_by_member::A"* +// WIN64-LABEL: define dso_local i8* @"?foo@deleted_by_member@@YAPEAXUA@1@@Z"(%"struct.deleted_by_member::A"* } namespace deleted_by_base { @@ -254,7 +254,7 @@ struct A : B { void *foo(A a) { return a.p; } // NEWABI-LABEL: define{{.*}} i8* @_ZN15deleted_by_base3fooENS_1AE(%"struct.deleted_by_base::A"* // OLDABI-LABEL: define{{.*}} i8* @_ZN15deleted_by_base3fooENS_1AE(i8* -// WIN64-LABEL: define dso_local noundef i8* @"?foo@deleted_by_base@@YAPEAXUA@1@@Z"(%"struct.deleted_by_base::A"* +// WIN64-LABEL: define dso_local i8* @"?foo@deleted_by_base@@YAPEAXUA@1@@Z"(%"struct.deleted_by_base::A"* } namespace deleted_by_member_copy { @@ -270,7 +270,7 @@ struct A { void *foo(A a) { return a.b.p; } // NEWABI-LABEL: define{{.*}} i8* @_ZN22deleted_by_member_copy3fooENS_1AE(%"struct.deleted_by_member_copy::A"* // OLDABI-LABEL: define{{.*}} i8* @_ZN22deleted_by_member_copy3fooENS_1AE(i8* -// WIN64-LABEL: define dso_local noundef i8* @"?foo@deleted_by_member_copy@@YAPEAXUA@1@@Z"(%"struct.deleted_by_member_copy::A"* +// WIN64-LABEL: define dso_local i8* @"?foo@deleted_by_member_copy@@YAPEAXUA@1@@Z"(%"struct.deleted_by_member_copy::A"* } namespace deleted_by_base_copy { @@ -285,7 +285,7 @@ struct A : B { void *foo(A a) { return a.p; } // NEWABI-LABEL: define{{.*}} i8* @_ZN20deleted_by_base_copy3fooENS_1AE(%"struct.deleted_by_base_copy::A"* // OLDABI-LABEL: define{{.*}} i8* @_ZN20deleted_by_base_copy3fooENS_1AE(i8* -// WIN64-LABEL: define dso_local noundef i8* @"?foo@deleted_by_base_copy@@YAPEAXUA@1@@Z"(%"struct.deleted_by_base_copy::A"* +// WIN64-LABEL: define dso_local i8* @"?foo@deleted_by_base_copy@@YAPEAXUA@1@@Z"(%"struct.deleted_by_base_copy::A"* } namespace explicit_delete { @@ -296,7 +296,7 @@ struct A { }; // NEWABI-LABEL: define{{.*}} i8* @_ZN15explicit_delete3fooENS_1AE(%"struct.explicit_delete::A"* // OLDABI-LABEL: define{{.*}} i8* @_ZN15explicit_delete3fooENS_1AE(i8* -// WIN64-LABEL: define dso_local noundef i8* @"?foo@explicit_delete@@YAPEAXUA@1@@Z"(%"struct.explicit_delete::A"* +// WIN64-LABEL: define dso_local i8* @"?foo@explicit_delete@@YAPEAXUA@1@@Z"(%"struct.explicit_delete::A"* void *foo(A a) { return a.p; } } diff --git a/clang/test/CodeGenCXX/unknown-anytype.cpp b/clang/test/CodeGenCXX/unknown-anytype.cpp index 029b58cc859c449a9057baef6f2bffcdff411059..045b445037271a26add0586b38e3676e966db5b9 100644 --- a/clang/test/CodeGenCXX/unknown-anytype.cpp +++ b/clang/test/CodeGenCXX/unknown-anytype.cpp @@ -18,7 +18,7 @@ int test0() { int test1() { extern __unknown_anytype test1_any(); - // COMMON: call noundef i32 @_Z9test1_anyv() + // COMMON: call i32 @_Z9test1_anyv() return (int) test1_any(); } @@ -39,7 +39,7 @@ float test2a() { float test3() { extern __unknown_anytype test3_any; // COMMON: [[FN:%.*]] = load float (i32)*, float (i32)** @test3_any, - // COMMON: call noundef float [[FN]](i32 noundef 5) + // COMMON: call float [[FN]](i32 5) return ((float(*)(int)) test3_any)(5); } @@ -62,7 +62,7 @@ void test5() { extern "C" __unknown_anytype test6_any(float *); long test6() { - // COMMON: call i64 @test6_any(float* noundef null) + // COMMON: call i64 @test6_any(float* null) return (long long) test6_any(0); } @@ -71,7 +71,7 @@ struct Test7 { }; extern "C" __unknown_anytype test7_any(int); Test7 test7() { - // COMMON: call void @test7_any({{%.*}}* sret({{%.*}}) align 1 {{%.*}}, i32 noundef 5) + // COMMON: call void @test7_any({{%.*}}* sret({{%.*}}) align 1 {{%.*}}, i32 5) return (Test7) test7_any(5); } @@ -83,24 +83,24 @@ struct Test8 { }; void Test8::test() { float f; - // COMMON: call noundef i32 @_ZN5Test83fooEv( + // COMMON: call i32 @_ZN5Test83fooEv( f = (int) foo(); - // COMMON: call noundef i32 @_ZN5Test83fooEi( + // COMMON: call i32 @_ZN5Test83fooEi( f = (int) foo(5); - // COMMON: call noundef i32 @_ZN5Test83fooEv( + // COMMON: call i32 @_ZN5Test83fooEv( f = (float) this->foo(); - // COMMON: call noundef i32 @_ZN5Test83fooEi( + // COMMON: call i32 @_ZN5Test83fooEi( f = (float) this->foo(5); } void test8(Test8 *p) { double d; - // COMMON: call noundef i32 @_ZN5Test83fooEv( + // COMMON: call i32 @_ZN5Test83fooEv( d = (double) p->foo(); - // COMMON: call noundef i32 @_ZN5Test83fooEi( + // COMMON: call i32 @_ZN5Test83fooEi( d = (double) p->foo(5); - // COMMON: call noundef i32 @_ZN5Test83fooEv( + // COMMON: call i32 @_ZN5Test83fooEv( d = (bool) (*p).foo(); - // COMMON: call noundef i32 @_ZN5Test83fooEi( + // COMMON: call i32 @_ZN5Test83fooEi( d = (bool) (*p).foo(5); } @@ -119,7 +119,7 @@ void test10() { extern "C" __unknown_anytype malloc(...); void test11() { void *s = (void*)malloc(12); - // COMMON: call i8* (i32, ...) @malloc(i32 noundef 12) + // COMMON: call i8* (i32, ...) @malloc(i32 12) void *d = (void*)malloc(435); - // COMMON: call i8* (i32, ...) @malloc(i32 noundef 435) + // COMMON: call i8* (i32, ...) @malloc(i32 435) } diff --git a/clang/test/CodeGenCXX/value-init.cpp b/clang/test/CodeGenCXX/value-init.cpp index bdcc20c5d752d71e1c4bed919dfb54cadd58dad8..f9f7d1be71143665a523621f1299199c1b24cce5 100644 --- a/clang/test/CodeGenCXX/value-init.cpp +++ b/clang/test/CodeGenCXX/value-init.cpp @@ -209,7 +209,7 @@ namespace test6 { // CHECK-NEXT: [[INNER:%.*]] = getelementptr inbounds [10 x [20 x [[A]]]], [10 x [20 x [[A]]]]* [[ARR]], i64 0, i64 0 // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [20 x [[A]]], [20 x [[A]]]* [[INNER]], i64 0, i64 0 - // CHECK-NEXT: call void @_ZN5test61AC1Ei([[A]]* {{[^,]*}} [[T0]], i32 noundef 5) + // CHECK-NEXT: call void @_ZN5test61AC1Ei([[A]]* {{[^,]*}} [[T0]], i32 5) // CHECK-NEXT: [[BEGIN:%.*]] = getelementptr inbounds [[A]], [[A]]* [[T0]], i64 1 // CHECK-NEXT: [[END:%.*]] = getelementptr inbounds [[A]], [[A]]* [[T0]], i64 20 // CHECK-NEXT: br label @@ -261,7 +261,7 @@ namespace PR11124 { // Ensure we produce an i1 here, and don't assert. // CHECK-LABEL: define{{.*}} void @_Z9r170806_bv( -// CHECK: call void @_Z9r170806_ab(i1 noundef zeroext false) +// CHECK: call void @_Z9r170806_ab(i1 zeroext false) void r170806_a(bool b = bool()); void r170806_b() { r170806_a(); } diff --git a/clang/test/CodeGenCXX/varargs.cpp b/clang/test/CodeGenCXX/varargs.cpp index 0417bf03f76d81c52319002b0e31f5f9daf3cf41..bb33ee7577d93ee0149c1945385a547b6b2677a2 100644 --- a/clang/test/CodeGenCXX/varargs.cpp +++ b/clang/test/CodeGenCXX/varargs.cpp @@ -12,7 +12,7 @@ namespace test0 { return -1; } - // CHECK: call noundef i32 (...) @_ZN5test05test1Ez(i32 noundef 0) + // CHECK: call i32 (...) @_ZN5test05test1Ez(i32 0) void test() { test1(0); } diff --git a/clang/test/CodeGenCXX/variadic-templates.cpp b/clang/test/CodeGenCXX/variadic-templates.cpp index 768fa113e1ae0339942801d30df8ae53b3960e4a..4974b6517b89fd45e192d29b095e6947112db474 100644 --- a/clang/test/CodeGenCXX/variadic-templates.cpp +++ b/clang/test/CodeGenCXX/variadic-templates.cpp @@ -5,7 +5,7 @@ int get_num_types(Types...) { return sizeof...(Types); } -// CHECK-LABEL: define weak_odr noundef i32 @_Z13get_num_typesIJifdEEiDpT_ +// CHECK-LABEL: define weak_odr i32 @_Z13get_num_typesIJifdEEiDpT_ // CHECK: ret i32 3 template int get_num_types(int, float, double); diff --git a/clang/test/CodeGenCXX/virtual-base-destructor-call.cpp b/clang/test/CodeGenCXX/virtual-base-destructor-call.cpp index 2cfd18338779c15b6e9d40b2a79d564b4cc236e3..29f1f5c7946e793cf246e377d897f09af3bf8fe3 100644 --- a/clang/test/CodeGenCXX/virtual-base-destructor-call.cpp +++ b/clang/test/CodeGenCXX/virtual-base-destructor-call.cpp @@ -41,11 +41,11 @@ int main() { // CHECK: call {{.*}} @_ZdlPv // basic_istream's base dtor is a no-op. -// CHECK: define linkonce_odr {{.*}} @_ZN13basic_istreamIcED2Ev(%struct.basic_istream* {{.*}}%this, i8** noundef %vtt) unnamed_addr +// CHECK: define linkonce_odr {{.*}} @_ZN13basic_istreamIcED2Ev(%struct.basic_istream* {{.*}}%this, i8** %vtt) unnamed_addr // CHECK-NOT: call // CHECK: } // basic_iostream's base dtor calls its non-virtual base dtor. -// CHECK: define linkonce_odr {{.*}} @_ZN14basic_iostreamIcED2Ev(%struct.basic_iostream* {{.*}}%this, i8** noundef %vtt) unnamed_addr +// CHECK: define linkonce_odr {{.*}} @_ZN14basic_iostreamIcED2Ev(%struct.basic_iostream* {{.*}}%this, i8** %vtt) unnamed_addr // CHECK: call {{.*}} @_ZN13basic_istreamIcED2Ev // CHECK: } diff --git a/clang/test/CodeGenCXX/virtual-bases.cpp b/clang/test/CodeGenCXX/virtual-bases.cpp index bce20bc7158faf4495adecb3498906121d2680a5..77fbf1465fea6a25ffc6e131b3a37bbeb5014258 100644 --- a/clang/test/CodeGenCXX/virtual-bases.cpp +++ b/clang/test/CodeGenCXX/virtual-bases.cpp @@ -12,7 +12,7 @@ struct B : virtual A { B(); }; -// CHECK-LABEL: define{{.*}} void @_ZN1BC2Ev(%struct.B* {{[^,]*}} %this, i8** noundef %vtt) unnamed_addr +// CHECK-LABEL: define{{.*}} void @_ZN1BC2Ev(%struct.B* {{[^,]*}} %this, i8** %vtt) unnamed_addr // CHECK-LABEL: define{{.*}} void @_ZN1BC1Ev(%struct.B* {{[^,]*}} %this) unnamed_addr B::B() { } @@ -20,8 +20,8 @@ struct C : virtual A { C(bool); }; -// CHECK-LABEL: define{{.*}} void @_ZN1CC2Eb(%struct.C* {{[^,]*}} %this, i8** noundef %vtt, i1 noundef zeroext %0) unnamed_addr -// CHECK-LABEL: define{{.*}} void @_ZN1CC1Eb(%struct.C* {{[^,]*}} %this, i1 noundef zeroext %0) unnamed_addr +// CHECK-LABEL: define{{.*}} void @_ZN1CC2Eb(%struct.C* {{[^,]*}} %this, i8** %vtt, i1 zeroext %0) unnamed_addr +// CHECK-LABEL: define{{.*}} void @_ZN1CC1Eb(%struct.C* {{[^,]*}} %this, i1 zeroext %0) unnamed_addr C::C(bool) { } // PR6251 @@ -58,7 +58,7 @@ namespace virtualBaseAlignment { // CHECK: %[[X:.*]] = getelementptr inbounds %[[STRUCT_B]], %[[STRUCT_B]]* %[[THIS1]], i32 0, i32 2 // CHECK: store i32 123, i32* %[[X]], align 16 -// CHECK: define linkonce_odr void @_ZN20virtualBaseAlignment1BC2Ev(%[[STRUCT_B]]* {{[^,]*}} %[[THIS:.*]], i8** noundef %{{.*}}) +// CHECK: define linkonce_odr void @_ZN20virtualBaseAlignment1BC2Ev(%[[STRUCT_B]]* {{[^,]*}} %[[THIS:.*]], i8** %{{.*}}) // CHECK: %[[THIS_ADDR:.*]] = alloca %[[STRUCT_B]]*, align 8 // CHECK: store %[[STRUCT_B]]* %[[THIS]], %[[STRUCT_B]]** %[[THIS_ADDR]], align 8 // CHECK: %[[THIS1:.*]] = load %[[STRUCT_B]]*, %[[STRUCT_B]]** %[[THIS_ADDR]], align 8 diff --git a/clang/test/CodeGenCXX/virtual-operator-call.cpp b/clang/test/CodeGenCXX/virtual-operator-call.cpp index cccf8148ac9225e7a825ea8c163a8a9af127f1a7..a3c3646ab12e06e0c27f1f5c26f9ed9883da0dc5 100644 --- a/clang/test/CodeGenCXX/virtual-operator-call.cpp +++ b/clang/test/CodeGenCXX/virtual-operator-call.cpp @@ -5,9 +5,9 @@ struct A { }; void f(A a, A *ap) { - // CHECK: call noundef i32 @_ZN1AngEv(%struct.A* {{[^,]*}} %a) + // CHECK: call i32 @_ZN1AngEv(%struct.A* {{[^,]*}} %a) -a; - // CHECK: call noundef i32 % + // CHECK: call i32 % -*ap; } diff --git a/clang/test/CodeGenCXX/visibility-inlines-hidden-staticvar.cpp b/clang/test/CodeGenCXX/visibility-inlines-hidden-staticvar.cpp index ac73b59816060e9dc8b79e91383908c654e8ec86..e50d8ddb4b4cf8b98649efe8b237bb4a712bf8e9 100644 --- a/clang/test/CodeGenCXX/visibility-inlines-hidden-staticvar.cpp +++ b/clang/test/CodeGenCXX/visibility-inlines-hidden-staticvar.cpp @@ -13,12 +13,12 @@ // CHECK-DAG: @_ZZ19inline_default_funcvE3var = linkonce_odr global i32 0, comdat // CHECK-DAG: @_ZZN13ExportedClass10inl_methodEvE3var = linkonce_odr global i32 0, comdat, align 4 // CHECK-DAG: define{{.*}} i32 @_Z4funcv() -// CHECK-DAG: define hidden noundef i32 @_Z11hidden_funcv() +// CHECK-DAG: define hidden i32 @_Z11hidden_funcv() // CHECK-DAG: define{{.*}} i32 @_Z12default_funcv() -// CHECK-DAG: define linkonce_odr hidden noundef i32 @_Z11inline_funcv() -// CHECK-DAG: define linkonce_odr hidden noundef i32 @_Z18inline_hidden_funcv() -// CHECK-DAG: define linkonce_odr noundef i32 @_Z19inline_default_funcv() -// CHECK-DAG: define linkonce_odr hidden noundef i32 @_ZN13ExportedClass10inl_methodEv({{.*}}) +// CHECK-DAG: define linkonce_odr hidden i32 @_Z11inline_funcv() +// CHECK-DAG: define linkonce_odr hidden i32 @_Z18inline_hidden_funcv() +// CHECK-DAG: define linkonce_odr i32 @_Z19inline_default_funcv() +// CHECK-DAG: define linkonce_odr hidden i32 @_ZN13ExportedClass10inl_methodEv({{.*}}) // CHECK-DAG: define{{.*}} i32 @_ZN13ExportedClass10ext_methodEv({{.*}}) // CHECK-NO-VIH-DAG: @_ZZ4funcvE3var = internal global i32 0 @@ -29,12 +29,12 @@ // CHECK-NO-VIH-DAG: @_ZZ19inline_default_funcvE3var = linkonce_odr global i32 0, comdat // CHECK-NO-VIH-DAG: @_ZZN13ExportedClass10inl_methodEvE3var = linkonce_odr global i32 0, comdat, align 4 // CHECK-NO-VIH-DAG: define{{.*}} i32 @_Z4funcv() -// CHECK-NO-VIH-DAG: define hidden noundef i32 @_Z11hidden_funcv() +// CHECK-NO-VIH-DAG: define hidden i32 @_Z11hidden_funcv() // CHECK-NO-VIH-DAG: define{{.*}} i32 @_Z12default_funcv() -// CHECK-NO-VIH-DAG: define linkonce_odr noundef i32 @_Z11inline_funcv() -// CHECK-NO-VIH-DAG: define linkonce_odr hidden noundef i32 @_Z18inline_hidden_funcv() -// CHECK-NO-VIH-DAG: define linkonce_odr noundef i32 @_Z19inline_default_funcv() -// CHECK-NO-VIH-DAG: define linkonce_odr noundef i32 @_ZN13ExportedClass10inl_methodEv({{.*}}) +// CHECK-NO-VIH-DAG: define linkonce_odr i32 @_Z11inline_funcv() +// CHECK-NO-VIH-DAG: define linkonce_odr hidden i32 @_Z18inline_hidden_funcv() +// CHECK-NO-VIH-DAG: define linkonce_odr i32 @_Z19inline_default_funcv() +// CHECK-NO-VIH-DAG: define linkonce_odr i32 @_ZN13ExportedClass10inl_methodEv({{.*}}) // CHECK-NO-VIH-DAG: define{{.*}} i32 @_ZN13ExportedClass10ext_methodEv({{.*}}) // CHECK-VIS-HIDDEN-DAG: @_ZZ4funcvE3var = internal global i32 0 @@ -44,13 +44,13 @@ // CHECK-VIS-HIDDEN-DAG: @_ZZ18inline_hidden_funcvE3var = linkonce_odr hidden global i32 0, comdat // CHECK-VIS-HIDDEN-DAG: @_ZZ19inline_default_funcvE3var = linkonce_odr global i32 0, comdat // CHECK-VIS-HIDDEN-DAG: @_ZZN13ExportedClass10inl_methodEvE3var = linkonce_odr global i32 0, comdat, align 4 -// CHECK-VIS-HIDDEN-DAG: define hidden noundef i32 @_Z4funcv() -// CHECK-VIS-HIDDEN-DAG: define hidden noundef i32 @_Z11hidden_funcv() +// CHECK-VIS-HIDDEN-DAG: define hidden i32 @_Z4funcv() +// CHECK-VIS-HIDDEN-DAG: define hidden i32 @_Z11hidden_funcv() // CHECK-VIS-HIDDEN-DAG: define{{.*}} i32 @_Z12default_funcv() -// CHECK-VIS-HIDDEN-DAG: define linkonce_odr hidden noundef i32 @_Z11inline_funcv() -// CHECK-VIS-HIDDEN-DAG: define linkonce_odr hidden noundef i32 @_Z18inline_hidden_funcv() -// CHECK-VIS-HIDDEN-DAG: define linkonce_odr noundef i32 @_Z19inline_default_funcv() -// CHECK-VIS-HIDDEN-DAG: define linkonce_odr hidden noundef i32 @_ZN13ExportedClass10inl_methodEv({{.*}}) +// CHECK-VIS-HIDDEN-DAG: define linkonce_odr hidden i32 @_Z11inline_funcv() +// CHECK-VIS-HIDDEN-DAG: define linkonce_odr hidden i32 @_Z18inline_hidden_funcv() +// CHECK-VIS-HIDDEN-DAG: define linkonce_odr i32 @_Z19inline_default_funcv() +// CHECK-VIS-HIDDEN-DAG: define linkonce_odr hidden i32 @_ZN13ExportedClass10inl_methodEv({{.*}}) // CHECK-VIS-HIDDEN-DAG: define{{.*}} i32 @_ZN13ExportedClass10ext_methodEv({{.*}}) // CHECK-VIS-PROTECTED-DAG: @_ZZ4funcvE3var = internal global i32 0 @@ -60,13 +60,13 @@ // CHECK-VIS-PROTECTED-DAG: @_ZZ18inline_hidden_funcvE3var = linkonce_odr hidden global i32 0, comdat // CHECK-VIS-PROTECTED-DAG: @_ZZ19inline_default_funcvE3var = linkonce_odr global i32 0, comdat // CHECK-VIS-PROTECTED-DAG: @_ZZN13ExportedClass10inl_methodEvE3var = linkonce_odr global i32 0, comdat, align 4 -// CHECK-VIS-PROTECTED-DAG: define protected noundef i32 @_Z4funcv() -// CHECK-VIS-PROTECTED-DAG: define hidden noundef i32 @_Z11hidden_funcv() +// CHECK-VIS-PROTECTED-DAG: define protected i32 @_Z4funcv() +// CHECK-VIS-PROTECTED-DAG: define hidden i32 @_Z11hidden_funcv() // CHECK-VIS-PROTECTED-DAG: define{{.*}} i32 @_Z12default_funcv() -// CHECK-VIS-PROTECTED-DAG: define linkonce_odr hidden noundef i32 @_Z11inline_funcv() -// CHECK-VIS-PROTECTED-DAG: define linkonce_odr hidden noundef i32 @_Z18inline_hidden_funcv() -// CHECK-VIS-PROTECTED-DAG: define linkonce_odr noundef i32 @_Z19inline_default_funcv() -// CHECK-VIS-PROTECTED-DAG: define linkonce_odr hidden noundef i32 @_ZN13ExportedClass10inl_methodEv({{.*}}) +// CHECK-VIS-PROTECTED-DAG: define linkonce_odr hidden i32 @_Z11inline_funcv() +// CHECK-VIS-PROTECTED-DAG: define linkonce_odr hidden i32 @_Z18inline_hidden_funcv() +// CHECK-VIS-PROTECTED-DAG: define linkonce_odr i32 @_Z19inline_default_funcv() +// CHECK-VIS-PROTECTED-DAG: define linkonce_odr hidden i32 @_ZN13ExportedClass10inl_methodEv({{.*}}) // CHECK-VIS-PROTECTED-DAG: define{{.*}} i32 @_ZN13ExportedClass10ext_methodEv({{.*}}) int func(void) { diff --git a/clang/test/CodeGenCXX/visibility-inlines-hidden.cpp b/clang/test/CodeGenCXX/visibility-inlines-hidden.cpp index 4744888a6c44cbbc32d148d3329ae0dcbee89269..20e4a1f45e3c696c1bfa61a7fcddbe9114bce730 100644 --- a/clang/test/CodeGenCXX/visibility-inlines-hidden.cpp +++ b/clang/test/CodeGenCXX/visibility-inlines-hidden.cpp @@ -106,7 +106,7 @@ namespace PR11642 { }; extern template class Foo; template class Foo; - // CHECK-LABEL: define weak_odr noundef i32 @_ZN7PR116423FooIiE3fooEi + // CHECK-LABEL: define weak_odr i32 @_ZN7PR116423FooIiE3fooEi } // Test that clang implements the new gcc behaviour for inline functions. @@ -166,7 +166,7 @@ namespace test6 { namespace PR34811 { template void tf() {} - // CHECK-LABEL: define linkonce_odr hidden noundef i8* @_ZN7PR348111fEv( + // CHECK-LABEL: define linkonce_odr hidden i8* @_ZN7PR348111fEv( inline void *f() { auto l = []() {}; // CHECK-LABEL: define linkonce_odr hidden void @_ZN7PR348112tfIZNS_1fEvEUlvE_EEvv( diff --git a/clang/test/CodeGenCXX/vla-consruct.cpp b/clang/test/CodeGenCXX/vla-consruct.cpp index 2b7bf029eca4825399b2614d7de334d7f67016c0..f9f966f641d5f7837affea6b906462d38b4ba5ac 100644 --- a/clang/test/CodeGenCXX/vla-consruct.cpp +++ b/clang/test/CodeGenCXX/vla-consruct.cpp @@ -18,7 +18,7 @@ void print(int n, int a, int b, int c, int d) { } void test(int n) { - // CHECK: define{{.*}} void {{.*test.*}}(i32 noundef [[n:%.+]]) # + // CHECK: define{{.*}} void {{.*test.*}}(i32 [[n:%.+]]) # // CHECK: [[n_addr:%.+]] = alloca // CHECK-NEXT: [[saved_stack:%.+]] = alloca // CHECK-NEXT: [[vla_expr:%.+]] = alloca i64, align 8 @@ -79,7 +79,7 @@ void test(int n) { // CHECK-NEXT: [[t13:%.+]] = load i32, i32* [[sizeof_array_t_0_0]] // CHECK-NEXT: [[t14:%.+]] = load i32, i32* [[sizeof_array_t_0]] // CHECK-NEXT: [[t15:%.+]] = load i32, i32* [[sizeof_array_t]] - // CHECK-NEXT: invoke void @{{.*print.*}}(i32 noundef [[t11]], i32 noundef [[t12]], i32 noundef [[t13]], i32 noundef [[t14]], i32 noundef [[t15]]) + // CHECK-NEXT: invoke void @{{.*print.*}}(i32 [[t11]], i32 [[t12]], i32 [[t13]], i32 [[t14]], i32 [[t15]]) // CHECK-NEXT: to label %[[invoke_cont:.+]] unwind label %[[lpad:.+]] // CHECK: [[invoke_cont]] diff --git a/clang/test/CodeGenCXX/vla-lambda-capturing.cpp b/clang/test/CodeGenCXX/vla-lambda-capturing.cpp index 7507163e40b03e8bda47a5681e25a301d6b80da6..7a101addddcb6928af3152bcaa36163ffb248057 100644 --- a/clang/test/CodeGenCXX/vla-lambda-capturing.cpp +++ b/clang/test/CodeGenCXX/vla-lambda-capturing.cpp @@ -70,11 +70,11 @@ void b(intptr_t n, T arg) { // CHECK-LABEL: @main int main() { - // CHECK: call {{.*}}void [[G]]([[INTPTR_T]] noundef [[INTPTR_T_ATTR:(signext )?]]1) + // CHECK: call {{.*}}void [[G]]([[INTPTR_T]] [[INTPTR_T_ATTR:(signext )?]]1) g((intptr_t)1); - // CHECK: call {{.*}}void [[F_INT:@.+]]([[INTPTR_T]] noundef [[INTPTR_T_ATTR]]1, [[INTPTR_T]] noundef [[INTPTR_T_ATTR]]2) + // CHECK: call {{.*}}void [[F_INT:@.+]]([[INTPTR_T]] [[INTPTR_T_ATTR]]1, [[INTPTR_T]] [[INTPTR_T_ATTR]]2) f((intptr_t)1, (intptr_t)2); - // CHECK: call {{.*}}void [[B_INT:@.+]]([[INTPTR_T]] noundef [[INTPTR_T_ATTR]]12, [[INTPTR_T]] noundef [[INTPTR_T_ATTR]]13) + // CHECK: call {{.*}}void [[B_INT:@.+]]([[INTPTR_T]] [[INTPTR_T_ATTR]]12, [[INTPTR_T]] [[INTPTR_T_ATTR]]13) b((intptr_t)12, (intptr_t)13); // CHECK: ret i32 0 return 0; diff --git a/clang/test/CodeGenCXX/vla.cpp b/clang/test/CodeGenCXX/vla.cpp index 3c5af8cea508bcd778739235c7a78a87ca69b017..858fd40d1edbdc6477af9c2c32ca99f5abb534b1 100644 --- a/clang/test/CodeGenCXX/vla.cpp +++ b/clang/test/CodeGenCXX/vla.cpp @@ -66,7 +66,7 @@ void test0(void *array, int n) { void test2(int b) { - // CHECK-LABEL: define{{.*}} void {{.*}}test2{{.*}}(i32 noundef %b) + // CHECK-LABEL: define{{.*}} void {{.*}}test2{{.*}}(i32 %b) int varr[b]; // AMDGCN: %__end1 = alloca i32*, align 8, addrspace(5) // AMDGCN: [[END:%.*]] = addrspacecast i32* addrspace(5)* %__end1 to i32** @@ -92,7 +92,7 @@ void test2(int b) { } void test3(int b, int c) { - // CHECK-LABEL: define{{.*}} void {{.*}}test3{{.*}}(i32 noundef %b, i32 noundef %c) + // CHECK-LABEL: define{{.*}} void {{.*}}test3{{.*}}(i32 %b, i32 %c) int varr[b][c]; // AMDGCN: %__end1 = alloca i32*, align 8, addrspace(5) // AMDGCN: [[END:%.*]] = addrspacecast i32* addrspace(5)* %__end1 to i32** diff --git a/clang/test/CodeGenCXX/volatile.cpp b/clang/test/CodeGenCXX/volatile.cpp index e94c209f54a9764921a9e3a3f5555f7274fb61a7..b20fffbeaf9d9bc9502f03b99e786111b3c70e5a 100644 --- a/clang/test/CodeGenCXX/volatile.cpp +++ b/clang/test/CodeGenCXX/volatile.cpp @@ -16,7 +16,7 @@ namespace test0 { void test(A t) { // CHECK: [[ARR:%.*]] = load [[A:%.*]]*, [[A:%.*]]** @_ZN5test05arrayE, align 8 // CHECK-NEXT: [[IDX:%.*]] = getelementptr inbounds [[A]], [[A]]* [[ARR]], i64 0 - // CHECK-NEXT: [[TMP:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[A]]* @_ZNV5test01AaSERVKS0_([[A]]* {{[^,]*}} [[IDX]], [[A]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[T:%.*]]) + // CHECK-NEXT: [[TMP:%.*]] = call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[A]]* @_ZNV5test01AaSERVKS0_([[A]]* {{[^,]*}} [[IDX]], [[A]]* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[T:%.*]]) // CHECK-NEXT: ret void array[0] = t; } diff --git a/clang/test/CodeGenCXX/vtable-assume-load.cpp b/clang/test/CodeGenCXX/vtable-assume-load.cpp index 6a25ebe87a1cd1e9db26334b8df5e5ef59382c3c..2d7aeebf9f331c16dd22122883baac63f2799ebc 100644 --- a/clang/test/CodeGenCXX/vtable-assume-load.cpp +++ b/clang/test/CodeGenCXX/vtable-assume-load.cpp @@ -164,7 +164,7 @@ void g(S &s) { s.foo(); } // if struct has novtable specifier, then we can't generate assumes // CHECK-MS-LABEL: define dso_local void @"?test@testMS@@YAXXZ"() -// CHECK-MS: call x86_thiscallcc noundef %"struct.testMS::S"* @"??0S@testMS@@QAE@XZ"( +// CHECK-MS: call x86_thiscallcc %"struct.testMS::S"* @"??0S@testMS@@QAE@XZ"( // CHECK-MS-NOT: @llvm.assume // CHECK-MS-LABEL: {{^}}} diff --git a/clang/test/CodeGenCXX/vtable-available-externally.cpp b/clang/test/CodeGenCXX/vtable-available-externally.cpp index d1648195c4a374c6024a4fd8ba23c98bc959feab..7ef7b1c1713e9b3b917ca6ea3efaa503165e0774 100644 --- a/clang/test/CodeGenCXX/vtable-available-externally.cpp +++ b/clang/test/CodeGenCXX/vtable-available-externally.cpp @@ -445,7 +445,7 @@ namespace Test18 { // CHECK-FORCE-EMIT-DAG: @_ZTVN6Test187DerivedE = linkonce_odr unnamed_addr constant {{.*}} @_ZTIN6Test187DerivedE {{.*}} @_ZN6Test184Base3funEv {{.*}} @_ZN6Test184BaseD2Ev {{.*}} @_ZN6Test187DerivedD0Ev // CHECK-FORCE-EMIT-DAG: define linkonce_odr void @_ZN6Test187DerivedD0Ev // CHECK-FORCE-EMIT-DAG: define linkonce_odr void @_ZN6Test184BaseD2Ev -// CHECK-FORCE-EMIT-DAG: define linkonce_odr noundef i32 @_ZN6Test184Base3funEv +// CHECK-FORCE-EMIT-DAG: define linkonce_odr i32 @_ZN6Test184Base3funEv // CHECK-FORCE-EMIT-DAG: @_ZTIN6Test187DerivedE = linkonce_odr constant struct Base { @@ -466,13 +466,13 @@ int foo() { namespace TestTemplates { // CHECK-FORCE-EMIT-DAG: @_ZTVN13TestTemplates8TemplateIiEE = linkonce_odr unnamed_addr constant {{.*}} @_ZTIN13TestTemplates8TemplateIiEE {{.*}} @_ZN13TestTemplates8TemplateIiE3fooEi {{.*}}@_ZN13TestTemplates8TemplateIiE22thisShouldBeEmittedTooEi {{.*}}@_ZN13TestTemplates8TemplateIiED1Ev {{.*}}@_ZN13TestTemplates8TemplateIiED0Ev -// CHECK-FORCE-EMIT-DAG: define linkonce_odr noundef i32 @_ZN13TestTemplates8TemplateIiE22thisShouldBeEmittedTooEi +// CHECK-FORCE-EMIT-DAG: define linkonce_odr i32 @_ZN13TestTemplates8TemplateIiE22thisShouldBeEmittedTooEi template struct Template { Template(); virtual T foo(T val); - // CHECK-FORCE-EMIT-DAG: define linkonce_odr noundef i32 @_ZN13TestTemplates8TemplateIiE22thisShouldBeEmittedTooEi + // CHECK-FORCE-EMIT-DAG: define linkonce_odr i32 @_ZN13TestTemplates8TemplateIiE22thisShouldBeEmittedTooEi virtual T thisShouldBeEmittedToo(T val) { return val; } virtual ~Template(); }; @@ -482,7 +482,7 @@ struct NonTemplate { typedef int T; NonTemplate(); virtual T foo(T val); - // CHECK-FORCE-EMIT-DAG: define linkonce_odr noundef i32 @_ZN13TestTemplates11NonTemplate22thisShouldBeEmittedTooEi + // CHECK-FORCE-EMIT-DAG: define linkonce_odr i32 @_ZN13TestTemplates11NonTemplate22thisShouldBeEmittedTooEi virtual T thisShouldBeEmittedToo(T val) { return val; } virtual ~NonTemplate(); }; @@ -494,7 +494,7 @@ struct OuterNonTemplate { struct NestedTemplateInNonTemplate { NestedTemplateInNonTemplate(); virtual T foo(T val); - // CHECK-FORCE-EMIT-DAG: define linkonce_odr noundef i32 @_ZN13TestTemplates16OuterNonTemplate27NestedTemplateInNonTemplateIiE22thisShouldBeEmittedTooEi + // CHECK-FORCE-EMIT-DAG: define linkonce_odr i32 @_ZN13TestTemplates16OuterNonTemplate27NestedTemplateInNonTemplateIiE22thisShouldBeEmittedTooEi virtual T thisShouldBeEmittedToo(T val) { return val; } virtual ~NestedTemplateInNonTemplate(); }; @@ -503,7 +503,7 @@ struct OuterNonTemplate { typedef int T; NestedNonTemplateInNonTemplate(); virtual T foo(T val); - // CHECK-FORCE-EMIT-DAG: define linkonce_odr noundef i32 @_ZN13TestTemplates16OuterNonTemplate30NestedNonTemplateInNonTemplate22thisShouldBeEmittedTooEi + // CHECK-FORCE-EMIT-DAG: define linkonce_odr i32 @_ZN13TestTemplates16OuterNonTemplate30NestedNonTemplateInNonTemplate22thisShouldBeEmittedTooEi virtual T thisShouldBeEmittedToo(T val) { return val; } virtual ~NestedNonTemplateInNonTemplate(); }; @@ -515,7 +515,7 @@ struct OuterTemplate { struct NestedTemplateInTemplate { NestedTemplateInTemplate(); virtual T foo(T val); - // CHECK-FORCE-EMIT-DAG: define linkonce_odr noundef i32 @_ZN13TestTemplates13OuterTemplateIlE24NestedTemplateInTemplateIiE22thisShouldBeEmittedTooEi + // CHECK-FORCE-EMIT-DAG: define linkonce_odr i32 @_ZN13TestTemplates13OuterTemplateIlE24NestedTemplateInTemplateIiE22thisShouldBeEmittedTooEi virtual T thisShouldBeEmittedToo(T val) { return val; } virtual ~NestedTemplateInTemplate(); }; @@ -524,7 +524,7 @@ struct OuterTemplate { typedef int T; NestedNonTemplateInTemplate(); virtual T foo(T val); - // CHECK-FORCE-EMIT-DAG: define linkonce_odr noundef i32 @_ZN13TestTemplates13OuterTemplateIlE27NestedNonTemplateInTemplate22thisShouldBeEmittedTooEi + // CHECK-FORCE-EMIT-DAG: define linkonce_odr i32 @_ZN13TestTemplates13OuterTemplateIlE27NestedNonTemplateInTemplate22thisShouldBeEmittedTooEi virtual T thisShouldBeEmittedToo(T val) { return val; } virtual ~NestedNonTemplateInTemplate(); }; diff --git a/clang/test/CodeGenCXX/wasm-args-returns.cpp b/clang/test/CodeGenCXX/wasm-args-returns.cpp index a0fa6b4482acc135c436f71270fd9c4f4c452c6e..c05bb44c05a3348b704073d393a9240e40de777d 100644 --- a/clang/test/CodeGenCXX/wasm-args-returns.cpp +++ b/clang/test/CodeGenCXX/wasm-args-returns.cpp @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -O1 -triple wasm32-unknown-unknown -emit-llvm -o - %s \ +// RUN: %clang_cc1 -O1 -triple wasm32-unknown-unknown -emit-llvm -o - %s \ // RUN: | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis -O1 -triple wasm64-unknown-unknown -emit-llvm -o - %s \ +// RUN: %clang_cc1 -O1 -triple wasm64-unknown-unknown -emit-llvm -o - %s \ // RUN: | FileCheck %s #define concat_(x, y) x##y diff --git a/clang/test/CodeGenCXX/wasm-eh.cpp b/clang/test/CodeGenCXX/wasm-eh.cpp index c5ae67ef96f78befe2d1ecc3fba2b37672079975..a323a73c9cb648f409dea23c01404edaaddb4c68 100644 --- a/clang/test/CodeGenCXX/wasm-eh.cpp +++ b/clang/test/CodeGenCXX/wasm-eh.cpp @@ -124,7 +124,7 @@ void test3() { // CHECK: [[EHCLEANUP_BB]]: // CHECK-NEXT: %[[CLEANUPPAD:.*]] = cleanuppad within none [] -// CHECK-NEXT: call noundef %struct.Cleanup* @_ZN7CleanupD1Ev(%struct.Cleanup* {{[^,]*}} %{{.*}}) {{.*}} [ "funclet"(token %[[CLEANUPPAD]]) ] +// CHECK-NEXT: call %struct.Cleanup* @_ZN7CleanupD1Ev(%struct.Cleanup* {{[^,]*}} %{{.*}}) {{.*}} [ "funclet"(token %[[CLEANUPPAD]]) ] // CHECK-NEXT: cleanupret from %[[CLEANUPPAD]] unwind to caller // Possibly throwing function call within a catch @@ -209,7 +209,7 @@ void test6() { // CHECK: [[EHCLEANUP_BB0]]: // CHECK-NEXT: %[[CLEANUPPAD0:.*]] = cleanuppad within none [] -// CHECK-NEXT: call noundef %struct.Cleanup* @_ZN7CleanupD1Ev(%struct.Cleanup* {{.*}}) {{.*}} [ "funclet"(token %[[CLEANUPPAD0]]) ] +// CHECK-NEXT: call %struct.Cleanup* @_ZN7CleanupD1Ev(%struct.Cleanup* {{.*}}) {{.*}} [ "funclet"(token %[[CLEANUPPAD0]]) ] // CHECK-NEXT: cleanupret from %[[CLEANUPPAD0]] unwind label %[[CATCH_DISPATCH_BB:.*]] // CHECK: [[CATCH_DISPATCH_BB]]: @@ -232,7 +232,7 @@ void test6() { // CHECK: [[EHCLEANUP_BB2]]: // CHECK-NEXT: %[[CLEANUPPAD2:.*]] = cleanuppad within %[[CATCHPAD]] [] -// CHECK-NEXT: call noundef %struct.Cleanup* @_ZN7CleanupD1Ev(%struct.Cleanup* {{[^,]*}} %{{.*}}) {{.*}} [ "funclet"(token %[[CLEANUPPAD2]]) ] +// CHECK-NEXT: call %struct.Cleanup* @_ZN7CleanupD1Ev(%struct.Cleanup* {{[^,]*}} %{{.*}}) {{.*}} [ "funclet"(token %[[CLEANUPPAD2]]) ] // CHECK-NEXT: cleanupret from %[[CLEANUPPAD2]] unwind label %[[EHCLEANUP_BB3:.*]] // CHECK: [[EHCLEANUP_BB3]]: @@ -241,7 +241,7 @@ void test6() { // CHECK: [[EHCLEANUP_BB1]]: // CHECK-NEXT: %[[CLEANUPPAD1:.*]] = cleanuppad within none [] -// CHECK-NEXT: call noundef %struct.Cleanup* @_ZN7CleanupD1Ev(%struct.Cleanup* {{[^,]*}} %{{.*}}) {{.*}} [ "funclet"(token %[[CLEANUPPAD1]]) ] +// CHECK-NEXT: call %struct.Cleanup* @_ZN7CleanupD1Ev(%struct.Cleanup* {{[^,]*}} %{{.*}}) {{.*}} [ "funclet"(token %[[CLEANUPPAD1]]) ] // CHECK-NEXT: cleanupret from %[[CLEANUPPAD1]] unwind to caller // CHECK: [[UNREACHABLE_BB]]: diff --git a/clang/test/CodeGenCXX/windows-on-arm-itanium-thread-local.cpp b/clang/test/CodeGenCXX/windows-on-arm-itanium-thread-local.cpp index 0cc80576ba715b51f6bb289cfe8184bad1068eda..ace6599139d4577637666172aeab31d251cb9359 100644 --- a/clang/test/CodeGenCXX/windows-on-arm-itanium-thread-local.cpp +++ b/clang/test/CodeGenCXX/windows-on-arm-itanium-thread-local.cpp @@ -6,7 +6,7 @@ void f(void *p) { c = p; } -// CHECK-LABEL: @_Z1fPv(i8* noundef %p) +// CHECK-LABEL: @_Z1fPv(i8* %p) // CHECK-NOT: call i8** @_ZTWL1c() // CHECK: call arm_aapcs_vfpcc i8** @_ZTWL1c() diff --git a/clang/test/CodeGenCXX/windows-x86-swiftcall.cpp b/clang/test/CodeGenCXX/windows-x86-swiftcall.cpp index b1aa8aad30f741cf666a8ab451032a8a6b486f62..d9fed9cf60419eecb3c5bb5c9ad9295ea8ba38d1 100644 --- a/clang/test/CodeGenCXX/windows-x86-swiftcall.cpp +++ b/clang/test/CodeGenCXX/windows-x86-swiftcall.cpp @@ -18,12 +18,12 @@ struct NonTrivial { SWIFTCALL int receiveNonTrivial(NonTrivial o) { return o.o; } -// CHECK-LABEL: define dso_local swiftcc noundef i32 @"?receiveNonTrivial@@YSHUNonTrivial@@@Z"(%struct.NonTrivial* noundef %o) +// CHECK-LABEL: define dso_local swiftcc i32 @"?receiveNonTrivial@@YSHUNonTrivial@@@Z"(%struct.NonTrivial* %o) int passNonTrivial() { return receiveNonTrivial({}); } -// CHECK-LABEL: define dso_local noundef i32 @"?passNonTrivial@@YAHXZ"() +// CHECK-LABEL: define dso_local i32 @"?passNonTrivial@@YAHXZ"() // CHECK-NOT: stacksave -// CHECK: call swiftcc noundef i32 @"?receiveNonTrivial@@YSHUNonTrivial@@@Z"(%struct.NonTrivial* noundef %{{.*}}) +// CHECK: call swiftcc i32 @"?receiveNonTrivial@@YSHUNonTrivial@@@Z"(%struct.NonTrivial* %{{.*}}) diff --git a/clang/test/CodeGenCXX/x86_32-arguments.cpp b/clang/test/CodeGenCXX/x86_32-arguments.cpp index 5f3241fd5e295a7b5cf5757ae49bcf2e317c3cda..9f7abaf1d7ad253b4c4799ea6adef6acae5b2831 100644 --- a/clang/test/CodeGenCXX/x86_32-arguments.cpp +++ b/clang/test/CodeGenCXX/x86_32-arguments.cpp @@ -8,7 +8,7 @@ struct S { // CHECK-LABEL: define{{.*}} void @_Z1fv(%struct.S* noalias sret(%struct.S) align 2 % S f() { return S(); } -// CHECK-LABEL: define{{.*}} void @_Z1f1S(%struct.S* noundef %0) +// CHECK-LABEL: define{{.*}} void @_Z1f1S(%struct.S* %0) void f(S) { } // Non-trivial dtors, should both be passed indirectly. @@ -21,7 +21,7 @@ public: // CHECK-LABEL: define{{.*}} void @_Z1gv(%class.C* noalias sret(%class.C) align 4 % C g() { return C(); } -// CHECK-LABEL: define{{.*}} void @_Z1f1C(%class.C* noundef %0) +// CHECK-LABEL: define{{.*}} void @_Z1f1C(%class.C* %0) void f(C) { } @@ -31,7 +31,7 @@ void f(C) { } // CHECK-LABEL: define{{.*}} void @_ZThn4_N18BasicAliasAnalysis13getModRefInfoE8CallSite // ... -// CHECK: %struct.CallSite* noundef byval(%struct.CallSite) align 4 %CS) +// CHECK: %struct.CallSite* byval(%struct.CallSite) align 4 %CS) struct CallSite { unsigned Ptr; CallSite(unsigned XX) : Ptr(XX) {} @@ -89,7 +89,7 @@ struct s5 { s5(); int &x; }; s5 f5() { return s5(); } // CHECK-LABEL: define{{.*}} i32 @_Z4f6_0M2s6i(i32 %a) -// CHECK: define{{.*}} i64 @_Z4f6_1M2s6FivE({ i32, i32 }* noundef byval({ i32, i32 }) align 4 %0) +// CHECK: define{{.*}} i64 @_Z4f6_1M2s6FivE({ i32, i32 }* byval({ i32, i32 }) align 4 %0) // FIXME: It would be nice to avoid byval on the previous case. struct s6 {}; typedef int s6::* s6_mdp; diff --git a/clang/test/CodeGenCXX/x86_64-arguments-avx.cpp b/clang/test/CodeGenCXX/x86_64-arguments-avx.cpp index fdd1c78e53f55a26d6afcd9301bd574c6746c61b..584b4d5a25282b158797b5c3e12c22920fcd7bab 100644 --- a/clang/test/CodeGenCXX/x86_64-arguments-avx.cpp +++ b/clang/test/CodeGenCXX/x86_64-arguments-avx.cpp @@ -56,6 +56,6 @@ union U { __attribute__((__vector_size__(32))) float f1; int f2; }; -// CHECK: define{{.*}} i32 @_ZN5test31fENS_1UE({{.*}}* noundef byval({{.*}}) align 32 +// CHECK: define{{.*}} i32 @_ZN5test31fENS_1UE({{.*}}* byval({{.*}}) align 32 int f(U u) { return u.f2; } } diff --git a/clang/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp b/clang/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp index f408d7e548f36421c861d4b9b13eeba7c4d358da..62df3ee37ab5ae45160cbd24005d9ea79c14fa5b 100644 --- a/clang/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp +++ b/clang/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp @@ -35,7 +35,7 @@ void f_struct_with_mfp_0(struct_with_mfp_0 a) { (void)a; } struct struct_with_mfp_1 { char *a; char *b; test_struct_mfp c; }; void f_struct_with_mfp_1(struct_with_mfp_1 a) { (void)a; } -// CHECK-LABEL: define{{.*}} void @{{.*}}f_struct_with_mfp_too_much{{.*}}({{.*}} byval({{.*}}) {{.*}} %a, i32 noundef %x) +// CHECK-LABEL: define{{.*}} void @{{.*}}f_struct_with_mfp_too_much{{.*}}({{.*}} byval({{.*}}) {{.*}} %a, i32 %x) struct struct_with_mfp_too_much { char *a; char *b; char *c; test_struct_mfp d; }; diff --git a/clang/test/CodeGenCXX/x86_64-arguments.cpp b/clang/test/CodeGenCXX/x86_64-arguments.cpp index 3ac753dbed1e79b72f8261c10f620839b220bd8f..40885bfec0a97f4b6efaf720d1d5ae81d5d9d663 100644 --- a/clang/test/CodeGenCXX/x86_64-arguments.cpp +++ b/clang/test/CodeGenCXX/x86_64-arguments.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-unknown-unknown -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | FileCheck %s // Basic base class test. struct f0_s0 { unsigned a; }; diff --git a/clang/test/CodeGenCoroutines/coro-alloc.cpp b/clang/test/CodeGenCoroutines/coro-alloc.cpp index 25a97b6d47f9abe8942a1139891f4449c76f18ee..c60ca5a83d484d35e9e833a91256d8efa7d5e17d 100644 --- a/clang/test/CodeGenCoroutines/coro-alloc.cpp +++ b/clang/test/CodeGenCoroutines/coro-alloc.cpp @@ -61,7 +61,7 @@ extern "C" void f0(global_new_delete_tag) { // CHECK: [[AllocBB]]: // CHECK: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() - // CHECK: %[[MEM:.+]] = call noalias noundef nonnull i8* @_Znwm(i64 noundef %[[SIZE]]) + // CHECK: %[[MEM:.+]] = call noalias nonnull i8* @_Znwm(i64 %[[SIZE]]) // CHECK: br label %[[InitBB]] // CHECK: [[InitBB]]: @@ -73,7 +73,7 @@ extern "C" void f0(global_new_delete_tag) { // CHECK: br i1 %[[NeedDealloc]], label %[[FreeBB:.+]], label %[[Afterwards:.+]] // CHECK: [[FreeBB]]: - // CHECK: call void @_ZdlPv(i8* noundef %[[MEM]]) + // CHECK: call void @_ZdlPv(i8* %[[MEM]]) // CHECK: br label %[[Afterwards]] // CHECK: [[Afterwards]]: @@ -98,11 +98,11 @@ struct std::experimental::coroutine_traits { extern "C" void f1(promise_new_tag ) { // CHECK: %[[ID:.+]] = call token @llvm.coro.id(i32 16 // CHECK: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() - // CHECK: call noundef i8* @_ZNSt12experimental16coroutine_traitsIJv15promise_new_tagEE12promise_typenwEm(i64 noundef %[[SIZE]]) + // CHECK: call i8* @_ZNSt12experimental16coroutine_traitsIJv15promise_new_tagEE12promise_typenwEm(i64 %[[SIZE]]) // CHECK: %[[FRAME:.+]] = call i8* @llvm.coro.begin( // CHECK: %[[MEM:.+]] = call i8* @llvm.coro.free(token %[[ID]], i8* %[[FRAME]]) - // CHECK: call void @_ZdlPv(i8* noundef %[[MEM]]) + // CHECK: call void @_ZdlPv(i8* %[[MEM]]) co_return; } @@ -130,7 +130,7 @@ extern "C" void f1a(promise_matching_placement_new_tag, int x, float y , double // CHECK: %[[INT:.+]] = load i32, i32* %x.addr, align 4 // CHECK: %[[FLOAT:.+]] = load float, float* %y.addr, align 4 // CHECK: %[[DOUBLE:.+]] = load double, double* %z.addr, align 8 - // CHECK: call noundef i8* @_ZNSt12experimental16coroutine_traitsIJv34promise_matching_placement_new_tagifdEE12promise_typenwEmS1_ifd(i64 noundef %[[SIZE]], i32 noundef %[[INT]], float noundef %[[FLOAT]], double noundef %[[DOUBLE]]) + // CHECK: call i8* @_ZNSt12experimental16coroutine_traitsIJv34promise_matching_placement_new_tagifdEE12promise_typenwEmS1_ifd(i64 %[[SIZE]], i32 %[[INT]], float %[[FLOAT]], double %[[DOUBLE]]) co_return; } @@ -156,7 +156,7 @@ struct std::experimental::coroutine_traits { extern "C" void f2(promise_delete_tag) { // CHECK: %[[ID:.+]] = call token @llvm.coro.id(i32 16 // CHECK: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() - // CHECK: call noalias noundef nonnull i8* @_Znwm(i64 noundef %[[SIZE]]) + // CHECK: call noalias nonnull i8* @_Znwm(i64 %[[SIZE]]) // CHECK: %[[FRAME:.+]] = call i8* @llvm.coro.begin( // CHECK: %[[MEM:.+]] = call i8* @llvm.coro.free(token %[[ID]], i8* %[[FRAME]]) - // CHECK: call void @_ZNSt12experimental16coroutine_traitsIJv18promise_delete_tagEE12promise_typedlEPv(i8* noundef %[[MEM]]) + // CHECK: call void @_ZNSt12experimental16coroutine_traitsIJv18promise_delete_tagEE12promise_typedlEPv(i8* %[[MEM]]) co_return; } @@ -202,12 +202,12 @@ struct std::experimental::coroutine_traits { extern "C" void f3(promise_sized_delete_tag) { // CHECK: %[[ID:.+]] = call token @llvm.coro.id(i32 16 // CHECK: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() - // CHECK: call noalias noundef nonnull i8* @_Znwm(i64 noundef %[[SIZE]]) + // CHECK: call noalias nonnull i8* @_Znwm(i64 %[[SIZE]]) // CHECK: %[[FRAME:.+]] = call i8* @llvm.coro.begin( // CHECK: %[[MEM:.+]] = call i8* @llvm.coro.free(token %[[ID]], i8* %[[FRAME]]) // CHECK: %[[SIZE2:.+]] = call i64 @llvm.coro.size.i64() - // CHECK: call void @_ZNSt12experimental16coroutine_traitsIJv24promise_sized_delete_tagEE12promise_typedlEPvm(i8* noundef %[[MEM]], i64 noundef %[[SIZE2]]) + // CHECK: call void @_ZNSt12experimental16coroutine_traitsIJv24promise_sized_delete_tagEE12promise_typedlEPvm(i8* %[[MEM]], i64 %[[SIZE2]]) co_return; } @@ -230,17 +230,17 @@ extern "C" int f4(promise_on_alloc_failure_tag) { // CHECK: %[[Gro:.+]] = alloca i32 // CHECK: %[[ID:.+]] = call token @llvm.coro.id(i32 16 // CHECK: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() - // CHECK: %[[MEM:.+]] = call noalias noundef i8* @_ZnwmRKSt9nothrow_t(i64 noundef %[[SIZE]], %"struct.std::nothrow_t"* noundef nonnull align 1 dereferenceable(1) @_ZStL7nothrow) + // CHECK: %[[MEM:.+]] = call noalias i8* @_ZnwmRKSt9nothrow_t(i64 %[[SIZE]], %"struct.std::nothrow_t"* nonnull align 1 dereferenceable(1) @_ZStL7nothrow) // CHECK: %[[OK:.+]] = icmp ne i8* %[[MEM]], null // CHECK: br i1 %[[OK]], label %[[OKBB:.+]], label %[[ERRBB:.+]] // CHECK: [[ERRBB]]: - // CHECK: %[[FailRet:.+]] = call noundef i32 @_ZNSt12experimental16coroutine_traitsIJi28promise_on_alloc_failure_tagEE12promise_type39get_return_object_on_allocation_failureEv( + // CHECK: %[[FailRet:.+]] = call i32 @_ZNSt12experimental16coroutine_traitsIJi28promise_on_alloc_failure_tagEE12promise_type39get_return_object_on_allocation_failureEv( // CHECK: store i32 %[[FailRet]], i32* %[[RetVal]] // CHECK: br label %[[RetBB:.+]] // CHECK: [[OKBB]]: - // CHECK: %[[OkRet:.+]] = call noundef i32 @_ZNSt12experimental16coroutine_traitsIJi28promise_on_alloc_failure_tagEE12promise_type17get_return_objectEv( + // CHECK: %[[OkRet:.+]] = call i32 @_ZNSt12experimental16coroutine_traitsIJi28promise_on_alloc_failure_tagEE12promise_type17get_return_objectEv( // CHECK: store i32 %[[OkRet]], i32* %[[Gro]] // CHECK: %[[Tmp1:.*]] = load i32, i32* %[[Gro]] diff --git a/clang/test/CodeGenCoroutines/coro-await.cpp b/clang/test/CodeGenCoroutines/coro-await.cpp index 0b44e0b9ce8e967668dcf20448cbf95169f95f12..3fa45d5f9ab68c620ac6d42514116d29bdd88c4f 100644 --- a/clang/test/CodeGenCoroutines/coro-await.cpp +++ b/clang/test/CodeGenCoroutines/coro-await.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-unknown-linux-gnu -fcoroutines-ts -std=c++14 \ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fcoroutines-ts -std=c++14 \ // RUN: -emit-llvm %s -o - -disable-llvm-passes -Wno-coroutine -Wno-unused | FileCheck %s namespace std { diff --git a/clang/test/CodeGenCoroutines/coro-builtins.c b/clang/test/CodeGenCoroutines/coro-builtins.c index 186d8f4fe11698773b8fbb6a17246424b9f52f44..9800eef0ed819c47bed6cc3706078d12cca78444 100644 --- a/clang/test/CodeGenCoroutines/coro-builtins.c +++ b/clang/test/CodeGenCoroutines/coro-builtins.c @@ -21,7 +21,7 @@ void f(int n) { __builtin_coro_noop(); // CHECK-NEXT: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() - // CHECK-NEXT: %[[MEM:.+]] = call i8* @myAlloc(i64 noundef %[[SIZE]]) + // CHECK-NEXT: %[[MEM:.+]] = call i8* @myAlloc(i64 %[[SIZE]]) // CHECK-NEXT: %[[FRAME:.+]] = call i8* @llvm.coro.begin(token %[[COROID]], i8* %[[MEM]]) __builtin_coro_begin(myAlloc(__builtin_coro_size())); diff --git a/clang/test/CodeGenCoroutines/coro-cleanup.cpp b/clang/test/CodeGenCoroutines/coro-cleanup.cpp index e0d1d32dc55ff87015d463987b385275b5f5b20c..7ef614e817d2ef38f25d6e953f73e12857e0f88f 100644 --- a/clang/test/CodeGenCoroutines/coro-cleanup.cpp +++ b/clang/test/CodeGenCoroutines/coro-cleanup.cpp @@ -39,7 +39,7 @@ void may_throw(); // CHECK-LABEL: define{{.*}} void @_Z1fv( void f() { - // CHECK: call noalias noundef nonnull i8* @_Znwm(i64 + // CHECK: call noalias nonnull i8* @_Znwm(i64 // If promise constructor throws, check that we free the memory. @@ -79,11 +79,11 @@ void f() { // CHECK: [[Cleanup]]: // CHECK: call void @_ZNSt12experimental16coroutine_traitsIJvEE12promise_typeD1Ev( // CHECK: %[[Mem0:.+]] = call i8* @llvm.coro.free( - // CHECK: call void @_ZdlPv(i8* noundef %[[Mem0]] + // CHECK: call void @_ZdlPv(i8* %[[Mem0]] // CHECK: [[Dealloc]]: // CHECK: %[[Mem:.+]] = call i8* @llvm.coro.free( - // CHECK: call void @_ZdlPv(i8* noundef %[[Mem]]) + // CHECK: call void @_ZdlPv(i8* %[[Mem]]) co_return; } diff --git a/clang/test/CodeGenCoroutines/coro-gro-nrvo.cpp b/clang/test/CodeGenCoroutines/coro-gro-nrvo.cpp index 437a21f968d06c2527c6681216595078216873ca..940617197bc958254cfd81c89e64358abf6cda94 100644 --- a/clang/test/CodeGenCoroutines/coro-gro-nrvo.cpp +++ b/clang/test/CodeGenCoroutines/coro-gro-nrvo.cpp @@ -34,9 +34,9 @@ struct coro { }; // Verify that the NRVO is applied to the Gro object. -// CHECK-LABEL: define{{.*}} void @_Z1fi(%struct.coro* noalias sret(%struct.coro) align 8 %agg.result, i32 noundef %0) +// CHECK-LABEL: define{{.*}} void @_Z1fi(%struct.coro* noalias sret(%struct.coro) align 8 %agg.result, i32 %0) coro f(int) { -// CHECK: %call = call noalias noundef nonnull i8* @_Znwm( +// CHECK: %call = call noalias nonnull i8* @_Znwm( // CHECK-NEXT: br label %[[CoroInit:.*]] // CHECK: {{.*}}[[CoroInit]]: @@ -65,10 +65,10 @@ struct coro_two { }; // Verify that the NRVO is applied to the Gro object. -// CHECK-LABEL: define{{.*}} void @_Z1hi(%struct.coro_two* noalias sret(%struct.coro_two) align 8 %agg.result, i32 noundef %0) +// CHECK-LABEL: define{{.*}} void @_Z1hi(%struct.coro_two* noalias sret(%struct.coro_two) align 8 %agg.result, i32 %0) coro_two h(int) { -// CHECK: %call = call noalias noundef i8* @_ZnwmRKSt9nothrow_t +// CHECK: %call = call noalias i8* @_ZnwmRKSt9nothrow_t // CHECK-NEXT: %[[CheckNull:.*]] = icmp ne i8* %call, null // CHECK-NEXT: br i1 %[[CheckNull]], label %[[InitOnSuccess:.*]], label %[[InitOnFailure:.*]] diff --git a/clang/test/CodeGenCoroutines/coro-gro.cpp b/clang/test/CodeGenCoroutines/coro-gro.cpp index 2c981dff468aef89318eec56dfff79ec2252c6c1..dd07185e3f8488b6569897ca9df428c8e5ce710b 100644 --- a/clang/test/CodeGenCoroutines/coro-gro.cpp +++ b/clang/test/CodeGenCoroutines/coro-gro.cpp @@ -49,7 +49,7 @@ int f() { // CHECK: %[[GroActive:.+]] = alloca i1 // CHECK: %[[Size:.+]] = call i64 @llvm.coro.size.i64() - // CHECK: call noalias noundef nonnull i8* @_Znwm(i64 noundef %[[Size]]) + // CHECK: call noalias nonnull i8* @_Znwm(i64 %[[Size]]) // CHECK: store i1 false, i1* %[[GroActive]] // CHECK: call void @_ZNSt12experimental16coroutine_traitsIJiEE12promise_typeC1Ev( // CHECK: call void @_ZNSt12experimental16coroutine_traitsIJiEE12promise_type17get_return_objectEv( @@ -67,11 +67,11 @@ int f() { // CHECK: call void @_ZNSt12experimental16coroutine_traitsIJiEE12promise_typeD1Ev( // CHECK: %[[Mem:.+]] = call i8* @llvm.coro.free( - // CHECK: call void @_ZdlPv(i8* noundef %[[Mem]]) + // CHECK: call void @_ZdlPv(i8* %[[Mem]]) // Initialize retval from Gro and destroy Gro - // CHECK: %[[Conv:.+]] = call noundef i32 @_ZN7GroTypecviEv( + // CHECK: %[[Conv:.+]] = call i32 @_ZN7GroTypecviEv( // CHECK: store i32 %[[Conv]], i32* %[[RetVal]] // CHECK: %[[IsActive:.+]] = load i1, i1* %[[GroActive]] // CHECK: br i1 %[[IsActive]], label %[[CleanupGro:.+]], label %[[Done:.+]] diff --git a/clang/test/CodeGenCoroutines/coro-params.cpp b/clang/test/CodeGenCoroutines/coro-params.cpp index 8908c6e3e7a538e2f6e3a8c0d87277c74d167c63..28753d524df285bafbca2e91237ac9a2c589d629 100644 --- a/clang/test/CodeGenCoroutines/coro-params.cpp +++ b/clang/test/CodeGenCoroutines/coro-params.cpp @@ -62,17 +62,17 @@ struct MoveAndCopy { void consume(int,int,int) noexcept; // TODO: Add support for CopyOnly params -// CHECK: define{{.*}} void @_Z1fi8MoveOnly11MoveAndCopy(i32 noundef %val, %struct.MoveOnly* noundef %[[MoParam:.+]], %struct.MoveAndCopy* noundef %[[McParam:.+]]) #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8* +// CHECK: define{{.*}} void @_Z1fi8MoveOnly11MoveAndCopy(i32 %val, %struct.MoveOnly* %[[MoParam:.+]], %struct.MoveAndCopy* %[[McParam:.+]]) #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8* void f(int val, MoveOnly moParam, MoveAndCopy mcParam) { // CHECK: %[[MoCopy:.+]] = alloca %struct.MoveOnly // CHECK: %[[McCopy:.+]] = alloca %struct.MoveAndCopy // CHECK: store i32 %val, i32* %[[ValAddr:.+]] // CHECK: call i8* @llvm.coro.begin( - // CHECK: call void @_ZN8MoveOnlyC1EOS_(%struct.MoveOnly* {{[^,]*}} %[[MoCopy]], %struct.MoveOnly* noundef nonnull align 4 dereferenceable(4) %[[MoParam]]) + // CHECK: call void @_ZN8MoveOnlyC1EOS_(%struct.MoveOnly* {{[^,]*}} %[[MoCopy]], %struct.MoveOnly* nonnull align 4 dereferenceable(4) %[[MoParam]]) // CHECK-NEXT: bitcast %struct.MoveAndCopy* %[[McCopy]] to i8* // CHECK-NEXT: call void @llvm.lifetime.start.p0i8( - // CHECK-NEXT: call void @_ZN11MoveAndCopyC1EOS_(%struct.MoveAndCopy* {{[^,]*}} %[[McCopy]], %struct.MoveAndCopy* noundef nonnull align 4 dereferenceable(4) %[[McParam]]) # + // CHECK-NEXT: call void @_ZN11MoveAndCopyC1EOS_(%struct.MoveAndCopy* {{[^,]*}} %[[McCopy]], %struct.MoveAndCopy* nonnull align 4 dereferenceable(4) %[[McParam]]) # // CHECK-NEXT: bitcast %"struct.std::experimental::coroutine_traits::promise_type"* %__promise to i8* // CHECK-NEXT: call void @llvm.lifetime.start.p0i8( // CHECK-NEXT: invoke void @_ZNSt12experimental16coroutine_traitsIJvi8MoveOnly11MoveAndCopyEE12promise_typeC1Ev( @@ -83,7 +83,7 @@ void f(int val, MoveOnly moParam, MoveAndCopy mcParam) { // CHECK: %[[MoVal:.+]] = load i32, i32* %[[MoGep]] // CHECK: %[[McGep:.+]] = getelementptr inbounds %struct.MoveAndCopy, %struct.MoveAndCopy* %[[McCopy]], i32 0, i32 0 // CHECK: %[[McVal:.+]] = load i32, i32* %[[McGep]] - // CHECK: call void @_Z7consumeiii(i32 noundef %[[IntParam]], i32 noundef %[[MoVal]], i32 noundef %[[McVal]]) + // CHECK: call void @_Z7consumeiii(i32 %[[IntParam]], i32 %[[MoVal]], i32 %[[McVal]]) consume(val, moParam.val, mcParam.val); co_return; @@ -107,7 +107,7 @@ void f(int val, MoveOnly moParam, MoveAndCopy mcParam) { // CHECK-NEXT: call i8* @llvm.coro.free( } -// CHECK-LABEL: void @_Z16dependent_paramsI1A1BEvT_T0_S3_(%struct.A* noundef %x, %struct.B* noundef %0, %struct.B* noundef %y) +// CHECK-LABEL: void @_Z16dependent_paramsI1A1BEvT_T0_S3_(%struct.A* %x, %struct.B* %0, %struct.B* %y) template void dependent_params(T x, U, U y) { // CHECK: %[[x_copy:.+]] = alloca %struct.A @@ -117,13 +117,13 @@ void dependent_params(T x, U, U y) { // CHECK: call i8* @llvm.coro.begin // CHECK-NEXT: bitcast %struct.A* %[[x_copy]] to i8* // CHECK-NEXT: call void @llvm.lifetime.start.p0i8( - // CHECK-NEXT: call void @_ZN1AC1EOS_(%struct.A* {{[^,]*}} %[[x_copy]], %struct.A* noundef nonnull align 4 dereferenceable(512) %x) + // CHECK-NEXT: call void @_ZN1AC1EOS_(%struct.A* {{[^,]*}} %[[x_copy]], %struct.A* nonnull align 4 dereferenceable(512) %x) // CHECK-NEXT: bitcast %struct.B* %[[unnamed_copy]] to i8* // CHECK-NEXT: call void @llvm.lifetime.start.p0i8( - // CHECK-NEXT: call void @_ZN1BC1EOS_(%struct.B* {{[^,]*}} %[[unnamed_copy]], %struct.B* noundef nonnull align 4 dereferenceable(512) %0) + // CHECK-NEXT: call void @_ZN1BC1EOS_(%struct.B* {{[^,]*}} %[[unnamed_copy]], %struct.B* nonnull align 4 dereferenceable(512) %0) // CHECK-NEXT: bitcast %struct.B* %[[y_copy]] to i8* // CHECK-NEXT: call void @llvm.lifetime.start.p0i8( - // CHECK-NEXT: call void @_ZN1BC1EOS_(%struct.B* {{[^,]*}} %[[y_copy]], %struct.B* noundef nonnull align 4 dereferenceable(512) %y) + // CHECK-NEXT: call void @_ZN1BC1EOS_(%struct.B* {{[^,]*}} %[[y_copy]], %struct.B* nonnull align 4 dereferenceable(512) %y) // CHECK-NEXT: bitcast %"struct.std::experimental::coroutine_traits::promise_type"* %__promise to i8* // CHECK-NEXT: call void @llvm.lifetime.start.p0i8( // CHECK-NEXT: invoke void @_ZNSt12experimental16coroutine_traitsIJv1A1BS2_EE12promise_typeC1Ev( @@ -168,12 +168,12 @@ struct std::experimental::coroutine_traits::promise_type"* {{[^,]*}} %__promise, i32 noundef %[[INT]], float noundef %[[FLOAT]], double noundef %[[DOUBLE]]) + // CHECK: invoke void @_ZNSt12experimental16coroutine_traitsIJv28promise_matching_constructorifdEE12promise_typeC1ES1_ifd(%"struct.std::experimental::coroutine_traits::promise_type"* {{[^,]*}} %__promise, i32 %[[INT]], float %[[FLOAT]], double %[[DOUBLE]]) co_return; } @@ -198,6 +198,6 @@ struct some_class { // CHECK-LABEL: define{{.*}} void @_ZN10some_class39good_coroutine_calls_custom_constructorEf(%struct.some_class* method some_class::good_coroutine_calls_custom_constructor(float) { - // CHECK: invoke void @_ZNSt12experimental16coroutine_traitsIJ6methodR10some_classfEE12promise_typeC1ES3_f(%"struct.std::experimental::coroutine_traits::promise_type"* {{[^,]*}} %__promise, %struct.some_class* noundef nonnull align 1 dereferenceable(1) %{{.+}}, float + // CHECK: invoke void @_ZNSt12experimental16coroutine_traitsIJ6methodR10some_classfEE12promise_typeC1ES3_f(%"struct.std::experimental::coroutine_traits::promise_type"* {{[^,]*}} %__promise, %struct.some_class* nonnull align 1 dereferenceable(1) %{{.+}}, float co_return; } diff --git a/clang/test/CodeGenCoroutines/coro-promise-dtor.cpp b/clang/test/CodeGenCoroutines/coro-promise-dtor.cpp index be92f1d2ab9ec09cef8a989e9addcd0c512451af..4fb0f0fef79401ecfc7ca4d45f30b7c2eab6761b 100644 --- a/clang/test/CodeGenCoroutines/coro-promise-dtor.cpp +++ b/clang/test/CodeGenCoroutines/coro-promise-dtor.cpp @@ -32,7 +32,7 @@ coro_t f() { // CHECK: %gro.active = alloca i1 // CHECK: store i1 false, i1* %gro.active -// CHECK: invoke noundef %"struct.coro_t::promise_type"* @"??0promise_type@coro_t@@QEAA@XZ"( +// CHECK: invoke %"struct.coro_t::promise_type"* @"??0promise_type@coro_t@@QEAA@XZ"( // CHECK: invoke void @"?get_return_object@promise_type@coro_t@@QEAA?AU2@XZ"( // CHECK: store i1 true, i1* %gro.active diff --git a/clang/test/CodeGenCoroutines/coro-ret-void.cpp b/clang/test/CodeGenCoroutines/coro-ret-void.cpp index d92fae96fdaf70b73f6319a630783e4cdfbf3588..1ef2950dd020bbdfb1ffc8869c295a06f8858bbe 100644 --- a/clang/test/CodeGenCoroutines/coro-ret-void.cpp +++ b/clang/test/CodeGenCoroutines/coro-ret-void.cpp @@ -50,4 +50,4 @@ coro2 g() { // CHECK-LABEL: define{{.*}} void @_Z1gv( // CHECK: call void @_ZNSt12experimental13coroutines_v113suspend_never12await_resumeEv(%"struct.std::experimental::coroutines_v1::suspend_never"* -// CHECK: call void @_ZN5coro212promise_type12return_valueEi(%"struct.coro2::promise_type"* {{[^,]*}} %__promise, i32 noundef 42) +// CHECK: call void @_ZN5coro212promise_type12return_valueEi(%"struct.coro2::promise_type"* {{[^,]*}} %__promise, i32 42) diff --git a/clang/test/CodeGenCoroutines/coro-return.cpp b/clang/test/CodeGenCoroutines/coro-return.cpp index 2625d8c95fd10d25d252a80236a9ca9d61e792b9..d35954ed7a861499240059035e647eae2122a6c8 100644 --- a/clang/test/CodeGenCoroutines/coro-return.cpp +++ b/clang/test/CodeGenCoroutines/coro-return.cpp @@ -33,7 +33,7 @@ template <> struct std::experimental::coroutine_traits { // CHECK-LABEL: f0( extern "C" void f0() { // CHECK: %__promise = alloca %"struct.std::experimental::coroutine_traits::promise_type" - // CHECK: %call = call noalias noundef nonnull i8* @_Znwm( + // CHECK: %call = call noalias nonnull i8* @_Znwm( // CHECK: call void @_ZNSt12experimental16coroutine_traitsIJvEE12promise_type11return_voidEv(%"struct.std::experimental::coroutine_traits::promise_type"* {{[^,]*}} %__promise) // CHECK: call void @_ZdlPv co_return; @@ -52,8 +52,8 @@ struct std::experimental::coroutine_traits { // CHECK-LABEL: f1( extern "C" int f1() { // CHECK: %__promise = alloca %"struct.std::experimental::coroutine_traits::promise_type" - // CHECK: %call = call noalias noundef nonnull i8* @_Znwm( - // CHECK: call void @_ZNSt12experimental16coroutine_traitsIJiEE12promise_type12return_valueEi(%"struct.std::experimental::coroutine_traits::promise_type"* {{[^,]*}} %__promise, i32 noundef 42) + // CHECK: %call = call noalias nonnull i8* @_Znwm( + // CHECK: call void @_ZNSt12experimental16coroutine_traitsIJiEE12promise_type12return_valueEi(%"struct.std::experimental::coroutine_traits::promise_type"* {{[^,]*}} %__promise, i32 42) // CHECK: call void @_ZdlPv co_return 42; } diff --git a/clang/test/CodeGenCoroutines/coro-symmetric-transfer-01.cpp b/clang/test/CodeGenCoroutines/coro-symmetric-transfer-01.cpp index cf902eb5b5562a85fecb25758290bf654787c282..e9f09c8da038ba3a2982022e934046a94b1a22ba 100644 --- a/clang/test/CodeGenCoroutines/coro-symmetric-transfer-01.cpp +++ b/clang/test/CodeGenCoroutines/coro-symmetric-transfer-01.cpp @@ -57,7 +57,7 @@ detached_task foo() { // CHECK: %[[CALL:.+]] = call i8* @_ZN13detached_task12promise_type13final_awaiter13await_suspendENSt12experimental13coroutines_v116coroutine_handleIS0_EE( // CHECK: %[[HDL_CAST2:.+]] = getelementptr inbounds %"struct.std::experimental::coroutines_v1::coroutine_handle.0", %"struct.std::experimental::coroutines_v1::coroutine_handle.0"* %[[HDL]], i32 0, i32 0 // CHECK: store i8* %[[CALL]], i8** %[[HDL_CAST2]], align 8 -// CHECK: %[[HDL_TRANSFER:.+]] = call noundef i8* @_ZNKSt12experimental13coroutines_v116coroutine_handleIvE7addressEv(%"struct.std::experimental::coroutines_v1::coroutine_handle.0"* noundef %[[HDL]]) +// CHECK: %[[HDL_TRANSFER:.+]] = call i8* @_ZNKSt12experimental13coroutines_v116coroutine_handleIvE7addressEv(%"struct.std::experimental::coroutines_v1::coroutine_handle.0"* nonnull align 8 dereferenceable(8) %[[HDL]]) // CHECK: %[[HDL_CAST3:.+]] = bitcast %"struct.std::experimental::coroutines_v1::coroutine_handle.0"* %[[HDL]] to i8* // CHECK: call void @llvm.lifetime.end.p0i8(i64 8, i8* %[[HDL_CAST3]]) // CHECK: call void @llvm.coro.resume(i8* %[[HDL_TRANSFER]]) diff --git a/clang/test/CodeGenObjC/arc-blocks.m b/clang/test/CodeGenObjC/arc-blocks.m index feb6629a5670c01dbed537c3dc9e5054ac6124c4..6fa25a0aa0857c6005397da64b03aef702216be8 100644 --- a/clang/test/CodeGenObjC/arc-blocks.m +++ b/clang/test/CodeGenObjC/arc-blocks.m @@ -49,7 +49,7 @@ void test2(id x) { extern void test2_helper(id (^)(void)); test2_helper(^{ return x; }); -// CHECK: define linkonce_odr hidden void @__copy_helper_block_8_32s(i8* noundef %0, i8* noundef %1) unnamed_addr #{{[0-9]+}} { +// CHECK: define linkonce_odr hidden void @__copy_helper_block_8_32s(i8* %0, i8* %1) unnamed_addr #{{[0-9]+}} { // CHECK: [[T0:%.*]] = load i8*, i8** // CHECK-NEXT: [[SRC:%.*]] = bitcast i8* [[T0]] to [[BLOCK_T]]* // CHECK-NEXT: [[T0:%.*]] = load i8*, i8** @@ -60,7 +60,7 @@ void test2(id x) { // CHECK-NEXT: ret void -// CHECK: define linkonce_odr hidden void @__destroy_helper_block_8_32s(i8* noundef %0) unnamed_addr #{{[0-9]+}} { +// CHECK: define linkonce_odr hidden void @__destroy_helper_block_8_32s(i8* %0) unnamed_addr #{{[0-9]+}} { // CHECK: [[T0:%.*]] = load i8*, i8** // CHECK-NEXT: [[T1:%.*]] = bitcast i8* [[T0]] to [[BLOCK_T]]* // CHECK-NEXT: [[T2:%.*]] = getelementptr inbounds [[BLOCK_T]], [[BLOCK_T]]* [[T1]], i32 0, i32 5 @@ -93,7 +93,7 @@ void test3(void (^sink)(id*)) { // CHECK-NEXT: store i8* [[V]], i8** [[TEMP]] // CHECK-NEXT: [[F0:%.*]] = load i8*, i8** // CHECK-NEXT: [[F1:%.*]] = bitcast i8* [[F0]] to void (i8*, i8**)* - // CHECK-NEXT: call void [[F1]](i8* noundef [[BLOCK]], i8** noundef [[TEMP]]) + // CHECK-NEXT: call void [[F1]](i8* [[BLOCK]], i8** [[TEMP]]) // CHECK-NEXT: [[T0:%.*]] = load i8*, i8** [[TEMP]] // CHECK-NEXT: [[T1:%.*]] = call i8* @llvm.objc.retain(i8* [[T0]]) // CHECK-NEXT: call void (...) @llvm.objc.clang.arc.use(i8* [[V]]) [[NUW]] @@ -141,7 +141,7 @@ void test4(void) { // CHECK-NEXT: call void @llvm.objc.release(i8* [[T0]]) // CHECK: ret void - // CHECK-LABEL: define internal void @__Block_byref_object_copy_(i8* noundef %0, i8* noundef %1) #{{[0-9]+}} { + // CHECK-LABEL: define internal void @__Block_byref_object_copy_(i8* %0, i8* %1) #{{[0-9]+}} { // CHECK: [[T0:%.*]] = getelementptr inbounds [[BYREF_T]], [[BYREF_T]]* {{%.*}}, i32 0, i32 6 // CHECK-NEXT: load i8*, i8** // CHECK-NEXT: bitcast i8* {{%.*}} to [[BYREF_T]]* @@ -150,7 +150,7 @@ void test4(void) { // CHECK-NEXT: store i8* [[T2]], i8** [[T0]] // CHECK-NEXT: store i8* null, i8** [[T1]] - // CHECK-LABEL: define internal void @__Block_byref_object_dispose_(i8* noundef %0) #{{[0-9]+}} { + // CHECK-LABEL: define internal void @__Block_byref_object_dispose_(i8* %0) #{{[0-9]+}} { // CHECK: [[T0:%.*]] = getelementptr inbounds [[BYREF_T]], [[BYREF_T]]* {{%.*}}, i32 0, i32 6 // CHECK-NEXT: [[T1:%.*]] = load i8*, i8** [[T0]] // CHECK-NEXT: call void @llvm.objc.release(i8* [[T1]]) @@ -162,10 +162,10 @@ void test4(void) { // CHECK-NEXT: call void @llvm.objc.release(i8* [[T0]]) // CHECK-NEXT: ret void - // CHECK-LABEL: define linkonce_odr hidden void @__copy_helper_block_8_32r(i8* noundef %0, i8* noundef %1) unnamed_addr #{{[0-9]+}} { + // CHECK-LABEL: define linkonce_odr hidden void @__copy_helper_block_8_32r(i8* %0, i8* %1) unnamed_addr #{{[0-9]+}} { // CHECK: call void @_Block_object_assign(i8* {{%.*}}, i8* {{%.*}}, i32 8) - // CHECK-LABEL: define linkonce_odr hidden void @__destroy_helper_block_8_32r(i8* noundef %0) unnamed_addr #{{[0-9]+}} { + // CHECK-LABEL: define linkonce_odr hidden void @__destroy_helper_block_8_32r(i8* %0) unnamed_addr #{{[0-9]+}} { // CHECK: call void @_Block_object_dispose(i8* {{%.*}}, i32 8) } @@ -230,14 +230,14 @@ void test6(void) { // CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 48, i8* [[VARPTR2]]) // CHECK-NEXT: ret void - // CHECK-LABEL: define internal void @__Block_byref_object_copy_.{{[0-9]+}}(i8* noundef %0, i8* noundef %1) #{{[0-9]+}} { + // CHECK-LABEL: define internal void @__Block_byref_object_copy_.{{[0-9]+}}(i8* %0, i8* %1) #{{[0-9]+}} { // CHECK: [[T0:%.*]] = getelementptr inbounds [[BYREF_T]], [[BYREF_T]]* {{%.*}}, i32 0, i32 6 // CHECK-NEXT: load i8*, i8** // CHECK-NEXT: bitcast i8* {{%.*}} to [[BYREF_T]]* // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[BYREF_T]], [[BYREF_T]]* {{%.*}}, i32 0, i32 6 // CHECK-NEXT: call void @llvm.objc.moveWeak(i8** [[T0]], i8** [[T1]]) - // CHECK-LABEL: define internal void @__Block_byref_object_dispose_.{{[0-9]+}}(i8* noundef %0) #{{[0-9]+}} { + // CHECK-LABEL: define internal void @__Block_byref_object_dispose_.{{[0-9]+}}(i8* %0) #{{[0-9]+}} { // CHECK: [[T0:%.*]] = getelementptr inbounds [[BYREF_T]], [[BYREF_T]]* {{%.*}}, i32 0, i32 6 // CHECK-NEXT: call void @llvm.objc.destroyWeak(i8** [[T0]]) @@ -273,16 +273,16 @@ void test7(void) { // CHECK-LABEL: define internal void @__test7_block_invoke // CHECK: [[SLOT:%.*]] = getelementptr inbounds [[BLOCK_T]], [[BLOCK_T]]* {{%.*}}, i32 0, i32 5 // CHECK-NEXT: [[T0:%.*]] = call i8* @llvm.objc.loadWeakRetained(i8** [[SLOT]]) - // CHECK-NEXT: call void @test7_consume(i8* noundef [[T0]]) + // CHECK-NEXT: call void @test7_consume(i8* [[T0]]) // CHECK-NEXT: call void @llvm.objc.release(i8* [[T0]]) // CHECK: ret void - // CHECK-LABEL: define linkonce_odr hidden void @__copy_helper_block_8_32w(i8* noundef %0, i8* noundef %1) unnamed_addr #{{[0-9]+}} { + // CHECK-LABEL: define linkonce_odr hidden void @__copy_helper_block_8_32w(i8* %0, i8* %1) unnamed_addr #{{[0-9]+}} { // CHECK: getelementptr // CHECK-NEXT: getelementptr // CHECK-NEXT: call void @llvm.objc.copyWeak( - // CHECK-LABEL: define linkonce_odr hidden void @__destroy_helper_block_8_32w(i8* noundef %0) unnamed_addr #{{[0-9]+}} { + // CHECK-LABEL: define linkonce_odr hidden void @__destroy_helper_block_8_32w(i8* %0) unnamed_addr #{{[0-9]+}} { // CHECK: getelementptr // CHECK-NEXT: call void @llvm.objc.destroyWeak( } @@ -372,7 +372,7 @@ void test10a(void) { // We can also use _Block_object_assign/destroy with // BLOCK_FIELD_IS_BLOCK as long as we don't pass BLOCK_BYREF_CALLER. -// CHECK-LABEL: define internal void @__Block_byref_object_copy_.{{[0-9]+}}(i8* noundef %0, i8* noundef %1) #{{[0-9]+}} { +// CHECK-LABEL: define internal void @__Block_byref_object_copy_.{{[0-9]+}}(i8* %0, i8* %1) #{{[0-9]+}} { // CHECK: [[D0:%.*]] = load i8*, i8** {{%.*}} // CHECK-NEXT: [[D1:%.*]] = bitcast i8* [[D0]] to [[BYREF_T]]* // CHECK-NEXT: [[D2:%.*]] = getelementptr inbounds [[BYREF_T]], [[BYREF_T]]* [[D1]], i32 0, i32 6 @@ -386,7 +386,7 @@ void test10a(void) { // CHECK-NEXT: store void ()* [[T3]], void ()** [[D2]], align 8 // CHECK: ret void -// CHECK-LABEL: define internal void @__Block_byref_object_dispose_.{{[0-9]+}}(i8* noundef %0) #{{[0-9]+}} { +// CHECK-LABEL: define internal void @__Block_byref_object_dispose_.{{[0-9]+}}(i8* %0) #{{[0-9]+}} { // CHECK: [[T0:%.*]] = load i8*, i8** {{%.*}} // CHECK-NEXT: [[T1:%.*]] = bitcast i8* [[T0]] to [[BYREF_T]]* // CHECK-NEXT: [[T2:%.*]] = getelementptr inbounds [[BYREF_T]], [[BYREF_T]]* [[T1]], i32 0, i32 6 @@ -448,7 +448,7 @@ void test11a(void) { // CHECK-NEXT: [[T2:%.*]] = call i8* @llvm.objc.retainBlock(i8* [[T1]]) // CHECK-NEXT: [[T3:%.*]] = bitcast i8* [[T2]] to void ()* // CHECK-NEXT: [[T4:%.*]] = bitcast void ()* [[T3]] to i8* - // CHECK-NEXT: call void @test11_helper(i8* noundef [[T4]]) + // CHECK-NEXT: call void @test11_helper(i8* [[T4]]) // CHECK-NEXT: [[T5:%.*]] = bitcast void ()* [[T3]] to i8* // CHECK-NEXT: call void @llvm.objc.release(i8* [[T5]]) // CHECK: ret void @@ -480,16 +480,16 @@ void test11b(void) { @implementation Test12 @synthesize ablock, nblock; // CHECK: define internal void ()* @"\01-[Test12 ablock]"( -// CHECK: call i8* @objc_getProperty(i8* noundef {{%.*}}, i8* noundef {{%.*}}, i64 noundef {{%.*}}, i1 noundef zeroext true) +// CHECK: call i8* @objc_getProperty(i8* {{%.*}}, i8* {{%.*}}, i64 {{%.*}}, i1 zeroext true) // CHECK: define internal void @"\01-[Test12 setAblock:]"( -// CHECK: call void @objc_setProperty(i8* noundef {{%.*}}, i8* noundef {{%.*}}, i64 noundef {{%.*}}, i8* noundef {{%.*}}, i1 noundef zeroext true, i1 noundef zeroext true) +// CHECK: call void @objc_setProperty(i8* {{%.*}}, i8* {{%.*}}, i64 {{%.*}}, i8* {{%.*}}, i1 zeroext true, i1 zeroext true) // CHECK: define internal void ()* @"\01-[Test12 nblock]"( // CHECK: %add.ptr = getelementptr inbounds i8, i8* %1, i64 %ivar // CHECK: define internal void @"\01-[Test12 setNblock:]"( -// CHECK: call void @objc_setProperty(i8* noundef {{%.*}}, i8* noundef {{%.*}}, i64 noundef {{%.*}}, i8* noundef {{%.*}}, i1 noundef zeroext false, i1 noundef zeroext true) +// CHECK: call void @objc_setProperty(i8* {{%.*}}, i8* {{%.*}}, i64 {{%.*}}, i8* {{%.*}}, i1 zeroext false, i1 zeroext true) @end // rdar://problem/10131784 @@ -531,7 +531,7 @@ void test13(id x) { // CHECK-NEXT: [[T3:%.*]] = bitcast i8* [[T2]] to void ()* // CHECK-NEXT: store void ()* [[T3]], void ()** [[B]], align 8 // CHECK-NEXT: [[T0:%.*]] = load void ()*, void ()** [[B]], align 8 - // CHECK-NEXT: call void @test13_use(void ()* noundef [[T0]]) + // CHECK-NEXT: call void @test13_use(void ()* [[T0]]) // CHECK-NEXT: [[T0:%.*]] = load void ()*, void ()** [[B]] // CHECK-NEXT: [[T1:%.*]] = bitcast void ()* [[T0]] to i8* // CHECK-NEXT: call void @llvm.objc.release(i8* [[T1]]) @@ -683,7 +683,7 @@ void test19(void (^b)(void)) { // CHECK-NEXT: store void ()* [[T3]], void ()** [[SLOT]], // Call. // CHECK-NEXT: [[T0:%.*]] = bitcast [[BLOCK_T]]* [[BLOCK]] to void (i32)* -// CHECK-NEXT: call void @test19_sink(void (i32)* noundef [[T0]]) +// CHECK-NEXT: call void @test19_sink(void (i32)* [[T0]]) test19_sink(^(int x) { b(); }); @@ -731,7 +731,7 @@ void test20(const id x) { // CHECK-LABEL: define{{.*}} void @test21( // CHECK: %[[V6:.*]] = call i8* @llvm.objc.retainBlock( // CHECK: %[[V7:.*]] = bitcast i8* %[[V6]] to void ()* -// CHECK: call void (i32, ...) @test21_callee(i32 noundef 1, void ()* noundef %[[V7]]), +// CHECK: call void (i32, ...) @test21_callee(i32 1, void ()* %[[V7]]), void test21_callee(int n, ...); void test21(id x) { @@ -763,7 +763,7 @@ id test22(int c, id x) { // CHECK-COMMON-LABEL: define{{.*}} void @test23( // CHECK-COMMON: %[[V9:.*]] = call i8* @llvm.objc.retainBlock( // CHECK-COMMON: %[[V10:.*]] = bitcast i8* %[[V9]] to void ()* -// CHECK-COMMON: call void (i8*, i8*, i32, ...) bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i32, ...)*)(i8* noundef %{{.*}}, i8* noundef %{{.*}}, i32 noundef 123, void ()* noundef %[[V10]]) +// CHECK-COMMON: call void (i8*, i8*, i32, ...) bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i32, ...)*)(i8* %{{.*}}, i8* %{{.*}}, i32 123, void ()* %[[V10]]) void test23(id x, Test23 *t) { [t m:123, ^{ (void)x; }]; diff --git a/clang/test/CodeGenObjC/arc-foreach.m b/clang/test/CodeGenObjC/arc-foreach.m index 441b134fc2c036004d3c9dd514dc9683b9a0bf3a..a7274b991a89f7e338a10cd9216f1b36348f55aa 100644 --- a/clang/test/CodeGenObjC/arc-foreach.m +++ b/clang/test/CodeGenObjC/arc-foreach.m @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-apple-darwin -fblocks -fobjc-arc -fobjc-runtime-has-weak -emit-llvm %s -o - | FileCheck -check-prefix CHECK-LP64 %s -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-apple-darwin -O1 -fblocks -fobjc-arc -fobjc-runtime-has-weak -emit-llvm %s -o - | FileCheck -check-prefix CHECK-LP64-OPT %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin -fblocks -fobjc-arc -fobjc-runtime-has-weak -emit-llvm %s -o - | FileCheck -check-prefix CHECK-LP64 %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -fblocks -fobjc-arc -fobjc-runtime-has-weak -emit-llvm %s -o - | FileCheck -check-prefix CHECK-LP64-OPT %s // rdar://9503326 // rdar://9606600 diff --git a/clang/test/CodeGenObjC/arc-literals.m b/clang/test/CodeGenObjC/arc-literals.m index fa76ea18438259fa3696723bac06929aa75b292d..a42c4b18f5c82be558e3a2a1d0d46b5bfd1cf0a9 100644 --- a/clang/test/CodeGenObjC/arc-literals.m +++ b/clang/test/CodeGenObjC/arc-literals.m @@ -14,16 +14,16 @@ // CHECK-LABEL: define{{.*}} void @test_numeric() void test_numeric() { - // CHECK: {{call.*objc_msgSend.*i32 noundef 17}} + // CHECK: {{call.*objc_msgSend.*i32 17}} // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue id ilit = @17; - // CHECK: {{call.*objc_msgSend.*i32 noundef 25}} + // CHECK: {{call.*objc_msgSend.*i32 25}} // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue id ulit = @25u; - // CHECK: {{call.*objc_msgSend.*i64 noundef 42}} + // CHECK: {{call.*objc_msgSend.*i64 42}} // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue id ulllit = @42ull; - // CHECK: {{call.*objc_msgSend.*i8 noundef signext 97}} + // CHECK: {{call.*objc_msgSend.*i8 signext 97}} // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue id charlit = @'a'; // CHECK: call void @llvm.objc.release @@ -58,7 +58,7 @@ void test_array(id a, id b) { // CHECK-NEXT: [[SEL:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES // CHECK-NEXT: [[T1:%.*]] = bitcast [[CLASS_T]]* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [2 x i8*]* [[OBJECTS]] to i8** - // CHECK-NEXT: [[T3:%.*]] = call i8* bitcast ({{.*@objc_msgSend.*}})(i8* noundef [[T1]], i8* noundef [[SEL]], i8** noundef [[T2]], i64 noundef 2) + // CHECK-NEXT: [[T3:%.*]] = call i8* bitcast ({{.*@objc_msgSend.*}})(i8* [[T1]], i8* [[SEL]], i8** [[T2]], i64 2) // CHECK-NEXT: [[T4:%.*]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[T3]]) // CHECK: call void (...) @llvm.objc.clang.arc.use(i8* [[V0]], i8* [[V1]]) id arr = @[a, b]; @@ -102,7 +102,7 @@ void test_dictionary(id k1, id o1, id k2, id o2) { // CHECK-NEXT: [[T1:%.*]] = bitcast [[CLASS_T]]* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [2 x i8*]* [[OBJECTS]] to i8** // CHECK-NEXT: [[T3:%.*]] = bitcast [2 x i8*]* [[KEYS]] to i8** - // CHECK-NEXT: [[T4:%.*]] = call i8* bitcast ({{.*@objc_msgSend.*}})(i8* noundef [[T1]], i8* noundef [[SEL]], i8** noundef [[T2]], i8** noundef [[T3]], i64 noundef 2) + // CHECK-NEXT: [[T4:%.*]] = call i8* bitcast ({{.*@objc_msgSend.*}})(i8* [[T1]], i8* [[SEL]], i8** [[T2]], i8** [[T3]], i64 2) // CHECK-NEXT: [[T5:%.*]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[T4]]) // CHECK-NEXT: call void (...) @llvm.objc.clang.arc.use(i8* [[V0]], i8* [[V1]], i8* [[V2]], i8* [[V3]]) @@ -133,7 +133,7 @@ void test_property(B *b) { // Invoke 'prop' // CHECK: [[SEL:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES // CHECK-NEXT: [[T1:%.*]] = bitcast - // CHECK-NEXT: [[T2:%.*]] = call [[B:%.*]]* bitcast ({{.*}} @objc_msgSend to {{.*}})(i8* noundef [[T1]], i8* noundef [[SEL]]) + // CHECK-NEXT: [[T2:%.*]] = call [[B:%.*]]* bitcast ({{.*}} @objc_msgSend to {{.*}})(i8* [[T1]], i8* [[SEL]]) // CHECK-NEXT: [[T3:%.*]] = bitcast [[B]]* [[T2]] to i8* // CHECK-NEXT: [[T4:%.*]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[T3]]) // CHECK-NEXT: [[V0:%.*]] = bitcast i8* [[T4]] to [[B]]* @@ -147,7 +147,7 @@ void test_property(B *b) { // CHECK-NEXT: [[SEL:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES // CHECK-NEXT: [[T1:%.*]] = bitcast [[CLASS_T]]* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [1 x i8*]* [[OBJECTS]] to i8** - // CHECK-NEXT: [[T3:%.*]] = call i8* bitcast ({{.*}} @objc_msgSend to {{.*}}(i8* noundef [[T1]], i8* noundef [[SEL]], i8** noundef [[T2]], i64 noundef 1) + // CHECK-NEXT: [[T3:%.*]] = call i8* bitcast ({{.*}} @objc_msgSend to {{.*}}(i8* [[T1]], i8* [[SEL]], i8** [[T2]], i64 1) // CHECK-NEXT: call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[T3]]) // CHECK-NEXT: call void (...) @llvm.objc.clang.arc.use(i8* [[V1]]) // CHECK-NEXT: bitcast diff --git a/clang/test/CodeGenObjC/arc-no-arc-exceptions.m b/clang/test/CodeGenObjC/arc-no-arc-exceptions.m index 62715f11e77f4a3caed8def0adcdaab3dde59daa..07b41e8145d733c13e3a2c335fb41f3d0130d462 100644 --- a/clang/test/CodeGenObjC/arc-no-arc-exceptions.m +++ b/clang/test/CodeGenObjC/arc-no-arc-exceptions.m @@ -34,7 +34,7 @@ void test1(id x) { void NSLog(id, ...); // CHECK-LABEL: define{{.*}} void @test2( -// CHECK: invoke void (i8*, ...) @NSLog(i8* noundef bitcast (%struct.__NSConstantString_tag* @_unnamed_cfstring_ to i8*), i32* noundef %{{.*}}) +// CHECK: invoke void (i8*, ...) @NSLog(i8* bitcast (%struct.__NSConstantString_tag* @_unnamed_cfstring_ to i8*), i32* %{{.*}}) // CHECK: to label %{{.*}} unwind label %{{.*}}, !clang.arc.no_objc_arc_exceptions ! // NO-METADATA-LABEL: define{{.*}} void @test2( // NO-METADATA-NOT: !clang.arc.no_objc_arc_exceptions @@ -48,7 +48,7 @@ void test2(void) { } // CHECK-LABEL: define{{.*}} void @test3( -// CHECK: invoke void %{{.*}}(i8* noundef %{{.*}}) +// CHECK: invoke void %{{.*}}(i8* %{{.*}}) // CHECK: to label %{{.*}} unwind label %{{.*}}, !clang.arc.no_objc_arc_exceptions ! // NO-METADATA-LABEL: define{{.*}} void @test3( // NO-METADATA-NOT: !clang.arc.no_objc_arc_exceptions @@ -63,7 +63,7 @@ void test3(void) { } // CHECK-LABEL: define{{.*}} void @test4( -// CHECK: invoke void %{{.*}}(i8* noundef %{{.*}}) +// CHECK: invoke void %{{.*}}(i8* %{{.*}}) // CHECK: to label %{{.*}} unwind label %{{.*}}, !clang.arc.no_objc_arc_exceptions ! // NO-METADATA-LABEL: define{{.*}} void @test4( // NO-METADATA-NOT: !clang.arc.no_objc_arc_exceptions diff --git a/clang/test/CodeGenObjC/arc-precise-lifetime.m b/clang/test/CodeGenObjC/arc-precise-lifetime.m index 0ec8aab5a7fa696eb64e2e690c3ec42211f9054c..c1bad4bf562176f17afed9f5ae143eb2f8aeb3e3 100644 --- a/clang/test/CodeGenObjC/arc-precise-lifetime.m +++ b/clang/test/CodeGenObjC/arc-precise-lifetime.m @@ -247,7 +247,7 @@ void test1d_message(void) { // CHECK-NEXT: [[T0:%.*]] = load [[TEST1]]*, [[TEST1]]** // CHECK-NEXT: [[SEVEN:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: [[EIGHT:%.*]] = bitcast [[TEST1]]* [[T0]] to i8* - // CHECK-NEXT: [[CALL1:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* noundef [[EIGHT]], i8* noundef [[SEVEN]]) + // CHECK-NEXT: [[CALL1:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* [[EIGHT]], i8* [[SEVEN]]) // CHECK-NEXT: store i8* [[CALL1]], i8** // CHECK-NEXT: [[PCPTR2:%.*]] = bitcast i8** [[PC]] to i8* // CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[PCPTR2]]) @@ -277,7 +277,7 @@ void test1d_property(void) { // CHECK-NEXT: [[T0:%.*]] = load [[TEST1]]*, [[TEST1]]** // CHECK-NEXT: [[SEVEN:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: [[EIGHT:%.*]] = bitcast [[TEST1]]* [[T0]] to i8* - // CHECK-NEXT: [[CALL1:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* noundef [[EIGHT]], i8* noundef [[SEVEN]]) + // CHECK-NEXT: [[CALL1:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* [[EIGHT]], i8* [[SEVEN]]) // CHECK-NEXT: store i8* [[CALL1]], i8** // CHECK-NEXT: [[PCPTR2:%.*]] = bitcast i8** [[PC]] to i8* // CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[PCPTR2]]) diff --git a/clang/test/CodeGenObjC/arc-property.m b/clang/test/CodeGenObjC/arc-property.m index 5c33eaffcb6348ace3f587dcb3ca37702c4cbe64..4e525cc5cf7d7522e05d62e432bf4bd376bc70c8 100644 --- a/clang/test/CodeGenObjC/arc-property.m +++ b/clang/test/CodeGenObjC/arc-property.m @@ -36,7 +36,7 @@ struct S1 { Class isa; }; // CHECK-NEXT: [[OFFSET:%.*]] = load i64, i64* @"OBJC_IVAR_$_Test1.pointer" // CHECK-NEXT: [[T1:%.*]] = load [[S1]]*, [[S1]]** {{%.*}} // CHECK-NEXT: [[T2:%.*]] = bitcast [[S1]]* [[T1]] to i8* -// CHECK-NEXT: call void @objc_setProperty(i8* noundef [[T0]], i8* noundef {{%.*}}, i64 noundef [[OFFSET]], i8* noundef [[T2]], i1 noundef zeroext false, i1 noundef zeroext false) +// CHECK-NEXT: call void @objc_setProperty(i8* [[T0]], i8* {{%.*}}, i64 [[OFFSET]], i8* [[T2]], i1 zeroext false, i1 zeroext false) // CHECK-NEXT: ret void @@ -67,14 +67,14 @@ static Class theGlobalClass; // CHECK: define internal i8* @"\01-[Test2 theClass]"( // CHECK: [[OFFSET:%.*]] = load i64, i64* @"OBJC_IVAR_$_Test2._theClass" -// CHECK-NEXT: [[T0:%.*]] = tail call i8* @objc_getProperty(i8* noundef {{.*}}, i8* noundef {{.*}}, i64 noundef [[OFFSET]], i1 noundef zeroext true) +// CHECK-NEXT: [[T0:%.*]] = tail call i8* @objc_getProperty(i8* {{.*}}, i8* {{.*}}, i64 [[OFFSET]], i1 zeroext true) // CHECK-NEXT: ret i8* [[T0]] // CHECK: define internal void @"\01-[Test2 setTheClass:]"( // CHECK: [[T0:%.*]] = bitcast [[TEST2]]* {{%.*}} to i8* // CHECK-NEXT: [[OFFSET:%.*]] = load i64, i64* @"OBJC_IVAR_$_Test2._theClass" // CHECK-NEXT: [[T1:%.*]] = load i8*, i8** {{%.*}} -// CHECK-NEXT: call void @objc_setProperty(i8* noundef [[T0]], i8* noundef {{%.*}}, i64 noundef [[OFFSET]], i8* noundef [[T1]], i1 noundef zeroext true, i1 noundef zeroext true) +// CHECK-NEXT: call void @objc_setProperty(i8* [[T0]], i8* {{%.*}}, i64 [[OFFSET]], i8* [[T1]], i1 zeroext true, i1 zeroext true) // CHECK-NEXT: ret void // CHECK: define internal void @"\01-[Test2 .cxx_destruct]"( @@ -103,13 +103,13 @@ void test3(Test3 *t) { // CHECK: [[T0:%.*]] = load [[TEST3]]*, [[TEST3]]** [[T]], // CHECK-NEXT: [[SEL:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES // CHECK-NEXT: [[T1:%.*]] = bitcast [[TEST3]]* [[T0]] to i8* -// CHECK-NEXT: [[T2:%.*]] = call i8* bitcast ({{.*}} @objc_msgSend to {{.*}})(i8* noundef [[T1]], i8* noundef [[SEL]]) +// CHECK-NEXT: [[T2:%.*]] = call i8* bitcast ({{.*}} @objc_msgSend to {{.*}})(i8* [[T1]], i8* [[SEL]]) // CHECK-NEXT: store i8* [[T2]], i8** [[X]], // Message send. // CHECK-NEXT: [[T0:%.*]] = load [[TEST3]]*, [[TEST3]]** [[T]], // CHECK-NEXT: [[SEL:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES // CHECK-NEXT: [[T1:%.*]] = bitcast [[TEST3]]* [[T0]] to i8* -// CHECK-NEXT: [[T2:%.*]] = call i8* bitcast ({{.*}} @objc_msgSend to {{.*}})(i8* noundef [[T1]], i8* noundef [[SEL]]) +// CHECK-NEXT: [[T2:%.*]] = call i8* bitcast ({{.*}} @objc_msgSend to {{.*}})(i8* [[T1]], i8* [[SEL]]) // CHECK-NEXT: [[T3:%.*]] = load i8*, i8** [[X]], // CHECK-NEXT: store i8* [[T2]], i8** [[X]], // CHECK-NEXT: call void @llvm.objc.release(i8* [[T3]]) diff --git a/clang/test/CodeGenObjC/arc-ternary-op.m b/clang/test/CodeGenObjC/arc-ternary-op.m index 7a963c290a827b8e32a20eeabb1e8912a12604e4..c75f5d9b63b50516fe756cc991687c73f99384c2 100644 --- a/clang/test/CodeGenObjC/arc-ternary-op.m +++ b/clang/test/CodeGenObjC/arc-ternary-op.m @@ -72,7 +72,7 @@ void test1(int cond) { // CHECK-NEXT: store i8* [[T0]], i8** [[TEMP1]] // CHECK-NEXT: br label // CHECK: [[W:%.*]] = phi i8* [ [[T0]], {{%.*}} ], [ undef, {{%.*}} ] - // CHECK-NEXT: call void @test1_sink(i8** noundef [[T1]]) + // CHECK-NEXT: call void @test1_sink(i8** [[T1]]) // CHECK-NEXT: [[T0:%.*]] = icmp eq i8** [[ARG]], null // CHECK-NEXT: br i1 [[T0]], // CHECK: [[T0:%.*]] = load i8*, i8** [[TEMP1]] @@ -95,7 +95,7 @@ void test1(int cond) { // CHECK-NEXT: store i1 true, i1* [[CONDCLEANUP]] // CHECK-NEXT: store i8* [[T0]], i8** [[TEMP2]] // CHECK-NEXT: br label - // CHECK: call void @test1_sink(i8** noundef [[T1]]) + // CHECK: call void @test1_sink(i8** [[T1]]) // CHECK-NEXT: [[T0:%.*]] = icmp eq i8** [[ARG]], null // CHECK-NEXT: br i1 [[T0]], // CHECK: [[T0:%.*]] = load i8*, i8** [[TEMP2]] diff --git a/clang/test/CodeGenObjC/arc.m b/clang/test/CodeGenObjC/arc.m index effdef88986963315087583ad9ee5bce9c7f1607..c335e76e0399a43c53908d99d7d55bbd7daac869 100644 --- a/clang/test/CodeGenObjC/arc.m +++ b/clang/test/CodeGenObjC/arc.m @@ -119,7 +119,7 @@ void test3_unelided() { // CHECK-NEXT: [[T0:%.*]] = load [[TEST3]]*, [[TEST3]]** [[X]] // CHECK-NEXT: load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: [[T1:%.*]] = bitcast [[TEST3]]* [[T0]] to i8* - // CHECK-NEXT: [[COPY:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend {{.*}})(i8* noundef [[T1]], + // CHECK-NEXT: [[COPY:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend {{.*}})(i8* [[T1]], // CHECK-NEXT: call void @llvm.objc.release(i8* [[COPY]]) [[NUW:#[0-9]+]] [x copy]; @@ -158,7 +158,7 @@ void test3() { // Call to -copy. // CHECK-NEXT: [[V:%.*]] = load i8*, i8** [[X]] // CHECK-NEXT: load i8*, i8** @OBJC_SELECTOR_REFERENCES_ - // CHECK-NEXT: [[COPY:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend {{.*}})(i8* noundef [[V]], + // CHECK-NEXT: [[COPY:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend {{.*}})(i8* [[V]], // Assignment to x. // CHECK-NEXT: [[TMP:%.*]] = load i8*, i8** [[X]] @@ -187,7 +187,7 @@ id test4() { // Call to -initWith: with elided retain of consumed argument. // CHECK-NEXT: load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: [[ALLOC:%.*]] = bitcast - // CHECK-NEXT: [[INIT:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*, i32)*)(i8* noundef [[ALLOC]], + // CHECK-NEXT: [[INIT:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*, i32)*)(i8* [[ALLOC]], // Initialization of return value, occurring within full-expression. // Retain/release elided. @@ -274,7 +274,7 @@ void test7() { // CHECK-NEXT: store i8* null, i8** [[X]] // CHECK-NEXT: [[T0:%.*]] = load i8*, i8** [[X]] // CHECK-NEXT: [[T1:%.*]] = call i8* @llvm.objc.retain(i8* [[T0]]) [[NUW]] - // CHECK-NEXT: call void @test7_helper(i8* noundef [[T1]]) + // CHECK-NEXT: call void @test7_helper(i8* [[T1]]) // CHECK-NEXT: [[T1:%.*]] = load i8*, i8** [[X]] // CHECK-NEXT: call void @llvm.objc.release(i8* [[T1]]) [[NUW]], !clang.imprecise_release // CHECK-NEXT: [[XPTR2:%.*]] = bitcast i8** [[X]] to i8* @@ -411,7 +411,7 @@ void test13(void) { // CHECK-NEXT: [[FN:%.*]] = load void (i8*)*, void (i8*)** @test13_func, align // CHECK-NEXT: [[X_VAL:%.*]] = load i8*, i8** [[X]], align // CHECK-NEXT: [[X_TMP:%.*]] = call i8* @llvm.objc.retain(i8* [[X_VAL]]) [[NUW]] - // CHECK-NEXT: call void [[FN]](i8* noundef [[X_TMP]]) + // CHECK-NEXT: call void [[FN]](i8* [[X_TMP]]) test13_func(x); extern fnty ^test13_block; @@ -423,7 +423,7 @@ void test13(void) { // CHECK-NEXT: [[X_TMP:%.*]] = call i8* @llvm.objc.retain(i8* [[X_VAL]]) [[NUW]] // CHECK-NEXT: [[BLOCK_FN_TMP:%.*]] = load i8*, i8** [[BLOCK_FN_PTR]] // CHECK-NEXT: [[BLOCK_FN:%.*]] = bitcast i8* [[BLOCK_FN_TMP]] to void (i8*, i8*)* - // CHECK-NEXT: call void [[BLOCK_FN]](i8* noundef [[BLOCK_OPAQUE]], i8* noundef [[X_TMP]]) + // CHECK-NEXT: call void [[BLOCK_FN]](i8* [[BLOCK_OPAQUE]], i8* [[X_TMP]]) test13_block(x); // CHECK-NEXT: [[T0:%.*]] = load i8*, i8** [[X]] @@ -710,7 +710,7 @@ void test21(unsigned n) { @implementation Test29 static id _test29_allocator = 0; - (id) init { -// CHECK: define internal i8* @"\01-[Test29 init]"([[TEST29:%[^*]*]]* noundef {{%.*}}, +// CHECK: define internal i8* @"\01-[Test29 init]"([[TEST29:%[^*]*]]* {{%.*}}, // CHECK: [[SELF:%.*]] = alloca [[TEST29]]*, align 8 // CHECK-NEXT: [[CMD:%.*]] = alloca i8*, align 8 // CHECK-NEXT: store [[TEST29]]* {{%.*}}, [[TEST29]]** [[SELF]] @@ -727,7 +727,7 @@ static id _test29_allocator = 0; // Actual message send. // CHECK-NEXT: [[T2:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: [[T3:%.*]] = bitcast [[TEST29]]* [[T0]] to i8* -// CHECK-NEXT: [[CALL:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*, i8*)*)(i8* noundef [[T3]], i8* noundef [[T2]], i8* noundef [[T1]]) +// CHECK-NEXT: [[CALL:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*, i8*)*)(i8* [[T3]], i8* [[T2]], i8* [[T1]]) // Implicit write of result back into 'self'. This is not supposed to // be detectable because we're supposed to ban accesses to the old @@ -820,7 +820,7 @@ typedef struct Test30_helper Test30_helper; char *helper; } - (id) init { -// CHECK: define internal i8* @"\01-[Test30 init]"([[TEST30:%[^*]*]]* noundef {{%.*}}, +// CHECK: define internal i8* @"\01-[Test30 init]"([[TEST30:%[^*]*]]* {{%.*}}, // CHECK: [[RET:%.*]] = alloca [[TEST30]]* // CHECK-NEXT: alloca i8* // CHECK-NEXT: store [[TEST30]]* {{%.*}}, [[TEST30]]** [[SELF]] @@ -830,7 +830,7 @@ char *helper; // CHECK-NEXT: [[T0:%.*]] = load [[TEST30]]*, [[TEST30]]** [[SELF]] // CHECK-NEXT: [[T1:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: [[T2:%.*]] = bitcast [[TEST30]]* [[T0]] to i8* -// CHECK-NEXT: [[CALL:%.*]] = call [[TEST30_HELPER:%.*]]* bitcast {{.*}} @objc_msgSend {{.*}}(i8* noundef [[T2]], i8* noundef [[T1]]) +// CHECK-NEXT: [[CALL:%.*]] = call [[TEST30_HELPER:%.*]]* bitcast {{.*}} @objc_msgSend {{.*}}(i8* [[T2]], i8* [[T1]]) // Assignment. // CHECK-NEXT: [[T0:%.*]] = bitcast [[TEST30_HELPER]]* [[CALL]] to i8* @@ -917,7 +917,7 @@ void test33(Test33 *ptr) { // CHECK-NEXT: store [[A_T]]* [[W0]], [[A_T]]** [[TEMP0]] // CHECK-NEXT: load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: bitcast - // CHECK-NEXT: objc_msgSend{{.*}}, [[A_T]]** noundef [[TEMP0]]) + // CHECK-NEXT: objc_msgSend{{.*}}, [[A_T]]** [[TEMP0]]) // CHECK-NEXT: [[T0:%.*]] = load [[A_T]]*, [[A_T]]** [[TEMP0]] // CHECK-NEXT: [[T1:%.*]] = bitcast [[A_T]]* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = call i8* @llvm.objc.retain(i8* [[T1]]) @@ -933,7 +933,7 @@ void test33(Test33 *ptr) { // CHECK-NEXT: store [[A_T]]* [[W0]], [[A_T]]** [[TEMP1]] // CHECK-NEXT: load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: bitcast - // CHECK-NEXT: objc_msgSend{{.*}}, [[A_T]]** noundef [[TEMP1]]) + // CHECK-NEXT: objc_msgSend{{.*}}, [[A_T]]** [[TEMP1]]) // CHECK-NEXT: [[T0:%.*]] = load [[A_T]]*, [[A_T]]** [[TEMP1]] // CHECK-NEXT: [[T1:%.*]] = bitcast [[A_T]]* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = call i8* @llvm.objc.retain(i8* [[T1]]) @@ -947,19 +947,19 @@ void test33(Test33 *ptr) { // CHECK-NEXT: load [[TEST33]]*, [[TEST33]]** [[PTR]] // CHECK-NEXT: load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: bitcast - // CHECK-NEXT: objc_msgSend{{.*}}, [[A_T]]** noundef [[A]]) + // CHECK-NEXT: objc_msgSend{{.*}}, [[A_T]]** [[A]]) // CHECK-NEXT: load [[TEST33]]*, [[TEST33]]** [[PTR]] // CHECK-NEXT: load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: bitcast - // CHECK-NEXT: objc_msgSend{{.*}}, [[A_T]]** noundef [[A]]) + // CHECK-NEXT: objc_msgSend{{.*}}, [[A_T]]** [[A]]) // 'out' // CHECK-NEXT: load [[TEST33]]*, [[TEST33]]** [[PTR]] // CHECK-NEXT: store [[A_T]]* null, [[A_T]]** [[TEMP2]] // CHECK-NEXT: load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: bitcast - // CHECK-NEXT: objc_msgSend{{.*}}, [[A_T]]** noundef [[TEMP2]]) + // CHECK-NEXT: objc_msgSend{{.*}}, [[A_T]]** [[TEMP2]]) // CHECK-NEXT: [[T0:%.*]] = load [[A_T]]*, [[A_T]]** [[TEMP2]] // CHECK-NEXT: [[T1:%.*]] = bitcast [[A_T]]* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = call i8* @llvm.objc.retain(i8* [[T1]]) @@ -1019,7 +1019,7 @@ void test37(void) { // CHECK-NEXT: [[W0:%.*]] = load [[TEST37]]*, [[TEST37]]** [[VAR]] // CHECK-NEXT: [[W1:%.*]] = bitcast [[TEST37]]* [[W0]] to i8* // CHECK-NEXT: store i8* [[W1]], i8** [[TEMP]] - // CHECK-NEXT: call void @test37_helper(i8** noundef [[TEMP]]) + // CHECK-NEXT: call void @test37_helper(i8** [[TEMP]]) // CHECK-NEXT: [[T0:%.*]] = load i8*, i8** [[TEMP]] // CHECK-NEXT: [[T1:%.*]] = bitcast i8* [[T0]] to [[TEST37]]* // CHECK-NEXT: [[T2:%.*]] = bitcast [[TEST37]]* [[T1]] to i8* @@ -1185,7 +1185,7 @@ id test52(void) { // CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[XPTR1]]) // CHECK-NEXT: store i32 5, i32* [[X]], // CHECK-NEXT: [[T0:%.*]] = load i32, i32* [[X]], -// CHECK-NEXT: [[T1:%.*]] = call i8* @test52_helper(i32 noundef [[T0]]) +// CHECK-NEXT: [[T1:%.*]] = call i8* @test52_helper(i32 [[T0]]) // CHECK-NEXT: store i8* [[T1]], i8** [[TMPALLOCA]] // CHECK-NEXT: [[XPTR2:%.*]] = bitcast i32* [[X]] to i8* // CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[XPTR2]]) @@ -1228,7 +1228,7 @@ void test53(void) { } // -// CHECK-LABEL: define{{.*}} void @test54(i32 noundef %first, ...) +// CHECK-LABEL: define{{.*}} void @test54(i32 %first, ...) void test54(int first, ...) { __builtin_va_list arglist; // CHECK: call void @llvm.va_start @@ -1353,7 +1353,7 @@ void test61(void) { // CHECK-NEXT: [[T1:%.*]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[T0]]) // CHECK-NEXT: [[T2:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: [[T3:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_ - // CHECK-NEXT: [[T4:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*, i8*)*)(i8* noundef [[T1]], i8* noundef [[T3]], i8* noundef [[T2]]) + // CHECK-NEXT: [[T4:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*, i8*)*)(i8* [[T1]], i8* [[T3]], i8* [[T2]]) // CHECK-NEXT: call void @llvm.objc.release(i8* [[T1]]) [test61_make() performSelector: @selector(test61_void)]; @@ -1363,7 +1363,7 @@ void test61(void) { // CHECK-NEXT: [[T1:%.*]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[T0]]) // CHECK-NEXT: [[T2:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: [[T3:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_ - // CHECK-NEXT: [[T4:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*, i8*)*)(i8* noundef [[T1]], i8* noundef [[T3]], i8* noundef [[T2]]) + // CHECK-NEXT: [[T4:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*, i8*)*)(i8* [[T1]], i8* [[T3]], i8* [[T2]]) // CHECK-NEXT: [[T5:%.*]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[T4]]) // CHECK-NEXT: store i8* [[T5]], i8** [[Y]] // CHECK-NEXT: call void @llvm.objc.release(i8* [[T1]]) @@ -1463,7 +1463,7 @@ void test66(void) { // CHECK-NEXT: [[T7:%.*]] = bitcast [[TEST66]]* [[T3]] to i8* // CHECK-NEXT: [[SIX:%.*]] = icmp eq i8* [[T7]], null // CHECK-NEXT: br i1 [[SIX]], label [[NULINIT:%.*]], label [[CALL:%.*]] -// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i8*)*)(i8* noundef [[T7]], i8* noundef [[T6]], i8* noundef [[T5]]) +// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i8*)*)(i8* [[T7]], i8* [[T6]], i8* [[T5]]) // CHECK-NEXT: br label [[CONT:%.*]] // CHECK: call void @llvm.objc.release(i8* [[T5]]) [[NUW]] // CHECK-NEXT: br label [[CONT:%.*]] @@ -1556,7 +1556,7 @@ void test71(void) { // Check that no extra release calls are emitted to detruct the compond literal. -// CHECK: define{{.*}} void @test72(i8* noundef %[[A:.*]], i8* noundef %[[B:.*]]) +// CHECK: define{{.*}} void @test72(i8* %[[A:.*]], i8* %[[B:.*]]) // CHECK: %[[A_ADDR:.*]] = alloca i8*, align 8 // CHECK: %[[B_ADDR:.*]] = alloca i8*, align 8 // CHECK: %[[T:.*]] = alloca [2 x i8*], align 16 diff --git a/clang/test/CodeGenObjC/arm-atomic-scalar-setter-getter.m b/clang/test/CodeGenObjC/arm-atomic-scalar-setter-getter.m index 5341221401376f72eb1e3972cfb8756a03d421da..6eb58906e63920bb743921a16edaf9985b285829 100644 --- a/clang/test/CodeGenObjC/arm-atomic-scalar-setter-getter.m +++ b/clang/test/CodeGenObjC/arm-atomic-scalar-setter-getter.m @@ -8,6 +8,6 @@ @implementation I @synthesize LONG_PROP; @end -// CHECK-ARM: call void @objc_copyStruct(i8* noundef %{{.*}}, i8* noundef %{{.*}}, i32 noundef 8, i1 noundef zeroext true, i1 noundef zeroext false) -// CHECK-ARM: call void @objc_copyStruct(i8* noundef %{{.*}}, i8* noundef %{{.*}}, i32 noundef 8, i1 noundef zeroext true, i1 noundef zeroext false) +// CHECK-ARM: call void @objc_copyStruct(i8* %{{.*}}, i8* %{{.*}}, i32 8, i1 zeroext true, i1 zeroext false) +// CHECK-ARM: call void @objc_copyStruct(i8* %{{.*}}, i8* %{{.*}}, i32 8, i1 zeroext true, i1 zeroext false) diff --git a/clang/test/CodeGenObjC/atomic-aggregate-property.m b/clang/test/CodeGenObjC/atomic-aggregate-property.m index 4f9fba03cbbafe215540d12c2352c7e84255dc11..3bef0a0ed71f19d6d2b90128001438424910513f 100644 --- a/clang/test/CodeGenObjC/atomic-aggregate-property.m +++ b/clang/test/CodeGenObjC/atomic-aggregate-property.m @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-apple-darwin10 -fobjc-gc -emit-llvm -o - %s | FileCheck -check-prefix CHECK-LP64 %s -// RUN: %clang_cc1 -disable-noundef-analysis -x objective-c++ -triple x86_64-apple-darwin10 -fobjc-gc -emit-llvm -o - %s | FileCheck -check-prefix CHECK-LP64 %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -fobjc-gc -emit-llvm -o - %s | FileCheck -check-prefix CHECK-LP64 %s +// RUN: %clang_cc1 -x objective-c++ -triple x86_64-apple-darwin10 -fobjc-gc -emit-llvm -o - %s | FileCheck -check-prefix CHECK-LP64 %s // rdar: // 7849824 // diff --git a/clang/test/CodeGenObjC/availability-cf-link-guard.m b/clang/test/CodeGenObjC/availability-cf-link-guard.m index dd599df30397ceab4a3c8d0ee1e7fa7368780411..54ad19c9640a72c73c83515f8dc440533f459ac7 100644 --- a/clang/test/CodeGenObjC/availability-cf-link-guard.m +++ b/clang/test/CodeGenObjC/availability-cf-link-guard.m @@ -15,7 +15,7 @@ struct CFBundle; typedef struct CFBundle *CFBundleRef; unsigned CFBundleGetVersionNumber(CFBundleRef bundle); -// CHECK_CF: declare i32 @CFBundleGetVersionNumber(%struct.CFBundle* noundef) +// CHECK_CF: declare i32 @CFBundleGetVersionNumber(%struct.CFBundle*) // CHECK_CF: @__clang_at_available_requires_core_foundation_framework // CHECK_CF-NEXT: call {{.*}}@CFBundleGetVersionNumber #endif diff --git a/clang/test/CodeGenObjC/blocks.m b/clang/test/CodeGenObjC/blocks.m index b6308bff691fbe1ae771594f8f7383b7ca1db3c3..ab2e237a28dab63b2a79562701f1e76b266477af 100644 --- a/clang/test/CodeGenObjC/blocks.m +++ b/clang/test/CodeGenObjC/blocks.m @@ -115,7 +115,7 @@ void test3(void (^block)(int, ...)) { // CHECK-NEXT: [[T3:%.*]] = bitcast [[BLOCK_T]]* [[T1]] to i8* // CHECK-NEXT: [[T4:%.*]] = load i8*, i8** [[T2]] // CHECK-NEXT: [[T5:%.*]] = bitcast i8* [[T4]] to void (i8*, i32, ...)* -// CHECK-NEXT: call void (i8*, i32, ...) [[T5]](i8* noundef [[T3]], i32 noundef 0, i32 noundef 1, i32 noundef 2, i32 noundef 3) +// CHECK-NEXT: call void (i8*, i32, ...) [[T5]](i8* [[T3]], i32 0, i32 1, i32 2, i32 3) // CHECK-NEXT: ret void void test4(void (^block)()) { @@ -130,5 +130,5 @@ void test4(void (^block)()) { // CHECK-NEXT: [[T3:%.*]] = bitcast [[BLOCK_T]]* [[T1]] to i8* // CHECK-NEXT: [[T4:%.*]] = load i8*, i8** [[T2]] // CHECK-NEXT: [[T5:%.*]] = bitcast i8* [[T4]] to void (i8*, i32, i32, i32, i32)* -// CHECK-NEXT: call void [[T5]](i8* noundef [[T3]], i32 noundef 0, i32 noundef 1, i32 noundef 2, i32 noundef 3) +// CHECK-NEXT: call void [[T5]](i8* [[T3]], i32 0, i32 1, i32 2, i32 3) // CHECK-NEXT: ret void diff --git a/clang/test/CodeGenObjC/builtin-constant-p.m b/clang/test/CodeGenObjC/builtin-constant-p.m index 9d7a3e54d06b76c42366b46a0cfebef93a62c304..0b83c544f0d8a17db0d27d02d3a3bb38ac3f3557 100644 --- a/clang/test/CodeGenObjC/builtin-constant-p.m +++ b/clang/test/CodeGenObjC/builtin-constant-p.m @@ -8,7 +8,7 @@ extern void callee(void); -// CHECK-LABEL: define{{.*}} void @test(%0* noundef %foo, %1* noundef %bar) +// CHECK-LABEL: define{{.*}} void @test(%0* %foo, %1* %bar) void test(Foo *foo, Bar *bar) { // CHECK: [[ADDR_FOO:%.*]] = bitcast %0* %{{.*}} to i8* // CHECK-NEXT: call i1 @llvm.is.constant.p0i8(i8* [[ADDR_FOO]]) @@ -19,7 +19,7 @@ void test(Foo *foo, Bar *bar) { } // Test other Objective-C types. -// CHECK-LABEL: define{{.*}} void @test_more(i8* noundef %object, i8* noundef %klass) +// CHECK-LABEL: define{{.*}} void @test_more(i8* %object, i8* %klass) void test_more(id object, Class klass) { // CHECK: call i1 @llvm.is.constant.p0i8(i8* %{{.*}}) // CHECK: call i1 @llvm.is.constant.p0i8(i8* %{{.*}}) diff --git a/clang/test/CodeGenObjC/class-stubs.m b/clang/test/CodeGenObjC/class-stubs.m index 9f7f240b889bd7bdd8c18798686b370b181501df..6096cefce0839be8cfd21cf1aee41d732573f639 100644 --- a/clang/test/CodeGenObjC/class-stubs.m +++ b/clang/test/CodeGenObjC/class-stubs.m @@ -44,7 +44,7 @@ int main() { // CHECK-NEXT: [[CLASS:%.*]] = call %struct._class_t* @objc_loadClassref(i8** @"OBJC_CLASSLIST_REFERENCES_$_") // CHECK-NEXT: [[SELECTOR:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: [[RECEIVER:%.*]] = bitcast %struct._class_t* [[CLASS]] to i8* -// CHECK-NEXT: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*)*)(i8* noundef [[RECEIVER]], i8* noundef [[SELECTOR]]) +// CHECK-NEXT: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*)*)(i8* [[RECEIVER]], i8* [[SELECTOR]]) // CHECK-NEXT: ret i32 0 // CHECK-LABEL: declare extern_weak %struct._class_t* @objc_loadClassref(i8**) @@ -55,27 +55,27 @@ int main() { + (void) anotherClassMethod { [super classMethod]; } -// CHECK-LABEL: define internal void @"\01+[Derived(MyCategory) anotherClassMethod]"(i8* noundef %self, i8* noundef %_cmd) #0 { +// CHECK-LABEL: define internal void @"\01+[Derived(MyCategory) anotherClassMethod]"(i8* %self, i8* %_cmd) #0 { // CHECK-NEXT: entry: // CHECK: [[SUPER:%.*]] = alloca %struct._objc_super, align 8 // CHECK: [[METACLASS_REF:%.*]] = load %struct._class_t*, %struct._class_t** @"OBJC_CLASSLIST_SUP_REFS_$_", align 8 // CHECK: [[CAST_METACLASS_REF:%.*]] = bitcast %struct._class_t* [[METACLASS_REF]] to i8* // CHECK: [[DEST:%.*]] = getelementptr inbounds %struct._objc_super, %struct._objc_super* [[SUPER]], i32 0, i32 1 // CHECK: store i8* [[CAST_METACLASS_REF]], i8** [[DEST]], align 8 -// CHECK: call void bitcast (i8* (%struct._objc_super*, i8*, ...)* @objc_msgSendSuper2 to void (%struct._objc_super*, i8*)*)(%struct._objc_super* noundef [[SUPER]], i8* noundef {{%.*}}) +// CHECK: call void bitcast (i8* (%struct._objc_super*, i8*, ...)* @objc_msgSendSuper2 to void (%struct._objc_super*, i8*)*)(%struct._objc_super* [[SUPER]], i8* {{%.*}}) // CHECK: ret void - (void) anotherInstanceMethod { [super instanceMethod]; } -// CHECK-LABEL: define internal void @"\01-[Derived(MyCategory) anotherInstanceMethod]"(%0* noundef %self, i8* noundef %_cmd) #0 { +// CHECK-LABEL: define internal void @"\01-[Derived(MyCategory) anotherInstanceMethod]"(%0* %self, i8* %_cmd) #0 { // CHECK-NEXT: entry: // CHECK: [[SUPER:%.*]] = alloca %struct._objc_super, align 8 // CHECK: [[CLASS_REF:%.*]] = call %struct._class_t* @objc_loadClassref(i8** @"OBJC_CLASSLIST_SUP_REFS_$_.1") // CHECK: [[CAST_CLASS_REF:%.*]] = bitcast %struct._class_t* [[CLASS_REF]] to i8* // CHECK: [[DEST:%.*]] = getelementptr inbounds %struct._objc_super, %struct._objc_super* [[SUPER]], i32 0, i32 1 // CHECK: store i8* [[CAST_CLASS_REF]], i8** [[DEST]], align 8 -// CHECK: call void bitcast (i8* (%struct._objc_super*, i8*, ...)* @objc_msgSendSuper2 to void (%struct._objc_super*, i8*)*)(%struct._objc_super* noundef [[SUPER]], i8* noundef {{%.*}}) +// CHECK: call void bitcast (i8* (%struct._objc_super*, i8*, ...)* @objc_msgSendSuper2 to void (%struct._objc_super*, i8*)*)(%struct._objc_super* [[SUPER]], i8* {{%.*}}) // CHECK: ret void @end diff --git a/clang/test/CodeGenObjC/debug-info-blocks.m b/clang/test/CodeGenObjC/debug-info-blocks.m index 5694862ac6edf975554e92a96646ff3e6ee328f6..64392e2d8bc5aa09afcf3c94f4c914d82c31aabf 100644 --- a/clang/test/CodeGenObjC/debug-info-blocks.m +++ b/clang/test/CodeGenObjC/debug-info-blocks.m @@ -13,7 +13,7 @@ // Test that we do emit scope info for the helper functions, and that the // parameters to these functions are marked as artificial (so the debugger // doesn't accidentally step into the function). -// CHECK: define {{.*}} @__copy_helper_block_{{.*}}(i8* noundef %0, i8* noundef %1) +// CHECK: define {{.*}} @__copy_helper_block_{{.*}}(i8* %0, i8* %1) // CHECK-NOT: ret // CHECK: call {{.*}}, !dbg ![[DBG_LINE:[0-9]+]] // CHECK-NOT: ret diff --git a/clang/test/CodeGenObjC/debug-info-nested-blocks.m b/clang/test/CodeGenObjC/debug-info-nested-blocks.m index f73a0485ae90021ef8c7362453dd1d5bea9fec38..fe6c55bfcd6f92976954018a56ebb4bbf527db82 100644 --- a/clang/test/CodeGenObjC/debug-info-nested-blocks.m +++ b/clang/test/CodeGenObjC/debug-info-nested-blocks.m @@ -21,6 +21,6 @@ void bar(void) { // Verify that debug info for BlockPointerDbgLoc is emitted for the // innermost block. // -// CHECK: define {{.*}}void @__bar_block_invoke_3(i8* noundef %.block_descriptor) +// CHECK: define {{.*}}void @__bar_block_invoke_3(i8* %.block_descriptor) // CHECK: %[[BLOCKADDR:.*]] = alloca <{{.*}}>*, align // CHECK: call void @llvm.dbg.declare(metadata {{.*}}%[[BLOCKADDR]] diff --git a/clang/test/CodeGenObjC/exceptions.m b/clang/test/CodeGenObjC/exceptions.m index af522fbdc6aa41fa8612144aac94a5c8d925f807..1db03be2516a9a111ec5cf5eda1d36d30e2a7179 100644 --- a/clang/test/CodeGenObjC/exceptions.m +++ b/clang/test/CodeGenObjC/exceptions.m @@ -91,7 +91,7 @@ void f3() { // CHECK-NEXT: br i1 [[DEST1]] @try { - // CHECK: call void @f3_helper(i32 noundef 0, i32* noundef nonnull [[X]]) + // CHECK: call void @f3_helper(i32 0, i32* nonnull [[X]]) // CHECK: call void @objc_exception_try_exit( f3_helper(0, &x); } @finally { @@ -100,11 +100,11 @@ void f3() { // CHECK-NEXT: [[DEST2:%.*]] = icmp eq // CHECK-NEXT: br i1 [[DEST2]] @try { - // CHECK: call void @f3_helper(i32 noundef 1, i32* noundef nonnull [[X]]) + // CHECK: call void @f3_helper(i32 1, i32* nonnull [[X]]) // CHECK: call void @objc_exception_try_exit( f3_helper(1, &x); } @finally { - // CHECK: call void @f3_helper(i32 noundef 2, i32* noundef nonnull [[X]]) + // CHECK: call void @f3_helper(i32 2, i32* nonnull [[X]]) f3_helper(2, &x); // This loop is large enough to dissuade the optimizer from just @@ -121,7 +121,7 @@ void f3() { // CHECK: [[DEST1]] } - // CHECK: call void @f3_helper(i32 noundef 4, i32* noundef nonnull [[X]]) + // CHECK: call void @f3_helper(i32 4, i32* nonnull [[X]]) // CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[XPTR]]) // CHECK-NEXT: ret void f3_helper(4, &x); @@ -136,14 +136,14 @@ void f4() { // CHECK: call void @objc_exception_try_enter([[EXNDATA_T]]* nonnull [[EXNDATA]]) // CHECK: call i32 @_setjmp @try { - // CHECK: call void @f4_help(i32 noundef 0) + // CHECK: call void @f4_help(i32 0) f4_help(0); // The finally cleanup has two threaded entrypoints after optimization: // finally.no-call-exit: Predecessor is when the catch throws. // CHECK: call i8* @objc_exception_extract([[EXNDATA_T]]* nonnull [[EXNDATA]]) - // CHECK-NEXT: call void @f4_help(i32 noundef 2) + // CHECK-NEXT: call void @f4_help(i32 2) // CHECK-NEXT: br label // -> rethrow @@ -153,7 +153,7 @@ void f4() { // CHECK: phi i8* // CHECK-NEXT: phi i1 // CHECK-NEXT: call void @objc_exception_try_exit([[EXNDATA_T]]* nonnull [[EXNDATA]]) - // CHECK-NEXT: call void @f4_help(i32 noundef 2) + // CHECK-NEXT: call void @f4_help(i32 2) // CHECK-NEXT: br i1 // -> ret, rethrow @@ -169,7 +169,7 @@ void f4() { // -> finally.call-exit, match } @catch (NSArray *a) { // match: - // CHECK: call void @f4_help(i32 noundef 1) + // CHECK: call void @f4_help(i32 1) // CHECK-NEXT: br label // -> finally.call-exit f4_help(1); diff --git a/clang/test/CodeGenObjC/for-in.m b/clang/test/CodeGenObjC/for-in.m index ed618e09dd5b4f9540ee01b724c6e9c01998806f..30d46da20752da17d3671ba530f923c5208a4390 100644 --- a/clang/test/CodeGenObjC/for-in.m +++ b/clang/test/CodeGenObjC/for-in.m @@ -30,7 +30,7 @@ void t0() { // CHECK: [[expectedCls:%.*]] = load %struct._class_t*, {{.*}}, !nosanitize // CHECK-NEXT: [[kindOfClassSel:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES{{.*}}, !nosanitize // CHECK-NEXT: [[expectedClsI8:%.*]] = bitcast %struct._class_t* [[expectedCls]] to i8*, !nosanitize - // CHECK-NEXT: [[isCls:%.*]] = call zeroext i1 bitcast {{.*}}@objc_msgSend to i1 (i8*, i8*, {{.*}})(i8* noundef [[theItem:%.*]], i8* noundef [[kindOfClassSel]], i8* noundef [[expectedClsI8]]), !nosanitize + // CHECK-NEXT: [[isCls:%.*]] = call zeroext i1 bitcast {{.*}}@objc_msgSend to i1 (i8*, i8*, {{.*}})(i8* [[theItem:%.*]], i8* [[kindOfClassSel]], i8* [[expectedClsI8]]), !nosanitize // CHECK: br i1 [[isCls]] // CHECK: ptrtoint i8* [[theItem]] to i64, !nosanitize diff --git a/clang/test/CodeGenObjC/fragile-arc.m b/clang/test/CodeGenObjC/fragile-arc.m index 8a46292480bacfc4b0ea3fdebe85bc4a8984487c..b6852d7cc2c6e4e928f84b74fa0db3652df78f96 100644 --- a/clang/test/CodeGenObjC/fragile-arc.m +++ b/clang/test/CodeGenObjC/fragile-arc.m @@ -142,10 +142,10 @@ void testBlockLayoutWeak(__weak id x) { // CHECK: [[Y:%.*]] = alloca i8*, align 4 // CHECK: call void @objc_exception_try_enter // CHECK: br i1 -// CHECK: call void @checkpoint(i32 noundef 0) +// CHECK: call void @checkpoint(i32 0) // CHECK: call void @objc_exception_try_exit // CHECK: br label -// CHECK: call void @checkpoint(i32 noundef 3) +// CHECK: call void @checkpoint(i32 3) // CHECK: [[EXN:%.*]] = call i8* @objc_exception_extract // CHECK: call i32 @objc_exception_match( // CHECK: br i1 @@ -154,13 +154,13 @@ void testBlockLayoutWeak(__weak id x) { // CHECK: [[T2:%.*]] = call i8* @llvm.objc.retain(i8* [[T1]]) // CHECK: [[T3:%.*]] = bitcast i8* [[T2]] to [[A]]* // CHECK: store [[A]]* [[T3]], [[A]]** [[X]] -// CHECK: call void @checkpoint(i32 noundef 1) +// CHECK: call void @checkpoint(i32 1) // CHECK: [[T0:%.*]] = bitcast [[A]]** [[X]] to i8** // CHECK: call void @llvm.objc.storeStrong(i8** [[T0]], i8* null) // CHECK: br label // CHECK: [[T0:%.*]] = call i8* @llvm.objc.retain(i8* [[EXN]]) // CHECK: store i8* [[T0]], i8** [[Y]] -// CHECK: call void @checkpoint(i32 noundef 2) +// CHECK: call void @checkpoint(i32 2) // CHECK: call void @llvm.objc.storeStrong(i8** [[Y]], i8* null) extern void checkpoint(int n); void testCatch() { diff --git a/clang/test/CodeGenObjC/gnu-exceptions.m b/clang/test/CodeGenObjC/gnu-exceptions.m index d441e984968ecea1d0e8d103f1dde99dd7822045..0de34c4cdc3470c67081dc9296785f280ea70240 100644 --- a/clang/test/CodeGenObjC/gnu-exceptions.m +++ b/clang/test/CodeGenObjC/gnu-exceptions.m @@ -13,14 +13,14 @@ void test0() { // CHECK: invoke void @opaque() opaque(); - // CHECK: call void @log(i32 noundef 1) + // CHECK: call void @log(i32 1) } @catch (C *c) { // CHECK: landingpad { i8*, i32 } // CHECK-NEXT: catch i8* getelementptr inbounds ([2 x i8], [2 x i8]* @0, i64 0, i64 0) // CHECK: br i1 - // CHECK: call void @log(i32 noundef 0) + // CHECK: call void @log(i32 0) // CHECK: resume // NEW-ABI: objc_begin_catch diff --git a/clang/test/CodeGenObjC/implicit-objc_msgSend.m b/clang/test/CodeGenObjC/implicit-objc_msgSend.m index 465cbc896e929358a01782c383639167e18ad38c..6fc3d46d50d9153dfda1e067acb5ab6ec8d6132e 100644 --- a/clang/test/CodeGenObjC/implicit-objc_msgSend.m +++ b/clang/test/CodeGenObjC/implicit-objc_msgSend.m @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple x86_64-apple-darwin9 -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o %t %s -// RUN: grep -F 'declare i8* @objc_msgSend(i8* noundef, i8* noundef, ...)' %t +// RUN: grep -F 'declare i8* @objc_msgSend(i8*, i8*, ...)' %t typedef struct objc_selector *SEL; id f0(id x, SEL s) { diff --git a/clang/test/CodeGenObjC/ivar-invariant.m b/clang/test/CodeGenObjC/ivar-invariant.m index 8bd8e7abb1f99eab85316ff49c8e7e00cdead5c0..c86df948969b868cc7430432c15e98d5b91326c9 100644 --- a/clang/test/CodeGenObjC/ivar-invariant.m +++ b/clang/test/CodeGenObjC/ivar-invariant.m @@ -40,7 +40,7 @@ void * variant_load_1(int i) { return ptr; } -// CHECK-LABEL: define{{.*}} i8* @variant_load_1(i32 noundef %i) +// CHECK-LABEL: define{{.*}} i8* @variant_load_1(i32 %i) // CHECK: [[IVAR:%.*]] = load i64, i64* @"OBJC_IVAR_$_Derived.member", align 8{{$}} @interface Container : Derived @end diff --git a/clang/test/CodeGenObjC/local-static-block.m b/clang/test/CodeGenObjC/local-static-block.m index d656962fd471bbc65d84b6a3b1392fa842bf5b08..26d87b03f6f357f926deb4e6c4db4a7c868166c8 100644 --- a/clang/test/CodeGenObjC/local-static-block.m +++ b/clang/test/CodeGenObjC/local-static-block.m @@ -59,7 +59,7 @@ void FUNC2() { // CHECK-LABEL: define{{.*}} void @FUNC2( // CHECK: define internal void @_block_invoke{{.*}}( -// CHECK: call void %{{.*}}(i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global{{.*}} to i8*), i32 noundef %{{.*}}) +// CHECK: call void %{{.*}}(i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global{{.*}} to i8*), i32 %{{.*}}) void FUNC1() { diff --git a/clang/test/CodeGenObjC/mangle-blocks.m b/clang/test/CodeGenObjC/mangle-blocks.m index ea34d0215911a74036718e7ee652b120391a9739..73522cd41c638c30f76812436124b64a27fff0d2 100644 --- a/clang/test/CodeGenObjC/mangle-blocks.m +++ b/clang/test/CodeGenObjC/mangle-blocks.m @@ -21,8 +21,8 @@ void __assert_rtn(const char *, const char *, int, const char *); // CHECK: @.str{{.*}} = private unnamed_addr constant {{.*}}, align 1 // CHECK: @.str[[STR1:.*]] = private unnamed_addr constant [7 x i8] c"mangle\00", align 1 -// CHECK: define internal void @"__14-[Test mangle]_block_invoke"(i8* noundef %.block_descriptor) +// CHECK: define internal void @"__14-[Test mangle]_block_invoke"(i8* %.block_descriptor) -// CHECK: define internal void @"__14-[Test mangle]_block_invoke_2"(i8* noundef %.block_descriptor){{.*}}{ -// CHECK: call void @__assert_rtn(i8* noundef getelementptr inbounds ([30 x i8], [30 x i8]* @"__func__.__14-[Test mangle]_block_invoke_2", i32 0, i32 0), i8* noundef getelementptr inbounds {{.*}}, i32 noundef 14, i8* noundef getelementptr inbounds ([7 x i8], [7 x i8]* @.str[[STR1]], i32 0, i32 0)) +// CHECK: define internal void @"__14-[Test mangle]_block_invoke_2"(i8* %.block_descriptor){{.*}}{ +// CHECK: call void @__assert_rtn(i8* getelementptr inbounds ([30 x i8], [30 x i8]* @"__func__.__14-[Test mangle]_block_invoke_2", i32 0, i32 0), i8* getelementptr inbounds {{.*}}, i32 14, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str[[STR1]], i32 0, i32 0)) // CHECK: } diff --git a/clang/test/CodeGenObjC/matrix-type-builtins.m b/clang/test/CodeGenObjC/matrix-type-builtins.m index 883f9a1cdf705303e0a259bc9dac26f5cb276b44..0d517dd4964a87eb87af154546e330d8d76ef507 100644 --- a/clang/test/CodeGenObjC/matrix-type-builtins.m +++ b/clang/test/CodeGenObjC/matrix-type-builtins.m @@ -12,6 +12,13 @@ __attribute__((objc_root_class)) @end void test_transpose_placeholder_get(DoubleMatrixValue *m, double2x4 *r) { + // CHECK-LABEL: define{{.*}} void @test_transpose_placeholder_get( + // CHECK: [[MATRIX:%.*]] = call <8 x double> bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to <8 x double> (i8*, i8*)*)( + // CHECK-NEXT: [[MT:%.*]] = call <8 x double> @llvm.matrix.transpose.v8f64(<8 x double> %call, i32 4, i32 2) + // CHECK-NEXT: [[R_ADDR:%.*]] = load [8 x double]*, [8 x double]** %r.addr, align 8 + // CHECK-NEXT: [[R_ADDR_C:%.*]] = bitcast [8 x double]* [[R_ADDR]] to <8 x double>* + // CHECK-NEXT: store <8 x double> [[MT]], <8 x double>* [[R_ADDR_C]], align 8 + // CHECK-NEXT: ret void *r = __builtin_matrix_transpose(m.value); } @@ -25,6 +32,11 @@ __attribute__((objc_root_class)) @end void test_transpose_placeholder_set(UnsignedMatrixValue *m, u4x3 *r) { + // CHECK-LABEL: define{{.*}} void @test_transpose_placeholder_set( + // CHECK: [[MATRIX:%.*]] = load <12 x i32>, <12 x i32>* {{.*}}, align 4 + // CHECK-NEXT: [[MT:%.*]] = call <12 x i32> @llvm.matrix.transpose.v12i32(<12 x i32> [[MATRIX]], i32 4, i32 3) + // CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, <12 x i32>)*)(i8* {{.*}}, i8* {{.*}}, <12 x i32> [[MT]]) + // CHECK-NEXT: ret void m.value = __builtin_matrix_transpose(*r); } @@ -40,7 +52,7 @@ __attribute__((objc_root_class)) @end void test_column_major_load(PtrValue *Ptr, IntValue *Stride) { - // CHECK-LABEL: define{{.*}} void @test_column_major_load(%2* noundef %Ptr, %3* noundef %Stride) #4 { + // CHECK-LABEL: define{{.*}} void @test_column_major_load(%2* %Ptr, %3* %Stride) #4 { // CHECK: [[STRIDE:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*) // CHECK-NEXT: [[STRIDE_EXT:%.*]] = sext i32 [[STRIDE]] to i64 // CHECK: [[PTR:%.*]] = call i32* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32* (i8*, i8*)*) @@ -50,7 +62,7 @@ void test_column_major_load(PtrValue *Ptr, IntValue *Stride) { } void test_column_major_store(UnsignedMatrixValue *M, PtrValue *Ptr, IntValue *Stride) { - // CHECK-LABEL: define{{.*}} void @test_column_major_store(%1* noundef %M, %2* noundef %Ptr, %3* noundef %Stride) #3 { + // CHECK-LABEL: define{{.*}} void @test_column_major_store(%1* %M, %2* %Ptr, %3* %Stride) #3 { // CHECK: [[M:%.*]] = call <12 x i32> bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to <12 x i32> (i8*, i8*)*) // CHECK: [[PTR:%.*]] = call i32* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32* (i8*, i8*)*) // CHECK: [[IDX:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*) diff --git a/clang/test/CodeGenObjC/matrix-type-operators.m b/clang/test/CodeGenObjC/matrix-type-operators.m index 4e5684e283fc278307c08cd99227cd489e61d8bc..8e3986e21e5045aa3f9b5fb835a35db64ff35c46 100644 --- a/clang/test/CodeGenObjC/matrix-type-operators.m +++ b/clang/test/CodeGenObjC/matrix-type-operators.m @@ -15,12 +15,12 @@ typedef double double4x4 __attribute__((matrix_type(4, 4))); // CHECK: [[IV:%.*]] = load %0*, %0** [[IV_ADDR:%.*]], align 8 // CHECK-NEXT: [[SEL:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_, align 8, !invariant.load !7 // CHECK-NEXT: [[IV_PTR:%.*]] = bitcast %0* [[IV]] to i8* -// CHECK-NEXT: [[CALL:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*)(i8* noundef [[IV_PTR]], i8* noundef [[SEL]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*)(i8* [[IV_PTR]], i8* [[SEL]]) // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64 // CHECK-NEXT: [[IV2:%.*]] = load %0*, %0** [[IV_ADDR]], align 8 // CHECK-NEXT: [[SEL2:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_, align 8, !invariant.load !7 // CHECK-NEXT: [[IV2_PTR:%.*]] = bitcast %0* [[IV2]] to i8* -// CHECK-NEXT: [[CALL1:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*)(i8* noundef [[IV2_PTR]], i8* noundef [[SEL2]]) +// CHECK-NEXT: [[CALL1:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*)(i8* [[IV2_PTR]], i8* [[SEL2]]) // CHECK-NEXT: [[CONV2:%.*]] = sext i32 [[CALL1]] to i64 // CHECK-NEXT: [[IDX1:%.*]] = mul i64 [[CONV2]], 4 // CHECK-NEXT: [[IDX2:%.*]] = add i64 [[IDX1]], [[CONV]] @@ -42,19 +42,19 @@ __attribute__((objc_root_class)) // CHECK: [[IV:%.*]] = load %0*, %0** [[IV_ADDR:%.*]], align 8 // CHECK-NEXT: [[SEL:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_, align 8, !invariant.load !7 // CHECK-NEXT: [[IV_PTR:%.*]] = bitcast %0* [[IV]] to i8* -// CHECK-NEXT: [[CALL:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*)(i8* noundef [[IV_PTR]], i8* noundef [[SEL]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*)(i8* [[IV_PTR]], i8* [[SEL]]) // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64 // CHECK-NEXT: [[IV2:%.*]] = load %0*, %0** [[IV_ADDR]], align 8 // CHECK-NEXT: [[SEL2:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_, align 8, !invariant.load !7 // CHECK-NEXT: [[IV2_PTR:%.*]] = bitcast %0* [[IV2]] to i8* -// CHECK-NEXT: [[CALL1:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*)(i8* noundef [[IV2_PTR]], i8* noundef [[SEL2]]) +// CHECK-NEXT: [[CALL1:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*)(i8* [[IV2_PTR]], i8* [[SEL2]]) // CHECK-NEXT: [[CONV2:%.*]] = sext i32 [[CALL1]] to i64 // CHECK-NEXT: [[IDX1:%.*]] = mul i64 [[CONV2]], 4 // CHECK-NEXT: [[IDX2:%.*]] = add i64 [[IDX1]], [[CONV]] // CHECK-NEXT: [[M:%.*]] = load %1*, %1** %m.addr, align 8 // CHECK-NEXT: [[SEL3:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_, align 8, !invariant.load !7 // CHECK-NEXT: [[M_PTR:%.*]] = bitcast %1* [[M]] to i8* -// CHECK-NEXT: [[MAT:%.*]] = call <16 x double> bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to <16 x double> (i8*, i8*)*)(i8* noundef [[M_PTR]], i8* noundef [[SEL3]]) +// CHECK-NEXT: [[MAT:%.*]] = call <16 x double> bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to <16 x double> (i8*, i8*)*)(i8* [[M_PTR]], i8* [[SEL3]]) // CHECK-NEXT: [[MATEXT:%.*]] = extractelement <16 x double> [[MAT]], i64 [[IDX2]] // CHECK-NEXT: ret double [[MATEXT]] // diff --git a/clang/test/CodeGenObjC/noescape.m b/clang/test/CodeGenObjC/noescape.m index e3a11605bb1df41b5b812a8d736a7229fd4f5034..1bdcce2efdd05effbfa5d3b84a12693933e1bdb5 100644 --- a/clang/test/CodeGenObjC/noescape.m +++ b/clang/test/CodeGenObjC/noescape.m @@ -29,21 +29,21 @@ void noescapeFunc3(__attribute__((noescape)) union U); // CHECK-LABEL: define{{.*}} void @test0( // CHECK: call void @noescapeFunc0({{.*}}, {{.*}} nocapture {{.*}}) -// CHECK: declare void @noescapeFunc0(i8* noundef, {{.*}} nocapture noundef) +// CHECK: declare void @noescapeFunc0(i8*, {{.*}} nocapture) void test0(BlockTy b) { noescapeFunc0(0, b); } // CHECK-LABEL: define{{.*}} void @test1( // CHECK: call void @noescapeFunc1({{.*}} nocapture {{.*}}) -// CHECK: declare void @noescapeFunc1({{.*}} nocapture noundef) +// CHECK: declare void @noescapeFunc1({{.*}} nocapture) void test1(int *i) { noescapeFunc1(i); } // CHECK-LABEL: define{{.*}} void @test2( // CHECK: call void @noescapeFunc2({{.*}} nocapture {{.*}}) -// CHECK: declare void @noescapeFunc2({{.*}} nocapture noundef) +// CHECK: declare void @noescapeFunc2({{.*}} nocapture) void test2(id i) { noescapeFunc2(i); } @@ -74,7 +74,7 @@ void test4(C0 *c0, int *p) { } // CHECK-LABEL: define{{.*}} void @test5( -// CHECK: call void {{.*}}(i8* noundef bitcast ({ i8**, i32, i32, i8*, {{.*}} }* @{{.*}} to i8*), i32* nocapture {{.*}}) +// CHECK: call void {{.*}}(i8* bitcast ({ i8**, i32, i32, i8*, {{.*}} }* @{{.*}} to i8*), i32* nocapture {{.*}}) // CHECK: call void {{.*}}(i8* {{.*}}, i32* nocapture {{.*}}) // CHECK: define internal void @{{.*}}(i8* {{.*}}, i32* nocapture {{.*}}) @@ -88,7 +88,7 @@ void test5(BlockTy2 b, int *p) { // If the block is non-escaping, set the BLOCK_IS_NOESCAPE and BLOCK_IS_GLOBAL // bits of field 'flags' and set the 'isa' field to 'NSConcreteGlobalBlock'. -// CHECK: define{{.*}} void @test6(i8* noundef %{{.*}}, i8* noundef %[[B:.*]]) +// CHECK: define{{.*}} void @test6(i8* %{{.*}}, i8* %[[B:.*]]) // CHECK: %{{.*}} = alloca i8*, align 8 // CHECK: %[[B_ADDR:.*]] = alloca i8*, align 8 // CHECK: %[[BLOCK:.*]] = alloca <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]*, i8* }>, align 8 diff --git a/clang/test/CodeGenObjC/nontrivial-c-struct-exception.m b/clang/test/CodeGenObjC/nontrivial-c-struct-exception.m index 649de8d8d3f16b990e3439bf0507a327039c0002..7fd0f23943c090ff66a4abe185f8d29a7eb676b5 100644 --- a/clang/test/CodeGenObjC/nontrivial-c-struct-exception.m +++ b/clang/test/CodeGenObjC/nontrivial-c-struct-exception.m @@ -44,7 +44,7 @@ void testStrongException(void) { // CHECK: call void @genWeak(%[[STRUCT_WEAK]]* sret(%[[STRUCT_WEAK]]) align 8 %[[AGG_TMP]]) // CHECK: invoke void @genWeak(%[[STRUCT_WEAK]]* sret(%[[STRUCT_WEAK]]) align 8 %[[AGG_TMP1]]) -// CHECK: call void @calleeWeak(%[[STRUCT_WEAK]]* noundef %[[AGG_TMP]], %[[STRUCT_WEAK]]* noundef %[[AGG_TMP1]]) +// CHECK: call void @calleeWeak(%[[STRUCT_WEAK]]* %[[AGG_TMP]], %[[STRUCT_WEAK]]* %[[AGG_TMP1]]) // CHECK: ret void // CHECK: landingpad { i8*, i32 } diff --git a/clang/test/CodeGenObjC/nontrivial-c-struct-within-struct-name.m b/clang/test/CodeGenObjC/nontrivial-c-struct-within-struct-name.m index dac8686f1833a4c103860408622db1b996594844..854c097c0eab7c95a1be871e73c1c0f7d98be87b 100644 --- a/clang/test/CodeGenObjC/nontrivial-c-struct-within-struct-name.m +++ b/clang/test/CodeGenObjC/nontrivial-c-struct-within-struct-name.m @@ -22,21 +22,21 @@ void f() { Baz baz = {bar}; } -// CHECK: define linkonce_odr hidden void @__destructor_8_S_S_s0(i8** noundef %[[DST:.*]]) +// CHECK: define linkonce_odr hidden void @__destructor_8_S_S_s0(i8** %[[DST:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8 // CHECK: call void @__destructor_8_S_s0(i8** %[[V0]]) // CHECK: ret void -// CHECK: define linkonce_odr hidden void @__destructor_8_S_s0(i8** noundef %[[DST:.*]]) +// CHECK: define linkonce_odr hidden void @__destructor_8_S_s0(i8** %[[DST:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8 // CHECK: call void @__destructor_8_s0(i8** %[[V0]]) // CHECK: ret void -// CHECK: define linkonce_odr hidden void @__destructor_8_s0(i8** noundef %dst) +// CHECK: define linkonce_odr hidden void @__destructor_8_s0(i8** %dst) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8 diff --git a/clang/test/CodeGenObjC/nsvalue-objc-boxable-ios-arc.m b/clang/test/CodeGenObjC/nsvalue-objc-boxable-ios-arc.m index d1ad8a0d3cbedadcb60129dcf3826c50a69a1c04..00fffddf570b421ad30e1dc84061b06417c30dbf 100644 --- a/clang/test/CodeGenObjC/nsvalue-objc-boxable-ios-arc.m +++ b/clang/test/CodeGenObjC/nsvalue-objc-boxable-ios-arc.m @@ -24,7 +24,7 @@ void doRange() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* NSRange ns_range = { .location = 0, .length = 42 }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8* {{.*}}[[RANGE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8* {{.*}}[[RANGE_STR]]{{.*}}) // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue NSValue *range = @(ns_range); // CHECK: call void @llvm.objc.release @@ -43,7 +43,7 @@ void doPoint() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* CGPoint cg_point = { .x = 42, .y = 24 }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8* {{.*}}[[POINT_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8* {{.*}}[[POINT_STR]]{{.*}}) // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue NSValue *point = @(cg_point); // CHECK: call void @llvm.objc.release @@ -62,7 +62,7 @@ void doSize() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* CGSize cg_size = { .width = 42, .height = 24 }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8* {{.*}}[[SIZE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8* {{.*}}[[SIZE_STR]]{{.*}}) // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue NSValue *size = @(cg_size); // CHECK: call void @llvm.objc.release @@ -83,7 +83,7 @@ void doRect() { CGPoint cg_point = { .x = 42, .y = 24 }; CGSize cg_size = { .width = 42, .height = 24 }; CGRect cg_rect = { .origin = cg_point, .size = cg_size }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8*{{.*}}[[RECT_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8*{{.*}}[[RECT_STR]]{{.*}}) // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue NSValue *rect = @(cg_rect); // CHECK: call void @llvm.objc.release @@ -102,7 +102,7 @@ void doNSEdgeInsets() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* NSEdgeInsets ns_edge_insets; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8*{{.*}}[[EDGE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8*{{.*}}[[EDGE_STR]]{{.*}}) // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue NSValue *edge_insets = @(ns_edge_insets); // CHECK: call void @llvm.objc.release @@ -117,7 +117,7 @@ void doRangeRValue() { // CHECK: [[COERCE_CAST:%.*]] = bitcast %struct._NSRange* [[COERCE]]{{.*}} // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[COERCE_CAST]], i8* {{.*}}[[RANGE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[COERCE_CAST]], i8* {{.*}}[[RANGE_STR]]{{.*}}) // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue NSValue *range_rvalue = @(getRange()); // CHECK: call void @llvm.objc.release diff --git a/clang/test/CodeGenObjC/nsvalue-objc-boxable-ios.m b/clang/test/CodeGenObjC/nsvalue-objc-boxable-ios.m index be4b7ca22d6e17d217bb762f3bd0aae8cdf5c8f5..f9faa92e4ca2872281bb5346ef70aa1811fa8a52 100644 --- a/clang/test/CodeGenObjC/nsvalue-objc-boxable-ios.m +++ b/clang/test/CodeGenObjC/nsvalue-objc-boxable-ios.m @@ -24,7 +24,7 @@ void doRange() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* NSRange ns_range = { .location = 0, .length = 42 }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8* noundef {{.*}}[[RANGE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8* {{.*}}[[RANGE_STR]]{{.*}}) NSValue *range = @(ns_range); // CHECK: ret void } @@ -41,7 +41,7 @@ void doPoint() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* CGPoint cg_point = { .x = 42, .y = 24 }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8* noundef {{.*}}[[POINT_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8* {{.*}}[[POINT_STR]]{{.*}}) NSValue *point = @(cg_point); // CHECK: ret void } @@ -58,7 +58,7 @@ void doSize() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* CGSize cg_size = { .width = 42, .height = 24 }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8* noundef {{.*}}[[SIZE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8* {{.*}}[[SIZE_STR]]{{.*}}) NSValue *size = @(cg_size); // CHECK: ret void } @@ -77,7 +77,7 @@ void doRect() { CGPoint cg_point = { .x = 42, .y = 24 }; CGSize cg_size = { .width = 42, .height = 24 }; CGRect cg_rect = { .origin = cg_point, .size = cg_size }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8*{{.*}}[[RECT_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8*{{.*}}[[RECT_STR]]{{.*}}) NSValue *rect = @(cg_rect); // CHECK: ret void } @@ -94,7 +94,7 @@ void doNSEdgeInsets() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* NSEdgeInsets ns_edge_insets; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8*{{.*}}[[EDGE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8*{{.*}}[[EDGE_STR]]{{.*}}) NSValue *edge_insets = @(ns_edge_insets); // CHECK: ret void } @@ -107,7 +107,7 @@ void doRangeRValue() { // CHECK: [[COERCE_CAST:%.*]] = bitcast %struct._NSRange* [[COERCE]]{{.*}} // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[COERCE_CAST]], i8* noundef {{.*}}[[RANGE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[COERCE_CAST]], i8* {{.*}}[[RANGE_STR]]{{.*}}) NSValue *range_rvalue = @(getRange()); // CHECK: ret void } diff --git a/clang/test/CodeGenObjC/nsvalue-objc-boxable-mac-arc.m b/clang/test/CodeGenObjC/nsvalue-objc-boxable-mac-arc.m index d941eaecb12e7da807b618363769351bffbc6ef9..3b4c71d54ffb43816f2d4d0435002c630f4a78bf 100644 --- a/clang/test/CodeGenObjC/nsvalue-objc-boxable-mac-arc.m +++ b/clang/test/CodeGenObjC/nsvalue-objc-boxable-mac-arc.m @@ -24,7 +24,7 @@ void doRange() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* NSRange ns_range = { .location = 0, .length = 42 }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8* {{.*}}[[RANGE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8* {{.*}}[[RANGE_STR]]{{.*}}) // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue NSValue *range = @(ns_range); // CHECK: call void @llvm.objc.release @@ -43,7 +43,7 @@ void doPoint() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* NSPoint ns_point = { .x = 42, .y = 24 }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8* {{.*}}[[POINT_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8* {{.*}}[[POINT_STR]]{{.*}}) // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue NSValue *point = @(ns_point); // CHECK: call void @llvm.objc.release @@ -62,7 +62,7 @@ void doSize() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* NSSize ns_size = { .width = 42, .height = 24 }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8* {{.*}}[[SIZE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8* {{.*}}[[SIZE_STR]]{{.*}}) // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue NSValue *size = @(ns_size); // CHECK: call void @llvm.objc.release @@ -83,7 +83,7 @@ void doRect() { NSPoint ns_point = { .x = 42, .y = 24 }; NSSize ns_size = { .width = 42, .height = 24 }; NSRect ns_rect = { .origin = ns_point, .size = ns_size }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8*{{.*}}[[RECT_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8*{{.*}}[[RECT_STR]]{{.*}}) // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue NSValue *rect = @(ns_rect); // CHECK: call void @llvm.objc.release @@ -102,7 +102,7 @@ void doNSEdgeInsets() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* NSEdgeInsets ns_edge_insets; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8*{{.*}}[[EDGE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8*{{.*}}[[EDGE_STR]]{{.*}}) // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue NSValue *edge_insets = @(ns_edge_insets); // CHECK: call void @llvm.objc.release @@ -121,7 +121,7 @@ void doRangeRValue() { // CHECK: [[COERCE_CAST:%.*]] = bitcast %struct._NSRange* [[COERCE]]{{.*}} // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[COERCE_CAST]], i8* {{.*}}[[RANGE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[COERCE_CAST]], i8* {{.*}}[[RANGE_STR]]{{.*}}) // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue NSValue *range_rvalue = @(getRange()); // CHECK: call void @llvm.objc.release diff --git a/clang/test/CodeGenObjC/nsvalue-objc-boxable-mac.m b/clang/test/CodeGenObjC/nsvalue-objc-boxable-mac.m index a10885d7ff75e7925dd4d7ce40b616060f52bb88..02c4ba75b6e5f5504389e56af46cdb69d9110511 100644 --- a/clang/test/CodeGenObjC/nsvalue-objc-boxable-mac.m +++ b/clang/test/CodeGenObjC/nsvalue-objc-boxable-mac.m @@ -24,7 +24,7 @@ void doRange() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* NSRange ns_range = { .location = 0, .length = 42 }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8* noundef {{.*}}[[RANGE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8* {{.*}}[[RANGE_STR]]{{.*}}) NSValue *range = @(ns_range); // CHECK: ret void } @@ -41,7 +41,7 @@ void doPoint() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* NSPoint ns_point = { .x = 42, .y = 24 }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8* noundef {{.*}}[[POINT_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8* {{.*}}[[POINT_STR]]{{.*}}) NSValue *point = @(ns_point); // CHECK: ret void } @@ -58,7 +58,7 @@ void doSize() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* NSSize ns_size = { .width = 42, .height = 24 }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8* noundef {{.*}}[[SIZE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8* {{.*}}[[SIZE_STR]]{{.*}}) NSValue *size = @(ns_size); // CHECK: ret void } @@ -77,7 +77,7 @@ void doRect() { NSPoint ns_point = { .x = 42, .y = 24 }; NSSize ns_size = { .width = 42, .height = 24 }; NSRect ns_rect = { .origin = ns_point, .size = ns_size }; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8*{{.*}}[[RECT_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8*{{.*}}[[RECT_STR]]{{.*}}) NSValue *rect = @(ns_rect); // CHECK: ret void } @@ -94,7 +94,7 @@ void doNSEdgeInsets() { // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* NSEdgeInsets ns_edge_insets; - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[PARAM_CAST]], i8*{{.*}}[[EDGE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[PARAM_CAST]], i8*{{.*}}[[EDGE_STR]]{{.*}}) NSValue *edge_insets = @(ns_edge_insets); // CHECK: ret void } @@ -111,7 +111,7 @@ void doRangeRValue() { // CHECK: [[COERCE_CAST:%.*]] = bitcast %struct._NSRange* [[COERCE]]{{.*}} // CHECK: [[SEL:%.*]] = load i8*, i8** [[VALUE_SEL]] // CHECK: [[RECV:%.*]] = bitcast %struct._class_t* [[RECV_PTR]] to i8* - // CHECK: call {{.*objc_msgSend.*}}(i8* noundef [[RECV]], i8* noundef [[SEL]], i8* noundef [[COERCE_CAST]], i8* noundef {{.*}}[[RANGE_STR]]{{.*}}) + // CHECK: call {{.*objc_msgSend.*}}(i8* [[RECV]], i8* [[SEL]], i8* [[COERCE_CAST]], i8* {{.*}}[[RANGE_STR]]{{.*}}) NSValue *range_rvalue = @(getRange()); // CHECK: ret void } diff --git a/clang/test/CodeGenObjC/objc-container-subscripting-1.m b/clang/test/CodeGenObjC/objc-container-subscripting-1.m index 248135d882f62e6315106ab4ee1dc072315bb9f0..18f2f8cf6ffdb21c67ab22dcfc2f002a74c02519 100644 --- a/clang/test/CodeGenObjC/objc-container-subscripting-1.m +++ b/clang/test/CodeGenObjC/objc-container-subscripting-1.m @@ -21,7 +21,7 @@ int main() { // CHECK: [[ARR:%.*]] = load {{%.*}} [[array:%.*]], align 8 // CHECK-NEXT: [[SEL:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: [[ARRC:%.*]] = bitcast {{%.*}} [[ARR]] to i8* -// CHECK-NEXT: [[CALL:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*, i32)*)(i8* noundef [[ARRC]], i8* noundef [[SEL]], i32 noundef 10) +// CHECK-NEXT: [[CALL:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*, i32)*)(i8* [[ARRC]], i8* [[SEL]], i32 10) // CHECK-NEXT: store i8* [[CALL]], i8** [[OLDOBJ:%.*]], align 8 val = (array[10] = oldObject); @@ -29,7 +29,7 @@ int main() { // CHECK-NEXT: [[THREE:%.*]] = load {{%.*}} [[array:%.*]], align 8 // CHECK-NEXT: [[FIVE:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_.2 // CHECK-NEXT: [[SIX:%.*]] = bitcast {{%.*}} [[THREE]] to i8* -// CHECK-NEXT: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i8*, i32)*)(i8* noundef [[SIX]], i8* noundef [[FIVE]], i8* noundef [[FOUR]], i32 noundef 10) +// CHECK-NEXT: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i8*, i32)*)(i8* [[SIX]], i8* [[FIVE]], i8* [[FOUR]], i32 10) // CHECK-NEXT: store i8* [[FOUR]], i8** [[val:%.*]] NSMutableDictionary *dictionary; @@ -40,7 +40,7 @@ int main() { // CHECK-NEXT: [[EIGHT:%.*]] = load i8*, i8** [[KEY:%.*]], align 8 // CHECK-NEXT: [[TEN:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_.4 // CHECK-NEXT: [[ELEVEN:%.*]] = bitcast {{%.*}} [[SEVEN]] to i8* -// CHECK-NEXT: [[CALL1:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*, i8*)*)(i8* noundef [[ELEVEN]], i8* noundef [[TEN]], i8* noundef [[EIGHT]]) +// CHECK-NEXT: [[CALL1:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*, i8*)*)(i8* [[ELEVEN]], i8* [[TEN]], i8* [[EIGHT]]) // CHECK-NEXT: store i8* [[CALL1]], i8** [[oldObject:%.*]], align 8 @@ -50,7 +50,7 @@ int main() { // CHECK-NEXT: [[THIRTEEN:%.*]] = load i8*, i8** [[KEY]], align 8 // CHECK-NEXT: [[SIXTEEN:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_.6 // CHECK-NEXT: [[SEVENTEEN:%.*]] = bitcast {{%.*}} [[TWELVE]] to i8* -// CHECK-NEXT: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i8*, i8*)*)(i8* noundef [[SEVENTEEN]], i8* noundef [[SIXTEEN]], i8* noundef [[FOURTEEN]], i8* noundef [[THIRTEEN]]) +// CHECK-NEXT: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i8*, i8*)*)(i8* [[SEVENTEEN]], i8* [[SIXTEEN]], i8* [[FOURTEEN]], i8* [[THIRTEEN]]) // CHECK-NEXT: store i8* [[FOURTEEN]], i8** [[val:%.*]] } diff --git a/clang/test/CodeGenObjC/objc-literal-tests.m b/clang/test/CodeGenObjC/objc-literal-tests.m index 09561f9fe2d363536acd0a8f79556689371db693..4cb152d1dd3d4f3d5c2e2f16d6e2f9230c0d1a00 100644 --- a/clang/test/CodeGenObjC/objc-literal-tests.m +++ b/clang/test/CodeGenObjC/objc-literal-tests.m @@ -55,31 +55,31 @@ id NSUserName(); // CHECK: define{{.*}} i32 @main() [[NUW:#[0-9]+]] int main() { - // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 noundef signext 97 + // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 signext 97 NSNumber *aNumber = @'a'; - // CHECK: call{{.*}}@objc_msgSend{{.*}}i32 noundef 42 + // CHECK: call{{.*}}@objc_msgSend{{.*}}i32 42 NSNumber *fortyTwo = @42; - // CHECK: call{{.*}}@objc_msgSend{{.*}}i32 noundef -42 + // CHECK: call{{.*}}@objc_msgSend{{.*}}i32 -42 NSNumber *negativeFortyTwo = @-42; - // CHECK: call{{.*}}@objc_msgSend{{.*}}i32 noundef 42 + // CHECK: call{{.*}}@objc_msgSend{{.*}}i32 42 NSNumber *positiveFortyTwo = @+42; - // CHECK: call{{.*}}@objc_msgSend{{.*}}i32 noundef 42 + // CHECK: call{{.*}}@objc_msgSend{{.*}}i32 42 NSNumber *fortyTwoUnsigned = @42u; - // CHECK: call{{.*}}@objc_msgSend{{.*}}i64 noundef 42 + // CHECK: call{{.*}}@objc_msgSend{{.*}}i64 42 NSNumber *fortyTwoLong = @42l; - // CHECK: call{{.*}}@objc_msgSend{{.*}}i64 noundef 42 + // CHECK: call{{.*}}@objc_msgSend{{.*}}i64 42 NSNumber *fortyTwoLongLong = @42ll; - // CHECK: call{{.*}}@objc_msgSend{{.*}}float noundef 0x400921FB60000000 + // CHECK: call{{.*}}@objc_msgSend{{.*}}float 0x400921FB60000000 NSNumber *piFloat = @3.141592654f; - // CHECK: call{{.*}}@objc_msgSend{{.*}}double noundef 0x400921FB54411744 + // CHECK: call{{.*}}@objc_msgSend{{.*}}double 0x400921FB54411744 NSNumber *piDouble = @3.1415926535; - // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 noundef signext 1 + // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 signext 1 NSNumber *yesNumber = @__objc_yes; - // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 noundef signext 0 + // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 signext 0 NSNumber *noNumber = @__objc_no; - // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 noundef signext 1 + // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 signext 1 NSNumber *yesNumber1 = @YES; - // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 noundef signext 0 + // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 signext 0 NSNumber *noNumber1 = @NO; NSDictionary *dictionary = @{@"name" : NSUserName(), @"date" : [NSDate date] }; diff --git a/clang/test/CodeGenObjC/objc-non-trivial-struct-nrvo.m b/clang/test/CodeGenObjC/objc-non-trivial-struct-nrvo.m index 669bf839a561f0a2d5a60c494fa8784a73e70fc2..752f42da53002697d954b388c4264011150b040a 100644 --- a/clang/test/CodeGenObjC/objc-non-trivial-struct-nrvo.m +++ b/clang/test/CodeGenObjC/objc-non-trivial-struct-nrvo.m @@ -23,7 +23,7 @@ typedef struct { // CHECK: define{{.*}} i32 @testTrivial() // CHECK: %[[RETVAL:.*]] = alloca %[[STRUCT_TRIVIAL]], align 4 -// CHECK-NEXT: call void @func0(%[[STRUCT_TRIVIAL]]* noundef %[[RETVAL]]) +// CHECK-NEXT: call void @func0(%[[STRUCT_TRIVIAL]]* %[[RETVAL]]) // CHECK-NOT: memcpy // CHECK: ret i32 % @@ -38,7 +38,7 @@ Trivial testTrivial(void) { void func1(TrivialBig *); // CHECK: define{{.*}} void @testTrivialBig(%[[STRUCT_TRIVIALBIG]]* noalias sret(%[[STRUCT_TRIVIALBIG]]) align 4 %[[AGG_RESULT:.*]]) -// CHECK: call void @func1(%[[STRUCT_TRIVIALBIG]]* noundef %[[AGG_RESULT]]) +// CHECK: call void @func1(%[[STRUCT_TRIVIALBIG]]* %[[AGG_RESULT]]) // CHECK-NEXT: ret void TrivialBig testTrivialBig(void) { @@ -105,7 +105,7 @@ Weak testWeak2(int c) { return b; } -// CHECK: define internal void @"\01-[C1 foo1]"(%[[STRUCT_WEAK]]* noalias sret(%[[STRUCT_WEAK]]) align 8 %[[AGG_RESULT:.*]], %{{.*}}* noundef %{{.*}}, i8* noundef %{{.*}}) +// CHECK: define internal void @"\01-[C1 foo1]"(%[[STRUCT_WEAK]]* noalias sret(%[[STRUCT_WEAK]]) align 8 %[[AGG_RESULT:.*]], %{{.*}}* %{{.*}}, i8* %{{.*}}) // CHECK: %[[NRVO:.*]] = alloca i1, align 1 // CHECK: %[[V0:.*]] = bitcast %[[STRUCT_WEAK]]* %[[AGG_RESULT]] to i8** // CHECK: call void @__default_constructor_8_w0(i8** %[[V0]]) diff --git a/clang/test/CodeGenObjC/objfw.m b/clang/test/CodeGenObjC/objfw.m index bb1a45a0ddb04cfbd9b43247f8545034752a5ae1..3aecbef8a66c568022a8b85f00c65c1b3a2e951c 100644 --- a/clang/test/CodeGenObjC/objfw.m +++ b/clang/test/CodeGenObjC/objfw.m @@ -11,5 +11,5 @@ void test0(void) { // CHECK-LABEL: define{{.*}} void @test0() // CHECK: [[T0:%.*]] = call i8* (i8*, i8*, ...)* @objc_msg_lookup(i8* bitcast (i64* @_OBJC_CLASS_Test0 to i8*), // CHECK-NEXT: [[T1:%.*]] = bitcast i8* (i8*, i8*, ...)* [[T0]] to void (i8*, i8*)* -// CHECK-NEXT: call void [[T1]](i8* noundef bitcast (i64* @_OBJC_CLASS_Test0 to i8*), +// CHECK-NEXT: call void [[T1]](i8* bitcast (i64* @_OBJC_CLASS_Test0 to i8*), // CHECK-NEXT: ret void diff --git a/clang/test/CodeGenObjC/optimize-ivar-offset-load.m b/clang/test/CodeGenObjC/optimize-ivar-offset-load.m index ef9d1fa93c27e60a766d74bbc9fb440a7f3b596e..6f902d79d369d528c578ea40df6e65b37e8d9024 100644 --- a/clang/test/CodeGenObjC/optimize-ivar-offset-load.m +++ b/clang/test/CodeGenObjC/optimize-ivar-offset-load.m @@ -31,7 +31,7 @@ extern void foo(int); // CHECK: [[ADDPTR:%.*]] = getelementptr inbounds i8, i8* [[THREE]], i64 [[IVAR]] // CHECK: [[FOUR:%.*]] = bitcast i8* [[ADDPTR]] to i32* // CHECK: [[FIVE:%.*]] = load i32, i32* [[FOUR]], align 4 -// CHECK: call void @foo(i32 noundef [[FIVE]]) +// CHECK: call void @foo(i32 [[FIVE]]) @implementation SampleClass + (SampleClass*) new { return 0; } diff --git a/clang/test/CodeGenObjC/os_log.m b/clang/test/CodeGenObjC/os_log.m index 1918db590d189b4d336dc58ad1fc9dd7f3f26d7a..fc03f0e6a8db9753ea5629d7ca61c978f039f8a0 100644 --- a/clang/test/CodeGenObjC/os_log.m +++ b/clang/test/CodeGenObjC/os_log.m @@ -37,10 +37,10 @@ void os_log_pack_send(void *); // CHECK: %[[V8:.*]] = ptrtoint %{{.*}}* %[[V7]] to i64 // CHECK: %[[V9:.*]] = load i8*, i8** %[[A_ADDR]], align 8 // CHECK: %[[V10:.*]] = ptrtoint i8* %[[V9]] to i64 -// CHECK: call void @__os_log_helper_1_2_2_8_64_8_64(i8* noundef %{{.*}}, i64 noundef %[[V8]], i64 noundef %[[V10]]) +// CHECK: call void @__os_log_helper_1_2_2_8_64_8_64(i8* %{{.*}}, i64 %[[V8]], i64 %[[V10]]) // CHECK: %[[V11:.*]] = bitcast %{{.*}}* %[[V4]] to i8* // CHECK: call void @llvm.objc.release(i8* %[[V11]]) -// CHECK: call void @os_log_pack_send(i8* noundef %{{.*}}) +// CHECK: call void @os_log_pack_send(i8* %{{.*}}) // CHECK-O2: call void (...) @llvm.objc.clang.arc.use(%{{.*}}* %[[V7]]) // CHECK-O2: %[[V13:.*]] = load %{{.*}}*, %{{.*}}** %[[OS_LOG_ARG]], align 8 // CHECK-O2: %[[V14:.*]] = bitcast %{{.*}}* %[[V13]] to i8* @@ -79,10 +79,10 @@ void test_builtin_os_log2(void *buf, id __unsafe_unretained a) { // CHECK: %[[V5:.*]] = call i8* @llvm.objc.retain(i8* %[[V4]]) // CHECK: store i8* %[[V5]], i8** %[[OS_LOG_ARG]], align 8 // CHECK: %[[V6:.*]] = ptrtoint i8* %[[V5]] to i64 -// CHECK: call void @__os_log_helper_1_2_1_8_64(i8* noundef %{{.*}}, i64 noundef %[[V6]]) +// CHECK: call void @__os_log_helper_1_2_1_8_64(i8* %{{.*}}, i64 %[[V6]]) // CHECK: %[[V7:.*]] = bitcast %{{.*}}* %[[V3]] to i8* // CHECK: call void @llvm.objc.release(i8* %[[V7]]) -// CHECK: call void @os_log_pack_send(i8* noundef %{{.*}}) +// CHECK: call void @os_log_pack_send(i8* %{{.*}}) // CHECK-O2: call void (...) @llvm.objc.clang.arc.use(i8* %[[V5]]) // CHECK-O2: %[[V9:.*]] = load i8*, i8** %[[OS_LOG_ARG]], align 8 // CHECK-O2: call void @llvm.objc.release(i8* %[[V9]]) @@ -107,10 +107,10 @@ void test_builtin_os_log3(void *buf) { // CHECK: %[[V11:.*]] = call i8* @llvm.objc.retain(i8* %[[V10]]) // CHECK: store i8* %[[V11]], i8** %[[OS_LOG_ARG2]], align 8 // CHECK: %[[V12:.*]] = ptrtoint i8* %[[V11]] to i64 -// CHECK: call void @__os_log_helper_1_2_2_8_64_8_64(i8* noundef %{{.*}}, i64 noundef %[[V6]], i64 noundef %[[V12]]) +// CHECK: call void @__os_log_helper_1_2_2_8_64_8_64(i8* %{{.*}}, i64 %[[V6]], i64 %[[V12]]) // CHECK: call void @llvm.objc.release(i8* %[[V10]]) // CHECK: call void @llvm.objc.release(i8* %[[V4]]) -// CHECK: call void @os_log_pack_send(i8* noundef %{{.*}}) +// CHECK: call void @os_log_pack_send(i8* %{{.*}}) // CHECK-O2: call void (...) @llvm.objc.clang.arc.use(i8* %[[V11]]) // CHECK-O2: %[[V14:.*]] = load i8*, i8** %[[OS_LOG_ARG2]], align 8 // CHECK-O2: call void @llvm.objc.release(i8* %[[V14]]) diff --git a/clang/test/CodeGenObjC/parameterized_classes.m b/clang/test/CodeGenObjC/parameterized_classes.m index dbc1059ea8dec2feff0c24b37c2454311aa72983..11df89a3cc9f00ca6f590f0e0491f346907f5b47 100644 --- a/clang/test/CodeGenObjC/parameterized_classes.m +++ b/clang/test/CodeGenObjC/parameterized_classes.m @@ -105,7 +105,7 @@ void blockTest(NSMutableArray *array, NSString *name) { // CHECK: %[[V4:.*]] = load %[[TY]]*, %[[TY]]** %[[D]] // CHECK: store %[[TY]]* %[[V4]], %[[TY]]** %[[TEMP]] // CHECK: %[[V7:.*]] = bitcast %[[TY]]** %[[TEMP]] to i8** -// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i8**)*)(i8* noundef %{{.*}}, i8* noundef %{{.*}}, i8** noundef %[[V7]]) +// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i8**)*)(i8* %{{.*}}, i8* %{{.*}}, i8** %[[V7]]) @interface P0 : NSObject - (void)m0:(ObjectType *)first; diff --git a/clang/test/CodeGenObjC/pass-by-value-noalias.m b/clang/test/CodeGenObjC/pass-by-value-noalias.m index 1f2ba7600f515d0ac633ef9a2b4157a13fe880f3..489c5bb41a4cca639ff4214d29887da9f8b9b6a7 100644 --- a/clang/test/CodeGenObjC/pass-by-value-noalias.m +++ b/clang/test/CodeGenObjC/pass-by-value-noalias.m @@ -17,6 +17,6 @@ struct Foo { Bar *__weak f; }; -// WITH_NOALIAS: define{{.*}} void @take(%struct.Foo* noundef %arg) -// NO_NOALIAS: define{{.*}} void @take(%struct.Foo* noundef %arg) +// WITH_NOALIAS: define{{.*}} void @take(%struct.Foo* %arg) +// NO_NOALIAS: define{{.*}} void @take(%struct.Foo* %arg) void take(struct Foo arg) {} diff --git a/clang/test/CodeGenObjC/property-array-type.m b/clang/test/CodeGenObjC/property-array-type.m index 3a46b9cd72fd32ffe4647b066730537fbee91758..a7f770d173f1946584bf6e8f68fe668ee5efedf0 100644 --- a/clang/test/CodeGenObjC/property-array-type.m +++ b/clang/test/CodeGenObjC/property-array-type.m @@ -27,4 +27,4 @@ typedef struct _GLKMatrix4 GLKMatrix4; // CHECK: [[M:%.*]] = getelementptr inbounds %struct._GLKMatrix4, %struct._GLKMatrix4* [[TMP:%.*]], i32 0, i32 0 // CHECK: [[ARRAYDECAY:%.*]] = getelementptr inbounds [16 x float], [16 x float]* [[M]], i64 0, i64 0 // CHECK: [[SIX:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES -// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, float*)*)(i8* noundef [[SEVEN:%.*]], i8* noundef [[SIX]], float* noundef [[ARRAYDECAY]]) +// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, float*)*)(i8* [[SEVEN:%.*]], i8* [[SIX]], float* [[ARRAYDECAY]]) diff --git a/clang/test/CodeGenObjC/property-atomic-bool.m b/clang/test/CodeGenObjC/property-atomic-bool.m index 4bbb29abca478daf7b0dd3d194f03547c8502d22..b53e8322ab5a7f5a0244c81944c32f9afdc51a90 100644 --- a/clang/test/CodeGenObjC/property-atomic-bool.m +++ b/clang/test/CodeGenObjC/property-atomic-bool.m @@ -5,7 +5,7 @@ // CHECK: %[[TOBOOL:.*]] = trunc i8 %[[ATOMIC_LOAD]] to i1 // CHECK: ret i1 %[[TOBOOL]] -// CHECK: define internal void @"\01-[A0 setP:]"({{.*}} i1 noundef zeroext {{.*}}) +// CHECK: define internal void @"\01-[A0 setP:]"({{.*}} i1 zeroext {{.*}}) // CHECK: store atomic i8 %{{.*}}, i8* %{{.*}} seq_cst, align 1 // CHECK: ret void @@ -14,7 +14,7 @@ // CHECK: %[[TOBOOL:.*]] = trunc i8 %load to i1 // CHECK: ret i1 %[[TOBOOL]] -// CHECK: define internal void @"\01-[A1 setP:]"({{.*}} i1 noundef zeroext %p) +// CHECK: define internal void @"\01-[A1 setP:]"({{.*}} i1 zeroext %p) // CHECK: store atomic i8 %{{.*}}, i8* %{{.*}} unordered, align 1 // CHECK: ret void diff --git a/clang/test/CodeGenObjC/property-ref-cast-to-void.m b/clang/test/CodeGenObjC/property-ref-cast-to-void.m index 6f24d629f540e02d10a6917e233c6ef9eb3c9d95..ae2a4583629bb9a52349cc9bc547ebbffa442733 100644 --- a/clang/test/CodeGenObjC/property-ref-cast-to-void.m +++ b/clang/test/CodeGenObjC/property-ref-cast-to-void.m @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-apple-darwin9 -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis -x objective-c++ -triple x86_64-apple-darwin9 -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin9 -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -x objective-c++ -triple x86_64-apple-darwin9 -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o - %s | FileCheck %s // rdar: // 8399655 @interface TestClass diff --git a/clang/test/CodeGenObjC/property.m b/clang/test/CodeGenObjC/property.m index f9b9d83f73ffa5f5df7e81ec9ef2f2e5d33e4b0f..66564bc72c9f4973534082aa09aa23246e645381 100644 --- a/clang/test/CodeGenObjC/property.m +++ b/clang/test/CodeGenObjC/property.m @@ -60,21 +60,21 @@ void test2() { // CHECK: [[BASE:%.*]] = call [[A:%.*]]* @test2_helper() // CHECK-NEXT: [[SEL:%.*]] = load i8*, i8** // CHECK-NEXT: [[BASETMP:%.*]] = bitcast [[A]]* [[BASE]] to i8* - // CHECK-NEXT: [[LD:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*)(i8* noundef [[BASETMP]], i8* noundef [[SEL]]) + // CHECK-NEXT: [[LD:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*)(i8* [[BASETMP]], i8* [[SEL]]) // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[LD]], 1 // CHECK-NEXT: [[SEL:%.*]] = load i8*, i8** // CHECK-NEXT: [[BASETMP:%.*]] = bitcast [[A]]* [[BASE]] to i8* - // CHECK-NEXT: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i32)*)(i8* noundef [[BASETMP]], i8* noundef [[SEL]], i32 noundef [[ADD]]) + // CHECK-NEXT: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i32)*)(i8* [[BASETMP]], i8* [[SEL]], i32 [[ADD]]) test2_helper().dyn++; // CHECK: [[BASE:%.*]] = call [[A]]* @test2_helper() // CHECK-NEXT: [[SEL:%.*]] = load i8*, i8** // CHECK-NEXT: [[BASETMP:%.*]] = bitcast [[A]]* [[BASE]] to i8* - // CHECK-NEXT: [[LD:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*)(i8* noundef [[BASETMP]], i8* noundef [[SEL]]) + // CHECK-NEXT: [[LD:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*)(i8* [[BASETMP]], i8* [[SEL]]) // CHECK-NEXT: [[ADD:%.*]] = mul nsw i32 [[LD]], 10 // CHECK-NEXT: [[SEL:%.*]] = load i8*, i8** // CHECK-NEXT: [[BASETMP:%.*]] = bitcast [[A]]* [[BASE]] to i8* - // CHECK-NEXT: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i32)*)(i8* noundef [[BASETMP]], i8* noundef [[SEL]], i32 noundef [[ADD]]) + // CHECK-NEXT: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i32)*)(i8* [[BASETMP]], i8* [[SEL]], i32 [[ADD]]) test2_helper().dyn *= 10; } @@ -99,7 +99,7 @@ void test4(Test4 *t) { extern int test4_printf(const char *, ...); // CHECK: [[TMP:%.*]] = call float {{.*}} @objc_msgSend // CHECK-NEXT: [[EXT:%.*]] = fpext float [[TMP]] to double - // CHECK-NEXT: call i32 (i8*, ...) @test4_printf(i8* {{.*}}, double noundef [[EXT]]) + // CHECK-NEXT: call i32 (i8*, ...) @test4_printf(i8* {{.*}}, double [[EXT]]) // CHECK-NEXT: ret void test4_printf("%.2f", t.f); } diff --git a/clang/test/CodeGenObjC/return-objc-object.mm b/clang/test/CodeGenObjC/return-objc-object.mm index ef0bdd5eef9970dfb14de0d1a08a48b75dbec922..d1cbd3da64f8e36dfd37eddebe6ecaf96a48f9d1 100644 --- a/clang/test/CodeGenObjC/return-objc-object.mm +++ b/clang/test/CodeGenObjC/return-objc-object.mm @@ -15,5 +15,5 @@ void call_once() { f(); f1(); } -// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0* @_Z1fv() -// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0* @_Z2f1v() +// CHECK: call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0* @_Z1fv() +// CHECK: call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0* @_Z2f1v() diff --git a/clang/test/CodeGenObjC/stret_lookup.m b/clang/test/CodeGenObjC/stret_lookup.m index 48984204cc5336d8e422bc872d8455afd163d76d..b97adaca00e49ef85e3d2630e43610292889029e 100644 --- a/clang/test/CodeGenObjC/stret_lookup.m +++ b/clang/test/CodeGenObjC/stret_lookup.m @@ -21,9 +21,9 @@ void test0(void) { // HASSTRET-LABEL: define{{.*}} void @test0() // HASSTRET: [[T0:%.*]] = call i8* (i8*, i8*, ...)* @objc_msg_lookup_stret(i8* bitcast (i64* @_OBJC_CLASS_Test0 to i8*), // HASSTRET-NEXT: [[T1:%.*]] = bitcast i8* (i8*, i8*, ...)* [[T0]] to void (%struct.test*, i8*, i8*)* -// HASSTRET-NEXT: call void [[T1]](%struct.test* sret(%struct.test) {{.*}}, i8* noundef bitcast (i64* @_OBJC_CLASS_Test0 to i8*), +// HASSTRET-NEXT: call void [[T1]](%struct.test* sret(%struct.test) {{.*}}, i8* bitcast (i64* @_OBJC_CLASS_Test0 to i8*), // NOSTRET-LABEL: define{{.*}} void @test0() // NOSTRET: [[T0:%.*]] = call i8* (i8*, i8*, ...)* @objc_msg_lookup(i8* // NOSTRET-NEXT: [[T1:%.*]] = bitcast i8* (i8*, i8*, ...)* [[T0]] to void (%struct.test*, i8*, i8*)* -// NOSTRET-NEXT: call void [[T1]](%struct.test* sret(%struct.test) {{.*}}, i8* {{.*}}, i8* noundef bitcast ([2 x { i8*, i8* }]* +// NOSTRET-NEXT: call void [[T1]](%struct.test* sret(%struct.test) {{.*}}, i8* {{.*}}, i8* bitcast ([2 x { i8*, i8* }]* diff --git a/clang/test/CodeGenObjC/strong-in-c-struct.m b/clang/test/CodeGenObjC/strong-in-c-struct.m index c5eae31c74e6c3c300b4bf607f55b3044a561b6e..3d7ce08861507310fa5667354e1bfbfe357911e7 100644 --- a/clang/test/CodeGenObjC/strong-in-c-struct.m +++ b/clang/test/CodeGenObjC/strong-in-c-struct.m @@ -119,7 +119,7 @@ StrongSmall g1, g2; // CHECK: call void @__destructor_8_S_s16_s24(i8** %[[V1]]) // CHECK: ret void -// CHECK: define linkonce_odr hidden void @__default_constructor_8_S_s16_s24(i8** noundef %[[DST:.*]]) +// CHECK: define linkonce_odr hidden void @__default_constructor_8_S_s16_s24(i8** %[[DST:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8 @@ -131,7 +131,7 @@ StrongSmall g1, g2; // CHECK: call void @llvm.memset.p0i8.i64(i8* align 8 %[[V4]], i8 0, i64 8, i1 false) // CHECK: ret void -// CHECK: define linkonce_odr hidden void @__default_constructor_8_s16(i8** noundef %[[DST:.*]]) +// CHECK: define linkonce_odr hidden void @__default_constructor_8_s16(i8** %[[DST:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8 @@ -142,7 +142,7 @@ StrongSmall g1, g2; // CHECK: call void @llvm.memset.p0i8.i64(i8* align 8 %[[V4]], i8 0, i64 8, i1 false) // CHECK: ret void -// CHECK: define linkonce_odr hidden void @__destructor_8_S_s16_s24(i8** noundef %[[DST:.*]]) +// CHECK: define linkonce_odr hidden void @__destructor_8_S_s16_s24(i8** %[[DST:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8 @@ -153,7 +153,7 @@ StrongSmall g1, g2; // CHECK: call void @llvm.objc.storeStrong(i8** %[[V3]], i8* null) // CHECK: ret void -// CHECK: define linkonce_odr hidden void @__destructor_8_s16(i8** noundef %[[DST:.*]]) +// CHECK: define linkonce_odr hidden void @__destructor_8_s16(i8** %[[DST:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8 @@ -167,7 +167,7 @@ void test_constructor_destructor_StrongOuter(void) { StrongOuter t; } -// CHECK: define{{.*}} void @test_copy_constructor_StrongOuter(%[[STRUCT_STRONGOUTER]]* noundef %[[S:.*]]) +// CHECK: define{{.*}} void @test_copy_constructor_StrongOuter(%[[STRUCT_STRONGOUTER]]* %[[S:.*]]) // CHECK: %[[S_ADDR:.*]] = alloca %[[STRUCT_STRONGOUTER]]*, align 8 // CHECK: %[[T:.*]] = alloca %[[STRUCT_STRONGOUTER]], align 8 // CHECK: store %[[STRUCT_STRONGOUTER]]* %[[S]], %[[STRUCT_STRONGOUTER]]** %[[S_ADDR]], align 8 @@ -179,7 +179,7 @@ void test_constructor_destructor_StrongOuter(void) { // CHECK: call void @__destructor_8_S_s16_s24(i8** %[[V3]]) // CHECK: ret void -// CHECK: define linkonce_odr hidden void @__copy_constructor_8_8_S_t0w16_s16_s24_t32w8(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +// CHECK: define linkonce_odr hidden void @__copy_constructor_8_8_S_t0w16_s16_s24_t32w8(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: %[[SRC_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 @@ -208,7 +208,7 @@ void test_constructor_destructor_StrongOuter(void) { // CHECK: store i64 %[[V18]], i64* %[[V16]], align 8 // CHECK: ret void -// CHECK: define linkonce_odr hidden void @__copy_constructor_8_8_t0w16_s16(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +// CHECK: define linkonce_odr hidden void @__copy_constructor_8_8_t0w16_s16(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: %[[SRC_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 @@ -233,7 +233,7 @@ void test_copy_constructor_StrongOuter(StrongOuter *s) { StrongOuter t = *s; } -/// CHECK: define linkonce_odr hidden void @__copy_assignment_8_8_S_t0w16_s16_s24_t32w8(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +/// CHECK: define linkonce_odr hidden void @__copy_assignment_8_8_S_t0w16_s16_s24_t32w8(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: %[[SRC_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 @@ -261,10 +261,10 @@ void test_copy_assignment_StrongOuter(StrongOuter *d, StrongOuter *s) { // CHECK: %[[V9:.*]] = bitcast %[[STRUCT_STRONGOUTER]]* %[[T2]] to i8** // CHECK: call void @__destructor_8_S_s16_s24(i8** %[[V9]]) -// CHECK: define internal void @__Block_byref_object_copy_(i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @__Block_byref_object_copy_(i8* %0, i8* %1) // CHECK: call void @__move_constructor_8_8_S_t0w16_s16_s24_t32w8( -// CHECK: define linkonce_odr hidden void @__move_constructor_8_8_S_t0w16_s16_s24_t32w8(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +// CHECK: define linkonce_odr hidden void @__move_constructor_8_8_S_t0w16_s16_s24_t32w8(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: %[[SRC_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 @@ -282,7 +282,7 @@ void test_copy_assignment_StrongOuter(StrongOuter *d, StrongOuter *s) { // CHECK: store i8* null, i8** %[[V7]], align 8 // CHECK: store i8* %[[V8]], i8** %[[V4]], align 8 -// CHECK: define internal void @__Block_byref_object_dispose_(i8* noundef %0) +// CHECK: define internal void @__Block_byref_object_dispose_(i8* %0) // CHECK: call void @__destructor_8_S_s16_s24( void test_move_constructor_StrongOuter(void) { @@ -290,7 +290,7 @@ void test_move_constructor_StrongOuter(void) { BlockTy b = ^{ (void)t; }; } -// CHECK: define linkonce_odr hidden void @__move_assignment_8_8_S_t0w16_s16_s24_t32w8(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +// CHECK: define linkonce_odr hidden void @__move_assignment_8_8_S_t0w16_s16_s24_t32w8(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: %[[SRC_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 @@ -314,7 +314,7 @@ void test_move_assignment_StrongOuter(StrongOuter *p) { *p = getStrongOuter(); } -// CHECK: define linkonce_odr hidden void @__default_constructor_8_s0_S_s24(i8** noundef %[[DST:.*]]) +// CHECK: define linkonce_odr hidden void @__default_constructor_8_s0_S_s24(i8** %[[DST:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8 @@ -325,7 +325,7 @@ void test_move_assignment_StrongOuter(StrongOuter *p) { // CHECK: %[[V4:.*]] = bitcast i8* %[[V3]] to i8** // CHECK: call void @__default_constructor_8_s16(i8** %[[V4]]) -// CHECK: define linkonce_odr hidden void @__destructor_8_s0_S_s24(i8** noundef %[[DST:.*]]) +// CHECK: define linkonce_odr hidden void @__destructor_8_s0_S_s24(i8** %[[DST:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8 @@ -339,7 +339,7 @@ void test_constructor_destructor_StrongOuter2(void) { StrongOuter2 t; } -// CHECK: define linkonce_odr hidden void @__copy_constructor_8_8_s0_S_t8w16_s24(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +// CHECK: define linkonce_odr hidden void @__copy_constructor_8_8_s0_S_t8w16_s24(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: %[[SRC_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 @@ -361,7 +361,7 @@ void test_copy_constructor_StrongOuter2(StrongOuter2 *s) { StrongOuter2 t = *s; } -// CHECK: define linkonce_odr hidden void @__copy_assignment_8_8_s0_S_t8w16_s24(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +// CHECK: define linkonce_odr hidden void @__copy_assignment_8_8_s0_S_t8w16_s24(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: %[[SRC_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 @@ -382,7 +382,7 @@ void test_copy_assignment_StrongOuter2(StrongOuter2 *d, StrongOuter2 *s) { *d = *s; } -// CHECK: define linkonce_odr hidden void @__move_constructor_8_8_s0_S_t8w16_s24(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +// CHECK: define linkonce_odr hidden void @__move_constructor_8_8_s0_S_t8w16_s24(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: %[[SRC_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 @@ -405,7 +405,7 @@ void test_move_constructor_StrongOuter2(void) { BlockTy b = ^{ (void)t; }; } -// CHECK: define linkonce_odr hidden void @__move_assignment_8_8_s0_S_t8w16_s24(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +// CHECK: define linkonce_odr hidden void @__move_assignment_8_8_s0_S_t8w16_s24(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: %[[SRC_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 @@ -490,7 +490,7 @@ void test_destructor_ignored_result(void) { getStrongSmall(); } -// CHECK: define{{.*}} void @test_destructor_ignored_result2(%{{.*}}* noundef %[[C:.*]]) +// CHECK: define{{.*}} void @test_destructor_ignored_result2(%{{.*}}* %[[C:.*]]) // CHECK: %[[TMP:.*]] = alloca %[[STRUCT_STRONGSMALL]], align 8 // CHECK: %[[CALL:.*]] = call [2 x i64]{{.*}}@objc_msgSend // CHECK: %[[V5:.*]] = bitcast %[[STRUCT_STRONGSMALL]]* %[[TMP]] to [2 x i64]* @@ -507,7 +507,7 @@ void test_destructor_ignored_result2(C *c) { // CHECK: call void @__destructor_8_sb0( // CHECK: ret void -// CHECK: define linkonce_odr hidden void @__copy_constructor_8_8_sb0(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +// CHECK: define linkonce_odr hidden void @__copy_constructor_8_8_sb0(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: %[[SRC_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 @@ -523,10 +523,10 @@ void test_copy_constructor_StrongBlock(StrongBlock *s) { StrongBlock t = *s; } -// CHECK: define{{.*}} void @test_copy_assignment_StrongBlock(%[[STRUCT_STRONGBLOCK]]* noundef %[[D:.*]], %[[STRUCT_STRONGBLOCK]]* noundef %[[S:.*]]) +// CHECK: define{{.*}} void @test_copy_assignment_StrongBlock(%[[STRUCT_STRONGBLOCK]]* %[[D:.*]], %[[STRUCT_STRONGBLOCK]]* %[[S:.*]]) // CHECK: call void @__copy_assignment_8_8_sb0( -// CHECK: define linkonce_odr hidden void @__copy_assignment_8_8_sb0(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +// CHECK: define linkonce_odr hidden void @__copy_assignment_8_8_sb0(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: %[[SRC_ADDR:.*]] = alloca i8**, align 8 // CHECK: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 @@ -591,7 +591,7 @@ void test_copy_constructor_StrongVolatile1(Strong *s) { // CHECK: call void @__destructor_8_s16( // CHECK: ret void -// CHECK: define linkonce_odr hidden void @__copy_helper_block_8_32n13_8_8_t0w16_s16(i8* noundef %0, i8* noundef %1) +// CHECK: define linkonce_odr hidden void @__copy_helper_block_8_32n13_8_8_t0w16_s16(i8* %0, i8* %1) // CHECK: call void @__copy_constructor_8_8_t0w16_s16( // CHECK: ret void @@ -604,7 +604,7 @@ void test_block_capture_Strong(void) { BlockTy b = ^(){ (void)t; }; } -// CHECK: define{{.*}} void @test_variable_length_array(i32 noundef %[[N:.*]]) +// CHECK: define{{.*}} void @test_variable_length_array(i32 %[[N:.*]]) // CHECK: %[[N_ADDR:.*]] = alloca i32, align 4 // CHECK: store i32 %[[N]], i32* %[[N_ADDR]], align 4 // CHECK: %[[V0:.*]] = load i32, i32* %[[N_ADDR]], align 4 @@ -627,7 +627,7 @@ void test_block_capture_Strong(void) { // CHECK: %[[V7]] = bitcast i8* %[[V9]] to i8** // CHECK: br label -// CHECK: call void @func(%[[STRUCT_STRONG]]* noundef %[[VLA]]) +// CHECK: call void @func(%[[STRUCT_STRONG]]* %[[VLA]]) // CHECK: %[[V10:.*]] = getelementptr inbounds %[[STRUCT_STRONG]], %[[STRUCT_STRONG]]* %[[VLA]], i64 %[[V1]] // CHECK: %[[ARRAYDESTROY_ISEMPTY:.*]] = icmp eq %[[STRUCT_STRONG]]* %[[VLA]], %[[V10]] // CHECK: br i1 %[[ARRAYDESTROY_ISEMPTY]], label @@ -659,7 +659,7 @@ void test_constructor_destructor_StructArray(void) { // Test that StructArray's field 'd' is copied before entering the loop. -// CHECK: define linkonce_odr hidden void @__copy_constructor_8_8_t0w8_AB8s24n4_S_t8w16_s24_AE(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +// CHECK: define linkonce_odr hidden void @__copy_constructor_8_8_t0w8_AB8s24n4_S_t8w16_s24_AE(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // CHECK: entry: // CHECK: %[[DST_ADDR:.*]] = alloca i8**, align 8 // CHECK: %[[SRC_ADDR:.*]] = alloca i8**, align 8 @@ -865,7 +865,7 @@ void test_member_access(void) { func(0); } -// CHECK: define{{.*}} void @test_member_access2(%{{.*}}* noundef %[[C:.*]]) +// CHECK: define{{.*}} void @test_member_access2(%{{.*}}* %[[C:.*]]) // CHECK: %[[COERCE:.*]] = alloca %[[STRUCT_STRONGSMALL]], align 8 // CHECK: %[[V8:.*]] = bitcast %[[STRUCT_STRONGSMALL]]* %[[COERCE]] to i8** // CHECK: call void @__destructor_8_s8(i8** %[[V8]]) diff --git a/clang/test/CodeGenObjC/tentative-cfconstantstring.m b/clang/test/CodeGenObjC/tentative-cfconstantstring.m index cfe3a417668c1814cd808f1caca4dee330498399..ed3dbca3aeb7bbe3a5b89914d6db78cfd9e7e5dc 100644 --- a/clang/test/CodeGenObjC/tentative-cfconstantstring.m +++ b/clang/test/CodeGenObjC/tentative-cfconstantstring.m @@ -38,5 +38,5 @@ static inline void _inlineFunction() { // CHECK: [[ZERO:%.*]] = load %struct._class_t*, %struct._class_t** @"OBJC_CLASSLIST_REFERENCES_ // CHECK-NEXT: [[ONE:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK-NEXT: [[TWO:%.*]] = bitcast %struct._class_t* [[ZERO]] to i8* -// CHECK-NEXT: call void (i8*, i8*, [[T:%.*]]*, ...) bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, [[T:%.*]]*, ...)*)(i8* noundef [[TWO]], i8* noundef [[ONE]], [[T:%.*]]* noundef bitcast (%struct.__NSConstantString_tag* @_unnamed_cfstring_{{.*}} to [[T:%.*]]*)) +// CHECK-NEXT: call void (i8*, i8*, [[T:%.*]]*, ...) bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, [[T:%.*]]*, ...)*)(i8* [[TWO]], i8* [[ONE]], [[T:%.*]]* bitcast (%struct.__NSConstantString_tag* @_unnamed_cfstring_{{.*}} to [[T:%.*]]*)) // CHECK-NEXT: ret void diff --git a/clang/test/CodeGenObjC/terminate.m b/clang/test/CodeGenObjC/terminate.m index 6aa50abe28a5765026c54972f315f57b992bc84a..dcd54bcb1254b1f89f74ae436387158e5b175b5b 100644 --- a/clang/test/CodeGenObjC/terminate.m +++ b/clang/test/CodeGenObjC/terminate.m @@ -12,9 +12,9 @@ void test0(void) { // CHECK-WITH-LABEL: define{{.*}} void @test0() // CHECK-WITH-SAME: personality i8* bitcast (i32 (...)* @__gcc_personality_v0 to i8*) // CHECK-WITH: [[PTR:%.*]] = alloca i8*, - // CHECK-WITH: call void @destroy(i8** noundef [[PTR]]) + // CHECK-WITH: call void @destroy(i8** [[PTR]]) // CHECK-WITH-NEXT: ret void - // CHECK-WITH: invoke void @destroy(i8** noundef [[PTR]]) + // CHECK-WITH: invoke void @destroy(i8** [[PTR]]) // CHECK-WITH: landingpad { i8*, i32 } // CHECK-WITH-NEXT: catch i8* null // CHECK-WITH-NEXT: call void @objc_terminate() @@ -22,9 +22,9 @@ void test0(void) { // CHECK-WITHOUT-LABEL: define{{.*}} void @test0() // CHECK-WITHOUT-SAME: personality i8* bitcast (i32 (...)* @__gcc_personality_v0 to i8*) // CHECK-WITHOUT: [[PTR:%.*]] = alloca i8*, - // CHECK-WITHOUT: call void @destroy(i8** noundef [[PTR]]) + // CHECK-WITHOUT: call void @destroy(i8** [[PTR]]) // CHECK-WITHOUT-NEXT: ret void - // CHECK-WITHOUT: invoke void @destroy(i8** noundef [[PTR]]) + // CHECK-WITHOUT: invoke void @destroy(i8** [[PTR]]) // CHECK-WITHOUT: landingpad { i8*, i32 } // CHECK-WITHOUT-NEXT: catch i8* null // CHECK-WITHOUT-NEXT: call void @abort() diff --git a/clang/test/CodeGenObjC/ubsan-bool.m b/clang/test/CodeGenObjC/ubsan-bool.m index 0490100c53f15f40f07c2f910c4757ce53b3ed5e..b30562c4d423354ea7c50e7dd72dc0da0d20c969 100644 --- a/clang/test/CodeGenObjC/ubsan-bool.m +++ b/clang/test/CodeGenObjC/ubsan-bool.m @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -x objective-c -emit-llvm -triple x86_64-apple-macosx10.10.0 -fsanitize=bool %s -o - -w | FileCheck %s -check-prefixes=SHARED,OBJC -// RUN: %clang_cc1 -disable-noundef-analysis -x objective-c++ -emit-llvm -triple x86_64-apple-macosx10.10.0 -fsanitize=bool %s -o - -w | FileCheck %s -check-prefixes=SHARED,OBJC -// RUN: %clang_cc1 -disable-noundef-analysis -x c -emit-llvm -triple x86_64-apple-macosx10.10.0 -fsanitize=bool %s -o - | FileCheck %s -check-prefixes=SHARED,C +// RUN: %clang_cc1 -x objective-c -emit-llvm -triple x86_64-apple-macosx10.10.0 -fsanitize=bool %s -o - -w | FileCheck %s -check-prefixes=SHARED,OBJC +// RUN: %clang_cc1 -x objective-c++ -emit-llvm -triple x86_64-apple-macosx10.10.0 -fsanitize=bool %s -o - -w | FileCheck %s -check-prefixes=SHARED,OBJC +// RUN: %clang_cc1 -x c -emit-llvm -triple x86_64-apple-macosx10.10.0 -fsanitize=bool %s -o - | FileCheck %s -check-prefixes=SHARED,C typedef signed char BOOL; diff --git a/clang/test/CodeGenObjC/ubsan-nonnull.m b/clang/test/CodeGenObjC/ubsan-nonnull.m index 1cf827bcf6cacd01c54fccfd32eae34f869a2cd5..c12edb2f75e019bff04146ff888cd02fa48a7541 100644 --- a/clang/test/CodeGenObjC/ubsan-nonnull.m +++ b/clang/test/CodeGenObjC/ubsan-nonnull.m @@ -13,15 +13,15 @@ @implementation A // CHECK-LABEL: define internal void @"\01-[A one_arg:]" -// CHECK-SAME: i32* noundef nonnull +// CHECK-SAME: i32* nonnull -(void) one_arg: (__attribute__((nonnull)) int *) arg1 {} // CHECK-LABEL: define internal void @"\01-[A varargs:]" -// CHECK-SAME: i32* noundef nonnull +// CHECK-SAME: i32* nonnull -(void) varargs: (__attribute__((nonnull)) int *) arg1, ... {} // CHECK-LABEL: define internal void @"\01+[A clsmethod:]" -// CHECK-SAME: i32* noundef nonnull +// CHECK-SAME: i32* nonnull +(void) clsmethod: (__attribute__((nonnull)) int *) arg1 {} @end @@ -31,18 +31,18 @@ void call_A(A *a, int *p) { // CHECK: [[ICMP:%.*]] = icmp ne i32* [[P1:%.*]], null, !nosanitize // CHECK: br i1 [[ICMP]], {{.*}}, !nosanitize // CHECK: call void @__ubsan_handle_nonnull_arg{{.*}} !nosanitize - // CHECK: call void {{.*}} @objc_msgSend {{.*}} ({{.*}}, i32* noundef [[P1]]) + // CHECK: call void {{.*}} @objc_msgSend {{.*}} ({{.*}}, i32* [[P1]]) [a one_arg: p]; // CHECK: [[ICMP:%.*]] = icmp ne i32* [[P2:%.*]], null, !nosanitize // CHECK: br i1 [[ICMP]], {{.*}}, !nosanitize // CHECK: call void @__ubsan_handle_nonnull_arg{{.*}} !nosanitize - // CHECK: call void {{.*}} @objc_msgSend {{.*}} ({{.*}}, i32* noundef [[P2]], {{.*}}) + // CHECK: call void {{.*}} @objc_msgSend {{.*}} ({{.*}}, i32* [[P2]], {{.*}}) [a varargs: p, p]; // CHECK: [[ICMP:%.*]] = icmp ne i32* [[P3:%.*]], null, !nosanitize // CHECK: br i1 [[ICMP]], {{.*}}, !nosanitize // CHECK: call void @__ubsan_handle_nonnull_arg{{.*}} !nosanitize - // CHECK: call void {{.*}} @objc_msgSend {{.*}} ({{.*}}, i32* noundef [[P3]]) + // CHECK: call void {{.*}} @objc_msgSend {{.*}} ({{.*}}, i32* [[P3]]) [A clsmethod: p]; } diff --git a/clang/test/CodeGenObjC/ubsan-nullability.m b/clang/test/CodeGenObjC/ubsan-nullability.m index 7e714c93c5b53761866cf68347eb38ba6a7dd196..011486cd993931e53f4533eb26f33acfc809baa4 100644 --- a/clang/test/CodeGenObjC/ubsan-nullability.m +++ b/clang/test/CodeGenObjC/ubsan-nullability.m @@ -1,6 +1,6 @@ // REQUIRES: asserts -// RUN: %clang_cc1 -disable-noundef-analysis -x objective-c -emit-llvm -triple x86_64-apple-macosx10.10.0 -fblocks -fobjc-arc -fsanitize=nullability-arg,nullability-assign,nullability-return -w %s -o - | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis -x objective-c++ -emit-llvm -triple x86_64-apple-macosx10.10.0 -fblocks -fobjc-arc -fsanitize=nullability-arg,nullability-assign,nullability-return -w %s -o - | FileCheck %s +// RUN: %clang_cc1 -x objective-c -emit-llvm -triple x86_64-apple-macosx10.10.0 -fblocks -fobjc-arc -fsanitize=nullability-arg,nullability-assign,nullability-return -w %s -o - | FileCheck %s +// RUN: %clang_cc1 -x objective-c++ -emit-llvm -triple x86_64-apple-macosx10.10.0 -fblocks -fobjc-arc -fsanitize=nullability-arg,nullability-assign,nullability-return -w %s -o - | FileCheck %s // CHECK: [[NONNULL_RV_LOC1:@.*]] = private unnamed_addr global {{.*}} i32 100, i32 6 // CHECK: [[NONNULL_ARG_LOC:@.*]] = private unnamed_addr global {{.*}} i32 204, i32 15 {{.*}} i32 190, i32 23 diff --git a/clang/test/CodeGenObjC/weak-in-c-struct.m b/clang/test/CodeGenObjC/weak-in-c-struct.m index 0caf5cc709304c4ffba72e63f9639b0492e681a1..cb6955a6617ba2829efc71b4787ecd91e24b695c 100644 --- a/clang/test/CodeGenObjC/weak-in-c-struct.m +++ b/clang/test/CodeGenObjC/weak-in-c-struct.m @@ -23,7 +23,7 @@ void calleeWeak(Weak); // ARM64: call void @__destructor_8_w8(i8** %[[V1]]) // ARM64: ret void -// ARM64: define linkonce_odr hidden void @__default_constructor_8_w8(i8** noundef %[[DST:.*]]) +// ARM64: define linkonce_odr hidden void @__default_constructor_8_w8(i8** %[[DST:.*]]) // ARM64: %[[DST_ADDR:.*]] = alloca i8**, align 8 // ARM64: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 // ARM64: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8 @@ -33,7 +33,7 @@ void calleeWeak(Weak); // ARM64: %[[V4:.*]] = bitcast i8** %[[V3]] to i8* // ARM64: call void @llvm.memset.p0i8.i64(i8* align 8 %[[V4]], i8 0, i64 8, i1 false) -// ARM64: define linkonce_odr hidden void @__destructor_8_w8(i8** noundef %[[DST:.*]]) +// ARM64: define linkonce_odr hidden void @__destructor_8_w8(i8** %[[DST:.*]]) // ARM64: %[[DST_ADDR:.*]] = alloca i8**, align 8 // ARM64: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 // ARM64: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8 @@ -50,11 +50,11 @@ void test_constructor_destructor_Weak(void) { Weak t; } -// ARM64: define{{.*}} void @test_copy_constructor_Weak(%[[STRUCT_WEAK]]* noundef %{{.*}}) +// ARM64: define{{.*}} void @test_copy_constructor_Weak(%[[STRUCT_WEAK]]* %{{.*}}) // ARM64: call void @__copy_constructor_8_8_t0w4_w8(i8** %{{.*}}, i8** %{{.*}}) // ARM64: call void @__destructor_8_w8(i8** %{{.*}}) -// ARM64: define linkonce_odr hidden void @__copy_constructor_8_8_t0w4_w8(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +// ARM64: define linkonce_odr hidden void @__copy_constructor_8_8_t0w4_w8(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // ARM64: %[[DST_ADDR:.*]] = alloca i8**, align 8 // ARM64: %[[SRC_ADDR:.*]] = alloca i8**, align 8 // ARM64: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 @@ -77,10 +77,10 @@ void test_copy_constructor_Weak(Weak *s) { Weak t = *s; } -// ARM64: define{{.*}} void @test_copy_assignment_Weak(%[[STRUCT_WEAK]]* noundef %{{.*}}, %[[STRUCT_WEAK]]* noundef %{{.*}}) +// ARM64: define{{.*}} void @test_copy_assignment_Weak(%[[STRUCT_WEAK]]* %{{.*}}, %[[STRUCT_WEAK]]* %{{.*}}) // ARM64: call void @__copy_assignment_8_8_t0w4_w8(i8** %{{.*}}, i8** %{{.*}}) -// ARM64: define linkonce_odr hidden void @__copy_assignment_8_8_t0w4_w8(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +// ARM64: define linkonce_odr hidden void @__copy_assignment_8_8_t0w4_w8(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // ARM64: %[[DST_ADDR:.*]] = alloca i8**, align 8 // ARM64: %[[SRC_ADDR:.*]] = alloca i8**, align 8 // ARM64: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 @@ -105,10 +105,10 @@ void test_copy_assignment_Weak(Weak *d, Weak *s) { *d = *s; } -// ARM64: define internal void @__Block_byref_object_copy_(i8* noundef %0, i8* noundef %1) +// ARM64: define internal void @__Block_byref_object_copy_(i8* %0, i8* %1) // ARM64: call void @__move_constructor_8_8_t0w4_w8(i8** %{{.*}}, i8** %{{.*}}) -// ARM64: define linkonce_odr hidden void @__move_constructor_8_8_t0w4_w8(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +// ARM64: define linkonce_odr hidden void @__move_constructor_8_8_t0w4_w8(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // ARM64: %[[DST_ADDR:.*]] = alloca i8**, align 8 // ARM64: %[[SRC_ADDR:.*]] = alloca i8**, align 8 // ARM64: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 @@ -132,10 +132,10 @@ void test_move_constructor_Weak(void) { BlockTy b = ^{ (void)t; }; } -// ARM64: define{{.*}} void @test_move_assignment_Weak(%[[STRUCT_WEAK]]* noundef %{{.*}}) +// ARM64: define{{.*}} void @test_move_assignment_Weak(%[[STRUCT_WEAK]]* %{{.*}}) // ARM64: call void @__move_assignment_8_8_t0w4_w8(i8** %{{.*}}, i8** %{{.*}}) -// ARM64: define linkonce_odr hidden void @__move_assignment_8_8_t0w4_w8(i8** noundef %[[DST:.*]], i8** noundef %[[SRC:.*]]) +// ARM64: define linkonce_odr hidden void @__move_assignment_8_8_t0w4_w8(i8** %[[DST:.*]], i8** %[[SRC:.*]]) // ARM64: %[[DST_ADDR:.*]] = alloca i8**, align 8 // ARM64: %[[SRC_ADDR:.*]] = alloca i8**, align 8 // ARM64: store i8** %[[DST]], i8*** %[[DST_ADDR]], align 8 @@ -161,14 +161,14 @@ void test_move_assignment_Weak(Weak *p) { *p = getWeak(); } -// COMMON: define{{.*}} void @test_parameter_Weak(%[[STRUCT_WEAK]]* noundef %[[A:.*]]) +// COMMON: define{{.*}} void @test_parameter_Weak(%[[STRUCT_WEAK]]* %[[A:.*]]) // COMMON: %[[V0:.*]] = bitcast %[[STRUCT_WEAK]]* %[[A]] to i8** // COMMON: call void @__destructor_{{.*}}(i8** %[[V0]]) void test_parameter_Weak(Weak a) { } -// COMMON: define{{.*}} void @test_argument_Weak(%[[STRUCT_WEAK]]* noundef %[[A:.*]]) +// COMMON: define{{.*}} void @test_argument_Weak(%[[STRUCT_WEAK]]* %[[A:.*]]) // COMMON: %[[A_ADDR:.*]] = alloca %[[STRUCT_WEAK]]* // COMMON: %[[AGG_TMP:.*]] = alloca %[[STRUCT_WEAK]] // COMMON: store %[[STRUCT_WEAK]]* %[[A]], %[[STRUCT_WEAK]]** %[[A_ADDR]] @@ -176,14 +176,14 @@ void test_parameter_Weak(Weak a) { // COMMON: %[[V1:.*]] = bitcast %[[STRUCT_WEAK]]* %[[AGG_TMP]] to i8** // COMMON: %[[V2:.*]] = bitcast %[[STRUCT_WEAK]]* %[[V0]] to i8** // COMMON: call void @__copy_constructor_{{.*}}(i8** %[[V1]], i8** %[[V2]]) -// COMMON: call void @calleeWeak(%[[STRUCT_WEAK]]* noundef %[[AGG_TMP]]) +// COMMON: call void @calleeWeak(%[[STRUCT_WEAK]]* %[[AGG_TMP]]) // COMMON-NEXT: ret void test_argument_Weak(Weak *a) { calleeWeak(*a); } -// COMMON: define{{.*}} void @test_return_Weak(%[[STRUCT_WEAK]]* noalias sret(%[[STRUCT_WEAK]]) align {{.*}} %[[AGG_RESULT:.*]], %[[STRUCT_WEAK]]* noundef %[[A:.*]]) +// COMMON: define{{.*}} void @test_return_Weak(%[[STRUCT_WEAK]]* noalias sret(%[[STRUCT_WEAK]]) align {{.*}} %[[AGG_RESULT:.*]], %[[STRUCT_WEAK]]* %[[A:.*]]) // COMMON: %[[A_ADDR:.*]] = alloca %[[STRUCT_WEAK]]* // COMMON: store %[[STRUCT_WEAK]]* %[[A]], %[[STRUCT_WEAK]]** %[[A_ADDR]] // COMMON: %[[V0:.*]] = load %[[STRUCT_WEAK]]*, %[[STRUCT_WEAK]]** %[[A_ADDR]] @@ -200,7 +200,7 @@ Weak test_return_Weak(Weak *a) { // COMMON: %[[AGG_TMP:.*]] = alloca %[[STRUCT_WEAK]] // COMMON: br i1 -// COMMON: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %[[STRUCT_WEAK]]*)*)({{.*}}, %[[STRUCT_WEAK]]* noundef %[[AGG_TMP]]) +// COMMON: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %[[STRUCT_WEAK]]*)*)({{.*}}, %[[STRUCT_WEAK]]* %[[AGG_TMP]]) // COMMON: br // COMMON: %[[V6:.*]] = bitcast %[[STRUCT_WEAK]]* %[[AGG_TMP]] to i8** diff --git a/clang/test/CodeGenObjCXX/arc-attrs.mm b/clang/test/CodeGenObjCXX/arc-attrs.mm index 4ecfce713df41526bbf1ee6716e523e03a779927..f6da5427f39440878849c9dec8f3f089a4915847 100644 --- a/clang/test/CodeGenObjCXX/arc-attrs.mm +++ b/clang/test/CodeGenObjCXX/arc-attrs.mm @@ -7,12 +7,12 @@ void releaseObject(__attribute__((ns_consumed)) id); // CHECK-LABEL: define{{.*}} void @_Z10sanityTestv void sanityTest() { // CHECK: [[X:%.*]] = alloca i8*, align 8 - // CHECK-NEXT: [[OBJ1:%.*]] = call noundef i8* @_Z11makeObject1v() + // CHECK-NEXT: [[OBJ1:%.*]] = call i8* @_Z11makeObject1v() // CHECK-NEXT: store i8* [[OBJ1]], i8** [[X]], align 8 id x = makeObject1(); - // CHECK-NEXT: [[OBJ2:%.*]] = call noundef i8* @_Z11makeObject2v() - // CHECK-NEXT: call void @_Z13releaseObjectP11objc_object(i8* noundef [[OBJ2]]) + // CHECK-NEXT: [[OBJ2:%.*]] = call i8* @_Z11makeObject2v() + // CHECK-NEXT: call void @_Z13releaseObjectP11objc_object(i8* [[OBJ2]]) releaseObject(makeObject2()); // CHECK-NEXT: call void @llvm.objc.storeStrong(i8** [[X]], i8* null) @@ -31,16 +31,16 @@ void releaseObjectT(__attribute__((ns_consumed)) T); // CHECK-LABEL: define{{.*}} void @_Z12templateTestv void templateTest() { // CHECK: [[X:%.*]] = alloca i8*, align 8 - // CHECK-NEXT: [[OBJ1:%.*]] = call noundef i8* @_Z12makeObjectT1IU8__strongP11objc_objectET_v() + // CHECK-NEXT: [[OBJ1:%.*]] = call i8* @_Z12makeObjectT1IU8__strongP11objc_objectET_v() // CHECK-NEXT: store i8* [[OBJ1]], i8** [[X]], align 8 id x = makeObjectT1(); - // CHECK-NEXT: [[OBJ2:%.*]] = call noundef i8* @_Z12makeObjectT2IU8__strongP11objc_objectET_v() - // CHECK-NEXT: call void @_Z13releaseObjectP11objc_object(i8* noundef [[OBJ2]]) + // CHECK-NEXT: [[OBJ2:%.*]] = call i8* @_Z12makeObjectT2IU8__strongP11objc_objectET_v() + // CHECK-NEXT: call void @_Z13releaseObjectP11objc_object(i8* [[OBJ2]]) releaseObject(makeObjectT2()); - // CHECK-NEXT: [[OBJ3:%.*]] = call noundef i8* @_Z11makeObject1v() - // CHECK-NEXT: call void @_Z14releaseObjectTIU8__strongP11objc_objectEvT_(i8* noundef [[OBJ3]]) + // CHECK-NEXT: [[OBJ3:%.*]] = call i8* @_Z11makeObject1v() + // CHECK-NEXT: call void @_Z14releaseObjectTIU8__strongP11objc_objectEvT_(i8* [[OBJ3]]) releaseObjectT(makeObject1()); // CHECK-NEXT: call void @llvm.objc.storeStrong(i8** [[X]], i8* null) @@ -65,5 +65,5 @@ ForwardConsumed::ForwardConsumed(__attribute__((ns_consumed)) id x) {} // CHECK: store i8* {{.*}}, i8** [[X:%.*]], // CHECK: [[T0:%.*]] = load i8*, i8** [[X]], // CHECK-NEXT: store i8* null, i8** [[X]], -// CHECK-NEXT: call void @_ZN15ForwardConsumedC2EP11objc_object({{.*}}, i8* noundef [[T0]]) +// CHECK-NEXT: call void @_ZN15ForwardConsumedC2EP11objc_object({{.*}}, i8* [[T0]]) // CHECK: call void @llvm.objc.storeStrong(i8** [[X]], i8* null) diff --git a/clang/test/CodeGenObjCXX/arc-blocks.mm b/clang/test/CodeGenObjCXX/arc-blocks.mm index b8040153143f93f410200625ec79b893724b456c..2f07f99df02c568792d817a0822ede94599d26ca 100644 --- a/clang/test/CodeGenObjCXX/arc-blocks.mm +++ b/clang/test/CodeGenObjCXX/arc-blocks.mm @@ -47,7 +47,7 @@ namespace test0 { // CHECK-NEXT: load // CHECK-NEXT: [[T2:%.*]] = bitcast i8* {{.*}} to [[BYREF_A]]* // CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds [[BYREF_A]], [[BYREF_A]]* [[T2]], i32 0, i32 7 - // CHECK-NEXT: call void @_ZN5test01AC1ERKS0_([[A]]* {{[^,]*}} [[T1]], [[A]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[T3]]) + // CHECK-NEXT: call void @_ZN5test01AC1ERKS0_([[A]]* {{[^,]*}} [[T1]], [[A]]* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[T3]]) // CHECK-NEXT: ret void // CHECK: define internal void [[DISPOSE_HELPER]]( @@ -88,13 +88,13 @@ namespace test1 { // CHECK: %[[V11:.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]*, i8*, i8*, i8*, %[[STRUCT_TEST1_S0]], %[[STRUCT_TEST1_S0]], %[[STRUCT_TRIVIAL_INTERNAL]] }>, <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]*, i8*, i8*, i8*, %[[STRUCT_TEST1_S0]], %[[STRUCT_TEST1_S0]], %[[STRUCT_TRIVIAL_INTERNAL]] }>* %[[BLOCK_SOURCE]], i32 0, i32 8 // CHECK: %[[V12:.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]*, i8*, i8*, i8*, %[[STRUCT_TEST1_S0]], %[[STRUCT_TEST1_S0]], %[[STRUCT_TRIVIAL_INTERNAL]] }>, <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]*, i8*, i8*, i8*, %[[STRUCT_TEST1_S0]], %[[STRUCT_TEST1_S0]], %[[STRUCT_TRIVIAL_INTERNAL]] }>* %[[BLOCK_DEST]], i32 0, i32 8 -// CHECK: invoke void @_ZN5test12S0C1ERKS0_(%[[STRUCT_TEST1_S0]]* {{[^,]*}} %[[V12]], %[[STRUCT_TEST1_S0]]* noundef nonnull align 4 dereferenceable(4) %[[V11]]) +// CHECK: invoke void @_ZN5test12S0C1ERKS0_(%[[STRUCT_TEST1_S0]]* {{[^,]*}} %[[V12]], %[[STRUCT_TEST1_S0]]* nonnull align 4 dereferenceable(4) %[[V11]]) // CHECK: to label %[[INVOKE_CONT:.*]] unwind label %[[LPAD:.*]] // CHECK: [[INVOKE_CONT]]: // CHECK: %[[V13:.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]*, i8*, i8*, i8*, %[[STRUCT_TEST1_S0]], %[[STRUCT_TEST1_S0]], %[[STRUCT_TRIVIAL_INTERNAL]] }>, <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]*, i8*, i8*, i8*, %[[STRUCT_TEST1_S0]], %[[STRUCT_TEST1_S0]], %[[STRUCT_TRIVIAL_INTERNAL]] }>* %[[BLOCK_SOURCE]], i32 0, i32 9 // CHECK: %[[V14:.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]*, i8*, i8*, i8*, %[[STRUCT_TEST1_S0]], %[[STRUCT_TEST1_S0]], %[[STRUCT_TRIVIAL_INTERNAL]] }>, <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]*, i8*, i8*, i8*, %[[STRUCT_TEST1_S0]], %[[STRUCT_TEST1_S0]], %[[STRUCT_TRIVIAL_INTERNAL]] }>* %[[BLOCK_DEST]], i32 0, i32 9 -// CHECK: invoke void @_ZN5test12S0C1ERKS0_(%[[STRUCT_TEST1_S0]]* {{[^,]*}} %[[V14]], %[[STRUCT_TEST1_S0]]* noundef nonnull align 4 dereferenceable(4) %[[V13]]) +// CHECK: invoke void @_ZN5test12S0C1ERKS0_(%[[STRUCT_TEST1_S0]]* {{[^,]*}} %[[V14]], %[[STRUCT_TEST1_S0]]* nonnull align 4 dereferenceable(4) %[[V13]]) // CHECK: to label %[[INVOKE_CONT4:.*]] unwind label %[[LPAD3:.*]] // CHECK: [[INVOKE_CONT4]]: diff --git a/clang/test/CodeGenObjCXX/arc-cxx11-init-list.mm b/clang/test/CodeGenObjCXX/arc-cxx11-init-list.mm index cbd942f7d581e77d0451fee8203ff93c0e96e54c..7627139b00d658b169f20cfcad214079ba82808e 100644 --- a/clang/test/CodeGenObjCXX/arc-cxx11-init-list.mm +++ b/clang/test/CodeGenObjCXX/arc-cxx11-init-list.mm @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -triple armv7-ios5.0 -std=c++11 -fmerge-all-constants -fobjc-arc -Os -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple armv7-ios5.0 -std=c++11 -fmerge-all-constants -fobjc-arc -Os -emit-llvm -o - %s | FileCheck %s // CHECK: @[[STR0:.*]] = private unnamed_addr constant [5 x i8] c"str0\00", section "__TEXT,__cstring,cstring_literals" // CHECK: @[[UNNAMED_CFSTRING0:.*]] = private global %struct.__NSConstantString_tag { i32* getelementptr inbounds ([0 x i32], [0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @[[STR0]], i32 0, i32 0), i32 4 }, section "__DATA,__cfstring" diff --git a/clang/test/CodeGenObjCXX/arc-cxx11-member-init.mm b/clang/test/CodeGenObjCXX/arc-cxx11-member-init.mm index ab76951aea3b380485b086619c7377ebbd4edb07..89683ba3a89634feb59a8a5b3f51078a3852589f 100644 --- a/clang/test/CodeGenObjCXX/arc-cxx11-member-init.mm +++ b/clang/test/CodeGenObjCXX/arc-cxx11-member-init.mm @@ -26,7 +26,7 @@ class XClipboardDataSet // CHECK: [[ZERO:%.*]] = load %struct._class_t*, %struct._class_t** @"OBJC_CLASSLIST_REFERENCES_$_" // CHECK: [[ONE:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_ // CHECK: [[TWO:%.*]] = bitcast %struct._class_t* [[ZERO]] to i8* -// CHECK: [[CALL:%.*]] = call noundef i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* noundef [[TWO]], i8* noundef [[ONE]]) +// CHECK: [[CALL:%.*]] = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* [[TWO]], i8* [[ONE]]) // CHECK: [[THREE:%.*]] = bitcast i8* [[CALL]] to [[T:%.*]]* // CHECK: store [[T]]* [[THREE]], [[T]]** [[mClipData]], align 8 @@ -42,4 +42,4 @@ __attribute__((objc_root_class)) @end @implementation Foo @end -// CHECK-NOT: define internal noundef i8* @"\01-[Foo .cxx_construct +// CHECK-NOT: define internal i8* @"\01-[Foo .cxx_construct diff --git a/clang/test/CodeGenObjCXX/arc-exceptions.mm b/clang/test/CodeGenObjCXX/arc-exceptions.mm index 9951dcb225d69d0d2807db299b1376dc24ae8bf6..8814866c5fc0e50bd27cb62ec553f74464c56e0b 100644 --- a/clang/test/CodeGenObjCXX/arc-exceptions.mm +++ b/clang/test/CodeGenObjCXX/arc-exceptions.mm @@ -137,21 +137,21 @@ void test5(void) { // CHECK-NEXT: store [2 x i8*]* [[A0]], // CHECK-NEXT: [[A00:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[A0]], i64 0, i64 0 // CHECK-NEXT: store i8** [[A00]], -// CHECK-NEXT: [[T0:%.*]] = invoke noundef i8* @_Z12test5_helperj(i32 noundef 0) +// CHECK-NEXT: [[T0:%.*]] = invoke i8* @_Z12test5_helperj(i32 0) // CHECK: store i8* [[T0]], i8** [[A00]], align // CHECK-NEXT: [[A01:%.*]] = getelementptr inbounds i8*, i8** [[A00]], i64 1 // CHECK-NEXT: store i8** [[A01]], -// CHECK-NEXT: [[T0:%.*]] = invoke noundef i8* @_Z12test5_helperj(i32 noundef 1) +// CHECK-NEXT: [[T0:%.*]] = invoke i8* @_Z12test5_helperj(i32 1) // CHECK: store i8* [[T0]], i8** [[A01]], align // CHECK-NEXT: [[A1:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[A0]], i64 1 // CHECK-NEXT: store [2 x i8*]* [[A1]], // CHECK-NEXT: [[A10:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[A1]], i64 0, i64 0 // CHECK-NEXT: store i8** [[A10]], -// CHECK-NEXT: [[T0:%.*]] = invoke noundef i8* @_Z12test5_helperj(i32 noundef 2) +// CHECK-NEXT: [[T0:%.*]] = invoke i8* @_Z12test5_helperj(i32 2) // CHECK: store i8* [[T0]], i8** [[A10]], align // CHECK-NEXT: [[A11:%.*]] = getelementptr inbounds i8*, i8** [[A10]], i64 1 // CHECK-NEXT: store i8** [[A11]], -// CHECK-NEXT: [[T0:%.*]] = invoke noundef i8* @_Z12test5_helperj(i32 noundef 3) +// CHECK-NEXT: [[T0:%.*]] = invoke i8* @_Z12test5_helperj(i32 3) // CHECK: store i8* [[T0]], i8** [[A11]], align // CHECK: attributes [[NUW]] = { nounwind } diff --git a/clang/test/CodeGenObjCXX/arc-forwarded-lambda-call.mm b/clang/test/CodeGenObjCXX/arc-forwarded-lambda-call.mm index 07d958f7d42c7bce96099a4baea35355ae5f08b7..37a68136dd56dba2152f30b3651664f29a99c657 100644 --- a/clang/test/CodeGenObjCXX/arc-forwarded-lambda-call.mm +++ b/clang/test/CodeGenObjCXX/arc-forwarded-lambda-call.mm @@ -3,8 +3,8 @@ void test0(id x) { extern void test0_helper(id (^)(void)); test0_helper([=]() { return x; }); - // CHECK-LABEL: define internal noundef i8* @___Z5test0P11objc_object_block_invoke - // CHECK: [[T0:%.*]] = call noundef i8* @"_ZZ5test0P11objc_objectENK3$_0clEv" + // CHECK-LABEL: define internal i8* @___Z5test0P11objc_object_block_invoke + // CHECK: [[T0:%.*]] = call i8* @"_ZZ5test0P11objc_objectENK3$_0clEv" // CHECK-NEXT: [[T1:%.*]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[T0]]) // CHECK-NEXT: [[T2:%.*]] = tail call i8* @llvm.objc.autoreleaseReturnValue(i8* [[T1]]) // CHECK-NEXT: ret i8* [[T2]] @@ -26,8 +26,8 @@ id test1_rv; void test1() { extern void test1_helper(id (*)(void)); test1_helper([](){ return test1_rv; }); - // CHECK-LABEL: define internal noundef i8* @"_ZZ5test1vEN3$_18__invokeEv" - // CHECK: [[T0:%.*]] = call noundef i8* @"_ZZ5test1vENK3$_1clEv" + // CHECK-LABEL: define internal i8* @"_ZZ5test1vEN3$_18__invokeEv" + // CHECK: [[T0:%.*]] = call i8* @"_ZZ5test1vENK3$_1clEv" // CHECK-NEXT: [[T1:%.*]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[T0]]) // CHECK-NEXT: [[T2:%.*]] = tail call i8* @llvm.objc.autoreleaseReturnValue(i8* [[T1]]) // CHECK-NEXT: ret i8* [[T2]] diff --git a/clang/test/CodeGenObjCXX/arc-globals.mm b/clang/test/CodeGenObjCXX/arc-globals.mm index 9385a997623f5136e59ac5e66b19649dd129b56b..d5116ee96c93b768e090685e938b65871f5e5124 100644 --- a/clang/test/CodeGenObjCXX/arc-globals.mm +++ b/clang/test/CodeGenObjCXX/arc-globals.mm @@ -6,14 +6,14 @@ id getObject(); // CHECK-LABEL: define internal void @__cxx_global_var_init -// CHECK: call noundef i8* @_Z9getObjectv +// CHECK: call i8* @_Z9getObjectv // CHECK-NEXT: call i8* @llvm.objc.retainAutoreleasedReturnValue // CHECK-NEXT: {{store i8*.*@global_obj}} // CHECK-NEXT: ret void id global_obj = getObject(); // CHECK-LABEL: define internal void @__cxx_global_var_init -// CHECK: call noundef i8* @_Z9getObjectv +// CHECK: call i8* @_Z9getObjectv // CHECK-NEXT: call i8* @llvm.objc.retainAutoreleasedReturnValue // CHECK-NEXT: {{store i8*.*@global_obj2}} // CHECK-NEXT: ret void diff --git a/clang/test/CodeGenObjCXX/arc-list-init-destruct.mm b/clang/test/CodeGenObjCXX/arc-list-init-destruct.mm index 857cee7b04b2e471061e89b5b2dc34749d7202a4..0db96faec995884d3cb067b8a374ee793a38dbfe 100644 --- a/clang/test/CodeGenObjCXX/arc-list-init-destruct.mm +++ b/clang/test/CodeGenObjCXX/arc-list-init-destruct.mm @@ -24,7 +24,7 @@ bool getBool() { Class0 *g; // CHECK: define {{.*}} @_Z4testv() -// CHECK: invoke noundef zeroext i1 @_Z7getBoolv() +// CHECK: invoke zeroext i1 @_Z7getBoolv() // CHECK: landingpad { i8*, i32 } // CHECK: call void @_ZN6Class1D1Ev(%[[STRUCT_CLASS1]]* {{[^,]*}} %{{.*}}) // CHECK: br label diff --git a/clang/test/CodeGenObjCXX/arc-mangle.mm b/clang/test/CodeGenObjCXX/arc-mangle.mm index 8f3219f194619042a4d34fe0ee0161722bde839b..b061b3f63774eaab2b46b24cb14df19d4f67b56e 100644 --- a/clang/test/CodeGenObjCXX/arc-mangle.mm +++ b/clang/test/CodeGenObjCXX/arc-mangle.mm @@ -1,21 +1,21 @@ // RUN: %clang_cc1 -fobjc-arc -fobjc-runtime-has-weak -triple %itanium_abi_triple -emit-llvm -fblocks -o - %s | FileCheck %s // RUN: %clang_cc1 -DTEST_UNALIGNED -fms-extensions -fobjc-arc -fobjc-runtime-has-weak -triple %itanium_abi_triple -emit-llvm -fblocks -o - %s | FileCheck %s --check-prefix=UNALIGNED -// CHECK-LABEL: define {{.*}}void @_Z1fPU8__strongP11objc_object(i8** noundef %0) +// CHECK-LABEL: define {{.*}}void @_Z1fPU8__strongP11objc_object(i8** %0) void f(__strong id *) {} -// CHECK-LABEL: define {{.*}}void @_Z1fPU6__weakP11objc_object(i8** noundef %0) +// CHECK-LABEL: define {{.*}}void @_Z1fPU6__weakP11objc_object(i8** %0) void f(__weak id *) {} -// CHECK-LABEL: define {{.*}}void @_Z1fPU15__autoreleasingP11objc_object(i8** noundef %0) +// CHECK-LABEL: define {{.*}}void @_Z1fPU15__autoreleasingP11objc_object(i8** %0) void f(__autoreleasing id *) {} -// CHECK-LABEL: define {{.*}}void @_Z1fPP11objc_object(i8** noundef %0) +// CHECK-LABEL: define {{.*}}void @_Z1fPP11objc_object(i8** %0) void f(__unsafe_unretained id *) {} -// CHECK-LABEL: define {{.*}}void @_Z1fPU8__strongKP11objc_object(i8** noundef %0) +// CHECK-LABEL: define {{.*}}void @_Z1fPU8__strongKP11objc_object(i8** %0) void f(const __strong id *) {} -// CHECK-LABEL: define {{.*}}void @_Z1fPU6__weakKP11objc_object(i8** noundef %0) +// CHECK-LABEL: define {{.*}}void @_Z1fPU6__weakKP11objc_object(i8** %0) void f(const __weak id *) {} -// CHECK-LABEL: define {{.*}}void @_Z1fPU15__autoreleasingKP11objc_object(i8** noundef %0) +// CHECK-LABEL: define {{.*}}void @_Z1fPU15__autoreleasingKP11objc_object(i8** %0) void f(const __autoreleasing id *) {} -// CHECK-LABEL: define {{.*}}void @_Z1fPKP11objc_object(i8** noundef %0) +// CHECK-LABEL: define {{.*}}void @_Z1fPKP11objc_object(i8** %0) void f(const __unsafe_unretained id *) {} // CHECK-LABEL: define {{.*}}void @_Z1fPFU19ns_returns_retainedP11objc_objectvE void f(__attribute__((ns_returns_retained)) id (*fn)()) {} @@ -35,10 +35,10 @@ templatevoid g(unsigned_c(unsigned_c *); #if TEST_UNALIGNED -// UNALIGNED-LABEL: define {{.*}}void @_Z1gPU6__weakU11__unalignedP11objc_object(i8** noundef %0) +// UNALIGNED-LABEL: define {{.*}}void @_Z1gPU6__weakU11__unalignedP11objc_object(i8** %0) void g(__weak __unaligned id *) {} -// UNALIGNED-LABEL: define {{.*}}void @_Z1gPU11__unalignedU8__strongP11objc_object(i8** noundef %0) +// UNALIGNED-LABEL: define {{.*}}void @_Z1gPU11__unalignedU8__strongP11objc_object(i8** %0) void g(__strong __unaligned id *) {} -// UNALIGNED-LABEL: define {{.*}}void @_Z1gPU11__unalignedU15__autoreleasingP11objc_object(i8** noundef %0) +// UNALIGNED-LABEL: define {{.*}}void @_Z1gPU11__unalignedU15__autoreleasingP11objc_object(i8** %0) void g(__autoreleasing __unaligned id *) {} #endif // TEST_UNALIGNED diff --git a/clang/test/CodeGenObjCXX/arc-marker-funclet.mm b/clang/test/CodeGenObjCXX/arc-marker-funclet.mm index 5f0c481a0d30af3b02b6e88e1636d51bc3f29713..900c2788daedba15cd04d3b73b11a9ea8576e91c 100644 --- a/clang/test/CodeGenObjCXX/arc-marker-funclet.mm +++ b/clang/test/CodeGenObjCXX/arc-marker-funclet.mm @@ -10,7 +10,7 @@ void g() { } } -// CHECK: call noundef i8* @"?f@@YAPAUobjc_object@@XZ"() [ "funclet"(token %1) ] +// CHECK: call i8* @"?f@@YAPAUobjc_object@@XZ"() [ "funclet"(token %1) ] // CHECK-NEXT: call void asm sideeffect "movl{{.*}}%ebp, %ebp{{.*}}", ""() [ "funclet"(token %1) ] // The corresponding f() call was invoked from the entry basic block. diff --git a/clang/test/CodeGenObjCXX/arc-move.mm b/clang/test/CodeGenObjCXX/arc-move.mm index 3b000226578f848ec9a097fb276b3ae501786f1f..af6cce56dddb788a9e601129449426c5f477d3e2 100644 --- a/clang/test/CodeGenObjCXX/arc-move.mm +++ b/clang/test/CodeGenObjCXX/arc-move.mm @@ -33,7 +33,7 @@ typename remove_reference::type&& move(T &&x) { // CHECK-LABEL: define{{.*}} void @_Z12library_moveRU8__strongP11objc_objectS2_ void library_move(__strong id &x, __strong id &y) { - // CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i8** @_Z4moveIRU8__strongP11objc_objectEON16remove_referenceIT_E4typeEOS5_ + // CHECK: call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i8** @_Z4moveIRU8__strongP11objc_objectEON16remove_referenceIT_E4typeEOS5_ // CHECK: load i8*, i8** // CHECK: store i8* null, i8** // CHECK: load i8**, i8*** @@ -50,7 +50,7 @@ void library_move(__strong id &y) { // CHECK: [[I:%.*]] = alloca i32, align 4 // CHECK: [[XPTR1:%.*]] = bitcast i8** [[X]] to i8* // CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[XPTR1]]) - // CHECK: [[Y:%[a-zA-Z0-9]+]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i8** @_Z4moveIRU8__strongP11objc_objectEON16remove_referenceIT_E4typeEOS5_ + // CHECK: [[Y:%[a-zA-Z0-9]+]] = call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i8** @_Z4moveIRU8__strongP11objc_objectEON16remove_referenceIT_E4typeEOS5_ // Load the object // CHECK-NEXT: [[OBJ:%[a-zA-Z0-9]+]] = load i8*, i8** [[Y]] // Null out y @@ -75,7 +75,7 @@ void library_move(__strong id &y) { // CHECK-LABEL: define{{.*}} void @_Z10const_moveRU8__strongKP11objc_object( void const_move(const __strong id &x) { // CHECK: [[Y:%.*]] = alloca i8*, - // CHECK: [[X:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i8** @_Z4moveIRU8__strongKP11objc_objectEON16remove_referenceIT_E4typeEOS5_( + // CHECK: [[X:%.*]] = call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i8** @_Z4moveIRU8__strongKP11objc_objectEON16remove_referenceIT_E4typeEOS5_( // CHECK-NEXT: [[T0:%.*]] = load i8*, i8** [[X]] // CHECK-NEXT: [[T1:%.*]] = call i8* @llvm.objc.retain(i8* [[T0]]) // CHECK-NEXT: store i8* [[T1]], i8** [[Y]] diff --git a/clang/test/CodeGenObjCXX/arc-new-delete.mm b/clang/test/CodeGenObjCXX/arc-new-delete.mm index 3387270536eb7aa7301137835ece3acb1d398f01..5760eed18c1fabf614c63a4de44a8ca59a31431f 100644 --- a/clang/test/CodeGenObjCXX/arc-new-delete.mm +++ b/clang/test/CodeGenObjCXX/arc-new-delete.mm @@ -12,32 +12,32 @@ void test_new(id invalue) { // OPT-NEXT: [[T0:%.*]] = call i8* @llvm.objc.retain(i8* [[INVALUE:%.*]]) // OPT-NEXT: store i8* [[T0]], i8** [[INVALUEADDR]] - // CHECK: [[CALL:%.*]] = call noalias noundef nonnull i8* @_Znwm + // CHECK: [[CALL:%.*]] = call noalias nonnull i8* @_Znwm // CHECK-NEXT: {{bitcast i8\*.*to i8\*\*}} // CHECK-NEXT: store i8* null, i8** new strong_id; - // CHECK: [[CALL:%.*]] = call noalias noundef nonnull i8* @_Znwm + // CHECK: [[CALL:%.*]] = call noalias nonnull i8* @_Znwm // CHECK-NEXT: {{bitcast i8\*.*to i8\*\*}} // UNOPT-NEXT: store i8* null, i8** // OPT-NEXT: call i8* @llvm.objc.initWeak(i8** {{.*}}, i8* null) new weak_id; - // CHECK: [[CALL:%.*]] = call noalias noundef nonnull i8* @_Znwm + // CHECK: [[CALL:%.*]] = call noalias nonnull i8* @_Znwm // CHECK-NEXT: {{bitcast i8\*.*to i8\*\*}} // CHECK-NEXT: store i8* null, i8** new __strong id; - // CHECK: [[CALL:%.*]] = call noalias noundef nonnull i8* @_Znwm + // CHECK: [[CALL:%.*]] = call noalias nonnull i8* @_Znwm // CHECK-NEXT: {{bitcast i8\*.*to i8\*\*}} // UNOPT-NEXT: store i8* null, i8** // OPT-NEXT: call i8* @llvm.objc.initWeak(i8** {{.*}}, i8* null) new __weak id; - // CHECK: [[CALL:%.*]] = call noalias noundef nonnull i8* @_Znwm + // CHECK: [[CALL:%.*]] = call noalias nonnull i8* @_Znwm // CHECK: call i8* @llvm.objc.retain // CHECK: store i8* new __strong id(invalue); - // CHECK: [[CALL:%.*]] = call noalias noundef nonnull i8* @_Znwm + // CHECK: [[CALL:%.*]] = call noalias nonnull i8* @_Znwm // CHECK: call i8* @llvm.objc.initWeak new __weak id(invalue); @@ -48,12 +48,12 @@ void test_new(id invalue) { // CHECK-LABEL: define{{.*}} void @_Z14test_array_new void test_array_new() { - // CHECK: call noalias noundef nonnull i8* @_Znam + // CHECK: call noalias nonnull i8* @_Znam // CHECK: store i64 17, i64* // CHECK: call void @llvm.memset.p0i8.i64 new strong_id[17]; - // CHECK: call noalias noundef nonnull i8* @_Znam + // CHECK: call noalias nonnull i8* @_Znam // CHECK: store i64 17, i64* // CHECK: call void @llvm.memset.p0i8.i64 new weak_id[17]; diff --git a/clang/test/CodeGenObjCXX/arc-references.mm b/clang/test/CodeGenObjCXX/arc-references.mm index 48b778e4f6e790edaa4f77a3ebf0896b11967132..250e27d4c6dd7d9a49972b85407c4a3155302007 100644 --- a/clang/test/CodeGenObjCXX/arc-references.mm +++ b/clang/test/CodeGenObjCXX/arc-references.mm @@ -9,12 +9,12 @@ void callee(); // Lifetime extension for binding a reference to an rvalue // CHECK-LABEL: define{{.*}} void @_Z5test0v() void test0() { - // CHECK: call noundef i8* @_Z9getObjectv + // CHECK: call i8* @_Z9getObjectv // CHECK-NEXT: call i8* @llvm.objc.retainAutoreleasedReturnValue const __strong id &ref1 = getObject(); // CHECK: call void @_Z6calleev callee(); - // CHECK: call noundef i8* @_Z9getObjectv + // CHECK: call i8* @_Z9getObjectv // CHECK-NEXT: call i8* @llvm.objc.retainAutoreleasedReturnValue // CHECK-NEXT: call i8* @llvm.objc.autorelease const __autoreleasing id &ref2 = getObject(); @@ -84,7 +84,7 @@ void test5(__strong id &x) { } // CHECK-LABEL: define internal void @__cxx_global_var_init( -// CHECK: call noundef i8* @_Z9getObjectv +// CHECK: call i8* @_Z9getObjectv // CHECK-NEXT: call i8* @llvm.objc.retainAutoreleasedReturnValue const __strong id &global_ref = getObject(); diff --git a/clang/test/CodeGenObjCXX/arc-rv-attr.mm b/clang/test/CodeGenObjCXX/arc-rv-attr.mm index c982be13ae20e9831e69efc7fd1e73cca3a93cff..85d5787d50dceec5d9d6f4484e0ceac85d9f0730 100644 --- a/clang/test/CodeGenObjCXX/arc-rv-attr.mm +++ b/clang/test/CodeGenObjCXX/arc-rv-attr.mm @@ -3,7 +3,7 @@ id foo(void); // CHECK-LABEL: define{{.*}} void @_Z14test_list_initv( -// CHECK: %[[CALL1:.*]] = call noundef i8* @_Z3foov() [ "clang.arc.attachedcall"(i8* (i8*)* @llvm.objc.retainAutoreleasedReturnValue) ] +// CHECK: %[[CALL1:.*]] = call i8* @_Z3foov() [ "clang.arc.attachedcall"(i8* (i8*)* @llvm.objc.retainAutoreleasedReturnValue) ] // CHECK: call i8* @llvm.objc.retain(i8* %[[CALL1]]) void test_list_init() { diff --git a/clang/test/CodeGenObjCXX/arc-special-member-functions.mm b/clang/test/CodeGenObjCXX/arc-special-member-functions.mm index a1ab43dde3fc36fbc95b9ffd3bbc5bb4d20f2f3f..9c001eac3724d2356c545d55098f9794d5e6b4ed 100644 --- a/clang/test/CodeGenObjCXX/arc-special-member-functions.mm +++ b/clang/test/CodeGenObjCXX/arc-special-member-functions.mm @@ -151,7 +151,7 @@ void test_ObjCBlockMember_copy_assign(ObjCBlockMember m1, ObjCBlockMember m2) { } // Implicitly-generated copy assignment operator for ObjCBlockMember -// CHECK: define linkonce_odr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) {{%.*}}* @_ZN15ObjCBlockMemberaSERKS_( +// CHECK: define linkonce_odr nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) {{%.*}}* @_ZN15ObjCBlockMemberaSERKS_( // CHECK: [[T0:%.*]] = getelementptr inbounds [[T:%.*]], [[T:%.*]]* {{%.*}}, i32 0, i32 0 // CHECK-NEXT: [[T1:%.*]] = load i32 (i32)*, i32 (i32)** [[T0]], align 8 // CHECK-NEXT: [[T2:%.*]] = bitcast i32 (i32)* [[T1]] to i8* diff --git a/clang/test/CodeGenObjCXX/arc.mm b/clang/test/CodeGenObjCXX/arc.mm index 93c0a63504cacfaf9502c0371ea099064ea212d7..bb576b051161d2a810f4e145f7d9d14237c39b3d 100644 --- a/clang/test/CodeGenObjCXX/arc.mm +++ b/clang/test/CodeGenObjCXX/arc.mm @@ -19,7 +19,7 @@ void test0(__weak id *wp, __weak volatile id *wvp) { // TODO: this is sub-optimal, we should retain at the actual call site. // TODO: in the non-volatile case, we do not need to be reloading. - // CHECK: [[T0:%.*]] = call noundef i8* @_Z12test0_helperv() + // CHECK: [[T0:%.*]] = call i8* @_Z12test0_helperv() // CHECK-NEXT: [[T1:%.*]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[T0]]) // CHECK-NEXT: [[T2:%.*]] = load i8**, i8*** {{%.*}}, align 8 // CHECK-NEXT: [[T3:%.*]] = call i8* @llvm.objc.storeWeak(i8** [[T2]], i8* [[T1]]) @@ -28,7 +28,7 @@ void test0(__weak id *wp, __weak volatile id *wvp) { // CHECK-NEXT: call void @llvm.objc.release(i8* [[T1]]) id x = *wp = test0_helper(); - // CHECK: [[T0:%.*]] = call noundef i8* @_Z12test0_helperv() + // CHECK: [[T0:%.*]] = call i8* @_Z12test0_helperv() // CHECK-NEXT: [[T1:%.*]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[T0]]) // CHECK-NEXT: [[T2:%.*]] = load i8**, i8*** {{%.*}}, align 8 // CHECK-NEXT: [[T3:%.*]] = call i8* @llvm.objc.storeWeak(i8** [[T2]], i8* [[T1]]) @@ -42,7 +42,7 @@ void test0(__weak id *wp, __weak volatile id *wvp) { struct Test1_helper { Test1_helper(); }; @interface Test1 @end @implementation Test1 { Test1_helper x; } @end -// CHECK: define internal noundef i8* @"\01-[Test1 .cxx_construct]"( +// CHECK: define internal i8* @"\01-[Test1 .cxx_construct]"( // CHECK: call void @_ZN12Test1_helperC1Ev( // CHECK-NEXT: load // CHECK-NEXT: bitcast @@ -81,7 +81,7 @@ void test34(int cond) { // CHECK-NEXT: store i8* [[T0]], i8** [[TEMP1]] // CHECK-NEXT: br label // CHECK: [[W0:%.*]] = phi i8* [ [[T0]], {{%.*}} ], [ undef, {{%.*}} ] - // CHECK: call void @_Z11test34_sinkPU15__autoreleasingP11objc_object(i8** noundef [[T1]]) + // CHECK: call void @_Z11test34_sinkPU15__autoreleasingP11objc_object(i8** [[T1]]) // CHECK-NEXT: [[T0:%.*]] = icmp eq i8** [[ARG]], null // CHECK-NEXT: br i1 [[T0]], // CHECK: [[T0:%.*]] = load i8*, i8** [[TEMP1]] @@ -104,7 +104,7 @@ void test34(int cond) { // CHECK-NEXT: store i1 true, i1* [[CONDCLEANUP]] // CHECK-NEXT: store i8* [[T0]], i8** [[TEMP2]] // CHECK-NEXT: br label - // CHECK: call void @_Z11test34_sinkPU15__autoreleasingP11objc_object(i8** noundef [[T1]]) + // CHECK: call void @_Z11test34_sinkPU15__autoreleasingP11objc_object(i8** [[T1]]) // CHECK-NEXT: [[T0:%.*]] = icmp eq i8** [[ARG]], null // CHECK-NEXT: br i1 [[T0]], // CHECK: [[T0:%.*]] = load i8*, i8** [[TEMP2]] @@ -125,25 +125,25 @@ struct Test35_Helper { // CHECK-LABEL: define{{.*}} void @_Z6test3513Test35_HelperPS_ void test35(Test35_Helper x0, Test35_Helper *x0p) { // CHECK: call void @llvm.lifetime.start - // CHECK: call noundef i8* @_ZN13Test35_Helper11makeObject1Ev + // CHECK: call i8* @_ZN13Test35_Helper11makeObject1Ev // CHECK-NOT: call i8* @llvm.objc.retain id obj1 = Test35_Helper::makeObject1(); // CHECK: call void @llvm.lifetime.start - // CHECK: call noundef i8* @_ZN13Test35_Helper11makeObject2Ev + // CHECK: call i8* @_ZN13Test35_Helper11makeObject2Ev // CHECK-NOT: call i8* @llvm.objc.retain id obj2 = x0.makeObject2(); // CHECK: call void @llvm.lifetime.start - // CHECK: call noundef i8* @_ZN13Test35_Helper11makeObject2Ev + // CHECK: call i8* @_ZN13Test35_Helper11makeObject2Ev // CHECK-NOT: call i8* @llvm.objc.retain id obj3 = x0p->makeObject2(); id (Test35_Helper::*pmf)() __attribute__((ns_returns_retained)) = &Test35_Helper::makeObject2; // CHECK: call void @llvm.lifetime.start - // CHECK: call noundef i8* % + // CHECK: call i8* % // CHECK-NOT: call i8* @llvm.objc.retain id obj4 = (x0.*pmf)(); // CHECK: call void @llvm.lifetime.start - // CHECK: call noundef i8* % + // CHECK: call i8* % // CHECK-NOT: call i8* @llvm.objc.retain id obj5 = (x0p->*pmf)(); @@ -163,24 +163,24 @@ void test35(Test35_Helper x0, Test35_Helper *x0p) { // CHECK-LABEL: define{{.*}} void @_Z7test35b13Test35_HelperPS_ void test35b(Test35_Helper x0, Test35_Helper *x0p) { // CHECK: call void @llvm.lifetime.start - // CHECK: call noundef i8* @_ZN13Test35_Helper11makeObject3Ev + // CHECK: call i8* @_ZN13Test35_Helper11makeObject3Ev // CHECK: call i8* @llvm.objc.retain id obj1 = Test35_Helper::makeObject3(); // CHECK: call void @llvm.lifetime.start - // CHECK: call noundef i8* @_ZN13Test35_Helper11makeObject4Ev + // CHECK: call i8* @_ZN13Test35_Helper11makeObject4Ev // CHECK: call i8* @llvm.objc.retain id obj2 = x0.makeObject4(); // CHECK: call void @llvm.lifetime.start - // CHECK: call noundef i8* @_ZN13Test35_Helper11makeObject4Ev + // CHECK: call i8* @_ZN13Test35_Helper11makeObject4Ev // CHECK: call i8* @llvm.objc.retain id obj3 = x0p->makeObject4(); id (Test35_Helper::*pmf)() = &Test35_Helper::makeObject4; // CHECK: call void @llvm.lifetime.start - // CHECK: call noundef i8* % + // CHECK: call i8* % // CHECK: call i8* @llvm.objc.retain id obj4 = (x0.*pmf)(); // CHECK: call void @llvm.lifetime.start - // CHECK: call noundef i8* % + // CHECK: call i8* % // CHECK: call i8* @llvm.objc.retain id obj5 = (x0p->*pmf)(); @@ -222,7 +222,7 @@ template void test37(T *a) { extern template void test37(Test37 *a); template void test37(Test37 *a); // CHECK-LABEL: define weak_odr void @_Z6test37I6Test37EvPT_( -// CHECK: [[T0:%.*]] = call noundef [[NSARRAY]]* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to [[NSARRAY]]* (i8*, i8*)*)( +// CHECK: [[T0:%.*]] = call [[NSARRAY]]* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to [[NSARRAY]]* (i8*, i8*)*)( // CHECK-NEXT: [[T1:%.*]] = bitcast [[NSARRAY]]* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[T1]]) // CHECK-NEXT: [[COLL:%.*]] = bitcast i8* [[T2]] to [[NSARRAY]]* @@ -250,7 +250,7 @@ void send_release() { } // CHECK-LABEL: define weak_odr void @_Z12send_releaseIiEvv( -// CHECK: call noundef %0* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend +// CHECK: call %0* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend // CHECK-NEXT: bitcast // CHECK-NEXT: call i8* @llvm.objc.retainAutoreleasedReturnValue // CHECK-NEXT: bitcast @@ -265,9 +265,9 @@ Test37 *instantiate_init() { return result; } -// CHECK-LABEL: define weak_odr noundef %2* @_Z16instantiate_initIiEP6Test37v -// CHECK: call noundef i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend -// CHECK: call noundef i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend +// CHECK-LABEL: define weak_odr %2* @_Z16instantiate_initIiEP6Test37v +// CHECK: call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend +// CHECK: call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend // CHECK: call i8* @llvm.objc.retain // CHECK: call void @llvm.objc.release // CHECK: call i8* @llvm.objc.autoreleaseReturnValue @@ -298,7 +298,7 @@ class Test39 : Test39_base1, Test39_base2 { // base2 is at non-zero offset id Test39::bar() { return 0; } // Note lack of autorelease. // CHECK-LABEL: define{{.*}} i8* @_ZThn8_N6Test393barEv( -// CHECK: call noundef i8* @_ZN6Test393barEv( +// CHECK: call i8* @_ZN6Test393barEv( // CHECK-NEXT: ret i8* // rdar://13617051 @@ -345,6 +345,6 @@ void test42() { // Check that the pointer returned by test42_0 is released after the full expression. // CHECK-LABEL: define void @_Z6test42v() -// CHECK: %[[CALL:.*]] = call noundef i8* @_Z8test42_0v() +// CHECK: %[[CALL:.*]] = call i8* @_Z8test42_0v() // CHECK: call void @_Z8test42_2OU15__autoreleasingP11objc_object( // CHECK: call void @llvm.objc.release(i8* %[[CALL]]) diff --git a/clang/test/CodeGenObjCXX/auto-release-result-assert.mm b/clang/test/CodeGenObjCXX/auto-release-result-assert.mm index fb24711380431b2787b6b3878d21bb3af5961e0d..ea29f1f8f10d3a635dd741acbcba2de78b75590b 100644 --- a/clang/test/CodeGenObjCXX/auto-release-result-assert.mm +++ b/clang/test/CodeGenObjCXX/auto-release-result-assert.mm @@ -1,15 +1,15 @@ // RUN: %clang_cc1 -triple x86_64-apple-darwin10 -emit-llvm -fblocks -fobjc-arc -o - %s | FileCheck %s // CHECK-LABEL: define{{.*}} %struct.S1* @_Z4foo1i( -// CHECK: %[[CALL:[a-z0-9]+]] = call noundef %struct.S1* @_Z4foo0i +// CHECK: %[[CALL:[a-z0-9]+]] = call %struct.S1* @_Z4foo0i // CHECK: ret %struct.S1* %[[CALL]] // CHECK-LABEL: define{{.*}} %struct.S1* @_ZN2S22m1Ev( -// CHECK: %[[CALL:[a-z0-9]+]] = call noundef %struct.S1* @_Z4foo0i +// CHECK: %[[CALL:[a-z0-9]+]] = call %struct.S1* @_Z4foo0i // CHECK: ret %struct.S1* %[[CALL]] -// CHECK-LABEL: define internal noundef %struct.S1* @Block1_block_invoke( -// CHECK: %[[CALL:[a-z0-9]+]] = call noundef %struct.S1* @_Z4foo0i +// CHECK-LABEL: define internal %struct.S1* @Block1_block_invoke( +// CHECK: %[[CALL:[a-z0-9]+]] = call %struct.S1* @_Z4foo0i // CHECK: ret %struct.S1* %[[CALL]] struct S1; diff --git a/clang/test/CodeGenObjCXX/block-default-arg.mm b/clang/test/CodeGenObjCXX/block-default-arg.mm index e262a5478d5bc76fc3cfce441cc7d6336d63e8c5..167b31d405494e7b167ad68d3b17dbd1726d8a7b 100644 --- a/clang/test/CodeGenObjCXX/block-default-arg.mm +++ b/clang/test/CodeGenObjCXX/block-default-arg.mm @@ -1,10 +1,10 @@ // RUN: %clang_cc1 -triple x86_64-apple-darwin10.0.0 -emit-llvm -o - %s -std=c++11 -fblocks -fobjc-arc | FileCheck %s -// CHECK: define internal void @___Z16test_default_argi_block_invoke(i8* noundef %[[BLOCK_DESCRIPTOR:.*]]) +// CHECK: define internal void @___Z16test_default_argi_block_invoke(i8* %[[BLOCK_DESCRIPTOR:.*]]) // CHECK: %[[BLOCK:.*]] = bitcast i8* %[[BLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* // CHECK: %[[BLOCK_CAPTURE_ADDR:.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* %[[BLOCK]], i32 0, i32 5 // CHECK: %[[V0:.*]] = load i32, i32* %[[BLOCK_CAPTURE_ADDR]] -// CHECK: call void @_Z4foo1i(i32 noundef %[[V0]]) +// CHECK: call void @_Z4foo1i(i32 %[[V0]]) void foo1(int); diff --git a/clang/test/CodeGenObjCXX/block-nested-in-lambda.mm b/clang/test/CodeGenObjCXX/block-nested-in-lambda.mm index d0f819195f0a35dd32a8289914e97bad86af6257..6268cbfbce5da122330dea21a047558218f707f6 100644 --- a/clang/test/CodeGenObjCXX/block-nested-in-lambda.mm +++ b/clang/test/CodeGenObjCXX/block-nested-in-lambda.mm @@ -70,7 +70,7 @@ struct S { S getS(); -// CHECK: define internal noundef i32 @"_ZZN18CaptureByReference5test2EvENK3$_1clIiEEDaT_"(%[[CLASS_ANON_2]]* {{[^,]*}} %{{.*}}, i32 noundef %{{.*}}) +// CHECK: define internal i32 @"_ZZN18CaptureByReference5test2EvENK3$_1clIiEEDaT_"(%[[CLASS_ANON_2]]* {{[^,]*}} %{{.*}}, i32 %{{.*}}) // CHECK: %[[BLOCK:.*]] = alloca <{ i8*, i32, i32, i8*, %{{.*}}, %[[S]]* }>, align 8 // CHECK: %[[BLOCK_CAPTURED:.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %{{.*}}, %[[S]]* }>, <{ i8*, i32, i32, i8*, %{{.*}}, %[[S]]* }>* %[[BLOCK]], i32 0, i32 5 // CHECK: %[[V0:.*]] = getelementptr inbounds %[[CLASS_ANON_2]], %[[CLASS_ANON_2]]* %{{.*}}, i32 0, i32 0 @@ -87,7 +87,7 @@ int test2() { return fn(123); } -// CHECK: define internal noundef i32 @"_ZZN18CaptureByReference5test3EvENK3$_2clIiEEDaT_"(%[[CLASS_ANON_3]]* {{[^,]*}} %{{.*}}, i32 noundef %{{.*}}) +// CHECK: define internal i32 @"_ZZN18CaptureByReference5test3EvENK3$_2clIiEEDaT_"(%[[CLASS_ANON_3]]* {{[^,]*}} %{{.*}}, i32 %{{.*}}) // CHECK: %[[BLOCK:.*]] = alloca <{ i8*, i32, i32, i8*, %{{.*}}*, %[[S]] }>, align 8 // CHECK: %[[BLOCK_CAPTURED:.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %{{.*}}*, %[[S]] }>, <{ i8*, i32, i32, i8*, %{{.*}}*, %[[S]] }>* %[[BLOCK]], i32 0, i32 5 // CHECK: %[[V0:.*]] = getelementptr inbounds %[[CLASS_ANON_3]], %[[CLASS_ANON_3]]* %{{.*}}, i32 0, i32 0 diff --git a/clang/test/CodeGenObjCXX/copy.mm b/clang/test/CodeGenObjCXX/copy.mm index eeb7d79014b4a5c371e074346cffe375627393e7..94cd049804672d9879fe8ef2892fccd64c3ba67e 100644 --- a/clang/test/CodeGenObjCXX/copy.mm +++ b/clang/test/CodeGenObjCXX/copy.mm @@ -11,7 +11,7 @@ namespace test0 { // CHECK: alloca // CHECK-NEXT: getelementptr // CHECK-NEXT: store - // CHECK-NEXT: [[CALL:%.*]] = call noalias noundef nonnull i8* @_Znwm( + // CHECK-NEXT: [[CALL:%.*]] = call noalias nonnull i8* @_Znwm( // CHECK-NEXT: bitcast // CHECK-NEXT: bitcast // CHECK-NEXT: bitcast diff --git a/clang/test/CodeGenObjCXX/implicit-copy-assign-operator.mm b/clang/test/CodeGenObjCXX/implicit-copy-assign-operator.mm index bf99f2a7f5e6b23a2d2bd457bd3990a6a03bd8e7..2fd2d5db30305d4aefb3c6a2ebaf46b4940aaf88 100644 --- a/clang/test/CodeGenObjCXX/implicit-copy-assign-operator.mm +++ b/clang/test/CodeGenObjCXX/implicit-copy-assign-operator.mm @@ -43,7 +43,7 @@ void test_D(D d1, D d2) { d1 = d2; } -// CHECK-OBJ-LABEL: define linkonce_odr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.D* @_ZN1DaSERS_ +// CHECK-OBJ-LABEL: define linkonce_odr nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.D* @_ZN1DaSERS_ // CHECK-OBJ: {{call.*_ZN1AaSERS_}} // CHECK-OBJ: {{call.*_ZN1BaSERS_}} // CHECK-OBJ: {{call.*_ZN1CaSERKS_}} diff --git a/clang/test/CodeGenObjCXX/implicit-copy-constructor.mm b/clang/test/CodeGenObjCXX/implicit-copy-constructor.mm index 1e40331aba8bdfc41ccc18c1828e11a937cf7be6..7e962f5b9f218e37e3706b8e7ff59c03a4eae04e 100644 --- a/clang/test/CodeGenObjCXX/implicit-copy-constructor.mm +++ b/clang/test/CodeGenObjCXX/implicit-copy-constructor.mm @@ -41,7 +41,7 @@ void f(D d) { D d2(d); } -// CHECK-LABEL: define linkonce_odr void @_ZN1DC1ERS_(%struct.D* {{[^,]*}} %this, %struct.D* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr +// CHECK-LABEL: define linkonce_odr void @_ZN1DC1ERS_(%struct.D* {{[^,]*}} %this, %struct.D* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr // CHECK: call void @_ZN1AC1Ev // CHECK: call void @_ZN1CC2ERS_1A // CHECK: call void @_ZN1AD1Ev diff --git a/clang/test/CodeGenObjCXX/inheriting-constructor-cleanup.mm b/clang/test/CodeGenObjCXX/inheriting-constructor-cleanup.mm index 16598ec7b47f8576de6a94eadbdd663c4919aa76..7ad39027ec4a4ef83dcd9a7e87dfd5a3b6d1ae9d 100644 --- a/clang/test/CodeGenObjCXX/inheriting-constructor-cleanup.mm +++ b/clang/test/CodeGenObjCXX/inheriting-constructor-cleanup.mm @@ -22,7 +22,7 @@ void f() { Inheritor({g()}); } // CHECK-LABEL: define{{.*}} void @_Z1fv -// CHECK: %[[TMP:.*]] = call noundef i8* @_Z1gv() +// CHECK: %[[TMP:.*]] = call i8* @_Z1gv() // CHECK: {{.*}} = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* %[[TMP]]) // CHECK: call void (%struct.Base*, i8*, ...) @_ZN4BaseC2E6Strongz(%struct.Base* {{.*}}, i8* {{.*}}) // CHECK-NEXT: call void @_ZN9InheritorD1Ev(%struct.Inheritor* {{.*}}) diff --git a/clang/test/CodeGenObjCXX/lambda-expressions.mm b/clang/test/CodeGenObjCXX/lambda-expressions.mm index 0ac6db888449fb4d9641b4f4fe0e4dc0cbc988a0..001b091657e4e6a18d891767760d6e01d3704a23 100644 --- a/clang/test/CodeGenObjCXX/lambda-expressions.mm +++ b/clang/test/CodeGenObjCXX/lambda-expressions.mm @@ -9,15 +9,15 @@ fp f() { auto x = []{ return 3; }; return x; } // MRC: @OBJC_METH_VAR_NAME{{.*}} = private unnamed_addr constant [5 x i8] c"copy\00" // MRC: @OBJC_METH_VAR_NAME{{.*}} = private unnamed_addr constant [12 x i8] c"autorelease\00" // MRC-LABEL: define{{.*}} i32 ()* @_Z1fv( -// MRC-LABEL: define internal noundef i32 ()* @"_ZZ1fvENK3$_0cvU13block_pointerFivEEv" +// MRC-LABEL: define internal i32 ()* @"_ZZ1fvENK3$_0cvU13block_pointerFivEEv" // MRC: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*) // MRC: store i8* bitcast (i32 (i8*)* @"___ZZ1fvENK3$_0cvU13block_pointerFivEEv_block_invoke" to i8*) -// MRC: call noundef i32 ()* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 ()* (i8*, i8*)*) -// MRC: call noundef i32 ()* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 ()* (i8*, i8*)*) +// MRC: call i32 ()* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 ()* (i8*, i8*)*) +// MRC: call i32 ()* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 ()* (i8*, i8*)*) // MRC: ret i32 ()* // ARC-LABEL: define{{.*}} i32 ()* @_Z1fv( -// ARC-LABEL: define internal noundef i32 ()* @"_ZZ1fvENK3$_0cvU13block_pointerFivEEv" +// ARC-LABEL: define internal i32 ()* @"_ZZ1fvENK3$_0cvU13block_pointerFivEEv" // ARC: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*) // ARC: store i8* bitcast (i32 (i8*)* @"___ZZ1fvENK3$_0cvU13block_pointerFivEEv_block_invoke" to i8*) // ARC: call i8* @llvm.objc.retainBlock @@ -37,8 +37,8 @@ void f2() { global = []{ return 3; }; } // ARC: store i8* bitcast (i32 (i8*)* @___Z2f2v_block_invoke to i8*), // ARC: call i8* @llvm.objc.retainBlock // ARC: call void @llvm.objc.release -// ARC-LABEL: define internal noundef i32 @___Z2f2v_block_invoke -// ARC: call noundef i32 @"_ZZ2f2vENK3$_1clEv +// ARC-LABEL: define internal i32 @___Z2f2v_block_invoke +// ARC: call i32 @"_ZZ2f2vENK3$_1clEv template void take_lambda(T &&lambda) { lambda(); } void take_block(void (^block)()) { block(); } @@ -62,7 +62,7 @@ void take_block(void (^block)()) { block(); } } @end -// ARC: define{{.*}} void @_ZN13LambdaCapture4foo1ERi(i32* noundef nonnull align 4 dereferenceable(4) %{{.*}}) +// ARC: define{{.*}} void @_ZN13LambdaCapture4foo1ERi(i32* nonnull align 4 dereferenceable(4) %{{.*}}) // ARC: %[[CAPTURE0:.*]] = getelementptr inbounds %[[LAMBDACLASS]], %[[LAMBDACLASS]]* %{{.*}}, i32 0, i32 0 // ARC: store i32 %{{.*}}, i32* %[[CAPTURE0]] @@ -79,7 +79,7 @@ void take_block(void (^block)()) { block(); } // ARC: %[[CAPTURE2:.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* %{{.*}}, i32 0, i32 5 // ARC: store i32 %{{.*}}, i32* %[[CAPTURE2]] -// ARC: define internal void @"___ZZN13LambdaCapture4foo1ERiENK3$_3clEv_block_invoke_2"(i8* noundef %{{.*}}) +// ARC: define internal void @"___ZZN13LambdaCapture4foo1ERiENK3$_3clEv_block_invoke_2"(i8* %{{.*}}) // ARC: %[[CAPTURE3:.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* %{{.*}}, i32 0, i32 5 // ARC: %[[V1:.*]] = load i32, i32* %[[CAPTURE3]] // ARC: store i32 %[[V1]], i32* @_ZN13LambdaCapture1iE @@ -100,10 +100,10 @@ namespace LambdaCapture { } } -// ARC-LABEL: define linkonce_odr noundef i32 ()* @_ZZNK13StaticMembersIfE1fMUlvE_clEvENKUlvE_cvU13block_pointerFivEEv +// ARC-LABEL: define linkonce_odr i32 ()* @_ZZNK13StaticMembersIfE1fMUlvE_clEvENKUlvE_cvU13block_pointerFivEEv // Check lines for BlockInLambda test below -// ARC-LABEL: define internal noundef i32 @___ZZN13BlockInLambda1X1fEvENKUlvE_clEv_block_invoke +// ARC-LABEL: define internal i32 @___ZZN13BlockInLambda1X1fEvENKUlvE_clEv_block_invoke // ARC: [[Y:%.*]] = getelementptr inbounds %"struct.BlockInLambda::X", %"struct.BlockInLambda::X"* {{.*}}, i32 0, i32 1 // ARC-NEXT: [[YVAL:%.*]] = load i32, i32* [[Y]], align 4 // ARC-NEXT: ret i32 [[YVAL]] diff --git a/clang/test/CodeGenObjCXX/lambda-to-block.mm b/clang/test/CodeGenObjCXX/lambda-to-block.mm index b1de065dbbc57c0e644b728d2b30692c673be121..45dd6fe115d407daf79596c59d9c04c111c41675 100644 --- a/clang/test/CodeGenObjCXX/lambda-to-block.mm +++ b/clang/test/CodeGenObjCXX/lambda-to-block.mm @@ -40,18 +40,18 @@ void hasLambda(Copyable x) { // CHECK: define internal void @[[COPY_HELPER1]] // CHECK: define{{.*}} void @_Z17testHelperMerging8Copyable( -// CHECK: %[[CALL:.*]] = call noundef void ()* @[[CONV_FUNC0:.*]](%[[CLASS_ANON_1]]* -// CHECK: call void @_Z10takesBlockU13block_pointerFvvE(void ()* noundef %[[CALL]]) -// CHECK: %[[CALL1:.*]] = call noundef void ()* @[[CONV_FUNC0]](%[[CLASS_ANON_1]]* -// CHECK: call void @_Z10takesBlockU13block_pointerFvvE(void ()* noundef %[[CALL1]]) -// CHECK: %[[CALL2:.*]] = call noundef void ()* @[[CONV_FUNC1:.*]](%[[CLASS_ANON_2]]* -// CHECK: call void @_Z10takesBlockU13block_pointerFvvE(void ()* noundef %[[CALL2]]) - -// CHECK: define internal noundef void ()* @[[CONV_FUNC0]]( +// CHECK: %[[CALL:.*]] = call void ()* @[[CONV_FUNC0:.*]](%[[CLASS_ANON_1]]* +// CHECK: call void @_Z10takesBlockU13block_pointerFvvE(void ()* %[[CALL]]) +// CHECK: %[[CALL1:.*]] = call void ()* @[[CONV_FUNC0]](%[[CLASS_ANON_1]]* +// CHECK: call void @_Z10takesBlockU13block_pointerFvvE(void ()* %[[CALL1]]) +// CHECK: %[[CALL2:.*]] = call void ()* @[[CONV_FUNC1:.*]](%[[CLASS_ANON_2]]* +// CHECK: call void @_Z10takesBlockU13block_pointerFvvE(void ()* %[[CALL2]]) + +// CHECK: define internal void ()* @[[CONV_FUNC0]]( // CHECK: %[[BLOCK_DESCRIPTOR:.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]*, %[[CLASS_ANON_1]] }>, <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]*, %[[CLASS_ANON_1]] }>* %{{.*}}, i32 0, i32 4 // CHECK: store %[[STRUCT_BLOCK_DESCRIPTOR]]* bitcast ({ i64, i64, i8*, i8*, i8*, i8* }* @[[BLOCK_DESC2]] to %[[STRUCT_BLOCK_DESCRIPTOR]]*), %[[STRUCT_BLOCK_DESCRIPTOR]]** %[[BLOCK_DESCRIPTOR]], align 8 -// CHECK: define internal noundef void ()* @[[CONV_FUNC1]]( +// CHECK: define internal void ()* @[[CONV_FUNC1]]( // CHECK: %[[BLOCK_DESCRIPTOR:.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]*, %[[CLASS_ANON_2]] }>, <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]*, %[[CLASS_ANON_2]] }>* %{{.*}}, i32 0, i32 4 // CHECK: store %[[STRUCT_BLOCK_DESCRIPTOR]]* bitcast ({ i64, i64, i8*, i8*, i8*, i8* }* @[[BLOCK_DESC3]] to %[[STRUCT_BLOCK_DESCRIPTOR]]*), %[[STRUCT_BLOCK_DESCRIPTOR]]** %[[BLOCK_DESCRIPTOR]], align 8 diff --git a/clang/test/CodeGenObjCXX/literals.mm b/clang/test/CodeGenObjCXX/literals.mm index 954f7d07288a3d5ecf4b4e34ce71f648a8ecc651..3cdde2089de836dda655ed183fb2a3474ddf8032 100644 --- a/clang/test/CodeGenObjCXX/literals.mm +++ b/clang/test/CodeGenObjCXX/literals.mm @@ -28,7 +28,7 @@ void test_array() { // CHECK-NEXT: [[TMP_CAST:%.*]] = bitcast {{.*}} [[TMPX]] to i8* // CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 1, i8* [[TMP_CAST]]) // CHECK-NEXT: call void @_ZN1XC1Ev({{.*}} [[TMPX]]) - // CHECK-NEXT: [[OBJECT0:%[a-zA-Z0-9.]+]] = invoke noundef i8* @_ZNK1XcvP11objc_objectEv + // CHECK-NEXT: [[OBJECT0:%[a-zA-Z0-9.]+]] = invoke i8* @_ZNK1XcvP11objc_objectEv // CHECK: [[RET0:%[a-zA-Z0-9.]+]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[OBJECT0]]) // CHECK: store i8* [[RET0]], i8** [[ELEMENT0]] @@ -37,7 +37,7 @@ void test_array() { // CHECK-NEXT: [[TMP_CAST:%.*]] = bitcast {{.*}} [[TMPY]] to i8* // CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 1, i8* [[TMP_CAST]]) // CHECK-NEXT: invoke void @_ZN1YC1Ev({{.*}} [[TMPY]]) - // CHECK: [[OBJECT1:%[a-zA-Z0-9.]+]] = invoke noundef i8* @_ZNK1YcvP11objc_objectEv + // CHECK: [[OBJECT1:%[a-zA-Z0-9.]+]] = invoke i8* @_ZNK1YcvP11objc_objectEv // CHECK: [[RET1:%[a-zA-Z0-9.]+]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[OBJECT1]]) // CHECK: store i8* [[RET1]], i8** [[ELEMENT1]] @@ -82,14 +82,14 @@ void test_array_instantiation() { // CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[PTR1]]) // CHECK: [[ELEMENT0:%[a-zA-Z0-9.]+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[OBJECTS]], i64 0, i64 0 // CHECK: call void @_ZN1XC1Ev - // CHECK-NEXT: [[OBJECT0:%[a-zA-Z0-9.]+]] = invoke noundef i8* @_ZNK1XcvP11objc_objectEv + // CHECK-NEXT: [[OBJECT0:%[a-zA-Z0-9.]+]] = invoke i8* @_ZNK1XcvP11objc_objectEv // CHECK: [[RET0:%[a-zA-Z0-9.]+]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[OBJECT0]]) // CHECK: store i8* [[RET0]], i8** [[ELEMENT0]] // Initializing the second element // CHECK: [[ELEMENT1:%[a-zA-Z0-9.]+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[OBJECTS]], i64 0, i64 1 // CHECK: invoke void @_ZN1YC1Ev - // CHECK: [[OBJECT1:%[a-zA-Z0-9.]+]] = invoke noundef i8* @_ZNK1YcvP11objc_objectEv + // CHECK: [[OBJECT1:%[a-zA-Z0-9.]+]] = invoke i8* @_ZNK1YcvP11objc_objectEv // CHECK: [[RET1:%[a-zA-Z0-9.]+]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [[OBJECT1]]) // CHECK: store i8* [[RET1]], i8** [[ELEMENT1]] diff --git a/clang/test/CodeGenObjCXX/lvalue-reference-getter.mm b/clang/test/CodeGenObjCXX/lvalue-reference-getter.mm index d89447f4849a4c443f8d3625f16f48ce14bc2b29..b495300480a327f7ff48928a446b354164c5502e 100644 --- a/clang/test/CodeGenObjCXX/lvalue-reference-getter.mm +++ b/clang/test/CodeGenObjCXX/lvalue-reference-getter.mm @@ -24,5 +24,5 @@ static SetSection gSetSection; // CHECK: [[SELF:%.*]] = alloca [[T6:%.*]]*, align // CHECK: [[T0:%.*]] = load {{.*}}, {{.*}}* [[SELF]], align // CHECK: [[T1:%.*]] = load {{.*}}, {{.*}}* @OBJC_SELECTOR_REFERENCES_ -// CHECK: [[C:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.SetSection* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend -// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_ZN10SetSection2atEi(%struct.SetSection* {{[^,]*}} [[C]] +// CHECK: [[C:%.*]] = call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.SetSection* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend +// CHECK: call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* @_ZN10SetSection2atEi(%struct.SetSection* {{[^,]*}} [[C]] diff --git a/clang/test/CodeGenObjCXX/mangle-blocks.mm b/clang/test/CodeGenObjCXX/mangle-blocks.mm index e24d58305625365fa9569d67e2414d838c8d9061..bbe5c1f77f4d1cc2ba0da55a1e734f34d067da36 100644 --- a/clang/test/CodeGenObjCXX/mangle-blocks.mm +++ b/clang/test/CodeGenObjCXX/mangle-blocks.mm @@ -8,7 +8,7 @@ int f(); void foo() { - // CHECK-LABEL: define internal noundef i32 @___Z3foov_block_invoke + // CHECK-LABEL: define internal i32 @___Z3foov_block_invoke // CHECK: call i32 @__cxa_guard_acquire(i64* @_ZGVZZ3foovEUb_E5value (void)^(int x) { static int value = f(); @@ -16,7 +16,7 @@ void foo() { }; } -// CHECK-LABEL: define internal noundef i32 @i_block_invoke +// CHECK-LABEL: define internal i32 @i_block_invoke int i = ^(int x) { return x;}(i); @interface A @@ -25,7 +25,7 @@ int i = ^(int x) { return x;}(i); @implementation A - (void)method { - // CHECK: define internal noundef signext i8 @"__11-[A method]_block_invoke" + // CHECK: define internal signext i8 @"__11-[A method]_block_invoke" (void)^(int x) { // CHECK: @"_ZZZ11-[A method]EUb1_E4name" static const char *name = "hello"; @@ -42,7 +42,7 @@ void foo(int) { } namespace N { - // CHECK-LABEL: define internal noundef signext i8 @___Z3fooi_block_invoke + // CHECK-LABEL: define internal signext i8 @___Z3fooi_block_invoke void bar() { (void)^(int x) { // CHECK: @_ZZZN1N3barEvEUb3_E4name diff --git a/clang/test/CodeGenObjCXX/message-reference.mm b/clang/test/CodeGenObjCXX/message-reference.mm index 523a0da6417764d115d62a422eb673df56b1e8ff..3d1d2b19c202a71b2223ff28e84c30ab846b4cee 100644 --- a/clang/test/CodeGenObjCXX/message-reference.mm +++ b/clang/test/CodeGenObjCXX/message-reference.mm @@ -15,6 +15,6 @@ } @end -// CHECK: [[T:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend +// CHECK: [[T:%.*]] = call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) i32* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend // CHECK: [[U:%.*]] = load i32, i32* [[T]] // CHECK: [[V:%.*]] = icmp eq i32 [[U]], 0 diff --git a/clang/test/CodeGenObjCXX/message.mm b/clang/test/CodeGenObjCXX/message.mm index 137c77190ed4c3ee1820207bfba6bc2dac6db056..b2942448758dda04b2b67f2df52d886689260f78 100644 --- a/clang/test/CodeGenObjCXX/message.mm +++ b/clang/test/CodeGenObjCXX/message.mm @@ -16,9 +16,9 @@ namespace test0 { } template void foo(); // CHECK-LABEL: define weak_odr void @_ZN5test03fooIiEEvv() - // CHECK: [[T0:%.*]] = call noundef [[TEST0:%.*]]* @_ZN5test01AcvP5Test0Ev( + // CHECK: [[T0:%.*]] = call [[TEST0:%.*]]* @_ZN5test01AcvP5Test0Ev( // CHECK-NEXT: [[T1:%.*]] = load i8*, i8** // CHECK-NEXT: [[T2:%.*]] = bitcast [[TEST0]]* [[T0]] to i8* - // CHECK-NEXT: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*)*)(i8* noundef [[T2]], i8* noundef [[T1]]) + // CHECK-NEXT: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*)*)(i8* [[T2]], i8* [[T1]]) // CHECK-NEXT: ret void } diff --git a/clang/test/CodeGenObjCXX/objc-container-subscripting.mm b/clang/test/CodeGenObjCXX/objc-container-subscripting.mm index 4fdc51f5042d59b6fc2635f387f3b5b029d52bb9..8b7d8b53162bd331e2bcf244b3e3b9606dc3d3d7 100644 --- a/clang/test/CodeGenObjCXX/objc-container-subscripting.mm +++ b/clang/test/CodeGenObjCXX/objc-container-subscripting.mm @@ -50,7 +50,7 @@ template void test3(NSMutableArray*); // CHECK-LABEL: define{{.*}} void @_Z11static_dataP14NSMutableArray void static_data(NSMutableArray *array) { // CHECK: call i32 @__cxa_guard_acquire - // CHECK: {{call noundef i8*.*@objc_msgSend }} + // CHECK: {{call i8*.*@objc_msgSend }} // CHECK: call void @__cxa_guard_release static id x = array[4]; // CHECK: ret void diff --git a/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm b/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm index 68440ff2ad9ee3e85c75f6c3d0c11249e957e767..ad75a387d275f2e6f4e2a4f15680a86e0e5b7fc7 100644 --- a/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm +++ b/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm @@ -76,20 +76,20 @@ struct ContainsNonTrivial { - (void)passNonTrivial:(NonTrivial)a; @end -// CHECK: define{{.*}} void @_Z19testParamStrongWeak10StrongWeak(%[[STRUCT_STRONGWEAK]]* noundef %{{.*}}) -// CHECK: call noundef %struct.StrongWeak* @_ZN10StrongWeakD1Ev( +// CHECK: define{{.*}} void @_Z19testParamStrongWeak10StrongWeak(%[[STRUCT_STRONGWEAK]]* %{{.*}}) +// CHECK: call %struct.StrongWeak* @_ZN10StrongWeakD1Ev( // CHECK-NEXT: ret void void testParamStrongWeak(StrongWeak a) { } -// CHECK: define{{.*}} void @_Z18testCallStrongWeakP10StrongWeak(%[[STRUCT_STRONGWEAK]]* noundef %[[A:.*]]) +// CHECK: define{{.*}} void @_Z18testCallStrongWeakP10StrongWeak(%[[STRUCT_STRONGWEAK]]* %[[A:.*]]) // CHECK: %[[A_ADDR:.*]] = alloca %[[STRUCT_STRONGWEAK]]*, align 8 // CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_STRONGWEAK]], align 8 // CHECK: store %[[STRUCT_STRONGWEAK]]* %[[A]], %[[STRUCT_STRONGWEAK]]** %[[A_ADDR]], align 8 // CHECK: %[[V0:.*]] = load %[[STRUCT_STRONGWEAK]]*, %[[STRUCT_STRONGWEAK]]** %[[A_ADDR]], align 8 -// CHECK: %[[CALL:.*]] = call noundef %[[STRUCT_STRONGWEAK]]* @_ZN10StrongWeakC1ERKS_(%[[STRUCT_STRONGWEAK]]* {{[^,]*}} %[[AGG_TMP]], %[[STRUCT_STRONGWEAK]]* noundef nonnull align 8 dereferenceable(16) %[[V0]]) -// CHECK: call void @_Z19testParamStrongWeak10StrongWeak(%[[STRUCT_STRONGWEAK]]* noundef %[[AGG_TMP]]) +// CHECK: %[[CALL:.*]] = call %[[STRUCT_STRONGWEAK]]* @_ZN10StrongWeakC1ERKS_(%[[STRUCT_STRONGWEAK]]* {{[^,]*}} %[[AGG_TMP]], %[[STRUCT_STRONGWEAK]]* nonnull align 8 dereferenceable(16) %[[V0]]) +// CHECK: call void @_Z19testParamStrongWeak10StrongWeak(%[[STRUCT_STRONGWEAK]]* %[[AGG_TMP]]) // CHECK-NOT: call // CHECK: ret void @@ -97,25 +97,25 @@ void testCallStrongWeak(StrongWeak *a) { testParamStrongWeak(*a); } -// CHECK: define{{.*}} void @_Z20testReturnStrongWeakP10StrongWeak(%[[STRUCT_STRONGWEAK:.*]]* noalias sret(%[[STRUCT_STRONGWEAK]]) align 8 %[[AGG_RESULT:.*]], %[[STRUCT_STRONGWEAK]]* noundef %[[A:.*]]) +// CHECK: define{{.*}} void @_Z20testReturnStrongWeakP10StrongWeak(%[[STRUCT_STRONGWEAK:.*]]* noalias sret(%[[STRUCT_STRONGWEAK]]) align 8 %[[AGG_RESULT:.*]], %[[STRUCT_STRONGWEAK]]* %[[A:.*]]) // CHECK: %[[A_ADDR:.*]] = alloca %[[STRUCT_STRONGWEAK]]*, align 8 // CHECK: store %[[STRUCT_STRONGWEAK]]* %[[A]], %[[STRUCT_STRONGWEAK]]** %[[A_ADDR]], align 8 // CHECK: %[[V0:.*]] = load %[[STRUCT_STRONGWEAK]]*, %[[STRUCT_STRONGWEAK]]** %[[A_ADDR]], align 8 -// CHECK: %[[CALL:.*]] = call noundef %[[STRUCT_STRONGWEAK]]* @_ZN10StrongWeakC1ERKS_(%[[STRUCT_STRONGWEAK]]* {{[^,]*}} %[[AGG_RESULT]], %[[STRUCT_STRONGWEAK]]* noundef nonnull align 8 dereferenceable(16) %[[V0]]) +// CHECK: %[[CALL:.*]] = call %[[STRUCT_STRONGWEAK]]* @_ZN10StrongWeakC1ERKS_(%[[STRUCT_STRONGWEAK]]* {{[^,]*}} %[[AGG_RESULT]], %[[STRUCT_STRONGWEAK]]* nonnull align 8 dereferenceable(16) %[[V0]]) // CHECK: ret void StrongWeak testReturnStrongWeak(StrongWeak *a) { return *a; } -// CHECK: define{{.*}} void @_Z27testParamContainsStrongWeak18ContainsStrongWeak(%[[STRUCT_CONTAINSSTRONGWEAK]]* noundef %[[A:.*]]) -// CHECK: call noundef %[[STRUCT_CONTAINSSTRONGWEAK]]* @_ZN18ContainsStrongWeakD1Ev(%[[STRUCT_CONTAINSSTRONGWEAK]]* {{[^,]*}} %[[A]]) +// CHECK: define{{.*}} void @_Z27testParamContainsStrongWeak18ContainsStrongWeak(%[[STRUCT_CONTAINSSTRONGWEAK]]* %[[A:.*]]) +// CHECK: call %[[STRUCT_CONTAINSSTRONGWEAK]]* @_ZN18ContainsStrongWeakD1Ev(%[[STRUCT_CONTAINSSTRONGWEAK]]* {{[^,]*}} %[[A]]) void testParamContainsStrongWeak(ContainsStrongWeak a) { } -// CHECK: define{{.*}} void @_Z26testParamDerivedStrongWeak17DerivedStrongWeak(%[[STRUCT_DERIVEDSTRONGWEAK]]* noundef %[[A:.*]]) -// CHECK: call noundef %[[STRUCT_DERIVEDSTRONGWEAK]]* @_ZN17DerivedStrongWeakD1Ev(%[[STRUCT_DERIVEDSTRONGWEAK]]* {{[^,]*}} %[[A]]) +// CHECK: define{{.*}} void @_Z26testParamDerivedStrongWeak17DerivedStrongWeak(%[[STRUCT_DERIVEDSTRONGWEAK]]* %[[A:.*]]) +// CHECK: call %[[STRUCT_DERIVEDSTRONGWEAK]]* @_ZN17DerivedStrongWeakD1Ev(%[[STRUCT_DERIVEDSTRONGWEAK]]* {{[^,]*}} %[[A]]) void testParamDerivedStrongWeak(DerivedStrongWeak a) { } @@ -125,20 +125,20 @@ void testParamDerivedStrongWeak(DerivedStrongWeak a) { // CHECK: %[[COERCE_DIVE:.*]] = getelementptr inbounds %[[STRUCT_STRONG]], %[[STRUCT_STRONG]]* %[[A]], i32 0, i32 0 // CHECK: %[[COERCE_VAL_IP:.*]] = inttoptr i64 %[[A_COERCE]] to i8* // CHECK: store i8* %[[COERCE_VAL_IP]], i8** %[[COERCE_DIVE]], align 8 -// CHECK: %[[CALL:.*]] = call noundef %[[STRUCT_STRONG]]* @_ZN6StrongD1Ev(%[[STRUCT_STRONG]]* {{[^,]*}} %[[A]]) +// CHECK: %[[CALL:.*]] = call %[[STRUCT_STRONG]]* @_ZN6StrongD1Ev(%[[STRUCT_STRONG]]* {{[^,]*}} %[[A]]) // CHECK: ret void -// CHECK: define linkonce_odr noundef %[[STRUCT_STRONG]]* @_ZN6StrongD1Ev( +// CHECK: define linkonce_odr %[[STRUCT_STRONG]]* @_ZN6StrongD1Ev( void testParamStrong(Strong a) { } -// CHECK: define{{.*}} void @_Z14testCallStrongP6Strong(%[[STRUCT_STRONG]]* noundef %[[A:.*]]) +// CHECK: define{{.*}} void @_Z14testCallStrongP6Strong(%[[STRUCT_STRONG]]* %[[A:.*]]) // CHECK: %[[A_ADDR:.*]] = alloca %[[STRUCT_STRONG]]*, align 8 // CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_STRONG]], align 8 // CHECK: store %[[STRUCT_STRONG]]* %[[A]], %[[STRUCT_STRONG]]** %[[A_ADDR]], align 8 // CHECK: %[[V0:.*]] = load %[[STRUCT_STRONG]]*, %[[STRUCT_STRONG]]** %[[A_ADDR]], align 8 -// CHECK: %[[CALL:.*]] = call noundef %[[STRUCT_STRONG]]* @_ZN6StrongC1ERKS_(%[[STRUCT_STRONG]]* {{[^,]*}} %[[AGG_TMP]], %[[STRUCT_STRONG]]* noundef nonnull align 8 dereferenceable(8) %[[V0]]) +// CHECK: %[[CALL:.*]] = call %[[STRUCT_STRONG]]* @_ZN6StrongC1ERKS_(%[[STRUCT_STRONG]]* {{[^,]*}} %[[AGG_TMP]], %[[STRUCT_STRONG]]* nonnull align 8 dereferenceable(8) %[[V0]]) // CHECK: %[[COERCE_DIVE:.*]] = getelementptr inbounds %[[STRUCT_STRONG]], %[[STRUCT_STRONG]]* %[[AGG_TMP]], i32 0, i32 0 // CHECK: %[[V1:.*]] = load i8*, i8** %[[COERCE_DIVE]], align 8 // CHECK: %[[COERCE_VAL_PI:.*]] = ptrtoint i8* %[[V1]] to i64 @@ -149,12 +149,12 @@ void testCallStrong(Strong *a) { testParamStrong(*a); } -// CHECK: define{{.*}} i64 @_Z16testReturnStrongP6Strong(%[[STRUCT_STRONG]]* noundef %[[A:.*]]) +// CHECK: define{{.*}} i64 @_Z16testReturnStrongP6Strong(%[[STRUCT_STRONG]]* %[[A:.*]]) // CHECK: %[[RETVAL:.*]] = alloca %[[STRUCT_STRONG]], align 8 // CHECK: %[[A_ADDR:.*]] = alloca %[[STRUCT_STRONG]]*, align 8 // CHECK: store %[[STRUCT_STRONG]]* %[[A]], %[[STRUCT_STRONG]]** %[[A_ADDR]], align 8 // CHECK: %[[V0:.*]] = load %[[STRUCT_STRONG]]*, %[[STRUCT_STRONG]]** %[[A_ADDR]], align 8 -// CHECK: %[[CALL:.*]] = call noundef %[[STRUCT_STRONG]]* @_ZN6StrongC1ERKS_(%[[STRUCT_STRONG]]* {{[^,]*}} %[[RETVAL]], %[[STRUCT_STRONG]]* noundef nonnull align 8 dereferenceable(8) %[[V0]]) +// CHECK: %[[CALL:.*]] = call %[[STRUCT_STRONG]]* @_ZN6StrongC1ERKS_(%[[STRUCT_STRONG]]* {{[^,]*}} %[[RETVAL]], %[[STRUCT_STRONG]]* nonnull align 8 dereferenceable(8) %[[V0]]) // CHECK: %[[COERCE_DIVE:.*]] = getelementptr inbounds %[[STRUCT_STRONG]], %[[STRUCT_STRONG]]* %[[RETVAL]], i32 0, i32 0 // CHECK: %[[V1:.*]] = load i8*, i8** %[[COERCE_DIVE]], align 8 // CHECK: %[[COERCE_VAL_PI:.*]] = ptrtoint i8* %[[V1]] to i64 @@ -164,14 +164,14 @@ Strong testReturnStrong(Strong *a) { return *a; } -// CHECK: define{{.*}} void @_Z21testParamWeakTemplate1SIU6__weakP11objc_objectE(%[[STRUCT_S]]* noundef %{{.*}}) -// CHECK: call noundef %struct.S* @_ZN1SIU6__weakP11objc_objectED1Ev( +// CHECK: define{{.*}} void @_Z21testParamWeakTemplate1SIU6__weakP11objc_objectE(%[[STRUCT_S]]* %{{.*}}) +// CHECK: call %struct.S* @_ZN1SIU6__weakP11objc_objectED1Ev( // CHECK-NEXT: ret void void testParamWeakTemplate(S<__weak id> a) { } -// CHECK: define{{.*}} void @_Z27testParamContainsNonTrivial18ContainsNonTrivial(%[[STRUCT_CONTAINSNONTRIVIAL]]* noundef %{{.*}}) +// CHECK: define{{.*}} void @_Z27testParamContainsNonTrivial18ContainsNonTrivial(%[[STRUCT_CONTAINSNONTRIVIAL]]* %{{.*}}) // CHECK-NOT: call // CHECK: ret void @@ -179,8 +179,8 @@ void testParamContainsNonTrivial(ContainsNonTrivial a) { } // CHECK: define{{.*}} void @_Z26testCallContainsNonTrivialP18ContainsNonTrivial( -// CHECK: call void @_Z27testParamContainsNonTrivial18ContainsNonTrivial(%[[STRUCT_CONTAINSNONTRIVIAL]]* noundef %{{.*}}) -// CHECK: call noundef %struct.ContainsNonTrivial* @_ZN18ContainsNonTrivialD1Ev(%[[STRUCT_CONTAINSNONTRIVIAL]]* {{[^,]*}} %{{.*}}) +// CHECK: call void @_Z27testParamContainsNonTrivial18ContainsNonTrivial(%[[STRUCT_CONTAINSNONTRIVIAL]]* %{{.*}}) +// CHECK: call %struct.ContainsNonTrivial* @_ZN18ContainsNonTrivialD1Ev(%[[STRUCT_CONTAINSNONTRIVIAL]]* {{[^,]*}} %{{.*}}) void testCallContainsNonTrivial(ContainsNonTrivial *a) { testParamContainsNonTrivial(*a); @@ -227,7 +227,7 @@ namespace testNullReceiver { // CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i64)*)({{.*}}, i64 %[[COERCE_VAL_PI]]) // CHECK: br -// CHECK: %[[CALL1:.*]] = call noundef %[[STRUCT_STRONG]]* @_ZN6StrongD1Ev(%[[STRUCT_STRONG]]* noundef %[[AGG_TMP]]) +// CHECK: %[[CALL1:.*]] = call %[[STRUCT_STRONG]]* @_ZN6StrongD1Ev(%[[STRUCT_STRONG]]* nonnull align 8 dereferenceable(8) %[[AGG_TMP]]) // CHECK: br void test0(C *c) { @@ -238,10 +238,10 @@ void test0(C *c) { // CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_STRONGWEAK]], align 8 // CHECK: br i1 -// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void ({{.*}}, %[[STRUCT_STRONGWEAK]]* noundef %[[AGG_TMP]]) +// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void ({{.*}}, %[[STRUCT_STRONGWEAK]]* %[[AGG_TMP]]) // CHECK: br -// CHECK: %[[CALL1:.*]] = call noundef %[[STRUCT_STRONGWEAK]]* @_ZN10StrongWeakD1Ev(%[[STRUCT_STRONGWEAK]]* noundef %[[AGG_TMP]]) +// CHECK: %[[CALL1:.*]] = call %[[STRUCT_STRONGWEAK]]* @_ZN10StrongWeakD1Ev(%[[STRUCT_STRONGWEAK]]* nonnull align 8 dereferenceable(16) %[[AGG_TMP]]) // CHECK: br void test1(C *c) { @@ -252,8 +252,8 @@ void test1(C *c) { // CHECK-LABEL: define{{.*}} void @_ZN16testNullReceiver5test2EP1C( // CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_NONTRIVIAL]], align 8 -// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %[[STRUCT_NONTRIVIAL]]*)*)({{.*}}, %[[STRUCT_NONTRIVIAL]]* noundef %[[AGG_TMP]]) -// CHECK-NEXT: call noundef %[[STRUCT_NONTRIVIAL]]* @_ZN10NonTrivialD1Ev(%[[STRUCT_NONTRIVIAL]]* noundef %[[AGG_TMP]]) +// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %[[STRUCT_NONTRIVIAL]]*)*)({{.*}}, %[[STRUCT_NONTRIVIAL]]* %[[AGG_TMP]]) +// CHECK-NEXT: call %[[STRUCT_NONTRIVIAL]]* @_ZN10NonTrivialD1Ev(%[[STRUCT_NONTRIVIAL]]* nonnull align 8 dereferenceable(8) %[[AGG_TMP]]) void test2(C *c) { [c passNonTrivial:NonTrivial()]; diff --git a/clang/test/CodeGenObjCXX/objc-weak.mm b/clang/test/CodeGenObjCXX/objc-weak.mm index 6c60ed9917e5dc9c1476e23e9c19c773598fb6a7..85058bf0745bb57b864e598b580ee07c9fee8983 100644 --- a/clang/test/CodeGenObjCXX/objc-weak.mm +++ b/clang/test/CodeGenObjCXX/objc-weak.mm @@ -12,7 +12,7 @@ id test0() { } // Copy Assignment Operator -// CHECK-LABEL: define linkonce_odr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.A* @_ZN1AaSERKS_( +// CHECK-LABEL: define linkonce_odr nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.A* @_ZN1AaSERKS_( // CHECK: [[THISADDR:%this.*]] = alloca [[A:.*]]* // CHECK: [[OBJECTADDR:%.*]] = alloca [[A:.*]]* // CHECK: [[THIS:%this.*]] = load [[A]]*, [[A]]** [[THISADDR]] @@ -23,7 +23,7 @@ id test0() { // CHECK-NEXT: [[T3:%.*]] = call i8* @llvm.objc.storeWeak(i8** [[T2]], i8* [[T1]]) // Move Assignment Operator -// CHECK-LABEL: define linkonce_odr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.A* @_ZN1AaSEOS_( +// CHECK-LABEL: define linkonce_odr nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.A* @_ZN1AaSEOS_( // CHECK: [[THISADDR:%this.*]] = alloca [[A:.*]]* // CHECK: [[OBJECTADDR:%.*]] = alloca [[A:.*]]* // CHECK: [[THIS:%this.*]] = load [[A]]*, [[A]]** [[THISADDR]] diff --git a/clang/test/CodeGenObjCXX/property-dot-copy-elision.mm b/clang/test/CodeGenObjCXX/property-dot-copy-elision.mm index 452810cd06432a77067684983e8e8c3c617e3053..1c98d3565cf93f3fe2863002a46479048bc9e728 100644 --- a/clang/test/CodeGenObjCXX/property-dot-copy-elision.mm +++ b/clang/test/CodeGenObjCXX/property-dot-copy-elision.mm @@ -23,8 +23,8 @@ struct S1 { // CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_S1:.*]], align // CHECK: %[[AGG_TMP_1:.*]] = alloca %[[STRUCT_S0:.*]], align // CHECK: call void @_ZN2S0C1Ev(%[[STRUCT_S0]]* {{[^,]*}} %[[AGG_TMP_1]]) -// CHECK: call void @_ZN2S1C1E2S0(%[[STRUCT_S1]]* {{[^,]*}} %[[AGG_TMP]], %[[STRUCT_S0]]* noundef %[[AGG_TMP_1]]) -// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %[[STRUCT_S1]]*)*)(i8* noundef %{{.*}}, i8* noundef %{{.*}}, %[[STRUCT_S1]]* noundef %[[AGG_TMP]]) +// CHECK: call void @_ZN2S1C1E2S0(%[[STRUCT_S1]]* {{[^,]*}} %[[AGG_TMP]], %[[STRUCT_S0]]* %[[AGG_TMP_1]]) +// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %[[STRUCT_S1]]*)*)(i8* %{{.*}}, i8* %{{.*}}, %[[STRUCT_S1]]* %[[AGG_TMP]]) void test0(C *c) { c.f = S0(); @@ -34,7 +34,7 @@ void test0(C *c) { // CHECK: %{{.*}} = alloca % // CHECK: %[[TEMP_LVALUE:.*]] = alloca %[[STRUCT_S1:.*]], align // CHECK: call void @_ZN2S1C1Ev(%[[STRUCT_S1]]* {{[^,]*}} %[[TEMP_LVALUE]]) -// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %[[STRUCT_S1]]*)*)(i8* noundef %{{.*}}, i8* noundef %{{.*}}, %[[STRUCT_S1]]* noundef %[[TEMP_LVALUE]]) +// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %[[STRUCT_S1]]*)*)(i8* %{{.*}}, i8* %{{.*}}, %[[STRUCT_S1]]* %[[TEMP_LVALUE]]) void test1(C *c) { c.f = S1(); diff --git a/clang/test/CodeGenObjCXX/property-dot-reference.mm b/clang/test/CodeGenObjCXX/property-dot-reference.mm index 31b970244c8250c0a45bc53b4e37711f72f49a47..853e21bcce84346acb57ed0331720342055dd31b 100644 --- a/clang/test/CodeGenObjCXX/property-dot-reference.mm +++ b/clang/test/CodeGenObjCXX/property-dot-reference.mm @@ -11,7 +11,7 @@ void GetURL() const; @implementation TNodeIconAndNameCell - (const TFENode&) node { -// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.TFENode* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend +// CHECK: call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.TFENode* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend // CHECK-NEXT: call void @_ZNK7TFENode6GetURLEv(%struct.TFENode* {{[^,]*}} %{{.*}}) self.node.GetURL(); } // expected-warning {{non-void function does not return a value}} @@ -27,12 +27,12 @@ void f0(const X &parent); - (const X&) target; @end void f1(A *a) { -// CHECK: [[PRP:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.X* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend -// CHECK-NEXT:call void @_Z2f0RK1X(%struct.X* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[PRP]]) +// CHECK: [[PRP:%.*]] = call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.X* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend +// CHECK-NEXT:call void @_Z2f0RK1X(%struct.X* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[PRP]]) f0(a.target); -// CHECK: [[MSG:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.X* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend -// CHECK-NEXT:call void @_Z2f0RK1X(%struct.X* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[MSG]]) +// CHECK: [[MSG:%.*]] = call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.X* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend +// CHECK-NEXT:call void @_Z2f0RK1X(%struct.X* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[MSG]]) f0([a target]); } @@ -51,12 +51,12 @@ void test2() { void(obj.myGetter); } // CHECK-LABEL: define{{.*}} void @_Z5test2v() -// CHECK: call noundef i32 bitcast -// CHECK: call noundef double bitcast -// CHECK: call noundef i32 bitcast -// CHECK: call noundef double bitcast -// CHECK: call noundef i32 bitcast -// CHECK: call noundef double bitcast +// CHECK: call i32 bitcast +// CHECK: call double bitcast +// CHECK: call i32 bitcast +// CHECK: call double bitcast +// CHECK: call i32 bitcast +// CHECK: call double bitcast // PR8751 int test3(Test2 *obj) { return obj.myProperty; } diff --git a/clang/test/CodeGenObjCXX/property-lvalue-capture.mm b/clang/test/CodeGenObjCXX/property-lvalue-capture.mm index 591d921fb6151a9c7c8bc17c0d4cbe4357e05d02..2a293702d9df988fab8838be71cb53038518a4a2 100644 --- a/clang/test/CodeGenObjCXX/property-lvalue-capture.mm +++ b/clang/test/CodeGenObjCXX/property-lvalue-capture.mm @@ -26,10 +26,10 @@ typedef Quad2 Quad2d; // CHECK: [[TWO:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_, align 8, !invariant.load ![[MD_NUM:[0-9]+]] // CHECK: [[THREE:%.*]] = bitcast [[ONET:%.*]]* [[ONE:%.*]] to i8* -// CHECK: [[CALL:%.*]] = call noundef nonnull align 1 %struct.Quad2* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %struct.Quad2* (i8*, i8*)*)(i8* noundef [[THREE]], i8* noundef [[TWO]]) +// CHECK: [[CALL:%.*]] = call nonnull align 1 %struct.Quad2* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %struct.Quad2* (i8*, i8*)*)(i8* [[THREE]], i8* [[TWO]]) // CHECK: [[FOUR:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_.2, align 8, !invariant.load ![[MD_NUM]] // CHECK: [[FIVE:%.*]] = bitcast [[ONET]]* [[ZERO:%.*]] to i8* -// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %struct.Quad2*)*)(i8* noundef [[FIVE]], i8* noundef [[FOUR]], %struct.Quad2* noundef nonnull align 1 [[CALL]]) +// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %struct.Quad2*)*)(i8* [[FIVE]], i8* [[FOUR]], %struct.Quad2* nonnull align 1 [[CALL]]) struct A { @@ -49,5 +49,5 @@ void test(C *c, const A &a) { // CHECK: [[ONE1:%.*]] = load %struct.A*, %struct.A** [[AADDR:%.*]], align 8 // CHECK: [[TWO1:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_.5, align 8, !invariant.load ![[MD_NUM]] // CHECK: [[THREE1:%.*]] = bitcast [[TWOT:%.*]]* [[ZERO1:%.*]] to i8* -// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %struct.A*)*)(i8* noundef [[THREE1]], i8* noundef [[TWO1]], %struct.A* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[ONE1]]) +// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %struct.A*)*)(i8* [[THREE1]], i8* [[TWO1]], %struct.A* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[ONE1]]) // CHECK: store %struct.A* [[ONE1]], %struct.A** [[RESULT:%.*]], align 8 diff --git a/clang/test/CodeGenObjCXX/property-lvalue-lambda.mm b/clang/test/CodeGenObjCXX/property-lvalue-lambda.mm index 1051887ecdb3e9dfbd260d1c42215e63abf447a2..80968ab2313641718d765dc16733c98d4fcc89f3 100644 --- a/clang/test/CodeGenObjCXX/property-lvalue-lambda.mm +++ b/clang/test/CodeGenObjCXX/property-lvalue-lambda.mm @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -fblocks -disable-llvm-passes -triple x86_64-apple-darwin10 -std=c++17 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -fblocks -disable-llvm-passes -triple x86_64-apple-darwin10 -std=c++17 -emit-llvm -o - %s | FileCheck %s typedef void (^blk_t)(); typedef void (*fnptr_t)(); diff --git a/clang/test/CodeGenObjCXX/property-object-reference-1.mm b/clang/test/CodeGenObjCXX/property-object-reference-1.mm index 56f763ddb39036f2ce961f11392355fb8bd565b3..4eb771329051c1d74ca22a10f234f9393459667c 100644 --- a/clang/test/CodeGenObjCXX/property-object-reference-1.mm +++ b/clang/test/CodeGenObjCXX/property-object-reference-1.mm @@ -28,4 +28,4 @@ struct TCPPObject // CHECK: store %struct.TCPPObject* [[cppObject:%.*]], %struct.TCPPObject** [[cppObjectaddr]], align 8 // CHECK: [[THREE:%.*]] = load %struct.TCPPObject*, %struct.TCPPObject** [[cppObjectaddr]], align 8 // CHECK: [[FOUR:%.*]] = bitcast %struct.TCPPObject* [[THREE]] to i8* -// CHECK: call void @objc_copyStruct(i8* noundef [[TWO:%.*]], i8* noundef [[FOUR]], i64 noundef 256, i1 noundef zeroext true, i1 noundef zeroext false) +// CHECK: call void @objc_copyStruct(i8* [[TWO:%.*]], i8* [[FOUR]], i64 256, i1 zeroext true, i1 zeroext false) diff --git a/clang/test/CodeGenObjCXX/property-object-reference-2.mm b/clang/test/CodeGenObjCXX/property-object-reference-2.mm index 71fd1f87462e64e90eaa11a0bf1b8be2e95caff9..11da855ff925c97c4f782c46175799fceac64599 100644 --- a/clang/test/CodeGenObjCXX/property-object-reference-2.mm +++ b/clang/test/CodeGenObjCXX/property-object-reference-2.mm @@ -29,31 +29,31 @@ struct TCPPObject @synthesize MyProperty1 = _cppObject1; @end -// CHECK-LABEL: define internal void @__copy_helper_atomic_property_(%struct.TCPPObject* noundef %0, %struct.TCPPObject* noundef %1) # +// CHECK-LABEL: define internal void @__copy_helper_atomic_property_(%struct.TCPPObject* %0, %struct.TCPPObject* %1) # // CHECK: [[TWO:%.*]] = load %struct.TCPPObject*, %struct.TCPPObject** [[ADDR:%.*]], align 8 // CHECK: [[THREE:%.*]] = load %struct.TCPPObject*, %struct.TCPPObject** [[ADDR1:%.*]], align 8 -// CHECK: [[CALL:%.*]] = call noundef i32 @_Z7DEFAULTv() -// CHECK: call void @_ZN10TCPPObjectC1ERKS_i(%struct.TCPPObject* {{[^,]*}} [[TWO]], %struct.TCPPObject* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[THREE]], i32 noundef [[CALL]]) +// CHECK: [[CALL:%.*]] = call i32 @_Z7DEFAULTv() +// CHECK: call void @_ZN10TCPPObjectC1ERKS_i(%struct.TCPPObject* {{[^,]*}} [[TWO]], %struct.TCPPObject* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[THREE]], i32 [[CALL]]) // CHECK: ret void // CHECK: define internal void @"\01-[MyDocument MyProperty]"( // CHECK: [[ONE:%.*]] = bitcast i8* [[ADDPTR:%.*]] to %struct.TCPPObject* // CHECK: [[TWO:%.*]] = bitcast %struct.TCPPObject* [[ONE]] to i8* // CHECK: [[THREE:%.*]] = bitcast %struct.TCPPObject* [[AGGRESULT:%.*]] to i8* -// CHECK: call void @objc_copyCppObjectAtomic(i8* noundef [[THREE]], i8* noundef [[TWO]], i8* noundef bitcast (void (%struct.TCPPObject*, %struct.TCPPObject*)* @__copy_helper_atomic_property_ to i8*)) +// CHECK: call void @objc_copyCppObjectAtomic(i8* [[THREE]], i8* [[TWO]], i8* bitcast (void (%struct.TCPPObject*, %struct.TCPPObject*)* @__copy_helper_atomic_property_ to i8*)) // CHECK: ret void -// CHECK-LABEL: define internal void @__assign_helper_atomic_property_(%struct.TCPPObject* noundef %0, %struct.TCPPObject* noundef %1) # +// CHECK-LABEL: define internal void @__assign_helper_atomic_property_(%struct.TCPPObject* %0, %struct.TCPPObject* %1) # // CHECK: [[THREE:%.*]] = load %struct.TCPPObject*, %struct.TCPPObject** [[ADDR1:%.*]], align 8 // CHECK: [[TWO:%.*]] = load %struct.TCPPObject*, %struct.TCPPObject** [[ADDR:%.*]], align 8 -// CHECK: [[CALL:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.TCPPObject* @_ZN10TCPPObjectaSERKS_(%struct.TCPPObject* {{[^,]*}} [[TWO]], %struct.TCPPObject* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[THREE]]) +// CHECK: [[CALL:%.*]] = call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.TCPPObject* @_ZN10TCPPObjectaSERKS_(%struct.TCPPObject* {{[^,]*}} [[TWO]], %struct.TCPPObject* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[THREE]]) // CHECK: ret void // CHECK: define internal void @"\01-[MyDocument setMyProperty:]"( // CHECK: [[ONE:%.*]] = bitcast i8* [[ADDRPTR:%.*]] to %struct.TCPPObject* // CHECK: [[TWO:%.*]] = bitcast %struct.TCPPObject* [[ONE]] to i8* // CHECK: [[THREE:%.*]] = bitcast %struct.TCPPObject* [[MYPROPERTY:%.*]] to i8* -// CHECK: call void @objc_copyCppObjectAtomic(i8* noundef [[TWO]], i8* noundef [[THREE]], i8* noundef bitcast (void (%struct.TCPPObject*, %struct.TCPPObject*)* @__assign_helper_atomic_property_ to i8*)) +// CHECK: call void @objc_copyCppObjectAtomic(i8* [[TWO]], i8* [[THREE]], i8* bitcast (void (%struct.TCPPObject*, %struct.TCPPObject*)* @__assign_helper_atomic_property_ to i8*)) // CHECK: ret void // CHECK-GNUSTEP: objc_getCppObjectAtomic diff --git a/clang/test/CodeGenObjCXX/property-objects.mm b/clang/test/CodeGenObjCXX/property-objects.mm index a5eb6202733649ca9b725a6ee91208a64b943ad9..149d1bd8e95db1c6b47058e7d5f80d1825477969 100644 --- a/clang/test/CodeGenObjCXX/property-objects.mm +++ b/clang/test/CodeGenObjCXX/property-objects.mm @@ -32,7 +32,7 @@ struct CGRect { @synthesize frame; // CHECK: define internal void @"\01-[I setPosition:]" -// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %class.S* @_ZN1SaSERKS_ +// CHECK: call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %class.S* @_ZN1SaSERKS_ // CHECK-NEXT: ret void // Don't attach debug locations to the prologue instructions. These were @@ -60,8 +60,8 @@ struct CGRect { @end // CHECK-LABEL: define{{.*}} i32 @main -// CHECK: call void @_ZN1SC1ERKS_(%class.S* {{[^,]*}} [[AGGTMP:%[a-zA-Z0-9\.]+]], %class.S* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) {{%[a-zA-Z0-9\.]+}}) -// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %class.S*)*)(i8* noundef {{%[a-zA-Z0-9\.]+}}, i8* noundef {{%[a-zA-Z0-9\.]+}}, %class.S* noundef [[AGGTMP]]) +// CHECK: call void @_ZN1SC1ERKS_(%class.S* {{[^,]*}} [[AGGTMP:%[a-zA-Z0-9\.]+]], %class.S* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) {{%[a-zA-Z0-9\.]+}}) +// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %class.S*)*)(i8* {{%[a-zA-Z0-9\.]+}}, i8* {{%[a-zA-Z0-9\.]+}}, %class.S* [[AGGTMP]]) // CHECK-NEXT: ret i32 0 int main() { I *i; @@ -73,8 +73,8 @@ int main() { // rdar://8379892 // CHECK-LABEL: define{{.*}} void @_Z1fP1A // CHECK: call void @_ZN1XC1Ev(%struct.X* {{[^,]*}} [[LVTEMP:%[a-zA-Z0-9\.]+]]) -// CHECK: call void @_ZN1XC1ERKS_(%struct.X* {{[^,]*}} [[AGGTMP:%[a-zA-Z0-9\.]+]], %struct.X* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[LVTEMP]]) -// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %struct.X*)*)({{.*}} %struct.X* noundef [[AGGTMP]]) +// CHECK: call void @_ZN1XC1ERKS_(%struct.X* {{[^,]*}} [[AGGTMP:%[a-zA-Z0-9\.]+]], %struct.X* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[LVTEMP]]) +// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %struct.X*)*)({{.*}} %struct.X* [[AGGTMP]]) struct X { X(); X(const X&); @@ -120,7 +120,7 @@ void testB1(B *b) { // CHECK: [[BVAR:%.*]] = alloca [[B]]*, align 8 // CHECK: [[TEMP:%.*]] = alloca [[B0:%.*]], align 8 // CHECK: [[X:%.*]] = getelementptr inbounds [[B0]], [[B0]]* [[TEMP]], i32 0, i32 0 -// CHECK-NEXT: [[T0:%.*]] = call noundef i32 @_Z9b_makeIntv() +// CHECK-NEXT: [[T0:%.*]] = call i32 @_Z9b_makeIntv() // CHECK-NEXT: [[T1:%.*]] = sext i32 [[T0]] to i64 // CHECK-NEXT: store i64 [[T1]], i64* [[X]], align 8 // CHECK: load [[B]]*, [[B]]** [[BVAR]] @@ -139,7 +139,7 @@ void testB1(B *b) { // CHECK-NOT: call // CHECK: store i64 [[T0]], // CHECK-NOT: call -// CHECK: [[T0:%.*]] = call noundef i32 @_Z9b_makeIntv() +// CHECK: [[T0:%.*]] = call i32 @_Z9b_makeIntv() // CHECK-NEXT: [[T1:%.*]] = sext i32 [[T0]] to i64 // CHECK-NEXT: store i64 [[T1]], i64* {{.*}}, align 8 // CHECK-NOT: call diff --git a/clang/test/CodeGenObjCXX/property-reference.mm b/clang/test/CodeGenObjCXX/property-reference.mm index 572360cedf989e387dc2798bca1b4b20ea1d8c69..db4537d999ad0693babb0bc39e64d861be19fe43 100644 --- a/clang/test/CodeGenObjCXX/property-reference.mm +++ b/clang/test/CodeGenObjCXX/property-reference.mm @@ -26,7 +26,7 @@ void test0() { const MyStruct& currentMyStruct = myClass.foo; } -// CHECK: [[C:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.MyStruct* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend +// CHECK: [[C:%.*]] = call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.MyStruct* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend // CHECK: store %struct.MyStruct* [[C]], %struct.MyStruct** [[D:%.*]] namespace test1 { @@ -40,7 +40,7 @@ namespace test1 { @implementation Test1 @synthesize prop1 = ivar; @end -// CHECK: define internal noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[A:%.*]]* @"\01-[Test1 prop1]"( +// CHECK: define internal nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[A:%.*]]* @"\01-[Test1 prop1]"( // CHECK: [[SELF:%.*]] = alloca [[TEST1:%.*]]*, align 8 // CHECK: [[T0:%.*]] = load [[TEST1]]*, [[TEST1]]** [[SELF]] // CHECK-NEXT: [[T1:%.*]] = bitcast [[TEST1]]* [[T0]] to i8* @@ -49,7 +49,7 @@ namespace test1 { // CHECK-NEXT: ret [[A]]* [[T3]] // CHECK: define internal void @"\01-[Test1 setProp1:]"( -// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[A]]* @_ZN5test11AaSERKS0_( +// CHECK: call nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[A]]* @_ZN5test11AaSERKS0_( // CHECK-NEXT: ret void // rdar://problem/10497174 diff --git a/clang/test/CodeGenObjCXX/selector-expr-lvalue.mm b/clang/test/CodeGenObjCXX/selector-expr-lvalue.mm index 2fa52d51d3bbe26adca3c4c08003f029137583b4..bd726863110d9283dd755e1ec2863460f496aedb 100644 --- a/clang/test/CodeGenObjCXX/selector-expr-lvalue.mm +++ b/clang/test/CodeGenObjCXX/selector-expr-lvalue.mm @@ -13,7 +13,7 @@ // CHECK-LABEL: define internal void @"\01-[NSObject Meth]"( - (void)Meth { -// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i8**, i8**)*){{.*}}, i8** noundef @[[setpriosel]]) +// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i8**, i8**)*){{.*}}, i8** @[[setpriosel]]) [self respondsToSelector:@selector(setPriority:) ps:&@selector(setPriority:)]; } - (void)setPriority:(int)p { diff --git a/clang/test/CodeGenObjCXX/synthesized-property-cleanup.mm b/clang/test/CodeGenObjCXX/synthesized-property-cleanup.mm index 385f87194ac2990d30779785a464276b82aa77b8..5accd52531613d254c61c7e5c9384196d49cf8ca 100644 --- a/clang/test/CodeGenObjCXX/synthesized-property-cleanup.mm +++ b/clang/test/CodeGenObjCXX/synthesized-property-cleanup.mm @@ -10,7 +10,7 @@ // CHECK: define {{.*}}@"\01-[MyData setData:]" // CHECK: [[DATA:%.*]] = alloca %struct.Data -// CHECK: call noundef %struct.Data* @_ZN4DataD1Ev(%struct.Data* {{[^,]*}} [[DATA]]){{.*}}, !dbg [[DATA_PROPERTY_LOC:![0-9]+]] +// CHECK: call %struct.Data* @_ZN4DataD1Ev(%struct.Data* {{[^,]*}} [[DATA]]){{.*}}, !dbg [[DATA_PROPERTY_LOC:![0-9]+]] // CHECK-NEXT: ret void // CHECK: define {{.*}}@"\01-[MyData string]" diff --git a/clang/test/CodeGenObjCXX/ubsan-nullability-return-notypeloc.mm b/clang/test/CodeGenObjCXX/ubsan-nullability-return-notypeloc.mm index 7397c292689744b3003fc597a4be898d800e098f..2f2cc1fc6554c3c9eb8419bffc07162740ac9a85 100644 --- a/clang/test/CodeGenObjCXX/ubsan-nullability-return-notypeloc.mm +++ b/clang/test/CodeGenObjCXX/ubsan-nullability-return-notypeloc.mm @@ -3,7 +3,7 @@ // CHECK: [[ATTR_LOC:@[0-9]+]] = {{.*}} global { {{.*}} i32 15, i32 38 // CHECK-LABEL: define{{.*}} i8* @_Z3foov() -// CHECK: [[CALL:%.*]] = call noundef i8* @_Z6helperv() +// CHECK: [[CALL:%.*]] = call i8* @_Z6helperv() // CHECK: icmp ne i8* [[CALL]] // CHECK: call void @__ubsan_handle_nullability_return_v1_abort({{.*}}[[ATTR_LOC]] diff --git a/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl b/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl index 93cb79f1cd02ae86f1d462b9539940e106a279d5..d24c9c5f85a4b12e6e67d2e79f697cabc0841acf 100644 --- a/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl +++ b/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl @@ -45,7 +45,7 @@ struct LargeStructTwoMember { struct LargeStructOneMember g_s; #endif -// X86-LABEL: define{{.*}} void @foo(%struct.Mat4X4* noalias sret(%struct.Mat4X4) align 4 %agg.result, %struct.Mat3X3* noundef byval(%struct.Mat3X3) align 4 %in) +// X86-LABEL: define{{.*}} void @foo(%struct.Mat4X4* noalias sret(%struct.Mat4X4) align 4 %agg.result, %struct.Mat3X3* byval(%struct.Mat3X3) align 4 %in) // AMDGCN-LABEL: define{{.*}} %struct.Mat4X4 @foo([9 x i32] %in.coerce) Mat4X4 __attribute__((noinline)) foo(Mat3X3 in) { Mat4X4 out; @@ -65,8 +65,8 @@ kernel void ker(global Mat3X3 *in, global Mat4X4 *out) { out[0] = foo(in[1]); } -// X86-LABEL: define{{.*}} void @foo_large(%struct.Mat64X64* noalias sret(%struct.Mat64X64) align 4 %agg.result, %struct.Mat32X32* noundef byval(%struct.Mat32X32) align 4 %in) -// AMDGCN-LABEL: define{{.*}} void @foo_large(%struct.Mat64X64 addrspace(5)* noalias sret(%struct.Mat64X64) align 4 %agg.result, %struct.Mat32X32 addrspace(5)* noundef byval(%struct.Mat32X32) align 4 %in) +// X86-LABEL: define{{.*}} void @foo_large(%struct.Mat64X64* noalias sret(%struct.Mat64X64) align 4 %agg.result, %struct.Mat32X32* byval(%struct.Mat32X32) align 4 %in) +// AMDGCN-LABEL: define{{.*}} void @foo_large(%struct.Mat64X64 addrspace(5)* noalias sret(%struct.Mat64X64) align 4 %agg.result, %struct.Mat32X32 addrspace(5)* byval(%struct.Mat32X32) align 4 %in) Mat64X64 __attribute__((noinline)) foo_large(Mat32X32 in) { Mat64X64 out; return out; @@ -88,7 +88,7 @@ void FuncOneMember(struct StructOneMember u) { u.x = (int2)(0, 0); } -// AMDGCN-LABEL: define{{.*}} void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* noundef byval(%struct.LargeStructOneMember) align 8 %u) +// AMDGCN-LABEL: define{{.*}} void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* byval(%struct.LargeStructOneMember) align 8 %u) // AMDGCN-NOT: addrspacecast // AMDGCN: store <2 x i32> %{{.*}}, <2 x i32> addrspace(5)* void FuncOneLargeMember(struct LargeStructOneMember u) { @@ -99,7 +99,7 @@ void FuncOneLargeMember(struct LargeStructOneMember u) { // AMDGCN20: %[[byval_temp:.*]] = alloca %struct.LargeStructOneMember, align 8, addrspace(5) // AMDGCN20: %[[r0:.*]] = bitcast %struct.LargeStructOneMember addrspace(5)* %[[byval_temp]] to i8 addrspace(5)* // AMDGCN20: call void @llvm.memcpy.p5i8.p1i8.i64(i8 addrspace(5)* align 8 %[[r0]], i8 addrspace(1)* align 8 bitcast (%struct.LargeStructOneMember addrspace(1)* @g_s to i8 addrspace(1)*), i64 800, i1 false) -// AMDGCN20: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* noundef byval(%struct.LargeStructOneMember) align 8 %[[byval_temp]]) +// AMDGCN20: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* byval(%struct.LargeStructOneMember) align 8 %[[byval_temp]]) #if (__OPENCL_C_VERSION__ == 200) || (__OPENCL_C_VERSION__ >= 300 && defined(__opencl_c_program_scope_global_variables)) void test_indirect_arg_globl(void) { FuncOneLargeMember(g_s); @@ -110,7 +110,7 @@ void test_indirect_arg_globl(void) { // AMDGCN: %[[byval_temp:.*]] = alloca %struct.LargeStructOneMember, align 8, addrspace(5) // AMDGCN: %[[r0:.*]] = bitcast %struct.LargeStructOneMember addrspace(5)* %[[byval_temp]] to i8 addrspace(5)* // AMDGCN: call void @llvm.memcpy.p5i8.p3i8.i64(i8 addrspace(5)* align 8 %[[r0]], i8 addrspace(3)* align 8 bitcast (%struct.LargeStructOneMember addrspace(3)* @test_indirect_arg_local.l_s to i8 addrspace(3)*), i64 800, i1 false) -// AMDGCN: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* noundef byval(%struct.LargeStructOneMember) align 8 %[[byval_temp]]) +// AMDGCN: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* byval(%struct.LargeStructOneMember) align 8 %[[byval_temp]]) kernel void test_indirect_arg_local(void) { local struct LargeStructOneMember l_s; FuncOneLargeMember(l_s); @@ -119,7 +119,7 @@ kernel void test_indirect_arg_local(void) { // AMDGCN-LABEL: define{{.*}} void @test_indirect_arg_private() // AMDGCN: %[[p_s:.*]] = alloca %struct.LargeStructOneMember, align 8, addrspace(5) // AMDGCN-NOT: @llvm.memcpy -// AMDGCN-NEXT: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* noundef byval(%struct.LargeStructOneMember) align 8 %[[p_s]]) +// AMDGCN-NEXT: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* byval(%struct.LargeStructOneMember) align 8 %[[p_s]]) void test_indirect_arg_private(void) { struct LargeStructOneMember p_s; FuncOneLargeMember(p_s); @@ -144,7 +144,7 @@ kernel void KernelOneMemberSpir(global struct StructOneMember* u) { // AMDGCN-LABEL: define{{.*}} amdgpu_kernel void @KernelLargeOneMember( // AMDGCN: %[[U:.*]] = alloca %struct.LargeStructOneMember, align 8, addrspace(5) // AMDGCN: store %struct.LargeStructOneMember %u.coerce, %struct.LargeStructOneMember addrspace(5)* %[[U]], align 8 -// AMDGCN: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* noundef byval(%struct.LargeStructOneMember) align 8 %[[U]]) +// AMDGCN: call void @FuncOneLargeMember(%struct.LargeStructOneMember addrspace(5)* byval(%struct.LargeStructOneMember) align 8 %[[U]]) kernel void KernelLargeOneMember(struct LargeStructOneMember u) { FuncOneLargeMember(u); } @@ -154,7 +154,7 @@ void FuncTwoMember(struct StructTwoMember u) { u.y = (int2)(0, 0); } -// AMDGCN-LABEL: define{{.*}} void @FuncLargeTwoMember(%struct.LargeStructTwoMember addrspace(5)* noundef byval(%struct.LargeStructTwoMember) align 8 %u) +// AMDGCN-LABEL: define{{.*}} void @FuncLargeTwoMember(%struct.LargeStructTwoMember addrspace(5)* byval(%struct.LargeStructTwoMember) align 8 %u) void FuncLargeTwoMember(struct LargeStructTwoMember u) { u.y[0] = (int2)(0, 0); } @@ -173,7 +173,7 @@ kernel void KernelTwoMember(struct StructTwoMember u) { // AMDGCN-SAME: (%struct.LargeStructTwoMember %[[u_coerce:.*]]) // AMDGCN: %[[u:.*]] = alloca %struct.LargeStructTwoMember, align 8, addrspace(5) // AMDGCN: store %struct.LargeStructTwoMember %[[u_coerce]], %struct.LargeStructTwoMember addrspace(5)* %[[u]] -// AMDGCN: call void @FuncLargeTwoMember(%struct.LargeStructTwoMember addrspace(5)* noundef byval(%struct.LargeStructTwoMember) align 8 %[[u]]) +// AMDGCN: call void @FuncLargeTwoMember(%struct.LargeStructTwoMember addrspace(5)* byval(%struct.LargeStructTwoMember) align 8 %[[u]]) kernel void KernelLargeTwoMember(struct LargeStructTwoMember u) { FuncLargeTwoMember(u); } diff --git a/clang/test/CodeGenOpenCL/address-spaces.cl b/clang/test/CodeGenOpenCL/address-spaces.cl index 5d59f960e91019f62b7f814eea657cc54f6954ba..b1c73561ade84959ece29662d36c87cf28ccfb37 100644 --- a/clang/test/CodeGenOpenCL/address-spaces.cl +++ b/clang/test/CodeGenOpenCL/address-spaces.cl @@ -72,10 +72,10 @@ int *ptr; // CL20AMDGCN-DAG: @ptr = {{(dso_local )?}}addrspace(1) global i32* null #endif -// SPIR: i32* noundef %arg -// AMDGCN: i32 addrspace(5)* noundef %arg -// CL20SPIR-DAG: i32 addrspace(4)* noundef %arg -// CL20AMDGCN-DAG: i32* noundef %arg +// SPIR: i32* %arg +// AMDGCN: i32 addrspace(5)* %arg +// CL20SPIR-DAG: i32 addrspace(4)* %arg +// CL20AMDGCN-DAG: i32* %arg void f(int *arg) { int i; @@ -92,7 +92,7 @@ void f(int *arg) { typedef int int_td; typedef int *intp_td; -// SPIR: define {{(dso_local )?}}void @{{.*}}test_typedef{{.*}}(i32 addrspace(1)* noundef %x, i32 addrspace(2)* noundef %y, i32* noundef %z) +// SPIR: define {{(dso_local )?}}void @{{.*}}test_typedef{{.*}}(i32 addrspace(1)* %x, i32 addrspace(2)* %y, i32* %z) void test_typedef(global int_td *x, constant int_td *y, intp_td z) { *x = *y; *z = 0; diff --git a/clang/test/CodeGenOpenCL/amdgcn-automatic-variable.cl b/clang/test/CodeGenOpenCL/amdgcn-automatic-variable.cl index 35163f2fe97a54664cf0565dbde4825ec36ec99f..546a61a6ec9398e7914f2d936793f20ef573b3be 100644 --- a/clang/test/CodeGenOpenCL/amdgcn-automatic-variable.cl +++ b/clang/test/CodeGenOpenCL/amdgcn-automatic-variable.cl @@ -1,8 +1,8 @@ // RUN: %clang_cc1 -O0 -cl-std=CL1.2 -triple amdgcn---amdgizcl -emit-llvm %s -o - | FileCheck -check-prefixes=CHECK,CL12 %s // RUN: %clang_cc1 -O0 -cl-std=CL2.0 -triple amdgcn---amdgizcl -emit-llvm %s -o - | FileCheck -check-prefixes=CHECK,CL20 %s -// CL12-LABEL: define{{.*}} void @func1(i32 addrspace(5)* noundef %x) -// CL20-LABEL: define{{.*}} void @func1(i32* noundef %x) +// CL12-LABEL: define{{.*}} void @func1(i32 addrspace(5)* %x) +// CL20-LABEL: define{{.*}} void @func1(i32* %x) void func1(int *x) { // CL12: %[[x_addr:.*]] = alloca i32 addrspace(5)*{{.*}}addrspace(5) // CL12: store i32 addrspace(5)* %x, i32 addrspace(5)* addrspace(5)* %[[x_addr]] @@ -48,9 +48,9 @@ void func2(void) { // CL20: store i32* %[[r1]], i32* addrspace(5)* %lp2, align 8 int *lp2 = la; - // CL12: call void @func1(i32 addrspace(5)* noundef %lv1) + // CL12: call void @func1(i32 addrspace(5)* %lv1) // CL20: %[[r2:.*]] = addrspacecast i32 addrspace(5)* %lv1 to i32* - // CL20: call void @func1(i32* noundef %[[r2]]) + // CL20: call void @func1(i32* %[[r2]]) func1(&lv1); // CHECK: store i32 4, i32 addrspace(5)* %lvc diff --git a/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl b/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl index c85eb4fb3a88fde9e5aba0339f2e69a7694c48c2..0a8abf9a958e8d0a76051a526c3d070d2338e39c 100644 --- a/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl +++ b/clang/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl @@ -248,22 +248,22 @@ __kernel void kernel_single_struct_element_struct_arg(single_struct_element_stru // CHECK: void @kernel_different_size_type_pair_arg(%struct.different_size_type_pair %arg1.coerce) __kernel void kernel_different_size_type_pair_arg(different_size_type_pair arg1) { } -// CHECK: define{{.*}} void @func_f32_arg(float noundef %arg) +// CHECK: define{{.*}} void @func_f32_arg(float %arg) void func_f32_arg(float arg) { } -// CHECK: define{{.*}} void @func_v2i16_arg(<2 x i16> noundef %arg) +// CHECK: define{{.*}} void @func_v2i16_arg(<2 x i16> %arg) void func_v2i16_arg(short2 arg) { } -// CHECK: define{{.*}} void @func_v3i32_arg(<3 x i32> noundef %arg) +// CHECK: define{{.*}} void @func_v3i32_arg(<3 x i32> %arg) void func_v3i32_arg(int3 arg) { } -// CHECK: define{{.*}} void @func_v4i32_arg(<4 x i32> noundef %arg) +// CHECK: define{{.*}} void @func_v4i32_arg(<4 x i32> %arg) void func_v4i32_arg(int4 arg) { } -// CHECK: define{{.*}} void @func_v16i32_arg(<16 x i32> noundef %arg) +// CHECK: define{{.*}} void @func_v16i32_arg(<16 x i32> %arg) void func_v16i32_arg(int16 arg) { } -// CHECK: define{{.*}} void @func_v32i32_arg(<32 x i32> noundef %arg) +// CHECK: define{{.*}} void @func_v32i32_arg(<32 x i32> %arg) void func_v32i32_arg(int32 arg) { } // CHECK: define{{.*}} void @func_empty_struct_arg() @@ -308,7 +308,7 @@ void func_single_struct_element_struct_arg(single_struct_element_struct_arg_t ar // CHECK: void @func_different_size_type_pair_arg(i64 %arg1.coerce0, i32 %arg1.coerce1) void func_different_size_type_pair_arg(different_size_type_pair arg1) { } -// CHECK: void @func_flexible_array_arg(%struct.flexible_array addrspace(5)* nocapture noundef byval(%struct.flexible_array) align 4 %arg) +// CHECK: void @func_flexible_array_arg(%struct.flexible_array addrspace(5)* nocapture byval(%struct.flexible_array) align 4 %arg) void func_flexible_array_arg(flexible_array arg) { } // CHECK: define{{.*}} float @func_f32_ret() @@ -446,20 +446,20 @@ flexible_array func_flexible_array_ret() return s; } -// CHECK: define{{.*}} void @func_reg_state_lo(<4 x i32> noundef %arg0, <4 x i32> noundef %arg1, <4 x i32> noundef %arg2, i32 noundef %arg3, i32 %s.coerce0, float %s.coerce1, i32 %s.coerce2) +// CHECK: define{{.*}} void @func_reg_state_lo(<4 x i32> %arg0, <4 x i32> %arg1, <4 x i32> %arg2, i32 %arg3, i32 %s.coerce0, float %s.coerce1, i32 %s.coerce2) void func_reg_state_lo(int4 arg0, int4 arg1, int4 arg2, int arg3, struct_arg_t s) { } -// CHECK: define{{.*}} void @func_reg_state_hi(<4 x i32> noundef %arg0, <4 x i32> noundef %arg1, <4 x i32> noundef %arg2, i32 noundef %arg3, i32 noundef %arg4, %struct.struct_arg addrspace(5)* nocapture noundef byval(%struct.struct_arg) align 4 %s) +// CHECK: define{{.*}} void @func_reg_state_hi(<4 x i32> %arg0, <4 x i32> %arg1, <4 x i32> %arg2, i32 %arg3, i32 %arg4, %struct.struct_arg addrspace(5)* nocapture byval(%struct.struct_arg) align 4 %s) void func_reg_state_hi(int4 arg0, int4 arg1, int4 arg2, int arg3, int arg4, struct_arg_t s) { } // XXX - Why don't the inner structs flatten? -// CHECK: define{{.*}} void @func_reg_state_num_regs_nested_struct(<4 x i32> noundef %arg0, i32 noundef %arg1, i32 %arg2.coerce0, %struct.nested %arg2.coerce1, i32 %arg3.coerce0, %struct.nested %arg3.coerce1, %struct.num_regs_nested_struct addrspace(5)* nocapture noundef byval(%struct.num_regs_nested_struct) align 8 %arg4) +// CHECK: define{{.*}} void @func_reg_state_num_regs_nested_struct(<4 x i32> %arg0, i32 %arg1, i32 %arg2.coerce0, %struct.nested %arg2.coerce1, i32 %arg3.coerce0, %struct.nested %arg3.coerce1, %struct.num_regs_nested_struct addrspace(5)* nocapture byval(%struct.num_regs_nested_struct) align 8 %arg4) void func_reg_state_num_regs_nested_struct(int4 arg0, int arg1, num_regs_nested_struct arg2, num_regs_nested_struct arg3, num_regs_nested_struct arg4) { } -// CHECK: define{{.*}} void @func_double_nested_struct_arg(<4 x i32> noundef %arg0, i32 noundef %arg1, i32 %arg2.coerce0, %struct.double_nested %arg2.coerce1, i16 %arg2.coerce2) +// CHECK: define{{.*}} void @func_double_nested_struct_arg(<4 x i32> %arg0, i32 %arg1, i32 %arg2.coerce0, %struct.double_nested %arg2.coerce1, i16 %arg2.coerce2) void func_double_nested_struct_arg(int4 arg0, int arg1, double_nested_struct arg2) { } -// CHECK: define{{.*}} %struct.double_nested_struct @func_double_nested_struct_ret(<4 x i32> noundef %arg0, i32 noundef %arg1) +// CHECK: define{{.*}} %struct.double_nested_struct @func_double_nested_struct_ret(<4 x i32> %arg0, i32 %arg1) double_nested_struct func_double_nested_struct_ret(int4 arg0, int arg1) { double_nested_struct s = { 0 }; return s; @@ -468,55 +468,55 @@ double_nested_struct func_double_nested_struct_ret(int4 arg0, int arg1) { // CHECK: define{{.*}} void @func_large_struct_padding_arg_direct(i8 %arg.coerce0, i32 %arg.coerce1, i8 %arg.coerce2, i32 %arg.coerce3, i8 %arg.coerce4, i8 %arg.coerce5, i16 %arg.coerce6, i16 %arg.coerce7, [3 x i8] %arg.coerce8, i64 %arg.coerce9, i32 %arg.coerce10, i8 %arg.coerce11, i32 %arg.coerce12, i16 %arg.coerce13, i8 %arg.coerce14) void func_large_struct_padding_arg_direct(large_struct_padding arg) { } -// CHECK: define{{.*}} void @func_large_struct_padding_arg_store(%struct.large_struct_padding addrspace(1)* nocapture noundef %out, %struct.large_struct_padding addrspace(5)* nocapture noundef readonly byval(%struct.large_struct_padding) align 8 %arg) +// CHECK: define{{.*}} void @func_large_struct_padding_arg_store(%struct.large_struct_padding addrspace(1)* nocapture %out, %struct.large_struct_padding addrspace(5)* nocapture readonly byval(%struct.large_struct_padding) align 8 %arg) void func_large_struct_padding_arg_store(global large_struct_padding* out, large_struct_padding arg) { *out = arg; } -// CHECK: define{{.*}} void @v3i32_reg_count(<3 x i32> noundef %arg1, <3 x i32> noundef %arg2, <3 x i32> noundef %arg3, <3 x i32> noundef %arg4, i32 %arg5.coerce0, float %arg5.coerce1, i32 %arg5.coerce2) +// CHECK: define{{.*}} void @v3i32_reg_count(<3 x i32> %arg1, <3 x i32> %arg2, <3 x i32> %arg3, <3 x i32> %arg4, i32 %arg5.coerce0, float %arg5.coerce1, i32 %arg5.coerce2) void v3i32_reg_count(int3 arg1, int3 arg2, int3 arg3, int3 arg4, struct_arg_t arg5) { } // Function signature from blender, nothing should be passed byval. The v3i32 // should not count as 4 passed registers. -// CHECK: define{{.*}} void @v3i32_pair_reg_count(%struct.int3_pair addrspace(5)* nocapture noundef %arg0, <3 x i32> %arg1.coerce0, <3 x i32> %arg1.coerce1, <3 x i32> noundef %arg2, <3 x i32> %arg3.coerce0, <3 x i32> %arg3.coerce1, <3 x i32> noundef %arg4, float noundef %arg5) +// CHECK: define{{.*}} void @v3i32_pair_reg_count(%struct.int3_pair addrspace(5)* nocapture %arg0, <3 x i32> %arg1.coerce0, <3 x i32> %arg1.coerce1, <3 x i32> %arg2, <3 x i32> %arg3.coerce0, <3 x i32> %arg3.coerce1, <3 x i32> %arg4, float %arg5) void v3i32_pair_reg_count(int3_pair *arg0, int3_pair arg1, int3 arg2, int3_pair arg3, int3 arg4, float arg5) { } // Each short4 should fit pack into 2 registers. -// CHECK: define{{.*}} void @v4i16_reg_count(<4 x i16> noundef %arg0, <4 x i16> noundef %arg1, <4 x i16> noundef %arg2, <4 x i16> noundef %arg3, <4 x i16> noundef %arg4, <4 x i16> noundef %arg5, i32 %arg6.coerce0, i32 %arg6.coerce1, i32 %arg6.coerce2, i32 %arg6.coerce3) +// CHECK: define{{.*}} void @v4i16_reg_count(<4 x i16> %arg0, <4 x i16> %arg1, <4 x i16> %arg2, <4 x i16> %arg3, <4 x i16> %arg4, <4 x i16> %arg5, i32 %arg6.coerce0, i32 %arg6.coerce1, i32 %arg6.coerce2, i32 %arg6.coerce3) void v4i16_reg_count(short4 arg0, short4 arg1, short4 arg2, short4 arg3, short4 arg4, short4 arg5, struct_4regs arg6) { } -// CHECK: define{{.*}} void @v4i16_pair_reg_count_over(<4 x i16> noundef %arg0, <4 x i16> noundef %arg1, <4 x i16> noundef %arg2, <4 x i16> noundef %arg3, <4 x i16> noundef %arg4, <4 x i16> noundef %arg5, <4 x i16> noundef %arg6, %struct.struct_4regs addrspace(5)* nocapture noundef byval(%struct.struct_4regs) align 4 %arg7) +// CHECK: define{{.*}} void @v4i16_pair_reg_count_over(<4 x i16> %arg0, <4 x i16> %arg1, <4 x i16> %arg2, <4 x i16> %arg3, <4 x i16> %arg4, <4 x i16> %arg5, <4 x i16> %arg6, %struct.struct_4regs addrspace(5)* nocapture byval(%struct.struct_4regs) align 4 %arg7) void v4i16_pair_reg_count_over(short4 arg0, short4 arg1, short4 arg2, short4 arg3, short4 arg4, short4 arg5, short4 arg6, struct_4regs arg7) { } -// CHECK: define{{.*}} void @v3i16_reg_count(<3 x i16> noundef %arg0, <3 x i16> noundef %arg1, <3 x i16> noundef %arg2, <3 x i16> noundef %arg3, <3 x i16> noundef %arg4, <3 x i16> noundef %arg5, i32 %arg6.coerce0, i32 %arg6.coerce1, i32 %arg6.coerce2, i32 %arg6.coerce3) +// CHECK: define{{.*}} void @v3i16_reg_count(<3 x i16> %arg0, <3 x i16> %arg1, <3 x i16> %arg2, <3 x i16> %arg3, <3 x i16> %arg4, <3 x i16> %arg5, i32 %arg6.coerce0, i32 %arg6.coerce1, i32 %arg6.coerce2, i32 %arg6.coerce3) void v3i16_reg_count(short3 arg0, short3 arg1, short3 arg2, short3 arg3, short3 arg4, short3 arg5, struct_4regs arg6) { } -// CHECK: define{{.*}} void @v3i16_reg_count_over(<3 x i16> noundef %arg0, <3 x i16> noundef %arg1, <3 x i16> noundef %arg2, <3 x i16> noundef %arg3, <3 x i16> noundef %arg4, <3 x i16> noundef %arg5, <3 x i16> noundef %arg6, %struct.struct_4regs addrspace(5)* nocapture noundef byval(%struct.struct_4regs) align 4 %arg7) +// CHECK: define{{.*}} void @v3i16_reg_count_over(<3 x i16> %arg0, <3 x i16> %arg1, <3 x i16> %arg2, <3 x i16> %arg3, <3 x i16> %arg4, <3 x i16> %arg5, <3 x i16> %arg6, %struct.struct_4regs addrspace(5)* nocapture byval(%struct.struct_4regs) align 4 %arg7) void v3i16_reg_count_over(short3 arg0, short3 arg1, short3 arg2, short3 arg3, short3 arg4, short3 arg5, short3 arg6, struct_4regs arg7) { } -// CHECK: define{{.*}} void @v2i16_reg_count(<2 x i16> noundef %arg0, <2 x i16> noundef %arg1, <2 x i16> noundef %arg2, <2 x i16> noundef %arg3, <2 x i16> noundef %arg4, <2 x i16> noundef %arg5, <2 x i16> noundef %arg6, <2 x i16> noundef %arg7, <2 x i16> noundef %arg8, <2 x i16> noundef %arg9, <2 x i16> noundef %arg10, <2 x i16> noundef %arg11, i32 %arg13.coerce0, i32 %arg13.coerce1, i32 %arg13.coerce2, i32 %arg13.coerce3) +// CHECK: define{{.*}} void @v2i16_reg_count(<2 x i16> %arg0, <2 x i16> %arg1, <2 x i16> %arg2, <2 x i16> %arg3, <2 x i16> %arg4, <2 x i16> %arg5, <2 x i16> %arg6, <2 x i16> %arg7, <2 x i16> %arg8, <2 x i16> %arg9, <2 x i16> %arg10, <2 x i16> %arg11, i32 %arg13.coerce0, i32 %arg13.coerce1, i32 %arg13.coerce2, i32 %arg13.coerce3) void v2i16_reg_count(short2 arg0, short2 arg1, short2 arg2, short2 arg3, short2 arg4, short2 arg5, short2 arg6, short2 arg7, short2 arg8, short2 arg9, short2 arg10, short2 arg11, struct_4regs arg13) { } -// CHECK: define{{.*}} void @v2i16_reg_count_over(<2 x i16> noundef %arg0, <2 x i16> noundef %arg1, <2 x i16> noundef %arg2, <2 x i16> noundef %arg3, <2 x i16> noundef %arg4, <2 x i16> noundef %arg5, <2 x i16> noundef %arg6, <2 x i16> noundef %arg7, <2 x i16> noundef %arg8, <2 x i16> noundef %arg9, <2 x i16> noundef %arg10, <2 x i16> noundef %arg11, <2 x i16> noundef %arg12, %struct.struct_4regs addrspace(5)* nocapture noundef byval(%struct.struct_4regs) align 4 %arg13) +// CHECK: define{{.*}} void @v2i16_reg_count_over(<2 x i16> %arg0, <2 x i16> %arg1, <2 x i16> %arg2, <2 x i16> %arg3, <2 x i16> %arg4, <2 x i16> %arg5, <2 x i16> %arg6, <2 x i16> %arg7, <2 x i16> %arg8, <2 x i16> %arg9, <2 x i16> %arg10, <2 x i16> %arg11, <2 x i16> %arg12, %struct.struct_4regs addrspace(5)* nocapture byval(%struct.struct_4regs) align 4 %arg13) void v2i16_reg_count_over(short2 arg0, short2 arg1, short2 arg2, short2 arg3, short2 arg4, short2 arg5, short2 arg6, short2 arg7, short2 arg8, short2 arg9, short2 arg10, short2 arg11, short2 arg12, struct_4regs arg13) { } -// CHECK: define{{.*}} void @v2i8_reg_count(<2 x i8> noundef %arg0, <2 x i8> noundef %arg1, <2 x i8> noundef %arg2, <2 x i8> noundef %arg3, <2 x i8> noundef %arg4, <2 x i8> noundef %arg5, i32 %arg6.coerce0, i32 %arg6.coerce1, i32 %arg6.coerce2, i32 %arg6.coerce3) +// CHECK: define{{.*}} void @v2i8_reg_count(<2 x i8> %arg0, <2 x i8> %arg1, <2 x i8> %arg2, <2 x i8> %arg3, <2 x i8> %arg4, <2 x i8> %arg5, i32 %arg6.coerce0, i32 %arg6.coerce1, i32 %arg6.coerce2, i32 %arg6.coerce3) void v2i8_reg_count(char2 arg0, char2 arg1, char2 arg2, char2 arg3, char2 arg4, char2 arg5, struct_4regs arg6) { } -// CHECK: define{{.*}} void @v2i8_reg_count_over(<2 x i8> noundef %arg0, <2 x i8> noundef %arg1, <2 x i8> noundef %arg2, <2 x i8> noundef %arg3, <2 x i8> noundef %arg4, <2 x i8> noundef %arg5, i32 noundef %arg6, %struct.struct_4regs addrspace(5)* nocapture noundef byval(%struct.struct_4regs) align 4 %arg7) +// CHECK: define{{.*}} void @v2i8_reg_count_over(<2 x i8> %arg0, <2 x i8> %arg1, <2 x i8> %arg2, <2 x i8> %arg3, <2 x i8> %arg4, <2 x i8> %arg5, i32 %arg6, %struct.struct_4regs addrspace(5)* nocapture byval(%struct.struct_4regs) align 4 %arg7) void v2i8_reg_count_over(char2 arg0, char2 arg1, char2 arg2, char2 arg3, char2 arg4, char2 arg5, int arg6, struct_4regs arg7) { } -// CHECK: define{{.*}} void @num_regs_left_64bit_aggregate(<4 x i32> noundef %arg0, <4 x i32> noundef %arg1, <4 x i32> noundef %arg2, <3 x i32> noundef %arg3, [2 x i32] %arg4.coerce, i32 noundef %arg5) +// CHECK: define{{.*}} void @num_regs_left_64bit_aggregate(<4 x i32> %arg0, <4 x i32> %arg1, <4 x i32> %arg2, <3 x i32> %arg3, [2 x i32] %arg4.coerce, i32 %arg5) void num_regs_left_64bit_aggregate(int4 arg0, int4 arg1, int4 arg2, int3 arg3, struct_char_x8 arg4, int arg5) { } diff --git a/clang/test/CodeGenOpenCL/amdgpu-call-kernel.cl b/clang/test/CodeGenOpenCL/amdgpu-call-kernel.cl index 041bd836c694a3405cd27e4671df4ed1d3293728..9ecdeeb32c5b2c4d0a4e0c23d133c25037d36297 100755 --- a/clang/test/CodeGenOpenCL/amdgpu-call-kernel.cl +++ b/clang/test/CodeGenOpenCL/amdgpu-call-kernel.cl @@ -1,6 +1,6 @@ // REQUIRES: amdgpu-registered-target // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -S -emit-llvm -o - %s | FileCheck %s -// CHECK: define{{.*}} amdgpu_kernel void @test_call_kernel(i32 addrspace(1)* nocapture noundef %out) +// CHECK: define{{.*}} amdgpu_kernel void @test_call_kernel(i32 addrspace(1)* nocapture %out) // CHECK: store i32 4, i32 addrspace(1)* %out, align 4 kernel void test_kernel(global int *out) diff --git a/clang/test/CodeGenOpenCL/amdgpu-nullptr.cl b/clang/test/CodeGenOpenCL/amdgpu-nullptr.cl index ca9980b7bbac5bda0ed40921af55a3be4475fc6d..dfea0f8d9f969af52a7b6ea6c74733fe231ccfad 100644 --- a/clang/test/CodeGenOpenCL/amdgpu-nullptr.cl +++ b/clang/test/CodeGenOpenCL/amdgpu-nullptr.cl @@ -1,7 +1,7 @@ -// RUN: %clang_cc1 -disable-noundef-analysis %s -cl-std=CL2.0 -include opencl-c.h -triple amdgcn -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis %s -O0 -cl-std=CL2.0 -include opencl-c.h -triple amdgcn -emit-llvm -o - | FileCheck --check-prefix=NOOPT %s -// RUN: %clang_cc1 -disable-noundef-analysis %s -cl-std=CL2.0 -include opencl-c.h -triple amdgcn---opencl -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -disable-noundef-analysis %s -cl-std=CL2.0 -include opencl-c.h -triple amdgcn -fcommon -emit-llvm -o - | FileCheck %s --check-prefix=COMMON +// RUN: %clang_cc1 %s -cl-std=CL2.0 -include opencl-c.h -triple amdgcn -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 %s -O0 -cl-std=CL2.0 -include opencl-c.h -triple amdgcn -emit-llvm -o - | FileCheck --check-prefix=NOOPT %s +// RUN: %clang_cc1 %s -cl-std=CL2.0 -include opencl-c.h -triple amdgcn---opencl -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 %s -cl-std=CL2.0 -include opencl-c.h -triple amdgcn -fcommon -emit-llvm -o - | FileCheck %s --check-prefix=COMMON typedef struct { private char *p1; diff --git a/clang/test/CodeGenOpenCL/as_type.cl b/clang/test/CodeGenOpenCL/as_type.cl index 14fe797b8153a8be77af80a3693b69009ea8349a..295afa207ae40f32a13bd29d002108aeed2ce9c6 100644 --- a/clang/test/CodeGenOpenCL/as_type.cl +++ b/clang/test/CodeGenOpenCL/as_type.cl @@ -5,21 +5,21 @@ typedef __attribute__(( ext_vector_type(4) )) char char4; typedef __attribute__(( ext_vector_type(16) )) char char16; typedef __attribute__(( ext_vector_type(3) )) int int3; -//CHECK: define{{.*}} spir_func <3 x i8> @f1(<4 x i8> noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func <3 x i8> @f1(<4 x i8> %[[x:.*]]) //CHECK: %[[astype:.*]] = shufflevector <4 x i8> %[[x]], <4 x i8> poison, <3 x i32> //CHECK: ret <3 x i8> %[[astype]] char3 f1(char4 x) { return __builtin_astype(x, char3); } -//CHECK: define{{.*}} spir_func <4 x i8> @f2(<3 x i8> noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func <4 x i8> @f2(<3 x i8> %[[x:.*]]) //CHECK: %[[astype:.*]] = shufflevector <3 x i8> %[[x]], <3 x i8> poison, <4 x i32> //CHECK: ret <4 x i8> %[[astype]] char4 f2(char3 x) { return __builtin_astype(x, char4); } -//CHECK: define{{.*}} spir_func <3 x i8> @f3(i32 noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func <3 x i8> @f3(i32 %[[x:.*]]) //CHECK: %[[cast:.*]] = bitcast i32 %[[x]] to <4 x i8> //CHECK: %[[astype:.*]] = shufflevector <4 x i8> %[[cast]], <4 x i8> poison, <3 x i32> //CHECK: ret <3 x i8> %[[astype]] @@ -27,7 +27,7 @@ char3 f3(int x) { return __builtin_astype(x, char3); } -//CHECK: define{{.*}} spir_func <4 x i8> @f4(i32 noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func <4 x i8> @f4(i32 %[[x:.*]]) //CHECK: %[[astype:.*]] = bitcast i32 %[[x]] to <4 x i8> //CHECK-NOT: shufflevector //CHECK: ret <4 x i8> %[[astype]] @@ -35,7 +35,7 @@ char4 f4(int x) { return __builtin_astype(x, char4); } -//CHECK: define{{.*}} spir_func i32 @f5(<3 x i8> noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func i32 @f5(<3 x i8> %[[x:.*]]) //CHECK: %[[shuffle:.*]] = shufflevector <3 x i8> %[[x]], <3 x i8> poison, <4 x i32> //CHECK: %[[astype:.*]] = bitcast <4 x i8> %[[shuffle]] to i32 //CHECK: ret i32 %[[astype]] @@ -43,7 +43,7 @@ int f5(char3 x) { return __builtin_astype(x, int); } -//CHECK: define{{.*}} spir_func i32 @f6(<4 x i8> noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func i32 @f6(<4 x i8> %[[x:.*]]) //CHECK: %[[astype:.*]] = bitcast <4 x i8> %[[x]] to i32 //CHECK-NOT: shufflevector //CHECK: ret i32 %[[astype]] @@ -51,7 +51,7 @@ int f6(char4 x) { return __builtin_astype(x, int); } -//CHECK: define{{.*}} spir_func <3 x i8> @f7(<3 x i8> noundef returned %[[x:.*]]) +//CHECK: define{{.*}} spir_func <3 x i8> @f7(<3 x i8> returned %[[x:.*]]) //CHECK-NOT: bitcast //CHECK-NOT: shufflevector //CHECK: ret <3 x i8> %[[x]] @@ -59,7 +59,7 @@ char3 f7(char3 x) { return __builtin_astype(x, char3); } -//CHECK: define{{.*}} spir_func <3 x i32> @f8(<16 x i8> noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func <3 x i32> @f8(<16 x i8> %[[x:.*]]) //CHECK: %[[cast:.*]] = bitcast <16 x i8> %[[x]] to <4 x i32> //CHECK: %[[astype:.*]] = shufflevector <4 x i32> %[[cast]], <4 x i32> poison, <3 x i32> //CHECK: ret <3 x i32> %[[astype]] @@ -67,28 +67,28 @@ int3 f8(char16 x) { return __builtin_astype(x, int3); } -//CHECK: define{{.*}} spir_func i32 addrspace(1)* @addr_cast(i32* noundef readnone %[[x:.*]]) +//CHECK: define{{.*}} spir_func i32 addrspace(1)* @addr_cast(i32* readnone %[[x:.*]]) //CHECK: %[[cast:.*]] ={{.*}} addrspacecast i32* %[[x]] to i32 addrspace(1)* //CHECK: ret i32 addrspace(1)* %[[cast]] global int* addr_cast(int *x) { return __builtin_astype(x, global int*); } -//CHECK: define{{.*}} spir_func i32 addrspace(1)* @int_to_ptr(i32 noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func i32 addrspace(1)* @int_to_ptr(i32 %[[x:.*]]) //CHECK: %[[cast:.*]] = inttoptr i32 %[[x]] to i32 addrspace(1)* //CHECK: ret i32 addrspace(1)* %[[cast]] global int* int_to_ptr(int x) { return __builtin_astype(x, global int*); } -//CHECK: define{{.*}} spir_func i32 @ptr_to_int(i32* noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func i32 @ptr_to_int(i32* %[[x:.*]]) //CHECK: %[[cast:.*]] = ptrtoint i32* %[[x]] to i32 //CHECK: ret i32 %[[cast]] int ptr_to_int(int *x) { return __builtin_astype(x, int); } -//CHECK: define{{.*}} spir_func <3 x i8> @ptr_to_char3(i32* noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func <3 x i8> @ptr_to_char3(i32* %[[x:.*]]) //CHECK: %[[cast1:.*]] = ptrtoint i32* %[[x]] to i32 //CHECK: %[[cast2:.*]] = bitcast i32 %[[cast1]] to <4 x i8> //CHECK: %[[astype:.*]] = shufflevector <4 x i8> %[[cast2]], <4 x i8> poison, <3 x i32> @@ -97,7 +97,7 @@ char3 ptr_to_char3(int *x) { return __builtin_astype(x, char3); } -//CHECK: define{{.*}} spir_func i32* @char3_to_ptr(<3 x i8> noundef %[[x:.*]]) +//CHECK: define{{.*}} spir_func i32* @char3_to_ptr(<3 x i8> %[[x:.*]]) //CHECK: %[[astype:.*]] = shufflevector <3 x i8> %[[x]], <3 x i8> poison, <4 x i32> //CHECK: %[[cast1:.*]] = bitcast <4 x i8> %[[astype]] to i32 //CHECK: %[[cast2:.*]] = inttoptr i32 %[[cast1]] to i32* diff --git a/clang/test/CodeGenOpenCL/atomic-ops-libcall.cl b/clang/test/CodeGenOpenCL/atomic-ops-libcall.cl index f752a737cb3730b24f59c3e0ea861bb1c1c0439b..a6f7e14f29c3c9b79e56d4db6e3144a778f7f051 100644 --- a/clang/test/CodeGenOpenCL/atomic-ops-libcall.cl +++ b/clang/test/CodeGenOpenCL/atomic-ops-libcall.cl @@ -20,63 +20,63 @@ typedef enum memory_scope { void f(atomic_int *i, global atomic_int *gi, local atomic_int *li, private atomic_int *pi, atomic_uint *ui, int cmp, int order, int scope) { int x; - // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_load_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_load_4(i8* noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_load_4(i8 addrspace(4)* {{%[0-9]+}}, i32 5, i32 1) + // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_load_4(i8* {{%[0-9]+}}, i32 5, i32 1) x = __opencl_atomic_load(i, memory_order_seq_cst, memory_scope_work_group); - // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: call void @__opencl_atomic_store_4(i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) + // ARM: call void @__opencl_atomic_store_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) __opencl_atomic_store(i, 1, memory_order_seq_cst, memory_scope_work_group); // SPIR: %[[GP:[0-9]+]] = addrspacecast i8 addrspace(1)* {{%[0-9]+}} to i8 addrspace(4)* - // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* noundef %[[GP]], i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: call void @__opencl_atomic_store_4(i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* %[[GP]], i32 {{%[0-9]+}}, i32 5, i32 1) + // ARM: call void @__opencl_atomic_store_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) __opencl_atomic_store(gi, 1, memory_order_seq_cst, memory_scope_work_group); // SPIR: %[[GP:[0-9]+]] = addrspacecast i8 addrspace(3)* {{%[0-9]+}} to i8 addrspace(4)* - // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* noundef %[[GP]], i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: call void @__opencl_atomic_store_4(i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* %[[GP]], i32 {{%[0-9]+}}, i32 5, i32 1) + // ARM: call void @__opencl_atomic_store_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) __opencl_atomic_store(li, 1, memory_order_seq_cst, memory_scope_work_group); // SPIR: %[[GP:[0-9]+]] = addrspacecast i8* {{%[0-9]+}} to i8 addrspace(4)* - // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* noundef %[[GP]], i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: call void @__opencl_atomic_store_4(i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* %[[GP]], i32 {{%[0-9]+}}, i32 5, i32 1) + // ARM: call void @__opencl_atomic_store_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) __opencl_atomic_store(pi, 1, memory_order_seq_cst, memory_scope_work_group); - // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_add_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_add_4(i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_add_4(i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) + // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_add_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) x = __opencl_atomic_fetch_add(i, 3, memory_order_seq_cst, memory_scope_work_group); - // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_min_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_min_4(i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_min_4(i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) + // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_min_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) x = __opencl_atomic_fetch_min(i, 3, memory_order_seq_cst, memory_scope_work_group); - // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_umin_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) - // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_umin_4(i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 1) + // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_umin_4(i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) + // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_umin_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1) x = __opencl_atomic_fetch_min(ui, 3, memory_order_seq_cst, memory_scope_work_group); - // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 1) - // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* noundef {{%[0-9]+}}, i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 1) + // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 1) + // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* {{%[0-9]+}}, i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 1) x = __opencl_atomic_compare_exchange_strong(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_work_group); - // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 1) - // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* noundef {{%[0-9]+}}, i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 1) + // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 1) + // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* {{%[0-9]+}}, i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 1) x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_work_group); - // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 2) - // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* noundef {{%[0-9]+}}, i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 2) + // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 2) + // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* {{%[0-9]+}}, i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 2) x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_device); - // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 3) - // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* noundef {{%[0-9]+}}, i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 3) + // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 3) + // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* {{%[0-9]+}}, i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 3) x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_all_svm_devices); #ifdef cl_khr_subgroups - // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef 5, i32 noundef 5, i32 noundef 4) + // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 4) x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_sub_group); #endif - // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* noundef {{%[0-9]+}}, i8 addrspace(4)* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef %{{.*}}, i32 noundef %{{.*}}, i32 noundef %{{.*}}) - // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* noundef {{%[0-9]+}}, i8* noundef {{%[0-9]+}}, i32 noundef {{%[0-9]+}}, i32 noundef %{{.*}}, i32 noundef %{{.*}}, i32 noundef %{{.*}}) + // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) + // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* {{%[0-9]+}}, i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}}) x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, order, order, scope); } diff --git a/clang/test/CodeGenOpenCL/blocks.cl b/clang/test/CodeGenOpenCL/blocks.cl index e669c42a75364e0de3f0819973e7514103de9f69..f8315515f1d9d939b96c932cc27213c534358f30 100644 --- a/clang/test/CodeGenOpenCL/blocks.cl +++ b/clang/test/CodeGenOpenCL/blocks.cl @@ -9,8 +9,8 @@ // AMDGCN: @__block_literal_global = internal addrspace(1) constant { i32, i32, i8* } { i32 16, i32 8, i8* bitcast (void (i8*, i8 addrspace(3)*)* @block_A_block_invoke to i8*) } // COMMON-NOT: .str -// SPIR-LABEL: define internal {{.*}}void @block_A_block_invoke(i8 addrspace(4)* noundef %.block_descriptor, i8 addrspace(3)* noundef %a) -// AMDGCN-LABEL: define internal {{.*}}void @block_A_block_invoke(i8* noundef %.block_descriptor, i8 addrspace(3)* noundef %a) +// SPIR-LABEL: define internal {{.*}}void @block_A_block_invoke(i8 addrspace(4)* %.block_descriptor, i8 addrspace(3)* %a) +// AMDGCN-LABEL: define internal {{.*}}void @block_A_block_invoke(i8* %.block_descriptor, i8 addrspace(3)* %a) void (^block_A)(local void *) = ^(local void *a) { return; }; @@ -40,7 +40,7 @@ void foo(){ // SPIR: store %struct.__opencl_block_literal_generic addrspace(4)* %[[blk_gen_ptr]], %struct.__opencl_block_literal_generic addrspace(4)** %[[block_B:.*]], // SPIR: %[[block_literal:.*]] = load %struct.__opencl_block_literal_generic addrspace(4)*, %struct.__opencl_block_literal_generic addrspace(4)** %[[block_B]] // SPIR: %[[blk_gen_ptr:.*]] = bitcast %struct.__opencl_block_literal_generic addrspace(4)* %[[block_literal]] to i8 addrspace(4)* - // SPIR: call {{.*}}i32 @__foo_block_invoke(i8 addrspace(4)* noundef %[[blk_gen_ptr]]) + // SPIR: call {{.*}}i32 @__foo_block_invoke(i8 addrspace(4)* %[[blk_gen_ptr]]) // AMDGCN: %[[block_invoke:.*]] = getelementptr inbounds <{ i32, i32, i8*, i32 }>, <{ i32, i32, i8*, i32 }> addrspace(5)* %[[block:.*]], i32 0, i32 2 // AMDGCN: store i8* bitcast (i32 (i8*)* @__foo_block_invoke to i8*), i8* addrspace(5)* %[[block_invoke]] // AMDGCN: %[[block_captured:.*]] = getelementptr inbounds <{ i32, i32, i8*, i32 }>, <{ i32, i32, i8*, i32 }> addrspace(5)* %[[block]], i32 0, i32 3 @@ -51,7 +51,7 @@ void foo(){ // AMDGCN: store %struct.__opencl_block_literal_generic* %[[blk_gen_ptr]], %struct.__opencl_block_literal_generic* addrspace(5)* %[[block_B:.*]], // AMDGCN: %[[block_literal:.*]] = load %struct.__opencl_block_literal_generic*, %struct.__opencl_block_literal_generic* addrspace(5)* %[[block_B]] // AMDGCN: %[[blk_gen_ptr:.*]] = bitcast %struct.__opencl_block_literal_generic* %[[block_literal]] to i8* - // AMDGCN: call {{.*}}i32 @__foo_block_invoke(i8* noundef %[[blk_gen_ptr]]) + // AMDGCN: call {{.*}}i32 @__foo_block_invoke(i8* %[[blk_gen_ptr]]) int (^ block_B)(void) = ^{ return i; @@ -59,11 +59,11 @@ void foo(){ block_B(); } -// SPIR-LABEL: define internal {{.*}}i32 @__foo_block_invoke(i8 addrspace(4)* noundef %.block_descriptor) +// SPIR-LABEL: define internal {{.*}}i32 @__foo_block_invoke(i8 addrspace(4)* %.block_descriptor) // SPIR: %[[block:.*]] = bitcast i8 addrspace(4)* %.block_descriptor to <{ i32, i32, i8 addrspace(4)*, i32 }> addrspace(4)* // SPIR: %[[block_capture_addr:.*]] = getelementptr inbounds <{ i32, i32, i8 addrspace(4)*, i32 }>, <{ i32, i32, i8 addrspace(4)*, i32 }> addrspace(4)* %[[block]], i32 0, i32 3 // SPIR: %[[block_capture:.*]] = load i32, i32 addrspace(4)* %[[block_capture_addr]] -// AMDGCN-LABEL: define internal {{.*}}i32 @__foo_block_invoke(i8* noundef %.block_descriptor) +// AMDGCN-LABEL: define internal {{.*}}i32 @__foo_block_invoke(i8* %.block_descriptor) // AMDGCN: %[[block:.*]] = bitcast i8* %.block_descriptor to <{ i32, i32, i8*, i32 }>* // AMDGCN: %[[block_capture_addr:.*]] = getelementptr inbounds <{ i32, i32, i8*, i32 }>, <{ i32, i32, i8*, i32 }>* %[[block]], i32 0, i32 3 // AMDGCN: %[[block_capture:.*]] = load i32, i32* %[[block_capture_addr]] diff --git a/clang/test/CodeGenOpenCL/byval.cl b/clang/test/CodeGenOpenCL/byval.cl index a889e660b14539e7155e95be0503a17e6540174a..05c72c514ca267322e0d9e5554f8e296460d75f5 100644 --- a/clang/test/CodeGenOpenCL/byval.cl +++ b/clang/test/CodeGenOpenCL/byval.cl @@ -8,8 +8,8 @@ int f(struct A a); int g() { struct A a; - // CHECK: call i32 @f(%struct.A addrspace(5)* noundef byval{{.*}}%a) + // CHECK: call i32 @f(%struct.A addrspace(5)* byval{{.*}}%a) return f(a); } -// CHECK: declare i32 @f(%struct.A addrspace(5)* noundef byval{{.*}}) +// CHECK: declare i32 @f(%struct.A addrspace(5)* byval{{.*}}) diff --git a/clang/test/CodeGenOpenCL/cl20-device-side-enqueue.cl b/clang/test/CodeGenOpenCL/cl20-device-side-enqueue.cl index 39ee88f31afb5c4086760b437762a652ea59eed2..afae12f7d25aaf094743aa66e4d6d39f0cbfecda 100644 --- a/clang/test/CodeGenOpenCL/cl20-device-side-enqueue.cl +++ b/clang/test/CodeGenOpenCL/cl20-device-side-enqueue.cl @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -disable-noundef-analysis %s -cl-std=CL2.0 -ffake-address-space-map -O0 -emit-llvm -o - -triple "spir-unknown-unknown" | FileCheck %s --check-prefix=COMMON --check-prefix=B32 -// RUN: %clang_cc1 -disable-noundef-analysis %s -cl-std=CL2.0 -ffake-address-space-map -O0 -emit-llvm -o - -triple "spir64-unknown-unknown" | FileCheck %s --check-prefix=COMMON --check-prefix=B64 -// RUN: %clang_cc1 -disable-noundef-analysis %s -cl-std=CL2.0 -ffake-address-space-map -O1 -emit-llvm -o - -triple "spir64-unknown-unknown" | FileCheck %s --check-prefix=CHECK-LIFETIMES +// RUN: %clang_cc1 %s -cl-std=CL2.0 -ffake-address-space-map -O0 -emit-llvm -o - -triple "spir-unknown-unknown" | FileCheck %s --check-prefix=COMMON --check-prefix=B32 +// RUN: %clang_cc1 %s -cl-std=CL2.0 -ffake-address-space-map -O0 -emit-llvm -o - -triple "spir64-unknown-unknown" | FileCheck %s --check-prefix=COMMON --check-prefix=B64 +// RUN: %clang_cc1 %s -cl-std=CL2.0 -ffake-address-space-map -O1 -emit-llvm -o - -triple "spir64-unknown-unknown" | FileCheck %s --check-prefix=CHECK-LIFETIMES #pragma OPENCL EXTENSION cl_khr_subgroups : enable diff --git a/clang/test/CodeGenOpenCL/const-str-array-decay.cl b/clang/test/CodeGenOpenCL/const-str-array-decay.cl index 69c28e6dedb501723105f0546d0c319bfae5f9b9..353aa3a9a083d458d6994beb25e5e6c93a26912e 100644 --- a/clang/test/CodeGenOpenCL/const-str-array-decay.cl +++ b/clang/test/CodeGenOpenCL/const-str-array-decay.cl @@ -6,6 +6,6 @@ kernel void str_array_decy() { test_func("Test string literal"); } -// CHECK: i8 addrspace(2)* noundef getelementptr inbounds ([20 x i8], [20 x i8] addrspace(2)* +// CHECK: i8 addrspace(2)* getelementptr inbounds ([20 x i8], [20 x i8] addrspace(2)* // CHECK-NOT: addrspacecast diff --git a/clang/test/CodeGenOpenCL/constant-addr-space-globals.cl b/clang/test/CodeGenOpenCL/constant-addr-space-globals.cl index d5ed9e2943abb4e9e5c85add072d15c726ebe803..8f7c0a12fcc611e872e61d4cf161d4ac5fb84f2e 100644 --- a/clang/test/CodeGenOpenCL/constant-addr-space-globals.cl +++ b/clang/test/CodeGenOpenCL/constant-addr-space-globals.cl @@ -26,6 +26,6 @@ kernel void k(void) { constant int var1 = 1; - // CHECK: call spir_func void @foo(i32 addrspace(2)* noundef @k.var1, i32 addrspace(2)* noundef getelementptr inbounds ([3 x i32], [3 x i32] addrspace(2)* @k.arr1, i64 0, i64 0) + // CHECK: call spir_func void @foo(i32 addrspace(2)* @k.var1, i32 addrspace(2)* getelementptr inbounds ([3 x i32], [3 x i32] addrspace(2)* @k.arr1, i64 0, i64 0) foo(&var1, arr1, arr2, arr3); } diff --git a/clang/test/CodeGenOpenCL/convergent.cl b/clang/test/CodeGenOpenCL/convergent.cl index 46e3c082894851deb179e7799bded8ad974b187c..086a3ab4e8b0700458bc424f7a8bf7c291852d9a 100644 --- a/clang/test/CodeGenOpenCL/convergent.cl +++ b/clang/test/CodeGenOpenCL/convergent.cl @@ -1,5 +1,4 @@ -// RUN: %clang_cc1 -triple spir-unknown-unknown -emit-llvm %s -o - -fno-experimental-new-pass-manager | opt -instnamer -S | FileCheck -enable-var-scope %s -// RUN: %clang_cc1 -triple spir-unknown-unknown -emit-llvm %s -o - -fexperimental-new-pass-manager | opt -instnamer -S | FileCheck -enable-var-scope %s +// RUN: %clang_cc1 -triple spir-unknown-unknown -emit-llvm %s -o - | opt -instnamer -S | FileCheck -enable-var-scope %s // This is initially assumed convergent, but can be deduced to not require it. @@ -28,7 +27,7 @@ void g(void); // non_convfun(); // } // -// CHECK-LABEL: define{{.*}} spir_func void @test_merge_if(i32 noundef %a) local_unnamed_addr #1 { +// CHECK-LABEL: define{{.*}} spir_func void @test_merge_if(i32 %a) local_unnamed_addr #1 { // CHECK: %[[tobool:.+]] = icmp eq i32 %a, 0 // CHECK: br i1 %[[tobool]], label %[[if_end3_critedge:.+]], label %[[if_then:.+]] @@ -61,7 +60,7 @@ void test_merge_if(int a) { // Test two if's are not merged. -// CHECK-LABEL: define{{.*}} spir_func void @test_no_merge_if(i32 noundef %a) local_unnamed_addr #1 +// CHECK-LABEL: define{{.*}} spir_func void @test_no_merge_if(i32 %a) local_unnamed_addr #1 // CHECK: %[[tobool:.+]] = icmp eq i32 %a, 0 // CHECK: br i1 %[[tobool]], label %[[if_end:.+]], label %[[if_then:.+]] // CHECK: [[if_then]]: diff --git a/clang/test/CodeGenOpenCL/fpmath.cl b/clang/test/CodeGenOpenCL/fpmath.cl index 904c508d00f7ee1e0bdb14ef253445c47cef3f6e..374b58c9bc04ead03802d32607c3c4d24ea99add 100644 --- a/clang/test/CodeGenOpenCL/fpmath.cl +++ b/clang/test/CodeGenOpenCL/fpmath.cl @@ -25,8 +25,8 @@ float4 spvectordiv(float4 a, float4 b) { void printf(constant char* fmt, ...); void testdbllit(long *val) { - // CHECK-FLT: float noundef 2.000000e+01 - // CHECK-DBL: double noundef 2.000000e+01 + // CHECK-FLT: float 2.000000e+01 + // CHECK-DBL: double 2.000000e+01 printf("%f", 20.0); } diff --git a/clang/test/CodeGenOpenCL/half.cl b/clang/test/CodeGenOpenCL/half.cl index 6ade7e691aa93ad1498fc612844e4a81358b2d6e..eae8cdcb03ec3b9cd896060732ba2a9ef20da068 100644 --- a/clang/test/CodeGenOpenCL/half.cl +++ b/clang/test/CodeGenOpenCL/half.cl @@ -15,7 +15,7 @@ half test() // CHECK: half 0xH3260 } -// CHECK-LABEL: @test_inc(half noundef %x) +// CHECK-LABEL: @test_inc(half %x) // CHECK: [[INC:%.*]] = fadd half %x, 0xH3C00 // CHECK: ret half [[INC]] half test_inc(half x) @@ -30,12 +30,12 @@ __attribute__((overloadable)) float min(float, float); __kernel void foo( __global half* buf, __global float* buf2 ) { buf[0] = min( buf[0], 1.5h ); -// CHECK: half noundef 0xH3E00 +// CHECK: half 0xH3E00 buf[0] = min( buf2[0], 1.5f ); -// CHECK: float noundef 1.500000e+00 +// CHECK: float 1.500000e+00 const half one = 1.6666; buf[1] = min( buf[1], one ); -// CHECK: half noundef 0xH3EAB +// CHECK: half 0xH3EAB } diff --git a/clang/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl b/clang/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl index a8853b7e68ad640fce1614515701ec899aad64ac..3b5a784d7cdf0de5b0ec98fb50ece5caa3b305ee 100644 --- a/clang/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl +++ b/clang/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl @@ -28,7 +28,7 @@ kernel void test_single(int_single input, global int* output) { // CHECK: spir_kernel // AMDGCN: define{{.*}} amdgpu_kernel void @test_single // CHECK: struct.int_single* nocapture {{.*}} byval(%struct.int_single) -// CHECK: i32* nocapture noundef %output +// CHECK: i32* nocapture %output output[0] = input.a; } @@ -36,7 +36,7 @@ kernel void test_pair(int_pair input, global int* output) { // CHECK: spir_kernel // AMDGCN: define{{.*}} amdgpu_kernel void @test_pair // CHECK: struct.int_pair* nocapture {{.*}} byval(%struct.int_pair) -// CHECK: i32* nocapture noundef %output +// CHECK: i32* nocapture %output output[0] = (int)input.a; output[1] = (int)input.b; } @@ -45,7 +45,7 @@ kernel void test_kernel(test_struct input, global int* output) { // CHECK: spir_kernel // AMDGCN: define{{.*}} amdgpu_kernel void @test_kernel // CHECK: struct.test_struct* nocapture {{.*}} byval(%struct.test_struct) -// CHECK: i32* nocapture noundef %output +// CHECK: i32* nocapture %output output[0] = input.elementA; output[1] = input.elementB; output[2] = (int)input.elementC; @@ -59,7 +59,7 @@ kernel void test_kernel(test_struct input, global int* output) { void test_function(int_pair input, global int* output) { // CHECK-NOT: spir_kernel // AMDGCN-NOT: define{{.*}} amdgpu_kernel void @test_function -// CHECK: i64 %input.coerce0, i64 %input.coerce1, i32* nocapture noundef %output +// CHECK: i64 %input.coerce0, i64 %input.coerce1, i32* nocapture %output output[0] = (int)input.a; output[1] = (int)input.b; } diff --git a/clang/test/CodeGenOpenCL/no-half.cl b/clang/test/CodeGenOpenCL/no-half.cl index 5f10ddd1aca248e527ae617d7c197dd04589f172..aee8f678f01a51c2901ea5013253c78051f4ef1b 100644 --- a/clang/test/CodeGenOpenCL/no-half.cl +++ b/clang/test/CodeGenOpenCL/no-half.cl @@ -4,7 +4,7 @@ #pragma OPENCL EXTENSION cl_khr_fp64:enable -// CHECK-LABEL: @test_store_float(float noundef %foo, half addrspace({{.}}){{.*}} %bar) +// CHECK-LABEL: @test_store_float(float %foo, half addrspace({{.}}){{.*}} %bar) __kernel void test_store_float(float foo, __global half* bar) { __builtin_store_halff(foo, bar); @@ -12,7 +12,7 @@ __kernel void test_store_float(float foo, __global half* bar) // CHECK: store half [[HALF_VAL]], half addrspace({{.}})* %bar, align 2 } -// CHECK-LABEL: @test_store_double(double noundef %foo, half addrspace({{.}}){{.*}} %bar) +// CHECK-LABEL: @test_store_double(double %foo, half addrspace({{.}}){{.*}} %bar) __kernel void test_store_double(double foo, __global half* bar) { __builtin_store_half(foo, bar); diff --git a/clang/test/CodeGenOpenCL/overload.cl b/clang/test/CodeGenOpenCL/overload.cl index 1c1eb7f586392469378020731686fec19f9d0a40..bc844595a59a50c60a2d68e7197789f17cfb5f9b 100644 --- a/clang/test/CodeGenOpenCL/overload.cl +++ b/clang/test/CodeGenOpenCL/overload.cl @@ -3,9 +3,9 @@ typedef short short4 __attribute__((ext_vector_type(4))); -// CHECK-DAG: declare spir_func <4 x i16> @_Z5clampDv4_sS_S_(<4 x i16> noundef, <4 x i16> noundef, <4 x i16> noundef) +// CHECK-DAG: declare spir_func <4 x i16> @_Z5clampDv4_sS_S_(<4 x i16>, <4 x i16>, <4 x i16>) short4 __attribute__ ((overloadable)) clamp(short4 x, short4 minval, short4 maxval); -// CHECK-DAG: declare spir_func <4 x i16> @_Z5clampDv4_sss(<4 x i16> noundef, i16 noundef signext, i16 noundef signext) +// CHECK-DAG: declare spir_func <4 x i16> @_Z5clampDv4_sss(<4 x i16>, i16 signext, i16 signext) short4 __attribute__ ((overloadable)) clamp(short4 x, short minval, short maxval); void __attribute__((overloadable)) foo(global int *a, global int *b); void __attribute__((overloadable)) foo(generic int *a, generic int *b); @@ -21,18 +21,18 @@ void kernel test1() { generic int *generic *gengen; generic int *local *genloc; generic int *global *genglob; - // CHECK-DAG: call spir_func void @_Z3fooPU3AS1iS0_(i32 addrspace(1)* noundef undef, i32 addrspace(1)* noundef undef) + // CHECK-DAG: call spir_func void @_Z3fooPU3AS1iS0_(i32 addrspace(1)* undef, i32 addrspace(1)* undef) foo(a, b); - // CHECK-DAG: call spir_func void @_Z3fooPU3AS4iS0_(i32 addrspace(4)* noundef undef, i32 addrspace(4)* noundef undef) + // CHECK-DAG: call spir_func void @_Z3fooPU3AS4iS0_(i32 addrspace(4)* undef, i32 addrspace(4)* undef) foo(b, c); - // CHECK-DAG: call spir_func void @_Z3fooPU3AS4iS0_(i32 addrspace(4)* noundef undef, i32 addrspace(4)* noundef undef) + // CHECK-DAG: call spir_func void @_Z3fooPU3AS4iS0_(i32 addrspace(4)* undef, i32 addrspace(4)* undef) foo(a, d); - // CHECK-DAG: call spir_func void @_Z3barPU3AS4PU3AS4iS2_(i32 addrspace(4)* addrspace(4)* noundef undef, i32 addrspace(4)* addrspace(4)* noundef undef) + // CHECK-DAG: call spir_func void @_Z3barPU3AS4PU3AS4iS2_(i32 addrspace(4)* addrspace(4)* undef, i32 addrspace(4)* addrspace(4)* undef) bar(gengen, genloc); - // CHECK-DAG: call spir_func void @_Z3barPU3AS4PU3AS4iS2_(i32 addrspace(4)* addrspace(4)* noundef undef, i32 addrspace(4)* addrspace(4)* noundef undef) + // CHECK-DAG: call spir_func void @_Z3barPU3AS4PU3AS4iS2_(i32 addrspace(4)* addrspace(4)* undef, i32 addrspace(4)* addrspace(4)* undef) bar(gengen, genglob); - // CHECK-DAG: call spir_func void @_Z3barPU3AS1PU3AS4iS2_(i32 addrspace(4)* addrspace(1)* noundef undef, i32 addrspace(4)* addrspace(1)* noundef undef) + // CHECK-DAG: call spir_func void @_Z3barPU3AS1PU3AS4iS2_(i32 addrspace(4)* addrspace(1)* undef, i32 addrspace(4)* addrspace(1)* undef) bar(genglob, genglob); } @@ -40,8 +40,8 @@ void kernel test1() { void kernel test2() { short4 e0=0; - // CHECK-DAG: call spir_func <4 x i16> @_Z5clampDv4_sss(<4 x i16> noundef zeroinitializer, i16 noundef signext 0, i16 noundef signext 255) + // CHECK-DAG: call spir_func <4 x i16> @_Z5clampDv4_sss(<4 x i16> zeroinitializer, i16 signext 0, i16 signext 255) clamp(e0, 0, 255); - // CHECK-DAG: call spir_func <4 x i16> @_Z5clampDv4_sS_S_(<4 x i16> noundef zeroinitializer, <4 x i16> noundef zeroinitializer, <4 x i16> noundef zeroinitializer) + // CHECK-DAG: call spir_func <4 x i16> @_Z5clampDv4_sS_S_(<4 x i16> zeroinitializer, <4 x i16> zeroinitializer, <4 x i16> zeroinitializer) clamp(e0, e0, e0); } diff --git a/clang/test/CodeGenOpenCL/printf.cl b/clang/test/CodeGenOpenCL/printf.cl index 2764d29859a39abe9f03ff610bc2fe2d94d8b7ce..8c63796d876ba33c4778ee0a81933cdba87e8a9c 100644 --- a/clang/test/CodeGenOpenCL/printf.cl +++ b/clang/test/CodeGenOpenCL/printf.cl @@ -1,9 +1,9 @@ -// RUN: %clang_cc1 -disable-noundef-analysis -cl-std=CL1.2 -cl-ext=-+cl_khr_fp64 -triple spir-unknown-unknown -disable-llvm-passes -emit-llvm -o - %s | FileCheck -check-prefixes=FP64,ALL %s -// RUN: %clang_cc1 -disable-noundef-analysis -cl-std=CL1.2 -cl-ext=-cl_khr_fp64 -triple spir-unknown-unknown -disable-llvm-passes -emit-llvm -o - %s | FileCheck -check-prefixes=NOFP64,ALL %s -// RUN: %clang_cc1 -disable-noundef-analysis -cl-std=CL3.0 -cl-ext=+__opencl_c_fp64,+cl_khr_fp64 -triple spir-unknown-unknown -disable-llvm-passes -emit-llvm -o - %s | FileCheck -check-prefixes=FP64,ALL %s -// RUN: %clang_cc1 -disable-noundef-analysis -cl-std=CL3.0 -cl-ext=-__opencl_c_fp64,-cl_khr_fp64 -triple spir-unknown-unknown -disable-llvm-passes -emit-llvm -o - %s | FileCheck -check-prefixes=NOFP64,ALL %s -// RUN: %clang_cc1 -disable-noundef-analysis -cl-std=clc++2021 -cl-ext=+__opencl_c_fp64,+cl_khr_fp64 -triple spir-unknown-unknown -disable-llvm-passes -emit-llvm -o - %s | FileCheck -check-prefixes=FP64,ALL %s -// RUN: %clang_cc1 -disable-noundef-analysis -cl-std=clc++2021 -cl-ext=-__opencl_c_fp64,-cl_khr_fp64 -triple spir-unknown-unknown -disable-llvm-passes -emit-llvm -o - %s | FileCheck -check-prefixes=NOFP64,ALL %s +// RUN: %clang_cc1 -cl-std=CL1.2 -cl-ext=-+cl_khr_fp64 -triple spir-unknown-unknown -disable-llvm-passes -emit-llvm -o - %s | FileCheck -check-prefixes=FP64,ALL %s +// RUN: %clang_cc1 -cl-std=CL1.2 -cl-ext=-cl_khr_fp64 -triple spir-unknown-unknown -disable-llvm-passes -emit-llvm -o - %s | FileCheck -check-prefixes=NOFP64,ALL %s +// RUN: %clang_cc1 -cl-std=CL3.0 -cl-ext=+__opencl_c_fp64,+cl_khr_fp64 -triple spir-unknown-unknown -disable-llvm-passes -emit-llvm -o - %s | FileCheck -check-prefixes=FP64,ALL %s +// RUN: %clang_cc1 -cl-std=CL3.0 -cl-ext=-__opencl_c_fp64,-cl_khr_fp64 -triple spir-unknown-unknown -disable-llvm-passes -emit-llvm -o - %s | FileCheck -check-prefixes=NOFP64,ALL %s +// RUN: %clang_cc1 -cl-std=clc++2021 -cl-ext=+__opencl_c_fp64,+cl_khr_fp64 -triple spir-unknown-unknown -disable-llvm-passes -emit-llvm -o - %s | FileCheck -check-prefixes=FP64,ALL %s +// RUN: %clang_cc1 -cl-std=clc++2021 -cl-ext=-__opencl_c_fp64,-cl_khr_fp64 -triple spir-unknown-unknown -disable-llvm-passes -emit-llvm -o - %s | FileCheck -check-prefixes=NOFP64,ALL %s typedef __attribute__((ext_vector_type(2))) float float2; typedef __attribute__((ext_vector_type(2))) half half2; diff --git a/clang/test/CodeGenOpenCL/size_t.cl b/clang/test/CodeGenOpenCL/size_t.cl index 2b00e0da60212d94615be6b9fda4f8e205edd0a0..b9bb72ac45a0e22946feef0975cb422e527d2b05 100644 --- a/clang/test/CodeGenOpenCL/size_t.cl +++ b/clang/test/CodeGenOpenCL/size_t.cl @@ -3,74 +3,74 @@ // RUN: %clang_cc1 %s -cl-std=CL2.0 -finclude-default-header -fdeclare-opencl-builtins -emit-llvm -O0 -triple amdgcn -o - | FileCheck --check-prefix=SZ64 --check-prefix=AMDGCN %s // RUN: %clang_cc1 %s -cl-std=CL2.0 -finclude-default-header -fdeclare-opencl-builtins -emit-llvm -O0 -triple amdgcn---opencl -o - | FileCheck --check-prefix=SZ64 --check-prefix=AMDGCN %s -//SZ32: define{{.*}} i32 @test_ptrtoint_private(i8* noundef %x) +//SZ32: define{{.*}} i32 @test_ptrtoint_private(i8* %x) //SZ32: ptrtoint i8* %{{.*}} to i32 -//SZ64ONLY: define{{.*}} i64 @test_ptrtoint_private(i8* noundef %x) +//SZ64ONLY: define{{.*}} i64 @test_ptrtoint_private(i8* %x) //SZ64ONLY: ptrtoint i8* %{{.*}} to i64 -//AMDGCN: define{{.*}} i64 @test_ptrtoint_private(i8 addrspace(5)* noundef %x) +//AMDGCN: define{{.*}} i64 @test_ptrtoint_private(i8 addrspace(5)* %x) //AMDGCN: ptrtoint i8 addrspace(5)* %{{.*}} to i64 size_t test_ptrtoint_private(private char* x) { return (size_t)x; } -//SZ32: define{{.*}} i32 @test_ptrtoint_global(i8 addrspace(1)* noundef %x) +//SZ32: define{{.*}} i32 @test_ptrtoint_global(i8 addrspace(1)* %x) //SZ32: ptrtoint i8 addrspace(1)* %{{.*}} to i32 -//SZ64: define{{.*}} i64 @test_ptrtoint_global(i8 addrspace(1)* noundef %x) +//SZ64: define{{.*}} i64 @test_ptrtoint_global(i8 addrspace(1)* %x) //SZ64: ptrtoint i8 addrspace(1)* %{{.*}} to i64 intptr_t test_ptrtoint_global(global char* x) { return (intptr_t)x; } -//SZ32: define{{.*}} i32 @test_ptrtoint_constant(i8 addrspace(2)* noundef %x) +//SZ32: define{{.*}} i32 @test_ptrtoint_constant(i8 addrspace(2)* %x) //SZ32: ptrtoint i8 addrspace(2)* %{{.*}} to i32 -//SZ64ONLY: define{{.*}} i64 @test_ptrtoint_constant(i8 addrspace(2)* noundef %x) +//SZ64ONLY: define{{.*}} i64 @test_ptrtoint_constant(i8 addrspace(2)* %x) //SZ64ONLY: ptrtoint i8 addrspace(2)* %{{.*}} to i64 -//AMDGCN: define{{.*}} i64 @test_ptrtoint_constant(i8 addrspace(4)* noundef %x) +//AMDGCN: define{{.*}} i64 @test_ptrtoint_constant(i8 addrspace(4)* %x) //AMDGCN: ptrtoint i8 addrspace(4)* %{{.*}} to i64 uintptr_t test_ptrtoint_constant(constant char* x) { return (uintptr_t)x; } -//SZ32: define{{.*}} i32 @test_ptrtoint_local(i8 addrspace(3)* noundef %x) +//SZ32: define{{.*}} i32 @test_ptrtoint_local(i8 addrspace(3)* %x) //SZ32: ptrtoint i8 addrspace(3)* %{{.*}} to i32 -//SZ64: define{{.*}} i64 @test_ptrtoint_local(i8 addrspace(3)* noundef %x) +//SZ64: define{{.*}} i64 @test_ptrtoint_local(i8 addrspace(3)* %x) //SZ64: ptrtoint i8 addrspace(3)* %{{.*}} to i64 size_t test_ptrtoint_local(local char* x) { return (size_t)x; } -//SZ32: define{{.*}} i32 @test_ptrtoint_generic(i8 addrspace(4)* noundef %x) +//SZ32: define{{.*}} i32 @test_ptrtoint_generic(i8 addrspace(4)* %x) //SZ32: ptrtoint i8 addrspace(4)* %{{.*}} to i32 -//SZ64ONLY: define{{.*}} i64 @test_ptrtoint_generic(i8 addrspace(4)* noundef %x) +//SZ64ONLY: define{{.*}} i64 @test_ptrtoint_generic(i8 addrspace(4)* %x) //SZ64ONLY: ptrtoint i8 addrspace(4)* %{{.*}} to i64 -//AMDGCN: define{{.*}} i64 @test_ptrtoint_generic(i8* noundef %x) +//AMDGCN: define{{.*}} i64 @test_ptrtoint_generic(i8* %x) //AMDGCN: ptrtoint i8* %{{.*}} to i64 size_t test_ptrtoint_generic(generic char* x) { return (size_t)x; } -//SZ32: define{{.*}} i8* @test_inttoptr_private(i32 noundef %x) +//SZ32: define{{.*}} i8* @test_inttoptr_private(i32 %x) //SZ32: inttoptr i32 %{{.*}} to i8* -//SZ64ONLY: define{{.*}} i8* @test_inttoptr_private(i64 noundef %x) +//SZ64ONLY: define{{.*}} i8* @test_inttoptr_private(i64 %x) //SZ64ONLY: inttoptr i64 %{{.*}} to i8* -//AMDGCN: define{{.*}} i8 addrspace(5)* @test_inttoptr_private(i64 noundef %x) +//AMDGCN: define{{.*}} i8 addrspace(5)* @test_inttoptr_private(i64 %x) //AMDGCN: trunc i64 %{{.*}} to i32 //AMDGCN: inttoptr i32 %{{.*}} to i8 addrspace(5)* private char* test_inttoptr_private(size_t x) { return (private char*)x; } -//SZ32: define{{.*}} i8 addrspace(1)* @test_inttoptr_global(i32 noundef %x) +//SZ32: define{{.*}} i8 addrspace(1)* @test_inttoptr_global(i32 %x) //SZ32: inttoptr i32 %{{.*}} to i8 addrspace(1)* -//SZ64: define{{.*}} i8 addrspace(1)* @test_inttoptr_global(i64 noundef %x) +//SZ64: define{{.*}} i8 addrspace(1)* @test_inttoptr_global(i64 %x) //SZ64: inttoptr i64 %{{.*}} to i8 addrspace(1)* global char* test_inttoptr_global(size_t x) { return (global char*)x; } -//SZ32: define{{.*}} i8 addrspace(3)* @test_add_local(i8 addrspace(3)* noundef %x, i32 noundef %y) +//SZ32: define{{.*}} i8 addrspace(3)* @test_add_local(i8 addrspace(3)* %x, i32 %y) //SZ32: getelementptr inbounds i8, i8 addrspace(3)* %{{.*}}, i32 -//SZ64: define{{.*}} i8 addrspace(3)* @test_add_local(i8 addrspace(3)* noundef %x, i64 noundef %y) +//SZ64: define{{.*}} i8 addrspace(3)* @test_add_local(i8 addrspace(3)* %x, i64 %y) //AMDGCN: trunc i64 %{{.*}} to i32 //AMDGCN: getelementptr inbounds i8, i8 addrspace(3)* %{{.*}}, i32 //SZ64ONLY: getelementptr inbounds i8, i8 addrspace(3)* %{{.*}}, i64 @@ -78,44 +78,44 @@ local char* test_add_local(local char* x, ptrdiff_t y) { return x + y; } -//SZ32: define{{.*}} i8 addrspace(1)* @test_add_global(i8 addrspace(1)* noundef %x, i32 noundef %y) +//SZ32: define{{.*}} i8 addrspace(1)* @test_add_global(i8 addrspace(1)* %x, i32 %y) //SZ32: getelementptr inbounds i8, i8 addrspace(1)* %{{.*}}, i32 -//SZ64: define{{.*}} i8 addrspace(1)* @test_add_global(i8 addrspace(1)* noundef %x, i64 noundef %y) +//SZ64: define{{.*}} i8 addrspace(1)* @test_add_global(i8 addrspace(1)* %x, i64 %y) //SZ64: getelementptr inbounds i8, i8 addrspace(1)* %{{.*}}, i64 global char* test_add_global(global char* x, ptrdiff_t y) { return x + y; } -//SZ32: define{{.*}} i32 @test_sub_local(i8 addrspace(3)* noundef %x, i8 addrspace(3)* noundef %y) +//SZ32: define{{.*}} i32 @test_sub_local(i8 addrspace(3)* %x, i8 addrspace(3)* %y) //SZ32: ptrtoint i8 addrspace(3)* %{{.*}} to i32 //SZ32: ptrtoint i8 addrspace(3)* %{{.*}} to i32 -//SZ64: define{{.*}} i64 @test_sub_local(i8 addrspace(3)* noundef %x, i8 addrspace(3)* noundef %y) +//SZ64: define{{.*}} i64 @test_sub_local(i8 addrspace(3)* %x, i8 addrspace(3)* %y) //SZ64: ptrtoint i8 addrspace(3)* %{{.*}} to i64 //SZ64: ptrtoint i8 addrspace(3)* %{{.*}} to i64 ptrdiff_t test_sub_local(local char* x, local char *y) { return x - y; } -//SZ32: define{{.*}} i32 @test_sub_private(i8* noundef %x, i8* noundef %y) +//SZ32: define{{.*}} i32 @test_sub_private(i8* %x, i8* %y) //SZ32: ptrtoint i8* %{{.*}} to i32 //SZ32: ptrtoint i8* %{{.*}} to i32 -//SZ64ONLY: define{{.*}} i64 @test_sub_private(i8* noundef %x, i8* noundef %y) +//SZ64ONLY: define{{.*}} i64 @test_sub_private(i8* %x, i8* %y) //SZ64ONLY: ptrtoint i8* %{{.*}} to i64 //SZ64ONLY: ptrtoint i8* %{{.*}} to i64 -//AMDGCN: define{{.*}} i64 @test_sub_private(i8 addrspace(5)* noundef %x, i8 addrspace(5)* noundef %y) +//AMDGCN: define{{.*}} i64 @test_sub_private(i8 addrspace(5)* %x, i8 addrspace(5)* %y) //AMDGCN: ptrtoint i8 addrspace(5)* %{{.*}} to i64 //AMDGCN: ptrtoint i8 addrspace(5)* %{{.*}} to i64 ptrdiff_t test_sub_private(private char* x, private char *y) { return x - y; } -//SZ32: define{{.*}} i32 @test_sub_mix(i8* noundef %x, i8 addrspace(4)* noundef %y) +//SZ32: define{{.*}} i32 @test_sub_mix(i8* %x, i8 addrspace(4)* %y) //SZ32: ptrtoint i8* %{{.*}} to i32 //SZ32: ptrtoint i8 addrspace(4)* %{{.*}} to i32 -//SZ64ONLY: define{{.*}} i64 @test_sub_mix(i8* noundef %x, i8 addrspace(4)* noundef %y) +//SZ64ONLY: define{{.*}} i64 @test_sub_mix(i8* %x, i8 addrspace(4)* %y) //SZ64ONLY: ptrtoint i8* %{{.*}} to i64 //SZ64ONLY: ptrtoint i8 addrspace(4)* %{{.*}} to i64 -//AMDGCN: define{{.*}} i64 @test_sub_mix(i8 addrspace(5)* noundef %x, i8* noundef %y) +//AMDGCN: define{{.*}} i64 @test_sub_mix(i8 addrspace(5)* %x, i8* %y) //AMDGCN: ptrtoint i8 addrspace(5)* %{{.*}} to i64 //AMDGCN: ptrtoint i8* %{{.*}} to i64 ptrdiff_t test_sub_mix(private char* x, generic char *y) { diff --git a/clang/test/CodeGenOpenCL/spir-calling-conv.cl b/clang/test/CodeGenOpenCL/spir-calling-conv.cl index 9bd70f8cedb24673fcfcb27a596d9fe370aa7d49..3c20a53fe30d0ec5ec746fe2d6195d4a228f3cdd 100644 --- a/clang/test/CodeGenOpenCL/spir-calling-conv.cl +++ b/clang/test/CodeGenOpenCL/spir-calling-conv.cl @@ -5,14 +5,14 @@ int get_dummy_id(int D); kernel void bar(global int *A); kernel void foo(global int *A) -// CHECK: define{{.*}} spir_kernel void @foo(i32 addrspace(1)* noundef %A) +// CHECK: define{{.*}} spir_kernel void @foo(i32 addrspace(1)* %A) { int id = get_dummy_id(0); - // CHECK: %{{[a-z0-9_]+}} = tail call spir_func i32 @get_dummy_id(i32 noundef 0) + // CHECK: %{{[a-z0-9_]+}} = tail call spir_func i32 @get_dummy_id(i32 0) A[id] = id; bar(A); - // CHECK: tail call spir_kernel void @bar(i32 addrspace(1)* noundef %A) + // CHECK: tail call spir_kernel void @bar(i32 addrspace(1)* %A) } -// CHECK: declare spir_func i32 @get_dummy_id(i32 noundef) -// CHECK: declare spir_kernel void @bar(i32 addrspace(1)* noundef) +// CHECK: declare spir_func i32 @get_dummy_id(i32) +// CHECK: declare spir_kernel void @bar(i32 addrspace(1)*) diff --git a/clang/test/CodeGenOpenCLCXX/address-space-deduction.clcpp b/clang/test/CodeGenOpenCLCXX/address-space-deduction.clcpp index d534b90cd9f1dace57a90296f04a722cc9bcae8a..e7c883bb8bcb8d16c0353f11337eaf38a9707a0b 100644 --- a/clang/test/CodeGenOpenCLCXX/address-space-deduction.clcpp +++ b/clang/test/CodeGenOpenCLCXX/address-space-deduction.clcpp @@ -21,7 +21,7 @@ int PTR glob_p = ADR(glob); //COMMON: @loc_ext_p = external addrspace(1) {{global|constant}} i32 addrspace(4)* //COMMON: @loc_ext = external addrspace(1) global i32 -//COMMON: define{{.*}} spir_func noundef i32 @_Z3fooi{{P|R}}U3AS4i(i32 noundef %par, i32 addrspace(4)*{{.*}} %par_p) +//COMMON: define{{.*}} spir_func i32 @_Z3fooi{{P|R}}U3AS4i(i32 %par, i32 addrspace(4)*{{.*}} %par_p) int foo(int par, int PTR par_p){ //COMMON: %loc = alloca i32 int loc; diff --git a/clang/test/CodeGenOpenCLCXX/addrspace-derived-base.clcpp b/clang/test/CodeGenOpenCLCXX/addrspace-derived-base.clcpp index 86c24092f2e09988d86a6eb0cf0439672327327f..6b087e75c4861f0b3673bc0f4096e98df8e3ce88 100644 --- a/clang/test/CodeGenOpenCLCXX/addrspace-derived-base.clcpp +++ b/clang/test/CodeGenOpenCLCXX/addrspace-derived-base.clcpp @@ -13,13 +13,13 @@ void foo() { D d; //CHECK-LABEL: foo //CHECK: addrspacecast %class.D* %d to %class.D addrspace(4)* - //CHECK: call spir_func noundef i32 @_ZNU3AS41D5getmbEv(%class.D addrspace(4)* + //CHECK: call spir_func i32 @_ZNU3AS41D5getmbEv(%class.D addrspace(4)* d.getmb(); } //Derived and Base are in the same address space. -//CHECK: define linkonce_odr spir_func noundef i32 @_ZNU3AS41D5getmbEv(%class.D addrspace(4)* {{[^,]*}} %this) +//CHECK: define linkonce_odr spir_func i32 @_ZNU3AS41D5getmbEv(%class.D addrspace(4)* {{[^,]*}} %this) //CHECK: bitcast %class.D addrspace(4)* %this1 to %struct.B addrspace(4)* diff --git a/clang/test/CodeGenOpenCLCXX/addrspace-new-delete.clcpp b/clang/test/CodeGenOpenCLCXX/addrspace-new-delete.clcpp index 85bd1ffe5ca160b18357af39cfc9cfc478bbe2a9..a78c0373ed1859917212d7ec32455116cb3ebb5a 100644 --- a/clang/test/CodeGenOpenCLCXX/addrspace-new-delete.clcpp +++ b/clang/test/CodeGenOpenCLCXX/addrspace-new-delete.clcpp @@ -9,7 +9,7 @@ public: }; void test_new_delete(A **a) { -// CHECK: %{{.*}} = call spir_func noundef i8 addrspace(4)* @_ZNU3AS41AnwEj(i32 {{.*}}) +// CHECK: %{{.*}} = call spir_func i8 addrspace(4)* @_ZNU3AS41AnwEj(i32 {{.*}}) *a = new A; // CHECK: call spir_func void @_ZNU3AS41AdlEPU3AS4v(i8 addrspace(4)* {{.*}}) delete *a; diff --git a/clang/test/CodeGenOpenCLCXX/addrspace-of-this.clcpp b/clang/test/CodeGenOpenCLCXX/addrspace-of-this.clcpp index 5b543c388537d8c6fc3e82d2771fd052724f44b4..50c146bae6ebbb1a016e216c6f1ea39e193c3e64 100644 --- a/clang/test/CodeGenOpenCLCXX/addrspace-of-this.clcpp +++ b/clang/test/CodeGenOpenCLCXX/addrspace-of-this.clcpp @@ -86,18 +86,18 @@ __kernel void test__global() { // COMMON-LABEL: @test__global() // Test the address space of 'this' when invoking a method. -// COMMON: call spir_func noundef i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) +// COMMON: call spir_func i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) // Test the address space of 'this' when invoking a method using a pointer to the object. -// COMMON: call spir_func noundef i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) +// COMMON: call spir_func i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) // Test the address space of 'this' when invoking a method that is declared in the file contex. -// COMMON: call spir_func noundef i32 @_ZNU3AS41C7outsideEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) +// COMMON: call spir_func i32 @_ZNU3AS41C7outsideEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) // Test the address space of 'this' when invoking copy-constructor. // COMMON: [[C1GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c1 to %class.C addrspace(4)* // IMPL: [[C1VOID:%[0-9]+]] = bitcast %class.C* %c1 to i8* // IMPL: call void @llvm.memcpy.p0i8.p4i8.i32(i8* {{.*}}[[C1VOID]], i8 addrspace(4)* {{.*}}addrspacecast (i8 addrspace(1)* bitcast (%class.C addrspace(1)* @c to i8 addrspace(1)*) to i8 addrspace(4)*) -// EXPL: call spir_func void @_ZNU3AS41CC1ERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) +// EXPL: call spir_func void @_ZNU3AS41CC1ERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) addrspacecast (%class.C addrspace(1)* @c to %class.C addrspace(4)*)) // Test the address space of 'this' when invoking a constructor. // EXPL: [[C2GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c2 to %class.C addrspace(4)* @@ -106,7 +106,7 @@ __kernel void test__global() { // Test the address space of 'this' when invoking assignment operator. // COMMON: [[C1GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c1 to %class.C addrspace(4)* // COMMON: [[C2GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c2 to %class.C addrspace(4)* -// EXPL: call spir_func noundef align 4 dereferenceable(4) %class.C addrspace(4)* @_ZNU3AS41CaSERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C2GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) [[C1GEN]]) +// EXPL: call spir_func align 4 dereferenceable(4) %class.C addrspace(4)* @_ZNU3AS41CaSERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C2GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) [[C1GEN]]) // IMPL: [[C2GENVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[C2GEN]] to i8 addrspace(4)* // IMPL: [[C1GENVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[C1GEN]] to i8 addrspace(4)* // IMPL: call void @llvm.memcpy.p4i8.p4i8.i32(i8 addrspace(4)* {{.*}}[[C2GENVOID]], i8 addrspace(4)* {{.*}}[[C1GENVOID]] @@ -114,20 +114,20 @@ __kernel void test__global() { // Test the address space of 'this' when invoking the operator+ // COMMON: [[C1GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c1 to %class.C addrspace(4)* // COMMON: [[C2GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c2 to %class.C addrspace(4)* -// COMMON: call spir_func void @_ZNU3AS41CplERU3AS4KS_(%class.C* sret(%class.C) align 4 %c3, %class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) [[C2GEN]]) +// COMMON: call spir_func void @_ZNU3AS41CplERU3AS4KS_(%class.C* sret(%class.C) align 4 %c3, %class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) [[C2GEN]]) // Test the address space of 'this' when invoking the move constructor // COMMON: [[C4GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c4 to %class.C addrspace(4)* -// COMMON: [[CALL:%call[0-9]+]] = call spir_func noundef align 4 dereferenceable(4) %class.C addrspace(4)* @_Z3foov() -// EXPL: call spir_func void @_ZNU3AS41CC1EOU3AS4S_(%class.C addrspace(4)* {{[^,]*}} [[C4GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) [[CALL]]) +// COMMON: [[CALL:%call[0-9]+]] = call spir_func align 4 dereferenceable(4) %class.C addrspace(4)* @_Z3foov() +// EXPL: call spir_func void @_ZNU3AS41CC1EOU3AS4S_(%class.C addrspace(4)* {{[^,]*}} [[C4GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) [[CALL]]) // IMPL: [[C4VOID:%[0-9]+]] = bitcast %class.C* %c4 to i8* // IMPL: [[CALLVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[CALL]] to i8 addrspace(4)* // IMPL: call void @llvm.memcpy.p0i8.p4i8.i32(i8* {{.*}}[[C4VOID]], i8 addrspace(4)* {{.*}}[[CALLVOID]] // Test the address space of 'this' when invoking the move assignment // COMMON: [[C5GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c5 to %class.C addrspace(4)* -// COMMON: [[CALL:%call[0-9]+]] = call spir_func noundef align 4 dereferenceable(4) %class.C addrspace(4)* @_Z3foov() -// EXPL: call spir_func void @_ZNU3AS41CC1EOU3AS4S_(%class.C addrspace(4)* {{[^,]*}} [[C5GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) [[CALL]]) +// COMMON: [[CALL:%call[0-9]+]] = call spir_func align 4 dereferenceable(4) %class.C addrspace(4)* @_Z3foov() +// EXPL: call spir_func void @_ZNU3AS41CC1EOU3AS4S_(%class.C addrspace(4)* {{[^,]*}} [[C5GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) [[CALL]]) // IMPL: [[C5VOID:%[0-9]+]] = bitcast %class.C* %c5 to i8* // IMPL: [[CALLVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[CALL]] to i8 addrspace(4)* // IMPL: call void @llvm.memcpy.p0i8.p4i8.i32(i8* {{.*}}[[C5VOID]], i8 addrspace(4)* {{.*}}[[CALLVOID]] @@ -152,11 +152,11 @@ TEST(__local) // EXPL-NOT: call spir_func void @_ZNU3AS41CC1Ev(%class.C addrspace(4)* addrspacecast (%class.C addrspace(3)* @_ZZ11test__localE1c to %class.C addrspace(4)*)) // Test the address space of 'this' when invoking a method. -// COMMON: call spir_func noundef i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(3)* @_ZZ11test__localE1c to %class.C addrspace(4)*)) +// COMMON: call spir_func i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} addrspacecast (%class.C addrspace(3)* @_ZZ11test__localE1c to %class.C addrspace(4)*)) // Test the address space of 'this' when invoking copy-constructor. // COMMON: [[C1GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c1 to %class.C addrspace(4)* -// EXPL: call spir_func void @_ZNU3AS41CC1ERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) addrspacecast (%class.C addrspace(3)* @_ZZ11test__localE1c to %class.C addrspace(4)*)) +// EXPL: call spir_func void @_ZNU3AS41CC1ERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) addrspacecast (%class.C addrspace(3)* @_ZZ11test__localE1c to %class.C addrspace(4)*)) // IMPL: [[C1VOID:%[0-9]+]] = bitcast %class.C* %c1 to i8* // IMPL: call void @llvm.memcpy.p0i8.p4i8.i32(i8* {{.*}}[[C1VOID]], i8 addrspace(4)* {{.*}}addrspacecast (i8 addrspace(3)* bitcast (%class.C addrspace(3)* @_ZZ11test__localE1c to i8 addrspace(3)*) to i8 addrspace(4)*), i32 4, i1 false) @@ -167,7 +167,7 @@ TEST(__local) // Test the address space of 'this' when invoking assignment operator. // COMMON: [[C1GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c1 to %class.C addrspace(4)* // COMMON: [[C2GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c2 to %class.C addrspace(4)* -// EXPL: call spir_func noundef align 4 dereferenceable(4) %class.C addrspace(4)* @_ZNU3AS41CaSERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C2GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) [[C1GEN]]) +// EXPL: call spir_func align 4 dereferenceable(4) %class.C addrspace(4)* @_ZNU3AS41CaSERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C2GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) [[C1GEN]]) // IMPL: [[C2GENVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[C2GEN]] to i8 addrspace(4)* // IMPL: [[C1GENVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[C1GEN]] to i8 addrspace(4)* // IMPL: call void @llvm.memcpy.p4i8.p4i8.i32(i8 addrspace(4)* {{.*}}[[C2GENVOID]], i8 addrspace(4)* {{.*}}[[C1GENVOID]] @@ -182,12 +182,12 @@ TEST(__private) // Test the address space of 'this' when invoking a method. // COMMON: [[CGEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c to %class.C addrspace(4)* -// COMMON: call spir_func noundef i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} [[CGEN]]) +// COMMON: call spir_func i32 @_ZNU3AS41C3getEv(%class.C addrspace(4)* {{[^,]*}} [[CGEN]]) // Test the address space of 'this' when invoking a copy-constructor. // COMMON: [[C1GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c1 to %class.C addrspace(4)* // COMMON: [[CGEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c to %class.C addrspace(4)* -// EXPL: call spir_func void @_ZNU3AS41CC1ERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) [[CGEN]]) +// EXPL: call spir_func void @_ZNU3AS41CC1ERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C1GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) [[CGEN]]) // IMPL: [[C1VOID:%[0-9]+]] = bitcast %class.C* %c1 to i8* // IMPL: [[CGENVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[CGEN]] to i8 addrspace(4)* // IMPL: call void @llvm.memcpy.p0i8.p4i8.i32(i8* {{.*}}[[C1VOID]], i8 addrspace(4)* {{.*}}[[CGENVOID]] @@ -199,7 +199,7 @@ TEST(__private) // Test the address space of 'this' when invoking a copy-assignment. // COMMON: [[C1GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c1 to %class.C addrspace(4)* // COMMON: [[C2GEN:%[.a-z0-9]+]] = addrspacecast %class.C* %c2 to %class.C addrspace(4)* -// EXPL: call spir_func noundef align 4 dereferenceable(4) %class.C addrspace(4)* @_ZNU3AS41CaSERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C2GEN]], %class.C addrspace(4)* noundef align 4 dereferenceable(4) [[C1GEN]]) +// EXPL: call spir_func align 4 dereferenceable(4) %class.C addrspace(4)* @_ZNU3AS41CaSERU3AS4KS_(%class.C addrspace(4)* {{[^,]*}} [[C2GEN]], %class.C addrspace(4)* align 4 dereferenceable(4) [[C1GEN]]) // IMPL: [[C2GENVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[C2GEN]] to i8 addrspace(4)* // IMPL: [[C1GENVOID:%[0-9]+]] = bitcast %class.C addrspace(4)* [[C1GEN]] to i8 addrspace(4)* // IMPL: call void @llvm.memcpy.p4i8.p4i8.i32(i8 addrspace(4)* {{.*}}[[C2GENVOID]], i8 addrspace(4)* {{.*}}[[C1GENVOID]] diff --git a/clang/test/CodeGenOpenCLCXX/addrspace-operators.clcpp b/clang/test/CodeGenOpenCLCXX/addrspace-operators.clcpp index 7bd344119d34a0719a6d6fcab858bb823bbe6759..bd3832635d9b1d872135d0b62aa7bf0b5478b9c1 100644 --- a/clang/test/CodeGenOpenCLCXX/addrspace-operators.clcpp +++ b/clang/test/CodeGenOpenCLCXX/addrspace-operators.clcpp @@ -20,10 +20,10 @@ __global int globI; void bar() { C c; //CHECK: [[A1:%[.a-z0-9]+]] ={{.*}} addrspacecast %class.C* [[C:%[a-z0-9]+]] to %class.C addrspace(4)* - //CHECK: call spir_func void @_ZNU3AS41C6AssignE1E(%class.C addrspace(4)* {{[^,]*}} [[A1]], i32 noundef 0) + //CHECK: call spir_func void @_ZNU3AS41C6AssignE1E(%class.C addrspace(4)* {{[^,]*}} [[A1]], i32 0) c.Assign(a); //CHECK: [[A2:%[.a-z0-9]+]] ={{.*}} addrspacecast %class.C* [[C]] to %class.C addrspace(4)* - //CHECK: call spir_func void @_ZNU3AS41C8OrAssignE1E(%class.C addrspace(4)* {{[^,]*}} [[A2]], i32 noundef 0) + //CHECK: call spir_func void @_ZNU3AS41C8OrAssignE1E(%class.C addrspace(4)* {{[^,]*}} [[A2]], i32 0) c.OrAssign(a); E e; diff --git a/clang/test/CodeGenOpenCLCXX/addrspace-references.clcpp b/clang/test/CodeGenOpenCLCXX/addrspace-references.clcpp index 52f192f264228fb2211874849a3b036f4c91f881..d8e83450a9e57e9baef5663acbc9f9d530853ce9 100644 --- a/clang/test/CodeGenOpenCLCXX/addrspace-references.clcpp +++ b/clang/test/CodeGenOpenCLCXX/addrspace-references.clcpp @@ -17,7 +17,7 @@ void scalar() { // CHECK: [[REF:%.*]] = alloca i32 // CHECK: store i32 1, i32* [[REF]] // CHECK: [[REG:%[.a-z0-9]+]] ={{.*}} addrspacecast i32* [[REF]] to i32 addrspace(4)* - // CHECK: call spir_func noundef i32 @_Z3barRU3AS4Kj(i32 addrspace(4)* noundef align 4 dereferenceable(4) [[REG]]) + // CHECK: call spir_func i32 @_Z3barRU3AS4Kj(i32 addrspace(4)* align 4 dereferenceable(4) [[REG]]) bar(1); } diff --git a/clang/test/CodeGenOpenCLCXX/addrspace-with-class.clcpp b/clang/test/CodeGenOpenCLCXX/addrspace-with-class.clcpp index 23bfe99ac390af700b18ed0cab93b4834e694307..c4051f93442e92bc5fe5bb50dc7884cca4325d66 100644 --- a/clang/test/CodeGenOpenCLCXX/addrspace-with-class.clcpp +++ b/clang/test/CodeGenOpenCLCXX/addrspace-with-class.clcpp @@ -23,15 +23,15 @@ __constant MyType const2(2); // CHECK: @glob ={{.*}} addrspace(1) global %struct.MyType zeroinitializer MyType glob(1); -// CHECK: call spir_func void @_ZNU3AS26MyTypeC1Ei(%struct.MyType addrspace(2)* {{[^,]*}} @const1, i32 noundef 1) -// CHECK: call spir_func void @_ZNU3AS26MyTypeC1Ei(%struct.MyType addrspace(2)* {{[^,]*}} @const2, i32 noundef 2) -// CHECK: call spir_func void @_ZNU3AS46MyTypeC1Ei(%struct.MyType addrspace(4)* {{[^,]*}} addrspacecast (%struct.MyType addrspace(1)* @glob to %struct.MyType addrspace(4)*), i32 noundef 1) +// CHECK: call spir_func void @_ZNU3AS26MyTypeC1Ei(%struct.MyType addrspace(2)* {{[^,]*}} @const1, i32 1) +// CHECK: call spir_func void @_ZNU3AS26MyTypeC1Ei(%struct.MyType addrspace(2)* {{[^,]*}} @const2, i32 2) +// CHECK: call spir_func void @_ZNU3AS46MyTypeC1Ei(%struct.MyType addrspace(4)* {{[^,]*}} addrspacecast (%struct.MyType addrspace(1)* @glob to %struct.MyType addrspace(4)*), i32 1) // CHECK-LABEL: define{{.*}} spir_kernel void @fooGlobal() kernel void fooGlobal() { - // CHECK: call spir_func noundef i32 @_ZNU3AS46MyType3barEv(%struct.MyType addrspace(4)* {{[^,]*}} addrspacecast (%struct.MyType addrspace(1)* @glob to %struct.MyType addrspace(4)*)) + // CHECK: call spir_func i32 @_ZNU3AS46MyType3barEv(%struct.MyType addrspace(4)* {{[^,]*}} addrspacecast (%struct.MyType addrspace(1)* @glob to %struct.MyType addrspace(4)*)) glob.bar(); - // CHECK: call spir_func noundef i32 @_ZNU3AS26MyType3barEv(%struct.MyType addrspace(2)* {{[^,]*}} @const1) + // CHECK: call spir_func i32 @_ZNU3AS26MyType3barEv(%struct.MyType addrspace(2)* {{[^,]*}} @const1) const1.bar(); // CHECK: call spir_func void @_ZNU3AS26MyTypeD1Ev(%struct.MyType addrspace(2)* {{[^,]*}} @const1) const1.~MyType(); @@ -41,19 +41,19 @@ kernel void fooGlobal() { kernel void fooLocal() { // CHECK: [[VAR:%.*]] = alloca %struct.MyType // CHECK: [[REG:%.*]] ={{.*}} addrspacecast %struct.MyType* [[VAR]] to %struct.MyType addrspace(4)* - // CHECK: call spir_func void @_ZNU3AS46MyTypeC1Ei(%struct.MyType addrspace(4)* {{[^,]*}} [[REG]], i32 noundef 3) + // CHECK: call spir_func void @_ZNU3AS46MyTypeC1Ei(%struct.MyType addrspace(4)* {{[^,]*}} [[REG]], i32 3) MyType myLocal(3); // CHECK: [[REG:%.*]] ={{.*}} addrspacecast %struct.MyType* [[VAR]] to %struct.MyType addrspace(4)* - // CHECK: call spir_func noundef i32 @_ZNU3AS46MyType3barEv(%struct.MyType addrspace(4)* {{[^,]*}} [[REG]]) + // CHECK: call spir_func i32 @_ZNU3AS46MyType3barEv(%struct.MyType addrspace(4)* {{[^,]*}} [[REG]]) myLocal.bar(); // CHECK: [[REG:%.*]] ={{.*}} addrspacecast %struct.MyType* [[VAR]] to %struct.MyType addrspace(4)* // CHECK: call spir_func void @_ZNU3AS46MyTypeD1Ev(%struct.MyType addrspace(4)* {{[^,]*}} [[REG]]) } // Ensure all members are defined for all the required address spaces. -// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func void @_ZNU3AS26MyTypeC1Ei(%struct.MyType addrspace(2)* {{[^,]*}} %this, i32 noundef %i) -// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func void @_ZNU3AS46MyTypeC1Ei(%struct.MyType addrspace(4)* {{[^,]*}} %this, i32 noundef %i) +// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func void @_ZNU3AS26MyTypeC1Ei(%struct.MyType addrspace(2)* {{[^,]*}} %this, i32 %i) +// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func void @_ZNU3AS46MyTypeC1Ei(%struct.MyType addrspace(4)* {{[^,]*}} %this, i32 %i) // CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func void @_ZNU3AS26MyTypeD1Ev(%struct.MyType addrspace(2)* {{[^,]*}} %this) // CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func void @_ZNU3AS46MyTypeD1Ev(%struct.MyType addrspace(4)* {{[^,]*}} %this) -// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func noundef i32 @_ZNU3AS26MyType3barEv(%struct.MyType addrspace(2)* {{[^,]*}} %this) -// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func noundef i32 @_ZNU3AS46MyType3barEv(%struct.MyType addrspace(4)* {{[^,]*}} %this) +// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func i32 @_ZNU3AS26MyType3barEv(%struct.MyType addrspace(2)* {{[^,]*}} %this) +// CHECK-DEFINITIONS-DAG: define linkonce_odr spir_func i32 @_ZNU3AS46MyType3barEv(%struct.MyType addrspace(4)* {{[^,]*}} %this) diff --git a/clang/test/CodeGenOpenCLCXX/template-address-spaces.clcpp b/clang/test/CodeGenOpenCLCXX/template-address-spaces.clcpp index 9cc3c39afc40734d64293095f0afaa3e00d8a53c..d3814204ed99ce73274f9bec785551937caa49d3 100644 --- a/clang/test/CodeGenOpenCLCXX/template-address-spaces.clcpp +++ b/clang/test/CodeGenOpenCLCXX/template-address-spaces.clcpp @@ -14,11 +14,11 @@ T S::foo() { return a;} // CHECK: %struct.S.1 = type { i32 addrspace(1)* } // CHECK: [[A1:%[.a-z0-9]+]] = addrspacecast %struct.S* %{{[a-z0-9]+}} to %struct.S addrspace(4)* -// CHECK: %call = call spir_func noundef i32 @_ZNU3AS41SIiE3fooEv(%struct.S addrspace(4)* {{[^,]*}} [[A1]]) #1 +// CHECK: %call = call spir_func i32 @_ZNU3AS41SIiE3fooEv(%struct.S addrspace(4)* {{[^,]*}} [[A1]]) #1 // CHECK: [[A2:%[.a-z0-9]+]] = addrspacecast %struct.S.0* %{{[a-z0-9]+}} to %struct.S.0 addrspace(4)* -// CHECK: %call1 = call spir_func noundef i32 addrspace(4)* @_ZNU3AS41SIPU3AS4iE3fooEv(%struct.S.0 addrspace(4)* {{[^,]*}} [[A2]]) #1 +// CHECK: %call1 = call spir_func i32 addrspace(4)* @_ZNU3AS41SIPU3AS4iE3fooEv(%struct.S.0 addrspace(4)* {{[^,]*}} [[A2]]) #1 // CHECK: [[A3:%[.a-z0-9]+]] = addrspacecast %struct.S.1* %{{[a-z0-9]+}} to %struct.S.1 addrspace(4)* -// CHECK: %call2 = call spir_func noundef i32 addrspace(1)* @_ZNU3AS41SIPU3AS1iE3fooEv(%struct.S.1 addrspace(4)* {{[^,]*}} [[A3]]) #1 +// CHECK: %call2 = call spir_func i32 addrspace(1)* @_ZNU3AS41SIPU3AS1iE3fooEv(%struct.S.1 addrspace(4)* {{[^,]*}} [[A3]]) #1 void bar(){ S sint; diff --git a/clang/test/CodeGenSYCL/address-space-conversions.cpp b/clang/test/CodeGenSYCL/address-space-conversions.cpp index e2fb755a29a6cbba766cafeb7de058f011d07aa1..3732c4a1b889b1e22ef2f967f9d2814741884536 100644 --- a/clang/test/CodeGenSYCL/address-space-conversions.cpp +++ b/clang/test/CodeGenSYCL/address-space-conversions.cpp @@ -1,16 +1,16 @@ // RUN: %clang_cc1 -triple spir64 -fsycl-is-device -disable-llvm-passes -emit-llvm %s -o - | FileCheck %s void bar(int &Data) {} -// CHECK-DAG: define{{.*}} spir_func void @[[RAW_REF:[a-zA-Z0-9_]+]](i32 addrspace(4)* noundef align 4 dereferenceable(4) % +// CHECK-DAG: define{{.*}} spir_func void @[[RAW_REF:[a-zA-Z0-9_]+]](i32 addrspace(4)* align 4 dereferenceable(4) % void bar2(int &Data) {} -// CHECK-DAG: define{{.*}} spir_func void @[[RAW_REF2:[a-zA-Z0-9_]+]](i32 addrspace(4)* noundef align 4 dereferenceable(4) % +// CHECK-DAG: define{{.*}} spir_func void @[[RAW_REF2:[a-zA-Z0-9_]+]](i32 addrspace(4)* align 4 dereferenceable(4) % void bar(__attribute__((opencl_local)) int &Data) {} -// CHECK-DAG: define{{.*}} spir_func void [[LOC_REF:@[a-zA-Z0-9_]+]](i32 addrspace(3)* noundef align 4 dereferenceable(4) % +// CHECK-DAG: define{{.*}} spir_func void [[LOC_REF:@[a-zA-Z0-9_]+]](i32 addrspace(3)* align 4 dereferenceable(4) % void foo(int *Data) {} -// CHECK-DAG: define{{.*}} spir_func void @[[RAW_PTR:[a-zA-Z0-9_]+]](i32 addrspace(4)* noundef % +// CHECK-DAG: define{{.*}} spir_func void @[[RAW_PTR:[a-zA-Z0-9_]+]](i32 addrspace(4)* % void foo2(int *Data) {} -// CHECK-DAG: define{{.*}} spir_func void @[[RAW_PTR2:[a-zA-Z0-9_]+]](i32 addrspace(4)* noundef % +// CHECK-DAG: define{{.*}} spir_func void @[[RAW_PTR2:[a-zA-Z0-9_]+]](i32 addrspace(4)* % void foo(__attribute__((opencl_local)) int *Data) {} -// CHECK-DAG: define{{.*}} spir_func void [[LOC_PTR:@[a-zA-Z0-9_]+]](i32 addrspace(3)* noundef % +// CHECK-DAG: define{{.*}} spir_func void [[LOC_PTR:@[a-zA-Z0-9_]+]](i32 addrspace(3)* % template void tmpl(T t) {} @@ -74,65 +74,65 @@ void usages() { bar(*GLOB); // CHECK-DAG: [[GLOB_LOAD:%[a-zA-Z0-9]+]] = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* [[GLOB]].ascast // CHECK-DAG: [[GLOB_CAST:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(1)* [[GLOB_LOAD]] to i32 addrspace(4)* - // CHECK-DAG: call spir_func void @[[RAW_REF]](i32 addrspace(4)* noundef align 4 dereferenceable(4) [[GLOB_CAST]]) + // CHECK-DAG: call spir_func void @[[RAW_REF]](i32 addrspace(4)* align 4 dereferenceable(4) [[GLOB_CAST]]) bar2(*GLOB); // CHECK-DAG: [[GLOB_LOAD2:%[a-zA-Z0-9]+]] = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* [[GLOB]].ascast // CHECK-DAG: [[GLOB_CAST2:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(1)* [[GLOB_LOAD2]] to i32 addrspace(4)* - // CHECK-DAG: call spir_func void @[[RAW_REF2]](i32 addrspace(4)* noundef align 4 dereferenceable(4) [[GLOB_CAST2]]) + // CHECK-DAG: call spir_func void @[[RAW_REF2]](i32 addrspace(4)* align 4 dereferenceable(4) [[GLOB_CAST2]]) bar(*LOC); // CHECK-DAG: [[LOC_LOAD:%[a-zA-Z0-9]+]] = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(4)* [[LOC]].ascast - // CHECK-DAG: call spir_func void [[LOC_REF]](i32 addrspace(3)* noundef align 4 dereferenceable(4) [[LOC_LOAD]]) + // CHECK-DAG: call spir_func void [[LOC_REF]](i32 addrspace(3)* align 4 dereferenceable(4) [[LOC_LOAD]]) bar2(*LOC); // CHECK-DAG: [[LOC_LOAD2:%[a-zA-Z0-9]+]] = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(4)* [[LOC]].ascast // CHECK-DAG: [[LOC_CAST2:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(3)* [[LOC_LOAD2]] to i32 addrspace(4)* - // CHECK-DAG: call spir_func void @[[RAW_REF2]](i32 addrspace(4)* noundef align 4 dereferenceable(4) [[LOC_CAST2]]) + // CHECK-DAG: call spir_func void @[[RAW_REF2]](i32 addrspace(4)* align 4 dereferenceable(4) [[LOC_CAST2]]) bar(*NoAS); // CHECK-DAG: [[NoAS_LOAD:%[a-zA-Z0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* [[NoAS]].ascast - // CHECK-DAG: call spir_func void @[[RAW_REF]](i32 addrspace(4)* noundef align 4 dereferenceable(4) [[NoAS_LOAD]]) + // CHECK-DAG: call spir_func void @[[RAW_REF]](i32 addrspace(4)* align 4 dereferenceable(4) [[NoAS_LOAD]]) bar2(*NoAS); // CHECK-DAG: [[NoAS_LOAD2:%[a-zA-Z0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* [[NoAS]].ascast - // CHECK-DAG: call spir_func void @[[RAW_REF2]](i32 addrspace(4)* noundef align 4 dereferenceable(4) [[NoAS_LOAD2]]) + // CHECK-DAG: call spir_func void @[[RAW_REF2]](i32 addrspace(4)* align 4 dereferenceable(4) [[NoAS_LOAD2]]) foo(GLOB); // CHECK-DAG: [[GLOB_LOAD3:%[a-zA-Z0-9]+]] = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* [[GLOB]].ascast // CHECK-DAG: [[GLOB_CAST3:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(1)* [[GLOB_LOAD3]] to i32 addrspace(4)* - // CHECK-DAG: call spir_func void @[[RAW_PTR]](i32 addrspace(4)* noundef [[GLOB_CAST3]]) + // CHECK-DAG: call spir_func void @[[RAW_PTR]](i32 addrspace(4)* [[GLOB_CAST3]]) foo2(GLOB); // CHECK-DAG: [[GLOB_LOAD4:%[a-zA-Z0-9]+]] = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* [[GLOB]].ascast // CHECK-DAG: [[GLOB_CAST4:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(1)* [[GLOB_LOAD4]] to i32 addrspace(4)* - // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* noundef [[GLOB_CAST4]]) + // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* [[GLOB_CAST4]]) foo(LOC); // CHECK-DAG: [[LOC_LOAD3:%[a-zA-Z0-9]+]] = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(4)* [[LOC]].ascast - // CHECK-DAG: call spir_func void [[LOC_PTR]](i32 addrspace(3)* noundef [[LOC_LOAD3]]) + // CHECK-DAG: call spir_func void [[LOC_PTR]](i32 addrspace(3)* [[LOC_LOAD3]]) foo2(LOC); // CHECK-DAG: [[LOC_LOAD4:%[a-zA-Z0-9]+]] = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(4)* [[LOC]].ascast // CHECK-DAG: [[LOC_CAST4:%[a-zA-Z0-9]+]] = addrspacecast i32 addrspace(3)* [[LOC_LOAD4]] to i32 addrspace(4)* - // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* noundef [[LOC_CAST4]]) + // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* [[LOC_CAST4]]) foo(NoAS); // CHECK-DAG: [[NoAS_LOAD3:%[a-zA-Z0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* [[NoAS]].ascast - // CHECK-DAG: call spir_func void @[[RAW_PTR]](i32 addrspace(4)* noundef [[NoAS_LOAD3]]) + // CHECK-DAG: call spir_func void @[[RAW_PTR]](i32 addrspace(4)* [[NoAS_LOAD3]]) foo2(NoAS); // CHECK-DAG: [[NoAS_LOAD4:%[a-zA-Z0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* [[NoAS]].ascast - // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* noundef [[NoAS_LOAD4]]) + // CHECK-DAG: call spir_func void @[[RAW_PTR2]](i32 addrspace(4)* [[NoAS_LOAD4]]) // Ensure that we still get 3 different template instantiations. tmpl(GLOB); // CHECK-DAG: [[GLOB_LOAD4:%[a-zA-Z0-9]+]] = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* [[GLOB]].ascast - // CHECK-DAG: call spir_func void @_Z4tmplIPU3AS1iEvT_(i32 addrspace(1)* noundef [[GLOB_LOAD4]]) + // CHECK-DAG: call spir_func void @_Z4tmplIPU3AS1iEvT_(i32 addrspace(1)* [[GLOB_LOAD4]]) tmpl(LOC); // CHECK-DAG: [[LOC_LOAD5:%[a-zA-Z0-9]+]] = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(4)* [[LOC]].ascast - // CHECK-DAG: call spir_func void @_Z4tmplIPU3AS3iEvT_(i32 addrspace(3)* noundef [[LOC_LOAD5]]) + // CHECK-DAG: call spir_func void @_Z4tmplIPU3AS3iEvT_(i32 addrspace(3)* [[LOC_LOAD5]]) tmpl(PRIV); // CHECK-DAG: [[PRIV_LOAD5:%[a-zA-Z0-9]+]] = load i32*, i32* addrspace(4)* [[PRIV]].ascast - // CHECK-DAG: call spir_func void @_Z4tmplIPU3AS0iEvT_(i32* noundef [[PRIV_LOAD5]]) + // CHECK-DAG: call spir_func void @_Z4tmplIPU3AS0iEvT_(i32* [[PRIV_LOAD5]]) tmpl(NoAS); // CHECK-DAG: [[NoAS_LOAD5:%[a-zA-Z0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* [[NoAS]].ascast - // CHECK-DAG: call spir_func void @_Z4tmplIPiEvT_(i32 addrspace(4)* noundef [[NoAS_LOAD5]]) + // CHECK-DAG: call spir_func void @_Z4tmplIPiEvT_(i32 addrspace(4)* [[NoAS_LOAD5]]) } -// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPU3AS1iEvT_(i32 addrspace(1)* noundef % -// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPU3AS3iEvT_(i32 addrspace(3)* noundef % -// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPU3AS0iEvT_(i32* noundef % -// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPiEvT_(i32 addrspace(4)* noundef % +// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPU3AS1iEvT_(i32 addrspace(1)* % +// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPU3AS3iEvT_(i32 addrspace(3)* % +// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPU3AS0iEvT_(i32* % +// CHECK-DAG: define linkonce_odr spir_func void @_Z4tmplIPiEvT_(i32 addrspace(4)* % diff --git a/clang/test/CodeGenSYCL/address-space-mangling.cpp b/clang/test/CodeGenSYCL/address-space-mangling.cpp index 37df32493e3491eb15a213436bf0a9491f2c3902..76feec552fa2b7c46e4658bbd51e9196ebd97b84 100644 --- a/clang/test/CodeGenSYCL/address-space-mangling.cpp +++ b/clang/test/CodeGenSYCL/address-space-mangling.cpp @@ -8,15 +8,15 @@ void foo(__attribute__((opencl_local)) int *); void foo(__attribute__((opencl_private)) int *); void foo(int *); -// SPIR: declare spir_func void @_Z3fooPU3AS1i(i32 addrspace(1)* noundef) #1 -// SPIR: declare spir_func void @_Z3fooPU3AS3i(i32 addrspace(3)* noundef) #1 -// SPIR: declare spir_func void @_Z3fooPU3AS0i(i32* noundef) #1 -// SPIR: declare spir_func void @_Z3fooPi(i32 addrspace(4)* noundef) #1 +// SPIR: declare spir_func void @_Z3fooPU3AS1i(i32 addrspace(1)*) #1 +// SPIR: declare spir_func void @_Z3fooPU3AS3i(i32 addrspace(3)*) #1 +// SPIR: declare spir_func void @_Z3fooPU3AS0i(i32*) #1 +// SPIR: declare spir_func void @_Z3fooPi(i32 addrspace(4)*) #1 -// X86: declare void @_Z3fooPU8SYglobali(i32* noundef) #1 -// X86: declare void @_Z3fooPU7SYlocali(i32* noundef) #1 -// X86: declare void @_Z3fooPU9SYprivatei(i32* noundef) #1 -// X86: declare void @_Z3fooPi(i32* noundef) #1 +// X86: declare void @_Z3fooPU8SYglobali(i32*) #1 +// X86: declare void @_Z3fooPU7SYlocali(i32*) #1 +// X86: declare void @_Z3fooPU9SYprivatei(i32*) #1 +// X86: declare void @_Z3fooPi(i32*) #1 void test() { __attribute__((opencl_global)) int *glob; diff --git a/clang/test/CodeGenSYCL/unique_stable_name.cpp b/clang/test/CodeGenSYCL/unique_stable_name.cpp index be3e25a97a804a6b337ea4e981ed82de25a236d9..462541a29fc2a1609e6e4ad036aa175038a1060a 100644 --- a/clang/test/CodeGenSYCL/unique_stable_name.cpp +++ b/clang/test/CodeGenSYCL/unique_stable_name.cpp @@ -67,48 +67,48 @@ template int main() { kernel_single_task(func); - // CHECK: call spir_func void @_Z18kernel_single_taskIZ4mainE7kernel2PFPKcvEEvT0_(i8 addrspace(4)* ()* noundef @_Z4funcI4DerpEDTu33__builtin_sycl_unique_stable_nameDtsrT_3strEEEv) + // CHECK: call spir_func void @_Z18kernel_single_taskIZ4mainE7kernel2PFPKcvEEvT0_(i8 addrspace(4)* ()* @_Z4funcI4DerpEDTu33__builtin_sycl_unique_stable_nameDtsrT_3strEEEv) auto l1 = []() { return 1; }; auto l2 = [](decltype(l1) *l = nullptr) { return 2; }; kernel_single_task(l2); puts(__builtin_sycl_unique_stable_name(decltype(l2))); // CHECK: call spir_func void @_Z18kernel_single_taskIZ4mainE7kernel3Z4mainEUlPZ4mainEUlvE_E_EvT0_ - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[LAMBDA_K3_SIZE]], [[LAMBDA_K3_SIZE]]* @[[LAMBDA_KERNEL3]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[LAMBDA_K3_SIZE]], [[LAMBDA_K3_SIZE]]* @[[LAMBDA_KERNEL3]], i32 0, i32 0) to i8 addrspace(4)*)) constexpr const char str[] = "lalala"; static_assert(__builtin_strcmp(__builtin_sycl_unique_stable_name(decltype(str)), "_ZTSA7_Kc\0") == 0, "unexpected mangling"); int i = 0; puts(__builtin_sycl_unique_stable_name(decltype(i++))); - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[INT_SIZE]], [[INT_SIZE]]* @[[INT1]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[INT_SIZE]], [[INT_SIZE]]* @[[INT1]], i32 0, i32 0) to i8 addrspace(4)*)) // FIXME: Ensure that j is incremented because VLAs are terrible. int j = 55; puts(__builtin_sycl_unique_stable_name(int[++j])); - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[STRING_SIZE]], [[STRING_SIZE]]* @[[STRING]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[STRING_SIZE]], [[STRING_SIZE]]* @[[STRING]], i32 0, i32 0) to i8 addrspace(4)*)) // CHECK: define internal spir_func void @_Z18kernel_single_taskIZ4mainE7kernel2PFPKcvEEvT0_ - // CHECK: declare spir_func noundef i8 addrspace(4)* @_Z4funcI4DerpEDTu33__builtin_sycl_unique_stable_nameDtsrT_3strEEEv + // CHECK: declare spir_func i8 addrspace(4)* @_Z4funcI4DerpEDTu33__builtin_sycl_unique_stable_nameDtsrT_3strEEEv // CHECK: define internal spir_func void @_Z18kernel_single_taskIZ4mainE7kernel3Z4mainEUlPZ4mainEUlvE_E_EvT0_ // CHECK: define internal spir_func void @_Z18kernel_single_taskIZ4mainE6kernelZ4mainEUlvE0_EvT0_ kernel_single_task( []() { puts(__builtin_sycl_unique_stable_name(int)); - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[INT_SIZE]], [[INT_SIZE]]* @[[INT2]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[INT_SIZE]], [[INT_SIZE]]* @[[INT2]], i32 0, i32 0) to i8 addrspace(4)*)) auto x = []() {}; puts(__builtin_sycl_unique_stable_name(decltype(x))); - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[LAMBDA_X_SIZE]], [[LAMBDA_X_SIZE]]* @[[LAMBDA_X]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[LAMBDA_X_SIZE]], [[LAMBDA_X_SIZE]]* @[[LAMBDA_X]], i32 0, i32 0) to i8 addrspace(4)*)) DEF_IN_MACRO(); - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[MACRO_SIZE]], [[MACRO_SIZE]]* @[[MACRO_X]], i32 0, i32 0) to i8 addrspace(4)*)) - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[MACRO_SIZE]], [[MACRO_SIZE]]* @[[MACRO_Y]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[MACRO_SIZE]], [[MACRO_SIZE]]* @[[MACRO_X]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[MACRO_SIZE]], [[MACRO_SIZE]]* @[[MACRO_Y]], i32 0, i32 0) to i8 addrspace(4)*)) MACRO_CALLS_MACRO(); - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[MACRO_MACRO_SIZE]], [[MACRO_MACRO_SIZE]]* @[[MACRO_MACRO_X]], i32 0, i32 0) to i8 addrspace(4)*)) - // CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[MACRO_MACRO_SIZE]], [[MACRO_MACRO_SIZE]]* @[[MACRO_MACRO_Y]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[MACRO_MACRO_SIZE]], [[MACRO_MACRO_SIZE]]* @[[MACRO_MACRO_X]], i32 0, i32 0) to i8 addrspace(4)*)) + // CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[MACRO_MACRO_SIZE]], [[MACRO_MACRO_SIZE]]* @[[MACRO_MACRO_Y]], i32 0, i32 0) to i8 addrspace(4)*)) template_param(); // CHECK: call spir_func void @_Z14template_paramIiEvv @@ -123,7 +123,7 @@ int main() { // CHECK: call spir_func void @_Z28lambda_in_dependent_functionIZZ4mainENKUlvE0_clEvEUlvE_Evv lambda_no_dep(3, 5.5); - // CHECK: call spir_func void @_Z13lambda_no_depIidEvT_T0_(i32 noundef 3, double noundef 5.500000e+00) + // CHECK: call spir_func void @_Z13lambda_no_depIidEvT_T0_(i32 3, double 5.500000e+00) int a = 5; double b = 10.7; @@ -138,22 +138,22 @@ int main() { } // CHECK: define linkonce_odr spir_func void @_Z14template_paramIiEvv -// CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[INT_SIZE]], [[INT_SIZE]]* @[[INT3]], i32 0, i32 0) to i8 addrspace(4)*)) +// CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[INT_SIZE]], [[INT_SIZE]]* @[[INT3]], i32 0, i32 0) to i8 addrspace(4)*)) // CHECK: define internal spir_func void @_Z14template_paramIZZ4mainENKUlvE0_clEvEUlvE_Evv -// CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[LAMBDA_SIZE]], [[LAMBDA_SIZE]]* @[[LAMBDA]], i32 0, i32 0) to i8 addrspace(4)*)) +// CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[LAMBDA_SIZE]], [[LAMBDA_SIZE]]* @[[LAMBDA]], i32 0, i32 0) to i8 addrspace(4)*)) // CHECK: define linkonce_odr spir_func void @_Z28lambda_in_dependent_functionIiEvv -// CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[DEP_INT_SIZE]], [[DEP_INT_SIZE]]* @[[LAMBDA_IN_DEP_INT]], i32 0, i32 0) to i8 addrspace(4)*)) +// CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[DEP_INT_SIZE]], [[DEP_INT_SIZE]]* @[[LAMBDA_IN_DEP_INT]], i32 0, i32 0) to i8 addrspace(4)*)) // CHECK: define internal spir_func void @_Z28lambda_in_dependent_functionIZZ4mainENKUlvE0_clEvEUlvE_Evv -// CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[DEP_LAMBDA_SIZE]], [[DEP_LAMBDA_SIZE]]* @[[LAMBDA_IN_DEP_X]], i32 0, i32 0) to i8 addrspace(4)*)) +// CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[DEP_LAMBDA_SIZE]], [[DEP_LAMBDA_SIZE]]* @[[LAMBDA_IN_DEP_X]], i32 0, i32 0) to i8 addrspace(4)*)) -// CHECK: define linkonce_odr spir_func void @_Z13lambda_no_depIidEvT_T0_(i32 noundef %a, double noundef %b) -// CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[NO_DEP_LAMBDA_SIZE]], [[NO_DEP_LAMBDA_SIZE]]* @[[LAMBDA_NO_DEP]], i32 0, i32 0) to i8 addrspace(4)*)) +// CHECK: define linkonce_odr spir_func void @_Z13lambda_no_depIidEvT_T0_(i32 %a, double %b) +// CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[NO_DEP_LAMBDA_SIZE]], [[NO_DEP_LAMBDA_SIZE]]* @[[LAMBDA_NO_DEP]], i32 0, i32 0) to i8 addrspace(4)*)) // CHECK: define internal spir_func void @_Z14lambda_two_depIZZ4mainENKUlvE0_clEvEUliE_ZZ4mainENKS0_clEvEUldE_Evv -// CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[DEP_LAMBDA1_SIZE]], [[DEP_LAMBDA1_SIZE]]* @[[LAMBDA_TWO_DEP]], i32 0, i32 0) to i8 addrspace(4)*)) +// CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[DEP_LAMBDA1_SIZE]], [[DEP_LAMBDA1_SIZE]]* @[[LAMBDA_TWO_DEP]], i32 0, i32 0) to i8 addrspace(4)*)) // CHECK: define internal spir_func void @_Z14lambda_two_depIZZ4mainENKUlvE0_clEvEUldE_ZZ4mainENKS0_clEvEUliE_Evv -// CHECK: call spir_func void @puts(i8 addrspace(4)* noundef addrspacecast (i8* getelementptr inbounds ([[DEP_LAMBDA2_SIZE]], [[DEP_LAMBDA2_SIZE]]* @[[LAMBDA_TWO_DEP2]], i32 0, i32 0) to i8 addrspace(4)*)) +// CHECK: call spir_func void @puts(i8 addrspace(4)* addrspacecast (i8* getelementptr inbounds ([[DEP_LAMBDA2_SIZE]], [[DEP_LAMBDA2_SIZE]]* @[[LAMBDA_TWO_DEP2]], i32 0, i32 0) to i8 addrspace(4)*)) diff --git a/clang/test/Driver/asan.c b/clang/test/Driver/asan.c index be6a4fbe0a41a6d259f9d4ebf7771ffb23344a50..3df7ec6013bc988626771cfb8de5f55a5b055f04 100644 --- a/clang/test/Driver/asan.c +++ b/clang/test/Driver/asan.c @@ -1,74 +1,39 @@ -// RUN: %clang -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-ASAN -// RUN: %clang -O1 -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-ASAN -// RUN: %clang -O2 -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-ASAN -// RUN: %clang -O3 -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-ASAN -// RUN: %clang -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-ASAN -// RUN: %clang -O2 -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-ASAN -// RUN: %clang -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-ASAN -// RUN: %clang -O2 -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-ASAN +// RUN: %clang -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-ASAN +// RUN: %clang -O1 -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-ASAN +// RUN: %clang -O2 -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-ASAN +// RUN: %clang -O3 -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-ASAN +// RUN: %clang -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-ASAN +// RUN: %clang -O2 -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-ASAN +// RUN: %clang -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-ASAN +// RUN: %clang -O2 -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-ASAN + +// RUN: %clang -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KASAN +// RUN: %clang -O1 -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KASAN +// RUN: %clang -O2 -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KASAN +// RUN: %clang -O3 -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KASAN +// RUN: %clang -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-KASAN +// RUN: %clang -O2 -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-KASAN +// RUN: %clang -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-KASAN +// RUN: %clang -O2 -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-KASAN + +// RUN: %clang -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-HWASAN +// RUN: %clang -O1 -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-HWASAN +// RUN: %clang -O2 -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-HWASAN +// RUN: %clang -O3 -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-HWASAN +// RUN: %clang -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-HWASAN +// RUN: %clang -O2 -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-HWASAN +// RUN: %clang -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-HWASAN +// RUN: %clang -O2 -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-HWASAN + +// RUN: %clang -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KHWASAN +// RUN: %clang -O1 -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KHWASAN +// RUN: %clang -O2 -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KHWASAN +// RUN: %clang -O3 -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KHWASAN +// RUN: %clang -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-KHWASAN +// RUN: %clang -O2 -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-KHWASAN +// RUN: %clang -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-KHWASAN +// RUN: %clang -O2 -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-KHWASAN -// RUN: %clang -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-ASAN -// RUN: %clang -O1 -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-ASAN -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-ASAN -// RUN: %clang -O3 -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-ASAN -// RUN: %clang -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-ASAN -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-ASAN -// RUN: %clang -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-ASAN -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=address %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-ASAN - -// RUN: %clang -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KASAN -// RUN: %clang -O1 -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KASAN -// RUN: %clang -O2 -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KASAN -// RUN: %clang -O3 -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KASAN -// RUN: %clang -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-KASAN -// RUN: %clang -O2 -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-KASAN -// RUN: %clang -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-KASAN -// RUN: %clang -O2 -fexperimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-KASAN - -// RUN: %clang -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KASAN -// RUN: %clang -O1 -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KASAN -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KASAN -// RUN: %clang -O3 -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KASAN -// RUN: %clang -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-KASAN -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-KASAN -// RUN: %clang -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-KASAN -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target i386-unknown-linux -fsanitize=kernel-address %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-KASAN - -// RUN: %clang -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-HWASAN -// RUN: %clang -O1 -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-HWASAN -// RUN: %clang -O2 -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-HWASAN -// RUN: %clang -O3 -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-HWASAN -// RUN: %clang -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-HWASAN -// RUN: %clang -O2 -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-HWASAN -// RUN: %clang -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-HWASAN -// RUN: %clang -O2 -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-HWASAN - -// RUN: %clang -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-HWASAN -// RUN: %clang -O1 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-HWASAN -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-HWASAN -// RUN: %clang -O3 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-HWASAN -// RUN: %clang -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-HWASAN -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-HWASAN -// RUN: %clang -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-HWASAN -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=hwaddress %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-HWASAN - -// RUN: %clang -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KHWASAN -// RUN: %clang -O1 -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KHWASAN -// RUN: %clang -O2 -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KHWASAN -// RUN: %clang -O3 -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KHWASAN -// RUN: %clang -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-KHWASAN -// RUN: %clang -O2 -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-KHWASAN -// RUN: %clang -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-KHWASAN -// RUN: %clang -O2 -fexperimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-KHWASAN - -// RUN: %clang -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KHWASAN -// RUN: %clang -O1 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KHWASAN -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KHWASAN -// RUN: %clang -O3 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -o - | FileCheck %s --check-prefix=CHECK-KHWASAN -// RUN: %clang -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-KHWASAN -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefix=CHECK-KHWASAN -// RUN: %clang -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-KHWASAN -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -fsanitize=kernel-hwaddress %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefix=CHECK-KHWASAN // Verify that -fsanitize={address,hwaddres,kernel-address,kernel-hwaddress} invokes ASan, HWAsan, KASan or KHWASan instrumentation. int foo(int *a) { return *a; } diff --git a/clang/test/Driver/dfsan.c b/clang/test/Driver/dfsan.c index 7871863c8b3da3969612432c0a914123c1cce82b..fa565235c484833ab84e7b47f0ba6cf5b32b375a 100644 --- a/clang/test/Driver/dfsan.c +++ b/clang/test/Driver/dfsan.c @@ -1,20 +1,11 @@ -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O1 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O2 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O3 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -O2 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -flto -o - | FileCheck %s -// RUN: %clang -O2 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -flto -o - | FileCheck %s - -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O1 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O3 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -flto -o - | FileCheck %s -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -flto -o - | FileCheck %s +// RUN: %clang -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -O1 -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -O2 -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -O3 -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -flto=thin -o - | FileCheck %s +// RUN: %clang -O2 -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -flto=thin -o - | FileCheck %s +// RUN: %clang -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -flto -o - | FileCheck %s +// RUN: %clang -O2 -target x86_64-unknown-linux -fsanitize=dataflow %s -S -emit-llvm -flto -o - | FileCheck %s // Verify that -fsanitize=dataflow invokes DataFlowSanitizerPass instrumentation. diff --git a/clang/test/Driver/memtag.c b/clang/test/Driver/memtag.c index 0de5aaa35fb72bca096687af4b90f3e78bf6a108..d244444066925c2794326d0e8ac3f8765ebba291 100644 --- a/clang/test/Driver/memtag.c +++ b/clang/test/Driver/memtag.c @@ -1,16 +1,9 @@ // REQUIRES: aarch64-registered-target -// Old pass manager. -// RUN: %clang -fno-experimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print=1 %s -S -o - 2>&1 | FileCheck %s --check-prefix=CHECK-NO-SAFETY -// RUN: %clang -O1 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print=1 %s -S -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SAFETY -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print=1 %s -S -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SAFETY -// RUN: %clang -O3 -fno-experimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print=1 %s -S -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SAFETY - -// New pass manager. -// RUN: %clang -fexperimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print=1 %s -S -o - 2>&1 | FileCheck %s --check-prefix=CHECK-NO-SAFETY -// RUN: %clang -O1 -fexperimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print=1 %s -S -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SAFETY -// RUN: %clang -O2 -fexperimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print=1 %s -S -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SAFETY -// RUN: %clang -O3 -fexperimental-new-pass-manager -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print=1 %s -S -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SAFETY +// RUN: %clang -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print=1 %s -S -o - 2>&1 | FileCheck %s --check-prefix=CHECK-NO-SAFETY +// RUN: %clang -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print=1 %s -S -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SAFETY +// RUN: %clang -O2 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print=1 %s -S -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SAFETY +// RUN: %clang -O3 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print=1 %s -S -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SAFETY int z; __attribute__((noinline)) void use(int *p) { *p = z; } diff --git a/clang/test/Driver/memtag_lto.c b/clang/test/Driver/memtag_lto.c index 3421e4028db1a8aeb891b021c311a180bfe75876..2d3445c359fa5e651a001725157124309cb4271a 100644 --- a/clang/test/Driver/memtag_lto.c +++ b/clang/test/Driver/memtag_lto.c @@ -5,23 +5,11 @@ // RUN: rm -f %t* // -O1, no tagging -// RUN: %clang -fno-experimental-new-pass-manager -O1 -target aarch64-unknown-linux -mllvm -stack-safety-print %s -S -o - 2>&1 | FileCheck %s -// RUN: %clang -fexperimental-new-pass-manager -O1 -target aarch64-unknown-linux -mllvm -stack-safety-print %s -S -o - 2>&1 | FileCheck %s +// RUN: %clang -O1 -target aarch64-unknown-linux -mllvm -stack-safety-print %s -S -o - 2>&1 | FileCheck %s // Full LTO -// RUN: %clang -fno-experimental-new-pass-manager -O1 -target aarch64-unknown-linux -c %s -flto=full -o %t.lto1.bc -// RUN: %clang -fno-experimental-new-pass-manager -O1 -target aarch64-unknown-linux -c -DBUILD2 %s -flto=full -o %t.lto2.bc -// RUN: llvm-lto2 run -o %t.lto %t.lto1.bc %t.lto2.bc -save-temps -stack-safety-print -thinlto-threads 1 -O1 \ -// RUN: -r %t.lto1.bc,fn,plx \ -// RUN: -r %t.lto1.bc,use,lx \ -// RUN: -r %t.lto1.bc,use_local,plx \ -// RUN: -r %t.lto1.bc,w, \ -// RUN: -r %t.lto2.bc,use,plx \ -// RUN: -r %t.lto2.bc,z, 2>&1 | FileCheck %s --allow-empty - -// Full LTO, new PM -// RUN: %clang -fexperimental-new-pass-manager -O1 -target aarch64-unknown-linux -c %s -flto=full -o %t.ltonewpm1.bc -// RUN: %clang -fexperimental-new-pass-manager -O1 -target aarch64-unknown-linux -c -DBUILD2 %s -flto=full -o %t.ltonewpm2.bc +// RUN: %clang -O1 -target aarch64-unknown-linux -c %s -flto=full -o %t.ltonewpm1.bc +// RUN: %clang -O1 -target aarch64-unknown-linux -c -DBUILD2 %s -flto=full -o %t.ltonewpm2.bc // RUN: llvm-lto2 run -use-new-pm -o %t.ltonewpm %t.ltonewpm1.bc %t.ltonewpm2.bc -save-temps -stack-safety-print -thinlto-threads 1 -O1 \ // RUN: -r %t.ltonewpm1.bc,fn,plx \ // RUN: -r %t.ltonewpm1.bc,use,lx \ @@ -30,20 +18,9 @@ // RUN: -r %t.ltonewpm2.bc,use,plx \ // RUN: -r %t.ltonewpm2.bc,z, 2>&1 | FileCheck %s --allow-empty -// Thin LTO -// RUN: %clang -fno-experimental-new-pass-manager -O1 -target aarch64-unknown-linux -c %s -flto=thin -o %t.thinlto1.bc -// RUN: %clang -fno-experimental-new-pass-manager -O1 -target aarch64-unknown-linux -c -DBUILD2 %s -flto=thin -o %t.thinlto2.bc -// RUN: llvm-lto2 run -o %t.thinlto %t.thinlto1.bc %t.thinlto2.bc -save-temps -stack-safety-print -thinlto-threads 1 -O1 \ -// RUN: -r %t.thinlto1.bc,fn,plx \ -// RUN: -r %t.thinlto1.bc,use,lx \ -// RUN: -r %t.thinlto1.bc,use_local,plx \ -// RUN: -r %t.thinlto1.bc,w, \ -// RUN: -r %t.thinlto2.bc,use,plx \ -// RUN: -r %t.thinlto2.bc,z, 2>&1 | FileCheck %s --allow-empty - // Thin LTO, new PM -// RUN: %clang -fexperimental-new-pass-manager -O1 -target aarch64-unknown-linux -c %s -flto=thin -o %t.thinltonewpm1.bc -// RUN: %clang -fexperimental-new-pass-manager -O1 -target aarch64-unknown-linux -c -DBUILD2 %s -flto=thin -o %t.thinltonewpm2.bc +// RUN: %clang -O1 -target aarch64-unknown-linux -c %s -flto=thin -o %t.thinltonewpm1.bc +// RUN: %clang -O1 -target aarch64-unknown-linux -c -DBUILD2 %s -flto=thin -o %t.thinltonewpm2.bc // RUN: llvm-lto2 run -use-new-pm -o %t.thinltonewpm %t.thinltonewpm1.bc %t.thinltonewpm2.bc -save-temps -stack-safety-print -thinlto-threads 1 -O1 \ // RUN: -r %t.thinltonewpm1.bc,fn,plx \ // RUN: -r %t.thinltonewpm1.bc,use,lx \ @@ -56,27 +33,14 @@ // RUN: rm -f %t* // -O0: both are unsafe. -// RUN: %clang -fno-experimental-new-pass-manager -O0 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print %s -S -o - 2>&1 | FileCheck %s -// RUN: %clang -fexperimental-new-pass-manager -O0 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print %s -S -o - 2>&1 | FileCheck %s +// RUN: %clang -O0 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print %s -S -o - 2>&1 | FileCheck %s // No LTO: just one is safe. -// RUN: %clang -fno-experimental-new-pass-manager -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print %s -S -o /dev/null 2>&1 | FileCheck %s -check-prefixes=SSI,XUNSAFE,YSAFE -// RUN: %clang -fexperimental-new-pass-manager -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print %s -S -o /dev/null 2>&1 | FileCheck %s -check-prefixes=SSI,XUNSAFE,YSAFE +// RUN: %clang -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -mllvm -stack-safety-print %s -S -o /dev/null 2>&1 | FileCheck %s -check-prefixes=SSI,XUNSAFE,YSAFE // Full LTO: both are safe. -// RUN: %clang -fno-experimental-new-pass-manager -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -c %s -flto=full -o %t.lto1.bc -// RUN: %clang -fno-experimental-new-pass-manager -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -c -DBUILD2 %s -flto=full -o %t.lto2.bc -// RUN: llvm-lto2 run -o %t.lto %t.lto1.bc %t.lto2.bc -save-temps -stack-safety-print -thinlto-threads 1 -O1 \ -// RUN: -r %t.lto1.bc,fn,plx \ -// RUN: -r %t.lto1.bc,use,lx \ -// RUN: -r %t.lto1.bc,use_local,plx \ -// RUN: -r %t.lto1.bc,w, \ -// RUN: -r %t.lto2.bc,use,plx \ -// RUN: -r %t.lto2.bc,z, 2>&1 | FileCheck %s -check-prefixes=SSI,XSAFE,YSAFE - -// Full LTO, new PM: both are safe. -// RUN: %clang -fexperimental-new-pass-manager -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -c %s -flto=full -o %t.ltonewpm1.bc -// RUN: %clang -fexperimental-new-pass-manager -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -c -DBUILD2 %s -flto=full -o %t.ltonewpm2.bc +// RUN: %clang -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -c %s -flto=full -o %t.ltonewpm1.bc +// RUN: %clang -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -c -DBUILD2 %s -flto=full -o %t.ltonewpm2.bc // RUN: llvm-lto2 run -use-new-pm -o %t.ltonewpm %t.ltonewpm1.bc %t.ltonewpm2.bc -save-temps -stack-safety-print -thinlto-threads 1 -O1 \ // RUN: -r %t.ltonewpm1.bc,fn,plx \ // RUN: -r %t.ltonewpm1.bc,use,lx \ @@ -86,19 +50,8 @@ // RUN: -r %t.ltonewpm2.bc,z, 2>&1 | FileCheck %s -check-prefixes=SSI,XSAFE,YSAFE // Thin LTO: both are safe. -// RUN: %clang -fno-experimental-new-pass-manager -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -c %s -flto=thin -o %t.thinlto1.bc -// RUN: %clang -fno-experimental-new-pass-manager -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -c -DBUILD2 %s -flto=thin -o %t.thinlto2.bc -// RUN: llvm-lto2 run -o %t.thinlto %t.thinlto1.bc %t.thinlto2.bc -save-temps -stack-safety-print -thinlto-threads 1 -O1 \ -// RUN: -r %t.thinlto1.bc,fn,plx \ -// RUN: -r %t.thinlto1.bc,use,lx \ -// RUN: -r %t.thinlto1.bc,use_local,plx \ -// RUN: -r %t.thinlto1.bc,w, \ -// RUN: -r %t.thinlto2.bc,use,plx \ -// RUN: -r %t.thinlto2.bc,z, 2>&1 | FileCheck %s -check-prefixes=SSI,XSAFE,YSAFE - -// Thin LTO, new PM: both are safe. -// RUN: %clang -fexperimental-new-pass-manager -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -c %s -flto=thin -o %t.thinltonewpm1.bc -// RUN: %clang -fexperimental-new-pass-manager -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -c -DBUILD2 %s -flto=thin -o %t.thinltonewpm2.bc +// RUN: %clang -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -c %s -flto=thin -o %t.thinltonewpm1.bc +// RUN: %clang -O1 -target aarch64-unknown-linux -march=armv8+memtag -fsanitize=memtag -c -DBUILD2 %s -flto=thin -o %t.thinltonewpm2.bc // RUN: llvm-lto2 run -use-new-pm -o %t.thinltonewpm %t.thinltonewpm1.bc %t.thinltonewpm2.bc -save-temps -stack-safety-print -thinlto-threads 1 -O1 \ // RUN: -r %t.thinltonewpm1.bc,fn,plx \ // RUN: -r %t.thinltonewpm1.bc,use,lx \ diff --git a/clang/test/Driver/msan.c b/clang/test/Driver/msan.c index 103d192c3af0fdf65ab5181b0169de76ab1576fa..339840a7a96059bb56620f968497c12eb4dfb0a1 100644 --- a/clang/test/Driver/msan.c +++ b/clang/test/Driver/msan.c @@ -1,23 +1,5 @@ // REQUIRES: x86-registered-target -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK0 -// RUN: %clang -O1 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O3 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefixes=CHECK0 -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefixes=CHECK0 -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -flto -o - | FileCheck %s - -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK0 -// RUN: %clang -O1 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O3 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefixes=CHECK0 -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefixes=CHECK0 -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -flto -o - | FileCheck %s - // RUN: %clang -target mips64-linux-gnu -fsanitize=memory %s -S -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK0 // RUN: %clang -target mips64el-unknown-linux-gnu -fsanitize=memory %s -S -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK0 // RUN: %clang -target powerpc64-unknown-linux-gnu -fsanitize=memory %s -S -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK0 @@ -25,24 +7,23 @@ // Verify that -fsanitize=memory and -fsanitize=kernel-memory invoke MSan/KMSAN instrumentation. -// Also check that this works with the new pass manager with and without optimization -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK0 -// RUN: %clang -O1 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O2 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O3 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefixes=CHECK0 -// RUN: %clang -O2 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefixes=CHECK0 -// RUN: %clang -O2 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -flto -o - | FileCheck %s - -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK0 -// RUN: %clang -O1 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O2 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O3 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefixes=CHECK0 -// RUN: %clang -O2 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefixes=CHECK0 -// RUN: %clang -O2 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -flto -o - | FileCheck %s +// RUN: %clang -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK0 +// RUN: %clang -O1 -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -O2 -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -O3 -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefixes=CHECK0 +// RUN: %clang -O2 -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -flto=thin -o - | FileCheck %s +// RUN: %clang -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefixes=CHECK0 +// RUN: %clang -O2 -target x86_64-unknown-linux -fsanitize=memory %s -S -emit-llvm -flto -o - | FileCheck %s + +// RUN: %clang -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK0 +// RUN: %clang -O1 -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -O2 -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -O3 -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -flto=thin -o - | FileCheck %s --check-prefixes=CHECK0 +// RUN: %clang -O2 -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -flto=thin -o - | FileCheck %s +// RUN: %clang -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -flto -o - | FileCheck %s --check-prefixes=CHECK0 +// RUN: %clang -O2 -target x86_64-unknown-linux -fsanitize=kernel-memory %s -S -emit-llvm -flto -o - | FileCheck %s int foo(int *a) { return *a; } // CHECK0: = alloca diff --git a/clang/test/Driver/sancov.c b/clang/test/Driver/sancov.c index 62dde0da7968f2bf061eb808f25c5a231b2e77de..64181ccf59a96cd6de096e36caea1aace7175e6e 100644 --- a/clang/test/Driver/sancov.c +++ b/clang/test/Driver/sancov.c @@ -1,20 +1,11 @@ -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O1 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O2 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O3 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -O2 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -flto -o - | FileCheck %s -// RUN: %clang -O2 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -flto -o - | FileCheck %s - -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O1 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O3 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -flto -o - | FileCheck %s -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -flto -o - | FileCheck %s +// RUN: %clang -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -O1 -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -O2 -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -O3 -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -flto=thin -o - | FileCheck %s +// RUN: %clang -O2 -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -flto=thin -o - | FileCheck %s +// RUN: %clang -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -flto -o - | FileCheck %s +// RUN: %clang -O2 -target x86_64-unknown-linux -fsanitize-coverage=trace-pc-guard %s -S -emit-llvm -flto -o - | FileCheck %s // Verify that -fsanitize-coverage invokes ModuleSanitizerCoveragePass instrumentation. diff --git a/clang/test/Driver/tsan.c b/clang/test/Driver/tsan.c index 5913695d81f004a6a70cb5d5ee51f29e12968aab..82f4d72bdc4c5b675c5bc8e41c383552ec4c02f9 100644 --- a/clang/test/Driver/tsan.c +++ b/clang/test/Driver/tsan.c @@ -1,27 +1,14 @@ // REQUIRES: x86-registered-target -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O1 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O3 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -flto -o - | FileCheck %s -// RUN: %clang -O2 -fno-experimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -flto -o - | FileCheck %s -// Verify that -fsanitize=thread invokes tsan instrumentation. - -// Also check that this works with the new pass manager with and without -// optimization -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O1 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O2 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -O3 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -o - | FileCheck %s -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -O2 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -flto=thin -o - | FileCheck %s -// RUN: %clang -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -flto -o - | FileCheck %s -// RUN: %clang -O2 -fexperimental-new-pass-manager -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -flto -o - | FileCheck %s +// RUN: %clang -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -O1 -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -O2 -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -O3 -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -o - | FileCheck %s +// RUN: %clang -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -flto=thin -o - | FileCheck %s +// RUN: %clang -O2 -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -flto=thin -o - | FileCheck %s +// RUN: %clang -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -flto -o - | FileCheck %s +// RUN: %clang -O2 -target x86_64-unknown-linux -fsanitize=thread %s -S -emit-llvm -flto -o - | FileCheck %s int foo(int *a) { return *a; } // CHECK: __tsan_init diff --git a/clang/test/Frontend/optimization-remark-line-directive.c b/clang/test/Frontend/optimization-remark-line-directive.c index 32b098916e6fecfd563fc290206439e6eafddbed..1de474ec8138c8818c82093e72e4e951e28b5b0e 100644 --- a/clang/test/Frontend/optimization-remark-line-directive.c +++ b/clang/test/Frontend/optimization-remark-line-directive.c @@ -2,11 +2,9 @@ // directives. We cannot map #line directives back to // a SourceLocation. -// RUN: %clang_cc1 %s -Rpass=inline -debug-info-kind=line-tables-only -emit-llvm-only -verify -fno-experimental-new-pass-manager - // The new PM inliner is not added to the default pipeline at O0, so we add // some optimizations to trigger it. -// RUN: %clang_cc1 %s -Rpass=inline -fexperimental-new-pass-manager -O1 -debug-info-kind=line-tables-only -emit-llvm-only -verify +// RUN: %clang_cc1 %s -Rpass=inline -O1 -debug-info-kind=line-tables-only -emit-llvm-only -verify int foo(int x, int y) __attribute__((always_inline)); int foo(int x, int y) { return x + y; } diff --git a/clang/test/Headers/ms-arm64-intrin.cpp b/clang/test/Headers/ms-arm64-intrin.cpp index 76a424e0ce4cd3812c24fac6a9866d41da788b36..2e052b33bf8ec219f8d06be754864fdf3643f369 100644 --- a/clang/test/Headers/ms-arm64-intrin.cpp +++ b/clang/test/Headers/ms-arm64-intrin.cpp @@ -14,16 +14,16 @@ void check_nop() { } unsigned short check_byteswap_ushort(unsigned short val) { -// CHECK: call i16 @_byteswap_ushort(i16 noundef %val) +// CHECK: call i16 @_byteswap_ushort(i16 %val) return _byteswap_ushort(val); } unsigned long check_byteswap_ulong(unsigned long val) { -// CHECK: call i32 @_byteswap_ulong(i32 noundef %val) +// CHECK: call i32 @_byteswap_ulong(i32 %val) return _byteswap_ulong(val); } unsigned __int64 check_byteswap_uint64(unsigned __int64 val) { -// CHECK: call i64 @_byteswap_uint64(i64 noundef %val) +// CHECK: call i64 @_byteswap_uint64(i64 %val) return _byteswap_uint64(val); } diff --git a/clang/test/Headers/stdarg.cpp b/clang/test/Headers/stdarg.cpp index 9f65f2e50626b2652add13533606d53d3ce8ccb3..2278780d0c46d2a0b335f24f25afa02500c7ed08 100644 --- a/clang/test/Headers/stdarg.cpp +++ b/clang/test/Headers/stdarg.cpp @@ -15,18 +15,18 @@ #include -// AARCH64-C: define {{.*}} @f(i32 noundef %n, %"struct.std::__va_list"* noundef %list) -// AARCH64-CXX: define {{.*}} @_Z1fiSt9__va_list(i32 noundef %n, %"struct.std::__va_list"* noundef %list) -// X86_64-C: define {{.*}} @f(i32 noundef %n, %struct.__va_list_tag* noundef %list) -// X86_64-CXX: define {{.*}} @_Z1fiP13__va_list_tag(i32 noundef %n, %struct.__va_list_tag* noundef %list) -// PPC64-C: define {{.*}} @f(i32 noundef signext %n, i8* noundef %list) -// PPC64-CXX: define {{.*}} @_Z1fiPc(i32 noundef signext %n, i8* noundef %list) -// AAPCS-C: define {{.*}} @f(i32 noundef %n, [1 x i32] %list.coerce) -// AAPCS-CXX: define {{.*}} @_Z1fiSt9__va_list(i32 noundef %n, [1 x i32] %list.coerce) -// SYSTEMZ-C: define {{.*}} @f(i32 noundef signext %n, %struct.__va_list_tag* noundef %list) -// SYSTEMZ-CXX: define {{.*}} @_Z1fiP13__va_list_tag(i32 noundef signext %n, %struct.__va_list_tag* noundef %list) -// CHARPTR-C: define {{.*}} @f(i32 noundef %n, i8* noundef %list) -// CHARPTR-CXX: define {{.*}} @_Z1fiPc(i32 noundef %n, i8* noundef %list) -// VOIDPTR-C: define {{.*}} @f(i32 noundef %n, i8* noundef %list) -// VOIDPTR-CXX: define {{.*}} @_Z1fiPv(i32 noundef %n, i8* noundef %list) +// AARCH64-C: define {{.*}} @f(i32 %n, %"struct.std::__va_list"* %list) +// AARCH64-CXX: define {{.*}} @_Z1fiSt9__va_list(i32 %n, %"struct.std::__va_list"* %list) +// X86_64-C: define {{.*}} @f(i32 %n, %struct.__va_list_tag* %list) +// X86_64-CXX: define {{.*}} @_Z1fiP13__va_list_tag(i32 %n, %struct.__va_list_tag* %list) +// PPC64-C: define {{.*}} @f(i32 signext %n, i8* %list) +// PPC64-CXX: define {{.*}} @_Z1fiPc(i32 signext %n, i8* %list) +// AAPCS-C: define {{.*}} @f(i32 %n, [1 x i32] %list.coerce) +// AAPCS-CXX: define {{.*}} @_Z1fiSt9__va_list(i32 %n, [1 x i32] %list.coerce) +// SYSTEMZ-C: define {{.*}} @f(i32 signext %n, %struct.__va_list_tag* %list) +// SYSTEMZ-CXX: define {{.*}} @_Z1fiP13__va_list_tag(i32 signext %n, %struct.__va_list_tag* %list) +// CHARPTR-C: define {{.*}} @f(i32 %n, i8* %list) +// CHARPTR-CXX: define {{.*}} @_Z1fiPc(i32 %n, i8* %list) +// VOIDPTR-C: define {{.*}} @f(i32 %n, i8* %list) +// VOIDPTR-CXX: define {{.*}} @_Z1fiPv(i32 %n, i8* %list) void f(int n, va_list list) {} diff --git a/clang/test/Misc/clear-ast-before-backend.c b/clang/test/Misc/clear-ast-before-backend.c index 8e46d3bcb06821afa38c5338a62313629bf2c217..88809b86f866ed8c2cb2c10a1e1f6e284949a5de 100644 --- a/clang/test/Misc/clear-ast-before-backend.c +++ b/clang/test/Misc/clear-ast-before-backend.c @@ -1,3 +1,9 @@ // RUN: %clang_cc1 -clear-ast-before-backend %s -emit-obj -o /dev/null -O1 +// RUN: %clang_cc1 -clear-ast-before-backend %s -emit-obj -o /dev/null -print-stats 2>&1 | FileCheck %s + +// CHECK: *** Decl Stats: +// CHECK: {{.*}} decls total +// CHECK: 1 Function decls +// CHECK: Total bytes = void f() {} diff --git a/clang/test/Misc/pr32207.c b/clang/test/Misc/pr32207.c deleted file mode 100644 index dccec03d8cc7cdf8b99c3c61dd7800083834a16f..0000000000000000000000000000000000000000 --- a/clang/test/Misc/pr32207.c +++ /dev/null @@ -1,4 +0,0 @@ -// test for r305179 -// RUN: %clang_cc1 -emit-llvm -O2 -fno-experimental-new-pass-manager -mllvm -print-after-all %s -o %t 2>&1 | FileCheck %s -// CHECK: *** IR Dump After Function Integration/Inlining (inline) *** -void foo() {} diff --git a/clang/test/Modules/codegen-extern-template.cpp b/clang/test/Modules/codegen-extern-template.cpp index d43dc14b9b5ee45ce67dcf8da66d1ac72b4a4bbd..56916e710cb12cb0a483b66d9555bcffbf907335 100644 --- a/clang/test/Modules/codegen-extern-template.cpp +++ b/clang/test/Modules/codegen-extern-template.cpp @@ -6,4 +6,4 @@ template int foo(); -// CHECK: define weak_odr noundef i32 @_Z3fooIiET_v +// CHECK: define weak_odr i32 @_Z3fooIiET_v diff --git a/clang/test/Modules/codegen.test b/clang/test/Modules/codegen.test index da997640a0d8caaff60b3baa3bc6d16531b3cba8..9d0aea502cc9bcdcf06d320103725e6a46d76c9e 100644 --- a/clang/test/Modules/codegen.test +++ b/clang/test/Modules/codegen.test @@ -25,7 +25,7 @@ FOO: $_ZN13implicit_dtorD1Ev = comdat any USE: $_Z4instIiEvv = comdat any USE: $_Z10always_inlv = comdat any FOO: $_ZN13implicit_dtorD2Ev = comdat any -FOO: define weak_odr void @_Z2f1PKcz(i8* noundef %fmt, ...) #{{[0-9]+}} comdat +FOO: define weak_odr void @_Z2f1PKcz(i8* %fmt, ...) #{{[0-9]+}} comdat FOO: call void @llvm.va_start(i8* %{{[a-zA-Z0-9]*}}) Test that implicit special members are emitted into the FOO module if they're diff --git a/clang/test/Modules/cxx-irgen.cpp b/clang/test/Modules/cxx-irgen.cpp index b6529f61c8ca6236d6107aaea067dcf830d2c2e7..3decdd1e87f3a2812be5ee2a134cef02068c2456 100644 --- a/clang/test/Modules/cxx-irgen.cpp +++ b/clang/test/Modules/cxx-irgen.cpp @@ -52,7 +52,7 @@ namespace ImplicitSpecialMembers { // CHECK-LABEL: define {{.*}} @_ZN20OperatorDeleteLookup1AD0Ev( // CHECK: call {{.*}}void @_ZN20OperatorDeleteLookup1AdlEPv( - // CHECK-DAG: call {{.*}}i32 @_ZN8CtorInitIiE1fEv( + // CHECK-DAG: call {{[a-z\_\d]*[ ]?i32}} @_ZN8CtorInitIiE1fEv( extern B b1; B b2(b1); diff --git a/clang/test/Modules/initializers.cpp b/clang/test/Modules/initializers.cpp index d27502eb43cb405fef94109b206bd05cf7ea922b..8d12df8cb5d6237cd687dd9235529ec7ea84ccaa 100644 --- a/clang/test/Modules/initializers.cpp +++ b/clang/test/Modules/initializers.cpp @@ -217,7 +217,7 @@ inline void use(bool b, ...) { // CHECK: store {{.*}}, i32* @[[XB]], // CHECK-IMPORT: define {{.*}} @[[A_INIT:__cxx_global.*]]() -// CHECK-IMPORT: call noundef i32 @_Z11non_trivialv( +// CHECK-IMPORT: call i32 @_Z11non_trivialv( // CHECK-IMPORT: store {{.*}}, i32* @[[A]], // CHECK-IMPORT: define {{.*}} @[[B_INIT:__cxx_global.*]]() @@ -225,7 +225,7 @@ inline void use(bool b, ...) { // CHECK-IMPORT: store {{.*}}, i32* @[[B]], // CHECK-IMPORT: define {{.*}} @[[C_INIT:__cxx_global.*]]() -// CHECK-IMPORT: call noundef i32 @_Z11non_trivialv( +// CHECK-IMPORT: call i32 @_Z11non_trivialv( // CHECK-IMPORT: store {{.*}}, i32* @[[C]], // CHECK-IMPORT: define {{.*}} @[[D_INIT:__cxx_global.*]]() diff --git a/clang/test/Modules/templates.mm b/clang/test/Modules/templates.mm index ac61398a710f6de9b9b8fb8336e9ba61a06d1ebd..afe4aa77b19ca1295b9076c7ce0df50591fe9dfa 100644 --- a/clang/test/Modules/templates.mm +++ b/clang/test/Modules/templates.mm @@ -83,9 +83,9 @@ unsigned testMixedStruct() { // CHECK: call {{.*}}memcpy{{.*}}(i8* align {{[0-9]+}} %{{.*}}, i8* align {{[0-9]+}} bitcast ({{.*}}* @__const._Z15testMixedStructv.r to i8*), i64 16, ListInt_right r{0, 2}; - // CHECK: call void @_Z10useListIntR4ListIiE(%[[ListInt]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %[[l]]) + // CHECK: call void @_Z10useListIntR4ListIiE(%[[ListInt]]* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %[[l]]) useListInt(l); - // CHECK: call void @_Z10useListIntR4ListIiE(%[[ListInt]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %[[r]]) + // CHECK: call void @_Z10useListIntR4ListIiE(%[[ListInt]]* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %[[r]]) useListInt(r); // CHECK: load i32, i32* bitcast (i8* getelementptr inbounds (i8, i8* bitcast ({{.*}}* @list_left to i8*), i64 8) to i32*) @@ -107,11 +107,11 @@ void testDelayUpdatesImpl() { testDelayUpdates(); } void testStaticDataMember() { WithUndefinedStaticDataMember load_it; - // CHECK-LABEL: define linkonce_odr noundef i32* @_Z23getStaticDataMemberLeftv( + // CHECK-LABEL: define linkonce_odr i32* @_Z23getStaticDataMemberLeftv( // CHECK: ret i32* getelementptr inbounds ([0 x i32], [0 x i32]* @_ZN29WithUndefinedStaticDataMemberIA_iE9undefinedE, i64 0, i64 0) (void) getStaticDataMemberLeft(); - // CHECK-LABEL: define linkonce_odr noundef i32* @_Z24getStaticDataMemberRightv( + // CHECK-LABEL: define linkonce_odr i32* @_Z24getStaticDataMemberRightv( // CHECK: ret i32* getelementptr inbounds ([0 x i32], [0 x i32]* @_ZN29WithUndefinedStaticDataMemberIA_iE9undefinedE, i64 0, i64 0) (void) getStaticDataMemberRight(); } diff --git a/clang/test/OpenMP/allocate_codegen.cpp b/clang/test/OpenMP/allocate_codegen.cpp index 72672e8e44ab1b851ffa50d92825fc7b7321895d..eb70bf3c293998aac34a0c0bbcfeaebbd80f5df1 100644 --- a/clang/test/OpenMP/allocate_codegen.cpp +++ b/clang/test/OpenMP/allocate_codegen.cpp @@ -93,7 +93,7 @@ int main () { // CHECK-NOT: call {{.+}} {{__kmpc_alloc|__kmpc_free}} extern template int ST::m; -// CHECK: define{{.*}} void @{{.+}}bar{{.+}}(i32 noundef %{{.+}}, float* noundef {{.+}}) +// CHECK: define{{.*}} void @{{.+}}bar{{.+}}(i32 %{{.+}}, float* {{.+}}) void bar(int a, float &z) { // CHECK: [[A_VOID_PTR:%.+]] = call i8* @__kmpc_alloc(i32 [[GTID:%.+]], i64 4, i8* inttoptr (i64 1 to i8*)) // CHECK: [[A_ADDR:%.+]] = bitcast i8* [[A_VOID_PTR]] to i32* diff --git a/clang/test/OpenMP/allocate_codegen_attr.cpp b/clang/test/OpenMP/allocate_codegen_attr.cpp index ede6f9af5eccaf0e870b12d6797d230bfcbe766d..0ef5c77a2738ffe9b1dc2d645f1b9bc73feb5515 100644 --- a/clang/test/OpenMP/allocate_codegen_attr.cpp +++ b/clang/test/OpenMP/allocate_codegen_attr.cpp @@ -93,7 +93,7 @@ int main () { // CHECK-NOT: call {{.+}} {{__kmpc_alloc|__kmpc_free}} extern template int ST::m; -// CHECK: define{{.*}} void @{{.+}}bar{{.+}}(i32 noundef %{{.+}}, float* noundef {{.+}}) +// CHECK: define{{.*}} void @{{.+}}bar{{.+}}(i32 %{{.+}}, float* {{.+}}) void bar(int a, float &z) { // CHECK: [[A_VOID_PTR:%.+]] = call i8* @__kmpc_alloc(i32 [[GTID:%.+]], i64 4, i8* inttoptr (i64 1 to i8*)) // CHECK: [[A_ADDR:%.+]] = bitcast i8* [[A_VOID_PTR]] to i32* diff --git a/clang/test/OpenMP/assumes_include_nvptx.cpp b/clang/test/OpenMP/assumes_include_nvptx.cpp index 60ccae8f1d7dc9531a4ae21407e3a5cb8c28a05c..cab2c8a6be22034501d7c8bd7041738cb70e726d 100644 --- a/clang/test/OpenMP/assumes_include_nvptx.cpp +++ b/clang/test/OpenMP/assumes_include_nvptx.cpp @@ -13,11 +13,11 @@ // CHECK: define weak void @__omp_offloading_{{.*}}__Z17complex_reductionIfEvv_{{.*}}() [[attr0:#[0-9]]] // CHECK: call i32 @__kmpc_target_init( -// CHECK: declare noundef float @_Z3sinf(float noundef) [[attr1:#[0-9]*]] +// CHECK: declare float @_Z3sinf(float) [[attr1:#[0-9]*]] // CHECK: declare void @__kmpc_target_deinit( // CHECK: define weak void @__omp_offloading_{{.*}}__Z17complex_reductionIdEvv_{{.*}}() [[attr0]] -// CHECK: %call = call noundef double @_Z3sind(double noundef 0.000000e+00) [[attr2:#[0-9]]] -// CHECK: declare noundef double @_Z3sind(double noundef) [[attr1]] +// CHECK: %call = call double @_Z3sind(double 0.000000e+00) [[attr2:#[0-9]]] +// CHECK: declare double @_Z3sind(double) [[attr1]] // CHECK: attributes [[attr0]] // CHECK-NOT: "llvm.assume" diff --git a/clang/test/OpenMP/atomic_capture_codegen.cpp b/clang/test/OpenMP/atomic_capture_codegen.cpp index 8e653d8bb104f71c4d0acf830caf53711abce4f7..1cdd5056397b63d9ce0ad7f706e778d7a1243c65 100644 --- a/clang/test/OpenMP/atomic_capture_codegen.cpp +++ b/clang/test/OpenMP/atomic_capture_codegen.cpp @@ -278,7 +278,7 @@ int main() { // CHECK: [[EXPR_RE:%.+]] = load i32, i32* getelementptr inbounds ({ i32, i32 }, { i32, i32 }* @{{.+}}, i32 0, i32 0) // CHECK: [[EXPR_IM:%.+]] = load i32, i32* getelementptr inbounds ({ i32, i32 }, { i32, i32 }* @{{.+}}, i32 0, i32 1) // CHECK: [[BITCAST:%.+]] = bitcast { i32, i32 }* [[EXPECTED_ADDR:%.+]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 8, i8* noundef bitcast ({ i32, i32 }* [[X_ADDR:@.+]] to i8*), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 8, i8* bitcast ({ i32, i32 }* [[X_ADDR:@.+]] to i8*), i8* [[BITCAST]], i32 0) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[LD_RE_ADDR:%.+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* [[EXPECTED_ADDR]], i32 0, i32 0 @@ -292,7 +292,7 @@ int main() { // CHECK: store i32 [[NEW_IM:%.+]], i32* [[X_IM_ADDR]] // CHECK: [[EXPECTED:%.+]] = bitcast { i32, i32 }* [[EXPECTED_ADDR]] to i8* // CHECK: [[DESIRED:%.+]] = bitcast { i32, i32 }* [[DESIRED_ADDR]] to i8* -// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, i8* noundef bitcast ({ i32, i32 }* [[X_ADDR]] to i8*), i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 0, i32 noundef 0) +// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 8, i8* bitcast ({ i32, i32 }* [[X_ADDR]] to i8*), i8* [[EXPECTED]], i8* [[DESIRED]], i32 0, i32 0) // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] // CHECK: [[RE_CAST:%.+]] = sitofp i32 [[NEW_RE]] to float @@ -304,7 +304,7 @@ int main() { // CHECK: [[EXPR_RE:%.+]] = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @{{.+}}, i32 0, i32 0) // CHECK: [[EXPR_IM:%.+]] = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @{{.+}}, i32 0, i32 1) // CHECK: [[BITCAST:%.+]] = bitcast { float, float }* [[EXPECTED_ADDR:%.+]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 8, i8* noundef bitcast ({ float, float }* [[X_ADDR:@.+]] to i8*), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 8, i8* bitcast ({ float, float }* [[X_ADDR:@.+]] to i8*), i8* [[BITCAST]], i32 0) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds { float, float }, { float, float }* [[EXPECTED_ADDR]], i32 0, i32 0 @@ -318,7 +318,7 @@ int main() { // CHECK: store float [[NEW_IM:%.+]], float* [[X_IM_ADDR]] // CHECK: [[EXPECTED:%.+]] = bitcast { float, float }* [[EXPECTED_ADDR]] to i8* // CHECK: [[DESIRED:%.+]] = bitcast { float, float }* [[DESIRED_ADDR]] to i8* -// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, i8* noundef bitcast ({ float, float }* [[X_ADDR]] to i8*), i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 0, i32 noundef 0) +// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 8, i8* bitcast ({ float, float }* [[X_ADDR]] to i8*), i8* [[EXPECTED]], i8* [[DESIRED]], i32 0, i32 0) // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] // CHECK: [[RE_CAST:%.+]] = fptosi float [[X_RE_OLD]] to i32 @@ -330,7 +330,7 @@ int main() { // CHECK: [[EXPR_RE:%.+]] = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @{{.+}}, i32 0, i32 0) // CHECK: [[EXPR_IM:%.+]] = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @{{.+}}, i32 0, i32 1) // CHECK: [[BITCAST:%.+]] = bitcast { double, double }* [[EXPECTED_ADDR:%.+]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 16, i8* noundef bitcast ({ double, double }* [[X_ADDR:@.+]] to i8*), i8* noundef [[BITCAST]], i32 noundef 5) +// CHECK: call void @__atomic_load(i64 16, i8* bitcast ({ double, double }* [[X_ADDR:@.+]] to i8*), i8* [[BITCAST]], i32 5) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds { double, double }, { double, double }* [[EXPECTED_ADDR]], i32 0, i32 0 @@ -344,7 +344,7 @@ int main() { // CHECK: store double [[NEW_IM:%.+]], double* [[X_IM_ADDR]] // CHECK: [[EXPECTED:%.+]] = bitcast { double, double }* [[EXPECTED_ADDR]] to i8* // CHECK: [[DESIRED:%.+]] = bitcast { double, double }* [[DESIRED_ADDR]] to i8* -// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 16, i8* noundef bitcast ({ double, double }* [[X_ADDR]] to i8*), i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 5, i32 noundef 5) +// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* bitcast ({ double, double }* [[X_ADDR]] to i8*), i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] // CHECK: [[RE_CAST:%.+]] = fptrunc double [[NEW_RE]] to float @@ -455,7 +455,7 @@ int main() { iv = ix = ix & uiv; // CHECK: [[EXPR:%.+]] = load i64, i64* @{{.+}}, // CHECK: [[BITCAST:%.+]] = bitcast { i32, i32 }* [[EXPECTED_ADDR:%.+]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 8, i8* noundef bitcast ({ i32, i32 }* [[X_ADDR:@.+]] to i8*), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 8, i8* bitcast ({ i32, i32 }* [[X_ADDR:@.+]] to i8*), i8* [[BITCAST]], i32 0) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* [[EXPECTED_ADDR]], i32 0, i32 0 @@ -469,7 +469,7 @@ int main() { // CHECK: store i32 %{{.+}}, i32* [[X_IM_ADDR]] // CHECK: [[EXPECTED:%.+]] = bitcast { i32, i32 }* [[EXPECTED_ADDR]] to i8* // CHECK: [[DESIRED:%.+]] = bitcast { i32, i32 }* [[DESIRED_ADDR]] to i8* -// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, i8* noundef bitcast ({ i32, i32 }* [[X_ADDR]] to i8*), i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 0, i32 noundef 0) +// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 8, i8* bitcast ({ i32, i32 }* [[X_ADDR]] to i8*), i8* [[EXPECTED]], i8* [[DESIRED]], i32 0, i32 0) // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] // CHECK: store i32 [[OLD_RE]], i32* getelementptr inbounds ({ i32, i32 }, { i32, i32 }* @{{.+}}, i32 0, i32 0), @@ -538,7 +538,7 @@ int main() { {ldv = ldx; ldx -= ullv;} // CHECK: [[EXPR:%.+]] = load float, float* @{{.+}}, // CHECK: [[BITCAST:%.+]] = bitcast { i32, i32 }* [[EXPECTED_ADDR:%.+]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 8, i8* noundef bitcast ({ i32, i32 }* [[X_ADDR:@.+]] to i8*), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 8, i8* bitcast ({ i32, i32 }* [[X_ADDR:@.+]] to i8*), i8* [[BITCAST]], i32 0) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* [[EXPECTED_ADDR]], i32 0, i32 0 @@ -552,7 +552,7 @@ int main() { // CHECK: store i32 [[NEW_IM:%.+]], i32* [[X_IM_ADDR]] // CHECK: [[EXPECTED:%.+]] = bitcast { i32, i32 }* [[EXPECTED_ADDR]] to i8* // CHECK: [[DESIRED:%.+]] = bitcast { i32, i32 }* [[DESIRED_ADDR]] to i8* -// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, i8* noundef bitcast ({ i32, i32 }* [[X_ADDR]] to i8*), i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 0, i32 noundef 0) +// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 8, i8* bitcast ({ i32, i32 }* [[X_ADDR]] to i8*), i8* [[EXPECTED]], i8* [[DESIRED]], i32 0, i32 0) // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] // CHECK: store i32 [[NEW_RE]], i32* getelementptr inbounds ({ i32, i32 }, { i32, i32 }* @{{.+}}, i32 0, i32 0), @@ -680,7 +680,7 @@ int main() { iv = bfx.a = bfx.a - ldv; // CHECK: [[EXPR:%.+]] = load x86_fp80, x86_fp80* @{{.+}} // CHECK: [[BITCAST:%.+]] = bitcast i32* [[LDTEMP:%.+]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 4, i8* noundef getelementptr (i8, i8* bitcast (%struct.BitFields_packed* @{{.+}} to i8*), i64 4), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 4, i8* getelementptr (i8, i8* bitcast (%struct.BitFields_packed* @{{.+}} to i8*), i64 4), i8* [[BITCAST]], i32 0) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[OLD:%.+]] = load i32, i32* [[LDTEMP]], @@ -700,7 +700,7 @@ int main() { // CHECK: store i32 %{{.+}}, i32* [[TEMP1]] // CHECK: [[BITCAST_TEMP_OLD_BF_ADDR:%.+]] = bitcast i32* [[LDTEMP]] to i8* // CHECK: [[BITCAST_TEMP_NEW_BF_ADDR:%.+]] = bitcast i32* [[TEMP1]] to i8* -// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 4, i8* noundef getelementptr (i8, i8* bitcast (%struct.BitFields_packed* @{{.+}} to i8*), i64 4), i8* noundef [[BITCAST_TEMP_OLD_BF_ADDR]], i8* noundef [[BITCAST_TEMP_NEW_BF_ADDR]], i32 noundef 0, i32 noundef 0) +// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 4, i8* getelementptr (i8, i8* bitcast (%struct.BitFields_packed* @{{.+}} to i8*), i64 4), i8* [[BITCAST_TEMP_OLD_BF_ADDR]], i8* [[BITCAST_TEMP_NEW_BF_ADDR]], i32 0, i32 0) // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] // CHECK: store i32 [[A_ASHR]], i32* @{{.+}}, @@ -795,7 +795,7 @@ int main() { // CHECK: [[EXPR:%.+]] = load x86_fp80, x86_fp80* @{{.+}} // CHECK: [[LDTEMP:%.+]] = bitcast i32* %{{.+}} to i24* // CHECK: [[BITCAST:%.+]] = bitcast i24* [[LDTEMP]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 3, i8* noundef getelementptr (i8, i8* bitcast (%struct.BitFields3_packed* @{{.+}} to i8*), i64 1), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 3, i8* getelementptr (i8, i8* bitcast (%struct.BitFields3_packed* @{{.+}} to i8*), i64 1), i8* [[BITCAST]], i32 0) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[OLD:%.+]] = load i24, i24* [[LDTEMP]], @@ -818,7 +818,7 @@ int main() { // CHECK: store i24 %{{.+}}, i24* [[BITCAST2]] // CHECK: [[BITCAST_TEMP_OLD_BF_ADDR:%.+]] = bitcast i24* [[LDTEMP]] to i8* // CHECK: [[BITCAST_TEMP_NEW_BF_ADDR:%.+]] = bitcast i24* [[BITCAST2]] to i8* -// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 3, i8* noundef getelementptr (i8, i8* bitcast (%struct.BitFields3_packed* @{{.+}} to i8*), i64 1), i8* noundef [[BITCAST_TEMP_OLD_BF_ADDR]], i8* noundef [[BITCAST_TEMP_NEW_BF_ADDR]], i32 noundef 0, i32 noundef 0) +// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 3, i8* getelementptr (i8, i8* bitcast (%struct.BitFields3_packed* @{{.+}} to i8*), i64 1), i8* [[BITCAST_TEMP_OLD_BF_ADDR]], i8* [[BITCAST_TEMP_NEW_BF_ADDR]], i32 0, i32 0) // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] // CHECK: store i32 [[NEW_VAL]], i32* @{{.+}}, diff --git a/clang/test/OpenMP/atomic_codegen.cpp b/clang/test/OpenMP/atomic_codegen.cpp index e04f5d60a0b861500079f8aa9bfe5ecd5e2b99b2..ada47d44cc5d222867c31c199cc2dc80ee04dfc9 100644 --- a/clang/test/OpenMP/atomic_codegen.cpp +++ b/clang/test/OpenMP/atomic_codegen.cpp @@ -26,7 +26,7 @@ void parallel_atomic_ewc() { #pragma omp parallel { // CHECK: invoke void @_ZN2StC1Ev(%struct.St* {{[^,]*}} [[TEMP_ST_ADDR:%.+]]) - // CHECK: [[SCALAR_ADDR:%.+]] = invoke noundef nonnull align 4 dereferenceable(4) i32* @_ZN2St3getEv(%struct.St* {{[^,]*}} [[TEMP_ST_ADDR]]) + // CHECK: [[SCALAR_ADDR:%.+]] = invoke nonnull align 4 dereferenceable(4) i32* @_ZN2St3getEv(%struct.St* {{[^,]*}} [[TEMP_ST_ADDR]]) // CHECK: [[SCALAR_VAL:%.+]] = load atomic i32, i32* [[SCALAR_ADDR]] monotonic, align 4 // CHECK: store i32 [[SCALAR_VAL]], i32* @b // CHECK98: invoke void @_ZN2StD1Ev(%struct.St* {{[^,]*}} [[TEMP_ST_ADDR]]) @@ -34,14 +34,14 @@ void parallel_atomic_ewc() { #pragma omp atomic read b = St().get(); // CHECK-DAG: invoke void @_ZN2StC1Ev(%struct.St* {{[^,]*}} [[TEMP_ST_ADDR:%.+]]) - // CHECK-DAG: [[SCALAR_ADDR:%.+]] = invoke noundef nonnull align 4 dereferenceable(4) i32* @_ZN2St3getEv(%struct.St* {{[^,]*}} [[TEMP_ST_ADDR]]) + // CHECK-DAG: [[SCALAR_ADDR:%.+]] = invoke nonnull align 4 dereferenceable(4) i32* @_ZN2St3getEv(%struct.St* {{[^,]*}} [[TEMP_ST_ADDR]]) // CHECK-DAG: [[B_VAL:%.+]] = load i32, i32* @b // CHECK: store atomic i32 [[B_VAL]], i32* [[SCALAR_ADDR]] monotonic, align 4 // CHECK: {{invoke|call}} void @_ZN2StD1Ev(%struct.St* {{[^,]*}} [[TEMP_ST_ADDR]]) #pragma omp atomic write St().get() = b; // CHECK: invoke void @_ZN2StC1Ev(%struct.St* {{[^,]*}} [[TEMP_ST_ADDR:%.+]]) - // CHECK: [[SCALAR_ADDR:%.+]] = invoke noundef nonnull align 4 dereferenceable(4) i32* @_ZN2St3getEv(%struct.St* {{[^,]*}} [[TEMP_ST_ADDR]]) + // CHECK: [[SCALAR_ADDR:%.+]] = invoke nonnull align 4 dereferenceable(4) i32* @_ZN2St3getEv(%struct.St* {{[^,]*}} [[TEMP_ST_ADDR]]) // CHECK: [[B_VAL:%.+]] = load i32, i32* @b // CHECK: [[OLD_VAL:%.+]] = load atomic i32, i32* [[SCALAR_ADDR]] monotonic, align 4 // CHECK: br label %[[OMP_UPDATE:.+]] @@ -61,7 +61,7 @@ void parallel_atomic_ewc() { #pragma omp atomic hint(6) s.field++; // CHECK: invoke void @_ZN2StC1Ev(%struct.St* {{[^,]*}} [[TEMP_ST_ADDR:%.+]]) - // CHECK: [[SCALAR_ADDR:%.+]] = invoke noundef nonnull align 4 dereferenceable(4) i32* @_ZN2St3getEv(%struct.St* {{[^,]*}} [[TEMP_ST_ADDR]]) + // CHECK: [[SCALAR_ADDR:%.+]] = invoke nonnull align 4 dereferenceable(4) i32* @_ZN2St3getEv(%struct.St* {{[^,]*}} [[TEMP_ST_ADDR]]) // CHECK: [[B_VAL:%.+]] = load i32, i32* @b // CHECK: [[OLD_VAL:%.+]] = load atomic i32, i32* [[SCALAR_ADDR]] monotonic, align 4 // CHECK: br label %[[OMP_UPDATE:.+]] diff --git a/clang/test/OpenMP/atomic_read_codegen.c b/clang/test/OpenMP/atomic_read_codegen.c index d4b68f2c3aa7373012e73974ae5aec53dee9d23e..ce9d5527a81c10c7ccd591813e5c45fe87b0a8fa 100644 --- a/clang/test/OpenMP/atomic_read_codegen.c +++ b/clang/test/OpenMP/atomic_read_codegen.c @@ -145,17 +145,17 @@ int main() { // CHECK: store x86_fp80 [[LD]] #pragma omp atomic read ldv = ldx; -// CHECK: call{{.*}} void @__atomic_load(i64 noundef 8, +// CHECK: call{{.*}} void @__atomic_load(i64 8, // CHECK: store i32 // CHECK: store i32 #pragma omp atomic read civ = cix; -// CHECK: call{{.*}} void @__atomic_load(i64 noundef 8, +// CHECK: call{{.*}} void @__atomic_load(i64 8, // CHECK: store float // CHECK: store float #pragma omp atomic read cfv = cfx; -// CHECK: call{{.*}} void @__atomic_load(i64 noundef 16, +// CHECK: call{{.*}} void @__atomic_load(i64 16, // CHECK: call{{.*}} @__kmpc_flush( // CHECK: store double // CHECK: store double @@ -191,7 +191,7 @@ int main() { // CHECK: store i32 #pragma omp atomic read uiv = ix; -// CHECK: call{{.*}} void @__atomic_load(i64 noundef 8, +// CHECK: call{{.*}} void @__atomic_load(i64 8, // CHECK: store i64 #pragma omp atomic read lv = cix; @@ -207,7 +207,7 @@ int main() { // CHECK: store i64 #pragma omp atomic read ullv = ldx; -// CHECK: call{{.*}} void @__atomic_load(i64 noundef 8, +// CHECK: call{{.*}} void @__atomic_load(i64 8, // CHECK: store float #pragma omp atomic read fv = cix; @@ -251,7 +251,7 @@ int main() { #pragma omp atomic read ldv = bfx.a; // CHECK: [[LDTEMP_VOID_PTR:%.+]] = bitcast i32* [[LDTEMP:%.+]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 4, i8* noundef getelementptr (i8, i8* bitcast (%struct.BitFields_packed* @bfx_packed to i8*), i64 4), i8* noundef [[LDTEMP_VOID_PTR]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 4, i8* getelementptr (i8, i8* bitcast (%struct.BitFields_packed* @bfx_packed to i8*), i64 4), i8* [[LDTEMP_VOID_PTR]], i32 0) // CHECK: [[LD:%.+]] = load i32, i32* [[LDTEMP]] // CHECK: [[SHL:%.+]] = shl i32 [[LD]], 1 // CHECK: ashr i32 [[SHL]], 1 @@ -281,7 +281,7 @@ int main() { #pragma omp atomic read ldv = bfx3.a; // CHECK: [[LDTEMP_VOID_PTR:%.+]] = bitcast i24* [[LDTEMP:%.+]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 3, i8* noundef getelementptr (i8, i8* bitcast (%struct.BitFields3_packed* @bfx3_packed to i8*), i64 1), i8* noundef [[LDTEMP_VOID_PTR]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 3, i8* getelementptr (i8, i8* bitcast (%struct.BitFields3_packed* @bfx3_packed to i8*), i64 1), i8* [[LDTEMP_VOID_PTR]], i32 0) // CHECK: [[LD:%.+]] = load i24, i24* [[LDTEMP]] // CHECK: [[SHL:%.+]] = shl i24 [[LD]], 7 // CHECK: [[ASHR:%.+]] = ashr i24 [[SHL]], 10 diff --git a/clang/test/OpenMP/atomic_update_codegen.cpp b/clang/test/OpenMP/atomic_update_codegen.cpp index 063009ef3424c1cfbb9f4fdcd0579cc5765add5d..fc0673617997eb983800b20eb270ab655cbcdde3 100644 --- a/clang/test/OpenMP/atomic_update_codegen.cpp +++ b/clang/test/OpenMP/atomic_update_codegen.cpp @@ -248,7 +248,7 @@ int main() { // CHECK: [[EXPR_RE:%.+]] = load i32, i32* getelementptr inbounds ({ i32, i32 }, { i32, i32 }* @{{.+}}, i32 0, i32 0) // CHECK: [[EXPR_IM:%.+]] = load i32, i32* getelementptr inbounds ({ i32, i32 }, { i32, i32 }* @{{.+}}, i32 0, i32 1) // CHECK: [[BITCAST:%.+]] = bitcast { i32, i32 }* [[EXPECTED_ADDR:%.+]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 8, i8* noundef bitcast ({ i32, i32 }* [[X_ADDR:@.+]] to i8*), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 8, i8* bitcast ({ i32, i32 }* [[X_ADDR:@.+]] to i8*), i8* [[BITCAST]], i32 0) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* [[EXPECTED_ADDR]], i32 0, i32 0 @@ -262,7 +262,7 @@ int main() { // CHECK: store i32 %{{.+}}, i32* [[X_IM_ADDR]] // CHECK: [[EXPECTED:%.+]] = bitcast { i32, i32 }* [[EXPECTED_ADDR]] to i8* // CHECK: [[DESIRED:%.+]] = bitcast { i32, i32 }* [[DESIRED_ADDR]] to i8* -// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, i8* noundef bitcast ({ i32, i32 }* [[X_ADDR]] to i8*), i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 0, i32 noundef 0) +// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 8, i8* bitcast ({ i32, i32 }* [[X_ADDR]] to i8*), i8* [[EXPECTED]], i8* [[DESIRED]], i32 0, i32 0) // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] #pragma omp atomic @@ -270,7 +270,7 @@ int main() { // CHECK: [[EXPR_RE:%.+]] = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @{{.+}}, i32 0, i32 0) // CHECK: [[EXPR_IM:%.+]] = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @{{.+}}, i32 0, i32 1) // CHECK: [[BITCAST:%.+]] = bitcast { float, float }* [[EXPECTED_ADDR:%.+]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 8, i8* noundef bitcast ({ float, float }* [[X_ADDR:@.+]] to i8*), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 8, i8* bitcast ({ float, float }* [[X_ADDR:@.+]] to i8*), i8* [[BITCAST]], i32 0) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds { float, float }, { float, float }* [[EXPECTED_ADDR]], i32 0, i32 0 @@ -284,7 +284,7 @@ int main() { // CHECK: store float %{{.+}}, float* [[X_IM_ADDR]] // CHECK: [[EXPECTED:%.+]] = bitcast { float, float }* [[EXPECTED_ADDR]] to i8* // CHECK: [[DESIRED:%.+]] = bitcast { float, float }* [[DESIRED_ADDR]] to i8* -// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, i8* noundef bitcast ({ float, float }* [[X_ADDR]] to i8*), i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 0, i32 noundef 0) +// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 8, i8* bitcast ({ float, float }* [[X_ADDR]] to i8*), i8* [[EXPECTED]], i8* [[DESIRED]], i32 0, i32 0) // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] #pragma omp atomic update @@ -292,7 +292,7 @@ int main() { // CHECK: [[EXPR_RE:%.+]] = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @{{.+}}, i32 0, i32 0) // CHECK: [[EXPR_IM:%.+]] = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @{{.+}}, i32 0, i32 1) // CHECK: [[BITCAST:%.+]] = bitcast { double, double }* [[EXPECTED_ADDR:%.+]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 16, i8* noundef bitcast ({ double, double }* [[X_ADDR:@.+]] to i8*), i8* noundef [[BITCAST]], i32 noundef 5) +// CHECK: call void @__atomic_load(i64 16, i8* bitcast ({ double, double }* [[X_ADDR:@.+]] to i8*), i8* [[BITCAST]], i32 5) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds { double, double }, { double, double }* [[EXPECTED_ADDR]], i32 0, i32 0 @@ -306,7 +306,7 @@ int main() { // CHECK: store double %{{.+}}, double* [[X_IM_ADDR]] // CHECK: [[EXPECTED:%.+]] = bitcast { double, double }* [[EXPECTED_ADDR]] to i8* // CHECK: [[DESIRED:%.+]] = bitcast { double, double }* [[DESIRED_ADDR]] to i8* -// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 16, i8* noundef bitcast ({ double, double }* [[X_ADDR]] to i8*), i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 5, i32 noundef 5) +// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* bitcast ({ double, double }* [[X_ADDR]] to i8*), i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] // CHECK: call{{.*}} @__kmpc_flush( @@ -402,7 +402,7 @@ int main() { ix = ix & uiv; // CHECK: [[EXPR:%.+]] = load i64, i64* @{{.+}}, // CHECK: [[BITCAST:%.+]] = bitcast { i32, i32 }* [[EXPECTED_ADDR:%.+]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 8, i8* noundef bitcast ({ i32, i32 }* [[X_ADDR:@.+]] to i8*), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 8, i8* bitcast ({ i32, i32 }* [[X_ADDR:@.+]] to i8*), i8* [[BITCAST]], i32 0) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* [[EXPECTED_ADDR]], i32 0, i32 0 @@ -416,7 +416,7 @@ int main() { // CHECK: store i32 %{{.+}}, i32* [[X_IM_ADDR]] // CHECK: [[EXPECTED:%.+]] = bitcast { i32, i32 }* [[EXPECTED_ADDR]] to i8* // CHECK: [[DESIRED:%.+]] = bitcast { i32, i32 }* [[DESIRED_ADDR]] to i8* -// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, i8* noundef bitcast ({ i32, i32 }* [[X_ADDR]] to i8*), i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 0, i32 noundef 0) +// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 8, i8* bitcast ({ i32, i32 }* [[X_ADDR]] to i8*), i8* [[EXPECTED]], i8* [[DESIRED]], i32 0, i32 0) // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] #pragma omp atomic update @@ -479,7 +479,7 @@ int main() { ldx -= ullv; // CHECK: [[EXPR:%.+]] = load float, float* @{{.+}}, // CHECK: [[BITCAST:%.+]] = bitcast { i32, i32 }* [[EXPECTED_ADDR:%.+]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 8, i8* noundef bitcast ({ i32, i32 }* [[X_ADDR:@.+]] to i8*), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 8, i8* bitcast ({ i32, i32 }* [[X_ADDR:@.+]] to i8*), i8* [[BITCAST]], i32 0) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[X_RE_ADDR:%.+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* [[EXPECTED_ADDR]], i32 0, i32 0 @@ -493,7 +493,7 @@ int main() { // CHECK: store i32 %{{.+}}, i32* [[X_IM_ADDR]] // CHECK: [[EXPECTED:%.+]] = bitcast { i32, i32 }* [[EXPECTED_ADDR]] to i8* // CHECK: [[DESIRED:%.+]] = bitcast { i32, i32 }* [[DESIRED_ADDR]] to i8* -// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 8, i8* noundef bitcast ({ i32, i32 }* [[X_ADDR]] to i8*), i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 0, i32 noundef 0) +// CHECK: [[SUCCESS_FAIL:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 8, i8* bitcast ({ i32, i32 }* [[X_ADDR]] to i8*), i8* [[EXPECTED]], i8* [[DESIRED]], i32 0, i32 0) // CHECK: br i1 [[SUCCESS_FAIL]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] #pragma omp atomic update @@ -613,7 +613,7 @@ int main() { bfx.a = bfx.a - ldv; // CHECK: [[EXPR:%.+]] = load x86_fp80, x86_fp80* @{{.+}} // CHECK: [[BITCAST:%.+]] = bitcast i32* [[LDTEMP:%.+]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 4, i8* noundef getelementptr (i8, i8* bitcast (%struct.BitFields_packed* @{{.+}} to i8*), i64 4), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 4, i8* getelementptr (i8, i8* bitcast (%struct.BitFields_packed* @{{.+}} to i8*), i64 4), i8* [[BITCAST]], i32 0) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[PREV_VALUE:%.+]] = load i32, i32* [[LDTEMP]] @@ -633,7 +633,7 @@ int main() { // CHECK: store i32 %{{.+}}, i32* [[TEMP1]] // CHECK: [[BITCAST_TEMP_OLD_BF_ADDR:%.+]] = bitcast i32* [[LDTEMP]] to i8* // CHECK: [[BITCAST_TEMP_NEW_BF_ADDR:%.+]] = bitcast i32* [[TEMP1]] to i8* -// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 4, i8* noundef getelementptr (i8, i8* bitcast (%struct.BitFields_packed* @{{.+}} to i8*), i64 4), i8* noundef [[BITCAST_TEMP_OLD_BF_ADDR]], i8* noundef [[BITCAST_TEMP_NEW_BF_ADDR]], i32 noundef 0, i32 noundef 0) +// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 4, i8* getelementptr (i8, i8* bitcast (%struct.BitFields_packed* @{{.+}} to i8*), i64 4), i8* [[BITCAST_TEMP_OLD_BF_ADDR]], i8* [[BITCAST_TEMP_NEW_BF_ADDR]], i32 0, i32 0) // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] #pragma omp atomic update @@ -724,7 +724,7 @@ int main() { // CHECK: [[EXPR:%.+]] = load x86_fp80, x86_fp80* @{{.+}} // CHECK: [[LDTEMP:%.+]] = bitcast i32* %{{.+}} to i24* // CHECK: [[BITCAST:%.+]] = bitcast i24* %{{.+}} to i8* -// CHECK: call void @__atomic_load(i64 noundef 3, i8* noundef getelementptr (i8, i8* bitcast (%struct.BitFields3_packed* @{{.+}} to i8*), i64 1), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 3, i8* getelementptr (i8, i8* bitcast (%struct.BitFields3_packed* @{{.+}} to i8*), i64 1), i8* [[BITCAST]], i32 0) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[PREV_VALUE:%.+]] = load i24, i24* [[LDTEMP]] @@ -747,7 +747,7 @@ int main() { // CHECK: store i24 %{{.+}}, i24* [[TEMP1]] // CHECK: [[BITCAST_TEMP_OLD_BF_ADDR:%.+]] = bitcast i24* [[LDTEMP]] to i8* // CHECK: [[BITCAST_TEMP_NEW_BF_ADDR:%.+]] = bitcast i24* [[TEMP1]] to i8* -// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 3, i8* noundef getelementptr (i8, i8* bitcast (%struct.BitFields3_packed* @{{.+}} to i8*), i64 1), i8* noundef [[BITCAST_TEMP_OLD_BF_ADDR]], i8* noundef [[BITCAST_TEMP_NEW_BF_ADDR]], i32 noundef 0, i32 noundef 0) +// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 3, i8* getelementptr (i8, i8* bitcast (%struct.BitFields3_packed* @{{.+}} to i8*), i64 1), i8* [[BITCAST_TEMP_OLD_BF_ADDR]], i8* [[BITCAST_TEMP_NEW_BF_ADDR]], i32 0, i32 0) // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] #pragma omp atomic update diff --git a/clang/test/OpenMP/atomic_write_codegen.c b/clang/test/OpenMP/atomic_write_codegen.c index eecde89cdd2bd4b014dc3dc810660d03242cfbc4..6b1497bb90224db471d0399a081cd27a30cf2904 100644 --- a/clang/test/OpenMP/atomic_write_codegen.c +++ b/clang/test/OpenMP/atomic_write_codegen.c @@ -156,7 +156,7 @@ int main() { // CHECK: store i32 [[REAL_VAL]], i32* [[TEMP_REAL_REF]] // CHECK: store i32 [[IMG_VAL]], i32* [[TEMP_IMG_REF]] // CHECK: [[BITCAST:%.+]] = bitcast { i32, i32 }* [[TEMP]] to i8* -// CHECK: call void @__atomic_store(i64 noundef 8, i8* noundef bitcast ({ i32, i32 }* @{{.*}} to i8*), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_store(i64 8, i8* bitcast ({ i32, i32 }* @{{.*}} to i8*), i8* [[BITCAST]], i32 0) #pragma omp atomic write cix = civ; // CHECK: [[REAL_VAL:%.+]] = load float, float* getelementptr inbounds ({ float, float }, { float, float }* @{{.*}}, i32 0, i32 0) @@ -166,7 +166,7 @@ int main() { // CHECK: store float [[REAL_VAL]], float* [[TEMP_REAL_REF]] // CHECK: store float [[IMG_VAL]], float* [[TEMP_IMG_REF]] // CHECK: [[BITCAST:%.+]] = bitcast { float, float }* [[TEMP]] to i8* -// CHECK: call void @__atomic_store(i64 noundef 8, i8* noundef bitcast ({ float, float }* @{{.*}} to i8*), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_store(i64 8, i8* bitcast ({ float, float }* @{{.*}} to i8*), i8* [[BITCAST]], i32 0) #pragma omp atomic write cfx = cfv; // CHECK: [[REAL_VAL:%.+]] = load double, double* getelementptr inbounds ({ double, double }, { double, double }* @{{.*}}, i32 0, i32 0) @@ -176,7 +176,7 @@ int main() { // CHECK: store double [[REAL_VAL]], double* [[TEMP_REAL_REF]] // CHECK: store double [[IMG_VAL]], double* [[TEMP_IMG_REF]] // CHECK: [[BITCAST:%.+]] = bitcast { double, double }* [[TEMP]] to i8* -// CHECK: call void @__atomic_store(i64 noundef 16, i8* noundef bitcast ({ double, double }* @{{.*}} to i8*), i8* noundef [[BITCAST]], i32 noundef 5) +// CHECK: call void @__atomic_store(i64 16, i8* bitcast ({ double, double }* @{{.*}} to i8*), i8* [[BITCAST]], i32 5) // CHECK: call{{.*}} @__kmpc_flush( #pragma omp atomic seq_cst write cdx = cdv; @@ -217,7 +217,7 @@ int main() { // CHECK: store i32 [[VAL]], i32* [[TEMP_REAL_REF]] // CHECK: store i32 0, i32* [[TEMP_IMG_REF]] // CHECK: [[BITCAST:%.+]] = bitcast { i32, i32 }* [[TEMP]] to i8* -// CHECK: call void @__atomic_store(i64 noundef 8, i8* noundef bitcast ({ i32, i32 }* @{{.+}} to i8*), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_store(i64 8, i8* bitcast ({ i32, i32 }* @{{.+}} to i8*), i8* [[BITCAST]], i32 0) #pragma omp atomic write cix = lv; // CHECK: load i64, i64* @@ -245,7 +245,7 @@ int main() { // CHECK: store i32 [[VAL]], i32* [[TEMP_REAL_REF]] // CHECK: store i32 0, i32* [[TEMP_IMG_REF]] // CHECK: [[BITCAST:%.+]] = bitcast { i32, i32 }* [[TEMP]] to i8* -// CHECK: call void @__atomic_store(i64 noundef 8, i8* noundef bitcast ({ i32, i32 }* @{{.+}} to i8*), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_store(i64 8, i8* bitcast ({ i32, i32 }* @{{.+}} to i8*), i8* [[BITCAST]], i32 0) #pragma omp atomic write cix = fv; // CHECK: load double, double* @@ -313,7 +313,7 @@ int main() { // CHECK: load x86_fp80, x86_fp80* @{{.+}} // CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 %{{.+}} to i32 // CHECK: [[BITCAST:%.+]] = bitcast i32* [[LDTEMP:%.+]] to i8* -// CHECK: call void @__atomic_load(i64 noundef 4, i8* noundef getelementptr (i8, i8* bitcast (%struct.BitFields_packed* @{{.+}} to i8*), i64 4), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 4, i8* getelementptr (i8, i8* bitcast (%struct.BitFields_packed* @{{.+}} to i8*), i64 4), i8* [[BITCAST]], i32 0) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[OLD_BF_VALUE:%.+]] = load i32, i32* [[LDTEMP]], @@ -325,7 +325,7 @@ int main() { // CHECK: store i32 %{{.+}}, i32* [[LDTEMP1]] // CHECK: [[BITCAST_TEMP_OLD_BF_ADDR:%.+]] = bitcast i32* [[LDTEMP]] to i8* // CHECK: [[BITCAST_TEMP_NEW_BF_ADDR:%.+]] = bitcast i32* [[LDTEMP1]] to i8* -// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 4, i8* noundef getelementptr (i8, i8* bitcast (%struct.BitFields_packed* @{{.+}} to i8*), i64 4), i8* noundef [[BITCAST_TEMP_OLD_BF_ADDR]], i8* noundef [[BITCAST_TEMP_NEW_BF_ADDR]], i32 noundef 0, i32 noundef 0) +// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 4, i8* getelementptr (i8, i8* bitcast (%struct.BitFields_packed* @{{.+}} to i8*), i64 4), i8* [[BITCAST_TEMP_OLD_BF_ADDR]], i8* [[BITCAST_TEMP_NEW_BF_ADDR]], i32 0, i32 0) // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] #pragma omp atomic write @@ -392,7 +392,7 @@ int main() { // CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 %{{.+}} to i32 // CHECK: [[LDTEMP:%.+]] = bitcast i32* %{{.+}} to i24* // CHECK: [[BITCAST:%.+]] = bitcast i24* %{{.+}} to i8* -// CHECK: call void @__atomic_load(i64 noundef 3, i8* noundef getelementptr (i8, i8* bitcast (%struct.BitFields3_packed* @{{.+}} to i8*), i64 1), i8* noundef [[BITCAST]], i32 noundef 0) +// CHECK: call void @__atomic_load(i64 3, i8* getelementptr (i8, i8* bitcast (%struct.BitFields3_packed* @{{.+}} to i8*), i64 1), i8* [[BITCAST]], i32 0) // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[OLD_VAL:%.+]] = load i24, i24* %{{.+}}, @@ -405,7 +405,7 @@ int main() { // CHECK: store i24 %{{.+}}, i24* [[TEMP]] // CHECK: [[BITCAST_TEMP_OLD_BF_ADDR:%.+]] = bitcast i24* [[LDTEMP]] to i8* // CHECK: [[BITCAST_TEMP_NEW_BF_ADDR:%.+]] = bitcast i24* [[TEMP]] to i8* -// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 noundef 3, i8* noundef getelementptr (i8, i8* bitcast (%struct.BitFields3_packed* @{{.+}} to i8*), i64 1), i8* noundef [[BITCAST_TEMP_OLD_BF_ADDR]], i8* noundef [[BITCAST_TEMP_NEW_BF_ADDR]], i32 noundef 0, i32 noundef 0) +// CHECK: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i64 3, i8* getelementptr (i8, i8* bitcast (%struct.BitFields3_packed* @{{.+}} to i8*), i64 1), i8* [[BITCAST_TEMP_OLD_BF_ADDR]], i8* [[BITCAST_TEMP_NEW_BF_ADDR]], i32 0, i32 0) // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] #pragma omp atomic write diff --git a/clang/test/OpenMP/cancel_codegen.cpp b/clang/test/OpenMP/cancel_codegen.cpp index 67b0f14b79a05a320cd8798be052b70206fbf547..d87dee6184b0d2bd97e2923f0bc3290b872f8c86 100644 --- a/clang/test/OpenMP/cancel_codegen.cpp +++ b/clang/test/OpenMP/cancel_codegen.cpp @@ -79,7 +79,7 @@ for (int i = 0; i < argc; ++i) { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -301,7 +301,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -363,7 +363,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -411,7 +411,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -472,7 +472,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -542,7 +542,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -675,7 +675,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -699,7 +699,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -921,7 +921,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -983,7 +983,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1031,7 +1031,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1092,7 +1092,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1162,7 +1162,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1295,7 +1295,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1319,7 +1319,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1610,7 +1610,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1658,7 +1658,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1721,7 +1721,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1794,7 +1794,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR5]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR5]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1922,7 +1922,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1946,7 +1946,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2237,7 +2237,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2285,7 +2285,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2348,7 +2348,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2421,7 +2421,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR5]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR5]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2549,7 +2549,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2573,7 +2573,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2795,7 +2795,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2857,7 +2857,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK7-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK7-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2905,7 +2905,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2966,7 +2966,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3036,7 +3036,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3169,7 +3169,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK7-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK7-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3193,7 +3193,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3415,7 +3415,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3477,7 +3477,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK8-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK8-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -3525,7 +3525,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3586,7 +3586,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3656,7 +3656,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3789,7 +3789,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK8-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK8-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK8-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3813,7 +3813,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4104,7 +4104,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK9-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK9-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -4152,7 +4152,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4215,7 +4215,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4288,7 +4288,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4416,7 +4416,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4440,7 +4440,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4731,7 +4731,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK10-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK10-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -4779,7 +4779,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4842,7 +4842,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4915,7 +4915,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[R:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5043,7 +5043,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 diff --git a/clang/test/OpenMP/cancellation_point_codegen.cpp b/clang/test/OpenMP/cancellation_point_codegen.cpp index 9bc26393b9369ab027510d9eb1b1737c73dbbe59..401dc7f977d33a16b7ec10feadcc4ed3a5ed4886 100644 --- a/clang/test/OpenMP/cancellation_point_codegen.cpp +++ b/clang/test/OpenMP/cancellation_point_codegen.cpp @@ -81,7 +81,7 @@ for (int i = 0; i < argc; ++i) { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -316,7 +316,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -357,7 +357,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -412,7 +412,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..3 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -460,7 +460,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -527,7 +527,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -603,7 +603,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -711,7 +711,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -946,7 +946,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -987,7 +987,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1042,7 +1042,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..3 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1090,7 +1090,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1157,7 +1157,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1233,7 +1233,7 @@ for (int i = 0; i < argc; ++i) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/debug-info-complex-byval.cpp b/clang/test/OpenMP/debug-info-complex-byval.cpp index 9b277450a2f57989dccf8c33a2075d56e4ad6d64..cd09f80d55801801a8d74297b0b3643ac3829b56 100644 --- a/clang/test/OpenMP/debug-info-complex-byval.cpp +++ b/clang/test/OpenMP/debug-info-complex-byval.cpp @@ -12,21 +12,21 @@ void a() { // CHECK1-LABEL: define {{[^@]+}}@_Z1av -// CHECK1-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG7:![0-9]+]] { +// CHECK1-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[B:%.*]] = alloca { float, float }, align 4 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata { float, float }* [[B]], metadata [[META11:![0-9]+]], metadata !DIExpression()), !dbg [[DBG13:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load { float, float }, { float, float }* [[B]], align 4, !dbg [[DBG14:![0-9]+]] -// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to { float, float }*, !dbg [[DBG14]] -// CHECK1-NEXT: store { float, float } [[TMP0]], { float, float }* [[CONV]], align 4, !dbg [[DBG14]] -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_CASTED]], align 8, !dbg [[DBG14]] -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]), !dbg [[DBG14]] -// CHECK1-NEXT: ret void, !dbg [[DBG15:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata { float, float }* [[B]], metadata [[META10:![0-9]+]], metadata !DIExpression()), !dbg [[DBG12:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load { float, float }, { float, float }* [[B]], align 4, !dbg [[DBG13:![0-9]+]] +// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to { float, float }*, !dbg [[DBG13]] +// CHECK1-NEXT: store { float, float } [[TMP0]], { float, float }* [[CONV]], align 4, !dbg [[DBG13]] +// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_CASTED]], align 8, !dbg [[DBG13]] +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]]), !dbg [[DBG13]] +// CHECK1-NEXT: ret void, !dbg [[DBG14:![0-9]+]] // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined._debug__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], <2 x float> noundef [[B_COERCE:%.*]]) #[[ATTR2:[0-9]+]] !dbg [[DBG16:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], <2 x float> [[B_COERCE:%.*]]) #[[ATTR2:[0-9]+]] !dbg [[DBG15:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[B:%.*]] = alloca { float, float }, align 4 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -34,30 +34,31 @@ void a() { // CHECK1-NEXT: [[TMP0:%.*]] = bitcast { float, float }* [[B]] to <2 x float>* // CHECK1-NEXT: store <2 x float> [[B_COERCE]], <2 x float>* [[TMP0]], align 4 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META24:![0-9]+]], metadata !DIExpression()), !dbg [[DBG25:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META23:![0-9]+]], metadata !DIExpression()), !dbg [[DBG24:![0-9]+]] // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META26:![0-9]+]], metadata !DIExpression()), !dbg [[DBG25]] -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata { float, float }* [[B]], metadata [[META27:![0-9]+]], metadata !DIExpression()), !dbg [[DBG28:![0-9]+]] -// CHECK1-NEXT: ret void, !dbg [[DBG29:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META25:![0-9]+]], metadata !DIExpression()), !dbg [[DBG24]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata { float, float }* [[B]], metadata [[META26:![0-9]+]], metadata !DIExpression()), !dbg [[DBG27:![0-9]+]] +// CHECK1-NEXT: ret void, !dbg [[DBG28:![0-9]+]] // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[B:%.*]]) #[[ATTR3:[0-9]+]] !dbg [[DBG30:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[B:%.*]]) #[[ATTR3:[0-9]+]] !dbg [[DBG29:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META34:![0-9]+]], metadata !DIExpression()), !dbg [[DBG35:![0-9]+]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META33:![0-9]+]], metadata !DIExpression()), !dbg [[DBG34:![0-9]+]] // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META36:![0-9]+]], metadata !DIExpression()), !dbg [[DBG35]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META35:![0-9]+]], metadata !DIExpression()), !dbg [[DBG34]] // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i64* [[B_ADDR]], metadata [[META37:![0-9]+]], metadata !DIExpression()), !dbg [[DBG35]] -// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to { float, float }*, !dbg [[DBG38:![0-9]+]] -// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG38]] -// CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG38]] -// CHECK1-NEXT: [[TMP2:%.*]] = bitcast { float, float }* [[CONV]] to <2 x float>*, !dbg [[DBG38]] -// CHECK1-NEXT: [[TMP3:%.*]] = load <2 x float>, <2 x float>* [[TMP2]], align 8, !dbg [[DBG38]] -// CHECK1-NEXT: call void @.omp_outlined._debug__(i32* [[TMP0]], i32* [[TMP1]], <2 x float> [[TMP3]]) #[[ATTR4:[0-9]+]], !dbg [[DBG38]] -// CHECK1-NEXT: ret void, !dbg [[DBG38]] +// CHECK1-NEXT: call void @llvm.dbg.declare(metadata i64* [[B_ADDR]], metadata [[META36:![0-9]+]], metadata !DIExpression()), !dbg [[DBG34]] +// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to { float, float }*, !dbg [[DBG37:![0-9]+]] +// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG37]] +// CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG37]] +// CHECK1-NEXT: [[TMP2:%.*]] = bitcast { float, float }* [[CONV]] to <2 x float>*, !dbg [[DBG37]] +// CHECK1-NEXT: [[TMP3:%.*]] = load <2 x float>, <2 x float>* [[TMP2]], align 8, !dbg [[DBG37]] +// CHECK1-NEXT: call void @.omp_outlined._debug__(i32* [[TMP0]], i32* [[TMP1]], <2 x float> [[TMP3]]) #[[ATTR4:[0-9]+]], !dbg [[DBG37]] +// CHECK1-NEXT: ret void, !dbg [[DBG37]] // +// \ No newline at end of file diff --git a/clang/test/OpenMP/debug-info-openmp-array.cpp b/clang/test/OpenMP/debug-info-openmp-array.cpp index 719c458c229a908c8a4f6440cabb8c0744d15ed4..a81c121e56c94b45b59df940c7d14a16ab40a07a 100644 --- a/clang/test/OpenMP/debug-info-openmp-array.cpp +++ b/clang/test/OpenMP/debug-info-openmp-array.cpp @@ -14,7 +14,7 @@ void f(int m) { } // CHECK1-LABEL: define {{[^@]+}}@_Z1fi -// CHECK1-SAME: (i32 noundef [[M:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { +// CHECK1-SAME: (i32 [[M:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -38,7 +38,7 @@ void f(int m) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined._debug__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CEN:%.*]]) #[[ATTR3:[0-9]+]] !dbg [[DBG27:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[CEN:%.*]]) #[[ATTR3:[0-9]+]] !dbg [[DBG27:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -148,7 +148,7 @@ void f(int m) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CEN:%.*]]) #[[ATTR3]] !dbg [[DBG64:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[CEN:%.*]]) #[[ATTR3]] !dbg [[DBG64:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/declare_mapper_codegen.cpp b/clang/test/OpenMP/declare_mapper_codegen.cpp index 053aa9d2cc6df91e1984e281cb684ea479bc5492..5c74c71da7bffa153a610e9402560be230e5e74a 100644 --- a/clang/test/OpenMP/declare_mapper_codegen.cpp +++ b/clang/test/OpenMP/declare_mapper_codegen.cpp @@ -496,7 +496,7 @@ void foo(int a){ // CK0: {{.+}} = add nsw i32 [[VAL]], 1 // CK0: } -// CK0: define internal void [[OUTLINED:@.+]](i32 {{.*}}{{[^,]+}}, [[ANON_T]]* noalias noundef [[CTXARG:%.+]]) +// CK0: define internal void [[OUTLINED:@.+]](i32 {{.*}}{{[^,]+}}, [[ANON_T]]* noalias [[CTXARG:%.+]]) // CK0-DAG: call i32 @__tgt_target_nowait_mapper(%struct.ident_t* @{{.+}}, i64 {{.+}}, i8* {{.+}}, i32 1, i8** [[BPGEP:%[0-9]+]], i8** [[PGEP:%[0-9]+]], {{.+}}[[SIZEGEP:%[0-9]+]], {{.+}}[[NWTYPES]]{{.+}}, i8** null, i8** [[MPRGEP:%.+]], i32 0, i8* null, i32 0, i8* null) // CK0-DAG: [[BPGEP]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[BPFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0 // CK0-DAG: [[PGEP]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[PFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0 @@ -515,7 +515,7 @@ void foo(int a){ // CK0-DAG: store [[ANON_T]]* [[CTXARG]], [[ANON_T]]** [[CTXADDR]], align // CK0: } -// CK0: define internal {{.*}}i32 [[TASK_ENTRY]](i32 {{.*}}%0, [[KMP_TASK_T_WITH_PRIVATES]]* noalias noundef %1) +// CK0: define internal {{.*}}i32 [[TASK_ENTRY]](i32 {{.*}}%0, [[KMP_TASK_T_WITH_PRIVATES]]* noalias %1) // CK0: store [[KMP_TASK_T_WITH_PRIVATES]]* %1, [[KMP_TASK_T_WITH_PRIVATES]]** [[ADDR:%.+]], align // CK0: [[TASK_T_WITH_PRIVATES:%.+]] = load [[KMP_TASK_T_WITH_PRIVATES]]*, [[KMP_TASK_T_WITH_PRIVATES]]** [[ADDR]], align // CK0: [[TASKGEP:%.+]] = getelementptr inbounds [[KMP_TASK_T_WITH_PRIVATES]], [[KMP_TASK_T_WITH_PRIVATES]]* [[TASK_T_WITH_PRIVATES]], i32 0, i32 0 @@ -528,7 +528,7 @@ void foo(int a){ // CK0: call void [[OUTLINED]](i32 {{%.+}}, i32* {{%.+}}, i8* [[PRIVATES]], {{.+}}, i8* [[TASK_WITH_PRIVATES]], [[ANON_T]]* [[ANON]]) // CK0: } -// CK0: define internal void [[OUTLINE_1:@.+]](i32 {{.*}}%.global_tid.{{.+}}, [[ANON_T_0]]* noalias noundef [[CTXARG:%.+]]) +// CK0: define internal void [[OUTLINE_1:@.+]](i32 {{.*}}%.global_tid.{{.+}}, [[ANON_T_0]]* noalias [[CTXARG:%.+]]) // CK0-DAG: call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @{{.+}}, i64 {{.+}}, i8* {{.+}}, i32 1, i8** [[BPGEP:%[0-9]+]], i8** [[PGEP:%[0-9]+]], i64* [[SIZEGEP:%[0-9]+]], {{.+}}[[TEAMNWTYPES]]{{.+}}, i8** null, i8** [[MPRGEP:%.+]], i32 0, i32 0, i32 0, i8* null, i32 0, i8* null) // CK0-DAG: [[BPGEP]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[BPFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0 // CK0-DAG: [[PGEP]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[PFPADDR:%.+]], i[[SZ]] 0, i[[SZ]] 0 @@ -547,7 +547,7 @@ void foo(int a){ // CK0-DAG: store [[ANON_T_0]]* [[CTXARG]], [[ANON_T_0]]** [[CTXADDR]], align // CK0: } -// CK0: define internal {{.*}}i32 [[TASK_ENTRY_1]](i32 {{.*}}%0, [[KMP_TASK_T_WITH_PRIVATES_1]]* noalias noundef %1) +// CK0: define internal {{.*}}i32 [[TASK_ENTRY_1]](i32 {{.*}}%0, [[KMP_TASK_T_WITH_PRIVATES_1]]* noalias %1) // CK0: store [[KMP_TASK_T_WITH_PRIVATES_1]]* %1, [[KMP_TASK_T_WITH_PRIVATES_1]]** [[ADDR:%.+]], align // CK0: [[TASK_T_WITH_PRIVATES:%.+]] = load [[KMP_TASK_T_WITH_PRIVATES_1]]*, [[KMP_TASK_T_WITH_PRIVATES_1]]** [[ADDR]], align // CK0: [[TASKGEP:%.+]] = getelementptr inbounds [[KMP_TASK_T_WITH_PRIVATES_1]], [[KMP_TASK_T_WITH_PRIVATES_1]]* [[TASK_T_WITH_PRIVATES]], i32 0, i32 0 @@ -560,7 +560,7 @@ void foo(int a){ // CK0: call void [[OUTLINE_1]](i32 {{%.+}}, i32* {{%.+}}, i8* [[PRIVATES]], {{.+}}, i8* [[TASK_WITH_PRIVATES]], [[ANON_T_0]]* [[ANON]]) // CK0: } -// CK0: define internal void [[OMP_OUTLINED_16:@.+]](i32{{.*}} %{{[^,]+}}, i32* noalias noundef %{{[^,]+}}, i8* noalias noundef %{{[^,]+}} +// CK0: define internal void [[OMP_OUTLINED_16:@.+]](i32{{.*}} %{{[^,]+}}, i32* noalias %{{[^,]+}}, i8* noalias %{{[^,]+}} // CK0-DAG: call void @__tgt_target_data_begin_nowait_mapper(%struct.ident_t* @{{.+}}, i64 -1, i32 1, i8** [[BP:%[^,]+]], i8** [[P:%[^,]+]], i64* [[SZ:%[^,]+]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* [[EDNWTYPES]], i32 0, i32 0), i8** null, i8** [[MPR:%.+]]) // CK0-DAG: [[BP]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[BPADDR:%[^,]+]], i[[sz]] 0, i[[sz]] 0 // CK0-DAG: [[P]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[PADDR:%[^,]+]], i[[sz]] 0, i[[sz]] 0 @@ -575,12 +575,12 @@ void foo(int a){ // CK0: ret void // CK0: } -// CK0: define internal {{.*}}i32 [[OMP_TASK_ENTRY_18]](i32 {{.*}}%{{[^,]+}}, [[KMP_TASK_T_WITH_PRIVATES_4]]* noalias noundef %{{[^,]+}}) +// CK0: define internal {{.*}}i32 [[OMP_TASK_ENTRY_18]](i32 {{.*}}%{{[^,]+}}, [[KMP_TASK_T_WITH_PRIVATES_4]]* noalias %{{[^,]+}}) // CK0: call void [[OMP_OUTLINED_16]] // CK0: ret i32 0 // CK0: } -// CK0: define internal void [[OMP_OUTLINED_23:@.+]](i32{{.*}} %{{[^,]+}}, i32* noalias noundef %{{[^,]+}}, i8* noalias noundef %{{[^,]+}} +// CK0: define internal void [[OMP_OUTLINED_23:@.+]](i32{{.*}} %{{[^,]+}}, i32* noalias %{{[^,]+}}, i8* noalias %{{[^,]+}} // CK0-DAG: call void @__tgt_target_data_end_nowait_mapper(%struct.ident_t* @{{.+}}, i64 -1, i32 1, i8** [[BP:%[^,]+]], i8** [[P:%[^,]+]], i64* [[SZ:%[^,]+]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* [[EXDNWTYPES]], i32 0, i32 0), i8** null, i8** [[MPR:%.+]]) // CK0-DAG: [[BP]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[BPADDR:%[^,]+]], i[[sz]] 0, i[[sz]] 0 // CK0-DAG: [[P]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[PADDR:%[^,]+]], i[[sz]] 0, i[[sz]] 0 @@ -594,12 +594,12 @@ void foo(int a){ // CK0-DAG: call void [[FN]](i8* %{{[^,]+}}, [1 x i8*]** [[FPBPADDR]], [1 x i8*]** [[FPPADDR]], [1 x i64]** [[FPSZADDR]], [1 x i8*]** [[FPMPRADDR]]) // CK0: } -// CK0: define internal {{.*}}i32 [[OMP_TASK_ENTRY_25]](i32 {{.*}}%{{[^,]+}}, [[KMP_TASK_T_WITH_PRIVATES_7]]* noalias noundef %{{[^,]+}}) +// CK0: define internal {{.*}}i32 [[OMP_TASK_ENTRY_25]](i32 {{.*}}%{{[^,]+}}, [[KMP_TASK_T_WITH_PRIVATES_7]]* noalias %{{[^,]+}}) // CK0: call void [[OMP_OUTLINED_23]] // CK0: ret i32 0 // CK0: } -// CK0: define internal void [[OMP_OUTLINED_32:@.+]](i32{{.*}} %{{[^,]+}}, i32* noalias noundef %{{[^,]+}}, i8* noalias noundef %{{[^,]+}} +// CK0: define internal void [[OMP_OUTLINED_32:@.+]](i32{{.*}} %{{[^,]+}}, i32* noalias %{{[^,]+}}, i8* noalias %{{[^,]+}} // CK0-DAG: call void @__tgt_target_data_update_nowait_mapper(%struct.ident_t* @{{.+}}, i64 -1, i32 1, i8** [[BP:%[^,]+]], i8** [[P:%[^,]+]], i64* [[SZ:%[^,]+]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* [[FNWTYPES]], i32 0, i32 0), i8** null, i8** [[MPR:%.+]]) // CK0-DAG: [[BP]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[BPADDR:%[^,]+]], i[[sz]] 0, i[[sz]] 0 // CK0-DAG: [[P]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[PADDR:%[^,]+]], i[[sz]] 0, i[[sz]] 0 @@ -613,7 +613,7 @@ void foo(int a){ // CK0-DAG: call void [[FN]](i8* %{{[^,]+}}, [1 x i8*]** [[FPBPADDR]], [1 x i8*]** [[FPPADDR]], [1 x i64]** [[FPSZADDR]], [1 x i8*]** [[FPMPRADDR]]) // CK0: } -// CK0: define internal {{.*}}i32 [[OMP_TASK_ENTRY_34]](i32 {{.*}}%{{[^,]+}}, [[KMP_TASK_T_WITH_PRIVATES_10]]* noalias noundef %{{[^,]+}}) +// CK0: define internal {{.*}}i32 [[OMP_TASK_ENTRY_34]](i32 {{.*}}%{{[^,]+}}, [[KMP_TASK_T_WITH_PRIVATES_10]]* noalias %{{[^,]+}}) // CK0: call void [[OMP_OUTLINED_32]] // CK0: ret i32 0 // CK0: } diff --git a/clang/test/OpenMP/declare_reduction_codegen.c b/clang/test/OpenMP/declare_reduction_codegen.c index 438a6895e2cc350f833ce1860464a1dd6956d8bd..71f4be57f7c56b25e0eec122f61e8da0fa32cbf6 100644 --- a/clang/test/OpenMP/declare_reduction_codegen.c +++ b/clang/test/OpenMP/declare_reduction_codegen.c @@ -21,18 +21,18 @@ // CHECK-DAG: [[INT_INIT:@.+]] = private constant i32 0 #pragma omp declare reduction(+ : int, char : omp_out *= omp_in) -// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK: [[MUL:%.+]] = mul nsw i32 // CHECK-NEXT: store i32 [[MUL]], i32* // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK-LOAD: [[MUL:%.+]] = mul nsw i32 // CHECK-LOAD-NEXT: store i32 [[MUL]], i32* // CHECK-LOAD-NEXT: ret void // CHECK-LOAD-NEXT: } -// CHECK: define internal {{.*}}void @{{[^(]+}}(i8* noalias noundef %0, i8* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}(i8* noalias %0, i8* noalias %1) // CHECK: sext i8 // CHECK: sext i8 // CHECK: [[MUL:%.+]] = mul nsw i32 @@ -40,7 +40,7 @@ // CHECK-NEXT: store i8 [[TRUNC]], i8* // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i8* noalias noundef %0, i8* noalias noundef %1) +// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i8* noalias %0, i8* noalias %1) // CHECK-LOAD: sext i8 // CHECK-LOAD: sext i8 // CHECK-LOAD: [[MUL:%.+]] = mul nsw i32 @@ -50,22 +50,22 @@ // CHECK-LOAD-NEXT: } #pragma omp declare reduction(fun : float : omp_out += omp_in) initializer(omp_priv = 15 + omp_orig) -// CHECK: define internal {{.*}}void @{{[^(]+}}(float* noalias noundef %0, float* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}(float* noalias %0, float* noalias %1) // CHECK: [[ADD:%.+]] = fadd float // CHECK-NEXT: store float [[ADD]], float* // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK: define internal {{.*}}void @{{[^(]+}}(float* noalias noundef %0, float* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}(float* noalias %0, float* noalias %1) // CHECK: [[ADD:%.+]] = fadd float 1.5 // CHECK-NEXT: store float [[ADD]], float* // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(float* noalias noundef %0, float* noalias noundef %1) +// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(float* noalias %0, float* noalias %1) // CHECK-LOAD: [[ADD:%.+]] = fadd float // CHECK-LOAD-NEXT: store float [[ADD]], float* // CHECK-LOAD-NEXT: ret void // CHECK-LOAD-NEXT: } -// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(float* noalias noundef %0, float* noalias noundef %1) +// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(float* noalias %0, float* noalias %1) // CHECK-LOAD: [[ADD:%.+]] = fadd float 1.5 // CHECK-LOAD-NEXT: store float [[ADD]], float* // CHECK-LOAD-NEXT: ret void @@ -74,13 +74,13 @@ struct SSS { int field; #pragma omp declare reduction(+ : int, char : omp_out *= omp_in) - // CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) + // CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK: [[MUL:%.+]] = mul nsw i32 // CHECK-NEXT: store i32 [[MUL]], i32* // CHECK-NEXT: ret void // CHECK-NEXT: } - // CHECK: define internal {{.*}}void @{{[^(]+}}(i8* noalias noundef %0, i8* noalias noundef %1) + // CHECK: define internal {{.*}}void @{{[^(]+}}(i8* noalias %0, i8* noalias %1) // CHECK: sext i8 // CHECK: sext i8 // CHECK: [[MUL:%.+]] = mul nsw i32 @@ -93,19 +93,19 @@ struct SSS { void init(struct SSS *priv, struct SSS orig); #pragma omp declare reduction(fun : struct SSS : omp_out = omp_in) initializer(init(&omp_priv, omp_orig)) -// CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK: call void @llvm.memcpy // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK: call void @init( // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) +// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK-LOAD: call void @llvm.memcpy // CHECK-LOAD-NEXT: ret void // CHECK-LOAD-NEXT: } -// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) +// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK-LOAD: call void @init( // CHECK-LOAD-NEXT: ret void // CHECK-LOAD-NEXT: } @@ -114,37 +114,37 @@ void init(struct SSS *priv, struct SSS orig); // CHECK-LOAD-LABEL: @main int main() { #pragma omp declare reduction(fun : struct SSS : omp_out = omp_in) initializer(init(&omp_priv, omp_orig)) - // CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) + // CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK: call void @llvm.memcpy // CHECK-NEXT: ret void // CHECK-NEXT: } - // CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) + // CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK: call void @init( // CHECK-NEXT: ret void // CHECK-NEXT: } - // CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) + // CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK-LOAD: call void @llvm.memcpy // CHECK-LOAD-NEXT: ret void // CHECK-LOAD-NEXT: } - // CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) + // CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK-LOAD: call void @init( // CHECK-LOAD-NEXT: ret void // CHECK-LOAD-NEXT: } { #pragma omp declare reduction(fun : struct SSS : omp_out = omp_in) initializer(init(&omp_priv, omp_orig)) - // CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) + // CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK: call void @llvm.memcpy // CHECK-NEXT: ret void // CHECK-NEXT: } - // CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) + // CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK: call void @init( // CHECK-NEXT: ret void // CHECK-NEXT: } - // CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) + // CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK-LOAD: call void @llvm.memcpy // CHECK-LOAD-NEXT: ret void // CHECK-LOAD-NEXT: } - // CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) + // CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK-LOAD: call void @init( // CHECK-LOAD-NEXT: ret void // CHECK-LOAD-NEXT: } @@ -152,13 +152,13 @@ int main() { return 0; } -// OMP45-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// OMP45-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // OMP45-LOAD: [[MUL:%.+]] = mul nsw i32 // OMP45-LOAD-NEXT: store i32 [[MUL]], i32* // OMP45-LOAD-NEXT: ret void // OMP45-LOAD-NEXT: } -// OMP45-LOAD: define internal {{.*}}void @{{[^(]+}}(i8* noalias noundef %0, i8* noalias noundef %1) +// OMP45-LOAD: define internal {{.*}}void @{{[^(]+}}(i8* noalias %0, i8* noalias %1) // OMP45-LOAD: sext i8 // OMP45-LOAD: sext i8 // OMP45-LOAD: [[MUL:%.+]] = mul nsw i32 diff --git a/clang/test/OpenMP/declare_reduction_codegen.cpp b/clang/test/OpenMP/declare_reduction_codegen.cpp index fde9a37eeab3e07574333c1a1f5be5625ec37f6a..d70e03d0a3aaf6715a3ec4db92dd9f90c9c06ff9 100644 --- a/clang/test/OpenMP/declare_reduction_codegen.cpp +++ b/clang/test/OpenMP/declare_reduction_codegen.cpp @@ -39,18 +39,18 @@ void foo_reduction_array() { // OMP45: define internal void @ #pragma omp declare reduction(+ : int, char : omp_out *= omp_in) -// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK: [[MUL:%.+]] = mul nsw i32 // CHECK-NEXT: store i32 [[MUL]], i32* // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK-LOAD: [[MUL:%.+]] = mul nsw i32 // CHECK-LOAD-NEXT: store i32 [[MUL]], i32* // CHECK-LOAD-NEXT: ret void // CHECK-LOAD-NEXT: } -// CHECK: define internal {{.*}}void @{{[^(]+}}(i8* noalias noundef %0, i8* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}(i8* noalias %0, i8* noalias %1) // CHECK: sext i8 // CHECK: sext i8 // CHECK: [[MUL:%.+]] = mul nsw i32 @@ -59,7 +59,7 @@ void foo_reduction_array() { // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i8* noalias noundef %0, i8* noalias noundef %1) +// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i8* noalias %0, i8* noalias %1) // CHECK-LOAD: sext i8 // CHECK-LOAD: sext i8 // CHECK-LOAD: [[MUL:%.+]] = mul nsw i32 @@ -79,24 +79,24 @@ struct SSS { SSS d; -// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK: [[XOR:%.+]] = xor i32 // CHECK-NEXT: store i32 [[XOR]], i32* // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK: [[ADD:%.+]] = add nsw i32 24, // CHECK-NEXT: store i32 [[ADD]], i32* // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) -// CHECK: call void @_ZN3SSSIiE6ssssssERi(i32* noundef nonnull align {{[0-9]+}} dereferenceable{{.*}}) +// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) +// CHECK: call void @_ZN3SSSIiE6ssssssERi(i32* nonnull align {{[0-9]+}} dereferenceable{{.*}}) // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK: [[ADD:%.+]] = add nsw i32 18, // CHECK-NEXT: store i32 [[ADD]], i32* // CHECK-NEXT: ret void @@ -106,20 +106,20 @@ template void init(T &lhs, T &rhs) {} #pragma omp declare reduction(fun : SSS < int > : omp_out = omp_in) initializer(init(omp_priv, omp_orig)) -// CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK: call void @llvm.memcpy // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK: call {{.*}}void @_Z4initI3SSSIiEEvRT_S3_( // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) +// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK-LOAD: call void @llvm.memcpy // CHECK-LOAD-NEXT: ret void // CHECK-LOAD-NEXT: } -// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias noundef %0, [[SSS_INT]]* noalias noundef %1) +// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}([[SSS_INT]]* noalias %0, [[SSS_INT]]* noalias %1) // CHECK-LOAD: call {{.*}}void @_Z4initI3SSSIiEEvRT_S3_( // CHECK-LOAD-NEXT: ret void // CHECK-LOAD-NEXT: } @@ -185,57 +185,57 @@ int main() { // CHECK-LABEL: i32 @{{.+}}foo{{[^(].+}}(i32 // CHECK-LOAD-LABEL: i32 @{{.+}}foo{{[^(].+}}(i32 -// OMP45-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// OMP45-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // OMP45-LOAD: [[XOR:%.+]] = xor i32 // OMP45-LOAD-NEXT: store i32 [[XOR]], i32* // OMP45-LOAD-NEXT: ret void // OMP45-LOAD-NEXT: } -// OMP45-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// OMP45-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // OMP45-LOAD: [[ADD:%.+]] = add nsw i32 24, // OMP45-LOAD-NEXT: store i32 [[ADD]], i32* // OMP45-LOAD-NEXT: ret void // OMP45-LOAD-NEXT: } -// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK: [[ADD:%.+]] = add nsw i32 // CHECK-NEXT: store i32 [[ADD]], i32* // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK-LOAD: [[ADD:%.+]] = add nsw i32 // CHECK-LOAD-NEXT: store i32 [[ADD]], i32* // CHECK-LOAD-NEXT: ret void // CHECK-LOAD-NEXT: } -// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK: [[MUL:%.+]] = mul nsw i32 15, // CHECK-NEXT: store i32 [[MUL]], i32* // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK-LOAD: [[MUL:%.+]] = mul nsw i32 15, // CHECK-LOAD-NEXT: store i32 [[MUL]], i32* // CHECK-LOAD-NEXT: ret void // CHECK-LOAD-NEXT: } -// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK: [[DIV:%.+]] = sdiv i32 // CHECK-NEXT: store i32 [[DIV]], i32* // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK-LOAD: [[DIV:%.+]] = sdiv i32 // CHECK-LOAD-NEXT: store i32 [[DIV]], i32* // CHECK-LOAD-NEXT: ret void // CHECK-LOAD-NEXT: } -// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// CHECK: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK: [[SUB:%.+]] = sub nsw i32 11, // CHECK-NEXT: store i32 [[SUB]], i32* // CHECK-NEXT: ret void // CHECK-NEXT: } -// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias noundef %0, i32* noalias noundef %1) +// CHECK-LOAD: define internal {{.*}}void @{{[^(]+}}(i32* noalias %0, i32* noalias %1) // CHECK-LOAD: [[SUB:%.+]] = sub nsw i32 11, // CHECK-LOAD-NEXT: store i32 [[SUB]], i32* // CHECK-LOAD-NEXT: ret void diff --git a/clang/test/OpenMP/declare_reduction_codegen_in_templates.cpp b/clang/test/OpenMP/declare_reduction_codegen_in_templates.cpp index 3a86e6e59b4b42c5d547afb5620ee27aadac1120..0409c021914458ac527f50de635dbd7cb6a0fd03 100644 --- a/clang/test/OpenMP/declare_reduction_codegen_in_templates.cpp +++ b/clang/test/OpenMP/declare_reduction_codegen_in_templates.cpp @@ -10,7 +10,7 @@ // CHECK: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @{{.+}}, i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [[STD_D:%.+]]*)* [[OUTLINED:@.+]] to void (i32*, i32*, ...)*), [[STD_D]]* %{{.+}}) -// CHECK: define internal void [[OUTLINED]](i32* noalias noundef %{{.+}}, i32* noalias noundef %{{.+}}, [[STD_D]]* {{.+}}) +// CHECK: define internal void [[OUTLINED]](i32* noalias %{{.+}}, i32* noalias %{{.+}}, [[STD_D]]* {{.+}}) // CHECK: call i32 @__kmpc_reduce_nowait(%struct.ident_t* #ifndef HEADER diff --git a/clang/test/OpenMP/declare_target_codegen.cpp b/clang/test/OpenMP/declare_target_codegen.cpp index f06fd0905eaa17762ec7bee92012ff9da0e330ef..d6e97e3bbfe709cffe6ef08be81f034ccf352ef6 100644 --- a/clang/test/OpenMP/declare_target_codegen.cpp +++ b/clang/test/OpenMP/declare_target_codegen.cpp @@ -139,7 +139,7 @@ int bar() { return 1 + foo() + bar() + baz1() + baz2(); } int maini1() { int a; static long aa = 32 + bbb + ccc + fff + ggg; -// CHECK-DAG: define weak void @__omp_offloading_{{.*}}maini1{{.*}}_l[[@LINE+1]](i32* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %{{.*}}, i64 {{.*}}, i64 {{.*}}) +// CHECK-DAG: define weak void @__omp_offloading_{{.*}}maini1{{.*}}_l[[@LINE+1]](i32* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %{{.*}}, i64 {{.*}}, i64 {{.*}}) #pragma omp target map(tofrom \ : a, b) { @@ -243,7 +243,7 @@ struct TTT { // CHECK-DAG: define {{.*}}void @__omp_offloading_{{.*}}emitted{{.*}}_l[[@LINE-5]]() -// CHECK-DAG: declare extern_weak noundef signext i32 @__create() +// CHECK-DAG: declare extern_weak signext i32 @__create() // CHECK-NOT: define {{.*}}{{baz1|baz4|maini1|Base|virtual_}} diff --git a/clang/test/OpenMP/declare_target_codegen_globalization.cpp b/clang/test/OpenMP/declare_target_codegen_globalization.cpp index 52a72d50a736097701f3701d654b3fcc20ddf9aa..022a88c60a48bac18ad986943bee27b064874f1e 100644 --- a/clang/test/OpenMP/declare_target_codegen_globalization.cpp +++ b/clang/test/OpenMP/declare_target_codegen_globalization.cpp @@ -25,7 +25,7 @@ int maini1() { // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6maini1v_l16 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 @@ -48,7 +48,7 @@ int maini1() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -58,15 +58,15 @@ int maini1() { // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooRi(i32* noundef nonnull align 4 dereferenceable(4) [[B]]) #[[ATTR5:[0-9]+]] -// CHECK1-NEXT: [[CALL1:%.*]] = call noundef i32 @_Z3barv() #[[ATTR5]] +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z3fooRi(i32* nonnull align 4 dereferenceable(4) [[B]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: [[CALL1:%.*]] = call i32 @_Z3barv() #[[ATTR4]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_Z3fooRi -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 @@ -80,7 +80,7 @@ int maini1() { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A:%.*]] = call i8* @__kmpc_alloc_shared(i64 4) // CHECK1-NEXT: [[A_ON_STACK:%.*]] = bitcast i8* [[A]] to i32* -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooRi(i32* noundef nonnull align 4 dereferenceable(4) [[A_ON_STACK]]) #[[ATTR5]] +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z3fooRi(i32* nonnull align 4 dereferenceable(4) [[A_ON_STACK]]) #[[ATTR4]] // CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[A]], i64 4) // CHECK1-NEXT: ret i32 [[CALL]] // diff --git a/clang/test/OpenMP/declare_target_link_codegen.cpp b/clang/test/OpenMP/declare_target_link_codegen.cpp index 9236b7ca8e6d9b70551ab53c21cb7e74f3d88493..0b6b2b41eb4983e464cc09159e0b802e7b82e0f6 100644 --- a/clang/test/OpenMP/declare_target_link_codegen.cpp +++ b/clang/test/OpenMP/declare_target_link_codegen.cpp @@ -50,7 +50,7 @@ int maini1() { return 0; } -// DEVICE: define weak void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l42(i32* noundef nonnull align {{[0-9]+}} dereferenceable{{[^,]*}} +// DEVICE: define weak void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l42(i32* nonnull align {{[0-9]+}} dereferenceable{{[^,]*}} // DEVICE: [[C_REF:%.+]] = load i32*, i32** @c_decl_tgt_ref_ptr, // DEVICE: [[C:%.+]] = load i32, i32* [[C_REF]], // DEVICE: store i32 [[C]], i32* % @@ -81,7 +81,7 @@ int maini1() { // HOST: call void @__omp_offloading_{{.*}}_{{.*}}_{{.*}}maini1{{.*}}_l42(i32* %{{[^,]+}}) // HOST: call i32 @__tgt_target_teams_mapper(%struct.ident_t* @{{.+}}, i64 -1, i8* @.__omp_offloading_{{.+}}_l47.region_id, i32 2, {{.+}}) -// HOST: define internal void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l42(i32* noundef nonnull align {{[0-9]+}} dereferenceable{{.*}}) +// HOST: define internal void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l42(i32* nonnull align {{[0-9]+}} dereferenceable{{.*}}) // HOST: [[C:%.*]] = load i32, i32* @c, // HOST: store i32 [[C]], i32* % diff --git a/clang/test/OpenMP/declare_variant_mixed_codegen.c b/clang/test/OpenMP/declare_variant_mixed_codegen.c index 01add8583d5c726f99003e3e2ade8d0d08ffbfd5..f5a5801165cc662916834c693ff5d428ea197f57 100644 --- a/clang/test/OpenMP/declare_variant_mixed_codegen.c +++ b/clang/test/OpenMP/declare_variant_mixed_codegen.c @@ -27,8 +27,8 @@ int hst(double i) { return 1; } int base(); // HOST-LABEL: define{{.*}} void @foo() -// HOST: call i32 @hst(double noundef -1.000000e+00) -// HOST: call i32 @hst(double noundef -2.000000e+00) +// HOST: call i32 @hst(double -1.000000e+00) +// HOST: call i32 @hst(double -2.000000e+00) // HOST: call void [[OFFL:@.+_foo_l36]]() void foo() { base(-1); @@ -41,12 +41,12 @@ void foo() { } // HOST: define {{.*}}void [[OFFL]]() -// HOST: call i32 @hst(double noundef -3.000000e+00) -// HOST: call i32 @dev(double noundef -4.000000e+00) +// HOST: call i32 @hst(double -3.000000e+00) +// HOST: call i32 @dev(double -4.000000e+00) // GPU: define {{.*}}void @__omp_offloading_{{.+}}_foo_l36() -// GPU: call i32 @dev(double noundef -3.000000e+00) -// GPU: call i32 @dev(double noundef -4.000000e+00) +// GPU: call i32 @dev(double -3.000000e+00) +// GPU: call i32 @dev(double -4.000000e+00) // GPU-NOT: @base // GPU: define {{.*}}i32 @dev(double diff --git a/clang/test/OpenMP/distribute_codegen.cpp b/clang/test/OpenMP/distribute_codegen.cpp index a29000ca76b76388e1ed41dca7225cf756deec5f..234db93583a5a71e2b9e409fdf710b1136b4572d 100644 --- a/clang/test/OpenMP/distribute_codegen.cpp +++ b/clang/test/OpenMP/distribute_codegen.cpp @@ -117,7 +117,7 @@ int fint(void) { return ftemplate(); } #endif // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -181,7 +181,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -196,7 +196,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -290,7 +290,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -354,7 +354,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -369,7 +369,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -463,7 +463,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -527,7 +527,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -542,7 +542,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -703,7 +703,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -713,7 +713,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -808,7 +808,7 @@ int fint(void) { return ftemplate(); } // CHECK1-LABEL: define {{[^@]+}}@_Z4fintv // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -848,7 +848,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -858,7 +858,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -947,7 +947,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1011,7 +1011,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1026,7 +1026,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1120,7 +1120,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1184,7 +1184,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1199,7 +1199,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1293,7 +1293,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1357,7 +1357,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1372,7 +1372,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1533,7 +1533,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK2-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -1543,7 +1543,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1638,7 +1638,7 @@ int fint(void) { return ftemplate(); } // CHECK2-LABEL: define {{[^@]+}}@_Z4fintv // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -1678,7 +1678,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK2-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -1688,7 +1688,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1777,7 +1777,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -1841,7 +1841,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -1856,7 +1856,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1946,7 +1946,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2010,7 +2010,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2025,7 +2025,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2115,7 +2115,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2179,7 +2179,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2194,7 +2194,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2351,7 +2351,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 @@ -2361,7 +2361,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2456,7 +2456,7 @@ int fint(void) { return ftemplate(); } // CHECK3-LABEL: define {{[^@]+}}@_Z4fintv // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -2496,7 +2496,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -2506,7 +2506,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2595,7 +2595,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2659,7 +2659,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2674,7 +2674,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2764,7 +2764,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2828,7 +2828,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2843,7 +2843,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2933,7 +2933,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2997,7 +2997,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -3012,7 +3012,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3169,7 +3169,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK4-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 @@ -3179,7 +3179,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3274,7 +3274,7 @@ int fint(void) { return ftemplate(); } // CHECK4-LABEL: define {{[^@]+}}@_Z4fintv // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // @@ -3314,7 +3314,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK4-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -3324,7 +3324,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3413,7 +3413,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3477,7 +3477,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3492,7 +3492,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3586,7 +3586,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3650,7 +3650,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3665,7 +3665,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3759,7 +3759,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3823,7 +3823,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3838,7 +3838,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3999,7 +3999,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -4009,7 +4009,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4104,7 +4104,7 @@ int fint(void) { return ftemplate(); } // CHECK5-LABEL: define {{[^@]+}}@_Z4fintv // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK5-NEXT: ret i32 [[CALL]] // // @@ -4144,7 +4144,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK5-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -4154,7 +4154,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4243,7 +4243,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4307,7 +4307,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4322,7 +4322,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4416,7 +4416,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4480,7 +4480,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4495,7 +4495,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4589,7 +4589,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4653,7 +4653,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4668,7 +4668,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4829,7 +4829,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK6-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -4839,7 +4839,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4934,7 +4934,7 @@ int fint(void) { return ftemplate(); } // CHECK6-LABEL: define {{[^@]+}}@_Z4fintv // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK6-NEXT: ret i32 [[CALL]] // // @@ -4974,7 +4974,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK6-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -4984,7 +4984,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5073,7 +5073,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -5137,7 +5137,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -5152,7 +5152,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5242,7 +5242,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -5306,7 +5306,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -5321,7 +5321,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5411,7 +5411,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -5475,7 +5475,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -5490,7 +5490,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5647,7 +5647,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK7-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 @@ -5657,7 +5657,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5752,7 +5752,7 @@ int fint(void) { return ftemplate(); } // CHECK7-LABEL: define {{[^@]+}}@_Z4fintv // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK7-NEXT: ret i32 [[CALL]] // // @@ -5792,7 +5792,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK7-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -5802,7 +5802,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5891,7 +5891,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK8-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -5955,7 +5955,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK8-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -5970,7 +5970,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6060,7 +6060,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK8-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -6124,7 +6124,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK8-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -6139,7 +6139,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6229,7 +6229,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK8-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -6293,7 +6293,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK8-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -6308,7 +6308,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6465,7 +6465,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK8-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 @@ -6475,7 +6475,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6570,7 +6570,7 @@ int fint(void) { return ftemplate(); } // CHECK8-LABEL: define {{[^@]+}}@_Z4fintv // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK8-NEXT: ret i32 [[CALL]] // // @@ -6610,7 +6610,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK8-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -6620,7 +6620,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6709,7 +6709,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -6724,7 +6724,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6818,7 +6818,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -6833,7 +6833,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6927,7 +6927,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -6942,7 +6942,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7053,7 +7053,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK17-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -7063,7 +7063,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7156,7 +7156,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -7166,7 +7166,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7248,7 +7248,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK18-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -7263,7 +7263,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7357,7 +7357,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK18-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -7372,7 +7372,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7466,7 +7466,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK18-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -7481,7 +7481,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7592,7 +7592,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK18-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -7602,7 +7602,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7695,7 +7695,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK18-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -7705,7 +7705,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7787,7 +7787,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -7802,7 +7802,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7892,7 +7892,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -7907,7 +7907,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7997,7 +7997,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -8012,7 +8012,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8119,7 +8119,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK19-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 @@ -8129,7 +8129,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8222,7 +8222,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -8232,7 +8232,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8314,7 +8314,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 -// CHECK20-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -8329,7 +8329,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8419,7 +8419,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 -// CHECK20-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -8434,7 +8434,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8524,7 +8524,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 -// CHECK20-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -8539,7 +8539,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8646,7 +8646,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 -// CHECK20-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 @@ -8656,7 +8656,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8749,7 +8749,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 -// CHECK20-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -8759,7 +8759,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/distribute_firstprivate_codegen.cpp b/clang/test/OpenMP/distribute_firstprivate_codegen.cpp index a3723306984127417e3ede93feffabaa6697e31c..34156ca3dd88ce33d95ee17e83ea4f117f79f44f 100644 --- a/clang/test/OpenMP/distribute_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_firstprivate_codegen.cpp @@ -164,12 +164,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -191,7 +191,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -292,7 +292,7 @@ int main() { // CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 8 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -329,12 +329,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK2-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -356,7 +356,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -457,7 +457,7 @@ int main() { // CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 8 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -494,12 +494,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -529,7 +529,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -630,7 +630,7 @@ int main() { // CHECK3-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 4 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -667,12 +667,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -702,7 +702,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -803,7 +803,7 @@ int main() { // CHECK4-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 4 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -846,14 +846,14 @@ int main() { // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -918,7 +918,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -926,27 +926,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP39]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -954,12 +954,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -984,7 +984,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1110,14 +1110,14 @@ int main() { // CHECK9-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -1125,12 +1125,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1149,14 +1149,14 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1216,17 +1216,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP32]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1237,7 +1237,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1251,7 +1251,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1260,17 +1260,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1278,12 +1278,12 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1305,7 +1305,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1425,14 +1425,14 @@ int main() { // CHECK9-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done14: @@ -1440,17 +1440,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1461,7 +1461,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1475,7 +1475,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1510,14 +1510,14 @@ int main() { // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1582,7 +1582,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1590,27 +1590,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP39]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1618,12 +1618,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1648,7 +1648,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1774,14 +1774,14 @@ int main() { // CHECK10-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done15: @@ -1789,12 +1789,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -1813,14 +1813,14 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1880,17 +1880,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP32]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1901,7 +1901,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1915,7 +1915,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1924,17 +1924,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1942,12 +1942,12 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1969,7 +1969,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2089,14 +2089,14 @@ int main() { // CHECK10-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done14: @@ -2104,17 +2104,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2125,7 +2125,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2139,7 +2139,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2174,14 +2174,14 @@ int main() { // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -2244,7 +2244,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2252,27 +2252,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP39]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2280,12 +2280,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2308,7 +2308,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2432,14 +2432,14 @@ int main() { // CHECK11-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -2447,12 +2447,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2471,14 +2471,14 @@ int main() { // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2537,17 +2537,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP32]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2558,7 +2558,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2572,7 +2572,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2581,17 +2581,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2599,12 +2599,12 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2625,7 +2625,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2743,14 +2743,14 @@ int main() { // CHECK11-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -2758,17 +2758,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2779,7 +2779,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2793,7 +2793,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2828,14 +2828,14 @@ int main() { // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -2898,7 +2898,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2906,27 +2906,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP39]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2934,12 +2934,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2962,7 +2962,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3086,14 +3086,14 @@ int main() { // CHECK12-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done14: @@ -3101,12 +3101,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // @@ -3125,14 +3125,14 @@ int main() { // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3191,17 +3191,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP32]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3212,7 +3212,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3226,7 +3226,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3235,17 +3235,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3253,12 +3253,12 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3279,7 +3279,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3397,14 +3397,14 @@ int main() { // CHECK12-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done13: @@ -3412,17 +3412,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3433,7 +3433,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3447,7 +3447,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3461,3 +3461,4 @@ int main() { // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_lastprivate_codegen.cpp b/clang/test/OpenMP/distribute_lastprivate_codegen.cpp index 6ef2b7d1854bfac643b5bfb02c49bfe4f9833475..18a9ac314f8258abf5d4000e94528c79e5a0db80 100644 --- a/clang/test/OpenMP/distribute_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_lastprivate_codegen.cpp @@ -154,12 +154,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -181,7 +181,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -264,7 +264,7 @@ int main() { // CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -316,12 +316,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK2-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -343,7 +343,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -426,7 +426,7 @@ int main() { // CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -478,12 +478,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -513,7 +513,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -596,7 +596,7 @@ int main() { // CHECK3-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -648,12 +648,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -683,7 +683,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -766,7 +766,7 @@ int main() { // CHECK4-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 4 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -825,14 +825,14 @@ int main() { // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -897,7 +897,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -905,27 +905,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP39]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -933,12 +933,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -963,7 +963,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1011,13 +1011,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -1107,14 +1107,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP36]], i32* [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done16: @@ -1122,12 +1122,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1146,14 +1146,14 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1213,17 +1213,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP32]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1234,7 +1234,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1248,7 +1248,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1257,17 +1257,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1275,12 +1275,12 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1302,7 +1302,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1346,13 +1346,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -1440,14 +1440,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -1455,17 +1455,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1476,7 +1476,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1490,7 +1490,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1526,14 +1526,14 @@ int main() { // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1598,7 +1598,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1606,27 +1606,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP39]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1634,12 +1634,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1664,7 +1664,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1712,13 +1712,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -1808,14 +1808,14 @@ int main() { // CHECK10-NEXT: store i32 [[TMP36]], i32* [[TMP4]], align 4 // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done16: @@ -1823,12 +1823,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -1847,14 +1847,14 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1914,17 +1914,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP32]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1935,7 +1935,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1949,7 +1949,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1958,17 +1958,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1976,12 +1976,12 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2003,7 +2003,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2047,13 +2047,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -2141,14 +2141,14 @@ int main() { // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done15: @@ -2156,17 +2156,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2177,7 +2177,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2191,7 +2191,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2227,14 +2227,14 @@ int main() { // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -2297,7 +2297,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2305,27 +2305,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP39]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2333,12 +2333,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2361,7 +2361,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2409,13 +2409,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK11-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -2503,14 +2503,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP36]], i32* [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done15: @@ -2518,12 +2518,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2542,14 +2542,14 @@ int main() { // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2608,17 +2608,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP32]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2629,7 +2629,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2643,7 +2643,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2652,17 +2652,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2670,12 +2670,12 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2696,7 +2696,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2740,13 +2740,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK11-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -2832,14 +2832,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -2847,17 +2847,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2868,7 +2868,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2882,7 +2882,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2918,14 +2918,14 @@ int main() { // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -2988,7 +2988,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2996,27 +2996,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP39]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3024,12 +3024,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3052,7 +3052,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3100,13 +3100,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK12-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -3194,14 +3194,14 @@ int main() { // CHECK12-NEXT: store i32 [[TMP36]], i32* [[TMP4]], align 4 // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done15: @@ -3209,12 +3209,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // @@ -3233,14 +3233,14 @@ int main() { // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3299,17 +3299,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP32]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3320,7 +3320,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3334,7 +3334,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3343,17 +3343,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3361,12 +3361,12 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3387,7 +3387,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3431,13 +3431,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK12-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -3523,14 +3523,14 @@ int main() { // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false) // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done14: @@ -3538,17 +3538,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3559,7 +3559,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3573,7 +3573,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3587,3 +3587,4 @@ int main() { // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_codegen.cpp index 0825b1aa6077a32dd11014bbc794b24fcef9f819..d1a3f33c33d9c9bf98f6440768af68e986c22d7d 100644 --- a/clang/test/OpenMP/distribute_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_codegen.cpp @@ -790,12 +790,12 @@ int main() { // CHECK1-NEXT: store double** [[C]], double*** [[TMP3]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 // CHECK1-NEXT: store i32* [[CH]], i32** [[TMP4]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l117 -// CHECK1-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -811,7 +811,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -905,7 +905,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1014,7 +1014,7 @@ int main() { // CHECK1-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1035,7 +1035,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l160 -// CHECK1-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -1051,7 +1051,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1145,7 +1145,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1254,7 +1254,7 @@ int main() { // CHECK1-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1275,7 +1275,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l202 -// CHECK1-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -1294,7 +1294,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1416,7 +1416,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1525,7 +1525,7 @@ int main() { // CHECK1-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_2]], %class.anon.2* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1546,7 +1546,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l235 -// CHECK1-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -1562,7 +1562,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1656,7 +1656,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1765,7 +1765,7 @@ int main() { // CHECK1-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_3]], %class.anon.3* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1786,7 +1786,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l267 -// CHECK1-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -1805,7 +1805,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1910,7 +1910,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2032,7 +2032,7 @@ int main() { // CHECK1-NEXT: store double** [[TMP2]], double*** [[TMP33]], align 8 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[CLASS_ANON_4]], %class.anon.4* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store double** [[TMP3]], double*** [[TMP34]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2063,7 +2063,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l300 -// CHECK1-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -2079,7 +2079,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2173,7 +2173,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2279,7 +2279,7 @@ int main() { // CHECK1-NEXT: store double** [[TMP2]], double*** [[TMP31]], align 8, !llvm.access.group !12 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store double** [[TMP3]], double*** [[TMP32]], align 8, !llvm.access.group !12 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* noundef [[REF_TMP]]), !llvm.access.group !12 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !12 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2299,7 +2299,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l329 -// CHECK1-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -2318,7 +2318,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2423,7 +2423,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2533,7 +2533,7 @@ int main() { // CHECK1-NEXT: store double** [[TMP2]], double*** [[TMP32]], align 8, !llvm.access.group !15 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store double** [[TMP3]], double*** [[TMP33]], align 8, !llvm.access.group !15 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* noundef [[REF_TMP]]), !llvm.access.group !15 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !15 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2582,12 +2582,12 @@ int main() { // CHECK2-NEXT: store double** [[C]], double*** [[TMP3]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 // CHECK2-NEXT: store i32* [[CH]], i32** [[TMP4]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l117 -// CHECK2-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -2603,7 +2603,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2697,7 +2697,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2806,7 +2806,7 @@ int main() { // CHECK2-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2827,7 +2827,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l160 -// CHECK2-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -2843,7 +2843,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2937,7 +2937,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3046,7 +3046,7 @@ int main() { // CHECK2-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3067,7 +3067,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l202 -// CHECK2-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -3086,7 +3086,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3208,7 +3208,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3317,7 +3317,7 @@ int main() { // CHECK2-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_2]], %class.anon.2* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3338,7 +3338,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l235 -// CHECK2-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -3354,7 +3354,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3448,7 +3448,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3557,7 +3557,7 @@ int main() { // CHECK2-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_3]], %class.anon.3* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3578,7 +3578,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l267 -// CHECK2-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -3597,7 +3597,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3702,7 +3702,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3824,7 +3824,7 @@ int main() { // CHECK2-NEXT: store double** [[TMP2]], double*** [[TMP33]], align 8 // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[CLASS_ANON_4]], %class.anon.4* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store double** [[TMP3]], double*** [[TMP34]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3855,7 +3855,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l300 -// CHECK2-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -3871,7 +3871,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3965,7 +3965,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4071,7 +4071,7 @@ int main() { // CHECK2-NEXT: store double** [[TMP2]], double*** [[TMP31]], align 8, !llvm.access.group !12 // CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store double** [[TMP3]], double*** [[TMP32]], align 8, !llvm.access.group !12 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* noundef [[REF_TMP]]), !llvm.access.group !12 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !12 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -4091,7 +4091,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l329 -// CHECK2-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -4110,7 +4110,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4215,7 +4215,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4325,7 +4325,7 @@ int main() { // CHECK2-NEXT: store double** [[TMP2]], double*** [[TMP32]], align 8, !llvm.access.group !15 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store double** [[TMP3]], double*** [[TMP33]], align 8, !llvm.access.group !15 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* noundef [[REF_TMP]]), !llvm.access.group !15 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !15 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -4374,12 +4374,12 @@ int main() { // CHECK3-NEXT: store double** [[C]], double*** [[TMP3]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 // CHECK3-NEXT: store i32* [[CH]], i32** [[TMP4]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(20) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l117 -// CHECK3-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -4394,7 +4394,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4486,7 +4486,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4590,7 +4590,7 @@ int main() { // CHECK3-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -4611,7 +4611,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l160 -// CHECK3-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -4626,7 +4626,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4718,7 +4718,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4822,7 +4822,7 @@ int main() { // CHECK3-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -4843,7 +4843,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l202 -// CHECK3-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -4860,7 +4860,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4980,7 +4980,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5084,7 +5084,7 @@ int main() { // CHECK3-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_2]], %class.anon.2* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -5105,7 +5105,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l235 -// CHECK3-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -5120,7 +5120,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5212,7 +5212,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5316,7 +5316,7 @@ int main() { // CHECK3-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_3]], %class.anon.3* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -5337,7 +5337,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l267 -// CHECK3-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -5354,7 +5354,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5456,7 +5456,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5570,7 +5570,7 @@ int main() { // CHECK3-NEXT: store double** [[TMP2]], double*** [[TMP33]], align 4 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[CLASS_ANON_4]], %class.anon.4* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store double** [[TMP3]], double*** [[TMP34]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -5601,7 +5601,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l300 -// CHECK3-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -5616,7 +5616,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5708,7 +5708,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5809,7 +5809,7 @@ int main() { // CHECK3-NEXT: store double** [[TMP2]], double*** [[TMP31]], align 4, !llvm.access.group !13 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store double** [[TMP3]], double*** [[TMP32]], align 4, !llvm.access.group !13 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* noundef [[REF_TMP]]), !llvm.access.group !13 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !13 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -5829,7 +5829,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l329 -// CHECK3-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -5846,7 +5846,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5948,7 +5948,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6052,7 +6052,7 @@ int main() { // CHECK3-NEXT: store double** [[TMP2]], double*** [[TMP32]], align 4, !llvm.access.group !16 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store double** [[TMP3]], double*** [[TMP33]], align 4, !llvm.access.group !16 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* noundef [[REF_TMP]]), !llvm.access.group !16 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !16 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -6101,12 +6101,12 @@ int main() { // CHECK4-NEXT: store double** [[C]], double*** [[TMP3]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 // CHECK4-NEXT: store i32* [[CH]], i32** [[TMP4]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(20) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l117 -// CHECK4-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -6121,7 +6121,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6213,7 +6213,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6317,7 +6317,7 @@ int main() { // CHECK4-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -6338,7 +6338,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l160 -// CHECK4-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -6353,7 +6353,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6445,7 +6445,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6549,7 +6549,7 @@ int main() { // CHECK4-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -6570,7 +6570,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l202 -// CHECK4-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -6587,7 +6587,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6707,7 +6707,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6811,7 +6811,7 @@ int main() { // CHECK4-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_2]], %class.anon.2* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -6832,7 +6832,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l235 -// CHECK4-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -6847,7 +6847,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6939,7 +6939,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7043,7 +7043,7 @@ int main() { // CHECK4-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_3]], %class.anon.3* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -7064,7 +7064,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l267 -// CHECK4-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -7081,7 +7081,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7183,7 +7183,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7297,7 +7297,7 @@ int main() { // CHECK4-NEXT: store double** [[TMP2]], double*** [[TMP33]], align 4 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[CLASS_ANON_4]], %class.anon.4* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store double** [[TMP3]], double*** [[TMP34]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -7328,7 +7328,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l300 -// CHECK4-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -7343,7 +7343,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7435,7 +7435,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7536,7 +7536,7 @@ int main() { // CHECK4-NEXT: store double** [[TMP2]], double*** [[TMP31]], align 4, !llvm.access.group !13 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store double** [[TMP3]], double*** [[TMP32]], align 4, !llvm.access.group !13 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* noundef [[REF_TMP]]), !llvm.access.group !13 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !13 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -7556,7 +7556,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l329 -// CHECK4-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -7573,7 +7573,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7675,7 +7675,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7779,7 +7779,7 @@ int main() { // CHECK4-NEXT: store double** [[TMP2]], double*** [[TMP32]], align 4, !llvm.access.group !16 // CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store double** [[TMP3]], double*** [[TMP33]], align 4, !llvm.access.group !16 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* noundef [[REF_TMP]]), !llvm.access.group !16 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !16 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -8318,12 +8318,12 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562(i64 [[TMP213]], i64 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT91]] // CHECK9: omp_offload.cont91: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: ret i32 [[CALL]] // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369 -// CHECK9-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -8339,7 +8339,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8433,7 +8433,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8553,7 +8553,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408 -// CHECK9-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -8569,7 +8569,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8663,7 +8663,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8783,7 +8783,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447 -// CHECK9-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -8802,7 +8802,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8924,7 +8924,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9044,7 +9044,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478 -// CHECK9-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -9060,7 +9060,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9154,7 +9154,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9274,7 +9274,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506 -// CHECK9-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -9293,7 +9293,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9398,7 +9398,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9541,7 +9541,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536 -// CHECK9-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -9557,7 +9557,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9651,7 +9651,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9767,7 +9767,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562 -// CHECK9-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -9786,7 +9786,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9891,7 +9891,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10525,7 +10525,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -10541,7 +10541,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10635,7 +10635,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10770,7 +10770,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -10786,7 +10786,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10880,7 +10880,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..31 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11000,7 +11000,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59 -// CHECK9-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -11019,7 +11019,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..34 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11141,7 +11141,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..35 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11261,7 +11261,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -11277,7 +11277,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..38 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11371,7 +11371,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..39 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11491,7 +11491,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 -// CHECK9-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -11510,7 +11510,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..42 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11615,7 +11615,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..43 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11758,7 +11758,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -11774,7 +11774,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..46 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11868,7 +11868,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..47 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11984,7 +11984,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91 -// CHECK9-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -12003,7 +12003,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..50 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12108,7 +12108,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..51 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12747,12 +12747,12 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562(i64 [[TMP213]], i64 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT91]] // CHECK10: omp_offload.cont91: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: ret i32 [[CALL]] // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369 -// CHECK10-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -12768,7 +12768,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12862,7 +12862,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12982,7 +12982,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408 -// CHECK10-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -12998,7 +12998,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13092,7 +13092,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13212,7 +13212,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447 -// CHECK10-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -13231,7 +13231,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13353,7 +13353,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13473,7 +13473,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478 -// CHECK10-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -13489,7 +13489,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13583,7 +13583,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13703,7 +13703,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506 -// CHECK10-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -13722,7 +13722,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13827,7 +13827,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13970,7 +13970,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536 -// CHECK10-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -13986,7 +13986,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14080,7 +14080,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14196,7 +14196,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562 -// CHECK10-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -14215,7 +14215,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14320,7 +14320,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14954,7 +14954,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -14970,7 +14970,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15064,7 +15064,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15199,7 +15199,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -15215,7 +15215,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15309,7 +15309,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..31 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15429,7 +15429,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59 -// CHECK10-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -15448,7 +15448,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..34 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15570,7 +15570,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..35 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15690,7 +15690,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -15706,7 +15706,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..38 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15800,7 +15800,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..39 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15920,7 +15920,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 -// CHECK10-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -15939,7 +15939,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..42 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16044,7 +16044,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..43 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16187,7 +16187,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -16203,7 +16203,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..46 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16297,7 +16297,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..47 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16413,7 +16413,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91 -// CHECK10-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -16432,7 +16432,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..50 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16537,7 +16537,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..51 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17166,12 +17166,12 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562(i32 [[TMP213]], i32 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT82]] // CHECK11: omp_offload.cont82: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: ret i32 [[CALL]] // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369 -// CHECK11-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -17186,7 +17186,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17278,7 +17278,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17393,7 +17393,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408 -// CHECK11-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -17408,7 +17408,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17500,7 +17500,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17615,7 +17615,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447 -// CHECK11-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -17632,7 +17632,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17752,7 +17752,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17867,7 +17867,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478 -// CHECK11-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -17882,7 +17882,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17974,7 +17974,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18089,7 +18089,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506 -// CHECK11-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -18106,7 +18106,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18208,7 +18208,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18343,7 +18343,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536 -// CHECK11-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -18358,7 +18358,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18450,7 +18450,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18561,7 +18561,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562 -// CHECK11-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -18578,7 +18578,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18680,7 +18680,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19298,7 +19298,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -19313,7 +19313,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19405,7 +19405,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19535,7 +19535,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -19550,7 +19550,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19642,7 +19642,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..31 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19757,7 +19757,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59 -// CHECK11-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -19774,7 +19774,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..34 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19894,7 +19894,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..35 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20009,7 +20009,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -20024,7 +20024,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..38 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20116,7 +20116,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..39 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20231,7 +20231,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 -// CHECK11-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -20248,7 +20248,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..42 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20350,7 +20350,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..43 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20485,7 +20485,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -20500,7 +20500,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..46 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20592,7 +20592,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..47 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20703,7 +20703,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91 -// CHECK11-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -20720,7 +20720,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..50 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20822,7 +20822,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..51 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21445,12 +21445,12 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562(i32 [[TMP213]], i32 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT82]] // CHECK12: omp_offload.cont82: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: ret i32 [[CALL]] // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l369 -// CHECK12-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -21465,7 +21465,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21557,7 +21557,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21672,7 +21672,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l408 -// CHECK12-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -21687,7 +21687,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21779,7 +21779,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21894,7 +21894,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l447 -// CHECK12-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -21911,7 +21911,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22031,7 +22031,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22146,7 +22146,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l478 -// CHECK12-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -22161,7 +22161,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22253,7 +22253,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22368,7 +22368,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l506 -// CHECK12-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -22385,7 +22385,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22487,7 +22487,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22622,7 +22622,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l536 -// CHECK12-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -22637,7 +22637,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22729,7 +22729,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22840,7 +22840,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l562 -// CHECK12-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -22857,7 +22857,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22959,7 +22959,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23577,7 +23577,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -23592,7 +23592,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23684,7 +23684,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23814,7 +23814,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l51 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -23829,7 +23829,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23921,7 +23921,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..31 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24036,7 +24036,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l59 -// CHECK12-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -24053,7 +24053,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..34 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24173,7 +24173,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..35 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24288,7 +24288,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l67 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -24303,7 +24303,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..38 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24395,7 +24395,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..39 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24510,7 +24510,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 -// CHECK12-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -24527,7 +24527,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..42 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24629,7 +24629,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..43 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24764,7 +24764,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l83 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -24779,7 +24779,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..46 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24871,7 +24871,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..47 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24982,7 +24982,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l91 -// CHECK12-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -24999,7 +24999,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..50 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25101,7 +25101,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..51 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp index e1b321702223458f87783954a6f79c33f6049e67..ee085daa60a50dd5d5f31deb28c08217b24f8087 100644 --- a/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp @@ -277,12 +277,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -304,7 +304,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -417,7 +417,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -500,7 +500,7 @@ int main() { // CHECK1-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store float* [[CONV3]], float** [[TMP15]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -537,12 +537,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK2-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -564,7 +564,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -677,7 +677,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -760,7 +760,7 @@ int main() { // CHECK2-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store float* [[CONV3]], float** [[TMP15]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -797,12 +797,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -832,7 +832,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -937,7 +937,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], i32 noundef [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], i32 [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1020,7 +1020,7 @@ int main() { // CHECK3-NEXT: store i32* [[SVAR_ADDR]], i32** [[TMP16]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store float* [[CONV1]], float** [[TMP17]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1057,12 +1057,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -1092,7 +1092,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1197,7 +1197,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], i32 noundef [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], i32 [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1280,7 +1280,7 @@ int main() { // CHECK4-NEXT: store i32* [[SVAR_ADDR]], i32** [[TMP16]], align 4 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store float* [[CONV1]], float** [[TMP17]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1323,14 +1323,14 @@ int main() { // CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK8-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK8-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1395,7 +1395,7 @@ int main() { // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK8: omp_offload.cont: -// CHECK8-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1403,27 +1403,27 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done3: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP39]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1431,12 +1431,12 @@ int main() { // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK8-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK8-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1461,7 +1461,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1586,14 +1586,14 @@ int main() { // CHECK8-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK8-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done13: @@ -1601,7 +1601,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1728,14 +1728,14 @@ int main() { // CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR8]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 // CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done15: @@ -1743,12 +1743,12 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // @@ -1767,14 +1767,14 @@ int main() { // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1834,17 +1834,17 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP32]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1855,7 +1855,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1869,7 +1869,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1878,17 +1878,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1896,12 +1896,12 @@ int main() { // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 -// CHECK8-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1923,7 +1923,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2037,14 +2037,14 @@ int main() { // CHECK8-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done11: @@ -2052,7 +2052,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2176,14 +2176,14 @@ int main() { // CHECK8-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done14: @@ -2191,17 +2191,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2212,7 +2212,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2226,7 +2226,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2261,14 +2261,14 @@ int main() { // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -2333,7 +2333,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -2341,27 +2341,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP39]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2369,12 +2369,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2399,7 +2399,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2524,14 +2524,14 @@ int main() { // CHECK9-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP36]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done13: @@ -2539,7 +2539,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2666,14 +2666,14 @@ int main() { // CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR8]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -2681,12 +2681,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -2705,14 +2705,14 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -2772,17 +2772,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP32]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2793,7 +2793,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2807,7 +2807,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2816,17 +2816,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2834,12 +2834,12 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2861,7 +2861,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2975,14 +2975,14 @@ int main() { // CHECK9-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done11: @@ -2990,7 +2990,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3114,14 +3114,14 @@ int main() { // CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done14: @@ -3129,17 +3129,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3150,7 +3150,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3164,7 +3164,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3199,14 +3199,14 @@ int main() { // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -3269,7 +3269,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -3277,27 +3277,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP39]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3305,12 +3305,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK10-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3333,7 +3333,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3454,14 +3454,14 @@ int main() { // CHECK10-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done12: @@ -3469,7 +3469,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3590,14 +3590,14 @@ int main() { // CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done11: @@ -3605,12 +3605,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -3629,14 +3629,14 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3695,17 +3695,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP32]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3716,7 +3716,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3730,7 +3730,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3739,17 +3739,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3757,12 +3757,12 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 -// CHECK10-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3783,7 +3783,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3894,14 +3894,14 @@ int main() { // CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done11: @@ -3909,7 +3909,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4028,14 +4028,14 @@ int main() { // CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done11: @@ -4043,17 +4043,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4064,7 +4064,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4078,7 +4078,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4113,14 +4113,14 @@ int main() { // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -4183,7 +4183,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -4191,27 +4191,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP39]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4219,12 +4219,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -4247,7 +4247,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4368,14 +4368,14 @@ int main() { // CHECK11-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP33]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP34]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done12: @@ -4383,7 +4383,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4504,14 +4504,14 @@ int main() { // CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done11: @@ -4519,12 +4519,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -4543,14 +4543,14 @@ int main() { // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4609,17 +4609,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP32]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4630,7 +4630,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4644,7 +4644,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4653,17 +4653,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4671,12 +4671,12 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -4697,7 +4697,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4808,14 +4808,14 @@ int main() { // CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done11: @@ -4823,7 +4823,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4942,14 +4942,14 @@ int main() { // CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done11: @@ -4957,17 +4957,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4978,7 +4978,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4992,7 +4992,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5006,3 +5006,4 @@ int main() { // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) // CHECK11-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp index 4c07425fbbd04c183f58c8e56174d5396989ec66..828e820110f51c01f26d137d4fedd2dcea977f46 100644 --- a/clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp @@ -152,7 +152,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -212,7 +212,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -289,7 +289,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -354,7 +354,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -475,7 +475,7 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK1: omp_offload.cont6: // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -487,7 +487,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -547,7 +547,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -625,7 +625,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -690,7 +690,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -761,7 +761,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK1-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -771,7 +771,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -848,7 +848,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -919,7 +919,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK1-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -979,7 +979,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1039,7 +1039,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1117,7 +1117,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1182,7 +1182,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1253,7 +1253,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 -// CHECK1-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -1263,7 +1263,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1340,7 +1340,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1449,7 +1449,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1509,7 +1509,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1586,7 +1586,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1651,7 +1651,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1772,7 +1772,7 @@ int main() { // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK2: omp_offload.cont6: // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -1784,7 +1784,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1844,7 +1844,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1922,7 +1922,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1987,7 +1987,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2058,7 +2058,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK2-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -2068,7 +2068,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2145,7 +2145,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2216,7 +2216,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK2-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -2276,7 +2276,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2336,7 +2336,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2414,7 +2414,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2479,7 +2479,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2550,7 +2550,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 -// CHECK2-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -2560,7 +2560,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2637,7 +2637,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2746,7 +2746,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2806,7 +2806,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2883,7 +2883,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2948,7 +2948,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3069,7 +3069,7 @@ int main() { // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK5: omp_offload.cont6: // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK5-NEXT: ret i32 [[CALL]] // // @@ -3081,7 +3081,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3141,7 +3141,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3219,7 +3219,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3284,7 +3284,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3355,7 +3355,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK5-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -3365,7 +3365,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3442,7 +3442,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3513,7 +3513,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK5-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK5-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -3573,7 +3573,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3633,7 +3633,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3711,7 +3711,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3776,7 +3776,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3847,7 +3847,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 -// CHECK5-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -3857,7 +3857,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3934,7 +3934,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4043,7 +4043,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4103,7 +4103,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4180,7 +4180,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4245,7 +4245,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4366,7 +4366,7 @@ int main() { // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK6: omp_offload.cont6: // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK6-NEXT: ret i32 [[CALL]] // // @@ -4378,7 +4378,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4438,7 +4438,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4516,7 +4516,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4581,7 +4581,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4652,7 +4652,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK6-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -4662,7 +4662,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4739,7 +4739,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4810,7 +4810,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK6-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK6-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -4870,7 +4870,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4930,7 +4930,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5008,7 +5008,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5073,7 +5073,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5144,7 +5144,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 -// CHECK6-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -5154,7 +5154,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5231,7 +5231,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5340,7 +5340,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5400,7 +5400,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5477,7 +5477,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5542,7 +5542,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5663,7 +5663,7 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK9: omp_offload.cont6: // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK9-NEXT: ret i32 [[CALL]] // // @@ -5675,7 +5675,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5735,7 +5735,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5813,7 +5813,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5878,7 +5878,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5949,7 +5949,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK9-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -5959,7 +5959,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6036,7 +6036,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6107,7 +6107,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK9-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK9-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -6167,7 +6167,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6227,7 +6227,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6305,7 +6305,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6370,7 +6370,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6441,7 +6441,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 -// CHECK9-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -6451,7 +6451,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6528,7 +6528,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6637,7 +6637,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6697,7 +6697,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6774,7 +6774,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6839,7 +6839,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6960,7 +6960,7 @@ int main() { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK10: omp_offload.cont6: // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK10-NEXT: ret i32 [[CALL]] // // @@ -6972,7 +6972,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7032,7 +7032,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7110,7 +7110,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7175,7 +7175,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7246,7 +7246,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK10-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -7256,7 +7256,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7333,7 +7333,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7404,7 +7404,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK10-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK10-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -7464,7 +7464,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7524,7 +7524,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7602,7 +7602,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7667,7 +7667,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7738,7 +7738,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 -// CHECK10-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -7748,7 +7748,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7825,7 +7825,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7934,7 +7934,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7994,7 +7994,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8071,7 +8071,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8136,7 +8136,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8257,7 +8257,7 @@ int main() { // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK13: omp_offload.cont6: // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK13-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK13-NEXT: ret i32 [[CALL]] // // @@ -8269,7 +8269,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8329,7 +8329,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8407,7 +8407,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8472,7 +8472,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8543,7 +8543,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK13-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -8553,7 +8553,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8630,7 +8630,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8701,7 +8701,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK13-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK13-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -8761,7 +8761,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8821,7 +8821,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8899,7 +8899,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8964,7 +8964,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9035,7 +9035,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 -// CHECK13-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -9045,7 +9045,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9122,7 +9122,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9231,7 +9231,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9291,7 +9291,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9368,7 +9368,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9433,7 +9433,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9554,7 +9554,7 @@ int main() { // CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK14: omp_offload.cont6: // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK14-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK14-NEXT: ret i32 [[CALL]] // // @@ -9566,7 +9566,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9626,7 +9626,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9704,7 +9704,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9769,7 +9769,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9840,7 +9840,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 -// CHECK14-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -9850,7 +9850,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9927,7 +9927,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9998,7 +9998,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK14-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK14-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -10058,7 +10058,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10118,7 +10118,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10196,7 +10196,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10261,7 +10261,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10332,7 +10332,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l75 -// CHECK14-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -10342,7 +10342,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10419,7 +10419,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp index 6aa2a3f6d02793c0d9ffb841b20dab15068e3498..afaadba9d0c4776c1989f103c79a11e7701fe3f2 100644 --- a/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp @@ -218,12 +218,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -245,7 +245,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -345,7 +345,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -435,7 +435,7 @@ int main() { // CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -487,12 +487,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK2-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -514,7 +514,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -614,7 +614,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -704,7 +704,7 @@ int main() { // CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -756,12 +756,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -791,7 +791,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -889,7 +889,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -977,7 +977,7 @@ int main() { // CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1029,12 +1029,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -1064,7 +1064,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1162,7 +1162,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1250,7 +1250,7 @@ int main() { // CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1309,14 +1309,14 @@ int main() { // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1381,7 +1381,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1389,27 +1389,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP39]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1417,12 +1417,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1447,7 +1447,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1495,13 +1495,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -1580,14 +1580,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done13: @@ -1595,7 +1595,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1650,13 +1650,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -1746,14 +1746,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done16: @@ -1761,12 +1761,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1785,14 +1785,14 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1852,17 +1852,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP32]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1873,7 +1873,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1887,7 +1887,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1896,17 +1896,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1914,12 +1914,12 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1941,7 +1941,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1985,13 +1985,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -2068,14 +2068,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done12: @@ -2083,7 +2083,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2134,13 +2134,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -2228,14 +2228,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -2243,17 +2243,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2264,7 +2264,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2278,7 +2278,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2314,14 +2314,14 @@ int main() { // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -2386,7 +2386,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -2394,27 +2394,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP39]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2422,12 +2422,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2452,7 +2452,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2500,13 +2500,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -2585,14 +2585,14 @@ int main() { // CHECK10-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done13: @@ -2600,7 +2600,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2655,13 +2655,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -2751,14 +2751,14 @@ int main() { // CHECK10-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done16: @@ -2766,12 +2766,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -2790,14 +2790,14 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -2857,17 +2857,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP32]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2878,7 +2878,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2892,7 +2892,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2901,17 +2901,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2919,12 +2919,12 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2946,7 +2946,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2990,13 +2990,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -3073,14 +3073,14 @@ int main() { // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done12: @@ -3088,7 +3088,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3139,13 +3139,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -3233,14 +3233,14 @@ int main() { // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done15: @@ -3248,17 +3248,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3269,7 +3269,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3283,7 +3283,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3319,14 +3319,14 @@ int main() { // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -3389,7 +3389,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -3397,27 +3397,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP39]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3425,12 +3425,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3453,7 +3453,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3501,13 +3501,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK11-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -3584,14 +3584,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP33]], i32* [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -3599,7 +3599,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3652,13 +3652,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -3746,14 +3746,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -3761,12 +3761,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -3785,14 +3785,14 @@ int main() { // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3851,17 +3851,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP32]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3872,7 +3872,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3886,7 +3886,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3895,17 +3895,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3913,12 +3913,12 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3939,7 +3939,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3983,13 +3983,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK11-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -4064,14 +4064,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done12: @@ -4079,7 +4079,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4128,13 +4128,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -4220,14 +4220,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -4235,17 +4235,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4256,7 +4256,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4270,7 +4270,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4306,14 +4306,14 @@ int main() { // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -4376,7 +4376,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -4384,27 +4384,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP39]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4412,12 +4412,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -4440,7 +4440,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4488,13 +4488,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK12-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -4571,14 +4571,14 @@ int main() { // CHECK12-NEXT: store i32 [[TMP33]], i32* [[TMP4]], align 4 // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done13: @@ -4586,7 +4586,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4639,13 +4639,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -4733,14 +4733,14 @@ int main() { // CHECK12-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done14: @@ -4748,12 +4748,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // @@ -4772,14 +4772,14 @@ int main() { // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4838,17 +4838,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP32]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4859,7 +4859,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4873,7 +4873,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4882,17 +4882,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4900,12 +4900,12 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -4926,7 +4926,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4970,13 +4970,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK12-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -5051,14 +5051,14 @@ int main() { // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done12: @@ -5066,7 +5066,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5115,13 +5115,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -5207,14 +5207,14 @@ int main() { // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done13: @@ -5222,17 +5222,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5243,7 +5243,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5257,7 +5257,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5271,3 +5271,4 @@ int main() { // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp index 56f95cdd9a44eff8e1c331da9f0a77fd2be76329..b1a573ef88561eee96d640024a9469db6f7c1d02 100644 --- a/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp @@ -108,8 +108,8 @@ int main() { // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK1-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK1-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK1-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -127,7 +127,7 @@ int main() { // CHECK1-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK1-NEXT: br label [[EH_RESUME:%.*]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -154,16 +154,16 @@ int main() { // CHECK1: omp_offload.cont3: // CHECK1-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK1-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK1-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK1-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK1-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK1: invoke.cont5: // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK1-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK1-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK1: invoke.cont7: // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK1-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP17]] // CHECK1: eh.resume: @@ -175,7 +175,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -183,12 +183,12 @@ int main() { // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -208,7 +208,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -269,7 +269,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -355,7 +355,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -365,7 +365,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -431,7 +431,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -558,17 +558,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -582,7 +582,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -598,7 +598,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -659,7 +659,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -745,7 +745,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -806,7 +806,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -892,7 +892,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -953,7 +953,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1039,7 +1039,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1082,15 +1082,15 @@ int main() { // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: -// CHECK1-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) +// CHECK1-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK1: invoke.cont2: // CHECK1-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 @@ -1110,7 +1110,7 @@ int main() { // CHECK1-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 // CHECK1-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK1-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1130,7 +1130,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1230,8 +1230,8 @@ int main() { // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK2-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK2-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK2-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -1249,7 +1249,7 @@ int main() { // CHECK2-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK2-NEXT: br label [[EH_RESUME:%.*]] // CHECK2: omp_offload.cont: // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -1276,16 +1276,16 @@ int main() { // CHECK2: omp_offload.cont3: // CHECK2-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK2-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK2-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK2-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK2-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK2: invoke.cont5: // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK2-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK2-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK2: invoke.cont7: // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK2-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP17]] // CHECK2: eh.resume: @@ -1297,7 +1297,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -1305,12 +1305,12 @@ int main() { // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1330,7 +1330,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1391,7 +1391,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1477,7 +1477,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK2-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -1487,7 +1487,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1553,7 +1553,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1680,17 +1680,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -1704,7 +1704,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1720,7 +1720,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1781,7 +1781,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1867,7 +1867,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1928,7 +1928,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2014,7 +2014,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2075,7 +2075,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2161,7 +2161,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2204,15 +2204,15 @@ int main() { // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK2-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: -// CHECK2-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) +// CHECK2-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK2: invoke.cont2: // CHECK2-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 @@ -2232,7 +2232,7 @@ int main() { // CHECK2-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 // CHECK2-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK2-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2252,7 +2252,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2352,8 +2352,8 @@ int main() { // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK5-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK5-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK5-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -2371,7 +2371,7 @@ int main() { // CHECK5-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK5-NEXT: br label [[EH_RESUME:%.*]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -2398,16 +2398,16 @@ int main() { // CHECK5: omp_offload.cont3: // CHECK5-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK5-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK5-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK5-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK5-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK5: invoke.cont5: // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK5-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK5-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK5-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK5: invoke.cont7: // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK5-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP17]] // CHECK5: eh.resume: @@ -2419,7 +2419,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -2427,12 +2427,12 @@ int main() { // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2452,7 +2452,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2513,7 +2513,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2599,7 +2599,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -2609,7 +2609,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2675,7 +2675,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2802,17 +2802,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK5-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -2833,7 +2833,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2894,7 +2894,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2980,7 +2980,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3041,7 +3041,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3127,7 +3127,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3188,7 +3188,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3274,7 +3274,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3317,15 +3317,15 @@ int main() { // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: -// CHECK5-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) +// CHECK5-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK5-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK5: invoke.cont2: // CHECK5-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 // CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 @@ -3345,7 +3345,7 @@ int main() { // CHECK5-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK5-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 // CHECK5-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK5-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -3365,7 +3365,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3444,7 +3444,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3474,8 +3474,8 @@ int main() { // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK6-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK6-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK6-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -3493,7 +3493,7 @@ int main() { // CHECK6-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK6-NEXT: br label [[EH_RESUME:%.*]] // CHECK6: omp_offload.cont: // CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -3520,16 +3520,16 @@ int main() { // CHECK6: omp_offload.cont3: // CHECK6-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK6-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK6-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK6-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK6-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK6: invoke.cont5: // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK6-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK6-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK6-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK6: invoke.cont7: // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK6-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP17]] // CHECK6: eh.resume: @@ -3541,7 +3541,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -3549,12 +3549,12 @@ int main() { // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3574,7 +3574,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3635,7 +3635,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3721,7 +3721,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK6-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -3731,7 +3731,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3797,7 +3797,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3924,17 +3924,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK6-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -3955,7 +3955,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4016,7 +4016,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4102,7 +4102,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4163,7 +4163,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4249,7 +4249,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4310,7 +4310,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4396,7 +4396,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4439,15 +4439,15 @@ int main() { // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: -// CHECK6-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) +// CHECK6-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK6-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK6: invoke.cont2: // CHECK6-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 // CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 @@ -4467,7 +4467,7 @@ int main() { // CHECK6-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK6-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 // CHECK6-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK6-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4487,7 +4487,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4566,7 +4566,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4596,8 +4596,8 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK9-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK9-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK9-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK9: invoke.cont: // CHECK9-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -4615,7 +4615,7 @@ int main() { // CHECK9-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK9-NEXT: br label [[EH_RESUME:%.*]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -4642,16 +4642,16 @@ int main() { // CHECK9: omp_offload.cont3: // CHECK9-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK9-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK9-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK9-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK9-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK9: invoke.cont5: // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK9-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK9-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK9-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK9: invoke.cont7: // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK9-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP17]] // CHECK9: eh.resume: @@ -4663,7 +4663,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -4671,12 +4671,12 @@ int main() { // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4696,7 +4696,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4757,7 +4757,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4843,7 +4843,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK9-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -4853,7 +4853,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4919,7 +4919,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5046,17 +5046,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK9-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -5070,7 +5070,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5086,7 +5086,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5147,7 +5147,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5233,7 +5233,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5294,7 +5294,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5380,7 +5380,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5441,7 +5441,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5527,7 +5527,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5570,15 +5570,15 @@ int main() { // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK9-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK9: invoke.cont: -// CHECK9-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) +// CHECK9-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK9: invoke.cont2: // CHECK9-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 // CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 @@ -5598,7 +5598,7 @@ int main() { // CHECK9-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK9-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 // CHECK9-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK9-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -5618,7 +5618,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5718,8 +5718,8 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK10-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK10-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK10-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK10: invoke.cont: // CHECK10-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -5737,7 +5737,7 @@ int main() { // CHECK10-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK10-NEXT: br label [[EH_RESUME:%.*]] // CHECK10: omp_offload.cont: // CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -5764,16 +5764,16 @@ int main() { // CHECK10: omp_offload.cont3: // CHECK10-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK10-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK10-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK10-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK10-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK10: invoke.cont5: // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK10-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK10-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK10-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK10: invoke.cont7: // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK10-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP17]] // CHECK10: eh.resume: @@ -5785,7 +5785,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -5793,12 +5793,12 @@ int main() { // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5818,7 +5818,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5879,7 +5879,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5965,7 +5965,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK10-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -5975,7 +5975,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6041,7 +6041,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6168,17 +6168,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK10-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -6192,7 +6192,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6208,7 +6208,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6269,7 +6269,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6355,7 +6355,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6416,7 +6416,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6502,7 +6502,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6563,7 +6563,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6649,7 +6649,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6692,15 +6692,15 @@ int main() { // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK10-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK10: invoke.cont: -// CHECK10-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) +// CHECK10-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK10-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK10: invoke.cont2: // CHECK10-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 // CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 @@ -6720,7 +6720,7 @@ int main() { // CHECK10-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK10-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 // CHECK10-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK10-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -6740,7 +6740,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6840,8 +6840,8 @@ int main() { // CHECK13-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK13-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK13-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK13-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK13: invoke.cont: // CHECK13-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -6859,7 +6859,7 @@ int main() { // CHECK13-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK13-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK13-NEXT: br label [[EH_RESUME:%.*]] // CHECK13: omp_offload.cont: // CHECK13-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -6886,16 +6886,16 @@ int main() { // CHECK13: omp_offload.cont3: // CHECK13-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK13-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK13-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK13-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK13-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK13: invoke.cont5: // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK13-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK13-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK13-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK13: invoke.cont7: // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK13-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP17]] // CHECK13: eh.resume: @@ -6907,7 +6907,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -6915,12 +6915,12 @@ int main() { // CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6940,7 +6940,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7001,7 +7001,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7087,7 +7087,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK13-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK13-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -7097,7 +7097,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7163,7 +7163,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7290,17 +7290,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK13-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -7321,7 +7321,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7382,7 +7382,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7468,7 +7468,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7529,7 +7529,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7615,7 +7615,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7676,7 +7676,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7762,7 +7762,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7805,15 +7805,15 @@ int main() { // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK13-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK13: invoke.cont: -// CHECK13-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) +// CHECK13-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK13-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK13: invoke.cont2: // CHECK13-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 // CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 @@ -7833,7 +7833,7 @@ int main() { // CHECK13-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK13-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 // CHECK13-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK13-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -7853,7 +7853,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7932,7 +7932,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -7962,8 +7962,8 @@ int main() { // CHECK14-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK14-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK14-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK14-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK14: invoke.cont: // CHECK14-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -7981,7 +7981,7 @@ int main() { // CHECK14-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK14-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK14-NEXT: br label [[EH_RESUME:%.*]] // CHECK14: omp_offload.cont: // CHECK14-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -8008,16 +8008,16 @@ int main() { // CHECK14: omp_offload.cont3: // CHECK14-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK14-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK14-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK14-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK14-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK14: invoke.cont5: // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK14-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK14-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK14-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK14: invoke.cont7: // CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK14-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP17]] // CHECK14: eh.resume: @@ -8029,7 +8029,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -8037,12 +8037,12 @@ int main() { // CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -8062,7 +8062,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8123,7 +8123,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8209,7 +8209,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK14-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK14-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -8219,7 +8219,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8285,7 +8285,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8412,17 +8412,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK14-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -8443,7 +8443,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8504,7 +8504,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8590,7 +8590,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8651,7 +8651,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8737,7 +8737,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8798,7 +8798,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8884,7 +8884,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8927,15 +8927,15 @@ int main() { // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK14-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK14: invoke.cont: -// CHECK14-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) +// CHECK14-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK14-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK14: invoke.cont2: // CHECK14-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 // CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 @@ -8955,7 +8955,7 @@ int main() { // CHECK14-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK14-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 // CHECK14-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK14-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8975,7 +8975,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9054,7 +9054,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -9068,3 +9068,4 @@ int main() { // CHECK14-NEXT: call void @__tgt_register_requires(i64 1) // CHECK14-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp index 07ac3abe0d59a7819a07592ef7c29f07ff91f8fa..e4012ba7af823ea5b870f2a788af5973016bfaf6 100644 --- a/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp @@ -144,7 +144,7 @@ int main() { // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK1-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // @@ -156,7 +156,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -224,7 +224,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -301,7 +301,7 @@ int main() { // CHECK1-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -333,7 +333,7 @@ int main() { // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK2-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // @@ -345,7 +345,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -413,7 +413,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -490,7 +490,7 @@ int main() { // CHECK2-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 8 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -522,7 +522,7 @@ int main() { // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK3-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // @@ -534,7 +534,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -600,7 +600,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -675,7 +675,7 @@ int main() { // CHECK3-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -707,7 +707,7 @@ int main() { // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // @@ -719,7 +719,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -785,7 +785,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -860,7 +860,7 @@ int main() { // CHECK4-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 4 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -898,14 +898,14 @@ int main() { // CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) @@ -916,7 +916,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -924,27 +924,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP4]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -952,7 +952,7 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // @@ -964,7 +964,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -994,12 +994,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1044,14 +1044,14 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done5: @@ -1059,7 +1059,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1099,12 +1099,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP3]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -1161,14 +1161,14 @@ int main() { // CHECK9-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done9: @@ -1176,12 +1176,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1196,14 +1196,14 @@ int main() { // CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -1221,17 +1221,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP4]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1242,7 +1242,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1256,7 +1256,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1265,17 +1265,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1283,7 +1283,7 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // @@ -1295,7 +1295,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1324,12 +1324,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1374,14 +1374,14 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done5: @@ -1389,7 +1389,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1428,12 +1428,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -1490,14 +1490,14 @@ int main() { // CHECK9-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done9: @@ -1505,17 +1505,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1526,7 +1526,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1540,7 +1540,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1570,14 +1570,14 @@ int main() { // CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) @@ -1588,7 +1588,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1596,27 +1596,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP4]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1624,7 +1624,7 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // @@ -1636,7 +1636,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1666,12 +1666,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1716,14 +1716,14 @@ int main() { // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done5: @@ -1731,7 +1731,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1771,12 +1771,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP3]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -1833,14 +1833,14 @@ int main() { // CHECK10-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done9: @@ -1848,12 +1848,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -1868,14 +1868,14 @@ int main() { // CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -1893,17 +1893,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP4]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1914,7 +1914,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1928,7 +1928,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1937,17 +1937,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1955,7 +1955,7 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // @@ -1967,7 +1967,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1996,12 +1996,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2046,14 +2046,14 @@ int main() { // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done5: @@ -2061,7 +2061,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2100,12 +2100,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2162,14 +2162,14 @@ int main() { // CHECK10-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done9: @@ -2177,17 +2177,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2198,7 +2198,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2212,7 +2212,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2242,14 +2242,14 @@ int main() { // CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) @@ -2260,7 +2260,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2268,27 +2268,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP4]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2296,7 +2296,7 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // @@ -2308,7 +2308,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2338,12 +2338,12 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2386,14 +2386,14 @@ int main() { // CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done5: @@ -2401,7 +2401,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2439,12 +2439,12 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2499,14 +2499,14 @@ int main() { // CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -2514,12 +2514,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2534,14 +2534,14 @@ int main() { // CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -2559,17 +2559,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP4]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2580,7 +2580,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2594,7 +2594,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2603,17 +2603,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2621,7 +2621,7 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // @@ -2633,7 +2633,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2662,12 +2662,12 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2710,14 +2710,14 @@ int main() { // CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done5: @@ -2725,7 +2725,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2762,12 +2762,12 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2822,14 +2822,14 @@ int main() { // CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -2837,17 +2837,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2858,7 +2858,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2872,7 +2872,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2902,14 +2902,14 @@ int main() { // CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) @@ -2920,7 +2920,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2928,27 +2928,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP4]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2956,7 +2956,7 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // @@ -2968,7 +2968,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2998,12 +2998,12 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -3046,14 +3046,14 @@ int main() { // CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done5: @@ -3061,7 +3061,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3099,12 +3099,12 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -3159,14 +3159,14 @@ int main() { // CHECK12-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done7: @@ -3174,12 +3174,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // @@ -3194,14 +3194,14 @@ int main() { // CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -3219,17 +3219,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP4]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3240,7 +3240,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3254,7 +3254,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3263,17 +3263,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3281,7 +3281,7 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // @@ -3293,7 +3293,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3322,12 +3322,12 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -3370,14 +3370,14 @@ int main() { // CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done5: @@ -3385,7 +3385,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3422,12 +3422,12 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -3482,14 +3482,14 @@ int main() { // CHECK12-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done7: @@ -3497,17 +3497,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3518,7 +3518,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3532,7 +3532,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3546,3 +3546,4 @@ int main() { // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp index b820377f32a3f984482fcafbfab61fc6963ac337..074988443b4b5e5c7ff3a763d94cec744eb24419 100644 --- a/clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp @@ -76,7 +76,7 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41() #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT3]] // CHECK1: omp_offload.cont3: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -88,7 +88,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -149,7 +149,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -226,7 +226,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -287,7 +287,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -379,7 +379,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -440,7 +440,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -539,7 +539,7 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41() #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT3]] // CHECK2: omp_offload.cont3: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -551,7 +551,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -612,7 +612,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -689,7 +689,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -750,7 +750,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -842,7 +842,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -903,7 +903,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -978,3 +978,4 @@ int main() { // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) // CHECK2-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp index 601a78cc9f261293e29167b2d51eade9f88ccd4b..dec264ff9ea1c57c7ca5f8121f1ed8c0a14f765e 100644 --- a/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp @@ -37,7 +37,7 @@ int main(int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -54,7 +54,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14 -// CHECK1-SAME: (i64 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -72,7 +72,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -136,7 +136,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -425,7 +425,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init. -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -438,7 +438,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -456,7 +456,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init..2 -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -478,7 +478,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb..3 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -509,7 +509,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -523,7 +523,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -607,7 +607,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -656,7 +656,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -673,7 +673,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14 -// CHECK2-SAME: (i64 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -691,7 +691,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -755,7 +755,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1044,7 +1044,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init. -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1057,7 +1057,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1075,7 +1075,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init..2 -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1097,7 +1097,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb..3 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1128,7 +1128,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -1142,7 +1142,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1226,7 +1226,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp index 405b6c3d1e2977844dc4cad9ee0f1781049e2642..60b4685ed9b4630e279bc32f5d4eef7d855d2c93 100644 --- a/clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp @@ -790,12 +790,12 @@ int main() { // CHECK1-NEXT: store double** [[C]], double*** [[TMP3]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 // CHECK1-NEXT: store i32* [[CH]], i32** [[TMP4]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK1-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -811,7 +811,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -917,7 +917,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1026,7 +1026,7 @@ int main() { // CHECK1-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8, !llvm.access.group !14 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8, !llvm.access.group !14 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !14 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !14 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1059,7 +1059,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l159 -// CHECK1-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -1075,7 +1075,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1181,7 +1181,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1290,7 +1290,7 @@ int main() { // CHECK1-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8, !llvm.access.group !22 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8, !llvm.access.group !22 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* noundef [[REF_TMP]]), !llvm.access.group !22 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !22 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1323,7 +1323,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l201 -// CHECK1-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -1342,7 +1342,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1476,7 +1476,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1585,7 +1585,7 @@ int main() { // CHECK1-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8, !llvm.access.group !28 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_2]], %class.anon.2* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8, !llvm.access.group !28 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* noundef [[REF_TMP]]), !llvm.access.group !28 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !28 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1618,7 +1618,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l234 -// CHECK1-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -1634,7 +1634,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1740,7 +1740,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1849,7 +1849,7 @@ int main() { // CHECK1-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8, !llvm.access.group !34 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_3]], %class.anon.3* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8, !llvm.access.group !34 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* noundef [[REF_TMP]]), !llvm.access.group !34 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !34 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1882,7 +1882,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l266 -// CHECK1-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -1901,7 +1901,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2018,7 +2018,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2140,7 +2140,7 @@ int main() { // CHECK1-NEXT: store double** [[TMP2]], double*** [[TMP33]], align 8, !llvm.access.group !40 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[CLASS_ANON_4]], %class.anon.4* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store double** [[TMP3]], double*** [[TMP34]], align 8, !llvm.access.group !40 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* noundef [[REF_TMP]]), !llvm.access.group !40 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !40 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2183,7 +2183,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l299 -// CHECK1-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -2199,7 +2199,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2305,7 +2305,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2411,7 +2411,7 @@ int main() { // CHECK1-NEXT: store double** [[TMP2]], double*** [[TMP31]], align 8, !llvm.access.group !46 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store double** [[TMP3]], double*** [[TMP32]], align 8, !llvm.access.group !46 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* noundef [[REF_TMP]]), !llvm.access.group !46 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !46 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2443,7 +2443,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l328 -// CHECK1-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -2462,7 +2462,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2579,7 +2579,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2689,7 +2689,7 @@ int main() { // CHECK1-NEXT: store double** [[TMP2]], double*** [[TMP32]], align 8, !llvm.access.group !52 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store double** [[TMP3]], double*** [[TMP33]], align 8, !llvm.access.group !52 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* noundef [[REF_TMP]]), !llvm.access.group !52 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !52 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2750,12 +2750,12 @@ int main() { // CHECK2-NEXT: store double** [[C]], double*** [[TMP3]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 // CHECK2-NEXT: store i32* [[CH]], i32** [[TMP4]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK2-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -2771,7 +2771,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2877,7 +2877,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2986,7 +2986,7 @@ int main() { // CHECK2-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8, !llvm.access.group !14 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8, !llvm.access.group !14 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !14 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !14 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3019,7 +3019,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l159 -// CHECK2-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -3035,7 +3035,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3141,7 +3141,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3250,7 +3250,7 @@ int main() { // CHECK2-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8, !llvm.access.group !22 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8, !llvm.access.group !22 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* noundef [[REF_TMP]]), !llvm.access.group !22 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !22 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3283,7 +3283,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l201 -// CHECK2-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -3302,7 +3302,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3436,7 +3436,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3545,7 +3545,7 @@ int main() { // CHECK2-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8, !llvm.access.group !28 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_2]], %class.anon.2* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8, !llvm.access.group !28 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* noundef [[REF_TMP]]), !llvm.access.group !28 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !28 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3578,7 +3578,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l234 -// CHECK2-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -3594,7 +3594,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3700,7 +3700,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3809,7 +3809,7 @@ int main() { // CHECK2-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 8, !llvm.access.group !34 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_3]], %class.anon.3* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 8, !llvm.access.group !34 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* noundef [[REF_TMP]]), !llvm.access.group !34 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !34 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3842,7 +3842,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l266 -// CHECK2-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -3861,7 +3861,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3978,7 +3978,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4100,7 +4100,7 @@ int main() { // CHECK2-NEXT: store double** [[TMP2]], double*** [[TMP33]], align 8, !llvm.access.group !40 // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[CLASS_ANON_4]], %class.anon.4* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store double** [[TMP3]], double*** [[TMP34]], align 8, !llvm.access.group !40 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* noundef [[REF_TMP]]), !llvm.access.group !40 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !40 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -4143,7 +4143,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l299 -// CHECK2-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -4159,7 +4159,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4265,7 +4265,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4371,7 +4371,7 @@ int main() { // CHECK2-NEXT: store double** [[TMP2]], double*** [[TMP31]], align 8, !llvm.access.group !46 // CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store double** [[TMP3]], double*** [[TMP32]], align 8, !llvm.access.group !46 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* noundef [[REF_TMP]]), !llvm.access.group !46 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !46 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -4403,7 +4403,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l328 -// CHECK2-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -4422,7 +4422,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4539,7 +4539,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4649,7 +4649,7 @@ int main() { // CHECK2-NEXT: store double** [[TMP2]], double*** [[TMP32]], align 8, !llvm.access.group !52 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store double** [[TMP3]], double*** [[TMP33]], align 8, !llvm.access.group !52 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* noundef [[REF_TMP]]), !llvm.access.group !52 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !52 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -4710,12 +4710,12 @@ int main() { // CHECK3-NEXT: store double** [[C]], double*** [[TMP3]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 // CHECK3-NEXT: store i32* [[CH]], i32** [[TMP4]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(20) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK3-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -4730,7 +4730,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4834,7 +4834,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4938,7 +4938,7 @@ int main() { // CHECK3-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4, !llvm.access.group !15 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !15 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !15 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -4971,7 +4971,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l159 -// CHECK3-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -4986,7 +4986,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5090,7 +5090,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5194,7 +5194,7 @@ int main() { // CHECK3-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4, !llvm.access.group !23 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4, !llvm.access.group !23 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* noundef [[REF_TMP]]), !llvm.access.group !23 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !23 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -5227,7 +5227,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l201 -// CHECK3-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -5244,7 +5244,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5376,7 +5376,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5480,7 +5480,7 @@ int main() { // CHECK3-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4, !llvm.access.group !29 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_2]], %class.anon.2* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4, !llvm.access.group !29 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* noundef [[REF_TMP]]), !llvm.access.group !29 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !29 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -5513,7 +5513,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l234 -// CHECK3-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -5528,7 +5528,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5632,7 +5632,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5736,7 +5736,7 @@ int main() { // CHECK3-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4, !llvm.access.group !35 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_3]], %class.anon.3* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4, !llvm.access.group !35 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* noundef [[REF_TMP]]), !llvm.access.group !35 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !35 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -5769,7 +5769,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l266 -// CHECK3-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -5786,7 +5786,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5900,7 +5900,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6014,7 +6014,7 @@ int main() { // CHECK3-NEXT: store double** [[TMP2]], double*** [[TMP33]], align 4, !llvm.access.group !41 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[CLASS_ANON_4]], %class.anon.4* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store double** [[TMP3]], double*** [[TMP34]], align 4, !llvm.access.group !41 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* noundef [[REF_TMP]]), !llvm.access.group !41 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !41 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -6057,7 +6057,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l299 -// CHECK3-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -6072,7 +6072,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6176,7 +6176,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6277,7 +6277,7 @@ int main() { // CHECK3-NEXT: store double** [[TMP2]], double*** [[TMP31]], align 4, !llvm.access.group !47 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store double** [[TMP3]], double*** [[TMP32]], align 4, !llvm.access.group !47 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* noundef [[REF_TMP]]), !llvm.access.group !47 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !47 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -6309,7 +6309,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l328 -// CHECK3-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -6326,7 +6326,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6440,7 +6440,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6544,7 +6544,7 @@ int main() { // CHECK3-NEXT: store double** [[TMP2]], double*** [[TMP32]], align 4, !llvm.access.group !53 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store double** [[TMP3]], double*** [[TMP33]], align 4, !llvm.access.group !53 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* noundef [[REF_TMP]]), !llvm.access.group !53 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !53 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -6605,12 +6605,12 @@ int main() { // CHECK4-NEXT: store double** [[C]], double*** [[TMP3]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 // CHECK4-NEXT: store i32* [[CH]], i32** [[TMP4]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(20) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK4-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -6625,7 +6625,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6729,7 +6729,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6833,7 +6833,7 @@ int main() { // CHECK4-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4, !llvm.access.group !15 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !15 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !15 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -6866,7 +6866,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l159 -// CHECK4-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -6881,7 +6881,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6985,7 +6985,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7089,7 +7089,7 @@ int main() { // CHECK4-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4, !llvm.access.group !23 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4, !llvm.access.group !23 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* noundef [[REF_TMP]]), !llvm.access.group !23 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE0_clEv"(%class.anon.1* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !23 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -7122,7 +7122,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l201 -// CHECK4-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -7139,7 +7139,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7271,7 +7271,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7375,7 +7375,7 @@ int main() { // CHECK4-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4, !llvm.access.group !29 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_2]], %class.anon.2* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4, !llvm.access.group !29 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* noundef [[REF_TMP]]), !llvm.access.group !29 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE1_clEv"(%class.anon.2* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !29 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -7408,7 +7408,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l234 -// CHECK4-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -7423,7 +7423,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7527,7 +7527,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7631,7 +7631,7 @@ int main() { // CHECK4-NEXT: store double** [[TMP2]], double*** [[TMP30]], align 4, !llvm.access.group !35 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[CLASS_ANON_3]], %class.anon.3* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store double** [[TMP3]], double*** [[TMP31]], align 4, !llvm.access.group !35 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* noundef [[REF_TMP]]), !llvm.access.group !35 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE2_clEv"(%class.anon.3* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !35 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -7664,7 +7664,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l266 -// CHECK4-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -7681,7 +7681,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7795,7 +7795,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7909,7 +7909,7 @@ int main() { // CHECK4-NEXT: store double** [[TMP2]], double*** [[TMP33]], align 4, !llvm.access.group !41 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[CLASS_ANON_4]], %class.anon.4* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store double** [[TMP3]], double*** [[TMP34]], align 4, !llvm.access.group !41 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* noundef [[REF_TMP]]), !llvm.access.group !41 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE3_clEv"(%class.anon.4* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !41 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -7952,7 +7952,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l299 -// CHECK4-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -7967,7 +7967,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8071,7 +8071,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8172,7 +8172,7 @@ int main() { // CHECK4-NEXT: store double** [[TMP2]], double*** [[TMP31]], align 4, !llvm.access.group !47 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store double** [[TMP3]], double*** [[TMP32]], align 4, !llvm.access.group !47 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* noundef [[REF_TMP]]), !llvm.access.group !47 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !47 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -8204,7 +8204,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l328 -// CHECK4-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -8221,7 +8221,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8335,7 +8335,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8439,7 +8439,7 @@ int main() { // CHECK4-NEXT: store double** [[TMP2]], double*** [[TMP32]], align 4, !llvm.access.group !53 // CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store double** [[TMP3]], double*** [[TMP33]], align 4, !llvm.access.group !53 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* noundef [[REF_TMP]]), !llvm.access.group !53 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !53 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -8500,7 +8500,7 @@ int main() { // CHECK5-NEXT: store double** [[C]], double*** [[TMP3]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 // CHECK5-NEXT: store i32* [[CH]], i32** [[TMP4]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // @@ -8527,7 +8527,7 @@ int main() { // CHECK6-NEXT: store double** [[C]], double*** [[TMP3]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 // CHECK6-NEXT: store i32* [[CH]], i32** [[TMP4]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // @@ -8554,7 +8554,7 @@ int main() { // CHECK7-NEXT: store double** [[C]], double*** [[TMP3]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 // CHECK7-NEXT: store i32* [[CH]], i32** [[TMP4]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(20) [[REF_TMP]]) // CHECK7-NEXT: ret i32 0 // // @@ -8581,7 +8581,7 @@ int main() { // CHECK8-NEXT: store double** [[C]], double*** [[TMP3]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 4 // CHECK8-NEXT: store i32* [[CH]], i32** [[TMP4]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(20) [[REF_TMP]]) // CHECK8-NEXT: ret i32 0 // // @@ -9098,12 +9098,12 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l561(i64 [[TMP213]], i64 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT91]] // CHECK9: omp_offload.cont91: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: ret i32 [[CALL]] // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l368 -// CHECK9-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -9119,7 +9119,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9225,7 +9225,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9357,7 +9357,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l407 -// CHECK9-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -9373,7 +9373,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9479,7 +9479,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9611,7 +9611,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l446 -// CHECK9-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -9630,7 +9630,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9764,7 +9764,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9896,7 +9896,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l477 -// CHECK9-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -9912,7 +9912,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10018,7 +10018,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10150,7 +10150,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l505 -// CHECK9-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -10169,7 +10169,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10286,7 +10286,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10441,7 +10441,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l535 -// CHECK9-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -10457,7 +10457,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10563,7 +10563,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10691,7 +10691,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l561 -// CHECK9-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -10710,7 +10710,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10827,7 +10827,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11473,7 +11473,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -11489,7 +11489,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11595,7 +11595,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11727,7 +11727,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -11743,7 +11743,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11849,7 +11849,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..31 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11981,7 +11981,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l58 -// CHECK9-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -12000,7 +12000,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..34 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12134,7 +12134,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..35 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12266,7 +12266,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l66 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -12282,7 +12282,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..38 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12388,7 +12388,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..39 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12520,7 +12520,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l74 -// CHECK9-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -12539,7 +12539,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..42 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12656,7 +12656,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..43 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12811,7 +12811,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l82 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -12827,7 +12827,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..46 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12933,7 +12933,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..47 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13061,7 +13061,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l90 -// CHECK9-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -13080,7 +13080,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..50 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13197,7 +13197,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..51 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13848,12 +13848,12 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l561(i64 [[TMP213]], i64 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT91]] // CHECK10: omp_offload.cont91: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: ret i32 [[CALL]] // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l368 -// CHECK10-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -13869,7 +13869,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13975,7 +13975,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14107,7 +14107,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l407 -// CHECK10-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -14123,7 +14123,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14229,7 +14229,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14361,7 +14361,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l446 -// CHECK10-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -14380,7 +14380,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14514,7 +14514,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14646,7 +14646,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l477 -// CHECK10-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -14662,7 +14662,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14768,7 +14768,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14900,7 +14900,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l505 -// CHECK10-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -14919,7 +14919,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15036,7 +15036,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15191,7 +15191,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l535 -// CHECK10-SAME: (i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca double*, align 8 @@ -15207,7 +15207,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15313,7 +15313,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15441,7 +15441,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l561 -// CHECK10-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -15460,7 +15460,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15577,7 +15577,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], double** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 8 dereferenceable(8) [[A:%.*]], double** nonnull align 8 dereferenceable(8) [[B:%.*]], double** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16223,7 +16223,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -16239,7 +16239,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16345,7 +16345,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16477,7 +16477,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -16493,7 +16493,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16599,7 +16599,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..31 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16731,7 +16731,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l58 -// CHECK10-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -16750,7 +16750,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..34 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16884,7 +16884,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..35 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17016,7 +17016,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l66 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -17032,7 +17032,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..38 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17138,7 +17138,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..39 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17270,7 +17270,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l74 -// CHECK10-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -17289,7 +17289,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..42 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17406,7 +17406,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..43 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17561,7 +17561,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l82 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -17577,7 +17577,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..46 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17683,7 +17683,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..47 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17811,7 +17811,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l90 -// CHECK10-SAME: (i64 noundef [[CH:%.*]], i64 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[CH:%.*]], i64 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[CH_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -17830,7 +17830,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..50 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17947,7 +17947,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..51 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18588,12 +18588,12 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l561(i32 [[TMP213]], i32 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT82]] // CHECK11: omp_offload.cont82: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: ret i32 [[CALL]] // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l368 -// CHECK11-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -18608,7 +18608,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18712,7 +18712,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18839,7 +18839,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l407 -// CHECK11-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -18854,7 +18854,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18958,7 +18958,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19085,7 +19085,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l446 -// CHECK11-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -19102,7 +19102,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19234,7 +19234,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19361,7 +19361,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l477 -// CHECK11-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -19376,7 +19376,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19480,7 +19480,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19607,7 +19607,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l505 -// CHECK11-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -19624,7 +19624,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19738,7 +19738,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19885,7 +19885,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l535 -// CHECK11-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -19900,7 +19900,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20004,7 +20004,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20127,7 +20127,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l561 -// CHECK11-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -20144,7 +20144,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20258,7 +20258,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20888,7 +20888,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -20903,7 +20903,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21007,7 +21007,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21134,7 +21134,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -21149,7 +21149,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21253,7 +21253,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..31 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21380,7 +21380,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l58 -// CHECK11-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -21397,7 +21397,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..34 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21529,7 +21529,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..35 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21656,7 +21656,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l66 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -21671,7 +21671,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..38 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21775,7 +21775,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..39 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21902,7 +21902,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l74 -// CHECK11-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -21919,7 +21919,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..42 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22033,7 +22033,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..43 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22180,7 +22180,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l82 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -22195,7 +22195,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..46 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22299,7 +22299,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..47 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22422,7 +22422,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l90 -// CHECK11-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -22439,7 +22439,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..50 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22553,7 +22553,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..51 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23188,12 +23188,12 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l561(i32 [[TMP213]], i32 [[TMP215]], double* [[TMP216]], double* [[TMP217]], double* [[TMP218]]) #[[ATTR2]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT82]] // CHECK12: omp_offload.cont82: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: ret i32 [[CALL]] // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l368 -// CHECK12-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -23208,7 +23208,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23312,7 +23312,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23439,7 +23439,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l407 -// CHECK12-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -23454,7 +23454,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23558,7 +23558,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23685,7 +23685,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l446 -// CHECK12-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -23702,7 +23702,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23834,7 +23834,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23961,7 +23961,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l477 -// CHECK12-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -23976,7 +23976,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24080,7 +24080,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24207,7 +24207,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l505 -// CHECK12-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -24224,7 +24224,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24338,7 +24338,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24485,7 +24485,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l535 -// CHECK12-SAME: (i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca double*, align 4 @@ -24500,7 +24500,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24604,7 +24604,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24727,7 +24727,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l561 -// CHECK12-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], double* noundef [[A:%.*]], double* noundef [[B:%.*]], double* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], double* [[A:%.*]], double* [[B:%.*]], double* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -24744,7 +24744,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24858,7 +24858,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], double** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], double** nonnull align 4 dereferenceable(4) [[A:%.*]], double** nonnull align 4 dereferenceable(4) [[B:%.*]], double** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25488,7 +25488,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l42 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -25503,7 +25503,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25607,7 +25607,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25734,7 +25734,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -25749,7 +25749,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25853,7 +25853,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..31 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25980,7 +25980,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l58 -// CHECK12-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -25997,7 +25997,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..34 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26129,7 +26129,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..35 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26256,7 +26256,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l66 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -26271,7 +26271,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..38 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26375,7 +26375,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..39 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26502,7 +26502,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l74 -// CHECK12-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -26519,7 +26519,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..42 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26633,7 +26633,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..43 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26780,7 +26780,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l82 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -26795,7 +26795,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..46 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26899,7 +26899,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..47 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27022,7 +27022,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l90 -// CHECK12-SAME: (i32 noundef [[CH:%.*]], i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], i32* noundef [[B:%.*]], i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32 [[CH:%.*]], i32 [[N:%.*]], i32* [[A:%.*]], i32* [[B:%.*]], i32* [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[CH_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -27039,7 +27039,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..50 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[CH:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27153,7 +27153,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..51 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32** nonnull align 4 dereferenceable(4) [[A:%.*]], i32** nonnull align 4 dereferenceable(4) [[B:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27786,7 +27786,7 @@ int main() { // CHECK13-NEXT: store i32 [[ADD219]], i32* [[I199]], align 4 // CHECK13-NEXT: br label [[SIMD_IF_END220]] // CHECK13: simd.if.end220: -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: ret i32 [[CALL]] // // @@ -28793,7 +28793,7 @@ int main() { // CHECK14-NEXT: store i32 [[ADD219]], i32* [[I199]], align 4 // CHECK14-NEXT: br label [[SIMD_IF_END220]] // CHECK14: simd.if.end220: -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK14-NEXT: ret i32 [[CALL]] // // @@ -29779,7 +29779,7 @@ int main() { // CHECK15-NEXT: store i32 [[ADD199]], i32* [[I182]], align 4 // CHECK15-NEXT: br label [[SIMD_IF_END200]] // CHECK15: simd.if.end200: -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK15-NEXT: ret i32 [[CALL]] // // @@ -30744,7 +30744,7 @@ int main() { // CHECK16-NEXT: store i32 [[ADD199]], i32* [[I182]], align 4 // CHECK16-NEXT: br label [[SIMD_IF_END200]] // CHECK16: simd.if.end200: -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK16-NEXT: ret i32 [[CALL]] // // diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp index 9f4841755475da64557396d38169c351e5ccda15..ba48754a6b48303d6fed0b36e87f01f3792af0e1 100644 --- a/clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp @@ -276,12 +276,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -303,7 +303,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -374,40 +374,40 @@ int main() { // CHECK1-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK1-NEXT: [[TMP21:%.*]] = load double, double* [[G3]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP21:%.*]] = load double, double* [[G3]], align 8 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[G_CASTED]] to double* -// CHECK1-NEXT: store double [[TMP21]], double* [[CONV]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP22:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP23:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP24:%.*]] = load volatile double, double* [[TMP23]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: store double [[TMP21]], double* [[CONV]], align 8 +// CHECK1-NEXT: [[TMP22:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP24:%.*]] = load volatile double, double* [[TMP23]], align 8 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[G1_CASTED]] to double* -// CHECK1-NEXT: store double [[TMP24]], double* [[CONV9]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[SVAR6]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: store double [[TMP24]], double* [[CONV9]], align 8 +// CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[SVAR6]], align 4 // CHECK1-NEXT: [[CONV10:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK1-NEXT: store i32 [[TMP26]], i32* [[CONV10]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP27:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP28:%.*]] = load float, float* [[SFVAR7]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: store i32 [[TMP26]], i32* [[CONV10]], align 4 +// CHECK1-NEXT: [[TMP27:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK1-NEXT: [[TMP28:%.*]] = load float, float* [[SFVAR7]], align 4 // CHECK1-NEXT: [[CONV11:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float* -// CHECK1-NEXT: store float [[TMP28]], float* [[CONV11]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP29:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP25]], i64 [[TMP27]], i64 [[TMP29]]), !llvm.access.group !4 +// CHECK1-NEXT: store float [[TMP28]], float* [[CONV11]], align 4 +// CHECK1-NEXT: [[TMP29:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP25]], i64 [[TMP27]], i64 [[TMP29]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -423,7 +423,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -483,38 +483,38 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: store double 1.000000e+00, double* [[CONV]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store i32 3, i32* [[CONV2]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store float 4.000000e+00, float* [[CONV3]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: store double 1.000000e+00, double* [[CONV]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8 +// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8 +// CHECK1-NEXT: store i32 3, i32* [[CONV2]], align 8 +// CHECK1-NEXT: store float 4.000000e+00, float* [[CONV3]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK1-NEXT: store double* [[CONV]], double** [[TMP11]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: store double* [[CONV]], double** [[TMP11]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP13:%.*]] = load double*, double** [[TMP]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP13:%.*]] = load double*, double** [[TMP]], align 8 +// CHECK1-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK1-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK1-NEXT: store float* [[CONV3]], float** [[TMP15]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK1-NEXT: store float* [[CONV3]], float** [[TMP15]], align 8 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -550,12 +550,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK2-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -577,7 +577,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -648,40 +648,40 @@ int main() { // CHECK2-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK2-NEXT: [[TMP21:%.*]] = load double, double* [[G3]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP21:%.*]] = load double, double* [[G3]], align 8 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[G_CASTED]] to double* -// CHECK2-NEXT: store double [[TMP21]], double* [[CONV]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP22:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP23:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP24:%.*]] = load volatile double, double* [[TMP23]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: store double [[TMP21]], double* [[CONV]], align 8 +// CHECK2-NEXT: [[TMP22:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK2-NEXT: [[TMP23:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK2-NEXT: [[TMP24:%.*]] = load volatile double, double* [[TMP23]], align 8 // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[G1_CASTED]] to double* -// CHECK2-NEXT: store double [[TMP24]], double* [[CONV9]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP25:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[SVAR6]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: store double [[TMP24]], double* [[CONV9]], align 8 +// CHECK2-NEXT: [[TMP25:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[SVAR6]], align 4 // CHECK2-NEXT: [[CONV10:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK2-NEXT: store i32 [[TMP26]], i32* [[CONV10]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP27:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP28:%.*]] = load float, float* [[SFVAR7]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: store i32 [[TMP26]], i32* [[CONV10]], align 4 +// CHECK2-NEXT: [[TMP27:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK2-NEXT: [[TMP28:%.*]] = load float, float* [[SFVAR7]], align 4 // CHECK2-NEXT: [[CONV11:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float* -// CHECK2-NEXT: store float [[TMP28]], float* [[CONV11]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP29:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP25]], i64 [[TMP27]], i64 [[TMP29]]), !llvm.access.group !4 +// CHECK2-NEXT: store float [[TMP28]], float* [[CONV11]], align 4 +// CHECK2-NEXT: [[TMP29:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP25]], i64 [[TMP27]], i64 [[TMP29]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -697,7 +697,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -757,38 +757,38 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: store double 1.000000e+00, double* [[CONV]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store i32 3, i32* [[CONV2]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store float 4.000000e+00, float* [[CONV3]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: store double 1.000000e+00, double* [[CONV]], align 8 +// CHECK2-NEXT: [[TMP10:%.*]] = load double*, double** [[TMP]], align 8 +// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8 +// CHECK2-NEXT: store i32 3, i32* [[CONV2]], align 8 +// CHECK2-NEXT: store float 4.000000e+00, float* [[CONV3]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK2-NEXT: store double* [[CONV]], double** [[TMP11]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: store double* [[CONV]], double** [[TMP11]], align 8 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP13:%.*]] = load double*, double** [[TMP]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP13:%.*]] = load double*, double** [[TMP]], align 8 +// CHECK2-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK2-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK2-NEXT: store float* [[CONV3]], float** [[TMP15]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK2-NEXT: store float* [[CONV3]], float** [[TMP15]], align 8 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -824,12 +824,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -859,7 +859,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -929,33 +929,33 @@ int main() { // CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 4 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[G1_CASTED]] to double* -// CHECK3-NEXT: store double [[TMP20]], double* [[CONV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[G1_CASTED]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[SVAR6]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store i32 [[TMP22]], i32* [[SVAR_CASTED]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR7]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store double [[TMP20]], double* [[CONV]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[G1_CASTED]], align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[SVAR6]], align 4 +// CHECK3-NEXT: store i32 [[TMP22]], i32* [[SVAR_CASTED]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK3-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR7]], align 4 // CHECK3-NEXT: [[CONV9:%.*]] = bitcast i32* [[SFVAR_CASTED]] to float* -// CHECK3-NEXT: store float [[TMP24]], float* [[CONV9]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[SFVAR_CASTED]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], double* [[G3]], i32 [[TMP21]], i32 [[TMP23]], i32 [[TMP25]]), !llvm.access.group !5 +// CHECK3-NEXT: store float [[TMP24]], float* [[CONV9]], align 4 +// CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[SFVAR_CASTED]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], double* [[G3]], i32 [[TMP21]], i32 [[TMP23]], i32 [[TMP25]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -971,7 +971,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], i32 noundef [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], i32 [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1031,38 +1031,38 @@ int main() { // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP12:%.*]] = load double*, double** [[TMP]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP12]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store i32 3, i32* [[SVAR_ADDR]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store float 4.000000e+00, float* [[CONV1]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: store double 1.000000e+00, double* [[G3]], align 8 +// CHECK3-NEXT: [[TMP12:%.*]] = load double*, double** [[TMP]], align 4 +// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP12]], align 4 +// CHECK3-NEXT: store i32 3, i32* [[SVAR_ADDR]], align 4 +// CHECK3-NEXT: store float 4.000000e+00, float* [[CONV1]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK3-NEXT: store double* [[G3]], double** [[TMP13]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store double* [[G3]], double** [[TMP13]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP15:%.*]] = load double*, double** [[TMP]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store double* [[TMP15]], double** [[TMP14]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP15:%.*]] = load double*, double** [[TMP]], align 4 +// CHECK3-NEXT: store double* [[TMP15]], double** [[TMP14]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK3-NEXT: store i32* [[SVAR_ADDR]], i32** [[TMP16]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32* [[SVAR_ADDR]], i32** [[TMP16]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK3-NEXT: store float* [[CONV1]], float** [[TMP17]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !9 +// CHECK3-NEXT: store float* [[CONV1]], float** [[TMP17]], align 4 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1098,12 +1098,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -1133,7 +1133,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1203,33 +1203,33 @@ int main() { // CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 4 +// CHECK4-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 4 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[G1_CASTED]] to double* -// CHECK4-NEXT: store double [[TMP20]], double* [[CONV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[G1_CASTED]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[SVAR6]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store i32 [[TMP22]], i32* [[SVAR_CASTED]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR7]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store double [[TMP20]], double* [[CONV]], align 4 +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[G1_CASTED]], align 4 +// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[SVAR6]], align 4 +// CHECK4-NEXT: store i32 [[TMP22]], i32* [[SVAR_CASTED]], align 4 +// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK4-NEXT: [[TMP24:%.*]] = load float, float* [[SFVAR7]], align 4 // CHECK4-NEXT: [[CONV9:%.*]] = bitcast i32* [[SFVAR_CASTED]] to float* -// CHECK4-NEXT: store float [[TMP24]], float* [[CONV9]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[SFVAR_CASTED]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], double* [[G3]], i32 [[TMP21]], i32 [[TMP23]], i32 [[TMP25]]), !llvm.access.group !5 +// CHECK4-NEXT: store float [[TMP24]], float* [[CONV9]], align 4 +// CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[SFVAR_CASTED]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], double* [[G3]], i32 [[TMP21]], i32 [[TMP23]], i32 [[TMP25]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1245,7 +1245,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], i32 noundef [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], i32 [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1305,38 +1305,38 @@ int main() { // CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK4-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP12:%.*]] = load double*, double** [[TMP]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP12]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store i32 3, i32* [[SVAR_ADDR]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store float 4.000000e+00, float* [[CONV1]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: store double 1.000000e+00, double* [[G3]], align 8 +// CHECK4-NEXT: [[TMP12:%.*]] = load double*, double** [[TMP]], align 4 +// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP12]], align 4 +// CHECK4-NEXT: store i32 3, i32* [[SVAR_ADDR]], align 4 +// CHECK4-NEXT: store float 4.000000e+00, float* [[CONV1]], align 4 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK4-NEXT: store double* [[G3]], double** [[TMP13]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store double* [[G3]], double** [[TMP13]], align 4 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP15:%.*]] = load double*, double** [[TMP]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store double* [[TMP15]], double** [[TMP14]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP15:%.*]] = load double*, double** [[TMP]], align 4 +// CHECK4-NEXT: store double* [[TMP15]], double** [[TMP14]], align 4 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK4-NEXT: store i32* [[SVAR_ADDR]], i32** [[TMP16]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32* [[SVAR_ADDR]], i32** [[TMP16]], align 4 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK4-NEXT: store float* [[CONV1]], float** [[TMP17]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !9 +// CHECK4-NEXT: store float* [[CONV1]], float** [[TMP17]], align 4 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], 1 -// CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1372,7 +1372,7 @@ int main() { // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // @@ -1390,7 +1390,7 @@ int main() { // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // @@ -1408,7 +1408,7 @@ int main() { // CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK7-NEXT: ret i32 0 // // @@ -1432,14 +1432,14 @@ int main() { // CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK8-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK8-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1504,7 +1504,7 @@ int main() { // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK8: omp_offload.cont: -// CHECK8-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1512,27 +1512,27 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done3: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP39]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1540,12 +1540,12 @@ int main() { // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138 -// CHECK8-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK8-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1570,7 +1570,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1661,34 +1661,34 @@ int main() { // CHECK8-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK8-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] // CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK8: omp.inner.for.cond.cleanup: // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK8-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64 -// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK8-NEXT: [[TMP27:%.*]] = zext i32 [[TMP26]] to i64 -// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !5 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK8-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 4, !llvm.access.group !5 -// CHECK8-NEXT: [[TMP29:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK8-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8, !llvm.access.group !5 -// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[SVAR9]], align 4, !llvm.access.group !5 +// CHECK8-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 4 +// CHECK8-NEXT: [[TMP29:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK8-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8 +// CHECK8-NEXT: [[TMP31:%.*]] = load i32, i32* [[SVAR9]], align 4 // CHECK8-NEXT: [[CONV11:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK8-NEXT: store i32 [[TMP31]], i32* [[CONV11]], align 4, !llvm.access.group !5 -// CHECK8-NEXT: [[TMP32:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP25]], i64 [[TMP27]], [2 x i32]* [[VEC4]], i64 [[TMP29]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP30]], i64 [[TMP32]]), !llvm.access.group !5 +// CHECK8-NEXT: store i32 [[TMP31]], i32* [[CONV11]], align 4 +// CHECK8-NEXT: [[TMP32:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP25]], i64 [[TMP27]], [2 x i32]* [[VEC4]], i64 [[TMP29]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP30]], i64 [[TMP32]]) // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK8-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK8: omp.loop.exit: @@ -1702,14 +1702,14 @@ int main() { // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 // CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK8: .omp.final.done: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done13: @@ -1717,7 +1717,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1807,37 +1807,37 @@ int main() { // CHECK8-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] // CHECK8-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK8: omp.inner.for.cond.cleanup: // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 -// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]] -// CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8, !llvm.access.group !9 -// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 // CHECK8-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64 // CHECK8-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i64 0, i64 [[IDXPROM11]] // CHECK8-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* // CHECK8-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[TMP24]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false), !llvm.access.group !9 +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK8-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK8-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK8: omp.loop.exit: @@ -1851,14 +1851,14 @@ int main() { // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 // CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK8: .omp.final.done: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR8]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 // CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP33]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done15: @@ -1866,12 +1866,12 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // @@ -1890,14 +1890,14 @@ int main() { // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1957,17 +1957,17 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP32]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1978,7 +1978,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1992,7 +1992,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2001,17 +2001,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2019,12 +2019,12 @@ int main() { // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 -// CHECK8-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2046,7 +2046,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2130,30 +2130,30 @@ int main() { // CHECK8-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK8-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] // CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK8: omp.inner.for.cond.cleanup: // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK8-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 -// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK8-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64 -// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK8-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK8-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4, !llvm.access.group !14 -// CHECK8-NEXT: [[TMP27:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14 -// CHECK8-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !14 -// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP23]], i64 [[TMP25]], [2 x i32]* [[VEC4]], i64 [[TMP27]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP28]]), !llvm.access.group !14 +// CHECK8-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4 +// CHECK8-NEXT: [[TMP27:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK8-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP23]], i64 [[TMP25]], [2 x i32]* [[VEC4]], i64 [[TMP27]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP28]]) // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK8: omp.loop.exit: @@ -2167,14 +2167,14 @@ int main() { // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 // CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK8: .omp.final.done: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done11: @@ -2182,7 +2182,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2269,37 +2269,37 @@ int main() { // CHECK8-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] // CHECK8-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK8: omp.inner.for.cond.cleanup: // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17 -// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK8-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !17 -// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK8-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 +// CHECK8-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 // CHECK8-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64 // CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK8-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* // CHECK8-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false), !llvm.access.group !17 +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK8-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK8-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK8-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK8: omp.loop.exit: @@ -2313,14 +2313,14 @@ int main() { // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 // CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK8: .omp.final.done: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done14: @@ -2328,17 +2328,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2349,7 +2349,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2363,7 +2363,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2398,14 +2398,14 @@ int main() { // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -2470,7 +2470,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -2478,27 +2478,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP39]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2506,12 +2506,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2536,7 +2536,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2627,34 +2627,34 @@ int main() { // CHECK9-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP27:%.*]] = zext i32 [[TMP26]] to i64 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP29:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[SVAR9]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: store i32 [[TMP28]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP29:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK9-NEXT: [[TMP30:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8 +// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[SVAR9]], align 4 // CHECK9-NEXT: [[CONV11:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP31]], i32* [[CONV11]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP32:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP25]], i64 [[TMP27]], [2 x i32]* [[VEC4]], i64 [[TMP29]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP30]], i64 [[TMP32]]), !llvm.access.group !5 +// CHECK9-NEXT: store i32 [[TMP31]], i32* [[CONV11]], align 4 +// CHECK9-NEXT: [[TMP32:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP25]], i64 [[TMP27]], [2 x i32]* [[VEC4]], i64 [[TMP29]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP30]], i64 [[TMP32]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -2668,14 +2668,14 @@ int main() { // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done13: @@ -2683,7 +2683,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2773,37 +2773,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8 +// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP25]] to i64 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i64 0, i64 [[IDXPROM11]] // CHECK9-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* // CHECK9-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[TMP24]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false), !llvm.access.group !9 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -2817,14 +2817,14 @@ int main() { // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR8]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP33]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -2832,12 +2832,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -2856,14 +2856,14 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -2923,17 +2923,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP32]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2944,7 +2944,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2958,7 +2958,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2967,17 +2967,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2985,12 +2985,12 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -3012,7 +3012,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3096,30 +3096,30 @@ int main() { // CHECK9-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] // CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: [[TMP27:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14 -// CHECK9-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !14 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP23]], i64 [[TMP25]], [2 x i32]* [[VEC4]], i64 [[TMP27]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP28]]), !llvm.access.group !14 +// CHECK9-NEXT: store i32 [[TMP26]], i32* [[CONV]], align 4 +// CHECK9-NEXT: [[TMP27:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK9-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP23]], i64 [[TMP25]], [2 x i32]* [[VEC4]], i64 [[TMP27]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP28]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3133,14 +3133,14 @@ int main() { // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done11: @@ -3148,7 +3148,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3235,37 +3235,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] // CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 +// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP25]] to i64 // CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* // CHECK9-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false), !llvm.access.group !17 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3279,14 +3279,14 @@ int main() { // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done14: @@ -3294,17 +3294,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3315,7 +3315,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3329,7 +3329,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3364,14 +3364,14 @@ int main() { // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -3434,7 +3434,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -3442,27 +3442,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP39]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3470,12 +3470,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138 -// CHECK10-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3498,7 +3498,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3589,30 +3589,30 @@ int main() { // CHECK10-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] // CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: store i32 [[TMP26]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: [[TMP28:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[SVAR9]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: store i32 [[TMP29]], i32* [[SVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP24]], i32 [[TMP25]], [2 x i32]* [[VEC4]], i32 [[TMP27]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP28]], i32 [[TMP30]]), !llvm.access.group !6 +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK10-NEXT: store i32 [[TMP26]], i32* [[T_VAR_CASTED]], align 4 +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK10-NEXT: [[TMP28:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[SVAR9]], align 4 +// CHECK10-NEXT: store i32 [[TMP29]], i32* [[SVAR_CASTED]], align 4 +// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP24]], i32 [[TMP25]], [2 x i32]* [[VEC4]], i32 [[TMP27]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP28]], i32 [[TMP30]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -3626,14 +3626,14 @@ int main() { // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done12: @@ -3641,7 +3641,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3727,35 +3727,35 @@ int main() { // CHECK10-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP23]] -// CHECK10-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK10-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 [[TMP25]] // CHECK10-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[ARRAYIDX8]] to i8* // CHECK10-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[TMP24]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false), !llvm.access.group !10 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -3769,14 +3769,14 @@ int main() { // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP33]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done11: @@ -3784,12 +3784,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -3808,14 +3808,14 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3874,17 +3874,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP32]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3895,7 +3895,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3909,7 +3909,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3918,17 +3918,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3936,12 +3936,12 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 -// CHECK10-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3962,7 +3962,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4046,27 +4046,27 @@ int main() { // CHECK10-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] // CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: store i32 [[TMP24]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: [[TMP26:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP23]], [2 x i32]* [[VEC4]], i32 [[TMP25]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP26]]), !llvm.access.group !15 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK10-NEXT: store i32 [[TMP24]], i32* [[T_VAR_CASTED]], align 4 +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK10-NEXT: [[TMP26:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP23]], [2 x i32]* [[VEC4]], i32 [[TMP25]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP26]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -4080,14 +4080,14 @@ int main() { // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done11: @@ -4095,7 +4095,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4179,35 +4179,35 @@ int main() { // CHECK10-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP23]] -// CHECK10-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK10-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP25]] // CHECK10-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* // CHECK10-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false), !llvm.access.group !18 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -4221,14 +4221,14 @@ int main() { // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done11: @@ -4236,17 +4236,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4257,7 +4257,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4271,7 +4271,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4306,14 +4306,14 @@ int main() { // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -4376,7 +4376,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -4384,27 +4384,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP39]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4412,12 +4412,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l138 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -4440,7 +4440,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4531,30 +4531,30 @@ int main() { // CHECK11-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: store i32 [[TMP26]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP28:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[SVAR9]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: store i32 [[TMP29]], i32* [[SVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP24]], i32 [[TMP25]], [2 x i32]* [[VEC4]], i32 [[TMP27]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP28]], i32 [[TMP30]]), !llvm.access.group !6 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK11-NEXT: store i32 [[TMP26]], i32* [[T_VAR_CASTED]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4 +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[SVAR9]], align 4 +// CHECK11-NEXT: store i32 [[TMP29]], i32* [[SVAR_CASTED]], align 4 +// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP24]], i32 [[TMP25]], [2 x i32]* [[VEC4]], i32 [[TMP27]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP28]], i32 [[TMP30]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -4568,14 +4568,14 @@ int main() { // CHECK11-NEXT: store i32 2, i32* [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done12: @@ -4583,7 +4583,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4669,35 +4669,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] // CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP23]] -// CHECK11-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 [[TMP25]] // CHECK11-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[ARRAYIDX8]] to i8* // CHECK11-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[TMP24]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false), !llvm.access.group !10 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -4711,14 +4711,14 @@ int main() { // CHECK11-NEXT: store i32 2, i32* [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP33]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done11: @@ -4726,12 +4726,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -4750,14 +4750,14 @@ int main() { // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4816,17 +4816,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP32]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4837,7 +4837,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4851,7 +4851,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4860,17 +4860,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4878,12 +4878,12 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -4904,7 +4904,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4988,27 +4988,27 @@ int main() { // CHECK11-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] // CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: store i32 [[TMP24]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP26:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP23]], [2 x i32]* [[VEC4]], i32 [[TMP25]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP26]]), !llvm.access.group !15 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK11-NEXT: store i32 [[TMP24]], i32* [[T_VAR_CASTED]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP23]], [2 x i32]* [[VEC4]], i32 [[TMP25]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP26]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -5022,14 +5022,14 @@ int main() { // CHECK11-NEXT: store i32 2, i32* [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done11: @@ -5037,7 +5037,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5121,35 +5121,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] // CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP23]] -// CHECK11-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP25]] // CHECK11-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* // CHECK11-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false), !llvm.access.group !18 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -5163,14 +5163,14 @@ int main() { // CHECK11-NEXT: store i32 2, i32* [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done11: @@ -5178,17 +5178,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5199,7 +5199,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5213,7 +5213,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5249,14 +5249,14 @@ int main() { // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -5302,7 +5302,7 @@ int main() { // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -5310,27 +5310,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done7: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP17]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5338,7 +5338,7 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // @@ -5359,14 +5359,14 @@ int main() { // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -5419,27 +5419,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done7: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP17]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5450,7 +5450,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5459,7 +5459,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5473,17 +5473,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5491,22 +5491,22 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5517,7 +5517,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5531,7 +5531,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5560,14 +5560,14 @@ int main() { // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -5613,7 +5613,7 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -5621,27 +5621,27 @@ int main() { // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done7: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP17]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5649,7 +5649,7 @@ int main() { // CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK13-NEXT: ret void // // @@ -5670,14 +5670,14 @@ int main() { // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -5730,27 +5730,27 @@ int main() { // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done7: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP17]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5761,7 +5761,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5770,7 +5770,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5784,17 +5784,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5802,22 +5802,22 @@ int main() { // CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5828,7 +5828,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5842,7 +5842,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5871,14 +5871,14 @@ int main() { // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK14-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -5922,7 +5922,7 @@ int main() { // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK14-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -5930,27 +5930,27 @@ int main() { // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done6: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP17]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5958,7 +5958,7 @@ int main() { // CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK14-NEXT: ret void // // @@ -5979,14 +5979,14 @@ int main() { // CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -6037,27 +6037,27 @@ int main() { // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done6: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP17]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -6068,7 +6068,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -6077,7 +6077,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6091,17 +6091,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6109,22 +6109,22 @@ int main() { // CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -6135,7 +6135,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6149,7 +6149,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -6178,14 +6178,14 @@ int main() { // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -6229,7 +6229,7 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -6237,27 +6237,27 @@ int main() { // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done6: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP17]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6265,7 +6265,7 @@ int main() { // CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK15-NEXT: ret void // // @@ -6286,14 +6286,14 @@ int main() { // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -6344,27 +6344,27 @@ int main() { // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done6: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP17]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -6375,7 +6375,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -6384,7 +6384,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6398,17 +6398,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6416,22 +6416,22 @@ int main() { // CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -6442,7 +6442,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6456,7 +6456,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp index c72869cb4a880146e4c5cb432fd2b04efb4fce67..67a1d863a6fefaf7f2ef9291d966b3f38814de98 100644 --- a/clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp @@ -149,7 +149,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -184,22 +184,22 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !11 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -216,7 +216,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -261,22 +261,22 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -300,7 +300,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -336,26 +336,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !20 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !20 -// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !20 -// CHECK1-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !20 -// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 +// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK1-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !20 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -372,7 +372,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -417,23 +417,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 -// CHECK1-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !23 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: call void @_Z9gtid_testv() // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -500,7 +500,7 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK1: omp_offload.cont6: // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -512,7 +512,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -547,22 +547,22 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !26 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !26 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !26 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -579,7 +579,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -624,23 +624,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29 -// CHECK1-NEXT: call void @_Z3fn4v(), !llvm.access.group !29 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: call void @_Z3fn4v() // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -664,7 +664,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -700,26 +700,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !32 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !32 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !32 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !32 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !32 -// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !32 -// CHECK1-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !32 -// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !32 +// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK1-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !32 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -736,7 +736,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -781,23 +781,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35 -// CHECK1-NEXT: call void @_Z3fn5v(), !llvm.access.group !35 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: call void @_Z3fn5v() // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -814,7 +814,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK1-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -824,7 +824,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -863,35 +863,35 @@ int main() { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4, !llvm.access.group !38 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1: omp_if.then: -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !38 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !38 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38 -// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !38 -// CHECK1-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]], !llvm.access.group !38 -// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !38 +// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK1-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !38 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -908,7 +908,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -953,23 +953,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !41 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !41 -// CHECK1-NEXT: call void @_Z3fn6v(), !llvm.access.group !41 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: call void @_Z3fn6v() // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -986,7 +986,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK1-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1046,7 +1046,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1081,22 +1081,22 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !44 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !44 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !44 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !44 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !44 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1113,7 +1113,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1158,23 +1158,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47 -// CHECK1-NEXT: call void @_Z3fn1v(), !llvm.access.group !47 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: call void @_Z3fn1v() // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1198,7 +1198,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1234,26 +1234,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !50 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !50 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !50 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !50 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !50 -// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !50 -// CHECK1-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !50 -// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !50 +// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK1-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !50 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP51:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1270,7 +1270,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1315,23 +1315,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !53 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !53 -// CHECK1-NEXT: call void @_Z3fn2v(), !llvm.access.group !53 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: call void @_Z3fn2v() // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP54:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1348,7 +1348,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l71 -// CHECK1-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -1358,7 +1358,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1397,35 +1397,35 @@ int main() { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !56 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !56 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4, !llvm.access.group !56 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1: omp_if.then: -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !56 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !56 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !56 -// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !56 -// CHECK1-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]], !llvm.access.group !56 -// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !56 +// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK1-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !56 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !56 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !56 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP57:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1442,7 +1442,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1487,23 +1487,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !59 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !59 -// CHECK1-NEXT: call void @_Z3fn3v(), !llvm.access.group !59 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: call void @_Z3fn3v() // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP60:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1558,7 +1558,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1593,22 +1593,22 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !11 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1625,7 +1625,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1670,22 +1670,22 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1709,7 +1709,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1745,26 +1745,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !20 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !20 -// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !20 -// CHECK2-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !20 -// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 +// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK2-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !20 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1781,7 +1781,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1826,23 +1826,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 -// CHECK2-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !23 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: call void @_Z9gtid_testv() // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1909,7 +1909,7 @@ int main() { // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK2: omp_offload.cont6: // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -1921,7 +1921,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1956,22 +1956,22 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !26 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !26 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !26 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1988,7 +1988,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2033,23 +2033,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29 -// CHECK2-NEXT: call void @_Z3fn4v(), !llvm.access.group !29 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: call void @_Z3fn4v() // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2073,7 +2073,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2109,26 +2109,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !32 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !32 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !32 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !32 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !32 -// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !32 -// CHECK2-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !32 -// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !32 +// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK2-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !32 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2145,7 +2145,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2190,23 +2190,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35 -// CHECK2-NEXT: call void @_Z3fn5v(), !llvm.access.group !35 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: call void @_Z3fn5v() // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2223,7 +2223,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK2-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -2233,7 +2233,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2272,35 +2272,35 @@ int main() { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4, !llvm.access.group !38 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2: omp_if.then: -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !38 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2: omp_if.else: -// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !38 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38 -// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !38 -// CHECK2-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]], !llvm.access.group !38 -// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !38 +// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK2-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) // CHECK2-NEXT: br label [[OMP_IF_END]] // CHECK2: omp_if.end: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !38 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2317,7 +2317,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2362,23 +2362,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !41 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !41 -// CHECK2-NEXT: call void @_Z3fn6v(), !llvm.access.group !41 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: call void @_Z3fn6v() // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2395,7 +2395,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK2-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -2455,7 +2455,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2490,22 +2490,22 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !44 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !44 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !44 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !44 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !44 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2522,7 +2522,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2567,23 +2567,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47 -// CHECK2-NEXT: call void @_Z3fn1v(), !llvm.access.group !47 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: call void @_Z3fn1v() // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2607,7 +2607,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2643,26 +2643,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !50 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !50 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !50 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !50 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !50 -// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !50 -// CHECK2-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !50 -// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !50 +// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK2-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !50 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP51:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2679,7 +2679,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2724,23 +2724,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !53 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !53 -// CHECK2-NEXT: call void @_Z3fn2v(), !llvm.access.group !53 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: call void @_Z3fn2v() // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP54:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2757,7 +2757,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l71 -// CHECK2-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -2767,7 +2767,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2806,35 +2806,35 @@ int main() { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !56 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !56 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4, !llvm.access.group !56 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2: omp_if.then: -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !56 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2: omp_if.else: -// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !56 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !56 -// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !56 -// CHECK2-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]], !llvm.access.group !56 -// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !56 +// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK2-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) // CHECK2-NEXT: br label [[OMP_IF_END]] // CHECK2: omp_if.end: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !56 -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !56 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !56 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP57:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2851,7 +2851,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2896,23 +2896,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !59 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !59 -// CHECK2-NEXT: call void @_Z3fn3v(), !llvm.access.group !59 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: call void @_Z3fn3v() // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP60:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2967,7 +2967,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3002,22 +3002,22 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !11 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -3034,7 +3034,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3079,22 +3079,22 @@ int main() { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -3118,7 +3118,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3154,26 +3154,26 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !20 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !20 -// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !20 -// CHECK3-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !20 -// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !20 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -3190,7 +3190,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3235,23 +3235,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 -// CHECK3-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !23 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: call void @_Z9gtid_testv() // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -3318,7 +3318,7 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK3: omp_offload.cont6: // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -3330,7 +3330,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3365,22 +3365,22 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !26 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !26 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !26 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -3397,7 +3397,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3442,23 +3442,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29 -// CHECK3-NEXT: call void @_Z3fn4v(), !llvm.access.group !29 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: call void @_Z3fn4v() // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -3482,7 +3482,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3554,7 +3554,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3632,7 +3632,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK3-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -3642,7 +3642,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3693,41 +3693,41 @@ int main() { // CHECK3: omp_if.then: // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !35 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !35 +// CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK3-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK3-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[TOBOOL3]] to i8 -// CHECK3-NEXT: store i8 [[FROMBOOL4]], i8* [[CONV]], align 1, !llvm.access.group !35 -// CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !35 -// CHECK3-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !35 +// CHECK3-NEXT: store i8 [[FROMBOOL4]], i8* [[CONV]], align 1 +// CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK3-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK3-NEXT: [[TOBOOL5:%.*]] = trunc i8 [[TMP16]] to i1 // CHECK3-NEXT: br i1 [[TOBOOL5]], label [[OMP_IF_THEN6:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3: omp_if.then6: -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]), !llvm.access.group !35 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]) // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]), !llvm.access.group !35 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !35 -// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !35 -// CHECK3-NEXT: call void @.omp_outlined..9(i32* [[TMP17]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]) #[[ATTR2]], !llvm.access.group !35 -// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]), !llvm.access.group !35 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) +// CHECK3-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: call void @.omp_outlined..9(i32* [[TMP17]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !35 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_IF_END23:%.*]] @@ -3787,7 +3787,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3839,23 +3839,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 -// CHECK3-NEXT: call void @_Z3fn6v(), !llvm.access.group !39 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: call void @_Z3fn6v() // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] @@ -3915,7 +3915,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3967,23 +3967,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !43 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43 -// CHECK3-NEXT: call void @_Z3fn6v(), !llvm.access.group !43 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: call void @_Z3fn6v() // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] @@ -4043,7 +4043,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK3-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK3-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -4103,7 +4103,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4138,22 +4138,22 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !47 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !47 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !47 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !47 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !47 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4170,7 +4170,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4215,23 +4215,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !50 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !50 -// CHECK3-NEXT: call void @_Z3fn1v(), !llvm.access.group !50 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: call void @_Z3fn1v() // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP51:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4255,7 +4255,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4327,7 +4327,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4405,7 +4405,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l71 -// CHECK3-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -4415,7 +4415,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4454,35 +4454,35 @@ int main() { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !55 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !55 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4, !llvm.access.group !55 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3: omp_if.then: -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !55 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !55 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !55 -// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !55 -// CHECK3-NEXT: call void @.omp_outlined..16(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]], !llvm.access.group !55 -// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !55 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK3-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: call void @.omp_outlined..16(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !55 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !55 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !55 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP56:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4499,7 +4499,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4544,23 +4544,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !58 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !58 -// CHECK3-NEXT: call void @_Z3fn3v(), !llvm.access.group !58 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: call void @_Z3fn3v() // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP59:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4615,7 +4615,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4650,22 +4650,22 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !11 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4682,7 +4682,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4727,22 +4727,22 @@ int main() { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4766,7 +4766,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4802,26 +4802,26 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !20 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !20 -// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !20 -// CHECK4-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !20 -// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !20 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4838,7 +4838,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4883,23 +4883,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 -// CHECK4-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !23 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: call void @_Z9gtid_testv() // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4966,7 +4966,7 @@ int main() { // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK4: omp_offload.cont6: // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK4-NEXT: ret i32 [[CALL]] // // @@ -4978,7 +4978,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5013,22 +5013,22 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !26 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !26 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !26 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -5045,7 +5045,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5090,23 +5090,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29 -// CHECK4-NEXT: call void @_Z3fn4v(), !llvm.access.group !29 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: call void @_Z3fn4v() // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -5130,7 +5130,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5202,7 +5202,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5280,7 +5280,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK4-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -5290,7 +5290,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5341,41 +5341,41 @@ int main() { // CHECK4: omp_if.then: // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !35 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !35 +// CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK4-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK4-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[TOBOOL3]] to i8 -// CHECK4-NEXT: store i8 [[FROMBOOL4]], i8* [[CONV]], align 1, !llvm.access.group !35 -// CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !35 -// CHECK4-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !35 +// CHECK4-NEXT: store i8 [[FROMBOOL4]], i8* [[CONV]], align 1 +// CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK4-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK4-NEXT: [[TOBOOL5:%.*]] = trunc i8 [[TMP16]] to i1 // CHECK4-NEXT: br i1 [[TOBOOL5]], label [[OMP_IF_THEN6:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4: omp_if.then6: -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]), !llvm.access.group !35 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]) // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] // CHECK4: omp_if.else: -// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]), !llvm.access.group !35 -// CHECK4-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !35 -// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !35 -// CHECK4-NEXT: call void @.omp_outlined..9(i32* [[TMP17]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]) #[[ATTR2]], !llvm.access.group !35 -// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]), !llvm.access.group !35 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) +// CHECK4-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: call void @.omp_outlined..9(i32* [[TMP17]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) // CHECK4-NEXT: br label [[OMP_IF_END]] // CHECK4: omp_if.end: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 -// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !35 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_IF_END23:%.*]] @@ -5435,7 +5435,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5487,23 +5487,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 -// CHECK4-NEXT: call void @_Z3fn6v(), !llvm.access.group !39 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: call void @_Z3fn6v() // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] @@ -5563,7 +5563,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5615,23 +5615,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !43 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43 -// CHECK4-NEXT: call void @_Z3fn6v(), !llvm.access.group !43 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: call void @_Z3fn6v() // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] @@ -5691,7 +5691,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK4-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK4-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -5751,7 +5751,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5786,22 +5786,22 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !47 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !47 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !47 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !47 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !47 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -5818,7 +5818,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5863,23 +5863,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !50 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !50 -// CHECK4-NEXT: call void @_Z3fn1v(), !llvm.access.group !50 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: call void @_Z3fn1v() // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP51:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -5903,7 +5903,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5975,7 +5975,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6053,7 +6053,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l71 -// CHECK4-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK4-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -6063,7 +6063,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6102,35 +6102,35 @@ int main() { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !55 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !55 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4, !llvm.access.group !55 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4: omp_if.then: -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !55 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] // CHECK4: omp_if.else: -// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !55 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !55 -// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !55 -// CHECK4-NEXT: call void @.omp_outlined..16(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]], !llvm.access.group !55 -// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !55 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK4-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: call void @.omp_outlined..16(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) // CHECK4-NEXT: br label [[OMP_IF_END]] // CHECK4: omp_if.end: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !55 -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !55 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !55 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP56:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -6147,7 +6147,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6192,23 +6192,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !58 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !58 -// CHECK4-NEXT: call void @_Z3fn3v(), !llvm.access.group !58 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: call void @_Z3fn3v() // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP59:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -6250,22 +6250,22 @@ int main() { // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK5-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 100, i32* [[I]], align 4 @@ -6275,23 +6275,23 @@ int main() { // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK5: omp.inner.for.cond7: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !6 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK5: omp.inner.for.body9: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK5-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !6 -// CHECK5-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !6 +// CHECK5-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK5-NEXT: call void @_Z9gtid_testv() // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK5: omp.body.continue12: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK5: omp.inner.for.inc13: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK5: omp.inner.for.end15: // CHECK5-NEXT: store i32 100, i32* [[I6]], align 4 @@ -6324,23 +6324,23 @@ int main() { // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK5-NEXT: call void @_Z3fn4v(), !llvm.access.group !9 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: call void @_Z3fn4v() // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 100, i32* [[I]], align 4 @@ -6350,23 +6350,23 @@ int main() { // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK5: omp.inner.for.cond7: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !12 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK5: omp.inner.for.body9: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK5-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !12 -// CHECK5-NEXT: call void @_Z3fn5v(), !llvm.access.group !12 +// CHECK5-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK5-NEXT: call void @_Z3fn5v() // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK5: omp.body.continue12: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK5: omp.inner.for.inc13: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 +// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK5: omp.inner.for.end15: // CHECK5-NEXT: store i32 100, i32* [[I6]], align 4 @@ -6376,33 +6376,33 @@ int main() { // CHECK5-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK5: omp.inner.for.cond21: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !15 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK5-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK5-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK5: omp.inner.for.body23: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK5-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !15 -// CHECK5-NEXT: call void @_Z3fn6v(), !llvm.access.group !15 +// CHECK5-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK5-NEXT: call void @_Z3fn6v() // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK5: omp.body.continue26: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK5: omp.inner.for.inc27: -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK5-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 +// CHECK5-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK5: omp.inner.for.end29: // CHECK5-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK5-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK5-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -6427,23 +6427,23 @@ int main() { // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK5-NEXT: call void @_Z3fn1v(), !llvm.access.group !18 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: call void @_Z3fn1v() // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 100, i32* [[I]], align 4 @@ -6453,23 +6453,23 @@ int main() { // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK5: omp.inner.for.cond7: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK5: omp.inner.for.body9: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK5-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !21 -// CHECK5-NEXT: call void @_Z3fn2v(), !llvm.access.group !21 +// CHECK5-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK5-NEXT: call void @_Z3fn2v() // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK5: omp.body.continue12: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK5: omp.inner.for.inc13: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK5: omp.inner.for.end15: // CHECK5-NEXT: store i32 100, i32* [[I6]], align 4 @@ -6479,23 +6479,23 @@ int main() { // CHECK5-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK5: omp.inner.for.cond21: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK5-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK5-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK5: omp.inner.for.body23: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK5-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !24 -// CHECK5-NEXT: call void @_Z3fn3v(), !llvm.access.group !24 +// CHECK5-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK5-NEXT: call void @_Z3fn3v() // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK5: omp.body.continue26: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK5: omp.inner.for.inc27: -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK5-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK5: omp.inner.for.end29: // CHECK5-NEXT: store i32 100, i32* [[I20]], align 4 @@ -6521,22 +6521,22 @@ int main() { // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK6-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: store i32 100, i32* [[I]], align 4 @@ -6546,23 +6546,23 @@ int main() { // CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK6: omp.inner.for.cond7: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !6 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK6: omp.inner.for.body9: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK6-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !6 -// CHECK6-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !6 +// CHECK6-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK6-NEXT: call void @_Z9gtid_testv() // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK6: omp.body.continue12: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK6: omp.inner.for.inc13: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK6: omp.inner.for.end15: // CHECK6-NEXT: store i32 100, i32* [[I6]], align 4 @@ -6595,23 +6595,23 @@ int main() { // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK6-NEXT: call void @_Z3fn4v(), !llvm.access.group !9 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: call void @_Z3fn4v() // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: store i32 100, i32* [[I]], align 4 @@ -6621,23 +6621,23 @@ int main() { // CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK6: omp.inner.for.cond7: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !12 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK6: omp.inner.for.body9: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK6-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !12 -// CHECK6-NEXT: call void @_Z3fn5v(), !llvm.access.group !12 +// CHECK6-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK6-NEXT: call void @_Z3fn5v() // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK6: omp.body.continue12: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK6: omp.inner.for.inc13: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 +// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK6: omp.inner.for.end15: // CHECK6-NEXT: store i32 100, i32* [[I6]], align 4 @@ -6647,33 +6647,33 @@ int main() { // CHECK6-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK6: omp.inner.for.cond21: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !15 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK6-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK6-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK6: omp.inner.for.body23: -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK6-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK6-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !15 -// CHECK6-NEXT: call void @_Z3fn6v(), !llvm.access.group !15 +// CHECK6-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK6-NEXT: call void @_Z3fn6v() // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK6: omp.body.continue26: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK6: omp.inner.for.inc27: -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK6-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 +// CHECK6-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK6: omp.inner.for.end29: // CHECK6-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK6-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK6-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -6698,23 +6698,23 @@ int main() { // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK6-NEXT: call void @_Z3fn1v(), !llvm.access.group !18 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: call void @_Z3fn1v() // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: store i32 100, i32* [[I]], align 4 @@ -6724,23 +6724,23 @@ int main() { // CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK6: omp.inner.for.cond7: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK6: omp.inner.for.body9: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK6-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !21 -// CHECK6-NEXT: call void @_Z3fn2v(), !llvm.access.group !21 +// CHECK6-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK6-NEXT: call void @_Z3fn2v() // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK6: omp.body.continue12: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK6: omp.inner.for.inc13: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK6: omp.inner.for.end15: // CHECK6-NEXT: store i32 100, i32* [[I6]], align 4 @@ -6750,23 +6750,23 @@ int main() { // CHECK6-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK6: omp.inner.for.cond21: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK6-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK6-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK6: omp.inner.for.body23: -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK6-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK6-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !24 -// CHECK6-NEXT: call void @_Z3fn3v(), !llvm.access.group !24 +// CHECK6-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK6-NEXT: call void @_Z3fn3v() // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK6: omp.body.continue26: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK6: omp.inner.for.inc27: -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK6-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK6: omp.inner.for.end29: // CHECK6-NEXT: store i32 100, i32* [[I20]], align 4 @@ -6792,22 +6792,22 @@ int main() { // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 100, i32* [[I]], align 4 @@ -6817,23 +6817,23 @@ int main() { // CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK7: omp.inner.for.cond7: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !6 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK7: omp.inner.for.body9: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK7-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK7-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK7-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !6 +// CHECK7-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK7-NEXT: call void @_Z9gtid_testv() // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK7: omp.body.continue12: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK7: omp.inner.for.inc13: -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK7-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK7-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK7: omp.inner.for.end15: // CHECK7-NEXT: store i32 100, i32* [[I6]], align 4 @@ -6867,23 +6867,23 @@ int main() { // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK7-NEXT: call void @_Z3fn4v(), !llvm.access.group !9 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: call void @_Z3fn4v() // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 100, i32* [[I]], align 4 @@ -6927,23 +6927,23 @@ int main() { // CHECK7: omp_if.then: // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND22:%.*]] // CHECK7: omp.inner.for.cond22: -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK7-NEXT: [[CMP23:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK7-NEXT: br i1 [[CMP23]], label [[OMP_INNER_FOR_BODY24:%.*]], label [[OMP_INNER_FOR_END30:%.*]] // CHECK7: omp.inner.for.body24: -// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK7-NEXT: [[MUL25:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK7-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]] -// CHECK7-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4, !llvm.access.group !14 -// CHECK7-NEXT: call void @_Z3fn6v(), !llvm.access.group !14 +// CHECK7-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4 +// CHECK7-NEXT: call void @_Z3fn6v() // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]] // CHECK7: omp.body.continue27: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]] // CHECK7: omp.inner.for.inc28: -// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK7-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK7-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND22]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK7: omp.inner.for.end30: // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] @@ -6973,12 +6973,12 @@ int main() { // CHECK7: omp_if.end: // CHECK7-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP21]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP21]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK7-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK7-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -7003,23 +7003,23 @@ int main() { // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK7-NEXT: call void @_Z3fn1v(), !llvm.access.group !18 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: call void @_Z3fn1v() // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 100, i32* [[I]], align 4 @@ -7055,23 +7055,23 @@ int main() { // CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV19]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK7: omp.inner.for.cond21: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK7-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK7-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK7: omp.inner.for.body23: -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK7-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK7-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !22 -// CHECK7-NEXT: call void @_Z3fn3v(), !llvm.access.group !22 +// CHECK7-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK7-NEXT: call void @_Z3fn3v() // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK7: omp.body.continue26: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK7: omp.inner.for.inc27: -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK7-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK7-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK7: omp.inner.for.end29: // CHECK7-NEXT: store i32 100, i32* [[I20]], align 4 @@ -7097,22 +7097,22 @@ int main() { // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 100, i32* [[I]], align 4 @@ -7122,23 +7122,23 @@ int main() { // CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK8: omp.inner.for.cond7: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !6 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK8: omp.inner.for.body9: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK8-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK8-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK8-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !6 +// CHECK8-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK8-NEXT: call void @_Z9gtid_testv() // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK8: omp.body.continue12: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK8: omp.inner.for.inc13: -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK8-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK8-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK8-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK8: omp.inner.for.end15: // CHECK8-NEXT: store i32 100, i32* [[I6]], align 4 @@ -7172,23 +7172,23 @@ int main() { // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK8-NEXT: call void @_Z3fn4v(), !llvm.access.group !9 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: call void @_Z3fn4v() // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 100, i32* [[I]], align 4 @@ -7232,23 +7232,23 @@ int main() { // CHECK8: omp_if.then: // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND22:%.*]] // CHECK8: omp.inner.for.cond22: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK8-NEXT: [[CMP23:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK8-NEXT: br i1 [[CMP23]], label [[OMP_INNER_FOR_BODY24:%.*]], label [[OMP_INNER_FOR_END30:%.*]] // CHECK8: omp.inner.for.body24: -// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK8-NEXT: [[MUL25:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK8-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]] -// CHECK8-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4, !llvm.access.group !14 -// CHECK8-NEXT: call void @_Z3fn6v(), !llvm.access.group !14 +// CHECK8-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4 +// CHECK8-NEXT: call void @_Z3fn6v() // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]] // CHECK8: omp.body.continue27: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]] // CHECK8: omp.inner.for.inc28: -// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK8-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK8-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND22]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK8: omp.inner.for.end30: // CHECK8-NEXT: br label [[OMP_IF_END:%.*]] @@ -7278,12 +7278,12 @@ int main() { // CHECK8: omp_if.end: // CHECK8-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP21]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP21]]) // CHECK8-NEXT: ret i32 [[CALL]] // // // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK8-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK8-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -7308,23 +7308,23 @@ int main() { // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK8-NEXT: call void @_Z3fn1v(), !llvm.access.group !18 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: call void @_Z3fn1v() // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 100, i32* [[I]], align 4 @@ -7360,23 +7360,23 @@ int main() { // CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV19]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK8: omp.inner.for.cond21: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK8-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK8-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK8: omp.inner.for.body23: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK8-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK8-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !22 -// CHECK8-NEXT: call void @_Z3fn3v(), !llvm.access.group !22 +// CHECK8-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK8-NEXT: call void @_Z3fn3v() // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK8: omp.body.continue26: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK8: omp.inner.for.inc27: -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK8-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK8-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK8: omp.inner.for.end29: // CHECK8-NEXT: store i32 100, i32* [[I20]], align 4 @@ -7415,7 +7415,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7450,22 +7450,22 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -7482,7 +7482,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7527,22 +7527,22 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -7566,7 +7566,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7602,26 +7602,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !24 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !24 -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 +// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK9-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -7638,7 +7638,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7683,23 +7683,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !27 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: call void @_Z9gtid_testv() // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -7766,7 +7766,7 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK9: omp_offload.cont6: // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK9-NEXT: ret i32 [[CALL]] // // @@ -7778,7 +7778,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7813,22 +7813,22 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -7845,7 +7845,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7890,23 +7890,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 -// CHECK9-NEXT: call void @_Z3fn4v(), !llvm.access.group !33 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: call void @_Z3fn4v() // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -7930,7 +7930,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7966,26 +7966,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !36 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !36 -// CHECK9-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !36 -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36 +// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK9-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8002,7 +8002,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8047,23 +8047,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 -// CHECK9-NEXT: call void @_Z3fn5v(), !llvm.access.group !39 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: call void @_Z3fn5v() // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8080,7 +8080,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK9-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -8090,7 +8090,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8129,35 +8129,35 @@ int main() { // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9: omp_if.then: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !42 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9: omp_if.else: -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !42 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !42 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]], !llvm.access.group !42 -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !42 +// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK9-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) // CHECK9-NEXT: br label [[OMP_IF_END]] // CHECK9: omp_if.end: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8174,7 +8174,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8219,23 +8219,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 -// CHECK9-NEXT: call void @_Z3fn6v(), !llvm.access.group !45 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: call void @_Z3fn6v() // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8252,7 +8252,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK9-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK9-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -8312,7 +8312,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8347,22 +8347,22 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !48 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !48 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !48 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !48 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !48 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8379,7 +8379,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8424,23 +8424,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !51 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !51 -// CHECK9-NEXT: call void @_Z3fn1v(), !llvm.access.group !51 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: call void @_Z3fn1v() // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8464,7 +8464,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8500,26 +8500,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !54 -// CHECK9-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !54 -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54 +// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK9-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !54 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8536,7 +8536,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8581,23 +8581,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !57 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !57 -// CHECK9-NEXT: call void @_Z3fn2v(), !llvm.access.group !57 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: call void @_Z3fn2v() // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP58:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8614,7 +8614,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l71 -// CHECK9-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -8624,7 +8624,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8663,35 +8663,35 @@ int main() { // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !60 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !60 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4, !llvm.access.group !60 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9: omp_if.then: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !60 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9: omp_if.else: -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !60 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !60 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !60 -// CHECK9-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]], !llvm.access.group !60 -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !60 +// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK9-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) // CHECK9-NEXT: br label [[OMP_IF_END]] // CHECK9: omp_if.end: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !60 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !60 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !60 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP61:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8708,7 +8708,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8753,23 +8753,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !63 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !63 -// CHECK9-NEXT: call void @_Z3fn3v(), !llvm.access.group !63 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: call void @_Z3fn3v() // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP64:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8824,7 +8824,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8859,22 +8859,22 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8891,7 +8891,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8936,22 +8936,22 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8975,7 +8975,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9011,26 +9011,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !24 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !24 -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 +// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK10-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9047,7 +9047,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9092,23 +9092,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !27 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: call void @_Z9gtid_testv() // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9175,7 +9175,7 @@ int main() { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK10: omp_offload.cont6: // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK10-NEXT: ret i32 [[CALL]] // // @@ -9187,7 +9187,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9222,22 +9222,22 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9254,7 +9254,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9299,23 +9299,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 -// CHECK10-NEXT: call void @_Z3fn4v(), !llvm.access.group !33 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: call void @_Z3fn4v() // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9339,7 +9339,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9375,26 +9375,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !36 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !36 -// CHECK10-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !36 -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36 +// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK10-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9411,7 +9411,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9456,23 +9456,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 -// CHECK10-NEXT: call void @_Z3fn5v(), !llvm.access.group !39 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: call void @_Z3fn5v() // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9489,7 +9489,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK10-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -9499,7 +9499,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9538,35 +9538,35 @@ int main() { // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10: omp_if.then: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !42 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10: omp_if.else: -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !42 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !42 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]], !llvm.access.group !42 -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !42 +// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK10-NEXT: call void @.omp_outlined..9(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) // CHECK10-NEXT: br label [[OMP_IF_END]] // CHECK10: omp_if.end: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9583,7 +9583,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9628,23 +9628,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 -// CHECK10-NEXT: call void @_Z3fn6v(), !llvm.access.group !45 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: call void @_Z3fn6v() // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9661,7 +9661,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK10-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK10-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -9721,7 +9721,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9756,22 +9756,22 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !48 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !48 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !48 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !48 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !48 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9788,7 +9788,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9833,23 +9833,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !51 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !51 -// CHECK10-NEXT: call void @_Z3fn1v(), !llvm.access.group !51 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: call void @_Z3fn1v() // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9873,7 +9873,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9909,26 +9909,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !54 -// CHECK10-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !54 -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54 +// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK10-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !54 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9945,7 +9945,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9990,23 +9990,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !57 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !57 -// CHECK10-NEXT: call void @_Z3fn2v(), !llvm.access.group !57 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: call void @_Z3fn2v() // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP58:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10023,7 +10023,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l71 -// CHECK10-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -10033,7 +10033,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10072,35 +10072,35 @@ int main() { // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !60 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !60 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4, !llvm.access.group !60 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10: omp_if.then: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !60 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10: omp_if.else: -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !60 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !60 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !60 -// CHECK10-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]], !llvm.access.group !60 -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !60 +// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK10-NEXT: call void @.omp_outlined..15(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) // CHECK10-NEXT: br label [[OMP_IF_END]] // CHECK10: omp_if.end: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !60 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !60 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !60 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP61:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10117,7 +10117,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10162,23 +10162,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !63 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !63 -// CHECK10-NEXT: call void @_Z3fn3v(), !llvm.access.group !63 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: call void @_Z3fn3v() // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP64:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10233,7 +10233,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10268,22 +10268,22 @@ int main() { // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10300,7 +10300,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10345,22 +10345,22 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10384,7 +10384,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10420,26 +10420,26 @@ int main() { // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !24 -// CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !24 -// CHECK11-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !24 -// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 +// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK11-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10456,7 +10456,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10501,23 +10501,23 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 -// CHECK11-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !27 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: call void @_Z9gtid_testv() // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10584,7 +10584,7 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK11: omp_offload.cont6: // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK11-NEXT: ret i32 [[CALL]] // // @@ -10596,7 +10596,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10631,22 +10631,22 @@ int main() { // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10663,7 +10663,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10708,23 +10708,23 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 -// CHECK11-NEXT: call void @_Z3fn4v(), !llvm.access.group !33 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: call void @_Z3fn4v() // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10748,7 +10748,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10820,7 +10820,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10898,7 +10898,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK11-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -10908,7 +10908,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10959,41 +10959,41 @@ int main() { // CHECK11: omp_if.then: // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !39 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK11-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !39 +// CHECK11-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK11-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK11-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[TOBOOL3]] to i8 -// CHECK11-NEXT: store i8 [[FROMBOOL4]], i8* [[CONV]], align 1, !llvm.access.group !39 -// CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !39 -// CHECK11-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !39 +// CHECK11-NEXT: store i8 [[FROMBOOL4]], i8* [[CONV]], align 1 +// CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK11-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK11-NEXT: [[TOBOOL5:%.*]] = trunc i8 [[TMP16]] to i1 // CHECK11-NEXT: br i1 [[TOBOOL5]], label [[OMP_IF_THEN6:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11: omp_if.then6: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]), !llvm.access.group !39 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]) // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11: omp_if.else: -// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]), !llvm.access.group !39 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !39 -// CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !39 -// CHECK11-NEXT: call void @.omp_outlined..9(i32* [[TMP17]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]) #[[ATTR2]], !llvm.access.group !39 -// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]), !llvm.access.group !39 +// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) +// CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK11-NEXT: call void @.omp_outlined..9(i32* [[TMP17]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]) #[[ATTR2]] +// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) // CHECK11-NEXT: br label [[OMP_IF_END]] // CHECK11: omp_if.end: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !39 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_IF_END23:%.*]] @@ -11053,7 +11053,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11105,23 +11105,23 @@ int main() { // CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: call void @_Z3fn6v(), !llvm.access.group !43 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: call void @_Z3fn6v() // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] @@ -11181,7 +11181,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11233,23 +11233,23 @@ int main() { // CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47 -// CHECK11-NEXT: call void @_Z3fn6v(), !llvm.access.group !47 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: call void @_Z3fn6v() // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] @@ -11309,7 +11309,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK11-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK11-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -11369,7 +11369,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11404,22 +11404,22 @@ int main() { // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !51 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !51 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !51 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !51 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !51 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -11436,7 +11436,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11481,23 +11481,23 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !54 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !54 -// CHECK11-NEXT: call void @_Z3fn1v(), !llvm.access.group !54 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: call void @_Z3fn1v() // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -11521,7 +11521,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11593,7 +11593,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11671,7 +11671,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l71 -// CHECK11-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK11-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -11681,7 +11681,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11720,35 +11720,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !59 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4, !llvm.access.group !59 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11: omp_if.then: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !59 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11: omp_if.else: -// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !59 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !59 -// CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !59 -// CHECK11-NEXT: call void @.omp_outlined..16(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]], !llvm.access.group !59 -// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !59 +// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK11-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK11-NEXT: call void @.omp_outlined..16(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) // CHECK11-NEXT: br label [[OMP_IF_END]] // CHECK11: omp_if.end: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !59 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP60:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -11765,7 +11765,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11810,23 +11810,23 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !62 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !62 -// CHECK11-NEXT: call void @_Z3fn3v(), !llvm.access.group !62 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: call void @_Z3fn3v() // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP63:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -11881,7 +11881,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11916,22 +11916,22 @@ int main() { // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -11948,7 +11948,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11993,22 +11993,22 @@ int main() { // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -12032,7 +12032,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12068,26 +12068,26 @@ int main() { // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !24 -// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !24 -// CHECK12-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !24 -// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 +// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK12-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -12104,7 +12104,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12149,23 +12149,23 @@ int main() { // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 -// CHECK12-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !27 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: call void @_Z9gtid_testv() // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -12232,7 +12232,7 @@ int main() { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT6]] // CHECK12: omp_offload.cont6: // CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK12-NEXT: ret i32 [[CALL]] // // @@ -12244,7 +12244,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12279,22 +12279,22 @@ int main() { // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -12311,7 +12311,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12356,23 +12356,23 @@ int main() { // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 -// CHECK12-NEXT: call void @_Z3fn4v(), !llvm.access.group !33 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: call void @_Z3fn4v() // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -12396,7 +12396,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12468,7 +12468,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12546,7 +12546,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK12-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -12556,7 +12556,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12607,41 +12607,41 @@ int main() { // CHECK12: omp_if.then: // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !39 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK12-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !39 +// CHECK12-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK12-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK12-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[TOBOOL3]] to i8 -// CHECK12-NEXT: store i8 [[FROMBOOL4]], i8* [[CONV]], align 1, !llvm.access.group !39 -// CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !39 -// CHECK12-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !39 +// CHECK12-NEXT: store i8 [[FROMBOOL4]], i8* [[CONV]], align 1 +// CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK12-NEXT: [[TMP16:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK12-NEXT: [[TOBOOL5:%.*]] = trunc i8 [[TMP16]] to i1 // CHECK12-NEXT: br i1 [[TOBOOL5]], label [[OMP_IF_THEN6:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12: omp_if.then6: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]), !llvm.access.group !39 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]) // CHECK12-NEXT: br label [[OMP_IF_END:%.*]] // CHECK12: omp_if.else: -// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]), !llvm.access.group !39 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !39 -// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !39 -// CHECK12-NEXT: call void @.omp_outlined..9(i32* [[TMP17]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]) #[[ATTR2]], !llvm.access.group !39 -// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]), !llvm.access.group !39 +// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) +// CHECK12-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK12-NEXT: call void @.omp_outlined..9(i32* [[TMP17]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]]) #[[ATTR2]] +// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) // CHECK12-NEXT: br label [[OMP_IF_END]] // CHECK12: omp_if.end: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !39 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_IF_END23:%.*]] @@ -12701,7 +12701,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12753,23 +12753,23 @@ int main() { // CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: call void @_Z3fn6v(), !llvm.access.group !43 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: call void @_Z3fn6v() // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_IF_END:%.*]] @@ -12829,7 +12829,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12881,23 +12881,23 @@ int main() { // CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47 -// CHECK12-NEXT: call void @_Z3fn6v(), !llvm.access.group !47 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: call void @_Z3fn6v() // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_IF_END:%.*]] @@ -12957,7 +12957,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK12-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK12-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -13017,7 +13017,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13052,22 +13052,22 @@ int main() { // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !51 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !51 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !51 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !51 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !51 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -13084,7 +13084,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13129,23 +13129,23 @@ int main() { // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !54 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !54 -// CHECK12-NEXT: call void @_Z3fn1v(), !llvm.access.group !54 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: call void @_Z3fn1v() // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -13169,7 +13169,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13241,7 +13241,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13319,7 +13319,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l71 -// CHECK12-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK12-NEXT: store i64 [[ARG]], i64* [[ARG_ADDR]], align 8 @@ -13329,7 +13329,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13368,35 +13368,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !59 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4, !llvm.access.group !59 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0 // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12: omp_if.then: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !59 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK12-NEXT: br label [[OMP_IF_END:%.*]] // CHECK12: omp_if.else: -// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !59 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !59 -// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !59 -// CHECK12-NEXT: call void @.omp_outlined..16(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]], !llvm.access.group !59 -// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]), !llvm.access.group !59 +// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) +// CHECK12-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK12-NEXT: call void @.omp_outlined..16(i32* [[TMP13]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]]) #[[ATTR2]] +// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]]) // CHECK12-NEXT: br label [[OMP_IF_END]] // CHECK12: omp_if.end: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !59 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP60:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -13413,7 +13413,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13458,23 +13458,23 @@ int main() { // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !62 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !62 -// CHECK12-NEXT: call void @_Z3fn3v(), !llvm.access.group !62 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: call void @_Z3fn3v() // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP63:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -13516,22 +13516,22 @@ int main() { // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 100, i32* [[I]], align 4 @@ -13541,23 +13541,23 @@ int main() { // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK13: omp.inner.for.cond7: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK13: omp.inner.for.body9: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK13-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK13-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !10 -// CHECK13-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !10 +// CHECK13-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK13-NEXT: call void @_Z9gtid_testv() // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK13: omp.body.continue12: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK13: omp.inner.for.inc13: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK13: omp.inner.for.end15: // CHECK13-NEXT: store i32 100, i32* [[I6]], align 4 @@ -13590,23 +13590,23 @@ int main() { // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 -// CHECK13-NEXT: call void @_Z3fn4v(), !llvm.access.group !13 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK13-NEXT: call void @_Z3fn4v() // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK13-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 100, i32* [[I]], align 4 @@ -13616,23 +13616,23 @@ int main() { // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK13: omp.inner.for.cond7: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !16 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK13: omp.inner.for.body9: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK13-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK13-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !16 -// CHECK13-NEXT: call void @_Z3fn5v(), !llvm.access.group !16 +// CHECK13-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK13-NEXT: call void @_Z3fn5v() // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK13: omp.body.continue12: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK13: omp.inner.for.inc13: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 +// CHECK13-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK13: omp.inner.for.end15: // CHECK13-NEXT: store i32 100, i32* [[I6]], align 4 @@ -13642,33 +13642,33 @@ int main() { // CHECK13-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK13: omp.inner.for.cond21: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !19 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK13-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK13-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK13: omp.inner.for.body23: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK13-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK13-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !19 -// CHECK13-NEXT: call void @_Z3fn6v(), !llvm.access.group !19 +// CHECK13-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK13-NEXT: call void @_Z3fn6v() // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK13: omp.body.continue26: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK13: omp.inner.for.inc27: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK13-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 +// CHECK13-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK13: omp.inner.for.end29: // CHECK13-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK13-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK13-NEXT: ret i32 [[CALL]] // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK13-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK13-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -13693,23 +13693,23 @@ int main() { // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 -// CHECK13-NEXT: call void @_Z3fn1v(), !llvm.access.group !22 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK13-NEXT: call void @_Z3fn1v() // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK13-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 100, i32* [[I]], align 4 @@ -13719,23 +13719,23 @@ int main() { // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK13: omp.inner.for.cond7: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !25 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK13: omp.inner.for.body9: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK13-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK13-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !25 -// CHECK13-NEXT: call void @_Z3fn2v(), !llvm.access.group !25 +// CHECK13-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK13-NEXT: call void @_Z3fn2v() // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK13: omp.body.continue12: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK13: omp.inner.for.inc13: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 +// CHECK13-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK13: omp.inner.for.end15: // CHECK13-NEXT: store i32 100, i32* [[I6]], align 4 @@ -13745,23 +13745,23 @@ int main() { // CHECK13-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK13: omp.inner.for.cond21: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !28 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK13-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK13-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK13: omp.inner.for.body23: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK13-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK13-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !28 -// CHECK13-NEXT: call void @_Z3fn3v(), !llvm.access.group !28 +// CHECK13-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK13-NEXT: call void @_Z3fn3v() // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK13: omp.body.continue26: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK13: omp.inner.for.inc27: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK13-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 +// CHECK13-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP29:![0-9]+]] // CHECK13: omp.inner.for.end29: // CHECK13-NEXT: store i32 100, i32* [[I20]], align 4 @@ -13787,22 +13787,22 @@ int main() { // CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: store i32 100, i32* [[I]], align 4 @@ -13812,23 +13812,23 @@ int main() { // CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK14: omp.inner.for.cond7: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK14-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK14: omp.inner.for.body9: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK14-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK14-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !10 -// CHECK14-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !10 +// CHECK14-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK14-NEXT: call void @_Z9gtid_testv() // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK14: omp.body.continue12: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK14: omp.inner.for.inc13: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK14: omp.inner.for.end15: // CHECK14-NEXT: store i32 100, i32* [[I6]], align 4 @@ -13861,23 +13861,23 @@ int main() { // CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 -// CHECK14-NEXT: call void @_Z3fn4v(), !llvm.access.group !13 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: call void @_Z3fn4v() // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK14-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: store i32 100, i32* [[I]], align 4 @@ -13887,23 +13887,23 @@ int main() { // CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK14: omp.inner.for.cond7: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !16 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK14-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK14: omp.inner.for.body9: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK14-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK14-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !16 -// CHECK14-NEXT: call void @_Z3fn5v(), !llvm.access.group !16 +// CHECK14-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK14-NEXT: call void @_Z3fn5v() // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK14: omp.body.continue12: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK14: omp.inner.for.inc13: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 +// CHECK14-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK14: omp.inner.for.end15: // CHECK14-NEXT: store i32 100, i32* [[I6]], align 4 @@ -13913,33 +13913,33 @@ int main() { // CHECK14-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK14: omp.inner.for.cond21: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !19 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK14-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK14-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK14: omp.inner.for.body23: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK14-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK14-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !19 -// CHECK14-NEXT: call void @_Z3fn6v(), !llvm.access.group !19 +// CHECK14-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK14-NEXT: call void @_Z3fn6v() // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK14: omp.body.continue26: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK14: omp.inner.for.inc27: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK14-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 +// CHECK14-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK14: omp.inner.for.end29: // CHECK14-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* @Arg, align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP15]]) +// CHECK14-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP15]]) // CHECK14-NEXT: ret i32 [[CALL]] // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK14-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK14-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -13964,23 +13964,23 @@ int main() { // CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 -// CHECK14-NEXT: call void @_Z3fn1v(), !llvm.access.group !22 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: call void @_Z3fn1v() // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK14-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: store i32 100, i32* [[I]], align 4 @@ -13990,23 +13990,23 @@ int main() { // CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK14: omp.inner.for.cond7: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !25 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK14-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK14: omp.inner.for.body9: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK14-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK14-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !25 -// CHECK14-NEXT: call void @_Z3fn2v(), !llvm.access.group !25 +// CHECK14-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK14-NEXT: call void @_Z3fn2v() // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK14: omp.body.continue12: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK14: omp.inner.for.inc13: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 +// CHECK14-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK14: omp.inner.for.end15: // CHECK14-NEXT: store i32 100, i32* [[I6]], align 4 @@ -14016,23 +14016,23 @@ int main() { // CHECK14-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK14: omp.inner.for.cond21: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !28 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK14-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK14-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK14: omp.inner.for.body23: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK14-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK14-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !28 -// CHECK14-NEXT: call void @_Z3fn3v(), !llvm.access.group !28 +// CHECK14-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK14-NEXT: call void @_Z3fn3v() // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK14: omp.body.continue26: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK14: omp.inner.for.inc27: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK14-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 +// CHECK14-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP29:![0-9]+]] // CHECK14: omp.inner.for.end29: // CHECK14-NEXT: store i32 100, i32* [[I20]], align 4 @@ -14058,22 +14058,22 @@ int main() { // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 100, i32* [[I]], align 4 @@ -14083,23 +14083,23 @@ int main() { // CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK15: omp.inner.for.cond7: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !10 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK15: omp.inner.for.body9: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK15-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK15-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK15-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !10 -// CHECK15-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !10 +// CHECK15-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK15-NEXT: call void @_Z9gtid_testv() // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK15: omp.body.continue12: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK15: omp.inner.for.inc13: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK15-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK15-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK15: omp.inner.for.end15: // CHECK15-NEXT: store i32 100, i32* [[I6]], align 4 @@ -14133,23 +14133,23 @@ int main() { // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 -// CHECK15-NEXT: call void @_Z3fn4v(), !llvm.access.group !13 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK15-NEXT: call void @_Z3fn4v() // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 100, i32* [[I]], align 4 @@ -14193,23 +14193,23 @@ int main() { // CHECK15: omp_if.then: // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND22:%.*]] // CHECK15: omp.inner.for.cond22: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !18 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK15-NEXT: [[CMP23:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK15-NEXT: br i1 [[CMP23]], label [[OMP_INNER_FOR_BODY24:%.*]], label [[OMP_INNER_FOR_END30:%.*]] // CHECK15: omp.inner.for.body24: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK15-NEXT: [[MUL25:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK15-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]] -// CHECK15-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4, !llvm.access.group !18 -// CHECK15-NEXT: call void @_Z3fn6v(), !llvm.access.group !18 +// CHECK15-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4 +// CHECK15-NEXT: call void @_Z3fn6v() // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]] // CHECK15: omp.body.continue27: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]] // CHECK15: omp.inner.for.inc28: -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK15-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK15-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 +// CHECK15-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND22]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK15: omp.inner.for.end30: // CHECK15-NEXT: br label [[OMP_IF_END:%.*]] @@ -14239,12 +14239,12 @@ int main() { // CHECK15: omp_if.end: // CHECK15-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* @Arg, align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP21]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP21]]) // CHECK15-NEXT: ret i32 [[CALL]] // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK15-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK15-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -14269,23 +14269,23 @@ int main() { // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 -// CHECK15-NEXT: call void @_Z3fn1v(), !llvm.access.group !22 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK15-NEXT: call void @_Z3fn1v() // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 100, i32* [[I]], align 4 @@ -14321,23 +14321,23 @@ int main() { // CHECK15-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV19]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK15: omp.inner.for.cond21: -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !26 +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK15-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK15-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK15: omp.inner.for.body23: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK15-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK15-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK15-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !26 -// CHECK15-NEXT: call void @_Z3fn3v(), !llvm.access.group !26 +// CHECK15-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK15-NEXT: call void @_Z3fn3v() // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK15: omp.body.continue26: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK15: omp.inner.for.inc27: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK15-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK15-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 +// CHECK15-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK15: omp.inner.for.end29: // CHECK15-NEXT: store i32 100, i32* [[I20]], align 4 @@ -14363,22 +14363,22 @@ int main() { // CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK16: omp.body.continue: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: store i32 100, i32* [[I]], align 4 @@ -14388,23 +14388,23 @@ int main() { // CHECK16-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK16: omp.inner.for.cond7: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !10 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK16-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK16-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK16: omp.inner.for.body9: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK16-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK16-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK16-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !10 -// CHECK16-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !10 +// CHECK16-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK16-NEXT: call void @_Z9gtid_testv() // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK16: omp.body.continue12: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK16: omp.inner.for.inc13: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK16-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK16-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK16: omp.inner.for.end15: // CHECK16-NEXT: store i32 100, i32* [[I6]], align 4 @@ -14438,23 +14438,23 @@ int main() { // CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 -// CHECK16-NEXT: call void @_Z3fn4v(), !llvm.access.group !13 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: call void @_Z3fn4v() // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK16: omp.body.continue: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: store i32 100, i32* [[I]], align 4 @@ -14498,23 +14498,23 @@ int main() { // CHECK16: omp_if.then: // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND22:%.*]] // CHECK16: omp.inner.for.cond22: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !18 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK16-NEXT: [[CMP23:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK16-NEXT: br i1 [[CMP23]], label [[OMP_INNER_FOR_BODY24:%.*]], label [[OMP_INNER_FOR_END30:%.*]] // CHECK16: omp.inner.for.body24: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK16-NEXT: [[MUL25:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK16-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]] -// CHECK16-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4, !llvm.access.group !18 -// CHECK16-NEXT: call void @_Z3fn6v(), !llvm.access.group !18 +// CHECK16-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4 +// CHECK16-NEXT: call void @_Z3fn6v() // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]] // CHECK16: omp.body.continue27: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]] // CHECK16: omp.inner.for.inc28: -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK16-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK16-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 +// CHECK16-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND22]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK16: omp.inner.for.end30: // CHECK16-NEXT: br label [[OMP_IF_END:%.*]] @@ -14544,12 +14544,12 @@ int main() { // CHECK16: omp_if.end: // CHECK16-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* @Arg, align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP21]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP21]]) // CHECK16-NEXT: ret i32 [[CALL]] // // // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK16-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK16-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -14574,23 +14574,23 @@ int main() { // CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 -// CHECK16-NEXT: call void @_Z3fn1v(), !llvm.access.group !22 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: call void @_Z3fn1v() // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK16: omp.body.continue: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: store i32 100, i32* [[I]], align 4 @@ -14626,23 +14626,23 @@ int main() { // CHECK16-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV19]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK16: omp.inner.for.cond21: -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !26 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK16-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK16-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK16: omp.inner.for.body23: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK16-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK16-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK16-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !26 -// CHECK16-NEXT: call void @_Z3fn3v(), !llvm.access.group !26 +// CHECK16-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK16-NEXT: call void @_Z3fn3v() // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK16: omp.body.continue26: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK16: omp.inner.for.inc27: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK16-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK16-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 +// CHECK16-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK16: omp.inner.for.end29: // CHECK16-NEXT: store i32 100, i32* [[I20]], align 4 diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp index 1d8516151bcf3fd77802e32eb41f187bcf6dbd5c..a036fd3c8229663ec315dc8bbfeece0959105c04 100644 --- a/clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp @@ -221,12 +221,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -248,7 +248,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -307,24 +307,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[TMP17:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], double* [[G3]], double* [[TMP17]], i32* [[SVAR6]], float* [[SFVAR7]]), !llvm.access.group !4 +// CHECK1-NEXT: [[TMP17:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], double* [[G3]], double* [[TMP17]], i32* [[SVAR6]], float* [[SFVAR7]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -355,7 +355,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -422,38 +422,38 @@ int main() { // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: store double 1.000000e+00, double* [[G3]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8 +// CHECK1-NEXT: store i32 3, i32* [[SVAR6]], align 4 +// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK1-NEXT: store double* [[G3]], double** [[TMP16]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: store double* [[G3]], double** [[TMP16]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK1-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -504,12 +504,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK2-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -531,7 +531,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -590,24 +590,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK2-NEXT: [[TMP17:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], double* [[G3]], double* [[TMP17]], i32* [[SVAR6]], float* [[SFVAR7]]), !llvm.access.group !4 +// CHECK2-NEXT: [[TMP17:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], double* [[G3]], double* [[TMP17]], i32* [[SVAR6]], float* [[SFVAR7]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -638,7 +638,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -705,38 +705,38 @@ int main() { // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: store double 1.000000e+00, double* [[G3]], align 8 +// CHECK2-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8 +// CHECK2-NEXT: store i32 3, i32* [[SVAR6]], align 4 +// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK2-NEXT: store double* [[G3]], double** [[TMP16]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: store double* [[G3]], double** [[TMP16]], align 8 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK2-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -787,12 +787,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -822,7 +822,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -881,22 +881,22 @@ int main() { // CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP5]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], double* [[G3]], double* [[TMP15]], i32* [[SVAR6]], float* [[SFVAR7]]), !llvm.access.group !5 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP5]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], double* [[G3]], double* [[TMP15]], i32* [[SVAR6]], float* [[SFVAR7]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -927,7 +927,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -992,38 +992,38 @@ int main() { // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: store double 1.000000e+00, double* [[G2]], align 8 +// CHECK3-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4 +// CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4 +// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK3-NEXT: store double* [[G2]], double** [[TMP16]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store double* [[G2]], double** [[TMP16]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK3-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !9 +// CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1074,12 +1074,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -1109,7 +1109,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1168,22 +1168,22 @@ int main() { // CHECK4-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP5]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], double* [[G3]], double* [[TMP15]], i32* [[SVAR6]], float* [[SFVAR7]]), !llvm.access.group !5 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP5]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], double* [[G3]], double* [[TMP15]], i32* [[SVAR6]], float* [[SFVAR7]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1214,7 +1214,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1279,38 +1279,38 @@ int main() { // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: store double 1.000000e+00, double* [[G2]], align 8 +// CHECK4-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4 +// CHECK4-NEXT: store i32 3, i32* [[SVAR5]], align 4 +// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK4-NEXT: store double* [[G2]], double** [[TMP16]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store double* [[G2]], double** [[TMP16]], align 4 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK4-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !9 +// CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1361,7 +1361,7 @@ int main() { // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // @@ -1379,7 +1379,7 @@ int main() { // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // @@ -1397,7 +1397,7 @@ int main() { // CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK7-NEXT: ret i32 0 // // @@ -1415,7 +1415,7 @@ int main() { // CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK8-NEXT: ret i32 0 // // @@ -1440,14 +1440,14 @@ int main() { // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1512,7 +1512,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l125(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1520,27 +1520,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP39]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1548,12 +1548,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l125 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1578,7 +1578,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1626,13 +1626,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -1652,26 +1652,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP18]], i32* [[SVAR8]]), !llvm.access.group !5 +// CHECK9-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP18]], i32* [[SVAR8]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1718,14 +1718,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done13: @@ -1733,7 +1733,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1788,13 +1788,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -1814,37 +1814,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK9-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1891,14 +1891,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP39]], i32* [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP40]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done16: @@ -1906,12 +1906,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1930,14 +1930,14 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1997,17 +1997,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP32]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2018,7 +2018,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2032,7 +2032,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2041,17 +2041,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2059,12 +2059,12 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2086,7 +2086,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2130,13 +2130,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -2156,26 +2156,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP17]]), !llvm.access.group !14 +// CHECK9-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP17]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -2220,14 +2220,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done12: @@ -2235,7 +2235,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2286,13 +2286,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -2312,37 +2312,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 // CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* // CHECK9-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group !17 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -2387,14 +2387,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP36]], i8* align 4 [[TMP37]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -2402,17 +2402,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2423,7 +2423,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2437,7 +2437,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2473,14 +2473,14 @@ int main() { // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -2545,7 +2545,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l125(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -2553,27 +2553,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP39]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2581,12 +2581,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l125 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2611,7 +2611,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2659,13 +2659,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -2685,26 +2685,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP18]], i32* [[SVAR8]]), !llvm.access.group !5 +// CHECK10-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP18]], i32* [[SVAR8]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2751,14 +2751,14 @@ int main() { // CHECK10-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done13: @@ -2766,7 +2766,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2821,13 +2821,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -2847,37 +2847,37 @@ int main() { // CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK10-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK10-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2924,14 +2924,14 @@ int main() { // CHECK10-NEXT: store i32 [[TMP39]], i32* [[TMP4]], align 4 // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP40]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done16: @@ -2939,12 +2939,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -2963,14 +2963,14 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -3030,17 +3030,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP32]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3051,7 +3051,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3065,7 +3065,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3074,17 +3074,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3092,12 +3092,12 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -3119,7 +3119,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3163,13 +3163,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -3189,26 +3189,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK10-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP17]]), !llvm.access.group !14 +// CHECK10-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP17]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -3253,14 +3253,14 @@ int main() { // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done12: @@ -3268,7 +3268,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3319,13 +3319,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -3345,37 +3345,37 @@ int main() { // CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 // CHECK10-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK10-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* // CHECK10-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group !17 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -3420,14 +3420,14 @@ int main() { // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP36]], i8* align 4 [[TMP37]], i64 4, i1 false) // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done15: @@ -3435,17 +3435,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3456,7 +3456,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3470,7 +3470,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3506,14 +3506,14 @@ int main() { // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -3576,7 +3576,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l125(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -3584,27 +3584,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP39]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3612,12 +3612,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l125 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3640,7 +3640,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3688,13 +3688,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK11-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -3714,24 +3714,24 @@ int main() { // CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP16]], i32* [[SVAR8]]), !llvm.access.group !6 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP16]], i32* [[SVAR8]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -3778,14 +3778,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -3793,7 +3793,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3846,13 +3846,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -3872,35 +3872,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP17]] -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP19]] // CHECK11-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK11-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !10 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -3947,14 +3947,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP39]], i32* [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP40]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -3962,12 +3962,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -3986,14 +3986,14 @@ int main() { // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4052,17 +4052,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP32]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4073,7 +4073,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4087,7 +4087,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4096,17 +4096,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4114,12 +4114,12 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -4140,7 +4140,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4184,13 +4184,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK11-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -4210,24 +4210,24 @@ int main() { // CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP15]]), !llvm.access.group !15 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP15]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -4272,14 +4272,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done12: @@ -4287,7 +4287,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4336,13 +4336,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -4362,35 +4362,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP16]] -// CHECK11-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP18]] // CHECK11-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* // CHECK11-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group !18 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -4435,14 +4435,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP36]], i8* align 4 [[TMP37]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -4450,17 +4450,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4471,7 +4471,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4485,7 +4485,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4521,14 +4521,14 @@ int main() { // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -4591,7 +4591,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l125(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -4599,27 +4599,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP39]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4627,12 +4627,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l125 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -4655,7 +4655,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4703,13 +4703,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK12-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -4729,24 +4729,24 @@ int main() { // CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK12-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP16]], i32* [[SVAR8]]), !llvm.access.group !6 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP16]], i32* [[SVAR8]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -4793,14 +4793,14 @@ int main() { // CHECK12-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done13: @@ -4808,7 +4808,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4861,13 +4861,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -4887,35 +4887,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP17]] -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP19]] // CHECK12-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK12-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !10 +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -4962,14 +4962,14 @@ int main() { // CHECK12-NEXT: store i32 [[TMP39]], i32* [[TMP4]], align 4 // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP40]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done14: @@ -4977,12 +4977,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // @@ -5001,14 +5001,14 @@ int main() { // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -5067,17 +5067,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP32]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5088,7 +5088,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5102,7 +5102,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5111,17 +5111,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5129,12 +5129,12 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -5155,7 +5155,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5199,13 +5199,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK12-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -5225,24 +5225,24 @@ int main() { // CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP15]]), !llvm.access.group !15 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC4]], i32* [[T_VAR3]], [2 x %struct.S.0]* [[S_ARR5]], %struct.S.0* [[TMP15]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -5287,14 +5287,14 @@ int main() { // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done12: @@ -5302,7 +5302,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5351,13 +5351,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -5377,35 +5377,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP16]] -// CHECK12-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP18]] // CHECK12-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* // CHECK12-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group !18 +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -5450,14 +5450,14 @@ int main() { // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP36]], i8* align 4 [[TMP37]], i32 4, i1 false) // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done13: @@ -5465,17 +5465,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5486,7 +5486,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5500,7 +5500,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5543,14 +5543,14 @@ int main() { // CHECK13-NEXT: [[I16:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -5568,13 +5568,13 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: // CHECK13-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR7]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK13-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -5638,18 +5638,18 @@ int main() { // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) // CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK13-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4:[0-9]+]] // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 // CHECK13-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 @@ -5657,27 +5657,27 @@ int main() { // CHECK13: arraydestroy.body18: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST19:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE15]] ], [ [[ARRAYDESTROY_ELEMENT20:%.*]], [[ARRAYDESTROY_BODY18]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT20]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST19]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE21:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT20]], [[ARRAY_BEGIN17]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] // CHECK13: arraydestroy.done22: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP30]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5685,17 +5685,17 @@ int main() { // CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // @@ -5721,14 +5721,14 @@ int main() { // CHECK13-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK13-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -5746,13 +5746,13 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: // CHECK13-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR7]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK13-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -5814,14 +5814,14 @@ int main() { // CHECK13-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK13-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0 // CHECK13-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: @@ -5832,17 +5832,17 @@ int main() { // CHECK13: arraydestroy.body17: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE15]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK13: arraydestroy.done21: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP29]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5853,7 +5853,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5862,7 +5862,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5876,17 +5876,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5894,22 +5894,22 @@ int main() { // CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5920,7 +5920,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5934,7 +5934,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5970,14 +5970,14 @@ int main() { // CHECK14-NEXT: [[I16:%.*]] = alloca i32, align 4 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -5995,13 +5995,13 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: // CHECK14-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR7]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK14-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -6065,18 +6065,18 @@ int main() { // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) // CHECK14-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK14-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4:[0-9]+]] // CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 // CHECK14-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done15: -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 @@ -6084,27 +6084,27 @@ int main() { // CHECK14: arraydestroy.body18: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST19:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE15]] ], [ [[ARRAYDESTROY_ELEMENT20:%.*]], [[ARRAYDESTROY_BODY18]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT20]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST19]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE21:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT20]], [[ARRAY_BEGIN17]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] // CHECK14: arraydestroy.done22: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP30]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6112,17 +6112,17 @@ int main() { // CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // @@ -6148,14 +6148,14 @@ int main() { // CHECK14-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK14-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK14-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -6173,13 +6173,13 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: // CHECK14-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR7]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK14-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -6241,14 +6241,14 @@ int main() { // CHECK14-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK14-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0 // CHECK14-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done15: @@ -6259,17 +6259,17 @@ int main() { // CHECK14: arraydestroy.body17: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE15]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK14: arraydestroy.done21: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP29]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6280,7 +6280,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6289,7 +6289,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6303,17 +6303,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6321,22 +6321,22 @@ int main() { // CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -6347,7 +6347,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6361,7 +6361,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -6397,14 +6397,14 @@ int main() { // CHECK15-NEXT: [[I15:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -6422,13 +6422,13 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: // CHECK15-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR7]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK15-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -6490,18 +6490,18 @@ int main() { // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) // CHECK15-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK15-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4:[0-9]+]] // CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 // CHECK15-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done14: -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN16]], i32 2 @@ -6509,27 +6509,27 @@ int main() { // CHECK15: arraydestroy.body17: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST18]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK15: arraydestroy.done21: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP30]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6537,17 +6537,17 @@ int main() { // CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // @@ -6573,14 +6573,14 @@ int main() { // CHECK15-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK15-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -6598,13 +6598,13 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: // CHECK15-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR7]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK15-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -6664,14 +6664,14 @@ int main() { // CHECK15-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK15-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0 // CHECK15-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done14: @@ -6682,17 +6682,17 @@ int main() { // CHECK15: arraydestroy.body16: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST17]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK15: arraydestroy.done20: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP29]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -6703,7 +6703,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -6712,7 +6712,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6726,17 +6726,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6744,22 +6744,22 @@ int main() { // CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -6770,7 +6770,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6784,7 +6784,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -6820,14 +6820,14 @@ int main() { // CHECK16-NEXT: [[I15:%.*]] = alloca i32, align 4 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -6845,13 +6845,13 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: // CHECK16-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR7]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK16-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -6913,18 +6913,18 @@ int main() { // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) // CHECK16-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK16-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4:[0-9]+]] // CHECK16-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 // CHECK16-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done14: -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN16]], i32 2 @@ -6932,27 +6932,27 @@ int main() { // CHECK16: arraydestroy.body17: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST18]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK16: arraydestroy.done21: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP30]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6960,17 +6960,17 @@ int main() { // CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // @@ -6996,14 +6996,14 @@ int main() { // CHECK16-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK16-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK16-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -7021,13 +7021,13 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: // CHECK16-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR7]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK16-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -7087,14 +7087,14 @@ int main() { // CHECK16-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK16-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0 // CHECK16-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done14: @@ -7105,17 +7105,17 @@ int main() { // CHECK16: arraydestroy.body16: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST17]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK16: arraydestroy.done20: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP29]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -7126,7 +7126,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -7135,7 +7135,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -7149,17 +7149,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7167,22 +7167,22 @@ int main() { // CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -7193,7 +7193,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7207,7 +7207,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp index 253dd6a0562ffa7c49e663c59fba2459fc450b7e..ac57f7b96c9b5b86db38ad2e5b6d848fb973ce7d 100644 --- a/clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp @@ -108,8 +108,8 @@ int main() { // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK1-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK1-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK1-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -127,7 +127,7 @@ int main() { // CHECK1-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK1-NEXT: br label [[EH_RESUME:%.*]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -154,16 +154,16 @@ int main() { // CHECK1: omp_offload.cont3: // CHECK1-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK1-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK1-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK1-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK1-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK1: invoke.cont5: // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK1-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK1-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK1: invoke.cont7: // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK1-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP17]] // CHECK1: eh.resume: @@ -175,7 +175,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -183,12 +183,12 @@ int main() { // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -208,7 +208,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -243,24 +243,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !9 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !9 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -276,7 +276,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -321,26 +321,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !13 +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -357,7 +357,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK1-NEXT: catch i8* null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !13 +// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]] // CHECK1-NEXT: unreachable // // @@ -369,7 +369,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -379,7 +379,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -417,26 +417,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 // CHECK1-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !18 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !18 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -452,7 +452,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -497,26 +497,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !21 +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -533,7 +533,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK1-NEXT: catch i8* null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !21 +// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK1-NEXT: unreachable // // @@ -586,17 +586,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -610,7 +610,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -626,7 +626,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -661,24 +661,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !24 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -694,7 +694,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -739,26 +739,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !27 +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -775,7 +775,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK1-NEXT: catch i8* null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !27 +// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK1-NEXT: unreachable // // @@ -787,7 +787,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -822,24 +822,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !30 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -855,7 +855,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -900,26 +900,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !33 +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -936,7 +936,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK1-NEXT: catch i8* null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !33 +// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK1-NEXT: unreachable // // @@ -948,7 +948,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -983,24 +983,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !36 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1016,7 +1016,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1061,26 +1061,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !39 +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1097,7 +1097,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK1-NEXT: catch i8* null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !39 +// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK1-NEXT: unreachable // // @@ -1109,7 +1109,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1147,40 +1147,40 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !42 +// CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: -// CHECK1-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]], !llvm.access.group !42 +// CHECK1-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK1: invoke.cont2: // CHECK1-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !42 -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !42 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK1: lpad: // CHECK1-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } // CHECK1-NEXT: catch i8* null // CHECK1-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK1-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !42 +// CHECK1-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 -// CHECK1-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !42 -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42 +// CHECK1-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK1-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1198,16 +1198,16 @@ int main() { // CHECK1-NEXT: [[TMP19:%.*]] = landingpad { i8*, i32 } // CHECK1-NEXT: catch i8* null // CHECK1-NEXT: [[TMP20:%.*]] = extractvalue { i8*, i32 } [[TMP19]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !42 +// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]] // CHECK1-NEXT: unreachable // CHECK1: terminate.handler: -// CHECK1-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !llvm.access.group !42 -// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !42 +// CHECK1-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] // CHECK1-NEXT: unreachable // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1252,26 +1252,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !45 +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1288,7 +1288,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK1-NEXT: catch i8* null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !45 +// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK1-NEXT: unreachable // // @@ -1314,8 +1314,8 @@ int main() { // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK2-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK2-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK2-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -1333,7 +1333,7 @@ int main() { // CHECK2-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK2-NEXT: br label [[EH_RESUME:%.*]] // CHECK2: omp_offload.cont: // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -1360,16 +1360,16 @@ int main() { // CHECK2: omp_offload.cont3: // CHECK2-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK2-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK2-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK2-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK2-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK2: invoke.cont5: // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK2-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK2-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK2: invoke.cont7: // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK2-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP17]] // CHECK2: eh.resume: @@ -1381,7 +1381,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -1389,12 +1389,12 @@ int main() { // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1414,7 +1414,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1449,24 +1449,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !9 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !9 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1482,7 +1482,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1527,26 +1527,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: invoke void @_Z3foov() -// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !13 +// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1563,7 +1563,7 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK2-NEXT: catch i8* null // CHECK2-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !13 +// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]] // CHECK2-NEXT: unreachable // // @@ -1575,7 +1575,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK2-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -1585,7 +1585,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1623,26 +1623,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 // CHECK2-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !18 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !18 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1658,7 +1658,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1703,26 +1703,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: invoke void @_Z3foov() -// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !21 +// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1739,7 +1739,7 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK2-NEXT: catch i8* null // CHECK2-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !21 +// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK2-NEXT: unreachable // // @@ -1792,17 +1792,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -1816,7 +1816,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1832,7 +1832,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1867,24 +1867,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !24 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1900,7 +1900,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1945,26 +1945,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: invoke void @_Z3foov() -// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !27 +// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1981,7 +1981,7 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK2-NEXT: catch i8* null // CHECK2-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !27 +// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK2-NEXT: unreachable // // @@ -1993,7 +1993,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2028,24 +2028,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !30 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2061,7 +2061,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2106,26 +2106,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: invoke void @_Z3foov() -// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !33 +// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2142,7 +2142,7 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK2-NEXT: catch i8* null // CHECK2-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !33 +// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK2-NEXT: unreachable // // @@ -2154,7 +2154,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2189,24 +2189,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !36 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2222,7 +2222,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2267,26 +2267,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: invoke void @_Z3foov() -// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !39 +// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2303,7 +2303,7 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK2-NEXT: catch i8* null // CHECK2-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !39 +// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK2-NEXT: unreachable // // @@ -2315,7 +2315,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2353,40 +2353,40 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) -// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !42 +// CHECK2-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) +// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: -// CHECK2-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]], !llvm.access.group !42 +// CHECK2-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK2: invoke.cont2: // CHECK2-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !42 -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !42 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK2: lpad: // CHECK2-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } // CHECK2-NEXT: catch i8* null // CHECK2-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK2-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !42 +// CHECK2-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 -// CHECK2-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !42 -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42 +// CHECK2-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK2-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2404,16 +2404,16 @@ int main() { // CHECK2-NEXT: [[TMP19:%.*]] = landingpad { i8*, i32 } // CHECK2-NEXT: catch i8* null // CHECK2-NEXT: [[TMP20:%.*]] = extractvalue { i8*, i32 } [[TMP19]], 0 -// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !42 +// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]] // CHECK2-NEXT: unreachable // CHECK2: terminate.handler: -// CHECK2-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !llvm.access.group !42 -// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !42 +// CHECK2-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] // CHECK2-NEXT: unreachable // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2458,26 +2458,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: invoke void @_Z3foov() -// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !45 +// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2494,7 +2494,7 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK2-NEXT: catch i8* null // CHECK2-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !45 +// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK2-NEXT: unreachable // // @@ -2524,8 +2524,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I7:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK3-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK3-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK3-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK3: invoke.cont: // CHECK3-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -2562,7 +2562,7 @@ int main() { // CHECK3-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8 // CHECK3-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7:[0-9]+]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] // CHECK3-NEXT: br label [[EH_RESUME:%.*]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: store i32 100, i32* [[I]], align 4 @@ -2596,16 +2596,16 @@ int main() { // CHECK3-NEXT: store i32 100, i32* [[I7]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i8, i8* [[A]], align 1 // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP13]] to i32 -// CHECK3-NEXT: [[CALL19:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK3-NEXT: [[CALL19:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK3-NEXT: to label [[INVOKE_CONT18:%.*]] unwind label [[LPAD]] // CHECK3: invoke.cont18: // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV]], [[CALL19]] -// CHECK3-NEXT: [[CALL22:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK3-NEXT: [[CALL22:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK3-NEXT: to label [[INVOKE_CONT21:%.*]] unwind label [[LPAD]] // CHECK3: invoke.cont21: // CHECK3-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] // CHECK3-NEXT: store i32 [[ADD23]], i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP14]] // CHECK3: eh.resume: @@ -2623,7 +2623,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -2631,12 +2631,12 @@ int main() { // CHECK3-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2812,17 +2812,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR7]] +// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -2836,7 +2836,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2863,8 +2863,8 @@ int main() { // CHECK4-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[I7:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK4-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK4-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK4-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK4: invoke.cont: // CHECK4-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -2901,7 +2901,7 @@ int main() { // CHECK4-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8 // CHECK4-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7:[0-9]+]] +// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] // CHECK4-NEXT: br label [[EH_RESUME:%.*]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: store i32 100, i32* [[I]], align 4 @@ -2935,16 +2935,16 @@ int main() { // CHECK4-NEXT: store i32 100, i32* [[I7]], align 4 // CHECK4-NEXT: [[TMP13:%.*]] = load i8, i8* [[A]], align 1 // CHECK4-NEXT: [[CONV:%.*]] = sext i8 [[TMP13]] to i32 -// CHECK4-NEXT: [[CALL19:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK4-NEXT: [[CALL19:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK4-NEXT: to label [[INVOKE_CONT18:%.*]] unwind label [[LPAD]] // CHECK4: invoke.cont18: // CHECK4-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV]], [[CALL19]] -// CHECK4-NEXT: [[CALL22:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK4-NEXT: [[CALL22:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK4-NEXT: to label [[INVOKE_CONT21:%.*]] unwind label [[LPAD]] // CHECK4: invoke.cont21: // CHECK4-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] // CHECK4-NEXT: store i32 [[ADD23]], i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7]] +// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP14]] // CHECK4: eh.resume: @@ -2962,7 +2962,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -2970,12 +2970,12 @@ int main() { // CHECK4-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3151,17 +3151,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR7]] +// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -3175,7 +3175,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3198,8 +3198,8 @@ int main() { // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK5-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK5-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK5-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -3217,7 +3217,7 @@ int main() { // CHECK5-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK5-NEXT: br label [[EH_RESUME:%.*]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -3244,16 +3244,16 @@ int main() { // CHECK5: omp_offload.cont3: // CHECK5-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK5-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK5-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK5-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK5-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK5: invoke.cont5: // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK5-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK5-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK5-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK5: invoke.cont7: // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK5-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP17]] // CHECK5: eh.resume: @@ -3265,7 +3265,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -3273,12 +3273,12 @@ int main() { // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3298,7 +3298,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3333,24 +3333,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !9 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !9 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3366,7 +3366,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3411,26 +3411,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !13 +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3447,7 +3447,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK5-NEXT: catch i8* null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !13 +// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]] // CHECK5-NEXT: unreachable // // @@ -3459,7 +3459,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -3469,7 +3469,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3507,26 +3507,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 // CHECK5-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !18 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !18 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3542,7 +3542,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3587,26 +3587,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !21 +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3623,7 +3623,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK5-NEXT: catch i8* null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !21 +// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK5-NEXT: unreachable // // @@ -3676,17 +3676,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK5-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -3707,7 +3707,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3742,24 +3742,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !24 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3775,7 +3775,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3820,26 +3820,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !27 +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3856,7 +3856,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK5-NEXT: catch i8* null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !27 +// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK5-NEXT: unreachable // // @@ -3868,7 +3868,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3903,24 +3903,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !30 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3936,7 +3936,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3981,26 +3981,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !33 +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4017,7 +4017,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK5-NEXT: catch i8* null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !33 +// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK5-NEXT: unreachable // // @@ -4029,7 +4029,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4064,24 +4064,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !36 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4097,7 +4097,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4142,26 +4142,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !39 +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4178,7 +4178,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK5-NEXT: catch i8* null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !39 +// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK5-NEXT: unreachable // // @@ -4190,7 +4190,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4228,40 +4228,40 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !42 +// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: -// CHECK5-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK5-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]], !llvm.access.group !42 +// CHECK5-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK5-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK5: invoke.cont2: // CHECK5-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !42 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !42 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK5: lpad: // CHECK5-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } // CHECK5-NEXT: catch i8* null // CHECK5-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK5-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !42 +// CHECK5-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK5-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 -// CHECK5-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !42 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK5-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4279,16 +4279,16 @@ int main() { // CHECK5-NEXT: [[TMP19:%.*]] = landingpad { i8*, i32 } // CHECK5-NEXT: catch i8* null // CHECK5-NEXT: [[TMP20:%.*]] = extractvalue { i8*, i32 } [[TMP19]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !42 +// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]] // CHECK5-NEXT: unreachable // CHECK5: terminate.handler: -// CHECK5-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !llvm.access.group !42 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !42 +// CHECK5-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] // CHECK5-NEXT: unreachable // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4333,26 +4333,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !45 +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4369,12 +4369,12 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK5-NEXT: catch i8* null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !45 +// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK5-NEXT: unreachable // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4404,8 +4404,8 @@ int main() { // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK6-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK6-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK6-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -4423,7 +4423,7 @@ int main() { // CHECK6-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK6-NEXT: br label [[EH_RESUME:%.*]] // CHECK6: omp_offload.cont: // CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -4450,16 +4450,16 @@ int main() { // CHECK6: omp_offload.cont3: // CHECK6-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK6-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK6-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK6-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK6-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK6: invoke.cont5: // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK6-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK6-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK6-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK6: invoke.cont7: // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK6-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP17]] // CHECK6: eh.resume: @@ -4471,7 +4471,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -4479,12 +4479,12 @@ int main() { // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4504,7 +4504,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4539,24 +4539,24 @@ int main() { // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !9 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !9 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -4572,7 +4572,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4617,26 +4617,26 @@ int main() { // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !13 +// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -4653,7 +4653,7 @@ int main() { // CHECK6-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK6-NEXT: catch i8* null // CHECK6-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !13 +// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]] // CHECK6-NEXT: unreachable // // @@ -4665,7 +4665,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK6-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -4675,7 +4675,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4713,26 +4713,26 @@ int main() { // CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 // CHECK6-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !18 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !18 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -4748,7 +4748,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4793,26 +4793,26 @@ int main() { // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !21 +// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -4829,7 +4829,7 @@ int main() { // CHECK6-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK6-NEXT: catch i8* null // CHECK6-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !21 +// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK6-NEXT: unreachable // // @@ -4882,17 +4882,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK6-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -4913,7 +4913,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4948,24 +4948,24 @@ int main() { // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !24 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -4981,7 +4981,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5026,26 +5026,26 @@ int main() { // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !27 +// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5062,7 +5062,7 @@ int main() { // CHECK6-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK6-NEXT: catch i8* null // CHECK6-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !27 +// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK6-NEXT: unreachable // // @@ -5074,7 +5074,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5109,24 +5109,24 @@ int main() { // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !30 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5142,7 +5142,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5187,26 +5187,26 @@ int main() { // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !33 +// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5223,7 +5223,7 @@ int main() { // CHECK6-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK6-NEXT: catch i8* null // CHECK6-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !33 +// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK6-NEXT: unreachable // // @@ -5235,7 +5235,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5270,24 +5270,24 @@ int main() { // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !36 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5303,7 +5303,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5348,26 +5348,26 @@ int main() { // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !39 +// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5384,7 +5384,7 @@ int main() { // CHECK6-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK6-NEXT: catch i8* null // CHECK6-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !39 +// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK6-NEXT: unreachable // // @@ -5396,7 +5396,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5434,40 +5434,40 @@ int main() { // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !42 +// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) +// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: -// CHECK6-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK6-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]], !llvm.access.group !42 +// CHECK6-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK6-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK6: invoke.cont2: // CHECK6-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !42 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !42 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK6: lpad: // CHECK6-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } // CHECK6-NEXT: catch i8* null // CHECK6-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK6-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !42 +// CHECK6-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK6-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 -// CHECK6-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !42 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !42 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK6-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -5485,16 +5485,16 @@ int main() { // CHECK6-NEXT: [[TMP19:%.*]] = landingpad { i8*, i32 } // CHECK6-NEXT: catch i8* null // CHECK6-NEXT: [[TMP20:%.*]] = extractvalue { i8*, i32 } [[TMP19]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !42 +// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]] // CHECK6-NEXT: unreachable // CHECK6: terminate.handler: -// CHECK6-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !llvm.access.group !42 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !42 +// CHECK6-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] // CHECK6-NEXT: unreachable // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5539,26 +5539,26 @@ int main() { // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !45 +// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5575,12 +5575,12 @@ int main() { // CHECK6-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK6-NEXT: catch i8* null // CHECK6-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !45 +// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK6-NEXT: unreachable // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5614,8 +5614,8 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I7:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK7-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK7-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK7-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK7: invoke.cont: // CHECK7-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -5652,7 +5652,7 @@ int main() { // CHECK7-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8 // CHECK7-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1 // CHECK7-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7:[0-9]+]] +// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] // CHECK7-NEXT: br label [[EH_RESUME:%.*]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 100, i32* [[I]], align 4 @@ -5686,16 +5686,16 @@ int main() { // CHECK7-NEXT: store i32 100, i32* [[I7]], align 4 // CHECK7-NEXT: [[TMP13:%.*]] = load i8, i8* [[A]], align 1 // CHECK7-NEXT: [[CONV:%.*]] = sext i8 [[TMP13]] to i32 -// CHECK7-NEXT: [[CALL19:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK7-NEXT: [[CALL19:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK7-NEXT: to label [[INVOKE_CONT18:%.*]] unwind label [[LPAD]] // CHECK7: invoke.cont18: // CHECK7-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV]], [[CALL19]] -// CHECK7-NEXT: [[CALL22:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK7-NEXT: [[CALL22:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK7-NEXT: to label [[INVOKE_CONT21:%.*]] unwind label [[LPAD]] // CHECK7: invoke.cont21: // CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] // CHECK7-NEXT: store i32 [[ADD23]], i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7]] +// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP14]] // CHECK7: eh.resume: @@ -5713,7 +5713,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -5721,12 +5721,12 @@ int main() { // CHECK7-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5902,17 +5902,17 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR7]] +// CHECK7-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -5926,7 +5926,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5953,8 +5953,8 @@ int main() { // CHECK8-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I7:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK8-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK8-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK8-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK8: invoke.cont: // CHECK8-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -5991,7 +5991,7 @@ int main() { // CHECK8-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8 // CHECK8-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1 // CHECK8-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7:[0-9]+]] +// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] // CHECK8-NEXT: br label [[EH_RESUME:%.*]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 100, i32* [[I]], align 4 @@ -6025,16 +6025,16 @@ int main() { // CHECK8-NEXT: store i32 100, i32* [[I7]], align 4 // CHECK8-NEXT: [[TMP13:%.*]] = load i8, i8* [[A]], align 1 // CHECK8-NEXT: [[CONV:%.*]] = sext i8 [[TMP13]] to i32 -// CHECK8-NEXT: [[CALL19:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK8-NEXT: [[CALL19:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK8-NEXT: to label [[INVOKE_CONT18:%.*]] unwind label [[LPAD]] // CHECK8: invoke.cont18: // CHECK8-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV]], [[CALL19]] -// CHECK8-NEXT: [[CALL22:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK8-NEXT: [[CALL22:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK8-NEXT: to label [[INVOKE_CONT21:%.*]] unwind label [[LPAD]] // CHECK8: invoke.cont21: // CHECK8-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] // CHECK8-NEXT: store i32 [[ADD23]], i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7]] +// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP14]] // CHECK8: eh.resume: @@ -6052,7 +6052,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -6060,12 +6060,12 @@ int main() { // CHECK8-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6241,17 +6241,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR7]] +// CHECK8-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -6265,7 +6265,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6288,8 +6288,8 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK9-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK9-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK9-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK9: invoke.cont: // CHECK9-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -6307,7 +6307,7 @@ int main() { // CHECK9-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK9-NEXT: br label [[EH_RESUME:%.*]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -6334,16 +6334,16 @@ int main() { // CHECK9: omp_offload.cont3: // CHECK9-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK9-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK9-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK9-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK9-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK9: invoke.cont5: // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK9-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK9-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK9-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK9: invoke.cont7: // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK9-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP17]] // CHECK9: eh.resume: @@ -6355,7 +6355,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -6363,12 +6363,12 @@ int main() { // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6388,7 +6388,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6423,24 +6423,24 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !13 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13 +// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !13 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -6456,7 +6456,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6501,26 +6501,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !17 +// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK9: invoke.cont: // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -6537,7 +6537,7 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK9-NEXT: catch i8* null // CHECK9-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !17 +// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]] // CHECK9-NEXT: unreachable // // @@ -6549,7 +6549,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK9-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -6559,7 +6559,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6597,26 +6597,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1, !llvm.access.group !22 +// CHECK9-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 // CHECK9-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !22 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 +// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !22 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -6632,7 +6632,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6677,26 +6677,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !25 +// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK9: invoke.cont: // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -6713,7 +6713,7 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK9-NEXT: catch i8* null // CHECK9-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !25 +// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK9-NEXT: unreachable // // @@ -6766,17 +6766,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK9-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -6790,7 +6790,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6806,7 +6806,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6841,24 +6841,24 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !28 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28 +// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !28 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -6874,7 +6874,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6919,26 +6919,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !31 +// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK9: invoke.cont: // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -6955,7 +6955,7 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK9-NEXT: catch i8* null // CHECK9-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !31 +// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK9-NEXT: unreachable // // @@ -6967,7 +6967,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7002,24 +7002,24 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !34 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34 +// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !34 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -7035,7 +7035,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7080,26 +7080,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !37 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !37 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !37 +// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK9: invoke.cont: // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -7116,7 +7116,7 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK9-NEXT: catch i8* null // CHECK9-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !37 +// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK9-NEXT: unreachable // // @@ -7128,7 +7128,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7163,24 +7163,24 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !40 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40 +// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -7196,7 +7196,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7241,26 +7241,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !43 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !43 +// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK9: invoke.cont: // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -7277,7 +7277,7 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK9-NEXT: catch i8* null // CHECK9-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !43 +// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK9-NEXT: unreachable // // @@ -7289,7 +7289,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7327,40 +7327,40 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !46 +// CHECK9-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) +// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK9: invoke.cont: -// CHECK9-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK9-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]], !llvm.access.group !46 +// CHECK9-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK9-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK9: invoke.cont2: // CHECK9-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !46 -// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !46 +// CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) +// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !46 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !46 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK9: lpad: // CHECK9-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } // CHECK9-NEXT: catch i8* null // CHECK9-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK9-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !46 +// CHECK9-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK9-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !46 -// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46 +// CHECK9-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK9-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK9-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -7378,16 +7378,16 @@ int main() { // CHECK9-NEXT: [[TMP19:%.*]] = landingpad { i8*, i32 } // CHECK9-NEXT: catch i8* null // CHECK9-NEXT: [[TMP20:%.*]] = extractvalue { i8*, i32 } [[TMP19]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !46 +// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]] // CHECK9-NEXT: unreachable // CHECK9: terminate.handler: -// CHECK9-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !llvm.access.group !46 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !46 +// CHECK9-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] // CHECK9-NEXT: unreachable // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7432,26 +7432,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !49 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !49 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !49 +// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK9: invoke.cont: // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -7468,7 +7468,7 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK9-NEXT: catch i8* null // CHECK9-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !49 +// CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK9-NEXT: unreachable // // @@ -7494,8 +7494,8 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK10-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK10-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK10-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK10: invoke.cont: // CHECK10-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -7513,7 +7513,7 @@ int main() { // CHECK10-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK10-NEXT: br label [[EH_RESUME:%.*]] // CHECK10: omp_offload.cont: // CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -7540,16 +7540,16 @@ int main() { // CHECK10: omp_offload.cont3: // CHECK10-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK10-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK10-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK10-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK10-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK10: invoke.cont5: // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK10-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK10-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK10-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK10: invoke.cont7: // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK10-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP17]] // CHECK10: eh.resume: @@ -7561,7 +7561,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -7569,12 +7569,12 @@ int main() { // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -7594,7 +7594,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7629,24 +7629,24 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !13 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !13 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -7662,7 +7662,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7707,26 +7707,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK10-NEXT: invoke void @_Z3foov() -// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !17 +// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK10: invoke.cont: // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -7743,7 +7743,7 @@ int main() { // CHECK10-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK10-NEXT: catch i8* null // CHECK10-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !17 +// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]] // CHECK10-NEXT: unreachable // // @@ -7755,7 +7755,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK10-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -7765,7 +7765,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7803,26 +7803,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1, !llvm.access.group !22 +// CHECK10-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 // CHECK10-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !22 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 +// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !22 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -7838,7 +7838,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7883,26 +7883,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK10-NEXT: invoke void @_Z3foov() -// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !25 +// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK10: invoke.cont: // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -7919,7 +7919,7 @@ int main() { // CHECK10-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK10-NEXT: catch i8* null // CHECK10-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !25 +// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK10-NEXT: unreachable // // @@ -7972,17 +7972,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK10-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -7996,7 +7996,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -8012,7 +8012,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8047,24 +8047,24 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !28 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28 +// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !28 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -8080,7 +8080,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8125,26 +8125,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK10-NEXT: invoke void @_Z3foov() -// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !31 +// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK10: invoke.cont: // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -8161,7 +8161,7 @@ int main() { // CHECK10-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK10-NEXT: catch i8* null // CHECK10-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !31 +// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK10-NEXT: unreachable // // @@ -8173,7 +8173,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8208,24 +8208,24 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !34 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34 +// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !34 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -8241,7 +8241,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8286,26 +8286,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !37 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !37 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK10-NEXT: invoke void @_Z3foov() -// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !37 +// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK10: invoke.cont: // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -8322,7 +8322,7 @@ int main() { // CHECK10-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK10-NEXT: catch i8* null // CHECK10-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !37 +// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK10-NEXT: unreachable // // @@ -8334,7 +8334,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8369,24 +8369,24 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !40 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40 +// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -8402,7 +8402,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8447,26 +8447,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !43 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK10-NEXT: invoke void @_Z3foov() -// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !43 +// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK10: invoke.cont: // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -8483,7 +8483,7 @@ int main() { // CHECK10-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK10-NEXT: catch i8* null // CHECK10-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !43 +// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK10-NEXT: unreachable // // @@ -8495,7 +8495,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8533,40 +8533,40 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) -// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !46 +// CHECK10-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) +// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK10: invoke.cont: -// CHECK10-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK10-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]], !llvm.access.group !46 +// CHECK10-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK10-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK10: invoke.cont2: // CHECK10-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !46 -// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !46 +// CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) +// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !46 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !46 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK10: lpad: // CHECK10-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } // CHECK10-NEXT: catch i8* null // CHECK10-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK10-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !46 +// CHECK10-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK10-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !46 -// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46 +// CHECK10-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK10-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK10-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8584,16 +8584,16 @@ int main() { // CHECK10-NEXT: [[TMP19:%.*]] = landingpad { i8*, i32 } // CHECK10-NEXT: catch i8* null // CHECK10-NEXT: [[TMP20:%.*]] = extractvalue { i8*, i32 } [[TMP19]], 0 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !46 +// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]] // CHECK10-NEXT: unreachable // CHECK10: terminate.handler: -// CHECK10-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !llvm.access.group !46 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !46 +// CHECK10-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] // CHECK10-NEXT: unreachable // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8638,26 +8638,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !49 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !49 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK10-NEXT: invoke void @_Z3foov() -// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !49 +// CHECK10-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK10: invoke.cont: // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -8674,7 +8674,7 @@ int main() { // CHECK10-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK10-NEXT: catch i8* null // CHECK10-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !49 +// CHECK10-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK10-NEXT: unreachable // // @@ -8704,8 +8704,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I7:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK11-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK11-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK11-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK11-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK11: invoke.cont: // CHECK11-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -8742,7 +8742,7 @@ int main() { // CHECK11-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8 // CHECK11-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK11-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7:[0-9]+]] +// CHECK11-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] // CHECK11-NEXT: br label [[EH_RESUME:%.*]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: store i32 100, i32* [[I]], align 4 @@ -8776,16 +8776,16 @@ int main() { // CHECK11-NEXT: store i32 100, i32* [[I7]], align 4 // CHECK11-NEXT: [[TMP13:%.*]] = load i8, i8* [[A]], align 1 // CHECK11-NEXT: [[CONV:%.*]] = sext i8 [[TMP13]] to i32 -// CHECK11-NEXT: [[CALL19:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK11-NEXT: [[CALL19:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK11-NEXT: to label [[INVOKE_CONT18:%.*]] unwind label [[LPAD]] // CHECK11: invoke.cont18: // CHECK11-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV]], [[CALL19]] -// CHECK11-NEXT: [[CALL22:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK11-NEXT: [[CALL22:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK11-NEXT: to label [[INVOKE_CONT21:%.*]] unwind label [[LPAD]] // CHECK11: invoke.cont21: // CHECK11-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] // CHECK11-NEXT: store i32 [[ADD23]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7]] +// CHECK11-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP14]] // CHECK11: eh.resume: @@ -8803,7 +8803,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -8811,12 +8811,12 @@ int main() { // CHECK11-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -8992,17 +8992,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR7]] +// CHECK11-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -9016,7 +9016,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -9043,8 +9043,8 @@ int main() { // CHECK12-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[I7:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK12-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK12-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK12-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK12-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK12: invoke.cont: // CHECK12-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -9081,7 +9081,7 @@ int main() { // CHECK12-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8 // CHECK12-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK12-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7:[0-9]+]] +// CHECK12-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] // CHECK12-NEXT: br label [[EH_RESUME:%.*]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: store i32 100, i32* [[I]], align 4 @@ -9115,16 +9115,16 @@ int main() { // CHECK12-NEXT: store i32 100, i32* [[I7]], align 4 // CHECK12-NEXT: [[TMP13:%.*]] = load i8, i8* [[A]], align 1 // CHECK12-NEXT: [[CONV:%.*]] = sext i8 [[TMP13]] to i32 -// CHECK12-NEXT: [[CALL19:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK12-NEXT: [[CALL19:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK12-NEXT: to label [[INVOKE_CONT18:%.*]] unwind label [[LPAD]] // CHECK12: invoke.cont18: // CHECK12-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV]], [[CALL19]] -// CHECK12-NEXT: [[CALL22:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK12-NEXT: [[CALL22:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK12-NEXT: to label [[INVOKE_CONT21:%.*]] unwind label [[LPAD]] // CHECK12: invoke.cont21: // CHECK12-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] // CHECK12-NEXT: store i32 [[ADD23]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7]] +// CHECK12-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP14]] // CHECK12: eh.resume: @@ -9142,7 +9142,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -9150,12 +9150,12 @@ int main() { // CHECK12-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -9331,17 +9331,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR7]] +// CHECK12-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -9355,7 +9355,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -9378,8 +9378,8 @@ int main() { // CHECK13-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK13-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK13-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK13-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK13: invoke.cont: // CHECK13-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -9397,7 +9397,7 @@ int main() { // CHECK13-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK13-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK13-NEXT: br label [[EH_RESUME:%.*]] // CHECK13: omp_offload.cont: // CHECK13-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -9424,16 +9424,16 @@ int main() { // CHECK13: omp_offload.cont3: // CHECK13-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK13-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK13-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK13-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK13-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK13: invoke.cont5: // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK13-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK13-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK13-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK13: invoke.cont7: // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK13-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP17]] // CHECK13: eh.resume: @@ -9445,7 +9445,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -9453,12 +9453,12 @@ int main() { // CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -9478,7 +9478,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9513,24 +9513,24 @@ int main() { // CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !13 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13 +// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !13 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -9546,7 +9546,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9591,26 +9591,26 @@ int main() { // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !17 +// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK13: invoke.cont: // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -9627,7 +9627,7 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK13-NEXT: catch i8* null // CHECK13-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !17 +// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]] // CHECK13-NEXT: unreachable // // @@ -9639,7 +9639,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK13-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK13-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -9649,7 +9649,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9687,26 +9687,26 @@ int main() { // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1, !llvm.access.group !22 +// CHECK13-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 // CHECK13-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !22 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 +// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !22 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -9722,7 +9722,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9767,26 +9767,26 @@ int main() { // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !25 +// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK13: invoke.cont: // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -9803,7 +9803,7 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK13-NEXT: catch i8* null // CHECK13-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !25 +// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK13-NEXT: unreachable // // @@ -9856,17 +9856,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK13-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -9887,7 +9887,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9922,24 +9922,24 @@ int main() { // CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !28 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28 +// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !28 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -9955,7 +9955,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10000,26 +10000,26 @@ int main() { // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !31 +// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK13: invoke.cont: // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -10036,7 +10036,7 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK13-NEXT: catch i8* null // CHECK13-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !31 +// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK13-NEXT: unreachable // // @@ -10048,7 +10048,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10083,24 +10083,24 @@ int main() { // CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !34 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34 +// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !34 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -10116,7 +10116,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10161,26 +10161,26 @@ int main() { // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !37 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !37 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !37 +// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK13: invoke.cont: // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -10197,7 +10197,7 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK13-NEXT: catch i8* null // CHECK13-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !37 +// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK13-NEXT: unreachable // // @@ -10209,7 +10209,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10244,24 +10244,24 @@ int main() { // CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !40 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40 +// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -10277,7 +10277,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10322,26 +10322,26 @@ int main() { // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !43 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !43 +// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK13: invoke.cont: // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -10358,7 +10358,7 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK13-NEXT: catch i8* null // CHECK13-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !43 +// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK13-NEXT: unreachable // // @@ -10370,7 +10370,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10408,40 +10408,40 @@ int main() { // CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !46 +// CHECK13-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) +// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK13: invoke.cont: -// CHECK13-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK13-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]], !llvm.access.group !46 +// CHECK13-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK13-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK13: invoke.cont2: // CHECK13-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !46 -// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !46 +// CHECK13-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) +// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !46 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !46 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK13: lpad: // CHECK13-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } // CHECK13-NEXT: catch i8* null // CHECK13-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK13-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !46 +// CHECK13-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK13-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 -// CHECK13-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !46 -// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46 +// CHECK13-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK13-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK13-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10459,16 +10459,16 @@ int main() { // CHECK13-NEXT: [[TMP19:%.*]] = landingpad { i8*, i32 } // CHECK13-NEXT: catch i8* null // CHECK13-NEXT: [[TMP20:%.*]] = extractvalue { i8*, i32 } [[TMP19]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !46 +// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]] // CHECK13-NEXT: unreachable // CHECK13: terminate.handler: -// CHECK13-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !llvm.access.group !46 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !46 +// CHECK13-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] // CHECK13-NEXT: unreachable // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10513,26 +10513,26 @@ int main() { // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !49 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !49 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !49 +// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK13: invoke.cont: // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -10549,12 +10549,12 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK13-NEXT: catch i8* null // CHECK13-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !49 +// CHECK13-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK13-NEXT: unreachable // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -10584,8 +10584,8 @@ int main() { // CHECK14-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 // CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK14-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK14-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK14-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK14: invoke.cont: // CHECK14-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -10603,7 +10603,7 @@ int main() { // CHECK14-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK14-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK14-NEXT: br label [[EH_RESUME:%.*]] // CHECK14: omp_offload.cont: // CHECK14-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -10630,16 +10630,16 @@ int main() { // CHECK14: omp_offload.cont3: // CHECK14-NEXT: [[TMP16:%.*]] = load i8, i8* [[A]], align 1 // CHECK14-NEXT: [[CONV4:%.*]] = sext i8 [[TMP16]] to i32 -// CHECK14-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK14-NEXT: [[CALL6:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK14-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK14: invoke.cont5: // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK14-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK14-NEXT: [[CALL8:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK14-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK14: invoke.cont7: // CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK14-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP17]] // CHECK14: eh.resume: @@ -10651,7 +10651,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -10659,12 +10659,12 @@ int main() { // CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -10684,7 +10684,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10719,24 +10719,24 @@ int main() { // CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !13 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13 +// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !13 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -10752,7 +10752,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10797,26 +10797,26 @@ int main() { // CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK14-NEXT: invoke void @_Z3foov() -// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !17 +// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK14: invoke.cont: // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -10833,7 +10833,7 @@ int main() { // CHECK14-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK14-NEXT: catch i8* null // CHECK14-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]], !llvm.access.group !17 +// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10:[0-9]+]] // CHECK14-NEXT: unreachable // // @@ -10845,7 +10845,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK14-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK14-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 @@ -10855,7 +10855,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR3]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10893,26 +10893,26 @@ int main() { // CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1, !llvm.access.group !22 +// CHECK14-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP0]], align 1 // CHECK14-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group !22 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 +// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]) +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !22 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP11]], i64 [[TMP13]]) // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -10928,7 +10928,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10973,26 +10973,26 @@ int main() { // CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK14-NEXT: invoke void @_Z3foov() -// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !25 +// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK14: invoke.cont: // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -11009,7 +11009,7 @@ int main() { // CHECK14-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK14-NEXT: catch i8* null // CHECK14-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !25 +// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK14-NEXT: unreachable // // @@ -11062,17 +11062,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK14-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -11093,7 +11093,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11128,24 +11128,24 @@ int main() { // CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !28 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28 +// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !28 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -11161,7 +11161,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11206,26 +11206,26 @@ int main() { // CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK14-NEXT: invoke void @_Z3foov() -// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !31 +// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK14: invoke.cont: // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -11242,7 +11242,7 @@ int main() { // CHECK14-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK14-NEXT: catch i8* null // CHECK14-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !31 +// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK14-NEXT: unreachable // // @@ -11254,7 +11254,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11289,24 +11289,24 @@ int main() { // CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !34 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34 +// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !34 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -11322,7 +11322,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11367,26 +11367,26 @@ int main() { // CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !37 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !37 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK14-NEXT: invoke void @_Z3foov() -// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !37 +// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK14: invoke.cont: // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -11403,7 +11403,7 @@ int main() { // CHECK14-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK14-NEXT: catch i8* null // CHECK14-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !37 +// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK14-NEXT: unreachable // // @@ -11415,7 +11415,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11450,24 +11450,24 @@ int main() { // CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !40 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40 +// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -11483,7 +11483,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11528,26 +11528,26 @@ int main() { // CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !43 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK14-NEXT: invoke void @_Z3foov() -// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !43 +// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK14: invoke.cont: // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -11564,7 +11564,7 @@ int main() { // CHECK14-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK14-NEXT: catch i8* null // CHECK14-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !43 +// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK14-NEXT: unreachable // // @@ -11576,7 +11576,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11614,40 +11614,40 @@ int main() { // CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) -// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !46 +// CHECK14-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) +// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK14: invoke.cont: -// CHECK14-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK14-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]], !llvm.access.group !46 +// CHECK14-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK14-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] // CHECK14: invoke.cont2: // CHECK14-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group !46 -// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !46 +// CHECK14-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) +// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group !46 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]]) // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !46 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK14: lpad: // CHECK14-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } // CHECK14-NEXT: catch i8* null // CHECK14-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 -// CHECK14-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8, !llvm.access.group !46 +// CHECK14-NEXT: store i8* [[TMP15]], i8** [[EXN_SLOT]], align 8 // CHECK14-NEXT: [[TMP16:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 1 -// CHECK14-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4, !llvm.access.group !46 -// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]], !llvm.access.group !46 +// CHECK14-NEXT: store i32 [[TMP16]], i32* [[EHSELECTOR_SLOT]], align 4 +// CHECK14-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK14-NEXT: br label [[TERMINATE_HANDLER:%.*]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -11665,16 +11665,16 @@ int main() { // CHECK14-NEXT: [[TMP19:%.*]] = landingpad { i8*, i32 } // CHECK14-NEXT: catch i8* null // CHECK14-NEXT: [[TMP20:%.*]] = extractvalue { i8*, i32 } [[TMP19]], 0 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]], !llvm.access.group !46 +// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP20]]) #[[ATTR10]] // CHECK14-NEXT: unreachable // CHECK14: terminate.handler: -// CHECK14-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !llvm.access.group !46 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]], !llvm.access.group !46 +// CHECK14-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8 +// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR10]] // CHECK14-NEXT: unreachable // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11719,26 +11719,26 @@ int main() { // CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !49 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !49 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK14-NEXT: invoke void @_Z3foov() -// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !49 +// CHECK14-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK14: invoke.cont: // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -11755,12 +11755,12 @@ int main() { // CHECK14-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK14-NEXT: catch i8* null // CHECK14-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]], !llvm.access.group !49 +// CHECK14-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR10]] // CHECK14-NEXT: unreachable // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -11794,8 +11794,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I7:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK15-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK15-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK15-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK15-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK15: invoke.cont: // CHECK15-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -11832,7 +11832,7 @@ int main() { // CHECK15-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8 // CHECK15-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1 // CHECK15-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK15-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] // CHECK15-NEXT: br label [[EH_RESUME:%.*]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 100, i32* [[I]], align 4 @@ -11866,16 +11866,16 @@ int main() { // CHECK15-NEXT: store i32 100, i32* [[I7]], align 4 // CHECK15-NEXT: [[TMP13:%.*]] = load i8, i8* [[A]], align 1 // CHECK15-NEXT: [[CONV:%.*]] = sext i8 [[TMP13]] to i32 -// CHECK15-NEXT: [[CALL19:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK15-NEXT: [[CALL19:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK15-NEXT: to label [[INVOKE_CONT18:%.*]] unwind label [[LPAD]] // CHECK15: invoke.cont18: // CHECK15-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV]], [[CALL19]] -// CHECK15-NEXT: [[CALL22:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK15-NEXT: [[CALL22:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK15-NEXT: to label [[INVOKE_CONT21:%.*]] unwind label [[LPAD]] // CHECK15: invoke.cont21: // CHECK15-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] // CHECK15-NEXT: store i32 [[ADD23]], i32* [[RETVAL]], align 4 -// CHECK15-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7]] +// CHECK15-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP14]] // CHECK15: eh.resume: @@ -11893,7 +11893,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -11901,12 +11901,12 @@ int main() { // CHECK15-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK15-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -12082,17 +12082,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR7]] +// CHECK15-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -12106,7 +12106,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -12133,8 +12133,8 @@ int main() { // CHECK16-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[I7:%.*]] = alloca i32, align 4 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK16-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK16-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK16-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK16-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK16: invoke.cont: // CHECK16-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -12171,7 +12171,7 @@ int main() { // CHECK16-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8 // CHECK16-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1 // CHECK16-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK16-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7:[0-9]+]] // CHECK16-NEXT: br label [[EH_RESUME:%.*]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: store i32 100, i32* [[I]], align 4 @@ -12205,16 +12205,16 @@ int main() { // CHECK16-NEXT: store i32 100, i32* [[I7]], align 4 // CHECK16-NEXT: [[TMP13:%.*]] = load i8, i8* [[A]], align 1 // CHECK16-NEXT: [[CONV:%.*]] = sext i8 [[TMP13]] to i32 -// CHECK16-NEXT: [[CALL19:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() +// CHECK16-NEXT: [[CALL19:%.*]] = invoke i32 @_Z5tmainIcLi5EEiv() // CHECK16-NEXT: to label [[INVOKE_CONT18:%.*]] unwind label [[LPAD]] // CHECK16: invoke.cont18: // CHECK16-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV]], [[CALL19]] -// CHECK16-NEXT: [[CALL22:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() +// CHECK16-NEXT: [[CALL22:%.*]] = invoke i32 @_Z5tmainI1SLi1EEiv() // CHECK16-NEXT: to label [[INVOKE_CONT21:%.*]] unwind label [[LPAD]] // CHECK16: invoke.cont21: // CHECK16-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] // CHECK16-NEXT: store i32 [[ADD23]], i32* [[RETVAL]], align 4 -// CHECK16-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR7]] +// CHECK16-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR7]] // CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP14]] // CHECK16: eh.resume: @@ -12232,7 +12232,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -12240,12 +12240,12 @@ int main() { // CHECK16-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK16-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK16-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -12421,17 +12421,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK16-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR7]] +// CHECK16-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR7]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -12445,7 +12445,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp index 7e8c25351da74d9e61187ad8951dfda90378ca33..74ecab164c119ec67b11d060d546bc41e2128076 100644 --- a/clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp @@ -144,7 +144,7 @@ int main() { // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK1-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // @@ -156,7 +156,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -199,23 +199,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !4 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -231,7 +231,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -285,38 +285,38 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP10:%.*]] = load double*, double** [[_TMP3]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: store double 1.000000e+00, double* [[G]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load double*, double** [[_TMP3]], align 8 +// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8 +// CHECK1-NEXT: store i32 3, i32* [[SVAR]], align 4 +// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK1-NEXT: store double* [[G]], double** [[TMP11]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: store double* [[G]], double** [[TMP11]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP3]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP3]], align 8 +// CHECK1-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK1-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK1-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK1-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 8 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -347,7 +347,7 @@ int main() { // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK2-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // @@ -359,7 +359,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -402,23 +402,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !4 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -434,7 +434,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -488,38 +488,38 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP10:%.*]] = load double*, double** [[_TMP3]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: store double 1.000000e+00, double* [[G]], align 8 +// CHECK2-NEXT: [[TMP10:%.*]] = load double*, double** [[_TMP3]], align 8 +// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 8 +// CHECK2-NEXT: store i32 3, i32* [[SVAR]], align 4 +// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK2-NEXT: store double* [[G]], double** [[TMP11]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: store double* [[G]], double** [[TMP11]], align 8 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP3]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP3]], align 8 +// CHECK2-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK2-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 8 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK2-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK2-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 8 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -550,7 +550,7 @@ int main() { // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK3-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // @@ -562,7 +562,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -605,21 +605,21 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !5 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -635,7 +635,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -687,38 +687,38 @@ int main() { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP10:%.*]] = load double*, double** [[_TMP2]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: store double 1.000000e+00, double* [[G]], align 8 +// CHECK3-NEXT: [[TMP10:%.*]] = load double*, double** [[_TMP2]], align 4 +// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 4 +// CHECK3-NEXT: store i32 3, i32* [[SVAR]], align 4 +// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK3-NEXT: store double* [[G]], double** [[TMP11]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store double* [[G]], double** [[TMP11]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP2]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store double* [[TMP13]], double** [[TMP12]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP2]], align 4 +// CHECK3-NEXT: store double* [[TMP13]], double** [[TMP12]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK3-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK3-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !9 +// CHECK3-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 4 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -749,7 +749,7 @@ int main() { // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // @@ -761,7 +761,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -804,21 +804,21 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !5 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -834,7 +834,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -886,38 +886,38 @@ int main() { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP10:%.*]] = load double*, double** [[_TMP2]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: store double 1.000000e+00, double* [[G]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = load double*, double** [[_TMP2]], align 4 +// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP10]], align 4 +// CHECK4-NEXT: store i32 3, i32* [[SVAR]], align 4 +// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK4-NEXT: store double* [[G]], double** [[TMP11]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store double* [[G]], double** [[TMP11]], align 4 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP2]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store double* [[TMP13]], double** [[TMP12]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP2]], align 4 +// CHECK4-NEXT: store double* [[TMP13]], double** [[TMP12]], align 4 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK4-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32* [[SVAR]], i32** [[TMP14]], align 4 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK4-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !9 +// CHECK4-NEXT: store float* [[SFVAR]], float** [[TMP15]], align 4 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -948,7 +948,7 @@ int main() { // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // @@ -961,7 +961,7 @@ int main() { // CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // @@ -974,7 +974,7 @@ int main() { // CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK7-NEXT: ret i32 0 // // @@ -987,7 +987,7 @@ int main() { // CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK8-NEXT: ret i32 0 // // @@ -1006,14 +1006,14 @@ int main() { // CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) @@ -1024,7 +1024,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1032,27 +1032,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP4]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1060,7 +1060,7 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // @@ -1072,7 +1072,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1102,12 +1102,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1127,25 +1127,25 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !5 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1159,14 +1159,14 @@ int main() { // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done5: @@ -1174,7 +1174,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1214,12 +1214,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP3]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -1239,37 +1239,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP3]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP3]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK9-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* // CHECK9-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP12]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !9 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1283,14 +1283,14 @@ int main() { // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done9: @@ -1298,12 +1298,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1318,14 +1318,14 @@ int main() { // CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -1343,17 +1343,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP4]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1364,7 +1364,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1378,7 +1378,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1387,17 +1387,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1405,7 +1405,7 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // @@ -1417,7 +1417,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1446,12 +1446,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1471,25 +1471,25 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !14 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1503,14 +1503,14 @@ int main() { // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done5: @@ -1518,7 +1518,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1557,12 +1557,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -1582,37 +1582,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK9-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* // CHECK9-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !17 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1626,14 +1626,14 @@ int main() { // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done9: @@ -1641,17 +1641,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1662,7 +1662,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1676,7 +1676,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1706,14 +1706,14 @@ int main() { // CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) @@ -1724,7 +1724,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1732,27 +1732,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP4]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1760,7 +1760,7 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // @@ -1772,7 +1772,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1802,12 +1802,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1827,25 +1827,25 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !5 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -1859,14 +1859,14 @@ int main() { // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done5: @@ -1874,7 +1874,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1914,12 +1914,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP3]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -1939,37 +1939,37 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP3]], align 8, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP3]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 // CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK10-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* // CHECK10-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP12]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !9 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -1983,14 +1983,14 @@ int main() { // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done9: @@ -1998,12 +1998,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -2018,14 +2018,14 @@ int main() { // CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -2043,17 +2043,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP4]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2064,7 +2064,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2078,7 +2078,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2087,17 +2087,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2105,7 +2105,7 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // @@ -2117,7 +2117,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2146,12 +2146,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2171,25 +2171,25 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !14 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2203,14 +2203,14 @@ int main() { // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done5: @@ -2218,7 +2218,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2257,12 +2257,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2282,37 +2282,37 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 // CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK10-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* // CHECK10-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !17 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2326,14 +2326,14 @@ int main() { // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done9: @@ -2341,17 +2341,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2362,7 +2362,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2376,7 +2376,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2406,14 +2406,14 @@ int main() { // CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) @@ -2424,7 +2424,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2432,27 +2432,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP4]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2460,7 +2460,7 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // @@ -2472,7 +2472,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2502,12 +2502,12 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2527,23 +2527,23 @@ int main() { // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !6 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -2557,14 +2557,14 @@ int main() { // CHECK11-NEXT: store i32 2, i32* [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done5: @@ -2572,7 +2572,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2610,12 +2610,12 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2635,35 +2635,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK11-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* // CHECK11-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP12]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !10 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -2677,14 +2677,14 @@ int main() { // CHECK11-NEXT: store i32 2, i32* [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -2692,12 +2692,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2712,14 +2712,14 @@ int main() { // CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -2737,17 +2737,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP4]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2758,7 +2758,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2772,7 +2772,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2781,17 +2781,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2799,7 +2799,7 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // @@ -2811,7 +2811,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2840,12 +2840,12 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2865,23 +2865,23 @@ int main() { // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !15 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -2895,14 +2895,14 @@ int main() { // CHECK11-NEXT: store i32 2, i32* [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done5: @@ -2910,7 +2910,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2947,12 +2947,12 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2972,35 +2972,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK11-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* // CHECK11-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !18 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -3014,14 +3014,14 @@ int main() { // CHECK11-NEXT: store i32 2, i32* [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -3029,17 +3029,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3050,7 +3050,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3064,7 +3064,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3094,14 +3094,14 @@ int main() { // CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) @@ -3112,7 +3112,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l95() #[[ATTR4:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -3120,27 +3120,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP4]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3148,7 +3148,7 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // @@ -3160,7 +3160,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3190,12 +3190,12 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -3215,23 +3215,23 @@ int main() { // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !6 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3245,14 +3245,14 @@ int main() { // CHECK12-NEXT: store i32 2, i32* [[I]], align 4 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK12: .omp.final.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done5: @@ -3260,7 +3260,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3298,12 +3298,12 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -3323,35 +3323,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK12-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* // CHECK12-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP12]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !10 +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3365,14 +3365,14 @@ int main() { // CHECK12-NEXT: store i32 2, i32* [[I]], align 4 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK12: .omp.final.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done7: @@ -3380,12 +3380,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // @@ -3400,14 +3400,14 @@ int main() { // CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -3425,17 +3425,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP4]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3446,7 +3446,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3460,7 +3460,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3469,17 +3469,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3487,7 +3487,7 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // @@ -3499,7 +3499,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3528,12 +3528,12 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -3553,23 +3553,23 @@ int main() { // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !15 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3583,14 +3583,14 @@ int main() { // CHECK12-NEXT: store i32 2, i32* [[I]], align 4 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK12: .omp.final.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done5: @@ -3598,7 +3598,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3635,12 +3635,12 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -3660,35 +3660,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK12-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* // CHECK12-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !18 +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3702,14 +3702,14 @@ int main() { // CHECK12-NEXT: store i32 2, i32* [[I]], align 4 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK12: .omp.final.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done7: @@ -3717,17 +3717,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3738,7 +3738,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3752,7 +3752,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3792,14 +3792,14 @@ int main() { // CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3811,12 +3811,12 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK13-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -3853,18 +3853,18 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 @@ -3872,27 +3872,27 @@ int main() { // CHECK13: arraydestroy.body13: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK13: arraydestroy.done17: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP14]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3900,17 +3900,17 @@ int main() { // CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // @@ -3934,14 +3934,14 @@ int main() { // CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3953,12 +3953,12 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK13-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -3995,14 +3995,14 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -4013,17 +4013,17 @@ int main() { // CHECK13: arraydestroy.body13: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK13: arraydestroy.done17: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP14]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4034,7 +4034,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4043,7 +4043,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4057,17 +4057,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4075,22 +4075,22 @@ int main() { // CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4101,7 +4101,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4115,7 +4115,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4148,14 +4148,14 @@ int main() { // CHECK14-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -4167,12 +4167,12 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK14-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -4209,18 +4209,18 @@ int main() { // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done11: -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 @@ -4228,27 +4228,27 @@ int main() { // CHECK14: arraydestroy.body13: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK14: arraydestroy.done17: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP14]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4256,17 +4256,17 @@ int main() { // CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // @@ -4290,14 +4290,14 @@ int main() { // CHECK14-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK14-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK14-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -4309,12 +4309,12 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK14-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -4351,14 +4351,14 @@ int main() { // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done11: @@ -4369,17 +4369,17 @@ int main() { // CHECK14: arraydestroy.body13: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK14: arraydestroy.done17: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP14]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4390,7 +4390,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4399,7 +4399,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4413,17 +4413,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4431,22 +4431,22 @@ int main() { // CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4457,7 +4457,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4471,7 +4471,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4504,14 +4504,14 @@ int main() { // CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -4523,12 +4523,12 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK15-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -4563,18 +4563,18 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 @@ -4582,27 +4582,27 @@ int main() { // CHECK15: arraydestroy.body12: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK15: arraydestroy.done16: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP14]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4610,17 +4610,17 @@ int main() { // CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // @@ -4644,14 +4644,14 @@ int main() { // CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -4663,12 +4663,12 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -4703,14 +4703,14 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: @@ -4721,17 +4721,17 @@ int main() { // CHECK15: arraydestroy.body12: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK15: arraydestroy.done16: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP14]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4742,7 +4742,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4751,7 +4751,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4765,17 +4765,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4783,22 +4783,22 @@ int main() { // CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4809,7 +4809,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4823,7 +4823,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4856,14 +4856,14 @@ int main() { // CHECK16-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -4875,12 +4875,12 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK16-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -4915,18 +4915,18 @@ int main() { // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK16-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done10: -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 @@ -4934,27 +4934,27 @@ int main() { // CHECK16: arraydestroy.body12: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK16: arraydestroy.done16: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP14]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4962,17 +4962,17 @@ int main() { // CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // @@ -4996,14 +4996,14 @@ int main() { // CHECK16-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK16-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK16-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -5015,12 +5015,12 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -5055,14 +5055,14 @@ int main() { // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done10: @@ -5073,17 +5073,17 @@ int main() { // CHECK16: arraydestroy.body12: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK16: arraydestroy.done16: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP14]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5094,7 +5094,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5103,7 +5103,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5117,17 +5117,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5135,22 +5135,22 @@ int main() { // CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5161,7 +5161,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5175,7 +5175,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp index c911fd3715777d12e1536d49e6a4f3a209b4938b..e34d2366fa3df0d7ba0ca5bc07a1b3a5661f6db6 100644 --- a/clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp @@ -76,7 +76,7 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41() #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT3]] // CHECK1: omp_offload.cont3: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -88,7 +88,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -123,24 +123,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group !6 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !6 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -156,7 +156,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -201,23 +201,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -240,7 +240,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -275,24 +275,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group !15 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -308,7 +308,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -353,23 +353,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -407,7 +407,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -442,24 +442,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !21 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !21 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -475,7 +475,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -520,23 +520,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -581,7 +581,7 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41() #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT3]] // CHECK2: omp_offload.cont3: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -593,7 +593,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -628,24 +628,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group !6 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !6 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -661,7 +661,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -706,23 +706,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -745,7 +745,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -780,24 +780,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group !15 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -813,7 +813,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -858,23 +858,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -912,7 +912,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -947,24 +947,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !21 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !21 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -980,7 +980,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1025,23 +1025,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1128,7 +1128,7 @@ int main() { // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK3: omp.inner.for.end15: // CHECK3-NEXT: store i32 1000, i32* [[I6]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -1233,7 +1233,7 @@ int main() { // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK4: omp.inner.for.end15: // CHECK4-NEXT: store i32 1000, i32* [[I6]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // diff --git a/clang/test/OpenMP/distribute_private_codegen.cpp b/clang/test/OpenMP/distribute_private_codegen.cpp index 08a4fb8966a8d776e93219369f46c2eaa9c11afe..5b0eddeba9501ae38dc85e0e7f823f1693426274 100644 --- a/clang/test/OpenMP/distribute_private_codegen.cpp +++ b/clang/test/OpenMP/distribute_private_codegen.cpp @@ -123,7 +123,7 @@ int main() { // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK1-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // @@ -135,7 +135,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -202,7 +202,7 @@ int main() { // CHECK1-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -234,7 +234,7 @@ int main() { // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK2-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // @@ -246,7 +246,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -313,7 +313,7 @@ int main() { // CHECK2-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 8 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -345,7 +345,7 @@ int main() { // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK3-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // @@ -357,7 +357,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -424,7 +424,7 @@ int main() { // CHECK3-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -456,7 +456,7 @@ int main() { // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // @@ -468,7 +468,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -535,7 +535,7 @@ int main() { // CHECK4-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 4 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -575,14 +575,14 @@ int main() { // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) @@ -601,7 +601,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102() #[[ATTR4]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT4]] // CHECK9: omp_offload.cont4: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -609,27 +609,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done5: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP6]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -637,7 +637,7 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // @@ -649,7 +649,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -679,12 +679,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -741,14 +741,14 @@ int main() { // CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done8: @@ -756,12 +756,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -773,7 +773,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -844,14 +844,14 @@ int main() { // CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -869,17 +869,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP4]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -890,7 +890,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -904,7 +904,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -913,17 +913,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -931,7 +931,7 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // @@ -943,7 +943,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -972,12 +972,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1034,14 +1034,14 @@ int main() { // CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done8: @@ -1049,17 +1049,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1070,7 +1070,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1084,7 +1084,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1116,14 +1116,14 @@ int main() { // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) @@ -1142,7 +1142,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102() #[[ATTR4]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT4]] // CHECK10: omp_offload.cont4: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1150,27 +1150,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done5: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP6]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1178,7 +1178,7 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // @@ -1190,7 +1190,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1220,12 +1220,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1282,14 +1282,14 @@ int main() { // CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done8: @@ -1297,12 +1297,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -1314,7 +1314,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1385,14 +1385,14 @@ int main() { // CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -1410,17 +1410,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP4]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1431,7 +1431,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1445,7 +1445,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1454,17 +1454,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1472,7 +1472,7 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // @@ -1484,7 +1484,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1513,12 +1513,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1575,14 +1575,14 @@ int main() { // CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done8: @@ -1590,17 +1590,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1611,7 +1611,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1625,7 +1625,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1657,14 +1657,14 @@ int main() { // CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) @@ -1683,7 +1683,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102() #[[ATTR4]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT4]] // CHECK11: omp_offload.cont4: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -1691,27 +1691,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done5: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP6]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1719,7 +1719,7 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // @@ -1731,7 +1731,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1761,12 +1761,12 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1821,14 +1821,14 @@ int main() { // CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -1836,12 +1836,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1853,7 +1853,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1924,14 +1924,14 @@ int main() { // CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -1949,17 +1949,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP4]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1970,7 +1970,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1984,7 +1984,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1993,17 +1993,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2011,7 +2011,7 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // @@ -2023,7 +2023,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2052,12 +2052,12 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2112,14 +2112,14 @@ int main() { // CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -2127,17 +2127,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2148,7 +2148,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2162,7 +2162,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2194,14 +2194,14 @@ int main() { // CHECK12-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) @@ -2220,7 +2220,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102() #[[ATTR4]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT4]] // CHECK12: omp_offload.cont4: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2228,27 +2228,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done5: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP6]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2256,7 +2256,7 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // @@ -2268,7 +2268,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2298,12 +2298,12 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2358,14 +2358,14 @@ int main() { // CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done7: @@ -2373,12 +2373,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // @@ -2390,7 +2390,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2461,14 +2461,14 @@ int main() { // CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -2486,17 +2486,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP4]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2507,7 +2507,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2521,7 +2521,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2530,17 +2530,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2548,7 +2548,7 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // @@ -2560,7 +2560,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2589,12 +2589,12 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2649,14 +2649,14 @@ int main() { // CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done7: @@ -2664,17 +2664,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2685,7 +2685,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2699,7 +2699,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2713,3 +2713,4 @@ int main() { // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/distribute_simd_codegen.cpp b/clang/test/OpenMP/distribute_simd_codegen.cpp index 093adcdf61adb948e28244622f8dc80b68fceb00..d79f71d8fd1a9c39f96b976dea3848c4c991b52d 100644 --- a/clang/test/OpenMP/distribute_simd_codegen.cpp +++ b/clang/test/OpenMP/distribute_simd_codegen.cpp @@ -145,7 +145,7 @@ int fint(void) { return ftemplate(); } #endif // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -209,7 +209,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -224,7 +224,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -327,7 +327,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -391,7 +391,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -406,7 +406,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -507,7 +507,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -571,7 +571,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -586,7 +586,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -768,7 +768,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK1-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -781,7 +781,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -897,7 +897,7 @@ int fint(void) { return ftemplate(); } // CHECK1-LABEL: define {{[^@]+}}@_Z4fintv // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -937,7 +937,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -947,7 +947,7 @@ int fint(void) { return ftemplate(); } // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1043,7 +1043,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1107,7 +1107,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1122,7 +1122,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1225,7 +1225,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1289,7 +1289,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1304,7 +1304,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1405,7 +1405,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1469,7 +1469,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1484,7 +1484,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1666,7 +1666,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK2-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -1679,7 +1679,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1795,7 +1795,7 @@ int fint(void) { return ftemplate(); } // CHECK2-LABEL: define {{[^@]+}}@_Z4fintv // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -1835,7 +1835,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK2-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -1845,7 +1845,7 @@ int fint(void) { return ftemplate(); } // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1941,7 +1941,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2005,7 +2005,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2020,7 +2020,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2119,7 +2119,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2183,7 +2183,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2198,7 +2198,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2295,7 +2295,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2359,7 +2359,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2374,7 +2374,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2552,7 +2552,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK3-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2565,7 +2565,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2681,7 +2681,7 @@ int fint(void) { return ftemplate(); } // CHECK3-LABEL: define {{[^@]+}}@_Z4fintv // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -2721,7 +2721,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -2731,7 +2731,7 @@ int fint(void) { return ftemplate(); } // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2827,7 +2827,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2891,7 +2891,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -2906,7 +2906,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3005,7 +3005,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -3069,7 +3069,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -3084,7 +3084,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3181,7 +3181,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -3245,7 +3245,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -3260,7 +3260,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3438,7 +3438,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK4-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3451,7 +3451,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3567,7 +3567,7 @@ int fint(void) { return ftemplate(); } // CHECK4-LABEL: define {{[^@]+}}@_Z4fintv // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // @@ -3607,7 +3607,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK4-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -3617,7 +3617,7 @@ int fint(void) { return ftemplate(); } // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3713,7 +3713,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3777,7 +3777,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3792,7 +3792,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3895,7 +3895,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3959,7 +3959,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3974,7 +3974,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4075,7 +4075,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4139,7 +4139,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4154,7 +4154,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4336,7 +4336,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK5-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -4349,7 +4349,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4496,7 +4496,7 @@ int fint(void) { return ftemplate(); } // CHECK5-LABEL: define {{[^@]+}}@_Z4fintv // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK5-NEXT: ret i32 [[CALL]] // // @@ -4536,7 +4536,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK5-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -4546,7 +4546,7 @@ int fint(void) { return ftemplate(); } // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4642,7 +4642,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4706,7 +4706,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4721,7 +4721,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4824,7 +4824,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4888,7 +4888,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4903,7 +4903,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5004,7 +5004,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -5068,7 +5068,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -5083,7 +5083,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5265,7 +5265,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK6-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -5278,7 +5278,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5425,7 +5425,7 @@ int fint(void) { return ftemplate(); } // CHECK6-LABEL: define {{[^@]+}}@_Z4fintv // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK6-NEXT: ret i32 [[CALL]] // // @@ -5465,7 +5465,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK6-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -5475,7 +5475,7 @@ int fint(void) { return ftemplate(); } // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5571,7 +5571,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -5635,7 +5635,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -5650,7 +5650,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5749,7 +5749,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -5813,7 +5813,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -5828,7 +5828,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5925,7 +5925,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -5989,7 +5989,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK7-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -6004,7 +6004,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6182,7 +6182,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK7-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6195,7 +6195,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6342,7 +6342,7 @@ int fint(void) { return ftemplate(); } // CHECK7-LABEL: define {{[^@]+}}@_Z4fintv // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK7-NEXT: ret i32 [[CALL]] // // @@ -6382,7 +6382,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK7-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -6392,7 +6392,7 @@ int fint(void) { return ftemplate(); } // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6488,7 +6488,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK8-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -6552,7 +6552,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK8-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -6567,7 +6567,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6666,7 +6666,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK8-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -6730,7 +6730,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK8-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -6745,7 +6745,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6842,7 +6842,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK8-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -6906,7 +6906,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK8-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -6921,7 +6921,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7099,7 +7099,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK8-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7112,7 +7112,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7259,7 +7259,7 @@ int fint(void) { return ftemplate(); } // CHECK8-LABEL: define {{[^@]+}}@_Z4fintv // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK8-NEXT: ret i32 [[CALL]] // // @@ -7299,7 +7299,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK8-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -7309,7 +7309,7 @@ int fint(void) { return ftemplate(); } // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7405,7 +7405,7 @@ int fint(void) { return ftemplate(); } // // // CHECK9-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK9-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -7473,7 +7473,7 @@ int fint(void) { return ftemplate(); } // // // CHECK9-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK9-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -7539,7 +7539,7 @@ int fint(void) { return ftemplate(); } // // // CHECK9-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK9-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -7687,7 +7687,7 @@ int fint(void) { return ftemplate(); } // CHECK9-LABEL: define {{[^@]+}}@_Z4fintv // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK9-NEXT: ret i32 [[CALL]] // // @@ -7730,7 +7730,7 @@ int fint(void) { return ftemplate(); } // // // CHECK10-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK10-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -7798,7 +7798,7 @@ int fint(void) { return ftemplate(); } // // // CHECK10-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK10-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -7864,7 +7864,7 @@ int fint(void) { return ftemplate(); } // // // CHECK10-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK10-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -8012,7 +8012,7 @@ int fint(void) { return ftemplate(); } // CHECK10-LABEL: define {{[^@]+}}@_Z4fintv // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK10-NEXT: ret i32 [[CALL]] // // @@ -8055,7 +8055,7 @@ int fint(void) { return ftemplate(); } // // // CHECK11-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK11-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -8119,7 +8119,7 @@ int fint(void) { return ftemplate(); } // // // CHECK11-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK11-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -8181,7 +8181,7 @@ int fint(void) { return ftemplate(); } // // // CHECK11-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK11-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -8325,7 +8325,7 @@ int fint(void) { return ftemplate(); } // CHECK11-LABEL: define {{[^@]+}}@_Z4fintv // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK11-NEXT: ret i32 [[CALL]] // // @@ -8368,7 +8368,7 @@ int fint(void) { return ftemplate(); } // // // CHECK12-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK12-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -8432,7 +8432,7 @@ int fint(void) { return ftemplate(); } // // // CHECK12-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK12-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -8494,7 +8494,7 @@ int fint(void) { return ftemplate(); } // // // CHECK12-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK12-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -8638,7 +8638,7 @@ int fint(void) { return ftemplate(); } // CHECK12-LABEL: define {{[^@]+}}@_Z4fintv // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK12-NEXT: ret i32 [[CALL]] // // @@ -8681,7 +8681,7 @@ int fint(void) { return ftemplate(); } // // // CHECK13-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK13-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -8749,7 +8749,7 @@ int fint(void) { return ftemplate(); } // // // CHECK13-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK13-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -8815,7 +8815,7 @@ int fint(void) { return ftemplate(); } // // // CHECK13-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK13-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK13-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -8994,7 +8994,7 @@ int fint(void) { return ftemplate(); } // CHECK13-LABEL: define {{[^@]+}}@_Z4fintv // CHECK13-SAME: () #[[ATTR0]] { // CHECK13-NEXT: entry: -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK13-NEXT: ret i32 [[CALL]] // // @@ -9037,7 +9037,7 @@ int fint(void) { return ftemplate(); } // // // CHECK14-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK14-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK14-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -9105,7 +9105,7 @@ int fint(void) { return ftemplate(); } // // // CHECK14-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK14-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK14-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -9171,7 +9171,7 @@ int fint(void) { return ftemplate(); } // // // CHECK14-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK14-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK14-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -9350,7 +9350,7 @@ int fint(void) { return ftemplate(); } // CHECK14-LABEL: define {{[^@]+}}@_Z4fintv // CHECK14-SAME: () #[[ATTR0]] { // CHECK14-NEXT: entry: -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK14-NEXT: ret i32 [[CALL]] // // @@ -9393,7 +9393,7 @@ int fint(void) { return ftemplate(); } // // // CHECK15-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK15-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -9457,7 +9457,7 @@ int fint(void) { return ftemplate(); } // // // CHECK15-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK15-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -9519,7 +9519,7 @@ int fint(void) { return ftemplate(); } // // // CHECK15-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK15-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK15-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -9694,7 +9694,7 @@ int fint(void) { return ftemplate(); } // CHECK15-LABEL: define {{[^@]+}}@_Z4fintv // CHECK15-SAME: () #[[ATTR0]] { // CHECK15-NEXT: entry: -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK15-NEXT: ret i32 [[CALL]] // // @@ -9737,7 +9737,7 @@ int fint(void) { return ftemplate(); } // // // CHECK16-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK16-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK16-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -9801,7 +9801,7 @@ int fint(void) { return ftemplate(); } // // // CHECK16-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK16-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK16-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -9863,7 +9863,7 @@ int fint(void) { return ftemplate(); } // // // CHECK16-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK16-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK16-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -10038,7 +10038,7 @@ int fint(void) { return ftemplate(); } // CHECK16-LABEL: define {{[^@]+}}@_Z4fintv // CHECK16-SAME: () #[[ATTR0]] { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK16-NEXT: ret i32 [[CALL]] // // @@ -10081,7 +10081,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -10096,7 +10096,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10199,7 +10199,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -10214,7 +10214,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10315,7 +10315,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK17-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -10330,7 +10330,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10448,7 +10448,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK17-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -10461,7 +10461,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10575,7 +10575,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -10585,7 +10585,7 @@ int fint(void) { return ftemplate(); } // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10674,7 +10674,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK18-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -10689,7 +10689,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10792,7 +10792,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK18-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -10807,7 +10807,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10908,7 +10908,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK18-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -10923,7 +10923,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11041,7 +11041,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK18-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -11054,7 +11054,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11168,7 +11168,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK18-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -11178,7 +11178,7 @@ int fint(void) { return ftemplate(); } // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11267,7 +11267,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -11282,7 +11282,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11381,7 +11381,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -11396,7 +11396,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11493,7 +11493,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK19-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -11508,7 +11508,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11622,7 +11622,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK19-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -11635,7 +11635,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11749,7 +11749,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -11759,7 +11759,7 @@ int fint(void) { return ftemplate(); } // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11848,7 +11848,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK20-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -11863,7 +11863,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11962,7 +11962,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK20-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -11977,7 +11977,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12074,7 +12074,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK20-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -12089,7 +12089,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12203,7 +12203,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK20-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -12216,7 +12216,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12330,7 +12330,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK20-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -12340,7 +12340,7 @@ int fint(void) { return ftemplate(); } // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12429,7 +12429,7 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK21-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -12444,7 +12444,7 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12547,7 +12547,7 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK21-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -12562,7 +12562,7 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12663,7 +12663,7 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK21-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -12678,7 +12678,7 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12796,7 +12796,7 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK21-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -12809,7 +12809,7 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12954,7 +12954,7 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK21-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -12964,7 +12964,7 @@ int fint(void) { return ftemplate(); } // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13053,7 +13053,7 @@ int fint(void) { return ftemplate(); } // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK22-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -13068,7 +13068,7 @@ int fint(void) { return ftemplate(); } // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13171,7 +13171,7 @@ int fint(void) { return ftemplate(); } // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK22-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -13186,7 +13186,7 @@ int fint(void) { return ftemplate(); } // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13287,7 +13287,7 @@ int fint(void) { return ftemplate(); } // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK22-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -13302,7 +13302,7 @@ int fint(void) { return ftemplate(); } // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13420,7 +13420,7 @@ int fint(void) { return ftemplate(); } // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK22-SAME: (i64 noundef [[I:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i64 [[I:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -13433,7 +13433,7 @@ int fint(void) { return ftemplate(); } // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13578,7 +13578,7 @@ int fint(void) { return ftemplate(); } // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK22-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 @@ -13588,7 +13588,7 @@ int fint(void) { return ftemplate(); } // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13677,7 +13677,7 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK23-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -13692,7 +13692,7 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13791,7 +13791,7 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK23-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -13806,7 +13806,7 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13903,7 +13903,7 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK23-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -13918,7 +13918,7 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14032,7 +14032,7 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK23-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -14045,7 +14045,7 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14190,7 +14190,7 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK23-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -14200,7 +14200,7 @@ int fint(void) { return ftemplate(); } // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14289,7 +14289,7 @@ int fint(void) { return ftemplate(); } // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70 -// CHECK24-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -14304,7 +14304,7 @@ int fint(void) { return ftemplate(); } // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14403,7 +14403,7 @@ int fint(void) { return ftemplate(); } // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86 -// CHECK24-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -14418,7 +14418,7 @@ int fint(void) { return ftemplate(); } // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14515,7 +14515,7 @@ int fint(void) { return ftemplate(); } // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103 -// CHECK24-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -14530,7 +14530,7 @@ int fint(void) { return ftemplate(); } // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[A:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[B:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[C:%.*]], float** noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 4 dereferenceable(4) [[A:%.*]], float** nonnull align 4 dereferenceable(4) [[B:%.*]], float** nonnull align 4 dereferenceable(4) [[C:%.*]], float** nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14644,7 +14644,7 @@ int fint(void) { return ftemplate(); } // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115 -// CHECK24-SAME: (i32 noundef [[I:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32 [[I:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -14657,7 +14657,7 @@ int fint(void) { return ftemplate(); } // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[I:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[I:%.*]], i8* nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14802,7 +14802,7 @@ int fint(void) { return ftemplate(); } // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135 -// CHECK24-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 @@ -14812,7 +14812,7 @@ int fint(void) { return ftemplate(); } // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14901,7 +14901,7 @@ int fint(void) { return ftemplate(); } // // // CHECK25-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK25-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -14969,7 +14969,7 @@ int fint(void) { return ftemplate(); } // // // CHECK25-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK25-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -15035,7 +15035,7 @@ int fint(void) { return ftemplate(); } // // // CHECK25-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK25-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -15183,7 +15183,7 @@ int fint(void) { return ftemplate(); } // CHECK25-LABEL: define {{[^@]+}}@_Z4fintv // CHECK25-SAME: () #[[ATTR0]] { // CHECK25-NEXT: entry: -// CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK25-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK25-NEXT: ret i32 [[CALL]] // // @@ -15226,7 +15226,7 @@ int fint(void) { return ftemplate(); } // // // CHECK26-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK26-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -15294,7 +15294,7 @@ int fint(void) { return ftemplate(); } // // // CHECK26-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK26-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -15360,7 +15360,7 @@ int fint(void) { return ftemplate(); } // // // CHECK26-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK26-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -15508,7 +15508,7 @@ int fint(void) { return ftemplate(); } // CHECK26-LABEL: define {{[^@]+}}@_Z4fintv // CHECK26-SAME: () #[[ATTR0]] { // CHECK26-NEXT: entry: -// CHECK26-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK26-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK26-NEXT: ret i32 [[CALL]] // // @@ -15551,7 +15551,7 @@ int fint(void) { return ftemplate(); } // // // CHECK27-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK27-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -15615,7 +15615,7 @@ int fint(void) { return ftemplate(); } // // // CHECK27-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK27-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -15677,7 +15677,7 @@ int fint(void) { return ftemplate(); } // // // CHECK27-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK27-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -15821,7 +15821,7 @@ int fint(void) { return ftemplate(); } // CHECK27-LABEL: define {{[^@]+}}@_Z4fintv // CHECK27-SAME: () #[[ATTR0]] { // CHECK27-NEXT: entry: -// CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK27-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK27-NEXT: ret i32 [[CALL]] // // @@ -15864,7 +15864,7 @@ int fint(void) { return ftemplate(); } // // // CHECK28-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK28-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -15928,7 +15928,7 @@ int fint(void) { return ftemplate(); } // // // CHECK28-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK28-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -15990,7 +15990,7 @@ int fint(void) { return ftemplate(); } // // // CHECK28-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK28-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -16134,7 +16134,7 @@ int fint(void) { return ftemplate(); } // CHECK28-LABEL: define {{[^@]+}}@_Z4fintv // CHECK28-SAME: () #[[ATTR0]] { // CHECK28-NEXT: entry: -// CHECK28-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK28-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK28-NEXT: ret i32 [[CALL]] // // @@ -16177,7 +16177,7 @@ int fint(void) { return ftemplate(); } // // // CHECK29-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK29-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK29-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK29-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -16245,7 +16245,7 @@ int fint(void) { return ftemplate(); } // // // CHECK29-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK29-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK29-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK29-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -16311,7 +16311,7 @@ int fint(void) { return ftemplate(); } // // // CHECK29-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK29-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK29-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK29-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -16490,7 +16490,7 @@ int fint(void) { return ftemplate(); } // CHECK29-LABEL: define {{[^@]+}}@_Z4fintv // CHECK29-SAME: () #[[ATTR0]] { // CHECK29-NEXT: entry: -// CHECK29-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK29-NEXT: ret i32 [[CALL]] // // @@ -16533,7 +16533,7 @@ int fint(void) { return ftemplate(); } // // // CHECK30-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK30-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK30-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK30-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -16601,7 +16601,7 @@ int fint(void) { return ftemplate(); } // // // CHECK30-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK30-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK30-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK30-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -16667,7 +16667,7 @@ int fint(void) { return ftemplate(); } // // // CHECK30-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK30-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK30-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK30-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -16846,7 +16846,7 @@ int fint(void) { return ftemplate(); } // CHECK30-LABEL: define {{[^@]+}}@_Z4fintv // CHECK30-SAME: () #[[ATTR0]] { // CHECK30-NEXT: entry: -// CHECK30-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() +// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z9ftemplateIiET_v() // CHECK30-NEXT: ret i32 [[CALL]] // // @@ -16889,7 +16889,7 @@ int fint(void) { return ftemplate(); } // // // CHECK31-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK31-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK31-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK31-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -16953,7 +16953,7 @@ int fint(void) { return ftemplate(); } // // // CHECK31-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK31-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK31-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK31-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -17015,7 +17015,7 @@ int fint(void) { return ftemplate(); } // // // CHECK31-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK31-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK31-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK31-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -17190,7 +17190,7 @@ int fint(void) { return ftemplate(); } // CHECK31-LABEL: define {{[^@]+}}@_Z4fintv // CHECK31-SAME: () #[[ATTR0]] { // CHECK31-NEXT: entry: -// CHECK31-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK31-NEXT: ret i32 [[CALL]] // // @@ -17233,7 +17233,7 @@ int fint(void) { return ftemplate(); } // // // CHECK32-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK32-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK32-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK32-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -17297,7 +17297,7 @@ int fint(void) { return ftemplate(); } // // // CHECK32-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK32-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK32-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK32-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -17359,7 +17359,7 @@ int fint(void) { return ftemplate(); } // // // CHECK32-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK32-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK32-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 // CHECK32-NEXT: [[B_ADDR:%.*]] = alloca float*, align 4 @@ -17534,7 +17534,7 @@ int fint(void) { return ftemplate(); } // CHECK32-LABEL: define {{[^@]+}}@_Z4fintv // CHECK32-SAME: () #[[ATTR0]] { // CHECK32-NEXT: entry: -// CHECK32-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() +// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z9ftemplateIiET_v() // CHECK32-NEXT: ret i32 [[CALL]] // // diff --git a/clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp index 700eaa471e5535a23d9f24e6663158bb31677d7a..40328951e72828314c75a13a091f72b7fea9f553 100644 --- a/clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp @@ -167,12 +167,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -194,7 +194,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -262,48 +262,48 @@ int main() { // CHECK1-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP18:%.*]] = load double, double* [[G3]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = load double, double* [[G3]], align 8 // CHECK1-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00 -// CHECK1-NEXT: store double [[ADD9]], double* [[G3]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: store double [[ADD9]], double* [[G3]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 8 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00 -// CHECK1-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR6]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR6]], align 4 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3 -// CHECK1-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR7]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4 +// CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR7]], align 4 // CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double // CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00 // CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float -// CHECK1-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK1-NEXT: store double* [[G3]], double** [[TMP23]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: store double* [[G3]], double** [[TMP23]], align 8 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP25:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: store double* [[TMP25]], double** [[TMP24]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP25:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK1-NEXT: store double* [[TMP25]], double** [[TMP24]], align 8 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 8 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 8 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK1-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -339,12 +339,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK2-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -366,7 +366,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -434,48 +434,48 @@ int main() { // CHECK2-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP18:%.*]] = load double, double* [[G3]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP18:%.*]] = load double, double* [[G3]], align 8 // CHECK2-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00 -// CHECK2-NEXT: store double [[ADD9]], double* [[G3]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: store double [[ADD9]], double* [[G3]], align 8 +// CHECK2-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK2-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 8 // CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00 -// CHECK2-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR6]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 8 +// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR6]], align 4 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3 -// CHECK2-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR7]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4 +// CHECK2-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR7]], align 4 // CHECK2-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double // CHECK2-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00 // CHECK2-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float -// CHECK2-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK2-NEXT: store double* [[G3]], double** [[TMP23]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: store double* [[G3]], double** [[TMP23]], align 8 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP25:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: store double* [[TMP25]], double** [[TMP24]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP25:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK2-NEXT: store double* [[TMP25]], double** [[TMP24]], align 8 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 8 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 8 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK2-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -511,12 +511,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -546,7 +546,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -614,48 +614,48 @@ int main() { // CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP18:%.*]] = load double, double* [[G3]], align 8, !llvm.access.group !5 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load double, double* [[G3]], align 8 // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00 -// CHECK3-NEXT: store double [[ADD9]], double* [[G3]], align 8, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store double [[ADD9]], double* [[G3]], align 8 +// CHECK3-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 4 // CHECK3-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00 -// CHECK3-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR6]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR6]], align 4 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3 -// CHECK3-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR7]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR7]], align 4 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float -// CHECK3-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK3-NEXT: store double* [[G3]], double** [[TMP23]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store double* [[G3]], double** [[TMP23]], align 4 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP25:%.*]] = load double*, double** [[_TMP5]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store double* [[TMP25]], double** [[TMP24]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP25:%.*]] = load double*, double** [[_TMP5]], align 4 +// CHECK3-NEXT: store double* [[TMP25]], double** [[TMP24]], align 4 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK3-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 4 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK3-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !5 +// CHECK3-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 4 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK3-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -691,12 +691,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -726,7 +726,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -794,48 +794,48 @@ int main() { // CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP18:%.*]] = load double, double* [[G3]], align 8, !llvm.access.group !5 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load double, double* [[G3]], align 8 // CHECK4-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00 -// CHECK4-NEXT: store double [[ADD9]], double* [[G3]], align 8, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store double [[ADD9]], double* [[G3]], align 8 +// CHECK4-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 4 +// CHECK4-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 4 // CHECK4-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00 -// CHECK4-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR6]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 4 +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR6]], align 4 // CHECK4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3 -// CHECK4-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR7]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4 +// CHECK4-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR7]], align 4 // CHECK4-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double // CHECK4-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00 // CHECK4-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float -// CHECK4-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK4-NEXT: store double* [[G3]], double** [[TMP23]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store double* [[G3]], double** [[TMP23]], align 4 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP25:%.*]] = load double*, double** [[_TMP5]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store double* [[TMP25]], double** [[TMP24]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP25:%.*]] = load double*, double** [[_TMP5]], align 4 +// CHECK4-NEXT: store double* [[TMP25]], double** [[TMP24]], align 4 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK4-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 4 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK4-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !5 +// CHECK4-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 4 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK4-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -871,7 +871,7 @@ int main() { // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // @@ -889,7 +889,7 @@ int main() { // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // @@ -907,7 +907,7 @@ int main() { // CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK7-NEXT: ret i32 0 // // @@ -925,7 +925,7 @@ int main() { // CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK8-NEXT: ret i32 0 // // @@ -949,14 +949,14 @@ int main() { // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1021,7 +1021,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1029,27 +1029,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP39]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1057,12 +1057,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1087,7 +1087,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1176,37 +1176,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP26]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8 +// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP28]] to i64 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK9-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* // CHECK9-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false), !llvm.access.group !5 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1220,14 +1220,14 @@ int main() { // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -1235,12 +1235,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1259,14 +1259,14 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1326,17 +1326,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP32]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1347,7 +1347,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1361,7 +1361,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1370,17 +1370,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1388,12 +1388,12 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1415,7 +1415,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1498,37 +1498,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] // CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP26]] to i64 // CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* // CHECK9-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false), !llvm.access.group !11 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1542,14 +1542,14 @@ int main() { // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done14: @@ -1557,17 +1557,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1578,7 +1578,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1592,7 +1592,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1627,14 +1627,14 @@ int main() { // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1699,7 +1699,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1707,27 +1707,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP39]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1735,12 +1735,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1765,7 +1765,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1854,37 +1854,37 @@ int main() { // CHECK10-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] // CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP26]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8 +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP28]] to i64 // CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK10-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* // CHECK10-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false), !llvm.access.group !5 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK10-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -1898,14 +1898,14 @@ int main() { // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done15: @@ -1913,12 +1913,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -1937,14 +1937,14 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -2004,17 +2004,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP32]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2025,7 +2025,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2039,7 +2039,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2048,17 +2048,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2066,12 +2066,12 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2093,7 +2093,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2176,37 +2176,37 @@ int main() { // CHECK10-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] // CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP26]] to i64 // CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK10-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* // CHECK10-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false), !llvm.access.group !11 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2220,14 +2220,14 @@ int main() { // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done14: @@ -2235,17 +2235,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2256,7 +2256,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2270,7 +2270,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2305,14 +2305,14 @@ int main() { // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -2375,7 +2375,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2383,27 +2383,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP39]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2411,12 +2411,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2439,7 +2439,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2528,35 +2528,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP26]] -// CHECK11-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 [[TMP28]] // CHECK11-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK11-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false), !llvm.access.group !6 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK11-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -2570,14 +2570,14 @@ int main() { // CHECK11-NEXT: store i32 2, i32* [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -2585,12 +2585,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2609,14 +2609,14 @@ int main() { // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2675,17 +2675,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP32]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2696,7 +2696,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2710,7 +2710,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2719,17 +2719,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2737,12 +2737,12 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2763,7 +2763,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2846,35 +2846,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] // CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP24]] -// CHECK11-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 [[TMP26]] // CHECK11-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* // CHECK11-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false), !llvm.access.group !12 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK11-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -2888,14 +2888,14 @@ int main() { // CHECK11-NEXT: store i32 2, i32* [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -2903,17 +2903,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2924,7 +2924,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2938,7 +2938,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2973,14 +2973,14 @@ int main() { // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -3043,7 +3043,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -3051,27 +3051,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP39]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3079,12 +3079,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3107,7 +3107,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3196,35 +3196,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] // CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP26]] -// CHECK12-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 [[TMP28]] // CHECK12-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK12-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false), !llvm.access.group !6 +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK12-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3238,14 +3238,14 @@ int main() { // CHECK12-NEXT: store i32 2, i32* [[I]], align 4 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK12: .omp.final.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done14: @@ -3253,12 +3253,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // @@ -3277,14 +3277,14 @@ int main() { // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3343,17 +3343,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP32]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3364,7 +3364,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3378,7 +3378,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3387,17 +3387,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3405,12 +3405,12 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3431,7 +3431,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3514,35 +3514,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] // CHECK12-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP24]] -// CHECK12-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 [[TMP26]] // CHECK12-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* // CHECK12-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false), !llvm.access.group !12 +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 -// CHECK12-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3556,14 +3556,14 @@ int main() { // CHECK12-NEXT: store i32 2, i32* [[I]], align 4 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK12: .omp.final.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done13: @@ -3571,17 +3571,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3592,7 +3592,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3606,7 +3606,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3642,14 +3642,14 @@ int main() { // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -3695,7 +3695,7 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -3703,27 +3703,27 @@ int main() { // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done7: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP17]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3731,7 +3731,7 @@ int main() { // CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK13-NEXT: ret void // // @@ -3752,14 +3752,14 @@ int main() { // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -3812,27 +3812,27 @@ int main() { // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done7: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP17]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3843,7 +3843,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3852,7 +3852,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3866,17 +3866,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3884,22 +3884,22 @@ int main() { // CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3910,7 +3910,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3924,7 +3924,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3953,14 +3953,14 @@ int main() { // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -4006,7 +4006,7 @@ int main() { // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -4014,27 +4014,27 @@ int main() { // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done7: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP17]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4042,7 +4042,7 @@ int main() { // CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK14-NEXT: ret void // // @@ -4063,14 +4063,14 @@ int main() { // CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -4123,27 +4123,27 @@ int main() { // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done7: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP17]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4154,7 +4154,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4163,7 +4163,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4177,17 +4177,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4195,22 +4195,22 @@ int main() { // CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4221,7 +4221,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4235,7 +4235,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4264,14 +4264,14 @@ int main() { // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -4315,7 +4315,7 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -4323,27 +4323,27 @@ int main() { // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done6: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP17]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4351,7 +4351,7 @@ int main() { // CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK15-NEXT: ret void // // @@ -4372,14 +4372,14 @@ int main() { // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4430,27 +4430,27 @@ int main() { // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done6: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP17]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4461,7 +4461,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4470,7 +4470,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4484,17 +4484,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4502,22 +4502,22 @@ int main() { // CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4528,7 +4528,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4542,7 +4542,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4571,14 +4571,14 @@ int main() { // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -4622,7 +4622,7 @@ int main() { // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -4630,27 +4630,27 @@ int main() { // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done6: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP17]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4658,7 +4658,7 @@ int main() { // CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK16-NEXT: ret void // // @@ -4679,14 +4679,14 @@ int main() { // CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4737,27 +4737,27 @@ int main() { // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done6: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP17]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4768,7 +4768,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4777,7 +4777,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4791,17 +4791,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4809,22 +4809,22 @@ int main() { // CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4835,7 +4835,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4849,7 +4849,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp index 0ec3ef585fc77d33de0d50525da6a348baf0b6c9..2bf6d022e8fc51717b1a8ef8a6ebcdda77361cde 100644 --- a/clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp @@ -159,12 +159,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -186,7 +186,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -246,38 +246,38 @@ int main() { // CHECK1-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: store double 1.000000e+00, double* [[G3]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 8 +// CHECK1-NEXT: store i32 3, i32* [[SVAR6]], align 4 +// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK1-NEXT: store double* [[G3]], double** [[TMP15]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: store double* [[G3]], double** [[TMP15]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP17:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: store double* [[TMP17]], double** [[TMP16]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP17:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK1-NEXT: store double* [[TMP17]], double** [[TMP16]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 8 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -328,12 +328,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK2-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -355,7 +355,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -415,38 +415,38 @@ int main() { // CHECK2-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: store double 1.000000e+00, double* [[G3]], align 8 +// CHECK2-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 8 +// CHECK2-NEXT: store i32 3, i32* [[SVAR6]], align 4 +// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK2-NEXT: store double* [[G3]], double** [[TMP15]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: store double* [[G3]], double** [[TMP15]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP17:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: store double* [[TMP17]], double** [[TMP16]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP17:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK2-NEXT: store double* [[TMP17]], double** [[TMP16]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 8 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -497,12 +497,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -532,7 +532,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -592,38 +592,38 @@ int main() { // CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP5]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: store double 1.000000e+00, double* [[G3]], align 8 +// CHECK3-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP5]], align 4 +// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 4 +// CHECK3-NEXT: store i32 3, i32* [[SVAR6]], align 4 +// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK3-NEXT: store double* [[G3]], double** [[TMP15]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store double* [[G3]], double** [[TMP15]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP17:%.*]] = load double*, double** [[_TMP5]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store double* [[TMP17]], double** [[TMP16]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP17:%.*]] = load double*, double** [[_TMP5]], align 4 +// CHECK3-NEXT: store double* [[TMP17]], double** [[TMP16]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK3-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK3-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !5 +// CHECK3-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 4 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -674,12 +674,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -709,7 +709,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -769,38 +769,38 @@ int main() { // CHECK4-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP5]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: store double 1.000000e+00, double* [[G3]], align 8 +// CHECK4-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP5]], align 4 +// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP14]], align 4 +// CHECK4-NEXT: store i32 3, i32* [[SVAR6]], align 4 +// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK4-NEXT: store double* [[G3]], double** [[TMP15]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store double* [[G3]], double** [[TMP15]], align 4 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP17:%.*]] = load double*, double** [[_TMP5]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store double* [[TMP17]], double** [[TMP16]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP17:%.*]] = load double*, double** [[_TMP5]], align 4 +// CHECK4-NEXT: store double* [[TMP17]], double** [[TMP16]], align 4 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK4-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store i32* [[SVAR6]], i32** [[TMP18]], align 4 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK4-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !5 +// CHECK4-NEXT: store float* [[SFVAR7]], float** [[TMP19]], align 4 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -851,7 +851,7 @@ int main() { // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // @@ -869,7 +869,7 @@ int main() { // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // @@ -887,7 +887,7 @@ int main() { // CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK7-NEXT: ret i32 0 // // @@ -905,7 +905,7 @@ int main() { // CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK8-NEXT: ret i32 0 // // @@ -930,14 +930,14 @@ int main() { // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1002,7 +1002,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1010,27 +1010,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP39]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1038,12 +1038,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1068,7 +1068,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1116,13 +1116,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -1142,37 +1142,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 // CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK9-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[TMP17]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group !5 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1219,14 +1219,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP38]], i32* [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done16: @@ -1234,12 +1234,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1258,14 +1258,14 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1325,17 +1325,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP32]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1346,7 +1346,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1360,7 +1360,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1369,17 +1369,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1387,12 +1387,12 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1414,7 +1414,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1458,13 +1458,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -1484,37 +1484,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 // CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* // CHECK9-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !11 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1559,14 +1559,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -1574,17 +1574,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1595,7 +1595,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1609,7 +1609,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1645,14 +1645,14 @@ int main() { // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1717,7 +1717,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1725,27 +1725,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP39]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1753,12 +1753,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1783,7 +1783,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1831,13 +1831,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -1857,37 +1857,37 @@ int main() { // CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 // CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK10-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK10-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[TMP17]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group !5 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -1934,14 +1934,14 @@ int main() { // CHECK10-NEXT: store i32 [[TMP38]], i32* [[TMP4]], align 4 // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done16: @@ -1949,12 +1949,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -1973,14 +1973,14 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -2040,17 +2040,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP32]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2061,7 +2061,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2075,7 +2075,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2084,17 +2084,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2102,12 +2102,12 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2129,7 +2129,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2173,13 +2173,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -2199,37 +2199,37 @@ int main() { // CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 // CHECK10-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK10-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* // CHECK10-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !11 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2274,14 +2274,14 @@ int main() { // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done15: @@ -2289,17 +2289,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2310,7 +2310,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2324,7 +2324,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2360,14 +2360,14 @@ int main() { // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -2430,7 +2430,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2438,27 +2438,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP39]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2466,12 +2466,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2494,7 +2494,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2542,13 +2542,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK11-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -2568,35 +2568,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP16]] -// CHECK11-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 [[TMP18]] // CHECK11-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[ARRAYIDX10]] to i8* // CHECK11-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[TMP17]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group !6 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK11-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -2643,14 +2643,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP38]], i32* [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done15: @@ -2658,12 +2658,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2682,14 +2682,14 @@ int main() { // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2748,17 +2748,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP32]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2769,7 +2769,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2783,7 +2783,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2792,17 +2792,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2810,12 +2810,12 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2836,7 +2836,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2880,13 +2880,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK11-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -2906,35 +2906,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP15]] -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 [[TMP17]] // CHECK11-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* // CHECK11-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !12 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -2979,14 +2979,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -2994,17 +2994,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3015,7 +3015,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3029,7 +3029,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3065,14 +3065,14 @@ int main() { // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -3135,7 +3135,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -3143,27 +3143,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP39]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3171,12 +3171,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3199,7 +3199,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3247,13 +3247,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK12-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -3273,35 +3273,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK12-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP16]] -// CHECK12-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 [[TMP18]] // CHECK12-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[ARRAYIDX10]] to i8* // CHECK12-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[TMP17]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group !6 +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK12-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3348,14 +3348,14 @@ int main() { // CHECK12-NEXT: store i32 [[TMP38]], i32* [[TMP4]], align 4 // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done15: @@ -3363,12 +3363,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // @@ -3387,14 +3387,14 @@ int main() { // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3453,17 +3453,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP32]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3474,7 +3474,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3488,7 +3488,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3497,17 +3497,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3515,12 +3515,12 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3541,7 +3541,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3585,13 +3585,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK12-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -3611,35 +3611,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP15]] -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 [[TMP17]] // CHECK12-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* // CHECK12-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !12 +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3684,14 +3684,14 @@ int main() { // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i32 4, i1 false) // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done14: @@ -3699,17 +3699,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3720,7 +3720,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3734,7 +3734,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3777,14 +3777,14 @@ int main() { // CHECK13-NEXT: [[I16:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -3802,13 +3802,13 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: // CHECK13-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR7]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK13-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -3872,18 +3872,18 @@ int main() { // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) // CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK13-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4:[0-9]+]] // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 // CHECK13-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 @@ -3891,27 +3891,27 @@ int main() { // CHECK13: arraydestroy.body18: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST19:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE15]] ], [ [[ARRAYDESTROY_ELEMENT20:%.*]], [[ARRAYDESTROY_BODY18]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT20]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST19]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE21:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT20]], [[ARRAY_BEGIN17]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] // CHECK13: arraydestroy.done22: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP30]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3919,17 +3919,17 @@ int main() { // CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // @@ -3955,14 +3955,14 @@ int main() { // CHECK13-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK13-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -3980,13 +3980,13 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: // CHECK13-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR7]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK13-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -4048,14 +4048,14 @@ int main() { // CHECK13-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK13-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0 // CHECK13-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: @@ -4066,17 +4066,17 @@ int main() { // CHECK13: arraydestroy.body17: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE15]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK13: arraydestroy.done21: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP29]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4087,7 +4087,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4096,7 +4096,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4110,17 +4110,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4128,22 +4128,22 @@ int main() { // CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4154,7 +4154,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4168,7 +4168,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4204,14 +4204,14 @@ int main() { // CHECK14-NEXT: [[I16:%.*]] = alloca i32, align 4 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -4229,13 +4229,13 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: // CHECK14-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR7]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK14-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -4299,18 +4299,18 @@ int main() { // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) // CHECK14-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK14-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4:[0-9]+]] // CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 // CHECK14-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done15: -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 @@ -4318,27 +4318,27 @@ int main() { // CHECK14: arraydestroy.body18: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST19:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE15]] ], [ [[ARRAYDESTROY_ELEMENT20:%.*]], [[ARRAYDESTROY_BODY18]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT20]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST19]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE21:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT20]], [[ARRAY_BEGIN17]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] // CHECK14: arraydestroy.done22: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP30]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4346,17 +4346,17 @@ int main() { // CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // @@ -4382,14 +4382,14 @@ int main() { // CHECK14-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK14-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK14-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -4407,13 +4407,13 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: // CHECK14-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR7]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK14-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -4475,14 +4475,14 @@ int main() { // CHECK14-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK14-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0 // CHECK14-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done15: @@ -4493,17 +4493,17 @@ int main() { // CHECK14: arraydestroy.body17: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE15]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK14: arraydestroy.done21: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP29]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4514,7 +4514,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4523,7 +4523,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4537,17 +4537,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4555,22 +4555,22 @@ int main() { // CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4581,7 +4581,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4595,7 +4595,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4631,14 +4631,14 @@ int main() { // CHECK15-NEXT: [[I15:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -4656,13 +4656,13 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: // CHECK15-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR7]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK15-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -4724,18 +4724,18 @@ int main() { // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) // CHECK15-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK15-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4:[0-9]+]] // CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 // CHECK15-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done14: -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN16]], i32 2 @@ -4743,27 +4743,27 @@ int main() { // CHECK15: arraydestroy.body17: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST18]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK15: arraydestroy.done21: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP30]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4771,17 +4771,17 @@ int main() { // CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // @@ -4807,14 +4807,14 @@ int main() { // CHECK15-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK15-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4832,13 +4832,13 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: // CHECK15-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR7]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK15-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -4898,14 +4898,14 @@ int main() { // CHECK15-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK15-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0 // CHECK15-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done14: @@ -4916,17 +4916,17 @@ int main() { // CHECK15: arraydestroy.body16: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST17]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK15: arraydestroy.done20: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP29]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4937,7 +4937,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4946,7 +4946,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4960,17 +4960,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4978,22 +4978,22 @@ int main() { // CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5004,7 +5004,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5018,7 +5018,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5054,14 +5054,14 @@ int main() { // CHECK16-NEXT: [[I15:%.*]] = alloca i32, align 4 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -5079,13 +5079,13 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: // CHECK16-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR7]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK16-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -5147,18 +5147,18 @@ int main() { // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) // CHECK16-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK16-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4:[0-9]+]] // CHECK16-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR6]], i32 0, i32 0 // CHECK16-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done14: -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN16]], i32 2 @@ -5166,27 +5166,27 @@ int main() { // CHECK16: arraydestroy.body17: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST18]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK16: arraydestroy.done21: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP30]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5194,17 +5194,17 @@ int main() { // CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // @@ -5230,14 +5230,14 @@ int main() { // CHECK16-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK16-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK16-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -5255,13 +5255,13 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: // CHECK16-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR7]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK16-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -5321,14 +5321,14 @@ int main() { // CHECK16-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK16-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0 // CHECK16-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done14: @@ -5339,17 +5339,17 @@ int main() { // CHECK16: arraydestroy.body16: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST17]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK16: arraydestroy.done20: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP29]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5360,7 +5360,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5369,7 +5369,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5383,17 +5383,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5401,22 +5401,22 @@ int main() { // CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5427,7 +5427,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5441,7 +5441,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_simd_private_codegen.cpp b/clang/test/OpenMP/distribute_simd_private_codegen.cpp index 10aaf9070961f73f26290a02fe0f50ab771c8b3c..79bb945070d552914d4eee3863190f886207ab5a 100644 --- a/clang/test/OpenMP/distribute_simd_private_codegen.cpp +++ b/clang/test/OpenMP/distribute_simd_private_codegen.cpp @@ -124,7 +124,7 @@ int main() { // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK1-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // @@ -136,7 +136,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -180,38 +180,38 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP2]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: store double 1.000000e+00, double* [[G]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP2]], align 8 +// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 8 +// CHECK1-NEXT: store i32 3, i32* [[SVAR]], align 4 +// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK1-NEXT: store double* [[G]], double** [[TMP9]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: store double* [[G]], double** [[TMP9]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP11:%.*]] = load double*, double** [[_TMP2]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: store double* [[TMP11]], double** [[TMP10]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP11:%.*]] = load double*, double** [[_TMP2]], align 8 +// CHECK1-NEXT: store double* [[TMP11]], double** [[TMP10]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK1-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK1-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK1-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 8 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -242,7 +242,7 @@ int main() { // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK2-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // @@ -254,7 +254,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -298,38 +298,38 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP2]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: store double 1.000000e+00, double* [[G]], align 8 +// CHECK2-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP2]], align 8 +// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 8 +// CHECK2-NEXT: store i32 3, i32* [[SVAR]], align 4 +// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK2-NEXT: store double* [[G]], double** [[TMP9]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: store double* [[G]], double** [[TMP9]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP11:%.*]] = load double*, double** [[_TMP2]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: store double* [[TMP11]], double** [[TMP10]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP11:%.*]] = load double*, double** [[_TMP2]], align 8 +// CHECK2-NEXT: store double* [[TMP11]], double** [[TMP10]], align 8 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK2-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 8 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK2-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK2-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 8 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -360,7 +360,7 @@ int main() { // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK3-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // @@ -372,7 +372,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -416,38 +416,38 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP2]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: store double 1.000000e+00, double* [[G]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP2]], align 4 +// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 4 +// CHECK3-NEXT: store i32 3, i32* [[SVAR]], align 4 +// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK3-NEXT: store double* [[G]], double** [[TMP9]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store double* [[G]], double** [[TMP9]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP11:%.*]] = load double*, double** [[_TMP2]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store double* [[TMP11]], double** [[TMP10]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP11:%.*]] = load double*, double** [[_TMP2]], align 4 +// CHECK3-NEXT: store double* [[TMP11]], double** [[TMP10]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK3-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK3-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !5 +// CHECK3-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 4 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -478,7 +478,7 @@ int main() { // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // @@ -490,7 +490,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -534,38 +534,38 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store double 1.000000e+00, double* [[G]], align 8, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP2]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store i32 3, i32* [[SVAR]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: store double 1.000000e+00, double* [[G]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP2]], align 4 +// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP8]], align 4 +// CHECK4-NEXT: store i32 3, i32* [[SVAR]], align 4 +// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK4-NEXT: store double* [[G]], double** [[TMP9]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store double* [[G]], double** [[TMP9]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP11:%.*]] = load double*, double** [[_TMP2]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store double* [[TMP11]], double** [[TMP10]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP11:%.*]] = load double*, double** [[_TMP2]], align 4 +// CHECK4-NEXT: store double* [[TMP11]], double** [[TMP10]], align 4 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK4-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 4 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK4-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !5 +// CHECK4-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 4 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -596,7 +596,7 @@ int main() { // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // @@ -609,7 +609,7 @@ int main() { // CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // @@ -622,7 +622,7 @@ int main() { // CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK7-NEXT: ret i32 0 // // @@ -635,7 +635,7 @@ int main() { // CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK8-NEXT: ret i32 0 // // @@ -660,14 +660,14 @@ int main() { // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) @@ -700,7 +700,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i64 [[TMP4]]) #[[ATTR4]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT4]] // CHECK9: omp_offload.cont4: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -708,27 +708,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP14]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done5: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP15]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -736,7 +736,7 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // @@ -748,7 +748,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -778,12 +778,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -803,37 +803,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 -// CHECK9-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8, !llvm.access.group !6 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK9-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK9-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* // CHECK9-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP10]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !6 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -847,14 +847,14 @@ int main() { // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done8: @@ -862,17 +862,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK9-SAME: (i64 noundef [[I:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i64 [[I:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 @@ -882,7 +882,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -920,23 +920,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I1]], align 4, !llvm.access.group !12 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I1]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -962,14 +962,14 @@ int main() { // CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -987,17 +987,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP4]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1008,7 +1008,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1022,7 +1022,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1031,17 +1031,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1049,7 +1049,7 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // @@ -1061,7 +1061,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1090,12 +1090,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1115,37 +1115,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !15 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !15 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !15 -// CHECK9-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8, !llvm.access.group !15 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !15 +// CHECK9-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK9-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* // CHECK9-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !15 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1159,14 +1159,14 @@ int main() { // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done8: @@ -1174,17 +1174,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1195,7 +1195,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1209,7 +1209,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1245,14 +1245,14 @@ int main() { // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) @@ -1285,7 +1285,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i64 [[TMP4]]) #[[ATTR4]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT4]] // CHECK10: omp_offload.cont4: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1293,27 +1293,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP14]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done5: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP15]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1321,7 +1321,7 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // @@ -1333,7 +1333,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1363,12 +1363,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1388,37 +1388,37 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8, !llvm.access.group !6 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 // CHECK10-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK10-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[ARRAYIDX5]] to i8* // CHECK10-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP10]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !6 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -1432,14 +1432,14 @@ int main() { // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done8: @@ -1447,17 +1447,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK10-SAME: (i64 noundef [[I:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i64 [[I:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 @@ -1467,7 +1467,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1505,23 +1505,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I1]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I1]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -1547,14 +1547,14 @@ int main() { // CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -1572,17 +1572,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP4]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1593,7 +1593,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1607,7 +1607,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1616,17 +1616,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1634,7 +1634,7 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // @@ -1646,7 +1646,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1675,12 +1675,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1700,37 +1700,37 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8, !llvm.access.group !15 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 // CHECK10-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK10-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* // CHECK10-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !15 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -1744,14 +1744,14 @@ int main() { // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done8: @@ -1759,17 +1759,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1780,7 +1780,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1794,7 +1794,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1830,14 +1830,14 @@ int main() { // CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) @@ -1869,7 +1869,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i32 [[TMP4]]) #[[ATTR4]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT4]] // CHECK11: omp_offload.cont4: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -1877,27 +1877,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP14]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done5: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP15]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1905,7 +1905,7 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // @@ -1917,7 +1917,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1947,12 +1947,12 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1972,35 +1972,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !7 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7 -// CHECK11-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4, !llvm.access.group !7 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK11-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* // CHECK11-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP10]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !7 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -2014,14 +2014,14 @@ int main() { // CHECK11-NEXT: store i32 2, i32* [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -2029,17 +2029,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK11-SAME: (i32 noundef [[I:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32 [[I:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 @@ -2048,7 +2048,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2086,23 +2086,23 @@ int main() { // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I1]], align 4, !llvm.access.group !13 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I1]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -2128,14 +2128,14 @@ int main() { // CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -2153,17 +2153,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP4]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2174,7 +2174,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2188,7 +2188,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2197,17 +2197,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2215,7 +2215,7 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // @@ -2227,7 +2227,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2256,12 +2256,12 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2281,35 +2281,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !16 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !16 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] -// CHECK11-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !16 -// CHECK11-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !16 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !16 +// CHECK11-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK11-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* // CHECK11-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !16 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -2323,14 +2323,14 @@ int main() { // CHECK11-NEXT: store i32 2, i32* [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -2338,17 +2338,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2359,7 +2359,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2373,7 +2373,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2409,14 +2409,14 @@ int main() { // CHECK12-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) @@ -2448,7 +2448,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i32 [[TMP4]]) #[[ATTR4]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT4]] // CHECK12: omp_offload.cont4: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2456,27 +2456,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP14]], [[OMP_OFFLOAD_CONT4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done5: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP15]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2484,7 +2484,7 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // @@ -2496,7 +2496,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2526,12 +2526,12 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2551,35 +2551,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !7 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7 -// CHECK12-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4, !llvm.access.group !7 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load %struct.S*, %struct.S** [[_TMP2]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK12-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* // CHECK12-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[TMP10]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !7 +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -2593,14 +2593,14 @@ int main() { // CHECK12-NEXT: store i32 2, i32* [[I]], align 4 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK12: .omp.final.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done7: @@ -2608,17 +2608,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK12-SAME: (i32 noundef [[I:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32 [[I:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 @@ -2627,7 +2627,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2665,23 +2665,23 @@ int main() { // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I1]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I1]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -2707,14 +2707,14 @@ int main() { // CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -2732,17 +2732,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP4]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2753,7 +2753,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2767,7 +2767,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2776,17 +2776,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2794,7 +2794,7 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // @@ -2806,7 +2806,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2835,12 +2835,12 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2860,35 +2860,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !16 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !16 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] -// CHECK12-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !16 -// CHECK12-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !16 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !16 +// CHECK12-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK12-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* // CHECK12-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !16 +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -2902,14 +2902,14 @@ int main() { // CHECK12-NEXT: store i32 2, i32* [[I]], align 4 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK12: .omp.final.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done7: @@ -2917,17 +2917,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2938,7 +2938,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2952,7 +2952,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2998,14 +2998,14 @@ int main() { // CHECK13-NEXT: [[I17:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3017,12 +3017,12 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK13-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -3059,14 +3059,14 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -3095,7 +3095,7 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND18]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK13: omp.inner.for.end26: // CHECK13-NEXT: store i32 2, i32* [[I12]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[ARRAY_BEGIN27:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN27]], i64 2 @@ -3103,27 +3103,27 @@ int main() { // CHECK13: arraydestroy.body28: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST29:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_INNER_FOR_END26]] ], [ [[ARRAYDESTROY_ELEMENT30:%.*]], [[ARRAYDESTROY_BODY28]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT30]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST29]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT30]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT30]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE31:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT30]], [[ARRAY_BEGIN27]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE31]], label [[ARRAYDESTROY_DONE32:%.*]], label [[ARRAYDESTROY_BODY28]] // CHECK13: arraydestroy.done32: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP19]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3131,17 +3131,17 @@ int main() { // CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // @@ -3165,14 +3165,14 @@ int main() { // CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3184,12 +3184,12 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK13-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -3226,14 +3226,14 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -3244,17 +3244,17 @@ int main() { // CHECK13: arraydestroy.body13: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK13: arraydestroy.done17: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP14]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3265,7 +3265,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3274,7 +3274,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3288,17 +3288,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3306,22 +3306,22 @@ int main() { // CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3332,7 +3332,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3346,7 +3346,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3385,14 +3385,14 @@ int main() { // CHECK14-NEXT: [[I17:%.*]] = alloca i32, align 4 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 8 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3404,12 +3404,12 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK14-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -3446,14 +3446,14 @@ int main() { // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done11: @@ -3482,7 +3482,7 @@ int main() { // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND18]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK14: omp.inner.for.end26: // CHECK14-NEXT: store i32 2, i32* [[I12]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[ARRAY_BEGIN27:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN27]], i64 2 @@ -3490,27 +3490,27 @@ int main() { // CHECK14: arraydestroy.body28: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST29:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_INNER_FOR_END26]] ], [ [[ARRAYDESTROY_ELEMENT30:%.*]], [[ARRAYDESTROY_BODY28]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT30]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST29]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT30]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT30]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE31:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT30]], [[ARRAY_BEGIN27]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE31]], label [[ARRAYDESTROY_DONE32:%.*]], label [[ARRAYDESTROY_BODY28]] // CHECK14: arraydestroy.done32: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP19]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3518,17 +3518,17 @@ int main() { // CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // @@ -3552,14 +3552,14 @@ int main() { // CHECK14-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK14-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK14-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3571,12 +3571,12 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK14-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -3613,14 +3613,14 @@ int main() { // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK14-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done11: @@ -3631,17 +3631,17 @@ int main() { // CHECK14: arraydestroy.body13: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK14: arraydestroy.done17: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP14]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3652,7 +3652,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3661,7 +3661,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3675,17 +3675,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3693,22 +3693,22 @@ int main() { // CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3719,7 +3719,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3733,7 +3733,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3772,14 +3772,14 @@ int main() { // CHECK15-NEXT: [[I16:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3791,12 +3791,12 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK15-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -3831,14 +3831,14 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: @@ -3867,7 +3867,7 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND17]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK15: omp.inner.for.end25: // CHECK15-NEXT: store i32 2, i32* [[I11]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[ARRAY_BEGIN26:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN26]], i32 2 @@ -3875,27 +3875,27 @@ int main() { // CHECK15: arraydestroy.body27: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST28:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_INNER_FOR_END25]] ], [ [[ARRAYDESTROY_ELEMENT29:%.*]], [[ARRAYDESTROY_BODY27]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT29]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST28]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT29]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT29]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE30:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT29]], [[ARRAY_BEGIN26]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE30]], label [[ARRAYDESTROY_DONE31:%.*]], label [[ARRAYDESTROY_BODY27]] // CHECK15: arraydestroy.done31: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP19]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3903,17 +3903,17 @@ int main() { // CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // @@ -3937,14 +3937,14 @@ int main() { // CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3956,12 +3956,12 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -3996,14 +3996,14 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: @@ -4014,17 +4014,17 @@ int main() { // CHECK15: arraydestroy.body12: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK15: arraydestroy.done16: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP14]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4035,7 +4035,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4044,7 +4044,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4058,17 +4058,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4076,22 +4076,22 @@ int main() { // CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4102,7 +4102,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4116,7 +4116,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4155,14 +4155,14 @@ int main() { // CHECK16-NEXT: [[I16:%.*]] = alloca i32, align 4 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S* undef, %struct.S** [[_TMP1]], align 4 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -4174,12 +4174,12 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK16-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -4214,14 +4214,14 @@ int main() { // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK16-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN9]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done10: @@ -4250,7 +4250,7 @@ int main() { // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND17]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK16: omp.inner.for.end25: // CHECK16-NEXT: store i32 2, i32* [[I11]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[ARRAY_BEGIN26:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN26]], i32 2 @@ -4258,27 +4258,27 @@ int main() { // CHECK16: arraydestroy.body27: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST28:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_INNER_FOR_END25]] ], [ [[ARRAYDESTROY_ELEMENT29:%.*]], [[ARRAYDESTROY_BODY27]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT29]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST28]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT29]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT29]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE30:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT29]], [[ARRAY_BEGIN26]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE30]], label [[ARRAYDESTROY_DONE31:%.*]], label [[ARRAYDESTROY_BODY27]] // CHECK16: arraydestroy.done31: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP19]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4286,17 +4286,17 @@ int main() { // CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // @@ -4320,14 +4320,14 @@ int main() { // CHECK16-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK16-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK16-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -4339,12 +4339,12 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -4379,14 +4379,14 @@ int main() { // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK16-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done10: @@ -4397,17 +4397,17 @@ int main() { // CHECK16: arraydestroy.body12: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK16: arraydestroy.done16: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP14]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4418,7 +4418,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4427,7 +4427,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4441,17 +4441,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4459,22 +4459,22 @@ int main() { // CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4485,7 +4485,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4499,7 +4499,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_simd_reduction_codegen.cpp b/clang/test/OpenMP/distribute_simd_reduction_codegen.cpp index 104c63b0518e6727f9acfed288dda02a4e4f2587..fdbabd63429ff9b1c50e41749cf443d12488b328 100644 --- a/clang/test/OpenMP/distribute_simd_reduction_codegen.cpp +++ b/clang/test/OpenMP/distribute_simd_reduction_codegen.cpp @@ -114,12 +114,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 -// CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -129,7 +129,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -169,27 +169,27 @@ int main() { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -247,7 +247,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 @@ -257,7 +257,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -297,27 +297,27 @@ int main() { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -375,12 +375,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 -// CHECK2-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -390,7 +390,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -430,27 +430,27 @@ int main() { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -508,7 +508,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK2-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 @@ -518,7 +518,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -558,27 +558,27 @@ int main() { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -635,12 +635,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 -// CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 @@ -649,7 +649,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -689,27 +689,27 @@ int main() { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -766,7 +766,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 @@ -775,7 +775,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -815,27 +815,27 @@ int main() { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -892,12 +892,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 -// CHECK4-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 @@ -906,7 +906,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -946,27 +946,27 @@ int main() { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1023,7 +1023,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK4-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 @@ -1032,7 +1032,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1072,27 +1072,27 @@ int main() { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1163,7 +1163,7 @@ int main() { // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK5-NEXT: ret i32 [[CALL]] // // @@ -1263,7 +1263,7 @@ int main() { // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK6-NEXT: ret i32 [[CALL]] // // @@ -1363,7 +1363,7 @@ int main() { // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK7-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK7-NEXT: ret i32 [[CALL]] // // @@ -1463,7 +1463,7 @@ int main() { // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK8-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK8-NEXT: ret i32 [[CALL]] // // @@ -1524,12 +1524,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 -// CHECK9-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -1539,7 +1539,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1580,30 +1580,30 @@ int main() { // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1635,12 +1635,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 -// CHECK10-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -1650,7 +1650,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1691,30 +1691,30 @@ int main() { // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -1746,7 +1746,7 @@ int main() { // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: ret i32 0 // // @@ -1756,6 +1756,6 @@ int main() { // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK12-NEXT: ret i32 0 // diff --git a/clang/test/OpenMP/for_codegen.cpp b/clang/test/OpenMP/for_codegen.cpp index ff7da76dd9974ce67fef95434f11bc5bcf552282..64652e530f6a71d904e62e8e293bb7e5e99186ea 100644 --- a/clang/test/OpenMP/for_codegen.cpp +++ b/clang/test/OpenMP/for_codegen.cpp @@ -220,7 +220,7 @@ void loop_with_counter_collapse4() { } } -// CHECK-LABEL: define {{.*void}} @{{.*}}without_schedule_clause{{.*}}(float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}) +// CHECK-LABEL: define {{.*void}} @{{.*}}without_schedule_clause{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) void without_schedule_clause(float *a, float *b, float *c, float *d) { // CHECK: [[GTID:%.+]] = call i32 @__kmpc_global_thread_num([[IDENT_T_TY]]* [[DEFAULT_LOC:[@%].+]]) #pragma omp for nowait @@ -261,7 +261,7 @@ void without_schedule_clause(float *a, float *b, float *c, float *d) { // CHECK: ret void } -// CHECK-LABEL: define {{.*void}} @{{.*}}static_not_chunked{{.*}}(float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}) +// CHECK-LABEL: define {{.*void}} @{{.*}}static_not_chunked{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) void static_not_chunked(float *a, float *b, float *c, float *d) { // CHECK: [[GTID:%.+]] = call i32 @__kmpc_global_thread_num([[IDENT_T_TY]]* [[DEFAULT_LOC:[@%].+]]) #pragma omp for schedule(static) @@ -302,7 +302,7 @@ void static_not_chunked(float *a, float *b, float *c, float *d) { // CHECK: ret void } -// CHECK-LABEL: define {{.*void}} @{{.*}}static_chunked{{.*}}(float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}) +// CHECK-LABEL: define {{.*void}} @{{.*}}static_chunked{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) void static_chunked(float *a, float *b, float *c, float *d) { // CHECK: [[GTID:%.+]] = call i32 @__kmpc_global_thread_num([[IDENT_T_TY]]* [[DEFAULT_LOC:[@%].+]]) #pragma omp for schedule(monotonic: static, 5) @@ -362,7 +362,7 @@ void static_chunked(float *a, float *b, float *c, float *d) { // CHECK: ret void } -// CHECK-LABEL: define {{.*void}} @{{.*}}dynamic1{{.*}}(float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}) +// CHECK-LABEL: define {{.*void}} @{{.*}}dynamic1{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) void dynamic1(float *a, float *b, float *c, float *d) { // CHECK: [[GTID:%.+]] = call i32 @__kmpc_global_thread_num([[IDENT_T_TY]]* [[DEFAULT_LOC:[@%].+]]) #pragma omp for schedule(nonmonotonic: dynamic) @@ -404,7 +404,7 @@ void dynamic1(float *a, float *b, float *c, float *d) { // CHECK: ret void } -// CHECK-LABEL: define {{.*void}} @{{.*}}guided7{{.*}}(float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}) +// CHECK-LABEL: define {{.*void}} @{{.*}}guided7{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) void guided7(float *a, float *b, float *c, float *d) { // CHECK: [[GTID:%.+]] = call i32 @__kmpc_global_thread_num([[IDENT_T_TY]]* [[DEFAULT_LOC:[@%].+]]) #pragma omp for schedule(guided, 7) @@ -447,7 +447,7 @@ void guided7(float *a, float *b, float *c, float *d) { // CHECK: ret void } -// CHECK-LABEL: define {{.*void}} @{{.*}}test_auto{{.*}}(float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}) +// CHECK-LABEL: define {{.*void}} @{{.*}}test_auto{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) void test_auto(float *a, float *b, float *c, float *d) { unsigned int x = 0; unsigned int y = 0; @@ -493,7 +493,7 @@ void test_auto(float *a, float *b, float *c, float *d) { // CHECK: ret void } -// CHECK-LABEL: define {{.*void}} @{{.*}}runtime{{.*}}(float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}) +// CHECK-LABEL: define {{.*void}} @{{.*}}runtime{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) void runtime(float *a, float *b, float *c, float *d) { int x = 0; // CHECK: [[GTID:%.+]] = call i32 @__kmpc_global_thread_num([[IDENT_T_TY]]* [[DEFAULT_LOC:[@%].+]]) @@ -566,7 +566,7 @@ void parallel_for(float *a) { #pragma omp for schedule(static, 5) // TERM_DEBUG-NOT: __kmpc_global_thread_num // TERM_DEBUG: call void @__kmpc_for_static_init_4u({{.+}}), !dbg [[DBG_LOC:![0-9]+]] - // TERM_DEBUG: invoke noundef i32 {{.*}}foo{{.*}}() + // TERM_DEBUG: invoke i32 {{.*}}foo{{.*}}() // TERM_DEBUG: unwind label %[[TERM_LPAD:.+]], // TERM_DEBUG-NOT: __kmpc_global_thread_num // TERM_DEBUG: call void @__kmpc_for_static_fini({{.+}}), !dbg [[DBG_LOC]] diff --git a/clang/test/OpenMP/for_firstprivate_codegen.cpp b/clang/test/OpenMP/for_firstprivate_codegen.cpp index 858c16cbca947c1809d1612db8addd6738632e12..88538c93c302c1d91714cbe9cdece3400322144b 100644 --- a/clang/test/OpenMP/for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/for_firstprivate_codegen.cpp @@ -151,33 +151,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -190,7 +190,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -201,14 +201,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -216,12 +216,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -229,7 +229,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -237,7 +237,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -256,7 +256,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -296,17 +296,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done1: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP2]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR]], %struct.S* noundef nonnull align 4 dereferenceable(4) @var, %struct.St* noundef [[AGG_TMP2]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP2]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], %struct.S* nonnull align 4 dereferenceable(4) @var, %struct.St* [[AGG_TMP2]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[SIVAR]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -363,34 +363,34 @@ int main() { // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done9: // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -398,17 +398,17 @@ int main() { // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -421,14 +421,14 @@ int main() { // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP1]]) @@ -439,17 +439,17 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP3]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -462,7 +462,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -482,7 +482,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -491,17 +491,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -509,12 +509,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -568,18 +568,18 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done6: // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP10]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP10]], %struct.St* [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK1-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 @@ -636,14 +636,14 @@ int main() { // CHECK1-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done15: @@ -654,7 +654,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -662,22 +662,22 @@ int main() { // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -689,7 +689,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -705,7 +705,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -724,7 +724,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -744,33 +744,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -783,7 +783,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -794,14 +794,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -809,12 +809,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -822,7 +822,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -830,7 +830,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -849,7 +849,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -889,17 +889,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done1: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP2]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR]], %struct.S* noundef nonnull align 4 dereferenceable(4) @var, %struct.St* noundef [[AGG_TMP2]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP2]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], %struct.S* nonnull align 4 dereferenceable(4) @var, %struct.St* [[AGG_TMP2]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[SIVAR]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -956,34 +956,34 @@ int main() { // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done9: // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -991,17 +991,17 @@ int main() { // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // @@ -1014,14 +1014,14 @@ int main() { // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP1]]) @@ -1032,17 +1032,17 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP3]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1055,7 +1055,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1075,7 +1075,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1084,17 +1084,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1102,12 +1102,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1161,18 +1161,18 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done6: // CHECK2-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP10]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP10]], %struct.St* [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK2-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 @@ -1229,14 +1229,14 @@ int main() { // CHECK2-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done15: @@ -1247,7 +1247,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1255,22 +1255,22 @@ int main() { // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1282,7 +1282,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1298,7 +1298,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1317,7 +1317,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1337,33 +1337,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1376,7 +1376,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1387,14 +1387,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1402,12 +1402,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1415,7 +1415,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1423,7 +1423,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1442,7 +1442,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -1455,12 +1455,12 @@ int main() { // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1533,7 +1533,7 @@ int main() { // CHECK3-NEXT: store i32* [[TMP16]], i32** [[TMP15]], align 8 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store i32* [[SIVAR3]], i32** [[TMP17]], align 8 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1562,33 +1562,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1601,7 +1601,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1612,14 +1612,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1627,12 +1627,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1640,7 +1640,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -1648,7 +1648,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1667,7 +1667,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -1697,12 +1697,12 @@ int main() { // CHECK4-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP5]](i8* noundef [[TMP3]]) +// CHECK4-NEXT: call void [[TMP5]](i8* [[TMP3]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 @@ -1714,7 +1714,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1805,7 +1805,7 @@ int main() { // CHECK4-NEXT: [[TMP19:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP20:%.*]] = load i8*, i8** [[TMP18]], align 8 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast i8* [[TMP20]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP21]](i8* noundef [[TMP19]]) +// CHECK4-NEXT: call void [[TMP21]](i8* [[TMP19]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1823,7 +1823,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@var_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, i32 }>*, align 8 @@ -1848,3 +1848,4 @@ int main() { // CHECK4-NEXT: call void @__cxx_global_var_init.2() // CHECK4-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/for_lastprivate_codegen.cpp b/clang/test/OpenMP/for_lastprivate_codegen.cpp index c78c559ab48ac02391b62a2001bf97efe2b7ff5f..e06364ee01c33d5c8533d633c8e01a4372cb4edf 100644 --- a/clang/test/OpenMP/for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/for_lastprivate_codegen.cpp @@ -370,40 +370,40 @@ int main() { // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32* @_ZZ4mainE5sivar) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -411,22 +411,22 @@ int main() { // CHECK1-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -434,12 +434,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -481,12 +481,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR4]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -524,7 +524,7 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM7]] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[ARRAYIDX8]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX8]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[SIVAR5]], align 4 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP16]] @@ -560,25 +560,25 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL12:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL12:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done13: -// CHECK1-NEXT: [[CALL14:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[TMP3]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK1-NEXT: [[CALL14:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[SIVAR5]], align 4 // CHECK1-NEXT: store i32 [[TMP28]], i32* [[TMP4]], align 4 // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1: .omp.lastprivate.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done16: @@ -589,17 +589,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -678,7 +678,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -759,7 +759,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -850,15 +850,15 @@ int main() { // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 128 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef [[SST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 128 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 128 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP1]]) @@ -869,17 +869,17 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP3]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -979,7 +979,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1117,7 +1117,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1128,7 +1128,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1137,7 +1137,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1151,27 +1151,27 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK1-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1179,12 +1179,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1228,13 +1228,13 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK1-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -1274,7 +1274,7 @@ int main() { // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[ARRAYIDX10]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP16]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX10]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP16]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1306,24 +1306,24 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL13:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL13:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done14: // CHECK1-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK1-NEXT: [[CALL15:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[TMP5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP28]]) +// CHECK1-NEXT: [[CALL15:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP28]]) // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1: .omp.lastprivate.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN16]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN16]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done17: @@ -1334,17 +1334,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1355,7 +1355,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK1-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 @@ -1426,7 +1426,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1513,7 +1513,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1527,7 +1527,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1546,40 +1546,40 @@ int main() { // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32* @_ZZ4mainE5sivar) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -1587,22 +1587,22 @@ int main() { // CHECK2-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK2-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1610,12 +1610,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1657,12 +1657,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR4]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1700,7 +1700,7 @@ int main() { // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM7]] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[ARRAYIDX8]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX8]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[SIVAR5]], align 4 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP16]] @@ -1736,25 +1736,25 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL12:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL12:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done13: -// CHECK2-NEXT: [[CALL14:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[TMP3]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK2-NEXT: [[CALL14:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[SIVAR5]], align 4 // CHECK2-NEXT: store i32 [[TMP28]], i32* [[TMP4]], align 4 // CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK2: .omp.lastprivate.done: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done16: @@ -1765,17 +1765,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1854,7 +1854,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1935,7 +1935,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2026,15 +2026,15 @@ int main() { // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 128 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK2-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef [[SST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK2-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 128 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 128 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP1]]) @@ -2045,17 +2045,17 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP3]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -2155,7 +2155,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2293,7 +2293,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2304,7 +2304,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2313,7 +2313,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2327,27 +2327,27 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK2-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK2-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2355,12 +2355,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2404,13 +2404,13 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK2-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -2450,7 +2450,7 @@ int main() { // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[ARRAYIDX10]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP16]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX10]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP16]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2482,24 +2482,24 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL13:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL13:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done14: // CHECK2-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK2-NEXT: [[CALL15:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[TMP5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP28]]) +// CHECK2-NEXT: [[CALL15:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP28]]) // CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK2: .omp.lastprivate.done: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN16]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN16]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done17: @@ -2510,17 +2510,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2531,7 +2531,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK2-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 @@ -2602,7 +2602,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2689,7 +2689,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2703,7 +2703,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2718,15 +2718,15 @@ int main() { // CHECK3-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -2734,12 +2734,12 @@ int main() { // CHECK3-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -2804,7 +2804,7 @@ int main() { // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP4]], align 8 // CHECK3-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE0_clEv(%class.anon.1* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE0_clEv(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2822,7 +2822,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2918,7 +2918,7 @@ int main() { // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: [[TMP24:%.*]] = load i32*, i32** [[_TMP13]], align 8 // CHECK3-NEXT: store i32* [[TMP24]], i32** [[TMP23]], align 8 -// CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2961,7 +2961,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK3-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { +// CHECK3-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK3-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 @@ -2994,7 +2994,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE0_clEv -// CHECK3-SAME: (%class.anon.1* noundef [[THIS:%.*]]) #[[ATTR2]] align 2 { +// CHECK3-SAME: (%class.anon.1* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 // CHECK3-NEXT: store %class.anon.1* [[THIS]], %class.anon.1** [[THIS_ADDR]], align 8 @@ -3033,7 +3033,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3150,7 +3150,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3253,7 +3253,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3321,7 +3321,7 @@ int main() { // CHECK3-NEXT: store i32* [[TMP14]], i32** [[TMP13]], align 8 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_2]], %class.anon.2* [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store i32* [[SIVAR3]], i32** [[TMP15]], align 8 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.2* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.2* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3358,7 +3358,7 @@ int main() { // CHECK4-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 // CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 @@ -3378,12 +3378,12 @@ int main() { // CHECK4-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP5]](i8* noundef [[TMP3]]) +// CHECK4-NEXT: call void [[TMP5]](i8* [[TMP3]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -3391,12 +3391,12 @@ int main() { // CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 @@ -3408,7 +3408,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3497,7 +3497,7 @@ int main() { // CHECK4-NEXT: [[TMP18:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP19:%.*]] = load i8*, i8** [[TMP17]], align 8 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP20]](i8* noundef [[TMP18]]) +// CHECK4-NEXT: call void [[TMP20]](i8* [[TMP18]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3528,7 +3528,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@g1_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>*, align 8 @@ -3546,7 +3546,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -3627,7 +3627,7 @@ int main() { // CHECK4-NEXT: [[TMP12:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP11]], align 8 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP14]](i8* noundef [[TMP12]]) +// CHECK4-NEXT: call void [[TMP14]](i8* [[TMP12]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3645,7 +3645,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3758,7 +3758,7 @@ int main() { // CHECK4-NEXT: [[TMP24:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP25:%.*]] = load i8*, i8** [[TMP23]], align 8 // CHECK4-NEXT: [[TMP26:%.*]] = bitcast i8* [[TMP25]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP26]](i8* noundef [[TMP24]]) +// CHECK4-NEXT: call void [[TMP26]](i8* [[TMP24]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3801,7 +3801,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@g1_block_invoke_2 -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 @@ -3834,7 +3834,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3951,7 +3951,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>*, align 8 @@ -3992,7 +3992,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4102,40 +4102,40 @@ int main() { // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32* @_ZZ4mainE5sivar) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP2]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK5-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -4143,22 +4143,22 @@ int main() { // CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK5-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4166,12 +4166,12 @@ int main() { // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4213,12 +4213,12 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR4]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -4256,7 +4256,7 @@ int main() { // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM7]] -// CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[ARRAYIDX8]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK5-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX8]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[SIVAR5]], align 4 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP16]] @@ -4292,25 +4292,25 @@ int main() { // CHECK5: omp.arraycpy.body: // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK5-NEXT: [[CALL12:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK5-NEXT: [[CALL12:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] // CHECK5: omp.arraycpy.done13: -// CHECK5-NEXT: [[CALL14:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[TMP3]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK5-NEXT: [[CALL14:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[SIVAR5]], align 4 // CHECK5-NEXT: store i32 [[TMP28]], i32* [[TMP4]], align 4 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done16: @@ -4321,17 +4321,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4410,7 +4410,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4491,7 +4491,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4600,15 +4600,15 @@ int main() { // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 128 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK5-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef [[SST]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK5-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 128 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 128 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP1]]) @@ -4619,17 +4619,17 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP3]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -4729,7 +4729,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4867,7 +4867,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4878,7 +4878,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4892,7 +4892,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4901,27 +4901,27 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK5-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4929,12 +4929,12 @@ int main() { // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4978,13 +4978,13 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK5-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -5024,7 +5024,7 @@ int main() { // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] -// CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[ARRAYIDX10]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP16]]) +// CHECK5-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX10]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP16]]) // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -5056,24 +5056,24 @@ int main() { // CHECK5: omp.arraycpy.body: // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK5-NEXT: [[CALL13:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK5-NEXT: [[CALL13:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] // CHECK5: omp.arraycpy.done14: // CHECK5-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK5-NEXT: [[CALL15:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[TMP5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP28]]) +// CHECK5-NEXT: [[CALL15:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP28]]) // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR5]] // CHECK5-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN16]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN16]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done17: @@ -5084,17 +5084,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5105,7 +5105,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK5-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 @@ -5176,7 +5176,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5263,7 +5263,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5277,7 +5277,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5296,40 +5296,40 @@ int main() { // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK6-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32* @_ZZ4mainE5sivar) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP2]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK6-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -5337,22 +5337,22 @@ int main() { // CHECK6-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK6-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5360,12 +5360,12 @@ int main() { // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5407,12 +5407,12 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR4]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -5450,7 +5450,7 @@ int main() { // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 // CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM7]] -// CHECK6-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[ARRAYIDX8]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK6-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX8]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[SIVAR5]], align 4 // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP16]] @@ -5486,25 +5486,25 @@ int main() { // CHECK6: omp.arraycpy.body: // CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK6-NEXT: [[CALL12:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK6-NEXT: [[CALL12:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] // CHECK6: omp.arraycpy.done13: -// CHECK6-NEXT: [[CALL14:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[TMP3]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK6-NEXT: [[CALL14:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[SIVAR5]], align 4 // CHECK6-NEXT: store i32 [[TMP28]], i32* [[TMP4]], align 4 // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6: .omp.lastprivate.done: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK6-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done16: @@ -5515,17 +5515,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5604,7 +5604,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5685,7 +5685,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5794,15 +5794,15 @@ int main() { // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 // CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 128 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK6-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef [[SST]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK6-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 128 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 128 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP1]]) @@ -5813,17 +5813,17 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP3]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -5923,7 +5923,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6061,7 +6061,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6072,7 +6072,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6086,7 +6086,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6095,27 +6095,27 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK6-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK6-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6123,12 +6123,12 @@ int main() { // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6172,13 +6172,13 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: // CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK6-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -6218,7 +6218,7 @@ int main() { // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK6-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] -// CHECK6-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[ARRAYIDX10]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP16]]) +// CHECK6-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX10]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP16]]) // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -6250,24 +6250,24 @@ int main() { // CHECK6: omp.arraycpy.body: // CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK6-NEXT: [[CALL13:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK6-NEXT: [[CALL13:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] // CHECK6: omp.arraycpy.done14: // CHECK6-NEXT: [[TMP28:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 -// CHECK6-NEXT: [[CALL15:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[TMP5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP28]]) +// CHECK6-NEXT: [[CALL15:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP28]]) // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6: .omp.lastprivate.done: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR5]] // CHECK6-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK6-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN16]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN16]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done17: @@ -6278,17 +6278,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -6299,7 +6299,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK6-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 @@ -6370,7 +6370,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6457,7 +6457,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6471,7 +6471,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -6486,15 +6486,15 @@ int main() { // CHECK7-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 // CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK7-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) // CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 // CHECK7-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK7-NEXT: ret i32 0 // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK7-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -6502,12 +6502,12 @@ int main() { // CHECK7-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK7-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -6572,7 +6572,7 @@ int main() { // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 // CHECK7-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP4]], align 8 // CHECK7-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE0_clEv(%class.anon.1* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE0_clEv(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -6590,7 +6590,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6686,7 +6686,7 @@ int main() { // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK7-NEXT: [[TMP24:%.*]] = load i32*, i32** [[_TMP13]], align 8 // CHECK7-NEXT: store i32* [[TMP24]], i32** [[TMP23]], align 8 -// CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -6729,7 +6729,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK7-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { +// CHECK7-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK7-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 @@ -6762,7 +6762,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE0_clEv -// CHECK7-SAME: (%class.anon.1* noundef [[THIS:%.*]]) #[[ATTR2]] align 2 { +// CHECK7-SAME: (%class.anon.1* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 // CHECK7-NEXT: store %class.anon.1* [[THIS]], %class.anon.1** [[THIS_ADDR]], align 8 @@ -6801,7 +6801,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6918,7 +6918,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7021,7 +7021,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7089,7 +7089,7 @@ int main() { // CHECK7-NEXT: store i32* [[TMP14]], i32** [[TMP13]], align 8 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_2]], %class.anon.2* [[REF_TMP]], i32 0, i32 2 // CHECK7-NEXT: store i32* [[SIVAR3]], i32** [[TMP15]], align 8 -// CHECK7-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.2* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.2* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -7126,7 +7126,7 @@ int main() { // CHECK8-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 // CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK8-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) // CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 // CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 // CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 @@ -7146,12 +7146,12 @@ int main() { // CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP5]](i8* noundef [[TMP3]]) +// CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) // CHECK8-NEXT: ret i32 0 // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK8-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -7159,12 +7159,12 @@ int main() { // CHECK8-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK8-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(24) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 @@ -7176,7 +7176,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7265,7 +7265,7 @@ int main() { // CHECK8-NEXT: [[TMP18:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK8-NEXT: [[TMP19:%.*]] = load i8*, i8** [[TMP17]], align 8 // CHECK8-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP20]](i8* noundef [[TMP18]]) +// CHECK8-NEXT: call void [[TMP20]](i8* [[TMP18]]) // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -7296,7 +7296,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@g1_block_invoke -// CHECK8-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32, [84 x i8], i32 }>*, align 8 @@ -7314,7 +7314,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK8-SAME: (%struct.SS* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -7395,7 +7395,7 @@ int main() { // CHECK8-NEXT: [[TMP12:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK8-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP11]], align 8 // CHECK8-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP14]](i8* noundef [[TMP12]]) +// CHECK8-NEXT: call void [[TMP14]](i8* [[TMP12]]) // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -7413,7 +7413,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7526,7 +7526,7 @@ int main() { // CHECK8-NEXT: [[TMP24:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK8-NEXT: [[TMP25:%.*]] = load i8*, i8** [[TMP23]], align 8 // CHECK8-NEXT: [[TMP26:%.*]] = bitcast i8* [[TMP25]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP26]](i8* noundef [[TMP24]]) +// CHECK8-NEXT: call void [[TMP26]](i8* [[TMP24]]) // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -7569,7 +7569,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@g1_block_invoke_2 -// CHECK8-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 @@ -7602,7 +7602,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7719,7 +7719,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@___ZN2SSC2ERi_block_invoke -// CHECK8-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32* }>*, align 8 @@ -7760,7 +7760,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7858,3 +7858,4 @@ int main() { // CHECK8-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]]) // CHECK8-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/for_linear_codegen.cpp b/clang/test/OpenMP/for_linear_codegen.cpp index d7a1abefeb7e67d23145d0b65ad07f06f00bd144..a4e378c1ac80507bd68a29a979a2c3685bce08a4 100644 --- a/clang/test/OpenMP/for_linear_codegen.cpp +++ b/clang/test/OpenMP/for_linear_codegen.cpp @@ -193,21 +193,21 @@ int main() { // CHECK1-NEXT: [[PVAR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[LVAR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TEST]], i32 0, i32 0 // CHECK1-NEXT: store float* [[F]], float** [[PVAR]], align 8 // CHECK1-NEXT: store i64 0, i64* [[LVAR]], align 8 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64*)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[PVAR]], i64* [[LVAR]]) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP0]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -215,22 +215,22 @@ int main() { // CHECK1-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i64* noundef nonnull align 8 dereferenceable(8) [[LVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i64* nonnull align 8 dereferenceable(8) [[LVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -347,30 +347,30 @@ int main() { // CHECK1-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 // CHECK1-NEXT: [[PVAR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[LVAR:%.*]] = alloca i32*, align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef [[SST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 // CHECK1-NEXT: store i32* [[F]], i32** [[PVAR]], align 8 // CHECK1-NEXT: [[F1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 // CHECK1-NEXT: store i32* [[F1]], i32** [[LVAR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[LVAR]], align 8 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32**, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32** [[PVAR]], i32* [[TMP0]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -391,7 +391,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -545,7 +545,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -556,27 +556,27 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK1-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[LVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[LVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -694,17 +694,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -715,7 +715,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK1-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 @@ -727,7 +727,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -827,7 +827,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -836,7 +836,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -853,21 +853,21 @@ int main() { // CHECK2-NEXT: [[PVAR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[LVAR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TEST]], i32 0, i32 0 // CHECK2-NEXT: store float* [[F]], float** [[PVAR]], align 8 // CHECK2-NEXT: store i64 0, i64* [[LVAR]], align 8 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64*)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[PVAR]], i64* [[LVAR]]) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4:[0-9]+]] // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP0]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -875,22 +875,22 @@ int main() { // CHECK2-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK2-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i64* noundef nonnull align 8 dereferenceable(8) [[LVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i64* nonnull align 8 dereferenceable(8) [[LVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1007,30 +1007,30 @@ int main() { // CHECK2-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 // CHECK2-NEXT: [[PVAR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[LVAR:%.*]] = alloca i32*, align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK2-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef [[SST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK2-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 // CHECK2-NEXT: store i32* [[F]], i32** [[PVAR]], align 8 // CHECK2-NEXT: [[F1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 // CHECK2-NEXT: store i32* [[F1]], i32** [[LVAR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[LVAR]], align 8 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32**, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32** [[PVAR]], i32* [[TMP0]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -1051,7 +1051,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1205,7 +1205,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1216,27 +1216,27 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK2-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK2-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[LVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[LVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1354,17 +1354,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1375,7 +1375,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK2-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK2-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 @@ -1387,7 +1387,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1487,7 +1487,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1496,7 +1496,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1511,13 +1511,13 @@ int main() { // CHECK3-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -1525,12 +1525,12 @@ int main() { // CHECK3-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -1551,7 +1551,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1659,7 +1659,7 @@ int main() { // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: [[TMP28:%.*]] = load i32*, i32** [[_TMP11]], align 8 // CHECK3-NEXT: store i32* [[TMP28]], i32** [[TMP27]], align 8 -// CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1706,7 +1706,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK3-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { +// CHECK3-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK3-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 @@ -1739,7 +1739,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1890,7 +1890,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1972,7 +1972,7 @@ int main() { // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP20:%.*]] = load i32*, i32** [[_TMP3]], align 8 // CHECK3-NEXT: store i32* [[TMP20]], i32** [[TMP19]], align 8 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2010,15 +2010,15 @@ int main() { // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// CHECK4-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -2026,12 +2026,12 @@ int main() { // CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -2043,7 +2043,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2145,7 +2145,7 @@ int main() { // CHECK4-NEXT: [[TMP23:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP24:%.*]] = load i8*, i8** [[TMP22]], align 8 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8* [[TMP24]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP25]](i8* noundef [[TMP23]]) +// CHECK4-NEXT: call void [[TMP25]](i8* [[TMP23]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2178,7 +2178,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@g1_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32*, i32 }>*, align 8 @@ -2194,7 +2194,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -2215,7 +2215,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2340,7 +2340,7 @@ int main() { // CHECK4-NEXT: [[TMP28:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP29:%.*]] = load i8*, i8** [[TMP27]], align 8 // CHECK4-NEXT: [[TMP30:%.*]] = bitcast i8* [[TMP29]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP30]](i8* noundef [[TMP28]]) +// CHECK4-NEXT: call void [[TMP30]](i8* [[TMP28]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2387,7 +2387,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@g1_block_invoke_2 -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 @@ -2420,7 +2420,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2570,3 +2570,4 @@ int main() { // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) // CHECK4-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/for_private_codegen.cpp b/clang/test/OpenMP/for_private_codegen.cpp index e8c591adaf0468de20c1b696510d14a21f8bc4b4..21f14d5425e4497055abf99b13f7fcfa8f9481b0 100644 --- a/clang/test/OpenMP/for_private_codegen.cpp +++ b/clang/test/OpenMP/for_private_codegen.cpp @@ -118,18 +118,18 @@ int main() { // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK1-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -137,27 +137,27 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -165,12 +165,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -200,12 +200,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -262,14 +262,14 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -280,17 +280,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -360,14 +360,14 @@ int main() { // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 @@ -377,17 +377,17 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -398,7 +398,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -412,7 +412,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -421,17 +421,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -439,12 +439,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -473,12 +473,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -535,14 +535,14 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -553,17 +553,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -574,7 +574,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -588,7 +588,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -607,18 +607,18 @@ int main() { // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK2-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -626,27 +626,27 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -654,12 +654,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -689,12 +689,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[_TMP2]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -751,14 +751,14 @@ int main() { // CHECK2-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done8: @@ -769,17 +769,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -849,14 +849,14 @@ int main() { // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 @@ -866,17 +866,17 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -887,7 +887,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -901,7 +901,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -910,17 +910,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -928,12 +928,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -962,12 +962,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1024,14 +1024,14 @@ int main() { // CHECK2-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done8: @@ -1042,17 +1042,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1063,7 +1063,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1077,7 +1077,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1091,12 +1091,12 @@ int main() { // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1163,7 +1163,7 @@ int main() { // CHECK3-NEXT: store i32* [[SVAR]], i32** [[TMP12]], align 8 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store float* [[SFVAR]], float** [[TMP13]], align 8 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1187,12 +1187,12 @@ int main() { // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// CHECK4-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -1204,7 +1204,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1290,7 +1290,7 @@ int main() { // CHECK4-NEXT: [[TMP15:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP16:%.*]] = load i8*, i8** [[TMP14]], align 8 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8* [[TMP16]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP17]](i8* noundef [[TMP15]]) +// CHECK4-NEXT: call void [[TMP17]](i8* [[TMP15]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1308,7 +1308,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@g1_block_invoke_2 -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double*, i32, float }>*, align 8 @@ -1326,3 +1326,4 @@ int main() { // CHECK4-NEXT: store float 9.000000e+00, float* [[BLOCK_CAPTURE_ADDR3]], align 4 // CHECK4-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/for_reduction_codegen.cpp b/clang/test/OpenMP/for_reduction_codegen.cpp index d5585742f11b6e1597a8bb37726d829384ec8820..c6a883f4e033c68afd0ac060c09cbd62f1a220ea 100644 --- a/clang/test/OpenMP/for_reduction_codegen.cpp +++ b/clang/test/OpenMP/for_reduction_codegen.cpp @@ -545,38 +545,38 @@ int main() { // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_ELEMENT]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT1]], float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT1]], float 3.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_ELEMENT1]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT2]], float noundef 4.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT2]], float 4.000000e+00) // CHECK1-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], [10 x [4 x %struct.S]]* [[ARRS]], i32 0, i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 40 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef %struct.S** @_Z3foov() +// CHECK1-NEXT: [[CALL:%.*]] = call %struct.S** @_Z3foov() // CHECK1-NEXT: store %struct.S** [[CALL]], %struct.S*** [[VAR2]], align 8 // CHECK1-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[VVAR2]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 5 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP5:%.*]] // CHECK1: arrayctor.loop5: // CHECK1-NEXT: [[ARRAYCTOR_CUR6:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYCTOR_NEXT7:%.*]], [[ARRAYCTOR_LOOP5]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR6]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR6]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT7]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR6]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE8:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT7]], [[ARRAYCTOR_END4]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE8]], label [[ARRAYCTOR_CONT9:%.*]], label [[ARRAYCTOR_LOOP5]] @@ -608,7 +608,7 @@ int main() { // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [4 x %struct.S]*)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [4 x %struct.S]* [[TMP8]]) // CHECK1-NEXT: [[TMP9:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [4 x %struct.S]*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), [4 x %struct.S]* [[TMP9]]) -// CHECK1-NEXT: [[CALL10:%.*]] = call noundef i32 @_Z5tmainIiLi42EET_v() +// CHECK1-NEXT: [[CALL10:%.*]] = call i32 @_Z5tmainIiLi42EET_v() // CHECK1-NEXT: store i32 [[CALL10]], i32* [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) @@ -618,7 +618,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ARRAYCTOR_CONT9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5:[0-9]+]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done12: @@ -628,38 +628,38 @@ int main() { // CHECK1: arraydestroy.body14: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST15:%.*]] = phi %struct.S* [ [[TMP12]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT16:%.*]], [[ARRAYDESTROY_BODY14]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT16]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST15]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE17:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT16]], [[ARRAY_BEGIN13]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE17]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY14]] // CHECK1: arraydestroy.done18: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAY_BEGIN19:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN19]], i64 4 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY20:%.*]] // CHECK1: arraydestroy.body20: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST21:%.*]] = phi %struct.S* [ [[TMP13]], [[ARRAYDESTROY_DONE18]] ], [ [[ARRAYDESTROY_ELEMENT22:%.*]], [[ARRAYDESTROY_BODY20]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT22]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST21]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT22]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT22]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE23:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT22]], [[ARRAY_BEGIN19]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE23]], label [[ARRAYDESTROY_DONE24:%.*]], label [[ARRAYDESTROY_BODY20]] // CHECK1: arraydestroy.done24: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP14]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -667,12 +667,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [4 x %struct.S]* noundef nonnull align 4 dereferenceable(16) [[S_ARR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [4 x %struct.S]* nonnull align 4 dereferenceable(16) [[S_ARR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -726,9 +726,9 @@ int main() { // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store float 0.000000e+00, float* [[T_VAR3]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR4]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: store %struct.S* [[VAR4]], %struct.S** [[_TMP5]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR16]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR16]]) // CHECK1-NEXT: store float 0x47EFFFFFE0000000, float* [[T_VAR17]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -807,25 +807,25 @@ int main() { // CHECK1-NEXT: [[TMP34:%.*]] = load float, float* [[T_VAR3]], align 4 // CHECK1-NEXT: [[ADD12:%.*]] = fadd float [[TMP33]], [[TMP34]] // CHECK1-NEXT: store float [[ADD12]], float* [[TMP0]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* // CHECK1-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK1-NEXT: [[CALL13:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP2]]) +// CHECK1-NEXT: [[CALL13:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK1-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL13]], 0.000000e+00 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK1: land.rhs: -// CHECK1-NEXT: [[CALL14:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[VAR16]]) +// CHECK1-NEXT: [[CALL14:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR16]]) // CHECK1-NEXT: [[TOBOOL15:%.*]] = fcmp une float [[CALL14]], 0.000000e+00 // CHECK1-NEXT: br label [[LAND_END]] // CHECK1: land.end: // CHECK1-NEXT: [[TMP37:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL15]], [[LAND_RHS]] ] // CHECK1-NEXT: [[CONV16:%.*]] = uitofp i1 [[TMP37]] to float -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP]], float noundef [[CONV16]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV16]]) // CHECK1-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[TMP2]] to i8* // CHECK1-NEXT: [[TMP39:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP38]], i8* align 4 [[TMP39]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP40:%.*]] = load float, float* [[TMP3]], align 4 // CHECK1-NEXT: [[TMP41:%.*]] = load float, float* [[T_VAR17]], align 4 // CHECK1-NEXT: [[CMP17:%.*]] = fcmp olt float [[TMP40]], [[TMP41]] @@ -863,27 +863,27 @@ int main() { // CHECK1-NEXT: br i1 [[TMP55]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK1: atomic_exit: // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL24:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK1-NEXT: [[CALL24:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: [[TMP56:%.*]] = bitcast %struct.S* [[TMP7]] to i8* // CHECK1-NEXT: [[TMP57:%.*]] = bitcast %struct.S* [[CALL24]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP56]], i8* align 4 [[TMP57]], i64 4, i1 false) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL26:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP2]]) +// CHECK1-NEXT: [[CALL26:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK1-NEXT: [[TOBOOL27:%.*]] = fcmp une float [[CALL26]], 0.000000e+00 // CHECK1-NEXT: br i1 [[TOBOOL27]], label [[LAND_RHS28:%.*]], label [[LAND_END31:%.*]] // CHECK1: land.rhs28: -// CHECK1-NEXT: [[CALL29:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[VAR16]]) +// CHECK1-NEXT: [[CALL29:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR16]]) // CHECK1-NEXT: [[TOBOOL30:%.*]] = fcmp une float [[CALL29]], 0.000000e+00 // CHECK1-NEXT: br label [[LAND_END31]] // CHECK1: land.end31: // CHECK1-NEXT: [[TMP58:%.*]] = phi i1 [ false, [[ATOMIC_EXIT]] ], [ [[TOBOOL30]], [[LAND_RHS28]] ] // CHECK1-NEXT: [[CONV32:%.*]] = uitofp i1 [[TMP58]] to float -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP25]], float noundef [[CONV32]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP25]], float [[CONV32]]) // CHECK1-NEXT: [[TMP59:%.*]] = bitcast %struct.S* [[TMP2]] to i8* // CHECK1-NEXT: [[TMP60:%.*]] = bitcast %struct.S* [[REF_TMP25]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP59]], i8* align 4 [[TMP60]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP25]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP25]]) #[[ATTR5]] // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[TMP61:%.*]] = load float, float* [[T_VAR17]], align 4 // CHECK1-NEXT: [[TMP62:%.*]] = bitcast float* [[TMP3]] to i32* @@ -917,14 +917,14 @@ int main() { // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR16]]) #[[ATTR5]] -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR16]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP9]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -963,25 +963,25 @@ int main() { // CHECK1-NEXT: [[TMP31:%.*]] = load float, float* [[TMP8]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP30]], [[TMP31]] // CHECK1-NEXT: store float [[ADD]], float* [[TMP11]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP17]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP14]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP14]]) // CHECK1-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP17]] to i8* // CHECK1-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK1-NEXT: [[CALL2:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP23]]) +// CHECK1-NEXT: [[CALL2:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP23]]) // CHECK1-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL2]], 0.000000e+00 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK1: land.rhs: -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP20]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK1-NEXT: [[TOBOOL4:%.*]] = fcmp une float [[CALL3]], 0.000000e+00 // CHECK1-NEXT: br label [[LAND_END]] // CHECK1: land.end: // CHECK1-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] // CHECK1-NEXT: [[CONV:%.*]] = uitofp i1 [[TMP34]] to float -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP]], float noundef [[CONV]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV]]) // CHECK1-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP23]] to i8* // CHECK1-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP37:%.*]] = load float, float* [[TMP29]], align 4 // CHECK1-NEXT: [[TMP38:%.*]] = load float, float* [[TMP26]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP37]], [[TMP38]] @@ -999,7 +999,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEanERKS0_ -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 @@ -1010,7 +1010,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1019,17 +1019,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [10 x [4 x %struct.S]]* noundef nonnull align 4 dereferenceable(160) [[ARRS:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [10 x [4 x %struct.S]]* nonnull align 4 dereferenceable(160) [[ARRS:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1123,7 +1123,7 @@ int main() { // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY16]], label [[OMP_ARRAYINIT_DONE21:%.*]], label [[OMP_ARRAYINIT_BODY17:%.*]] // CHECK1: omp.arrayinit.body17: // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST18:%.*]] = phi %struct.S* [ [[VLA15]], [[OMP_ARRAYINIT_DONE]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT19:%.*]], [[OMP_ARRAYINIT_BODY17]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST18]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST18]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT19]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST18]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE20:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT19]], [[TMP30]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE20]], label [[OMP_ARRAYINIT_DONE21]], label [[OMP_ARRAYINIT_BODY17]] @@ -1228,7 +1228,7 @@ int main() { // CHECK1: omp.arraycpy.body32: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST33:%.*]] = phi %struct.S* [ [[VLA15]], [[OMP_ARRAYCPY_DONE30]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT36:%.*]], [[OMP_ARRAYCPY_BODY32]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST34:%.*]] = phi %struct.S* [ [[ARRAYIDX9]], [[OMP_ARRAYCPY_DONE30]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT35:%.*]], [[OMP_ARRAYCPY_BODY32]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST34]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST33]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST34]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST33]]) // CHECK1-NEXT: [[TMP68:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST34]] to i8* // CHECK1-NEXT: [[TMP69:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP68]], i8* align 4 [[TMP69]], i64 4, i1 false) @@ -1262,7 +1262,7 @@ int main() { // CHECK1-NEXT: [[TMP74:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP75:%.*]] = load i32, i32* [[TMP74]], align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP75]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL51:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST50]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST49]]) +// CHECK1-NEXT: [[CALL51:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST50]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST49]]) // CHECK1-NEXT: [[TMP76:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST50]] to i8* // CHECK1-NEXT: [[TMP77:%.*]] = bitcast %struct.S* [[CALL51]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP76]], i8* align 4 [[TMP77]], i64 4, i1 false) @@ -1280,7 +1280,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP78]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[VLA15]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE56]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done56: @@ -1290,7 +1290,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1339,7 +1339,7 @@ int main() { // CHECK1: omp.arraycpy.body4: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST5:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_ARRAYCPY_DONE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT8:%.*]], [[OMP_ARRAYCPY_BODY4]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST6:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_ARRAYCPY_DONE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT7:%.*]], [[OMP_ARRAYCPY_BODY4]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST6]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST5]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST6]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST5]]) // CHECK1-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST6]] to i8* // CHECK1-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) @@ -1352,7 +1352,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]], [10 x [4 x %struct.S]]* noundef nonnull align 4 dereferenceable(160) [[ARRS:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARR:%.*]], [10 x [4 x %struct.S]]* nonnull align 4 dereferenceable(160) [[ARRS:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1408,7 +1408,7 @@ int main() { // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY5]], label [[OMP_ARRAYINIT_DONE10:%.*]], label [[OMP_ARRAYINIT_BODY6:%.*]] // CHECK1: omp.arrayinit.body6: // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST7:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[OMP_ARRAYINIT_DONE]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT8:%.*]], [[OMP_ARRAYINIT_BODY6]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST7]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST7]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT8]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST7]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE9:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT8]], [[TMP9]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYINIT_DONE10]], label [[OMP_ARRAYINIT_BODY6]] @@ -1505,7 +1505,7 @@ int main() { // CHECK1: omp.arraycpy.body20: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST21:%.*]] = phi %struct.S* [ [[RHS_BEGIN]], [[OMP_ARRAYCPY_DONE18]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT24:%.*]], [[OMP_ARRAYCPY_BODY20]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST22:%.*]] = phi %struct.S* [ [[LHS_BEGIN]], [[OMP_ARRAYCPY_DONE18]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT23:%.*]], [[OMP_ARRAYCPY_BODY20]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST22]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST21]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST22]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST21]]) // CHECK1-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST22]] to i8* // CHECK1-NEXT: [[TMP39:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP38]], i8* align 4 [[TMP39]], i64 4, i1 false) @@ -1539,7 +1539,7 @@ int main() { // CHECK1-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP45]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL39:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST38]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST37]]) +// CHECK1-NEXT: [[CALL39:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST38]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST37]]) // CHECK1-NEXT: [[TMP46:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST38]] to i8* // CHECK1-NEXT: [[TMP47:%.*]] = bitcast %struct.S* [[CALL39]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 4, i1 false) @@ -1558,7 +1558,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP48]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN44]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE45:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done45: @@ -1571,7 +1571,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.4 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1617,7 +1617,7 @@ int main() { // CHECK1: omp.arraycpy.body4: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST5:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_ARRAYCPY_DONE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT8:%.*]], [[OMP_ARRAYCPY_BODY4]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST6:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_ARRAYCPY_DONE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT7:%.*]], [[OMP_ARRAYCPY_BODY4]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST6]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST5]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST6]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST5]]) // CHECK1-NEXT: [[TMP25:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST6]] to i8* // CHECK1-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) @@ -1630,7 +1630,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1784,7 +1784,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1819,7 +1819,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S*** noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S*** nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1867,7 +1867,7 @@ int main() { // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -1945,7 +1945,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[VLA]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST8:%.*]] = phi %struct.S* [ [[ARRAYIDX1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT9:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST8]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST8]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP40:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST8]] to i8* // CHECK1-NEXT: [[TMP41:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i64 4, i1 false) @@ -1966,7 +1966,7 @@ int main() { // CHECK1-NEXT: [[TMP43:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[TMP43]], align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP44]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL16:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST15]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST14]]) +// CHECK1-NEXT: [[CALL16:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST15]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST14]]) // CHECK1-NEXT: [[TMP45:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST15]] to i8* // CHECK1-NEXT: [[TMP46:%.*]] = bitcast %struct.S* [[CALL16]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP45]], i8* align 4 [[TMP46]], i64 4, i1 false) @@ -1985,7 +1985,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP47]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[VLA]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done21: @@ -1998,7 +1998,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.8 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2023,7 +2023,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP16:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK1-NEXT: [[TMP17:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i64 4, i1 false) @@ -2036,7 +2036,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S*** noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S*** nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2074,7 +2074,7 @@ int main() { // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -2151,7 +2151,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST9:%.*]] = phi %struct.S* [ [[ARRAYIDX1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT10:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST9]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST9]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST9]] to i8* // CHECK1-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) @@ -2172,7 +2172,7 @@ int main() { // CHECK1-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP36]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL17:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST16]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST15]]) +// CHECK1-NEXT: [[CALL17:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST16]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST15]]) // CHECK1-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST16]] to i8* // CHECK1-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[CALL17]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP37]], i8* align 4 [[TMP38]], i64 4, i1 false) @@ -2191,7 +2191,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN22]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE23:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done23: @@ -2202,7 +2202,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.10 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2224,7 +2224,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) @@ -2237,7 +2237,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S*** noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S*** nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2275,7 +2275,7 @@ int main() { // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -2352,7 +2352,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST9:%.*]] = phi %struct.S* [ [[ARRAYIDX1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT10:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST9]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST9]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST9]] to i8* // CHECK1-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) @@ -2373,7 +2373,7 @@ int main() { // CHECK1-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP36]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL17:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST16]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST15]]) +// CHECK1-NEXT: [[CALL17:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST16]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST15]]) // CHECK1-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST16]] to i8* // CHECK1-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[CALL17]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP37]], i8* align 4 [[TMP38]], i64 4, i1 false) @@ -2392,7 +2392,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN22]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE23:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done23: @@ -2403,7 +2403,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.12 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2425,7 +2425,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) @@ -2438,7 +2438,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S*** noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S*** nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2470,7 +2470,7 @@ int main() { // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds %struct.S*, %struct.S** [[TMP3]], i64 1 // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[ARRAYIDX2]], align 8 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP4]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR24]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR24]]) // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S**, %struct.S*** [[TMP0]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[TMP5]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint %struct.S* [[TMP6]] to i64 @@ -2531,7 +2531,7 @@ int main() { // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[ARRAYIDX1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR24]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR24]]) // CHECK1-NEXT: [[TMP25:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* // CHECK1-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) @@ -2539,7 +2539,7 @@ int main() { // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL9:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[ARRAYIDX1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR24]]) +// CHECK1-NEXT: [[CALL9:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR24]]) // CHECK1-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* // CHECK1-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[CALL9]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false) @@ -2547,13 +2547,13 @@ int main() { // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR24]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR24]]) #[[ATTR5]] // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP13]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.14 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2569,7 +2569,7 @@ int main() { // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to %struct.S* -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP11]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP8]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP11]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP8]]) // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[TMP11]] to i8* // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) @@ -2577,7 +2577,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [5 x %struct.S]* noundef nonnull align 4 dereferenceable(20) [[VVAR2:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [5 x %struct.S]* nonnull align 4 dereferenceable(20) [[VVAR2:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2607,7 +2607,7 @@ int main() { // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP1]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -2682,7 +2682,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST5:%.*]] = phi %struct.S* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT6:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST5]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST5]] to i8* // CHECK1-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) @@ -2703,7 +2703,7 @@ int main() { // CHECK1-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP32]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL13:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST12]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST11]]) +// CHECK1-NEXT: [[CALL13:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST12]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST11]]) // CHECK1-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST12]] to i8* // CHECK1-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[CALL13]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) @@ -2722,7 +2722,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN18]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done19: @@ -2733,7 +2733,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.16 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2755,7 +2755,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) @@ -2768,7 +2768,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2806,7 +2806,7 @@ int main() { // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -2883,7 +2883,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST8:%.*]] = phi %struct.S* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT9:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST8]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST8]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST8]] to i8* // CHECK1-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) @@ -2904,7 +2904,7 @@ int main() { // CHECK1-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP36]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL16:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST15]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST14]]) +// CHECK1-NEXT: [[CALL16:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST15]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST14]]) // CHECK1-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST15]] to i8* // CHECK1-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[CALL16]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP37]], i8* align 4 [[TMP38]], i64 4, i1 false) @@ -2923,7 +2923,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN21]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done22: @@ -2934,7 +2934,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.18 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2956,7 +2956,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) @@ -2969,7 +2969,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3007,7 +3007,7 @@ int main() { // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -3084,7 +3084,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST8:%.*]] = phi %struct.S* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT9:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST8]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST8]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST8]] to i8* // CHECK1-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) @@ -3105,7 +3105,7 @@ int main() { // CHECK1-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP36]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL16:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST15]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST14]]) +// CHECK1-NEXT: [[CALL16:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST15]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST14]]) // CHECK1-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST15]] to i8* // CHECK1-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[CALL16]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP37]], i8* align 4 [[TMP38]], i64 4, i1 false) @@ -3124,7 +3124,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN21]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done22: @@ -3135,7 +3135,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.20 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3157,7 +3157,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) @@ -3170,7 +3170,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3218,7 +3218,7 @@ int main() { // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP11]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -3296,7 +3296,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[VLA]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST7:%.*]] = phi %struct.S* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT8:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST7]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP40:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST7]] to i8* // CHECK1-NEXT: [[TMP41:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i64 4, i1 false) @@ -3317,7 +3317,7 @@ int main() { // CHECK1-NEXT: [[TMP43:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[TMP43]], align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP44]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL15:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST14]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST13]]) +// CHECK1-NEXT: [[CALL15:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST14]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST13]]) // CHECK1-NEXT: [[TMP45:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST14]] to i8* // CHECK1-NEXT: [[TMP46:%.*]] = bitcast %struct.S* [[CALL15]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP45]], i8* align 4 [[TMP46]], i64 4, i1 false) @@ -3336,7 +3336,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP47]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[VLA]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done20: @@ -3349,7 +3349,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.22 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3374,7 +3374,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP16:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK1-NEXT: [[TMP17:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i64 4, i1 false) @@ -3387,7 +3387,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3422,7 +3422,7 @@ int main() { // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -3491,7 +3491,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST7:%.*]] = phi %struct.S* [ [[LHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT8:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST7]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP22:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST7]] to i8* // CHECK1-NEXT: [[TMP23:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false) @@ -3512,7 +3512,7 @@ int main() { // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP26]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL15:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST14]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST13]]) +// CHECK1-NEXT: [[CALL15:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST14]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST13]]) // CHECK1-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST14]] to i8* // CHECK1-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[CALL15]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false) @@ -3531,7 +3531,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN20]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done21: @@ -3542,7 +3542,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.24 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3564,7 +3564,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) @@ -3589,22 +3589,22 @@ int main() { // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[ARR:%.*]] = alloca [42 x %struct.S.0], align 16 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiLi42EET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [42 x %struct.S.0], [42 x %struct.S.0]* [[ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 42 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] @@ -3622,28 +3622,28 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN1]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN3]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY4:%.*]] // CHECK1: arraydestroy.body4: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST5:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE2]] ], [ [[ARRAYDESTROY_ELEMENT6:%.*]], [[ARRAYDESTROY_BODY4]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT6]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST5]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT6]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT6]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE7:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT6]], [[ARRAY_BEGIN3]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE7]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY4]] // CHECK1: arraydestroy.done8: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP6]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3656,7 +3656,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3674,7 +3674,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3683,17 +3683,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3701,12 +3701,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3756,9 +3756,9 @@ int main() { // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, i32* [[T_VAR3]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR4]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[_TMP5]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR16]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR16]]) // CHECK1-NEXT: store i32 2147483647, i32* [[T_VAR17]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -3836,25 +3836,25 @@ int main() { // CHECK1-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] // CHECK1-NEXT: store i32 [[ADD12]], i32* [[TMP0]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* // CHECK1-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK1-NEXT: [[CALL13:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP2]]) +// CHECK1-NEXT: [[CALL13:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL13]], 0 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK1: land.rhs: -// CHECK1-NEXT: [[CALL14:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[VAR16]]) +// CHECK1-NEXT: [[CALL14:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR16]]) // CHECK1-NEXT: [[TOBOOL15:%.*]] = icmp ne i32 [[CALL14]], 0 // CHECK1-NEXT: br label [[LAND_END]] // CHECK1: land.end: // CHECK1-NEXT: [[TMP37:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL15]], [[LAND_RHS]] ] // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP37]] to i32 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[CONV]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) // CHECK1-NEXT: [[TMP38:%.*]] = bitcast %struct.S.0* [[TMP2]] to i8* // CHECK1-NEXT: [[TMP39:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP38]], i8* align 4 [[TMP39]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK1-NEXT: [[TMP41:%.*]] = load i32, i32* [[T_VAR17]], align 4 // CHECK1-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP40]], [[TMP41]] @@ -3874,39 +3874,39 @@ int main() { // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK1-NEXT: [[TMP45:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP44]] monotonic, align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL21:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK1-NEXT: [[CALL21:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: [[TMP46:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* // CHECK1-NEXT: [[TMP47:%.*]] = bitcast %struct.S.0* [[CALL21]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 4, i1 false) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL23:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP2]]) +// CHECK1-NEXT: [[CALL23:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK1-NEXT: [[TOBOOL24:%.*]] = icmp ne i32 [[CALL23]], 0 // CHECK1-NEXT: br i1 [[TOBOOL24]], label [[LAND_RHS25:%.*]], label [[LAND_END28:%.*]] // CHECK1: land.rhs25: -// CHECK1-NEXT: [[CALL26:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[VAR16]]) +// CHECK1-NEXT: [[CALL26:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR16]]) // CHECK1-NEXT: [[TOBOOL27:%.*]] = icmp ne i32 [[CALL26]], 0 // CHECK1-NEXT: br label [[LAND_END28]] // CHECK1: land.end28: // CHECK1-NEXT: [[TMP48:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE2]] ], [ [[TOBOOL27]], [[LAND_RHS25]] ] // CHECK1-NEXT: [[CONV29:%.*]] = zext i1 [[TMP48]] to i32 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP22]], i32 noundef [[CONV29]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP22]], i32 [[CONV29]]) // CHECK1-NEXT: [[TMP49:%.*]] = bitcast %struct.S.0* [[TMP2]] to i8* // CHECK1-NEXT: [[TMP50:%.*]] = bitcast %struct.S.0* [[REF_TMP22]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP22]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP22]]) #[[ATTR5]] // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[TMP51:%.*]] = load i32, i32* [[T_VAR17]], align 4 // CHECK1-NEXT: [[TMP52:%.*]] = atomicrmw min i32* [[TMP3]], i32 [[TMP51]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR16]]) #[[ATTR5]] -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR4]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR16]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.26 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3945,25 +3945,25 @@ int main() { // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP17]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP14]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP14]]) // CHECK1-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* // CHECK1-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK1-NEXT: [[CALL2:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP23]]) +// CHECK1-NEXT: [[CALL2:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP23]]) // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL2]], 0 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK1: land.rhs: -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP20]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK1-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[CALL3]], 0 // CHECK1-NEXT: br label [[LAND_END]] // CHECK1: land.end: // CHECK1-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP34]] to i32 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[CONV]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) // CHECK1-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* // CHECK1-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[TMP26]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] @@ -3981,7 +3981,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEanERKS0_ -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -3992,7 +3992,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEcviEv -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4001,17 +4001,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4157,7 +4157,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.28 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4188,7 +4188,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [42 x %struct.S.0]* noundef nonnull align 4 dereferenceable(168) [[ARR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [42 x %struct.S.0]* nonnull align 4 dereferenceable(168) [[ARR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4237,7 +4237,7 @@ int main() { // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -4324,14 +4324,14 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT13:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST10]]) -// CHECK1-NEXT: [[CALL11:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST10]]) +// CHECK1-NEXT: [[CALL11:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[CALL]], [[CALL11]] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[ADD12]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[ADD12]]) // CHECK1-NEXT: [[TMP39:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST10]] to i8* // CHECK1-NEXT: [[TMP40:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP39]], i8* align 4 [[TMP40]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT13]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE14:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT13]], [[TMP38]] @@ -4349,14 +4349,14 @@ int main() { // CHECK1-NEXT: [[TMP42:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP43:%.*]] = load i32, i32* [[TMP42]], align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP43]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL21:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST19]]) -// CHECK1-NEXT: [[CALL22:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST18]]) +// CHECK1-NEXT: [[CALL21:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST19]]) +// CHECK1-NEXT: [[CALL22:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST18]]) // CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[CALL21]], [[CALL22]] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP20]], i32 noundef [[ADD23]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP20]], i32 [[ADD23]]) // CHECK1-NEXT: [[TMP44:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST19]] to i8* // CHECK1-NEXT: [[TMP45:%.*]] = bitcast %struct.S.0* [[REF_TMP20]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP44]], i8* align 4 [[TMP45]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP20]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP20]]) #[[ATTR5]] // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP43]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT24]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST19]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT25]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST18]], i32 1 @@ -4372,7 +4372,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP46]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN28]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE29:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done29: @@ -4383,7 +4383,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.30 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4406,14 +4406,14 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) -// CHECK1-NEXT: [[CALL2:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK1-NEXT: [[CALL2:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL2]] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[ADD]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[ADD]]) // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] @@ -4423,7 +4423,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4436,7 +4436,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4454,7 +4454,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4480,38 +4480,38 @@ int main() { // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_ELEMENT]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT1]], float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT1]], float 3.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_ELEMENT1]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT2]], float noundef 4.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT2]], float 4.000000e+00) // CHECK2-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], [10 x [4 x %struct.S]]* [[ARRS]], i32 0, i32 0, i32 0 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 40 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef %struct.S** @_Z3foov() +// CHECK2-NEXT: [[CALL:%.*]] = call %struct.S** @_Z3foov() // CHECK2-NEXT: store %struct.S** [[CALL]], %struct.S*** [[VAR2]], align 8 // CHECK2-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [5 x %struct.S], [5 x %struct.S]* [[VVAR2]], i32 0, i32 0 // CHECK2-NEXT: [[ARRAYCTOR_END4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 5 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP5:%.*]] // CHECK2: arrayctor.loop5: // CHECK2-NEXT: [[ARRAYCTOR_CUR6:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYCTOR_NEXT7:%.*]], [[ARRAYCTOR_LOOP5]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR6]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR6]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT7]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR6]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE8:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT7]], [[ARRAYCTOR_END4]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE8]], label [[ARRAYCTOR_CONT9:%.*]], label [[ARRAYCTOR_LOOP5]] @@ -4543,7 +4543,7 @@ int main() { // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [4 x %struct.S]*)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [4 x %struct.S]* [[TMP8]]) // CHECK2-NEXT: [[TMP9:%.*]] = load [4 x %struct.S]*, [4 x %struct.S]** [[VAR3]], align 8 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [4 x %struct.S]*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), [4 x %struct.S]* [[TMP9]]) -// CHECK2-NEXT: [[CALL10:%.*]] = call noundef i32 @_Z5tmainIiLi42EET_v() +// CHECK2-NEXT: [[CALL10:%.*]] = call i32 @_Z5tmainIiLi42EET_v() // CHECK2-NEXT: store i32 [[CALL10]], i32* [[RETVAL]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) @@ -4553,7 +4553,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ARRAYCTOR_CONT9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5:[0-9]+]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done12: @@ -4563,38 +4563,38 @@ int main() { // CHECK2: arraydestroy.body14: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST15:%.*]] = phi %struct.S* [ [[TMP12]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT16:%.*]], [[ARRAYDESTROY_BODY14]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT16]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST15]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE17:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT16]], [[ARRAY_BEGIN13]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE17]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY14]] // CHECK2: arraydestroy.done18: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR1]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAY_BEGIN19:%.*]] = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN19]], i64 4 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY20:%.*]] // CHECK2: arraydestroy.body20: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST21:%.*]] = phi %struct.S* [ [[TMP13]], [[ARRAYDESTROY_DONE18]] ], [ [[ARRAYDESTROY_ELEMENT22:%.*]], [[ARRAYDESTROY_BODY20]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT22]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST21]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT22]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT22]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE23:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT22]], [[ARRAY_BEGIN19]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE23]], label [[ARRAYDESTROY_DONE24:%.*]], label [[ARRAYDESTROY_BODY20]] // CHECK2: arraydestroy.done24: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP14]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4602,12 +4602,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [4 x %struct.S]* noundef nonnull align 4 dereferenceable(16) [[S_ARR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [4 x %struct.S]* nonnull align 4 dereferenceable(16) [[S_ARR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4661,9 +4661,9 @@ int main() { // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: store float 0.000000e+00, float* [[T_VAR3]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR4]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK2-NEXT: store %struct.S* [[VAR4]], %struct.S** [[_TMP5]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR16]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR16]]) // CHECK2-NEXT: store float 0x47EFFFFFE0000000, float* [[T_VAR17]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -4742,25 +4742,25 @@ int main() { // CHECK2-NEXT: [[TMP34:%.*]] = load float, float* [[T_VAR3]], align 4 // CHECK2-NEXT: [[ADD12:%.*]] = fadd float [[TMP33]], [[TMP34]] // CHECK2-NEXT: store float [[ADD12]], float* [[TMP0]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK2-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* // CHECK2-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK2-NEXT: [[CALL13:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP2]]) +// CHECK2-NEXT: [[CALL13:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK2-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL13]], 0.000000e+00 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK2: land.rhs: -// CHECK2-NEXT: [[CALL14:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[VAR16]]) +// CHECK2-NEXT: [[CALL14:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR16]]) // CHECK2-NEXT: [[TOBOOL15:%.*]] = fcmp une float [[CALL14]], 0.000000e+00 // CHECK2-NEXT: br label [[LAND_END]] // CHECK2: land.end: // CHECK2-NEXT: [[TMP37:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL15]], [[LAND_RHS]] ] // CHECK2-NEXT: [[CONV16:%.*]] = uitofp i1 [[TMP37]] to float -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP]], float noundef [[CONV16]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV16]]) // CHECK2-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[TMP2]] to i8* // CHECK2-NEXT: [[TMP39:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP38]], i8* align 4 [[TMP39]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP40:%.*]] = load float, float* [[TMP3]], align 4 // CHECK2-NEXT: [[TMP41:%.*]] = load float, float* [[T_VAR17]], align 4 // CHECK2-NEXT: [[CMP17:%.*]] = fcmp olt float [[TMP40]], [[TMP41]] @@ -4798,27 +4798,27 @@ int main() { // CHECK2-NEXT: br i1 [[TMP55]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK2: atomic_exit: // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL24:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK2-NEXT: [[CALL24:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK2-NEXT: [[TMP56:%.*]] = bitcast %struct.S* [[TMP7]] to i8* // CHECK2-NEXT: [[TMP57:%.*]] = bitcast %struct.S* [[CALL24]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP56]], i8* align 4 [[TMP57]], i64 4, i1 false) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL26:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP2]]) +// CHECK2-NEXT: [[CALL26:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK2-NEXT: [[TOBOOL27:%.*]] = fcmp une float [[CALL26]], 0.000000e+00 // CHECK2-NEXT: br i1 [[TOBOOL27]], label [[LAND_RHS28:%.*]], label [[LAND_END31:%.*]] // CHECK2: land.rhs28: -// CHECK2-NEXT: [[CALL29:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[VAR16]]) +// CHECK2-NEXT: [[CALL29:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR16]]) // CHECK2-NEXT: [[TOBOOL30:%.*]] = fcmp une float [[CALL29]], 0.000000e+00 // CHECK2-NEXT: br label [[LAND_END31]] // CHECK2: land.end31: // CHECK2-NEXT: [[TMP58:%.*]] = phi i1 [ false, [[ATOMIC_EXIT]] ], [ [[TOBOOL30]], [[LAND_RHS28]] ] // CHECK2-NEXT: [[CONV32:%.*]] = uitofp i1 [[TMP58]] to float -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP25]], float noundef [[CONV32]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP25]], float [[CONV32]]) // CHECK2-NEXT: [[TMP59:%.*]] = bitcast %struct.S* [[TMP2]] to i8* // CHECK2-NEXT: [[TMP60:%.*]] = bitcast %struct.S* [[REF_TMP25]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP59]], i8* align 4 [[TMP60]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP25]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP25]]) #[[ATTR5]] // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[TMP61:%.*]] = load float, float* [[T_VAR17]], align 4 // CHECK2-NEXT: [[TMP62:%.*]] = bitcast float* [[TMP3]] to i32* @@ -4852,14 +4852,14 @@ int main() { // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK2: .omp.reduction.default: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR16]]) #[[ATTR5]] -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR16]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP9]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4898,25 +4898,25 @@ int main() { // CHECK2-NEXT: [[TMP31:%.*]] = load float, float* [[TMP8]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP30]], [[TMP31]] // CHECK2-NEXT: store float [[ADD]], float* [[TMP11]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP17]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP14]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP14]]) // CHECK2-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP17]] to i8* // CHECK2-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK2-NEXT: [[CALL2:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP23]]) +// CHECK2-NEXT: [[CALL2:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP23]]) // CHECK2-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL2]], 0.000000e+00 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK2: land.rhs: -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP20]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK2-NEXT: [[TOBOOL4:%.*]] = fcmp une float [[CALL3]], 0.000000e+00 // CHECK2-NEXT: br label [[LAND_END]] // CHECK2: land.end: // CHECK2-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] // CHECK2-NEXT: [[CONV:%.*]] = uitofp i1 [[TMP34]] to float -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP]], float noundef [[CONV]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV]]) // CHECK2-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP23]] to i8* // CHECK2-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP37:%.*]] = load float, float* [[TMP29]], align 4 // CHECK2-NEXT: [[TMP38:%.*]] = load float, float* [[TMP26]], align 4 // CHECK2-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP37]], [[TMP38]] @@ -4934,7 +4934,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEanERKS0_ -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR7:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 @@ -4945,7 +4945,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4954,17 +4954,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [10 x [4 x %struct.S]]* noundef nonnull align 4 dereferenceable(160) [[ARRS:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [10 x [4 x %struct.S]]* nonnull align 4 dereferenceable(160) [[ARRS:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5058,7 +5058,7 @@ int main() { // CHECK2-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY16]], label [[OMP_ARRAYINIT_DONE21:%.*]], label [[OMP_ARRAYINIT_BODY17:%.*]] // CHECK2: omp.arrayinit.body17: // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST18:%.*]] = phi %struct.S* [ [[VLA15]], [[OMP_ARRAYINIT_DONE]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT19:%.*]], [[OMP_ARRAYINIT_BODY17]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST18]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST18]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT19]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST18]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE20:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT19]], [[TMP30]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE20]], label [[OMP_ARRAYINIT_DONE21]], label [[OMP_ARRAYINIT_BODY17]] @@ -5163,7 +5163,7 @@ int main() { // CHECK2: omp.arraycpy.body32: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST33:%.*]] = phi %struct.S* [ [[VLA15]], [[OMP_ARRAYCPY_DONE30]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT36:%.*]], [[OMP_ARRAYCPY_BODY32]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST34:%.*]] = phi %struct.S* [ [[ARRAYIDX9]], [[OMP_ARRAYCPY_DONE30]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT35:%.*]], [[OMP_ARRAYCPY_BODY32]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST34]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST33]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST34]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST33]]) // CHECK2-NEXT: [[TMP68:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST34]] to i8* // CHECK2-NEXT: [[TMP69:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP68]], i8* align 4 [[TMP69]], i64 4, i1 false) @@ -5197,7 +5197,7 @@ int main() { // CHECK2-NEXT: [[TMP74:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP75:%.*]] = load i32, i32* [[TMP74]], align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP75]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL51:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST50]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST49]]) +// CHECK2-NEXT: [[CALL51:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST50]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST49]]) // CHECK2-NEXT: [[TMP76:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST50]] to i8* // CHECK2-NEXT: [[TMP77:%.*]] = bitcast %struct.S* [[CALL51]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP76]], i8* align 4 [[TMP77]], i64 4, i1 false) @@ -5215,7 +5215,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP78]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[VLA15]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE56]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done56: @@ -5225,7 +5225,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -5274,7 +5274,7 @@ int main() { // CHECK2: omp.arraycpy.body4: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST5:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_ARRAYCPY_DONE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT8:%.*]], [[OMP_ARRAYCPY_BODY4]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST6:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_ARRAYCPY_DONE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT7:%.*]], [[OMP_ARRAYCPY_BODY4]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST6]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST5]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST6]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST5]]) // CHECK2-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST6]] to i8* // CHECK2-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) @@ -5287,7 +5287,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]], [10 x [4 x %struct.S]]* noundef nonnull align 4 dereferenceable(160) [[ARRS:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARR:%.*]], [10 x [4 x %struct.S]]* nonnull align 4 dereferenceable(160) [[ARRS:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5343,7 +5343,7 @@ int main() { // CHECK2-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY5]], label [[OMP_ARRAYINIT_DONE10:%.*]], label [[OMP_ARRAYINIT_BODY6:%.*]] // CHECK2: omp.arrayinit.body6: // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST7:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[OMP_ARRAYINIT_DONE]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT8:%.*]], [[OMP_ARRAYINIT_BODY6]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST7]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST7]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT8]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST7]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE9:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT8]], [[TMP9]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYINIT_DONE10]], label [[OMP_ARRAYINIT_BODY6]] @@ -5440,7 +5440,7 @@ int main() { // CHECK2: omp.arraycpy.body20: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST21:%.*]] = phi %struct.S* [ [[RHS_BEGIN]], [[OMP_ARRAYCPY_DONE18]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT24:%.*]], [[OMP_ARRAYCPY_BODY20]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST22:%.*]] = phi %struct.S* [ [[LHS_BEGIN]], [[OMP_ARRAYCPY_DONE18]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT23:%.*]], [[OMP_ARRAYCPY_BODY20]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST22]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST21]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST22]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST21]]) // CHECK2-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST22]] to i8* // CHECK2-NEXT: [[TMP39:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP38]], i8* align 4 [[TMP39]], i64 4, i1 false) @@ -5474,7 +5474,7 @@ int main() { // CHECK2-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP45]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL39:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST38]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST37]]) +// CHECK2-NEXT: [[CALL39:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST38]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST37]]) // CHECK2-NEXT: [[TMP46:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST38]] to i8* // CHECK2-NEXT: [[TMP47:%.*]] = bitcast %struct.S* [[CALL39]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 4, i1 false) @@ -5493,7 +5493,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP48]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN44]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE45:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done45: @@ -5506,7 +5506,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.4 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -5552,7 +5552,7 @@ int main() { // CHECK2: omp.arraycpy.body4: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST5:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_ARRAYCPY_DONE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT8:%.*]], [[OMP_ARRAYCPY_BODY4]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST6:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_ARRAYCPY_DONE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT7:%.*]], [[OMP_ARRAYCPY_BODY4]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST6]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST5]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST6]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST5]]) // CHECK2-NEXT: [[TMP25:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST6]] to i8* // CHECK2-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) @@ -5565,7 +5565,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5719,7 +5719,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -5754,7 +5754,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S*** noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S*** nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5802,7 +5802,7 @@ int main() { // CHECK2-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK2: omp.arrayinit.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -5880,7 +5880,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[VLA]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST8:%.*]] = phi %struct.S* [ [[ARRAYIDX1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT9:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST8]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST8]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP40:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST8]] to i8* // CHECK2-NEXT: [[TMP41:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i64 4, i1 false) @@ -5901,7 +5901,7 @@ int main() { // CHECK2-NEXT: [[TMP43:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP44:%.*]] = load i32, i32* [[TMP43]], align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP44]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL16:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST15]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST14]]) +// CHECK2-NEXT: [[CALL16:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST15]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST14]]) // CHECK2-NEXT: [[TMP45:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST15]] to i8* // CHECK2-NEXT: [[TMP46:%.*]] = bitcast %struct.S* [[CALL16]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP45]], i8* align 4 [[TMP46]], i64 4, i1 false) @@ -5920,7 +5920,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP47]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[VLA]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done21: @@ -5933,7 +5933,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.8 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -5958,7 +5958,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP16:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK2-NEXT: [[TMP17:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i64 4, i1 false) @@ -5971,7 +5971,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S*** noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S*** nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6009,7 +6009,7 @@ int main() { // CHECK2-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK2: omp.arrayinit.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -6086,7 +6086,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST9:%.*]] = phi %struct.S* [ [[ARRAYIDX1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT10:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST9]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST9]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST9]] to i8* // CHECK2-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) @@ -6107,7 +6107,7 @@ int main() { // CHECK2-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP36]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL17:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST16]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST15]]) +// CHECK2-NEXT: [[CALL17:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST16]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST15]]) // CHECK2-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST16]] to i8* // CHECK2-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[CALL17]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP37]], i8* align 4 [[TMP38]], i64 4, i1 false) @@ -6126,7 +6126,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN22]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE23:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done23: @@ -6137,7 +6137,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.10 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -6159,7 +6159,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) @@ -6172,7 +6172,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S*** noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S*** nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6210,7 +6210,7 @@ int main() { // CHECK2-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK2: omp.arrayinit.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -6287,7 +6287,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST9:%.*]] = phi %struct.S* [ [[ARRAYIDX1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT10:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST9]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST9]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST9]] to i8* // CHECK2-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) @@ -6308,7 +6308,7 @@ int main() { // CHECK2-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP36]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL17:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST16]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST15]]) +// CHECK2-NEXT: [[CALL17:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST16]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST15]]) // CHECK2-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST16]] to i8* // CHECK2-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[CALL17]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP37]], i8* align 4 [[TMP38]], i64 4, i1 false) @@ -6327,7 +6327,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN22]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE23:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done23: @@ -6338,7 +6338,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.12 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -6360,7 +6360,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) @@ -6373,7 +6373,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S*** noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S*** nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6405,7 +6405,7 @@ int main() { // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds %struct.S*, %struct.S** [[TMP3]], i64 1 // CHECK2-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[ARRAYIDX2]], align 8 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP4]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR24]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR24]]) // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S**, %struct.S*** [[TMP0]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[TMP5]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = ptrtoint %struct.S* [[TMP6]] to i64 @@ -6466,7 +6466,7 @@ int main() { // CHECK2-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK2-NEXT: ] // CHECK2: .omp.reduction.case1: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[ARRAYIDX1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR24]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR24]]) // CHECK2-NEXT: [[TMP25:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* // CHECK2-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) @@ -6474,7 +6474,7 @@ int main() { // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK2: .omp.reduction.case2: // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL9:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[ARRAYIDX1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR24]]) +// CHECK2-NEXT: [[CALL9:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR24]]) // CHECK2-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* // CHECK2-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[CALL9]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false) @@ -6482,13 +6482,13 @@ int main() { // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK2: .omp.reduction.default: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR24]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR24]]) #[[ATTR5]] // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP13]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.14 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -6504,7 +6504,7 @@ int main() { // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 // CHECK2-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to %struct.S* -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP11]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP8]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP11]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP8]]) // CHECK2-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[TMP11]] to i8* // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) @@ -6512,7 +6512,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [5 x %struct.S]* noundef nonnull align 4 dereferenceable(20) [[VVAR2:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [5 x %struct.S]* nonnull align 4 dereferenceable(20) [[VVAR2:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6542,7 +6542,7 @@ int main() { // CHECK2-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK2: omp.arrayinit.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP1]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -6617,7 +6617,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST5:%.*]] = phi %struct.S* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT6:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST5]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST5]] to i8* // CHECK2-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP28]], i8* align 4 [[TMP29]], i64 4, i1 false) @@ -6638,7 +6638,7 @@ int main() { // CHECK2-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP32]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL13:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST12]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST11]]) +// CHECK2-NEXT: [[CALL13:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST12]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST11]]) // CHECK2-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST12]] to i8* // CHECK2-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[CALL13]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) @@ -6657,7 +6657,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN18]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done19: @@ -6668,7 +6668,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.16 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -6690,7 +6690,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) @@ -6703,7 +6703,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6741,7 +6741,7 @@ int main() { // CHECK2-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK2: omp.arrayinit.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -6818,7 +6818,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST8:%.*]] = phi %struct.S* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT9:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST8]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST8]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST8]] to i8* // CHECK2-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) @@ -6839,7 +6839,7 @@ int main() { // CHECK2-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP36]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL16:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST15]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST14]]) +// CHECK2-NEXT: [[CALL16:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST15]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST14]]) // CHECK2-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST15]] to i8* // CHECK2-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[CALL16]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP37]], i8* align 4 [[TMP38]], i64 4, i1 false) @@ -6858,7 +6858,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN21]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done22: @@ -6869,7 +6869,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.18 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -6891,7 +6891,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) @@ -6904,7 +6904,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6942,7 +6942,7 @@ int main() { // CHECK2-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK2: omp.arrayinit.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -7019,7 +7019,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST8:%.*]] = phi %struct.S* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT9:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST8]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST8]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST8]] to i8* // CHECK2-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) @@ -7040,7 +7040,7 @@ int main() { // CHECK2-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP35]], align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP36]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL16:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST15]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST14]]) +// CHECK2-NEXT: [[CALL16:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST15]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST14]]) // CHECK2-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST15]] to i8* // CHECK2-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[CALL16]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP37]], i8* align 4 [[TMP38]], i64 4, i1 false) @@ -7059,7 +7059,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN21]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done22: @@ -7070,7 +7070,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.20 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -7092,7 +7092,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) @@ -7105,7 +7105,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7153,7 +7153,7 @@ int main() { // CHECK2-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK2: omp.arrayinit.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP11]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -7231,7 +7231,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[VLA]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST7:%.*]] = phi %struct.S* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT8:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST7]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP40:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST7]] to i8* // CHECK2-NEXT: [[TMP41:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i64 4, i1 false) @@ -7252,7 +7252,7 @@ int main() { // CHECK2-NEXT: [[TMP43:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP44:%.*]] = load i32, i32* [[TMP43]], align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP44]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL15:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST14]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST13]]) +// CHECK2-NEXT: [[CALL15:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST14]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST13]]) // CHECK2-NEXT: [[TMP45:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST14]] to i8* // CHECK2-NEXT: [[TMP46:%.*]] = bitcast %struct.S* [[CALL15]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP45]], i8* align 4 [[TMP46]], i64 4, i1 false) @@ -7271,7 +7271,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP47]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[VLA]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done20: @@ -7284,7 +7284,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.22 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -7309,7 +7309,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP16:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK2-NEXT: [[TMP17:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i64 4, i1 false) @@ -7322,7 +7322,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [4 x %struct.S]* nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7357,7 +7357,7 @@ int main() { // CHECK2-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK2: omp.arrayinit.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -7426,7 +7426,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST7:%.*]] = phi %struct.S* [ [[LHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT8:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST7]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP22:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST7]] to i8* // CHECK2-NEXT: [[TMP23:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false) @@ -7447,7 +7447,7 @@ int main() { // CHECK2-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP26]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL15:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST14]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST13]]) +// CHECK2-NEXT: [[CALL15:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST14]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST13]]) // CHECK2-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST14]] to i8* // CHECK2-NEXT: [[TMP28:%.*]] = bitcast %struct.S* [[CALL15]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false) @@ -7466,7 +7466,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN20]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done21: @@ -7477,7 +7477,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.24 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -7499,7 +7499,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) @@ -7524,22 +7524,22 @@ int main() { // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK2-NEXT: [[ARR:%.*]] = alloca [42 x %struct.S.0], align 16 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiLi42EET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [42 x %struct.S.0], [42 x %struct.S.0]* [[ARR]], i32 0, i32 0 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 42 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] @@ -7557,28 +7557,28 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN1]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR1]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN3]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY4:%.*]] // CHECK2: arraydestroy.body4: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST5:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ARRAYDESTROY_DONE2]] ], [ [[ARRAYDESTROY_ELEMENT6:%.*]], [[ARRAYDESTROY_BODY4]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT6]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST5]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT6]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT6]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE7:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT6]], [[ARRAY_BEGIN3]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE7]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY4]] // CHECK2: arraydestroy.done8: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP6]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -7591,7 +7591,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -7609,7 +7609,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -7618,17 +7618,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7636,12 +7636,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7691,9 +7691,9 @@ int main() { // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: store i32 0, i32* [[T_VAR3]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR4]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK2-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[_TMP5]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR16]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR16]]) // CHECK2-NEXT: store i32 2147483647, i32* [[T_VAR17]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -7771,25 +7771,25 @@ int main() { // CHECK2-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] // CHECK2-NEXT: store i32 [[ADD12]], i32* [[TMP0]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK2-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* // CHECK2-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK2-NEXT: [[CALL13:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP2]]) +// CHECK2-NEXT: [[CALL13:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL13]], 0 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK2: land.rhs: -// CHECK2-NEXT: [[CALL14:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[VAR16]]) +// CHECK2-NEXT: [[CALL14:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR16]]) // CHECK2-NEXT: [[TOBOOL15:%.*]] = icmp ne i32 [[CALL14]], 0 // CHECK2-NEXT: br label [[LAND_END]] // CHECK2: land.end: // CHECK2-NEXT: [[TMP37:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL15]], [[LAND_RHS]] ] // CHECK2-NEXT: [[CONV:%.*]] = zext i1 [[TMP37]] to i32 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[CONV]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) // CHECK2-NEXT: [[TMP38:%.*]] = bitcast %struct.S.0* [[TMP2]] to i8* // CHECK2-NEXT: [[TMP39:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP38]], i8* align 4 [[TMP39]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK2-NEXT: [[TMP41:%.*]] = load i32, i32* [[T_VAR17]], align 4 // CHECK2-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP40]], [[TMP41]] @@ -7809,39 +7809,39 @@ int main() { // CHECK2-NEXT: [[TMP44:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK2-NEXT: [[TMP45:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP44]] monotonic, align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL21:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK2-NEXT: [[CALL21:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK2-NEXT: [[TMP46:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* // CHECK2-NEXT: [[TMP47:%.*]] = bitcast %struct.S.0* [[CALL21]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 4, i1 false) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL23:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP2]]) +// CHECK2-NEXT: [[CALL23:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK2-NEXT: [[TOBOOL24:%.*]] = icmp ne i32 [[CALL23]], 0 // CHECK2-NEXT: br i1 [[TOBOOL24]], label [[LAND_RHS25:%.*]], label [[LAND_END28:%.*]] // CHECK2: land.rhs25: -// CHECK2-NEXT: [[CALL26:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[VAR16]]) +// CHECK2-NEXT: [[CALL26:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR16]]) // CHECK2-NEXT: [[TOBOOL27:%.*]] = icmp ne i32 [[CALL26]], 0 // CHECK2-NEXT: br label [[LAND_END28]] // CHECK2: land.end28: // CHECK2-NEXT: [[TMP48:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE2]] ], [ [[TOBOOL27]], [[LAND_RHS25]] ] // CHECK2-NEXT: [[CONV29:%.*]] = zext i1 [[TMP48]] to i32 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP22]], i32 noundef [[CONV29]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP22]], i32 [[CONV29]]) // CHECK2-NEXT: [[TMP49:%.*]] = bitcast %struct.S.0* [[TMP2]] to i8* // CHECK2-NEXT: [[TMP50:%.*]] = bitcast %struct.S.0* [[REF_TMP22]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP22]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP22]]) #[[ATTR5]] // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[TMP51:%.*]] = load i32, i32* [[T_VAR17]], align 4 // CHECK2-NEXT: [[TMP52:%.*]] = atomicrmw min i32* [[TMP3]], i32 [[TMP51]] monotonic, align 4 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK2: .omp.reduction.default: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR16]]) #[[ATTR5]] -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR4]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR16]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.26 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -7880,25 +7880,25 @@ int main() { // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP17]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP14]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP14]]) // CHECK2-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* // CHECK2-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK2-NEXT: [[CALL2:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP23]]) +// CHECK2-NEXT: [[CALL2:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP23]]) // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL2]], 0 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK2: land.rhs: -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP20]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK2-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[CALL3]], 0 // CHECK2-NEXT: br label [[LAND_END]] // CHECK2: land.end: // CHECK2-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] // CHECK2-NEXT: [[CONV:%.*]] = zext i1 [[TMP34]] to i32 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[CONV]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) // CHECK2-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* // CHECK2-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK2-NEXT: [[TMP38:%.*]] = load i32, i32* [[TMP26]], align 4 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] @@ -7916,7 +7916,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEanERKS0_ -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -7927,7 +7927,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEcviEv -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -7936,17 +7936,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8092,7 +8092,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.28 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -8123,7 +8123,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [42 x %struct.S.0]* noundef nonnull align 4 dereferenceable(168) [[ARR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [42 x %struct.S.0]* nonnull align 4 dereferenceable(168) [[ARR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8172,7 +8172,7 @@ int main() { // CHECK2-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK2: omp.arrayinit.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] @@ -8259,14 +8259,14 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[RHS_BEGIN]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT13:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST10]]) -// CHECK2-NEXT: [[CALL11:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST10]]) +// CHECK2-NEXT: [[CALL11:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[CALL]], [[CALL11]] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[ADD12]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[ADD12]]) // CHECK2-NEXT: [[TMP39:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST10]] to i8* // CHECK2-NEXT: [[TMP40:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP39]], i8* align 4 [[TMP40]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT13]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE14:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT13]], [[TMP38]] @@ -8284,14 +8284,14 @@ int main() { // CHECK2-NEXT: [[TMP42:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP43:%.*]] = load i32, i32* [[TMP42]], align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP43]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL21:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST19]]) -// CHECK2-NEXT: [[CALL22:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST18]]) +// CHECK2-NEXT: [[CALL21:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST19]]) +// CHECK2-NEXT: [[CALL22:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST18]]) // CHECK2-NEXT: [[ADD23:%.*]] = add nsw i32 [[CALL21]], [[CALL22]] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP20]], i32 noundef [[ADD23]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP20]], i32 [[ADD23]]) // CHECK2-NEXT: [[TMP44:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST19]] to i8* // CHECK2-NEXT: [[TMP45:%.*]] = bitcast %struct.S.0* [[REF_TMP20]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP44]], i8* align 4 [[TMP45]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP20]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP20]]) #[[ATTR5]] // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP43]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT24]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST19]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT25]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST18]], i32 1 @@ -8307,7 +8307,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP46]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN28]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE29:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done29: @@ -8318,7 +8318,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.30 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -8341,14 +8341,14 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]]) -// CHECK2-NEXT: [[CALL2:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]]) +// CHECK2-NEXT: [[CALL2:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL2]] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[ADD]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[ADD]]) // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] @@ -8358,7 +8358,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -8371,7 +8371,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -8389,7 +8389,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -8403,12 +8403,12 @@ int main() { // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8476,7 +8476,7 @@ int main() { // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP2]], align 8 // CHECK3-NEXT: store double* [[TMP13]], double** [[TMP12]], align 8 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -8559,7 +8559,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -8599,12 +8599,12 @@ int main() { // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// CHECK4-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -8616,7 +8616,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8701,7 +8701,7 @@ int main() { // CHECK4-NEXT: [[TMP15:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP16:%.*]] = load i8*, i8** [[TMP14]], align 8 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8* [[TMP16]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP17]](i8* noundef [[TMP15]]) +// CHECK4-NEXT: call void [[TMP17]](i8* [[TMP15]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -8784,7 +8784,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@g1_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, double* }>*, align 8 @@ -8800,7 +8800,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 diff --git a/clang/test/OpenMP/for_reduction_codegen_UDR.cpp b/clang/test/OpenMP/for_reduction_codegen_UDR.cpp index c2a6c28432cd09c19a49e07a301d1186af16c0b3..d33753f0383e8d7e769f980cb834de8785f6d3b4 100644 --- a/clang/test/OpenMP/for_reduction_codegen_UDR.cpp +++ b/clang/test/OpenMP/for_reduction_codegen_UDR.cpp @@ -479,24 +479,24 @@ int main() { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[S]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S* [[S]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[S]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S]]) #[[ATTR4:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S* nonnull align 4 dereferenceable(12) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[S:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S* nonnull align 4 dereferenceable(12) [[S:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -510,7 +510,7 @@ int main() { // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: call void @.omp_initializer.(%struct.S* noundef [[S1]], %struct.S* noundef [[TMP0]]) +// CHECK1-NEXT: call void @.omp_initializer.(%struct.S* [[S1]], %struct.S* [[TMP0]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 @@ -533,13 +533,13 @@ int main() { // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: store i32 10, i32* [[I]], align 4 -// CHECK1-NEXT: call void @.omp_combiner.(%struct.S* noundef [[TMP0]], %struct.S* noundef [[S1]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[S1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @.omp_combiner.(%struct.S* [[TMP0]], %struct.S* [[S1]]) +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_combiner. -// CHECK1-SAME: (%struct.S* noalias noundef [[TMP0:%.*]], %struct.S* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (%struct.S* noalias [[TMP0:%.*]], %struct.S* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S*, align 8 @@ -556,7 +556,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_initializer. -// CHECK1-SAME: (%struct.S* noalias noundef [[TMP0:%.*]], %struct.S* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (%struct.S* noalias [[TMP0:%.*]], %struct.S* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S*, align 8 @@ -564,22 +564,22 @@ int main() { // CHECK1-NEXT: store %struct.S* [[TMP1]], %struct.S** [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[DOTADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[TMP3]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[TMP3]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S* nonnull align 4 dereferenceable(12) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -596,7 +596,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -622,38 +622,38 @@ int main() { // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[TEST]]) // CHECK1-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [4 x %struct.S.0], [4 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_ELEMENT]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_ELEMENT1]], float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT1]], float 3.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_ELEMENT1]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_ELEMENT2]], float noundef 4.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT2]], float 4.000000e+00) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[VAR1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[VAR1]]) // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [4 x %struct.S.0]], [10 x [4 x %struct.S.0]]* [[ARRS]], i32 0, i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 40 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef %struct.S.0** @_Z3foov() +// CHECK1-NEXT: [[CALL:%.*]] = call %struct.S.0** @_Z3foov() // CHECK1-NEXT: store %struct.S.0** [[CALL]], %struct.S.0*** [[VAR2]], align 8 // CHECK1-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [5 x %struct.S.0], [5 x %struct.S.0]* [[VVAR2]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN3]], i64 5 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP5:%.*]] // CHECK1: arrayctor.loop5: // CHECK1-NEXT: [[ARRAYCTOR_CUR6:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYCTOR_NEXT7:%.*]], [[ARRAYCTOR_LOOP5]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR6]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYCTOR_CUR6]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT7]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR6]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE8:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT7]], [[ARRAYCTOR_END4]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE8]], label [[ARRAYCTOR_CONT9:%.*]], label [[ARRAYCTOR_LOOP5]] @@ -677,7 +677,7 @@ int main() { // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [4 x %struct.S.0]*)* @.omp_outlined..19 to void (i32*, i32*, ...)*), [4 x %struct.S.0]* [[TMP6]]) // CHECK1-NEXT: [[TMP7:%.*]] = load [4 x %struct.S.0]*, [4 x %struct.S.0]** [[VAR3]], align 8 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [4 x %struct.S.0]*)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [4 x %struct.S.0]* [[TMP7]]) -// CHECK1-NEXT: [[CALL10:%.*]] = call noundef i32 @_Z5tmainIiLi42EET_v() +// CHECK1-NEXT: [[CALL10:%.*]] = call i32 @_Z5tmainIiLi42EET_v() // CHECK1-NEXT: store i32 [[CALL10]], i32* [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) @@ -687,7 +687,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[ARRAYCTOR_CONT9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done12: @@ -697,38 +697,38 @@ int main() { // CHECK1: arraydestroy.body14: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST15:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT16:%.*]], [[ARRAYDESTROY_BODY14]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT16]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST15]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE17:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT16]], [[ARRAY_BEGIN13]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE17]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY14]] // CHECK1: arraydestroy.done18: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[VAR1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[VAR1]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN19:%.*]] = getelementptr inbounds [4 x %struct.S.0], [4 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN19]], i64 4 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY20:%.*]] // CHECK1: arraydestroy.body20: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST21:%.*]] = phi %struct.S.0* [ [[TMP11]], [[ARRAYDESTROY_DONE18]] ], [ [[ARRAYDESTROY_ELEMENT22:%.*]], [[ARRAYDESTROY_BODY20]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT22]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST21]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT22]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT22]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE23:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT22]], [[ARRAY_BEGIN19]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE23]], label [[ARRAYDESTROY_DONE24:%.*]], label [[ARRAYDESTROY_BODY20]] // CHECK1: arraydestroy.done24: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP12]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -736,12 +736,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S.0* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(12) [[VAR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(12) [[VAR1:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [4 x %struct.S.0]* noundef nonnull align 4 dereferenceable(48) [[S_ARR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(12) [[VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(12) [[VAR1:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [4 x %struct.S.0]* nonnull align 4 dereferenceable(48) [[S_ARR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -787,7 +787,7 @@ int main() { // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: call void @.omp_initializer..3(float* noundef [[T_VAR3]], float* noundef [[TMP0]]) +// CHECK1-NEXT: call void @.omp_initializer..3(float* [[T_VAR3]], float* [[TMP0]]) // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* // CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[TMP8]], i64 4 @@ -795,9 +795,9 @@ int main() { // CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* // CHECK1-NEXT: [[ADD_PTR5:%.*]] = getelementptr inbounds i8, i8* [[TMP10]], i64 4 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[ADD_PTR5]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP9]], %struct.BaseS1* noundef [[TMP11]]) +// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP9]], %struct.BaseS1* [[TMP11]]) // CHECK1-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[_TMP6]], align 8 -// CHECK1-NEXT: call void @.omp_initializer..7(%struct.S.0* noundef [[VAR17]], %struct.S.0* noundef [[TMP2]]) +// CHECK1-NEXT: call void @.omp_initializer..7(%struct.S.0* [[VAR17]], %struct.S.0* [[TMP2]]) // CHECK1-NEXT: [[TMP12:%.*]] = load float, float* @.init, align 4 // CHECK1-NEXT: store float [[TMP12]], float* [[T_VAR18]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 @@ -839,7 +839,7 @@ int main() { // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP24]] to i64 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [4 x %struct.S.0], [4 x %struct.S.0]* [[TMP5]], i64 0, i64 [[IDXPROM10]] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S.0* @_ZN1SIfEaSERKS0_(%struct.S.0* noundef [[ARRAYIDX11]], %struct.S.0* noundef nonnull align 4 dereferenceable(12) [[TMP23]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S.0* @_ZN1SIfEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYIDX11]], %struct.S.0* nonnull align 4 dereferenceable(12) [[TMP23]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -871,21 +871,21 @@ int main() { // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: call void @.omp_combiner..2(float* noundef [[TMP0]], float* noundef [[T_VAR3]]) +// CHECK1-NEXT: call void @.omp_combiner..2(float* [[TMP0]], float* [[T_VAR3]]) // CHECK1-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* // CHECK1-NEXT: [[ADD_PTR13:%.*]] = getelementptr inbounds i8, i8* [[TMP36]], i64 4 // CHECK1-NEXT: [[TMP37:%.*]] = bitcast i8* [[ADD_PTR13]] to %struct.BaseS1* // CHECK1-NEXT: [[TMP38:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* // CHECK1-NEXT: [[ADD_PTR14:%.*]] = getelementptr inbounds i8, i8* [[TMP38]], i64 4 // CHECK1-NEXT: [[TMP39:%.*]] = bitcast i8* [[ADD_PTR14]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP37]], %struct.BaseS1* noundef [[TMP39]]) -// CHECK1-NEXT: call void @.omp_combiner..6(%struct.S.0* noundef [[TMP2]], %struct.S.0* noundef [[VAR17]]) -// CHECK1-NEXT: call void @.omp_combiner..8(float* noundef [[TMP3]], float* noundef [[T_VAR18]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP37]], %struct.BaseS1* [[TMP39]]) +// CHECK1-NEXT: call void @.omp_combiner..6(%struct.S.0* [[TMP2]], %struct.S.0* [[VAR17]]) +// CHECK1-NEXT: call void @.omp_combiner..8(float* [[TMP3]], float* [[T_VAR18]]) // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: call void @.omp_combiner..2(float* noundef [[TMP0]], float* noundef [[T_VAR3]]) +// CHECK1-NEXT: call void @.omp_combiner..2(float* [[TMP0]], float* [[T_VAR3]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[TMP40:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* @@ -894,25 +894,25 @@ int main() { // CHECK1-NEXT: [[TMP42:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* // CHECK1-NEXT: [[ADD_PTR16:%.*]] = getelementptr inbounds i8, i8* [[TMP42]], i64 4 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast i8* [[ADD_PTR16]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP41]], %struct.BaseS1* noundef [[TMP43]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP41]], %struct.BaseS1* [[TMP43]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: call void @.omp_combiner..6(%struct.S.0* noundef [[TMP2]], %struct.S.0* noundef [[VAR17]]) +// CHECK1-NEXT: call void @.omp_combiner..6(%struct.S.0* [[TMP2]], %struct.S.0* [[VAR17]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: call void @.omp_combiner..8(float* noundef [[TMP3]], float* noundef [[T_VAR18]]) +// CHECK1-NEXT: call void @.omp_combiner..8(float* [[TMP3]], float* [[T_VAR18]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[VAR17]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[VAR4]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[VAR17]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[VAR4]]) #[[ATTR4]] // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP14]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_combiner..2 -// CHECK1-SAME: (float* noalias noundef [[TMP0:%.*]], float* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (float* noalias [[TMP0:%.*]], float* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca float*, align 8 @@ -927,7 +927,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_initializer..3 -// CHECK1-SAME: (float* noalias noundef [[TMP0:%.*]], float* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (float* noalias [[TMP0:%.*]], float* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca float*, align 8 @@ -940,7 +940,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_combiner..4 -// CHECK1-SAME: (%struct.BaseS1* noalias noundef [[TMP0:%.*]], %struct.BaseS1* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (%struct.BaseS1* noalias [[TMP0:%.*]], %struct.BaseS1* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.BaseS1*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.BaseS1*, align 8 @@ -948,12 +948,12 @@ int main() { // CHECK1-NEXT: store %struct.BaseS1* [[TMP1]], %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR]], align 8 -// CHECK1-NEXT: call void @_Z3redR6BaseS1RKS_(%struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP2]]) +// CHECK1-NEXT: call void @_Z3redR6BaseS1RKS_(%struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_initializer..5 -// CHECK1-SAME: (%struct.BaseS1* noalias noundef [[TMP0:%.*]], %struct.BaseS1* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (%struct.BaseS1* noalias [[TMP0:%.*]], %struct.BaseS1* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.BaseS1*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.BaseS1*, align 8 @@ -961,12 +961,12 @@ int main() { // CHECK1-NEXT: store %struct.BaseS1* [[TMP1]], %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR]], align 8 -// CHECK1-NEXT: call void @_Z4initR6BaseS1RKS_(%struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP2]]) +// CHECK1-NEXT: call void @_Z4initR6BaseS1RKS_(%struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_combiner..6 -// CHECK1-SAME: (%struct.S.0* noalias noundef [[TMP0:%.*]], %struct.S.0* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (%struct.S.0* noalias [[TMP0:%.*]], %struct.S.0* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S.0*, align 8 @@ -984,7 +984,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_initializer..7 -// CHECK1-SAME: (%struct.S.0* noalias noundef [[TMP0:%.*]], %struct.S.0* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (%struct.S.0* noalias [[TMP0:%.*]], %struct.S.0* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S.0*, align 8 @@ -998,12 +998,12 @@ int main() { // CHECK1-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[TMP2]] to i8* // CHECK1-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP6]], i64 4 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK1-NEXT: call void @_Z5init1R6BaseS1RKS_(%struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP5]], %struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP7]]) +// CHECK1-NEXT: call void @_Z5init1R6BaseS1RKS_(%struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP5]], %struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP7]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1037,21 +1037,21 @@ int main() { // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 3 // CHECK1-NEXT: [[TMP28:%.*]] = load i8*, i8** [[TMP27]], align 8 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8* [[TMP28]] to float* -// CHECK1-NEXT: call void @.omp_combiner..2(float* noundef [[TMP11]], float* noundef [[TMP8]]) +// CHECK1-NEXT: call void @.omp_combiner..2(float* [[TMP11]], float* [[TMP8]]) // CHECK1-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* // CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[TMP30]], i64 4 // CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8* [[ADD_PTR]] to %struct.BaseS1* // CHECK1-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP14]] to i8* // CHECK1-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP32]], i64 4 // CHECK1-NEXT: [[TMP33:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP31]], %struct.BaseS1* noundef [[TMP33]]) -// CHECK1-NEXT: call void @.omp_combiner..6(%struct.S.0* noundef [[TMP23]], %struct.S.0* noundef [[TMP20]]) -// CHECK1-NEXT: call void @.omp_combiner..8(float* noundef [[TMP29]], float* noundef [[TMP26]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP31]], %struct.BaseS1* [[TMP33]]) +// CHECK1-NEXT: call void @.omp_combiner..6(%struct.S.0* [[TMP23]], %struct.S.0* [[TMP20]]) +// CHECK1-NEXT: call void @.omp_combiner..8(float* [[TMP29]], float* [[TMP26]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_combiner..8 -// CHECK1-SAME: (float* noalias noundef [[TMP0:%.*]], float* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (float* noalias [[TMP0:%.*]], float* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca float*, align 8 @@ -1066,17 +1066,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [10 x [4 x %struct.S.0]]* noundef nonnull align 4 dereferenceable(480) [[ARRS:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [10 x [4 x %struct.S.0]]* nonnull align 4 dereferenceable(480) [[ARRS:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1138,7 +1138,7 @@ int main() { // CHECK1: omp.arrayinit.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[ARRAYIDX3]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[VLA7]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT8:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK1-NEXT: call void @.omp_initializer..11(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: call void @.omp_initializer..11(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT8]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT8]], [[TMP16]] @@ -1179,7 +1179,7 @@ int main() { // CHECK1-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST19]] to i8* // CHECK1-NEXT: [[ADD_PTR21:%.*]] = getelementptr inbounds i8, i8* [[TMP33]], i64 4 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8* [[ADD_PTR21]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP32]], %struct.BaseS1* noundef [[TMP34]]) +// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP32]], %struct.BaseS1* [[TMP34]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT22]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST19]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT23]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST20]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE24:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT23]], [[TMP30]] @@ -1270,7 +1270,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST30:%.*]] = phi i32* [ [[VLA7]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST31:%.*]] = phi i32* [ [[ARRAYIDX3]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT32:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @.omp_combiner..10(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST31]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST30]]) +// CHECK1-NEXT: call void @.omp_combiner..10(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST31]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST30]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT32]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST31]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST30]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE33:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT32]], [[TMP68]] @@ -1288,7 +1288,7 @@ int main() { // CHECK1-NEXT: [[TMP72:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST37]] to i8* // CHECK1-NEXT: [[ADD_PTR40:%.*]] = getelementptr inbounds i8, i8* [[TMP72]], i64 4 // CHECK1-NEXT: [[TMP73:%.*]] = bitcast i8* [[ADD_PTR40]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP71]], %struct.BaseS1* noundef [[TMP73]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP71]], %struct.BaseS1* [[TMP73]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT41]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST38]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT42]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST37]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE43:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT41]], [[TMP69]] @@ -1306,7 +1306,7 @@ int main() { // CHECK1-NEXT: [[TMP75:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP76:%.*]] = load i32, i32* [[TMP75]], align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP76]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: call void @.omp_combiner..10(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST48]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST47]]) +// CHECK1-NEXT: call void @.omp_combiner..10(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST48]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST47]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP76]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT49]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST48]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT50]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST47]], i32 1 @@ -1328,7 +1328,7 @@ int main() { // CHECK1-NEXT: [[TMP82:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST55]] to i8* // CHECK1-NEXT: [[ADD_PTR58:%.*]] = getelementptr inbounds i8, i8* [[TMP82]], i64 4 // CHECK1-NEXT: [[TMP83:%.*]] = bitcast i8* [[ADD_PTR58]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP81]], %struct.BaseS1* noundef [[TMP83]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP81]], %struct.BaseS1* [[TMP83]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP79]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT59]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST56]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT60]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST55]], i32 1 @@ -1343,7 +1343,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP84]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[VLA16]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE63]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done63: @@ -1353,7 +1353,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_combiner..10 -// CHECK1-SAME: (i32* noalias noundef [[TMP0:%.*]], i32* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[TMP0:%.*]], i32* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32*, align 8 @@ -1368,7 +1368,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_initializer..11 -// CHECK1-SAME: (i32* noalias noundef [[TMP0:%.*]], i32* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[TMP0:%.*]], i32* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32*, align 8 @@ -1381,7 +1381,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.12 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1415,7 +1415,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @.omp_combiner..10(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: call void @.omp_combiner..10(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP24]] @@ -1433,7 +1433,7 @@ int main() { // CHECK1-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST5]] to i8* // CHECK1-NEXT: [[ADD_PTR7:%.*]] = getelementptr inbounds i8, i8* [[TMP28]], i64 4 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8* [[ADD_PTR7]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP27]], %struct.BaseS1* noundef [[TMP29]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP27]], %struct.BaseS1* [[TMP29]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT8]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST6]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT9]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST5]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE10:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT8]], [[TMP25]] @@ -1443,7 +1443,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]], [10 x [4 x %struct.S.0]]* noundef nonnull align 4 dereferenceable(480) [[ARRS:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARR:%.*]], [10 x [4 x %struct.S.0]]* nonnull align 4 dereferenceable(480) [[ARRS:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1489,7 +1489,7 @@ int main() { // CHECK1: omp.arrayinit.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[VLA3]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT4:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK1-NEXT: call void @.omp_initializer..11(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: call void @.omp_initializer..11(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP8]] @@ -1509,7 +1509,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST8]] to i8* // CHECK1-NEXT: [[ADD_PTR10:%.*]] = getelementptr inbounds i8, i8* [[TMP13]], i64 4 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8* [[ADD_PTR10]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP12]], %struct.BaseS1* noundef [[TMP14]]) +// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP12]], %struct.BaseS1* [[TMP14]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST8]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT12]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST9]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT12]], [[TMP10]] @@ -1592,7 +1592,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST18:%.*]] = phi i32* [ [[VLA3]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST19:%.*]] = phi i32* [ [[TMP2]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT20:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @.omp_combiner..10(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST19]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST18]]) +// CHECK1-NEXT: call void @.omp_combiner..10(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST19]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST18]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT20]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST19]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST18]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE21:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT20]], [[TMP39]] @@ -1610,7 +1610,7 @@ int main() { // CHECK1-NEXT: [[TMP43:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST25]] to i8* // CHECK1-NEXT: [[ADD_PTR28:%.*]] = getelementptr inbounds i8, i8* [[TMP43]], i64 4 // CHECK1-NEXT: [[TMP44:%.*]] = bitcast i8* [[ADD_PTR28]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP42]], %struct.BaseS1* noundef [[TMP44]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP42]], %struct.BaseS1* [[TMP44]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT29]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST26]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT30]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST25]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE31:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT29]], [[TMP40]] @@ -1628,7 +1628,7 @@ int main() { // CHECK1-NEXT: [[TMP46:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP47:%.*]] = load i32, i32* [[TMP46]], align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP47]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: call void @.omp_combiner..10(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST36]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST35]]) +// CHECK1-NEXT: call void @.omp_combiner..10(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST36]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST35]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP47]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT37]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST36]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT38]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST35]], i32 1 @@ -1650,7 +1650,7 @@ int main() { // CHECK1-NEXT: [[TMP53:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST43]] to i8* // CHECK1-NEXT: [[ADD_PTR46:%.*]] = getelementptr inbounds i8, i8* [[TMP53]], i64 4 // CHECK1-NEXT: [[TMP54:%.*]] = bitcast i8* [[ADD_PTR46]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP52]], %struct.BaseS1* noundef [[TMP54]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP52]], %struct.BaseS1* [[TMP54]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP50]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT47]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST44]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT48]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST43]], i32 1 @@ -1666,7 +1666,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP55]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE52:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done52: @@ -1679,7 +1679,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.14 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1710,7 +1710,7 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @.omp_combiner..10(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: call void @.omp_combiner..10(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]] @@ -1728,7 +1728,7 @@ int main() { // CHECK1-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST5]] to i8* // CHECK1-NEXT: [[ADD_PTR7:%.*]] = getelementptr inbounds i8, i8* [[TMP25]], i64 4 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8* [[ADD_PTR7]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP24]], %struct.BaseS1* noundef [[TMP26]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP24]], %struct.BaseS1* [[TMP26]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT8]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST6]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT9]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST5]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE10:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT8]], [[TMP22]] @@ -1738,7 +1738,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S.0*** noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S.0*** nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1793,7 +1793,7 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK1-NEXT: [[ADD_PTR4:%.*]] = getelementptr inbounds i8, i8* [[TMP15]], i64 4 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8* [[ADD_PTR4]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP14]], %struct.BaseS1* noundef [[TMP16]]) +// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP14]], %struct.BaseS1* [[TMP16]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT5]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT5]], [[TMP12]] @@ -1878,7 +1878,7 @@ int main() { // CHECK1-NEXT: [[TMP46:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST10]] to i8* // CHECK1-NEXT: [[ADD_PTR13:%.*]] = getelementptr inbounds i8, i8* [[TMP46]], i64 4 // CHECK1-NEXT: [[TMP47:%.*]] = bitcast i8* [[ADD_PTR13]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP45]], %struct.BaseS1* noundef [[TMP47]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP45]], %struct.BaseS1* [[TMP47]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT14]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE15:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT14]], [[TMP43]] @@ -1902,7 +1902,7 @@ int main() { // CHECK1-NEXT: [[TMP53:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST19]] to i8* // CHECK1-NEXT: [[ADD_PTR22:%.*]] = getelementptr inbounds i8, i8* [[TMP53]], i64 4 // CHECK1-NEXT: [[TMP54:%.*]] = bitcast i8* [[ADD_PTR22]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP52]], %struct.BaseS1* noundef [[TMP54]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP52]], %struct.BaseS1* [[TMP54]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP50]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT23]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST20]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT24]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST19]], i32 1 @@ -1918,7 +1918,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP55]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[VLA]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE27]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done27: @@ -1931,7 +1931,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.16 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1962,7 +1962,7 @@ int main() { // CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK1-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP18]], i64 4 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP17]], %struct.BaseS1* noundef [[TMP19]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP17]], %struct.BaseS1* [[TMP19]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] @@ -1972,7 +1972,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [5 x %struct.S.0]* noundef nonnull align 4 dereferenceable(60) [[VVAR2:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [5 x %struct.S.0]* nonnull align 4 dereferenceable(60) [[VVAR2:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2009,7 +2009,7 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK1-NEXT: [[ADD_PTR3:%.*]] = getelementptr inbounds i8, i8* [[TMP4]], i64 4 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[ADD_PTR3]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP3]], %struct.BaseS1* noundef [[TMP5]]) +// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP3]], %struct.BaseS1* [[TMP5]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP1]] @@ -2091,7 +2091,7 @@ int main() { // CHECK1-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST7]] to i8* // CHECK1-NEXT: [[ADD_PTR10:%.*]] = getelementptr inbounds i8, i8* [[TMP34]], i64 4 // CHECK1-NEXT: [[TMP35:%.*]] = bitcast i8* [[ADD_PTR10]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP33]], %struct.BaseS1* noundef [[TMP35]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP33]], %struct.BaseS1* [[TMP35]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST8]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST7]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE12:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT11]], [[TMP31]] @@ -2115,7 +2115,7 @@ int main() { // CHECK1-NEXT: [[TMP41:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST16]] to i8* // CHECK1-NEXT: [[ADD_PTR19:%.*]] = getelementptr inbounds i8, i8* [[TMP41]], i64 4 // CHECK1-NEXT: [[TMP42:%.*]] = bitcast i8* [[ADD_PTR19]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP40]], %struct.BaseS1* noundef [[TMP42]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP40]], %struct.BaseS1* [[TMP42]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP38]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT20]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST17]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT21]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST16]], i32 1 @@ -2131,7 +2131,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP43]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN24]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE25:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done25: @@ -2142,7 +2142,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.18 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2170,7 +2170,7 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK1-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP15]], i64 4 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP14]], %struct.BaseS1* noundef [[TMP16]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP14]], %struct.BaseS1* [[TMP16]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] @@ -2180,7 +2180,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [4 x %struct.S.0]* noundef nonnull align 4 dereferenceable(48) [[VAR3:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [4 x %struct.S.0]* nonnull align 4 dereferenceable(48) [[VAR3:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2225,7 +2225,7 @@ int main() { // CHECK1-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK1-NEXT: [[ADD_PTR5:%.*]] = getelementptr inbounds i8, i8* [[TMP7]], i64 4 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[ADD_PTR5]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP6]], %struct.BaseS1* noundef [[TMP8]]) +// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP6]], %struct.BaseS1* [[TMP8]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT6]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT6]], [[TMP4]] @@ -2309,7 +2309,7 @@ int main() { // CHECK1-NEXT: [[TMP38:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST10]] to i8* // CHECK1-NEXT: [[ADD_PTR13:%.*]] = getelementptr inbounds i8, i8* [[TMP38]], i64 4 // CHECK1-NEXT: [[TMP39:%.*]] = bitcast i8* [[ADD_PTR13]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP37]], %struct.BaseS1* noundef [[TMP39]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP37]], %struct.BaseS1* [[TMP39]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT14]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE15:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT14]], [[TMP35]] @@ -2333,7 +2333,7 @@ int main() { // CHECK1-NEXT: [[TMP45:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST19]] to i8* // CHECK1-NEXT: [[ADD_PTR22:%.*]] = getelementptr inbounds i8, i8* [[TMP45]], i64 4 // CHECK1-NEXT: [[TMP46:%.*]] = bitcast i8* [[ADD_PTR22]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP44]], %struct.BaseS1* noundef [[TMP46]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP44]], %struct.BaseS1* [[TMP46]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP42]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT23]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST20]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT24]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST19]], i32 1 @@ -2349,7 +2349,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP47]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN27]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE28:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done28: @@ -2360,7 +2360,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.20 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2388,7 +2388,7 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK1-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP15]], i64 4 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP14]], %struct.BaseS1* noundef [[TMP16]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP14]], %struct.BaseS1* [[TMP16]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] @@ -2398,7 +2398,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [4 x %struct.S.0]* noundef nonnull align 4 dereferenceable(48) [[VAR3:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [4 x %struct.S.0]* nonnull align 4 dereferenceable(48) [[VAR3:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2444,7 +2444,7 @@ int main() { // CHECK1-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK1-NEXT: [[ADD_PTR3:%.*]] = getelementptr inbounds i8, i8* [[TMP9]], i64 4 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8* [[ADD_PTR3]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP8]], %struct.BaseS1* noundef [[TMP10]]) +// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP8]], %struct.BaseS1* [[TMP10]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP6]] @@ -2514,7 +2514,7 @@ int main() { // CHECK1-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST8]] to i8* // CHECK1-NEXT: [[ADD_PTR11:%.*]] = getelementptr inbounds i8, i8* [[TMP25]], i64 4 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8* [[ADD_PTR11]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP24]], %struct.BaseS1* noundef [[TMP26]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP24]], %struct.BaseS1* [[TMP26]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT12]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST9]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST8]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT12]], [[TMP22]] @@ -2536,7 +2536,7 @@ int main() { // CHECK1-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST17]] to i8* // CHECK1-NEXT: [[ADD_PTR20:%.*]] = getelementptr inbounds i8, i8* [[TMP30]], i64 4 // CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8* [[ADD_PTR20]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP29]], %struct.BaseS1* noundef [[TMP31]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP29]], %struct.BaseS1* [[TMP31]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT21]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST18]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT22]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST17]], i32 1 @@ -2552,7 +2552,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN25]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE26:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done26: @@ -2563,7 +2563,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.22 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2591,7 +2591,7 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK1-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP15]], i64 4 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP14]], %struct.BaseS1* noundef [[TMP16]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP14]], %struct.BaseS1* [[TMP16]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] @@ -2613,22 +2613,22 @@ int main() { // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[ARR:%.*]] = alloca [42 x %struct.S], align 16 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiLi42EET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK1-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[VAR1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[VAR1]]) // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [42 x %struct.S], [42 x %struct.S]* [[ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 42 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] @@ -2646,28 +2646,28 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN1]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[VAR1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[VAR1]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY4:%.*]] // CHECK1: arraydestroy.body4: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST5:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE2]] ], [ [[ARRAYDESTROY_ELEMENT6:%.*]], [[ARRAYDESTROY_BODY4]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT6]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST5]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT6]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT6]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE7:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT6]], [[ARRAY_BEGIN3]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE7]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY4]] // CHECK1: arraydestroy.done8: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP6]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2684,7 +2684,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2706,7 +2706,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2715,7 +2715,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2723,12 +2723,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S* nonnull align 4 dereferenceable(12) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[VAR1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(24) [[S_ARR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(12) [[VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(12) [[VAR1:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(24) [[S_ARR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2774,7 +2774,7 @@ int main() { // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: call void @.omp_initializer..25(i32* noundef [[T_VAR3]], i32* noundef [[TMP0]]) +// CHECK1-NEXT: call void @.omp_initializer..25(i32* [[T_VAR3]], i32* [[TMP0]]) // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR4]] to i8* // CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[TMP8]], i64 4 @@ -2782,10 +2782,10 @@ int main() { // CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* // CHECK1-NEXT: [[ADD_PTR5:%.*]] = getelementptr inbounds i8, i8* [[TMP10]], i64 4 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[ADD_PTR5]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP9]], %struct.BaseS1* noundef [[TMP11]]) +// CHECK1-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP9]], %struct.BaseS1* [[TMP11]]) // CHECK1-NEXT: store %struct.S* [[VAR4]], %struct.S** [[_TMP6]], align 8 -// CHECK1-NEXT: call void @.omp_initializer..27(%struct.S* noundef [[VAR17]], %struct.S* noundef [[TMP2]]) -// CHECK1-NEXT: call void @.omp_initializer..29(i32* noundef [[T_VAR18]], i32* noundef [[TMP3]]) +// CHECK1-NEXT: call void @.omp_initializer..27(%struct.S* [[VAR17]], %struct.S* [[TMP2]]) +// CHECK1-NEXT: call void @.omp_initializer..29(i32* [[T_VAR18]], i32* [[TMP3]]) // CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2824,7 +2824,7 @@ int main() { // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP23]] to i64 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP5]], i64 0, i64 [[IDXPROM10]] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* noundef [[ARRAYIDX11]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[TMP22]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYIDX11]], %struct.S* nonnull align 4 dereferenceable(12) [[TMP22]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2856,21 +2856,21 @@ int main() { // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: call void @.omp_combiner..24(i32* noundef [[TMP0]], i32* noundef [[T_VAR3]]) +// CHECK1-NEXT: call void @.omp_combiner..24(i32* [[TMP0]], i32* [[T_VAR3]]) // CHECK1-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* // CHECK1-NEXT: [[ADD_PTR13:%.*]] = getelementptr inbounds i8, i8* [[TMP35]], i64 4 // CHECK1-NEXT: [[TMP36:%.*]] = bitcast i8* [[ADD_PTR13]] to %struct.BaseS1* // CHECK1-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[VAR4]] to i8* // CHECK1-NEXT: [[ADD_PTR14:%.*]] = getelementptr inbounds i8, i8* [[TMP37]], i64 4 // CHECK1-NEXT: [[TMP38:%.*]] = bitcast i8* [[ADD_PTR14]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP36]], %struct.BaseS1* noundef [[TMP38]]) -// CHECK1-NEXT: call void @.omp_combiner..26(%struct.S* noundef [[TMP2]], %struct.S* noundef [[VAR17]]) -// CHECK1-NEXT: call void @.omp_combiner..28(i32* noundef [[TMP3]], i32* noundef [[T_VAR18]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP36]], %struct.BaseS1* [[TMP38]]) +// CHECK1-NEXT: call void @.omp_combiner..26(%struct.S* [[TMP2]], %struct.S* [[VAR17]]) +// CHECK1-NEXT: call void @.omp_combiner..28(i32* [[TMP3]], i32* [[T_VAR18]]) // CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: call void @.omp_combiner..24(i32* noundef [[TMP0]], i32* noundef [[T_VAR3]]) +// CHECK1-NEXT: call void @.omp_combiner..24(i32* [[TMP0]], i32* [[T_VAR3]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[TMP39:%.*]] = bitcast %struct.S* [[TMP7]] to i8* @@ -2879,23 +2879,23 @@ int main() { // CHECK1-NEXT: [[TMP41:%.*]] = bitcast %struct.S* [[VAR4]] to i8* // CHECK1-NEXT: [[ADD_PTR16:%.*]] = getelementptr inbounds i8, i8* [[TMP41]], i64 4 // CHECK1-NEXT: [[TMP42:%.*]] = bitcast i8* [[ADD_PTR16]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP40]], %struct.BaseS1* noundef [[TMP42]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP40]], %struct.BaseS1* [[TMP42]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: call void @.omp_combiner..26(%struct.S* noundef [[TMP2]], %struct.S* noundef [[VAR17]]) +// CHECK1-NEXT: call void @.omp_combiner..26(%struct.S* [[TMP2]], %struct.S* [[VAR17]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: call void @.omp_combiner..28(i32* noundef [[TMP3]], i32* noundef [[T_VAR18]]) +// CHECK1-NEXT: call void @.omp_combiner..28(i32* [[TMP3]], i32* [[T_VAR18]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[VAR17]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[VAR17]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[VAR4]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_combiner..24 -// CHECK1-SAME: (i32* noalias noundef [[TMP0:%.*]], i32* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[TMP0:%.*]], i32* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32*, align 8 @@ -2910,7 +2910,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_initializer..25 -// CHECK1-SAME: (i32* noalias noundef [[TMP0:%.*]], i32* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[TMP0:%.*]], i32* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32*, align 8 @@ -2923,7 +2923,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_combiner..26 -// CHECK1-SAME: (%struct.S* noalias noundef [[TMP0:%.*]], %struct.S* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (%struct.S* noalias [[TMP0:%.*]], %struct.S* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S*, align 8 @@ -2940,7 +2940,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_initializer..27 -// CHECK1-SAME: (%struct.S* noalias noundef [[TMP0:%.*]], %struct.S* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (%struct.S* noalias [[TMP0:%.*]], %struct.S* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S*, align 8 @@ -2954,12 +2954,12 @@ int main() { // CHECK1-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[TMP2]] to i8* // CHECK1-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP6]], i64 4 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK1-NEXT: call void @_Z5init2R6BaseS1RKS_(%struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP5]], %struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP7]]) +// CHECK1-NEXT: call void @_Z5init2R6BaseS1RKS_(%struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP5]], %struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP7]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_combiner..28 -// CHECK1-SAME: (i32* noalias noundef [[TMP0:%.*]], i32* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[TMP0:%.*]], i32* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32*, align 8 @@ -2974,7 +2974,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_initializer..29 -// CHECK1-SAME: (i32* noalias noundef [[TMP0:%.*]], i32* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[TMP0:%.*]], i32* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32*, align 8 @@ -2989,7 +2989,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.30 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3023,21 +3023,21 @@ int main() { // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 3 // CHECK1-NEXT: [[TMP28:%.*]] = load i8*, i8** [[TMP27]], align 8 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8* [[TMP28]] to i32* -// CHECK1-NEXT: call void @.omp_combiner..24(i32* noundef [[TMP11]], i32* noundef [[TMP8]]) +// CHECK1-NEXT: call void @.omp_combiner..24(i32* [[TMP11]], i32* [[TMP8]]) // CHECK1-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP17]] to i8* // CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[TMP30]], i64 4 // CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8* [[ADD_PTR]] to %struct.BaseS1* // CHECK1-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP14]] to i8* // CHECK1-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP32]], i64 4 // CHECK1-NEXT: [[TMP33:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP31]], %struct.BaseS1* noundef [[TMP33]]) -// CHECK1-NEXT: call void @.omp_combiner..26(%struct.S* noundef [[TMP23]], %struct.S* noundef [[TMP20]]) -// CHECK1-NEXT: call void @.omp_combiner..28(i32* noundef [[TMP29]], i32* noundef [[TMP26]]) +// CHECK1-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP31]], %struct.BaseS1* [[TMP33]]) +// CHECK1-NEXT: call void @.omp_combiner..26(%struct.S* [[TMP23]], %struct.S* [[TMP20]]) +// CHECK1-NEXT: call void @.omp_combiner..28(i32* [[TMP29]], i32* [[TMP26]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..31 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(24) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[VAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(24) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(12) [[VAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3111,7 +3111,7 @@ int main() { // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i64 0, i64 [[IDXPROM5]] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* noundef [[ARRAYIDX6]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[TMP16]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYIDX6]], %struct.S* nonnull align 4 dereferenceable(12) [[TMP16]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3134,12 +3134,12 @@ int main() { // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: call void @.omp_combiner..34(i32* noundef [[TMP0]], i32* noundef [[T_VAR3]]) +// CHECK1-NEXT: call void @.omp_combiner..34(i32* [[TMP0]], i32* [[T_VAR3]]) // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: call void @.omp_combiner..34(i32* noundef [[TMP0]], i32* noundef [[T_VAR3]]) +// CHECK1-NEXT: call void @.omp_combiner..34(i32* [[TMP0]], i32* [[T_VAR3]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] @@ -3149,7 +3149,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.33 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3165,12 +3165,12 @@ int main() { // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK1-NEXT: call void @.omp_combiner..34(i32* noundef [[TMP11]], i32* noundef [[TMP8]]) +// CHECK1-NEXT: call void @.omp_combiner..34(i32* [[TMP11]], i32* [[TMP8]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_combiner..34 -// CHECK1-SAME: (i32* noalias noundef [[TMP0:%.*]], i32* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[TMP0:%.*]], i32* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32*, align 8 @@ -3185,7 +3185,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..35 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [42 x %struct.S]* noundef nonnull align 4 dereferenceable(504) [[ARR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(24) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[VAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [42 x %struct.S]* nonnull align 4 dereferenceable(504) [[ARR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(24) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(12) [[VAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3239,7 +3239,7 @@ int main() { // CHECK1-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK1-NEXT: [[ADD_PTR5:%.*]] = getelementptr inbounds i8, i8* [[TMP9]], i64 4 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8* [[ADD_PTR5]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_initializer..37(%struct.BaseS1* noundef [[TMP8]], %struct.BaseS1* noundef [[TMP10]]) +// CHECK1-NEXT: call void @.omp_initializer..37(%struct.BaseS1* [[TMP8]], %struct.BaseS1* [[TMP10]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT6]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT6]], [[TMP6]] @@ -3292,7 +3292,7 @@ int main() { // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP30]] to i64 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP3]], i64 0, i64 [[IDXPROM9]] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* noundef [[ARRAYIDX10]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[TMP29]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYIDX10]], %struct.S* nonnull align 4 dereferenceable(12) [[TMP29]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3331,7 +3331,7 @@ int main() { // CHECK1-NEXT: [[TMP43:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST12]] to i8* // CHECK1-NEXT: [[ADD_PTR15:%.*]] = getelementptr inbounds i8, i8* [[TMP43]], i64 4 // CHECK1-NEXT: [[TMP44:%.*]] = bitcast i8* [[ADD_PTR15]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..36(%struct.BaseS1* noundef [[TMP42]], %struct.BaseS1* noundef [[TMP44]]) +// CHECK1-NEXT: call void @.omp_combiner..36(%struct.BaseS1* [[TMP42]], %struct.BaseS1* [[TMP44]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT16]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST13]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST12]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE17:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT16]], [[TMP40]] @@ -3355,7 +3355,7 @@ int main() { // CHECK1-NEXT: [[TMP50:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST21]] to i8* // CHECK1-NEXT: [[ADD_PTR24:%.*]] = getelementptr inbounds i8, i8* [[TMP50]], i64 4 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8* [[ADD_PTR24]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..36(%struct.BaseS1* noundef [[TMP49]], %struct.BaseS1* noundef [[TMP51]]) +// CHECK1-NEXT: call void @.omp_combiner..36(%struct.BaseS1* [[TMP49]], %struct.BaseS1* [[TMP51]]) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP47]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT25]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST22]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT26]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST21]], i32 1 @@ -3371,7 +3371,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP52]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN29]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE30:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done30: @@ -3382,7 +3382,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_combiner..36 -// CHECK1-SAME: (%struct.BaseS1* noalias noundef [[TMP0:%.*]], %struct.BaseS1* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (%struct.BaseS1* noalias [[TMP0:%.*]], %struct.BaseS1* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.BaseS1*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.BaseS1*, align 8 @@ -3390,12 +3390,12 @@ int main() { // CHECK1-NEXT: store %struct.BaseS1* [[TMP1]], %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR]], align 8 -// CHECK1-NEXT: call void @_Z8red_plusR6BaseS1RKS_(%struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP2]]) +// CHECK1-NEXT: call void @_Z8red_plusR6BaseS1RKS_(%struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_initializer..37 -// CHECK1-SAME: (%struct.BaseS1* noalias noundef [[TMP0:%.*]], %struct.BaseS1* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (%struct.BaseS1* noalias [[TMP0:%.*]], %struct.BaseS1* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.BaseS1*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.BaseS1*, align 8 @@ -3403,12 +3403,12 @@ int main() { // CHECK1-NEXT: store %struct.BaseS1* [[TMP1]], %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR]], align 8 -// CHECK1-NEXT: call void @_Z9init_plusR6BaseS1RKS_(%struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP2]]) +// CHECK1-NEXT: call void @_Z9init_plusR6BaseS1RKS_(%struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.38 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3436,7 +3436,7 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK1-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP15]], i64 4 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK1-NEXT: call void @.omp_combiner..36(%struct.BaseS1* noundef [[TMP14]], %struct.BaseS1* noundef [[TMP16]]) +// CHECK1-NEXT: call void @.omp_combiner..36(%struct.BaseS1* [[TMP14]], %struct.BaseS1* [[TMP16]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] @@ -3446,7 +3446,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3471,24 +3471,24 @@ int main() { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[S]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S* [[S]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[S]]) #[[ATTR4:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S]]) #[[ATTR4:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S* nonnull align 4 dereferenceable(12) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[S:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S* nonnull align 4 dereferenceable(12) [[S:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3502,7 +3502,7 @@ int main() { // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: call void @.omp_initializer.(%struct.S* noundef [[S1]], %struct.S* noundef [[TMP0]]) +// CHECK2-NEXT: call void @.omp_initializer.(%struct.S* [[S1]], %struct.S* [[TMP0]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 @@ -3525,13 +3525,13 @@ int main() { // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: store i32 10, i32* [[I]], align 4 -// CHECK2-NEXT: call void @.omp_combiner.(%struct.S* noundef [[TMP0]], %struct.S* noundef [[S1]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[S1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @.omp_combiner.(%struct.S* [[TMP0]], %struct.S* [[S1]]) +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_combiner. -// CHECK2-SAME: (%struct.S* noalias noundef [[TMP0:%.*]], %struct.S* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (%struct.S* noalias [[TMP0:%.*]], %struct.S* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S*, align 8 @@ -3548,7 +3548,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_initializer. -// CHECK2-SAME: (%struct.S* noalias noundef [[TMP0:%.*]], %struct.S* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (%struct.S* noalias [[TMP0:%.*]], %struct.S* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S*, align 8 @@ -3556,22 +3556,22 @@ int main() { // CHECK2-NEXT: store %struct.S* [[TMP1]], %struct.S** [[DOTADDR1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[DOTADDR1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[DOTADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[TMP3]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[TMP3]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S* nonnull align 4 dereferenceable(12) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3588,7 +3588,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3614,38 +3614,38 @@ int main() { // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[TEST]]) // CHECK2-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [4 x %struct.S.0], [4 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_ELEMENT]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_ELEMENT1]], float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT1]], float 3.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_ELEMENT1]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_ELEMENT2]], float noundef 4.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT2]], float 4.000000e+00) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[VAR1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[VAR1]]) // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [4 x %struct.S.0]], [10 x [4 x %struct.S.0]]* [[ARRS]], i32 0, i32 0, i32 0 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 40 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef %struct.S.0** @_Z3foov() +// CHECK2-NEXT: [[CALL:%.*]] = call %struct.S.0** @_Z3foov() // CHECK2-NEXT: store %struct.S.0** [[CALL]], %struct.S.0*** [[VAR2]], align 8 // CHECK2-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [5 x %struct.S.0], [5 x %struct.S.0]* [[VVAR2]], i32 0, i32 0 // CHECK2-NEXT: [[ARRAYCTOR_END4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN3]], i64 5 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP5:%.*]] // CHECK2: arrayctor.loop5: // CHECK2-NEXT: [[ARRAYCTOR_CUR6:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYCTOR_NEXT7:%.*]], [[ARRAYCTOR_LOOP5]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR6]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYCTOR_CUR6]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT7]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR6]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE8:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT7]], [[ARRAYCTOR_END4]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE8]], label [[ARRAYCTOR_CONT9:%.*]], label [[ARRAYCTOR_LOOP5]] @@ -3669,7 +3669,7 @@ int main() { // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [4 x %struct.S.0]*)* @.omp_outlined..19 to void (i32*, i32*, ...)*), [4 x %struct.S.0]* [[TMP6]]) // CHECK2-NEXT: [[TMP7:%.*]] = load [4 x %struct.S.0]*, [4 x %struct.S.0]** [[VAR3]], align 8 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [4 x %struct.S.0]*)* @.omp_outlined..21 to void (i32*, i32*, ...)*), [4 x %struct.S.0]* [[TMP7]]) -// CHECK2-NEXT: [[CALL10:%.*]] = call noundef i32 @_Z5tmainIiLi42EET_v() +// CHECK2-NEXT: [[CALL10:%.*]] = call i32 @_Z5tmainIiLi42EET_v() // CHECK2-NEXT: store i32 [[CALL10]], i32* [[RETVAL]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP8]]) @@ -3679,7 +3679,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[ARRAYCTOR_CONT9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done12: @@ -3689,38 +3689,38 @@ int main() { // CHECK2: arraydestroy.body14: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST15:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT16:%.*]], [[ARRAYDESTROY_BODY14]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT16]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST15]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE17:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT16]], [[ARRAY_BEGIN13]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE17]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY14]] // CHECK2: arraydestroy.done18: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[VAR1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[VAR1]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN19:%.*]] = getelementptr inbounds [4 x %struct.S.0], [4 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN19]], i64 4 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY20:%.*]] // CHECK2: arraydestroy.body20: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST21:%.*]] = phi %struct.S.0* [ [[TMP11]], [[ARRAYDESTROY_DONE18]] ], [ [[ARRAYDESTROY_ELEMENT22:%.*]], [[ARRAYDESTROY_BODY20]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT22]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST21]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT22]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT22]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE23:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT22]], [[ARRAY_BEGIN19]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE23]], label [[ARRAYDESTROY_DONE24:%.*]], label [[ARRAYDESTROY_BODY20]] // CHECK2: arraydestroy.done24: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[TEST]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP12]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3728,12 +3728,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S.0* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(12) [[VAR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(12) [[VAR1:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [4 x %struct.S.0]* noundef nonnull align 4 dereferenceable(48) [[S_ARR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(12) [[VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(12) [[VAR1:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [4 x %struct.S.0]* nonnull align 4 dereferenceable(48) [[S_ARR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3779,7 +3779,7 @@ int main() { // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK2-NEXT: call void @.omp_initializer..3(float* noundef [[T_VAR3]], float* noundef [[TMP0]]) +// CHECK2-NEXT: call void @.omp_initializer..3(float* [[T_VAR3]], float* [[TMP0]]) // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* // CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[TMP8]], i64 4 @@ -3787,9 +3787,9 @@ int main() { // CHECK2-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* // CHECK2-NEXT: [[ADD_PTR5:%.*]] = getelementptr inbounds i8, i8* [[TMP10]], i64 4 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8* [[ADD_PTR5]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP9]], %struct.BaseS1* noundef [[TMP11]]) +// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP9]], %struct.BaseS1* [[TMP11]]) // CHECK2-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[_TMP6]], align 8 -// CHECK2-NEXT: call void @.omp_initializer..7(%struct.S.0* noundef [[VAR17]], %struct.S.0* noundef [[TMP2]]) +// CHECK2-NEXT: call void @.omp_initializer..7(%struct.S.0* [[VAR17]], %struct.S.0* [[TMP2]]) // CHECK2-NEXT: [[TMP12:%.*]] = load float, float* @.init, align 4 // CHECK2-NEXT: store float [[TMP12]], float* [[T_VAR18]], align 4 // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 @@ -3831,7 +3831,7 @@ int main() { // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP24]] to i64 // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [4 x %struct.S.0], [4 x %struct.S.0]* [[TMP5]], i64 0, i64 [[IDXPROM10]] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S.0* @_ZN1SIfEaSERKS0_(%struct.S.0* noundef [[ARRAYIDX11]], %struct.S.0* noundef nonnull align 4 dereferenceable(12) [[TMP23]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S.0* @_ZN1SIfEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYIDX11]], %struct.S.0* nonnull align 4 dereferenceable(12) [[TMP23]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3863,21 +3863,21 @@ int main() { // CHECK2-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK2-NEXT: ] // CHECK2: .omp.reduction.case1: -// CHECK2-NEXT: call void @.omp_combiner..2(float* noundef [[TMP0]], float* noundef [[T_VAR3]]) +// CHECK2-NEXT: call void @.omp_combiner..2(float* [[TMP0]], float* [[T_VAR3]]) // CHECK2-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* // CHECK2-NEXT: [[ADD_PTR13:%.*]] = getelementptr inbounds i8, i8* [[TMP36]], i64 4 // CHECK2-NEXT: [[TMP37:%.*]] = bitcast i8* [[ADD_PTR13]] to %struct.BaseS1* // CHECK2-NEXT: [[TMP38:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* // CHECK2-NEXT: [[ADD_PTR14:%.*]] = getelementptr inbounds i8, i8* [[TMP38]], i64 4 // CHECK2-NEXT: [[TMP39:%.*]] = bitcast i8* [[ADD_PTR14]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP37]], %struct.BaseS1* noundef [[TMP39]]) -// CHECK2-NEXT: call void @.omp_combiner..6(%struct.S.0* noundef [[TMP2]], %struct.S.0* noundef [[VAR17]]) -// CHECK2-NEXT: call void @.omp_combiner..8(float* noundef [[TMP3]], float* noundef [[T_VAR18]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP37]], %struct.BaseS1* [[TMP39]]) +// CHECK2-NEXT: call void @.omp_combiner..6(%struct.S.0* [[TMP2]], %struct.S.0* [[VAR17]]) +// CHECK2-NEXT: call void @.omp_combiner..8(float* [[TMP3]], float* [[T_VAR18]]) // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK2: .omp.reduction.case2: // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: call void @.omp_combiner..2(float* noundef [[TMP0]], float* noundef [[T_VAR3]]) +// CHECK2-NEXT: call void @.omp_combiner..2(float* [[TMP0]], float* [[T_VAR3]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[TMP40:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* @@ -3886,25 +3886,25 @@ int main() { // CHECK2-NEXT: [[TMP42:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* // CHECK2-NEXT: [[ADD_PTR16:%.*]] = getelementptr inbounds i8, i8* [[TMP42]], i64 4 // CHECK2-NEXT: [[TMP43:%.*]] = bitcast i8* [[ADD_PTR16]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP41]], %struct.BaseS1* noundef [[TMP43]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP41]], %struct.BaseS1* [[TMP43]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: call void @.omp_combiner..6(%struct.S.0* noundef [[TMP2]], %struct.S.0* noundef [[VAR17]]) +// CHECK2-NEXT: call void @.omp_combiner..6(%struct.S.0* [[TMP2]], %struct.S.0* [[VAR17]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: call void @.omp_combiner..8(float* noundef [[TMP3]], float* noundef [[T_VAR18]]) +// CHECK2-NEXT: call void @.omp_combiner..8(float* [[TMP3]], float* [[T_VAR18]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB3]], i32 [[TMP14]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK2: .omp.reduction.default: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[VAR17]]) #[[ATTR4]] -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[VAR4]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[VAR17]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[VAR4]]) #[[ATTR4]] // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP14]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_combiner..2 -// CHECK2-SAME: (float* noalias noundef [[TMP0:%.*]], float* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (float* noalias [[TMP0:%.*]], float* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca float*, align 8 @@ -3919,7 +3919,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_initializer..3 -// CHECK2-SAME: (float* noalias noundef [[TMP0:%.*]], float* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (float* noalias [[TMP0:%.*]], float* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca float*, align 8 @@ -3932,7 +3932,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_combiner..4 -// CHECK2-SAME: (%struct.BaseS1* noalias noundef [[TMP0:%.*]], %struct.BaseS1* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (%struct.BaseS1* noalias [[TMP0:%.*]], %struct.BaseS1* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.BaseS1*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.BaseS1*, align 8 @@ -3940,12 +3940,12 @@ int main() { // CHECK2-NEXT: store %struct.BaseS1* [[TMP1]], %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR]], align 8 -// CHECK2-NEXT: call void @_Z3redR6BaseS1RKS_(%struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP2]]) +// CHECK2-NEXT: call void @_Z3redR6BaseS1RKS_(%struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_initializer..5 -// CHECK2-SAME: (%struct.BaseS1* noalias noundef [[TMP0:%.*]], %struct.BaseS1* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (%struct.BaseS1* noalias [[TMP0:%.*]], %struct.BaseS1* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.BaseS1*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.BaseS1*, align 8 @@ -3953,12 +3953,12 @@ int main() { // CHECK2-NEXT: store %struct.BaseS1* [[TMP1]], %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR]], align 8 -// CHECK2-NEXT: call void @_Z4initR6BaseS1RKS_(%struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP2]]) +// CHECK2-NEXT: call void @_Z4initR6BaseS1RKS_(%struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_combiner..6 -// CHECK2-SAME: (%struct.S.0* noalias noundef [[TMP0:%.*]], %struct.S.0* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (%struct.S.0* noalias [[TMP0:%.*]], %struct.S.0* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S.0*, align 8 @@ -3976,7 +3976,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_initializer..7 -// CHECK2-SAME: (%struct.S.0* noalias noundef [[TMP0:%.*]], %struct.S.0* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (%struct.S.0* noalias [[TMP0:%.*]], %struct.S.0* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S.0*, align 8 @@ -3990,12 +3990,12 @@ int main() { // CHECK2-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[TMP2]] to i8* // CHECK2-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP6]], i64 4 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK2-NEXT: call void @_Z5init1R6BaseS1RKS_(%struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP5]], %struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP7]]) +// CHECK2-NEXT: call void @_Z5init1R6BaseS1RKS_(%struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP5]], %struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP7]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4029,21 +4029,21 @@ int main() { // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 3 // CHECK2-NEXT: [[TMP28:%.*]] = load i8*, i8** [[TMP27]], align 8 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8* [[TMP28]] to float* -// CHECK2-NEXT: call void @.omp_combiner..2(float* noundef [[TMP11]], float* noundef [[TMP8]]) +// CHECK2-NEXT: call void @.omp_combiner..2(float* [[TMP11]], float* [[TMP8]]) // CHECK2-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* // CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[TMP30]], i64 4 // CHECK2-NEXT: [[TMP31:%.*]] = bitcast i8* [[ADD_PTR]] to %struct.BaseS1* // CHECK2-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP14]] to i8* // CHECK2-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP32]], i64 4 // CHECK2-NEXT: [[TMP33:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP31]], %struct.BaseS1* noundef [[TMP33]]) -// CHECK2-NEXT: call void @.omp_combiner..6(%struct.S.0* noundef [[TMP23]], %struct.S.0* noundef [[TMP20]]) -// CHECK2-NEXT: call void @.omp_combiner..8(float* noundef [[TMP29]], float* noundef [[TMP26]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP31]], %struct.BaseS1* [[TMP33]]) +// CHECK2-NEXT: call void @.omp_combiner..6(%struct.S.0* [[TMP23]], %struct.S.0* [[TMP20]]) +// CHECK2-NEXT: call void @.omp_combiner..8(float* [[TMP29]], float* [[TMP26]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_combiner..8 -// CHECK2-SAME: (float* noalias noundef [[TMP0:%.*]], float* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (float* noalias [[TMP0:%.*]], float* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca float*, align 8 @@ -4058,17 +4058,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [10 x [4 x %struct.S.0]]* noundef nonnull align 4 dereferenceable(480) [[ARRS:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [10 x [4 x %struct.S.0]]* nonnull align 4 dereferenceable(480) [[ARRS:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4130,7 +4130,7 @@ int main() { // CHECK2: omp.arrayinit.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[ARRAYIDX3]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[VLA7]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT8:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK2-NEXT: call void @.omp_initializer..11(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: call void @.omp_initializer..11(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT8]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT8]], [[TMP16]] @@ -4171,7 +4171,7 @@ int main() { // CHECK2-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST19]] to i8* // CHECK2-NEXT: [[ADD_PTR21:%.*]] = getelementptr inbounds i8, i8* [[TMP33]], i64 4 // CHECK2-NEXT: [[TMP34:%.*]] = bitcast i8* [[ADD_PTR21]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP32]], %struct.BaseS1* noundef [[TMP34]]) +// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP32]], %struct.BaseS1* [[TMP34]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT22]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST19]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT23]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST20]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE24:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT23]], [[TMP30]] @@ -4262,7 +4262,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST30:%.*]] = phi i32* [ [[VLA7]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST31:%.*]] = phi i32* [ [[ARRAYIDX3]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT32:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @.omp_combiner..10(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST31]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST30]]) +// CHECK2-NEXT: call void @.omp_combiner..10(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST31]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST30]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT32]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST31]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST30]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE33:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT32]], [[TMP68]] @@ -4280,7 +4280,7 @@ int main() { // CHECK2-NEXT: [[TMP72:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST37]] to i8* // CHECK2-NEXT: [[ADD_PTR40:%.*]] = getelementptr inbounds i8, i8* [[TMP72]], i64 4 // CHECK2-NEXT: [[TMP73:%.*]] = bitcast i8* [[ADD_PTR40]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP71]], %struct.BaseS1* noundef [[TMP73]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP71]], %struct.BaseS1* [[TMP73]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT41]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST38]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT42]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST37]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE43:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT41]], [[TMP69]] @@ -4298,7 +4298,7 @@ int main() { // CHECK2-NEXT: [[TMP75:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP76:%.*]] = load i32, i32* [[TMP75]], align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP76]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: call void @.omp_combiner..10(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST48]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST47]]) +// CHECK2-NEXT: call void @.omp_combiner..10(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST48]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST47]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP76]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT49]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST48]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT50]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST47]], i32 1 @@ -4320,7 +4320,7 @@ int main() { // CHECK2-NEXT: [[TMP82:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST55]] to i8* // CHECK2-NEXT: [[ADD_PTR58:%.*]] = getelementptr inbounds i8, i8* [[TMP82]], i64 4 // CHECK2-NEXT: [[TMP83:%.*]] = bitcast i8* [[ADD_PTR58]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP81]], %struct.BaseS1* noundef [[TMP83]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP81]], %struct.BaseS1* [[TMP83]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP79]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT59]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST56]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT60]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST55]], i32 1 @@ -4335,7 +4335,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP84]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[VLA16]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE63]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done63: @@ -4345,7 +4345,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_combiner..10 -// CHECK2-SAME: (i32* noalias noundef [[TMP0:%.*]], i32* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[TMP0:%.*]], i32* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32*, align 8 @@ -4360,7 +4360,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_initializer..11 -// CHECK2-SAME: (i32* noalias noundef [[TMP0:%.*]], i32* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[TMP0:%.*]], i32* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32*, align 8 @@ -4373,7 +4373,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.12 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4407,7 +4407,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @.omp_combiner..10(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: call void @.omp_combiner..10(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP24]] @@ -4425,7 +4425,7 @@ int main() { // CHECK2-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST5]] to i8* // CHECK2-NEXT: [[ADD_PTR7:%.*]] = getelementptr inbounds i8, i8* [[TMP28]], i64 4 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8* [[ADD_PTR7]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP27]], %struct.BaseS1* noundef [[TMP29]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP27]], %struct.BaseS1* [[TMP29]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT8]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST6]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT9]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST5]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE10:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT8]], [[TMP25]] @@ -4435,7 +4435,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]], [10 x [4 x %struct.S.0]]* noundef nonnull align 4 dereferenceable(480) [[ARRS:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARR:%.*]], [10 x [4 x %struct.S.0]]* nonnull align 4 dereferenceable(480) [[ARRS:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4481,7 +4481,7 @@ int main() { // CHECK2: omp.arrayinit.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[VLA3]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT4:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK2-NEXT: call void @.omp_initializer..11(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: call void @.omp_initializer..11(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP8]] @@ -4501,7 +4501,7 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST8]] to i8* // CHECK2-NEXT: [[ADD_PTR10:%.*]] = getelementptr inbounds i8, i8* [[TMP13]], i64 4 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8* [[ADD_PTR10]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP12]], %struct.BaseS1* noundef [[TMP14]]) +// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP12]], %struct.BaseS1* [[TMP14]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST8]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT12]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST9]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT12]], [[TMP10]] @@ -4584,7 +4584,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST18:%.*]] = phi i32* [ [[VLA3]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST19:%.*]] = phi i32* [ [[TMP2]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT20:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @.omp_combiner..10(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST19]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST18]]) +// CHECK2-NEXT: call void @.omp_combiner..10(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST19]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST18]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT20]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST19]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST18]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE21:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT20]], [[TMP39]] @@ -4602,7 +4602,7 @@ int main() { // CHECK2-NEXT: [[TMP43:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST25]] to i8* // CHECK2-NEXT: [[ADD_PTR28:%.*]] = getelementptr inbounds i8, i8* [[TMP43]], i64 4 // CHECK2-NEXT: [[TMP44:%.*]] = bitcast i8* [[ADD_PTR28]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP42]], %struct.BaseS1* noundef [[TMP44]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP42]], %struct.BaseS1* [[TMP44]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT29]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST26]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT30]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST25]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE31:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT29]], [[TMP40]] @@ -4620,7 +4620,7 @@ int main() { // CHECK2-NEXT: [[TMP46:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP47:%.*]] = load i32, i32* [[TMP46]], align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP47]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: call void @.omp_combiner..10(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST36]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST35]]) +// CHECK2-NEXT: call void @.omp_combiner..10(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST36]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST35]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP47]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT37]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST36]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT38]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST35]], i32 1 @@ -4642,7 +4642,7 @@ int main() { // CHECK2-NEXT: [[TMP53:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST43]] to i8* // CHECK2-NEXT: [[ADD_PTR46:%.*]] = getelementptr inbounds i8, i8* [[TMP53]], i64 4 // CHECK2-NEXT: [[TMP54:%.*]] = bitcast i8* [[ADD_PTR46]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP52]], %struct.BaseS1* noundef [[TMP54]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP52]], %struct.BaseS1* [[TMP54]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP50]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT47]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST44]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT48]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST43]], i32 1 @@ -4658,7 +4658,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP55]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE52:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done52: @@ -4671,7 +4671,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.14 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4702,7 +4702,7 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi i32* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi i32* [ [[TMP11]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @.omp_combiner..10(i32* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* noundef [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: call void @.omp_combiner..10(i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, i32* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq i32* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]] @@ -4720,7 +4720,7 @@ int main() { // CHECK2-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST5]] to i8* // CHECK2-NEXT: [[ADD_PTR7:%.*]] = getelementptr inbounds i8, i8* [[TMP25]], i64 4 // CHECK2-NEXT: [[TMP26:%.*]] = bitcast i8* [[ADD_PTR7]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP24]], %struct.BaseS1* noundef [[TMP26]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP24]], %struct.BaseS1* [[TMP26]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT8]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST6]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT9]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST5]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE10:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT8]], [[TMP22]] @@ -4730,7 +4730,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S.0*** noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S.0*** nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4785,7 +4785,7 @@ int main() { // CHECK2-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK2-NEXT: [[ADD_PTR4:%.*]] = getelementptr inbounds i8, i8* [[TMP15]], i64 4 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8* [[ADD_PTR4]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP14]], %struct.BaseS1* noundef [[TMP16]]) +// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP14]], %struct.BaseS1* [[TMP16]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT5]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT5]], [[TMP12]] @@ -4870,7 +4870,7 @@ int main() { // CHECK2-NEXT: [[TMP46:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST10]] to i8* // CHECK2-NEXT: [[ADD_PTR13:%.*]] = getelementptr inbounds i8, i8* [[TMP46]], i64 4 // CHECK2-NEXT: [[TMP47:%.*]] = bitcast i8* [[ADD_PTR13]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP45]], %struct.BaseS1* noundef [[TMP47]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP45]], %struct.BaseS1* [[TMP47]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT14]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE15:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT14]], [[TMP43]] @@ -4894,7 +4894,7 @@ int main() { // CHECK2-NEXT: [[TMP53:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST19]] to i8* // CHECK2-NEXT: [[ADD_PTR22:%.*]] = getelementptr inbounds i8, i8* [[TMP53]], i64 4 // CHECK2-NEXT: [[TMP54:%.*]] = bitcast i8* [[ADD_PTR22]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP52]], %struct.BaseS1* noundef [[TMP54]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP52]], %struct.BaseS1* [[TMP54]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP50]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT23]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST20]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT24]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST19]], i32 1 @@ -4910,7 +4910,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP55]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[VLA]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE27]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done27: @@ -4923,7 +4923,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.16 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4954,7 +4954,7 @@ int main() { // CHECK2-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK2-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP18]], i64 4 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP17]], %struct.BaseS1* noundef [[TMP19]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP17]], %struct.BaseS1* [[TMP19]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] @@ -4964,7 +4964,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [5 x %struct.S.0]* noundef nonnull align 4 dereferenceable(60) [[VVAR2:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [5 x %struct.S.0]* nonnull align 4 dereferenceable(60) [[VVAR2:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5001,7 +5001,7 @@ int main() { // CHECK2-NEXT: [[TMP4:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK2-NEXT: [[ADD_PTR3:%.*]] = getelementptr inbounds i8, i8* [[TMP4]], i64 4 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[ADD_PTR3]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP3]], %struct.BaseS1* noundef [[TMP5]]) +// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP3]], %struct.BaseS1* [[TMP5]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP1]] @@ -5083,7 +5083,7 @@ int main() { // CHECK2-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST7]] to i8* // CHECK2-NEXT: [[ADD_PTR10:%.*]] = getelementptr inbounds i8, i8* [[TMP34]], i64 4 // CHECK2-NEXT: [[TMP35:%.*]] = bitcast i8* [[ADD_PTR10]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP33]], %struct.BaseS1* noundef [[TMP35]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP33]], %struct.BaseS1* [[TMP35]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT11]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST8]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST7]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE12:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT11]], [[TMP31]] @@ -5107,7 +5107,7 @@ int main() { // CHECK2-NEXT: [[TMP41:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST16]] to i8* // CHECK2-NEXT: [[ADD_PTR19:%.*]] = getelementptr inbounds i8, i8* [[TMP41]], i64 4 // CHECK2-NEXT: [[TMP42:%.*]] = bitcast i8* [[ADD_PTR19]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP40]], %struct.BaseS1* noundef [[TMP42]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP40]], %struct.BaseS1* [[TMP42]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP38]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT20]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST17]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT21]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST16]], i32 1 @@ -5123,7 +5123,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP43]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN24]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE25:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done25: @@ -5134,7 +5134,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.18 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -5162,7 +5162,7 @@ int main() { // CHECK2-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK2-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP15]], i64 4 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP14]], %struct.BaseS1* noundef [[TMP16]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP14]], %struct.BaseS1* [[TMP16]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] @@ -5172,7 +5172,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [4 x %struct.S.0]* noundef nonnull align 4 dereferenceable(48) [[VAR3:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [4 x %struct.S.0]* nonnull align 4 dereferenceable(48) [[VAR3:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5217,7 +5217,7 @@ int main() { // CHECK2-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK2-NEXT: [[ADD_PTR5:%.*]] = getelementptr inbounds i8, i8* [[TMP7]], i64 4 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[ADD_PTR5]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP6]], %struct.BaseS1* noundef [[TMP8]]) +// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP6]], %struct.BaseS1* [[TMP8]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT6]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT6]], [[TMP4]] @@ -5301,7 +5301,7 @@ int main() { // CHECK2-NEXT: [[TMP38:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST10]] to i8* // CHECK2-NEXT: [[ADD_PTR13:%.*]] = getelementptr inbounds i8, i8* [[TMP38]], i64 4 // CHECK2-NEXT: [[TMP39:%.*]] = bitcast i8* [[ADD_PTR13]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP37]], %struct.BaseS1* noundef [[TMP39]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP37]], %struct.BaseS1* [[TMP39]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT14]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST10]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE15:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT14]], [[TMP35]] @@ -5325,7 +5325,7 @@ int main() { // CHECK2-NEXT: [[TMP45:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST19]] to i8* // CHECK2-NEXT: [[ADD_PTR22:%.*]] = getelementptr inbounds i8, i8* [[TMP45]], i64 4 // CHECK2-NEXT: [[TMP46:%.*]] = bitcast i8* [[ADD_PTR22]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP44]], %struct.BaseS1* noundef [[TMP46]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP44]], %struct.BaseS1* [[TMP46]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP42]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT23]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST20]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT24]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST19]], i32 1 @@ -5341,7 +5341,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP47]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN27]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE28:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done28: @@ -5352,7 +5352,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.20 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -5380,7 +5380,7 @@ int main() { // CHECK2-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK2-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP15]], i64 4 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP14]], %struct.BaseS1* noundef [[TMP16]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP14]], %struct.BaseS1* [[TMP16]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] @@ -5390,7 +5390,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [4 x %struct.S.0]* noundef nonnull align 4 dereferenceable(48) [[VAR3:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [4 x %struct.S.0]* nonnull align 4 dereferenceable(48) [[VAR3:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5436,7 +5436,7 @@ int main() { // CHECK2-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK2-NEXT: [[ADD_PTR3:%.*]] = getelementptr inbounds i8, i8* [[TMP9]], i64 4 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8* [[ADD_PTR3]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP8]], %struct.BaseS1* noundef [[TMP10]]) +// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP8]], %struct.BaseS1* [[TMP10]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT4]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT4]], [[TMP6]] @@ -5506,7 +5506,7 @@ int main() { // CHECK2-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST8]] to i8* // CHECK2-NEXT: [[ADD_PTR11:%.*]] = getelementptr inbounds i8, i8* [[TMP25]], i64 4 // CHECK2-NEXT: [[TMP26:%.*]] = bitcast i8* [[ADD_PTR11]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP24]], %struct.BaseS1* noundef [[TMP26]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP24]], %struct.BaseS1* [[TMP26]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT12]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST9]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST8]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE13:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT12]], [[TMP22]] @@ -5528,7 +5528,7 @@ int main() { // CHECK2-NEXT: [[TMP30:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST17]] to i8* // CHECK2-NEXT: [[ADD_PTR20:%.*]] = getelementptr inbounds i8, i8* [[TMP30]], i64 4 // CHECK2-NEXT: [[TMP31:%.*]] = bitcast i8* [[ADD_PTR20]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP29]], %struct.BaseS1* noundef [[TMP31]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP29]], %struct.BaseS1* [[TMP31]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT21]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST18]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT22]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST17]], i32 1 @@ -5544,7 +5544,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN25]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE26:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done26: @@ -5555,7 +5555,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.22 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -5583,7 +5583,7 @@ int main() { // CHECK2-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK2-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP15]], i64 4 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP14]], %struct.BaseS1* noundef [[TMP16]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP14]], %struct.BaseS1* [[TMP16]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] @@ -5605,22 +5605,22 @@ int main() { // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK2-NEXT: [[ARR:%.*]] = alloca [42 x %struct.S], align 16 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiLi42EET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK2-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[VAR1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[VAR1]]) // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [42 x %struct.S], [42 x %struct.S]* [[ARR]], i32 0, i32 0 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 42 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] @@ -5638,28 +5638,28 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN1]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[VAR1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[VAR1]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY4:%.*]] // CHECK2: arraydestroy.body4: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST5:%.*]] = phi %struct.S* [ [[TMP5]], [[ARRAYDESTROY_DONE2]] ], [ [[ARRAYDESTROY_ELEMENT6:%.*]], [[ARRAYDESTROY_BODY4]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT6]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST5]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT6]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT6]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE7:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT6]], [[ARRAY_BEGIN3]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE7]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY4]] // CHECK2: arraydestroy.done8: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[TEST]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP6]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5676,7 +5676,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5698,7 +5698,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5707,7 +5707,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5715,12 +5715,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S* nonnull align 4 dereferenceable(12) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..23 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[VAR1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(24) [[S_ARR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(12) [[VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(12) [[VAR1:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(24) [[S_ARR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5766,7 +5766,7 @@ int main() { // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK2-NEXT: call void @.omp_initializer..25(i32* noundef [[T_VAR3]], i32* noundef [[TMP0]]) +// CHECK2-NEXT: call void @.omp_initializer..25(i32* [[T_VAR3]], i32* [[TMP0]]) // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR4]] to i8* // CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[TMP8]], i64 4 @@ -5774,10 +5774,10 @@ int main() { // CHECK2-NEXT: [[TMP10:%.*]] = bitcast %struct.S* [[TMP7]] to i8* // CHECK2-NEXT: [[ADD_PTR5:%.*]] = getelementptr inbounds i8, i8* [[TMP10]], i64 4 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8* [[ADD_PTR5]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* noundef [[TMP9]], %struct.BaseS1* noundef [[TMP11]]) +// CHECK2-NEXT: call void @.omp_initializer..5(%struct.BaseS1* [[TMP9]], %struct.BaseS1* [[TMP11]]) // CHECK2-NEXT: store %struct.S* [[VAR4]], %struct.S** [[_TMP6]], align 8 -// CHECK2-NEXT: call void @.omp_initializer..27(%struct.S* noundef [[VAR17]], %struct.S* noundef [[TMP2]]) -// CHECK2-NEXT: call void @.omp_initializer..29(i32* noundef [[T_VAR18]], i32* noundef [[TMP3]]) +// CHECK2-NEXT: call void @.omp_initializer..27(%struct.S* [[VAR17]], %struct.S* [[TMP2]]) +// CHECK2-NEXT: call void @.omp_initializer..29(i32* [[T_VAR18]], i32* [[TMP3]]) // CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -5816,7 +5816,7 @@ int main() { // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP23]] to i64 // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP5]], i64 0, i64 [[IDXPROM10]] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* noundef [[ARRAYIDX11]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[TMP22]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYIDX11]], %struct.S* nonnull align 4 dereferenceable(12) [[TMP22]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -5848,21 +5848,21 @@ int main() { // CHECK2-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK2-NEXT: ] // CHECK2: .omp.reduction.case1: -// CHECK2-NEXT: call void @.omp_combiner..24(i32* noundef [[TMP0]], i32* noundef [[T_VAR3]]) +// CHECK2-NEXT: call void @.omp_combiner..24(i32* [[TMP0]], i32* [[T_VAR3]]) // CHECK2-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP7]] to i8* // CHECK2-NEXT: [[ADD_PTR13:%.*]] = getelementptr inbounds i8, i8* [[TMP35]], i64 4 // CHECK2-NEXT: [[TMP36:%.*]] = bitcast i8* [[ADD_PTR13]] to %struct.BaseS1* // CHECK2-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[VAR4]] to i8* // CHECK2-NEXT: [[ADD_PTR14:%.*]] = getelementptr inbounds i8, i8* [[TMP37]], i64 4 // CHECK2-NEXT: [[TMP38:%.*]] = bitcast i8* [[ADD_PTR14]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP36]], %struct.BaseS1* noundef [[TMP38]]) -// CHECK2-NEXT: call void @.omp_combiner..26(%struct.S* noundef [[TMP2]], %struct.S* noundef [[VAR17]]) -// CHECK2-NEXT: call void @.omp_combiner..28(i32* noundef [[TMP3]], i32* noundef [[T_VAR18]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP36]], %struct.BaseS1* [[TMP38]]) +// CHECK2-NEXT: call void @.omp_combiner..26(%struct.S* [[TMP2]], %struct.S* [[VAR17]]) +// CHECK2-NEXT: call void @.omp_combiner..28(i32* [[TMP3]], i32* [[T_VAR18]]) // CHECK2-NEXT: call void @__kmpc_end_reduce_nowait(%struct.ident_t* @[[GLOB3]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK2: .omp.reduction.case2: // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: call void @.omp_combiner..24(i32* noundef [[TMP0]], i32* noundef [[T_VAR3]]) +// CHECK2-NEXT: call void @.omp_combiner..24(i32* [[TMP0]], i32* [[T_VAR3]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[TMP39:%.*]] = bitcast %struct.S* [[TMP7]] to i8* @@ -5871,23 +5871,23 @@ int main() { // CHECK2-NEXT: [[TMP41:%.*]] = bitcast %struct.S* [[VAR4]] to i8* // CHECK2-NEXT: [[ADD_PTR16:%.*]] = getelementptr inbounds i8, i8* [[TMP41]], i64 4 // CHECK2-NEXT: [[TMP42:%.*]] = bitcast i8* [[ADD_PTR16]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP40]], %struct.BaseS1* noundef [[TMP42]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP40]], %struct.BaseS1* [[TMP42]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: call void @.omp_combiner..26(%struct.S* noundef [[TMP2]], %struct.S* noundef [[VAR17]]) +// CHECK2-NEXT: call void @.omp_combiner..26(%struct.S* [[TMP2]], %struct.S* [[VAR17]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: call void @.omp_combiner..28(i32* noundef [[TMP3]], i32* noundef [[T_VAR18]]) +// CHECK2-NEXT: call void @.omp_combiner..28(i32* [[TMP3]], i32* [[T_VAR18]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK2: .omp.reduction.default: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[VAR17]]) #[[ATTR4]] -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[VAR17]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[VAR4]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_combiner..24 -// CHECK2-SAME: (i32* noalias noundef [[TMP0:%.*]], i32* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[TMP0:%.*]], i32* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32*, align 8 @@ -5902,7 +5902,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_initializer..25 -// CHECK2-SAME: (i32* noalias noundef [[TMP0:%.*]], i32* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[TMP0:%.*]], i32* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32*, align 8 @@ -5915,7 +5915,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_combiner..26 -// CHECK2-SAME: (%struct.S* noalias noundef [[TMP0:%.*]], %struct.S* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (%struct.S* noalias [[TMP0:%.*]], %struct.S* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S*, align 8 @@ -5932,7 +5932,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_initializer..27 -// CHECK2-SAME: (%struct.S* noalias noundef [[TMP0:%.*]], %struct.S* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (%struct.S* noalias [[TMP0:%.*]], %struct.S* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S*, align 8 @@ -5946,12 +5946,12 @@ int main() { // CHECK2-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[TMP2]] to i8* // CHECK2-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP6]], i64 4 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK2-NEXT: call void @_Z5init2R6BaseS1RKS_(%struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP5]], %struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP7]]) +// CHECK2-NEXT: call void @_Z5init2R6BaseS1RKS_(%struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP5]], %struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP7]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_combiner..28 -// CHECK2-SAME: (i32* noalias noundef [[TMP0:%.*]], i32* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[TMP0:%.*]], i32* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32*, align 8 @@ -5966,7 +5966,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_initializer..29 -// CHECK2-SAME: (i32* noalias noundef [[TMP0:%.*]], i32* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[TMP0:%.*]], i32* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32*, align 8 @@ -5981,7 +5981,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.30 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -6015,21 +6015,21 @@ int main() { // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[TMP3]], i64 0, i64 3 // CHECK2-NEXT: [[TMP28:%.*]] = load i8*, i8** [[TMP27]], align 8 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8* [[TMP28]] to i32* -// CHECK2-NEXT: call void @.omp_combiner..24(i32* noundef [[TMP11]], i32* noundef [[TMP8]]) +// CHECK2-NEXT: call void @.omp_combiner..24(i32* [[TMP11]], i32* [[TMP8]]) // CHECK2-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP17]] to i8* // CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[TMP30]], i64 4 // CHECK2-NEXT: [[TMP31:%.*]] = bitcast i8* [[ADD_PTR]] to %struct.BaseS1* // CHECK2-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP14]] to i8* // CHECK2-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP32]], i64 4 // CHECK2-NEXT: [[TMP33:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* noundef [[TMP31]], %struct.BaseS1* noundef [[TMP33]]) -// CHECK2-NEXT: call void @.omp_combiner..26(%struct.S* noundef [[TMP23]], %struct.S* noundef [[TMP20]]) -// CHECK2-NEXT: call void @.omp_combiner..28(i32* noundef [[TMP29]], i32* noundef [[TMP26]]) +// CHECK2-NEXT: call void @.omp_combiner..4(%struct.BaseS1* [[TMP31]], %struct.BaseS1* [[TMP33]]) +// CHECK2-NEXT: call void @.omp_combiner..26(%struct.S* [[TMP23]], %struct.S* [[TMP20]]) +// CHECK2-NEXT: call void @.omp_combiner..28(i32* [[TMP29]], i32* [[TMP26]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..31 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(24) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[VAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(24) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(12) [[VAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6103,7 +6103,7 @@ int main() { // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i64 0, i64 [[IDXPROM5]] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* noundef [[ARRAYIDX6]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[TMP16]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYIDX6]], %struct.S* nonnull align 4 dereferenceable(12) [[TMP16]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -6126,12 +6126,12 @@ int main() { // CHECK2-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK2-NEXT: ] // CHECK2: .omp.reduction.case1: -// CHECK2-NEXT: call void @.omp_combiner..34(i32* noundef [[TMP0]], i32* noundef [[T_VAR3]]) +// CHECK2-NEXT: call void @.omp_combiner..34(i32* [[TMP0]], i32* [[T_VAR3]]) // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK2: .omp.reduction.case2: // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: call void @.omp_combiner..34(i32* noundef [[TMP0]], i32* noundef [[T_VAR3]]) +// CHECK2-NEXT: call void @.omp_combiner..34(i32* [[TMP0]], i32* [[T_VAR3]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] @@ -6141,7 +6141,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.33 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -6157,12 +6157,12 @@ int main() { // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 // CHECK2-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* -// CHECK2-NEXT: call void @.omp_combiner..34(i32* noundef [[TMP11]], i32* noundef [[TMP8]]) +// CHECK2-NEXT: call void @.omp_combiner..34(i32* [[TMP11]], i32* [[TMP8]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_combiner..34 -// CHECK2-SAME: (i32* noalias noundef [[TMP0:%.*]], i32* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[TMP0:%.*]], i32* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32*, align 8 @@ -6177,7 +6177,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..35 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [42 x %struct.S]* noundef nonnull align 4 dereferenceable(504) [[ARR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(24) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[VAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [42 x %struct.S]* nonnull align 4 dereferenceable(504) [[ARR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(24) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(12) [[VAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6231,7 +6231,7 @@ int main() { // CHECK2-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK2-NEXT: [[ADD_PTR5:%.*]] = getelementptr inbounds i8, i8* [[TMP9]], i64 4 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8* [[ADD_PTR5]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_initializer..37(%struct.BaseS1* noundef [[TMP8]], %struct.BaseS1* noundef [[TMP10]]) +// CHECK2-NEXT: call void @.omp_initializer..37(%struct.BaseS1* [[TMP8]], %struct.BaseS1* [[TMP10]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT6]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT6]], [[TMP6]] @@ -6284,7 +6284,7 @@ int main() { // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP30]] to i64 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP3]], i64 0, i64 [[IDXPROM9]] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* noundef [[ARRAYIDX10]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[TMP29]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYIDX10]], %struct.S* nonnull align 4 dereferenceable(12) [[TMP29]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -6323,7 +6323,7 @@ int main() { // CHECK2-NEXT: [[TMP43:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST12]] to i8* // CHECK2-NEXT: [[ADD_PTR15:%.*]] = getelementptr inbounds i8, i8* [[TMP43]], i64 4 // CHECK2-NEXT: [[TMP44:%.*]] = bitcast i8* [[ADD_PTR15]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..36(%struct.BaseS1* noundef [[TMP42]], %struct.BaseS1* noundef [[TMP44]]) +// CHECK2-NEXT: call void @.omp_combiner..36(%struct.BaseS1* [[TMP42]], %struct.BaseS1* [[TMP44]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT16]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST13]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST12]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE17:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT16]], [[TMP40]] @@ -6347,7 +6347,7 @@ int main() { // CHECK2-NEXT: [[TMP50:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST21]] to i8* // CHECK2-NEXT: [[ADD_PTR24:%.*]] = getelementptr inbounds i8, i8* [[TMP50]], i64 4 // CHECK2-NEXT: [[TMP51:%.*]] = bitcast i8* [[ADD_PTR24]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..36(%struct.BaseS1* noundef [[TMP49]], %struct.BaseS1* noundef [[TMP51]]) +// CHECK2-NEXT: call void @.omp_combiner..36(%struct.BaseS1* [[TMP49]], %struct.BaseS1* [[TMP51]]) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP47]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT25]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST22]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT26]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST21]], i32 1 @@ -6363,7 +6363,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP52]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN29]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE30:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done30: @@ -6374,7 +6374,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_combiner..36 -// CHECK2-SAME: (%struct.BaseS1* noalias noundef [[TMP0:%.*]], %struct.BaseS1* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (%struct.BaseS1* noalias [[TMP0:%.*]], %struct.BaseS1* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.BaseS1*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.BaseS1*, align 8 @@ -6382,12 +6382,12 @@ int main() { // CHECK2-NEXT: store %struct.BaseS1* [[TMP1]], %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR]], align 8 -// CHECK2-NEXT: call void @_Z8red_plusR6BaseS1RKS_(%struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP2]]) +// CHECK2-NEXT: call void @_Z8red_plusR6BaseS1RKS_(%struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_initializer..37 -// CHECK2-SAME: (%struct.BaseS1* noalias noundef [[TMP0:%.*]], %struct.BaseS1* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (%struct.BaseS1* noalias [[TMP0:%.*]], %struct.BaseS1* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.BaseS1*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.BaseS1*, align 8 @@ -6395,12 +6395,12 @@ int main() { // CHECK2-NEXT: store %struct.BaseS1* [[TMP1]], %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR1]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.BaseS1*, %struct.BaseS1** [[DOTADDR]], align 8 -// CHECK2-NEXT: call void @_Z9init_plusR6BaseS1RKS_(%struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* noundef nonnull align 4 dereferenceable(4) [[TMP2]]) +// CHECK2-NEXT: call void @_Z9init_plusR6BaseS1RKS_(%struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.BaseS1* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.38 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR8]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR8]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -6428,7 +6428,7 @@ int main() { // CHECK2-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* // CHECK2-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[TMP15]], i64 4 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8* [[ADD_PTR2]] to %struct.BaseS1* -// CHECK2-NEXT: call void @.omp_combiner..36(%struct.BaseS1* noundef [[TMP14]], %struct.BaseS1* noundef [[TMP16]]) +// CHECK2-NEXT: call void @.omp_combiner..36(%struct.BaseS1* [[TMP14]], %struct.BaseS1* [[TMP16]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] @@ -6438,7 +6438,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6467,9 +6467,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[S]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S]]) // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: call void @.omp_initializer.(%struct.S* noundef [[S1]], %struct.S* noundef [[S]]) +// CHECK3-NEXT: call void @.omp_initializer.(%struct.S* [[S1]], %struct.S* [[S]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 @@ -6492,24 +6492,24 @@ int main() { // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: store i32 10, i32* [[I]], align 4 -// CHECK3-NEXT: call void @.omp_combiner.(%struct.S* noundef [[S]], %struct.S* noundef [[S1]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[S1]]) #[[ATTR7:[0-9]+]] -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[S]]) #[[ATTR7]] +// CHECK3-NEXT: call void @.omp_combiner.(%struct.S* [[S]], %struct.S* [[S1]]) +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S1]]) #[[ATTR7:[0-9]+]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S]]) #[[ATTR7]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S* nonnull align 4 dereferenceable(12) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@.omp_combiner. -// CHECK3-SAME: (%struct.S* noalias noundef [[TMP0:%.*]], %struct.S* noalias noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (%struct.S* noalias [[TMP0:%.*]], %struct.S* noalias [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S*, align 8 @@ -6526,7 +6526,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_initializer. -// CHECK3-SAME: (%struct.S* noalias noundef [[TMP0:%.*]], %struct.S* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (%struct.S* noalias [[TMP0:%.*]], %struct.S* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S*, align 8 @@ -6534,17 +6534,17 @@ int main() { // CHECK3-NEXT: store %struct.S* [[TMP1]], %struct.S** [[DOTADDR1]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[DOTADDR1]], align 8 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[DOTADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[TMP3]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[TMP3]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR7]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S* nonnull align 4 dereferenceable(12) [[THIS1]]) #[[ATTR7]] // CHECK3-NEXT: ret void // // @@ -6579,38 +6579,38 @@ int main() { // CHECK3-NEXT: [[_TMP61:%.*]] = alloca [4 x %struct.S.0]*, align 8 // CHECK3-NEXT: [[I62:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[TEST]]) // CHECK3-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [4 x %struct.S.0], [4 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_ELEMENT]], i64 1 -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_ELEMENT1]], float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT1]], float 3.000000e+00) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_ELEMENT1]], i64 1 -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_ELEMENT2]], float noundef 4.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT2]], float 4.000000e+00) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[VAR1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[VAR1]]) // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [4 x %struct.S.0]], [10 x [4 x %struct.S.0]]* [[ARRS]], i32 0, i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 40 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef %struct.S.0** @_Z3foov() +// CHECK3-NEXT: [[CALL:%.*]] = call %struct.S.0** @_Z3foov() // CHECK3-NEXT: store %struct.S.0** [[CALL]], %struct.S.0*** [[VAR2]], align 8 // CHECK3-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [5 x %struct.S.0], [5 x %struct.S.0]* [[VVAR2]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN3]], i64 5 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP5:%.*]] // CHECK3: arrayctor.loop5: // CHECK3-NEXT: [[ARRAYCTOR_CUR6:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYCTOR_NEXT7:%.*]], [[ARRAYCTOR_LOOP5]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR6]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYCTOR_CUR6]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT7]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR6]], i64 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE8:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT7]], [[ARRAYCTOR_END4]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE8]], label [[ARRAYCTOR_CONT9:%.*]], label [[ARRAYCTOR_LOOP5]] @@ -6637,7 +6637,7 @@ int main() { // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP7]] to i64 // CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [4 x %struct.S.0], [4 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM11]] -// CHECK3-NEXT: [[CALL13:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S.0* @_ZN1SIfEaSERKS0_(%struct.S.0* noundef [[ARRAYIDX12]], %struct.S.0* noundef nonnull align 4 dereferenceable(12) [[TMP6]]) +// CHECK3-NEXT: [[CALL13:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S.0* @_ZN1SIfEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYIDX12]], %struct.S.0* nonnull align 4 dereferenceable(12) [[TMP6]]) // CHECK3-NEXT: br label [[FOR_INC:%.*]] // CHECK3: for.inc: // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 @@ -6761,7 +6761,7 @@ int main() { // CHECK3-NEXT: store i32 [[INC67]], i32* [[I62]], align 4 // CHECK3-NEXT: br label [[FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK3: for.end68: -// CHECK3-NEXT: [[CALL69:%.*]] = call noundef i32 @_Z5tmainIiLi42EET_v() +// CHECK3-NEXT: [[CALL69:%.*]] = call i32 @_Z5tmainIiLi42EET_v() // CHECK3-NEXT: store i32 [[CALL69]], i32* [[RETVAL]], align 4 // CHECK3-NEXT: [[TMP35:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP35]]) @@ -6771,7 +6771,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[FOR_END68]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR7]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR7]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN70]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE71:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done71: @@ -6781,38 +6781,38 @@ int main() { // CHECK3: arraydestroy.body73: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST74:%.*]] = phi %struct.S.0* [ [[TMP37]], [[ARRAYDESTROY_DONE71]] ], [ [[ARRAYDESTROY_ELEMENT75:%.*]], [[ARRAYDESTROY_BODY73]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT75]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST74]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT75]]) #[[ATTR7]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT75]]) #[[ATTR7]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE76:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT75]], [[ARRAY_BEGIN72]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE76]], label [[ARRAYDESTROY_DONE77:%.*]], label [[ARRAYDESTROY_BODY73]] // CHECK3: arraydestroy.done77: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[VAR1]]) #[[ATTR7]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[VAR1]]) #[[ATTR7]] // CHECK3-NEXT: [[ARRAY_BEGIN78:%.*]] = getelementptr inbounds [4 x %struct.S.0], [4 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN78]], i64 4 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY79:%.*]] // CHECK3: arraydestroy.body79: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST80:%.*]] = phi %struct.S.0* [ [[TMP38]], [[ARRAYDESTROY_DONE77]] ], [ [[ARRAYDESTROY_ELEMENT81:%.*]], [[ARRAYDESTROY_BODY79]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT81]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST80]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT81]]) #[[ATTR7]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT81]]) #[[ATTR7]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE82:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT81]], [[ARRAY_BEGIN78]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE82]], label [[ARRAYDESTROY_DONE83:%.*]], label [[ARRAYDESTROY_BODY79]] // CHECK3: arraydestroy.done83: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR7]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[TEST]]) #[[ATTR7]] // CHECK3-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP39]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6820,7 +6820,7 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S.0* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // @@ -6846,22 +6846,22 @@ int main() { // CHECK3-NEXT: [[_TMP18:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[_TMP19:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[I20:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiLi42EET_v.vec to i8*), i64 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[VAR1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[VAR1]]) // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [42 x %struct.S], [42 x %struct.S]* [[ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 42 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] @@ -6886,7 +6886,7 @@ int main() { // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 // CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK3-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* noundef [[ARRAYIDX3]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[TMP6]]) +// CHECK3-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYIDX3]], %struct.S* nonnull align 4 dereferenceable(12) [[TMP6]]) // CHECK3-NEXT: br label [[FOR_INC:%.*]] // CHECK3: for.inc: // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 @@ -6914,7 +6914,7 @@ int main() { // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I6]], align 4 // CHECK3-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP15]] to i64 // CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM12]] -// CHECK3-NEXT: [[CALL14:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* noundef [[ARRAYIDX13]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[TMP14]]) +// CHECK3-NEXT: [[CALL14:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYIDX13]], %struct.S* nonnull align 4 dereferenceable(12) [[TMP14]]) // CHECK3-NEXT: br label [[FOR_INC15:%.*]] // CHECK3: for.inc15: // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I6]], align 4 @@ -6942,7 +6942,7 @@ int main() { // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[I20]], align 4 // CHECK3-NEXT: [[IDXPROM26:%.*]] = sext i32 [[TMP23]] to i64 // CHECK3-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM26]] -// CHECK3-NEXT: [[CALL28:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* noundef [[ARRAYIDX27]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[TMP22]]) +// CHECK3-NEXT: [[CALL28:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYIDX27]], %struct.S* nonnull align 4 dereferenceable(12) [[TMP22]]) // CHECK3-NEXT: br label [[FOR_INC29:%.*]] // CHECK3: for.inc29: // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[I20]], align 4 @@ -6957,38 +6957,38 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[FOR_END31]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR7]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR7]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN32]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE33:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done33: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[VAR1]]) #[[ATTR7]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[VAR1]]) #[[ATTR7]] // CHECK3-NEXT: [[ARRAY_BEGIN34:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN34]], i64 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY35:%.*]] // CHECK3: arraydestroy.body35: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST36:%.*]] = phi %struct.S* [ [[TMP26]], [[ARRAYDESTROY_DONE33]] ], [ [[ARRAYDESTROY_ELEMENT37:%.*]], [[ARRAYDESTROY_BODY35]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT37]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST36]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT37]]) #[[ATTR7]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT37]]) #[[ATTR7]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE38:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT37]], [[ARRAY_BEGIN34]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE38]], label [[ARRAYDESTROY_DONE39:%.*]], label [[ARRAYDESTROY_BODY35]] // CHECK3: arraydestroy.done39: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR7]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[TEST]]) #[[ATTR7]] // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP27]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR7]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS1]]) #[[ATTR7]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -7005,7 +7005,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -7014,7 +7014,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -7031,7 +7031,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -7040,7 +7040,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -7062,7 +7062,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7070,12 +7070,12 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S* nonnull align 4 dereferenceable(12) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7104,9 +7104,9 @@ int main() { // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[S]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S]]) // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 -// CHECK4-NEXT: call void @.omp_initializer.(%struct.S* noundef [[S1]], %struct.S* noundef [[S]]) +// CHECK4-NEXT: call void @.omp_initializer.(%struct.S* [[S1]], %struct.S* [[S]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 @@ -7129,24 +7129,24 @@ int main() { // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: store i32 10, i32* [[I]], align 4 -// CHECK4-NEXT: call void @.omp_combiner.(%struct.S* noundef [[S]], %struct.S* noundef [[S1]]) -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[S1]]) #[[ATTR7:[0-9]+]] -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[S]]) #[[ATTR7]] +// CHECK4-NEXT: call void @.omp_combiner.(%struct.S* [[S]], %struct.S* [[S1]]) +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S1]]) #[[ATTR7:[0-9]+]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S]]) #[[ATTR7]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S* nonnull align 4 dereferenceable(12) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@.omp_combiner. -// CHECK4-SAME: (%struct.S* noalias noundef [[TMP0:%.*]], %struct.S* noalias noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (%struct.S* noalias [[TMP0:%.*]], %struct.S* noalias [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S*, align 8 @@ -7163,7 +7163,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_initializer. -// CHECK4-SAME: (%struct.S* noalias noundef [[TMP0:%.*]], %struct.S* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (%struct.S* noalias [[TMP0:%.*]], %struct.S* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S*, align 8 @@ -7171,17 +7171,17 @@ int main() { // CHECK4-NEXT: store %struct.S* [[TMP1]], %struct.S** [[DOTADDR1]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[DOTADDR1]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[DOTADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[TMP3]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[TMP3]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR7]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S* nonnull align 4 dereferenceable(12) [[THIS1]]) #[[ATTR7]] // CHECK4-NEXT: ret void // // @@ -7216,38 +7216,38 @@ int main() { // CHECK4-NEXT: [[_TMP61:%.*]] = alloca [4 x %struct.S.0]*, align 8 // CHECK4-NEXT: [[I62:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[TEST]]) // CHECK4-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [4 x %struct.S.0], [4 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_ELEMENT]], i64 1 -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_ELEMENT1]], float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT1]], float 3.000000e+00) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_ELEMENT1]], i64 1 -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* noundef [[ARRAYINIT_ELEMENT2]], float noundef 4.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT2]], float 4.000000e+00) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[VAR1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[VAR1]]) // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [4 x %struct.S.0]], [10 x [4 x %struct.S.0]]* [[ARRS]], i32 0, i32 0, i32 0 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 40 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef %struct.S.0** @_Z3foov() +// CHECK4-NEXT: [[CALL:%.*]] = call %struct.S.0** @_Z3foov() // CHECK4-NEXT: store %struct.S.0** [[CALL]], %struct.S.0*** [[VAR2]], align 8 // CHECK4-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [5 x %struct.S.0], [5 x %struct.S.0]* [[VVAR2]], i32 0, i32 0 // CHECK4-NEXT: [[ARRAYCTOR_END4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN3]], i64 5 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP5:%.*]] // CHECK4: arrayctor.loop5: // CHECK4-NEXT: [[ARRAYCTOR_CUR6:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYCTOR_NEXT7:%.*]], [[ARRAYCTOR_LOOP5]] ] -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR6]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYCTOR_CUR6]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT7]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR6]], i64 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE8:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT7]], [[ARRAYCTOR_END4]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE8]], label [[ARRAYCTOR_CONT9:%.*]], label [[ARRAYCTOR_LOOP5]] @@ -7274,7 +7274,7 @@ int main() { // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP7]] to i64 // CHECK4-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [4 x %struct.S.0], [4 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM11]] -// CHECK4-NEXT: [[CALL13:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S.0* @_ZN1SIfEaSERKS0_(%struct.S.0* noundef [[ARRAYIDX12]], %struct.S.0* noundef nonnull align 4 dereferenceable(12) [[TMP6]]) +// CHECK4-NEXT: [[CALL13:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S.0* @_ZN1SIfEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYIDX12]], %struct.S.0* nonnull align 4 dereferenceable(12) [[TMP6]]) // CHECK4-NEXT: br label [[FOR_INC:%.*]] // CHECK4: for.inc: // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 @@ -7398,7 +7398,7 @@ int main() { // CHECK4-NEXT: store i32 [[INC67]], i32* [[I62]], align 4 // CHECK4-NEXT: br label [[FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK4: for.end68: -// CHECK4-NEXT: [[CALL69:%.*]] = call noundef i32 @_Z5tmainIiLi42EET_v() +// CHECK4-NEXT: [[CALL69:%.*]] = call i32 @_Z5tmainIiLi42EET_v() // CHECK4-NEXT: store i32 [[CALL69]], i32* [[RETVAL]], align 4 // CHECK4-NEXT: [[TMP35:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP35]]) @@ -7408,7 +7408,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[FOR_END68]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR7]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR7]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN70]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE71:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done71: @@ -7418,38 +7418,38 @@ int main() { // CHECK4: arraydestroy.body73: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST74:%.*]] = phi %struct.S.0* [ [[TMP37]], [[ARRAYDESTROY_DONE71]] ], [ [[ARRAYDESTROY_ELEMENT75:%.*]], [[ARRAYDESTROY_BODY73]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT75]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST74]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT75]]) #[[ATTR7]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT75]]) #[[ATTR7]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE76:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT75]], [[ARRAY_BEGIN72]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE76]], label [[ARRAYDESTROY_DONE77:%.*]], label [[ARRAYDESTROY_BODY73]] // CHECK4: arraydestroy.done77: -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[VAR1]]) #[[ATTR7]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[VAR1]]) #[[ATTR7]] // CHECK4-NEXT: [[ARRAY_BEGIN78:%.*]] = getelementptr inbounds [4 x %struct.S.0], [4 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN78]], i64 4 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY79:%.*]] // CHECK4: arraydestroy.body79: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST80:%.*]] = phi %struct.S.0* [ [[TMP38]], [[ARRAYDESTROY_DONE77]] ], [ [[ARRAYDESTROY_ELEMENT81:%.*]], [[ARRAYDESTROY_BODY79]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT81]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST80]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT81]]) #[[ATTR7]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT81]]) #[[ATTR7]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE82:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT81]], [[ARRAY_BEGIN78]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE82]], label [[ARRAYDESTROY_DONE83:%.*]], label [[ARRAYDESTROY_BODY79]] // CHECK4: arraydestroy.done83: -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR7]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[TEST]]) #[[ATTR7]] // CHECK4-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP39]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -7457,7 +7457,7 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S.0* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // @@ -7483,22 +7483,22 @@ int main() { // CHECK4-NEXT: [[_TMP18:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[_TMP19:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[I20:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiLi42EET_v.vec to i8*), i64 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[VAR1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[VAR1]]) // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [42 x %struct.S], [42 x %struct.S]* [[ARR]], i32 0, i32 0 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 42 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] @@ -7523,7 +7523,7 @@ int main() { // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP7]] to i64 // CHECK4-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] -// CHECK4-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* noundef [[ARRAYIDX3]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[TMP6]]) +// CHECK4-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYIDX3]], %struct.S* nonnull align 4 dereferenceable(12) [[TMP6]]) // CHECK4-NEXT: br label [[FOR_INC:%.*]] // CHECK4: for.inc: // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 @@ -7551,7 +7551,7 @@ int main() { // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[I6]], align 4 // CHECK4-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP15]] to i64 // CHECK4-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM12]] -// CHECK4-NEXT: [[CALL14:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* noundef [[ARRAYIDX13]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[TMP14]]) +// CHECK4-NEXT: [[CALL14:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYIDX13]], %struct.S* nonnull align 4 dereferenceable(12) [[TMP14]]) // CHECK4-NEXT: br label [[FOR_INC15:%.*]] // CHECK4: for.inc15: // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I6]], align 4 @@ -7579,7 +7579,7 @@ int main() { // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[I20]], align 4 // CHECK4-NEXT: [[IDXPROM26:%.*]] = sext i32 [[TMP23]] to i64 // CHECK4-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM26]] -// CHECK4-NEXT: [[CALL28:%.*]] = call noundef nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* noundef [[ARRAYIDX27]], %struct.S* noundef nonnull align 4 dereferenceable(12) [[TMP22]]) +// CHECK4-NEXT: [[CALL28:%.*]] = call nonnull align 4 dereferenceable(12) %struct.S* @_ZN1SIiEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYIDX27]], %struct.S* nonnull align 4 dereferenceable(12) [[TMP22]]) // CHECK4-NEXT: br label [[FOR_INC29:%.*]] // CHECK4: for.inc29: // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[I20]], align 4 @@ -7594,38 +7594,38 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[FOR_END31]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR7]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR7]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN32]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE33:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done33: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[VAR1]]) #[[ATTR7]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[VAR1]]) #[[ATTR7]] // CHECK4-NEXT: [[ARRAY_BEGIN34:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN34]], i64 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY35:%.*]] // CHECK4: arraydestroy.body35: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST36:%.*]] = phi %struct.S* [ [[TMP26]], [[ARRAYDESTROY_DONE33]] ], [ [[ARRAYDESTROY_ELEMENT37:%.*]], [[ARRAYDESTROY_BODY35]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT37]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST36]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT37]]) #[[ATTR7]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT37]]) #[[ATTR7]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE38:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT37]], [[ARRAY_BEGIN34]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE38]], label [[ARRAYDESTROY_DONE39:%.*]], label [[ARRAYDESTROY_BODY35]] // CHECK4: arraydestroy.done39: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR7]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[TEST]]) #[[ATTR7]] // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP27]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR7]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS1]]) #[[ATTR7]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -7642,7 +7642,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -7651,7 +7651,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -7668,7 +7668,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -7677,7 +7677,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(12) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -7699,7 +7699,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7707,12 +7707,12 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S* nonnull align 4 dereferenceable(12) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/for_reduction_task_codegen.cpp b/clang/test/OpenMP/for_reduction_task_codegen.cpp index 7fc4b8fedeef45e4e55591866db2f0c29046defb..9084fd57b605bc0850f142a844fc5150e959fa23 100644 --- a/clang/test/OpenMP/for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/for_reduction_task_codegen.cpp @@ -37,7 +37,7 @@ int main(int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -48,7 +48,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -334,7 +334,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init. -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -347,7 +347,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -365,7 +365,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -387,7 +387,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -418,7 +418,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -432,7 +432,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -516,7 +516,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -565,7 +565,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -576,7 +576,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -862,7 +862,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init. -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -875,7 +875,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -893,7 +893,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -915,7 +915,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -946,7 +946,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -960,7 +960,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1044,7 +1044,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 diff --git a/clang/test/OpenMP/for_scan_codegen.cpp b/clang/test/OpenMP/for_scan_codegen.cpp index 56cfd614c859b76f9e34ff47c4675e3b79ff57bd..54d4632f666c663eeb85a97307bccc77f3f30f1e 100644 --- a/clang/test/OpenMP/for_scan_codegen.cpp +++ b/clang/test/OpenMP/for_scan_codegen.cpp @@ -13,7 +13,7 @@ void foo(); void bar(); -// CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 noundef %n) +// CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 %n) void baz(int n) { static float a[10]; static double b; diff --git a/clang/test/OpenMP/for_simd_codegen.cpp b/clang/test/OpenMP/for_simd_codegen.cpp index 9639c1945f616819254a339d69bbb11701e88ba2..f4b2bc93b208bacb27ba8c9e5d088cd1a4ab358e 100644 --- a/clang/test/OpenMP/for_simd_codegen.cpp +++ b/clang/test/OpenMP/for_simd_codegen.cpp @@ -23,7 +23,7 @@ long long get_val() { extern void mayThrow(); mayThrow(); return 0; } double *g_ptr; -// CHECK-LABEL: define {{.*void}} @{{.*}}simple{{.*}}(float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}) +// CHECK-LABEL: define {{.*void}} @{{.*}}simple{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) void simple(float *a, float *b, float *c, float *d) { #ifdef OMP5 #pragma omp for simd if (true) @@ -438,7 +438,7 @@ int templ1(T a, T *z) { } // Instatiation templ1 -// CHECK-LABEL: define {{.*i32}} @{{.*}}templ1{{.*}}(float noundef {{.+}}, float* noundef {{.+}}) +// CHECK-LABEL: define {{.*i32}} @{{.*}}templ1{{.*}}(float {{.+}}, float* {{.+}}) // CHECK: call void @__kmpc_for_static_init_8(%struct.ident_t* {{[^,]+}}, i32 %{{[^,]+}}, i32 45, i32* %{{[^,]+}}, i64* [[LB:%[^,]+]], i64* [[UB:%[^,]+]], i64* [[STRIDE:%[^,]+]], i64 1, i64 2) // CHECK: [[UB_VAL:%.+]] = load i64, i64* [[UB]], // CHECK: [[CMP:%.+]] = icmp sgt i64 [[UB_VAL]], 15 @@ -792,7 +792,7 @@ void parallel_simd(float *a) { #pragma omp parallel #pragma omp for simd // TERM_DEBUG-NOT: __kmpc_global_thread_num - // TERM_DEBUG: invoke noundef i32 {{.*}}bar{{.*}}() + // TERM_DEBUG: invoke i32 {{.*}}bar{{.*}}() // TERM_DEBUG: unwind label %[[TERM_LPAD:[a-zA-Z0-9\.]+]], // TERM_DEBUG-NOT: __kmpc_global_thread_num // TERM_DEBUG: [[TERM_LPAD]] diff --git a/clang/test/OpenMP/for_simd_scan_codegen.cpp b/clang/test/OpenMP/for_simd_scan_codegen.cpp index b5b8f0081af22c330ef2d1166996bdb405374b35..2440342f6719c64726c43dc5b047140110b52724 100644 --- a/clang/test/OpenMP/for_simd_scan_codegen.cpp +++ b/clang/test/OpenMP/for_simd_scan_codegen.cpp @@ -13,7 +13,7 @@ void foo(); void bar(); -// CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 noundef %n) +// CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 %n) void baz(int n) { static float a[10]; static double b; diff --git a/clang/test/OpenMP/function-attr.cpp b/clang/test/OpenMP/function-attr.cpp index 0744538f8657fc87126399cd35ce14f4c8d8c398..676c71b337269a7298557ee602567403292b136b 100644 --- a/clang/test/OpenMP/function-attr.cpp +++ b/clang/test/OpenMP/function-attr.cpp @@ -14,7 +14,7 @@ struct S { ~S() {} }; -// CHECK: define internal void @.omp.copyprivate.copy_func(i8* noundef %0, i8* noundef %1) [[ATTR0:#[0-9]+]] { +// CHECK: define internal void @.omp.copyprivate.copy_func(i8* %0, i8* %1) [[ATTR0:#[0-9]+]] { void foo0(); @@ -30,8 +30,8 @@ int foo1() { } // CHECK: define internal void @.omp_task_privates_map.({{.*}}) [[ATTR3:#[0-9]+]] { -// CHECK: define internal noundef i32 @.omp_task_entry.({{.*}}) [[ATTR0]] { -// CHECK: define internal noundef i32 @.omp_task_destructor.({{.*}}) [[ATTR0]] { +// CHECK: define internal i32 @.omp_task_entry.({{.*}}) [[ATTR0]] { +// CHECK: define internal i32 @.omp_task_destructor.({{.*}}) [[ATTR0]] { int foo2() { S s_arr[] = {1, 2}; @@ -41,7 +41,7 @@ int foo2() { return 0; } -// CHECK: define internal void @.omp.reduction.reduction_func(i8* noundef %0, i8* noundef %1) [[ATTR0]] { +// CHECK: define internal void @.omp.reduction.reduction_func(i8* %0, i8* %1) [[ATTR0]] { float foo3(int n, float *a, float *b) { int i; diff --git a/clang/test/OpenMP/irbuilder_for_iterator.cpp b/clang/test/OpenMP/irbuilder_for_iterator.cpp index 36b1bc47afae9c93a59305c40e0aa192528a233d..c9e5192a70a698503d9f0b26563997b135fef5dc 100644 --- a/clang/test/OpenMP/irbuilder_for_iterator.cpp +++ b/clang/test/OpenMP/irbuilder_for_iterator.cpp @@ -28,7 +28,7 @@ extern "C" void workshareloop_iterator(float *a, float *b, float *c) { #endif // HEADER // CHECK-LABEL: define {{[^@]+}}@workshareloop_iterator -// CHECK-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -45,11 +45,11 @@ extern "C" void workshareloop_iterator(float *a, float *b, float *c) { // CHECK-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 // CHECK-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 // CHECK-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN10MyIteratorC1Ej(%struct.MyIterator* noundef [[IT]], i32 noundef 7) +// CHECK-NEXT: call void @_ZN10MyIteratorC1Ej(%struct.MyIterator* nonnull align 1 dereferenceable(1) [[IT]], i32 7) // CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 // CHECK-NEXT: store %struct.MyIterator* [[IT]], %struct.MyIterator** [[TMP0]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[AGG_CAPTURED1]], i32 0, i32 0 -// CHECK-NEXT: call void @_ZN10MyIteratorC1ERKS_(%struct.MyIterator* noundef [[TMP1]], %struct.MyIterator* noundef nonnull align 1 dereferenceable(1) [[IT]]) +// CHECK-NEXT: call void @_ZN10MyIteratorC1ERKS_(%struct.MyIterator* nonnull align 1 dereferenceable(1) [[TMP1]], %struct.MyIterator* nonnull align 1 dereferenceable(1) [[IT]]) // CHECK-NEXT: call void @__captured_stmt(i64* [[DOTCOUNT_ADDR]], %struct.anon* [[AGG_CAPTURED]]) // CHECK-NEXT: [[DOTCOUNT:%.*]] = load i64, i64* [[DOTCOUNT_ADDR]], align 8 // CHECK-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]] @@ -74,7 +74,7 @@ extern "C" void workshareloop_iterator(float *a, float *b, float *c) { // CHECK: omp_loop.body: // CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OMP_LOOP_IV]], [[TMP3]] // CHECK-NEXT: call void @__captured_stmt.1(%struct.MyIterator* [[IT]], i64 [[TMP7]], %struct.anon.0* [[AGG_CAPTURED1]]) -// CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_ZNK10MyIteratordeEv(%struct.MyIterator* noundef [[IT]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32 @_ZNK10MyIteratordeEv(%struct.MyIterator* nonnull align 1 dereferenceable(1) [[IT]]) // CHECK-NEXT: store i32 [[CALL]], i32* [[I]], align 4 // CHECK-NEXT: [[TMP8:%.*]] = load float*, float** [[B_ADDR]], align 8 // CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 @@ -106,7 +106,7 @@ extern "C" void workshareloop_iterator(float *a, float *b, float *c) { // // // CHECK-LABEL: define {{[^@]+}}@__captured_stmt -// CHECK-SAME: (i64* noundef nonnull align 8 dereferenceable(8) [[DISTANCE:%.*]], %struct.anon* noalias noundef [[__CONTEXT:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK-SAME: (i64* nonnull align 8 dereferenceable(8) [[DISTANCE:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DISTANCE_ADDR:%.*]] = alloca i64*, align 8 // CHECK-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 @@ -118,21 +118,21 @@ extern "C" void workshareloop_iterator(float *a, float *b, float *c) { // CHECK-NEXT: [[TMP0:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP0]], i32 0, i32 0 // CHECK-NEXT: [[TMP2:%.*]] = load %struct.MyIterator*, %struct.MyIterator** [[TMP1]], align 8 -// CHECK-NEXT: call void @_ZN10MyIteratorC1ERKS_(%struct.MyIterator* noundef [[DOTSTART]], %struct.MyIterator* noundef nonnull align 1 dereferenceable(1) [[TMP2]]) -// CHECK-NEXT: call void @_ZN10MyIteratorC1Ej(%struct.MyIterator* noundef [[DOTSTOP]], i32 noundef 41) +// CHECK-NEXT: call void @_ZN10MyIteratorC1ERKS_(%struct.MyIterator* nonnull align 1 dereferenceable(1) [[DOTSTART]], %struct.MyIterator* nonnull align 1 dereferenceable(1) [[TMP2]]) +// CHECK-NEXT: call void @_ZN10MyIteratorC1Ej(%struct.MyIterator* nonnull align 1 dereferenceable(1) [[DOTSTOP]], i32 41) // CHECK-NEXT: store i64 1, i64* [[DOTSTEP]], align 8 // CHECK-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTSTEP]], align 8 // CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP3]], 0 // CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK: cond.true: -// CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_ZNK10MyIteratormiERKS_(%struct.MyIterator* noundef [[DOTSTART]], %struct.MyIterator* noundef nonnull align 1 dereferenceable(1) [[DOTSTOP]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32 @_ZNK10MyIteratormiERKS_(%struct.MyIterator* nonnull align 1 dereferenceable(1) [[DOTSTART]], %struct.MyIterator* nonnull align 1 dereferenceable(1) [[DOTSTOP]]) // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64 // CHECK-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTSTEP]], align 8 // CHECK-NEXT: [[SUB:%.*]] = sub i64 0, [[TMP4]] // CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[CONV]], [[SUB]] // CHECK-NEXT: br label [[COND_END:%.*]] // CHECK: cond.false: -// CHECK-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZNK10MyIteratormiERKS_(%struct.MyIterator* noundef [[DOTSTOP]], %struct.MyIterator* noundef nonnull align 1 dereferenceable(1) [[DOTSTART]]) +// CHECK-NEXT: [[CALL1:%.*]] = call i32 @_ZNK10MyIteratormiERKS_(%struct.MyIterator* nonnull align 1 dereferenceable(1) [[DOTSTOP]], %struct.MyIterator* nonnull align 1 dereferenceable(1) [[DOTSTART]]) // CHECK-NEXT: [[CONV2:%.*]] = sext i32 [[CALL1]] to i64 // CHECK-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTSTEP]], align 8 // CHECK-NEXT: [[DIV3:%.*]] = udiv i64 [[CONV2]], [[TMP5]] @@ -145,7 +145,7 @@ extern "C" void workshareloop_iterator(float *a, float *b, float *c) { // // // CHECK-LABEL: define {{[^@]+}}@__captured_stmt.1 -// CHECK-SAME: (%struct.MyIterator* noundef nonnull align 1 dereferenceable(1) [[LOOPVAR:%.*]], i64 noundef [[LOGICAL:%.*]], %struct.anon.0* noalias noundef [[__CONTEXT:%.*]]) #[[ATTR2]] { +// CHECK-SAME: (%struct.MyIterator* nonnull align 1 dereferenceable(1) [[LOOPVAR:%.*]], i64 [[LOGICAL:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR2]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[LOOPVAR_ADDR:%.*]] = alloca %struct.MyIterator*, align 8 // CHECK-NEXT: [[LOGICAL_ADDR:%.*]] = alloca i64, align 8 @@ -159,8 +159,8 @@ extern "C" void workshareloop_iterator(float *a, float *b, float *c) { // CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[LOGICAL_ADDR]], align 8 // CHECK-NEXT: [[MUL:%.*]] = mul i64 1, [[TMP2]] // CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[MUL]] to i32 -// CHECK-NEXT: call void @_ZNK10MyIteratorplEj(%struct.MyIterator* sret([[STRUCT_MYITERATOR]]) align 1 [[REF_TMP]], %struct.MyIterator* noundef [[TMP1]], i32 noundef [[CONV]]) +// CHECK-NEXT: call void @_ZNK10MyIteratorplEj(%struct.MyIterator* sret([[STRUCT_MYITERATOR]]) align 1 [[REF_TMP]], %struct.MyIterator* nonnull align 1 dereferenceable(1) [[TMP1]], i32 [[CONV]]) // CHECK-NEXT: [[TMP3:%.*]] = load %struct.MyIterator*, %struct.MyIterator** [[LOOPVAR_ADDR]], align 8 -// CHECK-NEXT: [[CALL:%.*]] = call noundef nonnull align 1 dereferenceable(1) %struct.MyIterator* @_ZN10MyIteratoraSERKS_(%struct.MyIterator* noundef [[TMP3]], %struct.MyIterator* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) +// CHECK-NEXT: [[CALL:%.*]] = call nonnull align 1 dereferenceable(1) %struct.MyIterator* @_ZN10MyIteratoraSERKS_(%struct.MyIterator* nonnull align 1 dereferenceable(1) [[TMP3]], %struct.MyIterator* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK-NEXT: ret void // diff --git a/clang/test/OpenMP/irbuilder_for_rangefor.cpp b/clang/test/OpenMP/irbuilder_for_rangefor.cpp index 6f47dbade99a0a30ed215a9d62a542ee99911f9f..7e61dbb6e63c67052765460c48ea0335443d3217 100644 --- a/clang/test/OpenMP/irbuilder_for_rangefor.cpp +++ b/clang/test/OpenMP/irbuilder_for_rangefor.cpp @@ -34,7 +34,7 @@ extern "C" void workshareloop_rangefor(float *a, float *b, float *c) { #endif // HEADER // CHECK-LABEL: define {{[^@]+}}@workshareloop_rangefor -// CHECK-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -54,20 +54,20 @@ extern "C" void workshareloop_rangefor(float *a, float *b, float *c) { // CHECK-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 // CHECK-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 // CHECK-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN7MyRangeC1Ei(%struct.MyRange* noundef [[REF_TMP]], i32 noundef 42) +// CHECK-NEXT: call void @_ZN7MyRangeC1Ei(%struct.MyRange* nonnull align 1 dereferenceable(1) [[REF_TMP]], i32 42) // CHECK-NEXT: store %struct.MyRange* [[REF_TMP]], %struct.MyRange** [[__RANGE2]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load %struct.MyRange*, %struct.MyRange** [[__RANGE2]], align 8 -// CHECK-NEXT: call void @_ZN7MyRange5beginEv(%struct.MyIterator* sret([[STRUCT_MYITERATOR]]) align 1 [[__BEGIN2]], %struct.MyRange* noundef [[TMP0]]) +// CHECK-NEXT: call void @_ZN7MyRange5beginEv(%struct.MyIterator* sret([[STRUCT_MYITERATOR]]) align 1 [[__BEGIN2]], %struct.MyRange* nonnull align 1 dereferenceable(1) [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = load %struct.MyRange*, %struct.MyRange** [[__RANGE2]], align 8 -// CHECK-NEXT: call void @_ZN7MyRange3endEv(%struct.MyIterator* sret([[STRUCT_MYITERATOR]]) align 1 [[__END2]], %struct.MyRange* noundef [[TMP1]]) -// CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_ZNK10MyIteratordeEv(%struct.MyIterator* noundef [[__BEGIN2]]) +// CHECK-NEXT: call void @_ZN7MyRange3endEv(%struct.MyIterator* sret([[STRUCT_MYITERATOR]]) align 1 [[__END2]], %struct.MyRange* nonnull align 1 dereferenceable(1) [[TMP1]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32 @_ZNK10MyIteratordeEv(%struct.MyIterator* nonnull align 1 dereferenceable(1) [[__BEGIN2]]) // CHECK-NEXT: store i32 [[CALL]], i32* [[I]], align 4 // CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 // CHECK-NEXT: store %struct.MyIterator* [[__BEGIN2]], %struct.MyIterator** [[TMP2]], align 8 // CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 // CHECK-NEXT: store %struct.MyIterator* [[__END2]], %struct.MyIterator** [[TMP3]], align 8 // CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[AGG_CAPTURED1]], i32 0, i32 0 -// CHECK-NEXT: call void @_ZN10MyIteratorC1ERKS_(%struct.MyIterator* noundef [[TMP4]], %struct.MyIterator* noundef nonnull align 1 dereferenceable(1) [[__BEGIN2]]) +// CHECK-NEXT: call void @_ZN10MyIteratorC1ERKS_(%struct.MyIterator* nonnull align 1 dereferenceable(1) [[TMP4]], %struct.MyIterator* nonnull align 1 dereferenceable(1) [[__BEGIN2]]) // CHECK-NEXT: call void @__captured_stmt(i64* [[DOTCOUNT_ADDR]], %struct.anon* [[AGG_CAPTURED]]) // CHECK-NEXT: [[DOTCOUNT:%.*]] = load i64, i64* [[DOTCOUNT_ADDR]], align 8 // CHECK-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]] @@ -122,7 +122,7 @@ extern "C" void workshareloop_rangefor(float *a, float *b, float *c) { // // // CHECK-LABEL: define {{[^@]+}}@__captured_stmt -// CHECK-SAME: (i64* noundef nonnull align 8 dereferenceable(8) [[DISTANCE:%.*]], %struct.anon* noalias noundef [[__CONTEXT:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK-SAME: (i64* nonnull align 8 dereferenceable(8) [[DISTANCE:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DISTANCE_ADDR:%.*]] = alloca i64*, align 8 // CHECK-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 @@ -134,23 +134,23 @@ extern "C" void workshareloop_rangefor(float *a, float *b, float *c) { // CHECK-NEXT: [[TMP0:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP0]], i32 0, i32 0 // CHECK-NEXT: [[TMP2:%.*]] = load %struct.MyIterator*, %struct.MyIterator** [[TMP1]], align 8 -// CHECK-NEXT: call void @_ZN10MyIteratorC1ERKS_(%struct.MyIterator* noundef [[DOTSTART]], %struct.MyIterator* noundef nonnull align 1 dereferenceable(1) [[TMP2]]) +// CHECK-NEXT: call void @_ZN10MyIteratorC1ERKS_(%struct.MyIterator* nonnull align 1 dereferenceable(1) [[DOTSTART]], %struct.MyIterator* nonnull align 1 dereferenceable(1) [[TMP2]]) // CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP0]], i32 0, i32 1 // CHECK-NEXT: [[TMP4:%.*]] = load %struct.MyIterator*, %struct.MyIterator** [[TMP3]], align 8 -// CHECK-NEXT: call void @_ZN10MyIteratorC1ERKS_(%struct.MyIterator* noundef [[DOTSTOP]], %struct.MyIterator* noundef nonnull align 1 dereferenceable(1) [[TMP4]]) +// CHECK-NEXT: call void @_ZN10MyIteratorC1ERKS_(%struct.MyIterator* nonnull align 1 dereferenceable(1) [[DOTSTOP]], %struct.MyIterator* nonnull align 1 dereferenceable(1) [[TMP4]]) // CHECK-NEXT: store i64 1, i64* [[DOTSTEP]], align 8 // CHECK-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTSTEP]], align 8 // CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP5]], 0 // CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK: cond.true: -// CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_ZNK10MyIteratormiERKS_(%struct.MyIterator* noundef [[DOTSTART]], %struct.MyIterator* noundef nonnull align 1 dereferenceable(1) [[DOTSTOP]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32 @_ZNK10MyIteratormiERKS_(%struct.MyIterator* nonnull align 1 dereferenceable(1) [[DOTSTART]], %struct.MyIterator* nonnull align 1 dereferenceable(1) [[DOTSTOP]]) // CHECK-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64 // CHECK-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTSTEP]], align 8 // CHECK-NEXT: [[SUB:%.*]] = sub i64 0, [[TMP6]] // CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[CONV]], [[SUB]] // CHECK-NEXT: br label [[COND_END:%.*]] // CHECK: cond.false: -// CHECK-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZNK10MyIteratormiERKS_(%struct.MyIterator* noundef [[DOTSTOP]], %struct.MyIterator* noundef nonnull align 1 dereferenceable(1) [[DOTSTART]]) +// CHECK-NEXT: [[CALL1:%.*]] = call i32 @_ZNK10MyIteratormiERKS_(%struct.MyIterator* nonnull align 1 dereferenceable(1) [[DOTSTOP]], %struct.MyIterator* nonnull align 1 dereferenceable(1) [[DOTSTART]]) // CHECK-NEXT: [[CONV2:%.*]] = sext i32 [[CALL1]] to i64 // CHECK-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTSTEP]], align 8 // CHECK-NEXT: [[DIV3:%.*]] = udiv i64 [[CONV2]], [[TMP7]] @@ -163,7 +163,7 @@ extern "C" void workshareloop_rangefor(float *a, float *b, float *c) { // // // CHECK-LABEL: define {{[^@]+}}@__captured_stmt.1 -// CHECK-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i64 noundef [[LOGICAL:%.*]], %struct.anon.0* noalias noundef [[__CONTEXT:%.*]]) #[[ATTR2]] { +// CHECK-SAME: (i32* nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i64 [[LOGICAL:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR2]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[LOOPVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK-NEXT: [[LOGICAL_ADDR:%.*]] = alloca i64, align 8 @@ -177,8 +177,8 @@ extern "C" void workshareloop_rangefor(float *a, float *b, float *c) { // CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[LOGICAL_ADDR]], align 8 // CHECK-NEXT: [[MUL:%.*]] = mul i64 1, [[TMP2]] // CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[MUL]] to i32 -// CHECK-NEXT: call void @_ZNK10MyIteratorplEj(%struct.MyIterator* sret([[STRUCT_MYITERATOR]]) align 1 [[REF_TMP]], %struct.MyIterator* noundef [[TMP1]], i32 noundef [[CONV]]) -// CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_ZNK10MyIteratordeEv(%struct.MyIterator* noundef [[REF_TMP]]) +// CHECK-NEXT: call void @_ZNK10MyIteratorplEj(%struct.MyIterator* sret([[STRUCT_MYITERATOR]]) align 1 [[REF_TMP]], %struct.MyIterator* nonnull align 1 dereferenceable(1) [[TMP1]], i32 [[CONV]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32 @_ZNK10MyIteratordeEv(%struct.MyIterator* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK-NEXT: [[TMP3:%.*]] = load i32*, i32** [[LOOPVAR_ADDR]], align 8 // CHECK-NEXT: store i32 [[CALL]], i32* [[TMP3]], align 4 // CHECK-NEXT: ret void diff --git a/clang/test/OpenMP/irbuilder_for_unsigned.c b/clang/test/OpenMP/irbuilder_for_unsigned.c index a7e70391c027bb0d1834b1ba9497fb64121a9ddf..581b350736ef48fcc364d0e8c5cf60e9376fd31c 100644 --- a/clang/test/OpenMP/irbuilder_for_unsigned.c +++ b/clang/test/OpenMP/irbuilder_for_unsigned.c @@ -14,7 +14,7 @@ extern "C" void workshareloop_unsigned(float *a, float *b, float *c, float *d) { #endif // HEADER // CHECK-LABEL: define {{[^@]+}}@workshareloop_unsigned -// CHECK-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -98,7 +98,7 @@ extern "C" void workshareloop_unsigned(float *a, float *b, float *c, float *d) { // // // CHECK-LABEL: define {{[^@]+}}@__captured_stmt -// CHECK-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], %struct.anon* noalias noundef [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK-SAME: (i32* nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DISTANCE_ADDR:%.*]] = alloca i32*, align 8 // CHECK-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 @@ -135,7 +135,7 @@ extern "C" void workshareloop_unsigned(float *a, float *b, float *c, float *d) { // // // CHECK-LABEL: define {{[^@]+}}@__captured_stmt.1 -// CHECK-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], %struct.anon.0* noalias noundef [[__CONTEXT:%.*]]) #[[ATTR1]] { +// CHECK-SAME: (i32* nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 [[LOGICAL:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[LOOPVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK-NEXT: [[LOGICAL_ADDR:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_constant_for.c b/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_constant_for.c index fa25aa717de054d3a21667f30b6ebcd3e8923c4b..605c2bec0c3d06d0dc7768f3e67c70529e9a543a 100644 --- a/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_constant_for.c +++ b/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_constant_for.c @@ -102,7 +102,7 @@ double sind(double); // CHECK-NEXT: %[[ARRAYIDX:.+]] = getelementptr inbounds float, float* %[[TMP17]], i64 %[[IDXPROM]] // CHECK-NEXT: %[[TMP19:.+]] = load float, float* %[[ARRAYIDX]], align 4 // CHECK-NEXT: %[[CONV:.+]] = fpext float %[[TMP19]] to double -// CHECK-NEXT: %[[CALL:.+]] = call double @sind(double noundef %[[CONV]]) +// CHECK-NEXT: %[[CALL:.+]] = call double @sind(double %[[CONV]]) // CHECK-NEXT: %[[TMP20:.+]] = load float*, float** %[[C_ADDR]], align 8 // CHECK-NEXT: %[[TMP21:.+]] = load i32, i32* %[[I]], align 4 // CHECK-NEXT: %[[IDXPROM2:.+]] = sext i32 %[[TMP21]] to i64 diff --git a/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_for_collapse.c b/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_for_collapse.c index be974d5454bd1b2f54ed25f41a69cad6408aae50..d83a33bfc20e029c51aa3176d91052cc279badf4 100644 --- a/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_for_collapse.c +++ b/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_for_collapse.c @@ -9,6 +9,201 @@ double sind(double); +// CHECK-LABEL: define {{.*}}@unroll_partial_heuristic_for( +// CHECK-NEXT: [[ENTRY:.*]]: +// CHECK-NEXT: %[[M_ADDR:.+]] = alloca i32, align 4 +// CHECK-NEXT: %[[A_ADDR:.+]] = alloca float*, align 8 +// CHECK-NEXT: %[[B_ADDR:.+]] = alloca float*, align 8 +// CHECK-NEXT: %[[C_ADDR:.+]] = alloca float*, align 8 +// CHECK-NEXT: %[[D_ADDR:.+]] = alloca float*, align 8 +// CHECK-NEXT: %[[E_ADDR:.+]] = alloca float*, align 8 +// CHECK-NEXT: %[[OFFSET_ADDR:.+]] = alloca float, align 4 +// CHECK-NEXT: %[[DOTOMP_IV:.+]] = alloca i64, align 8 +// CHECK-NEXT: %[[TMP:.+]] = alloca i32, align 4 +// CHECK-NEXT: %[[TMP1:.+]] = alloca i32, align 4 +// CHECK-NEXT: %[[DOTCAPTURE_EXPR_:.+]] = alloca i32, align 4 +// CHECK-NEXT: %[[J:.+]] = alloca i32, align 4 +// CHECK-NEXT: %[[DOTCAPTURE_EXPR_2:.+]] = alloca i64, align 8 +// CHECK-NEXT: %[[I:.+]] = alloca i32, align 4 +// CHECK-NEXT: %[[DOTUNROLLED_IV_J:.+]] = alloca i32, align 4 +// CHECK-NEXT: %[[DOTOMP_LB:.+]] = alloca i64, align 8 +// CHECK-NEXT: %[[DOTOMP_UB:.+]] = alloca i64, align 8 +// CHECK-NEXT: %[[DOTOMP_STRIDE:.+]] = alloca i64, align 8 +// CHECK-NEXT: %[[DOTOMP_IS_LAST:.+]] = alloca i32, align 4 +// CHECK-NEXT: %[[I6:.+]] = alloca i32, align 4 +// CHECK-NEXT: %[[DOTUNROLLED_IV_J7:.+]] = alloca i32, align 4 +// CHECK-NEXT: %[[DOTUNROLL_INNER_IV_J:.+]] = alloca i32, align 4 +// CHECK-NEXT: store i32 %[[M:.+]], i32* %[[M_ADDR]], align 4 +// CHECK-NEXT: store float* %[[A:.+]], float** %[[A_ADDR]], align 8 +// CHECK-NEXT: store float* %[[B:.+]], float** %[[B_ADDR]], align 8 +// CHECK-NEXT: store float* %[[C:.+]], float** %[[C_ADDR]], align 8 +// CHECK-NEXT: store float* %[[D:.+]], float** %[[D_ADDR]], align 8 +// CHECK-NEXT: store float* %[[E:.+]], float** %[[E_ADDR]], align 8 +// CHECK-NEXT: store float %[[OFFSET:.+]], float* %[[OFFSET_ADDR]], align 4 +// CHECK-NEXT: %[[TMP0:.+]] = load i32, i32* %[[M_ADDR]], align 4 +// CHECK-NEXT: store i32 %[[TMP0]], i32* %[[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: store i32 0, i32* %[[J]], align 4 +// CHECK-NEXT: %[[TMP1_1:.+]] = load i32, i32* %[[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: %[[SUB:.+]] = sub nsw i32 %[[TMP1_1]], 0 +// CHECK-NEXT: %[[DIV:.+]] = sdiv i32 %[[SUB]], 1 +// CHECK-NEXT: %[[CONV:.+]] = sext i32 %[[DIV]] to i64 +// CHECK-NEXT: %[[MUL:.+]] = mul nsw i64 %[[CONV]], 4 +// CHECK-NEXT: %[[SUB3:.+]] = sub nsw i64 %[[MUL]], 1 +// CHECK-NEXT: store i64 %[[SUB3]], i64* %[[DOTCAPTURE_EXPR_2]], align 8 +// CHECK-NEXT: store i32 0, i32* %[[I]], align 4 +// CHECK-NEXT: store i32 0, i32* %[[DOTUNROLLED_IV_J]], align 4 +// CHECK-NEXT: %[[TMP2:.+]] = load i32, i32* %[[DOTCAPTURE_EXPR_]], align 4 +// CHECK-NEXT: %[[CMP:.+]] = icmp slt i32 0, %[[TMP2]] +// CHECK-NEXT: br i1 %[[CMP]], label %[[OMP_PRECOND_THEN:.+]], label %[[OMP_PRECOND_END:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_PRECOND_THEN]]: +// CHECK-NEXT: store i64 0, i64* %[[DOTOMP_LB]], align 8 +// CHECK-NEXT: %[[TMP3:.+]] = load i64, i64* %[[DOTCAPTURE_EXPR_2]], align 8 +// CHECK-NEXT: store i64 %[[TMP3]], i64* %[[DOTOMP_UB]], align 8 +// CHECK-NEXT: store i64 1, i64* %[[DOTOMP_STRIDE]], align 8 +// CHECK-NEXT: store i32 0, i32* %[[DOTOMP_IS_LAST]], align 4 +// CHECK-NEXT: %[[OMP_GLOBAL_THREAD_NUM:.+]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @3) +// CHECK-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @1, i32 %[[OMP_GLOBAL_THREAD_NUM]], i32 34, i32* %[[DOTOMP_IS_LAST]], i64* %[[DOTOMP_LB]], i64* %[[DOTOMP_UB]], i64* %[[DOTOMP_STRIDE]], i64 1, i64 1) +// CHECK-NEXT: %[[TMP4:.+]] = load i64, i64* %[[DOTOMP_UB]], align 8 +// CHECK-NEXT: %[[TMP5:.+]] = load i64, i64* %[[DOTCAPTURE_EXPR_2]], align 8 +// CHECK-NEXT: %[[CMP8:.+]] = icmp sgt i64 %[[TMP4]], %[[TMP5]] +// CHECK-NEXT: br i1 %[[CMP8]], label %[[COND_TRUE:.+]], label %[[COND_FALSE:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[COND_TRUE]]: +// CHECK-NEXT: %[[TMP6:.+]] = load i64, i64* %[[DOTCAPTURE_EXPR_2]], align 8 +// CHECK-NEXT: br label %[[COND_END:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[COND_FALSE]]: +// CHECK-NEXT: %[[TMP7:.+]] = load i64, i64* %[[DOTOMP_UB]], align 8 +// CHECK-NEXT: br label %[[COND_END]] +// CHECK-EMPTY: +// CHECK-NEXT: [[COND_END]]: +// CHECK-NEXT: %[[COND:.+]] = phi i64 [ %[[TMP6]], %[[COND_TRUE]] ], [ %[[TMP7]], %[[COND_FALSE]] ] +// CHECK-NEXT: store i64 %[[COND]], i64* %[[DOTOMP_UB]], align 8 +// CHECK-NEXT: %[[TMP8:.+]] = load i64, i64* %[[DOTOMP_LB]], align 8 +// CHECK-NEXT: store i64 %[[TMP8]], i64* %[[DOTOMP_IV]], align 8 +// CHECK-NEXT: br label %[[OMP_INNER_FOR_COND:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_INNER_FOR_COND]]: +// CHECK-NEXT: %[[TMP9:.+]] = load i64, i64* %[[DOTOMP_IV]], align 8 +// CHECK-NEXT: %[[TMP10:.+]] = load i64, i64* %[[DOTOMP_UB]], align 8 +// CHECK-NEXT: %[[CMP10:.+]] = icmp sle i64 %[[TMP9]], %[[TMP10]] +// CHECK-NEXT: br i1 %[[CMP10]], label %[[OMP_INNER_FOR_BODY:.+]], label %[[OMP_INNER_FOR_END:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_INNER_FOR_BODY]]: +// CHECK-NEXT: %[[TMP11:.+]] = load i64, i64* %[[DOTOMP_IV]], align 8 +// CHECK-NEXT: %[[DIV12:.+]] = sdiv i64 %[[TMP11]], 4 +// CHECK-NEXT: %[[MUL13:.+]] = mul nsw i64 %[[DIV12]], 1 +// CHECK-NEXT: %[[ADD:.+]] = add nsw i64 0, %[[MUL13]] +// CHECK-NEXT: %[[CONV14:.+]] = trunc i64 %[[ADD]] to i32 +// CHECK-NEXT: store i32 %[[CONV14]], i32* %[[I6]], align 4 +// CHECK-NEXT: %[[TMP12:.+]] = load i64, i64* %[[DOTOMP_IV]], align 8 +// CHECK-NEXT: %[[TMP13:.+]] = load i64, i64* %[[DOTOMP_IV]], align 8 +// CHECK-NEXT: %[[DIV15:.+]] = sdiv i64 %[[TMP13]], 4 +// CHECK-NEXT: %[[MUL16:.+]] = mul nsw i64 %[[DIV15]], 4 +// CHECK-NEXT: %[[SUB17:.+]] = sub nsw i64 %[[TMP12]], %[[MUL16]] +// CHECK-NEXT: %[[MUL18:.+]] = mul nsw i64 %[[SUB17]], 2 +// CHECK-NEXT: %[[ADD19:.+]] = add nsw i64 0, %[[MUL18]] +// CHECK-NEXT: %[[CONV20:.+]] = trunc i64 %[[ADD19]] to i32 +// CHECK-NEXT: store i32 %[[CONV20]], i32* %[[DOTUNROLLED_IV_J7]], align 4 +// CHECK-NEXT: %[[TMP14:.+]] = load i32, i32* %[[DOTUNROLLED_IV_J7]], align 4 +// CHECK-NEXT: store i32 %[[TMP14]], i32* %[[DOTUNROLL_INNER_IV_J]], align 4 +// CHECK-NEXT: br label %[[FOR_COND:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[FOR_COND]]: +// CHECK-NEXT: %[[TMP15:.+]] = load i32, i32* %[[DOTUNROLL_INNER_IV_J]], align 4 +// CHECK-NEXT: %[[TMP16:.+]] = load i32, i32* %[[DOTUNROLLED_IV_J7]], align 4 +// CHECK-NEXT: %[[ADD21:.+]] = add nsw i32 %[[TMP16]], 2 +// CHECK-NEXT: %[[CMP22:.+]] = icmp sle i32 %[[TMP15]], %[[ADD21]] +// CHECK-NEXT: br i1 %[[CMP22]], label %[[LAND_RHS:.+]], label %[[LAND_END:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[LAND_RHS]]: +// CHECK-NEXT: %[[TMP17:.+]] = load i32, i32* %[[DOTUNROLL_INNER_IV_J]], align 4 +// CHECK-NEXT: %[[CMP24:.+]] = icmp sle i32 %[[TMP17]], 8 +// CHECK-NEXT: br label %[[LAND_END]] +// CHECK-EMPTY: +// CHECK-NEXT: [[LAND_END]]: +// CHECK-NEXT: %[[TMP18:.+]] = phi i1 [ false, %[[FOR_COND]] ], [ %[[CMP24]], %[[LAND_RHS]] ] +// CHECK-NEXT: br i1 %[[TMP18]], label %[[FOR_BODY:.+]], label %[[FOR_END:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[FOR_BODY]]: +// CHECK-NEXT: %[[TMP19:.+]] = load i32, i32* %[[DOTUNROLL_INNER_IV_J]], align 4 +// CHECK-NEXT: %[[MUL26:.+]] = mul nsw i32 %[[TMP19]], 1 +// CHECK-NEXT: %[[ADD27:.+]] = add nsw i32 0, %[[MUL26]] +// CHECK-NEXT: store i32 %[[ADD27]], i32* %[[J]], align 4 +// CHECK-NEXT: %[[TMP20:.+]] = load float*, float** %[[B_ADDR]], align 8 +// CHECK-NEXT: %[[TMP21:.+]] = load i32, i32* %[[I6]], align 4 +// CHECK-NEXT: %[[IDXPROM:.+]] = sext i32 %[[TMP21]] to i64 +// CHECK-NEXT: %[[ARRAYIDX:.+]] = getelementptr inbounds float, float* %[[TMP20]], i64 %[[IDXPROM]] +// CHECK-NEXT: %[[TMP22:.+]] = load float, float* %[[ARRAYIDX]], align 4 +// CHECK-NEXT: %[[CONV28:.+]] = fpext float %[[TMP22]] to double +// CHECK-NEXT: %[[CALL:.+]] = call double @sind(double %[[CONV28]]) +// CHECK-NEXT: %[[TMP23:.+]] = load float*, float** %[[C_ADDR]], align 8 +// CHECK-NEXT: %[[TMP24:.+]] = load i32, i32* %[[I6]], align 4 +// CHECK-NEXT: %[[IDXPROM29:.+]] = sext i32 %[[TMP24]] to i64 +// CHECK-NEXT: %[[ARRAYIDX30:.+]] = getelementptr inbounds float, float* %[[TMP23]], i64 %[[IDXPROM29]] +// CHECK-NEXT: %[[TMP25:.+]] = load float, float* %[[ARRAYIDX30]], align 4 +// CHECK-NEXT: %[[CONV31:.+]] = fpext float %[[TMP25]] to double +// CHECK-NEXT: %[[MUL32:.+]] = fmul double %[[CALL]], %[[CONV31]] +// CHECK-NEXT: %[[TMP26:.+]] = load float*, float** %[[D_ADDR]], align 8 +// CHECK-NEXT: %[[TMP27:.+]] = load i32, i32* %[[I6]], align 4 +// CHECK-NEXT: %[[IDXPROM33:.+]] = sext i32 %[[TMP27]] to i64 +// CHECK-NEXT: %[[ARRAYIDX34:.+]] = getelementptr inbounds float, float* %[[TMP26]], i64 %[[IDXPROM33]] +// CHECK-NEXT: %[[TMP28:.+]] = load float, float* %[[ARRAYIDX34]], align 4 +// CHECK-NEXT: %[[CONV35:.+]] = fpext float %[[TMP28]] to double +// CHECK-NEXT: %[[MUL36:.+]] = fmul double %[[MUL32]], %[[CONV35]] +// CHECK-NEXT: %[[TMP29:.+]] = load float*, float** %[[E_ADDR]], align 8 +// CHECK-NEXT: %[[TMP30:.+]] = load i32, i32* %[[I6]], align 4 +// CHECK-NEXT: %[[IDXPROM37:.+]] = sext i32 %[[TMP30]] to i64 +// CHECK-NEXT: %[[ARRAYIDX38:.+]] = getelementptr inbounds float, float* %[[TMP29]], i64 %[[IDXPROM37]] +// CHECK-NEXT: %[[TMP31:.+]] = load float, float* %[[ARRAYIDX38]], align 4 +// CHECK-NEXT: %[[CONV39:.+]] = fpext float %[[TMP31]] to double +// CHECK-NEXT: %[[MUL40:.+]] = fmul double %[[MUL36]], %[[CONV39]] +// CHECK-NEXT: %[[TMP32:.+]] = load float, float* %[[OFFSET_ADDR]], align 4 +// CHECK-NEXT: %[[CONV41:.+]] = fpext float %[[TMP32]] to double +// CHECK-NEXT: %[[ADD42:.+]] = fadd double %[[MUL40]], %[[CONV41]] +// CHECK-NEXT: %[[TMP33:.+]] = load float*, float** %[[A_ADDR]], align 8 +// CHECK-NEXT: %[[TMP34:.+]] = load i32, i32* %[[I6]], align 4 +// CHECK-NEXT: %[[IDXPROM43:.+]] = sext i32 %[[TMP34]] to i64 +// CHECK-NEXT: %[[ARRAYIDX44:.+]] = getelementptr inbounds float, float* %[[TMP33]], i64 %[[IDXPROM43]] +// CHECK-NEXT: %[[TMP35:.+]] = load float, float* %[[ARRAYIDX44]], align 4 +// CHECK-NEXT: %[[CONV45:.+]] = fpext float %[[TMP35]] to double +// CHECK-NEXT: %[[ADD46:.+]] = fadd double %[[CONV45]], %[[ADD42]] +// CHECK-NEXT: %[[CONV47:.+]] = fptrunc double %[[ADD46]] to float +// CHECK-NEXT: store float %[[CONV47]], float* %[[ARRAYIDX44]], align 4 +// CHECK-NEXT: br label %[[FOR_INC:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[FOR_INC]]: +// CHECK-NEXT: %[[TMP36:.+]] = load i32, i32* %[[DOTUNROLL_INNER_IV_J]], align 4 +// CHECK-NEXT: %[[INC:.+]] = add nsw i32 %[[TMP36]], 1 +// CHECK-NEXT: store i32 %[[INC]], i32* %[[DOTUNROLL_INNER_IV_J]], align 4 +// CHECK-NEXT: br label %[[FOR_COND]], !llvm.loop ![[LOOP3:[0-9]+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[FOR_END]]: +// CHECK-NEXT: br label %[[OMP_BODY_CONTINUE:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_BODY_CONTINUE]]: +// CHECK-NEXT: br label %[[OMP_INNER_FOR_INC:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_INNER_FOR_INC]]: +// CHECK-NEXT: %[[TMP37:.+]] = load i64, i64* %[[DOTOMP_IV]], align 8 +// CHECK-NEXT: %[[ADD48:.+]] = add nsw i64 %[[TMP37]], 1 +// CHECK-NEXT: store i64 %[[ADD48]], i64* %[[DOTOMP_IV]], align 8 +// CHECK-NEXT: br label %[[OMP_INNER_FOR_COND]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_INNER_FOR_END]]: +// CHECK-NEXT: br label %[[OMP_LOOP_EXIT:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_LOOP_EXIT]]: +// CHECK-NEXT: %[[OMP_GLOBAL_THREAD_NUM49:.+]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @5) +// CHECK-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @1, i32 %[[OMP_GLOBAL_THREAD_NUM49]]) +// CHECK-NEXT: br label %[[OMP_PRECOND_END]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_PRECOND_END]]: +// CHECK-NEXT: %[[OMP_GLOBAL_THREAD_NUM50:.+]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @7) +// CHECK-NEXT: call void @__kmpc_barrier(%struct.ident_t* @6, i32 %[[OMP_GLOBAL_THREAD_NUM50]]) +// CHECK-NEXT: ret void +// CHECK-NEXT: } void unroll_partial_heuristic_for(int m, float *a, float *b, float *c, float *d, float *e, float offset) { #pragma omp for collapse(2) @@ -22,182 +217,9 @@ void unroll_partial_heuristic_for(int m, float *a, float *b, float *c, float *d, #endif // HEADER -// CHECK-LABEL: define {{[^@]+}}@unroll_partial_heuristic_for -// CHECK-SAME: (i32 noundef [[M:%.*]], float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]], float* noundef [[E:%.*]], float noundef [[OFFSET:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 -// CHECK-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 -// CHECK-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 -// CHECK-NEXT: [[E_ADDR:%.*]] = alloca float*, align 8 -// CHECK-NEXT: [[OFFSET_ADDR:%.*]] = alloca float, align 4 -// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 -// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTUNROLLED_IV_J:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[I6:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTUNROLLED_IV_J7:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTUNROLL_INNER_IV_J:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 -// CHECK-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// CHECK-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 -// CHECK-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 -// CHECK-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 -// CHECK-NEXT: store float* [[E]], float** [[E_ADDR]], align 8 -// CHECK-NEXT: store float [[OFFSET]], float* [[OFFSET_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[M_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK-NEXT: store i32 0, i32* [[J]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0 -// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], 4 -// CHECK-NEXT: [[SUB3:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK-NEXT: store i64 [[SUB3]], i64* [[DOTCAPTURE_EXPR_2]], align 8 -// CHECK-NEXT: store i32 0, i32* [[I]], align 4 -// CHECK-NEXT: store i32 0, i32* [[DOTUNROLLED_IV_J]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 -// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP2]] -// CHECK-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK: omp.precond.then: -// CHECK-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 -// CHECK-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8 -// CHECK-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 -// CHECK-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 -// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) -// CHECK-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 -// CHECK-NEXT: [[CMP8:%.*]] = icmp sgt i64 [[TMP4]], [[TMP5]] -// CHECK-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK: cond.true: -// CHECK-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 -// CHECK-NEXT: br label [[COND_END:%.*]] -// CHECK: cond.false: -// CHECK-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK-NEXT: br label [[COND_END]] -// CHECK: cond.end: -// CHECK-NEXT: [[COND:%.*]] = phi i64 [ [[TMP6]], [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// CHECK-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 -// CHECK-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// CHECK-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 -// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK: omp.inner.for.cond: -// CHECK-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 -// CHECK-NEXT: [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]] -// CHECK-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK: omp.inner.for.body: -// CHECK-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK-NEXT: [[DIV12:%.*]] = sdiv i64 [[TMP11]], 4 -// CHECK-NEXT: [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1 -// CHECK-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL13]] -// CHECK-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK-NEXT: store i32 [[CONV14]], i32* [[I6]], align 4 -// CHECK-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP13]], 4 -// CHECK-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 4 -// CHECK-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP12]], [[MUL16]] -// CHECK-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 2 -// CHECK-NEXT: [[ADD19:%.*]] = add nsw i64 0, [[MUL18]] -// CHECK-NEXT: [[CONV20:%.*]] = trunc i64 [[ADD19]] to i32 -// CHECK-NEXT: store i32 [[CONV20]], i32* [[DOTUNROLLED_IV_J7]], align 4 -// CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTUNROLLED_IV_J7]], align 4 -// CHECK-NEXT: store i32 [[TMP14]], i32* [[DOTUNROLL_INNER_IV_J]], align 4 -// CHECK-NEXT: br label [[FOR_COND:%.*]] -// CHECK: for.cond: -// CHECK-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTUNROLL_INNER_IV_J]], align 4 -// CHECK-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTUNROLLED_IV_J7]], align 4 -// CHECK-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP16]], 2 -// CHECK-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP15]], [[ADD21]] -// CHECK-NEXT: br i1 [[CMP22]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] -// CHECK: land.rhs: -// CHECK-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTUNROLL_INNER_IV_J]], align 4 -// CHECK-NEXT: [[CMP24:%.*]] = icmp sle i32 [[TMP17]], 8 -// CHECK-NEXT: br label [[LAND_END]] -// CHECK: land.end: -// CHECK-NEXT: [[TMP18:%.*]] = phi i1 [ false, [[FOR_COND]] ], [ [[CMP24]], [[LAND_RHS]] ] -// CHECK-NEXT: br i1 [[TMP18]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] -// CHECK: for.body: -// CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTUNROLL_INNER_IV_J]], align 4 -// CHECK-NEXT: [[MUL26:%.*]] = mul nsw i32 [[TMP19]], 1 -// CHECK-NEXT: [[ADD27:%.*]] = add nsw i32 0, [[MUL26]] -// CHECK-NEXT: store i32 [[ADD27]], i32* [[J]], align 4 -// CHECK-NEXT: [[TMP20:%.*]] = load float*, float** [[B_ADDR]], align 8 -// CHECK-NEXT: [[TMP21:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM]] -// CHECK-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX]], align 4 -// CHECK-NEXT: [[CONV28:%.*]] = fpext float [[TMP22]] to double -// CHECK-NEXT: [[CALL:%.*]] = call double @sind(double noundef [[CONV28]]) -// CHECK-NEXT: [[TMP23:%.*]] = load float*, float** [[C_ADDR]], align 8 -// CHECK-NEXT: [[TMP24:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK-NEXT: [[IDXPROM29:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM29]] -// CHECK-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX30]], align 4 -// CHECK-NEXT: [[CONV31:%.*]] = fpext float [[TMP25]] to double -// CHECK-NEXT: [[MUL32:%.*]] = fmul double [[CALL]], [[CONV31]] -// CHECK-NEXT: [[TMP26:%.*]] = load float*, float** [[D_ADDR]], align 8 -// CHECK-NEXT: [[TMP27:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM33]] -// CHECK-NEXT: [[TMP28:%.*]] = load float, float* [[ARRAYIDX34]], align 4 -// CHECK-NEXT: [[CONV35:%.*]] = fpext float [[TMP28]] to double -// CHECK-NEXT: [[MUL36:%.*]] = fmul double [[MUL32]], [[CONV35]] -// CHECK-NEXT: [[TMP29:%.*]] = load float*, float** [[E_ADDR]], align 8 -// CHECK-NEXT: [[TMP30:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP30]] to i64 -// CHECK-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM37]] -// CHECK-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX38]], align 4 -// CHECK-NEXT: [[CONV39:%.*]] = fpext float [[TMP31]] to double -// CHECK-NEXT: [[MUL40:%.*]] = fmul double [[MUL36]], [[CONV39]] -// CHECK-NEXT: [[TMP32:%.*]] = load float, float* [[OFFSET_ADDR]], align 4 -// CHECK-NEXT: [[CONV41:%.*]] = fpext float [[TMP32]] to double -// CHECK-NEXT: [[ADD42:%.*]] = fadd double [[MUL40]], [[CONV41]] -// CHECK-NEXT: [[TMP33:%.*]] = load float*, float** [[A_ADDR]], align 8 -// CHECK-NEXT: [[TMP34:%.*]] = load i32, i32* [[I6]], align 4 -// CHECK-NEXT: [[IDXPROM43:%.*]] = sext i32 [[TMP34]] to i64 -// CHECK-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds float, float* [[TMP33]], i64 [[IDXPROM43]] -// CHECK-NEXT: [[TMP35:%.*]] = load float, float* [[ARRAYIDX44]], align 4 -// CHECK-NEXT: [[CONV45:%.*]] = fpext float [[TMP35]] to double -// CHECK-NEXT: [[ADD46:%.*]] = fadd double [[CONV45]], [[ADD42]] -// CHECK-NEXT: [[CONV47:%.*]] = fptrunc double [[ADD46]] to float -// CHECK-NEXT: store float [[CONV47]], float* [[ARRAYIDX44]], align 4 -// CHECK-NEXT: br label [[FOR_INC:%.*]] -// CHECK: for.inc: -// CHECK-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTUNROLL_INNER_IV_J]], align 4 -// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP36]], 1 -// CHECK-NEXT: store i32 [[INC]], i32* [[DOTUNROLL_INNER_IV_J]], align 4 -// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] -// CHECK: for.end: -// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK: omp.body.continue: -// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK: omp.inner.for.inc: -// CHECK-NEXT: [[TMP37:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 -// CHECK-NEXT: [[ADD48:%.*]] = add nsw i64 [[TMP37]], 1 -// CHECK-NEXT: store i64 [[ADD48]], i64* [[DOTOMP_IV]], align 8 -// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK: omp.inner.for.end: -// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK: omp.loop.exit: -// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM49:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB5:[0-9]+]]) -// CHECK-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM49]]) -// CHECK-NEXT: br label [[OMP_PRECOND_END]] -// CHECK: omp.precond.end: -// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM50:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB7:[0-9]+]]) -// CHECK-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB6:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM50]]) -// CHECK-NEXT: ret void -// +// CHECK: ![[META0:[0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// CHECK: ![[META1:[0-9]+]] = !{i32 7, !"openmp", i32 51} +// CHECK: ![[META2:[0-9]+]] = +// CHECK: ![[LOOP3]] = distinct !{![[LOOP3]], ![[LOOPPROP4:[0-9]+]], ![[LOOPPROP5:[0-9]+]]} +// CHECK: ![[LOOPPROP4]] = !{!"llvm.loop.mustprogress"} +// CHECK: ![[LOOPPROP5]] = !{!"llvm.loop.unroll.count", i32 2} diff --git a/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_runtime_for.c b/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_runtime_for.c index 6a1bbf5fad003274b6aa7138b8bbab27635555fb..07a1b5999be67f4740bd8529c8ff42d4d7793fa7 100644 --- a/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_runtime_for.c +++ b/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_runtime_for.c @@ -104,7 +104,7 @@ double sind(double); // CHECK-NEXT: %[[ARRAYIDX:.+]] = getelementptr inbounds float, float* %[[TMP18]], i64 %[[IDXPROM]] // CHECK-NEXT: %[[TMP20:.+]] = load float, float* %[[ARRAYIDX]], align 4 // CHECK-NEXT: %[[CONV:.+]] = fpext float %[[TMP20]] to double -// CHECK-NEXT: %[[CALL:.+]] = call double @sind(double noundef %[[CONV]]) +// CHECK-NEXT: %[[CALL:.+]] = call double @sind(double %[[CONV]]) // CHECK-NEXT: %[[TMP21:.+]] = load float*, float** %[[C_ADDR]], align 8 // CHECK-NEXT: %[[TMP22:.+]] = load i32, i32* %[[I]], align 4 // CHECK-NEXT: %[[IDXPROM2:.+]] = sext i32 %[[TMP22]] to i64 diff --git a/clang/test/OpenMP/master_taskloop_codegen.cpp b/clang/test/OpenMP/master_taskloop_codegen.cpp index d7ede40992b54043089cce45f3b56dc7422c647c..37f1344cc596a6ec6488921c3bfcbe1f4a50ff6b 100644 --- a/clang/test/OpenMP/master_taskloop_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_codegen.cpp @@ -107,7 +107,7 @@ int main(int argc, char **argv) { } } -// CHECK: define internal noundef i32 [[TASK1]]( +// CHECK: define internal i32 [[TASK1]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 @@ -137,7 +137,7 @@ int main(int argc, char **argv) { // CHECK: br label % // CHECK: ret i32 0 -// CHECK: define internal noundef i32 [[TASK2]]( +// CHECK: define internal i32 [[TASK2]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 @@ -167,7 +167,7 @@ int main(int argc, char **argv) { // CHECK: br label % // CHECK: ret i32 0 -// CHECK: define internal noundef i32 [[TASK3]]( +// CHECK: define internal i32 [[TASK3]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 @@ -185,7 +185,7 @@ int main(int argc, char **argv) { // CHECK: br label // CHECK: ret i32 0 -// CHECK: define internal noundef i32 [[TASK_CANCEL]]( +// CHECK: define internal i32 [[TASK_CANCEL]]( // CHECK: [[RES:%.+]] = call i32 @__kmpc_cancel(%struct.ident_t* @{{.+}}, i32 %{{.+}}, i32 4) // CHECK: [[IS_CANCEL:%.+]] = icmp ne i32 [[RES]], 0 // CHECK: br i1 [[IS_CANCEL]], label %[[EXIT:.+]], label %[[CONTINUE:[^,]+]] @@ -227,7 +227,7 @@ struct S { } } s(1); -// CHECK: define internal noundef i32 [[TASK4]]( +// CHECK: define internal i32 [[TASK4]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 diff --git a/clang/test/OpenMP/master_taskloop_firstprivate_codegen.cpp b/clang/test/OpenMP/master_taskloop_firstprivate_codegen.cpp index f3aa2e9917306c7437741bd1d91e24c0667c4602..35e7e4902be31c20eeecb7e73d1ae930674dde2c 100644 --- a/clang/test/OpenMP/master_taskloop_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_firstprivate_codegen.cpp @@ -93,7 +93,7 @@ int main() { // LAMBDA: store volatile double 2.0{{.+}}, double* [[G_REF]] // LAMBDA: store double* %{{.+}}, double** %{{.+}}, - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -145,7 +145,7 @@ int main() { // BLOCKS: store double* %{{.+}}, double** %{{.+}}, // BLOCKS: store i{{[0-9]+}}* %{{.+}}, i{{[0-9]+}}** %{{.+}}, - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -259,7 +259,7 @@ int main() { // CHECK-NEXT: br label {{%?}}[[EXIT]] // CHECK: [[EXIT]] -// CHECK: = call noundef i{{.+}} [[TMAIN_INT:@.+]]() +// CHECK: = call i{{.+}} [[TMAIN_INT:@.+]]() // No destructors must be called for private copies of s_arr and var. // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 @@ -270,7 +270,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -289,7 +289,7 @@ int main() { // CHECK: store i{{[0-9]+}}* [[PRIV_SIVAR]], i{{[0-9]+}}** [[ARG5]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -317,7 +317,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0 @@ -334,7 +334,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_COPY_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -425,7 +425,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -441,7 +441,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, // CHECK-DAG: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*, @@ -464,7 +464,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* %{{.+}}, i32 0, i32 0 @@ -481,7 +481,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_COPY_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp b/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp index 5b9b5dc52412872b2adba7e4270b89d9e572551b..c6198994c9d267a80430b69ab7c7ecf9c35acfb7 100644 --- a/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -disable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/master_taskloop_lastprivate_codegen.cpp b/clang/test/OpenMP/master_taskloop_lastprivate_codegen.cpp index 50f9a4d4160925e04a792096c43aaed8cbd17d3b..6fc76077d5b1f2676fa549054fcdb0efb808449e 100644 --- a/clang/test/OpenMP/master_taskloop_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_lastprivate_codegen.cpp @@ -81,7 +81,7 @@ int main() { // LAMBDA: store double 2.0{{.+}}, double* [[G_REF]] // LAMBDA: store double* %{{.+}}, double** %{{.+}}, - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -125,7 +125,7 @@ int main() { // BLOCKS: store double* %{{.+}}, double** %{{.+}}, // BLOCKS: store i{{[0-9]+}}* %{{.+}}, i{{[0-9]+}}** %{{.+}}, - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -237,7 +237,7 @@ int main() { // CHECK-NEXT: br label {{%?}}[[EXIT]] // CHECK: [[EXIT]] -// CHECK: = call noundef i{{.+}} [[TMAIN_INT:@.+]]() +// CHECK: = call i{{.+}} [[TMAIN_INT:@.+]]() // No destructors must be called for private copies of s_arr and var. // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 @@ -248,7 +248,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -267,7 +267,7 @@ int main() { // CHECK: store i{{[0-9]+}}* [[PRIV_SIVAR]], i{{[0-9]+}}** [[ARG5]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -314,7 +314,7 @@ int main() { // CHECK: br label // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* %{{.+}}, i32 0, i32 8 // CHECK: load i32, i32* % @@ -335,7 +335,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -421,7 +421,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -437,7 +437,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, // CHECK-DAG: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*, @@ -477,7 +477,7 @@ int main() { // CHECK: br label // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* %{{.+}}, i32 0, i32 8 // CHECK: load i32, i32* % @@ -498,7 +498,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/master_taskloop_private_codegen.cpp b/clang/test/OpenMP/master_taskloop_private_codegen.cpp index 567a9917e1ee3ad9e955e0d946bdc4e06107fe5f..d960427a464bd08aac8ebaa7e64464a0e2beec9e 100644 --- a/clang/test/OpenMP/master_taskloop_private_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_private_codegen.cpp @@ -77,7 +77,7 @@ int main() { // LAMBDA: [[SIVAR_REF:%.+]] = load i{{[0-9]+}}*, i{{[0-9]+}}** [[SIVAR_PTR_REF]] // LAMBDA: store i{{[0-9]+}} 3, i{{[0-9]+}}* [[SIVAR_REF]] - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 2; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -113,7 +113,7 @@ int main() { // BLOCKS-NOT: [[SIVAR]]{{[[^:word:]]}} // BLOCKS: ret - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 3; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -202,7 +202,7 @@ int main() { // CHECK: [[EXIT]] // CHECK: call i32 @__kmpc_omp_task([[LOC]], i32 [[GTID]], i8* -// CHECK: = call noundef i{{.+}} [[TMAIN_INT:@.+]]() +// CHECK: = call i{{.+}} [[TMAIN_INT:@.+]]() // No destructors must be called for private copies of s_arr and var. // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 @@ -213,7 +213,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -229,7 +229,7 @@ int main() { // CHECK: store [2 x i32]* [[PRIV_VEC]], [2 x i32]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -255,7 +255,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0 @@ -272,7 +272,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_DEF_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -342,7 +342,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -358,7 +358,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -382,7 +382,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* %{{.+}}, i32 0, i32 0 @@ -399,7 +399,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_DEF_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/master_taskloop_reduction_codegen.cpp b/clang/test/OpenMP/master_taskloop_reduction_codegen.cpp index 0e772125e86b3f586f8cd89b85278bf967ae1909..05ff997a8af5e9454ddc4aa2d52743ad0b6d0e65 100644 --- a/clang/test/OpenMP/master_taskloop_reduction_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_reduction_codegen.cpp @@ -170,52 +170,52 @@ sum = 0.0; // CHECK: ret i32 -// CHECK: define internal void @[[RED_INIT1]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT1]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB1]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB1]](i8* %0, i8* %1) // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_INIT2]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT2]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK-NOT: call i8* @__kmpc_threadprivate_cached( // CHECK: call void [[OMP_INIT1:@.+]]( // CHECK: ret void -// CHECK: define internal void [[OMP_COMB1:@.+]](%struct.S* noalias noundef %0, %struct.S* noalias noundef %1) +// CHECK: define internal void [[OMP_COMB1:@.+]](%struct.S* noalias %0, %struct.S* noalias %1) // CHECK: fadd float % -// CHECK: define internal void [[OMP_INIT1]](%struct.S* noalias noundef %0, %struct.S* noalias noundef %1) +// CHECK: define internal void [[OMP_INIT1]](%struct.S* noalias %0, %struct.S* noalias %1) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64( -// CHECK: define internal void @[[RED_FINI2]](i8* noundef %0) +// CHECK: define internal void @[[RED_FINI2]](i8* %0) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: call void @ // CHECK: ret void -// CHECK: define internal void @[[RED_COMB2]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB2]](i8* %0, i8* %1) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: call void [[OMP_COMB1]]( // CHECK: ret void -// CHECK: define internal void @[[RED_INIT3]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT3]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB3]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB3]](i8* %0, i8* %1) // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_INIT4]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT4]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB4]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB4]](i8* %0, i8* %1) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % diff --git a/clang/test/OpenMP/master_taskloop_simd_codegen.cpp b/clang/test/OpenMP/master_taskloop_simd_codegen.cpp index 6cf82e4c1a030da53ad5c5a0dcbeee889b287550..e54aabf1de2187e927ee53b2866c0b3a2998b973 100644 --- a/clang/test/OpenMP/master_taskloop_simd_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_simd_codegen.cpp @@ -96,7 +96,7 @@ int main(int argc, char **argv) { ; } -// CHECK: define internal noundef i32 [[TASK1]]( +// CHECK: define internal i32 [[TASK1]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 @@ -126,7 +126,7 @@ int main(int argc, char **argv) { // CHECK: br label %{{.*}}!llvm.loop // CHECK: ret i32 0 -// CHECK: define internal noundef i32 [[TASK2]]( +// CHECK: define internal i32 [[TASK2]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 @@ -156,7 +156,7 @@ int main(int argc, char **argv) { // CHECK: br label %{{.*}}!llvm.loop // CHECK: ret i32 0 -// CHECK: define internal noundef i32 [[TASK3]]( +// CHECK: define internal i32 [[TASK3]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 @@ -208,7 +208,7 @@ struct S { } } s(1); -// CHECK: define internal noundef i32 [[TASK4]]( +// CHECK: define internal i32 [[TASK4]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 diff --git a/clang/test/OpenMP/master_taskloop_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/master_taskloop_simd_firstprivate_codegen.cpp index 4907079d315c748a5654f6f145a37f3609630181..1ec41bb47ca3c4e30d07f65fac6b0a2a73a50b31 100644 --- a/clang/test/OpenMP/master_taskloop_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_simd_firstprivate_codegen.cpp @@ -86,7 +86,7 @@ int main() { // LAMBDA: store volatile double 2.0{{.+}}, double* [[G_REF]] // LAMBDA: store double* %{{.+}}, double** %{{.+}}, - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -131,7 +131,7 @@ int main() { // BLOCKS: store double* %{{.+}}, double** %{{.+}}, // BLOCKS: store i{{[0-9]+}}* %{{.+}}, i{{[0-9]+}}** %{{.+}}, - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -238,7 +238,7 @@ int main() { // Start task. // CHECK: call void @__kmpc_taskloop([[LOC]], i32 [[GTID]], i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* bitcast (void ([[KMP_TASK_MAIN_TY]]*, [[KMP_TASK_MAIN_TY]]*, i32)* [[MAIN_DUP:@.+]] to i8*)) -// CHECK: = call noundef i{{.+}} [[TMAIN_INT:@.+]]() +// CHECK: = call i{{.+}} [[TMAIN_INT:@.+]]() // No destructors must be called for private copies of s_arr and var. // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 @@ -249,7 +249,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -268,7 +268,7 @@ int main() { // CHECK: store i{{[0-9]+}}* [[PRIV_SIVAR]], i{{[0-9]+}}** [[ARG5]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -296,7 +296,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0 @@ -313,7 +313,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_COPY_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -404,7 +404,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -420,7 +420,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, // CHECK-DAG: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*, @@ -443,7 +443,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* %{{.+}}, i32 0, i32 0 @@ -460,7 +460,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_COPY_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp b/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp index 7c8bb2b3273abc552d0f7ee355f87c53bb9306ae..e6b68b4766f4eb898036837bba90739252acd979 100644 --- a/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -disable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/master_taskloop_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/master_taskloop_simd_lastprivate_codegen.cpp index 7c87ae5da5eb423ee356b54345b6635d7f4a5b3f..01ff374141593f22780834d4a64bef1c655b1895 100644 --- a/clang/test/OpenMP/master_taskloop_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_simd_lastprivate_codegen.cpp @@ -79,7 +79,7 @@ int main() { // LAMBDA: store double 2.0{{.+}}, double* [[G_REF]] // LAMBDA: store double* %{{.+}}, double** %{{.+}}, - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -123,7 +123,7 @@ int main() { // BLOCKS: store double* %{{.+}}, double** %{{.+}}, // BLOCKS: store i{{[0-9]+}}* %{{.+}}, i{{[0-9]+}}** %{{.+}}, - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -228,7 +228,7 @@ int main() { // Start task. // CHECK: call void @__kmpc_taskloop([[LOC]], i32 [[GTID]], i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* bitcast (void ([[KMP_TASK_MAIN_TY]]*, [[KMP_TASK_MAIN_TY]]*, i32)* [[MAIN_DUP:@.+]] to i8*)) -// CHECK: = call noundef i{{.+}} [[TMAIN_INT:@.+]]() +// CHECK: = call i{{.+}} [[TMAIN_INT:@.+]]() // No destructors must be called for private copies of s_arr and var. // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 @@ -239,7 +239,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -258,7 +258,7 @@ int main() { // CHECK: store i{{[0-9]+}}* [[PRIV_SIVAR]], i{{[0-9]+}}** [[ARG5]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -305,7 +305,7 @@ int main() { // CHECK: br label // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* %{{.+}}, i32 0, i32 8 // CHECK: load i32, i32* % @@ -326,7 +326,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -412,7 +412,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -428,7 +428,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, // CHECK-DAG: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*, @@ -468,7 +468,7 @@ int main() { // CHECK: br label // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* %{{.+}}, i32 0, i32 8 // CHECK: load i32, i32* % @@ -489,7 +489,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/master_taskloop_simd_private_codegen.cpp b/clang/test/OpenMP/master_taskloop_simd_private_codegen.cpp index ca20b89870dff4bd47cfcb08d406375262f14f34..bdf6c0fe2491af9d1d73cb5a60e72726c64b8a74 100644 --- a/clang/test/OpenMP/master_taskloop_simd_private_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_simd_private_codegen.cpp @@ -77,7 +77,7 @@ int main() { // LAMBDA: [[SIVAR_REF:%.+]] = load i{{[0-9]+}}*, i{{[0-9]+}}** [[SIVAR_PTR_REF]] // LAMBDA: store i{{[0-9]+}} 3, i{{[0-9]+}}* [[SIVAR_REF]] - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 2; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -113,7 +113,7 @@ int main() { // BLOCKS-NOT: [[SIVAR]]{{[[^:word:]]}} // BLOCKS: ret - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 3; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -195,7 +195,7 @@ int main() { // CHECK: call void @__kmpc_taskloop([[LOC]], i32 [[GTID]], i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* bitcast (void ([[KMP_TASK_MAIN_TY]]*, [[KMP_TASK_MAIN_TY]]*, i32)* [[MAIN_DUP:@.+]] to i8*)) // CHECK: call i32 @__kmpc_omp_task([[LOC]], i32 [[GTID]], i8* -// CHECK: = call noundef i{{.+}} [[TMAIN_INT:@.+]]() +// CHECK: = call i{{.+}} [[TMAIN_INT:@.+]]() // No destructors must be called for private copies of s_arr and var. // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 @@ -206,7 +206,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -222,7 +222,7 @@ int main() { // CHECK: store [2 x i32]* [[PRIV_VEC]], [2 x i32]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -248,7 +248,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0 @@ -265,7 +265,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_DEF_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -335,7 +335,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -351,7 +351,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -375,7 +375,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* %{{.+}}, i32 0, i32 0 @@ -392,7 +392,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_DEF_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp b/clang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp index 36ea7bb4c6a6323a8cb288d61026ab1c9603cbeb..fe0fdce70197143e7be1d47c062d9be82ce35d51 100644 --- a/clang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp @@ -163,51 +163,51 @@ sum = 0.0; // CHECK: ret i32 -// CHECK: define internal void @[[RED_INIT1]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT1]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB1]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB1]](i8* %0, i8* %1) // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_INIT2]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT2]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: call void [[OMP_INIT1:@.+]]( // CHECK: ret void -// CHECK: define internal void [[OMP_COMB1:@.+]](%struct.S* noalias noundef %0, %struct.S* noalias noundef %1) +// CHECK: define internal void [[OMP_COMB1:@.+]](%struct.S* noalias %0, %struct.S* noalias %1) // CHECK: fadd float % -// CHECK: define internal void [[OMP_INIT1]](%struct.S* noalias noundef %0, %struct.S* noalias noundef %1) +// CHECK: define internal void [[OMP_INIT1]](%struct.S* noalias %0, %struct.S* noalias %1) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64( -// CHECK: define internal void @[[RED_FINI2]](i8* noundef %0) +// CHECK: define internal void @[[RED_FINI2]](i8* %0) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: call void @ // CHECK: ret void -// CHECK: define internal void @[[RED_COMB2]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB2]](i8* %0, i8* %1) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: call void [[OMP_COMB1]]( // CHECK: ret void -// CHECK: define internal void @[[RED_INIT3]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT3]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB3]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB3]](i8* %0, i8* %1) // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_INIT4]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT4]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB4]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB4]](i8* %0, i8* %1) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % diff --git a/clang/test/OpenMP/nvptx_allocate_codegen.cpp b/clang/test/OpenMP/nvptx_allocate_codegen.cpp index 38c935031e903a8d4bd8627d5d6b3353fc47abb5..74446fa67a166e7c12bdb33878967a35faa364b1 100644 --- a/clang/test/OpenMP/nvptx_allocate_codegen.cpp +++ b/clang/test/OpenMP/nvptx_allocate_codegen.cpp @@ -91,7 +91,7 @@ void bar() { // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK1-NEXT: store i32 2, i32* @_ZZ4mainE1a, align 4 // CHECK1-NEXT: store double 3.000000e+00, double* [[B]], align 8 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooIiET_v() #[[ATTR7:[0-9]+]] +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z3fooIiET_v() #[[ATTR7:[0-9]+]] // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -117,7 +117,7 @@ void bar() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -127,12 +127,12 @@ void bar() { // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[BAR_A]], align 4 // CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to double // CHECK1-NEXT: store double [[CONV]], double* addrspacecast (double addrspace(3)* @bar_b to double*), align 8 -// CHECK1-NEXT: call void @_Z3bazRf(float* noundef nonnull align 4 dereferenceable(4) [[BAR_A]]) #[[ATTR7]] +// CHECK1-NEXT: call void @_Z3bazRf(float* nonnull align 4 dereferenceable(4) [[BAR_A]]) #[[ATTR7]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/nvptx_data_sharing.cpp b/clang/test/OpenMP/nvptx_data_sharing.cpp index d46cec75e4f4905359a815091a9ce93c294d759f..f6317077d94d9545e6b9f21254f142a7ade8f4c9 100644 --- a/clang/test/OpenMP/nvptx_data_sharing.cpp +++ b/clang/test/OpenMP/nvptx_data_sharing.cpp @@ -427,7 +427,7 @@ void test_ds(){ // // // CHECK-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] { +// CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -441,7 +441,7 @@ void test_ds(){ // // // CHECK-LABEL: define {{[^@]+}}@__omp_outlined___wrapper -// CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -460,7 +460,7 @@ void test_ds(){ // // // CHECK-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] { +// CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -482,7 +482,7 @@ void test_ds(){ // // // CHECK-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/nvptx_declare_target_var_ctor_dtor_codegen.cpp b/clang/test/OpenMP/nvptx_declare_target_var_ctor_dtor_codegen.cpp index 975015cc58276f704422f129ee9b4eaa049c2176..7ed1ae39c4409b3f11c4da3a2c734bc805587f24 100644 --- a/clang/test/OpenMP/nvptx_declare_target_var_ctor_dtor_codegen.cpp +++ b/clang/test/OpenMP/nvptx_declare_target_var_ctor_dtor_codegen.cpp @@ -34,20 +34,20 @@ int car() { return 0; } #pragma omp declare target (bar) int caz() { return 0; } -// DEVICE-DAG: define{{ hidden | }}noundef i32 [[FOO:@.*foo.*]]() -// DEVICE-DAG: define{{ hidden | }}noundef i32 [[BAR:@.*bar.*]]() -// DEVICE-DAG: define{{ hidden | }}noundef i32 [[BAZ:@.*baz.*]]() -// DEVICE-DAG: define{{ hidden | }}noundef i32 [[DOO:@.*doo.*]]() -// DEVICE-DAG: define{{ hidden | }}noundef i32 [[CAR:@.*car.*]]() -// DEVICE-DAG: define{{ hidden | }}noundef i32 [[CAZ:@.*caz.*]]() +// DEVICE-DAG: define{{ hidden | }}i32 [[FOO:@.*foo.*]]() +// DEVICE-DAG: define{{ hidden | }}i32 [[BAR:@.*bar.*]]() +// DEVICE-DAG: define{{ hidden | }}i32 [[BAZ:@.*baz.*]]() +// DEVICE-DAG: define{{ hidden | }}i32 [[DOO:@.*doo.*]]() +// DEVICE-DAG: define{{ hidden | }}i32 [[CAR:@.*car.*]]() +// DEVICE-DAG: define{{ hidden | }}i32 [[CAZ:@.*caz.*]]() static int c = foo() + bar() + baz(); #pragma omp declare target (c) // HOST-DAG: @[[C_CTOR:__omp_offloading__.+_c_l44_ctor]] = private constant i8 0 // DEVICE-DAG: define internal void [[C_CTOR:@__omp_offloading__.+_c_l44_ctor]]() -// DEVICE-DAG: call noundef i32 [[FOO]]() -// DEVICE-DAG: call noundef i32 [[BAR]]() -// DEVICE-DAG: call noundef i32 [[BAZ]]() +// DEVICE-DAG: call i32 [[FOO]]() +// DEVICE-DAG: call i32 [[BAR]]() +// DEVICE-DAG: call i32 [[BAZ]]() // DEVICE-DAG: ret void struct S { @@ -62,9 +62,9 @@ S cd = doo() + car() + caz() + baz(); #pragma omp end declare target // HOST-DAG: @[[CD_CTOR:__omp_offloading__.+_cd_l61_ctor]] = private constant i8 0 // DEVICE-DAG: define internal void [[CD_CTOR:@__omp_offloading__.+_cd_l61_ctor]]() -// DEVICE-DAG: call noundef i32 [[DOO]]() -// DEVICE-DAG: call noundef i32 [[CAR]]() -// DEVICE-DAG: call noundef i32 [[CAZ]]() +// DEVICE-DAG: call i32 [[DOO]]() +// DEVICE-DAG: call i32 [[CAR]]() +// DEVICE-DAG: call i32 [[CAZ]]() // DEVICE-DAG: ret void // HOST-DAG: @[[CD_DTOR:__omp_offloading__.+_cd_l61_dtor]] = private constant i8 0 @@ -91,11 +91,11 @@ int maini1() { return 0; } -// DEVICE-DAG: define weak{{.*}} void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l[[@LINE-7]](i32* noundef nonnull align {{[0-9]+}} dereferenceable{{[^,]*}} +// DEVICE-DAG: define weak{{.*}} void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l[[@LINE-7]](i32* nonnull align {{[0-9]+}} dereferenceable{{[^,]*}} // DEVICE-DAG: [[C:%.+]] = load i32, i32* [[C_ADDR]], // DEVICE-DAG: store i32 [[C]], i32* % -// HOST: define internal void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l[[@LINE-11]](i32* noundef nonnull align {{[0-9]+}} dereferenceable{{.*}}) +// HOST: define internal void @__omp_offloading_{{.*}}_{{.*}}maini1{{.*}}_l[[@LINE-11]](i32* nonnull align {{[0-9]+}} dereferenceable{{.*}}) // HOST: [[C:%.*]] = load i32, i32* @[[C_ADDR]], // HOST: store i32 [[C]], i32* % diff --git a/clang/test/OpenMP/nvptx_declare_variant_name_mangling.cpp b/clang/test/OpenMP/nvptx_declare_variant_name_mangling.cpp index 78f316d288838b93737839c75a596b90ed5aa500..9f685e895254ee371c883ddb971025323c89b915 100644 --- a/clang/test/OpenMP/nvptx_declare_variant_name_mangling.cpp +++ b/clang/test/OpenMP/nvptx_declare_variant_name_mangling.cpp @@ -8,8 +8,8 @@ // CHECK-DAG: @_Z3bazv // CHECK-DAG: define{{.*}} @"_Z53bar$ompvariant$S2$s7$Pnvptx$Pnvptx64$S3$s9$Pmatch_anyv" // CHECK-DAG: define{{.*}} @"_Z53baz$ompvariant$S2$s7$Pnvptx$Pnvptx64$S3$s9$Pmatch_anyv" -// CHECK-DAG: call noundef i32 @"_Z53bar$ompvariant$S2$s7$Pnvptx$Pnvptx64$S3$s9$Pmatch_anyv"() -// CHECK-DAG: call noundef i32 @"_Z53baz$ompvariant$S2$s7$Pnvptx$Pnvptx64$S3$s9$Pmatch_anyv"() +// CHECK-DAG: call i32 @"_Z53bar$ompvariant$S2$s7$Pnvptx$Pnvptx64$S3$s9$Pmatch_anyv"() +// CHECK-DAG: call i32 @"_Z53baz$ompvariant$S2$s7$Pnvptx$Pnvptx64$S3$s9$Pmatch_anyv"() #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp b/clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp index 1442e98e07c43198db90cbee15cb334bb61a79d3..287119f3f6a91166234ddaf2c1f5071ac486e3db 100644 --- a/clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp +++ b/clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp @@ -2974,7 +2974,7 @@ int main(int argc, char **argv) { // CHECK12: omp.precond.end: // CHECK12-NEXT: ret void // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19 -// CHECK4-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[ARGC:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[ARGC:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -3013,7 +3013,7 @@ int main(int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[ARGC:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[ARGC:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3179,7 +3179,7 @@ int main(int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[C:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3259,23 +3259,23 @@ int main(int argc, char **argv) { // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[I6]]) #[[ATTR6:[0-9]+]] -// CHECK4-NEXT: [[CALL9:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[TMP1]]) #[[ATTR6]] +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I6]]) #[[ATTR6:[0-9]+]] +// CHECK4-NEXT: [[CALL9:%.*]] = call i32 @_Z3fooPi(i32* [[TMP1]]) #[[ATTR6]] // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[CALL]], [[CALL9]] // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B4]], i64 0, i64 [[IDXPROM]] -// CHECK4-NEXT: [[CALL11:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARRAYIDX]]) #[[ATTR6]] +// CHECK4-NEXT: [[CALL11:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX]]) #[[ATTR6]] // CHECK4-NEXT: [[ADD12:%.*]] = add nsw i32 [[ADD10]], [[CALL11]] // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[I6]], align 4 // CHECK4-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP20]] to i64 // CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[C5]], i64 0, i64 [[IDXPROM13]] -// CHECK4-NEXT: [[CALL15:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARRAYIDX14]]) #[[ATTR6]] +// CHECK4-NEXT: [[CALL15:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX14]]) #[[ATTR6]] // CHECK4-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD12]], [[CALL15]] // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[I6]], align 4 // CHECK4-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP21]] to i64 // CHECK4-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP4]], i64 0, i64 [[IDXPROM17]] -// CHECK4-NEXT: [[CALL19:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARRAYIDX18]]) #[[ATTR6]] +// CHECK4-NEXT: [[CALL19:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX18]]) #[[ATTR6]] // CHECK4-NEXT: [[ADD20:%.*]] = add nsw i32 [[ADD16]], [[CALL19]] // CHECK4-NEXT: store i32 [[ADD20]], i32* [[TMP1]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -3308,7 +3308,7 @@ int main(int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19 -// CHECK5-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[ARGC:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[ARGC:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -3345,7 +3345,7 @@ int main(int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[ARGC:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[ARGC:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3508,7 +3508,7 @@ int main(int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[C:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3585,20 +3585,20 @@ int main(int argc, char **argv) { // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK5-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[I5]]) #[[ATTR6:[0-9]+]] -// CHECK5-NEXT: [[CALL7:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[TMP1]]) #[[ATTR6]] +// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I5]]) #[[ATTR6:[0-9]+]] +// CHECK5-NEXT: [[CALL7:%.*]] = call i32 @_Z3fooPi(i32* [[TMP1]]) #[[ATTR6]] // CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[CALL]], [[CALL7]] // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B3]], i32 0, i32 [[TMP19]] -// CHECK5-NEXT: [[CALL9:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARRAYIDX]]) #[[ATTR6]] +// CHECK5-NEXT: [[CALL9:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX]]) #[[ATTR6]] // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD8]], [[CALL9]] // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[I5]], align 4 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[C4]], i32 0, i32 [[TMP20]] -// CHECK5-NEXT: [[CALL12:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARRAYIDX11]]) #[[ATTR6]] +// CHECK5-NEXT: [[CALL12:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX11]]) #[[ATTR6]] // CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD10]], [[CALL12]] // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I5]], align 4 // CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP4]], i32 0, i32 [[TMP21]] -// CHECK5-NEXT: [[CALL15:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARRAYIDX14]]) #[[ATTR6]] +// CHECK5-NEXT: [[CALL15:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX14]]) #[[ATTR6]] // CHECK5-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD13]], [[CALL15]] // CHECK5-NEXT: store i32 [[ADD16]], i32* [[TMP1]], align 4 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -3631,7 +3631,7 @@ int main(int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l19 -// CHECK6-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[ARGC:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[ARGC:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -3668,7 +3668,7 @@ int main(int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[ARGC:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[ARGC:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3831,7 +3831,7 @@ int main(int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[C:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[C:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3908,20 +3908,20 @@ int main(int argc, char **argv) { // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK6-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[I5]]) #[[ATTR6:[0-9]+]] -// CHECK6-NEXT: [[CALL7:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[TMP1]]) #[[ATTR6]] +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I5]]) #[[ATTR6:[0-9]+]] +// CHECK6-NEXT: [[CALL7:%.*]] = call i32 @_Z3fooPi(i32* [[TMP1]]) #[[ATTR6]] // CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[CALL]], [[CALL7]] // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B3]], i32 0, i32 [[TMP19]] -// CHECK6-NEXT: [[CALL9:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARRAYIDX]]) #[[ATTR6]] +// CHECK6-NEXT: [[CALL9:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX]]) #[[ATTR6]] // CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD8]], [[CALL9]] // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[I5]], align 4 // CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[C4]], i32 0, i32 [[TMP20]] -// CHECK6-NEXT: [[CALL12:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARRAYIDX11]]) #[[ATTR6]] +// CHECK6-NEXT: [[CALL12:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX11]]) #[[ATTR6]] // CHECK6-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD10]], [[CALL12]] // CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I5]], align 4 // CHECK6-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP4]], i32 0, i32 [[TMP21]] -// CHECK6-NEXT: [[CALL15:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARRAYIDX14]]) #[[ATTR6]] +// CHECK6-NEXT: [[CALL15:%.*]] = call i32 @_Z3fooPi(i32* [[ARRAYIDX14]]) #[[ATTR6]] // CHECK6-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD13]], [[CALL15]] // CHECK6-NEXT: store i32 [[ADD16]], i32* [[TMP1]], align 4 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] diff --git a/clang/test/OpenMP/nvptx_lambda_capturing.cpp b/clang/test/OpenMP/nvptx_lambda_capturing.cpp index 3c6f486dc1da69c9c460a553bec483eed7e68f21..ea59fe8b5aa480c4af21d7c762d0b10c9654e3f7 100644 --- a/clang/test/OpenMP/nvptx_lambda_capturing.cpp +++ b/clang/test/OpenMP/nvptx_lambda_capturing.cpp @@ -47,7 +47,7 @@ int main(int argc, char **argv) { #endif // HEADER // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -341,13 +341,13 @@ int main(int argc, char **argv) { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT11]] // CHECK1: omp_offload.cont11: // CHECK1-NEXT: [[TMP171:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN1S3fooEv(%struct.S* noundef @s) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN1S3fooEv(%struct.S* nonnull align 4 dereferenceable(4) @s) // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP171]], [[CALL]] // CHECK1-NEXT: ret i32 [[ADD]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 -// CHECK1-SAME: (i64 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 @@ -392,12 +392,12 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP10]], i32* [[C7]], align 4 // CHECK1-NEXT: store i32* [[C7]], i32** [[_TMP8]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load %class.anon*, %class.anon** [[_TMP4]], align 8 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[TMP11]]) +// CHECK1-NEXT: [[CALL:%.*]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[TMP11]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 @@ -431,7 +431,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -486,12 +486,12 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[A10]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load %class.anon*, %class.anon** [[_TMP4]], align 8 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[TMP14]]) +// CHECK1-NEXT: [[CALL:%.*]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[TMP14]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1S3fooEv -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR3:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[L:%.*]] = alloca %class.anon.0*, align 8 @@ -588,13 +588,13 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[TMP47:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[TMP48:%.*]] = load %class.anon.0*, %class.anon.0** [[L]], align 8 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooIZN1S3fooEvEUlvE_EiRKT_(%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[TMP48]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooIZN1S3fooEvEUlvE_EiRKT_(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP48]]) // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP47]], [[CALL]] // CHECK1-NEXT: ret i32 [[ADD]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27 -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.S* [[THIS:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[L_ADDR:%.*]] = alloca %class.anon.0*, align 8 @@ -612,12 +612,12 @@ int main(int argc, char **argv) { // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP3]], i8* align 8 [[TMP4]], i64 8, i1 false) // CHECK1-NEXT: store %class.anon.0* [[L1]], %class.anon.0** [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* noundef [[TMP5]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP5]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv -// CHECK1-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR3]] comdat align 2 { +// CHECK1-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR3]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK1-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 @@ -630,7 +630,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29 -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR5]] { +// CHECK1-SAME: (%struct.S* [[THIS:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR5]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[L_ADDR:%.*]] = alloca %class.anon.0*, align 8 @@ -646,7 +646,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S* noundef [[THIS:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S* [[THIS:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -668,12 +668,12 @@ int main(int argc, char **argv) { // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP3]], i8* align 8 [[TMP4]], i64 8, i1 false) // CHECK1-NEXT: store %class.anon.0* [[L1]], %class.anon.0** [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* noundef [[TMP5]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP5]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_Z3fooIZN1S3fooEvEUlvE_EiRKT_ -// CHECK1-SAME: (%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] comdat { +// CHECK1-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca %class.anon.0*, align 8 @@ -715,7 +715,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18 -// CHECK1-SAME: (%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR5]] { +// CHECK1-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR5]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca %class.anon.0*, align 8 @@ -728,7 +728,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -747,7 +747,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP2]], i8* align 8 [[TMP3]], i64 8, i1 false) // CHECK1-NEXT: store %class.anon.0* [[T1]], %class.anon.0** [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* noundef [[TMP4]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP4]]) // CHECK1-NEXT: ret void // // @@ -759,7 +759,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27 -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (%struct.S* [[THIS:%.*]], %class.anon* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[L_ADDR:%.*]] = alloca %class.anon*, align 8 @@ -784,7 +784,7 @@ int main(int argc, char **argv) { // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP6]], i32 0, i32 0 // CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP7]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load %class.anon*, %class.anon** [[_TMP2]], align 8 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon* noundef [[TMP8]]) #[[ATTR6:[0-9]+]] +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon* nonnull align 8 dereferenceable(8) [[TMP8]]) #[[ATTR6:[0-9]+]] // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -792,7 +792,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv -// CHECK2-SAME: (%class.anon* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%class.anon* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon*, align 8 // CHECK2-NEXT: store %class.anon* [[THIS]], %class.anon** [[THIS_ADDR]], align 8 @@ -805,7 +805,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29 -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (%struct.S* [[THIS:%.*]], %class.anon* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[L_ADDR:%.*]] = alloca %class.anon*, align 8 @@ -837,7 +837,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S* noundef [[THIS:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S* [[THIS:%.*]], %class.anon* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -862,12 +862,12 @@ int main(int argc, char **argv) { // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP5]], i32 0, i32 0 // CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load %class.anon*, %class.anon** [[_TMP2]], align 8 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon* noundef [[TMP7]]) #[[ATTR6]] +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon* nonnull align 8 dereferenceable(8) [[TMP7]]) #[[ATTR6]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 -// CHECK2-SAME: (i64 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon.0* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 @@ -929,7 +929,7 @@ int main(int argc, char **argv) { // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[TMP12]], i32 0, i32 4 // CHECK2-NEXT: store i32* [[TMP2]], i32** [[TMP19]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP4]], align 8 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(%class.anon.0* noundef [[TMP20]]) #[[ATTR6]] +// CHECK2-NEXT: [[CALL:%.*]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon.0* nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR6]] // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -937,7 +937,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon.0* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 @@ -999,7 +999,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon.0* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1067,12 +1067,12 @@ int main(int argc, char **argv) { // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[TMP14]], i32 0, i32 4 // CHECK2-NEXT: store i32* [[A10]], i32** [[TMP21]], align 8 // CHECK2-NEXT: [[TMP22:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP4]], align 8 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(%class.anon.0* noundef [[TMP22]]) #[[ATTR6]] +// CHECK2-NEXT: [[CALL:%.*]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon.0* nonnull align 8 dereferenceable(40) [[TMP22]]) #[[ATTR6]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18 -// CHECK2-SAME: (%class.anon* noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (%class.anon* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_ADDR:%.*]] = alloca %class.anon*, align 8 // CHECK2-NEXT: [[TMP:%.*]] = alloca %class.anon*, align 8 @@ -1098,7 +1098,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %class.anon* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1118,12 +1118,12 @@ int main(int argc, char **argv) { // CHECK2-NEXT: store %class.anon* [[T1]], %class.anon** [[_TMP2]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load %class.anon*, %class.anon** [[_TMP2]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load %class.anon*, %class.anon** [[_TMP2]], align 8 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon* noundef [[TMP5]]) #[[ATTR6]] +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon* nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR6]] // CHECK2-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 -// CHECK3-SAME: (i64 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 @@ -1185,7 +1185,7 @@ int main(int argc, char **argv) { // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP12]], i32 0, i32 4 // CHECK3-NEXT: store i32* [[TMP2]], i32** [[TMP19]], align 8 // CHECK3-NEXT: [[TMP20:%.*]] = load %class.anon*, %class.anon** [[_TMP4]], align 8 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[TMP20]]) #[[ATTR6:[0-9]+]] +// CHECK3-NEXT: [[CALL:%.*]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR6:[0-9]+]] // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK3-NEXT: ret void // CHECK3: worker.exit: @@ -1193,7 +1193,7 @@ int main(int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 @@ -1255,7 +1255,7 @@ int main(int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1323,12 +1323,12 @@ int main(int argc, char **argv) { // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP14]], i32 0, i32 4 // CHECK3-NEXT: store i32* [[A10]], i32** [[TMP21]], align 8 // CHECK3-NEXT: [[TMP22:%.*]] = load %class.anon*, %class.anon** [[_TMP4]], align 8 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[TMP22]]) #[[ATTR6]] +// CHECK3-NEXT: [[CALL:%.*]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[TMP22]]) #[[ATTR6]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27 -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (%struct.S* [[THIS:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[L_ADDR:%.*]] = alloca %class.anon.0*, align 8 @@ -1353,7 +1353,7 @@ int main(int argc, char **argv) { // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[TMP6]], i32 0, i32 0 // CHECK3-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP7]], align 8 // CHECK3-NEXT: [[TMP8:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* noundef [[TMP8]]) #[[ATTR6]] +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP8]]) #[[ATTR6]] // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK3-NEXT: ret void // CHECK3: worker.exit: @@ -1361,7 +1361,7 @@ int main(int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv -// CHECK3-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK3-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 @@ -1374,7 +1374,7 @@ int main(int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29 -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (%struct.S* [[THIS:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[L_ADDR:%.*]] = alloca %class.anon.0*, align 8 @@ -1406,7 +1406,7 @@ int main(int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S* noundef [[THIS:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S* [[THIS:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1431,12 +1431,12 @@ int main(int argc, char **argv) { // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[TMP5]], i32 0, i32 0 // CHECK3-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8 // CHECK3-NEXT: [[TMP7:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* noundef [[TMP7]]) #[[ATTR6]] +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP7]]) #[[ATTR6]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18 -// CHECK3-SAME: (%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK3-NEXT: [[TMP:%.*]] = alloca %class.anon.0*, align 8 @@ -1462,7 +1462,7 @@ int main(int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1482,12 +1482,12 @@ int main(int argc, char **argv) { // CHECK3-NEXT: store %class.anon.0* [[T1]], %class.anon.0** [[_TMP2]], align 8 // CHECK3-NEXT: [[TMP4:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 // CHECK3-NEXT: [[TMP5:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* noundef [[TMP5]]) #[[ATTR6]] +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR6]] // CHECK3-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 -// CHECK4-SAME: (i64 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 @@ -1549,7 +1549,7 @@ int main(int argc, char **argv) { // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP12]], i32 0, i32 4 // CHECK4-NEXT: store i32* [[TMP2]], i32** [[TMP19]], align 8 // CHECK4-NEXT: [[TMP20:%.*]] = load %class.anon*, %class.anon** [[_TMP4]], align 8 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[TMP20]]) #[[ATTR6:[0-9]+]] +// CHECK4-NEXT: [[CALL:%.*]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR6:[0-9]+]] // CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK4-NEXT: ret void // CHECK4: worker.exit: @@ -1557,7 +1557,7 @@ int main(int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32*, align 8 @@ -1619,7 +1619,7 @@ int main(int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i32* noundef [[D:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i32* [[D:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], %class.anon* nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1687,12 +1687,12 @@ int main(int argc, char **argv) { // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[TMP14]], i32 0, i32 4 // CHECK4-NEXT: store i32* [[A10]], i32** [[TMP21]], align 8 // CHECK4-NEXT: [[TMP22:%.*]] = load %class.anon*, %class.anon** [[_TMP4]], align 8 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[TMP22]]) #[[ATTR6]] +// CHECK4-NEXT: [[CALL:%.*]] = call i64 @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(40) [[TMP22]]) #[[ATTR6]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27 -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (%struct.S* [[THIS:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[L_ADDR:%.*]] = alloca %class.anon.0*, align 8 @@ -1717,7 +1717,7 @@ int main(int argc, char **argv) { // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[TMP6]], i32 0, i32 0 // CHECK4-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP7]], align 8 // CHECK4-NEXT: [[TMP8:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* noundef [[TMP8]]) #[[ATTR6]] +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP8]]) #[[ATTR6]] // CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true) // CHECK4-NEXT: ret void // CHECK4: worker.exit: @@ -1725,7 +1725,7 @@ int main(int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv -// CHECK4-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK4-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 @@ -1738,7 +1738,7 @@ int main(int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29 -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (%struct.S* [[THIS:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[L_ADDR:%.*]] = alloca %class.anon.0*, align 8 @@ -1770,7 +1770,7 @@ int main(int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S* noundef [[THIS:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S* [[THIS:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1795,12 +1795,12 @@ int main(int argc, char **argv) { // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[TMP5]], i32 0, i32 0 // CHECK4-NEXT: store %struct.S* [[TMP0]], %struct.S** [[TMP6]], align 8 // CHECK4-NEXT: [[TMP7:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* noundef [[TMP7]]) #[[ATTR6]] +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP7]]) #[[ATTR6]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18 -// CHECK4-SAME: (%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (%class.anon.0* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK4-NEXT: [[TMP:%.*]] = alloca %class.anon.0*, align 8 @@ -1826,7 +1826,7 @@ int main(int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %class.anon.0* noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %class.anon.0* nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1846,6 +1846,6 @@ int main(int argc, char **argv) { // CHECK4-NEXT: store %class.anon.0* [[T1]], %class.anon.0** [[_TMP2]], align 8 // CHECK4-NEXT: [[TMP4:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = load %class.anon.0*, %class.anon.0** [[_TMP2]], align 8 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* noundef [[TMP5]]) #[[ATTR6]] +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZZN1S3fooEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR6]] // CHECK4-NEXT: ret void // diff --git a/clang/test/OpenMP/nvptx_multi_target_parallel_codegen.cpp b/clang/test/OpenMP/nvptx_multi_target_parallel_codegen.cpp index b866634d0cb5015e50c66c82e7dd0a58f5f22555..52a500e892286d2eac7203917ed16e39c29254e8 100644 --- a/clang/test/OpenMP/nvptx_multi_target_parallel_codegen.cpp +++ b/clang/test/OpenMP/nvptx_multi_target_parallel_codegen.cpp @@ -43,7 +43,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -78,7 +78,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -89,7 +89,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -121,7 +121,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -156,7 +156,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -167,7 +167,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -199,7 +199,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -234,7 +234,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -245,7 +245,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK3-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/nvptx_nested_parallel_codegen.cpp b/clang/test/OpenMP/nvptx_nested_parallel_codegen.cpp index 69806d04a2aa3dc136706ace146b1fc7dc98ab4f..6c70478dbc0c6f109d83ff3a0db0f54f15efe21f 100644 --- a/clang/test/OpenMP/nvptx_nested_parallel_codegen.cpp +++ b/clang/test/OpenMP/nvptx_nested_parallel_codegen.cpp @@ -34,7 +34,7 @@ int main() { #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 @@ -45,7 +45,7 @@ int main() { // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1: user_code.entry: // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK1-NEXT: call void @_Z3usePi(i32* noundef [[TMP0]]) #[[ATTR6:[0-9]+]] +// CHECK1-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR6:[0-9]+]] // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 2) // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8* @@ -59,7 +59,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z3usePi -// CHECK1-SAME: (i32* noundef [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 @@ -75,7 +75,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -84,12 +84,12 @@ int main() { // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 8 -// CHECK1-NEXT: call void @_Z3usePi(i32* noundef [[TMP0]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR6]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -108,7 +108,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -118,12 +118,12 @@ int main() { // CHECK1-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP0]], align 8 -// CHECK1-NEXT: call void @_Z4workPi(i32* noundef [[TMP1]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_Z4workPi(i32* [[TMP1]]) #[[ATTR6]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_Z4workPi -// CHECK1-SAME: (i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* [[C:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4 @@ -132,7 +132,7 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8* -// CHECK1-NEXT: call void @__atomic_load(i64 noundef 4, i8* noundef [[TMP1]], i8* noundef [[TMP2]], i32 noundef 0) #[[ATTR6]] +// CHECK1-NEXT: call void @__atomic_load(i64 4, i8* [[TMP1]], i8* [[TMP2]], i32 0) #[[ATTR6]] // CHECK1-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK1: atomic_cont: // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ATOMIC_TEMP]], align 4 @@ -141,14 +141,14 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8* // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i32* [[ATOMIC_TEMP1]] to i8* -// CHECK1-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 4, i8* noundef [[TMP4]], i8* noundef [[TMP5]], i8* noundef [[TMP6]], i32 noundef 0, i32 noundef 0) #[[ATTR6]] +// CHECK1-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 4, i8* [[TMP4]], i8* [[TMP5]], i8* [[TMP6]], i32 0, i32 0) #[[ATTR6]] // CHECK1-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK1: atomic_exit: // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -167,7 +167,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -178,7 +178,7 @@ int main() { // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK2: user_code.entry: // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK2-NEXT: call void @_Z3usePi(i32* noundef [[TMP0]]) #[[ATTR6:[0-9]+]] +// CHECK2-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR6:[0-9]+]] // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 2) // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8* @@ -192,7 +192,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z3usePi -// CHECK2-SAME: (i32* noundef [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -208,7 +208,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -217,12 +217,12 @@ int main() { // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK2-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4 -// CHECK2-NEXT: call void @_Z3usePi(i32* noundef [[TMP0]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR6]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined___wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -241,7 +241,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -251,12 +251,12 @@ int main() { // CHECK2-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP0]], align 4 -// CHECK2-NEXT: call void @_Z4workPi(i32* noundef [[TMP1]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_Z4workPi(i32* [[TMP1]]) #[[ATTR6]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_Z4workPi -// CHECK2-SAME: (i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* [[C:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4 @@ -265,7 +265,7 @@ int main() { // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8* -// CHECK2-NEXT: call void @__atomic_load(i32 noundef 4, i8* noundef [[TMP1]], i8* noundef [[TMP2]], i32 noundef 0) #[[ATTR6]] +// CHECK2-NEXT: call void @__atomic_load(i32 4, i8* [[TMP1]], i8* [[TMP2]], i32 0) #[[ATTR6]] // CHECK2-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK2: atomic_cont: // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ATOMIC_TEMP]], align 4 @@ -274,14 +274,14 @@ int main() { // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8* // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i32* [[ATOMIC_TEMP1]] to i8* -// CHECK2-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i32 noundef 4, i8* noundef [[TMP4]], i8* noundef [[TMP5]], i8* noundef [[TMP6]], i32 noundef 0, i32 noundef 0) #[[ATTR6]] +// CHECK2-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 4, i8* [[TMP4]], i8* [[TMP5]], i8* [[TMP6]], i32 0, i32 0) #[[ATTR6]] // CHECK2-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK2: atomic_exit: // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -300,7 +300,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -311,7 +311,7 @@ int main() { // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK3: user_code.entry: // CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) -// CHECK3-NEXT: call void @_Z3usePi(i32* noundef [[TMP0]]) #[[ATTR6:[0-9]+]] +// CHECK3-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR6:[0-9]+]] // CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 2) // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8* @@ -325,7 +325,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z3usePi -// CHECK3-SAME: (i32* noundef [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32* [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -341,7 +341,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -350,12 +350,12 @@ int main() { // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store i32* [[C]], i32** [[C_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4 -// CHECK3-NEXT: call void @_Z3usePi(i32* noundef [[TMP0]]) #[[ATTR6]] +// CHECK3-NEXT: call void @_Z3usePi(i32* [[TMP0]]) #[[ATTR6]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined___wrapper -// CHECK3-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -374,7 +374,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32** noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -384,12 +384,12 @@ int main() { // CHECK3-NEXT: store i32** [[C]], i32*** [[C_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[C_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP0]], align 4 -// CHECK3-NEXT: call void @_Z4workPi(i32* noundef [[TMP1]]) #[[ATTR6]] +// CHECK3-NEXT: call void @_Z4workPi(i32* [[TMP1]]) #[[ATTR6]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_Z4workPi -// CHECK3-SAME: (i32* noundef [[C:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* [[C:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4 @@ -398,7 +398,7 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[C_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK3-NEXT: [[TMP2:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8* -// CHECK3-NEXT: call void @__atomic_load(i32 noundef 4, i8* noundef [[TMP1]], i8* noundef [[TMP2]], i32 noundef 0) #[[ATTR6]] +// CHECK3-NEXT: call void @__atomic_load(i32 4, i8* [[TMP1]], i8* [[TMP2]], i32 0) #[[ATTR6]] // CHECK3-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK3: atomic_cont: // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ATOMIC_TEMP]], align 4 @@ -407,14 +407,14 @@ int main() { // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP0]] to i8* // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i32* [[ATOMIC_TEMP]] to i8* // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i32* [[ATOMIC_TEMP1]] to i8* -// CHECK3-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i32 noundef 4, i8* noundef [[TMP4]], i8* noundef [[TMP5]], i8* noundef [[TMP6]], i32 noundef 0, i32 noundef 0) #[[ATTR6]] +// CHECK3-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 4, i8* [[TMP4]], i8* [[TMP5]], i8* [[TMP6]], i32 0, i32 0) #[[ATTR6]] // CHECK3-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK3: atomic_exit: // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK3-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/nvptx_parallel_codegen.cpp b/clang/test/OpenMP/nvptx_parallel_codegen.cpp index dcf099f7006ef73168c0d51605848cb1b47d8804..48fb62f9f2c89ce2880f018cb71a01d8392ef9eb 100644 --- a/clang/test/OpenMP/nvptx_parallel_codegen.cpp +++ b/clang/test/OpenMP/nvptx_parallel_codegen.cpp @@ -1438,7 +1438,7 @@ int bar(int n){ // CHECK5-NEXT: call void @__omp_outlined__4(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3]] // CHECK5-NEXT: ret void // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 @@ -1467,7 +1467,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1479,7 +1479,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1494,7 +1494,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1506,7 +1506,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1521,7 +1521,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1533,7 +1533,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1548,7 +1548,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43 -// CHECK1-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -1592,7 +1592,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1607,7 +1607,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1622,7 +1622,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 @@ -1653,7 +1653,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1695,7 +1695,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4_wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1714,7 +1714,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26 -// CHECK2-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 4 @@ -1742,7 +1742,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1754,7 +1754,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined___wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1769,7 +1769,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1781,7 +1781,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1796,7 +1796,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1808,7 +1808,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1823,7 +1823,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l43 -// CHECK2-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1865,7 +1865,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1880,7 +1880,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -1895,7 +1895,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55 -// CHECK2-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -1925,7 +1925,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1967,7 +1967,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4_wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/nvptx_parallel_for_codegen.cpp b/clang/test/OpenMP/nvptx_parallel_for_codegen.cpp index b9bc6b2041b5cafb41803a6aa2b7c9ea174956f1..fdd3cd6db8cf31625f2c42193ef30a23b8286c66 100644 --- a/clang/test/OpenMP/nvptx_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/nvptx_parallel_for_codegen.cpp @@ -456,7 +456,7 @@ int bar(int n){ // CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], [10 x i32]* [[TMP5]], i32* [[TMP8]]) #[[ATTR3]] // CHECK2-NEXT: ret void // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l13 -// CHECK-SAME: (i64 noundef [[N:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-SAME: (i64 [[N:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -494,7 +494,7 @@ int bar(int n){ // // // CHECK-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -584,7 +584,7 @@ int bar(int n){ // // // CHECK-LABEL: define {{[^@]+}}@__omp_outlined___wrapper -// CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/nvptx_target_codegen.cpp b/clang/test/OpenMP/nvptx_target_codegen.cpp index 19866cf303f9faa940c0e93660d96b05c597a882..b3f0746c1eae075c44af6aeed53e18bd914a9c22 100644 --- a/clang/test/OpenMP/nvptx_target_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_codegen.cpp @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK3 // expected-no-diagnostics #ifndef HEADER diff --git a/clang/test/OpenMP/nvptx_target_firstprivate_codegen.cpp b/clang/test/OpenMP/nvptx_target_firstprivate_codegen.cpp index 18265ef2ec2bc2cbd3e67388656fe8b0a8ddac51..b37d25922b7e009a1bd381e5f05ab1b3800bb6b8 100644 --- a/clang/test/OpenMP/nvptx_target_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_firstprivate_codegen.cpp @@ -33,7 +33,7 @@ int foo(int n, double *ptr) { b[a] += e.X; } - // TCHECK: define {{.*}}void @__omp_offloading_{{.+}}([10 x float] addrspace(1)* noalias noundef [[B_IN:%.+]], i{{[0-9]+}} noundef [[A_IN:%.+]], [[TTII]]* noalias noundef [[E_IN:%.+]]) + // TCHECK: define {{.*}}void @__omp_offloading_{{.+}}([10 x float] addrspace(1)* noalias [[B_IN:%.+]], i{{[0-9]+}} [[A_IN:%.+]], [[TTII]]* noalias [[E_IN:%.+]]) // TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK-NOT: alloca [[TTII]], // TCHECK: alloca i{{[0-9]+}}, @@ -95,7 +95,7 @@ int foo(int n, double *ptr) { ptr[0]++; } - // TCHECK: define weak void @__omp_offloading_{{.+}}(double* noundef [[PTR_IN:%.+]]) + // TCHECK: define weak void @__omp_offloading_{{.+}}(double* [[PTR_IN:%.+]]) // TCHECK: [[PTR_ADDR:%.+]] = alloca double*, // TCHECK-NOT: alloca double*, // TCHECK: store double* [[PTR_IN]], double** [[PTR_ADDR]], @@ -179,7 +179,7 @@ struct S1 { return (int)b; } - // TCHECK: define internal void @__omp_offloading_{{.+}}([[S1]]* noundef [[TH:%.+]], i{{[0-9]+}} noundef [[B_IN:%.+]]) + // TCHECK: define internal void @__omp_offloading_{{.+}}([[S1]]* [[TH:%.+]], i{{[0-9]+}} [[B_IN:%.+]]) // TCHECK: [[TH_ADDR:%.+]] = alloca [[S1]]*, // TCHECK: [[B_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK-NOT: alloca i{{[0-9]+}}, @@ -211,7 +211,7 @@ int bar(int n, double *ptr) { // template -// TCHECK: define internal void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} noundef [[B_IN:%.+]]) +// TCHECK: define internal void @__omp_offloading_{{.+}}(i{{[0-9]+}} [[A_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} [[B_IN:%.+]]) // TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[B_ADDR:%.+]] = alloca [10 x i{{[0-9]+}}]*, // TCHECK-NOT: alloca i{{[0-9]+}}, diff --git a/clang/test/OpenMP/nvptx_target_parallel_codegen.cpp b/clang/test/OpenMP/nvptx_target_parallel_codegen.cpp index 191df1ea669cd1c3b1c7365b810f8c1acf616aeb..cbf44c5060336a6d51aab56ada1a2b8723ab0f63 100644 --- a/clang/test/OpenMP/nvptx_target_parallel_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_parallel_codegen.cpp @@ -52,7 +52,7 @@ int bar(int n){ #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK1-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 @@ -75,7 +75,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -93,7 +93,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 @@ -128,7 +128,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -159,7 +159,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK2-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -182,7 +182,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -200,7 +200,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 @@ -235,7 +235,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -266,7 +266,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK3-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -289,7 +289,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -307,7 +307,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 @@ -342,7 +342,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -373,7 +373,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK4-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 // CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 @@ -396,7 +396,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -414,7 +414,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 @@ -449,7 +449,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -480,7 +480,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK5-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 // CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -503,7 +503,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -521,7 +521,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35 -// CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 @@ -556,7 +556,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -587,7 +587,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK6-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 // CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -610,7 +610,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -628,7 +628,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l35 -// CHECK6-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 @@ -663,7 +663,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp b/clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp index 75ab2d94bde91286004c4acbb2c722b56c797f3a..fb1e427cfed72fb2e3993c7abffcf561171015c1 100644 --- a/clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp @@ -47,7 +47,7 @@ int bar(int n){ #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25 -// CHECK1-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 @@ -70,7 +70,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -88,7 +88,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 @@ -127,7 +127,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -158,7 +158,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25 -// CHECK2-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -181,7 +181,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -199,7 +199,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 @@ -237,7 +237,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -268,7 +268,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25 -// CHECK3-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -291,7 +291,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -309,7 +309,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 @@ -347,7 +347,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -378,7 +378,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25 -// CHECK4-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 // CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 @@ -401,7 +401,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -419,7 +419,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 @@ -458,7 +458,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -489,7 +489,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25 -// CHECK5-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 // CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -512,7 +512,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -530,7 +530,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 @@ -568,7 +568,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -599,7 +599,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25 -// CHECK6-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-SAME: (i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 // CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 @@ -622,7 +622,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -640,7 +640,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 -// CHECK6-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 @@ -678,7 +678,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/nvptx_target_parallel_reduction_codegen.cpp b/clang/test/OpenMP/nvptx_target_parallel_reduction_codegen.cpp index bba2367207e7fad91fbf795b31814b3aaf59d3a2..9bb6b15536d7e27f3bd1a4002de42dc68e8933b3 100644 --- a/clang/test/OpenMP/nvptx_target_parallel_reduction_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_parallel_reduction_codegen.cpp @@ -82,7 +82,7 @@ int bar(int n){ // // Reduction function -// CHECK: define internal void [[REDUCTION_FUNC:@.+]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void [[REDUCTION_FUNC:@.+]](i8* %0, i8* %1) // CHECK: [[VAR_RHS_REF:%.+]] = getelementptr inbounds [[RLT]], [[RLT]]* [[RED_LIST_RHS:%.+]], i{{32|64}} 0, i{{32|64}} 0 // CHECK: [[VAR_RHS_VOID:%.+]] = load i8*, i8** [[VAR_RHS_REF]], // CHECK: [[VAR_RHS:%.+]] = bitcast i8* [[VAR_RHS_VOID]] to double* @@ -99,7 +99,7 @@ int bar(int n){ // // Shuffle and reduce function -// CHECK: define internal void [[SHUFFLE_REDUCE_FN]](i8* noundef %0, i16 noundef {{.*}}, i16 noundef {{.*}}, i16 noundef {{.*}}) +// CHECK: define internal void [[SHUFFLE_REDUCE_FN]](i8* %0, i16 {{.*}}, i16 {{.*}}, i16 {{.*}}) // CHECK: [[REMOTE_RED_LIST:%.+]] = alloca [[RLT]], align // CHECK: [[REMOTE_ELT:%.+]] = alloca double // @@ -176,7 +176,7 @@ int bar(int n){ // // Inter warp copy function -// CHECK: define internal void [[WARP_COPY_FN]](i8* noundef %0, i32 noundef %1) +// CHECK: define internal void [[WARP_COPY_FN]](i8* %0, i32 %1) // CHECK-DAG: [[LANEID:%.+]] = and i32 {{.+}}, 31 // CHECK-DAG: [[WARPID:%.+]] = ashr i32 {{.+}}, 5 // CHECK-DAG: [[RED_LIST:%.+]] = bitcast i8* {{.+}} to [[RLT]]* @@ -274,7 +274,7 @@ int bar(int n){ // // Reduction function -// CHECK: define internal void [[REDUCTION_FUNC:@.+]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void [[REDUCTION_FUNC:@.+]](i8* %0, i8* %1) // CHECK: [[VAR1_RHS_REF:%.+]] = getelementptr inbounds [[RLT]], [[RLT]]* [[RED_LIST_RHS:%.+]], i{{32|64}} 0, i{{32|64}} 0 // CHECK: [[VAR1_RHS:%.+]] = load i8*, i8** [[VAR1_RHS_REF]], // @@ -305,7 +305,7 @@ int bar(int n){ // // Shuffle and reduce function -// CHECK: define internal void [[SHUFFLE_REDUCE_FN]](i8* noundef %0, i16 noundef {{.*}}, i16 noundef {{.*}}, i16 noundef {{.*}}) +// CHECK: define internal void [[SHUFFLE_REDUCE_FN]](i8* %0, i16 {{.*}}, i16 {{.*}}, i16 {{.*}}) // CHECK: [[REMOTE_RED_LIST:%.+]] = alloca [[RLT]], align // CHECK: [[REMOTE_ELT1:%.+]] = alloca i8 // CHECK: [[REMOTE_ELT2:%.+]] = alloca float @@ -404,7 +404,7 @@ int bar(int n){ // // Inter warp copy function -// CHECK: define internal void [[WARP_COPY_FN]](i8* noundef %0, i32 noundef %1) +// CHECK: define internal void [[WARP_COPY_FN]](i8* %0, i32 %1) // CHECK-DAG: [[LANEID:%.+]] = and i32 {{.+}}, 31 // CHECK-DAG: [[WARPID:%.+]] = ashr i32 {{.+}}, 5 // CHECK-DAG: [[RED_LIST:%.+]] = bitcast i8* {{.+}} to [[RLT]]* @@ -557,7 +557,7 @@ int bar(int n){ // // Reduction function -// CHECK: define internal void [[REDUCTION_FUNC:@.+]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void [[REDUCTION_FUNC:@.+]](i8* %0, i8* %1) // CHECK: [[VAR1_RHS_REF:%.+]] = getelementptr inbounds [[RLT]], [[RLT]]* [[RED_LIST_RHS:%.+]], i{{32|64}} 0, i{{32|64}} 0 // CHECK: [[VAR1_RHS_VOID:%.+]] = load i8*, i8** [[VAR1_RHS_REF]], // CHECK: [[VAR1_RHS:%.+]] = bitcast i8* [[VAR1_RHS_VOID]] to i32* @@ -602,7 +602,7 @@ int bar(int n){ // // Shuffle and reduce function -// CHECK: define internal void [[SHUFFLE_REDUCE_FN]](i8* noundef %0, i16 noundef {{.*}}, i16 noundef {{.*}}, i16 noundef {{.*}}) +// CHECK: define internal void [[SHUFFLE_REDUCE_FN]](i8* %0, i16 {{.*}}, i16 {{.*}}, i16 {{.*}}) // CHECK: [[REMOTE_RED_LIST:%.+]] = alloca [[RLT]], align // CHECK: [[REMOTE_ELT1:%.+]] = alloca i32 // CHECK: [[REMOTE_ELT2:%.+]] = alloca i16 @@ -703,7 +703,7 @@ int bar(int n){ // // Inter warp copy function -// CHECK: define internal void [[WARP_COPY_FN]](i8* noundef %0, i32 noundef %1) +// CHECK: define internal void [[WARP_COPY_FN]](i8* %0, i32 %1) // CHECK-DAG: [[LANEID:%.+]] = and i32 {{.+}}, 31 // CHECK-DAG: [[WARPID:%.+]] = ashr i32 {{.+}}, 5 // CHECK-DAG: [[RED_LIST:%.+]] = bitcast i8* {{.+}} to [[RLT]]* diff --git a/clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp b/clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp index ad8078a752267e4220c1f0d5a00551c9db064d4b..207068081b661796bbef7cd04d1ef68f7122ed0c 100644 --- a/clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp +++ b/clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -disable-noundef-analysis -x c++ -O1 -disable-llvm-optzns -verify -fopenmp -internal-isystem %S/../Headers/Inputs/include -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -disable-noundef-analysis -x c++ -O1 -disable-llvm-optzns -verify -fopenmp -internal-isystem %S/../Headers/Inputs/include -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -triple nvptx64-unknown-unknown -aux-triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -disable-noundef-analysis -x c++ -O1 -disable-llvm-optzns -verify -fopenmp -internal-isystem %S/../Headers/Inputs/include -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -disable-noundef-analysis -x c++ -O1 -disable-llvm-optzns -verify -fopenmp -internal-isystem %S/../Headers/Inputs/include -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -triple nvptx64-unknown-unknown -aux-triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -disable-noundef-analysis -x c++ -O1 -disable-llvm-optzns -verify -fopenmp -internal-isystem %S/../Headers/Inputs/include -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -fexceptions -fcxx-exceptions -aux-triple powerpc64le-unknown-unknown -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -x c++ -O1 -disable-llvm-optzns -verify -fopenmp -internal-isystem %S/../Headers/Inputs/include -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -x c++ -O1 -disable-llvm-optzns -verify -fopenmp -internal-isystem %S/../Headers/Inputs/include -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -triple nvptx64-unknown-unknown -aux-triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -x c++ -O1 -disable-llvm-optzns -verify -fopenmp -internal-isystem %S/../Headers/Inputs/include -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -x c++ -O1 -disable-llvm-optzns -verify -fopenmp -internal-isystem %S/../Headers/Inputs/include -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -triple nvptx64-unknown-unknown -aux-triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -x c++ -O1 -disable-llvm-optzns -verify -fopenmp -internal-isystem %S/../Headers/Inputs/include -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -fexceptions -fcxx-exceptions -aux-triple powerpc64le-unknown-unknown -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK3 // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/nvptx_target_printf_codegen.c b/clang/test/OpenMP/nvptx_target_printf_codegen.c index 5aa1864a045e6f47c57b551b4a44cb0d132ffeef..361943138c32c0457e08eaed9f0dcce143a1a996 100644 --- a/clang/test/OpenMP/nvptx_target_printf_codegen.c +++ b/clang/test/OpenMP/nvptx_target_printf_codegen.c @@ -83,7 +83,7 @@ void CheckAllocaIsInEntryBlock() { // // // CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckAllocaIsInEntryBlock_l36 -// CHECK-64-SAME: (i64 noundef [[FOO:%.*]]) #[[ATTR0]] { +// CHECK-64-SAME: (i64 [[FOO:%.*]]) #[[ATTR0]] { // CHECK-64-NEXT: entry: // CHECK-64-NEXT: [[FOO_ADDR:%.*]] = alloca i64, align 8 // CHECK-64-NEXT: [[TMP:%.*]] = alloca [[PRINTF_ARGS_0:%.*]], align 8 @@ -152,7 +152,7 @@ void CheckAllocaIsInEntryBlock() { // // // CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_CheckAllocaIsInEntryBlock_l36 -// CHECK-32-SAME: (i32 noundef [[FOO:%.*]]) #[[ATTR0]] { +// CHECK-32-SAME: (i32 [[FOO:%.*]]) #[[ATTR0]] { // CHECK-32-NEXT: entry: // CHECK-32-NEXT: [[FOO_ADDR:%.*]] = alloca i32, align 4 // CHECK-32-NEXT: [[TMP:%.*]] = alloca [[PRINTF_ARGS_0:%.*]], align 8 diff --git a/clang/test/OpenMP/nvptx_target_teams_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_codegen.cpp index 209973153e98edb424388617aaf1318b9b7b9304..fbe62f191eec617123c02de532d6e0fbdc04028a 100644 --- a/clang/test/OpenMP/nvptx_target_teams_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_codegen.cpp @@ -50,7 +50,7 @@ int bar(int n){ #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l23 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -77,7 +77,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -91,7 +91,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28 -// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -118,7 +118,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -132,7 +132,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33 -// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -159,7 +159,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -180,7 +180,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -201,7 +201,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -215,7 +215,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l23 -// CHECK2-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -242,7 +242,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -256,7 +256,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28 -// CHECK2-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -283,7 +283,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -297,7 +297,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33 -// CHECK2-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -324,7 +324,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -345,7 +345,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -366,7 +366,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -380,7 +380,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l23 -// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -407,7 +407,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -421,7 +421,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l28 -// CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -448,7 +448,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -462,7 +462,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33 -// CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -489,7 +489,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -510,7 +510,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -531,7 +531,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_codegen.cpp index 55c6d373ca7e24740d230b5b4462e64f6483d0ea..6bf279444adb76523c19043f998137f265869eff 100644 --- a/clang/test/OpenMP/nvptx_target_teams_distribute_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_distribute_codegen.cpp @@ -594,7 +594,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -662,7 +662,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -678,7 +678,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -716,7 +716,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -784,7 +784,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -800,7 +800,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -838,7 +838,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -906,7 +906,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -922,7 +922,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper -// CHECK3-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp index c37489d99bb58db92577fd2a8cfe57919bc0cd47..d0b57801530b6b1d782709e7d74f13f1cea44d6a 100644 --- a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp @@ -18468,7 +18468,7 @@ int bar(int n){ // CHECK16: omp.precond.end: // CHECK16-NEXT: ret void // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -18506,7 +18506,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18661,7 +18661,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18795,7 +18795,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 8 @@ -18825,7 +18825,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18959,7 +18959,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19054,7 +19054,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39 -// CHECK1-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -19076,7 +19076,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19171,7 +19171,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19241,7 +19241,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44 -// CHECK1-SAME: ([10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: ([10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 // CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8 @@ -19271,7 +19271,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19380,7 +19380,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19474,7 +19474,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 @@ -19504,7 +19504,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19654,7 +19654,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19791,7 +19791,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -19824,7 +19824,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19964,7 +19964,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20062,7 +20062,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28 -// CHECK2-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -20100,7 +20100,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20255,7 +20255,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20389,7 +20389,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34 -// CHECK2-SAME: (i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 8 @@ -20419,7 +20419,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20553,7 +20553,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20648,7 +20648,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39 -// CHECK2-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -20670,7 +20670,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20765,7 +20765,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20835,7 +20835,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44 -// CHECK2-SAME: ([10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: ([10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 // CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8 @@ -20865,7 +20865,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20974,7 +20974,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21068,7 +21068,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52 -// CHECK2-SAME: (i64 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i64 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 @@ -21098,7 +21098,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21247,7 +21247,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21380,7 +21380,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59 -// CHECK2-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -21413,7 +21413,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21553,7 +21553,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21651,7 +21651,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28 -// CHECK3-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -21685,7 +21685,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21834,7 +21834,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21961,7 +21961,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34 -// CHECK3-SAME: (i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 4 @@ -21989,7 +21989,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22119,7 +22119,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22209,7 +22209,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39 -// CHECK3-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -22231,7 +22231,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22324,7 +22324,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22390,7 +22390,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44 -// CHECK3-SAME: ([10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: ([10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 // CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4 @@ -22418,7 +22418,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22523,7 +22523,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22611,7 +22611,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52 -// CHECK3-SAME: (i32 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 @@ -22639,7 +22639,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__8 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22789,7 +22789,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__9 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22926,7 +22926,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59 -// CHECK3-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -22957,7 +22957,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23093,7 +23093,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23185,7 +23185,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28 -// CHECK4-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -23219,7 +23219,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23368,7 +23368,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23495,7 +23495,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34 -// CHECK4-SAME: (i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 4 @@ -23523,7 +23523,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23653,7 +23653,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23743,7 +23743,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39 -// CHECK4-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -23765,7 +23765,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23858,7 +23858,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23924,7 +23924,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44 -// CHECK4-SAME: ([10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: ([10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 // CHECK4-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4 @@ -23952,7 +23952,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24057,7 +24057,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24145,7 +24145,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52 -// CHECK4-SAME: (i32 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 @@ -24173,7 +24173,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__8 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24323,7 +24323,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__9 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24460,7 +24460,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59 -// CHECK4-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -24491,7 +24491,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24627,7 +24627,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[V:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp index 24162001107970e16b37f7c2e433bf99806c2fea..98cfc7aa0db514b68c2b73ec7176387222eca0f3 100644 --- a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_generic_mode_codegen.cpp @@ -30,7 +30,7 @@ int main(int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 -// CHECK1-SAME: (i64 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -68,7 +68,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -213,7 +213,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -304,10 +304,10 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[I7]]) #[[ATTR5:[0-9]+]] -// CHECK1-NEXT: [[CALL13:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[TMP0]]) #[[ATTR5]] +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I7]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: [[CALL13:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR4]] // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[CALL]], [[CALL13]] -// CHECK1-NEXT: [[CALL15:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[CONV]]) #[[ATTR5]] +// CHECK1-NEXT: [[CALL15:%.*]] = call i32 @_Z3fooPi(i32* [[CONV]]) #[[ATTR4]] // CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD14]], [[CALL15]] // CHECK1-NEXT: store i32 [[ADD16]], i32* [[TMP0]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -340,7 +340,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -374,7 +374,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -513,7 +513,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -598,10 +598,10 @@ int main(int argc, char **argv) { // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[I4]]) #[[ATTR5:[0-9]+]] -// CHECK2-NEXT: [[CALL8:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[TMP0]]) #[[ATTR5]] +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I4]]) #[[ATTR4:[0-9]+]] +// CHECK2-NEXT: [[CALL8:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR4]] // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[CALL]], [[CALL8]] -// CHECK2-NEXT: [[CALL10:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARGC_ADDR]]) #[[ATTR5]] +// CHECK2-NEXT: [[CALL10:%.*]] = call i32 @_Z3fooPi(i32* [[ARGC_ADDR]]) #[[ATTR4]] // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]] // CHECK2-NEXT: store i32 [[ADD11]], i32* [[TMP0]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -634,7 +634,7 @@ int main(int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 -// CHECK3-SAME: (i32 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -668,7 +668,7 @@ int main(int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -807,7 +807,7 @@ int main(int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -892,10 +892,10 @@ int main(int argc, char **argv) { // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[I4]]) #[[ATTR5:[0-9]+]] -// CHECK3-NEXT: [[CALL8:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[TMP0]]) #[[ATTR5]] +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I4]]) #[[ATTR4:[0-9]+]] +// CHECK3-NEXT: [[CALL8:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR4]] // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[CALL]], [[CALL8]] -// CHECK3-NEXT: [[CALL10:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARGC_ADDR]]) #[[ATTR5]] +// CHECK3-NEXT: [[CALL10:%.*]] = call i32 @_Z3fooPi(i32* [[ARGC_ADDR]]) #[[ATTR4]] // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]] // CHECK3-NEXT: store i32 [[ADD11]], i32* [[TMP0]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -928,7 +928,7 @@ int main(int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 -// CHECK4-SAME: (i64 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -966,7 +966,7 @@ int main(int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1111,7 +1111,7 @@ int main(int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1202,10 +1202,10 @@ int main(int argc, char **argv) { // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[I7]]) #[[ATTR5:[0-9]+]] -// CHECK4-NEXT: [[CALL13:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[TMP0]]) #[[ATTR5]] +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I7]]) #[[ATTR4:[0-9]+]] +// CHECK4-NEXT: [[CALL13:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR4]] // CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[CALL]], [[CALL13]] -// CHECK4-NEXT: [[CALL15:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[CONV]]) #[[ATTR5]] +// CHECK4-NEXT: [[CALL15:%.*]] = call i32 @_Z3fooPi(i32* [[CONV]]) #[[ATTR4]] // CHECK4-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD14]], [[CALL15]] // CHECK4-NEXT: store i32 [[ADD16]], i32* [[TMP0]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -1238,7 +1238,7 @@ int main(int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 -// CHECK5-SAME: (i32 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -1272,7 +1272,7 @@ int main(int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1411,7 +1411,7 @@ int main(int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1496,10 +1496,10 @@ int main(int argc, char **argv) { // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[I4]]) #[[ATTR5:[0-9]+]] -// CHECK5-NEXT: [[CALL8:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[TMP0]]) #[[ATTR5]] +// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I4]]) #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: [[CALL8:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR4]] // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[CALL]], [[CALL8]] -// CHECK5-NEXT: [[CALL10:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARGC_ADDR]]) #[[ATTR5]] +// CHECK5-NEXT: [[CALL10:%.*]] = call i32 @_Z3fooPi(i32* [[ARGC_ADDR]]) #[[ATTR4]] // CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]] // CHECK5-NEXT: store i32 [[ADD11]], i32* [[TMP0]], align 4 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -1532,7 +1532,7 @@ int main(int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 -// CHECK6-SAME: (i32 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-SAME: (i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -1566,7 +1566,7 @@ int main(int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1705,7 +1705,7 @@ int main(int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[ARGC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1790,10 +1790,10 @@ int main(int argc, char **argv) { // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[I4]]) #[[ATTR5:[0-9]+]] -// CHECK6-NEXT: [[CALL8:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[TMP0]]) #[[ATTR5]] +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I4]]) #[[ATTR4:[0-9]+]] +// CHECK6-NEXT: [[CALL8:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR4]] // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[CALL]], [[CALL8]] -// CHECK6-NEXT: [[CALL10:%.*]] = call noundef i32 @_Z3fooPi(i32* noundef [[ARGC_ADDR]]) #[[ATTR5]] +// CHECK6-NEXT: [[CALL10:%.*]] = call i32 @_Z3fooPi(i32* [[ARGC_ADDR]]) #[[ATTR4]] // CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]] // CHECK6-NEXT: store i32 [[ADD11]], i32* [[TMP0]], align 4 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp index 4e46f4941e0f5324fc37d0e653f7416475eaf522..754f4ce08ca0911dc731cf53527f1dcd4467588d 100644 --- a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp @@ -9381,7 +9381,7 @@ int bar(int n){ // CHECK12: .omp.final.done: // CHECK12-NEXT: ret void // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -9419,7 +9419,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9586,7 +9586,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[L:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9732,7 +9732,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 8 @@ -9762,7 +9762,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9908,7 +9908,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10015,7 +10015,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37 -// CHECK1-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -10037,7 +10037,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10139,7 +10139,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10216,7 +10216,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42 -// CHECK1-SAME: ([10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: ([10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 // CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8 @@ -10246,7 +10246,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10363,7 +10363,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i64 [[F:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10465,7 +10465,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26 -// CHECK2-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -10499,7 +10499,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10660,7 +10660,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10799,7 +10799,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32 -// CHECK2-SAME: (i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 4 @@ -10827,7 +10827,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10969,7 +10969,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11071,7 +11071,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37 -// CHECK2-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -11093,7 +11093,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11193,7 +11193,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11266,7 +11266,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42 -// CHECK2-SAME: ([10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: ([10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 // CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4 @@ -11294,7 +11294,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11407,7 +11407,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11503,7 +11503,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l26 -// CHECK3-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -11537,7 +11537,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11698,7 +11698,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[L:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11837,7 +11837,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32 -// CHECK3-SAME: (i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca [1000 x i16]*, align 4 @@ -11865,7 +11865,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12007,7 +12007,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i16]* noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i16]* nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12109,7 +12109,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37 -// CHECK3-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -12131,7 +12131,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12231,7 +12231,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12304,7 +12304,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42 -// CHECK3-SAME: ([10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: ([10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 4 // CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4 @@ -12332,7 +12332,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12445,7 +12445,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[F:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp index 1b95d0887970aa070ff2c219ea54ce4d4b81fdd8..8f9fce851b05abc1fda3606cd0db03e91d3b0fa6 100644 --- a/clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp @@ -1,15 +1,15 @@ // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 - -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 + +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 // expected-no-diagnostics #ifndef HEADER diff --git a/clang/test/OpenMP/nvptx_teams_codegen.cpp b/clang/test/OpenMP/nvptx_teams_codegen.cpp index 45160b69c1637c589be827cc93dda85a03274efb..cc7050a7cb07e14840de87df31a4dd0899b370eb 100644 --- a/clang/test/OpenMP/nvptx_teams_codegen.cpp +++ b/clang/test/OpenMP/nvptx_teams_codegen.cpp @@ -891,7 +891,7 @@ int main (int argc, char **argv) { // CHECK8-NEXT: store i8** null, i8*** [[TMP0]], align 4 // CHECK8-NEXT: ret void // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 -// CHECK1-SAME: (i64 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -918,7 +918,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -932,7 +932,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l15 -// CHECK1-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -958,7 +958,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -972,7 +972,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -998,7 +998,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1012,7 +1012,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l15 -// CHECK2-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -1038,7 +1038,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1052,7 +1052,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 -// CHECK3-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1085,7 +1085,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1099,7 +1099,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l53 -// CHECK3-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1131,7 +1131,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1145,7 +1145,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1175,7 +1175,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1189,7 +1189,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l53 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1219,7 +1219,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp b/clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp index 67e1f184165fe8ce3e9b7dfc5831676e00d344e1..4d5863f81b825c8bf4e55dc5108245d86f67ff47 100644 --- a/clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp +++ b/clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp @@ -4207,7 +4207,7 @@ int bar(int n){ // CHECK6-NEXT: call void @"_omp$reduction$reduction_func14"(i8* [[TMP13]], i8* [[TMP12]]) #[[ATTR3]] // CHECK6-NEXT: ret void // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l20 -// CHECK1-SAME: (i64 noundef [[E:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i64 [[E:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[E_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 @@ -4234,7 +4234,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4273,7 +4273,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -4349,7 +4349,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -4410,7 +4410,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -4434,7 +4434,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -4458,7 +4458,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -4482,7 +4482,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -4506,7 +4506,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l26 -// CHECK1-SAME: (i64 noundef [[C:%.*]], i64 noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[C:%.*]], i64 [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i64, align 8 @@ -4540,7 +4540,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[C:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[C:%.*]], float* nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4599,7 +4599,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func3 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -4696,7 +4696,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func4 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -4772,7 +4772,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func5 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -4802,7 +4802,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func6 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -4830,7 +4830,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func7 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -4860,7 +4860,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func8 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -4888,7 +4888,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4913,7 +4913,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4979,7 +4979,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5052,7 +5052,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func12 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -5152,7 +5152,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func13 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -5230,7 +5230,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func15 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -5330,7 +5330,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func16 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -5408,7 +5408,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func17 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -5439,7 +5439,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func18 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -5468,7 +5468,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func19 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -5499,7 +5499,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func20 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -5528,7 +5528,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l20 -// CHECK2-SAME: (double* noundef nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (double* nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[E_ADDR:%.*]] = alloca double*, align 4 // CHECK2-NEXT: [[E1:%.*]] = alloca double, align 8 @@ -5553,7 +5553,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5592,7 +5592,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -5668,7 +5668,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -5729,7 +5729,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -5753,7 +5753,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -5777,7 +5777,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -5801,7 +5801,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -5825,7 +5825,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l26 -// CHECK2-SAME: (i32 noundef [[C:%.*]], i32 noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 [[C:%.*]], i32 [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4 @@ -5859,7 +5859,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[C:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[C:%.*]], float* nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5918,7 +5918,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func3 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -6015,7 +6015,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func4 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -6091,7 +6091,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func5 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -6121,7 +6121,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func6 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -6149,7 +6149,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func7 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -6179,7 +6179,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func8 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -6207,7 +6207,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33 -// CHECK2-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -6231,7 +6231,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6297,7 +6297,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6370,7 +6370,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func12 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -6470,7 +6470,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func13 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -6548,7 +6548,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func15 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -6648,7 +6648,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func16 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -6726,7 +6726,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func17 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -6757,7 +6757,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func18 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -6786,7 +6786,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func19 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -6817,7 +6817,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func20 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -6846,7 +6846,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l20 -// CHECK3-SAME: (double* noundef nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[E_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[E1:%.*]] = alloca double, align 8 @@ -6871,7 +6871,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6910,7 +6910,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -6986,7 +6986,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -7047,7 +7047,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -7071,7 +7071,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -7095,7 +7095,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -7119,7 +7119,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -7143,7 +7143,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l26 -// CHECK3-SAME: (i32 noundef [[C:%.*]], i32 noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[C:%.*]], i32 [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4 @@ -7177,7 +7177,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[C:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8* nonnull align 1 dereferenceable(1) [[C:%.*]], float* nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7236,7 +7236,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func3 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -7333,7 +7333,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func4 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -7409,7 +7409,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func5 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -7439,7 +7439,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func6 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -7467,7 +7467,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func7 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -7497,7 +7497,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func8 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -7525,7 +7525,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l33 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -7549,7 +7549,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__9 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7615,7 +7615,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7688,7 +7688,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func12 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -7788,7 +7788,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func13 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -7866,7 +7866,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func15 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i16 signext [[TMP1:%.*]], i16 signext [[TMP2:%.*]], i16 signext [[TMP3:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2 @@ -7966,7 +7966,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func16 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -8044,7 +8044,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func17 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -8075,7 +8075,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func18 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -8104,7 +8104,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func19 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 @@ -8135,7 +8135,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func20 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], i8* noundef [[TMP2:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i32 [[TMP1:%.*]], i8* [[TMP2:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/nvptx_unsupported_type_codegen.cpp b/clang/test/OpenMP/nvptx_unsupported_type_codegen.cpp index 43c47dbc5a973b8a8694c5c48cd04d8532711236..34d0087406daf2279580d40d2295654e2cb2fdff 100644 --- a/clang/test/OpenMP/nvptx_unsupported_type_codegen.cpp +++ b/clang/test/OpenMP/nvptx_unsupported_type_codegen.cpp @@ -34,7 +34,7 @@ struct T1 { #pragma omp declare target T a = T(); T f = a; -// CHECK: define{{ hidden | }}void @{{.+}}foo{{.+}}([[T]]* noundef byval([[T]]) align {{.+}}) +// CHECK: define{{ hidden | }}void @{{.+}}foo{{.+}}([[T]]* byval([[T]]) align {{.+}}) void foo(T a = T()) { return; } @@ -54,7 +54,7 @@ void baz() { } T1 a1 = T1(); T1 f1 = a1; -// CHECK: define{{ hidden | }}void @{{.+}}foo1{{.+}}([[T1]]* noundef byval([[T1]]) align {{.+}}) +// CHECK: define{{ hidden | }}void @{{.+}}foo1{{.+}}([[T1]]* byval([[T1]]) align {{.+}}) void foo1(T1 a = T1()) { return; } diff --git a/clang/test/OpenMP/openmp_offload_codegen.cpp b/clang/test/OpenMP/openmp_offload_codegen.cpp index 3630d5c72faf8e007224de696b81c3d7561b613b..4e3cf82bf8311e44b342a4b1005b363c13d46cb1 100644 --- a/clang/test/OpenMP/openmp_offload_codegen.cpp +++ b/clang/test/OpenMP/openmp_offload_codegen.cpp @@ -25,7 +25,7 @@ void target_maps_parallel_integer(int a){ } } -// CK1-DEVICE: {{.*}}void @__omp_offloading_{{.*}}(i32* noundef nonnull align 4 dereferenceable(4){{.*}} +// CK1-DEVICE: {{.*}}void @__omp_offloading_{{.*}}(i32* nonnull align 4 dereferenceable(4){{.*}} // CK1: {{.*}}void {{.*}}target_maps_parallel_integer{{.*}} { diff --git a/clang/test/OpenMP/openmp_win_codegen.cpp b/clang/test/OpenMP/openmp_win_codegen.cpp index f28028a70618e9fc742571298079acf46e8bfe94..4ccb85e93f11251503951b8ab43b0e32cce12c96 100644 --- a/clang/test/OpenMP/openmp_win_codegen.cpp +++ b/clang/test/OpenMP/openmp_win_codegen.cpp @@ -56,7 +56,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -98,7 +98,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[J:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[J:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[J_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -135,7 +135,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -155,3 +155,4 @@ int main() { // CHECK1-NEXT: store i32 [[TMP12]], i32* [[TMP8]], align 4 // CHECK1-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/ordered_codegen.cpp b/clang/test/OpenMP/ordered_codegen.cpp index 3871a978acd3de77cb89522830447ecde8e7e2f1..bb9e1f45805744f918d5587a335940a3e71b4334 100644 --- a/clang/test/OpenMP/ordered_codegen.cpp +++ b/clang/test/OpenMP/ordered_codegen.cpp @@ -123,7 +123,7 @@ void foo_simd(int low, int up) { #endif // HEADER // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -215,7 +215,7 @@ void foo_simd(int low, int up) { // // // CHECK1-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -303,7 +303,7 @@ void foo_simd(int low, int up) { // // // CHECK1-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -441,7 +441,7 @@ void foo_simd(int low, int up) { // // // CHECK1-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -546,7 +546,7 @@ void foo_simd(int low, int up) { // // // CHECK1-LABEL: define {{[^@]+}}@_Z8foo_simdii -// CHECK1-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 @@ -729,7 +729,7 @@ void foo_simd(int low, int up) { // // // CHECK1-LABEL: define {{[^@]+}}@__captured_stmt -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 @@ -742,7 +742,7 @@ void foo_simd(int low, int up) { // // // CHECK1-LABEL: define {{[^@]+}}@__captured_stmt.1 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 @@ -755,7 +755,7 @@ void foo_simd(int low, int up) { // // // CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -847,7 +847,7 @@ void foo_simd(int low, int up) { // // // CHECK2-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -935,7 +935,7 @@ void foo_simd(int low, int up) { // // // CHECK2-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1073,7 +1073,7 @@ void foo_simd(int low, int up) { // // // CHECK2-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1178,7 +1178,7 @@ void foo_simd(int low, int up) { // // // CHECK2-LABEL: define {{[^@]+}}@_Z8foo_simdii -// CHECK2-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 @@ -1361,7 +1361,7 @@ void foo_simd(int low, int up) { // // // CHECK2-LABEL: define {{[^@]+}}@__captured_stmt -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 @@ -1374,7 +1374,7 @@ void foo_simd(int low, int up) { // // // CHECK2-LABEL: define {{[^@]+}}@__captured_stmt.1 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 @@ -1387,7 +1387,7 @@ void foo_simd(int low, int up) { // // // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1479,7 +1479,7 @@ void foo_simd(int low, int up) { // // // CHECK3-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1567,7 +1567,7 @@ void foo_simd(int low, int up) { // // // CHECK3-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1705,7 +1705,7 @@ void foo_simd(int low, int up) { // // // CHECK3-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1810,7 +1810,7 @@ void foo_simd(int low, int up) { // // // CHECK3-LABEL: define {{[^@]+}}@_Z8foo_simdii -// CHECK3-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 @@ -1993,7 +1993,7 @@ void foo_simd(int low, int up) { // // // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 @@ -2006,7 +2006,7 @@ void foo_simd(int low, int up) { // // // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.1 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 @@ -2019,7 +2019,7 @@ void foo_simd(int low, int up) { // // // CHECK4-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2111,7 +2111,7 @@ void foo_simd(int low, int up) { // // // CHECK4-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2199,7 +2199,7 @@ void foo_simd(int low, int up) { // // // CHECK4-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2337,7 +2337,7 @@ void foo_simd(int low, int up) { // // // CHECK4-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2442,7 +2442,7 @@ void foo_simd(int low, int up) { // // // CHECK4-LABEL: define {{[^@]+}}@_Z8foo_simdii -// CHECK4-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 @@ -2625,7 +2625,7 @@ void foo_simd(int low, int up) { // // // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 @@ -2638,7 +2638,7 @@ void foo_simd(int low, int up) { // // // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt.1 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 @@ -2651,7 +2651,7 @@ void foo_simd(int low, int up) { // // // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2702,7 +2702,7 @@ void foo_simd(int low, int up) { // // // CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2749,7 +2749,7 @@ void foo_simd(int low, int up) { // // // CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2821,7 +2821,7 @@ void foo_simd(int low, int up) { // // // CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2889,7 +2889,7 @@ void foo_simd(int low, int up) { // // // CHECK5-LABEL: define {{[^@]+}}@_Z8foo_simdii -// CHECK5-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 @@ -3043,7 +3043,7 @@ void foo_simd(int low, int up) { // // // CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3094,7 +3094,7 @@ void foo_simd(int low, int up) { // // // CHECK6-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3141,7 +3141,7 @@ void foo_simd(int low, int up) { // // // CHECK6-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3213,7 +3213,7 @@ void foo_simd(int low, int up) { // // // CHECK6-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3281,7 +3281,7 @@ void foo_simd(int low, int up) { // // // CHECK6-LABEL: define {{[^@]+}}@_Z8foo_simdii -// CHECK6-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/parallel_codegen.cpp b/clang/test/OpenMP/parallel_codegen.cpp index 992feea6835697e21733e97a9b485e8eb0abf9a3..e3ec081943484d8b94cd3cb670933014b75c0041 100644 --- a/clang/test/OpenMP/parallel_codegen.cpp +++ b/clang/test/OpenMP/parallel_codegen.cpp @@ -71,7 +71,7 @@ int main (int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -91,7 +91,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i32* [[VLA]]) // CHECK1-NEXT: [[TMP3:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(i8** noundef [[TMP3]]) +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP3]]) // CHECK1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP4]]) @@ -100,7 +100,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -114,7 +114,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 1 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK1-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP2]]) +// CHECK1-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP2]]) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* @global, align 4 @@ -130,7 +130,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat { +// CHECK1-SAME: (i32 [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 @@ -145,7 +145,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -168,7 +168,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR2]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR2]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -185,7 +185,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[GLOBAL_ADDR]], align 8 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 1 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK1-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP3]]) +// CHECK1-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP3]]) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -201,7 +201,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -218,7 +218,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -232,7 +232,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 1 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK1-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP2]]) +// CHECK1-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP2]]) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* @global, align 4 @@ -248,7 +248,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK1-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR3]] comdat { +// CHECK1-SAME: (i8** [[ARGC:%.*]]) #[[ATTR3]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 // CHECK1-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 @@ -263,7 +263,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -277,7 +277,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[TMP0]], align 8 -// CHECK1-NEXT: invoke void @_Z3fooIPPcEvT_(i8** noundef [[TMP2]]) +// CHECK1-NEXT: invoke void @_Z3fooIPPcEvT_(i8** [[TMP2]]) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: [[TMP3:%.*]] = load double*, double** [[VAR]], align 8 @@ -294,7 +294,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ -// CHECK1-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR3]] comdat { +// CHECK1-SAME: (i8** [[ARGC:%.*]]) #[[ATTR3]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 // CHECK1-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 @@ -302,7 +302,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG11:![0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG11:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -326,7 +326,7 @@ int main (int argc, char **argv) { // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB5:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]), !dbg [[DBG32:![0-9]+]] // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB9:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP1]], i32* [[VLA]]), !dbg [[DBG33:![0-9]+]] // CHECK2-NEXT: [[TMP3:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8, !dbg [[DBG34:![0-9]+]] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(i8** noundef [[TMP3]]), !dbg [[DBG35:![0-9]+]] +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP3]]), !dbg [[DBG35:![0-9]+]] // CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4, !dbg [[DBG36:![0-9]+]] // CHECK2-NEXT: [[TMP4:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG37:![0-9]+]] // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP4]]), !dbg [[DBG37]] @@ -335,7 +335,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__ -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG38:![0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG38:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -353,7 +353,7 @@ int main (int argc, char **argv) { // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8, !dbg [[DBG52]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 1, !dbg [[DBG53:![0-9]+]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !dbg [[DBG53]] -// CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP2]]) +// CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP2]]) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG52]] // CHECK2: invoke.cont: // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* @global, align 4, !dbg [[DBG54:![0-9]+]] @@ -369,7 +369,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat !dbg [[DBG57:![0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat !dbg [[DBG57:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 @@ -385,7 +385,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG65:![0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG65:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -409,7 +409,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR3]] !dbg [[DBG74:![0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR3]] !dbg [[DBG74:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -438,7 +438,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG88:![0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG88:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -460,7 +460,7 @@ int main (int argc, char **argv) { // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[GLOBAL_ADDR]], align 8, !dbg [[DBG99]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 1, !dbg [[DBG100:![0-9]+]] // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !dbg [[DBG100]] -// CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP3]]) +// CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP3]]) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG99]] // CHECK2: invoke.cont: // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 4, !dbg [[DBG101:![0-9]+]] @@ -476,7 +476,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR3]] !dbg [[DBG104:![0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR3]] !dbg [[DBG104:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -505,7 +505,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR3]] !dbg [[DBG112:![0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR3]] !dbg [[DBG112:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -524,7 +524,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG118:![0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG118:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -545,7 +545,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG127:![0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG127:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -563,7 +563,7 @@ int main (int argc, char **argv) { // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8, !dbg [[DBG134]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 1, !dbg [[DBG135:![0-9]+]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !dbg [[DBG135]] -// CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP2]]) +// CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 [[TMP2]]) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG134]] // CHECK2: invoke.cont: // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* @global, align 4, !dbg [[DBG136:![0-9]+]] @@ -579,7 +579,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG139:![0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG139:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -603,7 +603,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG146:![0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG146:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -627,7 +627,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK2-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR4]] comdat !dbg [[DBG153:![0-9]+]] { +// CHECK2-SAME: (i8** [[ARGC:%.*]]) #[[ATTR4]] comdat !dbg [[DBG153:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 // CHECK2-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 @@ -643,7 +643,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG164:![0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]], i64 [[VLA:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG164:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -661,7 +661,7 @@ int main (int argc, char **argv) { // CHECK2-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8, !dbg [[DBG174:![0-9]+]] // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8, !dbg [[DBG174]] // CHECK2-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[TMP0]], align 8, !dbg [[DBG175:![0-9]+]] -// CHECK2-NEXT: invoke void @_Z3fooIPPcEvT_(i8** noundef [[TMP2]]) +// CHECK2-NEXT: invoke void @_Z3fooIPPcEvT_(i8** [[TMP2]]) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG177:![0-9]+]] // CHECK2: invoke.cont: // CHECK2-NEXT: call void @llvm.dbg.declare(metadata double** [[VAR]], metadata [[META178:![0-9]+]], metadata !DIExpression()), !dbg [[DBG185:![0-9]+]] @@ -679,7 +679,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ -// CHECK2-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR4]] comdat !dbg [[DBG188:![0-9]+]] { +// CHECK2-SAME: (i8** [[ARGC:%.*]]) #[[ATTR4]] comdat !dbg [[DBG188:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 // CHECK2-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 @@ -688,7 +688,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR3]] !dbg [[DBG194:![0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]], i64 [[VLA:%.*]]) #[[ATTR3]] !dbg [[DBG194:![0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -712,7 +712,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -737,7 +737,7 @@ int main (int argc, char **argv) { // CHECK3-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]] // CHECK3: omp.par.exit.split: // CHECK3-NEXT: [[TMP3:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(i8** noundef [[TMP3]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP3]]) // CHECK3-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP4]]) @@ -756,7 +756,7 @@ int main (int argc, char **argv) { // CHECK3: omp.par.region: // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK3-NEXT: call void @_Z3fooIiEvT_(i32 noundef [[TMP1]]) +// CHECK3-NEXT: call void @_Z3fooIiEvT_(i32 [[TMP1]]) // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @global, align 4 // CHECK3-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX1]], align 4 @@ -768,7 +768,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ -// CHECK3-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK3-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 @@ -776,7 +776,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK3-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { +// CHECK3-SAME: (i8** [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTRELOADED:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 @@ -811,7 +811,7 @@ int main (int argc, char **argv) { // CHECK3-NEXT: br label [[OMP_PAR_REGION:%.*]] // CHECK3: omp.par.region: // CHECK3-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8 -// CHECK3-NEXT: call void @_Z3fooIPPcEvT_(i8** noundef [[TMP2]]) +// CHECK3-NEXT: call void @_Z3fooIPPcEvT_(i8** [[TMP2]]) // CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[VAR]], align 8 // CHECK3-NEXT: [[TMP4:%.*]] = mul nsw i64 0, [[TMP1]] // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP3]], i64 [[TMP4]] @@ -824,7 +824,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ -// CHECK3-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR4]] comdat { +// CHECK3-SAME: (i8** [[ARGC:%.*]]) #[[ATTR4]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 // CHECK3-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 @@ -832,7 +832,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG11:![0-9]+]] { +// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG11:![0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -861,7 +861,7 @@ int main (int argc, char **argv) { // CHECK4-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]] // CHECK4: omp.par.exit.split: // CHECK4-NEXT: [[TMP3:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8, !dbg [[DBG30:![0-9]+]] -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(i8** noundef [[TMP3]]), !dbg [[DBG30]] +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP3]]), !dbg [[DBG30]] // CHECK4-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4, !dbg [[DBG30]] // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG31:![0-9]+]] // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP4]]), !dbg [[DBG31]] @@ -880,7 +880,7 @@ int main (int argc, char **argv) { // CHECK4: omp.par.region: // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG34:![0-9]+]] // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !dbg [[DBG34]] -// CHECK4-NEXT: call void @_Z3fooIiEvT_(i32 noundef [[TMP1]]), !dbg [[DBG34]] +// CHECK4-NEXT: call void @_Z3fooIiEvT_(i32 [[TMP1]]), !dbg [[DBG34]] // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* @global, align 4, !dbg [[DBG34]] // CHECK4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 1, !dbg [[DBG34]] // CHECK4-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX1]], align 4, !dbg [[DBG34]] @@ -892,7 +892,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ -// CHECK4-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat !dbg [[DBG35:![0-9]+]] { +// CHECK4-SAME: (i32 [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat !dbg [[DBG35:![0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 @@ -901,7 +901,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ -// CHECK4-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat !dbg [[DBG44:![0-9]+]] { +// CHECK4-SAME: (i8** [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat !dbg [[DBG44:![0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTRELOADED:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 @@ -937,7 +937,7 @@ int main (int argc, char **argv) { // CHECK4-NEXT: br label [[OMP_PAR_REGION:%.*]] // CHECK4: omp.par.region: // CHECK4-NEXT: [[TMP2:%.*]] = load i8**, i8*** [[ARGC_ADDR]], align 8, !dbg [[DBG57:![0-9]+]] -// CHECK4-NEXT: call void @_Z3fooIPPcEvT_(i8** noundef [[TMP2]]), !dbg [[DBG57]] +// CHECK4-NEXT: call void @_Z3fooIPPcEvT_(i8** [[TMP2]]), !dbg [[DBG57]] // CHECK4-NEXT: call void @llvm.dbg.declare(metadata double** [[VAR]], metadata [[META58:![0-9]+]], metadata !DIExpression()), !dbg [[DBG65:![0-9]+]] // CHECK4-NEXT: [[TMP3:%.*]] = load double*, double** [[VAR]], align 8, !dbg [[DBG65]] // CHECK4-NEXT: [[TMP4:%.*]] = mul nsw i64 0, [[TMP1]], !dbg [[DBG65]] @@ -951,7 +951,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ -// CHECK4-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR5]] comdat !dbg [[DBG67:![0-9]+]] { +// CHECK4-SAME: (i8** [[ARGC:%.*]]) #[[ATTR5]] comdat !dbg [[DBG67:![0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 // CHECK4-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 diff --git a/clang/test/OpenMP/parallel_copyin_codegen.cpp b/clang/test/OpenMP/parallel_copyin_codegen.cpp index 58470c68865523978d9b6998120d51685f89722c..e087090553ce0514c917a2fe7903293d3d26540e 100644 --- a/clang/test/OpenMP/parallel_copyin_codegen.cpp +++ b/clang/test/OpenMP/parallel_copyin_codegen.cpp @@ -216,13 +216,13 @@ void foo() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[REF_TMP]]) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[TEST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR3:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8 // CHECK1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] +// CHECK1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] // CHECK1: init.check: // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 @@ -230,15 +230,15 @@ void foo() { // CHECK1: init: // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK1-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast ([2 x %struct.S]* @_ZZ4mainE5s_arr to i8*), i8* (i8*)* @.__kmpc_global_ctor_., i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_.) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] // CHECK1-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] // CHECK1-NEXT: br label [[INIT_END]] // CHECK1: init.end: // CHECK1-NEXT: [[TMP4:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8 // CHECK1-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP4]], 0 -// CHECK1-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF3]] +// CHECK1-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] // CHECK1: init.check2: // CHECK1-NEXT: [[TMP5:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]] // CHECK1-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP5]], 0 @@ -246,32 +246,32 @@ void foo() { // CHECK1: init4: // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* (i8*)* @.__kmpc_global_ctor_..1, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..2) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @_ZZ4mainE3var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00) // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]] // CHECK1-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]] // CHECK1-NEXT: br label [[INIT_END5]] // CHECK1: init.end5: // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) -// CHECK1-NEXT: [[CALL6:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL6:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL6]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP8]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_ -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 @@ -282,32 +282,32 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [2 x %struct.S]* // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK1-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: ret i8* [[TMP3]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -315,12 +315,12 @@ void foo() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -331,7 +331,7 @@ void foo() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -339,7 +339,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -347,7 +347,7 @@ void foo() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -355,30 +355,30 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S* -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[TMP2]], float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], float 3.000000e+00) // CHECK1-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: ret i8* [[TMP3]] // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S* -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TMP2]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -407,7 +407,7 @@ void foo() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] @@ -415,7 +415,7 @@ void foo() { // CHECK1: omp.arraycpy.done1: // CHECK1-NEXT: [[TMP13:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i64 4, i8*** @_ZZ4mainE3var.cache.) // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to %struct.S* -// CHECK1-NEXT: [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[TMP14]], %struct.S* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) +// CHECK1-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP14]], %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) // CHECK1-NEXT: br label [[COPYIN_NOT_MASTER_END]] // CHECK1: copyin.not.master.end: // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP1]]) @@ -431,12 +431,12 @@ void foo() { // CHECK1-NEXT: [[TMP22:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x %struct.S]* @_ZZ4mainE5s_arr to i8*), i64 8, i8*** @_ZZ4mainE5s_arr.cache.) // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8* [[TMP22]] to [2 x %struct.S]* // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP23]], i64 0, i64 0 -// CHECK1-NEXT: [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[ARRAYIDX3]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP21]]) +// CHECK1-NEXT: [[CALL4:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP21]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -468,13 +468,13 @@ void foo() { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[REF_TMP]]) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] // CHECK1-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8 // CHECK1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3]] +// CHECK1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]] // CHECK1: init.check: // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 @@ -482,15 +482,15 @@ void foo() { // CHECK1: init: // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast ([2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr to i8*), i8* (i8*)* @.__kmpc_global_ctor_..4, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..5) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 noundef 1) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 noundef 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2) // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.6, i8* null, i8* @__dso_handle) #[[ATTR3]] // CHECK1-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] // CHECK1-NEXT: br label [[INIT_END]] // CHECK1: init.end: // CHECK1-NEXT: [[TMP4:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8 // CHECK1-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP4]], 0 -// CHECK1-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF3]] +// CHECK1-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] // CHECK1: init.check2: // CHECK1-NEXT: [[TMP5:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] // CHECK1-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP5]], 0 @@ -498,19 +498,19 @@ void foo() { // CHECK1: init4: // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* (i8*)* @.__kmpc_global_ctor_..7, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..8) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef @_ZZ5tmainIiET_vE3var, i32 noundef 3) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3) // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]] // CHECK1-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] // CHECK1-NEXT: br label [[INIT_END5]] // CHECK1: init.end5: // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*)) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -526,7 +526,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -535,7 +535,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -555,17 +555,17 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_ -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -576,32 +576,32 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..4 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [2 x %struct.S.0]* // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK1-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: ret i8* [[TMP3]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -609,12 +609,12 @@ void foo() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..5 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -625,7 +625,7 @@ void foo() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -633,7 +633,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.6 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -641,7 +641,7 @@ void foo() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -649,30 +649,30 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..7 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S.0* -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[TMP2]], i32 noundef 3) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]], i32 3) // CHECK1-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: ret i8* [[TMP3]] // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..8 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S.0* -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TMP2]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -701,7 +701,7 @@ void foo() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] @@ -709,7 +709,7 @@ void foo() { // CHECK1: omp.arraycpy.done1: // CHECK1-NEXT: [[TMP13:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i64 4, i8*** @_ZZ5tmainIiET_vE3var.cache.) // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to %struct.S.0* -// CHECK1-NEXT: [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[TMP14]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) +// CHECK1-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP14]], %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) // CHECK1-NEXT: br label [[COPYIN_NOT_MASTER_END]] // CHECK1: copyin.not.master.end: // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]]) @@ -725,12 +725,12 @@ void foo() { // CHECK1-NEXT: [[TMP22:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr to i8*), i64 8, i8*** @_ZZ5tmainIiET_vE5s_arr.cache.) // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8* [[TMP22]] to [2 x %struct.S.0]* // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP23]], i64 0, i64 0 -// CHECK1-NEXT: [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[ARRAYIDX3]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP21]]) +// CHECK1-NEXT: [[CALL4:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP21]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -753,7 +753,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -768,7 +768,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -777,7 +777,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -802,13 +802,13 @@ void foo() { // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[REF_TMP]]) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[TEST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR3:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]] // CHECK2-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8 // CHECK2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] +// CHECK2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] // CHECK2: init.check: // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 @@ -816,15 +816,15 @@ void foo() { // CHECK2: init: // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK2-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast ([2 x %struct.S]* @_ZZ4mainE5s_arr to i8*), i8* (i8*)* @.__kmpc_global_ctor_., i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_.) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] // CHECK2-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]] // CHECK2-NEXT: br label [[INIT_END]] // CHECK2: init.end: // CHECK2-NEXT: [[TMP4:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8 // CHECK2-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP4]], 0 -// CHECK2-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF3]] +// CHECK2-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] // CHECK2: init.check2: // CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]] // CHECK2-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP5]], 0 @@ -832,32 +832,32 @@ void foo() { // CHECK2: init4: // CHECK2-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* (i8*)* @.__kmpc_global_ctor_..1, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..2) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @_ZZ4mainE3var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00) // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]] // CHECK2-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]] // CHECK2-NEXT: br label [[INIT_END5]] // CHECK2: init.end5: // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) -// CHECK2-NEXT: [[CALL6:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL6:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: store i32 [[CALL6]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP8]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_ -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 @@ -868,32 +868,32 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [2 x %struct.S]* // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK2-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: ret i8* [[TMP3]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -901,12 +901,12 @@ void foo() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -917,7 +917,7 @@ void foo() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -925,7 +925,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -933,7 +933,7 @@ void foo() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -941,30 +941,30 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S* -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[TMP2]], float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], float 3.000000e+00) // CHECK2-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: ret i8* [[TMP3]] // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S* -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TMP2]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -993,7 +993,7 @@ void foo() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] @@ -1001,7 +1001,7 @@ void foo() { // CHECK2: omp.arraycpy.done1: // CHECK2-NEXT: [[TMP13:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i64 4, i8*** @_ZZ4mainE3var.cache.) // CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to %struct.S* -// CHECK2-NEXT: [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[TMP14]], %struct.S* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) +// CHECK2-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP14]], %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) // CHECK2-NEXT: br label [[COPYIN_NOT_MASTER_END]] // CHECK2: copyin.not.master.end: // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP1]]) @@ -1017,12 +1017,12 @@ void foo() { // CHECK2-NEXT: [[TMP22:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x %struct.S]* @_ZZ4mainE5s_arr to i8*), i64 8, i8*** @_ZZ4mainE5s_arr.cache.) // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8* [[TMP22]] to [2 x %struct.S]* // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP23]], i64 0, i64 0 -// CHECK2-NEXT: [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[ARRAYIDX3]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP21]]) +// CHECK2-NEXT: [[CALL4:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP21]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1054,13 +1054,13 @@ void foo() { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[REF_TMP]]) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] // CHECK2-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8 // CHECK2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3]] +// CHECK2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]] // CHECK2: init.check: // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 @@ -1068,15 +1068,15 @@ void foo() { // CHECK2: init: // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast ([2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr to i8*), i8* (i8*)* @.__kmpc_global_ctor_..4, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..5) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 noundef 1) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 noundef 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2) // CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.6, i8* null, i8* @__dso_handle) #[[ATTR3]] // CHECK2-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]] // CHECK2-NEXT: br label [[INIT_END]] // CHECK2: init.end: // CHECK2-NEXT: [[TMP4:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8 // CHECK2-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP4]], 0 -// CHECK2-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF3]] +// CHECK2-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]] // CHECK2: init.check2: // CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] // CHECK2-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[TMP5]], 0 @@ -1084,19 +1084,19 @@ void foo() { // CHECK2: init4: // CHECK2-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* (i8*)* @.__kmpc_global_ctor_..7, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..8) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef @_ZZ5tmainIiET_vE3var, i32 noundef 3) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3) // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]] // CHECK2-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]] // CHECK2-NEXT: br label [[INIT_END5]] // CHECK2: init.end5: // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*)) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1112,7 +1112,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1121,7 +1121,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1141,17 +1141,17 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_ -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1162,32 +1162,32 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..4 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [2 x %struct.S.0]* // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK2-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: ret i8* [[TMP3]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1195,12 +1195,12 @@ void foo() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..5 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1211,7 +1211,7 @@ void foo() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1219,7 +1219,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.6 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1227,7 +1227,7 @@ void foo() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1235,30 +1235,30 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..7 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S.0* -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[TMP2]], i32 noundef 3) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]], i32 3) // CHECK2-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: ret i8* [[TMP3]] // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..8 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S.0* -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TMP2]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1287,7 +1287,7 @@ void foo() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] @@ -1295,7 +1295,7 @@ void foo() { // CHECK2: omp.arraycpy.done1: // CHECK2-NEXT: [[TMP13:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i64 4, i8*** @_ZZ5tmainIiET_vE3var.cache.) // CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to %struct.S.0* -// CHECK2-NEXT: [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[TMP14]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) +// CHECK2-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP14]], %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) // CHECK2-NEXT: br label [[COPYIN_NOT_MASTER_END]] // CHECK2: copyin.not.master.end: // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]]) @@ -1311,12 +1311,12 @@ void foo() { // CHECK2-NEXT: [[TMP22:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr to i8*), i64 8, i8*** @_ZZ5tmainIiET_vE5s_arr.cache.) // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8* [[TMP22]] to [2 x %struct.S.0]* // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP23]], i64 0, i64 0 -// CHECK2-NEXT: [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[ARRAYIDX3]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP21]]) +// CHECK2-NEXT: [[CALL4:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP21]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1339,7 +1339,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1354,7 +1354,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1363,7 +1363,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1387,12 +1387,12 @@ void foo() { // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1415,7 +1415,7 @@ void foo() { // CHECK3-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @g to i8*), i64 4, i8*** @g.cache.) // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* // CHECK3-NEXT: store volatile i32 1, i32* [[TMP8]], align 128 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret void // // @@ -1426,12 +1426,12 @@ void foo() { // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// CHECK4-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -1443,7 +1443,7 @@ void foo() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1467,12 +1467,12 @@ void foo() { // CHECK4-NEXT: store volatile i32 1, i32* [[TMP8]], align 128 // CHECK4-NEXT: [[TMP9:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP10]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to i8*)) +// CHECK4-NEXT: call void [[TMP10]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to i8*)) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -1491,7 +1491,7 @@ void foo() { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ10array_funcvE1s to i8*) acquire, align 8 // CHECK5-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK5-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] +// CHECK5-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] // CHECK5: init.check: // CHECK5-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ10array_funcvE1s) #[[ATTR1:[0-9]+]] // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 @@ -1502,7 +1502,7 @@ void foo() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[INIT]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.St* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[STRUCT_ST]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2) // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] @@ -1516,7 +1516,7 @@ void foo() { // // // CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1527,7 +1527,7 @@ void foo() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.St* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.St* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] @@ -1537,17 +1537,17 @@ void foo() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK5-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 { +// CHECK5-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK5-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1558,7 +1558,7 @@ void foo() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.St* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]] +// CHECK5-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.St* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -1566,17 +1566,17 @@ void foo() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK5-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 { +// CHECK5-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK5-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR1]] +// CHECK5-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR1]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1584,7 +1584,7 @@ void foo() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([[STRUCT_ST:%.*]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]] +// CHECK5-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.St* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0) // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -1592,7 +1592,7 @@ void foo() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1617,7 +1617,7 @@ void foo() { // CHECK5: omp.arraycpy.body: // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.St* [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(8) %struct.St* @_ZN2StaSERKS_(%struct.St* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.St* noundef nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK5-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(8) %struct.St* @_ZN2StaSERKS_(%struct.St* nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.St* nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_ST]], %struct.St* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_ST]], %struct.St* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.St* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] @@ -1630,7 +1630,7 @@ void foo() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2StaSERKS_ -// CHECK5-SAME: (%struct.St* noundef [[THIS:%.*]], %struct.St* noundef nonnull align 4 dereferenceable(8) [[TMP0:%.*]]) #[[ATTR0]] align 2 { +// CHECK5-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* nonnull align 4 dereferenceable(8) [[TMP0:%.*]]) #[[ATTR0]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca %struct.St*, align 8 @@ -1641,7 +1641,7 @@ void foo() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK5-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 { +// CHECK5-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK5-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1654,7 +1654,7 @@ void foo() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK5-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 { +// CHECK5-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK5-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1669,50 +1669,50 @@ void foo() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[REF_TMP]]) -// CHECK11-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[TEST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK11-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* @_ZGVZ4mainE5s_arr, align 1 // CHECK11-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK11-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] +// CHECK11-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] // CHECK11: init.check: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK11-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR4]] // CHECK11-NEXT: store i8 1, i8* @_ZGVZ4mainE5s_arr, align 1 // CHECK11-NEXT: br label [[INIT_END]] // CHECK11: init.end: // CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* @_ZGVZ4mainE3var, align 1 // CHECK11-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0 -// CHECK11-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF3]] +// CHECK11-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]] // CHECK11: init.check2: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @_ZZ4mainE3var, float noundef 3.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00) // CHECK11-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR4]] // CHECK11-NEXT: store i8 1, i8* @_ZGVZ4mainE3var, align 1 // CHECK11-NEXT: br label [[INIT_END3]] // CHECK11: init.end3: // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var, [2 x i32]* @_ZZ4mainE3vec, [2 x %struct.S]* @_ZZ4mainE5s_arr, %struct.S* @_ZZ4mainE3var) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var) -// CHECK11-NEXT: [[CALL4:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL4:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL4]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP4]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_ -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 @@ -1723,17 +1723,17 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1741,12 +1741,12 @@ void foo() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section ".text.startup" { +// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section ".text.startup" { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1754,7 +1754,7 @@ void foo() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0) // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -1762,7 +1762,7 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1793,13 +1793,13 @@ void foo() { // CHECK11: omp.arraycpy.body: // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK11-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2) // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK11: omp.arraycpy.done1: -// CHECK11-NEXT: [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef @_ZZ4mainE3var, %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP3]]) +// CHECK11-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, %struct.S* nonnull align 4 dereferenceable(4) [[TMP3]]) // CHECK11-NEXT: br label [[COPYIN_NOT_MASTER_END]] // CHECK11: copyin.not.master.end: // CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1807,12 +1807,12 @@ void foo() { // CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP10]]) // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 // CHECK11-NEXT: store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4 -// CHECK11-NEXT: [[CALL3:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) +// CHECK11-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1843,37 +1843,37 @@ void foo() { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[REF_TMP]]) -// CHECK11-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK11-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP0:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8 // CHECK11-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK11-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3]] +// CHECK11-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]] // CHECK11: init.check: -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 noundef 1) -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2) // CHECK11-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor.2, i8* null, i8* @__dso_handle) #[[ATTR4]] // CHECK11-NEXT: store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8 // CHECK11-NEXT: br label [[INIT_END]] // CHECK11: init.end: // CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8 // CHECK11-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0 -// CHECK11-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF3]] +// CHECK11-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]] // CHECK11: init.check2: -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef @_ZZ5tmainIiET_vE3var, i32 noundef 3) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3) // CHECK11-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR4]] // CHECK11-NEXT: store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8 // CHECK11-NEXT: br label [[INIT_END3]] // CHECK11: init.end3: // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var, [2 x i32]* @_ZZ5tmainIiET_vE3vec, [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, %struct.S.0* @_ZZ5tmainIiET_vE3var) // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: ret i32 0 // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1886,7 +1886,7 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1895,7 +1895,7 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1912,17 +1912,17 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_ -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1933,17 +1933,17 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1951,12 +1951,12 @@ void foo() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.2 -// CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" { +// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1964,7 +1964,7 @@ void foo() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0) // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -1972,7 +1972,7 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2003,13 +2003,13 @@ void foo() { // CHECK11: omp.arraycpy.body: // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK11-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK11-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S_0]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2) // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK11: omp.arraycpy.done1: -// CHECK11-NEXT: [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef @_ZZ5tmainIiET_vE3var, %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP3]]) +// CHECK11-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]]) // CHECK11-NEXT: br label [[COPYIN_NOT_MASTER_END]] // CHECK11: copyin.not.master.end: // CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 @@ -2017,12 +2017,12 @@ void foo() { // CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128 // CHECK11-NEXT: store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128 -// CHECK11-NEXT: [[CALL3:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* noundef nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) +// CHECK11-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2046,7 +2046,7 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2058,7 +2058,7 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2067,7 +2067,7 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2094,50 +2094,50 @@ void foo() { // CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[REF_TMP]]) -// CHECK12-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[TEST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK12-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4:[0-9]+]] // CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* @_ZGVZ4mainE5s_arr, align 1 // CHECK12-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK12-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] +// CHECK12-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] // CHECK12: init.check: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK12-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR4]] // CHECK12-NEXT: store i8 1, i8* @_ZGVZ4mainE5s_arr, align 1 // CHECK12-NEXT: br label [[INIT_END]] // CHECK12: init.end: // CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* @_ZGVZ4mainE3var, align 1 // CHECK12-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0 -// CHECK12-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF3]] +// CHECK12-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]] // CHECK12: init.check2: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @_ZZ4mainE3var, float noundef 3.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00) // CHECK12-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR4]] // CHECK12-NEXT: store i8 1, i8* @_ZGVZ4mainE3var, align 1 // CHECK12-NEXT: br label [[INIT_END3]] // CHECK12: init.end3: // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var, [2 x i32]* @_ZZ4mainE3vec, [2 x %struct.S]* @_ZZ4mainE5s_arr, %struct.S* @_ZZ4mainE3var) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var) -// CHECK12-NEXT: [[CALL4:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL4:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL4]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP4]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_ -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 @@ -2148,17 +2148,17 @@ void foo() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2166,12 +2166,12 @@ void foo() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section ".text.startup" { +// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section ".text.startup" { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2179,7 +2179,7 @@ void foo() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0) // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done1: @@ -2187,7 +2187,7 @@ void foo() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2218,13 +2218,13 @@ void foo() { // CHECK12: omp.arraycpy.body: // CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK12-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2) // CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK12: omp.arraycpy.done1: -// CHECK12-NEXT: [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef @_ZZ4mainE3var, %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP3]]) +// CHECK12-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, %struct.S* nonnull align 4 dereferenceable(4) [[TMP3]]) // CHECK12-NEXT: br label [[COPYIN_NOT_MASTER_END]] // CHECK12: copyin.not.master.end: // CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 @@ -2232,12 +2232,12 @@ void foo() { // CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP10]]) // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4 // CHECK12-NEXT: store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4 -// CHECK12-NEXT: [[CALL3:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) +// CHECK12-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2268,37 +2268,37 @@ void foo() { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[REF_TMP]]) -// CHECK12-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK12-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP0:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8 // CHECK12-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK12-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3]] +// CHECK12-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]] // CHECK12: init.check: -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 noundef 1) -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2) // CHECK12-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor.2, i8* null, i8* @__dso_handle) #[[ATTR4]] // CHECK12-NEXT: store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8 // CHECK12-NEXT: br label [[INIT_END]] // CHECK12: init.end: // CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8 // CHECK12-NEXT: [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0 -// CHECK12-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF3]] +// CHECK12-NEXT: br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]] // CHECK12: init.check2: -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef @_ZZ5tmainIiET_vE3var, i32 noundef 3) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3) // CHECK12-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR4]] // CHECK12-NEXT: store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8 // CHECK12-NEXT: br label [[INIT_END3]] // CHECK12: init.end3: // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var, [2 x i32]* @_ZZ5tmainIiET_vE3vec, [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, %struct.S.0* @_ZZ5tmainIiET_vE3var) // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var) -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: ret i32 0 // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2311,7 +2311,7 @@ void foo() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2320,7 +2320,7 @@ void foo() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2337,17 +2337,17 @@ void foo() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_ -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -2358,17 +2358,17 @@ void foo() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2376,12 +2376,12 @@ void foo() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.2 -// CHECK12-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" { +// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2389,7 +2389,7 @@ void foo() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0) // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done1: @@ -2397,7 +2397,7 @@ void foo() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2428,13 +2428,13 @@ void foo() { // CHECK12: omp.arraycpy.body: // CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK12-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK12-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S_0]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2) // CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK12: omp.arraycpy.done1: -// CHECK12-NEXT: [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef @_ZZ5tmainIiET_vE3var, %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP3]]) +// CHECK12-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]]) // CHECK12-NEXT: br label [[COPYIN_NOT_MASTER_END]] // CHECK12: copyin.not.master.end: // CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 @@ -2442,12 +2442,12 @@ void foo() { // CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128 // CHECK12-NEXT: store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128 -// CHECK12-NEXT: [[CALL3:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* noundef nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) +// CHECK12-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2471,7 +2471,7 @@ void foo() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2483,7 +2483,7 @@ void foo() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2492,7 +2492,7 @@ void foo() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2518,12 +2518,12 @@ void foo() { // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK13-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK13-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK13-NEXT: ret i32 0 // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2545,7 +2545,7 @@ void foo() { // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK13-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]]) // CHECK13-NEXT: store volatile i32 1, i32* @g, align 128 -// CHECK13-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK13-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK13-NEXT: ret void // // @@ -2561,12 +2561,12 @@ void foo() { // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK14-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK14-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// CHECK14-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) // CHECK14-NEXT: ret i32 0 // // // CHECK14-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK14-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK14-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK14-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -2578,7 +2578,7 @@ void foo() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2601,12 +2601,12 @@ void foo() { // CHECK14-NEXT: store volatile i32 1, i32* @g, align 128 // CHECK14-NEXT: [[TMP6:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK14-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to void (i8*)* -// CHECK14-NEXT: call void [[TMP7]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to i8*)) +// CHECK14-NEXT: call void [[TMP7]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to i8*)) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@g_block_invoke -// CHECK14-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK14-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -2627,12 +2627,12 @@ void foo() { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[TMP0:%.*]] = load i8, i8* @_ZGVZ10array_funcvE1s, align 1 // CHECK15-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK15-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] +// CHECK15-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] // CHECK15: init.check: // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[INIT_CHECK]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[ARRAYCTOR_CUR]], i64 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.St* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[STRUCT_ST]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2) // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] @@ -2646,17 +2646,17 @@ void foo() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK15-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK15-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] section ".text.startup" { +// CHECK15-SAME: (i8* [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] section ".text.startup" { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK15-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2664,7 +2664,7 @@ void foo() { // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([[STRUCT_ST:%.*]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.St* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0) // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done1: @@ -2672,17 +2672,17 @@ void foo() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK15-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK15-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], [2 x %struct.St]* noundef nonnull align 4 dereferenceable(16) [[S:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], [2 x %struct.St]* nonnull align 4 dereferenceable(16) [[S:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2705,7 +2705,7 @@ void foo() { // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.St* [ [[TMP5]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(8) %struct.St* @_ZN2StaSERKS_(%struct.St* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.St* noundef nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK15-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(8) %struct.St* @_ZN2StaSERKS_(%struct.St* nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.St* nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_ST]], %struct.St* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_ST]], %struct.St* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.St* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_ST]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2) @@ -2720,7 +2720,7 @@ void foo() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StaSERKS_ -// CHECK15-SAME: (%struct.St* noundef [[THIS:%.*]], %struct.St* noundef nonnull align 4 dereferenceable(8) [[TMP0:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* nonnull align 4 dereferenceable(8) [[TMP0:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK15-NEXT: [[DOTADDR:%.*]] = alloca %struct.St*, align 8 @@ -2731,7 +2731,7 @@ void foo() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK15-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -2744,7 +2744,7 @@ void foo() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK15-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -2755,7 +2755,7 @@ void foo() { // CHECK16-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK16-SAME: () #[[ATTR0:[0-9]+]] section ".text.startup" { // CHECK16-NEXT: entry: -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z6t_initv() +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z6t_initv() // CHECK16-NEXT: store i32 [[CALL]], i32* @t, align 4 // CHECK16-NEXT: ret void // @@ -2768,7 +2768,7 @@ void foo() { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2780,7 +2780,7 @@ void foo() { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T:%.*]]) #[[ATTR3]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T:%.*]]) #[[ATTR3]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2820,7 +2820,7 @@ void foo() { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[TMP0:%.*]] = load i8, i8* @__tls_guard, align 1 // CHECK16-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK16-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF5:![0-9]+]] +// CHECK16-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF4:![0-9]+]] // CHECK16: init: // CHECK16-NEXT: store i8 1, i8* @__tls_guard, align 1 // CHECK16-NEXT: call void @__cxx_global_var_init() @@ -2828,3 +2828,4 @@ void foo() { // CHECK16: exit: // CHECK16-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_firstprivate_codegen.cpp index 2b40e9a19f6901321cd201f1ae94abe58eeaee1a..35eb8d05123e656258e76e369a4cf33d59a7f987 100644 --- a/clang/test/OpenMP/parallel_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_firstprivate_codegen.cpp @@ -1,31 +1,31 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef ARRAY #ifndef HEADER diff --git a/clang/test/OpenMP/parallel_for_codegen.cpp b/clang/test/OpenMP/parallel_for_codegen.cpp index 9de1f87d57c87b0cdc84faa5d525561d748f57bf..3550e76f21c4beb81f7c4ad4c0affaaa83c313ff 100644 --- a/clang/test/OpenMP/parallel_for_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_codegen.cpp @@ -259,7 +259,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -368,7 +368,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -383,7 +383,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -477,7 +477,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -492,7 +492,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -586,7 +586,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -601,7 +601,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -712,7 +712,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -727,7 +727,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -814,7 +814,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -829,7 +829,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -916,7 +916,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -935,7 +935,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1073,7 +1073,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1090,7 +1090,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1199,7 +1199,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z12parallel_forPfi -// CHECK1-SAME: (float* noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1225,7 +1225,7 @@ void range_for_collapsed() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], i64 [[VLA:%.*]], i64 [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1295,7 +1295,7 @@ void range_for_collapsed() { // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127 // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = invoke noundef i32 @_Z3foov() +// CHECK1-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float @@ -1373,7 +1373,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1482,7 +1482,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1497,7 +1497,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1591,7 +1591,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1606,7 +1606,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1700,7 +1700,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1715,7 +1715,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1826,7 +1826,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1841,7 +1841,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1928,7 +1928,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -1943,7 +1943,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2030,7 +2030,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2049,7 +2049,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2187,7 +2187,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2204,7 +2204,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2313,7 +2313,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z12parallel_forPfi -// CHECK2-SAME: (float* noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -2339,7 +2339,7 @@ void range_for_collapsed() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], i64 [[VLA:%.*]], i64 [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2409,7 +2409,7 @@ void range_for_collapsed() { // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127 // CHECK2-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = invoke noundef i32 @_Z3foov() +// CHECK2-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float @@ -2487,7 +2487,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2596,7 +2596,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2611,7 +2611,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2705,7 +2705,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2720,7 +2720,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2814,7 +2814,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2829,7 +2829,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2940,7 +2940,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -2955,7 +2955,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3042,7 +3042,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3057,7 +3057,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3144,7 +3144,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3163,7 +3163,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3301,7 +3301,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK3-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3318,7 +3318,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3427,7 +3427,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z12parallel_forPfi -// CHECK3-SAME: (float* noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -3453,7 +3453,7 @@ void range_for_collapsed() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], i64 [[VLA:%.*]], i64 [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3523,7 +3523,7 @@ void range_for_collapsed() { // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127 // CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = invoke noundef i32 @_Z3foov() +// CHECK3-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK3: invoke.cont: // CHECK3-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float @@ -3601,7 +3601,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3710,7 +3710,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3725,7 +3725,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3819,7 +3819,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3834,7 +3834,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3928,7 +3928,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -3943,7 +3943,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4054,7 +4054,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4069,7 +4069,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4156,7 +4156,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4171,7 +4171,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4258,7 +4258,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4277,7 +4277,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4415,7 +4415,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK4-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4432,7 +4432,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4541,7 +4541,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@_Z12parallel_forPfi -// CHECK4-SAME: (float* noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -4567,7 +4567,7 @@ void range_for_collapsed() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], i64 [[VLA:%.*]], i64 [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4637,7 +4637,7 @@ void range_for_collapsed() { // CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127 // CHECK4-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = invoke noundef i32 @_Z3foov() +// CHECK4-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK4: invoke.cont: // CHECK4-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float @@ -4715,7 +4715,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG13:![0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG13:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4824,7 +4824,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG21:![0-9]+]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG21:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4839,7 +4839,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG24:![0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG24:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4933,7 +4933,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG30:![0-9]+]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG30:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -4948,7 +4948,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG33:![0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG33:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5042,7 +5042,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG39:![0-9]+]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG39:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -5057,7 +5057,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG42:![0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG42:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5168,7 +5168,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG49:![0-9]+]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG49:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -5183,7 +5183,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG52:![0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG52:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5270,7 +5270,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG61:![0-9]+]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG61:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -5285,7 +5285,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG64:![0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG64:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5372,7 +5372,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG73:![0-9]+]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG73:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -5391,7 +5391,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG78:![0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG78:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5529,7 +5529,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG88:![0-9]+]] { +// CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG88:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -5546,7 +5546,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG92:![0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG92:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5655,7 +5655,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z12parallel_forPfi -// CHECK5-SAME: (float* noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] !dbg [[DBG104:![0-9]+]] { +// CHECK5-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] !dbg [[DBG104:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -5681,7 +5681,7 @@ void range_for_collapsed() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG108:![0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], i64 [[VLA:%.*]], i64 [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG108:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5751,7 +5751,7 @@ void range_for_collapsed() { // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127, !dbg [[DBG110]] // CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG110]] // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG110]] -// CHECK5-NEXT: [[CALL:%.*]] = invoke noundef i32 @_Z3foov() +// CHECK5-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG111:![0-9]+]] // CHECK5: invoke.cont: // CHECK5-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float, !dbg [[DBG111]] @@ -5829,7 +5829,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5938,7 +5938,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -5953,7 +5953,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6047,7 +6047,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -6062,7 +6062,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6156,7 +6156,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -6171,7 +6171,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6282,7 +6282,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -6297,7 +6297,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6384,7 +6384,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -6399,7 +6399,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6486,7 +6486,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -6505,7 +6505,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6643,7 +6643,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ -// CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 @@ -6660,7 +6660,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6769,7 +6769,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@_Z12parallel_forPfi -// CHECK6-SAME: (float* noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -6795,7 +6795,7 @@ void range_for_collapsed() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], i64 [[VLA:%.*]], i64 [[N:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6865,7 +6865,7 @@ void range_for_collapsed() { // CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127 // CHECK6-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3foov() +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z3foov() // CHECK6-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64 @@ -7031,7 +7031,7 @@ void range_for_collapsed() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7150,7 +7150,7 @@ void range_for_collapsed() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7460,7 +7460,7 @@ void range_for_collapsed() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7579,7 +7579,7 @@ void range_for_collapsed() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/parallel_for_lastprivate_conditional.cpp b/clang/test/OpenMP/parallel_for_lastprivate_conditional.cpp index 9ca2e8bc8a0236dc7294708585366fc4425cd60f..9a9cd8dc148966ed748a226d82739ea26831caab 100644 --- a/clang/test/OpenMP/parallel_for_lastprivate_conditional.cpp +++ b/clang/test/OpenMP/parallel_for_lastprivate_conditional.cpp @@ -45,7 +45,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -191,7 +191,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -237,7 +237,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -261,7 +261,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -293,7 +293,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -439,7 +439,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -485,7 +485,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -509,7 +509,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -528,3 +528,4 @@ int main() { // CHECK2-NEXT: store atomic volatile i8 1, i8* [[TMP5]] unordered, align 1 // CHECK2-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_for_linear_codegen.cpp b/clang/test/OpenMP/parallel_for_linear_codegen.cpp index db2f3f75fb9cd28d10e9cc051f10ac0a5922f2a7..19ab3938a970016951dedbe30d719c5fbd90cb2b 100644 --- a/clang/test/OpenMP/parallel_for_linear_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_linear_codegen.cpp @@ -94,30 +94,30 @@ int main() { // CHECK1-NEXT: [[PVAR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: [[LVAR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TEST]], i32 0, i32 0 // CHECK1-NEXT: store float* [[F]], float** [[PVAR]], align 8 // CHECK1-NEXT: store i64 0, i64* [[LVAR]], align 8 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64*)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[PVAR]], i64* [[LVAR]]) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP0]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i64* noundef nonnull align 8 dereferenceable(8) [[LVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i64* nonnull align 8 dereferenceable(8) [[LVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -227,27 +227,27 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[PVAR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[LVAR:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 // CHECK1-NEXT: store i32* [[F]], i32** [[PVAR]], align 8 // CHECK1-NEXT: store i32 0, i32* [[LVAR]], align 4 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32**, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32** [[PVAR]], i32* [[LVAR]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -258,17 +258,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[LVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[LVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -372,17 +372,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -393,7 +393,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -402,7 +402,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -418,30 +418,30 @@ int main() { // CHECK2-NEXT: [[PVAR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: [[LVAR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TEST]], i32 0, i32 0 // CHECK2-NEXT: store float* [[F]], float** [[PVAR]], align 8 // CHECK2-NEXT: store i64 0, i64* [[LVAR]], align 8 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64*)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[PVAR]], i64* [[LVAR]]) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4:[0-9]+]] // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP0]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i64* noundef nonnull align 8 dereferenceable(8) [[LVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i64* nonnull align 8 dereferenceable(8) [[LVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -551,27 +551,27 @@ int main() { // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK2-NEXT: [[PVAR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[LVAR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 // CHECK2-NEXT: store i32* [[F]], i32** [[PVAR]], align 8 // CHECK2-NEXT: store i32 0, i32* [[LVAR]], align 4 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32**, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32** [[PVAR]], i32* [[LVAR]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -582,17 +582,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[LVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[LVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -696,17 +696,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -717,7 +717,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -726,7 +726,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -740,12 +740,12 @@ int main() { // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -808,7 +808,7 @@ int main() { // CHECK3-NEXT: store i32 [[ADD5]], i32* [[G1]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store i32* [[G1]], i32** [[TMP13]], align 8 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -840,12 +840,12 @@ int main() { // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// CHECK4-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -857,7 +857,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -938,7 +938,7 @@ int main() { // CHECK4-NEXT: [[TMP16:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP17:%.*]] = load i8*, i8** [[TMP15]], align 8 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8* [[TMP17]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP18]](i8* noundef [[TMP16]]) +// CHECK4-NEXT: call void [[TMP18]](i8* [[TMP16]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -964,7 +964,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 @@ -975,3 +975,4 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 // CHECK4-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp index 0b78b407dd0757e8886258869f9147e213f5a2b0..f90e9027997ab5bafb7c19703b59f985cfa9a8cf 100644 --- a/clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp @@ -36,7 +36,7 @@ int main(int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -48,7 +48,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -329,7 +329,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init. -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -342,7 +342,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -360,7 +360,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -382,7 +382,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -413,7 +413,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -427,7 +427,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -511,7 +511,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -560,7 +560,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -572,7 +572,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -853,7 +853,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init. -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -866,7 +866,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -884,7 +884,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -906,7 +906,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -937,7 +937,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -951,7 +951,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1035,7 +1035,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 diff --git a/clang/test/OpenMP/parallel_for_scan_codegen.cpp b/clang/test/OpenMP/parallel_for_scan_codegen.cpp index 6988e2a42df008646045a3eca79e9546dd8a632f..7e42d7ec49e061f3102072ee2e80b62b4d562972 100644 --- a/clang/test/OpenMP/parallel_for_scan_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_scan_codegen.cpp @@ -13,7 +13,7 @@ void foo(int n); void bar(); -// CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 noundef %n) +// CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 %n) void baz(int n) { static float a[10]; static double b; diff --git a/clang/test/OpenMP/parallel_for_simd_aligned_codegen.cpp b/clang/test/OpenMP/parallel_for_simd_aligned_codegen.cpp index a7889ae8edf979d9c780c7e43382f3b8012f1ed5..5e8756d37d91ed3a5506d2f93137ecee69dc0491 100644 --- a/clang/test/OpenMP/parallel_for_simd_aligned_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_simd_aligned_codegen.cpp @@ -22,7 +22,7 @@ void foo(float *c) { #endif // CHECK1-LABEL: define {{[^@]+}}@_Z3fooPf -// CHECK1-SAME: (float* noundef [[C:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (float* [[C:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 @@ -31,7 +31,7 @@ void foo(float *c) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -71,23 +71,23 @@ void foo(float *c) { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -103,7 +103,7 @@ void foo(float *c) { // // // CHECK2-LABEL: define {{[^@]+}}@_Z3fooPf -// CHECK2-SAME: (float* noundef [[C:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (float* [[C:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 @@ -112,7 +112,7 @@ void foo(float *c) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -152,23 +152,23 @@ void foo(float *c) { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -184,7 +184,7 @@ void foo(float *c) { // // // CHECK3-LABEL: define {{[^@]+}}@_Z3fooPf -// CHECK3-SAME: (float* noundef [[C:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (float* [[C:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 @@ -193,7 +193,7 @@ void foo(float *c) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -233,23 +233,23 @@ void foo(float *c) { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -265,7 +265,7 @@ void foo(float *c) { // // // CHECK4-LABEL: define {{[^@]+}}@_Z3fooPf -// CHECK4-SAME: (float* noundef [[C:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (float* [[C:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 @@ -274,7 +274,7 @@ void foo(float *c) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -314,23 +314,23 @@ void foo(float *c) { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: diff --git a/clang/test/OpenMP/parallel_for_simd_codegen.cpp b/clang/test/OpenMP/parallel_for_simd_codegen.cpp index aee36ba4c6109d8015f45deebeb391cc53b2de7d..eca2f18242c0a50e02e5739182916c8a4b8879e2 100644 --- a/clang/test/OpenMP/parallel_for_simd_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_simd_codegen.cpp @@ -25,7 +25,7 @@ long long get_val() { extern void mayThrow(); mayThrow(); return 0; } double *g_ptr; -// CHECK-LABEL: define {{.*void}} @{{.*}}simple{{.*}}(float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}) +// CHECK-LABEL: define {{.*void}} @{{.*}}simple{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) void simple(float *a, float *b, float *c, float *d) { // CHECK: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( // CHECK: [[K0:%.+]] = call {{.*}}i64 @{{.*}}get_val @@ -388,7 +388,7 @@ int templ1(T a, T *z) { } // Instatiation templ1 -// CHECK-LABEL: define {{.*i32}} @{{.*}}templ1{{.*}}(float noundef {{.+}}, float* noundef {{.+}}) +// CHECK-LABEL: define {{.*i32}} @{{.*}}templ1{{.*}}(float {{.+}}, float* {{.+}}) // CHECK: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( void inst_templ1() { float a; @@ -809,7 +809,7 @@ int bar() { extern void mayThrow(); mayThrow(); return 0; }; void parallel_simd(float *a) { #pragma omp parallel for simd // TERM_DEBUG-NOT: __kmpc_global_thread_num - // TERM_DEBUG: invoke noundef i32 {{.*}}bar{{.*}}() + // TERM_DEBUG: invoke i32 {{.*}}bar{{.*}}() // TERM_DEBUG: unwind label %[[TERM_LPAD:[a-zA-Z0-9\.]+]], // TERM_DEBUG-NOT: __kmpc_global_thread_num // TERM_DEBUG: [[TERM_LPAD]] diff --git a/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp b/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp index 0a80db1c6caa503d5c1f229b79b9f178be130aef..71c6447c0ff95043d54f5c2993fcba3c919ab4b0 100644 --- a/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp @@ -13,7 +13,7 @@ void foo(); void bar(); -// CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 noundef %n) +// CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 %n) void baz(int n) { static float a[10]; static double b; diff --git a/clang/test/OpenMP/parallel_if_codegen.cpp b/clang/test/OpenMP/parallel_if_codegen.cpp index b508070aa076341cadddfe9b742b46969af5d46c..191ec7cf5059e3afeb87afb745e0c50cae54d57c 100644 --- a/clang/test/OpenMP/parallel_if_codegen.cpp +++ b/clang/test/OpenMP/parallel_if_codegen.cpp @@ -75,7 +75,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -93,7 +93,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -134,12 +134,12 @@ int main() { // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP2]]) +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -150,7 +150,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -161,7 +161,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -172,7 +172,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK1-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -205,7 +205,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -216,7 +216,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -227,7 +227,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -245,7 +245,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -263,7 +263,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -304,12 +304,12 @@ int main() { // CHECK2-NEXT: br label [[OMP_IF_END]] // CHECK2: omp_if.end: // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP2]]) +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -320,7 +320,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -331,7 +331,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -342,7 +342,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK2-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -375,7 +375,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -386,7 +386,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -397,7 +397,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -415,7 +415,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -433,7 +433,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -474,12 +474,12 @@ int main() { // CHECK5-NEXT: br label [[OMP_IF_END]] // CHECK5: omp_if.end: // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP2]]) +// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -490,7 +490,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -501,7 +501,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -512,7 +512,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK5-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK5-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -545,7 +545,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -556,7 +556,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -567,7 +567,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -585,7 +585,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -603,7 +603,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -644,12 +644,12 @@ int main() { // CHECK6-NEXT: br label [[OMP_IF_END]] // CHECK6: omp_if.end: // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP2]]) +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -660,7 +660,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -671,7 +671,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -682,7 +682,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK6-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK6-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -715,7 +715,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -726,7 +726,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -737,7 +737,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -755,7 +755,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -773,7 +773,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -814,12 +814,12 @@ int main() { // CHECK7-NEXT: br label [[OMP_IF_END]] // CHECK7: omp_if.end: // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP2]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -830,7 +830,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -841,7 +841,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -852,7 +852,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK7-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK7-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -885,7 +885,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -896,7 +896,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -907,7 +907,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/parallel_if_codegen_PR51349.cpp b/clang/test/OpenMP/parallel_if_codegen_PR51349.cpp index 5c2455588a2cbefad7bb22a44824766bfcbe4845..a00b5ec95ca0f9d20895f5a32a95de7f4abc52a1 100644 --- a/clang/test/OpenMP/parallel_if_codegen_PR51349.cpp +++ b/clang/test/OpenMP/parallel_if_codegen_PR51349.cpp @@ -28,7 +28,7 @@ void foo() { // // CHECK: Function Attrs: noinline norecurse nounwind // CHECK-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/parallel_master_codegen.cpp b/clang/test/OpenMP/parallel_master_codegen.cpp index 6d803b0132906e5b8fbdfe43dcdbb6b906ea4f33..dc8343941a67c97a36385d9ccbab0a22eed9bc67 100644 --- a/clang/test/OpenMP/parallel_master_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_codegen.cpp @@ -301,7 +301,7 @@ void parallel_master_allocate() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -359,7 +359,7 @@ void parallel_master_allocate() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -411,7 +411,7 @@ void parallel_master_allocate() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -442,7 +442,7 @@ void parallel_master_allocate() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -473,7 +473,7 @@ void parallel_master_allocate() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -506,7 +506,7 @@ void parallel_master_allocate() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -544,7 +544,7 @@ void parallel_master_allocate() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -582,7 +582,7 @@ void parallel_master_allocate() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -611,28 +611,28 @@ void parallel_master_allocate() { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 // CHECK17-NEXT: [[Y_CASTED:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[A]]) +// CHECK17-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[A]]) // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ36parallel_master_default_firstprivatevE1y, align 4 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[Y_CASTED]] to i32* // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[Y_CASTED]], align 8 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[A]], i64 [[TMP1]]) -// CHECK17-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[A]]) #[[ATTR3:[0-9]+]] +// CHECK17-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[A]]) #[[ATTR3:[0-9]+]] // CHECK17-NEXT: ret void // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK17-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK17-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK17-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK17-NEXT: ret void // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.St* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i64 noundef [[Y:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* nonnull align 4 dereferenceable(8) [[A:%.*]], i64 [[Y:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -671,17 +671,17 @@ void parallel_master_allocate() { // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK17-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] comdat align 2 { +// CHECK17-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR3]] +// CHECK17-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK17-NEXT: ret void // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK17-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { +// CHECK17-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -694,7 +694,7 @@ void parallel_master_allocate() { // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK17-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { +// CHECK17-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -707,28 +707,28 @@ void parallel_master_allocate() { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 // CHECK18-NEXT: [[Y_CASTED:%.*]] = alloca i64, align 8 -// CHECK18-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[A]]) +// CHECK18-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[A]]) // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ36parallel_master_default_firstprivatevE1y, align 4 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[Y_CASTED]] to i32* // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[Y_CASTED]], align 8 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[A]], i64 [[TMP1]]) -// CHECK18-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[A]]) #[[ATTR3:[0-9]+]] +// CHECK18-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[A]]) #[[ATTR3:[0-9]+]] // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK18-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK18-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK18-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.St* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i64 noundef [[Y:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* nonnull align 4 dereferenceable(8) [[A:%.*]], i64 [[Y:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -767,17 +767,17 @@ void parallel_master_allocate() { // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK18-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] comdat align 2 { +// CHECK18-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR3]] +// CHECK18-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK18-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { +// CHECK18-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -790,7 +790,7 @@ void parallel_master_allocate() { // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK18-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { +// CHECK18-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -812,7 +812,7 @@ void parallel_master_allocate() { // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -850,7 +850,7 @@ void parallel_master_allocate() { // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -882,7 +882,7 @@ void parallel_master_allocate() { // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -924,7 +924,7 @@ void parallel_master_allocate() { // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -966,7 +966,7 @@ void parallel_master_allocate() { // // // CHECK29-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK29-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK29-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK29-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1005,3 +1005,4 @@ void parallel_master_allocate() { // CHECK29-SAME: () #[[ATTR4:[0-9]+]] comdat { // CHECK29-NEXT: ret i32* @a // +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp b/clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp index df366df3cdec5d4a43b0b050b1d0009b23c1a5ac..3c75c4c74c710168fe595f51f38cb3fdcc76eec0 100644 --- a/clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp @@ -36,7 +36,7 @@ int main(int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -48,7 +48,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -284,7 +284,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init. -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -297,7 +297,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -315,7 +315,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -337,7 +337,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -368,7 +368,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -382,7 +382,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -466,7 +466,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -515,7 +515,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -527,7 +527,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -763,7 +763,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init. -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -776,7 +776,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -794,7 +794,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -816,7 +816,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -847,7 +847,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -861,7 +861,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -945,7 +945,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 diff --git a/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp index eeb5b71ab08c2c3ba1c634ceddc47a804f7b576a..b0b1dfee0213671d0b6527d2f986f0c354d6803e 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_codegen.cpp @@ -51,7 +51,7 @@ struct S { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -121,7 +121,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -165,7 +165,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -241,7 +241,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -281,7 +281,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..4 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -357,7 +357,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -454,7 +454,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..7 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -615,7 +615,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -652,7 +652,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..10 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -751,12 +751,12 @@ struct S { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR7:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SC1Ei(%struct.S* noundef @s, i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1Ei -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -764,12 +764,12 @@ struct S { // CHECK1-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SC2Ei(%struct.S* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SC2Ei(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ei -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -793,7 +793,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -864,7 +864,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..13 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -977,7 +977,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1047,7 +1047,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1091,7 +1091,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1167,7 +1167,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1207,7 +1207,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..4 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1283,7 +1283,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1380,7 +1380,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..7 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1541,7 +1541,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1578,7 +1578,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..10 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1677,12 +1677,12 @@ struct S { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR7:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SC1Ei(%struct.S* noundef @s, i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC1Ei -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -1690,12 +1690,12 @@ struct S { // CHECK2-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SC2Ei(%struct.S* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SC2Ei(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ei -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -1719,7 +1719,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1790,7 +1790,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..13 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp index d23a4581a66aa709cf71c3eacc311adbe5758d75..5df64611fde5ae212b47d641edb0852eadfc22dd 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp @@ -93,7 +93,7 @@ int main() { // LAMBDA: store double 2.0{{.+}}, double* [[G_REF]] // LAMBDA: store double* %{{.+}}, double** %{{.+}}, - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -145,7 +145,7 @@ int main() { // BLOCKS: store double* %{{.+}}, double** %{{.+}}, // BLOCKS: store i{{[0-9]+}}* %{{.+}}, i{{[0-9]+}}** %{{.+}}, - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -258,7 +258,7 @@ int main() { // CHECK-NEXT: br label {{%?}}[[EXIT]] // CHECK: [[EXIT]] -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -277,7 +277,7 @@ int main() { // CHECK: store i{{[0-9]+}}* [[PRIV_SIVAR]], i{{[0-9]+}}** [[ARG5]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -305,7 +305,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0 @@ -322,7 +322,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_COPY_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %{{.+}}, [[KMP_TASK_MAIN_TY]]* noalias noundef %{{.+}}) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %{{.+}}, [[KMP_TASK_MAIN_TY]]* noalias %{{.+}}) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -402,7 +402,7 @@ int main() { // Start task. // CHECK: call void @__kmpc_taskloop(%struct.ident_t* @{{.+}}, i32 %{{.+}}, i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* bitcast (void ([[KMP_TASK_TMAIN_TY]]*, [[KMP_TASK_TMAIN_TY]]*, i32)* [[TMAIN_DUP:@.+]] to i8*)) -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %{{.+}}, i32** noalias noundef %{{.+}}, [2 x i32]** noalias noundef %{{.+}}, [2 x [[S_INT_TY]]]** noalias noundef %{{.+}}, [[S_INT_TY]]** noalias noundef %{{.+}}) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %{{.+}}, i32** noalias %{{.+}}, [2 x i32]** noalias %{{.+}}, [2 x [[S_INT_TY]]]** noalias %{{.+}}, [[S_INT_TY]]** noalias %{{.+}}) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -418,7 +418,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, // CHECK-DAG: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*, @@ -441,7 +441,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* %{{.+}}, i32 0, i32 0 @@ -458,7 +458,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_COPY_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp index 730dd4eb060a110c430c7de1d1c27ca53c23e28a..5b971bd16b471ddf31a9e5b908901b7fef3a934e 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp @@ -208,48 +208,48 @@ void loop() { // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TTT]]) -// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double 1.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[VAR]], double noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]], double 3.000000e+00) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]]) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TTT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 @@ -257,12 +257,12 @@ void loop() { // CHECK1-NEXT: store double [[A]], double* [[A_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef [[THIS1]], double noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]], double [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], %struct.S* nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -313,13 +313,13 @@ void loop() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP19]], i32 0, i32 1 -// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TMP21]]) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TMP21]]) // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP15]], i32 0, i32 3 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP22]] to i32 (i32, i8*)** // CHECK1-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_destructor. to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP23]], align 8 @@ -342,7 +342,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], %struct.S** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]], [2 x %struct.S]** noalias noundef [[TMP3:%.*]], [2 x i32]** noalias noundef [[TMP4:%.*]], i32** noalias noundef [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], %struct.S** noalias [[TMP1:%.*]], i32** noalias [[TMP2:%.*]], [2 x %struct.S]** noalias [[TMP3:%.*]], [2 x i32]** noalias [[TMP4:%.*]], i32** noalias [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S**, align 8 @@ -376,7 +376,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -521,7 +521,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK1-SAME: (%struct.kmp_task_t_with_privates* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { +// CHECK1-SAME: (%struct.kmp_task_t_with_privates* [[TMP0:%.*]], %struct.kmp_task_t_with_privates* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR7]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 @@ -541,18 +541,18 @@ void loop() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 1 -// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TMP9]]) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TMP9]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_destructor. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 @@ -563,14 +563,14 @@ void loop() { // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP2]], i32 0, i32 1 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TMP5]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: @@ -579,12 +579,12 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -598,37 +598,37 @@ void loop() { // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TTT]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TTT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -639,7 +639,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 @@ -653,7 +653,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -662,17 +662,17 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -680,12 +680,12 @@ void loop() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -734,13 +734,13 @@ void loop() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP18]], i32 0, i32 3 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TMP20]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP14]], i32 0, i32 3 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP21]] to i32 (i32, i8*)** // CHECK1-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.2*)* @.omp_task_destructor..7 to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP22]], align 8 @@ -763,7 +763,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map..4 -// CHECK1-SAME: (%struct..kmp_privates.t.3* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]], [2 x i32]** noalias noundef [[TMP2:%.*]], [2 x %struct.S.0]** noalias noundef [[TMP3:%.*]], %struct.S.0** noalias noundef [[TMP4:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (%struct..kmp_privates.t.3* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]], [2 x i32]** noalias [[TMP2:%.*]], [2 x %struct.S.0]** noalias [[TMP3:%.*]], %struct.S.0** noalias [[TMP4:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t.3*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -792,7 +792,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..5 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias [[TMP1:%.*]]) #[[ATTR7]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -930,7 +930,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_dup..6 -// CHECK1-SAME: (%struct.kmp_task_t_with_privates.2* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { +// CHECK1-SAME: (%struct.kmp_task_t_with_privates.2* [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR7]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 @@ -950,18 +950,18 @@ void loop() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP7]], i32 0, i32 3 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TMP9]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_destructor..7 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias [[TMP1:%.*]]) #[[ATTR7]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 @@ -972,14 +972,14 @@ void loop() { // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP2]], i32 0, i32 2 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 2 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 3 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TMP5]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: @@ -988,17 +988,17 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1009,7 +1009,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1023,7 +1023,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1042,48 +1042,48 @@ void loop() { // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TTT]]) -// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double 1.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[VAR]], double noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]], double 3.000000e+00) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]]) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] -// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TTT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 @@ -1091,12 +1091,12 @@ void loop() { // CHECK2-NEXT: store double [[A]], double* [[A_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef [[THIS1]], double noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]], double [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], %struct.S* nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1147,13 +1147,13 @@ void loop() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP19]], i32 0, i32 1 -// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TMP21]]) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TMP21]]) // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP15]], i32 0, i32 3 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP22]] to i32 (i32, i8*)** // CHECK2-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_destructor. to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP23]], align 8 @@ -1176,7 +1176,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], %struct.S** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]], [2 x %struct.S]** noalias noundef [[TMP3:%.*]], [2 x i32]** noalias noundef [[TMP4:%.*]], i32** noalias noundef [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], %struct.S** noalias [[TMP1:%.*]], i32** noalias [[TMP2:%.*]], [2 x %struct.S]** noalias [[TMP3:%.*]], [2 x i32]** noalias [[TMP4:%.*]], i32** noalias [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S**, align 8 @@ -1210,7 +1210,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1355,7 +1355,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK2-SAME: (%struct.kmp_task_t_with_privates* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { +// CHECK2-SAME: (%struct.kmp_task_t_with_privates* [[TMP0:%.*]], %struct.kmp_task_t_with_privates* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR7]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 @@ -1375,18 +1375,18 @@ void loop() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 1 -// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TMP9]]) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TMP9]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_destructor. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 @@ -1397,14 +1397,14 @@ void loop() { // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP2]], i32 0, i32 1 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1 -// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TMP5]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: @@ -1413,12 +1413,12 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIdED2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // @@ -1432,37 +1432,37 @@ void loop() { // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TTT]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TTT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1473,7 +1473,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 @@ -1487,7 +1487,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1496,17 +1496,17 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1514,12 +1514,12 @@ void loop() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1568,13 +1568,13 @@ void loop() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP18]], i32 0, i32 3 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TMP20]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP14]], i32 0, i32 3 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP21]] to i32 (i32, i8*)** // CHECK2-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.2*)* @.omp_task_destructor..7 to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP22]], align 8 @@ -1597,7 +1597,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map..4 -// CHECK2-SAME: (%struct..kmp_privates.t.3* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]], [2 x i32]** noalias noundef [[TMP2:%.*]], [2 x %struct.S.0]** noalias noundef [[TMP3:%.*]], %struct.S.0** noalias noundef [[TMP4:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (%struct..kmp_privates.t.3* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]], [2 x i32]** noalias [[TMP2:%.*]], [2 x %struct.S.0]** noalias [[TMP3:%.*]], %struct.S.0** noalias [[TMP4:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t.3*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -1626,7 +1626,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..5 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias [[TMP1:%.*]]) #[[ATTR7]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1764,7 +1764,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_dup..6 -// CHECK2-SAME: (%struct.kmp_task_t_with_privates.2* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { +// CHECK2-SAME: (%struct.kmp_task_t_with_privates.2* [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR7]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 @@ -1784,18 +1784,18 @@ void loop() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP7]], i32 0, i32 3 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TMP9]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_destructor..7 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias [[TMP1:%.*]]) #[[ATTR7]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 @@ -1806,14 +1806,14 @@ void loop() { // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP2]], i32 0, i32 2 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 2 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 3 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TMP5]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: @@ -1822,17 +1822,17 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1843,7 +1843,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1857,7 +1857,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1871,12 +1871,12 @@ void loop() { // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1922,7 +1922,7 @@ void loop() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], double** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], double** noalias [[TMP1:%.*]], i32** noalias [[TMP2:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca double**, align 8 @@ -1941,7 +1941,7 @@ void loop() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2029,7 +2029,7 @@ void loop() { // CHECK3-NEXT: store double* [[TMP30]], double** [[TMP36]], align 8, !noalias !14 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP_I]], i32 0, i32 1 // CHECK3-NEXT: store i32* [[TMP31]], i32** [[TMP37]], align 8, !noalias !14 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP_I]]) #[[ATTR3]] +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP_I]]) #[[ATTR3]] // CHECK3-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14 // CHECK3-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP38]], 1 // CHECK3-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14 @@ -2049,7 +2049,7 @@ void loop() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK3-SAME: (%struct.kmp_task_t_with_privates* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR6]] { +// CHECK3-SAME: (%struct.kmp_task_t_with_privates* [[TMP0:%.*]], %struct.kmp_task_t_with_privates* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR6]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 @@ -2073,12 +2073,12 @@ void loop() { // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// CHECK4-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -2090,7 +2090,7 @@ void loop() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2136,7 +2136,7 @@ void loop() { // // // CHECK4-LABEL: define {{[^@]+}}@_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8 @@ -2151,7 +2151,7 @@ void loop() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK4-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], double** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK4-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], double** noalias [[TMP1:%.*]], i32** noalias [[TMP2:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca double**, align 8 @@ -2170,7 +2170,7 @@ void loop() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2276,7 +2276,7 @@ void loop() { // CHECK4-NEXT: [[TMP40:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL_I]] to i8* // CHECK4-NEXT: [[TMP41:%.*]] = load i8*, i8** [[TMP39]], align 8, !noalias !14 // CHECK4-NEXT: [[TMP42:%.*]] = bitcast i8* [[TMP41]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP42]](i8* noundef [[TMP40]]) #[[ATTR4]] +// CHECK4-NEXT: call void [[TMP42]](i8* [[TMP40]]) #[[ATTR4]] // CHECK4-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14 // CHECK4-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP43]], 1 // CHECK4-NEXT: store i32 [[ADD4_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14 @@ -2296,7 +2296,7 @@ void loop() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK4-SAME: (%struct.kmp_task_t_with_privates* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { +// CHECK4-SAME: (%struct.kmp_task_t_with_privates* [[TMP0:%.*]], %struct.kmp_task_t_with_privates* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR7]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 @@ -2314,7 +2314,7 @@ void loop() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St -// CHECK5-SAME: (i32 noundef [[N:%.*]], float* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (i32 [[N:%.*]], float* [[A:%.*]], %struct.St* [[S:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 @@ -2329,7 +2329,7 @@ void loop() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], %struct.St** noundef nonnull align 8 dereferenceable(8) [[S:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], %struct.St** nonnull align 8 dereferenceable(8) [[S:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2386,7 +2386,7 @@ void loop() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK5-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], float*** noalias noundef [[TMP1:%.*]], %struct.St*** noalias noundef [[TMP2:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK5-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], float*** noalias [[TMP1:%.*]], %struct.St*** noalias [[TMP2:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca float***, align 8 @@ -2405,7 +2405,7 @@ void loop() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK5-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2507,7 +2507,7 @@ void loop() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK5-SAME: (%struct.kmp_task_t_with_privates* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK5-SAME: (%struct.kmp_task_t_with_privates* [[TMP0:%.*]], %struct.kmp_task_t_with_privates* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 @@ -2533,7 +2533,7 @@ void loop() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2580,7 +2580,7 @@ void loop() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK6-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK6-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -2594,7 +2594,7 @@ void loop() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2689,7 +2689,7 @@ void loop() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK6-SAME: (%struct.kmp_task_t_with_privates* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK6-SAME: (%struct.kmp_task_t_with_privates* [[TMP0:%.*]], %struct.kmp_task_t_with_privates* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 diff --git a/clang/test/OpenMP/parallel_master_taskloop_private_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_private_codegen.cpp index d112a8d5837b43134bf788324d54a28384e7d674..0dd3046fe98fb5cdfc279110c4ed90d9437f7984 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_private_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_private_codegen.cpp @@ -77,7 +77,7 @@ int main() { // LAMBDA: [[SIVAR_REF:%.+]] = load i{{[0-9]+}}*, i{{[0-9]+}}** [[SIVAR_PTR_REF]] // LAMBDA: store i{{[0-9]+}} 3, i{{[0-9]+}}* [[SIVAR_REF]] - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 2; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -113,7 +113,7 @@ int main() { // BLOCKS-NOT: [[SIVAR]]{{[[^:word:]]}} // BLOCKS: ret - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 3; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -205,7 +205,7 @@ int main() { // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -221,7 +221,7 @@ int main() { // CHECK: store [2 x i32]* [[PRIV_VEC]], [2 x i32]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -247,7 +247,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0 @@ -264,7 +264,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_DEF_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -328,7 +328,7 @@ int main() { // CHECK-NOT: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -344,7 +344,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -368,7 +368,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* %{{.+}}, i32 0, i32 0 @@ -385,7 +385,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_DEF_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp index 1597a8840119c7198e6d93edcfbda249859d4d88..4674c77707246133bde127d01185fb32c9be2686 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp @@ -168,51 +168,51 @@ sum = 0.0; // CHECK-NEXT: br label {{%?}}[[EXIT]] // CHECK: [[EXIT]] -// CHECK: define internal void @[[RED_INIT1]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT1]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB1]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB1]](i8* %0, i8* %1) // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_INIT2]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT2]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: call void [[OMP_INIT1:@.+]]( // CHECK: ret void -// CHECK: define internal void [[OMP_COMB1:@.+]](%struct.S* noalias noundef %0, %struct.S* noalias noundef %1) +// CHECK: define internal void [[OMP_COMB1:@.+]](%struct.S* noalias %0, %struct.S* noalias %1) // CHECK: fadd float % -// CHECK: define internal void [[OMP_INIT1]](%struct.S* noalias noundef %0, %struct.S* noalias noundef %1) +// CHECK: define internal void [[OMP_INIT1]](%struct.S* noalias %0, %struct.S* noalias %1) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64( -// CHECK: define internal void @[[RED_FINI2]](i8* noundef %0) +// CHECK: define internal void @[[RED_FINI2]](i8* %0) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: call void @ // CHECK: ret void -// CHECK: define internal void @[[RED_COMB2]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB2]](i8* %0, i8* %1) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: call void [[OMP_COMB1]]( // CHECK: ret void -// CHECK: define internal void @[[RED_INIT3]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT3]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB3]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB3]](i8* %0, i8* %1) // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_INIT4]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT4]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB4]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB4]](i8* %0, i8* %1) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp index 0a19b39764b709b090419f4a7accb8d81a119f6d..2b3752cf01cdb68479cd6d01d60c4676ebea9e73 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp @@ -54,7 +54,7 @@ struct S { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -123,7 +123,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -167,7 +167,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -243,7 +243,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -283,7 +283,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..4 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -359,7 +359,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -462,7 +462,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -476,7 +476,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..7 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -653,7 +653,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK1-SAME: (%struct.kmp_task_t_with_privates.3* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (%struct.kmp_task_t_with_privates.3* [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates.3*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.3*, align 8 @@ -673,12 +673,12 @@ struct S { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SC1Ei(%struct.S* noundef @s, i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1Ei -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -686,12 +686,12 @@ struct S { // CHECK1-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SC2Ei(%struct.S* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SC2Ei(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ei -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -715,7 +715,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -786,7 +786,7 @@ struct S { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..10 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -899,7 +899,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -968,7 +968,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1012,7 +1012,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1088,7 +1088,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1128,7 +1128,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..4 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1204,7 +1204,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1307,7 +1307,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -1321,7 +1321,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..7 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1498,7 +1498,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK2-SAME: (%struct.kmp_task_t_with_privates.3* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (%struct.kmp_task_t_with_privates.3* [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates.3*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.3*, align 8 @@ -1516,7 +1516,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ei -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -1540,7 +1540,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1611,7 +1611,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..10 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1717,7 +1717,7 @@ struct S { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC1Ei -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -1725,14 +1725,14 @@ struct S { // CHECK2-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SC2Ei(%struct.S* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SC2Ei(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SC1Ei(%struct.S* noundef @s, i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1) // CHECK2-NEXT: ret void // // @@ -1744,7 +1744,7 @@ struct S { // // // CHECK3-LABEL: define {{[^@]+}}@main -// CHECK3-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1813,7 +1813,7 @@ struct S { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1857,7 +1857,7 @@ struct S { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1933,7 +1933,7 @@ struct S { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1973,7 +1973,7 @@ struct S { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..4 -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2049,7 +2049,7 @@ struct S { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2157,7 +2157,7 @@ struct S { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK3-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -2171,7 +2171,7 @@ struct S { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..7 -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2398,7 +2398,7 @@ struct S { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK3-SAME: (%struct.kmp_task_t_with_privates.3* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (%struct.kmp_task_t_with_privates.3* [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates.3*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.3*, align 8 @@ -2418,12 +2418,12 @@ struct S { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SC1Ei(%struct.S* noundef @s, i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1Ei -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -2431,12 +2431,12 @@ struct S { // CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SC2Ei(%struct.S* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SC2Ei(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ei -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -2460,7 +2460,7 @@ struct S { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2531,7 +2531,7 @@ struct S { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..10 -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2644,7 +2644,7 @@ struct S { // // // CHECK4-LABEL: define {{[^@]+}}@main -// CHECK4-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2713,7 +2713,7 @@ struct S { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2757,7 +2757,7 @@ struct S { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2833,7 +2833,7 @@ struct S { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2873,7 +2873,7 @@ struct S { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..4 -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2949,7 +2949,7 @@ struct S { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3057,7 +3057,7 @@ struct S { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK4-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK4-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -3071,7 +3071,7 @@ struct S { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..7 -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -3298,7 +3298,7 @@ struct S { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK4-SAME: (%struct.kmp_task_t_with_privates.3* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (%struct.kmp_task_t_with_privates.3* [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates.3*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.3*, align 8 @@ -3318,12 +3318,12 @@ struct S { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SC1Ei(%struct.S* noundef @s, i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1Ei -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -3331,12 +3331,12 @@ struct S { // CHECK4-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SC2Ei(%struct.S* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SC2Ei(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2Ei -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -3360,7 +3360,7 @@ struct S { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3431,7 +3431,7 @@ struct S { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..10 -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -3544,7 +3544,7 @@ struct S { // // // CHECK5-LABEL: define {{[^@]+}}@main -// CHECK5-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3774,12 +3774,12 @@ struct S { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK5-SAME: () #[[ATTR2:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SC1Ei(%struct.S* noundef @s, i32 noundef 1) +// CHECK5-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1Ei -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -3787,12 +3787,12 @@ struct S { // CHECK5-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SC2Ei(%struct.S* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SC2Ei(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2Ei -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3]] align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR3]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -3883,7 +3883,7 @@ struct S { // // // CHECK6-LABEL: define {{[^@]+}}@main -// CHECK6-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4111,7 +4111,7 @@ struct S { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SC2Ei -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -4195,7 +4195,7 @@ struct S { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SC1Ei -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -4203,14 +4203,14 @@ struct S { // CHECK6-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SC2Ei(%struct.S* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SC2Ei(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR3:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SC1Ei(%struct.S* noundef @s, i32 noundef 1) +// CHECK6-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1) // CHECK6-NEXT: ret void // // @@ -4222,7 +4222,7 @@ struct S { // // // CHECK7-LABEL: define {{[^@]+}}@main -// CHECK7-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4517,12 +4517,12 @@ struct S { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK7-SAME: () #[[ATTR2:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SC1Ei(%struct.S* noundef @s, i32 noundef 1) +// CHECK7-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SC1Ei -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -4530,12 +4530,12 @@ struct S { // CHECK7-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SC2Ei(%struct.S* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SC2Ei(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SC2Ei -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3]] align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR3]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -4626,7 +4626,7 @@ struct S { // // // CHECK8-LABEL: define {{[^@]+}}@main -// CHECK8-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4919,7 +4919,7 @@ struct S { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SC2Ei -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -5003,7 +5003,7 @@ struct S { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SC1Ei -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[C:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 @@ -5011,14 +5011,14 @@ struct S { // CHECK8-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[C_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SC2Ei(%struct.S* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SC2Ei(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK8-SAME: () #[[ATTR3:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SC1Ei(%struct.S* noundef @s, i32 noundef 1) +// CHECK8-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1) // CHECK8-NEXT: ret void // // diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp index c7d3b19910ab83fc693e608371a00df8f02437ca..bfb9ad713576008ef9f641bc9cd7f4b1fb357024 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp @@ -93,7 +93,7 @@ int main() { // LAMBDA: store double 2.0{{.+}}, double* [[G_REF]] // LAMBDA: store double* %{{.+}}, double** %{{.+}}, - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -145,7 +145,7 @@ int main() { // BLOCKS: store double* %{{.+}}, double** %{{.+}}, // BLOCKS: store i{{[0-9]+}}* %{{.+}}, i{{[0-9]+}}** %{{.+}}, - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -258,7 +258,7 @@ int main() { // CHECK-NEXT: br label {{%?}}[[EXIT]] // CHECK: [[EXIT]] -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -277,7 +277,7 @@ int main() { // CHECK: store i{{[0-9]+}}* [[PRIV_SIVAR]], i{{[0-9]+}}** [[ARG5]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -305,7 +305,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0 @@ -322,7 +322,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_COPY_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %{{.+}}, [[KMP_TASK_MAIN_TY]]* noalias noundef %{{.+}}) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %{{.+}}, [[KMP_TASK_MAIN_TY]]* noalias %{{.+}}) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -402,7 +402,7 @@ int main() { // Start task. // CHECK: call void @__kmpc_taskloop(%struct.ident_t* @{{.+}}, i32 %{{.+}}, i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* bitcast (void ([[KMP_TASK_TMAIN_TY]]*, [[KMP_TASK_TMAIN_TY]]*, i32)* [[TMAIN_DUP:@.+]] to i8*)) -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %{{.+}}, i32** noalias noundef %{{.+}}, [2 x i32]** noalias noundef %{{.+}}, [2 x [[S_INT_TY]]]** noalias noundef %{{.+}}, [[S_INT_TY]]** noalias noundef %{{.+}}) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %{{.+}}, i32** noalias %{{.+}}, [2 x i32]** noalias %{{.+}}, [2 x [[S_INT_TY]]]** noalias %{{.+}}, [[S_INT_TY]]** noalias %{{.+}}) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -418,7 +418,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, // CHECK-DAG: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*, @@ -441,7 +441,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* %{{.+}}, i32 0, i32 0 @@ -458,7 +458,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_COPY_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp index 120bd0a21526813346ec5757ab68d1c741f717f9..28b487ff220194f0a3670627085a6cf747ca9e8f 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp @@ -208,48 +208,48 @@ void loop() { // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TTT]]) -// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double 1.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[VAR]], double noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]], double 3.000000e+00) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]]) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TTT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 @@ -257,12 +257,12 @@ void loop() { // CHECK1-NEXT: store double [[A]], double* [[A_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef [[THIS1]], double noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]], double [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], %struct.S* nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -313,13 +313,13 @@ void loop() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP19]], i32 0, i32 1 -// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TMP21]]) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TMP21]]) // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP15]], i32 0, i32 3 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP22]] to i32 (i32, i8*)** // CHECK1-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_destructor. to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP23]], align 8 @@ -342,7 +342,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], %struct.S** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]], [2 x %struct.S]** noalias noundef [[TMP3:%.*]], [2 x i32]** noalias noundef [[TMP4:%.*]], i32** noalias noundef [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], %struct.S** noalias [[TMP1:%.*]], i32** noalias [[TMP2:%.*]], [2 x %struct.S]** noalias [[TMP3:%.*]], [2 x i32]** noalias [[TMP4:%.*]], i32** noalias [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S**, align 8 @@ -376,7 +376,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -521,7 +521,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK1-SAME: (%struct.kmp_task_t_with_privates* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { +// CHECK1-SAME: (%struct.kmp_task_t_with_privates* [[TMP0:%.*]], %struct.kmp_task_t_with_privates* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR7]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 @@ -541,18 +541,18 @@ void loop() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 1 -// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TMP9]]) +// CHECK1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TMP9]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_destructor. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 @@ -563,14 +563,14 @@ void loop() { // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP2]], i32 0, i32 1 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TMP5]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: @@ -579,12 +579,12 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -598,37 +598,37 @@ void loop() { // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TTT]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TTT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -639,7 +639,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 @@ -653,7 +653,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -662,17 +662,17 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -680,12 +680,12 @@ void loop() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -734,13 +734,13 @@ void loop() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP18]], i32 0, i32 3 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TMP20]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP14]], i32 0, i32 3 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP21]] to i32 (i32, i8*)** // CHECK1-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.2*)* @.omp_task_destructor..7 to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP22]], align 8 @@ -763,7 +763,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map..4 -// CHECK1-SAME: (%struct..kmp_privates.t.3* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]], [2 x i32]** noalias noundef [[TMP2:%.*]], [2 x %struct.S.0]** noalias noundef [[TMP3:%.*]], %struct.S.0** noalias noundef [[TMP4:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (%struct..kmp_privates.t.3* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]], [2 x i32]** noalias [[TMP2:%.*]], [2 x %struct.S.0]** noalias [[TMP3:%.*]], %struct.S.0** noalias [[TMP4:%.*]]) #[[ATTR6]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t.3*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -792,7 +792,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..5 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias [[TMP1:%.*]]) #[[ATTR7]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -930,7 +930,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_dup..6 -// CHECK1-SAME: (%struct.kmp_task_t_with_privates.2* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { +// CHECK1-SAME: (%struct.kmp_task_t_with_privates.2* [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR7]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 @@ -950,18 +950,18 @@ void loop() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP7]], i32 0, i32 3 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TMP9]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_destructor..7 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias [[TMP1:%.*]]) #[[ATTR7]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 @@ -972,14 +972,14 @@ void loop() { // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP2]], i32 0, i32 2 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 2 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 3 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TMP5]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: @@ -988,17 +988,17 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1009,7 +1009,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1023,7 +1023,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1042,48 +1042,48 @@ void loop() { // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TTT]]) -// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double 1.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[VAR]], double noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]], double 3.000000e+00) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]]) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] -// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TTT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 @@ -1091,12 +1091,12 @@ void loop() { // CHECK2-NEXT: store double [[A]], double* [[A_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef [[THIS1]], double noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]], double [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], %struct.S* nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1147,13 +1147,13 @@ void loop() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP19]], i32 0, i32 1 -// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TMP21]]) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TMP21]]) // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP15]], i32 0, i32 3 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP22]] to i32 (i32, i8*)** // CHECK2-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_destructor. to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP23]], align 8 @@ -1176,7 +1176,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], %struct.S** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]], [2 x %struct.S]** noalias noundef [[TMP3:%.*]], [2 x i32]** noalias noundef [[TMP4:%.*]], i32** noalias noundef [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], %struct.S** noalias [[TMP1:%.*]], i32** noalias [[TMP2:%.*]], [2 x %struct.S]** noalias [[TMP3:%.*]], [2 x i32]** noalias [[TMP4:%.*]], i32** noalias [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S**, align 8 @@ -1210,7 +1210,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1355,7 +1355,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK2-SAME: (%struct.kmp_task_t_with_privates* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { +// CHECK2-SAME: (%struct.kmp_task_t_with_privates* [[TMP0:%.*]], %struct.kmp_task_t_with_privates* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR7]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 @@ -1375,18 +1375,18 @@ void loop() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 1 -// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TMP9]]) +// CHECK2-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TMP9]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_destructor. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 @@ -1397,14 +1397,14 @@ void loop() { // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP2]], i32 0, i32 1 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1 -// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TMP5]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: @@ -1413,12 +1413,12 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIdED2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // @@ -1432,37 +1432,37 @@ void loop() { // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TTT]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TTT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1473,7 +1473,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 @@ -1487,7 +1487,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1496,17 +1496,17 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1514,12 +1514,12 @@ void loop() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1568,13 +1568,13 @@ void loop() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP18]], i32 0, i32 3 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TMP20]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP14]], i32 0, i32 3 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP21]] to i32 (i32, i8*)** // CHECK2-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.2*)* @.omp_task_destructor..7 to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP22]], align 8 @@ -1597,7 +1597,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map..4 -// CHECK2-SAME: (%struct..kmp_privates.t.3* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]], [2 x i32]** noalias noundef [[TMP2:%.*]], [2 x %struct.S.0]** noalias noundef [[TMP3:%.*]], %struct.S.0** noalias noundef [[TMP4:%.*]]) #[[ATTR6]] { +// CHECK2-SAME: (%struct..kmp_privates.t.3* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]], [2 x i32]** noalias [[TMP2:%.*]], [2 x %struct.S.0]** noalias [[TMP3:%.*]], %struct.S.0** noalias [[TMP4:%.*]]) #[[ATTR6]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t.3*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -1626,7 +1626,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..5 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias [[TMP1:%.*]]) #[[ATTR7]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1764,7 +1764,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_dup..6 -// CHECK2-SAME: (%struct.kmp_task_t_with_privates.2* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { +// CHECK2-SAME: (%struct.kmp_task_t_with_privates.2* [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR7]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 @@ -1784,18 +1784,18 @@ void loop() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP7]], i32 0, i32 3 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TMP9]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_destructor..7 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias [[TMP1:%.*]]) #[[ATTR7]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 @@ -1806,14 +1806,14 @@ void loop() { // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP2]], i32 0, i32 2 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 2 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 3 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TMP5]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: @@ -1822,17 +1822,17 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1843,7 +1843,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1857,7 +1857,7 @@ void loop() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1871,12 +1871,12 @@ void loop() { // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1922,7 +1922,7 @@ void loop() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], double** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], double** noalias [[TMP1:%.*]], i32** noalias [[TMP2:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca double**, align 8 @@ -1941,7 +1941,7 @@ void loop() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2029,7 +2029,7 @@ void loop() { // CHECK3-NEXT: store double* [[TMP30]], double** [[TMP36]], align 8, !noalias !14, !llvm.access.group !15 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP_I]], i32 0, i32 1 // CHECK3-NEXT: store i32* [[TMP31]], i32** [[TMP37]], align 8, !noalias !14, !llvm.access.group !15 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP_I]]) #[[ATTR3]], !llvm.access.group !15 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP_I]]) #[[ATTR3]], !llvm.access.group !15 // CHECK3-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15 // CHECK3-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP38]], 1 // CHECK3-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15 @@ -2049,7 +2049,7 @@ void loop() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK3-SAME: (%struct.kmp_task_t_with_privates* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR6]] { +// CHECK3-SAME: (%struct.kmp_task_t_with_privates* [[TMP0:%.*]], %struct.kmp_task_t_with_privates* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR6]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 @@ -2073,12 +2073,12 @@ void loop() { // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// CHECK4-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -2090,7 +2090,7 @@ void loop() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2136,7 +2136,7 @@ void loop() { // // // CHECK4-LABEL: define {{[^@]+}}@_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8 @@ -2151,7 +2151,7 @@ void loop() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK4-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], double** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK4-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], double** noalias [[TMP1:%.*]], i32** noalias [[TMP2:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca double**, align 8 @@ -2170,7 +2170,7 @@ void loop() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2276,7 +2276,7 @@ void loop() { // CHECK4-NEXT: [[TMP40:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL_I]] to i8* // CHECK4-NEXT: [[TMP41:%.*]] = load i8*, i8** [[TMP39]], align 8, !noalias !14, !llvm.access.group !15 // CHECK4-NEXT: [[TMP42:%.*]] = bitcast i8* [[TMP41]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP42]](i8* noundef [[TMP40]]) #[[ATTR4]], !llvm.access.group !15 +// CHECK4-NEXT: call void [[TMP42]](i8* [[TMP40]]) #[[ATTR4]], !llvm.access.group !15 // CHECK4-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15 // CHECK4-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP43]], 1 // CHECK4-NEXT: store i32 [[ADD4_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15 @@ -2296,7 +2296,7 @@ void loop() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK4-SAME: (%struct.kmp_task_t_with_privates* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { +// CHECK4-SAME: (%struct.kmp_task_t_with_privates* [[TMP0:%.*]], %struct.kmp_task_t_with_privates* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR7]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 @@ -2314,7 +2314,7 @@ void loop() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St -// CHECK5-SAME: (i32 noundef [[N:%.*]], float* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (i32 [[N:%.*]], float* [[A:%.*]], %struct.St* [[S:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 @@ -2329,7 +2329,7 @@ void loop() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], %struct.St** noundef nonnull align 8 dereferenceable(8) [[S:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], %struct.St** nonnull align 8 dereferenceable(8) [[S:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2386,7 +2386,7 @@ void loop() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK5-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], float*** noalias noundef [[TMP1:%.*]], %struct.St*** noalias noundef [[TMP2:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK5-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], float*** noalias [[TMP1:%.*]], %struct.St*** noalias [[TMP2:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca float***, align 8 @@ -2405,7 +2405,7 @@ void loop() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK5-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2507,7 +2507,7 @@ void loop() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK5-SAME: (%struct.kmp_task_t_with_privates* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR5]] { +// CHECK5-SAME: (%struct.kmp_task_t_with_privates* [[TMP0:%.*]], %struct.kmp_task_t_with_privates* [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 @@ -2534,7 +2534,7 @@ void loop() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[J:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[J:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2585,7 +2585,7 @@ void loop() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2710,28 +2710,28 @@ void loop() { // CHECK7-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TTT]]) -// CHECK7-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK7-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) +// CHECK7-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double 1.000000e+00) // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK7-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[VAR]], double noundef 3.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double 2.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]], double 3.000000e+00) // CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK7-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8 // CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 // CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK7-NEXT: store i32 [[CONV]], i32* [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[VAR1]]) +// CHECK7-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[VAR1]]) // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] @@ -2800,42 +2800,42 @@ void loop() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_ARRAYCPY_DONE9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done11: -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[VAR1]]) #[[ATTR4]] -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[VAR1]]) #[[ATTR4]] +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] // CHECK7: arraydestroy.body13: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S* [ [[TMP20]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK7: arraydestroy.done17: -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TTT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] // CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP21]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 @@ -2843,17 +2843,17 @@ void loop() { // CHECK7-NEXT: store double [[A]], double* [[A_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef [[THIS1]], double noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]], double [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIdED2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK7-NEXT: ret void // // @@ -2876,16 +2876,16 @@ void loop() { // CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 // CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK7-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TTT]]) -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK7-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8 // CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 @@ -2896,12 +2896,12 @@ void loop() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR4]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 @@ -2957,37 +2957,37 @@ void loop() { // CHECK7-NEXT: [[TMP16:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* // CHECK7-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i64 4, i1 false) -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR4]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP18]], [[OMP_ARRAYCPY_DONE9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done11: // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] // CHECK7: arraydestroy.body13: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP19]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK7: arraydestroy.done17: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TTT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP20]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2998,7 +2998,7 @@ void loop() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3007,7 +3007,7 @@ void loop() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 @@ -3021,17 +3021,17 @@ void loop() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3039,22 +3039,22 @@ void loop() { // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3065,7 +3065,7 @@ void loop() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3079,7 +3079,7 @@ void loop() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3108,28 +3108,28 @@ void loop() { // CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 // CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TTT]]) -// CHECK8-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) +// CHECK8-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double 1.000000e+00) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef [[VAR]], double noundef 3.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double 2.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]], double 3.000000e+00) // CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK8-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8 // CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 // CHECK8-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 // CHECK8-NEXT: store i32 [[CONV]], i32* [[DOTOMP_IV]], align 4 -// CHECK8-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[VAR1]]) +// CHECK8-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[VAR1]]) // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] @@ -3198,42 +3198,42 @@ void loop() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP19]], [[OMP_ARRAYCPY_DONE9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done11: -// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[VAR1]]) #[[ATTR4]] -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[VAR1]]) #[[ATTR4]] +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] // CHECK8: arraydestroy.body13: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S* [ [[TMP20]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK8: arraydestroy.done17: -// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] -// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef [[TTT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIdED1Ev(%struct.S* nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] // CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP21]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 @@ -3241,17 +3241,17 @@ void loop() { // CHECK8-NEXT: store double [[A]], double* [[A_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef [[THIS1]], double noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]], double [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIdED2Ev(%struct.S* nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // @@ -3274,16 +3274,16 @@ void loop() { // CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 // CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK8-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TTT]]) -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK8-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8 // CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 @@ -3294,12 +3294,12 @@ void loop() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR4]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 @@ -3355,37 +3355,37 @@ void loop() { // CHECK8-NEXT: [[TMP16:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* // CHECK8-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[VAR4]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP16]], i8* align 4 [[TMP17]], i64 4, i1 false) -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR4]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK8-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP18]], [[OMP_ARRAYCPY_DONE9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done11: // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] // CHECK8: arraydestroy.body13: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP19]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK8: arraydestroy.done17: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TTT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] // CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP20]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3396,7 +3396,7 @@ void loop() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3405,7 +3405,7 @@ void loop() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(8) [[THIS:%.*]], double [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 @@ -3419,17 +3419,17 @@ void loop() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3437,22 +3437,22 @@ void loop() { // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3463,7 +3463,7 @@ void loop() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3477,7 +3477,7 @@ void loop() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3491,7 +3491,7 @@ void loop() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // @@ -3502,12 +3502,12 @@ void loop() { // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK10-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// CHECK10-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK10-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -3563,7 +3563,7 @@ void loop() { // CHECK10-NEXT: [[TMP8:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK10-NEXT: [[TMP9:%.*]] = load i8*, i8** [[TMP7]], align 8, !llvm.access.group !2 // CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to void (i8*)* -// CHECK10-NEXT: call void [[TMP10]](i8* noundef [[TMP8]]), !llvm.access.group !2 +// CHECK10-NEXT: call void [[TMP10]](i8* [[TMP8]]), !llvm.access.group !2 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3582,7 +3582,7 @@ void loop() { // // // CHECK10-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// CHECK10-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8 @@ -3597,7 +3597,7 @@ void loop() { // // // CHECK11-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St -// CHECK11-SAME: (i32 noundef [[N:%.*]], float* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], float* [[A:%.*]], %struct.St* [[S:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_private_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_private_codegen.cpp index b6c6652482797a641841c53b97ed69c713343908..820f8747a80b322e4f2ccfdd41956eb763a7b11b 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_simd_private_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_simd_private_codegen.cpp @@ -77,7 +77,7 @@ int main() { // LAMBDA: [[SIVAR_REF:%.+]] = load i{{[0-9]+}}*, i{{[0-9]+}}** [[SIVAR_PTR_REF]] // LAMBDA: store i{{[0-9]+}} 3, i{{[0-9]+}}* [[SIVAR_REF]] - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 2; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -113,7 +113,7 @@ int main() { // BLOCKS-NOT: [[SIVAR]]{{[[^:word:]]}} // BLOCKS: ret - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 3; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -205,7 +205,7 @@ int main() { // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -221,7 +221,7 @@ int main() { // CHECK: store [2 x i32]* [[PRIV_VEC]], [2 x i32]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -247,7 +247,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0 @@ -264,7 +264,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_DEF_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -328,7 +328,7 @@ int main() { // CHECK-NOT: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -344,7 +344,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -368,7 +368,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* %{{.+}}, i32 0, i32 0 @@ -385,7 +385,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_DEF_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp index 340d1c0d3f82ab320bc0a35e2cc09ba2c8bf7a0f..1a0b09763e4980ec2f9090f9cf9b9cc74802efaf 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp @@ -168,51 +168,51 @@ sum = 0.0; // CHECK-NEXT: br label {{%?}}[[EXIT]] // CHECK: [[EXIT]] -// CHECK: define internal void @[[RED_INIT1]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT1]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB1]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB1]](i8* %0, i8* %1) // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_INIT2]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT2]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: call void [[OMP_INIT1:@.+]]( // CHECK: ret void -// CHECK: define internal void [[OMP_COMB1:@.+]](%struct.S* noalias noundef %0, %struct.S* noalias noundef %1) +// CHECK: define internal void [[OMP_COMB1:@.+]](%struct.S* noalias %0, %struct.S* noalias %1) // CHECK: fadd float % -// CHECK: define internal void [[OMP_INIT1]](%struct.S* noalias noundef %0, %struct.S* noalias noundef %1) +// CHECK: define internal void [[OMP_INIT1]](%struct.S* noalias %0, %struct.S* noalias %1) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64( -// CHECK: define internal void @[[RED_FINI2]](i8* noundef %0) +// CHECK: define internal void @[[RED_FINI2]](i8* %0) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: call void @ // CHECK: ret void -// CHECK: define internal void @[[RED_COMB2]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB2]](i8* %0, i8* %1) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: call void [[OMP_COMB1]]( // CHECK: ret void -// CHECK: define internal void @[[RED_INIT3]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT3]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB3]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB3]](i8* %0, i8* %1) // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_INIT4]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT4]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB4]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB4]](i8* %0, i8* %1) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % diff --git a/clang/test/OpenMP/parallel_num_threads_codegen.cpp b/clang/test/OpenMP/parallel_num_threads_codegen.cpp index e4ff9fb839fc51ec2710926c587a184f7af6a0cf..0fdb6cfbcfefef0db4a6a8fd713691ef6033d447 100644 --- a/clang/test/OpenMP/parallel_num_threads_codegen.cpp +++ b/clang/test/OpenMP/parallel_num_threads_codegen.cpp @@ -49,7 +49,7 @@ int main() { // CHECK-DAG: [[S_ADDR:%.+]] = alloca [[S_TY]] // CHECK-DAG: [[A_ADDR:%.+]] = alloca i8 // CHECK-DAG: [[GTID:%.+]] = call {{.*}}i32 @__kmpc_global_thread_num([[IDENT_T_TY]]* [[DEF_LOC_2]]) -// CHECK-DAG: call {{.*}} [[S_TY_CONSTR:@.+]]([[S_TY]]* {{[^,]*}} [[S_ADDR]], [[INTPTR_T_TY]] noundef [[INTPTR_T_TY_ATTR:(signext )?]]0) +// CHECK-DAG: call {{.*}} [[S_TY_CONSTR:@.+]]([[S_TY]]* {{[^,]*}} [[S_ADDR]], [[INTPTR_T_TY]] [[INTPTR_T_TY_ATTR:(signext )?]]0) // CHECK: [[S_CHAR_OP:%.+]] = invoke{{.*}} i8 [[S_TY_CHAR_OP:@.+]]([[S_TY]]* {{[^,]*}} [[S_ADDR]]) // CHECK: store i8 [[S_CHAR_OP]], i8* [[A_ADDR]] // CHECK: call {{.*}}void @__kmpc_push_num_threads([[IDENT_T_TY]]* [[DEF_LOC_2]], i32 [[GTID]], i32 2) @@ -77,7 +77,7 @@ int main() { // CHECK: [[GTID:%.+]] = call {{.*}}i32 @__kmpc_global_thread_num([[IDENT_T_TY]]* [[DEF_LOC_2]]) // CHECK: call {{.*}}void @__kmpc_push_num_threads([[IDENT_T_TY]]* [[DEF_LOC_2]], i32 [[GTID]], i32 1) // CHECK: call {{.*}}void {{.*}} @__kmpc_fork_call( -// CHECK: {{(invoke|call)}} {{.*}} [[S_TY_CONSTR]]([[S_TY]]* {{[^,]*}} [[S_TEMP:%.+]], [[INTPTR_T_TY]] noundef [[INTPTR_T_TY_ATTR]]23) +// CHECK: {{(invoke|call)}} {{.*}} [[S_TY_CONSTR]]([[S_TY]]* {{[^,]*}} [[S_TEMP:%.+]], [[INTPTR_T_TY]] [[INTPTR_T_TY_ATTR]]23) // CHECK: [[S_CHAR_OP:%.+]] = invoke{{.*}} i8 [[S_TY_CHAR_OP]]([[S_TY]]* {{[^,]*}} [[S_TEMP]]) // CHECK: [[RES:%.+]] = sext {{.*}}i8 [[S_CHAR_OP]] to i32 // CHECK: call {{.*}}void @__kmpc_push_num_threads([[IDENT_T_TY]]* [[DEF_LOC_2]], i32 [[GTID]], i32 [[RES]]) diff --git a/clang/test/OpenMP/parallel_private_codegen.cpp b/clang/test/OpenMP/parallel_private_codegen.cpp index 29388ab3245da3379da631ec878e6977d122d540..40d890b4bfb5ca9121c7244265e6267555dbd9bf 100644 --- a/clang/test/OpenMP/parallel_private_codegen.cpp +++ b/clang/test/OpenMP/parallel_private_codegen.cpp @@ -178,37 +178,37 @@ int main() { // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -216,22 +216,22 @@ int main() { // CHECK1-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -239,12 +239,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -260,12 +260,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 @@ -274,14 +274,14 @@ int main() { // CHECK1-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 4, i1 false) // CHECK1-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -289,12 +289,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -308,36 +308,36 @@ int main() { // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef [[SST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -358,7 +358,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -389,7 +389,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -400,7 +400,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -414,7 +414,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -423,27 +423,27 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK1-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -451,12 +451,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -471,12 +471,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 @@ -484,14 +484,14 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* // CHECK1-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -499,17 +499,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -520,7 +520,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK1-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 @@ -532,7 +532,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -557,7 +557,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -571,7 +571,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -590,37 +590,37 @@ int main() { // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -628,22 +628,22 @@ int main() { // CHECK2-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK2-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -651,12 +651,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -672,12 +672,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 @@ -686,14 +686,14 @@ int main() { // CHECK2-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 4, i1 false) // CHECK2-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done3: @@ -701,12 +701,12 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // @@ -720,36 +720,36 @@ int main() { // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK2-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef [[SST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK2-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -770,7 +770,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -801,7 +801,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -812,7 +812,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -826,7 +826,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -835,27 +835,27 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK2-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK2-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -863,12 +863,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -883,12 +883,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 @@ -896,14 +896,14 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* // CHECK2-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done3: @@ -911,17 +911,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -932,7 +932,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK2-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK2-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 @@ -944,7 +944,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -969,7 +969,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -983,7 +983,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -998,13 +998,13 @@ int main() { // CHECK3-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -1012,12 +1012,12 @@ int main() { // CHECK3-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -1038,7 +1038,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1065,12 +1065,12 @@ int main() { // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP1]], align 8 // CHECK3-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 8 -// CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK3-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { +// CHECK3-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK3-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 @@ -1097,7 +1097,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1128,7 +1128,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1143,7 +1143,7 @@ int main() { // CHECK3-NEXT: store i32* [[G]], i32** [[TMP0]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[TMP1]], align 8 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: ret void // // @@ -1153,15 +1153,15 @@ int main() { // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// CHECK4-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -1169,12 +1169,12 @@ int main() { // CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -1186,7 +1186,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1219,12 +1219,12 @@ int main() { // CHECK4-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP6]](i8* noundef [[TMP4]]) +// CHECK4-NEXT: call void [[TMP6]](i8* [[TMP4]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>*, align 8 @@ -1239,7 +1239,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -1260,7 +1260,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1304,12 +1304,12 @@ int main() { // CHECK4-NEXT: [[TMP6:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP5]], align 8 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP8]](i8* noundef [[TMP6]]) +// CHECK4-NEXT: call void [[TMP8]](i8* [[TMP6]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke_2 -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 @@ -1337,7 +1337,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1366,3 +1366,4 @@ int main() { // CHECK4-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 // CHECK4-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_reduction_codegen.cpp b/clang/test/OpenMP/parallel_reduction_codegen.cpp index 293c44b1735841b8fc922991cb926368e26f5611..acb891aa1c7a04adde4e79bd9f6b45013bbb3b1e 100644 --- a/clang/test/OpenMP/parallel_reduction_codegen.cpp +++ b/clang/test/OpenMP/parallel_reduction_codegen.cpp @@ -329,7 +329,7 @@ int main() { #endif // CHECK1-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs -// CHECK1-SAME: (i16* noundef [[X:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i16* [[X:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 // CHECK1-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 @@ -339,7 +339,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef [[X:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* [[X:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -459,7 +459,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -513,19 +513,19 @@ int main() { // CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[CF:%.*]] = alloca { float, float }, align 4 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @sivar) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, float*, [2 x %struct.S]*, %struct.S*, %struct.S*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], float* [[T_VAR]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], %struct.S* [[VAR1]], float* [[T_VAR1]]) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[VAR1]]) +// CHECK1-NEXT: [[CALL:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK1-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL]], 0.000000e+00 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] // CHECK1: if.then: @@ -533,27 +533,27 @@ int main() { // CHECK1-NEXT: br label [[IF_END]] // CHECK1: if.end: // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, { float, float }*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), { float, float }* [[CF]]) -// CHECK1-NEXT: [[CALL1:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL1:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL1]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR1]]) #[[ATTR5:[0-9]+]] -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[IF_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -561,22 +561,22 @@ int main() { // CHECK1-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -584,12 +584,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -625,8 +625,8 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR1_ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load float*, float** [[T_VAR1_ADDR]], align 8 // CHECK1-NEXT: store float 0.000000e+00, float* [[T_VAR2]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR3]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR14]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK1-NEXT: store float 0x47EFFFFFE0000000, float* [[T_VAR15]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load float, float* [[T_VAR2]], align 4 // CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32 @@ -661,25 +661,25 @@ int main() { // CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[T_VAR2]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP21]], [[TMP22]] // CHECK1-NEXT: store float [[ADD]], float* [[TMP1]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP3]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK1-NEXT: [[TMP23:%.*]] = bitcast %struct.S* [[TMP3]] to i8* // CHECK1-NEXT: [[TMP24:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i64 4, i1 false) -// CHECK1-NEXT: [[CALL7:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP4]]) +// CHECK1-NEXT: [[CALL7:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP4]]) // CHECK1-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL7]], 0.000000e+00 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK1: land.rhs: -// CHECK1-NEXT: [[CALL8:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[VAR14]]) +// CHECK1-NEXT: [[CALL8:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK1-NEXT: [[TOBOOL9:%.*]] = fcmp une float [[CALL8]], 0.000000e+00 // CHECK1-NEXT: br label [[LAND_END]] // CHECK1: land.end: // CHECK1-NEXT: [[TMP25:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL9]], [[LAND_RHS]] ] // CHECK1-NEXT: [[CONV10:%.*]] = uitofp i1 [[TMP25]] to float -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP]], float noundef [[CONV10]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV10]]) // CHECK1-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[TMP4]] to i8* // CHECK1-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP28:%.*]] = load float, float* [[TMP5]], align 4 // CHECK1-NEXT: [[TMP29:%.*]] = load float, float* [[T_VAR15]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP28]], [[TMP29]] @@ -717,27 +717,27 @@ int main() { // CHECK1-NEXT: br i1 [[TMP43]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK1: atomic_exit: // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL12:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP3]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK1-NEXT: [[CALL12:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK1-NEXT: [[TMP44:%.*]] = bitcast %struct.S* [[TMP3]] to i8* // CHECK1-NEXT: [[TMP45:%.*]] = bitcast %struct.S* [[CALL12]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP44]], i8* align 4 [[TMP45]], i64 4, i1 false) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL14:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP4]]) +// CHECK1-NEXT: [[CALL14:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP4]]) // CHECK1-NEXT: [[TOBOOL15:%.*]] = fcmp une float [[CALL14]], 0.000000e+00 // CHECK1-NEXT: br i1 [[TOBOOL15]], label [[LAND_RHS16:%.*]], label [[LAND_END19:%.*]] // CHECK1: land.rhs16: -// CHECK1-NEXT: [[CALL17:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[VAR14]]) +// CHECK1-NEXT: [[CALL17:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK1-NEXT: [[TOBOOL18:%.*]] = fcmp une float [[CALL17]], 0.000000e+00 // CHECK1-NEXT: br label [[LAND_END19]] // CHECK1: land.end19: // CHECK1-NEXT: [[TMP46:%.*]] = phi i1 [ false, [[ATOMIC_EXIT]] ], [ [[TOBOOL18]], [[LAND_RHS16]] ] // CHECK1-NEXT: [[CONV20:%.*]] = uitofp i1 [[TMP46]] to float -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP13]], float noundef [[CONV20]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP13]], float [[CONV20]]) // CHECK1-NEXT: [[TMP47:%.*]] = bitcast %struct.S* [[TMP4]] to i8* // CHECK1-NEXT: [[TMP48:%.*]] = bitcast %struct.S* [[REF_TMP13]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP13]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP13]]) #[[ATTR5]] // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[TMP49:%.*]] = load float, float* [[T_VAR15]], align 4 // CHECK1-NEXT: [[TMP50:%.*]] = bitcast float* [[TMP5]] to i32* @@ -770,13 +770,13 @@ int main() { // CHECK1: atomic_exit30: // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR14]]) #[[ATTR5]] -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR3]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -815,25 +815,25 @@ int main() { // CHECK1-NEXT: [[TMP31:%.*]] = load float, float* [[TMP8]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP30]], [[TMP31]] // CHECK1-NEXT: store float [[ADD]], float* [[TMP11]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP17]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP14]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP14]]) // CHECK1-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP17]] to i8* // CHECK1-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK1-NEXT: [[CALL2:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP23]]) +// CHECK1-NEXT: [[CALL2:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP23]]) // CHECK1-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL2]], 0.000000e+00 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK1: land.rhs: -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP20]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK1-NEXT: [[TOBOOL4:%.*]] = fcmp une float [[CALL3]], 0.000000e+00 // CHECK1-NEXT: br label [[LAND_END]] // CHECK1: land.end: // CHECK1-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] // CHECK1-NEXT: [[CONV:%.*]] = uitofp i1 [[TMP34]] to float -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP]], float noundef [[CONV]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV]]) // CHECK1-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP23]] to i8* // CHECK1-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP37:%.*]] = load float, float* [[TMP29]], align 4 // CHECK1-NEXT: [[TMP38:%.*]] = load float, float* [[TMP26]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP37]], [[TMP38]] @@ -851,7 +851,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEanERKS0_ -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR0]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 @@ -862,7 +862,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR0]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -871,17 +871,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -910,8 +910,8 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR1_ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load float*, float** [[T_VAR1_ADDR]], align 8 // CHECK1-NEXT: store float 0.000000e+00, float* [[T_VAR2]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR3]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR14]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK1-NEXT: store float 0x47EFFFFFE0000000, float* [[T_VAR15]], align 4 // CHECK1-NEXT: br label [[WHILE_COND:%.*]] // CHECK1: while.cond: @@ -925,11 +925,11 @@ int main() { // CHECK1-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* // CHECK1-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR3]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false) -// CHECK1-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP4:![0-9]+]] // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], { float, float }* noundef nonnull align 4 dereferenceable(8) [[CF:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], { float, float }* nonnull align 4 dereferenceable(8) [[CF:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -982,7 +982,7 @@ int main() { // CHECK1-NEXT: [[CF1_IMAG9:%.*]] = load float, float* [[CF1_IMAGP8]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast { float, float }* [[TMP0]] to i8* // CHECK1-NEXT: [[TMP8:%.*]] = bitcast { float, float }* [[ATOMIC_TEMP]] to i8* -// CHECK1-NEXT: call void @__atomic_load(i64 noundef 8, i8* noundef [[TMP7]], i8* noundef [[TMP8]], i32 noundef 0) +// CHECK1-NEXT: call void @__atomic_load(i64 8, i8* [[TMP7]], i8* [[TMP8]], i32 0) // CHECK1-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK1: atomic_cont: // CHECK1-NEXT: [[ATOMIC_TEMP_REALP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[ATOMIC_TEMP]], i32 0, i32 0 @@ -1010,7 +1010,7 @@ int main() { // CHECK1-NEXT: [[TMP9:%.*]] = bitcast { float, float }* [[TMP0]] to i8* // CHECK1-NEXT: [[TMP10:%.*]] = bitcast { float, float }* [[ATOMIC_TEMP]] to i8* // CHECK1-NEXT: [[TMP11:%.*]] = bitcast { float, float }* [[ATOMIC_TEMP10]] to i8* -// CHECK1-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 8, i8* noundef [[TMP9]], i8* noundef [[TMP10]], i8* noundef [[TMP11]], i32 noundef 0, i32 noundef 0) +// CHECK1-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, i8* [[TMP9]], i8* [[TMP10]], i8* [[TMP11]], i32 0, i32 0) // CHECK1-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK1: atomic_exit: // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] @@ -1019,7 +1019,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1065,38 +1065,38 @@ int main() { // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef [[SST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*, %struct.S.0*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]], %struct.S.0* [[VAR1]], i32* [[T_VAR1]]) // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR1]]) #[[ATTR5]] -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -1135,7 +1135,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1226,7 +1226,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.7 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1270,7 +1270,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1283,7 +1283,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1300,7 +1300,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1309,27 +1309,27 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK1-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1337,12 +1337,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1374,8 +1374,8 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR1_ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[T_VAR1_ADDR]], align 8 // CHECK1-NEXT: store i32 0, i32* [[T_VAR2]], align 128 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR3]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR14]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK1-NEXT: store i32 2147483647, i32* [[T_VAR15]], align 128 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR2]], align 128 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP0]], i64 0, i64 0 @@ -1409,25 +1409,25 @@ int main() { // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR2]], align 128 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP1]], align 128 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP3]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK1-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* // CHECK1-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP23]], i8* align 4 [[TMP24]], i64 4, i1 false) -// CHECK1-NEXT: [[CALL7:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP4]]) +// CHECK1-NEXT: [[CALL7:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP4]]) // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL7]], 0 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK1: land.rhs: -// CHECK1-NEXT: [[CALL8:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[VAR14]]) +// CHECK1-NEXT: [[CALL8:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK1-NEXT: [[TOBOOL9:%.*]] = icmp ne i32 [[CALL8]], 0 // CHECK1-NEXT: br label [[LAND_END]] // CHECK1: land.end: // CHECK1-NEXT: [[TMP25:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL9]], [[LAND_RHS]] ] // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP25]] to i32 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[CONV]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) // CHECK1-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* // CHECK1-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP5]], align 128 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[T_VAR15]], align 128 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP28]], [[TMP29]] @@ -1447,39 +1447,39 @@ int main() { // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[T_VAR2]], align 128 // CHECK1-NEXT: [[TMP33:%.*]] = atomicrmw add i32* [[TMP1]], i32 [[TMP32]] monotonic, align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL10:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP3]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK1-NEXT: [[CALL10:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK1-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* // CHECK1-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[CALL10]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL12:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP4]]) +// CHECK1-NEXT: [[CALL12:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP4]]) // CHECK1-NEXT: [[TOBOOL13:%.*]] = icmp ne i32 [[CALL12]], 0 // CHECK1-NEXT: br i1 [[TOBOOL13]], label [[LAND_RHS14:%.*]], label [[LAND_END17:%.*]] // CHECK1: land.rhs14: -// CHECK1-NEXT: [[CALL15:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[VAR14]]) +// CHECK1-NEXT: [[CALL15:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK1-NEXT: [[TOBOOL16:%.*]] = icmp ne i32 [[CALL15]], 0 // CHECK1-NEXT: br label [[LAND_END17]] // CHECK1: land.end17: // CHECK1-NEXT: [[TMP36:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE2]] ], [ [[TOBOOL16]], [[LAND_RHS14]] ] // CHECK1-NEXT: [[CONV18:%.*]] = zext i1 [[TMP36]] to i32 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP11]], i32 noundef [[CONV18]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP11]], i32 [[CONV18]]) // CHECK1-NEXT: [[TMP37:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* // CHECK1-NEXT: [[TMP38:%.*]] = bitcast %struct.S.0* [[REF_TMP11]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP37]], i8* align 4 [[TMP38]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP11]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP11]]) #[[ATTR5]] // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[TMP39:%.*]] = load i32, i32* [[T_VAR15]], align 128 // CHECK1-NEXT: [[TMP40:%.*]] = atomicrmw min i32* [[TMP5]], i32 [[TMP39]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR14]]) #[[ATTR5]] -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR3]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1518,25 +1518,25 @@ int main() { // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP8]], align 128 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 128 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP17]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP14]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP14]]) // CHECK1-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* // CHECK1-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK1-NEXT: [[CALL2:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP23]]) +// CHECK1-NEXT: [[CALL2:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP23]]) // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL2]], 0 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK1: land.rhs: -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP20]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK1-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[CALL3]], 0 // CHECK1-NEXT: br label [[LAND_END]] // CHECK1: land.end: // CHECK1-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP34]] to i32 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[CONV]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) // CHECK1-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* // CHECK1-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP29]], align 128 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[TMP26]], align 128 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] @@ -1554,7 +1554,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEanERKS0_ -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR0]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1565,7 +1565,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEcviEv -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) #[[ATTR0]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1574,17 +1574,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1596,7 +1596,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK1-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK1-NEXT: [[A2:%.*]] = alloca i32*, align 8 @@ -1612,7 +1612,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1679,7 +1679,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.11 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1703,7 +1703,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1719,7 +1719,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1728,7 +1728,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs -// CHECK2-SAME: (i16* noundef [[X:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i16* [[X:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 // CHECK2-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 @@ -1738,7 +1738,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef [[X:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* [[X:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1858,7 +1858,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1912,19 +1912,19 @@ int main() { // CHECK2-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK2-NEXT: [[CF:%.*]] = alloca { float, float }, align 4 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @sivar) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, float*, [2 x %struct.S]*, %struct.S*, %struct.S*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], float* [[T_VAR]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], %struct.S* [[VAR1]], float* [[T_VAR1]]) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[VAR1]]) +// CHECK2-NEXT: [[CALL:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK2-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL]], 0.000000e+00 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] // CHECK2: if.then: @@ -1932,27 +1932,27 @@ int main() { // CHECK2-NEXT: br label [[IF_END]] // CHECK2: if.end: // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, { float, float }*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), { float, float }* [[CF]]) -// CHECK2-NEXT: [[CALL1:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL1:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: store i32 [[CALL1]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR1]]) #[[ATTR5:[0-9]+]] -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[IF_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -1960,22 +1960,22 @@ int main() { // CHECK2-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK2-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1983,12 +1983,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2024,8 +2024,8 @@ int main() { // CHECK2-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR1_ADDR]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load float*, float** [[T_VAR1_ADDR]], align 8 // CHECK2-NEXT: store float 0.000000e+00, float* [[T_VAR2]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR3]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR14]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK2-NEXT: store float 0x47EFFFFFE0000000, float* [[T_VAR15]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load float, float* [[T_VAR2]], align 4 // CHECK2-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32 @@ -2060,25 +2060,25 @@ int main() { // CHECK2-NEXT: [[TMP22:%.*]] = load float, float* [[T_VAR2]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP21]], [[TMP22]] // CHECK2-NEXT: store float [[ADD]], float* [[TMP1]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP3]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK2-NEXT: [[TMP23:%.*]] = bitcast %struct.S* [[TMP3]] to i8* // CHECK2-NEXT: [[TMP24:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i64 4, i1 false) -// CHECK2-NEXT: [[CALL7:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP4]]) +// CHECK2-NEXT: [[CALL7:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP4]]) // CHECK2-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL7]], 0.000000e+00 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK2: land.rhs: -// CHECK2-NEXT: [[CALL8:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[VAR14]]) +// CHECK2-NEXT: [[CALL8:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK2-NEXT: [[TOBOOL9:%.*]] = fcmp une float [[CALL8]], 0.000000e+00 // CHECK2-NEXT: br label [[LAND_END]] // CHECK2: land.end: // CHECK2-NEXT: [[TMP25:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL9]], [[LAND_RHS]] ] // CHECK2-NEXT: [[CONV10:%.*]] = uitofp i1 [[TMP25]] to float -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP]], float noundef [[CONV10]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV10]]) // CHECK2-NEXT: [[TMP26:%.*]] = bitcast %struct.S* [[TMP4]] to i8* // CHECK2-NEXT: [[TMP27:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP28:%.*]] = load float, float* [[TMP5]], align 4 // CHECK2-NEXT: [[TMP29:%.*]] = load float, float* [[T_VAR15]], align 4 // CHECK2-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP28]], [[TMP29]] @@ -2116,27 +2116,27 @@ int main() { // CHECK2-NEXT: br i1 [[TMP43]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK2: atomic_exit: // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL12:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP3]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK2-NEXT: [[CALL12:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK2-NEXT: [[TMP44:%.*]] = bitcast %struct.S* [[TMP3]] to i8* // CHECK2-NEXT: [[TMP45:%.*]] = bitcast %struct.S* [[CALL12]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP44]], i8* align 4 [[TMP45]], i64 4, i1 false) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL14:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP4]]) +// CHECK2-NEXT: [[CALL14:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP4]]) // CHECK2-NEXT: [[TOBOOL15:%.*]] = fcmp une float [[CALL14]], 0.000000e+00 // CHECK2-NEXT: br i1 [[TOBOOL15]], label [[LAND_RHS16:%.*]], label [[LAND_END19:%.*]] // CHECK2: land.rhs16: -// CHECK2-NEXT: [[CALL17:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[VAR14]]) +// CHECK2-NEXT: [[CALL17:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK2-NEXT: [[TOBOOL18:%.*]] = fcmp une float [[CALL17]], 0.000000e+00 // CHECK2-NEXT: br label [[LAND_END19]] // CHECK2: land.end19: // CHECK2-NEXT: [[TMP46:%.*]] = phi i1 [ false, [[ATOMIC_EXIT]] ], [ [[TOBOOL18]], [[LAND_RHS16]] ] // CHECK2-NEXT: [[CONV20:%.*]] = uitofp i1 [[TMP46]] to float -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP13]], float noundef [[CONV20]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP13]], float [[CONV20]]) // CHECK2-NEXT: [[TMP47:%.*]] = bitcast %struct.S* [[TMP4]] to i8* // CHECK2-NEXT: [[TMP48:%.*]] = bitcast %struct.S* [[REF_TMP13]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP13]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP13]]) #[[ATTR5]] // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[TMP49:%.*]] = load float, float* [[T_VAR15]], align 4 // CHECK2-NEXT: [[TMP50:%.*]] = bitcast float* [[TMP5]] to i32* @@ -2169,13 +2169,13 @@ int main() { // CHECK2: atomic_exit30: // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK2: .omp.reduction.default: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR14]]) #[[ATTR5]] -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR3]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR5]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2214,25 +2214,25 @@ int main() { // CHECK2-NEXT: [[TMP31:%.*]] = load float, float* [[TMP8]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP30]], [[TMP31]] // CHECK2-NEXT: store float [[ADD]], float* [[TMP11]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP17]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP14]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP14]]) // CHECK2-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP17]] to i8* // CHECK2-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK2-NEXT: [[CALL2:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP23]]) +// CHECK2-NEXT: [[CALL2:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP23]]) // CHECK2-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL2]], 0.000000e+00 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK2: land.rhs: -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP20]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK2-NEXT: [[TOBOOL4:%.*]] = fcmp une float [[CALL3]], 0.000000e+00 // CHECK2-NEXT: br label [[LAND_END]] // CHECK2: land.end: // CHECK2-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] // CHECK2-NEXT: [[CONV:%.*]] = uitofp i1 [[TMP34]] to float -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP]], float noundef [[CONV]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV]]) // CHECK2-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP23]] to i8* // CHECK2-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP37:%.*]] = load float, float* [[TMP29]], align 4 // CHECK2-NEXT: [[TMP38:%.*]] = load float, float* [[TMP26]], align 4 // CHECK2-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP37]], [[TMP38]] @@ -2250,7 +2250,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEanERKS0_ -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR0]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR0]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 @@ -2261,7 +2261,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR0]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2270,17 +2270,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2309,8 +2309,8 @@ int main() { // CHECK2-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[VAR1_ADDR]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load float*, float** [[T_VAR1_ADDR]], align 8 // CHECK2-NEXT: store float 0.000000e+00, float* [[T_VAR2]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR3]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR14]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK2-NEXT: store float 0x47EFFFFFE0000000, float* [[T_VAR15]], align 4 // CHECK2-NEXT: br label [[WHILE_COND:%.*]] // CHECK2: while.cond: @@ -2324,11 +2324,11 @@ int main() { // CHECK2-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* // CHECK2-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR3]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false) -// CHECK2-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP4:![0-9]+]] // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], { float, float }* noundef nonnull align 4 dereferenceable(8) [[CF:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], { float, float }* nonnull align 4 dereferenceable(8) [[CF:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2381,7 +2381,7 @@ int main() { // CHECK2-NEXT: [[CF1_IMAG9:%.*]] = load float, float* [[CF1_IMAGP8]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast { float, float }* [[TMP0]] to i8* // CHECK2-NEXT: [[TMP8:%.*]] = bitcast { float, float }* [[ATOMIC_TEMP]] to i8* -// CHECK2-NEXT: call void @__atomic_load(i64 noundef 8, i8* noundef [[TMP7]], i8* noundef [[TMP8]], i32 noundef 0) +// CHECK2-NEXT: call void @__atomic_load(i64 8, i8* [[TMP7]], i8* [[TMP8]], i32 0) // CHECK2-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK2: atomic_cont: // CHECK2-NEXT: [[ATOMIC_TEMP_REALP:%.*]] = getelementptr inbounds { float, float }, { float, float }* [[ATOMIC_TEMP]], i32 0, i32 0 @@ -2409,7 +2409,7 @@ int main() { // CHECK2-NEXT: [[TMP9:%.*]] = bitcast { float, float }* [[TMP0]] to i8* // CHECK2-NEXT: [[TMP10:%.*]] = bitcast { float, float }* [[ATOMIC_TEMP]] to i8* // CHECK2-NEXT: [[TMP11:%.*]] = bitcast { float, float }* [[ATOMIC_TEMP10]] to i8* -// CHECK2-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 8, i8* noundef [[TMP9]], i8* noundef [[TMP10]], i8* noundef [[TMP11]], i32 noundef 0, i32 noundef 0) +// CHECK2-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, i8* [[TMP9]], i8* [[TMP10]], i8* [[TMP11]], i32 0, i32 0) // CHECK2-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK2: atomic_exit: // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] @@ -2418,7 +2418,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2464,38 +2464,38 @@ int main() { // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK2-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK2-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef [[SST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK2-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*, %struct.S.0*, i32*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]], %struct.S.0* [[VAR1]], i32* [[T_VAR1]]) // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR1]]) #[[ATTR5]] -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -2534,7 +2534,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2625,7 +2625,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.7 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2669,7 +2669,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2682,7 +2682,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2699,7 +2699,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2708,27 +2708,27 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK2-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK2-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2736,12 +2736,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2773,8 +2773,8 @@ int main() { // CHECK2-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR1_ADDR]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[T_VAR1_ADDR]], align 8 // CHECK2-NEXT: store i32 0, i32* [[T_VAR2]], align 128 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR3]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR14]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK2-NEXT: store i32 2147483647, i32* [[T_VAR15]], align 128 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR2]], align 128 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP0]], i64 0, i64 0 @@ -2808,25 +2808,25 @@ int main() { // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[T_VAR2]], align 128 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP1]], align 128 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP3]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK2-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* // CHECK2-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP23]], i8* align 4 [[TMP24]], i64 4, i1 false) -// CHECK2-NEXT: [[CALL7:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP4]]) +// CHECK2-NEXT: [[CALL7:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP4]]) // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL7]], 0 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK2: land.rhs: -// CHECK2-NEXT: [[CALL8:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[VAR14]]) +// CHECK2-NEXT: [[CALL8:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK2-NEXT: [[TOBOOL9:%.*]] = icmp ne i32 [[CALL8]], 0 // CHECK2-NEXT: br label [[LAND_END]] // CHECK2: land.end: // CHECK2-NEXT: [[TMP25:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL9]], [[LAND_RHS]] ] // CHECK2-NEXT: [[CONV:%.*]] = zext i1 [[TMP25]] to i32 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[CONV]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) // CHECK2-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* // CHECK2-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP26]], i8* align 4 [[TMP27]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP5]], align 128 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[T_VAR15]], align 128 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP28]], [[TMP29]] @@ -2846,39 +2846,39 @@ int main() { // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[T_VAR2]], align 128 // CHECK2-NEXT: [[TMP33:%.*]] = atomicrmw add i32* [[TMP1]], i32 [[TMP32]] monotonic, align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL10:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP3]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK2-NEXT: [[CALL10:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK2-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP3]] to i8* // CHECK2-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[CALL10]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL12:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP4]]) +// CHECK2-NEXT: [[CALL12:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP4]]) // CHECK2-NEXT: [[TOBOOL13:%.*]] = icmp ne i32 [[CALL12]], 0 // CHECK2-NEXT: br i1 [[TOBOOL13]], label [[LAND_RHS14:%.*]], label [[LAND_END17:%.*]] // CHECK2: land.rhs14: -// CHECK2-NEXT: [[CALL15:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[VAR14]]) +// CHECK2-NEXT: [[CALL15:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK2-NEXT: [[TOBOOL16:%.*]] = icmp ne i32 [[CALL15]], 0 // CHECK2-NEXT: br label [[LAND_END17]] // CHECK2: land.end17: // CHECK2-NEXT: [[TMP36:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE2]] ], [ [[TOBOOL16]], [[LAND_RHS14]] ] // CHECK2-NEXT: [[CONV18:%.*]] = zext i1 [[TMP36]] to i32 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP11]], i32 noundef [[CONV18]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP11]], i32 [[CONV18]]) // CHECK2-NEXT: [[TMP37:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* // CHECK2-NEXT: [[TMP38:%.*]] = bitcast %struct.S.0* [[REF_TMP11]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP37]], i8* align 4 [[TMP38]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP11]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP11]]) #[[ATTR5]] // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[TMP39:%.*]] = load i32, i32* [[T_VAR15]], align 128 // CHECK2-NEXT: [[TMP40:%.*]] = atomicrmw min i32* [[TMP5]], i32 [[TMP39]] monotonic, align 4 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK2: .omp.reduction.default: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR14]]) #[[ATTR5]] -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR3]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR5]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2917,25 +2917,25 @@ int main() { // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP8]], align 128 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 128 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP17]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP14]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP14]]) // CHECK2-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* // CHECK2-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK2-NEXT: [[CALL2:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP23]]) +// CHECK2-NEXT: [[CALL2:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP23]]) // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL2]], 0 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK2: land.rhs: -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP20]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK2-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[CALL3]], 0 // CHECK2-NEXT: br label [[LAND_END]] // CHECK2: land.end: // CHECK2-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] // CHECK2-NEXT: [[CONV:%.*]] = zext i1 [[TMP34]] to i32 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[CONV]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) // CHECK2-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* // CHECK2-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP29]], align 128 // CHECK2-NEXT: [[TMP38:%.*]] = load i32, i32* [[TMP26]], align 128 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] @@ -2953,7 +2953,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEanERKS0_ -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR0]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR0]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -2964,7 +2964,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEcviEv -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) #[[ATTR0]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2973,17 +2973,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2995,7 +2995,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK2-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK2-NEXT: [[A2:%.*]] = alloca i32*, align 8 @@ -3011,7 +3011,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3078,7 +3078,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.11 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3102,7 +3102,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3118,7 +3118,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3127,7 +3127,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs -// CHECK3-SAME: (i16* noundef [[X:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i16* [[X:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 // CHECK3-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 @@ -3137,7 +3137,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef [[X:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* [[X:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3257,7 +3257,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3304,13 +3304,13 @@ int main() { // CHECK3-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @sivar) -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -3318,12 +3318,12 @@ int main() { // CHECK3-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7]] align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR7]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -3362,7 +3362,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3408,7 +3408,7 @@ int main() { // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP6]], align 8 // CHECK3-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 -// CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i32* [[A2]] to i8* // CHECK3-NEXT: store i8* [[TMP13]], i8** [[TMP12]], align 8 @@ -3454,7 +3454,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK3-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR0]] align 2 { +// CHECK3-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR0]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK3-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 @@ -3487,7 +3487,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3531,7 +3531,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3622,7 +3622,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.4 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3666,7 +3666,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3682,7 +3682,7 @@ int main() { // CHECK3-NEXT: store i32 1, i32* [[G1]], align 128 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store i32* [[G1]], i32** [[TMP1]], align 8 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i32* [[G1]] to i8* // CHECK3-NEXT: store i8* [[TMP3]], i8** [[TMP2]], align 8 @@ -3710,7 +3710,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3734,7 +3734,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs -// CHECK4-SAME: (i16* noundef [[X:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i16* [[X:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[X_ADDR:%.*]] = alloca i16*, align 8 // CHECK4-NEXT: store i16* [[X]], i16** [[X_ADDR]], align 8 @@ -3744,7 +3744,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef [[X:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* [[X:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3864,7 +3864,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3910,15 +3910,15 @@ int main() { // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @sivar) +// CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @sivar) // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// CHECK4-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -3926,12 +3926,12 @@ int main() { // CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR8]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR8]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -3943,7 +3943,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3976,7 +3976,7 @@ int main() { // CHECK4-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP6]](i8* noundef [[TMP4]]) +// CHECK4-NEXT: call void [[TMP6]](i8* [[TMP4]]) // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i32* [[G1]] to i8* // CHECK4-NEXT: store i8* [[TMP8]], i8** [[TMP7]], align 8 @@ -4004,7 +4004,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR8]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR8]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, [96 x i8], i32 }>*, align 8 @@ -4017,7 +4017,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.3 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4041,7 +4041,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR8]] align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR8]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -4080,7 +4080,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4143,7 +4143,7 @@ int main() { // CHECK4-NEXT: [[TMP11:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP12:%.*]] = load i8*, i8** [[TMP10]], align 8 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8* [[TMP12]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP13]](i8* noundef [[TMP11]]) +// CHECK4-NEXT: call void [[TMP13]](i8* [[TMP11]]) // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i32* [[A2]] to i8* // CHECK4-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 @@ -4189,7 +4189,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke_2 -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR8]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR8]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 @@ -4222,7 +4222,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[B:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[B:%.*]], i32* nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4313,7 +4313,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4357,7 +4357,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.8 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4399,3 +4399,4 @@ int main() { // CHECK4-NEXT: store i32 [[ADD3]], i32* [[TMP23]], align 4 // CHECK4-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_reduction_task_codegen.cpp b/clang/test/OpenMP/parallel_reduction_task_codegen.cpp index e2c71c1d708a5869099746ef67c86a2e3bcfbe65..88784908cf6172d4a1df0569ff1ddc6f8d1dc8a4 100644 --- a/clang/test/OpenMP/parallel_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/parallel_reduction_task_codegen.cpp @@ -36,7 +36,7 @@ int main(int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -48,7 +48,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -275,7 +275,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init. -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -288,7 +288,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -306,7 +306,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -328,7 +328,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -359,7 +359,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -373,7 +373,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -457,7 +457,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -506,7 +506,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -518,7 +518,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -745,7 +745,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init. -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -758,7 +758,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -776,7 +776,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -798,7 +798,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -829,7 +829,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -843,7 +843,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -927,7 +927,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 diff --git a/clang/test/OpenMP/parallel_sections_codegen.cpp b/clang/test/OpenMP/parallel_sections_codegen.cpp index 6193bef018e839a376f9052cfc0e871a1b189951..2ab50de3f4da3761554e66d079cfe6fbc8aff13a 100644 --- a/clang/test/OpenMP/parallel_sections_codegen.cpp +++ b/clang/test/OpenMP/parallel_sections_codegen.cpp @@ -59,12 +59,12 @@ int main() { // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -143,7 +143,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -221,12 +221,12 @@ int main() { // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -305,7 +305,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -362,3 +362,4 @@ int main() { // CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP11]]) #[[ATTR7]] // CHECK2-NEXT: unreachable // +// \ No newline at end of file diff --git a/clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp b/clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp index eee8e56f460846efe9fe3595160cc9db1da9a7df..ba58ee0a4f8037472f7f094d70a57352d6163e66 100644 --- a/clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp @@ -36,7 +36,7 @@ int main(int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -48,7 +48,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -317,7 +317,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init. -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -330,7 +330,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -348,7 +348,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -370,7 +370,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -401,7 +401,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -415,7 +415,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -499,7 +499,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -548,7 +548,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -560,7 +560,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -829,7 +829,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init. -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -842,7 +842,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -860,7 +860,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -882,7 +882,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -913,7 +913,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -927,7 +927,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1011,7 +1011,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 diff --git a/clang/test/OpenMP/reduction_compound_op.cpp b/clang/test/OpenMP/reduction_compound_op.cpp index 36bc8d6842e38ec0d79abe8e2be70cb7d072e474..2e8797df21901299f7a13bee2bca27ec7007ceb8 100644 --- a/clang/test/OpenMP/reduction_compound_op.cpp +++ b/clang/test/OpenMP/reduction_compound_op.cpp @@ -1,21 +1,21 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs -//RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-unknown-linux-gnu -fopenmp -DNORM \ +//RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fopenmp -DNORM \ //RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix NORM -//RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-unknown-linux-gnu -fopenmp -DCOMP \ +//RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fopenmp -DCOMP \ //RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix COMP // Prefer compound operators since that is what the spec seems to say. -//RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-unknown-linux-gnu -fopenmp -DNORM -DCOMP \ +//RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fopenmp -DNORM -DCOMP \ //RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix COMP -//RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-unknown-linux-gnu -fopenmp-simd -DNORM \ +//RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fopenmp-simd -DNORM \ //RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix SIMD-ONLY -//RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-unknown-linux-gnu -fopenmp-simd -DCOMP \ +//RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fopenmp-simd -DCOMP \ //RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix SIMD-ONLY -//RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-unknown-linux-gnu -fopenmp-simd -DNORM -DCOMP \ +//RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fopenmp-simd -DNORM -DCOMP \ //RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix SIMD-ONLY // SIMD-ONLY-NOT: {{__kmpc|__tgt}} diff --git a/clang/test/OpenMP/sections_firstprivate_codegen.cpp b/clang/test/OpenMP/sections_firstprivate_codegen.cpp index 014f5a1c46f85d98d7cec7723330606ff291c1f4..22fc096043c5c482b713119db0e69f8a6a6a9a50 100644 --- a/clang/test/OpenMP/sections_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/sections_firstprivate_codegen.cpp @@ -150,33 +150,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -189,7 +189,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -200,14 +200,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -215,12 +215,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -228,7 +228,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -236,7 +236,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -255,7 +255,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -293,17 +293,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done1: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP2]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR]], %struct.S* noundef nonnull align 4 dereferenceable(4) @var, %struct.St* noundef [[AGG_TMP2]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP2]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], %struct.S* nonnull align 4 dereferenceable(4) @var, %struct.St* [[AGG_TMP2]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[SIVAR]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -343,33 +343,33 @@ int main() { // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done5: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -377,17 +377,17 @@ int main() { // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -400,35 +400,35 @@ int main() { // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -441,7 +441,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -461,7 +461,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -470,17 +470,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -488,12 +488,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -539,17 +539,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -593,14 +593,14 @@ int main() { // CHECK1-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done10: @@ -611,7 +611,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -619,22 +619,22 @@ int main() { // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -646,7 +646,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -662,7 +662,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -681,7 +681,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -701,33 +701,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -740,7 +740,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -751,14 +751,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -766,12 +766,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -779,7 +779,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -787,7 +787,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -806,7 +806,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -844,17 +844,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done1: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP2]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR]], %struct.S* noundef nonnull align 4 dereferenceable(4) @var, %struct.St* noundef [[AGG_TMP2]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP2]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], %struct.S* nonnull align 4 dereferenceable(4) @var, %struct.St* [[AGG_TMP2]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[SIVAR]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -894,33 +894,33 @@ int main() { // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done5: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -928,17 +928,17 @@ int main() { // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // @@ -951,35 +951,35 @@ int main() { // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -992,7 +992,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1012,7 +1012,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1021,17 +1021,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1039,12 +1039,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1090,17 +1090,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -1144,14 +1144,14 @@ int main() { // CHECK2-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done10: @@ -1162,7 +1162,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1170,22 +1170,22 @@ int main() { // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1197,7 +1197,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1213,7 +1213,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1232,7 +1232,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1252,33 +1252,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1291,7 +1291,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1302,14 +1302,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1317,12 +1317,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1330,7 +1330,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1338,7 +1338,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1357,7 +1357,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -1370,12 +1370,12 @@ int main() { // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1430,7 +1430,7 @@ int main() { // CHECK3-NEXT: store i32* [[G]], i32** [[TMP12]], align 8 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: store i32* [[SIVAR1]], i32** [[TMP13]], align 8 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK3: .omp.sections.exit: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1457,33 +1457,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1496,7 +1496,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1507,14 +1507,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1522,12 +1522,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1535,7 +1535,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -1543,7 +1543,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1562,7 +1562,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -1592,12 +1592,12 @@ int main() { // CHECK4-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP5]](i8* noundef [[TMP3]]) +// CHECK4-NEXT: call void [[TMP5]](i8* [[TMP3]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 @@ -1609,7 +1609,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1682,7 +1682,7 @@ int main() { // CHECK4-NEXT: [[TMP16:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP17:%.*]] = load i8*, i8** [[TMP15]], align 8 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8* [[TMP17]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP18]](i8* noundef [[TMP16]]) +// CHECK4-NEXT: call void [[TMP18]](i8* [[TMP16]]) // CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK4: .omp.sections.exit: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1698,7 +1698,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@var_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>*, align 8 @@ -1720,3 +1720,4 @@ int main() { // CHECK4-NEXT: call void @__cxx_global_var_init.2() // CHECK4-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/sections_lastprivate_codegen.cpp b/clang/test/OpenMP/sections_lastprivate_codegen.cpp index 1ddd76eae0a5f19fe5a4d110c363279448c06ba2..80001b843d24e51da1ac70b56528700c00dc3344 100644 --- a/clang/test/OpenMP/sections_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/sections_lastprivate_codegen.cpp @@ -198,47 +198,47 @@ int main() { // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32* @_ZZ4mainE5sivar) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -246,12 +246,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -291,12 +291,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR4]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -322,7 +322,7 @@ int main() { // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[ARRAYIDX6]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: store i32 31, i32* [[SIVAR5]], align 4 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.exit: @@ -353,25 +353,25 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP23]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN7]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL8:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL8:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP24]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done9: -// CHECK1-NEXT: [[CALL10:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[TMP3]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK1-NEXT: [[CALL10:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[SIVAR5]], align 4 // CHECK1-NEXT: store i32 [[TMP25]], i32* [[TMP4]], align 4 // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1: .omp.lastprivate.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done12: @@ -382,17 +382,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -466,35 +466,35 @@ int main() { // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -505,7 +505,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -514,7 +514,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -528,17 +528,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -546,12 +546,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -587,12 +587,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR4]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -621,7 +621,7 @@ int main() { // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.case5: // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[ARRAYIDX6]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.exit: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -651,23 +651,23 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP22]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN7]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL8:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL8:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP23]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done9: -// CHECK1-NEXT: [[CALL10:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[TMP3]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK1-NEXT: [[CALL10:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1: .omp.lastprivate.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR4]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done12: @@ -678,17 +678,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -699,7 +699,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -713,7 +713,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -731,47 +731,47 @@ int main() { // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32* @_ZZ4mainE5sivar) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -779,12 +779,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -824,12 +824,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR4]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -855,7 +855,7 @@ int main() { // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 // CHECK2-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[ARRAYIDX6]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK2-NEXT: store i32 31, i32* [[SIVAR5]], align 4 // CHECK2-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK2: .omp.sections.exit: @@ -886,25 +886,25 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP23]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN7]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL8:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL8:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP24]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done9: -// CHECK2-NEXT: [[CALL10:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[TMP3]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK2-NEXT: [[CALL10:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[SIVAR5]], align 4 // CHECK2-NEXT: store i32 [[TMP25]], i32* [[TMP4]], align 4 // CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK2: .omp.lastprivate.done: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done12: @@ -915,17 +915,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -999,35 +999,35 @@ int main() { // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1038,7 +1038,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1047,7 +1047,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1061,17 +1061,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1079,12 +1079,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1120,12 +1120,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR4]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -1154,7 +1154,7 @@ int main() { // CHECK2-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK2: .omp.sections.case5: // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[ARRAYIDX6]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK2-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK2: .omp.sections.exit: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1184,23 +1184,23 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP22]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN7]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL8:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL8:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP23]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done9: -// CHECK2-NEXT: [[CALL10:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[TMP3]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK2-NEXT: [[CALL10:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK2-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK2: .omp.lastprivate.done: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR4]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done12: @@ -1211,17 +1211,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1232,7 +1232,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1246,7 +1246,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1262,12 +1262,12 @@ int main() { // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1318,7 +1318,7 @@ int main() { // CHECK3-NEXT: store i32* [[G]], i32** [[TMP10]], align 8 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK3: .omp.sections.exit: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1368,12 +1368,12 @@ int main() { // CHECK4-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP5]](i8* noundef [[TMP3]]) +// CHECK4-NEXT: call void [[TMP5]](i8* [[TMP3]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 @@ -1385,7 +1385,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1454,7 +1454,7 @@ int main() { // CHECK4-NEXT: [[TMP14:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP15:%.*]] = load i8*, i8** [[TMP13]], align 8 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP15]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP16]](i8* noundef [[TMP14]]) +// CHECK4-NEXT: call void [[TMP16]](i8* [[TMP14]]) // CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK4: .omp.sections.exit: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1480,7 +1480,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>*, align 8 @@ -1504,47 +1504,47 @@ int main() { // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32* @_ZZ4mainE5sivar) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP2]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1552,12 +1552,12 @@ int main() { // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1597,12 +1597,12 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR4]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -1628,7 +1628,7 @@ int main() { // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 // CHECK5-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[ARRAYIDX6]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK5-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: store i32 31, i32* [[SIVAR5]], align 4 // CHECK5-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK5: .omp.sections.exit: @@ -1659,25 +1659,25 @@ int main() { // CHECK5: omp.arraycpy.body: // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP23]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN7]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK5-NEXT: [[CALL8:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK5-NEXT: [[CALL8:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP24]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] // CHECK5: omp.arraycpy.done9: -// CHECK5-NEXT: [[CALL10:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[TMP3]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK5-NEXT: [[CALL10:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[SIVAR5]], align 4 // CHECK5-NEXT: store i32 [[TMP25]], i32* [[TMP4]], align 4 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done12: @@ -1688,17 +1688,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1790,35 +1790,35 @@ int main() { // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP2]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1829,7 +1829,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1843,7 +1843,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1852,17 +1852,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1870,12 +1870,12 @@ int main() { // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1911,12 +1911,12 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR4]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -1945,7 +1945,7 @@ int main() { // CHECK5-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK5: .omp.sections.case5: // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[ARRAYIDX6]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK5-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK5: .omp.sections.exit: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1975,23 +1975,23 @@ int main() { // CHECK5: omp.arraycpy.body: // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP22]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN7]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK5-NEXT: [[CALL8:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK5-NEXT: [[CALL8:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP23]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] // CHECK5: omp.arraycpy.done9: -// CHECK5-NEXT: [[CALL10:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[TMP3]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK5-NEXT: [[CALL10:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR4]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done12: @@ -2002,17 +2002,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2023,7 +2023,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2037,7 +2037,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2055,47 +2055,47 @@ int main() { // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32* @_ZZ4mainE5sivar) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP2]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2103,12 +2103,12 @@ int main() { // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2148,12 +2148,12 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR4]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -2179,7 +2179,7 @@ int main() { // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 // CHECK6-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[ARRAYIDX6]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK6-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK6-NEXT: store i32 31, i32* [[SIVAR5]], align 4 // CHECK6-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK6: .omp.sections.exit: @@ -2210,25 +2210,25 @@ int main() { // CHECK6: omp.arraycpy.body: // CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP23]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN7]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK6-NEXT: [[CALL8:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK6-NEXT: [[CALL8:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP24]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] // CHECK6: omp.arraycpy.done9: -// CHECK6-NEXT: [[CALL10:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* noundef [[TMP3]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK6-NEXT: [[CALL10:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[SIVAR5]], align 4 // CHECK6-NEXT: store i32 [[TMP25]], i32* [[TMP4]], align 4 // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6: .omp.lastprivate.done: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK6-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done12: @@ -2239,17 +2239,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2341,35 +2341,35 @@ int main() { // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP2]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2380,7 +2380,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2394,7 +2394,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2403,17 +2403,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2421,12 +2421,12 @@ int main() { // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2462,12 +2462,12 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR4]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -2496,7 +2496,7 @@ int main() { // CHECK6-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK6: .omp.sections.case5: // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[ARRAYIDX6]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK6-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK6-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK6: .omp.sections.exit: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2526,23 +2526,23 @@ int main() { // CHECK6: omp.arraycpy.body: // CHECK6-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP22]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK6-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN7]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK6-NEXT: [[CALL8:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK6-NEXT: [[CALL8:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK6-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK6-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP23]] // CHECK6-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] // CHECK6: omp.arraycpy.done9: -// CHECK6-NEXT: [[CALL10:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* noundef [[TMP3]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) +// CHECK6-NEXT: [[CALL10:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6: .omp.lastprivate.done: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR4]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK6-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done12: @@ -2553,17 +2553,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2574,7 +2574,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2588,7 +2588,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2604,12 +2604,12 @@ int main() { // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 // CHECK7-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK7-NEXT: ret i32 0 // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2660,7 +2660,7 @@ int main() { // CHECK7-NEXT: store i32* [[G]], i32** [[TMP10]], align 8 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK7-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 -// CHECK7-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK7-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK7: .omp.sections.exit: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2710,12 +2710,12 @@ int main() { // CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP5]](i8* noundef [[TMP3]]) +// CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) // CHECK8-NEXT: ret i32 0 // // // CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK8-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 @@ -2727,7 +2727,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2796,7 +2796,7 @@ int main() { // CHECK8-NEXT: [[TMP14:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK8-NEXT: [[TMP15:%.*]] = load i8*, i8** [[TMP13]], align 8 // CHECK8-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP15]] to void (i8*)* -// CHECK8-NEXT: call void [[TMP16]](i8* noundef [[TMP14]]) +// CHECK8-NEXT: call void [[TMP16]](i8* [[TMP14]]) // CHECK8-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK8: .omp.sections.exit: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2822,7 +2822,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@g_block_invoke -// CHECK8-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>*, align 8 @@ -2835,3 +2835,4 @@ int main() { // CHECK8-NEXT: store i32 29, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 // CHECK8-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/sections_private_codegen.cpp b/clang/test/OpenMP/sections_private_codegen.cpp index 80abc0ac80ec6b6844beb13a95d9d17e94f5abeb..65d4b04138ab2e26ad3f1d7b032e9d150a1f2ac8 100644 --- a/clang/test/OpenMP/sections_private_codegen.cpp +++ b/clang/test/OpenMP/sections_private_codegen.cpp @@ -114,46 +114,46 @@ int main() { // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -161,12 +161,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -191,12 +191,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -238,14 +238,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -256,12 +256,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -274,35 +274,35 @@ int main() { // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -313,7 +313,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -327,7 +327,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -336,17 +336,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -354,12 +354,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -383,12 +383,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -432,14 +432,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN3]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done4: @@ -450,17 +450,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -471,7 +471,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -485,7 +485,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -503,46 +503,46 @@ int main() { // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -550,12 +550,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -580,12 +580,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -627,14 +627,14 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done3: @@ -645,12 +645,12 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // @@ -663,35 +663,35 @@ int main() { // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -702,7 +702,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -716,7 +716,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -725,17 +725,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -743,12 +743,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -772,12 +772,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -821,14 +821,14 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN3]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done4: @@ -839,17 +839,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -860,7 +860,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -874,7 +874,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -888,12 +888,12 @@ int main() { // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -941,7 +941,7 @@ int main() { // CHECK3-NEXT: store double* [[G]], double** [[TMP9]], align 8 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[TMP10]], align 8 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK3: .omp.sections.exit: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -963,12 +963,12 @@ int main() { // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// CHECK4-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -980,7 +980,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1046,7 +1046,7 @@ int main() { // CHECK4-NEXT: [[TMP13:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP14:%.*]] = load i8*, i8** [[TMP12]], align 8 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8* [[TMP14]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP15]](i8* noundef [[TMP13]]) +// CHECK4-NEXT: call void [[TMP15]](i8* [[TMP13]]) // CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK4: .omp.sections.exit: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1062,7 +1062,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8 @@ -1075,3 +1075,4 @@ int main() { // CHECK4-NEXT: store i32 222, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 // CHECK4-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/sections_reduction_codegen.cpp b/clang/test/OpenMP/sections_reduction_codegen.cpp index 27da052cf9ac6132a553831fc93fc13a597975da..9985d2fe69a99e0a6709e188508e0bc20b5e3f50 100644 --- a/clang/test/OpenMP/sections_reduction_codegen.cpp +++ b/clang/test/OpenMP/sections_reduction_codegen.cpp @@ -193,48 +193,48 @@ int main() { // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float*, %struct.S*, %struct.S*, float*, [2 x i32]*, [2 x %struct.S]*)* @.omp_outlined. to void (i32*, i32*, ...)*), float* [[T_VAR]], %struct.S* [[VAR]], %struct.S* [[VAR1]], float* [[T_VAR1]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]]) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR1]]) #[[ATTR4:[0-9]+]] -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -242,12 +242,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -292,8 +292,8 @@ int main() { // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 // CHECK1-NEXT: store float 0.000000e+00, float* [[T_VAR2]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR3]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR14]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK1-NEXT: store float 0x47EFFFFFE0000000, float* [[T_VAR15]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -365,25 +365,25 @@ int main() { // CHECK1-NEXT: [[TMP33:%.*]] = load float, float* [[T_VAR2]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP32]], [[TMP33]] // CHECK1-NEXT: store float [[ADD]], float* [[TMP0]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK1-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP1]] to i8* // CHECK1-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) -// CHECK1-NEXT: [[CALL10:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP2]]) +// CHECK1-NEXT: [[CALL10:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK1-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL10]], 0.000000e+00 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK1: land.rhs: -// CHECK1-NEXT: [[CALL11:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[VAR14]]) +// CHECK1-NEXT: [[CALL11:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK1-NEXT: [[TOBOOL12:%.*]] = fcmp une float [[CALL11]], 0.000000e+00 // CHECK1-NEXT: br label [[LAND_END]] // CHECK1: land.end: // CHECK1-NEXT: [[TMP36:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL12]], [[LAND_RHS]] ] // CHECK1-NEXT: [[CONV13:%.*]] = uitofp i1 [[TMP36]] to float -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP]], float noundef [[CONV13]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV13]]) // CHECK1-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[TMP2]] to i8* // CHECK1-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP37]], i8* align 4 [[TMP38]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP39:%.*]] = load float, float* [[TMP3]], align 4 // CHECK1-NEXT: [[TMP40:%.*]] = load float, float* [[T_VAR15]], align 4 // CHECK1-NEXT: [[CMP14:%.*]] = fcmp olt float [[TMP39]], [[TMP40]] @@ -421,27 +421,27 @@ int main() { // CHECK1-NEXT: br i1 [[TMP54]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK1: atomic_exit: // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL16:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK1-NEXT: [[CALL16:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK1-NEXT: [[TMP55:%.*]] = bitcast %struct.S* [[TMP1]] to i8* // CHECK1-NEXT: [[TMP56:%.*]] = bitcast %struct.S* [[CALL16]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP55]], i8* align 4 [[TMP56]], i64 4, i1 false) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL18:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP2]]) +// CHECK1-NEXT: [[CALL18:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK1-NEXT: [[TOBOOL19:%.*]] = fcmp une float [[CALL18]], 0.000000e+00 // CHECK1-NEXT: br i1 [[TOBOOL19]], label [[LAND_RHS20:%.*]], label [[LAND_END23:%.*]] // CHECK1: land.rhs20: -// CHECK1-NEXT: [[CALL21:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[VAR14]]) +// CHECK1-NEXT: [[CALL21:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK1-NEXT: [[TOBOOL22:%.*]] = fcmp une float [[CALL21]], 0.000000e+00 // CHECK1-NEXT: br label [[LAND_END23]] // CHECK1: land.end23: // CHECK1-NEXT: [[TMP57:%.*]] = phi i1 [ false, [[ATOMIC_EXIT]] ], [ [[TOBOOL22]], [[LAND_RHS20]] ] // CHECK1-NEXT: [[CONV24:%.*]] = uitofp i1 [[TMP57]] to float -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP17]], float noundef [[CONV24]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP17]], float [[CONV24]]) // CHECK1-NEXT: [[TMP58:%.*]] = bitcast %struct.S* [[TMP2]] to i8* // CHECK1-NEXT: [[TMP59:%.*]] = bitcast %struct.S* [[REF_TMP17]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP58]], i8* align 4 [[TMP59]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP17]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP17]]) #[[ATTR4]] // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[TMP60:%.*]] = load float, float* [[T_VAR15]], align 4 // CHECK1-NEXT: [[TMP61:%.*]] = bitcast float* [[TMP3]] to i32* @@ -475,14 +475,14 @@ int main() { // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR14]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR3]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR4]] // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP7]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -521,25 +521,25 @@ int main() { // CHECK1-NEXT: [[TMP31:%.*]] = load float, float* [[TMP8]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP30]], [[TMP31]] // CHECK1-NEXT: store float [[ADD]], float* [[TMP11]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP17]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP14]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP14]]) // CHECK1-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP17]] to i8* // CHECK1-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK1-NEXT: [[CALL2:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP23]]) +// CHECK1-NEXT: [[CALL2:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP23]]) // CHECK1-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL2]], 0.000000e+00 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK1: land.rhs: -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP20]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK1-NEXT: [[TOBOOL4:%.*]] = fcmp une float [[CALL3]], 0.000000e+00 // CHECK1-NEXT: br label [[LAND_END]] // CHECK1: land.end: // CHECK1-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] // CHECK1-NEXT: [[CONV:%.*]] = uitofp i1 [[TMP34]] to float -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP]], float noundef [[CONV]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV]]) // CHECK1-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP23]] to i8* // CHECK1-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP37:%.*]] = load float, float* [[TMP29]], align 4 // CHECK1-NEXT: [[TMP38:%.*]] = load float, float* [[TMP26]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP37]], [[TMP38]] @@ -557,7 +557,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEanERKS0_ -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 @@ -568,7 +568,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR6]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR6]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -577,12 +577,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -598,37 +598,37 @@ int main() { // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, %struct.S.0*, %struct.S.0*, i32*, [2 x i32]*, [2 x %struct.S.0]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR]], %struct.S.0* [[VAR]], %struct.S.0* [[VAR1]], i32* [[T_VAR1]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]]) // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR1]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -641,7 +641,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -659,7 +659,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -668,17 +668,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -686,12 +686,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -732,8 +732,8 @@ int main() { // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 // CHECK1-NEXT: store i32 0, i32* [[T_VAR2]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR3]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR14]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK1-NEXT: store i32 2147483647, i32* [[T_VAR15]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -799,25 +799,25 @@ int main() { // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK1-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP1]] to i8* // CHECK1-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) -// CHECK1-NEXT: [[CALL8:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP2]]) +// CHECK1-NEXT: [[CALL8:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL8]], 0 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK1: land.rhs: -// CHECK1-NEXT: [[CALL9:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[VAR14]]) +// CHECK1-NEXT: [[CALL9:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK1-NEXT: [[TOBOOL10:%.*]] = icmp ne i32 [[CALL9]], 0 // CHECK1-NEXT: br label [[LAND_END]] // CHECK1: land.end: // CHECK1-NEXT: [[TMP33:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL10]], [[LAND_RHS]] ] // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP33]] to i32 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[CONV]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) // CHECK1-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP2]] to i8* // CHECK1-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[T_VAR15]], align 4 // CHECK1-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP36]], [[TMP37]] @@ -837,39 +837,39 @@ int main() { // CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK1-NEXT: [[TMP41:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP40]] monotonic, align 4 // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL12:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK1-NEXT: [[CALL12:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK1-NEXT: [[TMP42:%.*]] = bitcast %struct.S.0* [[TMP1]] to i8* // CHECK1-NEXT: [[TMP43:%.*]] = bitcast %struct.S.0* [[CALL12]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 4, i1 false) // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: [[CALL14:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP2]]) +// CHECK1-NEXT: [[CALL14:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK1-NEXT: [[TOBOOL15:%.*]] = icmp ne i32 [[CALL14]], 0 // CHECK1-NEXT: br i1 [[TOBOOL15]], label [[LAND_RHS16:%.*]], label [[LAND_END19:%.*]] // CHECK1: land.rhs16: -// CHECK1-NEXT: [[CALL17:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[VAR14]]) +// CHECK1-NEXT: [[CALL17:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK1-NEXT: [[TOBOOL18:%.*]] = icmp ne i32 [[CALL17]], 0 // CHECK1-NEXT: br label [[LAND_END19]] // CHECK1: land.end19: // CHECK1-NEXT: [[TMP44:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE2]] ], [ [[TOBOOL18]], [[LAND_RHS16]] ] // CHECK1-NEXT: [[CONV20:%.*]] = zext i1 [[TMP44]] to i32 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP13]], i32 noundef [[CONV20]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP13]], i32 [[CONV20]]) // CHECK1-NEXT: [[TMP45:%.*]] = bitcast %struct.S.0* [[TMP2]] to i8* // CHECK1-NEXT: [[TMP46:%.*]] = bitcast %struct.S.0* [[REF_TMP13]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP45]], i8* align 4 [[TMP46]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP13]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP13]]) #[[ATTR4]] // CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[TMP47:%.*]] = load i32, i32* [[T_VAR15]], align 4 // CHECK1-NEXT: [[TMP48:%.*]] = atomicrmw min i32* [[TMP3]], i32 [[TMP47]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR14]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR3]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR5]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR5]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -908,25 +908,25 @@ int main() { // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP17]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP14]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP14]]) // CHECK1-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* // CHECK1-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK1-NEXT: [[CALL2:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP23]]) +// CHECK1-NEXT: [[CALL2:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP23]]) // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL2]], 0 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK1: land.rhs: -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP20]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK1-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[CALL3]], 0 // CHECK1-NEXT: br label [[LAND_END]] // CHECK1: land.end: // CHECK1-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP34]] to i32 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[CONV]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) // CHECK1-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* // CHECK1-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[TMP26]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] @@ -944,7 +944,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEanERKS0_ -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR6]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR6]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -955,7 +955,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEcviEv -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) #[[ATTR6]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR6]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -964,17 +964,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -987,7 +987,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1005,7 +1005,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1025,48 +1025,48 @@ int main() { // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK2-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store float 0.000000e+00, float* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float*, %struct.S*, %struct.S*, float*, [2 x i32]*, [2 x %struct.S]*)* @.omp_outlined. to void (i32*, i32*, ...)*), float* [[T_VAR]], %struct.S* [[VAR]], %struct.S* [[VAR1]], float* [[T_VAR1]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]]) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR1]]) #[[ATTR4:[0-9]+]] -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1074,12 +1074,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], float* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1124,8 +1124,8 @@ int main() { // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 // CHECK2-NEXT: store float 0.000000e+00, float* [[T_VAR2]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR3]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR14]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK2-NEXT: store float 0x47EFFFFFE0000000, float* [[T_VAR15]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -1197,25 +1197,25 @@ int main() { // CHECK2-NEXT: [[TMP33:%.*]] = load float, float* [[T_VAR2]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP32]], [[TMP33]] // CHECK2-NEXT: store float [[ADD]], float* [[TMP0]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK2-NEXT: [[TMP34:%.*]] = bitcast %struct.S* [[TMP1]] to i8* // CHECK2-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) -// CHECK2-NEXT: [[CALL10:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP2]]) +// CHECK2-NEXT: [[CALL10:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK2-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL10]], 0.000000e+00 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK2: land.rhs: -// CHECK2-NEXT: [[CALL11:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[VAR14]]) +// CHECK2-NEXT: [[CALL11:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK2-NEXT: [[TOBOOL12:%.*]] = fcmp une float [[CALL11]], 0.000000e+00 // CHECK2-NEXT: br label [[LAND_END]] // CHECK2: land.end: // CHECK2-NEXT: [[TMP36:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL12]], [[LAND_RHS]] ] // CHECK2-NEXT: [[CONV13:%.*]] = uitofp i1 [[TMP36]] to float -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP]], float noundef [[CONV13]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV13]]) // CHECK2-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[TMP2]] to i8* // CHECK2-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP37]], i8* align 4 [[TMP38]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP39:%.*]] = load float, float* [[TMP3]], align 4 // CHECK2-NEXT: [[TMP40:%.*]] = load float, float* [[T_VAR15]], align 4 // CHECK2-NEXT: [[CMP14:%.*]] = fcmp olt float [[TMP39]], [[TMP40]] @@ -1253,27 +1253,27 @@ int main() { // CHECK2-NEXT: br i1 [[TMP54]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK2: atomic_exit: // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL16:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK2-NEXT: [[CALL16:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP1]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK2-NEXT: [[TMP55:%.*]] = bitcast %struct.S* [[TMP1]] to i8* // CHECK2-NEXT: [[TMP56:%.*]] = bitcast %struct.S* [[CALL16]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP55]], i8* align 4 [[TMP56]], i64 4, i1 false) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL18:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP2]]) +// CHECK2-NEXT: [[CALL18:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK2-NEXT: [[TOBOOL19:%.*]] = fcmp une float [[CALL18]], 0.000000e+00 // CHECK2-NEXT: br i1 [[TOBOOL19]], label [[LAND_RHS20:%.*]], label [[LAND_END23:%.*]] // CHECK2: land.rhs20: -// CHECK2-NEXT: [[CALL21:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[VAR14]]) +// CHECK2-NEXT: [[CALL21:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK2-NEXT: [[TOBOOL22:%.*]] = fcmp une float [[CALL21]], 0.000000e+00 // CHECK2-NEXT: br label [[LAND_END23]] // CHECK2: land.end23: // CHECK2-NEXT: [[TMP57:%.*]] = phi i1 [ false, [[ATOMIC_EXIT]] ], [ [[TOBOOL22]], [[LAND_RHS20]] ] // CHECK2-NEXT: [[CONV24:%.*]] = uitofp i1 [[TMP57]] to float -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP17]], float noundef [[CONV24]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP17]], float [[CONV24]]) // CHECK2-NEXT: [[TMP58:%.*]] = bitcast %struct.S* [[TMP2]] to i8* // CHECK2-NEXT: [[TMP59:%.*]] = bitcast %struct.S* [[REF_TMP17]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP58]], i8* align 4 [[TMP59]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP17]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP17]]) #[[ATTR4]] // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[TMP60:%.*]] = load float, float* [[T_VAR15]], align 4 // CHECK2-NEXT: [[TMP61:%.*]] = bitcast float* [[TMP3]] to i32* @@ -1307,14 +1307,14 @@ int main() { // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.reduction.var) // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK2: .omp.reduction.default: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR14]]) #[[ATTR4]] -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR3]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR4]] // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP7]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1353,25 +1353,25 @@ int main() { // CHECK2-NEXT: [[TMP31:%.*]] = load float, float* [[TMP8]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP30]], [[TMP31]] // CHECK2-NEXT: store float [[ADD]], float* [[TMP11]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* noundef [[TMP17]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP14]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEanERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP14]]) // CHECK2-NEXT: [[TMP32:%.*]] = bitcast %struct.S* [[TMP17]] to i8* // CHECK2-NEXT: [[TMP33:%.*]] = bitcast %struct.S* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK2-NEXT: [[CALL2:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP23]]) +// CHECK2-NEXT: [[CALL2:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP23]]) // CHECK2-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL2]], 0.000000e+00 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK2: land.rhs: -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef float @_ZN1SIfEcvfEv(%struct.S* noundef [[TMP20]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call float @_ZN1SIfEcvfEv(%struct.S* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK2-NEXT: [[TOBOOL4:%.*]] = fcmp une float [[CALL3]], 0.000000e+00 // CHECK2-NEXT: br label [[LAND_END]] // CHECK2: land.end: // CHECK2-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] // CHECK2-NEXT: [[CONV:%.*]] = uitofp i1 [[TMP34]] to float -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[REF_TMP]], float noundef [[CONV]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]], float [[CONV]]) // CHECK2-NEXT: [[TMP35:%.*]] = bitcast %struct.S* [[TMP23]] to i8* // CHECK2-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[REF_TMP]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP37:%.*]] = load float, float* [[TMP29]], align 4 // CHECK2-NEXT: [[TMP38:%.*]] = load float, float* [[TMP26]], align 4 // CHECK2-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP37]], [[TMP38]] @@ -1389,7 +1389,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEanERKS0_ -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S*, align 8 @@ -1400,7 +1400,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR6]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR6]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1409,12 +1409,12 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // @@ -1430,37 +1430,37 @@ int main() { // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK2-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, %struct.S.0*, %struct.S.0*, i32*, [2 x i32]*, [2 x %struct.S.0]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR]], %struct.S.0* [[VAR]], %struct.S.0* [[VAR1]], i32* [[T_VAR1]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]]) // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR1]]) #[[ATTR4]] -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1473,7 +1473,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1491,7 +1491,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1500,17 +1500,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1518,12 +1518,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR1:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1564,8 +1564,8 @@ int main() { // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 // CHECK2-NEXT: store i32 0, i32* [[T_VAR2]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR3]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR14]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK2-NEXT: store i32 2147483647, i32* [[T_VAR15]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -1631,25 +1631,25 @@ int main() { // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK2-NEXT: [[TMP31:%.*]] = bitcast %struct.S.0* [[TMP1]] to i8* // CHECK2-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) -// CHECK2-NEXT: [[CALL8:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP2]]) +// CHECK2-NEXT: [[CALL8:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL8]], 0 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK2: land.rhs: -// CHECK2-NEXT: [[CALL9:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[VAR14]]) +// CHECK2-NEXT: [[CALL9:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK2-NEXT: [[TOBOOL10:%.*]] = icmp ne i32 [[CALL9]], 0 // CHECK2-NEXT: br label [[LAND_END]] // CHECK2: land.end: // CHECK2-NEXT: [[TMP33:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL10]], [[LAND_RHS]] ] // CHECK2-NEXT: [[CONV:%.*]] = zext i1 [[TMP33]] to i32 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[CONV]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) // CHECK2-NEXT: [[TMP34:%.*]] = bitcast %struct.S.0* [[TMP2]] to i8* // CHECK2-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP36:%.*]] = load i32, i32* [[TMP3]], align 4 // CHECK2-NEXT: [[TMP37:%.*]] = load i32, i32* [[T_VAR15]], align 4 // CHECK2-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP36]], [[TMP37]] @@ -1669,39 +1669,39 @@ int main() { // CHECK2-NEXT: [[TMP40:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK2-NEXT: [[TMP41:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP40]] monotonic, align 4 // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL12:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR3]]) +// CHECK2-NEXT: [[CALL12:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK2-NEXT: [[TMP42:%.*]] = bitcast %struct.S.0* [[TMP1]] to i8* // CHECK2-NEXT: [[TMP43:%.*]] = bitcast %struct.S.0* [[CALL12]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 4, i1 false) // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) -// CHECK2-NEXT: [[CALL14:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP2]]) +// CHECK2-NEXT: [[CALL14:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK2-NEXT: [[TOBOOL15:%.*]] = icmp ne i32 [[CALL14]], 0 // CHECK2-NEXT: br i1 [[TOBOOL15]], label [[LAND_RHS16:%.*]], label [[LAND_END19:%.*]] // CHECK2: land.rhs16: -// CHECK2-NEXT: [[CALL17:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[VAR14]]) +// CHECK2-NEXT: [[CALL17:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK2-NEXT: [[TOBOOL18:%.*]] = icmp ne i32 [[CALL17]], 0 // CHECK2-NEXT: br label [[LAND_END19]] // CHECK2: land.end19: // CHECK2-NEXT: [[TMP44:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE2]] ], [ [[TOBOOL18]], [[LAND_RHS16]] ] // CHECK2-NEXT: [[CONV20:%.*]] = zext i1 [[TMP44]] to i32 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP13]], i32 noundef [[CONV20]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP13]], i32 [[CONV20]]) // CHECK2-NEXT: [[TMP45:%.*]] = bitcast %struct.S.0* [[TMP2]] to i8* // CHECK2-NEXT: [[TMP46:%.*]] = bitcast %struct.S.0* [[REF_TMP13]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP45]], i8* align 4 [[TMP46]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP13]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP13]]) #[[ATTR4]] // CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], [8 x i32]* @.gomp_critical_user_.atomic_reduction.var) // CHECK2-NEXT: [[TMP47:%.*]] = load i32, i32* [[T_VAR15]], align 4 // CHECK2-NEXT: [[TMP48:%.*]] = atomicrmw min i32* [[TMP3]], i32 [[TMP47]] monotonic, align 4 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK2: .omp.reduction.default: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR14]]) #[[ATTR4]] -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR3]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR5]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR5]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1740,25 +1740,25 @@ int main() { // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP8]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* noundef [[TMP17]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP14]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEanERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP17]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP14]]) // CHECK2-NEXT: [[TMP32:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* // CHECK2-NEXT: [[TMP33:%.*]] = bitcast %struct.S.0* [[CALL]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) -// CHECK2-NEXT: [[CALL2:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP23]]) +// CHECK2-NEXT: [[CALL2:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP23]]) // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL2]], 0 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK2: land.rhs: -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZN1SIiEcviEv(%struct.S.0* noundef [[TMP20]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call i32 @_ZN1SIiEcviEv(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP20]]) // CHECK2-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[CALL3]], 0 // CHECK2-NEXT: br label [[LAND_END]] // CHECK2: land.end: // CHECK2-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ] // CHECK2-NEXT: [[CONV:%.*]] = zext i1 [[TMP34]] to i32 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[REF_TMP]], i32 noundef [[CONV]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 [[CONV]]) // CHECK2-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* // CHECK2-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[REF_TMP]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[REF_TMP]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP37:%.*]] = load i32, i32* [[TMP29]], align 4 // CHECK2-NEXT: [[TMP38:%.*]] = load i32, i32* [[TMP26]], align 4 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] @@ -1776,7 +1776,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEanERKS0_ -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR6]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR6]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1787,7 +1787,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEcviEv -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) #[[ATTR6]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR6]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1796,17 +1796,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1819,7 +1819,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1837,7 +1837,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1851,12 +1851,12 @@ int main() { // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1904,7 +1904,7 @@ int main() { // CHECK3: .omp.sections.case1: // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store double* [[G]], double** [[TMP9]], align 8 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK3: .omp.sections.exit: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1958,7 +1958,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1988,12 +1988,12 @@ int main() { // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// CHECK4-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -2005,7 +2005,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2070,7 +2070,7 @@ int main() { // CHECK4-NEXT: [[TMP12:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP11]], align 8 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8* [[TMP13]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP14]](i8* noundef [[TMP12]]) +// CHECK4-NEXT: call void [[TMP14]](i8* [[TMP12]]) // CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK4: .omp.sections.exit: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2124,7 +2124,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double }>*, align 8 @@ -2137,7 +2137,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2159,3 +2159,4 @@ int main() { // CHECK4-NEXT: store double [[ADD]], double* [[TMP11]], align 8 // CHECK4-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/sections_reduction_task_codegen.cpp b/clang/test/OpenMP/sections_reduction_task_codegen.cpp index f6f96d52564f6e67b49376dbe4437d6e0bc14579..34abfd05b887c5cf5aafea16f23c2b5254e60020 100644 --- a/clang/test/OpenMP/sections_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/sections_reduction_task_codegen.cpp @@ -37,7 +37,7 @@ int main(int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -48,7 +48,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -322,7 +322,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init. -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -335,7 +335,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -353,7 +353,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -375,7 +375,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -406,7 +406,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -420,7 +420,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -504,7 +504,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -553,7 +553,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -564,7 +564,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -838,7 +838,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init. -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -851,7 +851,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -869,7 +869,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -891,7 +891,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -922,7 +922,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -936,7 +936,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1020,7 +1020,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 diff --git a/clang/test/OpenMP/simd_codegen.cpp b/clang/test/OpenMP/simd_codegen.cpp index e261711f21de1446232c3c3a71f0efad80a4ed6e..335dfd78cacea68fa8aba715aa2319a93889a118 100644 --- a/clang/test/OpenMP/simd_codegen.cpp +++ b/clang/test/OpenMP/simd_codegen.cpp @@ -33,7 +33,7 @@ struct S { int a, b; }; -// CHECK-LABEL: define {{.*void}} @{{.*}}simple{{.*}}(float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}, float* noundef {{.+}}) +// CHECK-LABEL: define {{.*void}} @{{.*}}simple{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) void simple(float *a, float *b, float *c, float *d) { S s, *p; #ifdef OMP5 @@ -342,7 +342,7 @@ int templ1(T a, T *z) { } // Instatiation templ1 -// CHECK-LABEL: define {{.*i32}} @{{.*}}templ1{{.*}}(float noundef {{.+}}, float* noundef {{.+}}) +// CHECK-LABEL: define {{.*i32}} @{{.*}}templ1{{.*}}(float {{.+}}, float* {{.+}}) // CHECK: store i64 0, i64* [[T1_OMP_IV:[^,]+]] // ... // CHECK: [[IV:%.+]] = load i64, i64* [[T1_OMP_IV]]{{.*}}!llvm.access.group @@ -619,7 +619,7 @@ void widened(float *a, float *b, float *c, float *d) { // CHECK: ret void } -// CHECK-LABEL: define {{.*void}} @{{.*}}linear{{.*}}(float* noundef {{.+}}) +// CHECK-LABEL: define {{.*void}} @{{.*}}linear{{.*}}(float* {{.+}}) void linear(float *a) { // CHECK: [[VAL_ADDR:%.+]] = alloca i64, // CHECK: [[K_ADDR:%.+]] = alloca i64*, @@ -805,7 +805,7 @@ void parallel_simd(float *a) { #pragma omp parallel #pragma omp simd // TERM_DEBUG-NOT: __kmpc_global_thread_num - // TERM_DEBUG: invoke noundef i32 {{.*}}bar{{.*}}() + // TERM_DEBUG: invoke i32 {{.*}}bar{{.*}}() // TERM_DEBUG: unwind label %[[TERM_LPAD:[^,]+]], // TERM_DEBUG-NOT: __kmpc_global_thread_num // TERM_DEBUG: [[TERM_LPAD]] diff --git a/clang/test/OpenMP/single_codegen.cpp b/clang/test/OpenMP/single_codegen.cpp index 21c61aa6aca142cd1a6e125847cc03c23ac177d5..4f7777cad610577ce8df7a532c644c6060e16a84 100644 --- a/clang/test/OpenMP/single_codegen.cpp +++ b/clang/test/OpenMP/single_codegen.cpp @@ -144,45 +144,45 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %class.TestClass* -// CHECK1-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* noundef [[TMP2]]) +// CHECK1-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK1-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: ret i8* [[TMP3]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev -// CHECK1-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK1-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %class.TestClass* -// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[TMP2]]) #[[ATTR3:[0-9]+]] +// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK1-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK1-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* noundef [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // @@ -195,7 +195,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 @@ -208,7 +208,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] -// CHECK1-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1 @@ -229,7 +229,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -243,7 +243,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -254,7 +254,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -272,7 +272,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* noundef @tc) +// CHECK1-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) @tc) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%class.TestClass*)* @_ZN9TestClassD1Ev to void (i8*)*), i8* bitcast (%class.TestClass* @tc to i8*), i8* @__dso_handle) #[[ATTR3]] // CHECK1-NEXT: ret void // @@ -285,7 +285,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] -// CHECK1-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1 @@ -306,7 +306,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -320,7 +320,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -328,7 +328,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -336,7 +336,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev -// CHECK1-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK1-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 @@ -347,7 +347,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK1-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK1-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 @@ -378,8 +378,8 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK1-NEXT: store %class.TestClass* @tc, %class.TestClass** [[C]], align 8 -// CHECK1-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* noundef [[SST]]) -// CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)) +// CHECK1-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[SST]]) +// CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)) // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 // CHECK1-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] @@ -448,17 +448,17 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev -// CHECK1-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -466,7 +466,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK1-NEXT: ret void // // @@ -478,7 +478,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -500,14 +500,14 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP5]], i64 0, i64 1 // CHECK1-NEXT: [[TMP15:%.*]] = load i8*, i8** [[TMP14]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP15]] to %class.TestClass* -// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* noundef [[TMP13]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[TMP16]]) +// CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP13]], %class.TestClass* nonnull align 4 dereferenceable(4) [[TMP16]]) // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP3]], i64 0, i64 2 // CHECK1-NEXT: [[TMP18:%.*]] = load i8*, i8** [[TMP17]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8* [[TMP18]] to %class.TestClass* // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP5]], i64 0, i64 2 // CHECK1-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8* [[TMP21]] to %class.TestClass* -// CHECK1-NEXT: [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* noundef [[TMP19]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[TMP22]]) +// CHECK1-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP19]], %class.TestClass* nonnull align 4 dereferenceable(4) [[TMP22]]) // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP3]], i64 0, i64 3 // CHECK1-NEXT: [[TMP24:%.*]] = load i8*, i8** [[TMP23]], align 8 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP5]], i64 0, i64 3 @@ -525,7 +525,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP32]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP29]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %class.TestClass* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[CLASS_TESTCLASS]], %class.TestClass* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[CLASS_TESTCLASS]], %class.TestClass* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %class.TestClass* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP33]] @@ -535,7 +535,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassaSERKS_ -// CHECK1-SAME: (%class.TestClass* noundef [[THIS:%.*]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR10:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %class.TestClass* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR10:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %class.TestClass*, align 8 @@ -546,7 +546,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev -// CHECK1-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK1-NEXT: [[A2:%.*]] = alloca double*, align 8 @@ -567,7 +567,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR12:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR12:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -601,7 +601,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP1]], align 8 // CHECK1-NEXT: store double* [[TMP8]], double** [[TMP7]], align 8 -// CHECK1-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) @@ -632,7 +632,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv -// CHECK1-SAME: (%class.anon* noundef [[THIS:%.*]]) #[[ATTR4]] align 2 { +// CHECK1-SAME: (%class.anon* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon*, align 8 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 @@ -646,12 +646,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 1 // CHECK1-NEXT: [[TMP5:%.*]] = load double*, double** [[TMP4]], align 8 // CHECK1-NEXT: store double* [[TMP5]], double** [[TMP3]], align 8 -// CHECK1-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.0* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.5 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -673,7 +673,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv -// CHECK1-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR10]] align 2 { +// CHECK1-SAME: (%class.anon.0* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR10]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -697,7 +697,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR12]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR12]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -742,7 +742,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.7 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -764,7 +764,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -816,7 +816,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -866,7 +866,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[_TMP5]], align 8 // CHECK1-NEXT: store i32* [[TMP12]], i32** [[TMP11]], align 8 -// CHECK1-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.1* noundef [[REF_TMP]]) +// CHECK1-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.1* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) @@ -904,7 +904,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK1-SAME: (%class.anon.1* noundef [[THIS:%.*]]) #[[ATTR10]] align 2 { +// CHECK1-SAME: (%class.anon.1* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR10]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -952,7 +952,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.9 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -990,7 +990,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR12]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR12]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1060,7 +1060,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.11 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1105,7 +1105,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1155,28 +1155,28 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* noundef @tc) +// CHECK2-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) @tc) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%class.TestClass*)* @_ZN9TestClassD1Ev to void (i8*)*), i8* bitcast (%class.TestClass* @tc to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev -// CHECK2-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK2-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK2-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK2-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* noundef [[THIS1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // @@ -1188,7 +1188,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] -// CHECK2-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1 @@ -1209,7 +1209,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1223,7 +1223,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1231,7 +1231,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1239,25 +1239,25 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %class.TestClass* -// CHECK2-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* noundef [[TMP2]]) +// CHECK2-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK2-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: ret i8* [[TMP3]] // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %class.TestClass* -// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[TMP2]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // @@ -1270,7 +1270,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 @@ -1283,7 +1283,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] -// CHECK2-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1 @@ -1304,7 +1304,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1318,7 +1318,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..3 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1329,7 +1329,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1367,8 +1367,8 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK2-NEXT: store %class.TestClass* @tc, %class.TestClass** [[C]], align 8 -// CHECK2-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* noundef [[SST]]) -// CHECK2-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)) +// CHECK2-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[SST]]) +// CHECK2-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)) // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK2-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 // CHECK2-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] @@ -1437,17 +1437,17 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev -// CHECK2-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK2-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -1455,7 +1455,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK2-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK2-NEXT: ret void // // @@ -1467,7 +1467,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1489,14 +1489,14 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP5]], i64 0, i64 1 // CHECK2-NEXT: [[TMP15:%.*]] = load i8*, i8** [[TMP14]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP15]] to %class.TestClass* -// CHECK2-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* noundef [[TMP13]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[TMP16]]) +// CHECK2-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP13]], %class.TestClass* nonnull align 4 dereferenceable(4) [[TMP16]]) // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP3]], i64 0, i64 2 // CHECK2-NEXT: [[TMP18:%.*]] = load i8*, i8** [[TMP17]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8* [[TMP18]] to %class.TestClass* // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP5]], i64 0, i64 2 // CHECK2-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8* [[TMP21]] to %class.TestClass* -// CHECK2-NEXT: [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* noundef [[TMP19]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[TMP22]]) +// CHECK2-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP19]], %class.TestClass* nonnull align 4 dereferenceable(4) [[TMP22]]) // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP3]], i64 0, i64 3 // CHECK2-NEXT: [[TMP24:%.*]] = load i8*, i8** [[TMP23]], align 8 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP5]], i64 0, i64 3 @@ -1514,7 +1514,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP32]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP29]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %class.TestClass* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[CLASS_TESTCLASS]], %class.TestClass* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[CLASS_TESTCLASS]], %class.TestClass* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %class.TestClass* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP33]] @@ -1524,7 +1524,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN9TestClassaSERKS_ -// CHECK2-SAME: (%class.TestClass* noundef [[THIS:%.*]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR10:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %class.TestClass* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR10:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %class.TestClass*, align 8 @@ -1542,7 +1542,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR12:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR12:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1580,7 +1580,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev -// CHECK2-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK2-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 @@ -1591,7 +1591,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK2-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK2-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 @@ -1600,7 +1600,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -1652,7 +1652,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1702,7 +1702,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[_TMP5]], align 8 // CHECK2-NEXT: store i32* [[TMP12]], i32** [[TMP11]], align 8 -// CHECK2-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) @@ -1740,7 +1740,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK2-SAME: (%class.anon* noundef [[THIS:%.*]]) #[[ATTR10]] align 2 { +// CHECK2-SAME: (%class.anon* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR10]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon*, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -1788,7 +1788,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.6 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1826,7 +1826,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR12]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR12]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1896,7 +1896,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.8 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1934,7 +1934,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev -// CHECK2-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK2-NEXT: [[A2:%.*]] = alloca double*, align 8 @@ -1955,7 +1955,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1989,7 +1989,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP1]], align 8 // CHECK2-NEXT: store double* [[TMP8]], double** [[TMP7]], align 8 -// CHECK2-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon.0* noundef [[REF_TMP]]) +// CHECK2-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) @@ -2020,7 +2020,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv -// CHECK2-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR4]] align 2 { +// CHECK2-SAME: (%class.anon.0* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 @@ -2034,12 +2034,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 // CHECK2-NEXT: [[TMP5:%.*]] = load double*, double** [[TMP4]], align 8 // CHECK2-NEXT: store double* [[TMP5]], double** [[TMP3]], align 8 -// CHECK2-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.1* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.10 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2061,7 +2061,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv -// CHECK2-SAME: (%class.anon.1* noundef [[THIS:%.*]]) #[[ATTR10]] align 2 { +// CHECK2-SAME: (%class.anon.1* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR10]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -2085,7 +2085,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR12]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR12]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2130,7 +2130,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.12 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2162,45 +2162,45 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %class.TestClass* -// CHECK3-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* noundef [[TMP2]]) +// CHECK3-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK3-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK3-NEXT: ret i8* [[TMP3]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev -// CHECK3-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK3-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %class.TestClass* -// CHECK3-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[TMP2]]) #[[ATTR3:[0-9]+]] +// CHECK3-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR3:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK3-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK3-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* noundef [[THIS1]]) #[[ATTR3]] +// CHECK3-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK3-NEXT: ret void // // @@ -2213,7 +2213,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 @@ -2226,7 +2226,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] -// CHECK3-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]] // CHECK3: invoke.cont: // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1 @@ -2247,7 +2247,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK3-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -2261,7 +2261,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2272,7 +2272,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK3-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -2290,7 +2290,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* noundef @tc) +// CHECK3-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) @tc) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%class.TestClass*)* @_ZN9TestClassD1Ev to void (i8*)*), i8* bitcast (%class.TestClass* @tc to i8*), i8* @__dso_handle) #[[ATTR3]] // CHECK3-NEXT: ret void // @@ -2303,7 +2303,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] -// CHECK3-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]] // CHECK3: invoke.cont: // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1 @@ -2324,7 +2324,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK3-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -2338,7 +2338,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2346,7 +2346,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK3-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -2354,7 +2354,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev -// CHECK3-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK3-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK3-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 @@ -2365,7 +2365,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK3-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK3-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK3-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 @@ -2396,8 +2396,8 @@ void array_func(int n, int a[n], St s[2]) { // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK3-NEXT: store %class.TestClass* @tc, %class.TestClass** [[C]], align 8 -// CHECK3-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* noundef [[SST]]) -// CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)) +// CHECK3-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[SST]]) +// CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)) // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK3-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 // CHECK3-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] @@ -2466,17 +2466,17 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev -// CHECK3-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK3-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -2484,7 +2484,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK3-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK3-NEXT: ret void // // @@ -2496,7 +2496,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2518,14 +2518,14 @@ void array_func(int n, int a[n], St s[2]) { // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP5]], i64 0, i64 1 // CHECK3-NEXT: [[TMP15:%.*]] = load i8*, i8** [[TMP14]], align 8 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP15]] to %class.TestClass* -// CHECK3-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* noundef [[TMP13]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[TMP16]]) +// CHECK3-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP13]], %class.TestClass* nonnull align 4 dereferenceable(4) [[TMP16]]) // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP3]], i64 0, i64 2 // CHECK3-NEXT: [[TMP18:%.*]] = load i8*, i8** [[TMP17]], align 8 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8* [[TMP18]] to %class.TestClass* // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP5]], i64 0, i64 2 // CHECK3-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8* [[TMP21]] to %class.TestClass* -// CHECK3-NEXT: [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* noundef [[TMP19]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[TMP22]]) +// CHECK3-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP19]], %class.TestClass* nonnull align 4 dereferenceable(4) [[TMP22]]) // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP3]], i64 0, i64 3 // CHECK3-NEXT: [[TMP24:%.*]] = load i8*, i8** [[TMP23]], align 8 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP5]], i64 0, i64 3 @@ -2543,7 +2543,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP32]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP29]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: [[CALL3:%.*]] = call noundef nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK3-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %class.TestClass* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[CLASS_TESTCLASS]], %class.TestClass* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[CLASS_TESTCLASS]], %class.TestClass* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %class.TestClass* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP33]] @@ -2553,7 +2553,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN9TestClassaSERKS_ -// CHECK3-SAME: (%class.TestClass* noundef [[THIS:%.*]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR10:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %class.TestClass* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR10:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %class.TestClass*, align 8 @@ -2564,7 +2564,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev -// CHECK3-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK3-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK3-NEXT: [[A2:%.*]] = alloca double*, align 8 @@ -2585,7 +2585,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR12:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR12:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2619,7 +2619,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP1]], align 8 // CHECK3-NEXT: store double* [[TMP8]], double** [[TMP7]], align 8 -// CHECK3-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK3: invoke.cont: // CHECK3-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) @@ -2650,7 +2650,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv -// CHECK3-SAME: (%class.anon* noundef [[THIS:%.*]]) #[[ATTR4]] align 2 { +// CHECK3-SAME: (%class.anon* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon*, align 8 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 @@ -2664,12 +2664,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 1 // CHECK3-NEXT: [[TMP5:%.*]] = load double*, double** [[TMP4]], align 8 // CHECK3-NEXT: store double* [[TMP5]], double** [[TMP3]], align 8 -// CHECK3-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.5 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2691,7 +2691,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv -// CHECK3-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR10]] align 2 { +// CHECK3-SAME: (%class.anon.0* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR10]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -2715,7 +2715,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR12]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR12]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2760,7 +2760,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.7 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2782,7 +2782,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -2834,7 +2834,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2884,7 +2884,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: [[TMP12:%.*]] = load i32*, i32** [[_TMP5]], align 8 // CHECK3-NEXT: store i32* [[TMP12]], i32** [[TMP11]], align 8 -// CHECK3-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.1* noundef [[REF_TMP]]) +// CHECK3-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.1* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK3: invoke.cont: // CHECK3-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) @@ -2922,7 +2922,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK3-SAME: (%class.anon.1* noundef [[THIS:%.*]]) #[[ATTR10]] align 2 { +// CHECK3-SAME: (%class.anon.1* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR10]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -2970,7 +2970,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.9 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3008,7 +3008,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR12]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR12]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3078,7 +3078,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.11 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3123,7 +3123,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3175,51 +3175,51 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // CHECK4-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%class.TestClass* @tc to i8*), i8* (i8*)* @.__kmpc_global_ctor_., i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_.) -// CHECK4-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* noundef @tc) +// CHECK4-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) @tc) // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%class.TestClass*)* @_ZN9TestClassD1Ev to void (i8*)*), i8* bitcast (%class.TestClass* @tc to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %class.TestClass* -// CHECK4-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* noundef [[TMP2]]) +// CHECK4-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK4-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK4-NEXT: ret i8* [[TMP3]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev -// CHECK4-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK4-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %class.TestClass* -// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[TMP2]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR3]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK4-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK4-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* noundef [[THIS1]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK4-NEXT: ret void // // @@ -3233,7 +3233,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] -// CHECK4-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]] // CHECK4: invoke.cont: // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1 @@ -3254,7 +3254,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -3268,7 +3268,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..2 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 @@ -3281,7 +3281,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] -// CHECK4-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]] // CHECK4: invoke.cont: // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1 @@ -3302,7 +3302,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -3316,7 +3316,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..3 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3327,7 +3327,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -3335,7 +3335,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3343,7 +3343,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -3373,8 +3373,8 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: store %class.TestClass* @tc, %class.TestClass** [[C]], align 8 -// CHECK4-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* noundef [[SST]]) -// CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)) +// CHECK4-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[SST]]) +// CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)) // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK4-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 // CHECK4-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] @@ -3443,17 +3443,17 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev -// CHECK4-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK4-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -3461,7 +3461,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK4-NEXT: ret void // // @@ -3473,7 +3473,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3495,14 +3495,14 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP5]], i64 0, i64 1 // CHECK4-NEXT: [[TMP15:%.*]] = load i8*, i8** [[TMP14]], align 8 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP15]] to %class.TestClass* -// CHECK4-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* noundef [[TMP13]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[TMP16]]) +// CHECK4-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP13]], %class.TestClass* nonnull align 4 dereferenceable(4) [[TMP16]]) // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP3]], i64 0, i64 2 // CHECK4-NEXT: [[TMP18:%.*]] = load i8*, i8** [[TMP17]], align 8 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8* [[TMP18]] to %class.TestClass* // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP5]], i64 0, i64 2 // CHECK4-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8* [[TMP21]] to %class.TestClass* -// CHECK4-NEXT: [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* noundef [[TMP19]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[TMP22]]) +// CHECK4-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP19]], %class.TestClass* nonnull align 4 dereferenceable(4) [[TMP22]]) // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP3]], i64 0, i64 3 // CHECK4-NEXT: [[TMP24:%.*]] = load i8*, i8** [[TMP23]], align 8 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP5]], i64 0, i64 3 @@ -3520,7 +3520,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP32]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP29]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: [[CALL3:%.*]] = call noundef nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) +// CHECK4-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %class.TestClass* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[CLASS_TESTCLASS]], %class.TestClass* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[CLASS_TESTCLASS]], %class.TestClass* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %class.TestClass* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP33]] @@ -3530,7 +3530,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassaSERKS_ -// CHECK4-SAME: (%class.TestClass* noundef [[THIS:%.*]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR10:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %class.TestClass* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR10:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %class.TestClass*, align 8 @@ -3548,7 +3548,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR12:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR12:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3586,7 +3586,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev -// CHECK4-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK4-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK4-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 @@ -3597,7 +3597,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK4-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK4-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK4-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 @@ -3606,7 +3606,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -3658,7 +3658,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3708,7 +3708,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: [[TMP12:%.*]] = load i32*, i32** [[_TMP5]], align 8 // CHECK4-NEXT: store i32* [[TMP12]], i32** [[TMP11]], align 8 -// CHECK4-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK4: invoke.cont: // CHECK4-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) @@ -3746,7 +3746,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK4-SAME: (%class.anon* noundef [[THIS:%.*]]) #[[ATTR10]] align 2 { +// CHECK4-SAME: (%class.anon* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR10]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon*, align 8 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -3794,7 +3794,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.5 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3832,7 +3832,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR12]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR12]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3902,7 +3902,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.7 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3940,7 +3940,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev -// CHECK4-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK4-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK4-NEXT: [[A2:%.*]] = alloca double*, align 8 @@ -3961,7 +3961,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3995,7 +3995,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP1]], align 8 // CHECK4-NEXT: store double* [[TMP8]], double** [[TMP7]], align 8 -// CHECK4-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon.0* noundef [[REF_TMP]]) +// CHECK4-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK4: invoke.cont: // CHECK4-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) @@ -4026,7 +4026,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv -// CHECK4-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR4]] align 2 { +// CHECK4-SAME: (%class.anon.0* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 @@ -4040,12 +4040,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 // CHECK4-NEXT: [[TMP5:%.*]] = load double*, double** [[TMP4]], align 8 // CHECK4-NEXT: store double* [[TMP5]], double** [[TMP3]], align 8 -// CHECK4-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.1* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.9 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4067,7 +4067,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv -// CHECK4-SAME: (%class.anon.1* noundef [[THIS:%.*]]) #[[ATTR10]] align 2 { +// CHECK4-SAME: (%class.anon.1* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR10]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -4091,7 +4091,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR12]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR12]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4136,7 +4136,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.11 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4166,135 +4166,135 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG7:![0-9]+]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG6:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG10:![0-9]+]] -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %class.TestClass*, !dbg [[DBG10]] -// CHECK5-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* noundef [[TMP2]]), !dbg [[DBG11:![0-9]+]] -// CHECK5-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG10]] -// CHECK5-NEXT: ret i8* [[TMP3]], !dbg [[DBG10]] +// CHECK5-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG9:![0-9]+]] +// CHECK5-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %class.TestClass*, !dbg [[DBG9]] +// CHECK5-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP2]]), !dbg [[DBG10:![0-9]+]] +// CHECK5-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG9]] +// CHECK5-NEXT: ret i8* [[TMP3]], !dbg [[DBG9]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassC1Ev -// CHECK5-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 !dbg [[DBG12:![0-9]+]] { +// CHECK5-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 !dbg [[DBG11:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK5-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* noundef [[THIS1]]), !dbg [[DBG13:![0-9]+]] -// CHECK5-NEXT: ret void, !dbg [[DBG14:![0-9]+]] +// CHECK5-NEXT: call void @_ZN9TestClassC2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]), !dbg [[DBG12:![0-9]+]] +// CHECK5-NEXT: ret void, !dbg [[DBG13:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG15:![0-9]+]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG14:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG16:![0-9]+]] -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %class.TestClass*, !dbg [[DBG16]] -// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[TMP2]]) #[[ATTR3:[0-9]+]], !dbg [[DBG16]] -// CHECK5-NEXT: ret void, !dbg [[DBG17:![0-9]+]] +// CHECK5-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG15:![0-9]+]] +// CHECK5-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %class.TestClass*, !dbg [[DBG15]] +// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR3:[0-9]+]], !dbg [[DBG15]] +// CHECK5-NEXT: ret void, !dbg [[DBG16:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK5-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 !dbg [[DBG18:![0-9]+]] { +// CHECK5-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 !dbg [[DBG17:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK5-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %class.TestClass*, %class.TestClass** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* noundef [[THIS1]]) #[[ATTR3]], !dbg [[DBG19:![0-9]+]] -// CHECK5-NEXT: ret void, !dbg [[DBG20:![0-9]+]] +// CHECK5-NEXT: call void @_ZN9TestClassD2Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG18:![0-9]+]] +// CHECK5-NEXT: ret void, !dbg [[DBG19:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_. -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG21:![0-9]+]] { +// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG20:![0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]), !dbg [[DBG22:![0-9]+]] -// CHECK5-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%class.TestClass* @tc to i8*), i8* (i8*)* @.__kmpc_global_ctor_., i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_.), !dbg [[DBG22]] -// CHECK5-NEXT: ret void, !dbg [[DBG22]] +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]), !dbg [[DBG21:![0-9]+]] +// CHECK5-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%class.TestClass* @tc to i8*), i8* (i8*)* @.__kmpc_global_ctor_., i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_.), !dbg [[DBG21]] +// CHECK5-NEXT: ret void, !dbg [[DBG21]] // // // CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG23:![0-9]+]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG22:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG24:![0-9]+]] -// CHECK5-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [2 x %class.TestClass]*, !dbg [[DBG24]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %class.TestClass], [2 x %class.TestClass]* [[TMP2]], i32 0, i32 0, !dbg [[DBG25:![0-9]+]] -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[ARRAY_BEGIN]], i64 2, !dbg [[DBG25]] -// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]], !dbg [[DBG25]] +// CHECK5-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG23:![0-9]+]] +// CHECK5-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [2 x %class.TestClass]*, !dbg [[DBG23]] +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %class.TestClass], [2 x %class.TestClass]* [[TMP2]], i32 0, i32 0, !dbg [[DBG24:![0-9]+]] +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[ARRAY_BEGIN]], i64 2, !dbg [[DBG24]] +// CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]], !dbg [[DBG24]] // CHECK5: arrayctor.loop: -// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ], !dbg [[DBG25]] -// CHECK5-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* noundef [[ARRAYCTOR_CUR]]) -// CHECK5-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]], !dbg [[DBG25]] +// CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ], !dbg [[DBG24]] +// CHECK5-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]], !dbg [[DBG24]] // CHECK5: invoke.cont: -// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1, !dbg [[DBG25]] -// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]], !dbg [[DBG25]] -// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]], !dbg [[DBG25]] +// CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1, !dbg [[DBG24]] +// CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]], !dbg [[DBG24]] +// CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]], !dbg [[DBG24]] // CHECK5: arrayctor.cont: -// CHECK5-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG24]] -// CHECK5-NEXT: ret i8* [[TMP3]], !dbg [[DBG24]] +// CHECK5-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG23]] +// CHECK5-NEXT: ret i8* [[TMP3]], !dbg [[DBG23]] // CHECK5: lpad: // CHECK5-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// CHECK5-NEXT: cleanup, !dbg [[DBG26:![0-9]+]] -// CHECK5-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0, !dbg [[DBG26]] -// CHECK5-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG26]] -// CHECK5-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1, !dbg [[DBG26]] -// CHECK5-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG26]] -// CHECK5-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq %class.TestClass* [[ARRAY_BEGIN]], [[ARRAYCTOR_CUR]], !dbg [[DBG25]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG25]] +// CHECK5-NEXT: cleanup, !dbg [[DBG25:![0-9]+]] +// CHECK5-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0, !dbg [[DBG25]] +// CHECK5-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG25]] +// CHECK5-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1, !dbg [[DBG25]] +// CHECK5-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG25]] +// CHECK5-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq %class.TestClass* [[ARRAY_BEGIN]], [[ARRAYCTOR_CUR]], !dbg [[DBG24]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG24]] // CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG25]] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG25]] -// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG25]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]], !dbg [[DBG25]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG25]] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG24]] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG24]] +// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG24]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]], !dbg [[DBG24]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG24]] // CHECK5: arraydestroy.done1: -// CHECK5-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG25]] +// CHECK5-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG24]] // CHECK5: eh.resume: -// CHECK5-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG25]] -// CHECK5-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG25]] -// CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0, !dbg [[DBG25]] -// CHECK5-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG25]] -// CHECK5-NEXT: resume { i8*, i32 } [[LPAD_VAL2]], !dbg [[DBG25]] +// CHECK5-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG24]] +// CHECK5-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG24]] +// CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0, !dbg [[DBG24]] +// CHECK5-NEXT: [[LPAD_VAL2:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG24]] +// CHECK5-NEXT: resume { i8*, i32 } [[LPAD_VAL2]], !dbg [[DBG24]] // // // CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG27:![0-9]+]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG26:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG28:![0-9]+]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = bitcast i8* [[TMP1]] to %class.TestClass*, !dbg [[DBG28]] -// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[ARRAY_BEGIN]], i64 2, !dbg [[DBG28]] -// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG28]] +// CHECK5-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG27:![0-9]+]] +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = bitcast i8* [[TMP1]] to %class.TestClass*, !dbg [[DBG27]] +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[ARRAY_BEGIN]], i64 2, !dbg [[DBG27]] +// CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG27]] // CHECK5: arraydestroy.body: -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG28]] -// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG28]] -// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG28]] -// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]], !dbg [[DBG28]] -// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG28]] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG27]] +// CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG27]] +// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG27]] +// CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]], !dbg [[DBG27]] +// CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG27]] // CHECK5: arraydestroy.done1: -// CHECK5-NEXT: ret void, !dbg [[DBG29:![0-9]+]] +// CHECK5-NEXT: ret void, !dbg [[DBG28:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_..3 -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG30:![0-9]+]] { +// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG29:![0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]), !dbg [[DBG31:![0-9]+]] -// CHECK5-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB3]], i8* bitcast ([2 x %class.TestClass]* @tc2 to i8*), i8* (i8*)* @.__kmpc_global_ctor_..1, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..2), !dbg [[DBG31]] -// CHECK5-NEXT: ret void, !dbg [[DBG31]] +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]), !dbg [[DBG30:![0-9]+]] +// CHECK5-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB3]], i8* bitcast ([2 x %class.TestClass]* @tc2 to i8*), i8* (i8*)* @.__kmpc_global_ctor_..1, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..2), !dbg [[DBG30]] +// CHECK5-NEXT: ret void, !dbg [[DBG30]] // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG32:![0-9]+]] { +// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG31:![0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* noundef @tc), !dbg [[DBG33:![0-9]+]] +// CHECK5-NEXT: call void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) @tc), !dbg [[DBG33:![0-9]+]] // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%class.TestClass*)* @_ZN9TestClassD1Ev to void (i8*)*), i8* bitcast (%class.TestClass* @tc to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG35:![0-9]+]] // CHECK5-NEXT: ret void, !dbg [[DBG33]] // @@ -4307,7 +4307,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]], !dbg [[DBG37:![0-9]+]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ], !dbg [[DBG37]] -// CHECK5-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: invoke void @_ZN9TestClassC1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: to label [[INVOKE_CONT]] unwind label [[LPAD:%.*]], !dbg [[DBG37]] // CHECK5: invoke.cont: // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], %class.TestClass* [[ARRAYCTOR_CUR]], i64 1, !dbg [[DBG37]] @@ -4328,7 +4328,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG37]] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG37]] -// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG37]] +// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG37]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), !dbg [[DBG37]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG37]] // CHECK5: arraydestroy.done1: @@ -4342,7 +4342,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG41:![0-9]+]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG41:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4350,7 +4350,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %class.TestClass* [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG42]] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], %class.TestClass* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG42]] -// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG42]] +// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(%class.TestClass* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG42]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %class.TestClass* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %class.TestClass], [2 x %class.TestClass]* @tc2, i32 0, i32 0), !dbg [[DBG42]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG42]] // CHECK5: arraydestroy.done1: @@ -4358,7 +4358,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassC2Ev -// CHECK5-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG43:![0-9]+]] { +// CHECK5-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG43:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK5-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 @@ -4369,7 +4369,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK5-SAME: (%class.TestClass* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG46:![0-9]+]] { +// CHECK5-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG46:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK5-NEXT: store %class.TestClass* [[THIS]], %class.TestClass** [[THIS_ADDR]], align 8 @@ -4400,8 +4400,8 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB5:[0-9]+]]) // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store %class.TestClass* @tc, %class.TestClass** [[C]], align 8, !dbg [[DBG52:![0-9]+]] -// CHECK5-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* noundef [[SST]]), !dbg [[DBG53:![0-9]+]] -// CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)), !dbg [[DBG54:![0-9]+]] +// CHECK5-NEXT: call void @_ZN3SSTIdEC1Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[SST]]), !dbg [[DBG53:![0-9]+]] +// CHECK5-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], %class.TestClass* @tc, i32 0, i32 0)), !dbg [[DBG54:![0-9]+]] // CHECK5-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB5]], i32 [[TMP0]]), !dbg [[DBG55:![0-9]+]] // CHECK5-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG55]] // CHECK5-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG55]] @@ -4470,17 +4470,17 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIdEC1Ev -// CHECK5-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG69:![0-9]+]] { +// CHECK5-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG69:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK5-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* noundef [[THIS1]]), !dbg [[DBG70:![0-9]+]] +// CHECK5-NEXT: call void @_ZN3SSTIdEC2Ev(%struct.SST* nonnull align 8 dereferenceable(8) [[THIS1]]), !dbg [[DBG70:![0-9]+]] // CHECK5-NEXT: ret void, !dbg [[DBG71:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG72:![0-9]+]] { +// CHECK5-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG72:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -4488,7 +4488,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8, !dbg [[DBG73:![0-9]+]] -// CHECK5-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]), !dbg [[DBG73]] +// CHECK5-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]), !dbg [[DBG73]] // CHECK5-NEXT: ret void, !dbg [[DBG74:![0-9]+]] // // @@ -4500,7 +4500,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] !dbg [[DBG75:![0-9]+]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] !dbg [[DBG75:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4522,14 +4522,14 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP5]], i64 0, i64 1, !dbg [[DBG76]] // CHECK5-NEXT: [[TMP15:%.*]] = load i8*, i8** [[TMP14]], align 8, !dbg [[DBG76]] // CHECK5-NEXT: [[TMP16:%.*]] = bitcast i8* [[TMP15]] to %class.TestClass*, !dbg [[DBG76]] -// CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* noundef [[TMP13]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[TMP16]]), !dbg [[DBG78:![0-9]+]] +// CHECK5-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP13]], %class.TestClass* nonnull align 4 dereferenceable(4) [[TMP16]]), !dbg [[DBG78:![0-9]+]] // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP3]], i64 0, i64 2, !dbg [[DBG76]] // CHECK5-NEXT: [[TMP18:%.*]] = load i8*, i8** [[TMP17]], align 8, !dbg [[DBG76]] // CHECK5-NEXT: [[TMP19:%.*]] = bitcast i8* [[TMP18]] to %class.TestClass*, !dbg [[DBG76]] // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP5]], i64 0, i64 2, !dbg [[DBG76]] // CHECK5-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8, !dbg [[DBG76]] // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8* [[TMP21]] to %class.TestClass*, !dbg [[DBG76]] -// CHECK5-NEXT: [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* noundef [[TMP19]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[TMP22]]), !dbg [[DBG79:![0-9]+]] +// CHECK5-NEXT: [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* nonnull align 4 dereferenceable(4) [[TMP19]], %class.TestClass* nonnull align 4 dereferenceable(4) [[TMP22]]), !dbg [[DBG79:![0-9]+]] // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP3]], i64 0, i64 3, !dbg [[DBG76]] // CHECK5-NEXT: [[TMP24:%.*]] = load i8*, i8** [[TMP23]], align 8, !dbg [[DBG76]] // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[TMP5]], i64 0, i64 3, !dbg [[DBG76]] @@ -4547,7 +4547,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5: omp.arraycpy.body: // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP32]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ], !dbg [[DBG76]] // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %class.TestClass* [ [[TMP29]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ], !dbg [[DBG76]] -// CHECK5-NEXT: [[CALL3:%.*]] = call noundef nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]), !dbg [[DBG80:![0-9]+]] +// CHECK5-NEXT: [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %class.TestClass* @_ZN9TestClassaSERKS_(%class.TestClass* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %class.TestClass* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]), !dbg [[DBG80:![0-9]+]] // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[CLASS_TESTCLASS]], %class.TestClass* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1, !dbg [[DBG76]] // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[CLASS_TESTCLASS]], %class.TestClass* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1, !dbg [[DBG76]] // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %class.TestClass* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP33]], !dbg [[DBG76]] @@ -4557,7 +4557,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassaSERKS_ -// CHECK5-SAME: (%class.TestClass* noundef [[THIS:%.*]], %class.TestClass* noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR10:[0-9]+]] align 2 !dbg [[DBG81:![0-9]+]] { +// CHECK5-SAME: (%class.TestClass* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %class.TestClass* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR10:[0-9]+]] align 2 !dbg [[DBG81:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %class.TestClass*, align 8 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca %class.TestClass*, align 8 @@ -4568,7 +4568,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev -// CHECK5-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG83:![0-9]+]] { +// CHECK5-SAME: (%struct.SST* nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG83:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK5-NEXT: [[A2:%.*]] = alloca double*, align 8 @@ -4589,7 +4589,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR12:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG89:![0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR12:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG89:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4623,7 +4623,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1, !dbg [[DBG93]] // CHECK5-NEXT: [[TMP8:%.*]] = load double*, double** [[_TMP1]], align 8, !dbg [[DBG94:![0-9]+]] // CHECK5-NEXT: store double* [[TMP8]], double** [[TMP7]], align 8, !dbg [[DBG93]] -// CHECK5-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG93]] // CHECK5: invoke.cont: // CHECK5-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB16]], i32 [[TMP3]]), !dbg [[DBG93]] @@ -4654,7 +4654,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv -// CHECK5-SAME: (%class.anon* noundef [[THIS:%.*]]) #[[ATTR4]] align 2 !dbg [[DBG98:![0-9]+]] { +// CHECK5-SAME: (%class.anon* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] align 2 !dbg [[DBG98:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon*, align 8 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 @@ -4668,12 +4668,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[THIS1]], i32 0, i32 1, !dbg [[DBG100:![0-9]+]] // CHECK5-NEXT: [[TMP5:%.*]] = load double*, double** [[TMP4]], align 8, !dbg [[DBG100]] // CHECK5-NEXT: store double* [[TMP5]], double** [[TMP3]], align 8, !dbg [[DBG99]] -// CHECK5-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.0* noundef [[REF_TMP]]), !dbg [[DBG99]] +// CHECK5-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]), !dbg [[DBG99]] // CHECK5-NEXT: ret void, !dbg [[DBG101:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.5 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] !dbg [[DBG102:![0-9]+]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] !dbg [[DBG102:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4695,7 +4695,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv -// CHECK5-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR10]] align 2 !dbg [[DBG107:![0-9]+]] { +// CHECK5-SAME: (%class.anon.0* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR10]] align 2 !dbg [[DBG107:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -4719,7 +4719,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR12]] !dbg [[DBG113:![0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR12]] !dbg [[DBG113:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4764,7 +4764,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.7 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] !dbg [[DBG120:![0-9]+]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] !dbg [[DBG120:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4786,7 +4786,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG123:![0-9]+]] { +// CHECK5-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG123:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -4838,7 +4838,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG135:![0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG135:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4888,7 +4888,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 3, !dbg [[DBG140]] // CHECK5-NEXT: [[TMP12:%.*]] = load i32*, i32** [[_TMP5]], align 8, !dbg [[DBG141]] // CHECK5-NEXT: store i32* [[TMP12]], i32** [[TMP11]], align 8, !dbg [[DBG140]] -// CHECK5-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.1* noundef [[REF_TMP]]) +// CHECK5-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.1* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG140]] // CHECK5: invoke.cont: // CHECK5-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB24]], i32 [[TMP4]]), !dbg [[DBG140]] @@ -4926,7 +4926,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK5-SAME: (%class.anon.1* noundef [[THIS:%.*]]) #[[ATTR10]] align 2 !dbg [[DBG146:![0-9]+]] { +// CHECK5-SAME: (%class.anon.1* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR10]] align 2 !dbg [[DBG146:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.1*, align 8 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -4974,7 +4974,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.9 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] !dbg [[DBG158:![0-9]+]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] !dbg [[DBG158:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -5012,7 +5012,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR12]] !dbg [[DBG163:![0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR12]] !dbg [[DBG163:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5082,7 +5082,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.11 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR9]] !dbg [[DBG174:![0-9]+]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR9]] !dbg [[DBG174:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -5127,7 +5127,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG182:![0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR12]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG182:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5175,7 +5175,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK6-LABEL: define {{[^@]+}}@_Z10array_funciPiP2St -// CHECK6-SAME: (i32 noundef [[N:%.*]], i32* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-SAME: (i32 [[N:%.*]], i32* [[A:%.*]], %struct.St* [[S:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -5210,7 +5210,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -5238,3 +5238,4 @@ void array_func(int n, int a[n], St s[2]) { // CHECK6-NEXT: store %struct.St* [[TMP19]], %struct.St** [[TMP15]], align 8 // CHECK6-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/single_firstprivate_codegen.cpp b/clang/test/OpenMP/single_firstprivate_codegen.cpp index 90aa7029a2449977c26dbcf0168a74fecd99b4a7..c159d6f8f2d495d75503ea1b8a57c45b64c1fb5e 100644 --- a/clang/test/OpenMP/single_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/single_firstprivate_codegen.cpp @@ -136,33 +136,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -175,7 +175,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -186,14 +186,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -201,12 +201,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -214,7 +214,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -222,7 +222,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -241,7 +241,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -274,17 +274,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done1: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP2]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR]], %struct.S* noundef nonnull align 4 dereferenceable(4) @var, %struct.St* noundef [[AGG_TMP2]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP2]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], %struct.S* nonnull align 4 dereferenceable(4) @var, %struct.St* [[AGG_TMP2]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[SIVAR]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[T_VAR]], align 4 @@ -295,36 +295,36 @@ int main() { // CHECK1-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) // CHECK1-NEXT: store i32 41, i32* [[SIVAR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE1]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done5: // CHECK1-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -332,17 +332,17 @@ int main() { // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -355,35 +355,35 @@ int main() { // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -396,7 +396,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -416,7 +416,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -425,17 +425,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -443,12 +443,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -491,17 +491,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP11]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR1]], align 4 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4 @@ -509,14 +509,14 @@ int main() { // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* // CHECK1-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done9: @@ -528,7 +528,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -536,22 +536,22 @@ int main() { // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -563,7 +563,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -579,7 +579,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -598,7 +598,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -618,33 +618,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -657,7 +657,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -668,14 +668,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -683,12 +683,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -696,7 +696,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -704,7 +704,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -723,7 +723,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -756,17 +756,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done1: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP2]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR]], %struct.S* noundef nonnull align 4 dereferenceable(4) @var, %struct.St* noundef [[AGG_TMP2]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP2]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], %struct.S* nonnull align 4 dereferenceable(4) @var, %struct.St* [[AGG_TMP2]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[SIVAR]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[T_VAR]], align 4 @@ -777,36 +777,36 @@ int main() { // CHECK2-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) // CHECK2-NEXT: store i32 41, i32* [[SIVAR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE1]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done5: // CHECK2-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) // CHECK2-NEXT: br label [[OMP_IF_END]] // CHECK2: omp_if.end: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -814,17 +814,17 @@ int main() { // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // @@ -837,35 +837,35 @@ int main() { // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -878,7 +878,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -898,7 +898,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -907,17 +907,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -925,12 +925,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -973,17 +973,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP11]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR1]], align 4 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 // CHECK2-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4 @@ -991,14 +991,14 @@ int main() { // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* // CHECK2-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done9: @@ -1010,7 +1010,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1018,22 +1018,22 @@ int main() { // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1045,7 +1045,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1061,7 +1061,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1080,7 +1080,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1100,33 +1100,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1139,7 +1139,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1150,14 +1150,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1165,12 +1165,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1178,7 +1178,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1186,7 +1186,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1205,7 +1205,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -1218,12 +1218,12 @@ int main() { // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1251,7 +1251,7 @@ int main() { // CHECK3-NEXT: store i32* [[G]], i32** [[TMP7]], align 8 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: store i32* [[SIVAR1]], i32** [[TMP8]], align 8 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: @@ -1271,33 +1271,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1310,7 +1310,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1321,14 +1321,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1336,12 +1336,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1349,7 +1349,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -1357,7 +1357,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1376,7 +1376,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -1406,12 +1406,12 @@ int main() { // CHECK4-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP5]](i8* noundef [[TMP3]]) +// CHECK4-NEXT: call void [[TMP5]](i8* [[TMP3]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 @@ -1423,7 +1423,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1469,7 +1469,7 @@ int main() { // CHECK4-NEXT: [[TMP11:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP12:%.*]] = load i8*, i8** [[TMP10]], align 8 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8* [[TMP12]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP13]](i8* noundef [[TMP11]]) +// CHECK4-NEXT: call void [[TMP13]](i8* [[TMP11]]) // CHECK4-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) // CHECK4-NEXT: br label [[OMP_IF_END]] // CHECK4: omp_if.end: @@ -1478,7 +1478,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@var_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>*, align 8 @@ -1500,3 +1500,4 @@ int main() { // CHECK4-NEXT: call void @__cxx_global_var_init.2() // CHECK4-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/single_private_codegen.cpp b/clang/test/OpenMP/single_private_codegen.cpp index bcaa75d6276749bcac9a2b587cd08ef1fa0609ad..9f9697270e5e6e255a059a9541423cf0529149f2 100644 --- a/clang/test/OpenMP/single_private_codegen.cpp +++ b/clang/test/OpenMP/single_private_codegen.cpp @@ -101,46 +101,46 @@ int main() { // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -148,12 +148,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -175,12 +175,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 @@ -189,14 +189,14 @@ int main() { // CHECK1-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[VAR]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) // CHECK1-NEXT: store i32 303, i32* [[SIVAR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -208,12 +208,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // @@ -226,35 +226,35 @@ int main() { // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -265,7 +265,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -279,7 +279,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -288,17 +288,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -306,12 +306,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -332,12 +332,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 @@ -345,14 +345,14 @@ int main() { // CHECK1-NEXT: [[TMP5:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* // CHECK1-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -364,17 +364,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -385,7 +385,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -399,7 +399,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -417,46 +417,46 @@ int main() { // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -464,12 +464,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -491,12 +491,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 @@ -505,14 +505,14 @@ int main() { // CHECK2-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[VAR]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) // CHECK2-NEXT: store i32 303, i32* [[SIVAR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done3: @@ -524,12 +524,12 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK2-NEXT: ret void // // @@ -542,35 +542,35 @@ int main() { // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP2]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -581,7 +581,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -595,7 +595,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -604,17 +604,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -622,12 +622,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -648,12 +648,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4 @@ -661,14 +661,14 @@ int main() { // CHECK2-NEXT: [[TMP5:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* // CHECK2-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done3: @@ -680,17 +680,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -701,7 +701,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -715,7 +715,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -729,12 +729,12 @@ int main() { // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -755,7 +755,7 @@ int main() { // CHECK3-NEXT: store double* [[G]], double** [[TMP4]], align 8 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[TMP5]], align 8 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: @@ -770,12 +770,12 @@ int main() { // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// CHECK4-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 @@ -787,7 +787,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -826,7 +826,7 @@ int main() { // CHECK4-NEXT: [[TMP8:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* // CHECK4-NEXT: [[TMP9:%.*]] = load i8*, i8** [[TMP7]], align 8 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to void (i8*)* -// CHECK4-NEXT: call void [[TMP10]](i8* noundef [[TMP8]]) +// CHECK4-NEXT: call void [[TMP10]](i8* [[TMP8]]) // CHECK4-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) // CHECK4-NEXT: br label [[OMP_IF_END]] // CHECK4: omp_if.end: @@ -835,7 +835,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_block_invoke -// CHECK4-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8 @@ -848,3 +848,4 @@ int main() { // CHECK4-NEXT: store i32 203, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 // CHECK4-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_codegen.cpp b/clang/test/OpenMP/target_codegen.cpp index 0d7526bfaea7a1c71177dd69cf60820509bc8258..f6eecb82dca5e7204e01492871f2d044b217ece0 100644 --- a/clang/test/OpenMP/target_codegen.cpp +++ b/clang/test/OpenMP/target_codegen.cpp @@ -392,8 +392,8 @@ int foo(int n) { // CHECK: define internal void [[HVT0]]() -// CHECK: define internal void [[HVT0_:@.+]](i[[SZ]]* noundef {{%[^,]+}}, i[[SZ]] noundef {{%[^,]+}}) -// CHECK: define internal {{.*}}i32 [[OMP_TASK_ENTRY]](i32 {{.*}}%0, [[KMP_TASK_T_WITH_PRIVATES]]* noalias noundef %1) +// CHECK: define internal void [[HVT0_:@.+]](i[[SZ]]* {{%[^,]+}}, i[[SZ]] {{%[^,]+}}) +// CHECK: define internal {{.*}}i32 [[OMP_TASK_ENTRY]](i32 {{.*}}%0, [[KMP_TASK_T_WITH_PRIVATES]]* noalias %1) // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target_nowait_mapper(%struct.ident_t* @{{.+}}, i64 [[DEVICE:%.+]], i8* @{{[^,]+}}, i32 2, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i64* [[SIZE:%.+]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* [[MAPT]], i32 0, i32 0), i8** null, i8** null, i32 0, i8* null, i32 0, i8* null) // CHECK-DAG: [[DEVICE]] = sext i32 [[DEV:%.+]] to i64 // CHECK-DAG: [[DEV]] = load i32, i32* [[DEVADDR:%.+]], align @@ -421,7 +421,7 @@ int foo(int n) { // CHECK-NEXT: br label %[[END]] // CHECK: [[END]] -// CHECK: define internal void [[HVT1]](i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT1]](i[[SZ]] %{{.+}}) // Create stack storage and store argument in there. // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align @@ -429,7 +429,7 @@ int foo(int n) { // CHECK-64: load i32, i32* [[AA_CADDR]], align // CHECK-32: load i32, i32* [[AA_ADDR]], align -// CHECK: define internal void [[HVT2]](i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT2]](i[[SZ]] %{{.+}}) // Create stack storage and store argument in there. // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align @@ -740,7 +740,7 @@ int bar(int n){ // CHECK: [[IFEND]] -// OMP45: define internal void @__omp_offloading_{{.+}}_{{.+}}bar{{.+}}_l{{[0-9]+}}(i[[SZ]] noundef %{{.+}}) +// OMP45: define internal void @__omp_offloading_{{.+}}_{{.+}}bar{{.+}}_l{{[0-9]+}}(i[[SZ]] %{{.+}}) // OMP45: define {{.*}}@{{.*}}zee{{.*}} @@ -839,7 +839,7 @@ int bar(int n){ // CHECK-DAG: load i16, i16* [[REF_AA]] // CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 -// OMP50: define internal void @__omp_offloading_{{.+}}_{{.+}}bar{{.+}}_l{{[0-9]+}}(i[[SZ]] noundef %{{.+}}) +// OMP50: define internal void @__omp_offloading_{{.+}}_{{.+}}bar{{.+}}_l{{[0-9]+}}(i[[SZ]] %{{.+}}) // OMP50: define {{.*}}@{{.*}}zee{{.*}} diff --git a/clang/test/OpenMP/target_codegen_global_capture.cpp b/clang/test/OpenMP/target_codegen_global_capture.cpp index 497234fb9fd10c38ecff94881a89afe4f2706cac..3711603547762f44d3b623c2f9694fedf49fd4cd 100644 --- a/clang/test/OpenMP/target_codegen_global_capture.cpp +++ b/clang/test/OpenMP/target_codegen_global_capture.cpp @@ -167,7 +167,7 @@ int tbar2(short a, short b, short c, short d){ #endif // CHECK1-LABEL: define {{[^@]+}}@_Z3foossss -// CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -352,7 +352,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49 -// CHECK1-SAME: (i64 noundef [[B:%.*]], i64 noundef [[GB:%.*]], i64 noundef [[SB:%.*]], i64 noundef [[GC:%.*]], i64 noundef [[C:%.*]], i64 noundef [[SC:%.*]], i64 noundef [[D:%.*]], i64 noundef [[GD:%.*]], i64 noundef [[SD:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[B:%.*]], i64 [[GB:%.*]], i64 [[SB:%.*]], i64 [[GC:%.*]], i64 [[C:%.*]], i64 [[SC:%.*]], i64 [[D:%.*]], i64 [[GD:%.*]], i64 [[SD:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8 @@ -425,7 +425,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 8 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -457,7 +457,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z3barssss -// CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -495,7 +495,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -665,7 +665,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94 -// CHECK1-SAME: (i64 noundef [[B:%.*]], i64 noundef [[GB:%.*]], i64 noundef [[SB:%.*]], i64 noundef [[GC:%.*]], i64 noundef [[C:%.*]], i64 noundef [[SC:%.*]], i64 noundef [[D:%.*]], i64 noundef [[GD:%.*]], i64 noundef [[SD:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[B:%.*]], i64 [[GB:%.*]], i64 [[SB:%.*]], i64 [[GC:%.*]], i64 [[C:%.*]], i64 [[SC:%.*]], i64 [[D:%.*]], i64 [[GD:%.*]], i64 [[SD:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8 @@ -738,7 +738,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 8 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -770,7 +770,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tbar2ssss -// CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -784,12 +784,12 @@ int tbar2(short a, short b, short c, short d){ // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 noundef signext [[TMP0]], i16 noundef signext [[TMP1]], i16 noundef signext [[TMP2]], i16 noundef signext [[TMP3]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_ -// CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -827,7 +827,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -997,7 +997,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145 -// CHECK1-SAME: (i64 noundef [[B:%.*]], i64 noundef [[GB:%.*]], i64 noundef [[SB:%.*]], i64 noundef [[GC:%.*]], i64 noundef [[C:%.*]], i64 noundef [[SC:%.*]], i64 noundef [[D:%.*]], i64 noundef [[GD:%.*]], i64 noundef [[SD:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[B:%.*]], i64 [[GB:%.*]], i64 [[SB:%.*]], i64 [[GC:%.*]], i64 [[C:%.*]], i64 [[SC:%.*]], i64 [[D:%.*]], i64 [[GD:%.*]], i64 [[SD:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8 @@ -1070,7 +1070,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 8 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1109,7 +1109,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3foossss -// CHECK2-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -1294,7 +1294,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49 -// CHECK2-SAME: (i64 noundef [[B:%.*]], i64 noundef [[GB:%.*]], i64 noundef [[SB:%.*]], i64 noundef [[GC:%.*]], i64 noundef [[C:%.*]], i64 noundef [[SC:%.*]], i64 noundef [[D:%.*]], i64 noundef [[GD:%.*]], i64 noundef [[SD:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[B:%.*]], i64 [[GB:%.*]], i64 [[SB:%.*]], i64 [[GC:%.*]], i64 [[C:%.*]], i64 [[SC:%.*]], i64 [[D:%.*]], i64 [[GD:%.*]], i64 [[SD:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8 @@ -1367,7 +1367,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 8 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1399,7 +1399,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3barssss -// CHECK2-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -1437,7 +1437,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1607,7 +1607,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94 -// CHECK2-SAME: (i64 noundef [[B:%.*]], i64 noundef [[GB:%.*]], i64 noundef [[SB:%.*]], i64 noundef [[GC:%.*]], i64 noundef [[C:%.*]], i64 noundef [[SC:%.*]], i64 noundef [[D:%.*]], i64 noundef [[GD:%.*]], i64 noundef [[SD:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[B:%.*]], i64 [[GB:%.*]], i64 [[SB:%.*]], i64 [[GC:%.*]], i64 [[C:%.*]], i64 [[SC:%.*]], i64 [[D:%.*]], i64 [[GD:%.*]], i64 [[SD:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8 @@ -1680,7 +1680,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 8 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1712,7 +1712,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z5tbar2ssss -// CHECK2-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -1726,12 +1726,12 @@ int tbar2(short a, short b, short c, short d){ // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 noundef signext [[TMP0]], i16 noundef signext [[TMP1]], i16 noundef signext [[TMP2]], i16 noundef signext [[TMP3]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_ -// CHECK2-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -1769,7 +1769,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1939,7 +1939,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145 -// CHECK2-SAME: (i64 noundef [[B:%.*]], i64 noundef [[GB:%.*]], i64 noundef [[SB:%.*]], i64 noundef [[GC:%.*]], i64 noundef [[C:%.*]], i64 noundef [[SC:%.*]], i64 noundef [[D:%.*]], i64 noundef [[GD:%.*]], i64 noundef [[SD:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[B:%.*]], i64 [[GB:%.*]], i64 [[SB:%.*]], i64 [[GC:%.*]], i64 [[C:%.*]], i64 [[SC:%.*]], i64 [[D:%.*]], i64 [[GD:%.*]], i64 [[SD:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[GB_ADDR:%.*]] = alloca i64, align 8 @@ -2012,7 +2012,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 8 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2051,7 +2051,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3foossss -// CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -2221,7 +2221,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49 -// CHECK3-SAME: (i32 noundef [[B:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 noundef [[SB:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 noundef [[C:%.*]], i32 noundef [[SC:%.*]], i32 noundef [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 noundef [[SD:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 [[B:%.*]], double* nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 [[SB:%.*]], double* nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 [[C:%.*]], i32 [[SC:%.*]], i32 [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 [[SD:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4 @@ -2303,7 +2303,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2335,7 +2335,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3barssss -// CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -2373,7 +2373,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2528,7 +2528,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94 -// CHECK3-SAME: (i32 noundef [[B:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 noundef [[SB:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 noundef [[C:%.*]], i32 noundef [[SC:%.*]], i32 noundef [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 noundef [[SD:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[B:%.*]], double* nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 [[SB:%.*]], double* nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 [[C:%.*]], i32 [[SC:%.*]], i32 [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 [[SD:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4 @@ -2610,7 +2610,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2642,7 +2642,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z5tbar2ssss -// CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -2656,12 +2656,12 @@ int tbar2(short a, short b, short c, short d){ // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 noundef signext [[TMP0]], i16 noundef signext [[TMP1]], i16 noundef signext [[TMP2]], i16 noundef signext [[TMP3]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_ -// CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] comdat { +// CHECK3-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -2699,7 +2699,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2854,7 +2854,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145 -// CHECK3-SAME: (i32 noundef [[B:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 noundef [[SB:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 noundef [[C:%.*]], i32 noundef [[SC:%.*]], i32 noundef [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 noundef [[SD:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[B:%.*]], double* nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 [[SB:%.*]], double* nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 [[C:%.*]], i32 [[SC:%.*]], i32 [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 [[SD:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4 @@ -2936,7 +2936,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2975,7 +2975,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3foossss -// CHECK4-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -3145,7 +3145,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49 -// CHECK4-SAME: (i32 noundef [[B:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 noundef [[SB:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 noundef [[C:%.*]], i32 noundef [[SC:%.*]], i32 noundef [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 noundef [[SD:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32 [[B:%.*]], double* nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 [[SB:%.*]], double* nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 [[C:%.*]], i32 [[SC:%.*]], i32 [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 [[SD:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4 @@ -3227,7 +3227,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3259,7 +3259,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3barssss -// CHECK4-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -3297,7 +3297,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3452,7 +3452,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94 -// CHECK4-SAME: (i32 noundef [[B:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 noundef [[SB:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 noundef [[C:%.*]], i32 noundef [[SC:%.*]], i32 noundef [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 noundef [[SD:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[B:%.*]], double* nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 [[SB:%.*]], double* nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 [[C:%.*]], i32 [[SC:%.*]], i32 [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 [[SD:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4 @@ -3534,7 +3534,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3566,7 +3566,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z5tbar2ssss -// CHECK4-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -3580,12 +3580,12 @@ int tbar2(short a, short b, short c, short d){ // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[B_ADDR]], align 2 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[C_ADDR]], align 2 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[D_ADDR]], align 2 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 noundef signext [[TMP0]], i16 noundef signext [[TMP1]], i16 noundef signext [[TMP2]], i16 noundef signext [[TMP3]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 signext [[TMP0]], i16 signext [[TMP1]], i16 signext [[TMP2]], i16 signext [[TMP3]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_ -// CHECK4-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] comdat { +// CHECK4-SAME: (i16 signext [[A:%.*]], i16 signext [[B:%.*]], i16 signext [[C:%.*]], i16 signext [[D:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i16, align 2 @@ -3623,7 +3623,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[B:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[A:%.*]], i16* nonnull align 2 dereferenceable(2) [[B:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3778,7 +3778,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145 -// CHECK4-SAME: (i32 noundef [[B:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 noundef [[SB:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 noundef [[C:%.*]], i32 noundef [[SC:%.*]], i32 noundef [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 noundef [[SD:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[B:%.*]], double* nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 [[SB:%.*]], double* nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 [[C:%.*]], i32 [[SC:%.*]], i32 [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 [[SD:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[GB_ADDR:%.*]] = alloca double*, align 4 @@ -3860,7 +3860,7 @@ int tbar2(short a, short b, short c, short d){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[D:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i16* nonnull align 2 dereferenceable(2) [[D:%.*]], double* nonnull align 4 dereferenceable(8) [[GD:%.*]], float* nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/target_defaultmap_codegen_01.cpp b/clang/test/OpenMP/target_defaultmap_codegen_01.cpp index 8e08f21415ba6de0bcc53771409c2faf087c2ba8..6be64f3cdd0a1c87e172579f51ad8191133e5bd5 100644 --- a/clang/test/OpenMP/target_defaultmap_codegen_01.cpp +++ b/clang/test/OpenMP/target_defaultmap_codegen_01.cpp @@ -5,19 +5,19 @@ #ifdef CK1 ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK1 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK1 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK1 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK1 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 +// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 +// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 +// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK1 + +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -DCK1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s // SIMD-ONLY10-NOT: {{__kmpc|__tgt}} // CK1-LABEL: @.__omp_offloading_{{.*}}implicit_maps_double_complex{{.*}}_l{{[0-9]+}}.region_id = weak{{.*}} constant i8 0 @@ -54,19 +54,19 @@ void implicit_maps_double_complex (int a){ // CK1: {{.+}} = getelementptr inbounds { double, double }, { double, double }* [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK2 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK2 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK2 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK2 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK2 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK2 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK2 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK2 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 +// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 +// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 +// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK2 + +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -DCK2 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s // SIMD-ONLY10-NOT: {{__kmpc|__tgt}} #ifdef CK2 @@ -104,19 +104,19 @@ void implicit_maps_double_complex (int a){ // CK2: {{.+}} = getelementptr inbounds { double, double }, { double, double }* [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK3 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK3 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK3 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK3 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK3 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK3 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK3 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK3 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -DCK3 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 +// RUN: %clang_cc1 -DCK3 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 +// RUN: %clang_cc1 -DCK3 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 +// RUN: %clang_cc1 -DCK3 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK3 + +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s +// RUN: %clang_cc1 -DCK3 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY10 %s // SIMD-ONLY10-NOT: {{__kmpc|__tgt}} #ifdef CK3 @@ -154,19 +154,19 @@ void implicit_maps_double_complex (int a){ // CK3: {{.+}} = getelementptr inbounds { double, double }, { double, double }* [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK4 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-64 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK4 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-64 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK4 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-32 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK4 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-32 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK4 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK4 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK4 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK4 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -DCK4 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-64 +// RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-64 +// RUN: %clang_cc1 -DCK4 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-32 +// RUN: %clang_cc1 -DCK4 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK4 --check-prefix CK4-32 + +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -DCK4 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s // SIMD-ONLY6-NOT: {{__kmpc|__tgt}} #ifdef CK4 @@ -226,19 +226,19 @@ void implicit_maps_double (int a){ #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK5 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK5 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK5 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK5 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK5 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK5 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK5 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK5 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK5 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 +// RUN: %clang_cc1 -DCK5 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 +// RUN: %clang_cc1 -DCK5 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 +// RUN: %clang_cc1 -DCK5 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK5 + +// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK5 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK5 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK5 @@ -277,19 +277,19 @@ void implicit_maps_array (int a){ // CK5: {{.+}} = getelementptr inbounds [2 x double], [2 x double]* [[REF]], i{{64|32}} 0, i{{64|32}} 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK6 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK6 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK6 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK6 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK6 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK6 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK6 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK6 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK6 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 +// RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 +// RUN: %clang_cc1 -DCK6 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 +// RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 + +// RUN: %clang_cc1 -DCK6 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK6 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK6 @@ -328,19 +328,19 @@ void implicit_maps_array (int a){ // CK6: {{.+}} = getelementptr inbounds [2 x double], [2 x double]* [[REF]], i{{64|32}} 0, i{{64|32}} 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK7 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK7 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK7 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK7 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK7 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK7 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK7 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK7 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK7 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 +// RUN: %clang_cc1 -DCK7 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 +// RUN: %clang_cc1 -DCK7 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 +// RUN: %clang_cc1 -DCK7 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 + +// RUN: %clang_cc1 -DCK7 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK7 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK7 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK7 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK7 @@ -379,19 +379,19 @@ void implicit_maps_array (int a){ // CK7: {{.+}} = getelementptr inbounds [2 x double], [2 x double]* [[REF]], i{{64|32}} 0, i{{64|32}} 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK8 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK8 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK8 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK8 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK8 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK8 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK8 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK8 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK8 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 +// RUN: %clang_cc1 -DCK8 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 +// RUN: %clang_cc1 -DCK8 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 +// RUN: %clang_cc1 -DCK8 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 + +// RUN: %clang_cc1 -DCK8 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK8 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK8 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK8 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK8 @@ -431,19 +431,19 @@ void implicit_maps_array (int a){ #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK9 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-64 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK9 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-64 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK9 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-32 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK9 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-32 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK9 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK9 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK9 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK9 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s +// RUN: %clang_cc1 -DCK9 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-64 +// RUN: %clang_cc1 -DCK9 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-64 +// RUN: %clang_cc1 -DCK9 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-32 +// RUN: %clang_cc1 -DCK9 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK9 --check-prefix CK9-32 + +// RUN: %clang_cc1 -DCK9 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s +// RUN: %clang_cc1 -DCK9 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s +// RUN: %clang_cc1 -DCK9 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s +// RUN: %clang_cc1 -DCK9 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY26 %s // SIMD-ONLY26-NOT: {{__kmpc|__tgt}} #ifdef CK9 @@ -481,19 +481,19 @@ void zero_size_section_and_private_maps (int ii){ #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK10 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK10 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK10 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK10 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK10 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK10 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK10 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK10 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK10 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 +// RUN: %clang_cc1 -DCK10 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 +// RUN: %clang_cc1 -DCK10 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 +// RUN: %clang_cc1 -DCK10 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK10 + +// RUN: %clang_cc1 -DCK10 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK10 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK10 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK10 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK10 @@ -529,19 +529,19 @@ void explicit_maps_single (){ // CK10: define {{.+}}[[CALL]] #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK11 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK11 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK11 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK11 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK11 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK11 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK11 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK11 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK11 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 +// RUN: %clang_cc1 -DCK11 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 +// RUN: %clang_cc1 -DCK11 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 +// RUN: %clang_cc1 -DCK11 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK11 + +// RUN: %clang_cc1 -DCK11 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK11 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK11 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK11 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK11 @@ -577,19 +577,19 @@ void explicit_maps_single (){ // CK11: define {{.+}}[[CALL09]] #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK12 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK12 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK12 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK12 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK12 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK12 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK12 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK12 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK12 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 +// RUN: %clang_cc1 -DCK12 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 +// RUN: %clang_cc1 -DCK12 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 +// RUN: %clang_cc1 -DCK12 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK12 + +// RUN: %clang_cc1 -DCK12 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK12 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK12 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK12 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK12 @@ -625,19 +625,19 @@ void explicit_maps_single (){ // CK12: define {{.+}}[[CALL09]] #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK13 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK13 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK13 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK13 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK13 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK13 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK13 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK13 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK13 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -DCK13 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -DCK13 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 +// RUN: %clang_cc1 -DCK13 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK13 + +// RUN: %clang_cc1 -DCK13 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK13 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK13 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK13 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK13 @@ -673,19 +673,19 @@ void explicit_maps_single (){ // CK13: define {{.+}}[[CALL09]] #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK14 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK14 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK14 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK14 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK14 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK14 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK14 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK14 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK14 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 +// RUN: %clang_cc1 -DCK14 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 +// RUN: %clang_cc1 -DCK14 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 +// RUN: %clang_cc1 -DCK14 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK14 + +// RUN: %clang_cc1 -DCK14 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK14 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK14 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s +// RUN: %clang_cc1 -DCK14 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY8 %s // SIMD-ONLY8-NOT: {{__kmpc|__tgt}} #ifdef CK14 @@ -721,19 +721,19 @@ void explicit_maps_single (){ // CK14: define {{.+}}[[CALL09]] #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK15 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK15 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK15 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK15 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK15 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK15 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK15 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK15 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s +// RUN: %clang_cc1 -DCK15 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 +// RUN: %clang_cc1 -DCK15 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 +// RUN: %clang_cc1 -DCK15 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 +// RUN: %clang_cc1 -DCK15 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK15 + +// RUN: %clang_cc1 -DCK15 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s +// RUN: %clang_cc1 -DCK15 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s +// RUN: %clang_cc1 -DCK15 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s +// RUN: %clang_cc1 -DCK15 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY12 %s // SIMD-ONLY12-NOT: {{__kmpc|__tgt}} #ifdef CK15 @@ -803,19 +803,19 @@ void implicit_maps_variable_length_array (int a){ // CK15: {{.+}} = getelementptr inbounds double, double* [[REF]], i[[sz]] %{{.+}} #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK16 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK16 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK16 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK16 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK16 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK16 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK16 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK16 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK16 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 +// RUN: %clang_cc1 -DCK16 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 +// RUN: %clang_cc1 -DCK16 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 +// RUN: %clang_cc1 -DCK16 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK16 + +// RUN: %clang_cc1 -DCK16 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK16 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK16 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK16 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // SIMD-ONLY16-NOT: {{__kmpc|__tgt}} #ifdef CK16 @@ -860,19 +860,19 @@ void implicit_maps_struct (int a){ // CK16: {{.+}} = getelementptr inbounds [[ST]], [[ST]]* [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK17 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK17 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK17 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK17 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK17 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK17 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK17 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK17 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK17 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 +// RUN: %clang_cc1 -DCK17 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 +// RUN: %clang_cc1 -DCK17 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 +// RUN: %clang_cc1 -DCK17 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK17 + +// RUN: %clang_cc1 -DCK17 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK17 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK17 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK17 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // SIMD-ONLY16-NOT: {{__kmpc|__tgt}} #ifdef CK17 @@ -917,19 +917,19 @@ void implicit_maps_struct (int a){ // CK17: {{.+}} = getelementptr inbounds [[ST]], [[ST]]* [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK18 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK18 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK18 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK18 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK18 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK18 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK18 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK18 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK18 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 +// RUN: %clang_cc1 -DCK18 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 +// RUN: %clang_cc1 -DCK18 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 +// RUN: %clang_cc1 -DCK18 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK18 + +// RUN: %clang_cc1 -DCK18 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK18 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK18 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK18 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // SIMD-ONLY16-NOT: {{__kmpc|__tgt}} #ifdef CK18 @@ -974,19 +974,19 @@ void implicit_maps_struct (int a){ // CK18: {{.+}} = getelementptr inbounds [[ST]], [[ST]]* [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK19 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK19 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK19 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK19 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK19 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK19 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK19 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK19 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK19 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 +// RUN: %clang_cc1 -DCK19 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 +// RUN: %clang_cc1 -DCK19 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 +// RUN: %clang_cc1 -DCK19 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK19 + +// RUN: %clang_cc1 -DCK19 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK19 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK19 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK19 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // SIMD-ONLY16-NOT: {{__kmpc|__tgt}} #ifdef CK19 @@ -1031,19 +1031,19 @@ void implicit_maps_struct (int a){ // CK19: {{.+}} = getelementptr inbounds [[ST]], [[ST]]* [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK20 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-64 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK20 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-64 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK20 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-32 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK20 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-32 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK20 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK20 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK20 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK20 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -DCK20 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-64 +// RUN: %clang_cc1 -DCK20 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-64 +// RUN: %clang_cc1 -DCK20 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-32 +// RUN: %clang_cc1 -DCK20 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK20 --check-prefix CK20-32 + +// RUN: %clang_cc1 -DCK20 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -DCK20 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -DCK20 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s +// RUN: %clang_cc1 -DCK20 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY6 %s // SIMD-ONLY6-NOT: {{__kmpc|__tgt}} #ifdef CK20 @@ -1103,19 +1103,19 @@ void implicit_maps_double (int a){ #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK21 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK21 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK21 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK21 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK21 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK21 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK21 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK21 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK21 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 +// RUN: %clang_cc1 -DCK21 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 +// RUN: %clang_cc1 -DCK21 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 +// RUN: %clang_cc1 -DCK21 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK21 + +// RUN: %clang_cc1 -DCK21 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK21 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK21 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s +// RUN: %clang_cc1 -DCK21 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY16 %s // SIMD-ONLY16-NOT: {{__kmpc|__tgt}} #ifdef CK21 @@ -1160,19 +1160,19 @@ void implicit_maps_struct (int a){ // CK21: {{.+}} = getelementptr inbounds [[ST]], [[ST]]* [[REF]], i32 0, i32 0 #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK22 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK22 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK22 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK22 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK22 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK22 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK22 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK22 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s +// RUN: %clang_cc1 -DCK22 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 +// RUN: %clang_cc1 -DCK22 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 +// RUN: %clang_cc1 -DCK22 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 +// RUN: %clang_cc1 -DCK22 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK22 + +// RUN: %clang_cc1 -DCK22 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s +// RUN: %clang_cc1 -DCK22 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s +// RUN: %clang_cc1 -DCK22 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s +// RUN: %clang_cc1 -DCK22 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY9 %s // SIMD-ONLY9-NOT: {{__kmpc|__tgt}} #ifdef CK22 @@ -1212,19 +1212,19 @@ void implicit_maps_pointer (){ #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK23 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-64 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK23 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-64 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK23 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-32 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK23 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-32 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK23 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK23 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK23 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK23 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK23 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-64 +// RUN: %clang_cc1 -DCK23 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-64 +// RUN: %clang_cc1 -DCK23 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-32 +// RUN: %clang_cc1 -DCK23 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK23 --check-prefix CK23-32 + +// RUN: %clang_cc1 -DCK23 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK23 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK23 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -DCK23 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} #ifdef CK23 @@ -1397,19 +1397,19 @@ void bar(float *&a, int *&b) { #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK24 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-64 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK24 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-64 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK24 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-32 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK24 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-32 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK24 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK24 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK24 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK24 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -DCK24 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-64 +// RUN: %clang_cc1 -DCK24 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-64 +// RUN: %clang_cc1 -DCK24 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-32 +// RUN: %clang_cc1 -DCK24 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK24 --check-prefix CK24-32 + +// RUN: %clang_cc1 -DCK24 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -DCK24 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -DCK24 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -DCK24 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s // SIMD-ONLY18-NOT: {{__kmpc|__tgt}} #ifdef CK24 @@ -1469,19 +1469,19 @@ void explicit_maps_single (int ii){ #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK25 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-64 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK25 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-64 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK25 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-32 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK25 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-32 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK25 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK25 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK25 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK25 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -DCK25 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-64 +// RUN: %clang_cc1 -DCK25 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-64 +// RUN: %clang_cc1 -DCK25 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-32 +// RUN: %clang_cc1 -DCK25 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK25 --check-prefix CK25-32 + +// RUN: %clang_cc1 -DCK25 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -DCK25 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -DCK25 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -DCK25 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s // SIMD-ONLY18-NOT: {{__kmpc|__tgt}} #ifdef CK25 @@ -1504,19 +1504,19 @@ void declare_target_to() #endif ///==========================================================================/// -// RUN: %clang_cc1 -disable-noundef-analysis -DCK26 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-64 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK26 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-64 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK26 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-32 -// RUN: %clang_cc1 -disable-noundef-analysis -DCK26 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-32 - -// RUN: %clang_cc1 -disable-noundef-analysis -DCK26 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK26 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK26 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s -// RUN: %clang_cc1 -disable-noundef-analysis -DCK26 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -DCK26 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-64 +// RUN: %clang_cc1 -DCK26 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-64 +// RUN: %clang_cc1 -DCK26 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-32 +// RUN: %clang_cc1 -DCK26 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK26 --check-prefix CK26-32 + +// RUN: %clang_cc1 -DCK26 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -DCK26 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -DCK26 -verify -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s +// RUN: %clang_cc1 -DCK26 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap --check-prefix SIMD-ONLY18 %s // SIMD-ONLY18-NOT: {{__kmpc|__tgt}} #ifdef CK26 diff --git a/clang/test/OpenMP/target_depend_codegen.cpp b/clang/test/OpenMP/target_depend_codegen.cpp index d06c24e2b11ae0600353381120c7f7f1ad204d81..e2c13af25caa1a02d7e9fb2a8d9a3cb709e113f4 100644 --- a/clang/test/OpenMP/target_depend_codegen.cpp +++ b/clang/test/OpenMP/target_depend_codegen.cpp @@ -227,7 +227,7 @@ int foo(int n) { // CHECK: define internal void [[HVT0:@.+]]() -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias %1) // CHECK: store void (i8*, ...)* null, void (i8*, ...)** % // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0 // CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]], @@ -241,11 +241,11 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* noundef %{{.+}}, i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* %{{.+}}, i[[SZ]] %{{.+}}) -// CHECK: define internal void [[MAPPER_ID]](i8* noundef %{{.+}}, i8* noundef %{{.+}}, i8* noundef %{{.+}}, i64 noundef %{{.+}}, i64 noundef %{{.+}}) +// CHECK: define internal void [[MAPPER_ID]](i8* %{{.+}}, i8* %{{.+}}, i8* %{{.+}}, i64 %{{.+}}, i64 %{{.+}}) -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias noundef %{{.+}}) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias %{{.+}}) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* %{{.+}} to void (i8*, // CHECK: call void [[FN]](i8* %{{.+}}, i[[SZ]]*** %{{.+}}, i32** %{{.+}}, [3 x i8*]** [[BPTR_ADDR:%.+]], [3 x i8*]** [[PTR_ADDR:%.+]], [3 x i64]** [[SZ_ADDR:%.+]], [3 x i8*]** [[M_ADDR:%.+]]) // CHECK: [[BPTR_REF:%.+]] = load [3 x i8*]*, [3 x i8*]** [[BPTR_ADDR]], @@ -275,7 +275,7 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2 @@ -288,7 +288,7 @@ int foo(int n) { // CHECK: call void [[HVT1]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]]) // CHECK: ret i32 0 -// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] %{{.+}}) // Create stack storage and store argument in there. // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align @@ -296,7 +296,7 @@ int foo(int n) { // CHECK-64: load i32, i32* [[AA_CADDR]], align // CHECK-32: load i32, i32* [[AA_ADDR]], align -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[BP1_I32:%.+]] = load i32, i32* % diff --git a/clang/test/OpenMP/target_enter_data_codegen.cpp b/clang/test/OpenMP/target_enter_data_codegen.cpp index f803f845e927485ed208b0347a3c81f61d7f0297..d0643467dece928403aa7b468f56b8a23945269c 100644 --- a/clang/test/OpenMP/target_enter_data_codegen.cpp +++ b/clang/test/OpenMP/target_enter_data_codegen.cpp @@ -224,7 +224,7 @@ void foo(int arg) { } -// CK1: define internal {{.*}}i32 [[OMP_TASK_ENTRY]](i32 {{.*}}%0, [[KMP_TASK_T_WITH_PRIVATES]]* noalias noundef %1) +// CK1: define internal {{.*}}i32 [[OMP_TASK_ENTRY]](i32 {{.*}}%0, [[KMP_TASK_T_WITH_PRIVATES]]* noalias %1) // CK1-DAG: call void @__tgt_target_data_begin_nowait_mapper(%struct.ident_t* @{{.+}}, i64 %{{[^,]+}}, i32 1, i8** [[BPADDR:%[^,]+]], i8** [[PADDR:%[^,]+]], i64* [[SZADDR:%[^,]+]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* [[MTYPE00]], i32 0, i32 0), i8** null, i8** null) // CK1-DAG: [[BPADDR]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[FPBPADDR:%[^,]+]], i{{32|64}} 0, i{{32|64}} 0 // CK1-DAG: [[PADDR]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[FPPADDR:%[^,]+]], i{{32|64}} 0, i{{32|64}} 0 diff --git a/clang/test/OpenMP/target_enter_data_depend_codegen.cpp b/clang/test/OpenMP/target_enter_data_depend_codegen.cpp index 758b89b9421cbeed407d7aa03886902306800fc1..5f39a37c7d61e2a0e5a822a4633a8274a2e8c3fd 100644 --- a/clang/test/OpenMP/target_enter_data_depend_codegen.cpp +++ b/clang/test/OpenMP/target_enter_data_depend_codegen.cpp @@ -372,7 +372,7 @@ void foo(int arg) { {++arg;} } -// CK1: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, %struct.kmp_task_t_with_privates* noalias noundef %1) +// CK1: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, %struct.kmp_task_t_with_privates* noalias %1) // CK1-DAG: call void @__tgt_target_data_begin_nowait_mapper(%struct.ident_t* @{{.+}}, i64 [[DEV:%[^,]+]], i32 1, i8** [[GEPBP:%.+]], i8** [[GEPP:%.+]], i64* [[GEPS:%.+]], {{.+}}getelementptr {{.+}}[1 x i{{.+}}]* [[MTYPE00]]{{.+}}, i8** null) // CK1-DAG: [[DEV]] = sext i32 [[DEVi32:%[^,]+]] to i64 // CK1-DAG: [[DEVi32]] = load i32, i32* %{{[^,]+}}, @@ -387,7 +387,7 @@ void foo(int arg) { // CK1: ret i32 0 // CK1: } -// CK1: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias noundef %1) +// CK1: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias %1) // CK1-DAG: call void @__tgt_target_data_begin_mapper(%struct.ident_t* @{{.+}}, i64 4, i32 1, i8** [[GEPBP:%.+]], i8** [[GEPP:%.+]], i64* [[GEPS:%.+]], {{.+}}getelementptr {{.+}}[1 x i{{.+}}]* [[MTYPE02]]{{.+}}, i8** null) // CK1-DAG: [[GEPBP]] = getelementptr inbounds {{.+}}[[BP:%[^,]+]] // CK1-DAG: [[GEPP]] = getelementptr inbounds {{.+}}[[P:%[^,]+]] @@ -400,7 +400,7 @@ void foo(int arg) { // CK1: ret i32 0 // CK1: } -// CK1: define internal{{.*}} i32 [[TASK_ENTRY3]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias noundef %1) +// CK1: define internal{{.*}} i32 [[TASK_ENTRY3]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias %1) // CK1-DAG: call void @__tgt_target_data_begin_mapper(%struct.ident_t* @{{.+}}, i64 -1, i32 1, i8** [[GEPBP:%.+]], i8** [[GEPP:%.+]], i64* [[GEPS:%.+]], {{.+}}getelementptr {{.+}}[1 x i{{.+}}]* [[MTYPE03]]{{.+}}, i8** null) // CK1-DAG: [[GEPBP]] = getelementptr inbounds {{.+}}[[BP:%[^,]+]] // CK1-DAG: [[GEPP]] = getelementptr inbounds {{.+}}[[P:%[^,]+]] @@ -414,7 +414,7 @@ void foo(int arg) { // CK1: ret i32 0 // CK1: } -// CK1: define internal{{.*}} i32 [[TASK_ENTRY4]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias noundef %1) +// CK1: define internal{{.*}} i32 [[TASK_ENTRY4]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias %1) // CK1-DAG: call void @__tgt_target_data_begin_mapper(%struct.ident_t* @{{.+}}, i64 -1, i32 2, i8** [[GEPBP:%.+]], i8** [[GEPP:%.+]], i64* [[GEPS:%.+]], {{.+}}getelementptr {{.+}}[2 x i{{.+}}]* [[MTYPE04]]{{.+}}, i8** null) // CK1-DAG: [[GEPBP]] = getelementptr inbounds {{.+}}[[BP:%[^,]+]] // CK1-DAG: [[GEPP]] = getelementptr inbounds {{.+}}[[P:%[^,]+]] diff --git a/clang/test/OpenMP/target_exit_data_codegen.cpp b/clang/test/OpenMP/target_exit_data_codegen.cpp index 2622c5809f4922e089d69ece1321e1d6efe5db8e..f056ee1074eb398761ece45924a763808ad7421e 100644 --- a/clang/test/OpenMP/target_exit_data_codegen.cpp +++ b/clang/test/OpenMP/target_exit_data_codegen.cpp @@ -221,7 +221,7 @@ void foo(int arg) { {++arg;} } -// CK1: define internal {{.*}}i32 [[OMP_TASK_ENTRY]](i32 {{.*}}%{{[^,]+}}, [[KMP_TASK_T_WITH_PRIVATES]]* noalias noundef %{{[^,]+}}) +// CK1: define internal {{.*}}i32 [[OMP_TASK_ENTRY]](i32 {{.*}}%{{[^,]+}}, [[KMP_TASK_T_WITH_PRIVATES]]* noalias %{{[^,]+}}) // CK1-DAG: call void @__tgt_target_data_end_nowait_mapper(%struct.ident_t* @{{.+}}, i64 %{{[^,]+}}, i32 1, i8** [[BP:%[^,]+]], i8** [[P:%[^,]+]], i64* [[SZ:%[^,]+]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* [[MTYPE00]], i32 0, i32 0), i8** null, i8** null) // CK1-DAG: [[BP]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[BPADDR:%[^,]+]], i[[sz]] 0, i[[sz]] 0 // CK1-DAG: [[P]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[PADDR:%[^,]+]], i[[sz]] 0, i[[sz]] 0 diff --git a/clang/test/OpenMP/target_exit_data_depend_codegen.cpp b/clang/test/OpenMP/target_exit_data_depend_codegen.cpp index bc6d8aa49792c577478164386771cdbfe7350e4b..5f2103db7d4e7fbe6ff6a65c16a46f7ae7cfe238 100644 --- a/clang/test/OpenMP/target_exit_data_depend_codegen.cpp +++ b/clang/test/OpenMP/target_exit_data_depend_codegen.cpp @@ -372,7 +372,7 @@ void foo(int arg) { {++arg;} } -// CK1: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, %struct.kmp_task_t_with_privates* noalias noundef %1) +// CK1: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, %struct.kmp_task_t_with_privates* noalias %1) // CK1-DAG: call void @__tgt_target_data_end_nowait_mapper(%struct.ident_t* @{{.+}}, i64 [[DEV:%[^,]+]], i32 1, i8** [[GEPBP:%.+]], i8** [[GEPP:%.+]], i64* [[GEPS:%.+]], {{.+}}getelementptr {{.+}}[1 x i{{.+}}]* [[MTYPE00]]{{.+}}, i8** null) // CK1-DAG: [[DEV]] = sext i32 [[DEVi32:%[^,]+]] to i64 // CK1-DAG: [[DEVi32]] = load i32, i32* %{{[^,]+}}, @@ -387,7 +387,7 @@ void foo(int arg) { // CK1: ret i32 0 // CK1: } -// CK1: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias noundef %1) +// CK1: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias %1) // CK1-DAG: call void @__tgt_target_data_end_mapper(%struct.ident_t* @{{.+}}, i64 4, i32 1, i8** [[GEPBP:%.+]], i8** [[GEPP:%.+]], i64* [[GEPS:%.+]], {{.+}}getelementptr {{.+}}[1 x i{{.+}}]* [[MTYPE02]]{{.+}}, i8** null) // CK1-DAG: [[GEPBP]] = getelementptr inbounds {{.+}}[[BP:%[^,]+]] // CK1-DAG: [[GEPP]] = getelementptr inbounds {{.+}}[[P:%[^,]+]] @@ -400,7 +400,7 @@ void foo(int arg) { // CK1: ret i32 0 // CK1: } -// CK1: define internal{{.*}} i32 [[TASK_ENTRY3]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias noundef %1) +// CK1: define internal{{.*}} i32 [[TASK_ENTRY3]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias %1) // CK1-DAG: call void @__tgt_target_data_end_mapper(%struct.ident_t* @{{.+}}, i64 -1, i32 1, i8** [[GEPBP:%.+]], i8** [[GEPP:%.+]], i64* [[GEPS:%.+]], {{.+}}getelementptr {{.+}}[1 x i{{.+}}]* [[MTYPE03]]{{.+}}, i8** null) // CK1-DAG: [[GEPBP]] = getelementptr inbounds {{.+}}[[BP:%[^,]+]] // CK1-DAG: [[GEPP]] = getelementptr inbounds {{.+}}[[P:%[^,]+]] @@ -414,7 +414,7 @@ void foo(int arg) { // CK1: ret i32 0 // CK1: } -// CK1: define internal{{.*}} i32 [[TASK_ENTRY4]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias noundef %1) +// CK1: define internal{{.*}} i32 [[TASK_ENTRY4]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias %1) // CK1-DAG: call void @__tgt_target_data_end_mapper(%struct.ident_t* @{{.+}}, i64 -1, i32 2, i8** [[GEPBP:%.+]], i8** [[GEPP:%.+]], i64* [[GEPS:%.+]], {{.+}}getelementptr {{.+}}[2 x i{{.+}}]* [[MTYPE04]]{{.+}}, i8** null) // CK1-DAG: [[GEPBP]] = getelementptr inbounds {{.+}}[[BP:%[^,]+]] // CK1-DAG: [[GEPP]] = getelementptr inbounds {{.+}}[[P:%[^,]+]] diff --git a/clang/test/OpenMP/target_firstprivate_codegen.cpp b/clang/test/OpenMP/target_firstprivate_codegen.cpp index 8197d9a0b23be4ec32d5d56737b833c2578f4456..4a6d211a41579d13f50d652d06fad1f3551a16cf 100644 --- a/clang/test/OpenMP/target_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_firstprivate_codegen.cpp @@ -141,7 +141,7 @@ int foo(int n, double *ptr) { // CHECK: [[PTR_GEP_ARG:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[PTR_ARR]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 // CHECK: {{.+}} = call i32 @__tgt_target_mapper(%struct.ident_t* @{{.+}}, i64 -1, {{.+}}, i32 3, i8** [[BASE_PTR_GEP_ARG]], i8** [[PTR_GEP_ARG]], i[[SZ]]* getelementptr inbounds ([3 x i[[SZ]]], [3 x i[[SZ]]]* [[SIZET]], i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* [[MAPT]], i32 0, i32 0), i8** null, i8** null) - // TCHECK: define weak void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A_IN:%.+]], i32** noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[P_IN:%.+]], i{{[0-9]+}} noundef [[GA_IN:%.+]]) + // TCHECK: define weak void @__omp_offloading_{{.+}}(i{{[0-9]+}} [[A_IN:%.+]], i32** nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[P_IN:%.+]], i{{[0-9]+}} [[GA_IN:%.+]]) // TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[P_ADDR:%.+]] = alloca i32**, // TCHECK: [[GA_ADDR:%.+]] = alloca i{{64|32}}, @@ -269,7 +269,7 @@ int foo(int n, double *ptr) { // make sure that firstprivate variables are generated in all cases and that we use those instances for operations inside the // target region - // TCHECK: define {{.*}}void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A2_IN:%.+]], [10 x float]* {{.+}} [[B_IN:%.+]], i{{[0-9]+}} noundef [[BN_SZ:%.+]], float* {{.+}} [[BN_IN:%.+]], [5 x [10 x double]]* {{.+}} [[C_IN:%.+]], i{{[0-9]+}} noundef [[CN_SZ1:%.+]], i{{[0-9]+}} noundef [[CN_SZ2:%.+]], double* {{.+}} [[CN_IN:%.+]], [[TT]]* {{.+}} [[D_IN:%.+]]) + // TCHECK: define {{.*}}void @__omp_offloading_{{.+}}(i{{[0-9]+}} [[A2_IN:%.+]], [10 x float]* {{.+}} [[B_IN:%.+]], i{{[0-9]+}} [[BN_SZ:%.+]], float* {{.+}} [[BN_IN:%.+]], [5 x [10 x double]]* {{.+}} [[C_IN:%.+]], i{{[0-9]+}} [[CN_SZ1:%.+]], i{{[0-9]+}} [[CN_SZ2:%.+]], double* {{.+}} [[CN_IN:%.+]], [[TT]]* {{.+}} [[D_IN:%.+]]) // TCHECK: [[A2_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[B_ADDR:%.+]] = alloca [10 x float]*, // TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}}, @@ -364,7 +364,7 @@ int foo(int n, double *ptr) { // CHECK: [[PTR_GEP_ARG3:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[PTR_ARR3]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 // CHECK: {{.+}} = call i32 @__tgt_target_mapper(%struct.ident_t* @{{.+}}, i64 -1, {{.+}}, i32 2, i8** [[BASE_PTR_GEP_ARG3]], i8** [[PTR_GEP_ARG3]], i[[SZ]]* getelementptr inbounds ([2 x i[[SZ]]], [2 x i[[SZ]]]* [[SIZET3]], i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* [[MAPT3]], i32 0, i32 0), i8** null, i8** null) - // TCHECK: define weak void @__omp_offloading_{{.+}}(double* noundef [[PTR_IN:%.+]], [[TTII]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[E:%.+]]) + // TCHECK: define weak void @__omp_offloading_{{.+}}(double* [[PTR_IN:%.+]], [[TTII]]* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[E:%.+]]) // TCHECK: [[PTR_ADDR:%.+]] = alloca double*, // TCHECK-NOT: alloca [[TTII]], // TCHECK-NOT: alloca double*, @@ -403,7 +403,7 @@ static int fstatic(int n) { return a; } -// TCHECK: define weak void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A_IN:%.+]], i{{[0-9]+}} noundef [[A3_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} [[B_IN:%.+]]) +// TCHECK: define weak void @__omp_offloading_{{.+}}(i{{[0-9]+}} [[A_IN:%.+]], i{{[0-9]+}} [[A3_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} [[B_IN:%.+]]) // TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[A3_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[B_ADDR:%.+]] = alloca [10 x i{{[0-9]+}}]*, @@ -501,7 +501,7 @@ struct S1 { // only check that we use the map types stored in the global variable // CHECK: call i32 @__tgt_target_mapper(%struct.ident_t* @{{.+}}, i64 -1, {{.+}}, i32 5, i8** {{.+}}, i8** {{.+}}, i{{[0-9]+}}* {{.+}}, i64* getelementptr inbounds ([5 x i64], [5 x i64]* [[MAPT4]], i32 0, i32 0), i8** null, i8** null) - // TCHECK: define weak void @__omp_offloading_{{.+}}([[S1]]* noundef [[TH:%.+]], i{{[0-9]+}} noundef [[B_IN:%.+]], i{{[0-9]+}} noundef [[VLA:%.+]], i{{[0-9]+}} noundef [[VLA1:%.+]], i{{[0-9]+}}{{.+}} [[C_IN:%.+]]) + // TCHECK: define weak void @__omp_offloading_{{.+}}([[S1]]* [[TH:%.+]], i{{[0-9]+}} [[B_IN:%.+]], i{{[0-9]+}} [[VLA:%.+]], i{{[0-9]+}} [[VLA1:%.+]], i{{[0-9]+}}{{.+}} [[C_IN:%.+]]) // TCHECK: [[TH_ADDR:%.+]] = alloca [[S1]]*, // TCHECK: [[B_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}}, @@ -609,7 +609,7 @@ int bar(int n, double *ptr) { // CHECK: call i32 @__tgt_target_mapper(%struct.ident_t* @{{.+}}, i64 -1, {{.+}}, i32 2, i8** {{.+}}, i8** {{.+}}, i[[SZ]]* getelementptr inbounds ([2 x i[[SZ]]], [2 x i[[SZ]]]* [[SIZET6]], i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* [[MAPT6]], i32 0, i32 0), i8** null, i8** null) -// TCHECK: define weak void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} [[B_IN:%.+]]) +// TCHECK: define weak void @__omp_offloading_{{.+}}(i{{[0-9]+}} [[A_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} [[B_IN:%.+]]) // TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[B_ADDR:%.+]] = alloca [10 x i{{[0-9]+}}]*, // TCHECK-NOT: alloca i{{[0-9]+}}, diff --git a/clang/test/OpenMP/target_map_codegen_00.cpp b/clang/test/OpenMP/target_map_codegen_00.cpp index bd721703b7f8db5ad54fecc0a263dee94e074fe2..3fb1362247356b763dc0a3cd498cf40d79c1f381 100644 --- a/clang/test/OpenMP/target_map_codegen_00.cpp +++ b/clang/test/OpenMP/target_map_codegen_00.cpp @@ -93,7 +93,7 @@ void implicit_maps_integer (int a){ } } -// CK1: define internal void [[KERNEL]](i[[sz]] noundef [[ARG:%.+]]) +// CK1: define internal void [[KERNEL]](i[[sz]] [[ARG:%.+]]) // CK1: [[ADDR:%.+]] = alloca i[[sz]], // CK1: store i[[sz]] [[ARG]], i[[sz]]* [[ADDR]], // CK1-64: [[CADDR:%.+]] = bitcast i64* [[ADDR]] to i32* diff --git a/clang/test/OpenMP/target_map_codegen_01.cpp b/clang/test/OpenMP/target_map_codegen_01.cpp index 1a12438f9710500bfcb813eacb6f1becd5fb2293..4628c8b1136862dbd2cd5a19344d8577dcd2399c 100644 --- a/clang/test/OpenMP/target_map_codegen_01.cpp +++ b/clang/test/OpenMP/target_map_codegen_01.cpp @@ -87,7 +87,7 @@ void implicit_maps_reference (int a, int *b){ } } -// CK2: define internal void [[KERNEL]](i[[sz]] noundef [[ARG:%.+]]) +// CK2: define internal void [[KERNEL]](i[[sz]] [[ARG:%.+]]) // CK2: [[ADDR:%.+]] = alloca i[[sz]], // CK2: [[REF:%.+]] = alloca i32*, // CK2: store i[[sz]] [[ARG]], i[[sz]]* [[ADDR]], @@ -99,7 +99,7 @@ void implicit_maps_reference (int a, int *b){ // CK2-32: [[RVAL:%.+]] = load i32*, i32** [[REF]], // CK2-32: {{.+}} = load i32, i32* [[RVAL]], -// CK2: define internal void [[KERNEL2]](i32* noundef [[ARG:%.+]]) +// CK2: define internal void [[KERNEL2]](i32* [[ARG:%.+]]) // CK2: [[ADDR:%.+]] = alloca i32*, // CK2: [[REF:%.+]] = alloca i32**, // CK2: store i32* [[ARG]], i32** [[ADDR]], diff --git a/clang/test/OpenMP/target_map_codegen_02.cpp b/clang/test/OpenMP/target_map_codegen_02.cpp index 845dabad6516335828a4eeda7ba53e92aeaef5de..5308d8e2ce99226f26ba71effc5b57ec3721476b 100644 --- a/clang/test/OpenMP/target_map_codegen_02.cpp +++ b/clang/test/OpenMP/target_map_codegen_02.cpp @@ -62,7 +62,7 @@ void implicit_maps_parameter (int a){ } } -// CK3: define internal void [[KERNEL]](i[[sz]] noundef [[ARG:%.+]]) +// CK3: define internal void [[KERNEL]](i[[sz]] [[ARG:%.+]]) // CK3: [[ADDR:%.+]] = alloca i[[sz]], // CK3: store i[[sz]] [[ARG]], i[[sz]]* [[ADDR]], // CK3-64: [[CADDR:%.+]] = bitcast i64* [[ADDR]] to i32* diff --git a/clang/test/OpenMP/target_map_codegen_03.cpp b/clang/test/OpenMP/target_map_codegen_03.cpp index 4f101b02c23aab02163fb78f24da1782e053a186..053365a29bfc074789e08a3c986a9ce3c116a0ce 100644 --- a/clang/test/OpenMP/target_map_codegen_03.cpp +++ b/clang/test/OpenMP/target_map_codegen_03.cpp @@ -58,7 +58,7 @@ void implicit_maps_nested_integer (int a){ #endif // CK4 #endif // CHECK1-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK1-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -70,7 +70,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -108,7 +108,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z28implicit_maps_nested_integeri_l48 -// CHECK1-SAME: (i64 noundef [[I:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[I:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 @@ -118,7 +118,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -141,7 +141,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK2-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -153,7 +153,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -191,7 +191,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z28implicit_maps_nested_integeri_l48 -// CHECK2-SAME: (i64 noundef [[I:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[I:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 @@ -201,7 +201,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -224,7 +224,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -236,7 +236,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -273,7 +273,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z28implicit_maps_nested_integeri_l48 -// CHECK3-SAME: (i32 noundef [[I:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32 [[I:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 @@ -282,7 +282,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -305,7 +305,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK4-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -317,7 +317,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -354,7 +354,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z28implicit_maps_nested_integeri_l48 -// CHECK4-SAME: (i32 noundef [[I:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i32 [[I:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 @@ -363,7 +363,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -386,7 +386,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK5-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK5-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -398,7 +398,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -436,7 +436,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z28implicit_maps_nested_integeri_l48 -// CHECK5-SAME: (i64 noundef [[I:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-SAME: (i64 [[I:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 @@ -446,7 +446,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -469,7 +469,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK6-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK6-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -481,7 +481,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -519,7 +519,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z28implicit_maps_nested_integeri_l48 -// CHECK6-SAME: (i64 noundef [[I:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK6-SAME: (i64 [[I:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 @@ -529,7 +529,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -552,7 +552,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK7-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK7-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -564,7 +564,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -601,7 +601,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z28implicit_maps_nested_integeri_l48 -// CHECK7-SAME: (i32 noundef [[I:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK7-SAME: (i32 [[I:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 @@ -610,7 +610,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -633,7 +633,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK8-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK8-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -645,7 +645,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -682,7 +682,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z28implicit_maps_nested_integeri_l48 -// CHECK8-SAME: (i32 noundef [[I:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-SAME: (i32 [[I:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 @@ -691,7 +691,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -714,7 +714,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK9-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK9-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -726,7 +726,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -764,7 +764,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z28implicit_maps_nested_integeri_l48 -// CHECK9-SAME: (i64 noundef [[I:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[I:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 @@ -774,7 +774,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -797,7 +797,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK10-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK10-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -809,7 +809,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -847,7 +847,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z28implicit_maps_nested_integeri_l48 -// CHECK10-SAME: (i64 noundef [[I:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[I:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i64 [[I]], i64* [[I_ADDR]], align 8 @@ -857,7 +857,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -880,7 +880,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK11-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK11-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -892,7 +892,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -929,7 +929,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z28implicit_maps_nested_integeri_l48 -// CHECK11-SAME: (i32 noundef [[I:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[I:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 @@ -938,7 +938,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -961,7 +961,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK12-LABEL: define {{[^@]+}}@_Z28implicit_maps_nested_integeri -// CHECK12-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -973,7 +973,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1010,7 +1010,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z28implicit_maps_nested_integeri_l48 -// CHECK12-SAME: (i32 noundef [[I:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[I:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4 @@ -1019,7 +1019,7 @@ void implicit_maps_nested_integer (int a){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/target_map_codegen_04.cpp b/clang/test/OpenMP/target_map_codegen_04.cpp index dc0549e5cc2159d6db52a7f6bc885b3f0a0cb209..6c7d3a26004e5f2c09a5f93fe9e9cc86ec23edc8 100644 --- a/clang/test/OpenMP/target_map_codegen_04.cpp +++ b/clang/test/OpenMP/target_map_codegen_04.cpp @@ -69,7 +69,7 @@ void implicit_maps_nested_integer_and_enum (int a){ } } -// CK5: define internal void [[KERNEL]](i[[sz]] noundef [[ARG:%.+]]) +// CK5: define internal void [[KERNEL]](i[[sz]] [[ARG:%.+]]) // CK5: [[ADDR:%.+]] = alloca i[[sz]], // CK5: store i[[sz]] [[ARG]], i[[sz]]* [[ADDR]], // CK5-64: [[CADDR:%.+]] = bitcast i64* [[ADDR]] to i32* diff --git a/clang/test/OpenMP/target_map_codegen_05.cpp b/clang/test/OpenMP/target_map_codegen_05.cpp index a25d2f6c298682ddd59193d62186bdc8e53262dc..a7bd94e08455273820277a3c9d83396a246809b1 100644 --- a/clang/test/OpenMP/target_map_codegen_05.cpp +++ b/clang/test/OpenMP/target_map_codegen_05.cpp @@ -64,7 +64,7 @@ void implicit_maps_host_global (int a){ } } -// CK6: define internal void [[KERNEL]](i[[sz]] noundef [[ARG:%.+]]) +// CK6: define internal void [[KERNEL]](i[[sz]] [[ARG:%.+]]) // CK6: [[ADDR:%.+]] = alloca i[[sz]], // CK6: store i[[sz]] [[ARG]], i[[sz]]* [[ADDR]], // CK6-64: [[CADDR:%.+]] = bitcast i64* [[ADDR]] to i32* diff --git a/clang/test/OpenMP/target_map_codegen_06.cpp b/clang/test/OpenMP/target_map_codegen_06.cpp index 29a39621d5be372fc46ce467d25ccbfc4d848824..e385905134e99eea241f4b4cf7161c7fd20540bd 100644 --- a/clang/test/OpenMP/target_map_codegen_06.cpp +++ b/clang/test/OpenMP/target_map_codegen_06.cpp @@ -75,7 +75,7 @@ void implicit_maps_double (int a){ } } -// CK7-64: define internal void [[KERNEL]](i[[sz]] noundef [[ARG:%.+]]) +// CK7-64: define internal void [[KERNEL]](i[[sz]] [[ARG:%.+]]) // CK7-64: [[ADDR:%.+]] = alloca i[[sz]], // CK7-64: store i[[sz]] [[ARG]], i[[sz]]* [[ADDR]], // CK7-64: [[CADDR:%.+]] = bitcast i64* [[ADDR]] to double* diff --git a/clang/test/OpenMP/target_map_codegen_07.cpp b/clang/test/OpenMP/target_map_codegen_07.cpp index 9f7b794e4e4bcd90e56432f7077a7c6c9b24513f..778cf54bb075e9f181080c6fcabbdd4db8e29950 100644 --- a/clang/test/OpenMP/target_map_codegen_07.cpp +++ b/clang/test/OpenMP/target_map_codegen_07.cpp @@ -63,7 +63,7 @@ void implicit_maps_float (int a){ } } -// CK8: define internal void [[KERNEL]](i[[sz]] noundef [[ARG:%.+]]) +// CK8: define internal void [[KERNEL]](i[[sz]] [[ARG:%.+]]) // CK8: [[ADDR:%.+]] = alloca i[[sz]], // CK8: store i[[sz]] [[ARG]], i[[sz]]* [[ADDR]], // CK8: [[CADDR:%.+]] = bitcast i[[sz]]* [[ADDR]] to float* diff --git a/clang/test/OpenMP/target_map_codegen_11.cpp b/clang/test/OpenMP/target_map_codegen_11.cpp index 1eaadd5d290c69529117c702ed61d8bd573a3ae9..c152b7c648962c96ca3e40d27e6ae3f6b56eef2d 100644 --- a/clang/test/OpenMP/target_map_codegen_11.cpp +++ b/clang/test/OpenMP/target_map_codegen_11.cpp @@ -75,7 +75,7 @@ void implicit_maps_float_complex (int a){ } } -// CK12-64: define internal void [[KERNEL]](i[[sz]] noundef [[ARG:%.+]]) +// CK12-64: define internal void [[KERNEL]](i[[sz]] [[ARG:%.+]]) // CK12-64: [[ADDR:%.+]] = alloca i[[sz]], // CK12-64: store i[[sz]] [[ARG]], i[[sz]]* [[ADDR]], // CK12-64: [[CADDR:%.+]] = bitcast i[[sz]]* [[ADDR]] to { float, float }* diff --git a/clang/test/OpenMP/target_map_codegen_12.cpp b/clang/test/OpenMP/target_map_codegen_12.cpp index 598ceef40e6cb7e719dfff820738152736016cca..4de7595825ec5e93832e4e9debc7b727becf6c1c 100644 --- a/clang/test/OpenMP/target_map_codegen_12.cpp +++ b/clang/test/OpenMP/target_map_codegen_12.cpp @@ -86,7 +86,7 @@ void implicit_maps_variable_length_array (int a){ } } -// CK13: define internal void [[KERNEL]](i[[sz]] noundef [[VLA0:%.+]], i[[sz]] noundef [[VLA1:%.+]], double* {{.*}}[[ARG:%.+]]) +// CK13: define internal void [[KERNEL]](i[[sz]] [[VLA0:%.+]], i[[sz]] [[VLA1:%.+]], double* {{.*}}[[ARG:%.+]]) // CK13: [[ADDR0:%.+]] = alloca i[[sz]], // CK13: [[ADDR1:%.+]] = alloca i[[sz]], // CK13: [[ADDR2:%.+]] = alloca double*, diff --git a/clang/test/OpenMP/target_map_codegen_13.cpp b/clang/test/OpenMP/target_map_codegen_13.cpp index 27fe1698db9cc3a9dd7535aa332c64d8b52bb370..810e36397cb868f7c2840167bedb039e7d104f62 100644 --- a/clang/test/OpenMP/target_map_codegen_13.cpp +++ b/clang/test/OpenMP/target_map_codegen_13.cpp @@ -113,7 +113,7 @@ void implicit_maps_class (int a){ sss.foo(123); } -// CK14: define internal void [[KERNEL]]([[ST]]* noundef [[THIS:%.+]], i[[sz]] noundef [[ARG:%.+]]) +// CK14: define internal void [[KERNEL]]([[ST]]* [[THIS:%.+]], i[[sz]] [[ARG:%.+]]) // CK14: [[ADDR0:%.+]] = alloca [[ST]]*, // CK14: [[ADDR1:%.+]] = alloca i[[sz]], // CK14: store [[ST]]* [[THIS]], [[ST]]** [[ADDR0]], diff --git a/clang/test/OpenMP/target_map_codegen_14.cpp b/clang/test/OpenMP/target_map_codegen_14.cpp index e08c2361cbd8b833d5dcc8f45eb1dedf47b6ab7b..db8acf5c3bb3908fb3e2c0402f6eaae979887278 100644 --- a/clang/test/OpenMP/target_map_codegen_14.cpp +++ b/clang/test/OpenMP/target_map_codegen_14.cpp @@ -172,7 +172,7 @@ void implicit_maps_templated_class (int a){ ssst.bar<210>(789); } -// CK15: define internal void [[KERNEL]]([[ST]]* noundef [[THIS:%.+]], i[[sz]] noundef [[ARG:%.+]]) +// CK15: define internal void [[KERNEL]]([[ST]]* [[THIS:%.+]], i[[sz]] [[ARG:%.+]]) // CK15: [[ADDR0:%.+]] = alloca [[ST]]*, // CK15: [[ADDR1:%.+]] = alloca i[[sz]], // CK15: store [[ST]]* [[THIS]], [[ST]]** [[ADDR0]], @@ -183,7 +183,7 @@ void implicit_maps_templated_class (int a){ // CK15-32: {{.+}} = load i32, i32* [[ADDR1]], // CK15: {{.+}} = getelementptr inbounds [[ST]], [[ST]]* [[REF0]], i32 0, i32 0 -// CK15: define internal void [[KERNEL2]]([[ST]]* noundef [[THIS:%.+]], i[[sz]] noundef [[ARG:%.+]]) +// CK15: define internal void [[KERNEL2]]([[ST]]* [[THIS:%.+]], i[[sz]] [[ARG:%.+]]) // CK15: [[ADDR0:%.+]] = alloca [[ST]]*, // CK15: [[ADDR1:%.+]] = alloca i[[sz]], // CK15: store [[ST]]* [[THIS]], [[ST]]** [[ADDR0]], diff --git a/clang/test/OpenMP/target_map_codegen_15.cpp b/clang/test/OpenMP/target_map_codegen_15.cpp index 5e6bec97fb085fa117ef362da4f4a139a0b6a034..44eff760a6e543b6d73c5c6042f07f18079b8104 100644 --- a/clang/test/OpenMP/target_map_codegen_15.cpp +++ b/clang/test/OpenMP/target_map_codegen_15.cpp @@ -69,7 +69,7 @@ void implicit_maps_templated_function (int a){ // CK16: call void [[KERNEL:@.+]](i[[sz]] [[VAL]]) i = foo<543>(i); } -// CK16: define internal void [[KERNEL]](i[[sz]] noundef [[ARG:%.+]]) +// CK16: define internal void [[KERNEL]](i[[sz]] [[ARG:%.+]]) // CK16: [[ADDR:%.+]] = alloca i[[sz]], // CK16: store i[[sz]] [[ARG]], i[[sz]]* [[ADDR]], // CK16-64: [[CADDR:%.+]] = bitcast i64* [[ADDR]] to i32* diff --git a/clang/test/OpenMP/target_map_codegen_17.cpp b/clang/test/OpenMP/target_map_codegen_17.cpp index eaa688181294a863b2610b89673ae63c16046ede..df3c192b94847b3b2ca7d04c7e3ddc385746326c 100644 --- a/clang/test/OpenMP/target_map_codegen_17.cpp +++ b/clang/test/OpenMP/target_map_codegen_17.cpp @@ -68,7 +68,7 @@ void implicit_maps_template_type_capture (int a){ // CK18: call void [[KERNEL:@.+]](i[[sz]] [[VAL]]) i = foo(i); } -// CK18: define internal void [[KERNEL]](i[[sz]] noundef [[ARG:%.+]]) +// CK18: define internal void [[KERNEL]](i[[sz]] [[ARG:%.+]]) // CK18: [[ADDR:%.+]] = alloca i[[sz]], // CK18: store i[[sz]] [[ARG]], i[[sz]]* [[ADDR]], // CK18-64: [[CADDR:%.+]] = bitcast i64* [[ADDR]] to i32* diff --git a/clang/test/OpenMP/target_map_codegen_24.cpp b/clang/test/OpenMP/target_map_codegen_24.cpp index b26e2d4731d9db176de676cb52dd74f5aaf39f91..73f9a509daf7143f87c9f567a1a526d2ecb149c5 100644 --- a/clang/test/OpenMP/target_map_codegen_24.cpp +++ b/clang/test/OpenMP/target_map_codegen_24.cpp @@ -102,7 +102,7 @@ int explicit_maps_with_inner_lambda(int a){ return c.foo(a); } -// CK25: define {{.+}}[[CALL00]]([[ST]]* noundef [[VAL:%.+]]) +// CK25: define {{.+}}[[CALL00]]([[ST]]* [[VAL:%.+]]) // CK25: store [[ST]]* [[VAL]], [[ST]]** [[VALADDR:%[^,]+]], // CK25: [[VAL1:%.+]] = load [[ST]]*, [[ST]]** [[VALADDR]], // CK25: [[VALADDR1:%.+]] = getelementptr inbounds [[CA00]], [[CA00]]* [[CA:%[^,]+]], i32 0, i32 0 diff --git a/clang/test/OpenMP/target_map_names.cpp b/clang/test/OpenMP/target_map_names.cpp index 5178a27e546e4d97a745ad7979d0db6226e17224..92340cd68891e6287a7b5bd67e8d39dd3bb4f38c 100644 --- a/clang/test/OpenMP/target_map_names.cpp +++ b/clang/test/OpenMP/target_map_names.cpp @@ -221,7 +221,7 @@ void secondMapNameInClause() { // CHECK: call void @__tgt_target_data_update_nowait_mapper(%struct.ident_t* @{{.+}}, i64 -1, i32 1, i8** %{{.+}}, i8** %{{.+}}, i64* {{.+}}, i64* {{.+}}, i8** null, i8** {{.+}}) -// DEBUG: void @.omp_mapper._ZTS2S3.id(i8* {{.*}}, i8* {{.*}}, i8* {{.*}}, i64 {{.*}}, i64 {{.*}}, i8* noundef [[NAME_ARG:%.+]]) +// DEBUG: void @.omp_mapper._ZTS2S3.id(i8* {{.*}}, i8* {{.*}}, i8* {{.*}}, i64 {{.*}}, i64 {{.*}}, i8* [[NAME_ARG:%.+]]) // DEBUG: store i8* [[NAME_ARG]], i8** [[NAME_STACK:%.+]] // DEBUG: [[MAPPER_NAME:%.+]] = load i8*, i8** [[NAME_STACK]] // DEBUG: call void @__tgt_push_mapper_component(i8* %{{.*}}, i8* %{{.*}}, i8* %{{.*}}, i64 %{{.*}}, i64 %{{.*}}, i8* [[MAPPER_NAME]]) diff --git a/clang/test/OpenMP/target_map_names_attr.cpp b/clang/test/OpenMP/target_map_names_attr.cpp index 424204892ee0c6ee986558d50f69c350eaedb244..c45e7c8b996bb7e06f48c2d0cba6ecc71f0dcd68 100644 --- a/clang/test/OpenMP/target_map_names_attr.cpp +++ b/clang/test/OpenMP/target_map_names_attr.cpp @@ -206,7 +206,7 @@ void secondMapNameInClause() { // CHECK: call void @__tgt_target_data_update_nowait_mapper(%struct.ident_t* @{{.+}}, i64 -1, i32 1, i8** %{{.+}}, i8** %{{.+}}, i64* {{.+}}, i64* {{.+}}, i8** null, i8** {{.+}}) -// DEBUG: void @.omp_mapper._ZTS2S3.id(i8* {{.*}}, i8* {{.*}}, i8* {{.*}}, i64 {{.*}}, i64 {{.*}}, i8* noundef [[NAME_ARG:%.+]]) +// DEBUG: void @.omp_mapper._ZTS2S3.id(i8* {{.*}}, i8* {{.*}}, i8* {{.*}}, i64 {{.*}}, i64 {{.*}}, i8* [[NAME_ARG:%.+]]) // DEBUG: store i8* [[NAME_ARG]], i8** [[NAME_STACK:%.+]] // DEBUG: [[MAPPER_NAME:%.+]] = load i8*, i8** [[NAME_STACK]] // DEBUG: call void @__tgt_push_mapper_component(i8* %{{.*}}, i8* %{{.*}}, i8* %{{.*}}, i64 %{{.*}}, i64 %{{.*}}, i8* [[MAPPER_NAME]]) diff --git a/clang/test/OpenMP/target_parallel_codegen.cpp b/clang/test/OpenMP/target_parallel_codegen.cpp index ede3adacc1217e3b12e2777fa48f5125a2b0dd9f..012198a5ee7f11b4b013f8f9763f582df8478ef1 100644 --- a/clang/test/OpenMP/target_parallel_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_codegen.cpp @@ -292,7 +292,7 @@ int bar(int n){ #endif // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -536,7 +536,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -546,7 +546,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -588,7 +588,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -603,7 +603,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -619,7 +619,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -634,7 +634,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -661,7 +661,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -684,7 +684,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -708,7 +708,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -747,7 +747,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -820,7 +820,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z3bari -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -828,22 +828,22 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK1-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -852,7 +852,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -966,7 +966,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1050,7 +1050,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1119,7 +1119,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1146,7 +1146,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1185,7 +1185,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -1219,7 +1219,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1258,7 +1258,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -1284,7 +1284,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1322,7 +1322,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1566,7 +1566,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1576,7 +1576,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1618,7 +1618,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK2-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -1633,7 +1633,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1649,7 +1649,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK2-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -1664,7 +1664,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1691,7 +1691,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -1714,7 +1714,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1738,7 +1738,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK2-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -1777,7 +1777,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1850,7 +1850,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3bari -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1858,22 +1858,22 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK2-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -1882,7 +1882,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1996,7 +1996,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2080,7 +2080,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2149,7 +2149,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2176,7 +2176,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2215,7 +2215,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -2249,7 +2249,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2288,7 +2288,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -2314,7 +2314,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2352,7 +2352,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2593,7 +2593,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2603,7 +2603,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -2645,7 +2645,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -2658,7 +2658,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2673,7 +2673,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -2688,7 +2688,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2715,7 +2715,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -2736,7 +2736,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2759,7 +2759,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -2796,7 +2796,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2868,7 +2868,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3bari -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2876,22 +2876,22 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK3-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -2900,7 +2900,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -3013,7 +3013,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3096,7 +3096,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3164,7 +3164,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3189,7 +3189,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3227,7 +3227,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -3259,7 +3259,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3297,7 +3297,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -3321,7 +3321,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3358,7 +3358,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3599,7 +3599,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3609,7 +3609,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -3651,7 +3651,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK4-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -3664,7 +3664,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3679,7 +3679,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK4-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -3694,7 +3694,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3721,7 +3721,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -3742,7 +3742,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3765,7 +3765,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK4-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -3802,7 +3802,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3874,7 +3874,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3bari -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3882,22 +3882,22 @@ int bar(int n){ // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK4-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK4-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -3906,7 +3906,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -4019,7 +4019,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4102,7 +4102,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4170,7 +4170,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4195,7 +4195,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4233,7 +4233,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4265,7 +4265,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4303,7 +4303,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4327,7 +4327,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4371,7 +4371,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4381,7 +4381,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -4396,7 +4396,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4423,7 +4423,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -4446,7 +4446,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4470,7 +4470,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -4509,7 +4509,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4582,7 +4582,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -4616,7 +4616,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4655,7 +4655,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4682,7 +4682,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4721,7 +4721,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -4747,7 +4747,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4785,7 +4785,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4795,7 +4795,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK10-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -4810,7 +4810,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4837,7 +4837,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -4860,7 +4860,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4884,7 +4884,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK10-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -4923,7 +4923,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4996,7 +4996,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -5030,7 +5030,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5069,7 +5069,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -5096,7 +5096,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5135,7 +5135,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -5161,7 +5161,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5199,7 +5199,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5209,7 +5209,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -5224,7 +5224,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5251,7 +5251,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5272,7 +5272,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5295,7 +5295,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -5332,7 +5332,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5404,7 +5404,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5436,7 +5436,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5474,7 +5474,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5499,7 +5499,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5537,7 +5537,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5561,7 +5561,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5598,7 +5598,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5608,7 +5608,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK12-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -5623,7 +5623,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5650,7 +5650,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5671,7 +5671,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5694,7 +5694,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK12-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -5731,7 +5731,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5803,7 +5803,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5835,7 +5835,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5873,7 +5873,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5898,7 +5898,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5936,7 +5936,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5960,7 +5960,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5990,7 +5990,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6234,7 +6234,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6244,7 +6244,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK17-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -6286,7 +6286,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK17-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -6301,7 +6301,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6317,7 +6317,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -6332,7 +6332,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6359,7 +6359,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -6382,7 +6382,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6406,7 +6406,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -6445,7 +6445,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6518,7 +6518,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6526,22 +6526,22 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK17-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -6550,7 +6550,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -6664,7 +6664,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6748,7 +6748,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6817,7 +6817,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -6844,7 +6844,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6883,7 +6883,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -6917,7 +6917,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6956,7 +6956,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -6982,7 +6982,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7020,7 +7020,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -7264,7 +7264,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7274,7 +7274,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK18-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK18-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -7316,7 +7316,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK18-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -7331,7 +7331,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7347,7 +7347,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK18-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -7362,7 +7362,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7389,7 +7389,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -7412,7 +7412,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7436,7 +7436,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK18-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -7475,7 +7475,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7548,7 +7548,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -7556,22 +7556,22 @@ int bar(int n){ // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK18-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -7580,7 +7580,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -7694,7 +7694,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -7778,7 +7778,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -7847,7 +7847,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -7874,7 +7874,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7913,7 +7913,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -7947,7 +7947,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7986,7 +7986,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -8012,7 +8012,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8050,7 +8050,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -8291,7 +8291,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8301,7 +8301,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK19-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK19-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -8343,7 +8343,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK19-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -8356,7 +8356,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8371,7 +8371,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -8386,7 +8386,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8413,7 +8413,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -8434,7 +8434,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8457,7 +8457,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -8494,7 +8494,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8566,7 +8566,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -8574,22 +8574,22 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK19-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -8598,7 +8598,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -8711,7 +8711,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -8794,7 +8794,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -8862,7 +8862,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -8887,7 +8887,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8925,7 +8925,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -8957,7 +8957,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8995,7 +8995,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -9019,7 +9019,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9056,7 +9056,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -9297,7 +9297,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9307,7 +9307,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK20-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK20-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -9349,7 +9349,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK20-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -9362,7 +9362,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9377,7 +9377,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK20-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -9392,7 +9392,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9419,7 +9419,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -9440,7 +9440,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9463,7 +9463,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -9500,7 +9500,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9572,7 +9572,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -9580,22 +9580,22 @@ int bar(int n){ // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK20-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -9604,7 +9604,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -9717,7 +9717,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -9800,7 +9800,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -9868,7 +9868,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -9893,7 +9893,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9931,7 +9931,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -9963,7 +9963,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10001,7 +10001,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -10025,7 +10025,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10069,7 +10069,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10079,7 +10079,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK25-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -10094,7 +10094,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10121,7 +10121,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -10144,7 +10144,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10168,7 +10168,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK25-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -10207,7 +10207,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10280,7 +10280,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -10314,7 +10314,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10353,7 +10353,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -10380,7 +10380,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10419,7 +10419,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -10445,7 +10445,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10483,7 +10483,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10493,7 +10493,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK26-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -10508,7 +10508,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10535,7 +10535,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -10558,7 +10558,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10582,7 +10582,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK26-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -10621,7 +10621,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10694,7 +10694,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -10728,7 +10728,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10767,7 +10767,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -10794,7 +10794,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10833,7 +10833,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -10859,7 +10859,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10897,7 +10897,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10907,7 +10907,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK27-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -10922,7 +10922,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10949,7 +10949,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -10970,7 +10970,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10993,7 +10993,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK27-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -11030,7 +11030,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11102,7 +11102,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11134,7 +11134,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11172,7 +11172,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -11197,7 +11197,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11235,7 +11235,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11259,7 +11259,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11296,7 +11296,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11306,7 +11306,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK28-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -11321,7 +11321,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11348,7 +11348,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 -// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11369,7 +11369,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11392,7 +11392,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 -// CHECK28-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -11429,7 +11429,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11501,7 +11501,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 -// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11533,7 +11533,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11571,7 +11571,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -11596,7 +11596,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11634,7 +11634,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 -// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11658,7 +11658,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/target_parallel_debug_codegen.cpp b/clang/test/OpenMP/target_parallel_debug_codegen.cpp index 31f1585d4206d6ef66ca02688f7d64042604d8ca..81d1b14750c865518b56dfc7f1eb2106d443515e 100644 --- a/clang/test/OpenMP/target_parallel_debug_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_debug_codegen.cpp @@ -65,7 +65,7 @@ int main() { return 0; } // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug__ -// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]]* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG24:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]]* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG24:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -124,7 +124,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]]* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG52:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]]* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG52:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -219,7 +219,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG100:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG100:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -256,7 +256,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 -// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5:[0-9]+]] !dbg [[DBG115:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR4:[0-9]+]] !dbg [[DBG98:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -285,7 +285,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug__ -// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG124:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG124:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -345,7 +345,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG142:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG142:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -428,7 +428,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG183:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG183:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -466,7 +466,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37 -// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG192:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR4]] !dbg [[DBG168:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -496,7 +496,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug__ -// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 addrspace(1)* noalias noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG199:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 addrspace(1)* noalias [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG199:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32 addrspace(1)*, align 8 @@ -556,7 +556,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 addrspace(1)* noalias noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG217:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 addrspace(1)* noalias [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG217:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -648,7 +648,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG259:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG259:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -687,7 +687,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51 -// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG270:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR4]] !dbg [[DBG232:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/target_parallel_depend_codegen.cpp b/clang/test/OpenMP/target_parallel_depend_codegen.cpp index b081b45e662101d48d796f5e2156a2c2d98810e7..0f3aaf228f219a64b435783e1999bf07afb5a985 100644 --- a/clang/test/OpenMP/target_parallel_depend_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_depend_codegen.cpp @@ -182,7 +182,7 @@ int foo(int n) { // CHECK: define internal void [[HVT0:@.+]]() -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias %1) // CHECK: store void (i8*, ...)* null, void (i8*, ...)** % // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0 // CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]], @@ -196,9 +196,9 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* noundef %{{.+}}, i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* %{{.+}}, i[[SZ]] %{{.+}}) -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[SZT:%.+]] = getelementptr inbounds [2 x i64], [2 x i64]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0 @@ -221,7 +221,7 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2 @@ -234,7 +234,7 @@ int foo(int n) { // CHECK: call void [[HVT1]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]]) // CHECK: ret i32 0 -// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] %{{.+}}) // Create stack storage and store argument in there. // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align @@ -242,7 +242,7 @@ int foo(int n) { // CHECK-64: load i32, i32* [[AA_CADDR]], align // CHECK-32: load i32, i32* [[AA_ADDR]], align -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[BP1_I32:%.+]] = load i32, i32* % diff --git a/clang/test/OpenMP/target_parallel_for_codegen.cpp b/clang/test/OpenMP/target_parallel_for_codegen.cpp index 920d3248ddcd46935fd49a569d5727f7dcd142be..ea61220ba23f00360c429ed7c00be75987c7f0d7 100644 --- a/clang/test/OpenMP/target_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_codegen.cpp @@ -323,7 +323,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -379,7 +379,7 @@ int bar(int n){ // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK1-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK1-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* @@ -649,7 +649,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -726,7 +726,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 @@ -747,7 +747,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -831,7 +831,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -862,7 +862,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -893,7 +893,7 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK1-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -984,7 +984,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -1013,7 +1013,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1089,7 +1089,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -1112,7 +1112,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1187,7 +1187,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -1234,7 +1234,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1379,7 +1379,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z3bari -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1387,22 +1387,22 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK1-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -1411,7 +1411,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1525,7 +1525,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1609,7 +1609,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1678,7 +1678,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1705,7 +1705,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1794,7 +1794,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -1828,7 +1828,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1852,7 +1852,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -1878,7 +1878,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1972,7 +1972,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2028,7 +2028,7 @@ int bar(int n){ // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK2-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK2-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* @@ -2298,7 +2298,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2375,7 +2375,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 @@ -2396,7 +2396,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2480,7 +2480,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK2-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -2511,7 +2511,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2542,7 +2542,7 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK2-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK2-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK2-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -2633,7 +2633,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -2662,7 +2662,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2738,7 +2738,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -2761,7 +2761,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2836,7 +2836,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK2-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -2883,7 +2883,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3028,7 +3028,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3bari -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3036,22 +3036,22 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK2-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -3060,7 +3060,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -3174,7 +3174,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3258,7 +3258,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3327,7 +3327,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3354,7 +3354,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3443,7 +3443,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -3477,7 +3477,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3501,7 +3501,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -3527,7 +3527,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3621,7 +3621,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3674,7 +3674,7 @@ int bar(int n){ // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK3-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK3-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 @@ -3937,7 +3937,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4014,7 +4014,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 @@ -4030,7 +4030,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4114,7 +4114,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -4141,7 +4141,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4170,7 +4170,7 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK3-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK3-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -4261,7 +4261,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK3-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -4290,7 +4290,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -4364,7 +4364,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4385,7 +4385,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4459,7 +4459,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -4502,7 +4502,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4645,7 +4645,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3bari -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4653,22 +4653,22 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK3-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -4677,7 +4677,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -4790,7 +4790,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4873,7 +4873,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4941,7 +4941,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4966,7 +4966,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5054,7 +5054,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5086,7 +5086,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5109,7 +5109,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5133,7 +5133,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5226,7 +5226,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -5279,7 +5279,7 @@ int bar(int n){ // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK4-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK4-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 @@ -5542,7 +5542,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5619,7 +5619,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 @@ -5635,7 +5635,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5719,7 +5719,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK4-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -5746,7 +5746,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5775,7 +5775,7 @@ int bar(int n){ // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK4-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK4-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK4-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -5866,7 +5866,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK4-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK4-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -5895,7 +5895,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -5969,7 +5969,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5990,7 +5990,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6064,7 +6064,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK4-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -6107,7 +6107,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6250,7 +6250,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3bari -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6258,22 +6258,22 @@ int bar(int n){ // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK4-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK4-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -6282,7 +6282,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -6395,7 +6395,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6478,7 +6478,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6546,7 +6546,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -6571,7 +6571,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6659,7 +6659,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -6691,7 +6691,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6714,7 +6714,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -6738,7 +6738,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6832,7 +6832,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6909,7 +6909,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -6940,7 +6940,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6971,7 +6971,7 @@ int bar(int n){ // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK9-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK9-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -7068,7 +7068,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -7091,7 +7091,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7166,7 +7166,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -7213,7 +7213,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7358,7 +7358,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -7392,7 +7392,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7416,7 +7416,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -7443,7 +7443,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7532,7 +7532,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -7558,7 +7558,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7646,7 +7646,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7723,7 +7723,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK10-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -7754,7 +7754,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7785,7 +7785,7 @@ int bar(int n){ // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK10-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK10-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK10-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -7882,7 +7882,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -7905,7 +7905,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7980,7 +7980,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK10-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -8027,7 +8027,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8172,7 +8172,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -8206,7 +8206,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8230,7 +8230,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -8257,7 +8257,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8346,7 +8346,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -8372,7 +8372,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8460,7 +8460,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8537,7 +8537,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -8564,7 +8564,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8593,7 +8593,7 @@ int bar(int n){ // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK11-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK11-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -8690,7 +8690,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -8711,7 +8711,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8785,7 +8785,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -8828,7 +8828,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8971,7 +8971,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -9003,7 +9003,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9026,7 +9026,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -9051,7 +9051,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9139,7 +9139,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -9163,7 +9163,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9250,7 +9250,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9327,7 +9327,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK12-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -9354,7 +9354,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9383,7 +9383,7 @@ int bar(int n){ // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK12-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK12-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK12-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -9480,7 +9480,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -9501,7 +9501,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9575,7 +9575,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK12-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -9618,7 +9618,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9761,7 +9761,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -9793,7 +9793,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9816,7 +9816,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -9841,7 +9841,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9929,7 +9929,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -9953,7 +9953,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10039,7 +10039,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -10095,7 +10095,7 @@ int bar(int n){ // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK17: omp_offload.cont: -// CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK17-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK17-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* @@ -10365,7 +10365,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10442,7 +10442,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 @@ -10463,7 +10463,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10547,7 +10547,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -10578,7 +10578,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10609,7 +10609,7 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK17-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -10700,7 +10700,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK17-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK17-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -10729,7 +10729,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK17-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -10805,7 +10805,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -10828,7 +10828,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10903,7 +10903,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -10950,7 +10950,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11095,7 +11095,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -11103,22 +11103,22 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK17-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -11127,7 +11127,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -11241,7 +11241,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -11325,7 +11325,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -11394,7 +11394,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -11421,7 +11421,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11510,7 +11510,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -11544,7 +11544,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11568,7 +11568,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -11594,7 +11594,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11688,7 +11688,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -11744,7 +11744,7 @@ int bar(int n){ // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK18: omp_offload.cont: -// CHECK18-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK18-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK18-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* @@ -12014,7 +12014,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12091,7 +12091,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 @@ -12112,7 +12112,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12196,7 +12196,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK18-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -12227,7 +12227,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12258,7 +12258,7 @@ int bar(int n){ // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK18-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -12349,7 +12349,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK18-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK18-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -12378,7 +12378,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK18-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK18-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -12454,7 +12454,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -12477,7 +12477,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12552,7 +12552,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK18-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -12599,7 +12599,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12744,7 +12744,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -12752,22 +12752,22 @@ int bar(int n){ // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK18-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -12776,7 +12776,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -12890,7 +12890,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -12974,7 +12974,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -13043,7 +13043,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -13070,7 +13070,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13159,7 +13159,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -13193,7 +13193,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13217,7 +13217,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -13243,7 +13243,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13337,7 +13337,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -13390,7 +13390,7 @@ int bar(int n){ // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK19: omp_offload.cont: -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK19-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK19-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 @@ -13653,7 +13653,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13730,7 +13730,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 @@ -13746,7 +13746,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13830,7 +13830,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -13857,7 +13857,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13886,7 +13886,7 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK19-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK19-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -13977,7 +13977,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK19-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK19-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -14006,7 +14006,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK19-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK19-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -14080,7 +14080,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -14101,7 +14101,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14175,7 +14175,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -14218,7 +14218,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14361,7 +14361,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14369,22 +14369,22 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK19-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -14393,7 +14393,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -14506,7 +14506,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14589,7 +14589,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14657,7 +14657,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -14682,7 +14682,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14770,7 +14770,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -14802,7 +14802,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14825,7 +14825,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -14849,7 +14849,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14942,7 +14942,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14995,7 +14995,7 @@ int bar(int n){ // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]] // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK20: omp_offload.cont: -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK20-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK20-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4 @@ -15258,7 +15258,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15335,7 +15335,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 @@ -15351,7 +15351,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15435,7 +15435,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK20-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -15462,7 +15462,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15491,7 +15491,7 @@ int bar(int n){ // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK20-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK20-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -15582,7 +15582,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK20-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK20-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -15611,7 +15611,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK20-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK20-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -15685,7 +15685,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -15706,7 +15706,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15780,7 +15780,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -15823,7 +15823,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15966,7 +15966,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15974,22 +15974,22 @@ int bar(int n){ // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK20-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -15998,7 +15998,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -16111,7 +16111,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16194,7 +16194,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16262,7 +16262,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -16287,7 +16287,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16375,7 +16375,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -16407,7 +16407,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16430,7 +16430,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -16454,7 +16454,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16548,7 +16548,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16625,7 +16625,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK25-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -16656,7 +16656,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16687,7 +16687,7 @@ int bar(int n){ // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK25-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK25-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK25-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -16784,7 +16784,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -16807,7 +16807,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16882,7 +16882,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK25-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -16929,7 +16929,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17074,7 +17074,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -17108,7 +17108,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17132,7 +17132,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -17159,7 +17159,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17248,7 +17248,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -17274,7 +17274,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17362,7 +17362,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17439,7 +17439,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK26-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -17470,7 +17470,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17501,7 +17501,7 @@ int bar(int n){ // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK26-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK26-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK26-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -17598,7 +17598,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -17621,7 +17621,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17696,7 +17696,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK26-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -17743,7 +17743,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17888,7 +17888,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -17922,7 +17922,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17946,7 +17946,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -17973,7 +17973,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18062,7 +18062,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -18088,7 +18088,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18176,7 +18176,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18253,7 +18253,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK27-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -18280,7 +18280,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18309,7 +18309,7 @@ int bar(int n){ // CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK27-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK27-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK27-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK27-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -18406,7 +18406,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -18427,7 +18427,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18501,7 +18501,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK27-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -18544,7 +18544,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18687,7 +18687,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -18719,7 +18719,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18742,7 +18742,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -18767,7 +18767,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18855,7 +18855,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -18879,7 +18879,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18966,7 +18966,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19043,7 +19043,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138 -// CHECK28-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -19070,7 +19070,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19099,7 +19099,7 @@ int bar(int n){ // CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK28-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK28-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK28-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK28-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -19196,7 +19196,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146 -// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -19217,7 +19217,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19291,7 +19291,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170 -// CHECK28-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -19334,7 +19334,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19477,7 +19477,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224 -// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -19509,7 +19509,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19532,7 +19532,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242 -// CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -19557,7 +19557,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19645,7 +19645,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207 -// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -19669,7 +19669,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp b/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp index a9cd100ea7a9973944bd8894a49b0a8eeadc4397..87d1dfdd170f7cf926be7c99f3a9a0c5d01fd7dd 100644 --- a/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_debug_codegen.cpp @@ -55,7 +55,7 @@ int main() { return 0; } // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug__ -// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]]* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]], i1 noundef zeroext [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG14:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]]* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]], i1 zeroext [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG14:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -121,7 +121,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]]* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG47:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]]* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG47:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -289,7 +289,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG108:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG108:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -326,7 +326,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13 -// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR5:[0-9]+]] !dbg [[DBG123:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] !dbg [[DBG106:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -361,7 +361,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__ -// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG133:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG133:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -421,7 +421,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG151:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG151:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -577,7 +577,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG205:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG205:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -615,7 +615,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27 -// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 noundef [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG214:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR4]] !dbg [[DBG190:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -645,7 +645,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__ -// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 addrspace(1)* noalias noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG223:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 addrspace(1)* noalias [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG223:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32 addrspace(1)*, align 8 @@ -705,7 +705,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___debug__3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias noundef [[C:%.*]], i32 addrspace(1)* noalias noundef [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias noundef [[B:%.*]], i8 addrspace(1)* noalias noundef [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG241:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 addrspace(1)* noalias [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG241:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -870,7 +870,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG296:![0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG296:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -909,7 +909,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 -// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* noundef nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* noundef nonnull align 4 dereferenceable(400) [[B:%.*]], i8* noundef nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR5]] !dbg [[DBG307:![0-9]+]] { +// CHECK1-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR4]] !dbg [[DBG269:![0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/target_parallel_for_depend_codegen.cpp b/clang/test/OpenMP/target_parallel_for_depend_codegen.cpp index f66cbc6d95460e508202e367ac00025219ea0e46..1d0b8d13f22c02175e0c6deb4ee5543e1cd8e238 100644 --- a/clang/test/OpenMP/target_parallel_for_depend_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_depend_codegen.cpp @@ -177,7 +177,7 @@ int foo(int n) { // CHECK: define internal void [[HVT0:@.+]]() -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias %1) // CHECK: store void (i8*, ...)* null, void (i8*, ...)** % // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0 // CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]], @@ -191,9 +191,9 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* noundef %{{.+}}, i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* %{{.+}}, i[[SZ]] %{{.+}}) -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[SZT:%.+]] = getelementptr inbounds [2 x i64], [2 x i64]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0 @@ -216,7 +216,7 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2 @@ -229,7 +229,7 @@ int foo(int n) { // CHECK: call void [[HVT1]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]]) // CHECK: ret i32 0 -// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] %{{.+}}) // Create stack storage and store argument in there. // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align @@ -237,7 +237,7 @@ int foo(int n) { // CHECK-64: load i32, i32* [[AA_CADDR]], align // CHECK-32: load i32, i32* [[AA_ADDR]], align -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[BP1_I32:%.+]] = load i32, i32* % diff --git a/clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp index f0c0a902b4140c1c0cf7c208616429624d0f3114..f0aca4928a72d3c3ec5321c17633d95f1daba260 100644 --- a/clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp @@ -36,7 +36,7 @@ int main(int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -48,7 +48,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -61,7 +61,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -342,7 +342,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init. -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -355,7 +355,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -373,7 +373,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -395,7 +395,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -426,7 +426,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -440,7 +440,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -524,7 +524,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -573,7 +573,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -585,7 +585,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -598,7 +598,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -879,7 +879,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init. -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -892,7 +892,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -910,7 +910,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -932,7 +932,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -963,7 +963,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -977,7 +977,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1061,7 +1061,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 diff --git a/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp index ff4bc2f9d10a42d9165c00027baf85d17e063b94..5d8479ee7405e8108f98fdcd40977f915dd26c4d 100644 --- a/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp @@ -300,7 +300,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -353,7 +353,7 @@ int bar(int n){ // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]]) -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK1-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK1-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* @@ -597,7 +597,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -664,7 +664,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -706,7 +706,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 @@ -727,7 +727,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -818,7 +818,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -849,7 +849,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -880,7 +880,7 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK1-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -978,7 +978,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -1001,7 +1001,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1083,7 +1083,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -1130,7 +1130,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1282,7 +1282,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z3bari -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1290,22 +1290,22 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK1-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -1314,7 +1314,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1428,7 +1428,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1512,7 +1512,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1581,7 +1581,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1608,7 +1608,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1704,7 +1704,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -1738,7 +1738,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1762,7 +1762,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -1788,7 +1788,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1889,7 +1889,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1942,7 +1942,7 @@ int bar(int n){ // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 // CHECK2-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]]) -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK2-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK2-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* @@ -2186,7 +2186,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2253,7 +2253,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2295,7 +2295,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 @@ -2316,7 +2316,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2407,7 +2407,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK2-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -2438,7 +2438,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2469,7 +2469,7 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK2-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK2-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK2-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -2567,7 +2567,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -2590,7 +2590,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2672,7 +2672,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK2-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -2719,7 +2719,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2871,7 +2871,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3bari -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2879,22 +2879,22 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK2-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -2903,7 +2903,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -3017,7 +3017,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3101,7 +3101,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3170,7 +3170,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3197,7 +3197,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3293,7 +3293,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -3327,7 +3327,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3351,7 +3351,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -3377,7 +3377,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3478,7 +3478,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3528,7 +3528,7 @@ int bar(int n){ // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]]) -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK3-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK3-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 @@ -3765,7 +3765,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3832,7 +3832,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -3874,7 +3874,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 @@ -3890,7 +3890,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3981,7 +3981,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -4008,7 +4008,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4037,7 +4037,7 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK3-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK3-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -4135,7 +4135,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4156,7 +4156,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4237,7 +4237,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -4280,7 +4280,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4430,7 +4430,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3bari -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4438,22 +4438,22 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK3-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -4462,7 +4462,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -4575,7 +4575,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4658,7 +4658,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4726,7 +4726,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4751,7 +4751,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4846,7 +4846,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4878,7 +4878,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4901,7 +4901,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4925,7 +4925,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5025,7 +5025,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -5075,7 +5075,7 @@ int bar(int n){ // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 // CHECK4-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]]) -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK4-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK4-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 @@ -5312,7 +5312,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5379,7 +5379,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -5421,7 +5421,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 @@ -5437,7 +5437,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5528,7 +5528,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK4-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -5555,7 +5555,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5584,7 +5584,7 @@ int bar(int n){ // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK4-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK4-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK4-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -5682,7 +5682,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5703,7 +5703,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5784,7 +5784,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK4-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -5827,7 +5827,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5977,7 +5977,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3bari -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -5985,22 +5985,22 @@ int bar(int n){ // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK4-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK4-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -6009,7 +6009,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -6122,7 +6122,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6205,7 +6205,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6273,7 +6273,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -6298,7 +6298,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6393,7 +6393,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -6425,7 +6425,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6448,7 +6448,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -6472,7 +6472,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6572,7 +6572,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6625,7 +6625,7 @@ int bar(int n){ // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 // CHECK5-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]]) -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK5-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK5-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* @@ -6869,7 +6869,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6936,7 +6936,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK5-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -6978,7 +6978,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 @@ -6999,7 +6999,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7090,7 +7090,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK5-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -7121,7 +7121,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7152,7 +7152,7 @@ int bar(int n){ // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK5-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK5-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK5-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -7250,7 +7250,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -7273,7 +7273,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7355,7 +7355,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK5-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -7402,7 +7402,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7554,7 +7554,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -7562,22 +7562,22 @@ int bar(int n){ // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK5-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -7586,7 +7586,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -7725,7 +7725,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -7809,7 +7809,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -7878,7 +7878,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 -// CHECK5-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -7931,7 +7931,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8090,7 +8090,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -8124,7 +8124,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8148,7 +8148,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -8174,7 +8174,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8275,7 +8275,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK6-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -8328,7 +8328,7 @@ int bar(int n){ // CHECK6-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 // CHECK6-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]]) -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK6-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK6-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* @@ -8572,7 +8572,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8639,7 +8639,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK6-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK6-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -8681,7 +8681,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK6-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 @@ -8702,7 +8702,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[K:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8793,7 +8793,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK6-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -8824,7 +8824,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8855,7 +8855,7 @@ int bar(int n){ // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK6-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK6-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK6-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -8953,7 +8953,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK6-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -8976,7 +8976,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9058,7 +9058,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK6-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -9105,7 +9105,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9257,7 +9257,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -9265,22 +9265,22 @@ int bar(int n){ // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK6-NEXT: store i32 0, i32* [[A]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK6-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK6-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -9289,7 +9289,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -9428,7 +9428,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -9512,7 +9512,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -9581,7 +9581,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 -// CHECK6-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -9634,7 +9634,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9793,7 +9793,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK6-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -9827,7 +9827,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9851,7 +9851,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK6-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -9877,7 +9877,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9978,7 +9978,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -10028,7 +10028,7 @@ int bar(int n){ // CHECK7-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 // CHECK7-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]]) -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK7-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK7-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 // CHECK7-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 @@ -10265,7 +10265,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10332,7 +10332,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK7-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK7-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -10374,7 +10374,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK7-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 @@ -10390,7 +10390,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10481,7 +10481,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK7-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -10508,7 +10508,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10537,7 +10537,7 @@ int bar(int n){ // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK7-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK7-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK7-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -10635,7 +10635,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -10656,7 +10656,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10737,7 +10737,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK7-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -10780,7 +10780,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10930,7 +10930,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -10938,22 +10938,22 @@ int bar(int n){ // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK7-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -10962,7 +10962,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -11100,7 +11100,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -11183,7 +11183,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -11251,7 +11251,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 -// CHECK7-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -11302,7 +11302,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11460,7 +11460,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11492,7 +11492,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11515,7 +11515,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11539,7 +11539,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11639,7 +11639,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK8-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -11689,7 +11689,7 @@ int bar(int n){ // CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* // CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 // CHECK8-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]]) -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK8-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK8-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 // CHECK8-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 @@ -11926,7 +11926,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11993,7 +11993,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK8-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK8-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -12035,7 +12035,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK8-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 @@ -12051,7 +12051,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12142,7 +12142,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK8-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -12169,7 +12169,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12198,7 +12198,7 @@ int bar(int n){ // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK8-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK8-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK8-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK8-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -12296,7 +12296,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK8-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -12317,7 +12317,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12398,7 +12398,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK8-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -12441,7 +12441,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12591,7 +12591,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -12599,22 +12599,22 @@ int bar(int n){ // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK8-NEXT: store i32 0, i32* [[A]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK8-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK8-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -12623,7 +12623,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -12761,7 +12761,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -12844,7 +12844,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -12912,7 +12912,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 -// CHECK8-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -12963,7 +12963,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13121,7 +13121,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK8-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -13153,7 +13153,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13176,7 +13176,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK8-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -13200,7 +13200,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13300,7 +13300,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -13385,7 +13385,7 @@ int bar(int n){ // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK9-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK9-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK9-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -13435,7 +13435,7 @@ int bar(int n){ // CHECK9-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 // CHECK9-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK9-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK9-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK9-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK9: omp.inner.for.cond30: @@ -13598,7 +13598,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@_Z3bari -// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -13606,22 +13606,22 @@ int bar(int n){ // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK9-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK9-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK9-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK9-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK9-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK9-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK9-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK9-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK9-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK9-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -13630,7 +13630,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -13707,7 +13707,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -13728,7 +13728,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -13790,7 +13790,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK10-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -13875,7 +13875,7 @@ int bar(int n){ // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK10-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK10-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK10-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -13925,7 +13925,7 @@ int bar(int n){ // CHECK10-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 // CHECK10-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK10-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK10-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK10-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK10: omp.inner.for.cond30: @@ -14088,7 +14088,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@_Z3bari -// CHECK10-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14096,22 +14096,22 @@ int bar(int n){ // CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK10-NEXT: store i32 0, i32* [[A]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK10-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK10-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK10-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK10-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK10-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK10-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK10-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK10-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK10-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK10-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -14120,7 +14120,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK10-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -14197,7 +14197,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK10-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14218,7 +14218,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK10-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14280,7 +14280,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14363,7 +14363,7 @@ int bar(int n){ // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK11-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK11-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK11-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -14413,7 +14413,7 @@ int bar(int n){ // CHECK11-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 // CHECK11-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK11-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK11-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK11-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK11: omp.inner.for.cond30: @@ -14576,7 +14576,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@_Z3bari -// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14584,22 +14584,22 @@ int bar(int n){ // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK11-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK11-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK11-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK11-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -14608,7 +14608,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK11-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -14684,7 +14684,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14705,7 +14705,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14767,7 +14767,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14850,7 +14850,7 @@ int bar(int n){ // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK12-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK12-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK12-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -14900,7 +14900,7 @@ int bar(int n){ // CHECK12-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4 // CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 // CHECK12-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK12-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK12-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK12-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK12: omp.inner.for.cond30: @@ -15063,7 +15063,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@_Z3bari -// CHECK12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15071,22 +15071,22 @@ int bar(int n){ // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK12-NEXT: store i32 0, i32* [[A]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK12-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK12-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK12-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK12-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK12-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK12-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK12-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -15095,7 +15095,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK12-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -15171,7 +15171,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15192,7 +15192,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15254,7 +15254,7 @@ int bar(int n){ // // // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15339,7 +15339,7 @@ int bar(int n){ // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK13-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK13-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK13-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -15389,7 +15389,7 @@ int bar(int n){ // CHECK13-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 // CHECK13-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK13-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK13-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK13-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK13: omp.inner.for.cond30: @@ -15552,7 +15552,7 @@ int bar(int n){ // // // CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15560,22 +15560,22 @@ int bar(int n){ // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK13-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -15584,7 +15584,7 @@ int bar(int n){ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -15708,7 +15708,7 @@ int bar(int n){ // // // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15729,7 +15729,7 @@ int bar(int n){ // // // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15791,7 +15791,7 @@ int bar(int n){ // // // CHECK14-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK14-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15876,7 +15876,7 @@ int bar(int n){ // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK14-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK14-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK14-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -15926,7 +15926,7 @@ int bar(int n){ // CHECK14-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4 // CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 // CHECK14-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK14-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK14-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK14-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK14: omp.inner.for.cond30: @@ -16089,7 +16089,7 @@ int bar(int n){ // // // CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16097,22 +16097,22 @@ int bar(int n){ // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK14-NEXT: store i32 0, i32* [[A]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK14-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK14-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -16121,7 +16121,7 @@ int bar(int n){ // // // CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -16245,7 +16245,7 @@ int bar(int n){ // // // CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16266,7 +16266,7 @@ int bar(int n){ // // // CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16328,7 +16328,7 @@ int bar(int n){ // // // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16411,7 +16411,7 @@ int bar(int n){ // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK15-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK15-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK15-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -16461,7 +16461,7 @@ int bar(int n){ // CHECK15-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 // CHECK15-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK15-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK15-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK15-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK15: omp.inner.for.cond30: @@ -16624,7 +16624,7 @@ int bar(int n){ // // // CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16632,22 +16632,22 @@ int bar(int n){ // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK15-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -16656,7 +16656,7 @@ int bar(int n){ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -16779,7 +16779,7 @@ int bar(int n){ // // // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16800,7 +16800,7 @@ int bar(int n){ // // // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16862,7 +16862,7 @@ int bar(int n){ // // // CHECK16-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK16-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16945,7 +16945,7 @@ int bar(int n){ // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK16-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK16-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK16-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -16995,7 +16995,7 @@ int bar(int n){ // CHECK16-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4 // CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 // CHECK16-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK16-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK16-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK16-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK16: omp.inner.for.cond30: @@ -17158,7 +17158,7 @@ int bar(int n){ // // // CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -17166,22 +17166,22 @@ int bar(int n){ // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK16-NEXT: store i32 0, i32* [[A]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK16-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK16-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -17190,7 +17190,7 @@ int bar(int n){ // // // CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -17313,7 +17313,7 @@ int bar(int n){ // // // CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -17334,7 +17334,7 @@ int bar(int n){ // // // CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -17397,7 +17397,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17464,7 +17464,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -17495,7 +17495,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17526,7 +17526,7 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK17-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -17630,7 +17630,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -17653,7 +17653,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17735,7 +17735,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -17782,7 +17782,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17934,7 +17934,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -17968,7 +17968,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17992,7 +17992,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -18019,7 +18019,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18115,7 +18115,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -18141,7 +18141,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18236,7 +18236,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18303,7 +18303,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK18-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -18334,7 +18334,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18365,7 +18365,7 @@ int bar(int n){ // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK18-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -18469,7 +18469,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -18492,7 +18492,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18574,7 +18574,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK18-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -18621,7 +18621,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18773,7 +18773,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -18807,7 +18807,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18831,7 +18831,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -18858,7 +18858,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18954,7 +18954,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -18980,7 +18980,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19075,7 +19075,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19142,7 +19142,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -19169,7 +19169,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19198,7 +19198,7 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK19-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK19-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -19302,7 +19302,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -19323,7 +19323,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19404,7 +19404,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -19447,7 +19447,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19597,7 +19597,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -19629,7 +19629,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19652,7 +19652,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -19677,7 +19677,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19772,7 +19772,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -19796,7 +19796,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19890,7 +19890,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19957,7 +19957,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK20-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -19984,7 +19984,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20013,7 +20013,7 @@ int bar(int n){ // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK20-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK20-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -20117,7 +20117,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -20138,7 +20138,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20219,7 +20219,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -20262,7 +20262,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20412,7 +20412,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -20444,7 +20444,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20467,7 +20467,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -20492,7 +20492,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20587,7 +20587,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -20611,7 +20611,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20705,7 +20705,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20772,7 +20772,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK21-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -20803,7 +20803,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20834,7 +20834,7 @@ int bar(int n){ // CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK21-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK21-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK21-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -20938,7 +20938,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -20961,7 +20961,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21043,7 +21043,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK21-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -21090,7 +21090,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21242,7 +21242,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -21276,7 +21276,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21300,7 +21300,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 -// CHECK21-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -21353,7 +21353,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21512,7 +21512,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -21538,7 +21538,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21633,7 +21633,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21700,7 +21700,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK22-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 @@ -21731,7 +21731,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]], i64 [[LIN:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21762,7 +21762,7 @@ int bar(int n){ // CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK22-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK22-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK22-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK22-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK22-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -21866,7 +21866,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK22-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -21889,7 +21889,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21971,7 +21971,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK22-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -22018,7 +22018,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22170,7 +22170,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK22-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -22204,7 +22204,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22228,7 +22228,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 -// CHECK22-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -22281,7 +22281,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22440,7 +22440,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK22-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -22466,7 +22466,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22561,7 +22561,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22628,7 +22628,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK23-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -22655,7 +22655,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22684,7 +22684,7 @@ int bar(int n){ // CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK23-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK23-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK23-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK23-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -22788,7 +22788,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -22809,7 +22809,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22890,7 +22890,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK23-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -22933,7 +22933,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23083,7 +23083,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -23115,7 +23115,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23138,7 +23138,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 -// CHECK23-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -23189,7 +23189,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23347,7 +23347,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -23371,7 +23371,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23465,7 +23465,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23532,7 +23532,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 -// CHECK24-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 @@ -23559,7 +23559,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]], i32 [[LIN:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23588,7 +23588,7 @@ int bar(int n){ // CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK24-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] +// CHECK24-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] // CHECK24-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK24-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 // CHECK24-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 @@ -23692,7 +23692,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 -// CHECK24-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -23713,7 +23713,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23794,7 +23794,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 -// CHECK24-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -23837,7 +23837,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23987,7 +23987,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 -// CHECK24-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -24019,7 +24019,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24042,7 +24042,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 -// CHECK24-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -24093,7 +24093,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24251,7 +24251,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 -// CHECK24-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -24275,7 +24275,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24368,7 +24368,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -24453,7 +24453,7 @@ int bar(int n){ // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK25: omp.inner.for.end: // CHECK25-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK25-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK25-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK25-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK25-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -24503,7 +24503,7 @@ int bar(int n){ // CHECK25-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4 // CHECK25-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 // CHECK25-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK25-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK25-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK25-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK25: omp.inner.for.cond30: @@ -24666,7 +24666,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@_Z3bari -// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -24674,22 +24674,22 @@ int bar(int n){ // CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK25-NEXT: store i32 0, i32* [[A]], align 4 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK25-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK25-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK25-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK25-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK25-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK25-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK25-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK25-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK25-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK25-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK25-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK25-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK25-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -24698,7 +24698,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK25-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -24775,7 +24775,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -24796,7 +24796,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -24858,7 +24858,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -24943,7 +24943,7 @@ int bar(int n){ // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK26: omp.inner.for.end: // CHECK26-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK26-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK26-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK26-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK26-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -24993,7 +24993,7 @@ int bar(int n){ // CHECK26-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4 // CHECK26-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 // CHECK26-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK26-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK26-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK26-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK26: omp.inner.for.cond30: @@ -25156,7 +25156,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@_Z3bari -// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -25164,22 +25164,22 @@ int bar(int n){ // CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK26-NEXT: store i32 0, i32* [[A]], align 4 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK26-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK26-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK26-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK26-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK26-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK26-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK26-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK26-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK26-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK26-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK26-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK26-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK26-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK26-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -25188,7 +25188,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK26-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -25265,7 +25265,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -25286,7 +25286,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -25348,7 +25348,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -25431,7 +25431,7 @@ int bar(int n){ // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK27: omp.inner.for.end: // CHECK27-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK27-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK27-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK27-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK27-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -25481,7 +25481,7 @@ int bar(int n){ // CHECK27-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4 // CHECK27-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 // CHECK27-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK27-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK27-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK27-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK27: omp.inner.for.cond30: @@ -25644,7 +25644,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@_Z3bari -// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -25652,22 +25652,22 @@ int bar(int n){ // CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK27-NEXT: store i32 0, i32* [[A]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK27-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK27-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK27-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK27-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK27-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK27-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK27-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK27-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK27-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK27-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK27-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -25676,7 +25676,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK27-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -25752,7 +25752,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -25773,7 +25773,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -25835,7 +25835,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -25918,7 +25918,7 @@ int bar(int n){ // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK28: omp.inner.for.end: // CHECK28-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK28-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK28-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK28-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK28-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -25968,7 +25968,7 @@ int bar(int n){ // CHECK28-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4 // CHECK28-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 // CHECK28-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK28-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK28-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK28-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK28: omp.inner.for.cond30: @@ -26131,7 +26131,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@_Z3bari -// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26139,22 +26139,22 @@ int bar(int n){ // CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK28-NEXT: store i32 0, i32* [[A]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK28-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK28-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK28-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK28-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK28-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK28-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK28-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK28-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK28-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK28-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK28-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK28-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -26163,7 +26163,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK28-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -26239,7 +26239,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26260,7 +26260,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26322,7 +26322,7 @@ int bar(int n){ // // // CHECK29-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26407,7 +26407,7 @@ int bar(int n){ // CHECK29-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK29: omp.inner.for.end: // CHECK29-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK29-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK29-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK29-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK29-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -26457,7 +26457,7 @@ int bar(int n){ // CHECK29-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4 // CHECK29-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 // CHECK29-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK29-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK29-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK29-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK29-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK29: omp.inner.for.cond30: @@ -26620,7 +26620,7 @@ int bar(int n){ // // // CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26628,22 +26628,22 @@ int bar(int n){ // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK29-NEXT: store i32 0, i32* [[A]], align 4 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK29-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -26652,7 +26652,7 @@ int bar(int n){ // // // CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -26776,7 +26776,7 @@ int bar(int n){ // // // CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26797,7 +26797,7 @@ int bar(int n){ // // // CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26859,7 +26859,7 @@ int bar(int n){ // // // CHECK30-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26944,7 +26944,7 @@ int bar(int n){ // CHECK30-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK30: omp.inner.for.end: // CHECK30-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK30-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK30-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK30-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK30-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -26994,7 +26994,7 @@ int bar(int n){ // CHECK30-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START25]], align 4 // CHECK30-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 // CHECK30-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK30-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK30-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK30-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK30-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK30: omp.inner.for.cond30: @@ -27157,7 +27157,7 @@ int bar(int n){ // // // CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -27165,22 +27165,22 @@ int bar(int n){ // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK30-NEXT: store i32 0, i32* [[A]], align 4 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK30-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -27189,7 +27189,7 @@ int bar(int n){ // // // CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -27313,7 +27313,7 @@ int bar(int n){ // // // CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -27334,7 +27334,7 @@ int bar(int n){ // // // CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -27396,7 +27396,7 @@ int bar(int n){ // // // CHECK31-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -27479,7 +27479,7 @@ int bar(int n){ // CHECK31-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK31: omp.inner.for.end: // CHECK31-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK31-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK31-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK31-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK31-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -27529,7 +27529,7 @@ int bar(int n){ // CHECK31-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4 // CHECK31-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 // CHECK31-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK31-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK31-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK31-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK31-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK31: omp.inner.for.cond30: @@ -27692,7 +27692,7 @@ int bar(int n){ // // // CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -27700,22 +27700,22 @@ int bar(int n){ // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK31-NEXT: store i32 0, i32* [[A]], align 4 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK31-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -27724,7 +27724,7 @@ int bar(int n){ // // // CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -27847,7 +27847,7 @@ int bar(int n){ // // // CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -27868,7 +27868,7 @@ int bar(int n){ // // // CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -27930,7 +27930,7 @@ int bar(int n){ // // // CHECK32-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -28013,7 +28013,7 @@ int bar(int n){ // CHECK32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK32: omp.inner.for.end: // CHECK32-NEXT: store i32 33, i32* [[I]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK32-NEXT: [[CALL:%.*]] = call i64 @_Z7get_valv() // CHECK32-NEXT: store i64 [[CALL]], i64* [[K]], align 8 // CHECK32-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK32-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 @@ -28063,7 +28063,7 @@ int bar(int n){ // CHECK32-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START25]], align 4 // CHECK32-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 // CHECK32-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START26]], align 4 -// CHECK32-NEXT: [[CALL27:%.*]] = call noundef i64 @_Z7get_valv() +// CHECK32-NEXT: [[CALL27:%.*]] = call i64 @_Z7get_valv() // CHECK32-NEXT: store i64 [[CALL27]], i64* [[DOTLINEAR_STEP]], align 8 // CHECK32-NEXT: br label [[OMP_INNER_FOR_COND30:%.*]] // CHECK32: omp.inner.for.cond30: @@ -28226,7 +28226,7 @@ int bar(int n){ // // // CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -28234,22 +28234,22 @@ int bar(int n){ // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK32-NEXT: store i32 0, i32* [[A]], align 4 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK32-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -28258,7 +28258,7 @@ int bar(int n){ // // // CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -28381,7 +28381,7 @@ int bar(int n){ // // // CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -28402,7 +28402,7 @@ int bar(int n){ // // // CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/target_parallel_for_simd_depend_codegen.cpp b/clang/test/OpenMP/target_parallel_for_simd_depend_codegen.cpp index 99996713da0d120f87fbed97567576ae27c145f3..082bccc55b7c981bd007386bf46be3e37f8fc931 100644 --- a/clang/test/OpenMP/target_parallel_for_simd_depend_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_for_simd_depend_codegen.cpp @@ -177,7 +177,7 @@ int foo(int n) { // CHECK: define internal void [[HVT0:@.+]]() -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias %1) // CHECK: store void (i8*, ...)* null, void (i8*, ...)** % // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0 // CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]], @@ -191,9 +191,9 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* noundef %{{.+}}, i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* %{{.+}}, i[[SZ]] %{{.+}}) -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[SZT:%.+]] = getelementptr inbounds [2 x i64], [2 x i64]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0 @@ -216,7 +216,7 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2 @@ -229,7 +229,7 @@ int foo(int n) { // CHECK: call void [[HVT1]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]]) // CHECK: ret i32 0 -// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] %{{.+}}) // Create stack storage and store argument in there. // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align @@ -237,7 +237,7 @@ int foo(int n) { // CHECK-64: load i32, i32* [[AA_CADDR]], align // CHECK-32: load i32, i32* [[AA_ADDR]], align -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[BP1_I32:%.+]] = load i32, i32* % diff --git a/clang/test/OpenMP/target_parallel_if_codegen.cpp b/clang/test/OpenMP/target_parallel_if_codegen.cpp index a377c262344c2d0b41fa5ca935ecfd7832b6c803..68590aeffcb553e5738b18382375d68f598dbb6c 100644 --- a/clang/test/OpenMP/target_parallel_if_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_if_codegen.cpp @@ -183,7 +183,7 @@ int bar(int n){ #endif // CHECK1-LABEL: define {{[^@]+}}@_Z3bari -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -191,17 +191,17 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -210,7 +210,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -336,7 +336,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -407,7 +407,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -483,7 +483,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -520,7 +520,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -541,7 +541,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -570,7 +570,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -585,7 +585,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK1-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -611,7 +611,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -628,7 +628,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -638,7 +638,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -660,7 +660,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -676,7 +676,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -699,7 +699,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -727,7 +727,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3bari -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -735,17 +735,17 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -754,7 +754,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -880,7 +880,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -951,7 +951,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1027,7 +1027,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1064,7 +1064,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1085,7 +1085,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -1114,7 +1114,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1129,7 +1129,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK2-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -1155,7 +1155,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1172,7 +1172,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1182,7 +1182,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK2-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -1204,7 +1204,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1220,7 +1220,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1243,7 +1243,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1271,7 +1271,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3bari -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1279,17 +1279,17 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -1298,7 +1298,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1423,7 +1423,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -1494,7 +1494,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1568,7 +1568,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1603,7 +1603,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1623,7 +1623,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -1652,7 +1652,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1667,7 +1667,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK3-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -1693,7 +1693,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1710,7 +1710,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1720,7 +1720,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -1740,7 +1740,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1755,7 +1755,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1776,7 +1776,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1803,7 +1803,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3bari -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1811,17 +1811,17 @@ int bar(int n){ // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -1830,7 +1830,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1955,7 +1955,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -2026,7 +2026,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2100,7 +2100,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2135,7 +2135,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2155,7 +2155,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -2184,7 +2184,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2199,7 +2199,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK4-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -2225,7 +2225,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2242,7 +2242,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2252,7 +2252,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK4-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -2272,7 +2272,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2287,7 +2287,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2308,7 +2308,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2335,7 +2335,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -2361,7 +2361,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2378,7 +2378,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2388,7 +2388,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2425,7 +2425,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2446,7 +2446,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -2475,7 +2475,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2490,7 +2490,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK9-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -2512,7 +2512,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2528,7 +2528,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2551,7 +2551,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2572,7 +2572,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK10-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -2598,7 +2598,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2615,7 +2615,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2625,7 +2625,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2662,7 +2662,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2683,7 +2683,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -2712,7 +2712,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2727,7 +2727,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK10-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -2749,7 +2749,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2765,7 +2765,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2788,7 +2788,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2809,7 +2809,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -2835,7 +2835,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2852,7 +2852,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2862,7 +2862,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2897,7 +2897,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2917,7 +2917,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -2946,7 +2946,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2961,7 +2961,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK11-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -2981,7 +2981,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2996,7 +2996,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3017,7 +3017,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3037,7 +3037,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK12-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -3063,7 +3063,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3080,7 +3080,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3090,7 +3090,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3125,7 +3125,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3145,7 +3145,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -3174,7 +3174,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3189,7 +3189,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK12-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -3209,7 +3209,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3224,7 +3224,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3245,7 +3245,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3265,7 +3265,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3273,17 +3273,17 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -3292,7 +3292,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -3418,7 +3418,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -3489,7 +3489,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3565,7 +3565,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3602,7 +3602,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3623,7 +3623,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -3652,7 +3652,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3667,7 +3667,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK17-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -3693,7 +3693,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3710,7 +3710,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3720,7 +3720,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK17-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -3742,7 +3742,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3758,7 +3758,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3781,7 +3781,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3809,7 +3809,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3817,17 +3817,17 @@ int bar(int n){ // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -3836,7 +3836,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -3962,7 +3962,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -4033,7 +4033,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4109,7 +4109,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4146,7 +4146,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4167,7 +4167,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -4196,7 +4196,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4211,7 +4211,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK18-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -4237,7 +4237,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4254,7 +4254,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4264,7 +4264,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK18-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -4286,7 +4286,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4302,7 +4302,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4325,7 +4325,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4353,7 +4353,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4361,17 +4361,17 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -4380,7 +4380,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -4505,7 +4505,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -4576,7 +4576,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4650,7 +4650,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4685,7 +4685,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4705,7 +4705,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -4734,7 +4734,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4749,7 +4749,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK19-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -4775,7 +4775,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4792,7 +4792,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4802,7 +4802,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK19-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -4822,7 +4822,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4837,7 +4837,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4858,7 +4858,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4885,7 +4885,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4893,17 +4893,17 @@ int bar(int n){ // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -4912,7 +4912,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -5037,7 +5037,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -5108,7 +5108,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -5182,7 +5182,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5217,7 +5217,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5237,7 +5237,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -5266,7 +5266,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5281,7 +5281,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK20-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -5307,7 +5307,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5324,7 +5324,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5334,7 +5334,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK20-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -5354,7 +5354,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5369,7 +5369,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5390,7 +5390,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5417,7 +5417,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK25-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -5443,7 +5443,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5460,7 +5460,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5470,7 +5470,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -5507,7 +5507,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5528,7 +5528,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -5557,7 +5557,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5572,7 +5572,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK25-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -5594,7 +5594,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5610,7 +5610,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -5633,7 +5633,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5654,7 +5654,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK26-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -5680,7 +5680,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5697,7 +5697,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5707,7 +5707,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -5744,7 +5744,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5765,7 +5765,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -5794,7 +5794,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5809,7 +5809,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK26-SAME: (i64 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -5831,7 +5831,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5847,7 +5847,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -5870,7 +5870,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5891,7 +5891,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK27-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -5917,7 +5917,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5934,7 +5934,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5944,7 +5944,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5979,7 +5979,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5999,7 +5999,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -6028,7 +6028,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6043,7 +6043,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK27-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -6063,7 +6063,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6078,7 +6078,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -6099,7 +6099,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6119,7 +6119,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK28-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 @@ -6145,7 +6145,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6162,7 +6162,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6172,7 +6172,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -6207,7 +6207,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6227,7 +6227,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -6256,7 +6256,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6271,7 +6271,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 -// CHECK28-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -6291,7 +6291,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6306,7 +6306,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -6327,7 +6327,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp b/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp index 52eae452b0ea7a6259530c68f2674b5bd59a8ccd..ee15b339271d1ba91a5b5e500ba61e08290e85b8 100644 --- a/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp @@ -190,7 +190,7 @@ int bar(int n){ #endif // CHECK1-LABEL: define {{[^@]+}}@_Z3bari -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -198,17 +198,17 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -217,7 +217,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -307,7 +307,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -376,7 +376,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -452,7 +452,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -476,7 +476,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -497,7 +497,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -509,7 +509,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -524,7 +524,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK1-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -537,7 +537,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -547,7 +547,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK1-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -560,7 +560,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -579,7 +579,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -589,7 +589,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -619,7 +619,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -647,7 +647,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3bari -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -655,17 +655,17 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -674,7 +674,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -764,7 +764,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -833,7 +833,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -909,7 +909,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -933,7 +933,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -954,7 +954,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -966,7 +966,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -981,7 +981,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK2-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -994,7 +994,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1004,7 +1004,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK2-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1017,7 +1017,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1036,7 +1036,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1046,7 +1046,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1076,7 +1076,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1104,7 +1104,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3bari -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1112,17 +1112,17 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -1131,7 +1131,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1219,7 +1219,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -1286,7 +1286,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1361,7 +1361,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1382,7 +1382,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1402,7 +1402,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1414,7 +1414,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1429,7 +1429,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK3-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1441,7 +1441,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1451,7 +1451,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK3-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1463,7 +1463,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1482,7 +1482,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1492,7 +1492,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1520,7 +1520,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1547,7 +1547,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3bari -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1555,17 +1555,17 @@ int bar(int n){ // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -1574,7 +1574,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1662,7 +1662,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -1729,7 +1729,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1804,7 +1804,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1825,7 +1825,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1845,7 +1845,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1857,7 +1857,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1872,7 +1872,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK4-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1884,7 +1884,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1894,7 +1894,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK4-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1906,7 +1906,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1925,7 +1925,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1935,7 +1935,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1963,7 +1963,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1990,7 +1990,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -2003,7 +2003,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2013,7 +2013,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2026,7 +2026,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2036,7 +2036,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2060,7 +2060,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2081,7 +2081,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2093,7 +2093,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2117,7 +2117,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2127,7 +2127,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2157,7 +2157,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2178,7 +2178,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK10-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -2191,7 +2191,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2201,7 +2201,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK10-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2214,7 +2214,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2224,7 +2224,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2248,7 +2248,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2269,7 +2269,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2281,7 +2281,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2305,7 +2305,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2315,7 +2315,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2345,7 +2345,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2366,7 +2366,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -2378,7 +2378,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2388,7 +2388,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2400,7 +2400,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2410,7 +2410,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2431,7 +2431,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2451,7 +2451,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2463,7 +2463,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2487,7 +2487,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2497,7 +2497,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2525,7 +2525,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2545,7 +2545,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK12-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -2557,7 +2557,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2567,7 +2567,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK12-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2579,7 +2579,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2589,7 +2589,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2610,7 +2610,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2630,7 +2630,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2642,7 +2642,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2666,7 +2666,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2676,7 +2676,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2704,7 +2704,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2724,7 +2724,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2732,17 +2732,17 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -2751,7 +2751,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -2841,7 +2841,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -2910,7 +2910,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2986,7 +2986,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3010,7 +3010,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3031,7 +3031,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3043,7 +3043,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3058,7 +3058,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK17-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3071,7 +3071,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3081,7 +3081,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK17-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3094,7 +3094,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3113,7 +3113,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3123,7 +3123,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3153,7 +3153,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3181,7 +3181,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3189,17 +3189,17 @@ int bar(int n){ // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -3208,7 +3208,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -3298,7 +3298,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -3367,7 +3367,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3443,7 +3443,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3467,7 +3467,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3488,7 +3488,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3500,7 +3500,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3515,7 +3515,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK18-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3528,7 +3528,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3538,7 +3538,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK18-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3551,7 +3551,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3570,7 +3570,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3580,7 +3580,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3610,7 +3610,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3638,7 +3638,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3646,17 +3646,17 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -3665,7 +3665,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -3753,7 +3753,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -3820,7 +3820,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3895,7 +3895,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3916,7 +3916,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3936,7 +3936,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3948,7 +3948,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3963,7 +3963,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK19-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3975,7 +3975,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3985,7 +3985,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK19-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3997,7 +3997,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4016,7 +4016,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4026,7 +4026,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4054,7 +4054,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4081,7 +4081,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4089,17 +4089,17 @@ int bar(int n){ // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -4108,7 +4108,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -4196,7 +4196,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -4263,7 +4263,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4338,7 +4338,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4359,7 +4359,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4379,7 +4379,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4391,7 +4391,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4406,7 +4406,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK20-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4418,7 +4418,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4428,7 +4428,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK20-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4440,7 +4440,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4459,7 +4459,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4469,7 +4469,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4497,7 +4497,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4524,7 +4524,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK25-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -4537,7 +4537,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4547,7 +4547,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK25-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4560,7 +4560,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4570,7 +4570,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4594,7 +4594,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4615,7 +4615,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4627,7 +4627,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4651,7 +4651,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4661,7 +4661,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4691,7 +4691,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4712,7 +4712,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK26-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -4725,7 +4725,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4735,7 +4735,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK26-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4748,7 +4748,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4758,7 +4758,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4782,7 +4782,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4803,7 +4803,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4815,7 +4815,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4839,7 +4839,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4849,7 +4849,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4879,7 +4879,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4900,7 +4900,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK27-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -4912,7 +4912,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4922,7 +4922,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK27-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4934,7 +4934,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4944,7 +4944,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4965,7 +4965,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4985,7 +4985,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4997,7 +4997,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5021,7 +5021,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5031,7 +5031,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5059,7 +5059,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5079,7 +5079,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK28-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -5091,7 +5091,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5101,7 +5101,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK28-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -5113,7 +5113,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5123,7 +5123,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5144,7 +5144,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5164,7 +5164,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -5176,7 +5176,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5200,7 +5200,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5210,7 +5210,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5238,7 +5238,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp b/clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp index 24604c1608dfb730d89ae98c4205278d34d98f53..bdf2622c18f8a196e993c3ae25e1380829b6f9f5 100644 --- a/clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp @@ -36,7 +36,7 @@ int main(int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -48,7 +48,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -61,7 +61,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -288,7 +288,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init. -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -301,7 +301,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -319,7 +319,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -341,7 +341,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -372,7 +372,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -386,7 +386,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -470,7 +470,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -519,7 +519,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -531,7 +531,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -544,7 +544,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -771,7 +771,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init. -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -784,7 +784,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -802,7 +802,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -824,7 +824,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -855,7 +855,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -869,7 +869,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -953,7 +953,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 diff --git a/clang/test/OpenMP/target_private_codegen.cpp b/clang/test/OpenMP/target_private_codegen.cpp index 88e1f50f50ddea6ce1b99c4a79e6d4a6676ccbee..213a20fec3aa68fa5017305681aa5323f1fd9c97 100644 --- a/clang/test/OpenMP/target_private_codegen.cpp +++ b/clang/test/OpenMP/target_private_codegen.cpp @@ -85,7 +85,7 @@ int foo(int n) { } // make sure that private variables are generated in all cases and that we use those instances for operations inside the // target region - // TCHECK: define weak void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[VLA:%.+]], i{{[0-9]+}} noundef [[VLA1:%.+]], i{{[0-9]+}} noundef [[VLA3:%.+]]) + // TCHECK: define weak void @__omp_offloading_{{.+}}(i{{[0-9]+}} [[VLA:%.+]], i{{[0-9]+}} [[VLA1:%.+]], i{{[0-9]+}} [[VLA3:%.+]]) // TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[VLA_ADDR2:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[VLA_ADDR4:%.+]] = alloca i{{[0-9]+}}, @@ -207,7 +207,7 @@ struct S1 { return c[1][1] + (int)b; } - // TCHECK: define weak void @__omp_offloading_{{.+}}([[S1]]* noundef [[TH:%.+]], i{{[0-9]+}} noundef [[VLA:%.+]], i{{[0-9]+}} noundef [[VLA1:%.+]]) + // TCHECK: define weak void @__omp_offloading_{{.+}}([[S1]]* [[TH:%.+]], i{{[0-9]+}} [[VLA:%.+]], i{{[0-9]+}} [[VLA1:%.+]]) // TCHECK: [[TH_ADDR:%.+]] = alloca [[S1]]*, // TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[VLA_ADDR2:%.+]] = alloca i{{[0-9]+}}, diff --git a/clang/test/OpenMP/target_reduction_codegen.cpp b/clang/test/OpenMP/target_reduction_codegen.cpp index 444f5d13d0da037d74721951f3ba260953d9266e..38508006872ec5c62044e3820164d7290c8267e0 100644 --- a/clang/test/OpenMP/target_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_reduction_codegen.cpp @@ -154,7 +154,7 @@ struct S1 { return c[1][1] + (int)b; } - // TCHECK: define weak void @__omp_offloading_{{.+}}([[S1]]* noundef [[TH:%.+]], i32*{{.+}}, i{{[0-9]+}} noundef [[VLA:%.+]], i{{[0-9]+}} noundef [[VLA1:%.+]], i16*{{.+}}) + // TCHECK: define weak void @__omp_offloading_{{.+}}([[S1]]* [[TH:%.+]], i32*{{.+}}, i{{[0-9]+}} [[VLA:%.+]], i{{[0-9]+}} [[VLA1:%.+]], i16*{{.+}}) // TCHECK: [[TH_ADDR:%.+]] = alloca [[S1]]*, // TCHECK: [[B_ADDR:%.+]] = alloca i{{[0-9]+}}*, // TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}}, diff --git a/clang/test/OpenMP/target_simd_codegen.cpp b/clang/test/OpenMP/target_simd_codegen.cpp index ad1ad44e2ddf66dc81d05cfe9c218b8395109d36..eab741de249a7132982c6652afdf0569e9822717 100644 --- a/clang/test/OpenMP/target_simd_codegen.cpp +++ b/clang/test/OpenMP/target_simd_codegen.cpp @@ -356,7 +356,7 @@ int foo(int n) { // CHECK-NEXT: } -// CHECK: define internal {{.*}}i32 [[OMP_TASK_ENTRY]](i32 {{.*}}%0, [[KMP_TASK_T_WITH_PRIVATES]]* noalias noundef %1) +// CHECK: define internal {{.*}}i32 [[OMP_TASK_ENTRY]](i32 {{.*}}%0, [[KMP_TASK_T_WITH_PRIVATES]]* noalias %1) // CHECK: [[RET:%.+]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @{{.+}}, i64 -1, i8* @{{[^,]+}}, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 1, i32 0, i8* null, i32 0, i8* null) // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]] @@ -366,7 +366,7 @@ int foo(int n) { // CHECK: [[END]] -// CHECK: define internal void [[HVT1]](i[[SZ]] noundef %{{.+}}, i{{32|64}}{{[*]*.*}} %{{.+}}) +// CHECK: define internal void [[HVT1]](i[[SZ]] %{{.+}}, i{{32|64}}{{[*]*.*}} %{{.+}}) // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align // CHECK-64: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i32* @@ -377,7 +377,7 @@ int foo(int n) { // CHECK: ret void // CHECK-NEXT: } -// CHECK: define internal void [[HVT2]](i[[SZ]] noundef %{{.+}}, i[[SZ]] noundef %{{.+}}, i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT2]](i[[SZ]] %{{.+}}, i[[SZ]] %{{.+}}, i[[SZ]] %{{.+}}) // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align // CHECK: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i16* diff --git a/clang/test/OpenMP/target_simd_depend_codegen.cpp b/clang/test/OpenMP/target_simd_depend_codegen.cpp index b36cead4c41e184c12e00ccbfa0285b25a81c831..0570240494f0bf010003f845a964690e7b182f56 100644 --- a/clang/test/OpenMP/target_simd_depend_codegen.cpp +++ b/clang/test/OpenMP/target_simd_depend_codegen.cpp @@ -181,7 +181,7 @@ int foo(int n) { // CHECK: define internal void [[HVT0:@.+]]() -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias %1) // CHECK: store void (i8*, ...)* null, void (i8*, ...)** % // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0 // CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]], @@ -195,9 +195,9 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* noundef %{{.+}}, i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* %{{.+}}, i[[SZ]] %{{.+}}) -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[SZT:%.+]] = getelementptr inbounds [2 x i64], [2 x i64]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0 @@ -220,7 +220,7 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2 @@ -233,7 +233,7 @@ int foo(int n) { // CHECK: call void [[HVT1]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]]) // CHECK: ret i32 0 -// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] %{{.+}}) // Create stack storage and store argument in there. // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align @@ -241,7 +241,7 @@ int foo(int n) { // CHECK-64: load i32, i32* [[AA_CADDR]], align // CHECK-32: load i32, i32* [[AA_ADDR]], align -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[BP1_I32:%.+]] = load i32, i32* % diff --git a/clang/test/OpenMP/target_teams_codegen.cpp b/clang/test/OpenMP/target_teams_codegen.cpp index 775879776efa533650a8cd681d98c5573f034686..387be05f7bc04b8f86cc416aeb086189ca3f7a32 100644 --- a/clang/test/OpenMP/target_teams_codegen.cpp +++ b/clang/test/OpenMP/target_teams_codegen.cpp @@ -303,7 +303,7 @@ int bar(int n){ #endif // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -671,7 +671,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -696,7 +696,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -709,7 +709,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -738,7 +738,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -816,7 +816,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -831,7 +831,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -847,7 +847,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -862,7 +862,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -880,7 +880,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -903,7 +903,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -927,7 +927,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -966,7 +966,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1039,7 +1039,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK1-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -1054,7 +1054,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1073,7 +1073,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1086,7 +1086,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK1-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -1101,7 +1101,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1115,7 +1115,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1128,7 +1128,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK1-SAME: (i32 noundef signext [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 @@ -1160,7 +1160,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK1-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 @@ -1170,7 +1170,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1184,7 +1184,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z3bari -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1192,22 +1192,22 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK1-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -1216,7 +1216,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1330,7 +1330,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1414,7 +1414,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1483,7 +1483,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1510,7 +1510,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1549,7 +1549,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -1583,7 +1583,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1622,7 +1622,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -1648,7 +1648,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1686,7 +1686,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2054,7 +2054,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK2-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -2079,7 +2079,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2092,7 +2092,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -2121,7 +2121,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2199,7 +2199,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 -// CHECK2-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -2214,7 +2214,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2230,7 +2230,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK2-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -2245,7 +2245,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2263,7 +2263,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -2286,7 +2286,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2310,7 +2310,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK2-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -2349,7 +2349,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2422,7 +2422,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK2-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -2437,7 +2437,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2456,7 +2456,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2469,7 +2469,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK2-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -2484,7 +2484,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2498,7 +2498,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2511,7 +2511,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK2-SAME: (i32 noundef signext [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 @@ -2543,7 +2543,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK2-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 @@ -2553,7 +2553,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2567,7 +2567,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3bari -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2575,22 +2575,22 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK2-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -2599,7 +2599,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -2713,7 +2713,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2797,7 +2797,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2866,7 +2866,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2893,7 +2893,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2932,7 +2932,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -2966,7 +2966,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3005,7 +3005,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -3031,7 +3031,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3069,7 +3069,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3430,7 +3430,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -3453,7 +3453,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3466,7 +3466,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -3495,7 +3495,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -3571,7 +3571,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 -// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -3584,7 +3584,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3599,7 +3599,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -3614,7 +3614,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3632,7 +3632,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -3653,7 +3653,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3676,7 +3676,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -3713,7 +3713,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3785,7 +3785,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK3-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -3798,7 +3798,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3815,7 +3815,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3827,7 +3827,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK3-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -3840,7 +3840,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3853,7 +3853,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3866,7 +3866,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK3-SAME: (i32 noundef [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 @@ -3897,7 +3897,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK3-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 @@ -3907,7 +3907,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3921,7 +3921,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3bari -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3929,22 +3929,22 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK3-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -3953,7 +3953,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -4066,7 +4066,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4149,7 +4149,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4217,7 +4217,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4242,7 +4242,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4280,7 +4280,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4312,7 +4312,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4350,7 +4350,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4374,7 +4374,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4411,7 +4411,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4772,7 +4772,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK4-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -4795,7 +4795,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4808,7 +4808,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK4-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -4837,7 +4837,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -4913,7 +4913,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 -// CHECK4-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -4926,7 +4926,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4941,7 +4941,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK4-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -4956,7 +4956,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4974,7 +4974,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4995,7 +4995,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5018,7 +5018,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK4-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -5055,7 +5055,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5127,7 +5127,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK4-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -5140,7 +5140,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5157,7 +5157,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5169,7 +5169,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK4-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -5182,7 +5182,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5195,7 +5195,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5208,7 +5208,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK4-SAME: (i32 noundef [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 @@ -5239,7 +5239,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK4-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 @@ -5249,7 +5249,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5263,7 +5263,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3bari -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -5271,22 +5271,22 @@ int bar(int n){ // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK4-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK4-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -5295,7 +5295,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -5408,7 +5408,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -5491,7 +5491,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -5559,7 +5559,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5584,7 +5584,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5622,7 +5622,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5654,7 +5654,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5692,7 +5692,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5716,7 +5716,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5753,7 +5753,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -5778,7 +5778,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5791,7 +5791,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -5806,7 +5806,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5824,7 +5824,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -5847,7 +5847,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5871,7 +5871,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -5910,7 +5910,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5983,7 +5983,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK9-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -5998,7 +5998,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6017,7 +6017,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6030,7 +6030,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK9-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -6045,7 +6045,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6059,7 +6059,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6072,7 +6072,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK9-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 @@ -6082,7 +6082,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6096,7 +6096,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -6130,7 +6130,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6169,7 +6169,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -6196,7 +6196,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6235,7 +6235,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -6261,7 +6261,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6292,7 +6292,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK10-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -6317,7 +6317,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6330,7 +6330,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK10-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -6345,7 +6345,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6363,7 +6363,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -6386,7 +6386,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6410,7 +6410,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK10-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -6449,7 +6449,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6522,7 +6522,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK10-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -6537,7 +6537,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6556,7 +6556,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6569,7 +6569,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK10-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -6584,7 +6584,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6598,7 +6598,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6611,7 +6611,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK10-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 @@ -6621,7 +6621,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6635,7 +6635,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -6669,7 +6669,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6708,7 +6708,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -6735,7 +6735,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6774,7 +6774,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -6800,7 +6800,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6831,7 +6831,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -6854,7 +6854,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6867,7 +6867,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -6882,7 +6882,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6900,7 +6900,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -6921,7 +6921,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6944,7 +6944,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -6981,7 +6981,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7053,7 +7053,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK11-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -7066,7 +7066,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7083,7 +7083,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7095,7 +7095,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK11-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -7108,7 +7108,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7121,7 +7121,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7134,7 +7134,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK11-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 @@ -7144,7 +7144,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7158,7 +7158,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -7190,7 +7190,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7228,7 +7228,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -7253,7 +7253,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7291,7 +7291,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -7315,7 +7315,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7345,7 +7345,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK12-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -7368,7 +7368,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7381,7 +7381,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK12-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -7396,7 +7396,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7414,7 +7414,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -7435,7 +7435,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7458,7 +7458,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK12-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -7495,7 +7495,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7567,7 +7567,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK12-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -7580,7 +7580,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7597,7 +7597,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7609,7 +7609,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK12-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -7622,7 +7622,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7635,7 +7635,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7648,7 +7648,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK12-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 @@ -7658,7 +7658,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7672,7 +7672,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -7704,7 +7704,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7742,7 +7742,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -7767,7 +7767,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7805,7 +7805,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -7829,7 +7829,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7859,7 +7859,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -8227,7 +8227,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK17-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -8252,7 +8252,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8265,7 +8265,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK17-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK17-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -8294,7 +8294,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK17-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -8372,7 +8372,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 -// CHECK17-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -8387,7 +8387,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8403,7 +8403,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -8418,7 +8418,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8436,7 +8436,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -8459,7 +8459,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8483,7 +8483,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -8522,7 +8522,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8595,7 +8595,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK17-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -8610,7 +8610,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8629,7 +8629,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8642,7 +8642,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK17-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -8657,7 +8657,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8671,7 +8671,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8684,7 +8684,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK17-SAME: (i32 noundef signext [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 @@ -8716,7 +8716,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK17-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 @@ -8726,7 +8726,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8740,7 +8740,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -8748,22 +8748,22 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK17-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -8772,7 +8772,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -8886,7 +8886,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -8970,7 +8970,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -9039,7 +9039,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -9066,7 +9066,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9105,7 +9105,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -9139,7 +9139,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9178,7 +9178,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -9204,7 +9204,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9242,7 +9242,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -9610,7 +9610,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK18-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK18-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -9635,7 +9635,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9648,7 +9648,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK18-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK18-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -9677,7 +9677,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK18-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK18-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -9755,7 +9755,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 -// CHECK18-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -9770,7 +9770,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9786,7 +9786,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK18-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -9801,7 +9801,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9819,7 +9819,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -9842,7 +9842,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9866,7 +9866,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK18-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -9905,7 +9905,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9978,7 +9978,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK18-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -9993,7 +9993,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10012,7 +10012,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10025,7 +10025,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK18-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -10040,7 +10040,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10054,7 +10054,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10067,7 +10067,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK18-SAME: (i32 noundef signext [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 @@ -10099,7 +10099,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK18-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 @@ -10109,7 +10109,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10123,7 +10123,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -10131,22 +10131,22 @@ int bar(int n){ // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK18-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -10155,7 +10155,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -10269,7 +10269,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -10353,7 +10353,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -10422,7 +10422,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -10449,7 +10449,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10488,7 +10488,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -10522,7 +10522,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10561,7 +10561,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -10587,7 +10587,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10625,7 +10625,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -10986,7 +10986,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK19-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -11009,7 +11009,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11022,7 +11022,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK19-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK19-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -11051,7 +11051,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK19-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK19-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -11127,7 +11127,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 -// CHECK19-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -11140,7 +11140,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11155,7 +11155,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -11170,7 +11170,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11188,7 +11188,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11209,7 +11209,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11232,7 +11232,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -11269,7 +11269,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11341,7 +11341,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK19-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -11354,7 +11354,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11371,7 +11371,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11383,7 +11383,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK19-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -11396,7 +11396,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11409,7 +11409,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11422,7 +11422,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 @@ -11453,7 +11453,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK19-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 @@ -11463,7 +11463,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11477,7 +11477,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -11485,22 +11485,22 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK19-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -11509,7 +11509,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -11622,7 +11622,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -11705,7 +11705,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -11773,7 +11773,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -11798,7 +11798,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11836,7 +11836,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11868,7 +11868,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11906,7 +11906,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11930,7 +11930,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11967,7 +11967,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -12328,7 +12328,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK20-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK20-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -12351,7 +12351,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12364,7 +12364,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK20-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK20-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -12393,7 +12393,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK20-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK20-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -12469,7 +12469,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 -// CHECK20-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -12482,7 +12482,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12497,7 +12497,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK20-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -12512,7 +12512,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12530,7 +12530,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -12551,7 +12551,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12574,7 +12574,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -12611,7 +12611,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12683,7 +12683,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK20-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -12696,7 +12696,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12713,7 +12713,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12725,7 +12725,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK20-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -12738,7 +12738,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12751,7 +12751,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12764,7 +12764,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z6bazzzziPi -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 @@ -12795,7 +12795,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK20-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 @@ -12805,7 +12805,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..19 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12819,7 +12819,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -12827,22 +12827,22 @@ int bar(int n){ // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK20-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -12851,7 +12851,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -12964,7 +12964,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -13047,7 +13047,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -13115,7 +13115,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -13140,7 +13140,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13178,7 +13178,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -13210,7 +13210,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13248,7 +13248,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -13272,7 +13272,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..27 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13309,7 +13309,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK25-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -13334,7 +13334,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13347,7 +13347,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK25-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -13362,7 +13362,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13380,7 +13380,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -13403,7 +13403,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13427,7 +13427,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK25-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -13466,7 +13466,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13539,7 +13539,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK25-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -13554,7 +13554,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13573,7 +13573,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13586,7 +13586,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK25-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -13601,7 +13601,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13615,7 +13615,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13628,7 +13628,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK25-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 @@ -13638,7 +13638,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13652,7 +13652,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -13686,7 +13686,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13725,7 +13725,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -13752,7 +13752,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13791,7 +13791,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -13817,7 +13817,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13848,7 +13848,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK26-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -13873,7 +13873,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13886,7 +13886,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK26-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -13901,7 +13901,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13919,7 +13919,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -13942,7 +13942,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13966,7 +13966,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK26-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -14005,7 +14005,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14078,7 +14078,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK26-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -14093,7 +14093,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14112,7 +14112,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14125,7 +14125,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK26-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 @@ -14140,7 +14140,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14154,7 +14154,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14167,7 +14167,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK26-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 @@ -14177,7 +14177,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14191,7 +14191,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -14225,7 +14225,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14264,7 +14264,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -14291,7 +14291,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14330,7 +14330,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -14356,7 +14356,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14387,7 +14387,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK27-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -14410,7 +14410,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14423,7 +14423,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK27-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -14438,7 +14438,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14456,7 +14456,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -14477,7 +14477,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14500,7 +14500,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK27-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -14537,7 +14537,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14609,7 +14609,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK27-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -14622,7 +14622,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14639,7 +14639,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14651,7 +14651,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK27-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -14664,7 +14664,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14677,7 +14677,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14690,7 +14690,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK27-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 @@ -14700,7 +14700,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14714,7 +14714,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -14746,7 +14746,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14784,7 +14784,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -14809,7 +14809,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14847,7 +14847,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -14871,7 +14871,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14901,7 +14901,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 -// CHECK28-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -14924,7 +14924,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14937,7 +14937,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK28-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -14952,7 +14952,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14970,7 +14970,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -14991,7 +14991,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15014,7 +15014,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK28-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -15051,7 +15051,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15123,7 +15123,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 -// CHECK28-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -15136,7 +15136,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15153,7 +15153,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15165,7 +15165,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 -// CHECK28-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 @@ -15178,7 +15178,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15191,7 +15191,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15204,7 +15204,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 -// CHECK28-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 @@ -15214,7 +15214,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15228,7 +15228,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 -// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -15260,7 +15260,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15298,7 +15298,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 -// CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -15323,7 +15323,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15361,7 +15361,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 -// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -15385,7 +15385,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/target_teams_depend_codegen.cpp b/clang/test/OpenMP/target_teams_depend_codegen.cpp index 132793d3e2d281bb5e3b9dd67a719642107ddaf3..8ac2fad72f0a040b42114980fd46eccee07f359c 100644 --- a/clang/test/OpenMP/target_teams_depend_codegen.cpp +++ b/clang/test/OpenMP/target_teams_depend_codegen.cpp @@ -181,7 +181,7 @@ int foo(int n) { // CHECK: define internal void [[HVT0:@.+]]() -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias %1) // CHECK: store void (i8*, ...)* null, void (i8*, ...)** % // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0 // CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]], @@ -195,9 +195,9 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* noundef %{{.+}}, i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* %{{.+}}, i[[SZ]] %{{.+}}) -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[SZT:%.+]] = getelementptr inbounds [2 x i64], [2 x i64]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0 @@ -220,7 +220,7 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2 @@ -233,7 +233,7 @@ int foo(int n) { // CHECK: call void [[HVT1]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]]) // CHECK: ret i32 0 -// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] %{{.+}}) // Create stack storage and store argument in there. // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align @@ -241,7 +241,7 @@ int foo(int n) { // CHECK-64: load i32, i32* [[AA_CADDR]], align // CHECK-32: load i32, i32* [[AA_ADDR]], align -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[BP1_I32:%.+]] = load i32, i32* % diff --git a/clang/test/OpenMP/target_teams_distribute_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_codegen.cpp index 4e57b91bbb4f6a6fa7461b91841c8d3226cc15a9..63e5e4dc10ef529cf14335f32434adbb9ecd1564 100644 --- a/clang/test/OpenMP/target_teams_distribute_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_codegen.cpp @@ -295,7 +295,7 @@ int bar(int n){ #endif // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -635,7 +635,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -660,7 +660,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -723,7 +723,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -752,7 +752,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -831,7 +831,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -846,7 +846,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -912,7 +912,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -927,7 +927,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -995,7 +995,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -1018,7 +1018,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1092,7 +1092,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -1139,7 +1139,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1283,7 +1283,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z3bari -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1291,22 +1291,22 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK1-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -1315,7 +1315,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1431,7 +1431,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1548,7 +1548,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1619,7 +1619,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1646,7 +1646,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1735,7 +1735,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK1-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -1777,7 +1777,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1901,7 +1901,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -1927,7 +1927,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2015,7 +2015,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2355,7 +2355,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK2-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -2380,7 +2380,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2443,7 +2443,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -2472,7 +2472,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2551,7 +2551,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 -// CHECK2-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -2566,7 +2566,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2632,7 +2632,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK2-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -2647,7 +2647,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2715,7 +2715,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -2738,7 +2738,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2812,7 +2812,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK2-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -2859,7 +2859,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3003,7 +3003,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3bari -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3011,22 +3011,22 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK2-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -3035,7 +3035,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -3151,7 +3151,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3268,7 +3268,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3339,7 +3339,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3366,7 +3366,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3455,7 +3455,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK2-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -3497,7 +3497,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3621,7 +3621,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -3647,7 +3647,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3735,7 +3735,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4069,7 +4069,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -4092,7 +4092,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4155,7 +4155,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -4184,7 +4184,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -4261,7 +4261,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 -// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -4274,7 +4274,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4339,7 +4339,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -4354,7 +4354,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4422,7 +4422,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4443,7 +4443,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4516,7 +4516,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -4559,7 +4559,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4701,7 +4701,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3bari -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4709,22 +4709,22 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK3-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -4733,7 +4733,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -4848,7 +4848,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4963,7 +4963,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -5033,7 +5033,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5058,7 +5058,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5146,7 +5146,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK3-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5184,7 +5184,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5306,7 +5306,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5330,7 +5330,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5417,7 +5417,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -5751,7 +5751,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK4-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -5774,7 +5774,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5837,7 +5837,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK4-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -5866,7 +5866,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -5943,7 +5943,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 -// CHECK4-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -5956,7 +5956,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6021,7 +6021,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK4-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -6036,7 +6036,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6104,7 +6104,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -6125,7 +6125,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6198,7 +6198,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK4-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -6241,7 +6241,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6383,7 +6383,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3bari -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6391,22 +6391,22 @@ int bar(int n){ // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK4-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK4-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -6415,7 +6415,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -6530,7 +6530,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6645,7 +6645,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6715,7 +6715,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -6740,7 +6740,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6828,7 +6828,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK4-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6866,7 +6866,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6988,7 +6988,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -7012,7 +7012,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7099,7 +7099,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -7124,7 +7124,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7187,7 +7187,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -7202,7 +7202,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7270,7 +7270,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -7293,7 +7293,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7367,7 +7367,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -7414,7 +7414,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7558,7 +7558,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -7600,7 +7600,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7724,7 +7724,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -7751,7 +7751,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7840,7 +7840,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -7866,7 +7866,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7947,7 +7947,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK10-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -7972,7 +7972,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8035,7 +8035,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK10-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -8050,7 +8050,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8118,7 +8118,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -8141,7 +8141,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8215,7 +8215,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK10-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -8262,7 +8262,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8406,7 +8406,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -8448,7 +8448,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8572,7 +8572,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -8599,7 +8599,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8688,7 +8688,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -8714,7 +8714,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8795,7 +8795,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -8818,7 +8818,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8881,7 +8881,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -8896,7 +8896,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8964,7 +8964,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -8985,7 +8985,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9058,7 +9058,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -9101,7 +9101,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9243,7 +9243,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -9281,7 +9281,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9403,7 +9403,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -9428,7 +9428,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9516,7 +9516,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -9540,7 +9540,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9620,7 +9620,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK12-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -9643,7 +9643,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9706,7 +9706,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK12-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -9721,7 +9721,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9789,7 +9789,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -9810,7 +9810,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9883,7 +9883,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK12-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -9926,7 +9926,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10068,7 +10068,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -10106,7 +10106,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10228,7 +10228,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -10253,7 +10253,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10341,7 +10341,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -10365,7 +10365,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -10445,7 +10445,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -10785,7 +10785,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK17-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -10810,7 +10810,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10873,7 +10873,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK17-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK17-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -10902,7 +10902,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK17-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -10981,7 +10981,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 -// CHECK17-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -10996,7 +10996,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11062,7 +11062,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -11077,7 +11077,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11145,7 +11145,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -11168,7 +11168,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11242,7 +11242,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -11289,7 +11289,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11433,7 +11433,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -11441,22 +11441,22 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK17-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -11465,7 +11465,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -11581,7 +11581,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -11698,7 +11698,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -11769,7 +11769,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -11796,7 +11796,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11885,7 +11885,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -11927,7 +11927,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12051,7 +12051,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -12077,7 +12077,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12165,7 +12165,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -12505,7 +12505,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK18-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK18-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -12530,7 +12530,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12593,7 +12593,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK18-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK18-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -12622,7 +12622,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK18-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK18-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -12701,7 +12701,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 -// CHECK18-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -12716,7 +12716,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12782,7 +12782,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK18-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -12797,7 +12797,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12865,7 +12865,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -12888,7 +12888,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12962,7 +12962,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK18-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -13009,7 +13009,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13153,7 +13153,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -13161,22 +13161,22 @@ int bar(int n){ // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK18-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -13185,7 +13185,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -13301,7 +13301,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -13418,7 +13418,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -13489,7 +13489,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -13516,7 +13516,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13605,7 +13605,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK18-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -13647,7 +13647,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13771,7 +13771,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -13797,7 +13797,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13885,7 +13885,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14219,7 +14219,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK19-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -14242,7 +14242,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14305,7 +14305,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK19-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK19-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -14334,7 +14334,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK19-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK19-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -14411,7 +14411,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 -// CHECK19-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -14424,7 +14424,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14489,7 +14489,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -14504,7 +14504,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14572,7 +14572,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -14593,7 +14593,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14666,7 +14666,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -14709,7 +14709,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14851,7 +14851,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14859,22 +14859,22 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK19-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -14883,7 +14883,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -14998,7 +14998,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15113,7 +15113,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15183,7 +15183,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -15208,7 +15208,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15296,7 +15296,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -15334,7 +15334,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15456,7 +15456,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -15480,7 +15480,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15567,7 +15567,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15901,7 +15901,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK20-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK20-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -15924,7 +15924,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15987,7 +15987,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK20-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK20-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -16016,7 +16016,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK20-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK20-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -16093,7 +16093,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 -// CHECK20-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -16106,7 +16106,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16171,7 +16171,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK20-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -16186,7 +16186,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16254,7 +16254,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -16275,7 +16275,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16348,7 +16348,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -16391,7 +16391,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16533,7 +16533,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16541,22 +16541,22 @@ int bar(int n){ // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK20-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -16565,7 +16565,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -16680,7 +16680,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16795,7 +16795,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16865,7 +16865,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -16890,7 +16890,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16978,7 +16978,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -17016,7 +17016,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17138,7 +17138,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -17162,7 +17162,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17249,7 +17249,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK25-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -17274,7 +17274,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17337,7 +17337,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK25-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -17352,7 +17352,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17420,7 +17420,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -17443,7 +17443,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17517,7 +17517,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK25-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -17564,7 +17564,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17708,7 +17708,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK25-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -17750,7 +17750,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17874,7 +17874,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -17901,7 +17901,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17990,7 +17990,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -18016,7 +18016,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18097,7 +18097,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK26-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -18122,7 +18122,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18185,7 +18185,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK26-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -18200,7 +18200,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18268,7 +18268,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -18291,7 +18291,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18365,7 +18365,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK26-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -18412,7 +18412,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18556,7 +18556,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK26-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -18598,7 +18598,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18722,7 +18722,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -18749,7 +18749,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18838,7 +18838,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -18864,7 +18864,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18945,7 +18945,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK27-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -18968,7 +18968,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19031,7 +19031,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK27-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -19046,7 +19046,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19114,7 +19114,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -19135,7 +19135,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19208,7 +19208,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK27-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -19251,7 +19251,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19393,7 +19393,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK27-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -19431,7 +19431,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19553,7 +19553,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -19578,7 +19578,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19666,7 +19666,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -19690,7 +19690,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19770,7 +19770,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 -// CHECK28-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -19793,7 +19793,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19856,7 +19856,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 -// CHECK28-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -19871,7 +19871,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19939,7 +19939,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 -// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -19960,7 +19960,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20033,7 +20033,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 -// CHECK28-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -20076,7 +20076,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20218,7 +20218,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 -// CHECK28-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -20256,7 +20256,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20378,7 +20378,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 -// CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -20403,7 +20403,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20491,7 +20491,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 -// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -20515,7 +20515,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp index fc012f399040dcbbd394bf98c2bc2f7e14a23765..10a62a2c6f1791ce7fbd79478fc38b3741df2490 100644 --- a/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp @@ -98,12 +98,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -140,7 +140,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -150,7 +150,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -242,12 +242,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -284,7 +284,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -294,7 +294,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -386,12 +386,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -428,7 +428,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -438,7 +438,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -528,12 +528,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -570,7 +570,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -580,7 +580,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -667,7 +667,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -792,7 +792,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -801,7 +801,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -833,7 +833,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -981,7 +981,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -1013,7 +1013,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 -// CHECK9-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -1023,7 +1023,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1111,7 +1111,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1236,7 +1236,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: // CHECK10-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -1245,7 +1245,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -1277,7 +1277,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1425,7 +1425,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -1457,7 +1457,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 -// CHECK10-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -1467,7 +1467,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1555,7 +1555,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1677,7 +1677,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -1686,7 +1686,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -1714,7 +1714,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1858,7 +1858,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -1890,7 +1890,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 -// CHECK11-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -1900,7 +1900,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1986,7 +1986,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2108,7 +2108,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: // CHECK12-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -2117,7 +2117,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -2145,7 +2145,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2289,7 +2289,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -2321,7 +2321,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 -// CHECK12-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -2331,7 +2331,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2415,3 +2415,4 @@ int main (int argc, char **argv) { // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_depend_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_depend_codegen.cpp index 98883e78285c68de89efe69da6a31b1c7f088eb0..783c4d128252798c84fa9dca75d0dbe422795f71 100644 --- a/clang/test/OpenMP/target_teams_distribute_depend_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_depend_codegen.cpp @@ -177,7 +177,7 @@ int foo(int n) { // CHECK: define internal void [[HVT0:@.+]]() -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias %1) // CHECK: store void (i8*, ...)* null, void (i8*, ...)** % // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0 // CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]], @@ -191,9 +191,9 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* noundef %{{.+}}, i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* %{{.+}}, i[[SZ]] %{{.+}}) -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[SZT:%.+]] = getelementptr inbounds [2 x i64], [2 x i64]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0 @@ -216,7 +216,7 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2 @@ -229,7 +229,7 @@ int foo(int n) { // CHECK: call void [[HVT1]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]]) // CHECK: ret i32 0 -// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] %{{.+}}) // Create stack storage and store argument in there. // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align @@ -237,7 +237,7 @@ int foo(int n) { // CHECK-64: load i32, i32* [[AA_CADDR]], align // CHECK-32: load i32, i32* [[AA_ADDR]], align -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[BP1_I32:%.+]] = load i32, i32* % diff --git a/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp index 5055586f8f46b3d8e206acd36a17a878c58d7b6b..8a278c56a29e001d683f32d44f4383e9c2e9fd99 100644 --- a/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp @@ -126,12 +126,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -212,7 +212,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -222,7 +222,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -290,7 +290,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -300,7 +300,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -368,7 +368,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -378,7 +378,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -473,12 +473,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -559,7 +559,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -569,7 +569,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -637,7 +637,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -647,7 +647,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -715,7 +715,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -725,7 +725,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -820,12 +820,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -906,7 +906,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -916,7 +916,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -983,7 +983,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -993,7 +993,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1060,7 +1060,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1070,7 +1070,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1164,12 +1164,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -1250,7 +1250,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1260,7 +1260,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1327,7 +1327,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1337,7 +1337,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1404,7 +1404,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1414,7 +1414,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1505,7 +1505,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1734,7 +1734,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT34]] // CHECK9: omp_offload.cont34: // CHECK9-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP102]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) @@ -1743,7 +1743,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -1764,7 +1764,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1859,7 +1859,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -1880,7 +1880,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1975,7 +1975,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2004,7 +2004,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2120,7 +2120,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -2195,7 +2195,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -2205,7 +2205,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2272,7 +2272,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -2282,7 +2282,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2349,7 +2349,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -2359,7 +2359,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2450,7 +2450,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2679,7 +2679,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT34]] // CHECK10: omp_offload.cont34: // CHECK10-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP102]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) @@ -2688,7 +2688,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2709,7 +2709,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2804,7 +2804,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2825,7 +2825,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2920,7 +2920,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2949,7 +2949,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3065,7 +3065,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -3140,7 +3140,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3150,7 +3150,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3217,7 +3217,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3227,7 +3227,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3294,7 +3294,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3304,7 +3304,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3395,7 +3395,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3622,7 +3622,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT31]] // CHECK11: omp_offload.cont31: // CHECK11-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP104]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) @@ -3631,7 +3631,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -3650,7 +3650,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3743,7 +3743,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -3762,7 +3762,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3855,7 +3855,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -3880,7 +3880,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3993,7 +3993,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -4068,7 +4068,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -4078,7 +4078,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4144,7 +4144,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -4154,7 +4154,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4220,7 +4220,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -4230,7 +4230,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4320,7 +4320,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4547,7 +4547,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT31]] // CHECK12: omp_offload.cont31: // CHECK12-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP104]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) @@ -4556,7 +4556,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -4575,7 +4575,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4668,7 +4668,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -4687,7 +4687,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4780,7 +4780,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -4805,7 +4805,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4918,7 +4918,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -4993,7 +4993,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -5003,7 +5003,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5069,7 +5069,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -5079,7 +5079,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5145,7 +5145,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -5155,7 +5155,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp index facae5a7f66040d865c41e67508ad9c4720445b6..778dd0a0c3b0104c4159b3942398eb198f084246 100644 --- a/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp @@ -142,33 +142,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -181,7 +181,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -192,14 +192,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -207,12 +207,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -220,7 +220,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -228,7 +228,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -247,7 +247,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -321,12 +321,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK1-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -358,7 +358,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -406,17 +406,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -475,14 +475,14 @@ int main() { // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -490,17 +490,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -508,17 +508,17 @@ int main() { // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -537,14 +537,14 @@ int main() { // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -602,17 +602,17 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP30]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -625,7 +625,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -645,7 +645,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -654,17 +654,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -672,12 +672,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK1-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -704,7 +704,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -752,18 +752,18 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -820,14 +820,14 @@ int main() { // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -835,7 +835,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -843,22 +843,22 @@ int main() { // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -870,7 +870,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -886,7 +886,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -905,7 +905,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -932,33 +932,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -971,7 +971,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -982,14 +982,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -997,12 +997,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1010,7 +1010,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1018,7 +1018,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1037,7 +1037,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -1111,12 +1111,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK2-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -1148,7 +1148,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1196,17 +1196,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1265,14 +1265,14 @@ int main() { // CHECK2-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done13: @@ -1280,17 +1280,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1298,17 +1298,17 @@ int main() { // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // @@ -1327,14 +1327,14 @@ int main() { // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1392,17 +1392,17 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP30]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1415,7 +1415,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1435,7 +1435,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1444,17 +1444,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1462,12 +1462,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK2-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -1494,7 +1494,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1542,18 +1542,18 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -1610,14 +1610,14 @@ int main() { // CHECK2-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done13: @@ -1625,7 +1625,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1633,22 +1633,22 @@ int main() { // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1660,7 +1660,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1676,7 +1676,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1695,7 +1695,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1722,33 +1722,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1761,7 +1761,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1772,14 +1772,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1787,12 +1787,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1800,7 +1800,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1808,7 +1808,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1827,7 +1827,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -1899,12 +1899,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK3-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -1932,7 +1932,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1978,17 +1978,17 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done3: -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2045,14 +2045,14 @@ int main() { // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -2060,17 +2060,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2078,17 +2078,17 @@ int main() { // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -2107,14 +2107,14 @@ int main() { // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2171,17 +2171,17 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP30]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2194,7 +2194,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2214,7 +2214,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2223,17 +2223,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2241,12 +2241,12 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK3-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -2271,7 +2271,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2318,18 +2318,18 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done4: // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -2384,14 +2384,14 @@ int main() { // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -2399,7 +2399,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -2407,22 +2407,22 @@ int main() { // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2434,7 +2434,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2450,7 +2450,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -2469,7 +2469,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2496,33 +2496,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2535,7 +2535,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2546,14 +2546,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2561,12 +2561,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -2574,7 +2574,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -2582,7 +2582,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2601,7 +2601,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -2673,12 +2673,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK4-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -2706,7 +2706,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2752,17 +2752,17 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done3: -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2819,14 +2819,14 @@ int main() { // CHECK4-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done11: @@ -2834,17 +2834,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2852,17 +2852,17 @@ int main() { // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // @@ -2881,14 +2881,14 @@ int main() { // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2945,17 +2945,17 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP30]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2968,7 +2968,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2988,7 +2988,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2997,17 +2997,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3015,12 +3015,12 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK4-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -3045,7 +3045,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3092,18 +3092,18 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done4: // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -3158,14 +3158,14 @@ int main() { // CHECK4-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done12: @@ -3173,7 +3173,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3181,22 +3181,22 @@ int main() { // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3208,7 +3208,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3224,7 +3224,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3243,7 +3243,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3270,33 +3270,33 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3309,7 +3309,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3320,14 +3320,14 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3335,12 +3335,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3348,7 +3348,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -3356,7 +3356,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3375,7 +3375,7 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // @@ -3386,12 +3386,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -3425,7 +3425,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3492,7 +3492,7 @@ int main() { // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3527,33 +3527,33 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3566,7 +3566,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3577,14 +3577,14 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3592,12 +3592,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3605,7 +3605,7 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: @@ -3613,7 +3613,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3632,7 +3632,7 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // @@ -3643,12 +3643,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK10-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK10-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -3682,7 +3682,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3749,7 +3749,7 @@ int main() { // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3780,3 +3780,4 @@ int main() { // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp index 35535552d29af3b4989c5d751546bf89f2c43322..20008403c7c1937dc92c5f7faf5d1917308dcdee 100644 --- a/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp @@ -148,12 +148,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -195,7 +195,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -275,7 +275,7 @@ int main() { // CHECK1-NEXT: store i32* [[SVAR8]], i32** [[TMP13]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store float* [[SFVAR9]], float** [[TMP14]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -327,12 +327,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK2-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -374,7 +374,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -454,7 +454,7 @@ int main() { // CHECK2-NEXT: store i32* [[SVAR8]], i32** [[TMP13]], align 8 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store float* [[SFVAR9]], float** [[TMP14]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -506,12 +506,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -541,7 +541,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -620,7 +620,7 @@ int main() { // CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP15]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP16]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -672,12 +672,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -707,7 +707,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -786,7 +786,7 @@ int main() { // CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP15]], align 4 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP16]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -845,14 +845,14 @@ int main() { // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -915,7 +915,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -923,27 +923,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP37]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -951,12 +951,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK9-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -991,7 +991,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1036,13 +1036,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -1132,14 +1132,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 8 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done16: @@ -1147,12 +1147,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1171,14 +1171,14 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1236,17 +1236,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP30]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1257,7 +1257,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1271,7 +1271,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1280,17 +1280,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1298,12 +1298,12 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -1330,7 +1330,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1371,13 +1371,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -1465,14 +1465,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done14: @@ -1480,17 +1480,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1501,7 +1501,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1515,7 +1515,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1551,14 +1551,14 @@ int main() { // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1621,7 +1621,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1629,27 +1629,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP37]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1657,12 +1657,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK10-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -1697,7 +1697,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1742,13 +1742,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -1838,14 +1838,14 @@ int main() { // CHECK10-NEXT: store i32 [[TMP33]], i32* [[CONV1]], align 8 // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done16: @@ -1853,12 +1853,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -1877,14 +1877,14 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1942,17 +1942,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP30]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1963,7 +1963,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1977,7 +1977,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1986,17 +1986,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2004,12 +2004,12 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -2036,7 +2036,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2077,13 +2077,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK10-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -2171,14 +2171,14 @@ int main() { // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done14: @@ -2186,17 +2186,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2207,7 +2207,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2221,7 +2221,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2257,14 +2257,14 @@ int main() { // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -2325,7 +2325,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2333,27 +2333,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP37]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2361,12 +2361,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK11-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -2397,7 +2397,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2440,13 +2440,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -2534,14 +2534,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP33]], i32* [[SVAR_ADDR]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -2549,12 +2549,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2573,14 +2573,14 @@ int main() { // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2637,17 +2637,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP30]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2658,7 +2658,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2672,7 +2672,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2681,17 +2681,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2699,12 +2699,12 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -2729,7 +2729,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2769,13 +2769,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -2861,14 +2861,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -2876,17 +2876,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2897,7 +2897,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2911,7 +2911,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2947,14 +2947,14 @@ int main() { // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -3015,7 +3015,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -3023,27 +3023,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP37]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3051,12 +3051,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK12-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK12-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -3087,7 +3087,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3130,13 +3130,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -3224,14 +3224,14 @@ int main() { // CHECK12-NEXT: store i32 [[TMP33]], i32* [[SVAR_ADDR]], align 4 // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done14: @@ -3239,12 +3239,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // @@ -3263,14 +3263,14 @@ int main() { // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3327,17 +3327,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP30]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3348,7 +3348,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3362,7 +3362,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3371,17 +3371,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3389,12 +3389,12 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -3419,7 +3419,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3459,13 +3459,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -3551,14 +3551,14 @@ int main() { // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done13: @@ -3566,17 +3566,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3587,7 +3587,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3601,7 +3601,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3615,3 +3615,4 @@ int main() { // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp index de591a057164311b48f5acad519b8d5791c065a4..1b0bd4615118e946ef13c738211c0ebb89411198 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp @@ -72,7 +72,7 @@ int target_teams_fun(int *g){ #endif // CK1 #endif // HEADER // CHECK1-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK1-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -120,7 +120,7 @@ int target_teams_fun(int *g){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -148,7 +148,7 @@ int target_teams_fun(int *g){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -241,7 +241,7 @@ int target_teams_fun(int *g){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -358,7 +358,7 @@ int target_teams_fun(int *g){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -379,7 +379,7 @@ int target_teams_fun(int *g){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -475,7 +475,7 @@ int target_teams_fun(int *g){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -582,7 +582,7 @@ int target_teams_fun(int *g){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK2-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -738,7 +738,7 @@ int target_teams_fun(int *g){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK2-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -766,7 +766,7 @@ int target_teams_fun(int *g){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -859,7 +859,7 @@ int target_teams_fun(int *g){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -976,7 +976,7 @@ int target_teams_fun(int *g){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK2-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -997,7 +997,7 @@ int target_teams_fun(int *g){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1093,7 +1093,7 @@ int target_teams_fun(int *g){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1207,7 +1207,7 @@ int target_teams_fun(int *g){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK3-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -1363,7 +1363,7 @@ int target_teams_fun(int *g){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK3-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -1391,7 +1391,7 @@ int target_teams_fun(int *g){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1484,7 +1484,7 @@ int target_teams_fun(int *g){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1601,7 +1601,7 @@ int target_teams_fun(int *g){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK3-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -1622,7 +1622,7 @@ int target_teams_fun(int *g){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1718,7 +1718,7 @@ int target_teams_fun(int *g){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1832,7 +1832,7 @@ int target_teams_fun(int *g){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK4-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -1984,7 +1984,7 @@ int target_teams_fun(int *g){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK4-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -2008,7 +2008,7 @@ int target_teams_fun(int *g){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2097,7 +2097,7 @@ int target_teams_fun(int *g){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2210,7 +2210,7 @@ int target_teams_fun(int *g){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK4-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -2229,7 +2229,7 @@ int target_teams_fun(int *g){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2321,7 +2321,7 @@ int target_teams_fun(int *g){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2431,7 +2431,7 @@ int target_teams_fun(int *g){ // // // CHECK5-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK5-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -2583,7 +2583,7 @@ int target_teams_fun(int *g){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK5-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -2607,7 +2607,7 @@ int target_teams_fun(int *g){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2696,7 +2696,7 @@ int target_teams_fun(int *g){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2809,7 +2809,7 @@ int target_teams_fun(int *g){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK5-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -2828,7 +2828,7 @@ int target_teams_fun(int *g){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2920,7 +2920,7 @@ int target_teams_fun(int *g){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3030,7 +3030,7 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK10-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -3058,7 +3058,7 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3151,7 +3151,7 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3268,7 +3268,7 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK10-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -3289,7 +3289,7 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3385,7 +3385,7 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3492,7 +3492,7 @@ int target_teams_fun(int *g){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK11-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -3520,7 +3520,7 @@ int target_teams_fun(int *g){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3613,7 +3613,7 @@ int target_teams_fun(int *g){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3730,7 +3730,7 @@ int target_teams_fun(int *g){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK11-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -3751,7 +3751,7 @@ int target_teams_fun(int *g){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3847,7 +3847,7 @@ int target_teams_fun(int *g){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3954,7 +3954,7 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK12-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -3978,7 +3978,7 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4067,7 +4067,7 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4180,7 +4180,7 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK12-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -4199,7 +4199,7 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4291,7 +4291,7 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4394,7 +4394,7 @@ int target_teams_fun(int *g){ // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 -// CHECK13-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -4418,7 +4418,7 @@ int target_teams_fun(int *g){ // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4507,7 +4507,7 @@ int target_teams_fun(int *g){ // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4620,7 +4620,7 @@ int target_teams_fun(int *g){ // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 -// CHECK13-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -4639,7 +4639,7 @@ int target_teams_fun(int *g){ // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4731,7 +4731,7 @@ int target_teams_fun(int *g){ // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp index 267022955519acf676bf59f0f3822ed8ebbf251e..7ed17efc5ec456365d573902bd3925aefff81d7d 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp @@ -103,12 +103,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -145,7 +145,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -155,7 +155,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -220,7 +220,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -322,12 +322,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -364,7 +364,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -374,7 +374,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -439,7 +439,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -541,12 +541,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -583,7 +583,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -593,7 +593,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -656,7 +656,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -754,12 +754,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -796,7 +796,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -806,7 +806,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -869,7 +869,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -964,7 +964,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1089,7 +1089,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -1098,7 +1098,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -1130,7 +1130,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1252,7 +1252,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1408,7 +1408,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -1440,7 +1440,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK9-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -1450,7 +1450,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1515,7 +1515,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1613,7 +1613,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1738,7 +1738,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: // CHECK10-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -1747,7 +1747,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -1779,7 +1779,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1901,7 +1901,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2057,7 +2057,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -2089,7 +2089,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK10-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -2099,7 +2099,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2164,7 +2164,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2262,7 +2262,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2384,7 +2384,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -2393,7 +2393,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -2421,7 +2421,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2541,7 +2541,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2695,7 +2695,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -2727,7 +2727,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK11-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -2737,7 +2737,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2800,7 +2800,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2894,7 +2894,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3016,7 +3016,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: // CHECK12-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -3025,7 +3025,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -3053,7 +3053,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3173,7 +3173,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3327,7 +3327,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -3359,7 +3359,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK12-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -3369,7 +3369,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3432,7 +3432,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3524,3 +3524,4 @@ int main (int argc, char **argv) { // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_depend_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_depend_codegen.cpp index 32c407f2747fa3608cbcbebe91b62ea560f77c35..c035fff2addcab0a92290fb6a997fea7b7c252e2 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_depend_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_depend_codegen.cpp @@ -177,7 +177,7 @@ int foo(int n) { // CHECK: define internal void [[HVT0:@.+]]() -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias %1) // CHECK: store void (i8*, ...)* null, void (i8*, ...)** % // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0 // CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]], @@ -191,9 +191,9 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* noundef %{{.+}}, i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* %{{.+}}, i[[SZ]] %{{.+}}) -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[SZT:%.+]] = getelementptr inbounds [2 x i64], [2 x i64]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0 @@ -216,7 +216,7 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2 @@ -229,7 +229,7 @@ int foo(int n) { // CHECK: call void [[HVT1]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]]) // CHECK: ret i32 0 -// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] %{{.+}}) // Create stack storage and store argument in there. // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align @@ -237,7 +237,7 @@ int foo(int n) { // CHECK-64: load i32, i32* [[AA_CADDR]], align // CHECK-32: load i32, i32* [[AA_ADDR]], align -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[BP1_I32:%.+]] = load i32, i32* % diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp index dc4fb9a3d36312f879ff95dcecb2e43fc34d7a25..c5517aacd570b1c5c4547711f6ac2abce60fada1 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp @@ -138,12 +138,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -224,7 +224,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -234,7 +234,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -297,7 +297,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -375,7 +375,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -385,7 +385,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -448,7 +448,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -526,7 +526,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -536,7 +536,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -619,7 +619,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -707,12 +707,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -793,7 +793,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -803,7 +803,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -866,7 +866,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -944,7 +944,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -954,7 +954,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1017,7 +1017,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1095,7 +1095,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1105,7 +1105,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1188,7 +1188,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1276,12 +1276,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -1362,7 +1362,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1372,7 +1372,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1433,7 +1433,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1508,7 +1508,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1518,7 +1518,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1579,7 +1579,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1654,7 +1654,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1664,7 +1664,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1745,7 +1745,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1830,12 +1830,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -1916,7 +1916,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1926,7 +1926,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1987,7 +1987,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2062,7 +2062,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2072,7 +2072,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2133,7 +2133,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2208,7 +2208,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2218,7 +2218,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2299,7 +2299,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2381,7 +2381,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2612,7 +2612,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT34]] // CHECK9: omp_offload.cont34: // CHECK9-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP102]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) @@ -2621,7 +2621,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2642,7 +2642,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2738,7 +2738,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2843,7 +2843,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2864,7 +2864,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2960,7 +2960,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3065,7 +3065,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -3094,7 +3094,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3223,7 +3223,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3331,7 +3331,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -3424,7 +3424,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3434,7 +3434,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3497,7 +3497,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3574,7 +3574,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3584,7 +3584,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3647,7 +3647,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3724,7 +3724,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -3742,7 +3742,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3834,7 +3834,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3921,7 +3921,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4152,7 +4152,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT34]] // CHECK10: omp_offload.cont34: // CHECK10-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP102]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) @@ -4161,7 +4161,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -4182,7 +4182,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4278,7 +4278,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4383,7 +4383,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -4404,7 +4404,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4500,7 +4500,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4605,7 +4605,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -4634,7 +4634,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4763,7 +4763,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4871,7 +4871,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -4964,7 +4964,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -4974,7 +4974,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5037,7 +5037,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5114,7 +5114,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -5124,7 +5124,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5187,7 +5187,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5264,7 +5264,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -5282,7 +5282,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5374,7 +5374,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5461,7 +5461,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -5690,7 +5690,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT31]] // CHECK11: omp_offload.cont31: // CHECK11-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP104]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) @@ -5699,7 +5699,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -5718,7 +5718,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5810,7 +5810,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5911,7 +5911,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -5930,7 +5930,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6022,7 +6022,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6123,7 +6123,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -6148,7 +6148,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6271,7 +6271,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6374,7 +6374,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -6466,7 +6466,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -6476,7 +6476,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6537,7 +6537,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6611,7 +6611,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -6621,7 +6621,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6682,7 +6682,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6756,7 +6756,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -6772,7 +6772,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6860,7 +6860,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6943,7 +6943,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -7172,7 +7172,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT31]] // CHECK12: omp_offload.cont31: // CHECK12-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP104]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) @@ -7181,7 +7181,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -7200,7 +7200,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7292,7 +7292,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7393,7 +7393,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -7412,7 +7412,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7504,7 +7504,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7605,7 +7605,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -7630,7 +7630,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7753,7 +7753,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7856,7 +7856,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -7948,7 +7948,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -7958,7 +7958,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8019,7 +8019,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8093,7 +8093,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -8103,7 +8103,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8164,7 +8164,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8238,7 +8238,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -8254,7 +8254,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8342,7 +8342,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8423,3 +8423,4 @@ int main (int argc, char **argv) { // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp index b95d5b9e8d03ad1cc3e668fea2307a46472ac76a..3bac4276873968be29d1d270a5cfb5659759ae63 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp @@ -203,33 +203,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -242,7 +242,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -253,14 +253,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -268,12 +268,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -281,7 +281,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -289,7 +289,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -308,7 +308,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -382,12 +382,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK1-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -419,7 +419,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -469,17 +469,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -531,14 +531,14 @@ int main() { // CHECK1-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done11: @@ -546,17 +546,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -564,22 +564,22 @@ int main() { // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -637,17 +637,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done6: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -706,14 +706,14 @@ int main() { // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done15: @@ -735,14 +735,14 @@ int main() { // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -800,17 +800,17 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP30]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -823,7 +823,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -843,7 +843,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -852,17 +852,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -870,12 +870,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK1-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -902,7 +902,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -951,18 +951,18 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -1012,14 +1012,14 @@ int main() { // CHECK1-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done11: @@ -1027,7 +1027,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1035,12 +1035,12 @@ int main() { // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1098,18 +1098,18 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done6: // CHECK1-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK1-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -1166,14 +1166,14 @@ int main() { // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done15: @@ -1181,17 +1181,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1203,7 +1203,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1219,7 +1219,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1238,7 +1238,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1265,33 +1265,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1304,7 +1304,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1315,14 +1315,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1330,12 +1330,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1343,7 +1343,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1351,7 +1351,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1370,7 +1370,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -1444,12 +1444,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK2-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -1481,7 +1481,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1531,17 +1531,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1593,14 +1593,14 @@ int main() { // CHECK2-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done11: @@ -1608,17 +1608,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1626,22 +1626,22 @@ int main() { // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1699,17 +1699,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done6: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1768,14 +1768,14 @@ int main() { // CHECK2-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done15: @@ -1797,14 +1797,14 @@ int main() { // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1862,17 +1862,17 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP30]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1885,7 +1885,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1905,7 +1905,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1914,17 +1914,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1932,12 +1932,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK2-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -1964,7 +1964,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2013,18 +2013,18 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -2074,14 +2074,14 @@ int main() { // CHECK2-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done11: @@ -2089,7 +2089,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -2097,12 +2097,12 @@ int main() { // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2160,18 +2160,18 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done6: // CHECK2-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK2-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -2228,14 +2228,14 @@ int main() { // CHECK2-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done15: @@ -2243,17 +2243,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2265,7 +2265,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2281,7 +2281,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -2300,7 +2300,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2327,33 +2327,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2366,7 +2366,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2377,14 +2377,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2392,12 +2392,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -2405,7 +2405,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -2413,7 +2413,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2432,7 +2432,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -2504,12 +2504,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK3-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -2537,7 +2537,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2585,17 +2585,17 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done3: -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2643,14 +2643,14 @@ int main() { // CHECK3-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done8: @@ -2658,17 +2658,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2676,22 +2676,22 @@ int main() { // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2745,17 +2745,17 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done3: -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2812,14 +2812,14 @@ int main() { // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -2841,14 +2841,14 @@ int main() { // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2905,17 +2905,17 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP30]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2928,7 +2928,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2948,7 +2948,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2957,17 +2957,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2975,12 +2975,12 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK3-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -3005,7 +3005,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3053,18 +3053,18 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done4: // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -3111,14 +3111,14 @@ int main() { // CHECK3-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done10: @@ -3126,7 +3126,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3134,12 +3134,12 @@ int main() { // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3194,18 +3194,18 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done4: // CHECK3-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -3260,14 +3260,14 @@ int main() { // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -3275,17 +3275,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3297,7 +3297,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3313,7 +3313,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3332,7 +3332,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3359,33 +3359,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3398,7 +3398,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3409,14 +3409,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3424,12 +3424,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -3437,7 +3437,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -3445,7 +3445,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3464,7 +3464,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -3536,12 +3536,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK4-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -3569,7 +3569,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3617,17 +3617,17 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done3: -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3675,14 +3675,14 @@ int main() { // CHECK4-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done8: @@ -3690,17 +3690,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -3708,22 +3708,22 @@ int main() { // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3777,17 +3777,17 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done3: -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3844,14 +3844,14 @@ int main() { // CHECK4-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done11: @@ -3873,14 +3873,14 @@ int main() { // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3937,17 +3937,17 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP30]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -3960,7 +3960,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -3980,7 +3980,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -3989,17 +3989,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4007,12 +4007,12 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK4-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -4037,7 +4037,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4085,18 +4085,18 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done4: // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -4143,14 +4143,14 @@ int main() { // CHECK4-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done10: @@ -4158,7 +4158,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -4166,12 +4166,12 @@ int main() { // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4226,18 +4226,18 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done4: // CHECK4-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -4292,14 +4292,14 @@ int main() { // CHECK4-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done12: @@ -4307,17 +4307,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4329,7 +4329,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4345,7 +4345,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -4364,7 +4364,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4391,33 +4391,33 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4430,7 +4430,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4441,14 +4441,14 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4456,12 +4456,12 @@ int main() { // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4469,7 +4469,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -4477,7 +4477,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4496,7 +4496,7 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // @@ -4507,12 +4507,12 @@ int main() { // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK5-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK5-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -4546,7 +4546,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4633,7 +4633,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4710,7 +4710,7 @@ int main() { // CHECK5-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK5-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 -// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -4745,33 +4745,33 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4784,7 +4784,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4795,14 +4795,14 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4810,12 +4810,12 @@ int main() { // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4823,7 +4823,7 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: @@ -4831,7 +4831,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4850,7 +4850,7 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // @@ -4861,12 +4861,12 @@ int main() { // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK6-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK6-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -4900,7 +4900,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4987,7 +4987,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5064,7 +5064,7 @@ int main() { // CHECK6-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK6-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 -// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -5097,7 +5097,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK13-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -5129,7 +5129,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5179,17 +5179,17 @@ int main() { // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done4: -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -5241,14 +5241,14 @@ int main() { // CHECK13-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -5256,17 +5256,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK13-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -5274,22 +5274,22 @@ int main() { // CHECK13-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK13-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5347,17 +5347,17 @@ int main() { // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done6: -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] // CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -5416,14 +5416,14 @@ int main() { // CHECK13-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: @@ -5431,17 +5431,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK13-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -5468,7 +5468,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5517,18 +5517,18 @@ int main() { // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done4: // CHECK13-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK13-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -5578,14 +5578,14 @@ int main() { // CHECK13-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -5593,7 +5593,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -5601,12 +5601,12 @@ int main() { // CHECK13-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5664,18 +5664,18 @@ int main() { // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done6: // CHECK13-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] // CHECK13-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK13-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -5732,14 +5732,14 @@ int main() { // CHECK13-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: @@ -5747,17 +5747,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK13-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -5770,7 +5770,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK13-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -5779,7 +5779,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5788,7 +5788,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -5808,7 +5808,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5817,7 +5817,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -5836,7 +5836,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK14-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -5868,7 +5868,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5918,17 +5918,17 @@ int main() { // CHECK14: omp.arraycpy.body: // CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] // CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK14: omp.arraycpy.done4: -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -5980,14 +5980,14 @@ int main() { // CHECK14-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK14-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done11: @@ -5995,17 +5995,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK14-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -6013,22 +6013,22 @@ int main() { // CHECK14-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK14-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6086,17 +6086,17 @@ int main() { // CHECK14: omp.arraycpy.body: // CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK14: omp.arraycpy.done6: -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] // CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -6155,14 +6155,14 @@ int main() { // CHECK14-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK14-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done15: @@ -6170,17 +6170,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK14-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -6207,7 +6207,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6256,18 +6256,18 @@ int main() { // CHECK14: omp.arraycpy.body: // CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK14: omp.arraycpy.done4: // CHECK14-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK14-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -6317,14 +6317,14 @@ int main() { // CHECK14-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK14-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done11: @@ -6332,7 +6332,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -6340,12 +6340,12 @@ int main() { // CHECK14-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6403,18 +6403,18 @@ int main() { // CHECK14: omp.arraycpy.body: // CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK14: omp.arraycpy.done6: // CHECK14-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] // CHECK14-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK14-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -6471,14 +6471,14 @@ int main() { // CHECK14-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK14-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done15: @@ -6486,17 +6486,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK14-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -6509,7 +6509,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK14-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -6518,7 +6518,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6527,7 +6527,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -6547,7 +6547,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -6556,7 +6556,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -6575,7 +6575,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK15-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -6603,7 +6603,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6651,17 +6651,17 @@ int main() { // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done3: -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -6709,14 +6709,14 @@ int main() { // CHECK15-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done8: @@ -6724,17 +6724,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK15-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -6742,22 +6742,22 @@ int main() { // CHECK15-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK15-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6811,17 +6811,17 @@ int main() { // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done3: -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -6878,14 +6878,14 @@ int main() { // CHECK15-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done11: @@ -6893,17 +6893,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK15-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -6928,7 +6928,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6976,18 +6976,18 @@ int main() { // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done4: // CHECK15-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK15-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -7034,14 +7034,14 @@ int main() { // CHECK15-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: @@ -7049,7 +7049,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -7057,12 +7057,12 @@ int main() { // CHECK15-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7117,18 +7117,18 @@ int main() { // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done4: // CHECK15-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK15-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -7183,14 +7183,14 @@ int main() { // CHECK15-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done12: @@ -7198,17 +7198,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK15-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -7221,7 +7221,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK15-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -7230,7 +7230,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -7239,7 +7239,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -7259,7 +7259,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -7268,7 +7268,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -7287,7 +7287,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK16-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -7315,7 +7315,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7363,17 +7363,17 @@ int main() { // CHECK16: omp.arraycpy.body: // CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] // CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK16: omp.arraycpy.done3: -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] // CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -7421,14 +7421,14 @@ int main() { // CHECK16-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK16-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done8: @@ -7436,17 +7436,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK16-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -7454,22 +7454,22 @@ int main() { // CHECK16-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK16-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7523,17 +7523,17 @@ int main() { // CHECK16: omp.arraycpy.body: // CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK16: omp.arraycpy.done3: -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] // CHECK16-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -7590,14 +7590,14 @@ int main() { // CHECK16-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK16-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done11: @@ -7605,17 +7605,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK16-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -7640,7 +7640,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7688,18 +7688,18 @@ int main() { // CHECK16: omp.arraycpy.body: // CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK16: omp.arraycpy.done4: // CHECK16-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -7746,14 +7746,14 @@ int main() { // CHECK16-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK16-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done10: @@ -7761,7 +7761,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -7769,12 +7769,12 @@ int main() { // CHECK16-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7829,18 +7829,18 @@ int main() { // CHECK16: omp.arraycpy.body: // CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK16: omp.arraycpy.done4: // CHECK16-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK16-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -7895,14 +7895,14 @@ int main() { // CHECK16-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK16-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done12: @@ -7910,17 +7910,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK16-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -7933,7 +7933,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK16-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -7942,7 +7942,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -7951,7 +7951,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -7971,7 +7971,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -7980,7 +7980,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -7999,7 +7999,7 @@ int main() { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK17-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -8033,7 +8033,7 @@ int main() { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8120,7 +8120,7 @@ int main() { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8197,7 +8197,7 @@ int main() { // CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 // CHECK17-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 -// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* noundef [[REF_TMP]]) #[[ATTR3:[0-9]+]] +// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -8212,3 +8212,4 @@ int main() { // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK17-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp index 44d3fb6bfc2512db3f019a11e981765bb8c6ef34..5c9b5be7444d7a7435813dc715bdba253a92c643 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp @@ -137,7 +137,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -197,7 +197,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -274,7 +274,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -339,7 +339,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -471,7 +471,7 @@ int main() { // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -483,7 +483,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -543,7 +543,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -621,7 +621,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -686,7 +686,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -757,7 +757,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 -// CHECK1-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -774,7 +774,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -851,7 +851,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -922,7 +922,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK1-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -984,7 +984,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1044,7 +1044,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1122,7 +1122,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1187,7 +1187,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1258,7 +1258,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 -// CHECK1-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -1275,7 +1275,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1352,7 +1352,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1461,7 +1461,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1521,7 +1521,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1598,7 +1598,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1663,7 +1663,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1795,7 +1795,7 @@ int main() { // CHECK2-NEXT: br label [[OMP_IF_END]] // CHECK2: omp_if.end: // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -1807,7 +1807,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1867,7 +1867,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1945,7 +1945,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2010,7 +2010,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2081,7 +2081,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 -// CHECK2-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -2098,7 +2098,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2175,7 +2175,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2246,7 +2246,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK2-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -2308,7 +2308,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2368,7 +2368,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2446,7 +2446,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2511,7 +2511,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2582,7 +2582,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 -// CHECK2-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -2599,7 +2599,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2676,7 +2676,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2785,7 +2785,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2845,7 +2845,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2922,7 +2922,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2987,7 +2987,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3119,7 +3119,7 @@ int main() { // CHECK5-NEXT: br label [[OMP_IF_END]] // CHECK5: omp_if.end: // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK5-NEXT: ret i32 [[CALL]] // // @@ -3131,7 +3131,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3191,7 +3191,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3269,7 +3269,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3334,7 +3334,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3405,7 +3405,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 -// CHECK5-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -3422,7 +3422,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3499,7 +3499,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3570,7 +3570,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK5-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK5-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -3632,7 +3632,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3692,7 +3692,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3770,7 +3770,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3835,7 +3835,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3906,7 +3906,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 -// CHECK5-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -3923,7 +3923,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4000,7 +4000,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4109,7 +4109,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4169,7 +4169,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4246,7 +4246,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4311,7 +4311,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4443,7 +4443,7 @@ int main() { // CHECK6-NEXT: br label [[OMP_IF_END]] // CHECK6: omp_if.end: // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK6-NEXT: ret i32 [[CALL]] // // @@ -4455,7 +4455,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4515,7 +4515,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4593,7 +4593,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4658,7 +4658,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4729,7 +4729,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 -// CHECK6-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -4746,7 +4746,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4823,7 +4823,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4894,7 +4894,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK6-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK6-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -4956,7 +4956,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5016,7 +5016,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5094,7 +5094,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5159,7 +5159,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5230,7 +5230,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 -// CHECK6-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -5247,7 +5247,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5324,7 +5324,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5433,7 +5433,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5493,7 +5493,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5570,7 +5570,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5635,7 +5635,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5767,7 +5767,7 @@ int main() { // CHECK9-NEXT: br label [[OMP_IF_END]] // CHECK9: omp_if.end: // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK9-NEXT: ret i32 [[CALL]] // // @@ -5779,7 +5779,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5839,7 +5839,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5917,7 +5917,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5982,7 +5982,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6053,7 +6053,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -6070,7 +6070,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6147,7 +6147,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6218,7 +6218,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK9-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK9-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -6280,7 +6280,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6340,7 +6340,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6418,7 +6418,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6483,7 +6483,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6554,7 +6554,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -6571,7 +6571,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6648,7 +6648,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6757,7 +6757,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6817,7 +6817,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6894,7 +6894,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6959,7 +6959,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7091,7 +7091,7 @@ int main() { // CHECK10-NEXT: br label [[OMP_IF_END]] // CHECK10: omp_if.end: // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK10-NEXT: ret i32 [[CALL]] // // @@ -7103,7 +7103,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7163,7 +7163,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7241,7 +7241,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7306,7 +7306,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7377,7 +7377,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 -// CHECK10-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -7394,7 +7394,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7471,7 +7471,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7542,7 +7542,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK10-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK10-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -7604,7 +7604,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7664,7 +7664,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7742,7 +7742,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7807,7 +7807,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7878,7 +7878,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 -// CHECK10-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -7895,7 +7895,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7972,7 +7972,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8081,7 +8081,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8141,7 +8141,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8218,7 +8218,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8283,7 +8283,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8415,7 +8415,7 @@ int main() { // CHECK13-NEXT: br label [[OMP_IF_END]] // CHECK13: omp_if.end: // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK13-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK13-NEXT: ret i32 [[CALL]] // // @@ -8427,7 +8427,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8487,7 +8487,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8565,7 +8565,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8630,7 +8630,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8701,7 +8701,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 -// CHECK13-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -8718,7 +8718,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8795,7 +8795,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8866,7 +8866,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK13-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK13-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -8928,7 +8928,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8988,7 +8988,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9066,7 +9066,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9131,7 +9131,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9202,7 +9202,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 -// CHECK13-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -9219,7 +9219,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9296,7 +9296,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9405,7 +9405,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9465,7 +9465,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9542,7 +9542,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9607,7 +9607,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9739,7 +9739,7 @@ int main() { // CHECK14-NEXT: br label [[OMP_IF_END]] // CHECK14: omp_if.end: // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK14-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK14-NEXT: ret i32 [[CALL]] // // @@ -9751,7 +9751,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9811,7 +9811,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9889,7 +9889,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9954,7 +9954,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10025,7 +10025,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90 -// CHECK14-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -10042,7 +10042,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10119,7 +10119,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10190,7 +10190,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK14-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK14-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -10252,7 +10252,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10312,7 +10312,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10390,7 +10390,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10455,7 +10455,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10526,7 +10526,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 -// CHECK14-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -10543,7 +10543,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10620,7 +10620,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp index 89722a7dc6727f660befed95c67b9d501d497fd9..7a368c75c244963a3ff0ffc2dd096f74e244eee4 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp @@ -183,12 +183,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK1-SAME: (i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 @@ -230,7 +230,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -347,7 +347,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -436,7 +436,7 @@ int main() { // CHECK1-NEXT: store i32* [[SVAR10]], i32** [[TMP15]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store float* [[SFVAR11]], float** [[TMP16]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -488,12 +488,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK2-SAME: (i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 @@ -535,7 +535,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -652,7 +652,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -741,7 +741,7 @@ int main() { // CHECK2-NEXT: store i32* [[SVAR10]], i32** [[TMP15]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store float* [[SFVAR11]], float** [[TMP16]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -793,12 +793,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 @@ -828,7 +828,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -931,7 +931,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1017,7 +1017,7 @@ int main() { // CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1069,12 +1069,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 @@ -1104,7 +1104,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1207,7 +1207,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1293,7 +1293,7 @@ int main() { // CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1352,14 +1352,14 @@ int main() { // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK5-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1422,7 +1422,7 @@ int main() { // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1430,27 +1430,27 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done3: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP37]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1458,12 +1458,12 @@ int main() { // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK5-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -1498,7 +1498,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1545,13 +1545,13 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK5-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -1638,14 +1638,14 @@ int main() { // CHECK5-NEXT: store i32 [[TMP36]], i32* [[CONV1]], align 8 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done15: @@ -1653,7 +1653,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1708,13 +1708,13 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR8]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) // CHECK5-NEXT: store %struct.S* [[VAR8]], %struct.S** [[_TMP9]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -1804,14 +1804,14 @@ int main() { // CHECK5-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 8 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR8]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN17]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done18: @@ -1819,12 +1819,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: ret void // // @@ -1843,14 +1843,14 @@ int main() { // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1908,17 +1908,17 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP30]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1929,7 +1929,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1943,7 +1943,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1952,17 +1952,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1970,12 +1970,12 @@ int main() { // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50 -// CHECK5-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -2002,7 +2002,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2044,13 +2044,13 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -2131,14 +2131,14 @@ int main() { // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done12: @@ -2146,7 +2146,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2197,13 +2197,13 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR7]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK5-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -2291,14 +2291,14 @@ int main() { // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN15]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done16: @@ -2306,17 +2306,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2327,7 +2327,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2341,7 +2341,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2377,14 +2377,14 @@ int main() { // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK6-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -2447,7 +2447,7 @@ int main() { // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK6: omp_offload.cont: -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -2455,27 +2455,27 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done3: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK6-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP37]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2483,12 +2483,12 @@ int main() { // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK6-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -2523,7 +2523,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2570,13 +2570,13 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: // CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK6-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -2663,14 +2663,14 @@ int main() { // CHECK6-NEXT: store i32 [[TMP36]], i32* [[CONV1]], align 8 // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6: .omp.lastprivate.done: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK6-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done15: @@ -2678,7 +2678,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2733,13 +2733,13 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: // CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR8]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) // CHECK6-NEXT: store %struct.S* [[VAR8]], %struct.S** [[_TMP9]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -2829,14 +2829,14 @@ int main() { // CHECK6-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 8 // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6: .omp.lastprivate.done: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR8]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0 // CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN17]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done18: @@ -2844,12 +2844,12 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK6-NEXT: ret void // // @@ -2868,14 +2868,14 @@ int main() { // CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -2933,17 +2933,17 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done2: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP30]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2954,7 +2954,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2968,7 +2968,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2977,17 +2977,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2995,12 +2995,12 @@ int main() { // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50 -// CHECK6-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -3027,7 +3027,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3069,13 +3069,13 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: // CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK6-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -3156,14 +3156,14 @@ int main() { // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6: .omp.lastprivate.done: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK6-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done12: @@ -3171,7 +3171,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3222,13 +3222,13 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: // CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR7]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK6-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -3316,14 +3316,14 @@ int main() { // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6: .omp.lastprivate.done: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0 // CHECK6-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN15]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done16: @@ -3331,17 +3331,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3352,7 +3352,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3366,7 +3366,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3402,14 +3402,14 @@ int main() { // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK7-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK7-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -3470,7 +3470,7 @@ int main() { // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -3478,27 +3478,27 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done2: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK7-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP37]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3506,12 +3506,12 @@ int main() { // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK7-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -3542,7 +3542,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3587,13 +3587,13 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -3676,14 +3676,14 @@ int main() { // CHECK7-NEXT: store i32 [[TMP34]], i32* [[SVAR_ADDR]], align 4 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done12: @@ -3691,7 +3691,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3742,13 +3742,13 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: // CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -3836,14 +3836,14 @@ int main() { // CHECK7-NEXT: store i32 [[TMP35]], i32* [[SVAR_ADDR]], align 4 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done14: @@ -3851,12 +3851,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK7-NEXT: ret void // // @@ -3875,14 +3875,14 @@ int main() { // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3939,17 +3939,17 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done2: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP30]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3960,7 +3960,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3974,7 +3974,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3983,17 +3983,17 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4001,12 +4001,12 @@ int main() { // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50 -// CHECK7-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -4031,7 +4031,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4072,13 +4072,13 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -4156,14 +4156,14 @@ int main() { // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done11: @@ -4171,7 +4171,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4219,13 +4219,13 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: // CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -4311,14 +4311,14 @@ int main() { // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false) // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done13: @@ -4326,17 +4326,17 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4347,7 +4347,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4361,7 +4361,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4397,14 +4397,14 @@ int main() { // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK8-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK8-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -4465,7 +4465,7 @@ int main() { // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK8: omp_offload.cont: -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -4473,27 +4473,27 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP37]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4501,12 +4501,12 @@ int main() { // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK8-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK8-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -4537,7 +4537,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4582,13 +4582,13 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: // CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK8-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -4671,14 +4671,14 @@ int main() { // CHECK8-NEXT: store i32 [[TMP34]], i32* [[SVAR_ADDR]], align 4 // CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK8: .omp.lastprivate.done: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done12: @@ -4686,7 +4686,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4737,13 +4737,13 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: // CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK8-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -4831,14 +4831,14 @@ int main() { // CHECK8-NEXT: store i32 [[TMP35]], i32* [[SVAR_ADDR]], align 4 // CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK8: .omp.lastprivate.done: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done14: @@ -4846,12 +4846,12 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // @@ -4870,14 +4870,14 @@ int main() { // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4934,17 +4934,17 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP30]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4955,7 +4955,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4969,7 +4969,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4978,17 +4978,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4996,12 +4996,12 @@ int main() { // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50 -// CHECK8-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -5026,7 +5026,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5067,13 +5067,13 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: // CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -5151,14 +5151,14 @@ int main() { // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP30]], i8* align 4 [[TMP31]], i32 4, i1 false) // CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK8: .omp.lastprivate.done: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done11: @@ -5166,7 +5166,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5214,13 +5214,13 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: // CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -5306,14 +5306,14 @@ int main() { // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false) // CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK8: .omp.lastprivate.done: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done13: @@ -5321,17 +5321,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5342,7 +5342,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5356,7 +5356,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5370,3 +5370,4 @@ int main() { // CHECK8-NEXT: call void @__tgt_register_requires(i64 1) // CHECK8-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp index 8a02dbd96b0677326aa3e13268c25c0c4826a601..add8e3cd744afb1415b695e39969b7cfff915d7a 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp @@ -44,7 +44,7 @@ void gtid_test() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -104,7 +104,7 @@ void gtid_test() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -203,7 +203,7 @@ void gtid_test() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -263,7 +263,7 @@ void gtid_test() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp index fce6d5791b957658d672d199c9f30f70e6eceac7..fbb8f1fbbda7316eb18b49f13342af74375c1520 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp @@ -183,33 +183,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -222,7 +222,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -233,14 +233,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -248,12 +248,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -261,7 +261,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -269,7 +269,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -288,7 +288,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -307,7 +307,7 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -319,7 +319,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -346,12 +346,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -395,14 +395,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -410,7 +410,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -447,12 +447,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -511,14 +511,14 @@ int main() { // CHECK1-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -536,14 +536,14 @@ int main() { // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -561,27 +561,27 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP4]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -589,7 +589,7 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // @@ -601,7 +601,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -630,12 +630,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -680,14 +680,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done5: @@ -695,7 +695,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -734,12 +734,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -796,14 +796,14 @@ int main() { // CHECK1-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done9: @@ -811,17 +811,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -833,7 +833,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -849,7 +849,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -876,33 +876,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -915,7 +915,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -926,14 +926,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -941,12 +941,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -954,7 +954,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -962,7 +962,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -981,7 +981,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -1000,7 +1000,7 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -1012,7 +1012,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1039,12 +1039,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1088,14 +1088,14 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done3: @@ -1103,7 +1103,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1140,12 +1140,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1204,14 +1204,14 @@ int main() { // CHECK2-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done8: @@ -1229,14 +1229,14 @@ int main() { // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -1254,27 +1254,27 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP4]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1282,7 +1282,7 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // @@ -1294,7 +1294,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1323,12 +1323,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1373,14 +1373,14 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done5: @@ -1388,7 +1388,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1427,12 +1427,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -1489,14 +1489,14 @@ int main() { // CHECK2-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done9: @@ -1504,17 +1504,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1526,7 +1526,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1542,7 +1542,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1569,33 +1569,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1608,7 +1608,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1619,14 +1619,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1634,12 +1634,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1647,7 +1647,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1655,7 +1655,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1674,7 +1674,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -1693,7 +1693,7 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -1705,7 +1705,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1732,12 +1732,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1779,14 +1779,14 @@ int main() { // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done3: @@ -1794,7 +1794,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1829,12 +1829,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1891,14 +1891,14 @@ int main() { // CHECK3-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -1916,14 +1916,14 @@ int main() { // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -1941,27 +1941,27 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP4]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1969,7 +1969,7 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // @@ -1981,7 +1981,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2010,12 +2010,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2058,14 +2058,14 @@ int main() { // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done5: @@ -2073,7 +2073,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2110,12 +2110,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2170,14 +2170,14 @@ int main() { // CHECK3-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -2185,17 +2185,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2207,7 +2207,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2223,7 +2223,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2250,33 +2250,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2289,7 +2289,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2300,14 +2300,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2315,12 +2315,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -2328,7 +2328,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -2336,7 +2336,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2355,7 +2355,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -2374,7 +2374,7 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // @@ -2386,7 +2386,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2413,12 +2413,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2460,14 +2460,14 @@ int main() { // CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done3: @@ -2475,7 +2475,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2510,12 +2510,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2572,14 +2572,14 @@ int main() { // CHECK4-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done6: @@ -2597,14 +2597,14 @@ int main() { // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -2622,27 +2622,27 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP4]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2650,7 +2650,7 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // @@ -2662,7 +2662,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2691,12 +2691,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2739,14 +2739,14 @@ int main() { // CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done5: @@ -2754,7 +2754,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2791,12 +2791,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2851,14 +2851,14 @@ int main() { // CHECK4-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done7: @@ -2866,17 +2866,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2888,7 +2888,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2904,7 +2904,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2931,33 +2931,33 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2970,7 +2970,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2981,14 +2981,14 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2996,12 +2996,12 @@ int main() { // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3009,7 +3009,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -3017,7 +3017,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3036,7 +3036,7 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // @@ -3047,7 +3047,7 @@ int main() { // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // @@ -3059,7 +3059,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3126,7 +3126,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3199,7 +3199,7 @@ int main() { // CHECK5-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK5-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 -// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3234,33 +3234,33 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3273,7 +3273,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3284,14 +3284,14 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3299,12 +3299,12 @@ int main() { // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3312,7 +3312,7 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: @@ -3320,7 +3320,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3339,7 +3339,7 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // @@ -3350,7 +3350,7 @@ int main() { // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // @@ -3362,7 +3362,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3429,7 +3429,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3502,7 +3502,7 @@ int main() { // CHECK6-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK6-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 -// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3542,7 +3542,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3569,12 +3569,12 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3618,14 +3618,14 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK13-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done3: @@ -3633,17 +3633,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3680,12 +3680,12 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3744,14 +3744,14 @@ int main() { // CHECK13-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done8: @@ -3759,12 +3759,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // @@ -3776,7 +3776,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3805,12 +3805,12 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -3855,14 +3855,14 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done5: @@ -3870,17 +3870,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3919,12 +3919,12 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -3981,14 +3981,14 @@ int main() { // CHECK13-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done9: @@ -3996,17 +3996,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4019,7 +4019,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4028,7 +4028,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4040,7 +4040,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4056,7 +4056,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4083,12 +4083,12 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -4132,14 +4132,14 @@ int main() { // CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK14-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done3: @@ -4147,17 +4147,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4194,12 +4194,12 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -4258,14 +4258,14 @@ int main() { // CHECK14-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done8: @@ -4273,12 +4273,12 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK14-NEXT: ret void // // @@ -4290,7 +4290,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4319,12 +4319,12 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -4369,14 +4369,14 @@ int main() { // CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done5: @@ -4384,17 +4384,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4433,12 +4433,12 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -4495,14 +4495,14 @@ int main() { // CHECK14-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done9: @@ -4510,17 +4510,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4533,7 +4533,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4542,7 +4542,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4554,7 +4554,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4570,7 +4570,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4597,12 +4597,12 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -4644,14 +4644,14 @@ int main() { // CHECK15-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK15-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done3: @@ -4659,17 +4659,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4704,12 +4704,12 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -4766,14 +4766,14 @@ int main() { // CHECK15-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done6: @@ -4781,12 +4781,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // @@ -4798,7 +4798,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4827,12 +4827,12 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -4875,14 +4875,14 @@ int main() { // CHECK15-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done5: @@ -4890,17 +4890,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4937,12 +4937,12 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -4997,14 +4997,14 @@ int main() { // CHECK15-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done7: @@ -5012,17 +5012,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5035,7 +5035,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5044,7 +5044,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5056,7 +5056,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5072,7 +5072,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5099,12 +5099,12 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -5146,14 +5146,14 @@ int main() { // CHECK16-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK16-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done3: @@ -5161,17 +5161,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5206,12 +5206,12 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -5268,14 +5268,14 @@ int main() { // CHECK16-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done6: @@ -5283,12 +5283,12 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK16-NEXT: ret void // // @@ -5300,7 +5300,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5329,12 +5329,12 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -5377,14 +5377,14 @@ int main() { // CHECK16-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done5: @@ -5392,17 +5392,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5439,12 +5439,12 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -5499,14 +5499,14 @@ int main() { // CHECK16-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done7: @@ -5514,17 +5514,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5537,7 +5537,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5546,7 +5546,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5558,7 +5558,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5574,7 +5574,7 @@ int main() { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5641,7 +5641,7 @@ int main() { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5714,7 +5714,7 @@ int main() { // CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 // CHECK17-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 -// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* noundef [[REF_TMP]]) #[[ATTR3:[0-9]+]] +// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -5729,3 +5729,4 @@ int main() { // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) // CHECK17-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp index 62f96acf8a6fd25a04cfb71f0eededc97494ab5f..7ea3661c030b54b28c46ad85971ca05dd5eafa00 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp @@ -71,7 +71,7 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l38() #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT3]] // CHECK1: omp_offload.cont3: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -83,7 +83,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -144,7 +144,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -221,7 +221,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -282,7 +282,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -374,7 +374,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -435,7 +435,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -534,7 +534,7 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l38() #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT3]] // CHECK2: omp_offload.cont3: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -546,7 +546,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -607,7 +607,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -684,7 +684,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -745,7 +745,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -837,7 +837,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -898,7 +898,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -973,3 +973,4 @@ int main() { // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) // CHECK2-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp index 64cc47467f771c524515b56124201cd7f64a1f46..8c1df2cdc05d75ce58bcd42a1c6ba6bceb97c08a 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp @@ -117,12 +117,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -132,7 +132,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -219,7 +219,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -320,7 +320,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -344,7 +344,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -401,7 +401,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 @@ -411,7 +411,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -498,7 +498,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -599,7 +599,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -623,7 +623,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -680,12 +680,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -695,7 +695,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -782,7 +782,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -883,7 +883,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -907,7 +907,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -964,7 +964,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 @@ -974,7 +974,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1061,7 +1061,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1162,7 +1162,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1186,7 +1186,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1243,12 +1243,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 @@ -1258,7 +1258,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1343,7 +1343,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1442,7 +1442,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1466,7 +1466,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1523,7 +1523,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 @@ -1533,7 +1533,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1618,7 +1618,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1717,7 +1717,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1741,7 +1741,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1798,12 +1798,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 @@ -1813,7 +1813,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1898,7 +1898,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1997,7 +1997,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2021,7 +2021,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2078,7 +2078,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 @@ -2088,7 +2088,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2173,7 +2173,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2272,7 +2272,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2296,7 +2296,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2332,12 +2332,12 @@ int main() { // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 -// CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -2347,7 +2347,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2434,7 +2434,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2501,7 +2501,7 @@ int main() { // CHECK5-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK5-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8 -// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2539,7 +2539,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2563,7 +2563,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2599,12 +2599,12 @@ int main() { // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 -// CHECK6-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -2614,7 +2614,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2701,7 +2701,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2768,7 +2768,7 @@ int main() { // CHECK6-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 // CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK6-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8 -// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2806,7 +2806,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2830,7 +2830,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2859,3 +2859,4 @@ int main() { // CHECK6-NEXT: call void @__tgt_register_requires(i64 1) // CHECK6-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp index 9ded17d77f9d14e5cc600cf1f1a380db7bf7a54b..1978714a32482fe01905b3cca1c45984c3255d33 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp @@ -36,7 +36,7 @@ int main(int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -48,7 +48,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -61,7 +61,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -315,7 +315,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init. -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -328,7 +328,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -346,7 +346,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -368,7 +368,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -399,7 +399,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -688,7 +688,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init..4 -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -701,7 +701,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb..5 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -719,7 +719,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init..6 -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -741,7 +741,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb..7 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -772,7 +772,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -786,7 +786,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -870,7 +870,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -919,7 +919,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -968,7 +968,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -980,7 +980,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -993,7 +993,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1247,7 +1247,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init. -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1260,7 +1260,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1278,7 +1278,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1300,7 +1300,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1331,7 +1331,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1620,7 +1620,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init..4 -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1633,7 +1633,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb..5 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1651,7 +1651,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init..6 -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1673,7 +1673,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb..7 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1704,7 +1704,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -1718,7 +1718,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1802,7 +1802,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1851,7 +1851,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp index efed2bddce11dc7661ce63f3c836da95dcf8988c..364dac905a3d24ea3127b58346acf81c811bb68c 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp @@ -198,12 +198,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -330,7 +330,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -340,7 +340,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -403,7 +403,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -481,7 +481,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -491,7 +491,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -554,7 +554,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -632,7 +632,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -642,7 +642,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -705,7 +705,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -804,7 +804,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -814,7 +814,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -877,7 +877,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -953,7 +953,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -963,7 +963,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1026,7 +1026,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1112,12 +1112,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -1244,7 +1244,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1254,7 +1254,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1317,7 +1317,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1395,7 +1395,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1405,7 +1405,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1468,7 +1468,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1546,7 +1546,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1556,7 +1556,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1619,7 +1619,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1718,7 +1718,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1728,7 +1728,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1791,7 +1791,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1867,7 +1867,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1877,7 +1877,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1940,7 +1940,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2026,12 +2026,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -2158,7 +2158,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2168,7 +2168,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2229,7 +2229,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2304,7 +2304,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2314,7 +2314,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2375,7 +2375,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2450,7 +2450,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2460,7 +2460,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2521,7 +2521,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2615,7 +2615,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2625,7 +2625,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2686,7 +2686,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2759,7 +2759,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2769,7 +2769,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2830,7 +2830,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2913,12 +2913,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -3045,7 +3045,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3055,7 +3055,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3116,7 +3116,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3191,7 +3191,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3201,7 +3201,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3262,7 +3262,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3337,7 +3337,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3347,7 +3347,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3408,7 +3408,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3502,7 +3502,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3512,7 +3512,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3573,7 +3573,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3646,7 +3646,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3656,7 +3656,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3717,7 +3717,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3800,12 +3800,12 @@ int main (int argc, char **argv) { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -3932,7 +3932,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -3942,7 +3942,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4005,7 +4005,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4083,7 +4083,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -4093,7 +4093,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4156,7 +4156,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4234,7 +4234,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -4244,7 +4244,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4307,7 +4307,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4406,7 +4406,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -4416,7 +4416,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4479,7 +4479,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4555,7 +4555,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -4565,7 +4565,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4628,7 +4628,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4714,12 +4714,12 @@ int main (int argc, char **argv) { // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -4846,7 +4846,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -4856,7 +4856,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4919,7 +4919,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4997,7 +4997,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -5007,7 +5007,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5070,7 +5070,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5148,7 +5148,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -5158,7 +5158,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5221,7 +5221,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5320,7 +5320,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -5330,7 +5330,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5393,7 +5393,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5469,7 +5469,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -5479,7 +5479,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5542,7 +5542,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5628,12 +5628,12 @@ int main (int argc, char **argv) { // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -5760,7 +5760,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -5770,7 +5770,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5831,7 +5831,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5906,7 +5906,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -5916,7 +5916,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5977,7 +5977,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6052,7 +6052,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6062,7 +6062,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6123,7 +6123,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6217,7 +6217,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6227,7 +6227,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6288,7 +6288,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6361,7 +6361,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6371,7 +6371,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6432,7 +6432,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6515,12 +6515,12 @@ int main (int argc, char **argv) { // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK8-NEXT: ret i32 [[CALL]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -6647,7 +6647,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6657,7 +6657,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6718,7 +6718,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6793,7 +6793,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6803,7 +6803,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6864,7 +6864,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6939,7 +6939,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6949,7 +6949,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7010,7 +7010,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7104,7 +7104,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -7114,7 +7114,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7175,7 +7175,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7248,7 +7248,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -7258,7 +7258,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7319,7 +7319,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7399,7 +7399,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -7776,7 +7776,7 @@ int main (int argc, char **argv) { // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT67]] // CHECK13: omp_offload.cont67: // CHECK13-NEXT: [[TMP171:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP171]]) +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP171]]) // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP172:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP172]]) @@ -7785,7 +7785,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -7806,7 +7806,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7902,7 +7902,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8007,7 +8007,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -8028,7 +8028,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8124,7 +8124,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8229,7 +8229,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -8258,7 +8258,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8387,7 +8387,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8495,7 +8495,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -8516,7 +8516,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8612,7 +8612,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8713,7 +8713,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -8742,7 +8742,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8846,7 +8846,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8951,7 +8951,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -9104,7 +9104,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -9114,7 +9114,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9177,7 +9177,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9254,7 +9254,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -9264,7 +9264,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9327,7 +9327,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9404,7 +9404,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -9422,7 +9422,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9493,7 +9493,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9595,7 +9595,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -9605,7 +9605,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9668,7 +9668,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9743,7 +9743,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -9761,7 +9761,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9832,7 +9832,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9918,7 +9918,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -10295,7 +10295,7 @@ int main (int argc, char **argv) { // CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT67]] // CHECK14: omp_offload.cont67: // CHECK14-NEXT: [[TMP171:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP171]]) +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP171]]) // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[TMP172:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP172]]) @@ -10304,7 +10304,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -10325,7 +10325,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10421,7 +10421,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10526,7 +10526,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -10547,7 +10547,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10643,7 +10643,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10748,7 +10748,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -10777,7 +10777,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10906,7 +10906,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11014,7 +11014,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -11035,7 +11035,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11131,7 +11131,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11232,7 +11232,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -11261,7 +11261,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11365,7 +11365,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11470,7 +11470,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -11623,7 +11623,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -11633,7 +11633,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11696,7 +11696,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11773,7 +11773,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -11783,7 +11783,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11846,7 +11846,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11923,7 +11923,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -11941,7 +11941,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12012,7 +12012,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12114,7 +12114,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -12124,7 +12124,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12187,7 +12187,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12262,7 +12262,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -12280,7 +12280,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12351,7 +12351,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12437,7 +12437,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -12811,7 +12811,7 @@ int main (int argc, char **argv) { // CHECK15-NEXT: br label [[OMP_OFFLOAD_CONT61]] // CHECK15: omp_offload.cont61: // CHECK15-NEXT: [[TMP175:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP175]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP175]]) // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP176]]) @@ -12820,7 +12820,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -12839,7 +12839,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12931,7 +12931,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13032,7 +13032,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -13051,7 +13051,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13143,7 +13143,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13244,7 +13244,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -13269,7 +13269,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13392,7 +13392,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13495,7 +13495,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -13514,7 +13514,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13606,7 +13606,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13703,7 +13703,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -13728,7 +13728,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13826,7 +13826,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13926,7 +13926,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -14077,7 +14077,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -14087,7 +14087,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14148,7 +14148,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14222,7 +14222,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -14232,7 +14232,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14293,7 +14293,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14367,7 +14367,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -14383,7 +14383,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14450,7 +14450,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14546,7 +14546,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -14556,7 +14556,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14617,7 +14617,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14689,7 +14689,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -14705,7 +14705,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14772,7 +14772,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14854,7 +14854,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -15228,7 +15228,7 @@ int main (int argc, char **argv) { // CHECK16-NEXT: br label [[OMP_OFFLOAD_CONT61]] // CHECK16: omp_offload.cont61: // CHECK16-NEXT: [[TMP175:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP175]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP175]]) // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP176]]) @@ -15237,7 +15237,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK16-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -15256,7 +15256,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15348,7 +15348,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15449,7 +15449,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK16-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -15468,7 +15468,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15560,7 +15560,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15661,7 +15661,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK16-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -15686,7 +15686,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15809,7 +15809,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15912,7 +15912,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK16-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -15931,7 +15931,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16023,7 +16023,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16120,7 +16120,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK16-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -16145,7 +16145,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16243,7 +16243,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16343,7 +16343,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -16494,7 +16494,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -16504,7 +16504,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16565,7 +16565,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16639,7 +16639,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -16649,7 +16649,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16710,7 +16710,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16784,7 +16784,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -16800,7 +16800,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16867,7 +16867,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16963,7 +16963,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -16973,7 +16973,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17034,7 +17034,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17106,7 +17106,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -17122,7 +17122,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17189,7 +17189,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17271,7 +17271,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@main -// CHECK17-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -17648,7 +17648,7 @@ int main (int argc, char **argv) { // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT67]] // CHECK17: omp_offload.cont67: // CHECK17-NEXT: [[TMP171:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP171]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP171]]) // CHECK17-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK17-NEXT: [[TMP172:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP172]]) @@ -17657,7 +17657,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -17678,7 +17678,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17774,7 +17774,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17879,7 +17879,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -17900,7 +17900,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17996,7 +17996,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18101,7 +18101,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -18130,7 +18130,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18259,7 +18259,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18367,7 +18367,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -18388,7 +18388,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18484,7 +18484,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18585,7 +18585,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -18614,7 +18614,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18718,7 +18718,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18823,7 +18823,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK17-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK17-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -18976,7 +18976,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -18986,7 +18986,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19049,7 +19049,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19126,7 +19126,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -19136,7 +19136,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19199,7 +19199,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19276,7 +19276,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -19294,7 +19294,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19365,7 +19365,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19467,7 +19467,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -19477,7 +19477,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19540,7 +19540,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19615,7 +19615,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -19633,7 +19633,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19704,7 +19704,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19790,7 +19790,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@main -// CHECK18-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -20167,7 +20167,7 @@ int main (int argc, char **argv) { // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT67]] // CHECK18: omp_offload.cont67: // CHECK18-NEXT: [[TMP171:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP171]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP171]]) // CHECK18-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK18-NEXT: [[TMP172:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP172]]) @@ -20176,7 +20176,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK18-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -20197,7 +20197,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20293,7 +20293,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20398,7 +20398,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK18-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -20419,7 +20419,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20515,7 +20515,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20620,7 +20620,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK18-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -20649,7 +20649,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20778,7 +20778,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20886,7 +20886,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK18-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -20907,7 +20907,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21003,7 +21003,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21104,7 +21104,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK18-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -21133,7 +21133,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21237,7 +21237,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21342,7 +21342,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK18-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK18-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -21495,7 +21495,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -21505,7 +21505,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21568,7 +21568,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21645,7 +21645,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -21655,7 +21655,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21718,7 +21718,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21795,7 +21795,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -21813,7 +21813,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21884,7 +21884,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21986,7 +21986,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -21996,7 +21996,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22059,7 +22059,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22134,7 +22134,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -22152,7 +22152,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22223,7 +22223,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22309,7 +22309,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@main -// CHECK19-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -22683,7 +22683,7 @@ int main (int argc, char **argv) { // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT61]] // CHECK19: omp_offload.cont61: // CHECK19-NEXT: [[TMP175:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP175]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP175]]) // CHECK19-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK19-NEXT: [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP176]]) @@ -22692,7 +22692,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -22711,7 +22711,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22803,7 +22803,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22904,7 +22904,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -22923,7 +22923,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23015,7 +23015,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23116,7 +23116,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -23141,7 +23141,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23264,7 +23264,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23367,7 +23367,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -23386,7 +23386,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23478,7 +23478,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23575,7 +23575,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -23600,7 +23600,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23698,7 +23698,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23798,7 +23798,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK19-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK19-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -23949,7 +23949,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -23959,7 +23959,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24020,7 +24020,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24094,7 +24094,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -24104,7 +24104,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24165,7 +24165,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24239,7 +24239,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -24255,7 +24255,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24322,7 +24322,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24418,7 +24418,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -24428,7 +24428,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24489,7 +24489,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24561,7 +24561,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -24577,7 +24577,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24644,7 +24644,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24726,7 +24726,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@main -// CHECK20-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -25100,7 +25100,7 @@ int main (int argc, char **argv) { // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT61]] // CHECK20: omp_offload.cont61: // CHECK20-NEXT: [[TMP175:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP175]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP175]]) // CHECK20-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK20-NEXT: [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP176]]) @@ -25109,7 +25109,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -25128,7 +25128,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25220,7 +25220,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25321,7 +25321,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -25340,7 +25340,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25432,7 +25432,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25533,7 +25533,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -25558,7 +25558,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25681,7 +25681,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25784,7 +25784,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -25803,7 +25803,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25895,7 +25895,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25992,7 +25992,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -26017,7 +26017,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26115,7 +26115,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26215,7 +26215,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK20-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK20-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -26366,7 +26366,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -26376,7 +26376,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26437,7 +26437,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26511,7 +26511,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -26521,7 +26521,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26582,7 +26582,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26656,7 +26656,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -26672,7 +26672,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26739,7 +26739,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26835,7 +26835,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -26845,7 +26845,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26906,7 +26906,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26978,7 +26978,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -26994,7 +26994,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27061,7 +27061,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp index fc80c3a07c7b89d707ccbe03dc4843ca3a369bdb..7b289aa7a04a562d3090b489b47279cddb19f8f3 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp @@ -71,7 +71,7 @@ int target_teams_fun(int *g){ #endif // CK1 #endif // HEADER // CHECK1-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK1-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -241,7 +241,7 @@ int target_teams_fun(int *g){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50 -// CHECK1-SAME: (i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -277,7 +277,7 @@ int target_teams_fun(int *g){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -367,7 +367,7 @@ int target_teams_fun(int *g){ // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -392,7 +392,7 @@ int target_teams_fun(int *g){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -496,7 +496,7 @@ int target_teams_fun(int *g){ // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -527,7 +527,7 @@ int target_teams_fun(int *g){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -548,7 +548,7 @@ int target_teams_fun(int *g){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -610,28 +610,28 @@ int target_teams_fun(int *g){ // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !11 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]), !llvm.access.group !11 +// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -656,7 +656,7 @@ int target_teams_fun(int *g){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -727,30 +727,30 @@ int target_teams_fun(int *g){ // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !15 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 0 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -782,7 +782,7 @@ int target_teams_fun(int *g){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK2-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -952,7 +952,7 @@ int target_teams_fun(int *g){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50 -// CHECK2-SAME: (i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -988,7 +988,7 @@ int target_teams_fun(int *g){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1078,7 +1078,7 @@ int target_teams_fun(int *g){ // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1103,7 +1103,7 @@ int target_teams_fun(int *g){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1207,7 +1207,7 @@ int target_teams_fun(int *g){ // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1238,7 +1238,7 @@ int target_teams_fun(int *g){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56 -// CHECK2-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -1259,7 +1259,7 @@ int target_teams_fun(int *g){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1321,28 +1321,28 @@ int target_teams_fun(int *g){ // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !11 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]), !llvm.access.group !11 +// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 +// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK2-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1367,7 +1367,7 @@ int target_teams_fun(int *g){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1438,30 +1438,30 @@ int target_teams_fun(int *g){ // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !15 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 0 -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1493,7 +1493,7 @@ int target_teams_fun(int *g){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK3-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -1658,7 +1658,7 @@ int target_teams_fun(int *g){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50 -// CHECK3-SAME: (i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1688,7 +1688,7 @@ int target_teams_fun(int *g){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1772,7 +1772,7 @@ int target_teams_fun(int *g){ // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1797,7 +1797,7 @@ int target_teams_fun(int *g){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1896,7 +1896,7 @@ int target_teams_fun(int *g){ // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1927,7 +1927,7 @@ int target_teams_fun(int *g){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56 -// CHECK3-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -1946,7 +1946,7 @@ int target_teams_fun(int *g){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2007,25 +2007,25 @@ int target_teams_fun(int *g){ // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]), !llvm.access.group !12 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2050,7 +2050,7 @@ int target_teams_fun(int *g){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2118,29 +2118,29 @@ int target_teams_fun(int *g){ // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !16 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16 -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] -// CHECK3-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2172,7 +2172,7 @@ int target_teams_fun(int *g){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK4-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -2337,7 +2337,7 @@ int target_teams_fun(int *g){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50 -// CHECK4-SAME: (i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -2367,7 +2367,7 @@ int target_teams_fun(int *g){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2451,7 +2451,7 @@ int target_teams_fun(int *g){ // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2476,7 +2476,7 @@ int target_teams_fun(int *g){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2575,7 +2575,7 @@ int target_teams_fun(int *g){ // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2606,7 +2606,7 @@ int target_teams_fun(int *g){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56 -// CHECK4-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -2625,7 +2625,7 @@ int target_teams_fun(int *g){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2686,25 +2686,25 @@ int target_teams_fun(int *g){ // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]), !llvm.access.group !12 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2729,7 +2729,7 @@ int target_teams_fun(int *g){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2797,29 +2797,29 @@ int target_teams_fun(int *g){ // CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !16 -// CHECK4-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4, !llvm.access.group !16 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0 -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16 -// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !16 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] -// CHECK4-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4, !llvm.access.group !16 +// CHECK4-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2851,7 +2851,7 @@ int target_teams_fun(int *g){ // // // CHECK5-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK5-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -3003,7 +3003,7 @@ int target_teams_fun(int *g){ // // // CHECK6-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK6-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -3155,7 +3155,7 @@ int target_teams_fun(int *g){ // // // CHECK7-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK7-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -3305,7 +3305,7 @@ int target_teams_fun(int *g){ // // // CHECK8-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK8-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -3455,7 +3455,7 @@ int target_teams_fun(int *g){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50 -// CHECK9-SAME: (i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -3491,7 +3491,7 @@ int target_teams_fun(int *g){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3581,7 +3581,7 @@ int target_teams_fun(int *g){ // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] // CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3606,7 +3606,7 @@ int target_teams_fun(int *g){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3710,7 +3710,7 @@ int target_teams_fun(int *g){ // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3741,7 +3741,7 @@ int target_teams_fun(int *g){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56 -// CHECK9-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -3762,7 +3762,7 @@ int target_teams_fun(int *g){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3824,28 +3824,28 @@ int target_teams_fun(int *g){ // CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !12 -// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !12 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !12 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]), !llvm.access.group !12 +// CHECK9-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !12 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3870,7 +3870,7 @@ int target_teams_fun(int *g){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3941,30 +3941,30 @@ int target_teams_fun(int *g){ // CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !16 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !16 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 0 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !16 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4, !llvm.access.group !16 +// CHECK9-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3989,7 +3989,7 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50 -// CHECK10-SAME: (i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -4025,7 +4025,7 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4115,7 +4115,7 @@ int target_teams_fun(int *g){ // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] // CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -4140,7 +4140,7 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[I:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4244,7 +4244,7 @@ int target_teams_fun(int *g){ // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -4275,7 +4275,7 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56 -// CHECK10-SAME: (i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 @@ -4296,7 +4296,7 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4358,28 +4358,28 @@ int target_teams_fun(int *g){ // CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !12 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4, !llvm.access.group !12 -// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !12 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !12 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]), !llvm.access.group !12 +// CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !12 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -4404,7 +4404,7 @@ int target_teams_fun(int *g){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4475,30 +4475,30 @@ int target_teams_fun(int *g){ // CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !16 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8, !llvm.access.group !16 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 0 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !16 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4, !llvm.access.group !16 +// CHECK10-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -4523,7 +4523,7 @@ int target_teams_fun(int *g){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50 -// CHECK11-SAME: (i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -4553,7 +4553,7 @@ int target_teams_fun(int *g){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4637,7 +4637,7 @@ int target_teams_fun(int *g){ // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] // CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -4662,7 +4662,7 @@ int target_teams_fun(int *g){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4761,7 +4761,7 @@ int target_teams_fun(int *g){ // CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -4792,7 +4792,7 @@ int target_teams_fun(int *g){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56 -// CHECK11-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -4811,7 +4811,7 @@ int target_teams_fun(int *g){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4872,25 +4872,25 @@ int target_teams_fun(int *g){ // CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4, !llvm.access.group !13 -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4, !llvm.access.group !13 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4, !llvm.access.group !13 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4, !llvm.access.group !13 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]), !llvm.access.group !13 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -4915,7 +4915,7 @@ int target_teams_fun(int *g){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4983,29 +4983,29 @@ int target_teams_fun(int *g){ // CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !17 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4, !llvm.access.group !17 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !17 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 // CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] -// CHECK11-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4, !llvm.access.group !17 +// CHECK11-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -5030,7 +5030,7 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50 -// CHECK12-SAME: (i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -5060,7 +5060,7 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5144,7 +5144,7 @@ int target_teams_fun(int *g){ // CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] // CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -5169,7 +5169,7 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[I:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5268,7 +5268,7 @@ int target_teams_fun(int *g){ // CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -5299,7 +5299,7 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56 -// CHECK12-SAME: (i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 @@ -5318,7 +5318,7 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5379,25 +5379,25 @@ int target_teams_fun(int *g){ // CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4, !llvm.access.group !13 -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4, !llvm.access.group !13 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4, !llvm.access.group !13 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4, !llvm.access.group !13 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]), !llvm.access.group !13 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -5422,7 +5422,7 @@ int target_teams_fun(int *g){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], [1000 x i32]* noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* noundef [[G:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5490,29 +5490,29 @@ int target_teams_fun(int *g){ // CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !17 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 // CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] -// CHECK12-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -5537,7 +5537,7 @@ int target_teams_fun(int *g){ // // // CHECK13-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK13-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -5689,7 +5689,7 @@ int target_teams_fun(int *g){ // // // CHECK14-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK14-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -5841,7 +5841,7 @@ int target_teams_fun(int *g){ // // // CHECK15-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK15-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 @@ -5991,7 +5991,7 @@ int target_teams_fun(int *g){ // // // CHECK16-LABEL: define {{[^@]+}}@_Z16target_teams_funPi -// CHECK16-SAME: (i32* noundef [[G:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp index 5a0b735d75d42c1cc9ce384f76d57430a26b2bf9..79b93d237433a93f5214557f124a05b18276c6e7 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp @@ -103,12 +103,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -145,7 +145,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -155,7 +155,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -195,23 +195,23 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]), !llvm.access.group !4 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -228,7 +228,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -278,40 +278,40 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 456 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 456 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] // CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK1-NEXT: store i32 [[ADD7]], i32* [[J]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] -// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -338,12 +338,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -380,7 +380,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -390,7 +390,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -430,23 +430,23 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]), !llvm.access.group !4 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -463,7 +463,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -513,40 +513,40 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 456 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 456 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] // CHECK2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK2-NEXT: store i32 [[ADD7]], i32* [[J]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] -// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -573,12 +573,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -615,7 +615,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -625,7 +625,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -665,21 +665,21 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]), !llvm.access.group !5 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -696,7 +696,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -744,38 +744,38 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP13]] -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] -// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -802,12 +802,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -844,7 +844,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -854,7 +854,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -894,21 +894,21 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]), !llvm.access.group !5 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -925,7 +925,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -973,38 +973,38 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456 // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] // CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP13]] -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] -// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1031,12 +1031,12 @@ int main (int argc, char **argv) { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1102,12 +1102,12 @@ int main (int argc, char **argv) { // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1173,12 +1173,12 @@ int main (int argc, char **argv) { // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1242,12 +1242,12 @@ int main (int argc, char **argv) { // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK8-NEXT: ret i32 [[CALL]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1308,7 +1308,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1433,7 +1433,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -1442,7 +1442,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -1474,7 +1474,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1561,29 +1561,29 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] // CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8, !llvm.access.group !5 +// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK9-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !5 +// CHECK9-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]] -// CHECK9-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK9-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1614,7 +1614,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1707,13 +1707,13 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK9-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0 // CHECK9-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 // CHECK9-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] @@ -1722,16 +1722,16 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] // CHECK9-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK9-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 +// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK9-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0 // CHECK9-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 // CHECK9-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] // CHECK9-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 // CHECK9-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]] -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK9-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0 // CHECK9-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 // CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] @@ -1741,23 +1741,23 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 // CHECK9-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] // CHECK9-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 -// CHECK9-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 +// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 // CHECK9-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP28]] -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4 // CHECK9-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP29]] to i64 // CHECK9-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK9-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK9-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK9-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1788,7 +1788,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -1820,7 +1820,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK9-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -1830,7 +1830,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1870,23 +1870,23 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]), !llvm.access.group !14 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1903,7 +1903,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1953,39 +1953,39 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2 // CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] // CHECK9-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[J]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 // CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -2009,7 +2009,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2134,7 +2134,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: // CHECK10-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -2143,7 +2143,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -2175,7 +2175,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2262,29 +2262,29 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] // CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[CONV17:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8, !llvm.access.group !5 +// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV17]], align 4 +// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV3]], align 8 // CHECK10-NEXT: [[CONV18:%.*]] = bitcast i64* [[M_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !5 +// CHECK10-NEXT: store i32 [[TMP23]], i32* [[CONV18]], align 4 +// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[M_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP19]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]] -// CHECK10-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK10-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2315,7 +2315,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2408,13 +2408,13 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK10-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0 // CHECK10-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 // CHECK10-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] @@ -2423,16 +2423,16 @@ int main (int argc, char **argv) { // CHECK10-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] // CHECK10-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK10-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK10-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0 // CHECK10-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 // CHECK10-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] // CHECK10-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 // CHECK10-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]] -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 // CHECK10-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0 // CHECK10-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 // CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] @@ -2442,23 +2442,23 @@ int main (int argc, char **argv) { // CHECK10-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 // CHECK10-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] // CHECK10-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 -// CHECK10-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 // CHECK10-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP28]] -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4 // CHECK10-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP29]] to i64 // CHECK10-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK10-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK10-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK10-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2489,7 +2489,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -2521,7 +2521,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK10-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -2531,7 +2531,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2571,23 +2571,23 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]), !llvm.access.group !14 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2604,7 +2604,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2654,39 +2654,39 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2 // CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] // CHECK10-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[J]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 // CHECK10-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2710,7 +2710,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2832,7 +2832,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -2841,7 +2841,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -2869,7 +2869,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2954,29 +2954,29 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 // CHECK11-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32 -// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK11-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[N_ADDR]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: store i32 [[TMP23]], i32* [[N_CASTED]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[N_CASTED]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[M_ADDR]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: store i32 [[TMP25]], i32* [[M_CASTED]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[M_CASTED]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP20]], i32 [[TMP22]], i32 [[TMP24]], i32 [[TMP26]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !6 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP23]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP25]], i32* [[M_CASTED]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP20]], i32 [[TMP22]], i32 [[TMP24]], i32 [[TMP26]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP27]], [[TMP28]] -// CHECK11-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK11-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -3007,7 +3007,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3100,13 +3100,13 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK11-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK11-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK11-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0 // CHECK11-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 // CHECK11-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] @@ -3115,16 +3115,16 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] // CHECK11-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK11-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK11-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0 // CHECK11-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 // CHECK11-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] // CHECK11-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 // CHECK11-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]] -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK11-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0 // CHECK11-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 // CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] @@ -3134,21 +3134,21 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 // CHECK11-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] // CHECK11-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 -// CHECK11-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4 // CHECK11-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP1]] // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP28]] -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4 // CHECK11-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK11-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK11-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK11-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -3179,7 +3179,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -3211,7 +3211,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK11-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -3221,7 +3221,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3261,21 +3261,21 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]), !llvm.access.group !15 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -3292,7 +3292,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3340,37 +3340,37 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP13]] -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -3394,7 +3394,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3516,7 +3516,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: // CHECK12-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -3525,7 +3525,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -3553,7 +3553,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3638,29 +3638,29 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] // CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 // CHECK12-NEXT: [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32 -// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK12-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[N_ADDR]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: store i32 [[TMP23]], i32* [[N_CASTED]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[N_CASTED]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[M_ADDR]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: store i32 [[TMP25]], i32* [[M_CASTED]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[M_CASTED]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP20]], i32 [[TMP22]], i32 [[TMP24]], i32 [[TMP26]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !6 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP23]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[M_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP25]], i32* [[M_CASTED]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[M_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP20]], i32 [[TMP22]], i32 [[TMP24]], i32 [[TMP26]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP27]], [[TMP28]] -// CHECK12-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK12-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3691,7 +3691,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3784,13 +3784,13 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK12-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK12-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK12-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP22]], 0 // CHECK12-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 // CHECK12-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] @@ -3799,16 +3799,16 @@ int main (int argc, char **argv) { // CHECK12-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] // CHECK12-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK12-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK12-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP25]], 0 // CHECK12-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 // CHECK12-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] // CHECK12-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 // CHECK12-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP24]], [[CONV27]] -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK12-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP26]], 0 // CHECK12-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 // CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] @@ -3818,21 +3818,21 @@ int main (int argc, char **argv) { // CHECK12-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 // CHECK12-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] // CHECK12-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 -// CHECK12-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I13]], align 4 // CHECK12-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP1]] // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP28]] -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[J14]], align 4 // CHECK12-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK12-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK12-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK12-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3863,7 +3863,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -3895,7 +3895,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK12-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -3905,7 +3905,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3945,21 +3945,21 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]), !llvm.access.group !15 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3976,7 +3976,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4024,37 +4024,37 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 // CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] // CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP13]] -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -4078,7 +4078,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4214,7 +4214,7 @@ int main (int argc, char **argv) { // CHECK13-NEXT: br label [[SIMD_IF_END]] // CHECK13: simd.if.end: // CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP28]]) // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) @@ -4223,7 +4223,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -4281,7 +4281,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4417,7 +4417,7 @@ int main (int argc, char **argv) { // CHECK14-NEXT: br label [[SIMD_IF_END]] // CHECK14: simd.if.end: // CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP28]]) // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) @@ -4426,7 +4426,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -4484,7 +4484,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4616,7 +4616,7 @@ int main (int argc, char **argv) { // CHECK15-NEXT: br label [[SIMD_IF_END]] // CHECK15: simd.if.end: // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP26]]) // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP27]]) @@ -4625,7 +4625,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -4681,7 +4681,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4813,7 +4813,7 @@ int main (int argc, char **argv) { // CHECK16-NEXT: br label [[SIMD_IF_END]] // CHECK16: simd.if.end: // CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP26]]) // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP27]]) @@ -4822,7 +4822,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_depend_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_depend_codegen.cpp index a9ee35f9a2bd4022e1fc7476b5bc19ff64643dff..ff9e62b25a6c7f8bf07084375545249ca6ca74c4 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_depend_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_depend_codegen.cpp @@ -177,7 +177,7 @@ int foo(int n) { // CHECK: define internal void [[HVT0:@.+]]() -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias %1) // CHECK: store void (i8*, ...)* null, void (i8*, ...)** % // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0 // CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]], @@ -191,9 +191,9 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* noundef %{{.+}}, i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* %{{.+}}, i[[SZ]] %{{.+}}) -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[SZT:%.+]] = getelementptr inbounds [2 x i64], [2 x i64]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0 @@ -216,7 +216,7 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2 @@ -229,7 +229,7 @@ int foo(int n) { // CHECK: call void [[HVT1]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]]) // CHECK: ret i32 0 -// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] %{{.+}}) // Create stack storage and store argument in there. // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align @@ -237,7 +237,7 @@ int foo(int n) { // CHECK-64: load i32, i32* [[AA_CADDR]], align // CHECK-32: load i32, i32* [[AA_ADDR]], align -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[BP1_I32:%.+]] = load i32, i32* % diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp index 546db78ea17791355398190b80741c552949ba3b..60737285e51ba3f3605c4bf21c4db16ab05a3bad 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp @@ -138,12 +138,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -224,7 +224,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -234,7 +234,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -272,23 +272,23 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]), !llvm.access.group !6 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -304,7 +304,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -352,28 +352,28 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -389,7 +389,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -399,7 +399,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -437,23 +437,23 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]), !llvm.access.group !15 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -469,7 +469,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -517,28 +517,28 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -554,7 +554,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -564,7 +564,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -602,43 +602,43 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 123 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], %struct.SS* [[TMP0]]), !llvm.access.group !21 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], %struct.SS* [[TMP0]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP17]], 122 // CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] // CHECK1: cond.true5: // CHECK1-NEXT: br label [[COND_END7:%.*]] // CHECK1: cond.false6: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: br label [[COND_END7]] // CHECK1: cond.end7: // CHECK1-NEXT: [[COND8:%.*]] = phi i32 [ 122, [[COND_TRUE5]] ], [ [[TMP18]], [[COND_FALSE6]] ] -// CHECK1-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK1-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -654,7 +654,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -702,28 +702,28 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -749,12 +749,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -835,7 +835,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -845,7 +845,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -883,23 +883,23 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]), !llvm.access.group !6 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -915,7 +915,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -963,28 +963,28 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1000,7 +1000,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1010,7 +1010,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1048,23 +1048,23 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]), !llvm.access.group !15 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1080,7 +1080,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1128,28 +1128,28 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1165,7 +1165,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1175,7 +1175,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1213,43 +1213,43 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 123 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], %struct.SS* [[TMP0]]), !llvm.access.group !21 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], %struct.SS* [[TMP0]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP17]], 122 // CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] // CHECK2: cond.true5: // CHECK2-NEXT: br label [[COND_END7:%.*]] // CHECK2: cond.false6: -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: br label [[COND_END7]] // CHECK2: cond.end7: // CHECK2-NEXT: [[COND8:%.*]] = phi i32 [ 122, [[COND_TRUE5]] ], [ [[TMP18]], [[COND_FALSE6]] ] -// CHECK2-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK2-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1265,7 +1265,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1313,28 +1313,28 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1360,12 +1360,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -1446,7 +1446,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1456,7 +1456,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1494,21 +1494,21 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !7 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]), !llvm.access.group !7 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !7 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1524,7 +1524,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1570,27 +1570,27 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1606,7 +1606,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1616,7 +1616,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1654,21 +1654,21 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !16 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]), !llvm.access.group !16 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1684,7 +1684,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1730,27 +1730,27 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1766,7 +1766,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1776,7 +1776,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1814,41 +1814,41 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 123 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]], %struct.SS* [[TMP0]]), !llvm.access.group !22 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]], %struct.SS* [[TMP0]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP15]], 122 // CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] // CHECK3: cond.true5: // CHECK3-NEXT: br label [[COND_END7:%.*]] // CHECK3: cond.false6: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: br label [[COND_END7]] // CHECK3: cond.end7: // CHECK3-NEXT: [[COND8:%.*]] = phi i32 [ 122, [[COND_TRUE5]] ], [ [[TMP16]], [[COND_FALSE6]] ] -// CHECK3-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK3-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1864,7 +1864,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1910,27 +1910,27 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1956,12 +1956,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -2042,7 +2042,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2052,7 +2052,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2090,21 +2090,21 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !7 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]), !llvm.access.group !7 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !7 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2120,7 +2120,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2166,27 +2166,27 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2202,7 +2202,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2212,7 +2212,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2250,21 +2250,21 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !16 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]), !llvm.access.group !16 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !16 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2280,7 +2280,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2326,27 +2326,27 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19 +// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2362,7 +2362,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2372,7 +2372,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2410,41 +2410,41 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 123 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]], %struct.SS* [[TMP0]]), !llvm.access.group !22 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]], %struct.SS* [[TMP0]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP15]], 122 // CHECK4-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] // CHECK4: cond.true5: // CHECK4-NEXT: br label [[COND_END7:%.*]] // CHECK4: cond.false6: -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: br label [[COND_END7]] // CHECK4: cond.end7: // CHECK4-NEXT: [[COND8:%.*]] = phi i32 [ 122, [[COND_TRUE5]] ], [ [[TMP16]], [[COND_FALSE6]] ] -// CHECK4-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK4-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2460,7 +2460,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2506,27 +2506,27 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !25 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2552,12 +2552,12 @@ int main (int argc, char **argv) { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -2677,12 +2677,12 @@ int main (int argc, char **argv) { // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -2802,12 +2802,12 @@ int main (int argc, char **argv) { // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -2924,12 +2924,12 @@ int main (int argc, char **argv) { // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK8-NEXT: ret i32 [[CALL]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -3043,7 +3043,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3274,7 +3274,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT34]] // CHECK9: omp_offload.cont34: // CHECK9-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP102]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) @@ -3283,7 +3283,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -3304,7 +3304,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3367,27 +3367,27 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !9 +// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3412,7 +3412,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3484,27 +3484,27 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !13 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3529,7 +3529,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -3550,7 +3550,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3613,27 +3613,27 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !18 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !18 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !18 +// CHECK9-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3658,7 +3658,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3730,27 +3730,27 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !21 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !21 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3775,7 +3775,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -3804,7 +3804,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3872,55 +3872,55 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK9-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !24 +// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK9-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]), !llvm.access.group !24 +// CHECK9-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 +// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP30]], [[TMP31]] // CHECK9-NEXT: br i1 [[CMP13]], label [[COND_TRUE14:%.*]], label [[COND_FALSE15:%.*]] // CHECK9: cond.true14: -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK9-NEXT: br label [[COND_END16:%.*]] // CHECK9: cond.false15: -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: br label [[COND_END16]] // CHECK9: cond.end16: // CHECK9-NEXT: [[COND17:%.*]] = phi i32 [ [[TMP32]], [[COND_TRUE14]] ], [ [[TMP33]], [[COND_FALSE15]] ] -// CHECK9-NEXT: store i32 [[COND17]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: store i32 [[TMP34]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK9-NEXT: store i32 [[COND17]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP34]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3945,7 +3945,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4020,27 +4020,27 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I7]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I7]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I7]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4065,7 +4065,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -4158,7 +4158,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -4168,7 +4168,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4206,23 +4206,23 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]), !llvm.access.group !30 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4238,7 +4238,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4286,27 +4286,27 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4322,7 +4322,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -4332,7 +4332,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4370,23 +4370,23 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]), !llvm.access.group !36 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4402,7 +4402,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4450,27 +4450,27 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4486,7 +4486,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -4504,7 +4504,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4547,47 +4547,47 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42 +// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP20]], 9 // CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] // CHECK9: cond.true6: // CHECK9-NEXT: br label [[COND_END8:%.*]] // CHECK9: cond.false7: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: br label [[COND_END8]] // CHECK9: cond.end8: // CHECK9-NEXT: [[COND9:%.*]] = phi i32 [ 9, [[COND_TRUE6]] ], [ [[TMP21]], [[COND_FALSE7]] ] -// CHECK9-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK9-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4603,7 +4603,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4654,27 +4654,27 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4697,7 +4697,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4928,7 +4928,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT34]] // CHECK10: omp_offload.cont34: // CHECK10-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP102]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) @@ -4937,7 +4937,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -4958,7 +4958,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5021,27 +5021,27 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !9 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !9 +// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5066,7 +5066,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5138,27 +5138,27 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5183,7 +5183,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -5204,7 +5204,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5267,27 +5267,27 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !18 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !18 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !18 +// CHECK10-NEXT: store i32 [[TMP19]], i32* [[CONV6]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP0]], i32* [[TMP1]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5312,7 +5312,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5384,27 +5384,27 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !21 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !21 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I5]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5429,7 +5429,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -5458,7 +5458,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5526,55 +5526,55 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK10-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[CONV8:%.*]] = bitcast i64* [[N_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !24 +// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV8]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[N_CASTED]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK10-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]), !llvm.access.group !24 +// CHECK10-NEXT: store i32 [[TMP22]], i32* [[CONV9]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP0]], i32* [[TMP1]], i64 [[TMP23]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP30]], [[TMP31]] // CHECK10-NEXT: br i1 [[CMP13]], label [[COND_TRUE14:%.*]], label [[COND_FALSE15:%.*]] // CHECK10: cond.true14: -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 // CHECK10-NEXT: br label [[COND_END16:%.*]] // CHECK10: cond.false15: -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: br label [[COND_END16]] // CHECK10: cond.end16: // CHECK10-NEXT: [[COND17:%.*]] = phi i32 [ [[TMP32]], [[COND_TRUE14]] ], [ [[TMP33]], [[COND_FALSE15]] ] -// CHECK10-NEXT: store i32 [[COND17]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: store i32 [[TMP34]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK10-NEXT: store i32 [[COND17]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP34]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5599,7 +5599,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5674,27 +5674,27 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I7]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I7]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I7]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I7]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5719,7 +5719,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -5812,7 +5812,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -5822,7 +5822,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5860,23 +5860,23 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]), !llvm.access.group !30 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5892,7 +5892,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5940,27 +5940,27 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5976,7 +5976,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -5986,7 +5986,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6024,23 +6024,23 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]), !llvm.access.group !36 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -6056,7 +6056,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6104,27 +6104,27 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -6140,7 +6140,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -6158,7 +6158,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6201,47 +6201,47 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42 +// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP20]], 9 // CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] // CHECK10: cond.true6: // CHECK10-NEXT: br label [[COND_END8:%.*]] // CHECK10: cond.false7: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: br label [[COND_END8]] // CHECK10: cond.end8: // CHECK10-NEXT: [[COND9:%.*]] = phi i32 [ 9, [[COND_TRUE6]] ], [ [[TMP21]], [[COND_FALSE7]] ] -// CHECK10-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK10-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -6257,7 +6257,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6308,27 +6308,27 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -6351,7 +6351,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -6580,7 +6580,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT31]] // CHECK11: omp_offload.cont31: // CHECK11-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP104]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) @@ -6589,7 +6589,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -6608,7 +6608,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6670,24 +6670,24 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !10 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -6712,7 +6712,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6781,26 +6781,26 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !14 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -6825,7 +6825,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -6844,7 +6844,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6906,24 +6906,24 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !19 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !19 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -6948,7 +6948,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7017,26 +7017,26 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !22 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7061,7 +7061,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -7086,7 +7086,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7152,51 +7152,51 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !25 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK11-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: store i32 [[TMP18]], i32* [[N_CASTED]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[N_CASTED]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32 [[TMP19]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP21]]), !llvm.access.group !25 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP18]], i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32 [[TMP19]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP21]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25 +// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25 +// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !25 +// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK11-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP28]], [[TMP29]] // CHECK11-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] // CHECK11: cond.true11: -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !25 +// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK11-NEXT: br label [[COND_END13:%.*]] // CHECK11: cond.false12: -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 +// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: br label [[COND_END13]] // CHECK11: cond.end13: // CHECK11-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP30]], [[COND_TRUE11]] ], [ [[TMP31]], [[COND_FALSE12]] ] -// CHECK11-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: store i32 [[TMP32]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK11-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP32]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7221,7 +7221,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7292,26 +7292,26 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7336,7 +7336,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -7428,7 +7428,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -7438,7 +7438,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7476,21 +7476,21 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !31 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]), !llvm.access.group !31 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !31 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7506,7 +7506,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7552,26 +7552,26 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !34 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !34 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !34 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7587,7 +7587,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -7597,7 +7597,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7635,21 +7635,21 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !37 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !37 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !37 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]), !llvm.access.group !37 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !37 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7665,7 +7665,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7711,26 +7711,26 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !40 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !40 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !40 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !40 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7746,7 +7746,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -7762,7 +7762,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7804,44 +7804,44 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]), !llvm.access.group !43 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9 // CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] // CHECK11: cond.true5: // CHECK11-NEXT: br label [[COND_END7:%.*]] // CHECK11: cond.false6: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: br label [[COND_END7]] // CHECK11: cond.end7: // CHECK11-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ] -// CHECK11-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] +// CHECK11-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7857,7 +7857,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7905,26 +7905,26 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !46 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !46 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !46 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !46 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7947,7 +7947,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -8176,7 +8176,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT31]] // CHECK12: omp_offload.cont31: // CHECK12-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP104]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) @@ -8185,7 +8185,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -8204,7 +8204,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8266,24 +8266,24 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !10 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -8308,7 +8308,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8377,26 +8377,26 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -8421,7 +8421,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -8440,7 +8440,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8502,24 +8502,24 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]), !llvm.access.group !19 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP17]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32 [[TMP18]], i32 [[TMP0]], i32* [[TMP1]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !19 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -8544,7 +8544,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8613,26 +8613,26 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !22 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -8657,7 +8657,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -8682,7 +8682,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8748,51 +8748,51 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !25 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK12-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP14]], [[ADD]] // CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: store i32 [[TMP18]], i32* [[N_CASTED]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[N_CASTED]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32 [[TMP19]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP21]]), !llvm.access.group !25 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP18]], i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[N_CASTED]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32 [[TMP19]], i32 [[TMP0]], i32* [[TMP1]], i32 [[TMP21]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25 +// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP24]], [[TMP25]] -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25 +// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !25 +// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK12-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP28]], [[TMP29]] // CHECK12-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] // CHECK12: cond.true11: -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !25 +// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK12-NEXT: br label [[COND_END13:%.*]] // CHECK12: cond.false12: -// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 +// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: br label [[COND_END13]] // CHECK12: cond.end13: // CHECK12-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP30]], [[COND_TRUE11]] ], [ [[TMP31]], [[COND_FALSE12]] ] -// CHECK12-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: store i32 [[TMP32]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK12-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP32]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -8817,7 +8817,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8888,26 +8888,26 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 [[TMP18]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -8932,7 +8932,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -9024,7 +9024,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l81 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -9034,7 +9034,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9072,21 +9072,21 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !31 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]), !llvm.access.group !31 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !31 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -9102,7 +9102,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9148,26 +9148,26 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !34 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !34 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !34 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -9183,7 +9183,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l85 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -9193,7 +9193,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9231,21 +9231,21 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !37 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !37 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !37 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]), !llvm.access.group !37 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !37 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -9261,7 +9261,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9307,26 +9307,26 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !40 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !40 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !40 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !40 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -9342,7 +9342,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -9358,7 +9358,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9400,44 +9400,44 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]), !llvm.access.group !43 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9 // CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] // CHECK12: cond.true5: // CHECK12-NEXT: br label [[COND_END7:%.*]] // CHECK12: cond.false6: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: br label [[COND_END7]] // CHECK12: cond.end7: // CHECK12-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ] -// CHECK12-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] +// CHECK12-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -9453,7 +9453,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9501,26 +9501,26 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !46 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !46 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !46 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !46 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -9543,7 +9543,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -9738,7 +9738,7 @@ int main (int argc, char **argv) { // CHECK13-NEXT: br label [[SIMD_IF_END68]] // CHECK13: simd.if.end68: // CHECK13-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]]) +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP37]]) // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP38:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP38]]) @@ -9747,7 +9747,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -9863,7 +9863,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -10058,7 +10058,7 @@ int main (int argc, char **argv) { // CHECK14-NEXT: br label [[SIMD_IF_END68]] // CHECK14: simd.if.end68: // CHECK14-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]]) +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP37]]) // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[TMP38:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP38]]) @@ -10067,7 +10067,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -10183,7 +10183,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -10374,7 +10374,7 @@ int main (int argc, char **argv) { // CHECK15-NEXT: br label [[SIMD_IF_END66]] // CHECK15: simd.if.end66: // CHECK15-NEXT: [[TMP36:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP36]]) // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP37:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP37]]) @@ -10383,7 +10383,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -10496,7 +10496,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -10687,7 +10687,7 @@ int main (int argc, char **argv) { // CHECK16-NEXT: br label [[SIMD_IF_END66]] // CHECK16: simd.if.end66: // CHECK16-NEXT: [[TMP36:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP36]]) // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[TMP37:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP37]]) @@ -10696,7 +10696,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp index 278b3bd4256165a715dcd7e8144b018ecdaec265..501b5b289eb27e254a9a0b3c275d87a78dcc4bc9 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp @@ -201,33 +201,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -240,7 +240,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -251,14 +251,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -266,12 +266,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -279,7 +279,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -287,7 +287,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -306,7 +306,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -380,12 +380,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK1-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -417,7 +417,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -467,17 +467,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -496,33 +496,33 @@ int main() { // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5 +// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5 +// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -536,14 +536,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done11: @@ -551,17 +551,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -569,22 +569,22 @@ int main() { // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -642,17 +642,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done6: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -671,40 +671,40 @@ int main() { // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9 -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !9 +// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -718,14 +718,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done15: @@ -747,14 +747,14 @@ int main() { // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -812,17 +812,17 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP30]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -835,7 +835,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -855,7 +855,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -864,17 +864,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -882,12 +882,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK1-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -914,7 +914,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -963,18 +963,18 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -994,30 +994,30 @@ int main() { // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14 +// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 +// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1031,14 +1031,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done11: @@ -1046,7 +1046,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1054,12 +1054,12 @@ int main() { // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1117,18 +1117,18 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done6: // CHECK1-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK1-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -1148,37 +1148,37 @@ int main() { // CHECK1-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK1-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8* // CHECK1-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false), !llvm.access.group !17 +// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1192,14 +1192,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done15: @@ -1207,17 +1207,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1229,7 +1229,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1245,7 +1245,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1264,7 +1264,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1291,33 +1291,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1330,7 +1330,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1341,14 +1341,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1356,12 +1356,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1369,7 +1369,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1377,7 +1377,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1396,7 +1396,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -1470,12 +1470,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK2-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -1507,7 +1507,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1557,17 +1557,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1586,33 +1586,33 @@ int main() { // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5 +// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 +// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5 +// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 +// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1626,14 +1626,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done11: @@ -1641,17 +1641,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1659,22 +1659,22 @@ int main() { // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1732,17 +1732,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done6: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1761,40 +1761,40 @@ int main() { // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9 -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !9 +// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1808,14 +1808,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done15: @@ -1837,14 +1837,14 @@ int main() { // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1902,17 +1902,17 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP30]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1925,7 +1925,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1945,7 +1945,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1954,17 +1954,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1972,12 +1972,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK2-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -2004,7 +2004,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2053,18 +2053,18 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -2084,30 +2084,30 @@ int main() { // CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14 +// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 +// CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2121,14 +2121,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done11: @@ -2136,7 +2136,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -2144,12 +2144,12 @@ int main() { // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2207,18 +2207,18 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done6: // CHECK2-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK2-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -2238,37 +2238,37 @@ int main() { // CHECK2-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 +// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK2-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8* // CHECK2-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false), !llvm.access.group !17 +// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2282,14 +2282,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done15: @@ -2297,17 +2297,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2319,7 +2319,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2335,7 +2335,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -2354,7 +2354,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2381,33 +2381,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2420,7 +2420,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2431,14 +2431,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2446,12 +2446,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -2459,7 +2459,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -2467,7 +2467,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2486,7 +2486,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -2558,12 +2558,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK3-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -2591,7 +2591,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2639,17 +2639,17 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done3: -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2668,29 +2668,29 @@ int main() { // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]), !llvm.access.group !6 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2704,14 +2704,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done8: @@ -2719,17 +2719,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2737,22 +2737,22 @@ int main() { // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2806,17 +2806,17 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done3: -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2835,38 +2835,38 @@ int main() { // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]] -// CHECK3-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]] // CHECK3-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* // CHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !10 -// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) +// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2880,14 +2880,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -2909,14 +2909,14 @@ int main() { // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2973,17 +2973,17 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP30]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2996,7 +2996,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -3016,7 +3016,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -3025,17 +3025,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3043,12 +3043,12 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK3-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -3073,7 +3073,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3121,18 +3121,18 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done4: // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -3152,27 +3152,27 @@ int main() { // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]), !llvm.access.group !15 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -3186,14 +3186,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done10: @@ -3201,7 +3201,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3209,12 +3209,12 @@ int main() { // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3269,18 +3269,18 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done4: // CHECK3-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -3300,35 +3300,35 @@ int main() { // CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]] -// CHECK3-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]] // CHECK3-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* // CHECK3-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false), !llvm.access.group !18 +// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -3342,14 +3342,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -3357,17 +3357,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3379,7 +3379,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3395,7 +3395,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3414,7 +3414,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3441,33 +3441,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3480,7 +3480,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3491,14 +3491,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3506,12 +3506,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -3519,7 +3519,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -3527,7 +3527,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3546,7 +3546,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -3618,12 +3618,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK4-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -3651,7 +3651,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3699,17 +3699,17 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done3: -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3728,29 +3728,29 @@ int main() { // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]), !llvm.access.group !6 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -3764,14 +3764,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done8: @@ -3779,17 +3779,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -3797,22 +3797,22 @@ int main() { // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3866,17 +3866,17 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done3: -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3895,38 +3895,38 @@ int main() { // CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]] -// CHECK4-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]] // CHECK4-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* // CHECK4-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !10 -// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) +// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK4-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -3940,14 +3940,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done11: @@ -3969,14 +3969,14 @@ int main() { // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4033,17 +4033,17 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP30]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -4056,7 +4056,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -4076,7 +4076,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -4085,17 +4085,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4103,12 +4103,12 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK4-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -4133,7 +4133,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4181,18 +4181,18 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done4: // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -4212,27 +4212,27 @@ int main() { // CHECK4-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]), !llvm.access.group !15 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -4246,14 +4246,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done10: @@ -4261,7 +4261,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -4269,12 +4269,12 @@ int main() { // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4329,18 +4329,18 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done4: // CHECK4-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -4360,35 +4360,35 @@ int main() { // CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]] -// CHECK4-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]] // CHECK4-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* // CHECK4-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false), !llvm.access.group !18 +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -4402,14 +4402,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done12: @@ -4417,17 +4417,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4439,7 +4439,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4455,7 +4455,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -4474,7 +4474,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4501,33 +4501,33 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4540,7 +4540,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4551,14 +4551,14 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4566,12 +4566,12 @@ int main() { // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4579,7 +4579,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -4587,7 +4587,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4606,7 +4606,7 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // @@ -4617,12 +4617,12 @@ int main() { // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK5-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK5-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -4656,7 +4656,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4705,36 +4705,36 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* -// CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4 -// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4 -// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 -// CHECK5-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !4 +// CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK5-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 // CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* -// CHECK5-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4 -// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4 -// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8, !llvm.access.group !4 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK5-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4 -// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4 +// CHECK5-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 +// CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4750,7 +4750,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4807,35 +4807,35 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK5-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 -// CHECK5-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8 -// CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[CONV]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK5-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK5-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8 +// CHECK5-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 -// CHECK5-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK5-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK5-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8 -// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK5-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4869,33 +4869,33 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4908,7 +4908,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4919,14 +4919,14 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4934,12 +4934,12 @@ int main() { // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4947,7 +4947,7 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: @@ -4955,7 +4955,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4974,7 +4974,7 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // @@ -4985,12 +4985,12 @@ int main() { // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK6-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK6-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -5024,7 +5024,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5073,36 +5073,36 @@ int main() { // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK6-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* -// CHECK6-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4 -// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4 -// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 -// CHECK6-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !4 +// CHECK6-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK6-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 // CHECK6-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* -// CHECK6-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4 -// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4 -// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8, !llvm.access.group !4 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK6-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK6-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4 -// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4 +// CHECK6-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 +// CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5118,7 +5118,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5175,35 +5175,35 @@ int main() { // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK6-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 -// CHECK6-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8 -// CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[CONV]], align 8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK6-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK6-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8 +// CHECK6-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 -// CHECK6-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK6-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK6-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8 -// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK6-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5237,42 +5237,42 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5280,12 +5280,12 @@ int main() { // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -5293,7 +5293,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -5303,7 +5303,7 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // @@ -5357,7 +5357,7 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK7-NEXT: ret i32 [[CALL]] // // @@ -5376,14 +5376,14 @@ int main() { // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -5434,17 +5434,17 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done5: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP17]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5457,7 +5457,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5466,7 +5466,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5483,17 +5483,17 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5501,22 +5501,22 @@ int main() { // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5528,7 +5528,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5544,7 +5544,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5564,42 +5564,42 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5607,12 +5607,12 @@ int main() { // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -5620,7 +5620,7 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done1: @@ -5630,7 +5630,7 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // @@ -5684,7 +5684,7 @@ int main() { // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK8-NEXT: ret i32 [[CALL]] // // @@ -5703,14 +5703,14 @@ int main() { // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -5761,17 +5761,17 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done5: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP17]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5784,7 +5784,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5793,7 +5793,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5810,17 +5810,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5828,22 +5828,22 @@ int main() { // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5855,7 +5855,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5871,7 +5871,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5891,42 +5891,42 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5934,12 +5934,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -5947,7 +5947,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -5957,7 +5957,7 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // @@ -6009,7 +6009,7 @@ int main() { // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK9-NEXT: ret i32 [[CALL]] // // @@ -6028,14 +6028,14 @@ int main() { // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -6084,17 +6084,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done4: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP17]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -6107,7 +6107,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -6116,7 +6116,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6133,17 +6133,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6151,22 +6151,22 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -6178,7 +6178,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6194,7 +6194,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -6214,42 +6214,42 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6257,12 +6257,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -6270,7 +6270,7 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: @@ -6280,7 +6280,7 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // @@ -6332,7 +6332,7 @@ int main() { // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK10-NEXT: ret i32 [[CALL]] // // @@ -6351,14 +6351,14 @@ int main() { // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -6407,17 +6407,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done4: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP17]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -6430,7 +6430,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -6439,7 +6439,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6456,17 +6456,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6474,22 +6474,22 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -6501,7 +6501,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6517,7 +6517,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -6537,42 +6537,42 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6580,12 +6580,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -6593,7 +6593,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -6603,7 +6603,7 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // @@ -6614,12 +6614,12 @@ int main() { // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: ret i32 0 // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6632,7 +6632,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6641,7 +6641,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6669,42 +6669,42 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6712,12 +6712,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -6725,7 +6725,7 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done1: @@ -6735,7 +6735,7 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // @@ -6746,12 +6746,12 @@ int main() { // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK12-NEXT: ret i32 0 // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6764,7 +6764,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6773,7 +6773,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6799,7 +6799,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK13-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -6831,7 +6831,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6881,17 +6881,17 @@ int main() { // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done4: -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -6910,33 +6910,33 @@ int main() { // CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13: omp.inner.for.cond.cleanup: // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !6 +// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK13-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !6 -// CHECK13-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !6 -// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !6 +// CHECK13-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 +// CHECK13-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !6 -// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !6 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !6 +// CHECK13-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 +// CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -6950,14 +6950,14 @@ int main() { // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -6965,17 +6965,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK13-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -6983,22 +6983,22 @@ int main() { // CHECK13-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK13-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7056,17 +7056,17 @@ int main() { // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done6: -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] // CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -7085,40 +7085,40 @@ int main() { // CHECK13-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13: omp.inner.for.cond.cleanup: // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !10 -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK13-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK13-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !10 -// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !10 +// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) +// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK13-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK13-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !10 +// CHECK13-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK13-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -7132,14 +7132,14 @@ int main() { // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: @@ -7147,17 +7147,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK13-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK13-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -7184,7 +7184,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7233,18 +7233,18 @@ int main() { // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done4: // CHECK13-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK13-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -7264,30 +7264,30 @@ int main() { // CHECK13-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13: omp.inner.for.cond.cleanup: // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !15 +// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK13-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !15 -// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !15 -// CHECK13-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !15 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !15 +// CHECK13-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 +// CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK13-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -7301,14 +7301,14 @@ int main() { // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -7316,7 +7316,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -7324,12 +7324,12 @@ int main() { // CHECK13-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7387,18 +7387,18 @@ int main() { // CHECK13: omp.arraycpy.body: // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK13: omp.arraycpy.done6: // CHECK13-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] // CHECK13-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK13-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -7418,37 +7418,37 @@ int main() { // CHECK13-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13: omp.inner.for.cond.cleanup: // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !18 -// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK13-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !18 -// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK13-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 +// CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK13-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK13-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8* // CHECK13-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false), !llvm.access.group !18 +// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false) // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK13-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -7462,14 +7462,14 @@ int main() { // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: @@ -7477,17 +7477,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK13-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -7500,7 +7500,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK13-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK13-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -7509,7 +7509,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -7518,7 +7518,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -7538,7 +7538,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -7547,7 +7547,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -7566,7 +7566,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK14-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -7598,7 +7598,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7648,17 +7648,17 @@ int main() { // CHECK14: omp.arraycpy.body: // CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] // CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK14: omp.arraycpy.done4: -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -7677,33 +7677,33 @@ int main() { // CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14: omp.inner.for.cond.cleanup: // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK14-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !6 -// CHECK14-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !6 -// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !6 +// CHECK14-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 +// CHECK14-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !6 -// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !6 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !6 +// CHECK14-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 +// CHECK14-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -7717,14 +7717,14 @@ int main() { // CHECK14-NEXT: store i32 2, i32* [[I]], align 4 // CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK14: .omp.final.done: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK14-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done11: @@ -7732,17 +7732,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK14-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -7750,22 +7750,22 @@ int main() { // CHECK14-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK14-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7823,17 +7823,17 @@ int main() { // CHECK14: omp.arraycpy.body: // CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK14: omp.arraycpy.done6: -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] // CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -7852,40 +7852,40 @@ int main() { // CHECK14-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK14-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14: omp.inner.for.cond.cleanup: // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !10 -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK14-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK14-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK14-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK14-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !10 -// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !10 +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) +// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK14-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !10 +// CHECK14-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -7899,14 +7899,14 @@ int main() { // CHECK14-NEXT: store i32 2, i32* [[I]], align 4 // CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK14: .omp.final.done: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK14-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done15: @@ -7914,17 +7914,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK14-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK14-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -7951,7 +7951,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8000,18 +8000,18 @@ int main() { // CHECK14: omp.arraycpy.body: // CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK14: omp.arraycpy.done4: // CHECK14-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK14-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -8031,30 +8031,30 @@ int main() { // CHECK14-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14: omp.inner.for.cond.cleanup: // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK14-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !15 -// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !15 -// CHECK14-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !15 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !15 +// CHECK14-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 +// CHECK14-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK14-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -8068,14 +8068,14 @@ int main() { // CHECK14-NEXT: store i32 2, i32* [[I]], align 4 // CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK14: .omp.final.done: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK14-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done11: @@ -8083,7 +8083,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -8091,12 +8091,12 @@ int main() { // CHECK14-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8154,18 +8154,18 @@ int main() { // CHECK14: omp.arraycpy.body: // CHECK14-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK14-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK14-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK14-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK14-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK14: omp.arraycpy.done6: // CHECK14-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]]) #[[ATTR4]] -// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR5]] // CHECK14-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK14-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -8185,37 +8185,37 @@ int main() { // CHECK14-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK14-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14: omp.inner.for.cond.cleanup: // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !18 -// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK14-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK14-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !18 -// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 +// CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK14-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK14-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK14-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8* // CHECK14-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false), !llvm.access.group !18 +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false) // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -8229,14 +8229,14 @@ int main() { // CHECK14-NEXT: store i32 2, i32* [[I]], align 4 // CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK14: .omp.final.done: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK14-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done15: @@ -8244,17 +8244,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK14-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -8267,7 +8267,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK14-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK14-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -8276,7 +8276,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -8285,7 +8285,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -8305,7 +8305,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -8314,7 +8314,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -8333,7 +8333,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK15-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -8361,7 +8361,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8409,17 +8409,17 @@ int main() { // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done3: -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -8438,29 +8438,29 @@ int main() { // CHECK15-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK15-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK15: omp.inner.for.cond.cleanup: // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]), !llvm.access.group !7 +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4 +// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4 +// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]) // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !7 +// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK15: omp.loop.exit: @@ -8474,14 +8474,14 @@ int main() { // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done8: @@ -8489,17 +8489,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK15-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -8507,22 +8507,22 @@ int main() { // CHECK15-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK15-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8576,17 +8576,17 @@ int main() { // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done3: -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -8605,38 +8605,38 @@ int main() { // CHECK15-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK15-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK15: omp.inner.for.cond.cleanup: // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !11 -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]] -// CHECK15-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK15-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]] // CHECK15-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* // CHECK15-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !11 -// CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 -// CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !11 +// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) +// CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 // CHECK15-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK15-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !11 +// CHECK15-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK15-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK15-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK15: omp.loop.exit: @@ -8650,14 +8650,14 @@ int main() { // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done11: @@ -8665,17 +8665,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK15-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK15-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -8700,7 +8700,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8748,18 +8748,18 @@ int main() { // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done4: // CHECK15-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK15-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -8779,27 +8779,27 @@ int main() { // CHECK15-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK15: omp.inner.for.cond.cleanup: // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !16 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !16 -// CHECK15-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !16 -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !16 -// CHECK15-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !16 -// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]), !llvm.access.group !16 +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK15-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4 +// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK15-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]) // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !16 +// CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK15: omp.loop.exit: @@ -8813,14 +8813,14 @@ int main() { // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: @@ -8828,7 +8828,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -8836,12 +8836,12 @@ int main() { // CHECK15-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8896,18 +8896,18 @@ int main() { // CHECK15: omp.arraycpy.body: // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK15: omp.arraycpy.done4: // CHECK15-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK15-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -8927,35 +8927,35 @@ int main() { // CHECK15-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK15: omp.inner.for.cond.cleanup: // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 -// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !19 -// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]] -// CHECK15-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !19 -// CHECK15-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !19 -// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK15-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]] // CHECK15-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* // CHECK15-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false), !llvm.access.group !19 +// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false) // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK15-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK15-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK15: omp.loop.exit: @@ -8969,14 +8969,14 @@ int main() { // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done12: @@ -8984,17 +8984,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK15-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -9007,7 +9007,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK15-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK15-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -9016,7 +9016,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -9025,7 +9025,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -9045,7 +9045,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -9054,7 +9054,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -9073,7 +9073,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122 -// CHECK16-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -9101,7 +9101,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9149,17 +9149,17 @@ int main() { // CHECK16: omp.arraycpy.body: // CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4:[0-9]+]] -// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5:[0-9]+]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5:[0-9]+]] // CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK16: omp.arraycpy.done3: -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] // CHECK16-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -9178,29 +9178,29 @@ int main() { // CHECK16-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK16-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK16: omp.inner.for.cond.cleanup: // CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]), !llvm.access.group !7 +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]) // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK16: omp.loop.exit: @@ -9214,14 +9214,14 @@ int main() { // CHECK16-NEXT: store i32 2, i32* [[I]], align 4 // CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK16: .omp.final.done: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK16-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done8: @@ -9229,17 +9229,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK16-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -9247,22 +9247,22 @@ int main() { // CHECK16-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK16-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9316,17 +9316,17 @@ int main() { // CHECK16: omp.arraycpy.body: // CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK16: omp.arraycpy.done3: -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] // CHECK16-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -9345,38 +9345,38 @@ int main() { // CHECK16-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK16-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK16: omp.inner.for.cond.cleanup: // CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !11 -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]] -// CHECK16-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]] // CHECK16-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* // CHECK16-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !11 -// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 -// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) +// CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 // CHECK16-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK16-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK16: omp.body.continue: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK16-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK16-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK16: omp.loop.exit: @@ -9390,14 +9390,14 @@ int main() { // CHECK16-NEXT: store i32 2, i32* [[I]], align 4 // CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK16: .omp.final.done: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK16-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done11: @@ -9405,17 +9405,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 -// CHECK16-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK16-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -9440,7 +9440,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9488,18 +9488,18 @@ int main() { // CHECK16: omp.arraycpy.body: // CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK16: omp.arraycpy.done4: // CHECK16-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK16-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -9519,27 +9519,27 @@ int main() { // CHECK16-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK16-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK16-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK16: omp.inner.for.cond.cleanup: // CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !16 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !16 -// CHECK16-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !16 -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !16 -// CHECK16-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !16 -// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]), !llvm.access.group !16 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]) // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK16: omp.loop.exit: @@ -9553,14 +9553,14 @@ int main() { // CHECK16-NEXT: store i32 2, i32* [[I]], align 4 // CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK16: .omp.final.done: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK16-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done10: @@ -9568,7 +9568,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -9576,12 +9576,12 @@ int main() { // CHECK16-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9636,18 +9636,18 @@ int main() { // CHECK16: omp.arraycpy.body: // CHECK16-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK16-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] // CHECK16-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK16-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK16-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK16: omp.arraycpy.done4: // CHECK16-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]]) #[[ATTR4]] -// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR5]] // CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK16-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -9667,35 +9667,35 @@ int main() { // CHECK16-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK16-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK16: omp.inner.for.cond.cleanup: // CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 -// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !19 -// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]] -// CHECK16-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !19 -// CHECK16-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !19 -// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK16-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]] // CHECK16-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* // CHECK16-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false), !llvm.access.group !19 +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false) // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK16: omp.body.continue: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK16-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK16-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK16: omp.loop.exit: @@ -9709,14 +9709,14 @@ int main() { // CHECK16-NEXT: store i32 2, i32* [[I]], align 4 // CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK16: .omp.final.done: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK16-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done12: @@ -9724,17 +9724,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK16-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -9747,7 +9747,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK16-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK16-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -9756,7 +9756,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -9765,7 +9765,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -9785,7 +9785,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -9794,7 +9794,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -9813,7 +9813,7 @@ int main() { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK17-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -9847,7 +9847,7 @@ int main() { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9896,36 +9896,36 @@ int main() { // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !5 -// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !5 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !5 -// CHECK17-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !5 +// CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 +// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK17-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !5 -// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !5 -// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8, !llvm.access.group !5 +// CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 +// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK17-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !5 -// CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !5 +// CHECK17-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 +// CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -9941,7 +9941,7 @@ int main() { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9998,35 +9998,35 @@ int main() { // CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !9 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !9 -// CHECK17-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !9 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK17-NEXT: store i32 1, i32* [[CONV]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK17-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK17-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK17-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !9 +// CHECK17-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !9 -// CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !9 +// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK17-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !9 -// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* noundef [[REF_TMP]]) #[[ATTR3:[0-9]+]], !llvm.access.group !9 +// CHECK17-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 +// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -10044,42 +10044,42 @@ int main() { // CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK18-SAME: () #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK18-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK18-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK18-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK18-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK18-SAME: () #[[ATTR0]] { // CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK18-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -10087,12 +10087,12 @@ int main() { // CHECK18-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK18-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK18-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK18-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -10100,7 +10100,7 @@ int main() { // CHECK18: arraydestroy.body: // CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK18: arraydestroy.done1: @@ -10110,7 +10110,7 @@ int main() { // CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK18-SAME: () #[[ATTR0]] { // CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK18-NEXT: ret void // @@ -10164,7 +10164,7 @@ int main() { // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK18: omp.inner.for.end: // CHECK18-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK18-NEXT: ret i32 [[CALL]] // // @@ -10183,14 +10183,14 @@ int main() { // CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK18-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK18-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK18-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK18-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK18-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK18-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -10241,17 +10241,17 @@ int main() { // CHECK18: arraydestroy.body: // CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK18: arraydestroy.done5: -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK18-NEXT: ret i32 [[TMP17]] // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK18-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -10264,7 +10264,7 @@ int main() { // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK18-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -10273,7 +10273,7 @@ int main() { // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK18-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -10290,17 +10290,17 @@ int main() { // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK18-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK18-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK18-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -10308,22 +10308,22 @@ int main() { // CHECK18-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK18-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK18-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK18-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -10335,7 +10335,7 @@ int main() { // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK18-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -10351,7 +10351,7 @@ int main() { // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK18-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -10371,42 +10371,42 @@ int main() { // CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK19-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK19-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK19-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK19-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK19-SAME: () #[[ATTR0]] { // CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK19-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -10414,12 +10414,12 @@ int main() { // CHECK19-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK19-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK19-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK19-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK19-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK19-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -10427,7 +10427,7 @@ int main() { // CHECK19: arraydestroy.body: // CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK19-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK19: arraydestroy.done1: @@ -10437,7 +10437,7 @@ int main() { // CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK19-SAME: () #[[ATTR0]] { // CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK19-NEXT: ret void // @@ -10491,7 +10491,7 @@ int main() { // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK19-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK19-NEXT: ret i32 [[CALL]] // // @@ -10510,14 +10510,14 @@ int main() { // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK19-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK19-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK19-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK19-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK19-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -10568,17 +10568,17 @@ int main() { // CHECK19: arraydestroy.body: // CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK19-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK19: arraydestroy.done5: -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK19-NEXT: ret i32 [[TMP17]] // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK19-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -10591,7 +10591,7 @@ int main() { // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK19-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -10600,7 +10600,7 @@ int main() { // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK19-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -10617,17 +10617,17 @@ int main() { // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK19-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK19-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK19-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -10635,22 +10635,22 @@ int main() { // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK19-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK19-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK19-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK19-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -10662,7 +10662,7 @@ int main() { // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK19-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -10678,7 +10678,7 @@ int main() { // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK19-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -10698,42 +10698,42 @@ int main() { // CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK20-SAME: () #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK20-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK20-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK20-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK20-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK20-SAME: () #[[ATTR0]] { // CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK20-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -10741,12 +10741,12 @@ int main() { // CHECK20-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK20-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK20-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK20-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -10754,7 +10754,7 @@ int main() { // CHECK20: arraydestroy.body: // CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK20-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK20: arraydestroy.done1: @@ -10764,7 +10764,7 @@ int main() { // CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK20-SAME: () #[[ATTR0]] { // CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK20-NEXT: ret void // @@ -10816,7 +10816,7 @@ int main() { // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK20: omp.inner.for.end: // CHECK20-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK20-NEXT: ret i32 [[CALL]] // // @@ -10835,14 +10835,14 @@ int main() { // CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK20-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK20-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK20-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK20-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK20-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -10891,17 +10891,17 @@ int main() { // CHECK20: arraydestroy.body: // CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK20-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK20: arraydestroy.done4: -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK20-NEXT: ret i32 [[TMP17]] // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK20-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -10914,7 +10914,7 @@ int main() { // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK20-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -10923,7 +10923,7 @@ int main() { // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK20-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -10940,17 +10940,17 @@ int main() { // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK20-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK20-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK20-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -10958,22 +10958,22 @@ int main() { // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK20-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK20-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK20-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK20-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -10985,7 +10985,7 @@ int main() { // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK20-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -11001,7 +11001,7 @@ int main() { // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK20-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -11021,42 +11021,42 @@ int main() { // CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK21-SAME: () #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK21-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK21-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK21-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK21-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK21-SAME: () #[[ATTR0]] { // CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK21-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -11064,12 +11064,12 @@ int main() { // CHECK21-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK21-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK21-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK21-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK21-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -11077,7 +11077,7 @@ int main() { // CHECK21: arraydestroy.body: // CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK21: arraydestroy.done1: @@ -11087,7 +11087,7 @@ int main() { // CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK21-SAME: () #[[ATTR0]] { // CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK21-NEXT: ret void // @@ -11139,7 +11139,7 @@ int main() { // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK21-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK21-NEXT: ret i32 [[CALL]] // // @@ -11158,14 +11158,14 @@ int main() { // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK21-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK21-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK21-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK21-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK21-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK21-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK21-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK21-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -11214,17 +11214,17 @@ int main() { // CHECK21: arraydestroy.body: // CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK21: arraydestroy.done4: -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK21-NEXT: ret i32 [[TMP17]] // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK21-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -11237,7 +11237,7 @@ int main() { // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK21-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -11246,7 +11246,7 @@ int main() { // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK21-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -11263,17 +11263,17 @@ int main() { // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK21-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK21-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK21-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -11281,22 +11281,22 @@ int main() { // CHECK21-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK21-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK21-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK21-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK21-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -11308,7 +11308,7 @@ int main() { // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK21-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -11324,7 +11324,7 @@ int main() { // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK21-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -11344,42 +11344,42 @@ int main() { // CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK22-SAME: () #[[ATTR0:[0-9]+]] { // CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK22-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK22-NEXT: ret void // // // CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK22-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK22-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK22-NEXT: ret void // // // CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK22-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK22-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK22-NEXT: ret void // // // CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK22-SAME: () #[[ATTR0]] { // CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK22-NEXT: ret void // // // CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK22-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -11387,12 +11387,12 @@ int main() { // CHECK22-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK22-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK22-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK22-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK22-NEXT: ret void // // // CHECK22-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK22-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK22-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -11400,7 +11400,7 @@ int main() { // CHECK22: arraydestroy.body: // CHECK22-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK22-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK22-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK22-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK22-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK22-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK22: arraydestroy.done1: @@ -11410,7 +11410,7 @@ int main() { // CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK22-SAME: () #[[ATTR0]] { // CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK22-NEXT: ret void // @@ -11421,12 +11421,12 @@ int main() { // CHECK22-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK22-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK22-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK22-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK22-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK22-NEXT: ret i32 0 // // // CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK22-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -11439,7 +11439,7 @@ int main() { // // // CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK22-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -11448,7 +11448,7 @@ int main() { // // // CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK22-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp index 3582801ccd7ed6199fa7b1480b633b24b263ceb2..f21b6fa5ae214450481b29101a9fe101db6b8550 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp @@ -151,7 +151,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 -// CHECK1-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 @@ -166,7 +166,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -241,7 +241,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -329,7 +329,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -401,7 +401,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -540,7 +540,7 @@ int main() { // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -552,7 +552,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -619,7 +619,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -704,7 +704,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -776,7 +776,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -854,7 +854,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK1-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -871,7 +871,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -955,7 +955,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1033,7 +1033,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK1-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1095,7 +1095,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1162,7 +1162,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1247,7 +1247,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1319,7 +1319,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1397,7 +1397,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 -// CHECK1-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -1414,7 +1414,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1498,7 +1498,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1625,7 +1625,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 -// CHECK2-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 @@ -1640,7 +1640,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1715,7 +1715,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1803,7 +1803,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1875,7 +1875,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2014,7 +2014,7 @@ int main() { // CHECK2-NEXT: br label [[OMP_IF_END]] // CHECK2: omp_if.end: // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -2026,7 +2026,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2093,7 +2093,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2178,7 +2178,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2250,7 +2250,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2328,7 +2328,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK2-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -2345,7 +2345,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2429,7 +2429,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2507,7 +2507,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK2-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -2569,7 +2569,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2636,7 +2636,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2721,7 +2721,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2793,7 +2793,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2871,7 +2871,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 -// CHECK2-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -2888,7 +2888,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2972,7 +2972,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3099,7 +3099,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45 -// CHECK3-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 @@ -3114,7 +3114,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3189,7 +3189,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3277,7 +3277,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3349,7 +3349,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3488,7 +3488,7 @@ int main() { // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -3500,7 +3500,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3567,7 +3567,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3652,7 +3652,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3724,7 +3724,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3802,7 +3802,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK3-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -3819,7 +3819,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3959,7 +3959,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4087,7 +4087,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4215,7 +4215,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK3-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK3-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -4277,7 +4277,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4344,7 +4344,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4429,7 +4429,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4501,7 +4501,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4579,7 +4579,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 -// CHECK3-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -4596,7 +4596,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4680,7 +4680,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4807,7 +4807,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45 -// CHECK4-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 @@ -4822,7 +4822,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4897,7 +4897,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4985,7 +4985,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5057,7 +5057,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5196,7 +5196,7 @@ int main() { // CHECK4-NEXT: br label [[OMP_IF_END]] // CHECK4: omp_if.end: // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK4-NEXT: ret i32 [[CALL]] // // @@ -5208,7 +5208,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5275,7 +5275,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5360,7 +5360,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5432,7 +5432,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5510,7 +5510,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK4-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -5527,7 +5527,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5667,7 +5667,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5795,7 +5795,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5923,7 +5923,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK4-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK4-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -5985,7 +5985,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6052,7 +6052,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6137,7 +6137,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6209,7 +6209,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6287,7 +6287,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 -// CHECK4-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -6304,7 +6304,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6388,7 +6388,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6644,12 +6644,12 @@ int main() { // CHECK5: omp.inner.for.end29: // CHECK5-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* @Arg, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP16]]) +// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP16]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK5-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK5-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -6926,12 +6926,12 @@ int main() { // CHECK6: omp.inner.for.end29: // CHECK6-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* @Arg, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP16]]) +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP16]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK6-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK6-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -7237,12 +7237,12 @@ int main() { // CHECK7: omp_if.end: // CHECK7-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP21]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP21]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK7-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK7-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -7548,12 +7548,12 @@ int main() { // CHECK8: omp_if.end: // CHECK8-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP21]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP21]]) // CHECK8-NEXT: ret i32 [[CALL]] // // // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK8-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK8-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -7701,7 +7701,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 -// CHECK9-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 @@ -7716,7 +7716,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7791,7 +7791,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7879,7 +7879,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7951,7 +7951,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8090,7 +8090,7 @@ int main() { // CHECK9-NEXT: br label [[OMP_IF_END]] // CHECK9: omp_if.end: // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK9-NEXT: ret i32 [[CALL]] // // @@ -8102,7 +8102,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8169,7 +8169,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8254,7 +8254,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8326,7 +8326,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8404,7 +8404,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -8421,7 +8421,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8505,7 +8505,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8583,7 +8583,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK9-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK9-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -8645,7 +8645,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8712,7 +8712,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8797,7 +8797,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8869,7 +8869,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8947,7 +8947,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -8964,7 +8964,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9048,7 +9048,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9175,7 +9175,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l47 -// CHECK10-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 @@ -9190,7 +9190,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9265,7 +9265,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9353,7 +9353,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9425,7 +9425,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9564,7 +9564,7 @@ int main() { // CHECK10-NEXT: br label [[OMP_IF_END]] // CHECK10: omp_if.end: // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK10-NEXT: ret i32 [[CALL]] // // @@ -9576,7 +9576,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9643,7 +9643,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9728,7 +9728,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9800,7 +9800,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9878,7 +9878,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK10-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -9895,7 +9895,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9979,7 +9979,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10057,7 +10057,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK10-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK10-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -10119,7 +10119,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10186,7 +10186,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10271,7 +10271,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10343,7 +10343,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10421,7 +10421,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 -// CHECK10-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -10438,7 +10438,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10522,7 +10522,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10649,7 +10649,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45 -// CHECK11-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 @@ -10664,7 +10664,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10739,7 +10739,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10827,7 +10827,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10899,7 +10899,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11038,7 +11038,7 @@ int main() { // CHECK11-NEXT: br label [[OMP_IF_END]] // CHECK11: omp_if.end: // CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK11-NEXT: ret i32 [[CALL]] // // @@ -11050,7 +11050,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11117,7 +11117,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11202,7 +11202,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11274,7 +11274,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11352,7 +11352,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK11-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -11369,7 +11369,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11509,7 +11509,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11637,7 +11637,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11765,7 +11765,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK11-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK11-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -11827,7 +11827,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11894,7 +11894,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11979,7 +11979,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12051,7 +12051,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12129,7 +12129,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 -// CHECK11-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -12146,7 +12146,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12230,7 +12230,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12357,7 +12357,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l45 -// CHECK12-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[ARG_CASTED:%.*]] = alloca i64, align 8 @@ -12372,7 +12372,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12447,7 +12447,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12535,7 +12535,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12607,7 +12607,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12746,7 +12746,7 @@ int main() { // CHECK12-NEXT: br label [[OMP_IF_END]] // CHECK12: omp_if.end: // CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* @Arg, align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP17]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP17]]) // CHECK12-NEXT: ret i32 [[CALL]] // // @@ -12758,7 +12758,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12825,7 +12825,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12910,7 +12910,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12982,7 +12982,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13060,7 +13060,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK12-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -13077,7 +13077,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13217,7 +13217,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13345,7 +13345,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13473,7 +13473,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK12-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK12-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -13535,7 +13535,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13602,7 +13602,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13687,7 +13687,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13759,7 +13759,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13837,7 +13837,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l70 -// CHECK12-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 @@ -13854,7 +13854,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13938,7 +13938,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14194,12 +14194,12 @@ int main() { // CHECK13: omp.inner.for.end29: // CHECK13-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* @Arg, align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP16]]) +// CHECK13-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP16]]) // CHECK13-NEXT: ret i32 [[CALL]] // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK13-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK13-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -14476,12 +14476,12 @@ int main() { // CHECK14: omp.inner.for.end29: // CHECK14-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* @Arg, align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP16]]) +// CHECK14-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP16]]) // CHECK14-NEXT: ret i32 [[CALL]] // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK14-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK14-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -14787,12 +14787,12 @@ int main() { // CHECK15: omp_if.end: // CHECK15-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* @Arg, align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP21]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP21]]) // CHECK15-NEXT: ret i32 [[CALL]] // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK15-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK15-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -15098,12 +15098,12 @@ int main() { // CHECK16: omp_if.end: // CHECK16-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* @Arg, align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP21]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP21]]) // CHECK16-NEXT: ret i32 [[CALL]] // // // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK16-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK16-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp index d9d1969aa1fe811c9eae074f360c577cccee3174..07d47f3a78f42910c37f97c36fca3ae6254e0361 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp @@ -183,12 +183,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK1-SAME: (i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 @@ -230,7 +230,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -290,40 +290,40 @@ int main() { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[TMP12:%.*]] = load double*, double** [[_TMP7]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP13:%.*]] = load volatile double, double* [[TMP12]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP12:%.*]] = load double*, double** [[_TMP7]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = load volatile double, double* [[TMP12]], align 8 // CHECK1-NEXT: [[CONV11:%.*]] = bitcast i64* [[G1_CASTED]] to double* -// CHECK1-NEXT: store double [[TMP13]], double* [[CONV11]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[SVAR8]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: store double [[TMP13]], double* [[CONV11]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK1-NEXT: [[CONV12:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK1-NEXT: store i32 [[TMP15]], i32* [[CONV12]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[SFVAR9]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: store i32 [[TMP15]], i32* [[CONV12]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[SFVAR9]], align 4 // CHECK1-NEXT: [[CONV13:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float* -// CHECK1-NEXT: store float [[TMP17]], float* [[CONV13]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP19:%.*]] = load double, double* [[G5]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: store float [[TMP17]], float* [[CONV13]], align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = load double, double* [[G5]], align 8 // CHECK1-NEXT: [[CONV14:%.*]] = bitcast i64* [[G_CASTED]] to double* -// CHECK1-NEXT: store double [[TMP19]], double* [[CONV14]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]), !llvm.access.group !4 +// CHECK1-NEXT: store double [[TMP19]], double* [[CONV14]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -354,7 +354,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -421,37 +421,37 @@ int main() { // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP11:%.*]] = load double*, double** [[_TMP9]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP11]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store i32 3, i32* [[SVAR10]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR11]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load double*, double** [[_TMP9]], align 8 +// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP11]], align 8 +// CHECK1-NEXT: store i32 3, i32* [[SVAR10]], align 4 +// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR11]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK1-NEXT: store double* [[G7]], double** [[TMP12]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: store double* [[G7]], double** [[TMP12]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP9]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store double* [[TMP14]], double** [[TMP13]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP9]], align 8 +// CHECK1-NEXT: store double* [[TMP14]], double** [[TMP13]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK1-NEXT: store i32* [[SVAR10]], i32** [[TMP15]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: store i32* [[SVAR10]], i32** [[TMP15]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK1-NEXT: store float* [[SFVAR11]], float** [[TMP16]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK1-NEXT: store float* [[SFVAR11]], float** [[TMP16]], align 8 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -502,12 +502,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK2-SAME: (i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 @@ -549,7 +549,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -609,40 +609,40 @@ int main() { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK2-NEXT: [[TMP12:%.*]] = load double*, double** [[_TMP7]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP13:%.*]] = load volatile double, double* [[TMP12]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP12:%.*]] = load double*, double** [[_TMP7]], align 8 +// CHECK2-NEXT: [[TMP13:%.*]] = load volatile double, double* [[TMP12]], align 8 // CHECK2-NEXT: [[CONV11:%.*]] = bitcast i64* [[G1_CASTED]] to double* -// CHECK2-NEXT: store double [[TMP13]], double* [[CONV11]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[SVAR8]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: store double [[TMP13]], double* [[CONV11]], align 8 +// CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK2-NEXT: [[CONV12:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK2-NEXT: store i32 [[TMP15]], i32* [[CONV12]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[SFVAR9]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: store i32 [[TMP15]], i32* [[CONV12]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[SFVAR9]], align 4 // CHECK2-NEXT: [[CONV13:%.*]] = bitcast i64* [[SFVAR_CASTED]] to float* -// CHECK2-NEXT: store float [[TMP17]], float* [[CONV13]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP19:%.*]] = load double, double* [[G5]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: store float [[TMP17]], float* [[CONV13]], align 4 +// CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[SFVAR_CASTED]], align 8 +// CHECK2-NEXT: [[TMP19:%.*]] = load double, double* [[G5]], align 8 // CHECK2-NEXT: [[CONV14:%.*]] = bitcast i64* [[G_CASTED]] to double* -// CHECK2-NEXT: store double [[TMP19]], double* [[CONV14]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]), !llvm.access.group !4 +// CHECK2-NEXT: store double [[TMP19]], double* [[CONV14]], align 8 +// CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -673,7 +673,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]], i64 [[G:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -740,37 +740,37 @@ int main() { // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK2-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP11:%.*]] = load double*, double** [[_TMP9]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP11]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store i32 3, i32* [[SVAR10]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR11]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load double*, double** [[_TMP9]], align 8 +// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP11]], align 8 +// CHECK2-NEXT: store i32 3, i32* [[SVAR10]], align 4 +// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR11]], align 4 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK2-NEXT: store double* [[G7]], double** [[TMP12]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: store double* [[G7]], double** [[TMP12]], align 8 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP9]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store double* [[TMP14]], double** [[TMP13]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP9]], align 8 +// CHECK2-NEXT: store double* [[TMP14]], double** [[TMP13]], align 8 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK2-NEXT: store i32* [[SVAR10]], i32** [[TMP15]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: store i32* [[SVAR10]], i32** [[TMP15]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK2-NEXT: store float* [[SFVAR11]], float** [[TMP16]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK2-NEXT: store float* [[SFVAR11]], float** [[TMP16]], align 8 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -821,12 +821,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 @@ -856,7 +856,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -913,29 +913,29 @@ int main() { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP12:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[SVAR5]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store i32 [[TMP13]], i32* [[SVAR_CASTED]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP15:%.*]] = load float, float* [[SFVAR6]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[SVAR5]], align 4 +// CHECK3-NEXT: store i32 [[TMP13]], i32* [[SVAR_CASTED]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load float, float* [[SFVAR6]], align 4 // CHECK3-NEXT: [[CONV8:%.*]] = bitcast i32* [[SFVAR_CASTED]] to float* -// CHECK3-NEXT: store float [[TMP15]], float* [[CONV8]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[SFVAR_CASTED]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, i32, i32, double*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP10]], i32 [[TMP11]], double* [[TMP12]], i32 [[TMP14]], i32 [[TMP16]], double* [[G2]]), !llvm.access.group !5 +// CHECK3-NEXT: store float [[TMP15]], float* [[CONV8]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[SFVAR_CASTED]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, i32, i32, double*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP10]], i32 [[TMP11]], double* [[TMP12]], i32 [[TMP14]], i32 [[TMP16]], double* [[G2]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -966,7 +966,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1030,37 +1030,37 @@ int main() { // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 4 +// CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4 +// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK3-NEXT: store double* [[G2]], double** [[TMP14]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store double* [[G2]], double** [[TMP14]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store double* [[TMP16]], double** [[TMP15]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK3-NEXT: store double* [[TMP16]], double** [[TMP15]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !9 +// CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1111,12 +1111,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 @@ -1146,7 +1146,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1203,29 +1203,29 @@ int main() { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP12:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[SVAR5]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store i32 [[TMP13]], i32* [[SVAR_CASTED]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP15:%.*]] = load float, float* [[SFVAR6]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[SVAR5]], align 4 +// CHECK4-NEXT: store i32 [[TMP13]], i32* [[SVAR_CASTED]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load float, float* [[SFVAR6]], align 4 // CHECK4-NEXT: [[CONV8:%.*]] = bitcast i32* [[SFVAR_CASTED]] to float* -// CHECK4-NEXT: store float [[TMP15]], float* [[CONV8]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[SFVAR_CASTED]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, i32, i32, double*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP10]], i32 [[TMP11]], double* [[TMP12]], i32 [[TMP14]], i32 [[TMP16]], double* [[G2]]), !llvm.access.group !5 +// CHECK4-NEXT: store float [[TMP15]], float* [[CONV8]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[SFVAR_CASTED]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, i32, i32, double*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP10]], i32 [[TMP11]], double* [[TMP12]], i32 [[TMP14]], i32 [[TMP16]], double* [[G2]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1256,7 +1256,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1320,37 +1320,37 @@ int main() { // CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 4 +// CHECK4-NEXT: store i32 3, i32* [[SVAR5]], align 4 +// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK4-NEXT: store double* [[G2]], double** [[TMP14]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store double* [[G2]], double** [[TMP14]], align 4 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store double* [[TMP16]], double** [[TMP15]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK4-NEXT: store double* [[TMP16]], double** [[TMP15]], align 4 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !9 +// CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1408,14 +1408,14 @@ int main() { // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK5-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK5-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK5-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1478,7 +1478,7 @@ int main() { // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK5-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1486,27 +1486,27 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done3: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP37]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1514,12 +1514,12 @@ int main() { // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK5-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -1554,7 +1554,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1601,13 +1601,13 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK5-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -1627,34 +1627,34 @@ int main() { // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK5: omp.inner.for.cond.cleanup: // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !5 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK5-NEXT: [[CONV10:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK5-NEXT: store i32 [[TMP15]], i32* [[CONV10]], align 4, !llvm.access.group !5 -// CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK5-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8, !llvm.access.group !5 -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[SVAR8]], align 4, !llvm.access.group !5 +// CHECK5-NEXT: store i32 [[TMP15]], i32* [[CONV10]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK5-NEXT: [[CONV11:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK5-NEXT: store i32 [[TMP18]], i32* [[CONV11]], align 4, !llvm.access.group !5 -// CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP12]], i64 [[TMP14]], [2 x i32]* [[VEC4]], i64 [[TMP16]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP17]], i64 [[TMP19]]), !llvm.access.group !5 +// CHECK5-NEXT: store i32 [[TMP18]], i32* [[CONV11]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP12]], i64 [[TMP14]], [2 x i32]* [[VEC4]], i64 [[TMP16]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP17]], i64 [[TMP19]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -1701,14 +1701,14 @@ int main() { // CHECK5-NEXT: store i32 [[TMP38]], i32* [[CONV1]], align 8 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done15: @@ -1716,7 +1716,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1771,13 +1771,13 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR8]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) // CHECK5-NEXT: store %struct.S* [[VAR8]], %struct.S** [[_TMP9]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -1797,37 +1797,37 @@ int main() { // CHECK5-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK5-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK5: omp.inner.for.cond.cleanup: // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR5]], align 4, !llvm.access.group !9 -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR5]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC6]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK5-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8, !llvm.access.group !9 -// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK5-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP17]] to i64 // CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i64 0, i64 [[IDXPROM12]] // CHECK5-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX13]] to i8* // CHECK5-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !9 +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -1874,14 +1874,14 @@ int main() { // CHECK5-NEXT: store i32 [[TMP37]], i32* [[CONV1]], align 8 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR8]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN17]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done18: @@ -1889,12 +1889,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: ret void // // @@ -1913,14 +1913,14 @@ int main() { // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1978,17 +1978,17 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP30]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1999,7 +1999,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2013,7 +2013,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2022,17 +2022,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2040,12 +2040,12 @@ int main() { // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50 -// CHECK5-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -2072,7 +2072,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2114,13 +2114,13 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -2140,30 +2140,30 @@ int main() { // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK5: omp.inner.for.cond.cleanup: // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !14 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK5-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK5-NEXT: store i32 [[TMP15]], i32* [[CONV8]], align 4, !llvm.access.group !14 -// CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14 -// CHECK5-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !14 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP12]], i64 [[TMP14]], [2 x i32]* [[VEC3]], i64 [[TMP16]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP17]]), !llvm.access.group !14 +// CHECK5-NEXT: store i32 [[TMP15]], i32* [[CONV8]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP12]], i64 [[TMP14]], [2 x i32]* [[VEC3]], i64 [[TMP16]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP17]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2208,14 +2208,14 @@ int main() { // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done12: @@ -2223,7 +2223,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2274,13 +2274,13 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: // CHECK5-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR7]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK5-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -2300,37 +2300,37 @@ int main() { // CHECK5-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK5: omp.inner.for.cond.cleanup: // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR4]], align 4, !llvm.access.group !17 -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR4]], align 4 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]] -// CHECK5-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK5-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !17 -// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK5-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK5-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP17]] to i64 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i64 0, i64 [[IDXPROM10]] // CHECK5-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* // CHECK5-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !17 +// CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2375,14 +2375,14 @@ int main() { // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0 // CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN15]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done16: @@ -2390,17 +2390,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2411,7 +2411,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2425,7 +2425,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2461,14 +2461,14 @@ int main() { // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK6-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK6-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK6-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -2531,7 +2531,7 @@ int main() { // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK6: omp_offload.cont: -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK6-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -2539,27 +2539,27 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done3: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK6-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP37]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2567,12 +2567,12 @@ int main() { // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK6-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -2607,7 +2607,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2654,13 +2654,13 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: // CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK6-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -2680,34 +2680,34 @@ int main() { // CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK6: omp.inner.for.cond.cleanup: // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !5 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 // CHECK6-NEXT: [[CONV10:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK6-NEXT: store i32 [[TMP15]], i32* [[CONV10]], align 4, !llvm.access.group !5 -// CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK6-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8, !llvm.access.group !5 -// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[SVAR8]], align 4, !llvm.access.group !5 +// CHECK6-NEXT: store i32 [[TMP15]], i32* [[CONV10]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[SVAR8]], align 4 // CHECK6-NEXT: [[CONV11:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* -// CHECK6-NEXT: store i32 [[TMP18]], i32* [[CONV11]], align 4, !llvm.access.group !5 -// CHECK6-NEXT: [[TMP19:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP12]], i64 [[TMP14]], [2 x i32]* [[VEC4]], i64 [[TMP16]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP17]], i64 [[TMP19]]), !llvm.access.group !5 +// CHECK6-NEXT: store i32 [[TMP18]], i32* [[CONV11]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP12]], i64 [[TMP14]], [2 x i32]* [[VEC4]], i64 [[TMP16]], [2 x %struct.S]* [[S_ARR5]], %struct.S* [[TMP17]], i64 [[TMP19]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -2754,14 +2754,14 @@ int main() { // CHECK6-NEXT: store i32 [[TMP38]], i32* [[CONV1]], align 8 // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6: .omp.lastprivate.done: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK6-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP39]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done15: @@ -2769,7 +2769,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2824,13 +2824,13 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: // CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR8]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) // CHECK6-NEXT: store %struct.S* [[VAR8]], %struct.S** [[_TMP9]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -2850,37 +2850,37 @@ int main() { // CHECK6-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK6-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK6: omp.inner.for.cond.cleanup: // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR5]], align 4, !llvm.access.group !9 -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR5]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC6]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK6-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8, !llvm.access.group !9 -// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP9]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK6-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP17]] to i64 // CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i64 0, i64 [[IDXPROM12]] // CHECK6-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX13]] to i8* // CHECK6-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !9 +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -2927,14 +2927,14 @@ int main() { // CHECK6-NEXT: store i32 [[TMP37]], i32* [[CONV1]], align 8 // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6: .omp.lastprivate.done: -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR8]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR8]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR7]], i32 0, i32 0 // CHECK6-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN17]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN17]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done18: @@ -2942,12 +2942,12 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK6-NEXT: ret void // // @@ -2966,14 +2966,14 @@ int main() { // CHECK6-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK6-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -3031,17 +3031,17 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done2: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP30]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3052,7 +3052,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3066,7 +3066,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3075,17 +3075,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3093,12 +3093,12 @@ int main() { // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50 -// CHECK6-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK6-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -3125,7 +3125,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3167,13 +3167,13 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: // CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK6-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -3193,30 +3193,30 @@ int main() { // CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK6: omp.inner.for.cond.cleanup: // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !14 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK6-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK6-NEXT: store i32 [[TMP15]], i32* [[CONV8]], align 4, !llvm.access.group !14 -// CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14 -// CHECK6-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !14 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP12]], i64 [[TMP14]], [2 x i32]* [[VEC3]], i64 [[TMP16]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP17]]), !llvm.access.group !14 +// CHECK6-NEXT: store i32 [[TMP15]], i32* [[CONV8]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP12]], i64 [[TMP14]], [2 x i32]* [[VEC3]], i64 [[TMP16]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP17]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -3261,14 +3261,14 @@ int main() { // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6: .omp.lastprivate.done: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done12: @@ -3276,7 +3276,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3327,13 +3327,13 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: // CHECK6-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR7]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) // CHECK6-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 // CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -3353,37 +3353,37 @@ int main() { // CHECK6-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK6: omp.inner.for.cond.cleanup: // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR4]], align 4, !llvm.access.group !17 -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR4]], align 4 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC5]], i64 0, i64 [[IDXPROM]] -// CHECK6-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK6-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8, !llvm.access.group !17 -// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK6-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK6-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 +// CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP17]] to i64 // CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i64 0, i64 [[IDXPROM10]] // CHECK6-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* // CHECK6-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !17 +// CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -3428,14 +3428,14 @@ int main() { // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) // CHECK6-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK6: .omp.lastprivate.done: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR6]], i32 0, i32 0 // CHECK6-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN15]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done16: @@ -3443,17 +3443,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3464,7 +3464,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3478,7 +3478,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3514,14 +3514,14 @@ int main() { // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK7-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK7-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK7-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -3582,7 +3582,7 @@ int main() { // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK7-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -3590,27 +3590,27 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done2: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK7-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP37]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3618,12 +3618,12 @@ int main() { // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK7-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -3654,7 +3654,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3699,13 +3699,13 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -3725,30 +3725,30 @@ int main() { // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK7: omp.inner.for.cond.cleanup: // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: store i32 [[TMP13]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: [[TMP15:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[SVAR7]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: store i32 [[TMP16]], i32* [[SVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP11]], i32 [[TMP12]], [2 x i32]* [[VEC3]], i32 [[TMP14]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32 [[TMP17]]), !llvm.access.group !6 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK7-NEXT: store i32 [[TMP16]], i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP11]], i32 [[TMP12]], [2 x i32]* [[VEC3]], i32 [[TMP14]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32 [[TMP17]]) // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK7: omp.loop.exit: @@ -3795,14 +3795,14 @@ int main() { // CHECK7-NEXT: store i32 [[TMP36]], i32* [[SVAR_ADDR]], align 4 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done12: @@ -3810,7 +3810,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3861,13 +3861,13 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: // CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -3887,35 +3887,35 @@ int main() { // CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK7: omp.inner.for.cond.cleanup: // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !10 -// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]] -// CHECK7-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK7-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4, !llvm.access.group !10 -// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP17]] // CHECK7-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK7-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !10 +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK7-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK7-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK7: omp.loop.exit: @@ -3962,14 +3962,14 @@ int main() { // CHECK7-NEXT: store i32 [[TMP37]], i32* [[SVAR_ADDR]], align 4 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done14: @@ -3977,12 +3977,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK7-NEXT: ret void // // @@ -4001,14 +4001,14 @@ int main() { // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4065,17 +4065,17 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done2: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP30]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4086,7 +4086,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4100,7 +4100,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4109,17 +4109,17 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4127,12 +4127,12 @@ int main() { // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50 -// CHECK7-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -4157,7 +4157,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4198,13 +4198,13 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -4224,27 +4224,27 @@ int main() { // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK7: omp.inner.for.cond.cleanup: // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !15 -// CHECK7-NEXT: store i32 [[TMP13]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK7-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !15 -// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP11]], i32 [[TMP12]], [2 x i32]* [[VEC3]], i32 [[TMP14]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP15]]), !llvm.access.group !15 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: store i32 [[TMP13]], i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP11]], i32 [[TMP12]], [2 x i32]* [[VEC3]], i32 [[TMP14]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP15]]) // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK7: omp.loop.exit: @@ -4289,14 +4289,14 @@ int main() { // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done11: @@ -4304,7 +4304,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4352,13 +4352,13 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: // CHECK7-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -4378,35 +4378,35 @@ int main() { // CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK7: omp.inner.for.cond.cleanup: // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !18 -// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]] -// CHECK7-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK7-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !18 -// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK7-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP17]] // CHECK7-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* // CHECK7-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !18 +// CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK7: omp.loop.exit: @@ -4451,14 +4451,14 @@ int main() { // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i32 4, i1 false) // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done13: @@ -4466,17 +4466,17 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4487,7 +4487,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4501,7 +4501,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4537,14 +4537,14 @@ int main() { // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK8-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK8-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK8-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -4605,7 +4605,7 @@ int main() { // CHECK8-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK8: omp_offload.cont: -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK8-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -4613,27 +4613,27 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP37]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4641,12 +4641,12 @@ int main() { // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK8-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK8-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -4677,7 +4677,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4722,13 +4722,13 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: // CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK8-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -4748,30 +4748,30 @@ int main() { // CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK8: omp.inner.for.cond.cleanup: // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: store i32 [[TMP13]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: [[TMP15:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[SVAR7]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: store i32 [[TMP16]], i32* [[SVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP11]], i32 [[TMP12]], [2 x i32]* [[VEC3]], i32 [[TMP14]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32 [[TMP17]]), !llvm.access.group !6 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[SVAR7]], align 4 +// CHECK8-NEXT: store i32 [[TMP16]], i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP11]], i32 [[TMP12]], [2 x i32]* [[VEC3]], i32 [[TMP14]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32 [[TMP17]]) // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK8: omp.loop.exit: @@ -4818,14 +4818,14 @@ int main() { // CHECK8-NEXT: store i32 [[TMP36]], i32* [[SVAR_ADDR]], align 4 // CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK8: .omp.lastprivate.done: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done12: @@ -4833,7 +4833,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4884,13 +4884,13 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: // CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK8-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -4910,35 +4910,35 @@ int main() { // CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK8: omp.inner.for.cond.cleanup: // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !10 -// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]] -// CHECK8-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK8-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4, !llvm.access.group !10 -// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK8-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP17]] // CHECK8-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK8-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !10 +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK8-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK8-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK8: omp.loop.exit: @@ -4985,14 +4985,14 @@ int main() { // CHECK8-NEXT: store i32 [[TMP37]], i32* [[SVAR_ADDR]], align 4 // CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK8: .omp.lastprivate.done: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done14: @@ -5000,12 +5000,12 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // @@ -5024,14 +5024,14 @@ int main() { // CHECK8-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK8-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -5088,17 +5088,17 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP30]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5109,7 +5109,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5123,7 +5123,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5132,17 +5132,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5150,12 +5150,12 @@ int main() { // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50 -// CHECK8-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK8-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -5180,7 +5180,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5221,13 +5221,13 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: // CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -5247,27 +5247,27 @@ int main() { // CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] // CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK8: omp.inner.for.cond.cleanup: // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !15 -// CHECK8-NEXT: store i32 [[TMP13]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK8-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !15 -// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP11]], i32 [[TMP12]], [2 x i32]* [[VEC3]], i32 [[TMP14]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP15]]), !llvm.access.group !15 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: store i32 [[TMP13]], i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP11]], i32 [[TMP12]], [2 x i32]* [[VEC3]], i32 [[TMP14]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP15]]) // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK8: omp.loop.exit: @@ -5312,14 +5312,14 @@ int main() { // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) // CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK8: .omp.lastprivate.done: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done11: @@ -5327,7 +5327,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5375,13 +5375,13 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: // CHECK8-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -5401,35 +5401,35 @@ int main() { // CHECK8-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK8-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK8: omp.inner.for.cond.cleanup: // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !18 -// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]] -// CHECK8-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK8-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !18 -// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK8-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK8-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP17]] // CHECK8-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* // CHECK8-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[TMP16]] to i8* -// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !18 +// CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK8-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK8: omp.loop.exit: @@ -5474,14 +5474,14 @@ int main() { // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i32 4, i1 false) // CHECK8-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK8: .omp.lastprivate.done: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done13: @@ -5489,17 +5489,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5510,7 +5510,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5524,7 +5524,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5553,7 +5553,7 @@ int main() { // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK9-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK9-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // @@ -5571,7 +5571,7 @@ int main() { // CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK10-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK10-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // @@ -5589,7 +5589,7 @@ int main() { // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK11-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK11-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK11-NEXT: ret i32 0 // // @@ -5607,7 +5607,7 @@ int main() { // CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK12-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK12-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK12-NEXT: ret i32 0 // // @@ -5637,14 +5637,14 @@ int main() { // CHECK13-NEXT: [[I14:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -5660,13 +5660,13 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: // CHECK13-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK13-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -5730,18 +5730,18 @@ int main() { // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) // CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK13-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done13: -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 @@ -5749,27 +5749,27 @@ int main() { // CHECK13: arraydestroy.body16: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST17]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK13: arraydestroy.done20: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP30]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5777,17 +5777,17 @@ int main() { // CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // @@ -5811,14 +5811,14 @@ int main() { // CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -5834,13 +5834,13 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: // CHECK13-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK13-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -5902,14 +5902,14 @@ int main() { // CHECK13-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK13-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done13: @@ -5920,17 +5920,17 @@ int main() { // CHECK13: arraydestroy.body15: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK13: arraydestroy.done19: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP29]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5941,7 +5941,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5950,7 +5950,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5964,17 +5964,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5982,22 +5982,22 @@ int main() { // CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -6008,7 +6008,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6022,7 +6022,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -6056,14 +6056,14 @@ int main() { // CHECK14-NEXT: [[I14:%.*]] = alloca i32, align 4 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -6079,13 +6079,13 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: // CHECK14-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK14-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -6149,18 +6149,18 @@ int main() { // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) // CHECK14-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK14-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK14-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK14-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done13: -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 @@ -6168,27 +6168,27 @@ int main() { // CHECK14: arraydestroy.body16: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST17]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK14: arraydestroy.done20: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP30]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6196,17 +6196,17 @@ int main() { // CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // @@ -6230,14 +6230,14 @@ int main() { // CHECK14-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK14-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK14-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -6253,13 +6253,13 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: // CHECK14-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK14-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -6321,14 +6321,14 @@ int main() { // CHECK14-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK14-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK14-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done13: @@ -6339,17 +6339,17 @@ int main() { // CHECK14: arraydestroy.body15: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK14: arraydestroy.done19: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP29]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6360,7 +6360,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6369,7 +6369,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6383,17 +6383,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6401,22 +6401,22 @@ int main() { // CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -6427,7 +6427,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6441,7 +6441,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -6475,14 +6475,14 @@ int main() { // CHECK15-NEXT: [[I13:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -6498,13 +6498,13 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: // CHECK15-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK15-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -6566,18 +6566,18 @@ int main() { // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) // CHECK15-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK15-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done12: -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i32 2 @@ -6585,27 +6585,27 @@ int main() { // CHECK15: arraydestroy.body15: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST16]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK15: arraydestroy.done19: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP30]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6613,17 +6613,17 @@ int main() { // CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // @@ -6647,14 +6647,14 @@ int main() { // CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -6670,13 +6670,13 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: // CHECK15-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -6736,14 +6736,14 @@ int main() { // CHECK15-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK15-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done12: @@ -6754,17 +6754,17 @@ int main() { // CHECK15: arraydestroy.body14: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST15:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT16:%.*]], [[ARRAYDESTROY_BODY14]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT16]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST15]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE17:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT16]], [[ARRAY_BEGIN13]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE17]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY14]] // CHECK15: arraydestroy.done18: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP29]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -6775,7 +6775,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -6784,7 +6784,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6798,17 +6798,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6816,22 +6816,22 @@ int main() { // CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -6842,7 +6842,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6856,7 +6856,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -6890,14 +6890,14 @@ int main() { // CHECK16-NEXT: [[I13:%.*]] = alloca i32, align 4 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -6913,13 +6913,13 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: // CHECK16-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK16-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -6981,18 +6981,18 @@ int main() { // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) // CHECK16-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK16-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK16-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK16-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done12: -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i32 2 @@ -7000,27 +7000,27 @@ int main() { // CHECK16: arraydestroy.body15: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST16]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK16: arraydestroy.done19: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP30]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -7028,17 +7028,17 @@ int main() { // CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // @@ -7062,14 +7062,14 @@ int main() { // CHECK16-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK16-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK16-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -7085,13 +7085,13 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: // CHECK16-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -7151,14 +7151,14 @@ int main() { // CHECK16-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK16-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK16-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done12: @@ -7169,17 +7169,17 @@ int main() { // CHECK16: arraydestroy.body14: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST15:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT16:%.*]], [[ARRAYDESTROY_BODY14]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT16]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST15]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE17:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT16]], [[ARRAY_BEGIN13]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE17]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY14]] // CHECK16: arraydestroy.done18: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP29]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -7190,7 +7190,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -7199,7 +7199,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -7213,17 +7213,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7231,22 +7231,22 @@ int main() { // CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -7257,7 +7257,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7271,7 +7271,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp index d9e331739c47642fa481da1a26242e6148b4cf8e..2f7978381a4a6edc0b28cb1f5895b14d694ea15a 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp @@ -183,33 +183,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -222,7 +222,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -233,14 +233,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -248,12 +248,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -261,7 +261,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -269,7 +269,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -288,7 +288,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -307,7 +307,7 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -319,7 +319,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -346,12 +346,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -370,25 +370,25 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !5 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -402,14 +402,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -417,7 +417,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -454,12 +454,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -478,40 +478,40 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false), !llvm.access.group !9 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK1-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -525,14 +525,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -550,14 +550,14 @@ int main() { // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -575,27 +575,27 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP4]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -603,7 +603,7 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // @@ -615,7 +615,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -644,12 +644,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -669,25 +669,25 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !14 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -701,14 +701,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done5: @@ -716,7 +716,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -755,12 +755,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -780,37 +780,37 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* // CHECK1-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !17 +// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -824,14 +824,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done9: @@ -839,17 +839,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -861,7 +861,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -877,7 +877,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -904,33 +904,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -943,7 +943,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -954,14 +954,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -969,12 +969,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -982,7 +982,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -990,7 +990,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1009,7 +1009,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -1028,7 +1028,7 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -1040,7 +1040,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1067,12 +1067,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1091,25 +1091,25 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !5 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1123,14 +1123,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done3: @@ -1138,7 +1138,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1175,12 +1175,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1199,40 +1199,40 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false), !llvm.access.group !9 -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK2-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1246,14 +1246,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done8: @@ -1271,14 +1271,14 @@ int main() { // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -1296,27 +1296,27 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP4]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1324,7 +1324,7 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // @@ -1336,7 +1336,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1365,12 +1365,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1390,25 +1390,25 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !14 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1422,14 +1422,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done5: @@ -1437,7 +1437,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1476,12 +1476,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -1501,37 +1501,37 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* // CHECK2-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !17 +// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1545,14 +1545,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done9: @@ -1560,17 +1560,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1582,7 +1582,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1598,7 +1598,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1625,33 +1625,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1664,7 +1664,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1675,14 +1675,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1690,12 +1690,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1703,7 +1703,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1711,7 +1711,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1730,7 +1730,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -1749,7 +1749,7 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -1761,7 +1761,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1788,12 +1788,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1812,23 +1812,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !6 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1842,14 +1842,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done3: @@ -1857,7 +1857,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1892,12 +1892,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1916,38 +1916,38 @@ int main() { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]] // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* // CHECK3-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false), !llvm.access.group !10 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1961,14 +1961,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -1986,14 +1986,14 @@ int main() { // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -2011,27 +2011,27 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP4]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2039,7 +2039,7 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // @@ -2051,7 +2051,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2080,12 +2080,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2105,23 +2105,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !15 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2135,14 +2135,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done5: @@ -2150,7 +2150,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2187,12 +2187,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2212,35 +2212,35 @@ int main() { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK3-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* // CHECK3-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !18 +// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2254,14 +2254,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -2269,17 +2269,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2291,7 +2291,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2307,7 +2307,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2334,33 +2334,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2373,7 +2373,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2384,14 +2384,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2399,12 +2399,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -2412,7 +2412,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -2420,7 +2420,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2439,7 +2439,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -2458,7 +2458,7 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // @@ -2470,7 +2470,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2497,12 +2497,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2521,23 +2521,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !6 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2551,14 +2551,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done3: @@ -2566,7 +2566,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2601,12 +2601,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2625,38 +2625,38 @@ int main() { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK4-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]] // CHECK4-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* // CHECK4-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false), !llvm.access.group !10 -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2670,14 +2670,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done6: @@ -2695,14 +2695,14 @@ int main() { // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -2720,27 +2720,27 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP4]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2748,7 +2748,7 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // @@ -2760,7 +2760,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2789,12 +2789,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2814,23 +2814,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !15 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2844,14 +2844,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done5: @@ -2859,7 +2859,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2896,12 +2896,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2921,35 +2921,35 @@ int main() { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK4-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK4-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* // CHECK4-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !18 +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2963,14 +2963,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done7: @@ -2978,17 +2978,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3000,7 +3000,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3016,7 +3016,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3043,33 +3043,33 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3082,7 +3082,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3093,14 +3093,14 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3108,12 +3108,12 @@ int main() { // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3121,7 +3121,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -3129,7 +3129,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3148,7 +3148,7 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // @@ -3159,7 +3159,7 @@ int main() { // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // @@ -3171,7 +3171,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3213,23 +3213,23 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !4 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3245,7 +3245,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3298,35 +3298,35 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK5-NEXT: store i32 1, i32* [[G]], align 4, !llvm.access.group !8 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8, !llvm.access.group !8 -// CHECK5-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8 -// CHECK5-NEXT: store i32 2, i32* [[SIVAR]], align 4, !llvm.access.group !8 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: store i32 1, i32* [[G]], align 4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK5-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK5-NEXT: store i32 2, i32* [[SIVAR]], align 4 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[G]], i32** [[TMP11]], align 8, !llvm.access.group !8 +// CHECK5-NEXT: store i32* [[G]], i32** [[TMP11]], align 8 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8, !llvm.access.group !8 -// CHECK5-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK5-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK5-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8, !llvm.access.group !8 -// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK5-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3360,33 +3360,33 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3399,7 +3399,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3410,14 +3410,14 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3425,12 +3425,12 @@ int main() { // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3438,7 +3438,7 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: @@ -3446,7 +3446,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3465,7 +3465,7 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // @@ -3476,7 +3476,7 @@ int main() { // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // @@ -3488,7 +3488,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3530,23 +3530,23 @@ int main() { // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !4 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -3562,7 +3562,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3615,35 +3615,35 @@ int main() { // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK6-NEXT: store i32 1, i32* [[G]], align 4, !llvm.access.group !8 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8, !llvm.access.group !8 -// CHECK6-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8 -// CHECK6-NEXT: store i32 2, i32* [[SIVAR]], align 4, !llvm.access.group !8 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: store i32 1, i32* [[G]], align 4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK6-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK6-NEXT: store i32 2, i32* [[SIVAR]], align 4 // CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[G]], i32** [[TMP11]], align 8, !llvm.access.group !8 +// CHECK6-NEXT: store i32* [[G]], i32** [[TMP11]], align 8 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8, !llvm.access.group !8 -// CHECK6-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK6-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK6-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8, !llvm.access.group !8 -// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK6-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -3677,42 +3677,42 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3720,12 +3720,12 @@ int main() { // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3733,7 +3733,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -3743,7 +3743,7 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // @@ -3772,12 +3772,12 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 @@ -3816,18 +3816,18 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done6: -// CHECK7-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK7-NEXT: ret i32 [[CALL]] // // @@ -3851,14 +3851,14 @@ int main() { // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3870,12 +3870,12 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: @@ -3912,14 +3912,14 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done11: @@ -3930,17 +3930,17 @@ int main() { // CHECK7: arraydestroy.body13: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK7: arraydestroy.done17: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP14]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3953,7 +3953,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3962,7 +3962,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3979,17 +3979,17 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3997,22 +3997,22 @@ int main() { // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4024,7 +4024,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4040,7 +4040,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4060,42 +4060,42 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4103,12 +4103,12 @@ int main() { // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4116,7 +4116,7 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done1: @@ -4126,7 +4126,7 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // @@ -4155,12 +4155,12 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 @@ -4199,18 +4199,18 @@ int main() { // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done6: -// CHECK8-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK8-NEXT: ret i32 [[CALL]] // // @@ -4234,14 +4234,14 @@ int main() { // CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK8-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -4253,12 +4253,12 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: @@ -4295,14 +4295,14 @@ int main() { // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done11: @@ -4313,17 +4313,17 @@ int main() { // CHECK8: arraydestroy.body13: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK8: arraydestroy.done17: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP14]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4336,7 +4336,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4345,7 +4345,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4362,17 +4362,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4380,22 +4380,22 @@ int main() { // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4407,7 +4407,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4423,7 +4423,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4443,42 +4443,42 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4486,12 +4486,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -4499,7 +4499,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -4509,7 +4509,7 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // @@ -4538,12 +4538,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 @@ -4580,18 +4580,18 @@ int main() { // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done5: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK9-NEXT: ret i32 [[CALL]] // // @@ -4615,14 +4615,14 @@ int main() { // CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK9-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -4634,12 +4634,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: @@ -4674,14 +4674,14 @@ int main() { // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done10: @@ -4692,17 +4692,17 @@ int main() { // CHECK9: arraydestroy.body12: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK9: arraydestroy.done16: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP14]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4715,7 +4715,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4724,7 +4724,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4741,17 +4741,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4759,22 +4759,22 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4786,7 +4786,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4802,7 +4802,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4822,42 +4822,42 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4865,12 +4865,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -4878,7 +4878,7 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: @@ -4888,7 +4888,7 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // @@ -4917,12 +4917,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 @@ -4959,18 +4959,18 @@ int main() { // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done5: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK10-NEXT: ret i32 [[CALL]] // // @@ -4994,14 +4994,14 @@ int main() { // CHECK10-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK10-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK10-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -5013,12 +5013,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK10-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: @@ -5053,14 +5053,14 @@ int main() { // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done10: @@ -5071,17 +5071,17 @@ int main() { // CHECK10: arraydestroy.body12: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK10: arraydestroy.done16: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP14]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5094,7 +5094,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5103,7 +5103,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5120,17 +5120,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5138,22 +5138,22 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5165,7 +5165,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5181,7 +5181,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5201,42 +5201,42 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5244,12 +5244,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -5257,7 +5257,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -5267,7 +5267,7 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // @@ -5278,12 +5278,12 @@ int main() { // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: ret i32 0 // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5296,7 +5296,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5305,7 +5305,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5333,42 +5333,42 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5376,12 +5376,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -5389,7 +5389,7 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done1: @@ -5399,7 +5399,7 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // @@ -5410,12 +5410,12 @@ int main() { // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK12-NEXT: ret i32 0 // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5428,7 +5428,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5437,7 +5437,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5470,7 +5470,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5497,12 +5497,12 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -5521,25 +5521,25 @@ int main() { // CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13: omp.inner.for.cond.cleanup: // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !6 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -5553,14 +5553,14 @@ int main() { // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK13-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done3: @@ -5568,17 +5568,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5615,12 +5615,12 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -5639,40 +5639,40 @@ int main() { // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13: omp.inner.for.cond.cleanup: // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !10 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 // CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 // CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] // CHECK13-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* // CHECK13-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false), !llvm.access.group !10 -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK13-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK13-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -5686,14 +5686,14 @@ int main() { // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done8: @@ -5701,12 +5701,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // @@ -5718,7 +5718,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5747,12 +5747,12 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -5772,25 +5772,25 @@ int main() { // CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13: omp.inner.for.cond.cleanup: // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -5804,14 +5804,14 @@ int main() { // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done5: @@ -5819,17 +5819,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5868,12 +5868,12 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK13-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK13-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -5893,37 +5893,37 @@ int main() { // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK13-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK13: omp.inner.for.cond.cleanup: // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !18 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK13-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8, !llvm.access.group !18 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK13-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 // CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK13-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* // CHECK13-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !18 +// CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK13-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -5937,14 +5937,14 @@ int main() { // CHECK13-NEXT: store i32 2, i32* [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done9: @@ -5952,17 +5952,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5975,7 +5975,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5984,7 +5984,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5996,7 +5996,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -6012,7 +6012,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6039,12 +6039,12 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -6063,25 +6063,25 @@ int main() { // CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK14-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14: omp.inner.for.cond.cleanup: // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !6 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -6095,14 +6095,14 @@ int main() { // CHECK14-NEXT: store i32 2, i32* [[I]], align 4 // CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK14: .omp.final.done: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK14-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done3: @@ -6110,17 +6110,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6157,12 +6157,12 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK14-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -6181,40 +6181,40 @@ int main() { // CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK14-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14: omp.inner.for.cond.cleanup: // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !10 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 // CHECK14-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 // CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] // CHECK14-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* // CHECK14-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false), !llvm.access.group !10 -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK14-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK14-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -6228,14 +6228,14 @@ int main() { // CHECK14-NEXT: store i32 2, i32* [[I]], align 4 // CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK14: .omp.final.done: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done8: @@ -6243,12 +6243,12 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK14-NEXT: ret void // // @@ -6260,7 +6260,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6289,12 +6289,12 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -6314,25 +6314,25 @@ int main() { // CHECK14-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK14-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14: omp.inner.for.cond.cleanup: // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK14-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK14-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK14-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -6346,14 +6346,14 @@ int main() { // CHECK14-NEXT: store i32 2, i32* [[I]], align 4 // CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK14: .omp.final.done: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done5: @@ -6361,17 +6361,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6410,12 +6410,12 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK14-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK14-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -6435,37 +6435,37 @@ int main() { // CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK14-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK14: omp.inner.for.cond.cleanup: // CHECK14-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !18 -// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK14-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK14-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8, !llvm.access.group !18 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK14-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK14-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 // CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK14-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* // CHECK14-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !18 +// CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK14-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK14-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK14: omp.loop.exit: @@ -6479,14 +6479,14 @@ int main() { // CHECK14-NEXT: store i32 2, i32* [[I]], align 4 // CHECK14-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK14: .omp.final.done: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done9: @@ -6494,17 +6494,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6517,7 +6517,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6526,7 +6526,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -6538,7 +6538,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -6554,7 +6554,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6581,12 +6581,12 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -6605,23 +6605,23 @@ int main() { // CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK15: omp.inner.for.cond.cleanup: // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !7 +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !7 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK15: omp.loop.exit: @@ -6635,14 +6635,14 @@ int main() { // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK15-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done3: @@ -6650,17 +6650,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6695,12 +6695,12 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -6719,38 +6719,38 @@ int main() { // CHECK15-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK15: omp.inner.for.cond.cleanup: // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !11 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK15-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK15-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 // CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]] // CHECK15-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* // CHECK15-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false), !llvm.access.group !11 -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !11 +// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK15-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !11 +// CHECK15-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK15-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK15-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK15: omp.loop.exit: @@ -6764,14 +6764,14 @@ int main() { // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done6: @@ -6779,12 +6779,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // @@ -6796,7 +6796,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6825,12 +6825,12 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -6850,23 +6850,23 @@ int main() { // CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 +// CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK15-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK15-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK15: omp.inner.for.cond.cleanup: // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !16 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 -// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !16 +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK15-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !16 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK15: omp.loop.exit: @@ -6880,14 +6880,14 @@ int main() { // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done5: @@ -6895,17 +6895,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6942,12 +6942,12 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK15-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -6967,35 +6967,35 @@ int main() { // CHECK15-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK15-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK15: omp.inner.for.cond.cleanup: // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !19 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK15-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !19 -// CHECK15-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !19 -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK15-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK15-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* // CHECK15-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !19 +// CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK15-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK15-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK15: omp.loop.exit: @@ -7009,14 +7009,14 @@ int main() { // CHECK15-NEXT: store i32 2, i32* [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done7: @@ -7024,17 +7024,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -7047,7 +7047,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -7056,7 +7056,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -7068,7 +7068,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -7084,7 +7084,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7111,12 +7111,12 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]] // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -7135,23 +7135,23 @@ int main() { // CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK16: omp.inner.for.cond.cleanup: // CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !7 +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !7 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK16: omp.loop.exit: @@ -7165,14 +7165,14 @@ int main() { // CHECK16-NEXT: store i32 2, i32* [[I]], align 4 // CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK16: .omp.final.done: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK16-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done3: @@ -7180,17 +7180,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7225,12 +7225,12 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK16-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -7249,38 +7249,38 @@ int main() { // CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK16-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK16: omp.inner.for.cond.cleanup: // CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !11 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK16-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 // CHECK16-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]] // CHECK16-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* // CHECK16-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false), !llvm.access.group !11 -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK16-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK16: omp.body.continue: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK16-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK16-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK16-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK16: omp.loop.exit: @@ -7294,14 +7294,14 @@ int main() { // CHECK16-NEXT: store i32 2, i32* [[I]], align 4 // CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK16: .omp.final.done: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done6: @@ -7309,12 +7309,12 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK16-NEXT: ret void // // @@ -7326,7 +7326,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7355,12 +7355,12 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -7380,23 +7380,23 @@ int main() { // CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK16-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK16-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK16: omp.inner.for.cond.cleanup: // CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !16 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 -// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !16 +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK16-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !16 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK16: omp.loop.exit: @@ -7410,14 +7410,14 @@ int main() { // CHECK16-NEXT: store i32 2, i32* [[I]], align 4 // CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK16: .omp.final.done: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done5: @@ -7425,17 +7425,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7472,12 +7472,12 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK16-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK16-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -7497,35 +7497,35 @@ int main() { // CHECK16-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK16-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK16: omp.inner.for.cond.cleanup: // CHECK16-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 -// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !19 -// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK16-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK16-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !19 -// CHECK16-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !19 -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK16-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK16-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK16-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* // CHECK16-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !19 +// CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK16: omp.body.continue: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK16-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK16-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK16: omp.loop.exit: @@ -7539,14 +7539,14 @@ int main() { // CHECK16-NEXT: store i32 2, i32* [[I]], align 4 // CHECK16-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK16: .omp.final.done: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done7: @@ -7554,17 +7554,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -7577,7 +7577,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -7586,7 +7586,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -7598,7 +7598,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -7614,7 +7614,7 @@ int main() { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7656,23 +7656,23 @@ int main() { // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !5 +// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -7688,7 +7688,7 @@ int main() { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7741,35 +7741,35 @@ int main() { // CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK17-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: store i32 1, i32* [[G]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8, !llvm.access.group !9 -// CHECK17-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: store i32 2, i32* [[SIVAR]], align 4, !llvm.access.group !9 +// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK17-NEXT: store i32 1, i32* [[G]], align 4 +// CHECK17-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK17-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK17-NEXT: store i32 2, i32* [[SIVAR]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 -// CHECK17-NEXT: store i32* [[G]], i32** [[TMP11]], align 8, !llvm.access.group !9 +// CHECK17-NEXT: store i32* [[G]], i32** [[TMP11]], align 8 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8, !llvm.access.group !9 -// CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !9 +// CHECK17-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK17-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 2 -// CHECK17-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8, !llvm.access.group !9 -// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* noundef [[REF_TMP]]) #[[ATTR3:[0-9]+]], !llvm.access.group !9 +// CHECK17-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 +// CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -7787,42 +7787,42 @@ int main() { // CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK18-SAME: () #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK18-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK18-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK18-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK18-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK18-SAME: () #[[ATTR0]] { // CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK18-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -7830,12 +7830,12 @@ int main() { // CHECK18-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK18-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK18-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK18-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -7843,7 +7843,7 @@ int main() { // CHECK18: arraydestroy.body: // CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK18: arraydestroy.done1: @@ -7853,7 +7853,7 @@ int main() { // CHECK18-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK18-SAME: () #[[ATTR0]] { // CHECK18-NEXT: entry: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK18-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK18-NEXT: ret void // @@ -7882,12 +7882,12 @@ int main() { // CHECK18-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK18: arrayctor.loop: // CHECK18-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK18-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK18-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK18-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK18: arrayctor.cont: -// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK18-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK18: omp.inner.for.cond: // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 @@ -7926,18 +7926,18 @@ int main() { // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK18: omp.inner.for.end: // CHECK18-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK18-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 // CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK18: arraydestroy.body: // CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK18-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK18: arraydestroy.done6: -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK18-NEXT: ret i32 [[CALL]] // // @@ -7961,14 +7961,14 @@ int main() { // CHECK18-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK18-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK18-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK18-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK18-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK18-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK18-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK18-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK18-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK18-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -7980,12 +7980,12 @@ int main() { // CHECK18-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK18: arrayctor.loop: // CHECK18-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK18-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK18-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK18-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK18: arrayctor.cont: -// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK18-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK18-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK18: omp.inner.for.cond: @@ -8022,14 +8022,14 @@ int main() { // CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK18: omp.inner.for.end: // CHECK18-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK18-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK18-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK18: arraydestroy.body: // CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK18-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK18: arraydestroy.done11: @@ -8040,17 +8040,17 @@ int main() { // CHECK18: arraydestroy.body13: // CHECK18-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK18-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] +// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] // CHECK18-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK18-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK18: arraydestroy.done17: -// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK18-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK18-NEXT: ret i32 [[TMP14]] // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK18-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -8063,7 +8063,7 @@ int main() { // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK18-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK18-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -8072,7 +8072,7 @@ int main() { // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK18-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -8089,17 +8089,17 @@ int main() { // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK18-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK18-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK18-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -8107,22 +8107,22 @@ int main() { // CHECK18-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK18-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK18-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK18-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK18-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK18-NEXT: ret void // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK18-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -8134,7 +8134,7 @@ int main() { // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK18-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -8150,7 +8150,7 @@ int main() { // // // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK18-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK18-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -8170,42 +8170,42 @@ int main() { // CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK19-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK19-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK19-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK19-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK19-SAME: () #[[ATTR0]] { // CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK19-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -8213,12 +8213,12 @@ int main() { // CHECK19-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK19-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK19-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK19-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK19-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK19-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -8226,7 +8226,7 @@ int main() { // CHECK19: arraydestroy.body: // CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK19-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK19: arraydestroy.done1: @@ -8236,7 +8236,7 @@ int main() { // CHECK19-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK19-SAME: () #[[ATTR0]] { // CHECK19-NEXT: entry: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK19-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK19-NEXT: ret void // @@ -8265,12 +8265,12 @@ int main() { // CHECK19-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK19: arrayctor.loop: // CHECK19-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK19-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK19-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK19-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK19: arrayctor.cont: -// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK19-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK19: omp.inner.for.cond: // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 @@ -8309,18 +8309,18 @@ int main() { // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK19-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 // CHECK19-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK19: arraydestroy.body: // CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK19-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK19-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK19: arraydestroy.done6: -// CHECK19-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK19-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK19-NEXT: ret i32 [[CALL]] // // @@ -8344,14 +8344,14 @@ int main() { // CHECK19-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK19-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK19-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK19-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK19-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK19-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK19-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK19-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK19-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -8363,12 +8363,12 @@ int main() { // CHECK19-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK19: arrayctor.loop: // CHECK19-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK19-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK19-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK19-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK19: arrayctor.cont: -// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK19-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK19-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK19: omp.inner.for.cond: @@ -8405,14 +8405,14 @@ int main() { // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK19-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK19-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK19: arraydestroy.body: // CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK19-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK19: arraydestroy.done11: @@ -8423,17 +8423,17 @@ int main() { // CHECK19: arraydestroy.body13: // CHECK19-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK19-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] +// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] // CHECK19-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK19-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK19: arraydestroy.done17: -// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK19-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK19-NEXT: ret i32 [[TMP14]] // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK19-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -8446,7 +8446,7 @@ int main() { // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK19-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK19-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -8455,7 +8455,7 @@ int main() { // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK19-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -8472,17 +8472,17 @@ int main() { // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK19-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK19-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK19-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -8490,22 +8490,22 @@ int main() { // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK19-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK19-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK19-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK19-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK19-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK19-NEXT: ret void // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK19-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -8517,7 +8517,7 @@ int main() { // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK19-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -8533,7 +8533,7 @@ int main() { // // // CHECK19-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK19-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK19-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK19-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -8553,42 +8553,42 @@ int main() { // CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK20-SAME: () #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK20-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK20-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK20-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK20-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK20-SAME: () #[[ATTR0]] { // CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK20-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -8596,12 +8596,12 @@ int main() { // CHECK20-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK20-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK20-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK20-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -8609,7 +8609,7 @@ int main() { // CHECK20: arraydestroy.body: // CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK20-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK20: arraydestroy.done1: @@ -8619,7 +8619,7 @@ int main() { // CHECK20-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK20-SAME: () #[[ATTR0]] { // CHECK20-NEXT: entry: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK20-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK20-NEXT: ret void // @@ -8648,12 +8648,12 @@ int main() { // CHECK20-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK20: arrayctor.loop: // CHECK20-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK20-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK20-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK20-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK20: arrayctor.cont: -// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK20-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK20: omp.inner.for.cond: // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 @@ -8690,18 +8690,18 @@ int main() { // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK20: omp.inner.for.end: // CHECK20-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK20-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 // CHECK20-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK20: arraydestroy.body: // CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK20-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK20-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK20: arraydestroy.done5: -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK20-NEXT: ret i32 [[CALL]] // // @@ -8725,14 +8725,14 @@ int main() { // CHECK20-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK20-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK20-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK20-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK20-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK20-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK20-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK20-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK20-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -8744,12 +8744,12 @@ int main() { // CHECK20-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK20: arrayctor.loop: // CHECK20-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK20-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK20-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK20-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK20: arrayctor.cont: -// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK20-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK20-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK20: omp.inner.for.cond: @@ -8784,14 +8784,14 @@ int main() { // CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK20: omp.inner.for.end: // CHECK20-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK20-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK20-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK20: arraydestroy.body: // CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK20-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK20: arraydestroy.done10: @@ -8802,17 +8802,17 @@ int main() { // CHECK20: arraydestroy.body12: // CHECK20-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK20-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] +// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] // CHECK20-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK20-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK20: arraydestroy.done16: -// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK20-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK20-NEXT: ret i32 [[TMP14]] // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK20-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -8825,7 +8825,7 @@ int main() { // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK20-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK20-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -8834,7 +8834,7 @@ int main() { // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK20-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -8851,17 +8851,17 @@ int main() { // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK20-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK20-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK20-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -8869,22 +8869,22 @@ int main() { // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK20-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK20-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK20-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK20-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK20-NEXT: ret void // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK20-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -8896,7 +8896,7 @@ int main() { // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK20-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -8912,7 +8912,7 @@ int main() { // // // CHECK20-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK20-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK20-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK20-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -8932,42 +8932,42 @@ int main() { // CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK21-SAME: () #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK21-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK21-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK21-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK21-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK21-SAME: () #[[ATTR0]] { // CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK21-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -8975,12 +8975,12 @@ int main() { // CHECK21-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK21-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK21-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK21-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK21-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -8988,7 +8988,7 @@ int main() { // CHECK21: arraydestroy.body: // CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK21: arraydestroy.done1: @@ -8998,7 +8998,7 @@ int main() { // CHECK21-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK21-SAME: () #[[ATTR0]] { // CHECK21-NEXT: entry: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK21-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK21-NEXT: ret void // @@ -9027,12 +9027,12 @@ int main() { // CHECK21-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK21: arrayctor.loop: // CHECK21-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK21-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK21-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK21-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK21: arrayctor.cont: -// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK21-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21: omp.inner.for.cond: // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 @@ -9069,18 +9069,18 @@ int main() { // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK21-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK21-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 // CHECK21-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK21: arraydestroy.body: // CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK21-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK21: arraydestroy.done5: -// CHECK21-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK21-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK21-NEXT: ret i32 [[CALL]] // // @@ -9104,14 +9104,14 @@ int main() { // CHECK21-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK21-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK21-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK21-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK21-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK21-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK21-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK21-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK21-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK21-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK21-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -9123,12 +9123,12 @@ int main() { // CHECK21-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK21: arrayctor.loop: // CHECK21-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK21-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK21-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK21-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK21: arrayctor.cont: -// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK21-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK21-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK21: omp.inner.for.cond: @@ -9163,14 +9163,14 @@ int main() { // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK21: omp.inner.for.end: // CHECK21-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK21-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK21-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK21-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK21: arraydestroy.body: // CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK21-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK21: arraydestroy.done10: @@ -9181,17 +9181,17 @@ int main() { // CHECK21: arraydestroy.body12: // CHECK21-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK21-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] +// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] // CHECK21-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK21-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK21: arraydestroy.done16: -// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK21-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK21-NEXT: ret i32 [[TMP14]] // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK21-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -9204,7 +9204,7 @@ int main() { // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK21-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK21-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -9213,7 +9213,7 @@ int main() { // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK21-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -9230,17 +9230,17 @@ int main() { // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK21-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK21-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK21-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -9248,22 +9248,22 @@ int main() { // CHECK21-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK21-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK21-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK21-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK21-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK21-NEXT: ret void // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK21-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -9275,7 +9275,7 @@ int main() { // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK21-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -9291,7 +9291,7 @@ int main() { // // // CHECK21-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK21-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK21-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK21-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -9311,42 +9311,42 @@ int main() { // CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK22-SAME: () #[[ATTR0:[0-9]+]] { // CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK22-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK22-NEXT: ret void // // // CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK22-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK22-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK22-NEXT: ret void // // // CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK22-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK22-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK22-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK22-NEXT: ret void // // // CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK22-SAME: () #[[ATTR0]] { // CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK22-NEXT: ret void // // // CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK22-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -9354,12 +9354,12 @@ int main() { // CHECK22-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK22-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK22-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK22-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK22-NEXT: ret void // // // CHECK22-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK22-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK22-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -9367,7 +9367,7 @@ int main() { // CHECK22: arraydestroy.body: // CHECK22-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK22-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK22-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK22-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK22-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK22-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK22: arraydestroy.done1: @@ -9377,7 +9377,7 @@ int main() { // CHECK22-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK22-SAME: () #[[ATTR0]] { // CHECK22-NEXT: entry: -// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK22-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK22-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK22-NEXT: ret void // @@ -9388,12 +9388,12 @@ int main() { // CHECK22-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK22-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK22-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK22-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK22-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK22-NEXT: ret i32 0 // // // CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK22-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -9406,7 +9406,7 @@ int main() { // // // CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK22-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK22-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -9415,7 +9415,7 @@ int main() { // // // CHECK22-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK22-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK22-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp index b36abcd1248cf6241f7ed6d9f89cf673b6290027..380f7c0fbdb4c798047830699d6df3d51333e92a 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp @@ -71,7 +71,7 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l38() #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT3]] // CHECK1: omp_offload.cont3: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -83,7 +83,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -118,24 +118,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group !6 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !6 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -151,7 +151,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -196,23 +196,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -235,7 +235,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -270,24 +270,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group !15 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -303,7 +303,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -348,23 +348,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -402,7 +402,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -437,24 +437,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !21 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !21 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -470,7 +470,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -515,23 +515,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -576,7 +576,7 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l38() #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT3]] // CHECK2: omp_offload.cont3: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -588,7 +588,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -623,24 +623,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group !6 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !6 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -656,7 +656,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -701,23 +701,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -740,7 +740,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -775,24 +775,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group !15 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -808,7 +808,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -853,23 +853,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -907,7 +907,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -942,24 +942,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !21 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !21 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -975,7 +975,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1020,23 +1020,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1123,7 +1123,7 @@ int main() { // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK3: omp.inner.for.end15: // CHECK3-NEXT: store i32 1000, i32* [[I6]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -1228,7 +1228,7 @@ int main() { // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK4: omp.inner.for.end15: // CHECK4-NEXT: store i32 1000, i32* [[I6]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_codegen.cpp index ce0ba362269eae023c577476618c8efa030068be..96e28443c816f3ae4e3c4fe4bd6502e263ed1377 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_codegen.cpp @@ -117,12 +117,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -132,7 +132,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -173,23 +173,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]), !llvm.access.group !5 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -226,7 +226,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -277,27 +277,27 @@ int main() { // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -334,7 +334,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -358,7 +358,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -415,7 +415,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 @@ -425,7 +425,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -466,23 +466,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[T_VAR1]]), !llvm.access.group !14 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[T_VAR1]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -519,7 +519,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -570,27 +570,27 @@ int main() { // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK1-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -627,7 +627,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -651,7 +651,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -708,12 +708,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -723,7 +723,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -764,23 +764,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]), !llvm.access.group !5 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -817,7 +817,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -868,27 +868,27 @@ int main() { // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK2-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -925,7 +925,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -949,7 +949,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1006,7 +1006,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 @@ -1016,7 +1016,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1057,23 +1057,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[T_VAR1]]), !llvm.access.group !14 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[T_VAR1]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1110,7 +1110,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1161,27 +1161,27 @@ int main() { // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK2-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1218,7 +1218,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1242,7 +1242,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1299,12 +1299,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 @@ -1314,7 +1314,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1355,21 +1355,21 @@ int main() { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[SIVAR1]]), !llvm.access.group !6 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[SIVAR1]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1406,7 +1406,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1455,27 +1455,27 @@ int main() { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1512,7 +1512,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1536,7 +1536,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1593,7 +1593,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 @@ -1603,7 +1603,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1644,21 +1644,21 @@ int main() { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[T_VAR1]]), !llvm.access.group !15 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[T_VAR1]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1695,7 +1695,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1744,27 +1744,27 @@ int main() { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR1]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1801,7 +1801,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1825,7 +1825,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1882,12 +1882,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 @@ -1897,7 +1897,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1938,21 +1938,21 @@ int main() { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[SIVAR1]]), !llvm.access.group !6 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[SIVAR1]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1989,7 +1989,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2038,27 +2038,27 @@ int main() { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2095,7 +2095,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2119,7 +2119,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2176,7 +2176,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 @@ -2186,7 +2186,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2227,21 +2227,21 @@ int main() { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[T_VAR1]]), !llvm.access.group !15 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[T_VAR1]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2278,7 +2278,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2327,27 +2327,27 @@ int main() { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR1]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2384,7 +2384,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2408,7 +2408,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2444,12 +2444,12 @@ int main() { // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 -// CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -2459,7 +2459,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2500,23 +2500,23 @@ int main() { // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]), !llvm.access.group !4 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2553,7 +2553,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2605,30 +2605,30 @@ int main() { // CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4, !llvm.access.group !8 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK5-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !8 +// CHECK5-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8, !llvm.access.group !8 -// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK5-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8 +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2665,7 +2665,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2689,7 +2689,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2725,12 +2725,12 @@ int main() { // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 -// CHECK6-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -2740,7 +2740,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2781,23 +2781,23 @@ int main() { // CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]), !llvm.access.group !4 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -2834,7 +2834,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2886,30 +2886,30 @@ int main() { // CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4, !llvm.access.group !8 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK6-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !8 +// CHECK6-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 // CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK6-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8, !llvm.access.group !8 -// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK6-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8 +// CHECK6-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -2946,7 +2946,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2970,7 +2970,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3045,7 +3045,7 @@ int main() { // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK7-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK7-NEXT: ret i32 [[CALL]] // // @@ -3145,7 +3145,7 @@ int main() { // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK8-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK8-NEXT: ret i32 [[CALL]] // // @@ -3245,7 +3245,7 @@ int main() { // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK9-NEXT: ret i32 [[CALL]] // // @@ -3345,7 +3345,7 @@ int main() { // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK10-NEXT: ret i32 [[CALL]] // // @@ -3406,7 +3406,7 @@ int main() { // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: ret i32 0 // // @@ -3416,6 +3416,6 @@ int main() { // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK12-NEXT: ret i32 0 // diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp index aa8ea7b5e6de73de911cb06e318e9bb6571c57cf..da7a6b1712ce6c4239ccd24e45170eb72d87db82 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp @@ -198,12 +198,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -330,7 +330,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -340,7 +340,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -410,7 +410,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -495,7 +495,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -505,7 +505,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -575,7 +575,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -660,7 +660,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -670,7 +670,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -740,7 +740,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -846,7 +846,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -856,7 +856,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -926,7 +926,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1009,7 +1009,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1019,7 +1019,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1089,7 +1089,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1182,12 +1182,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -1314,7 +1314,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1324,7 +1324,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1394,7 +1394,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1479,7 +1479,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1489,7 +1489,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1559,7 +1559,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1644,7 +1644,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1654,7 +1654,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1724,7 +1724,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1830,7 +1830,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1840,7 +1840,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1910,7 +1910,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1993,7 +1993,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -2003,7 +2003,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2073,7 +2073,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2166,12 +2166,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -2298,7 +2298,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2308,7 +2308,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2376,7 +2376,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2458,7 +2458,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2468,7 +2468,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2536,7 +2536,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2618,7 +2618,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2628,7 +2628,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2696,7 +2696,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2797,7 +2797,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2807,7 +2807,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2875,7 +2875,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2955,7 +2955,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2965,7 +2965,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3033,7 +3033,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3123,12 +3123,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -3255,7 +3255,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3265,7 +3265,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3333,7 +3333,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3415,7 +3415,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3425,7 +3425,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3493,7 +3493,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3575,7 +3575,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3585,7 +3585,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3653,7 +3653,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3754,7 +3754,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3764,7 +3764,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3832,7 +3832,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3912,7 +3912,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3922,7 +3922,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3990,7 +3990,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4080,12 +4080,12 @@ int main (int argc, char **argv) { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -4212,7 +4212,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -4222,7 +4222,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4292,7 +4292,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4377,7 +4377,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -4387,7 +4387,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4457,7 +4457,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4542,7 +4542,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -4552,7 +4552,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4622,7 +4622,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4728,7 +4728,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -4738,7 +4738,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4808,7 +4808,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4891,7 +4891,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -4901,7 +4901,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4971,7 +4971,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5064,12 +5064,12 @@ int main (int argc, char **argv) { // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -5196,7 +5196,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -5206,7 +5206,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5276,7 +5276,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5361,7 +5361,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -5371,7 +5371,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5441,7 +5441,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5526,7 +5526,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -5536,7 +5536,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5606,7 +5606,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5712,7 +5712,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -5722,7 +5722,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5792,7 +5792,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5875,7 +5875,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -5885,7 +5885,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5955,7 +5955,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6048,12 +6048,12 @@ int main (int argc, char **argv) { // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -6180,7 +6180,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6190,7 +6190,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6258,7 +6258,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6340,7 +6340,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6350,7 +6350,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6418,7 +6418,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6500,7 +6500,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6510,7 +6510,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6578,7 +6578,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6679,7 +6679,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6689,7 +6689,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6757,7 +6757,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6837,7 +6837,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6847,7 +6847,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6915,7 +6915,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7005,12 +7005,12 @@ int main (int argc, char **argv) { // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK8-NEXT: ret i32 [[CALL]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -7137,7 +7137,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -7147,7 +7147,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7215,7 +7215,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7297,7 +7297,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -7307,7 +7307,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7375,7 +7375,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7457,7 +7457,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l44 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -7467,7 +7467,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7535,7 +7535,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7636,7 +7636,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l49 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -7646,7 +7646,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7714,7 +7714,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7794,7 +7794,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l54 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -7804,7 +7804,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7872,7 +7872,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7962,12 +7962,12 @@ int main (int argc, char **argv) { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK9-NEXT: ret i32 [[CALL]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK9-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -8157,12 +8157,12 @@ int main (int argc, char **argv) { // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK10-NEXT: ret i32 [[CALL]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK10-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK10-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -8352,12 +8352,12 @@ int main (int argc, char **argv) { // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK11-NEXT: ret i32 [[CALL]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK11-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK11-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -8542,12 +8542,12 @@ int main (int argc, char **argv) { // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK12-NEXT: ret i32 [[CALL]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK12-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK12-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -8729,7 +8729,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -9106,7 +9106,7 @@ int main (int argc, char **argv) { // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT67]] // CHECK13: omp_offload.cont67: // CHECK13-NEXT: [[TMP171:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP171]]) +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP171]]) // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP172:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP172]]) @@ -9115,7 +9115,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -9136,7 +9136,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9244,7 +9244,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9361,7 +9361,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -9382,7 +9382,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9490,7 +9490,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9607,7 +9607,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -9636,7 +9636,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9777,7 +9777,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9897,7 +9897,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -9918,7 +9918,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10026,7 +10026,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10139,7 +10139,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -10168,7 +10168,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10284,7 +10284,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10401,7 +10401,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -10554,7 +10554,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -10564,7 +10564,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10634,7 +10634,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10718,7 +10718,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -10728,7 +10728,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10798,7 +10798,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10882,7 +10882,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -10900,7 +10900,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10978,7 +10978,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11087,7 +11087,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -11097,7 +11097,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11167,7 +11167,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11249,7 +11249,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -11267,7 +11267,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11345,7 +11345,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11438,7 +11438,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -11815,7 +11815,7 @@ int main (int argc, char **argv) { // CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT67]] // CHECK14: omp_offload.cont67: // CHECK14-NEXT: [[TMP171:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP171]]) +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP171]]) // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[TMP172:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP172]]) @@ -11824,7 +11824,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -11845,7 +11845,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11953,7 +11953,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12070,7 +12070,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -12091,7 +12091,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12199,7 +12199,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12316,7 +12316,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -12345,7 +12345,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12486,7 +12486,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12606,7 +12606,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -12627,7 +12627,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12735,7 +12735,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12848,7 +12848,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -12877,7 +12877,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12993,7 +12993,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13110,7 +13110,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -13263,7 +13263,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -13273,7 +13273,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13343,7 +13343,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13427,7 +13427,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -13437,7 +13437,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13507,7 +13507,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13591,7 +13591,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -13609,7 +13609,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13687,7 +13687,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13796,7 +13796,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -13806,7 +13806,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13876,7 +13876,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13958,7 +13958,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -13976,7 +13976,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14054,7 +14054,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14147,7 +14147,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -14521,7 +14521,7 @@ int main (int argc, char **argv) { // CHECK15-NEXT: br label [[OMP_OFFLOAD_CONT61]] // CHECK15: omp_offload.cont61: // CHECK15-NEXT: [[TMP175:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP175]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP175]]) // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP176]]) @@ -14530,7 +14530,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -14549,7 +14549,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14653,7 +14653,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14766,7 +14766,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -14785,7 +14785,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14889,7 +14889,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15002,7 +15002,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -15027,7 +15027,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15162,7 +15162,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15277,7 +15277,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -15296,7 +15296,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15400,7 +15400,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15509,7 +15509,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -15534,7 +15534,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15644,7 +15644,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15756,7 +15756,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -15907,7 +15907,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -15917,7 +15917,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15985,7 +15985,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16066,7 +16066,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -16076,7 +16076,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16144,7 +16144,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16225,7 +16225,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -16241,7 +16241,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16315,7 +16315,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16418,7 +16418,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -16428,7 +16428,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16496,7 +16496,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16575,7 +16575,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -16591,7 +16591,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16665,7 +16665,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16754,7 +16754,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -17128,7 +17128,7 @@ int main (int argc, char **argv) { // CHECK16-NEXT: br label [[OMP_OFFLOAD_CONT61]] // CHECK16: omp_offload.cont61: // CHECK16-NEXT: [[TMP175:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP175]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP175]]) // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP176]]) @@ -17137,7 +17137,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK16-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -17156,7 +17156,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17260,7 +17260,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17373,7 +17373,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK16-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -17392,7 +17392,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17496,7 +17496,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17609,7 +17609,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK16-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -17634,7 +17634,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17769,7 +17769,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17884,7 +17884,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK16-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -17903,7 +17903,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18007,7 +18007,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18116,7 +18116,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK16-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -18141,7 +18141,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18251,7 +18251,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18363,7 +18363,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -18514,7 +18514,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -18524,7 +18524,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18592,7 +18592,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18673,7 +18673,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -18683,7 +18683,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18751,7 +18751,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18832,7 +18832,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -18848,7 +18848,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -18922,7 +18922,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19025,7 +19025,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -19035,7 +19035,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19103,7 +19103,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19182,7 +19182,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK16-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -19198,7 +19198,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19272,7 +19272,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19361,7 +19361,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@main -// CHECK17-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -19738,7 +19738,7 @@ int main (int argc, char **argv) { // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT67]] // CHECK17: omp_offload.cont67: // CHECK17-NEXT: [[TMP171:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP171]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP171]]) // CHECK17-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK17-NEXT: [[TMP172:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP172]]) @@ -19747,7 +19747,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -19768,7 +19768,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19876,7 +19876,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19993,7 +19993,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -20014,7 +20014,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20122,7 +20122,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20239,7 +20239,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -20268,7 +20268,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20409,7 +20409,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20529,7 +20529,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -20550,7 +20550,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20658,7 +20658,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20771,7 +20771,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -20800,7 +20800,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20916,7 +20916,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21033,7 +21033,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK17-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK17-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -21186,7 +21186,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -21196,7 +21196,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21266,7 +21266,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21350,7 +21350,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -21360,7 +21360,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21430,7 +21430,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21514,7 +21514,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -21532,7 +21532,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21610,7 +21610,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21719,7 +21719,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -21729,7 +21729,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21799,7 +21799,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21881,7 +21881,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -21899,7 +21899,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21977,7 +21977,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22070,7 +22070,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@main -// CHECK18-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -22447,7 +22447,7 @@ int main (int argc, char **argv) { // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT67]] // CHECK18: omp_offload.cont67: // CHECK18-NEXT: [[TMP171:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP171]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP171]]) // CHECK18-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK18-NEXT: [[TMP172:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP172]]) @@ -22456,7 +22456,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK18-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -22477,7 +22477,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22585,7 +22585,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22702,7 +22702,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK18-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -22723,7 +22723,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22831,7 +22831,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22948,7 +22948,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK18-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -22977,7 +22977,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -23118,7 +23118,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -23238,7 +23238,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK18-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -23259,7 +23259,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -23367,7 +23367,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -23480,7 +23480,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK18-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -23509,7 +23509,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -23625,7 +23625,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -23742,7 +23742,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK18-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK18-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -23895,7 +23895,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -23905,7 +23905,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -23975,7 +23975,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -24059,7 +24059,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -24069,7 +24069,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -24139,7 +24139,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -24223,7 +24223,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -24241,7 +24241,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -24319,7 +24319,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -24428,7 +24428,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -24438,7 +24438,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -24508,7 +24508,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -24590,7 +24590,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -24608,7 +24608,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -24686,7 +24686,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -24779,7 +24779,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@main -// CHECK19-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -25153,7 +25153,7 @@ int main (int argc, char **argv) { // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT61]] // CHECK19: omp_offload.cont61: // CHECK19-NEXT: [[TMP175:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP175]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP175]]) // CHECK19-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK19-NEXT: [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP176]]) @@ -25162,7 +25162,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -25181,7 +25181,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25285,7 +25285,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25398,7 +25398,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -25417,7 +25417,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25521,7 +25521,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25634,7 +25634,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -25659,7 +25659,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25794,7 +25794,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25909,7 +25909,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -25928,7 +25928,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26032,7 +26032,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26141,7 +26141,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -26166,7 +26166,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26276,7 +26276,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26388,7 +26388,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK19-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK19-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -26539,7 +26539,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -26549,7 +26549,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26617,7 +26617,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26698,7 +26698,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -26708,7 +26708,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26776,7 +26776,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26857,7 +26857,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -26873,7 +26873,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26947,7 +26947,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27050,7 +27050,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -27060,7 +27060,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27128,7 +27128,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27207,7 +27207,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -27223,7 +27223,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27297,7 +27297,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27386,7 +27386,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@main -// CHECK20-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -27760,7 +27760,7 @@ int main (int argc, char **argv) { // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT61]] // CHECK20: omp_offload.cont61: // CHECK20-NEXT: [[TMP175:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP175]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP175]]) // CHECK20-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK20-NEXT: [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP176]]) @@ -27769,7 +27769,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -27788,7 +27788,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27892,7 +27892,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28005,7 +28005,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l143 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -28024,7 +28024,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28128,7 +28128,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28241,7 +28241,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l147 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -28266,7 +28266,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28401,7 +28401,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28516,7 +28516,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l151 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -28535,7 +28535,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28639,7 +28639,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28748,7 +28748,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -28773,7 +28773,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28883,7 +28883,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28995,7 +28995,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK20-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK20-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -29146,7 +29146,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l112 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -29156,7 +29156,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29224,7 +29224,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29305,7 +29305,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -29315,7 +29315,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29383,7 +29383,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29464,7 +29464,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l120 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -29480,7 +29480,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29554,7 +29554,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29657,7 +29657,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l124 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -29667,7 +29667,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29735,7 +29735,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29814,7 +29814,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l128 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -29830,7 +29830,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29904,7 +29904,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29993,7 +29993,7 @@ int main (int argc, char **argv) { // // // CHECK21-LABEL: define {{[^@]+}}@main -// CHECK21-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK21-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -30305,7 +30305,7 @@ int main (int argc, char **argv) { // CHECK21-NEXT: br label [[SIMD_IF_END127]] // CHECK21: simd.if.end127: // CHECK21-NEXT: [[TMP60:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP60]]) +// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP60]]) // CHECK21-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK21-NEXT: [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP61]]) @@ -30314,7 +30314,7 @@ int main (int argc, char **argv) { // // // CHECK21-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK21-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK21-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -30501,7 +30501,7 @@ int main (int argc, char **argv) { // // // CHECK22-LABEL: define {{[^@]+}}@main -// CHECK22-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK22-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK22-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -30813,7 +30813,7 @@ int main (int argc, char **argv) { // CHECK22-NEXT: br label [[SIMD_IF_END127]] // CHECK22: simd.if.end127: // CHECK22-NEXT: [[TMP60:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP60]]) +// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP60]]) // CHECK22-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK22-NEXT: [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP61]]) @@ -30822,7 +30822,7 @@ int main (int argc, char **argv) { // // // CHECK22-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK22-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK22-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK22-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -31009,7 +31009,7 @@ int main (int argc, char **argv) { // // // CHECK23-LABEL: define {{[^@]+}}@main -// CHECK23-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK23-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -31315,7 +31315,7 @@ int main (int argc, char **argv) { // CHECK23-NEXT: br label [[SIMD_IF_END123]] // CHECK23: simd.if.end123: // CHECK23-NEXT: [[TMP59:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP59]]) +// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP59]]) // CHECK23-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK23-NEXT: [[TMP60:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP60]]) @@ -31324,7 +31324,7 @@ int main (int argc, char **argv) { // // // CHECK23-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK23-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK23-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -31506,7 +31506,7 @@ int main (int argc, char **argv) { // // // CHECK24-LABEL: define {{[^@]+}}@main -// CHECK24-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK24-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -31812,7 +31812,7 @@ int main (int argc, char **argv) { // CHECK24-NEXT: br label [[SIMD_IF_END123]] // CHECK24: simd.if.end123: // CHECK24-NEXT: [[TMP59:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP59]]) +// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP59]]) // CHECK24-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK24-NEXT: [[TMP60:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP60]]) @@ -31821,7 +31821,7 @@ int main (int argc, char **argv) { // // // CHECK24-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK24-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK24-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp index 256d228c99ee08b0c4b32c037f69163ae07b3c99..11c3c307298c5bada2d4b439d607f12c9e9a86d6 100644 --- a/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp @@ -122,33 +122,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -161,7 +161,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -172,14 +172,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -187,12 +187,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -200,7 +200,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -208,7 +208,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -227,7 +227,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -246,7 +246,7 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -258,7 +258,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -285,12 +285,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -349,14 +349,14 @@ int main() { // CHECK1-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done7: @@ -374,14 +374,14 @@ int main() { // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -399,27 +399,27 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP4]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -427,7 +427,7 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // @@ -439,7 +439,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -468,12 +468,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -530,14 +530,14 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -545,17 +545,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -567,7 +567,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -583,7 +583,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -610,33 +610,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -649,7 +649,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -660,14 +660,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -675,12 +675,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -688,7 +688,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -696,7 +696,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -715,7 +715,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -734,7 +734,7 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -746,7 +746,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -773,12 +773,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -837,14 +837,14 @@ int main() { // CHECK2-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done7: @@ -862,14 +862,14 @@ int main() { // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -887,27 +887,27 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP4]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -915,7 +915,7 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // @@ -927,7 +927,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -956,12 +956,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1018,14 +1018,14 @@ int main() { // CHECK2-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done8: @@ -1033,17 +1033,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1055,7 +1055,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1071,7 +1071,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1098,33 +1098,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1137,7 +1137,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1148,14 +1148,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1163,12 +1163,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1176,7 +1176,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1184,7 +1184,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1203,7 +1203,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -1222,7 +1222,7 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -1234,7 +1234,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1261,12 +1261,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1323,14 +1323,14 @@ int main() { // CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -1348,14 +1348,14 @@ int main() { // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -1373,27 +1373,27 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP4]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1401,7 +1401,7 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // @@ -1413,7 +1413,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1442,12 +1442,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1502,14 +1502,14 @@ int main() { // CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -1517,17 +1517,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -1539,7 +1539,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1555,7 +1555,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -1582,33 +1582,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1621,7 +1621,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1632,14 +1632,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1647,12 +1647,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1660,7 +1660,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -1668,7 +1668,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1687,7 +1687,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -1706,7 +1706,7 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // @@ -1718,7 +1718,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1745,12 +1745,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1807,14 +1807,14 @@ int main() { // CHECK4-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done6: @@ -1832,14 +1832,14 @@ int main() { // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -1857,27 +1857,27 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP4]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1885,7 +1885,7 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // @@ -1897,7 +1897,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1926,12 +1926,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1986,14 +1986,14 @@ int main() { // CHECK4-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done7: @@ -2001,17 +2001,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2023,7 +2023,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2039,7 +2039,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2066,33 +2066,33 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2105,7 +2105,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2116,14 +2116,14 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2131,12 +2131,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2144,7 +2144,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -2152,7 +2152,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2171,7 +2171,7 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // @@ -2182,7 +2182,7 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // @@ -2194,7 +2194,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2257,7 +2257,7 @@ int main() { // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2292,33 +2292,33 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2331,7 +2331,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2342,14 +2342,14 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2357,12 +2357,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2370,7 +2370,7 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: @@ -2378,7 +2378,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2397,7 +2397,7 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // @@ -2408,7 +2408,7 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // @@ -2420,7 +2420,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2483,7 +2483,7 @@ int main() { // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2514,3 +2514,4 @@ int main() { // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp index 7baf7e0d4f6bbd0e5f788f1e7048cf2511ff0edb..5dac84b39a1dff73c952ff62f38b4b62d1ad5a3a 100644 --- a/clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp @@ -105,12 +105,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -120,7 +120,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -212,7 +212,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -269,7 +269,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 @@ -279,7 +279,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -371,7 +371,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -428,12 +428,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -443,7 +443,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -535,7 +535,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -592,7 +592,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 @@ -602,7 +602,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -694,7 +694,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -751,12 +751,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 @@ -766,7 +766,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -858,7 +858,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -915,7 +915,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 @@ -925,7 +925,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1017,7 +1017,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1074,12 +1074,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(i32* @_ZZ4mainE5sivar) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 @@ -1089,7 +1089,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1181,7 +1181,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1238,7 +1238,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 @@ -1248,7 +1248,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1340,7 +1340,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1376,12 +1376,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 -// CHECK9-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -1391,7 +1391,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1448,7 +1448,7 @@ int main() { // CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1487,7 +1487,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1523,12 +1523,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 -// CHECK10-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -1538,7 +1538,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1595,7 +1595,7 @@ int main() { // CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1634,7 +1634,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1663,3 +1663,4 @@ int main() { // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp index 1858d2d9c2e9426bf75e02ae60340581393d3980..04016eb544e0bcaa31c3460fd036c8e849742aa1 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp @@ -294,7 +294,7 @@ int bar(int n){ #endif // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -616,7 +616,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -641,7 +641,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -711,7 +711,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -740,7 +740,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -818,7 +818,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -833,7 +833,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -906,7 +906,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -921,7 +921,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -996,7 +996,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -1019,7 +1019,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1100,7 +1100,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -1139,7 +1139,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1271,7 +1271,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z3bari -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1279,22 +1279,22 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK1-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -1303,7 +1303,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1419,7 +1419,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1536,7 +1536,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1607,7 +1607,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1634,7 +1634,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1730,7 +1730,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -1772,7 +1772,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1912,7 +1912,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -1938,7 +1938,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2033,7 +2033,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2355,7 +2355,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK2-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -2380,7 +2380,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2450,7 +2450,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -2479,7 +2479,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2557,7 +2557,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK2-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -2572,7 +2572,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2645,7 +2645,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK2-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -2660,7 +2660,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2735,7 +2735,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -2758,7 +2758,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2839,7 +2839,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK2-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -2878,7 +2878,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3010,7 +3010,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3bari -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3018,22 +3018,22 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK2-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -3042,7 +3042,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -3158,7 +3158,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3275,7 +3275,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3346,7 +3346,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3373,7 +3373,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3469,7 +3469,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -3511,7 +3511,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3651,7 +3651,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -3677,7 +3677,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3772,7 +3772,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4089,7 +4089,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -4112,7 +4112,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4182,7 +4182,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -4211,7 +4211,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -4287,7 +4287,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -4300,7 +4300,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4372,7 +4372,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -4387,7 +4387,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4462,7 +4462,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -4483,7 +4483,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4563,7 +4563,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -4600,7 +4600,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4731,7 +4731,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3bari -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4739,22 +4739,22 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK3-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -4763,7 +4763,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -4878,7 +4878,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4993,7 +4993,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -5063,7 +5063,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5088,7 +5088,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5183,7 +5183,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -5221,7 +5221,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5359,7 +5359,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -5383,7 +5383,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5477,7 +5477,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -5794,7 +5794,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK4-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -5817,7 +5817,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5887,7 +5887,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK4-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK4-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -5916,7 +5916,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -5992,7 +5992,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 -// CHECK4-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -6005,7 +6005,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6077,7 +6077,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK4-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -6092,7 +6092,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6167,7 +6167,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -6188,7 +6188,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6268,7 +6268,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK4-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -6305,7 +6305,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6436,7 +6436,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3bari -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6444,22 +6444,22 @@ int bar(int n){ // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK4-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK4-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -6468,7 +6468,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -6583,7 +6583,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6698,7 +6698,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6768,7 +6768,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -6793,7 +6793,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6888,7 +6888,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -6926,7 +6926,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7064,7 +7064,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -7088,7 +7088,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7182,7 +7182,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -7504,7 +7504,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK5-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -7529,7 +7529,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7599,7 +7599,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK5-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK5-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -7628,7 +7628,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK5-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -7706,7 +7706,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102 -// CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -7721,7 +7721,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7794,7 +7794,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK5-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -7809,7 +7809,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7884,7 +7884,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -7907,7 +7907,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7988,7 +7988,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK5-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -8027,7 +8027,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8159,7 +8159,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@_Z3bari -// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -8167,22 +8167,22 @@ int bar(int n){ // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK5-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK5-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -8191,7 +8191,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK5-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -8329,7 +8329,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -8446,7 +8446,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -8517,7 +8517,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK5-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -8554,7 +8554,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8695,7 +8695,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -8737,7 +8737,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8877,7 +8877,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -8903,7 +8903,7 @@ int bar(int n){ // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8998,7 +8998,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK6-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -9320,7 +9320,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK6-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK6-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -9345,7 +9345,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9415,7 +9415,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK6-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK6-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 @@ -9444,7 +9444,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK6-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK6-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -9522,7 +9522,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102 -// CHECK6-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -9537,7 +9537,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9610,7 +9610,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK6-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -9625,7 +9625,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9700,7 +9700,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK6-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -9723,7 +9723,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9804,7 +9804,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK6-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -9843,7 +9843,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9975,7 +9975,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@_Z3bari -// CHECK6-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -9983,22 +9983,22 @@ int bar(int n){ // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK6-NEXT: store i32 0, i32* [[A]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK6-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK6-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK6-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -10007,7 +10007,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK6-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -10145,7 +10145,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK6-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -10262,7 +10262,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK6-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -10333,7 +10333,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK6-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -10370,7 +10370,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10511,7 +10511,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK6-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -10553,7 +10553,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10693,7 +10693,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK6-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -10719,7 +10719,7 @@ int bar(int n){ // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10814,7 +10814,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -11131,7 +11131,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK7-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK7-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -11154,7 +11154,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11224,7 +11224,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK7-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK7-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -11253,7 +11253,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK7-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK7-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -11329,7 +11329,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102 -// CHECK7-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32 [[A:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -11342,7 +11342,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11414,7 +11414,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK7-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -11429,7 +11429,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11504,7 +11504,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -11525,7 +11525,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11605,7 +11605,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK7-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -11642,7 +11642,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -11773,7 +11773,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@_Z3bari -// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -11781,22 +11781,22 @@ int bar(int n){ // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK7-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK7-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -11805,7 +11805,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK7-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -11942,7 +11942,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -12057,7 +12057,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -12127,7 +12127,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK7-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -12162,7 +12162,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12302,7 +12302,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -12340,7 +12340,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12478,7 +12478,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -12502,7 +12502,7 @@ int bar(int n){ // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12596,7 +12596,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK8-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -12913,7 +12913,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK8-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -12936,7 +12936,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13006,7 +13006,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK8-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK8-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 // CHECK8-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 @@ -13035,7 +13035,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK8-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK8-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 @@ -13111,7 +13111,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102 -// CHECK8-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32 [[A:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 @@ -13124,7 +13124,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13196,7 +13196,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK8-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -13211,7 +13211,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13286,7 +13286,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK8-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -13307,7 +13307,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13387,7 +13387,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK8-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -13424,7 +13424,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13555,7 +13555,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@_Z3bari -// CHECK8-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -13563,22 +13563,22 @@ int bar(int n){ // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK8-NEXT: store i32 0, i32* [[A]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK8-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK8-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK8-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -13587,7 +13587,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK8-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -13724,7 +13724,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK8-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -13839,7 +13839,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK8-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -13909,7 +13909,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK8-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -13944,7 +13944,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14084,7 +14084,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK8-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -14122,7 +14122,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14260,7 +14260,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK8-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -14284,7 +14284,7 @@ int bar(int n){ // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14378,7 +14378,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14624,7 +14624,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@_Z3bari -// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14632,22 +14632,22 @@ int bar(int n){ // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK9-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK9-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK9-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK9-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK9-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK9-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK9-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK9-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK9-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK9-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -14656,7 +14656,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -14733,7 +14733,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14833,7 +14833,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK9-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -14889,7 +14889,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK10-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15135,7 +15135,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@_Z3bari -// CHECK10-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15143,22 +15143,22 @@ int bar(int n){ // CHECK10-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK10-NEXT: store i32 0, i32* [[A]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK10-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK10-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK10-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK10-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK10-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK10-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK10-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK10-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK10-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK10-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -15167,7 +15167,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK10-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -15244,7 +15244,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK10-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15344,7 +15344,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK10-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK10-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15400,7 +15400,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15644,7 +15644,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@_Z3bari -// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15652,22 +15652,22 @@ int bar(int n){ // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK11-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK11-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK11-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK11-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK11-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -15676,7 +15676,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK11-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -15752,7 +15752,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15852,7 +15852,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK11-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -15908,7 +15908,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16152,7 +16152,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@_Z3bari -// CHECK12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16160,22 +16160,22 @@ int bar(int n){ // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK12-NEXT: store i32 0, i32* [[A]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK12-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK12-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK12-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK12-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK12-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK12-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK12-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK12-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -16184,7 +16184,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK12-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -16260,7 +16260,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16360,7 +16360,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK12-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16416,7 +16416,7 @@ int bar(int n){ // // // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16662,7 +16662,7 @@ int bar(int n){ // // // CHECK13-LABEL: define {{[^@]+}}@_Z3bari -// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16670,22 +16670,22 @@ int bar(int n){ // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK13-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK13-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -16694,7 +16694,7 @@ int bar(int n){ // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK13-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -16818,7 +16818,7 @@ int bar(int n){ // // // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16918,7 +16918,7 @@ int bar(int n){ // // // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -16974,7 +16974,7 @@ int bar(int n){ // // // CHECK14-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK14-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -17220,7 +17220,7 @@ int bar(int n){ // // // CHECK14-LABEL: define {{[^@]+}}@_Z3bari -// CHECK14-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -17228,22 +17228,22 @@ int bar(int n){ // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK14-NEXT: store i32 0, i32* [[A]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK14-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK14-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK14-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -17252,7 +17252,7 @@ int bar(int n){ // // // CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK14-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -17376,7 +17376,7 @@ int bar(int n){ // // // CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK14-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -17476,7 +17476,7 @@ int bar(int n){ // // // CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK14-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -17532,7 +17532,7 @@ int bar(int n){ // // // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -17776,7 +17776,7 @@ int bar(int n){ // // // CHECK15-LABEL: define {{[^@]+}}@_Z3bari -// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -17784,22 +17784,22 @@ int bar(int n){ // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK15-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK15-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -17808,7 +17808,7 @@ int bar(int n){ // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK15-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -17931,7 +17931,7 @@ int bar(int n){ // // // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -18031,7 +18031,7 @@ int bar(int n){ // // // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -18087,7 +18087,7 @@ int bar(int n){ // // // CHECK16-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK16-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -18331,7 +18331,7 @@ int bar(int n){ // // // CHECK16-LABEL: define {{[^@]+}}@_Z3bari -// CHECK16-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -18339,22 +18339,22 @@ int bar(int n){ // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK16-NEXT: store i32 0, i32* [[A]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK16-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK16-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK16-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -18363,7 +18363,7 @@ int bar(int n){ // // // CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK16-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -18486,7 +18486,7 @@ int bar(int n){ // // // CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK16-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -18586,7 +18586,7 @@ int bar(int n){ // // // CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK16-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -18642,7 +18642,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -18667,7 +18667,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18737,7 +18737,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -18752,7 +18752,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18827,7 +18827,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -18850,7 +18850,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18931,7 +18931,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -18970,7 +18970,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19102,7 +19102,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -19144,7 +19144,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19284,7 +19284,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -19311,7 +19311,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19407,7 +19407,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -19433,7 +19433,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19521,7 +19521,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK18-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -19546,7 +19546,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19616,7 +19616,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK18-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -19631,7 +19631,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19706,7 +19706,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -19729,7 +19729,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19810,7 +19810,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK18-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -19849,7 +19849,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19981,7 +19981,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -20023,7 +20023,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20163,7 +20163,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -20190,7 +20190,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20286,7 +20286,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -20312,7 +20312,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20400,7 +20400,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -20423,7 +20423,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20493,7 +20493,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -20508,7 +20508,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20583,7 +20583,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -20604,7 +20604,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20684,7 +20684,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -20721,7 +20721,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20852,7 +20852,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -20890,7 +20890,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21028,7 +21028,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -21053,7 +21053,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21148,7 +21148,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -21172,7 +21172,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21259,7 +21259,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK20-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -21282,7 +21282,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21352,7 +21352,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK20-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -21367,7 +21367,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21442,7 +21442,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -21463,7 +21463,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21543,7 +21543,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -21580,7 +21580,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21711,7 +21711,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -21749,7 +21749,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21887,7 +21887,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -21912,7 +21912,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22007,7 +22007,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -22031,7 +22031,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22118,7 +22118,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK21-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK21-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -22143,7 +22143,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22213,7 +22213,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK21-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -22228,7 +22228,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22303,7 +22303,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -22326,7 +22326,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22407,7 +22407,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK21-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -22446,7 +22446,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22578,7 +22578,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -22620,7 +22620,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22760,7 +22760,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK21-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -22797,7 +22797,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22938,7 +22938,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK21-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -22964,7 +22964,7 @@ int bar(int n){ // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -23052,7 +23052,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK22-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK22-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 @@ -23077,7 +23077,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -23147,7 +23147,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK22-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 @@ -23162,7 +23162,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -23237,7 +23237,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK22-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -23260,7 +23260,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -23341,7 +23341,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK22-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 @@ -23380,7 +23380,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -23512,7 +23512,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK22-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -23554,7 +23554,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[N:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -23694,7 +23694,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK22-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK22-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -23731,7 +23731,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -23872,7 +23872,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK22-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK22-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK22-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 @@ -23898,7 +23898,7 @@ int bar(int n){ // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -23986,7 +23986,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK23-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK23-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -24009,7 +24009,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24079,7 +24079,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK23-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -24094,7 +24094,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24169,7 +24169,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -24190,7 +24190,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24270,7 +24270,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK23-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -24307,7 +24307,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24438,7 +24438,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -24476,7 +24476,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24614,7 +24614,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK23-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -24649,7 +24649,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24789,7 +24789,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK23-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -24813,7 +24813,7 @@ int bar(int n){ // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24900,7 +24900,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 -// CHECK24-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK24-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 @@ -24923,7 +24923,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24993,7 +24993,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 -// CHECK24-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 @@ -25008,7 +25008,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25083,7 +25083,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 -// CHECK24-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -25104,7 +25104,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25184,7 +25184,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 -// CHECK24-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 @@ -25221,7 +25221,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25352,7 +25352,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 -// CHECK24-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -25390,7 +25390,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[N:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25528,7 +25528,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 -// CHECK24-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK24-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -25563,7 +25563,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25703,7 +25703,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 -// CHECK24-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// CHECK24-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 @@ -25727,7 +25727,7 @@ int bar(int n){ // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25814,7 +25814,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26060,7 +26060,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@_Z3bari -// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26068,22 +26068,22 @@ int bar(int n){ // CHECK25-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK25-NEXT: store i32 0, i32* [[A]], align 4 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK25-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK25-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK25-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK25-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK25-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK25-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK25-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK25-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK25-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK25-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK25-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK25-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK25-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -26092,7 +26092,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK25-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -26169,7 +26169,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26269,7 +26269,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK25-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26325,7 +26325,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26571,7 +26571,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@_Z3bari -// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26579,22 +26579,22 @@ int bar(int n){ // CHECK26-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK26-NEXT: store i32 0, i32* [[A]], align 4 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK26-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK26-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK26-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK26-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK26-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK26-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK26-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK26-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK26-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK26-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK26-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK26-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK26-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK26-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -26603,7 +26603,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK26-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -26680,7 +26680,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26780,7 +26780,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK26-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -26836,7 +26836,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -27080,7 +27080,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@_Z3bari -// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -27088,22 +27088,22 @@ int bar(int n){ // CHECK27-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK27-NEXT: store i32 0, i32* [[A]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK27-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK27-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK27-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK27-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK27-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK27-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK27-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK27-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK27-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK27-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK27-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -27112,7 +27112,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK27-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -27188,7 +27188,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -27288,7 +27288,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK27-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -27344,7 +27344,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -27588,7 +27588,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@_Z3bari -// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -27596,22 +27596,22 @@ int bar(int n){ // CHECK28-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK28-NEXT: store i32 0, i32* [[A]], align 4 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK28-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK28-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK28-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK28-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK28-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK28-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK28-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK28-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK28-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK28-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK28-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK28-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -27620,7 +27620,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK28-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -27696,7 +27696,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -27796,7 +27796,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK28-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -27852,7 +27852,7 @@ int bar(int n){ // // // CHECK29-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -28098,7 +28098,7 @@ int bar(int n){ // // // CHECK29-LABEL: define {{[^@]+}}@_Z3bari -// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -28106,22 +28106,22 @@ int bar(int n){ // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK29-NEXT: store i32 0, i32* [[A]], align 4 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK29-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK29-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -28130,7 +28130,7 @@ int bar(int n){ // // // CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK29-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -28254,7 +28254,7 @@ int bar(int n){ // // // CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -28354,7 +28354,7 @@ int bar(int n){ // // // CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -28410,7 +28410,7 @@ int bar(int n){ // // // CHECK30-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -28656,7 +28656,7 @@ int bar(int n){ // // // CHECK30-LABEL: define {{[^@]+}}@_Z3bari -// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -28664,22 +28664,22 @@ int bar(int n){ // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK30-NEXT: store i32 0, i32* [[A]], align 4 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) +// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) // CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP2]]) +// CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) // CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) +// CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) // CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK30-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) +// CHECK30-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) // CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -28688,7 +28688,7 @@ int bar(int n){ // // // CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK30-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -28812,7 +28812,7 @@ int bar(int n){ // // // CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -28912,7 +28912,7 @@ int bar(int n){ // // // CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -28968,7 +28968,7 @@ int bar(int n){ // // // CHECK31-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -29212,7 +29212,7 @@ int bar(int n){ // // // CHECK31-LABEL: define {{[^@]+}}@_Z3bari -// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -29220,22 +29220,22 @@ int bar(int n){ // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK31-NEXT: store i32 0, i32* [[A]], align 4 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK31-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK31-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -29244,7 +29244,7 @@ int bar(int n){ // // // CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK31-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -29367,7 +29367,7 @@ int bar(int n){ // // // CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -29467,7 +29467,7 @@ int bar(int n){ // // // CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -29523,7 +29523,7 @@ int bar(int n){ // // // CHECK32-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -29767,7 +29767,7 @@ int bar(int n){ // // // CHECK32-LABEL: define {{[^@]+}}@_Z3bari -// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -29775,22 +29775,22 @@ int bar(int n){ // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK32-NEXT: store i32 0, i32* [[A]], align 4 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) +// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) // CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP2]]) +// CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) // CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) +// CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) // CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 // CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK32-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) +// CHECK32-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) // CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 // CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] // CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 @@ -29799,7 +29799,7 @@ int bar(int n){ // // // CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK32-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -29922,7 +29922,7 @@ int bar(int n){ // // // CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -30022,7 +30022,7 @@ int bar(int n){ // // // CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp index 432b2656fc19db78662f805b6caa8e21ae6931aa..89a4e1d65a4f24aedc739b51e6917882bf1d9e25 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp @@ -98,12 +98,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -140,7 +140,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -150,7 +150,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -250,12 +250,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -292,7 +292,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -302,7 +302,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -402,12 +402,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -444,7 +444,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -454,7 +454,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -552,12 +552,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -594,7 +594,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -604,7 +604,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -702,12 +702,12 @@ int main (int argc, char **argv) { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -773,12 +773,12 @@ int main (int argc, char **argv) { // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -844,12 +844,12 @@ int main (int argc, char **argv) { // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -913,12 +913,12 @@ int main (int argc, char **argv) { // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK8-NEXT: ret i32 [[CALL]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -979,7 +979,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1104,7 +1104,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -1113,7 +1113,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -1145,7 +1145,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1311,7 +1311,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -1343,7 +1343,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 -// CHECK9-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -1353,7 +1353,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1449,7 +1449,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1574,7 +1574,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: // CHECK10-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -1583,7 +1583,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -1615,7 +1615,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1781,7 +1781,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -1813,7 +1813,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 -// CHECK10-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -1823,7 +1823,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1919,7 +1919,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2041,7 +2041,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -2050,7 +2050,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -2078,7 +2078,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2240,7 +2240,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -2272,7 +2272,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 -// CHECK11-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -2282,7 +2282,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2376,7 +2376,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2498,7 +2498,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: // CHECK12-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -2507,7 +2507,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -2535,7 +2535,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2697,7 +2697,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -2729,7 +2729,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 -// CHECK12-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -2739,7 +2739,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2833,7 +2833,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2969,7 +2969,7 @@ int main (int argc, char **argv) { // CHECK13-NEXT: br label [[SIMD_IF_END]] // CHECK13: simd.if.end: // CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP28]]) // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) @@ -2978,7 +2978,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -3036,7 +3036,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3172,7 +3172,7 @@ int main (int argc, char **argv) { // CHECK14-NEXT: br label [[SIMD_IF_END]] // CHECK14: simd.if.end: // CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP28]]) // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) @@ -3181,7 +3181,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -3239,7 +3239,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3371,7 +3371,7 @@ int main (int argc, char **argv) { // CHECK15-NEXT: br label [[SIMD_IF_END]] // CHECK15: simd.if.end: // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP26]]) // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP27]]) @@ -3380,7 +3380,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -3436,7 +3436,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3568,7 +3568,7 @@ int main (int argc, char **argv) { // CHECK16-NEXT: br label [[SIMD_IF_END]] // CHECK16: simd.if.end: // CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP26]]) // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP27]]) @@ -3577,7 +3577,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_simd_depend_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_depend_codegen.cpp index 8435b4df14d1597e2088183dcbb709449923728c..5c1bc9f01dee2e1dca9cfc2a2f6fd01ee1566713 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_depend_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_depend_codegen.cpp @@ -216,7 +216,7 @@ int foo(int n) { // CHECK: define internal void [[HVT0:@.+]]() -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias %1) // CHECK: store void (i8*, ...)* null, void (i8*, ...)** % // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0 // CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]], @@ -230,9 +230,9 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* noundef %{{.+}}, i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* %{{.+}}, i[[SZ]] %{{.+}}) -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // OMP45: [[SZT:%.+]] = getelementptr inbounds [2 x i64], [2 x i64]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0 @@ -262,7 +262,7 @@ int foo(int n) { // CHECK: [[END]] // CHECK: ret i32 0 -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2 @@ -278,7 +278,7 @@ int foo(int n) { // CHECK: ret i32 0 -// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] noundef %{{.+}}) +// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] %{{.+}}) // Create stack storage and store argument in there. // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align @@ -286,7 +286,7 @@ int foo(int n) { // CHECK-64: load i32, i32* [[AA_CADDR]], align // CHECK-32: load i32, i32* [[AA_ADDR]], align -// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias noundef %1) +// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias %1) // CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* {{%.*}} to void (i8*, // CHECK: call void [[FN]]( // CHECK: [[BP1_I32:%.+]] = load i32, i32* % diff --git a/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp index 32e9f6b3b6199623b320ea7d35446835b108a072..1a8ace57e55897f7361ae6a5b6a4b47f280297f7 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp @@ -126,12 +126,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -212,7 +212,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -222,7 +222,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -297,7 +297,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -307,7 +307,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -382,7 +382,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -392,7 +392,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -494,12 +494,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -580,7 +580,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -590,7 +590,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -665,7 +665,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -675,7 +675,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -750,7 +750,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -760,7 +760,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -862,12 +862,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -948,7 +948,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -958,7 +958,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1032,7 +1032,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1042,7 +1042,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1116,7 +1116,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1126,7 +1126,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1227,12 +1227,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -1313,7 +1313,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1323,7 +1323,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1397,7 +1397,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l32 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1407,7 +1407,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1481,7 +1481,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1491,7 +1491,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1592,12 +1592,12 @@ int main (int argc, char **argv) { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1717,12 +1717,12 @@ int main (int argc, char **argv) { // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1842,12 +1842,12 @@ int main (int argc, char **argv) { // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1964,12 +1964,12 @@ int main (int argc, char **argv) { // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK8-NEXT: ret i32 [[CALL]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -2083,7 +2083,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2312,7 +2312,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT34]] // CHECK9: omp_offload.cont34: // CHECK9-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP102]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) @@ -2321,7 +2321,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2342,7 +2342,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2449,7 +2449,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2470,7 +2470,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2577,7 +2577,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2606,7 +2606,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2734,7 +2734,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -2809,7 +2809,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -2819,7 +2819,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2893,7 +2893,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -2903,7 +2903,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2977,7 +2977,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -2987,7 +2987,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3085,7 +3085,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3314,7 +3314,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT34]] // CHECK10: omp_offload.cont34: // CHECK10-NEXT: [[TMP102:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP102]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP102]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) @@ -3323,7 +3323,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -3344,7 +3344,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3451,7 +3451,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -3472,7 +3472,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3579,7 +3579,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -3608,7 +3608,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3736,7 +3736,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -3811,7 +3811,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3821,7 +3821,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3895,7 +3895,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3905,7 +3905,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3979,7 +3979,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3989,7 +3989,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4087,7 +4087,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4314,7 +4314,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT31]] // CHECK11: omp_offload.cont31: // CHECK11-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP104]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) @@ -4323,7 +4323,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -4342,7 +4342,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4447,7 +4447,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -4466,7 +4466,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4571,7 +4571,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -4596,7 +4596,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4721,7 +4721,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -4796,7 +4796,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -4806,7 +4806,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4879,7 +4879,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -4889,7 +4889,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4962,7 +4962,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -4972,7 +4972,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5069,7 +5069,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -5296,7 +5296,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT31]] // CHECK12: omp_offload.cont31: // CHECK12-NEXT: [[TMP104:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP104]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP104]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP105:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP105]]) @@ -5305,7 +5305,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -5324,7 +5324,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5429,7 +5429,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -5448,7 +5448,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5553,7 +5553,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -5578,7 +5578,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5703,7 +5703,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -5778,7 +5778,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l76 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -5788,7 +5788,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5861,7 +5861,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l80 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -5871,7 +5871,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5944,7 +5944,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -5954,7 +5954,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6051,7 +6051,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -6244,7 +6244,7 @@ int main (int argc, char **argv) { // CHECK13-NEXT: br label [[SIMD_IF_END68]] // CHECK13: simd.if.end68: // CHECK13-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]]) +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP37]]) // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP38:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP38]]) @@ -6253,7 +6253,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -6364,7 +6364,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -6557,7 +6557,7 @@ int main (int argc, char **argv) { // CHECK14-NEXT: br label [[SIMD_IF_END68]] // CHECK14: simd.if.end68: // CHECK14-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]]) +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP37]]) // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[TMP38:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP38]]) @@ -6566,7 +6566,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -6677,7 +6677,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -6866,7 +6866,7 @@ int main (int argc, char **argv) { // CHECK15-NEXT: br label [[SIMD_IF_END66]] // CHECK15: simd.if.end66: // CHECK15-NEXT: [[TMP36:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP36]]) // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP37:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP37]]) @@ -6875,7 +6875,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -6983,7 +6983,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -7172,7 +7172,7 @@ int main (int argc, char **argv) { // CHECK16-NEXT: br label [[SIMD_IF_END66]] // CHECK16: simd.if.end66: // CHECK16-NEXT: [[TMP36:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP36]]) // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[TMP37:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP37]]) @@ -7181,7 +7181,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp index fb138bd9e037b56a54f07978fd5ab66eb5e6e30f..ce209edf36ac2374dd18fbb5789e191a385ed35d 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp @@ -142,33 +142,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -181,7 +181,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -192,14 +192,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -207,12 +207,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -220,7 +220,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -228,7 +228,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -247,7 +247,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -321,12 +321,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK1-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -358,7 +358,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -406,17 +406,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -482,14 +482,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -497,17 +497,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -515,17 +515,17 @@ int main() { // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -544,14 +544,14 @@ int main() { // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -609,17 +609,17 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP30]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -632,7 +632,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -652,7 +652,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -661,17 +661,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -679,12 +679,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK1-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -711,7 +711,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -759,18 +759,18 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -834,14 +834,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -849,7 +849,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -857,22 +857,22 @@ int main() { // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -884,7 +884,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -900,7 +900,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -919,7 +919,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -946,33 +946,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -985,7 +985,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -996,14 +996,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1011,12 +1011,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1024,7 +1024,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1032,7 +1032,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1051,7 +1051,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -1125,12 +1125,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK2-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -1162,7 +1162,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1210,17 +1210,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1286,14 +1286,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done13: @@ -1301,17 +1301,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1319,17 +1319,17 @@ int main() { // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // @@ -1348,14 +1348,14 @@ int main() { // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1413,17 +1413,17 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP30]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1436,7 +1436,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1456,7 +1456,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1465,17 +1465,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1483,12 +1483,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK2-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -1515,7 +1515,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1563,18 +1563,18 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -1638,14 +1638,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done13: @@ -1653,7 +1653,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1661,22 +1661,22 @@ int main() { // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1688,7 +1688,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1704,7 +1704,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1723,7 +1723,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1750,33 +1750,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1789,7 +1789,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1800,14 +1800,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1815,12 +1815,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1828,7 +1828,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1836,7 +1836,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1855,7 +1855,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -1927,12 +1927,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK3-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -1960,7 +1960,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2006,17 +2006,17 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done3: -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2080,14 +2080,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -2095,17 +2095,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2113,17 +2113,17 @@ int main() { // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -2142,14 +2142,14 @@ int main() { // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2206,17 +2206,17 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP30]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2229,7 +2229,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2249,7 +2249,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2258,17 +2258,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2276,12 +2276,12 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK3-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -2306,7 +2306,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2353,18 +2353,18 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done4: // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -2426,14 +2426,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -2441,7 +2441,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -2449,22 +2449,22 @@ int main() { // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2476,7 +2476,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2492,7 +2492,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -2511,7 +2511,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2538,33 +2538,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2577,7 +2577,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2588,14 +2588,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2603,12 +2603,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -2616,7 +2616,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -2624,7 +2624,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2643,7 +2643,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -2715,12 +2715,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK4-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -2748,7 +2748,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2794,17 +2794,17 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done3: -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2868,14 +2868,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done11: @@ -2883,17 +2883,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2901,17 +2901,17 @@ int main() { // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // @@ -2930,14 +2930,14 @@ int main() { // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2994,17 +2994,17 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP30]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -3017,7 +3017,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -3037,7 +3037,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -3046,17 +3046,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3064,12 +3064,12 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK4-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -3094,7 +3094,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3141,18 +3141,18 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done4: // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -3214,14 +3214,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done12: @@ -3229,7 +3229,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3237,22 +3237,22 @@ int main() { // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3264,7 +3264,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3280,7 +3280,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3299,7 +3299,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3326,42 +3326,42 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3369,12 +3369,12 @@ int main() { // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3382,7 +3382,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -3392,7 +3392,7 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // @@ -3446,7 +3446,7 @@ int main() { // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK5-NEXT: ret i32 [[CALL]] // // @@ -3465,14 +3465,14 @@ int main() { // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -3522,17 +3522,17 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done5: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP16]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3545,7 +3545,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3554,7 +3554,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3571,17 +3571,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3589,22 +3589,22 @@ int main() { // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3616,7 +3616,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3632,7 +3632,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3652,42 +3652,42 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3695,12 +3695,12 @@ int main() { // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3708,7 +3708,7 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: @@ -3718,7 +3718,7 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // @@ -3772,7 +3772,7 @@ int main() { // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK6-NEXT: ret i32 [[CALL]] // // @@ -3791,14 +3791,14 @@ int main() { // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -3848,17 +3848,17 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done5: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP16]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3871,7 +3871,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3880,7 +3880,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3897,17 +3897,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3915,22 +3915,22 @@ int main() { // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3942,7 +3942,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3958,7 +3958,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3978,42 +3978,42 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4021,12 +4021,12 @@ int main() { // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -4034,7 +4034,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -4044,7 +4044,7 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // @@ -4096,7 +4096,7 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK7-NEXT: ret i32 [[CALL]] // // @@ -4115,14 +4115,14 @@ int main() { // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4170,17 +4170,17 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done4: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP16]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4193,7 +4193,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4202,7 +4202,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4219,17 +4219,17 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4237,22 +4237,22 @@ int main() { // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4264,7 +4264,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4280,7 +4280,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4300,42 +4300,42 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4343,12 +4343,12 @@ int main() { // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -4356,7 +4356,7 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done1: @@ -4366,7 +4366,7 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // @@ -4418,7 +4418,7 @@ int main() { // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK8-NEXT: ret i32 [[CALL]] // // @@ -4437,14 +4437,14 @@ int main() { // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4492,17 +4492,17 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done4: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP16]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4515,7 +4515,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4524,7 +4524,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4541,17 +4541,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4559,22 +4559,22 @@ int main() { // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4586,7 +4586,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4602,7 +4602,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4622,33 +4622,33 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4661,7 +4661,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4672,14 +4672,14 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4687,12 +4687,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4700,7 +4700,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -4708,7 +4708,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4727,7 +4727,7 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // @@ -4738,12 +4738,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -4777,7 +4777,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4844,7 +4844,7 @@ int main() { // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -4886,33 +4886,33 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4925,7 +4925,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4936,14 +4936,14 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4951,12 +4951,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4964,7 +4964,7 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: @@ -4972,7 +4972,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4991,7 +4991,7 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // @@ -5002,12 +5002,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 -// CHECK10-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK10-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -5041,7 +5041,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5108,7 +5108,7 @@ int main() { // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -5150,42 +5150,42 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5193,12 +5193,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -5206,7 +5206,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -5216,7 +5216,7 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // @@ -5227,12 +5227,12 @@ int main() { // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: ret i32 0 // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5245,7 +5245,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5254,7 +5254,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5282,42 +5282,42 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5325,12 +5325,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -5338,7 +5338,7 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done1: @@ -5348,7 +5348,7 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // @@ -5359,12 +5359,12 @@ int main() { // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK12-NEXT: ret i32 0 // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5377,7 +5377,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5386,7 +5386,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp index d6b1a6e04f3700c188676a65cd4c74f454d44309..db176f5468882148f56838b7e67edaabc9cc78da 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp @@ -148,12 +148,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -195,7 +195,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -275,7 +275,7 @@ int main() { // CHECK1-NEXT: store i32* [[SVAR8]], i32** [[TMP13]], align 8, !llvm.access.group !4 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store float* [[SFVAR9]], float** [[TMP14]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -334,12 +334,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK2-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -381,7 +381,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -461,7 +461,7 @@ int main() { // CHECK2-NEXT: store i32* [[SVAR8]], i32** [[TMP13]], align 8, !llvm.access.group !4 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store float* [[SFVAR9]], float** [[TMP14]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -520,12 +520,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -555,7 +555,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -634,7 +634,7 @@ int main() { // CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP15]], align 4, !llvm.access.group !5 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP16]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !5 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !5 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -693,12 +693,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l66 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -728,7 +728,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -807,7 +807,7 @@ int main() { // CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP15]], align 4, !llvm.access.group !5 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP16]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !5 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !5 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -866,7 +866,7 @@ int main() { // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // @@ -884,7 +884,7 @@ int main() { // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // @@ -902,7 +902,7 @@ int main() { // CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK7-NEXT: ret i32 0 // // @@ -920,7 +920,7 @@ int main() { // CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK8-NEXT: ret i32 0 // // @@ -945,14 +945,14 @@ int main() { // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1015,7 +1015,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR5:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1023,27 +1023,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK9-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP37]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1051,12 +1051,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK9-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -1091,7 +1091,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1136,13 +1136,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -1239,14 +1239,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 8 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR5]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR5]] // CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done16: @@ -1254,12 +1254,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK9-NEXT: ret void // // @@ -1278,14 +1278,14 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1343,17 +1343,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP30]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1364,7 +1364,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1378,7 +1378,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1387,17 +1387,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1405,12 +1405,12 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -1437,7 +1437,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1478,13 +1478,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -1579,14 +1579,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done14: @@ -1594,17 +1594,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1615,7 +1615,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1629,7 +1629,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1665,14 +1665,14 @@ int main() { // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1735,7 +1735,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR5:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1743,27 +1743,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK10-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP37]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1771,12 +1771,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK10-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -1811,7 +1811,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1856,13 +1856,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -1959,14 +1959,14 @@ int main() { // CHECK10-NEXT: store i32 [[TMP35]], i32* [[CONV1]], align 8 // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR5]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR5]] // CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done16: @@ -1974,12 +1974,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK10-NEXT: ret void // // @@ -1998,14 +1998,14 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -2063,17 +2063,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP30]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2084,7 +2084,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2098,7 +2098,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2107,17 +2107,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2125,12 +2125,12 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 @@ -2157,7 +2157,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2198,13 +2198,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK10-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -2299,14 +2299,14 @@ int main() { // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done14: @@ -2314,17 +2314,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2335,7 +2335,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2349,7 +2349,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2385,14 +2385,14 @@ int main() { // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -2453,7 +2453,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR5:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2461,27 +2461,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK11-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP37]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2489,12 +2489,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK11-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -2525,7 +2525,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2568,13 +2568,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -2669,14 +2669,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP35]], i32* [[SVAR_ADDR]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR5]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -2684,12 +2684,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK11-NEXT: ret void // // @@ -2708,14 +2708,14 @@ int main() { // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2772,17 +2772,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP30]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2793,7 +2793,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2807,7 +2807,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2816,17 +2816,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2834,12 +2834,12 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -2864,7 +2864,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2904,13 +2904,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -3003,14 +3003,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -3018,17 +3018,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3039,7 +3039,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3053,7 +3053,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3089,14 +3089,14 @@ int main() { // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -3157,7 +3157,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR5:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -3165,27 +3165,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR5]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK12-NEXT: [[TMP37:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP37]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3193,12 +3193,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK12-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK12-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -3229,7 +3229,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3272,13 +3272,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -3373,14 +3373,14 @@ int main() { // CHECK12-NEXT: store i32 [[TMP35]], i32* [[SVAR_ADDR]], align 4 // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR5]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done14: @@ -3388,12 +3388,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR5]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK12-NEXT: ret void // // @@ -3412,14 +3412,14 @@ int main() { // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3476,17 +3476,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR5]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP30]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3497,7 +3497,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3511,7 +3511,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3520,17 +3520,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3538,12 +3538,12 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 @@ -3568,7 +3568,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3608,13 +3608,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 @@ -3707,14 +3707,14 @@ int main() { // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i32 4, i1 false) // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR5]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR5]] // CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done13: @@ -3722,17 +3722,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR5]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3743,7 +3743,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3757,7 +3757,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3798,14 +3798,14 @@ int main() { // CHECK13-NEXT: [[I14:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -3820,13 +3820,13 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: // CHECK13-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK13-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -3890,18 +3890,18 @@ int main() { // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 4, i1 false) // CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK13-NEXT: store i32 [[TMP26]], i32* @_ZZ4mainE4svar, align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done13: -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 @@ -3909,27 +3909,27 @@ int main() { // CHECK13: arraydestroy.body16: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S* [ [[TMP28]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST17]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK13: arraydestroy.done20: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP29]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3937,17 +3937,17 @@ int main() { // CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // @@ -3971,14 +3971,14 @@ int main() { // CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -3993,13 +3993,13 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: // CHECK13-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK13-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -4061,14 +4061,14 @@ int main() { // CHECK13-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* // CHECK13-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 4, i1 false) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done13: @@ -4079,17 +4079,17 @@ int main() { // CHECK13: arraydestroy.body15: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi %struct.S.0* [ [[TMP27]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK13: arraydestroy.done19: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP28]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4100,7 +4100,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4109,7 +4109,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4123,17 +4123,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4141,22 +4141,22 @@ int main() { // CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4167,7 +4167,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4181,7 +4181,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4215,14 +4215,14 @@ int main() { // CHECK14-NEXT: [[I14:%.*]] = alloca i32, align 4 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -4237,13 +4237,13 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: // CHECK14-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK14-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -4307,18 +4307,18 @@ int main() { // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 4, i1 false) // CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK14-NEXT: store i32 [[TMP26]], i32* @_ZZ4mainE4svar, align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK14-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK14-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done13: -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 @@ -4326,27 +4326,27 @@ int main() { // CHECK14: arraydestroy.body16: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S* [ [[TMP28]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST17]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK14: arraydestroy.done20: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP29]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4354,17 +4354,17 @@ int main() { // CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // @@ -4388,14 +4388,14 @@ int main() { // CHECK14-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK14-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK14-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -4410,13 +4410,13 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: // CHECK14-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK14-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -4478,14 +4478,14 @@ int main() { // CHECK14-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* // CHECK14-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 4, i1 false) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK14-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done13: @@ -4496,17 +4496,17 @@ int main() { // CHECK14: arraydestroy.body15: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi %struct.S.0* [ [[TMP27]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK14: arraydestroy.done19: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP28]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4517,7 +4517,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4526,7 +4526,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4540,17 +4540,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4558,22 +4558,22 @@ int main() { // CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4584,7 +4584,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4598,7 +4598,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4632,14 +4632,14 @@ int main() { // CHECK15-NEXT: [[I13:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -4654,13 +4654,13 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: // CHECK15-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK15-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -4722,18 +4722,18 @@ int main() { // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 4, i1 false) // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK15-NEXT: store i32 [[TMP26]], i32* @_ZZ4mainE4svar, align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_ARRAYCPY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done12: -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i32 2 @@ -4741,27 +4741,27 @@ int main() { // CHECK15: arraydestroy.body15: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi %struct.S* [ [[TMP28]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST16]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK15: arraydestroy.done19: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP29]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4769,17 +4769,17 @@ int main() { // CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // @@ -4803,14 +4803,14 @@ int main() { // CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4825,13 +4825,13 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: // CHECK15-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK15-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -4891,14 +4891,14 @@ int main() { // CHECK15-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* // CHECK15-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 4, i1 false) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_ARRAYCPY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done12: @@ -4909,17 +4909,17 @@ int main() { // CHECK15: arraydestroy.body14: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST15:%.*]] = phi %struct.S.0* [ [[TMP27]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT16:%.*]], [[ARRAYDESTROY_BODY14]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT16]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST15]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE17:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT16]], [[ARRAY_BEGIN13]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE17]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY14]] // CHECK15: arraydestroy.done18: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP28]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4930,7 +4930,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4939,7 +4939,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4953,17 +4953,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4971,22 +4971,22 @@ int main() { // CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4997,7 +4997,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5011,7 +5011,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5045,14 +5045,14 @@ int main() { // CHECK16-NEXT: [[I13:%.*]] = alloca i32, align 4 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -5067,13 +5067,13 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: // CHECK16-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK16-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -5135,18 +5135,18 @@ int main() { // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 4, i1 false) // CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK16-NEXT: store i32 [[TMP26]], i32* @_ZZ4mainE4svar, align 4 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4:[0-9]+]] // CHECK16-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK16-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_ARRAYCPY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done12: -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i32 2 @@ -5154,27 +5154,27 @@ int main() { // CHECK16: arraydestroy.body15: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi %struct.S* [ [[TMP28]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST16]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK16: arraydestroy.done19: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP29]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5182,17 +5182,17 @@ int main() { // CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // @@ -5216,14 +5216,14 @@ int main() { // CHECK16-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK16-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK16-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -5238,13 +5238,13 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: // CHECK16-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK16-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -5304,14 +5304,14 @@ int main() { // CHECK16-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* // CHECK16-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 4, i1 false) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK16-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_ARRAYCPY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done12: @@ -5322,17 +5322,17 @@ int main() { // CHECK16: arraydestroy.body14: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST15:%.*]] = phi %struct.S.0* [ [[TMP27]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT16:%.*]], [[ARRAYDESTROY_BODY14]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT16]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST15]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE17:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT16]], [[ARRAY_BEGIN13]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE17]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY14]] // CHECK16: arraydestroy.done18: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP28]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5343,7 +5343,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5352,7 +5352,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5366,17 +5366,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5384,22 +5384,22 @@ int main() { // CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5410,7 +5410,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5424,7 +5424,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp index 269dfd5d2509e3f117f9258c8841f47acc3ecb28..55c84fa004e9fc0f03f4240fb14c54ae0325f785 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp @@ -122,33 +122,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -161,7 +161,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -172,14 +172,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -187,12 +187,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -200,7 +200,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -208,7 +208,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -227,7 +227,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -246,7 +246,7 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -258,7 +258,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -285,12 +285,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -356,14 +356,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done7: @@ -381,14 +381,14 @@ int main() { // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -406,27 +406,27 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP4]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -434,7 +434,7 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // @@ -446,7 +446,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -475,12 +475,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -544,14 +544,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -559,17 +559,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -581,7 +581,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -597,7 +597,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -624,33 +624,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -663,7 +663,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -674,14 +674,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -689,12 +689,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -702,7 +702,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -710,7 +710,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -729,7 +729,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -748,7 +748,7 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -760,7 +760,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -787,12 +787,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -858,14 +858,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done7: @@ -883,14 +883,14 @@ int main() { // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -908,27 +908,27 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP4]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -936,7 +936,7 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // @@ -948,7 +948,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -977,12 +977,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1046,14 +1046,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done8: @@ -1061,17 +1061,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1083,7 +1083,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1099,7 +1099,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1126,33 +1126,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1165,7 +1165,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1176,14 +1176,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1191,12 +1191,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1204,7 +1204,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1212,7 +1212,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1231,7 +1231,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -1250,7 +1250,7 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -1262,7 +1262,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1289,12 +1289,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1358,14 +1358,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -1383,14 +1383,14 @@ int main() { // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -1408,27 +1408,27 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP4]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1436,7 +1436,7 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // @@ -1448,7 +1448,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1477,12 +1477,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1544,14 +1544,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -1559,17 +1559,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -1581,7 +1581,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1597,7 +1597,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -1624,33 +1624,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1663,7 +1663,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1674,14 +1674,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1689,12 +1689,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1702,7 +1702,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -1710,7 +1710,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1729,7 +1729,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -1748,7 +1748,7 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // @@ -1760,7 +1760,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1787,12 +1787,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1856,14 +1856,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done6: @@ -1881,14 +1881,14 @@ int main() { // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -1906,27 +1906,27 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP4]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1934,7 +1934,7 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // @@ -1946,7 +1946,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1975,12 +1975,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2042,14 +2042,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done7: @@ -2057,17 +2057,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2079,7 +2079,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2095,7 +2095,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2122,42 +2122,42 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2165,12 +2165,12 @@ int main() { // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2178,7 +2178,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -2188,7 +2188,7 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // @@ -2217,12 +2217,12 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 @@ -2261,18 +2261,18 @@ int main() { // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done6: -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK5-NEXT: ret i32 [[CALL]] // // @@ -2296,14 +2296,14 @@ int main() { // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -2315,12 +2315,12 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: @@ -2357,14 +2357,14 @@ int main() { // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done11: @@ -2375,17 +2375,17 @@ int main() { // CHECK5: arraydestroy.body13: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK5: arraydestroy.done17: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP14]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2398,7 +2398,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2407,7 +2407,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2424,17 +2424,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2442,22 +2442,22 @@ int main() { // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2469,7 +2469,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2485,7 +2485,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2505,42 +2505,42 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2548,12 +2548,12 @@ int main() { // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2561,7 +2561,7 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: @@ -2571,7 +2571,7 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // @@ -2600,12 +2600,12 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 @@ -2644,18 +2644,18 @@ int main() { // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done6: -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK6-NEXT: ret i32 [[CALL]] // // @@ -2679,14 +2679,14 @@ int main() { // CHECK6-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK6-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK6-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -2698,12 +2698,12 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK6-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: @@ -2740,14 +2740,14 @@ int main() { // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done11: @@ -2758,17 +2758,17 @@ int main() { // CHECK6: arraydestroy.body13: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK6: arraydestroy.done17: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP14]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2781,7 +2781,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2790,7 +2790,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2807,17 +2807,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2825,22 +2825,22 @@ int main() { // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2852,7 +2852,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2868,7 +2868,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2888,42 +2888,42 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2931,12 +2931,12 @@ int main() { // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -2944,7 +2944,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -2954,7 +2954,7 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // @@ -2983,12 +2983,12 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 @@ -3025,18 +3025,18 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done5: -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK7-NEXT: ret i32 [[CALL]] // // @@ -3060,14 +3060,14 @@ int main() { // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3079,12 +3079,12 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: @@ -3119,14 +3119,14 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done10: @@ -3137,17 +3137,17 @@ int main() { // CHECK7: arraydestroy.body12: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK7: arraydestroy.done16: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP14]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3160,7 +3160,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3169,7 +3169,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3186,17 +3186,17 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3204,22 +3204,22 @@ int main() { // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3231,7 +3231,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3247,7 +3247,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3267,42 +3267,42 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3310,12 +3310,12 @@ int main() { // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -3323,7 +3323,7 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done1: @@ -3333,7 +3333,7 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // @@ -3362,12 +3362,12 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 @@ -3404,18 +3404,18 @@ int main() { // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done5: -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK8-NEXT: ret i32 [[CALL]] // // @@ -3439,14 +3439,14 @@ int main() { // CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK8-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3458,12 +3458,12 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: @@ -3498,14 +3498,14 @@ int main() { // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done10: @@ -3516,17 +3516,17 @@ int main() { // CHECK8: arraydestroy.body12: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK8: arraydestroy.done16: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP14]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3539,7 +3539,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3548,7 +3548,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3565,17 +3565,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3583,22 +3583,22 @@ int main() { // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3610,7 +3610,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3626,7 +3626,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3646,33 +3646,33 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3685,7 +3685,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3696,14 +3696,14 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3711,12 +3711,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3724,7 +3724,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -3732,7 +3732,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3751,7 +3751,7 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // @@ -3762,7 +3762,7 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // @@ -3774,7 +3774,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3837,7 +3837,7 @@ int main() { // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3879,33 +3879,33 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3918,7 +3918,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3929,14 +3929,14 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3944,12 +3944,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3957,7 +3957,7 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: @@ -3965,7 +3965,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3984,7 +3984,7 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // @@ -3995,7 +3995,7 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // @@ -4007,7 +4007,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4070,7 +4070,7 @@ int main() { // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -4112,42 +4112,42 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4155,12 +4155,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4168,7 +4168,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -4178,7 +4178,7 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // @@ -4189,12 +4189,12 @@ int main() { // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: ret i32 0 // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4207,7 +4207,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4216,7 +4216,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4244,42 +4244,42 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4287,12 +4287,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4300,7 +4300,7 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done1: @@ -4310,7 +4310,7 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // @@ -4321,12 +4321,12 @@ int main() { // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK12-NEXT: ret i32 0 // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4339,7 +4339,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4348,7 +4348,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_simd_reduction_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_reduction_codegen.cpp index 6c1412467018de59d308cf78094a9ea116c5d22b..07b8defc21be4100c579e0b1a4c3a9e04c0cdf23 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_reduction_codegen.cpp @@ -105,12 +105,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(i32* @_ZZ4mainE5sivar) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -120,7 +120,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -219,7 +219,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -276,7 +276,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 @@ -286,7 +286,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -385,7 +385,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -442,12 +442,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(i32* @_ZZ4mainE5sivar) #[[ATTR3:[0-9]+]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -457,7 +457,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -556,7 +556,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -613,7 +613,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 @@ -623,7 +623,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -722,7 +722,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -779,12 +779,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(i32* @_ZZ4mainE5sivar) #[[ATTR3:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 @@ -794,7 +794,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -893,7 +893,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -950,7 +950,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 @@ -960,7 +960,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1059,7 +1059,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1116,12 +1116,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(i32* @_ZZ4mainE5sivar) #[[ATTR3:[0-9]+]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 @@ -1131,7 +1131,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1230,7 +1230,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1287,7 +1287,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 @@ -1297,7 +1297,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1396,7 +1396,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1471,7 +1471,7 @@ int main() { // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK5-NEXT: ret i32 [[CALL]] // // @@ -1571,7 +1571,7 @@ int main() { // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK6-NEXT: ret i32 [[CALL]] // // @@ -1671,7 +1671,7 @@ int main() { // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK7-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK7-NEXT: ret i32 [[CALL]] // // @@ -1771,7 +1771,7 @@ int main() { // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK8-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK8-NEXT: ret i32 [[CALL]] // // @@ -1832,12 +1832,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 -// CHECK9-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -1847,7 +1847,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1904,7 +1904,7 @@ int main() { // CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1950,7 +1950,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1986,12 +1986,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 -// CHECK10-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 @@ -2001,7 +2001,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2058,7 +2058,7 @@ int main() { // CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2104,7 +2104,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2140,7 +2140,7 @@ int main() { // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: ret i32 0 // // @@ -2150,6 +2150,6 @@ int main() { // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK12-NEXT: ret i32 0 // diff --git a/clang/test/OpenMP/target_teams_map_codegen.cpp b/clang/test/OpenMP/target_teams_map_codegen.cpp index 3bc24e48f851e787ad5df05be168744386219e83..41b77fa04fdef4e1c88d1c8612702d711b290d2b 100644 --- a/clang/test/OpenMP/target_teams_map_codegen.cpp +++ b/clang/test/OpenMP/target_teams_map_codegen.cpp @@ -120,7 +120,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -168,7 +168,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 @@ -191,7 +191,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]], i64 noundef [[Y:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]], i64 [[Y:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -243,7 +243,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 @@ -256,7 +256,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -310,7 +310,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -371,7 +371,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 @@ -386,7 +386,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -426,7 +426,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 @@ -441,7 +441,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -481,7 +481,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 -// CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 @@ -496,7 +496,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -590,7 +590,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 -// CHECK1-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 8 // CHECK1-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 8 @@ -603,7 +603,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -685,7 +685,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.17 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -720,7 +720,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 -// CHECK1-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 8 // CHECK1-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 8 @@ -733,7 +733,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..20 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -815,7 +815,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.21 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -931,7 +931,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72 -// CHECK1-SAME: (i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca i128*, align 8 // CHECK1-NEXT: [[Z_ADDR:%.*]] = alloca i128*, align 8 @@ -944,7 +944,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -988,7 +988,7 @@ void mapInt128() { // CHECK1-NEXT: [[TMP11:%.*]] = load i128, i128* [[Z2]], align 16 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* -// CHECK1-NEXT: call void @__atomic_load(i64 noundef 16, i8* noundef [[TMP12]], i8* noundef [[TMP13]], i32 noundef signext 0) +// CHECK1-NEXT: call void @__atomic_load(i64 16, i8* [[TMP12]], i8* [[TMP13]], i32 signext 0) // CHECK1-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK1: atomic_cont: // CHECK1-NEXT: [[TMP14:%.*]] = load i128, i128* [[ATOMIC_TEMP]], align 16 @@ -1000,7 +1000,7 @@ void mapInt128() { // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i128* [[ATOMIC_TEMP3]] to i8* -// CHECK1-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 16, i8* noundef [[TMP17]], i8* noundef [[TMP18]], i8* noundef [[TMP19]], i32 noundef signext 0, i32 noundef signext 0) +// CHECK1-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* [[TMP17]], i8* [[TMP18]], i8* [[TMP19]], i32 signext 0, i32 signext 0) // CHECK1-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK1: atomic_exit: // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], [8 x i32]* @.gomp_critical_user_.reduction.var) @@ -1010,7 +1010,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.25 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1034,7 +1034,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74 -// CHECK1-SAME: (i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca i128*, align 8 // CHECK1-NEXT: [[Z_ADDR:%.*]] = alloca i128*, align 8 @@ -1047,7 +1047,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..28 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1091,7 +1091,7 @@ void mapInt128() { // CHECK1-NEXT: [[TMP11:%.*]] = load i128, i128* [[Z2]], align 16 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* -// CHECK1-NEXT: call void @__atomic_load(i64 noundef 16, i8* noundef [[TMP12]], i8* noundef [[TMP13]], i32 noundef signext 0) +// CHECK1-NEXT: call void @__atomic_load(i64 16, i8* [[TMP12]], i8* [[TMP13]], i32 signext 0) // CHECK1-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK1: atomic_cont: // CHECK1-NEXT: [[TMP14:%.*]] = load i128, i128* [[ATOMIC_TEMP]], align 16 @@ -1103,7 +1103,7 @@ void mapInt128() { // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i128* [[ATOMIC_TEMP3]] to i8* -// CHECK1-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 16, i8* noundef [[TMP17]], i8* noundef [[TMP18]], i8* noundef [[TMP19]], i32 noundef signext 0, i32 noundef signext 0) +// CHECK1-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* [[TMP17]], i8* [[TMP18]], i8* [[TMP19]], i32 signext 0, i32 signext 0) // CHECK1-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK1: atomic_exit: // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], [8 x i32]* @.gomp_critical_user_.reduction.var) @@ -1113,7 +1113,7 @@ void mapInt128() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.29 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1187,7 +1187,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1235,7 +1235,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 @@ -1258,7 +1258,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]], i64 noundef [[Y:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]], i64 [[Y:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1310,7 +1310,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 @@ -1323,7 +1323,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1377,7 +1377,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1438,7 +1438,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 @@ -1453,7 +1453,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1493,7 +1493,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 @@ -1508,7 +1508,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1548,7 +1548,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 -// CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 @@ -1563,7 +1563,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1657,7 +1657,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 -// CHECK2-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 8 // CHECK2-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 8 @@ -1670,7 +1670,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1752,7 +1752,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.17 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1787,7 +1787,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 -// CHECK2-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 8 // CHECK2-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 8 @@ -1800,7 +1800,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..20 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1882,7 +1882,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.21 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1998,7 +1998,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72 -// CHECK2-SAME: (i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[Y_ADDR:%.*]] = alloca i128*, align 8 // CHECK2-NEXT: [[Z_ADDR:%.*]] = alloca i128*, align 8 @@ -2011,7 +2011,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2055,7 +2055,7 @@ void mapInt128() { // CHECK2-NEXT: [[TMP11:%.*]] = load i128, i128* [[Z2]], align 16 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* -// CHECK2-NEXT: call void @__atomic_load(i64 noundef 16, i8* noundef [[TMP12]], i8* noundef [[TMP13]], i32 noundef signext 0) +// CHECK2-NEXT: call void @__atomic_load(i64 16, i8* [[TMP12]], i8* [[TMP13]], i32 signext 0) // CHECK2-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK2: atomic_cont: // CHECK2-NEXT: [[TMP14:%.*]] = load i128, i128* [[ATOMIC_TEMP]], align 16 @@ -2067,7 +2067,7 @@ void mapInt128() { // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* // CHECK2-NEXT: [[TMP19:%.*]] = bitcast i128* [[ATOMIC_TEMP3]] to i8* -// CHECK2-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 16, i8* noundef [[TMP17]], i8* noundef [[TMP18]], i8* noundef [[TMP19]], i32 noundef signext 0, i32 noundef signext 0) +// CHECK2-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* [[TMP17]], i8* [[TMP18]], i8* [[TMP19]], i32 signext 0, i32 signext 0) // CHECK2-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK2: atomic_exit: // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], [8 x i32]* @.gomp_critical_user_.reduction.var) @@ -2077,7 +2077,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.25 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2101,7 +2101,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74 -// CHECK2-SAME: (i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[Y_ADDR:%.*]] = alloca i128*, align 8 // CHECK2-NEXT: [[Z_ADDR:%.*]] = alloca i128*, align 8 @@ -2114,7 +2114,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..28 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2158,7 +2158,7 @@ void mapInt128() { // CHECK2-NEXT: [[TMP11:%.*]] = load i128, i128* [[Z2]], align 16 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* -// CHECK2-NEXT: call void @__atomic_load(i64 noundef 16, i8* noundef [[TMP12]], i8* noundef [[TMP13]], i32 noundef signext 0) +// CHECK2-NEXT: call void @__atomic_load(i64 16, i8* [[TMP12]], i8* [[TMP13]], i32 signext 0) // CHECK2-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK2: atomic_cont: // CHECK2-NEXT: [[TMP14:%.*]] = load i128, i128* [[ATOMIC_TEMP]], align 16 @@ -2170,7 +2170,7 @@ void mapInt128() { // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* // CHECK2-NEXT: [[TMP19:%.*]] = bitcast i128* [[ATOMIC_TEMP3]] to i8* -// CHECK2-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 16, i8* noundef [[TMP17]], i8* noundef [[TMP18]], i8* noundef [[TMP19]], i32 noundef signext 0, i32 noundef signext 0) +// CHECK2-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* [[TMP17]], i8* [[TMP18]], i8* [[TMP19]], i32 signext 0, i32 signext 0) // CHECK2-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK2: atomic_exit: // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], [8 x i32]* @.gomp_critical_user_.reduction.var) @@ -2180,7 +2180,7 @@ void mapInt128() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.29 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2254,7 +2254,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2302,7 +2302,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 4 @@ -2323,7 +2323,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2373,7 +2373,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 4 @@ -2386,7 +2386,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2440,7 +2440,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2501,7 +2501,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 @@ -2515,7 +2515,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2554,7 +2554,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 @@ -2568,7 +2568,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2607,7 +2607,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 -// CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 @@ -2621,7 +2621,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2714,7 +2714,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 -// CHECK3-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 4 // CHECK3-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 4 @@ -2727,7 +2727,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2809,7 +2809,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.17 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2844,7 +2844,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 -// CHECK3-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 4 // CHECK3-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 4 @@ -2857,7 +2857,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..20 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2939,7 +2939,7 @@ void mapInt128() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.21 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -3024,7 +3024,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3072,7 +3072,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 4 @@ -3093,7 +3093,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3143,7 +3143,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 4 @@ -3156,7 +3156,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3210,7 +3210,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -3271,7 +3271,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 @@ -3285,7 +3285,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3324,7 +3324,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 @@ -3338,7 +3338,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3377,7 +3377,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 -// CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 @@ -3391,7 +3391,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3484,7 +3484,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 -// CHECK4-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 4 // CHECK4-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 4 @@ -3497,7 +3497,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3579,7 +3579,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.17 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -3614,7 +3614,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 -// CHECK4-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 4 // CHECK4-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 4 @@ -3627,7 +3627,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..20 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3709,7 +3709,7 @@ void mapInt128() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.21 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -3758,7 +3758,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3770,7 +3770,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 -// CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 @@ -3793,7 +3793,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]], i64 noundef [[Y:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]], i64 [[Y:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3809,7 +3809,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 -// CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 @@ -3822,7 +3822,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3876,7 +3876,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3910,7 +3910,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 -// CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 @@ -3925,7 +3925,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3938,7 +3938,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 -// CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 @@ -3953,7 +3953,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3966,7 +3966,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 -// CHECK5-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 @@ -3981,7 +3981,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3994,7 +3994,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 -// CHECK5-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 8 // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 8 @@ -4007,7 +4007,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4089,7 +4089,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.7 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4124,7 +4124,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 -// CHECK5-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 8 // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 8 @@ -4137,7 +4137,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4219,7 +4219,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4254,7 +4254,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72 -// CHECK5-SAME: (i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca i128*, align 8 // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca i128*, align 8 @@ -4267,7 +4267,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4311,7 +4311,7 @@ void mapInt128() { // CHECK5-NEXT: [[TMP11:%.*]] = load i128, i128* [[Z2]], align 16 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK5-NEXT: [[TMP13:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* -// CHECK5-NEXT: call void @__atomic_load(i64 noundef 16, i8* noundef [[TMP12]], i8* noundef [[TMP13]], i32 noundef signext 0) #[[ATTR6:[0-9]+]] +// CHECK5-NEXT: call void @__atomic_load(i64 16, i8* [[TMP12]], i8* [[TMP13]], i32 signext 0) #[[ATTR6:[0-9]+]] // CHECK5-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK5: atomic_cont: // CHECK5-NEXT: [[TMP14:%.*]] = load i128, i128* [[ATOMIC_TEMP]], align 16 @@ -4323,7 +4323,7 @@ void mapInt128() { // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK5-NEXT: [[TMP18:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* // CHECK5-NEXT: [[TMP19:%.*]] = bitcast i128* [[ATOMIC_TEMP3]] to i8* -// CHECK5-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 16, i8* noundef [[TMP17]], i8* noundef [[TMP18]], i8* noundef [[TMP19]], i32 noundef signext 0, i32 noundef signext 0) #[[ATTR6]] +// CHECK5-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* [[TMP17]], i8* [[TMP18]], i8* [[TMP19]], i32 signext 0, i32 signext 0) #[[ATTR6]] // CHECK5-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK5: atomic_exit: // CHECK5-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], [8 x i32]* @.gomp_critical_user_.reduction.var) @@ -4333,7 +4333,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.11 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4357,7 +4357,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74 -// CHECK5-SAME: (i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca i128*, align 8 // CHECK5-NEXT: [[Z_ADDR:%.*]] = alloca i128*, align 8 @@ -4370,7 +4370,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4414,7 +4414,7 @@ void mapInt128() { // CHECK5-NEXT: [[TMP11:%.*]] = load i128, i128* [[Z2]], align 16 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK5-NEXT: [[TMP13:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* -// CHECK5-NEXT: call void @__atomic_load(i64 noundef 16, i8* noundef [[TMP12]], i8* noundef [[TMP13]], i32 noundef signext 0) #[[ATTR6]] +// CHECK5-NEXT: call void @__atomic_load(i64 16, i8* [[TMP12]], i8* [[TMP13]], i32 signext 0) #[[ATTR6]] // CHECK5-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK5: atomic_cont: // CHECK5-NEXT: [[TMP14:%.*]] = load i128, i128* [[ATOMIC_TEMP]], align 16 @@ -4426,7 +4426,7 @@ void mapInt128() { // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK5-NEXT: [[TMP18:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* // CHECK5-NEXT: [[TMP19:%.*]] = bitcast i128* [[ATOMIC_TEMP3]] to i8* -// CHECK5-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 16, i8* noundef [[TMP17]], i8* noundef [[TMP18]], i8* noundef [[TMP19]], i32 noundef signext 0, i32 noundef signext 0) #[[ATTR6]] +// CHECK5-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* [[TMP17]], i8* [[TMP18]], i8* [[TMP19]], i32 signext 0, i32 signext 0) #[[ATTR6]] // CHECK5-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK5: atomic_exit: // CHECK5-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], [8 x i32]* @.gomp_critical_user_.reduction.var) @@ -4436,7 +4436,7 @@ void mapInt128() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.13 -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4467,7 +4467,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4479,7 +4479,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 -// CHECK6-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 @@ -4502,7 +4502,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]], i64 noundef [[Y:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]], i64 [[Y:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4518,7 +4518,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 -// CHECK6-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 @@ -4531,7 +4531,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4585,7 +4585,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4619,7 +4619,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 -// CHECK6-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 @@ -4634,7 +4634,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4647,7 +4647,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 -// CHECK6-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 @@ -4662,7 +4662,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4675,7 +4675,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 -// CHECK6-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8 @@ -4690,7 +4690,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[X:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4703,7 +4703,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 -// CHECK6-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 8 // CHECK6-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 8 @@ -4716,7 +4716,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4798,7 +4798,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.7 -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4833,7 +4833,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 -// CHECK6-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 8 // CHECK6-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 8 @@ -4846,7 +4846,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4928,7 +4928,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -4963,7 +4963,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72 -// CHECK6-SAME: (i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca i128*, align 8 // CHECK6-NEXT: [[Z_ADDR:%.*]] = alloca i128*, align 8 @@ -4976,7 +4976,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5020,7 +5020,7 @@ void mapInt128() { // CHECK6-NEXT: [[TMP11:%.*]] = load i128, i128* [[Z2]], align 16 // CHECK6-NEXT: [[TMP12:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK6-NEXT: [[TMP13:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* -// CHECK6-NEXT: call void @__atomic_load(i64 noundef 16, i8* noundef [[TMP12]], i8* noundef [[TMP13]], i32 noundef signext 0) #[[ATTR6:[0-9]+]] +// CHECK6-NEXT: call void @__atomic_load(i64 16, i8* [[TMP12]], i8* [[TMP13]], i32 signext 0) #[[ATTR6:[0-9]+]] // CHECK6-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK6: atomic_cont: // CHECK6-NEXT: [[TMP14:%.*]] = load i128, i128* [[ATOMIC_TEMP]], align 16 @@ -5032,7 +5032,7 @@ void mapInt128() { // CHECK6-NEXT: [[TMP17:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK6-NEXT: [[TMP18:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* // CHECK6-NEXT: [[TMP19:%.*]] = bitcast i128* [[ATOMIC_TEMP3]] to i8* -// CHECK6-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 16, i8* noundef [[TMP17]], i8* noundef [[TMP18]], i8* noundef [[TMP19]], i32 noundef signext 0, i32 noundef signext 0) #[[ATTR6]] +// CHECK6-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* [[TMP17]], i8* [[TMP18]], i8* [[TMP19]], i32 signext 0, i32 signext 0) #[[ATTR6]] // CHECK6-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK6: atomic_exit: // CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], [8 x i32]* @.gomp_critical_user_.reduction.var) @@ -5042,7 +5042,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.11 -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -5066,7 +5066,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74 -// CHECK6-SAME: (i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca i128*, align 8 // CHECK6-NEXT: [[Z_ADDR:%.*]] = alloca i128*, align 8 @@ -5079,7 +5079,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* noundef nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i128* nonnull align 16 dereferenceable(16) [[Y:%.*]], i128* nonnull align 16 dereferenceable(16) [[Z:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5123,7 +5123,7 @@ void mapInt128() { // CHECK6-NEXT: [[TMP11:%.*]] = load i128, i128* [[Z2]], align 16 // CHECK6-NEXT: [[TMP12:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK6-NEXT: [[TMP13:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* -// CHECK6-NEXT: call void @__atomic_load(i64 noundef 16, i8* noundef [[TMP12]], i8* noundef [[TMP13]], i32 noundef signext 0) #[[ATTR6]] +// CHECK6-NEXT: call void @__atomic_load(i64 16, i8* [[TMP12]], i8* [[TMP13]], i32 signext 0) #[[ATTR6]] // CHECK6-NEXT: br label [[ATOMIC_CONT:%.*]] // CHECK6: atomic_cont: // CHECK6-NEXT: [[TMP14:%.*]] = load i128, i128* [[ATOMIC_TEMP]], align 16 @@ -5135,7 +5135,7 @@ void mapInt128() { // CHECK6-NEXT: [[TMP17:%.*]] = bitcast i128* [[TMP1]] to i8* // CHECK6-NEXT: [[TMP18:%.*]] = bitcast i128* [[ATOMIC_TEMP]] to i8* // CHECK6-NEXT: [[TMP19:%.*]] = bitcast i128* [[ATOMIC_TEMP3]] to i8* -// CHECK6-NEXT: [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 16, i8* noundef [[TMP17]], i8* noundef [[TMP18]], i8* noundef [[TMP19]], i32 noundef signext 0, i32 noundef signext 0) #[[ATTR6]] +// CHECK6-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* [[TMP17]], i8* [[TMP18]], i8* [[TMP19]], i32 signext 0, i32 signext 0) #[[ATTR6]] // CHECK6-NEXT: br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]] // CHECK6: atomic_exit: // CHECK6-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], [8 x i32]* @.gomp_critical_user_.reduction.var) @@ -5145,7 +5145,7 @@ void mapInt128() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.13 -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -5176,7 +5176,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5188,7 +5188,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 -// CHECK7-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 4 @@ -5209,7 +5209,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5223,7 +5223,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 -// CHECK7-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 4 @@ -5236,7 +5236,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5290,7 +5290,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK7-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK7-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -5324,7 +5324,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 -// CHECK7-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 @@ -5338,7 +5338,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5350,7 +5350,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 -// CHECK7-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 @@ -5364,7 +5364,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5376,7 +5376,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 -// CHECK7-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 @@ -5390,7 +5390,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5402,7 +5402,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 -// CHECK7-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 4 // CHECK7-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 4 @@ -5415,7 +5415,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5497,7 +5497,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.7 -// CHECK7-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -5532,7 +5532,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 -// CHECK7-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 4 // CHECK7-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 4 @@ -5545,7 +5545,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5627,7 +5627,7 @@ void mapInt128() { // // // CHECK7-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 -// CHECK7-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK7-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -5669,7 +5669,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5681,7 +5681,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33 -// CHECK8-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 4 @@ -5702,7 +5702,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5716,7 +5716,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39 -// CHECK8-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 4 @@ -5729,7 +5729,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5783,7 +5783,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK8-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK8-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK8-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -5817,7 +5817,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45 -// CHECK8-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 @@ -5831,7 +5831,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5843,7 +5843,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51 -// CHECK8-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 @@ -5857,7 +5857,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5869,7 +5869,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57 -// CHECK8-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[X_ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4 @@ -5883,7 +5883,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[X:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[X:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5895,7 +5895,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63 -// CHECK8-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 4 // CHECK8-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 4 @@ -5908,7 +5908,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5990,7 +5990,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.7 -// CHECK8-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK8-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -6025,7 +6025,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65 -// CHECK8-SAME: ([88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: ([88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[Y_ADDR:%.*]] = alloca [88 x i32]*, align 4 // CHECK8-NEXT: [[Z_ADDR:%.*]] = alloca [99 x i32]*, align 4 @@ -6038,7 +6038,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [88 x i32]* noundef nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* noundef nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [88 x i32]* nonnull align 4 dereferenceable(352) [[Y:%.*]], [99 x i32]* nonnull align 4 dereferenceable(396) [[Z:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6120,7 +6120,7 @@ void mapInt128() { // // // CHECK8-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 -// CHECK8-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK8-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR2]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK8-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 diff --git a/clang/test/OpenMP/target_teams_num_teams_codegen.cpp b/clang/test/OpenMP/target_teams_num_teams_codegen.cpp index b4f9f50b3ad3018239ab3564a5fe22e0f6763fbb..5122779d1ddb6326aee5c50ac00b501b1cfdccac 100644 --- a/clang/test/OpenMP/target_teams_num_teams_codegen.cpp +++ b/clang/test/OpenMP/target_teams_num_teams_codegen.cpp @@ -175,7 +175,7 @@ int bar(int n){ #endif // CHECK1-LABEL: define {{[^@]+}}@_Z3bari -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -183,17 +183,17 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -202,7 +202,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -292,7 +292,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -361,7 +361,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -437,7 +437,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -461,7 +461,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -482,7 +482,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -494,7 +494,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -509,7 +509,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK1-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -522,7 +522,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -532,7 +532,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK1-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -545,7 +545,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -564,7 +564,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -574,7 +574,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -604,7 +604,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -632,7 +632,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3bari -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -640,17 +640,17 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -659,7 +659,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -749,7 +749,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -818,7 +818,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -894,7 +894,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -918,7 +918,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -939,7 +939,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -951,7 +951,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -966,7 +966,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK2-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -979,7 +979,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -989,7 +989,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK2-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1002,7 +1002,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1021,7 +1021,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1031,7 +1031,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1061,7 +1061,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1089,7 +1089,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3bari -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1097,17 +1097,17 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -1116,7 +1116,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1204,7 +1204,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -1271,7 +1271,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1346,7 +1346,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1367,7 +1367,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1387,7 +1387,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1399,7 +1399,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1414,7 +1414,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK3-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1426,7 +1426,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1436,7 +1436,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK3-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1448,7 +1448,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1467,7 +1467,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1477,7 +1477,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1505,7 +1505,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1532,7 +1532,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3bari -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1540,17 +1540,17 @@ int bar(int n){ // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -1559,7 +1559,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1647,7 +1647,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -1714,7 +1714,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1789,7 +1789,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1810,7 +1810,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1830,7 +1830,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1842,7 +1842,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1857,7 +1857,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK4-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1869,7 +1869,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1879,7 +1879,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK4-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1891,7 +1891,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1910,7 +1910,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1920,7 +1920,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1948,7 +1948,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1975,7 +1975,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -1988,7 +1988,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1998,7 +1998,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2011,7 +2011,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2021,7 +2021,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2045,7 +2045,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2066,7 +2066,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2078,7 +2078,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2102,7 +2102,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2112,7 +2112,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2142,7 +2142,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2163,7 +2163,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK10-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -2176,7 +2176,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2186,7 +2186,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK10-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2199,7 +2199,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2209,7 +2209,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2233,7 +2233,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2254,7 +2254,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2266,7 +2266,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2290,7 +2290,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2300,7 +2300,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2330,7 +2330,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2351,7 +2351,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -2363,7 +2363,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2373,7 +2373,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2385,7 +2385,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2395,7 +2395,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2416,7 +2416,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2436,7 +2436,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2448,7 +2448,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2472,7 +2472,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2482,7 +2482,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2510,7 +2510,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2530,7 +2530,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK12-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -2542,7 +2542,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2552,7 +2552,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK12-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2564,7 +2564,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2574,7 +2574,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2595,7 +2595,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2615,7 +2615,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2627,7 +2627,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2651,7 +2651,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2661,7 +2661,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2689,7 +2689,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2709,7 +2709,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2717,17 +2717,17 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -2736,7 +2736,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -2826,7 +2826,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -2895,7 +2895,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2971,7 +2971,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2995,7 +2995,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3016,7 +3016,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3028,7 +3028,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3043,7 +3043,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK17-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3056,7 +3056,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3066,7 +3066,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK17-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3079,7 +3079,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3098,7 +3098,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3108,7 +3108,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3138,7 +3138,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3166,7 +3166,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3174,17 +3174,17 @@ int bar(int n){ // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -3193,7 +3193,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -3283,7 +3283,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -3352,7 +3352,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3428,7 +3428,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3452,7 +3452,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3473,7 +3473,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3485,7 +3485,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3500,7 +3500,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK18-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3513,7 +3513,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3523,7 +3523,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK18-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3536,7 +3536,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3555,7 +3555,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3565,7 +3565,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3595,7 +3595,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3623,7 +3623,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3631,17 +3631,17 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -3650,7 +3650,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -3738,7 +3738,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -3805,7 +3805,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3880,7 +3880,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3901,7 +3901,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3921,7 +3921,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3933,7 +3933,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3948,7 +3948,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK19-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3960,7 +3960,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3970,7 +3970,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK19-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3982,7 +3982,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4001,7 +4001,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4011,7 +4011,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4039,7 +4039,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4066,7 +4066,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4074,17 +4074,17 @@ int bar(int n){ // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -4093,7 +4093,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -4181,7 +4181,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -4248,7 +4248,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4323,7 +4323,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4344,7 +4344,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4364,7 +4364,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4376,7 +4376,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4391,7 +4391,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK20-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4403,7 +4403,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4413,7 +4413,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK20-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4425,7 +4425,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4444,7 +4444,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4454,7 +4454,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4482,7 +4482,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4509,7 +4509,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK25-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -4522,7 +4522,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4532,7 +4532,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK25-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4545,7 +4545,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4555,7 +4555,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4579,7 +4579,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4600,7 +4600,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4612,7 +4612,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4636,7 +4636,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4646,7 +4646,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4676,7 +4676,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4697,7 +4697,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK26-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -4710,7 +4710,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4720,7 +4720,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK26-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4733,7 +4733,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4743,7 +4743,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4767,7 +4767,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4788,7 +4788,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4800,7 +4800,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4824,7 +4824,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4834,7 +4834,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4864,7 +4864,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4885,7 +4885,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK27-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -4897,7 +4897,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4907,7 +4907,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK27-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4919,7 +4919,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4929,7 +4929,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4950,7 +4950,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4970,7 +4970,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4982,7 +4982,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5006,7 +5006,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5016,7 +5016,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5044,7 +5044,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5064,7 +5064,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK28-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) @@ -5076,7 +5076,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5086,7 +5086,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK28-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -5098,7 +5098,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5108,7 +5108,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5129,7 +5129,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5149,7 +5149,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -5161,7 +5161,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5185,7 +5185,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5195,7 +5195,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5223,7 +5223,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5241,3 +5241,4 @@ int bar(int n){ // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp b/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp index 61e559558e93481252cd2e18a2f99b593472bc38..51663d0feb220adfb72b73c2bc2679fb4bb8db47 100644 --- a/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp +++ b/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp @@ -175,7 +175,7 @@ int bar(int n){ #endif // CHECK1-LABEL: define {{[^@]+}}@_Z3bari -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -183,17 +183,17 @@ int bar(int n){ // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -202,7 +202,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -292,7 +292,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -379,7 +379,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -455,7 +455,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -479,7 +479,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -500,7 +500,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -512,7 +512,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -527,7 +527,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK1-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 @@ -544,7 +544,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -554,7 +554,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK1-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -567,7 +567,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -586,7 +586,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -596,7 +596,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -626,7 +626,7 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -654,7 +654,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z3bari -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -662,17 +662,17 @@ int bar(int n){ // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -681,7 +681,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -771,7 +771,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -858,7 +858,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -934,7 +934,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -958,7 +958,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -979,7 +979,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -991,7 +991,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1006,7 +1006,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK2-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 @@ -1023,7 +1023,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1033,7 +1033,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK2-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1046,7 +1046,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1065,7 +1065,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1075,7 +1075,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -1105,7 +1105,7 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1133,7 +1133,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z3bari -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1141,17 +1141,17 @@ int bar(int n){ // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -1160,7 +1160,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1248,7 +1248,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -1332,7 +1332,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1407,7 +1407,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1428,7 +1428,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1448,7 +1448,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1460,7 +1460,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1475,7 +1475,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK3-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 @@ -1490,7 +1490,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1500,7 +1500,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK3-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1512,7 +1512,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1531,7 +1531,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1541,7 +1541,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1569,7 +1569,7 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1596,7 +1596,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z3bari -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1604,17 +1604,17 @@ int bar(int n){ // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK4-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -1623,7 +1623,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -1711,7 +1711,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -1795,7 +1795,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1870,7 +1870,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -1891,7 +1891,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1911,7 +1911,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1923,7 +1923,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1938,7 +1938,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK4-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 @@ -1953,7 +1953,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1963,7 +1963,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK4-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1975,7 +1975,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1994,7 +1994,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2004,7 +2004,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2032,7 +2032,7 @@ int bar(int n){ // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2059,7 +2059,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 @@ -2076,7 +2076,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2086,7 +2086,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK9-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2099,7 +2099,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2109,7 +2109,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2133,7 +2133,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2154,7 +2154,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2166,7 +2166,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2190,7 +2190,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2200,7 +2200,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2230,7 +2230,7 @@ int bar(int n){ // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2251,7 +2251,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK10-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 @@ -2268,7 +2268,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2278,7 +2278,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK10-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2291,7 +2291,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2301,7 +2301,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2325,7 +2325,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2346,7 +2346,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2358,7 +2358,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2382,7 +2382,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2392,7 +2392,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -2422,7 +2422,7 @@ int bar(int n){ // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2443,7 +2443,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 @@ -2458,7 +2458,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2468,7 +2468,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK11-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2480,7 +2480,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2490,7 +2490,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2511,7 +2511,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2531,7 +2531,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2543,7 +2543,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2567,7 +2567,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2577,7 +2577,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2605,7 +2605,7 @@ int bar(int n){ // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2625,7 +2625,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK12-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 @@ -2640,7 +2640,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2650,7 +2650,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK12-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2662,7 +2662,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2672,7 +2672,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2693,7 +2693,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2713,7 +2713,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2725,7 +2725,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2749,7 +2749,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2759,7 +2759,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -2787,7 +2787,7 @@ int bar(int n){ // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2807,7 +2807,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z3bari -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2815,17 +2815,17 @@ int bar(int n){ // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -2834,7 +2834,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -2924,7 +2924,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -3011,7 +3011,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3087,7 +3087,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3111,7 +3111,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3132,7 +3132,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK17-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3144,7 +3144,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3159,7 +3159,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK17-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 @@ -3176,7 +3176,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3186,7 +3186,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK17-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3199,7 +3199,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3218,7 +3218,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3228,7 +3228,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3258,7 +3258,7 @@ int bar(int n){ // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3286,7 +3286,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z3bari -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3294,17 +3294,17 @@ int bar(int n){ // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef signext [[TMP0]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP2]]) +// CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP4]]) +// CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -3313,7 +3313,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -3403,7 +3403,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -3490,7 +3490,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3566,7 +3566,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3590,7 +3590,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3611,7 +3611,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK18-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3623,7 +3623,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3638,7 +3638,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK18-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 @@ -3655,7 +3655,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3665,7 +3665,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK18-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -3678,7 +3678,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3697,7 +3697,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3707,7 +3707,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3737,7 +3737,7 @@ int bar(int n){ // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3765,7 +3765,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z3bari -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3773,17 +3773,17 @@ int bar(int n){ // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -3792,7 +3792,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -3880,7 +3880,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -3964,7 +3964,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4039,7 +4039,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4060,7 +4060,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4080,7 +4080,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK19-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4092,7 +4092,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4107,7 +4107,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK19-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 @@ -4122,7 +4122,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4132,7 +4132,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK19-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4144,7 +4144,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4163,7 +4163,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4173,7 +4173,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK19-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4201,7 +4201,7 @@ int bar(int n){ // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4228,7 +4228,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z3bari -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4236,17 +4236,17 @@ int bar(int n){ // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef [[S]], i32 noundef [[TMP0]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP2]]) +// CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP4]]) +// CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 @@ -4255,7 +4255,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -4343,7 +4343,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 @@ -4427,7 +4427,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i -// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { +// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4502,7 +4502,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4523,7 +4523,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4543,7 +4543,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK20-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4555,7 +4555,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4570,7 +4570,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK20-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 @@ -4585,7 +4585,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4595,7 +4595,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK20-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4607,7 +4607,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4626,7 +4626,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4636,7 +4636,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK20-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4664,7 +4664,7 @@ int bar(int n){ // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4691,7 +4691,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK25-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 @@ -4708,7 +4708,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4718,7 +4718,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK25-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4731,7 +4731,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4741,7 +4741,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4765,7 +4765,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4786,7 +4786,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK25-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4798,7 +4798,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4822,7 +4822,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4832,7 +4832,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4862,7 +4862,7 @@ int bar(int n){ // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4883,7 +4883,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK26-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 @@ -4900,7 +4900,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4910,7 +4910,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK26-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4923,7 +4923,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4933,7 +4933,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -4957,7 +4957,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4978,7 +4978,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK26-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -4990,7 +4990,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5014,7 +5014,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5024,7 +5024,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -5054,7 +5054,7 @@ int bar(int n){ // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5075,7 +5075,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK27-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 @@ -5090,7 +5090,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5100,7 +5100,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK27-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -5112,7 +5112,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5122,7 +5122,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5143,7 +5143,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5163,7 +5163,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK27-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -5175,7 +5175,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5199,7 +5199,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5209,7 +5209,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5237,7 +5237,7 @@ int bar(int n){ // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5257,7 +5257,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 -// CHECK28-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 @@ -5272,7 +5272,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5282,7 +5282,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 -// CHECK28-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -5294,7 +5294,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5304,7 +5304,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 -// CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5325,7 +5325,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5345,7 +5345,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 -// CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK28-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -5357,7 +5357,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5381,7 +5381,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5391,7 +5391,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 -// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -5419,7 +5419,7 @@ int bar(int n){ // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5437,3 +5437,4 @@ int bar(int n){ // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 // CHECK28-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/target_update_codegen.cpp b/clang/test/OpenMP/target_update_codegen.cpp index 5c47dc42bc58a18bc64d7e522712c9cebeb875d7..9f76da7c67a28cc57880e58ff7c9b390c3b0a9be 100644 --- a/clang/test/OpenMP/target_update_codegen.cpp +++ b/clang/test/OpenMP/target_update_codegen.cpp @@ -162,7 +162,7 @@ void foo(int arg) { {++arg;} } -// CK1: define internal {{.*}}i32 [[OMP_TASK_ENTRY]](i32 {{.*}}%{{[^,]+}}, [[KMP_TASK_T_WITH_PRIVATES]]* noalias noundef %{{[^,]+}}) +// CK1: define internal {{.*}}i32 [[OMP_TASK_ENTRY]](i32 {{.*}}%{{[^,]+}}, [[KMP_TASK_T_WITH_PRIVATES]]* noalias %{{[^,]+}}) // CK1-DAG: call void @__tgt_target_data_update_nowait_mapper(%struct.ident_t* @{{.+}}, i64 %{{[^,]+}}, i32 1, i8** [[BP:%[^,]+]], i8** [[P:%[^,]+]], i64* [[SZ:%[^,]+]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* [[MTYPE00]], i32 0, i32 0), i8** null, i8** null) // CK1-DAG: [[BP]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[BPADDR:%[^,]+]], i[[sz]] 0, i[[sz]] 0 // CK1-DAG: [[P]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[PADDR:%[^,]+]], i[[sz]] 0, i[[sz]] 0 diff --git a/clang/test/OpenMP/target_update_depend_codegen.cpp b/clang/test/OpenMP/target_update_depend_codegen.cpp index b3272e5de92c4e92ef949415697640fceb8baacc..f80536f4f28d31361978915ccb6a5d3a0447cd1f 100644 --- a/clang/test/OpenMP/target_update_depend_codegen.cpp +++ b/clang/test/OpenMP/target_update_depend_codegen.cpp @@ -372,7 +372,7 @@ void foo(int arg) { {++arg;} } -// CK1: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, %struct.kmp_task_t_with_privates* noalias noundef %1) +// CK1: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, %struct.kmp_task_t_with_privates* noalias %1) // CK1-DAG: call void @__tgt_target_data_update_nowait_mapper(%struct.ident_t* @{{.+}}, i64 [[DEV:%[^,]+]], i32 1, i8** [[GEPBP:%.+]], i8** [[GEPP:%.+]], i64* [[GEPS:%.+]], {{.+}}getelementptr {{.+}}[1 x i{{.+}}]* [[MTYPE00]]{{.+}}, i8** null) // CK1-DAG: [[DEV]] = sext i32 [[DEVi32:%[^,]+]] to i64 // CK1-DAG: [[DEVi32]] = load i32, i32* %{{[^,]+}}, @@ -387,7 +387,7 @@ void foo(int arg) { // CK1: ret i32 0 // CK1: } -// CK1: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias noundef %1) +// CK1: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias %1) // CK1-DAG: call void @__tgt_target_data_update_mapper(%struct.ident_t* @{{.+}}, i64 4, i32 1, i8** [[GEPBP:%.+]], i8** [[GEPP:%.+]], i64* [[GEPS:%.+]], {{.+}}getelementptr {{.+}}[1 x i{{.+}}]* [[MTYPE02]]{{.+}}, i8** null) // CK1-DAG: [[GEPBP]] = getelementptr inbounds {{.+}}[[BP:%[^,]+]] // CK1-DAG: [[GEPP]] = getelementptr inbounds {{.+}}[[P:%[^,]+]] @@ -400,7 +400,7 @@ void foo(int arg) { // CK1: ret i32 0 // CK1: } -// CK1: define internal{{.*}} i32 [[TASK_ENTRY3]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias noundef %1) +// CK1: define internal{{.*}} i32 [[TASK_ENTRY3]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias %1) // CK1-DAG: call void @__tgt_target_data_update_mapper(%struct.ident_t* @{{.+}}, i64 -1, i32 1, i8** [[GEPBP:%.+]], i8** [[GEPP:%.+]], i64* [[GEPS:%.+]], {{.+}}getelementptr {{.+}}[1 x i{{.+}}]* [[MTYPE03]]{{.+}}, i8** null) // CK1-DAG: [[GEPBP]] = getelementptr inbounds {{.+}}[[BP:%[^,]+]] // CK1-DAG: [[GEPP]] = getelementptr inbounds {{.+}}[[P:%[^,]+]] @@ -414,7 +414,7 @@ void foo(int arg) { // CK1: ret i32 0 // CK1: } -// CK1: define internal{{.*}} i32 [[TASK_ENTRY4]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias noundef %1) +// CK1: define internal{{.*}} i32 [[TASK_ENTRY4]](i32{{.*}}, %struct.kmp_task_t_with_privates{{.+}}* noalias %1) // CK1-DAG: call void @__tgt_target_data_update_mapper(%struct.ident_t* @{{.+}}, i64 -1, i32 2, i8** [[GEPBP:%.+]], i8** [[GEPP:%.+]], i64* [[GEPS:%.+]], {{.+}}getelementptr {{.+}}[2 x i{{.+}}]* [[MTYPE04]]{{.+}}, i8** null) // CK1-DAG: [[GEPBP]] = getelementptr inbounds {{.+}}[[BP:%[^,]+]] // CK1-DAG: [[GEPP]] = getelementptr inbounds {{.+}}[[P:%[^,]+]] diff --git a/clang/test/OpenMP/task_codegen.cpp b/clang/test/OpenMP/task_codegen.cpp index 72df2e7a8a860a8197988b8c730b4c60287571b7..26ab2add1967a26e9acf903c9889f4f94d71723c 100644 --- a/clang/test/OpenMP/task_codegen.cpp +++ b/clang/test/OpenMP/task_codegen.cpp @@ -186,7 +186,7 @@ void xxxx() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] @@ -443,7 +443,7 @@ void xxxx() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP170]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN32]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE33:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done33: @@ -452,17 +452,17 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -508,7 +508,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..2 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -549,7 +549,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..4 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -612,7 +612,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..6 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -672,7 +672,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..8 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -732,7 +732,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..10 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -768,7 +768,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..12 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -804,7 +804,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..14 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -840,7 +840,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..16 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -879,7 +879,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -893,7 +893,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..19 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.18* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.18* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -938,17 +938,17 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map..20 -// CHECK1-SAME: (%struct..kmp_privates.t.20* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]], %struct.S** noalias noundef [[TMP2:%.*]], %struct.S*** noalias noundef [[TMP3:%.*]]) #[[ATTR7]] { +// CHECK1-SAME: (%struct..kmp_privates.t.20* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]], %struct.S** noalias [[TMP2:%.*]], %struct.S*** noalias [[TMP3:%.*]]) #[[ATTR7]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t.20*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -972,7 +972,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..21 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1039,7 +1039,7 @@ void xxxx() { // CHECK1-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]], i8* [[TMP24]]) #[[ATTR4]] // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]] // CHECK1: .untied.jmp.2.i: -// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[TMP17]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112 // CHECK1-NEXT: [[DOTS2__VOID_ADDR_I:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP26]], i64 4, i8* inttoptr (i64 7 to i8*)) #[[ATTR4]] // CHECK1-NEXT: [[DOTS2__ADDR_I:%.*]] = bitcast i8* [[DOTS2__VOID_ADDR_I]] to %struct.S* @@ -1051,7 +1051,7 @@ void xxxx() { // CHECK1-NEXT: [[TMP30:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]], i8* [[TMP29]]) #[[ATTR4]] // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK1: .untied.jmp.3.i: -// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[TMP19]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP19]]) #[[ATTR4]] // CHECK1-NEXT: [[A_I:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP19]], i32 0, i32 0 // CHECK1-NEXT: store i32 0, i32* [[A_I]], align 4 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112 @@ -1080,11 +1080,11 @@ void xxxx() { // CHECK1-NEXT: [[TMP49:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP47]], i8* [[TMP48]]) #[[ATTR4]] // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK1: .untied.jmp.7.i: -// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[REF_TMP_I]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP50:%.*]] = bitcast %struct.S* [[TMP17]] to i8* // CHECK1-NEXT: [[TMP51:%.*]] = bitcast %struct.S* [[REF_TMP_I]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i64 4, i1 false) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP_I]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] // CHECK1-NEXT: [[A9_I:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP19]], i32 0, i32 0 // CHECK1-NEXT: store i32 10, i32* [[A9_I]], align 4 // CHECK1-NEXT: [[TMP52:%.*]] = load i32, i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112 @@ -1096,11 +1096,11 @@ void xxxx() { // CHECK1-NEXT: [[TMP57:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP55]], i8* [[TMP56]]) #[[ATTR4]] // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK1: .untied.jmp.10.i: -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[TMP19]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP19]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112 // CHECK1-NEXT: [[TMP59:%.*]] = bitcast %struct.S* [[TMP19]] to i8* // CHECK1-NEXT: call void @__kmpc_free(i32 [[TMP58]], i8* [[TMP59]], i8* inttoptr (i64 7 to i8*)) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[TMP17]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]]) #[[ATTR4]] // CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112 // CHECK1-NEXT: br label [[CLEANUP_I]] // CHECK1: cleanup.i: @@ -1111,7 +1111,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1122,7 +1122,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1133,32 +1133,32 @@ void xxxx() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR7]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN2S1C1Ev(%struct.S1* noundef @s1) +// CHECK1-NEXT: call void @_ZN2S1C1Ev(%struct.S1* nonnull align 4 dereferenceable(4) @s1) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1C1Ev -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2S1C2Ev(%struct.S1* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN2S1C2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1C2Ev -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2S18taskinitEv(%struct.S1* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN2S18taskinitEv(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S18taskinitEv -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR8:[0-9]+]] align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR8:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_21:%.*]], align 8 @@ -1179,7 +1179,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..23 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.22* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.22* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1233,7 +1233,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR9:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR9:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1272,7 +1272,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map..26 -// CHECK1-SAME: (%struct..kmp_privates.t.25* noalias noundef [[TMP0:%.*]], double** noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK1-SAME: (%struct..kmp_privates.t.25* noalias [[TMP0:%.*]], double** noalias [[TMP1:%.*]]) #[[ATTR7]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t.25*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca double**, align 8 @@ -1286,7 +1286,7 @@ void xxxx() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..27 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.24* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.24* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1378,7 +1378,7 @@ void xxxx() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] @@ -1635,7 +1635,7 @@ void xxxx() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP170]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN32]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE33:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done33: @@ -1644,17 +1644,17 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1700,7 +1700,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..2 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1741,7 +1741,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..4 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1804,7 +1804,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..6 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1864,7 +1864,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..8 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1924,7 +1924,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..10 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1960,7 +1960,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..12 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1996,7 +1996,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..14 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2032,7 +2032,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..16 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2071,7 +2071,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -2085,7 +2085,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..19 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.18* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.18* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2130,17 +2130,17 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map..20 -// CHECK2-SAME: (%struct..kmp_privates.t.20* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]], %struct.S** noalias noundef [[TMP2:%.*]], %struct.S*** noalias noundef [[TMP3:%.*]]) #[[ATTR7]] { +// CHECK2-SAME: (%struct..kmp_privates.t.20* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]], %struct.S** noalias [[TMP2:%.*]], %struct.S*** noalias [[TMP3:%.*]]) #[[ATTR7]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t.20*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -2164,7 +2164,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..21 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2231,7 +2231,7 @@ void xxxx() { // CHECK2-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]], i8* [[TMP24]]) #[[ATTR4]] // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]] // CHECK2: .untied.jmp.2.i: -// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[TMP17]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112 // CHECK2-NEXT: [[DOTS2__VOID_ADDR_I:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP26]], i64 4, i8* inttoptr (i64 7 to i8*)) #[[ATTR4]] // CHECK2-NEXT: [[DOTS2__ADDR_I:%.*]] = bitcast i8* [[DOTS2__VOID_ADDR_I]] to %struct.S* @@ -2243,7 +2243,7 @@ void xxxx() { // CHECK2-NEXT: [[TMP30:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]], i8* [[TMP29]]) #[[ATTR4]] // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK2: .untied.jmp.3.i: -// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[TMP19]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP19]]) #[[ATTR4]] // CHECK2-NEXT: [[A_I:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP19]], i32 0, i32 0 // CHECK2-NEXT: store i32 0, i32* [[A_I]], align 4 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112 @@ -2272,11 +2272,11 @@ void xxxx() { // CHECK2-NEXT: [[TMP49:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP47]], i8* [[TMP48]]) #[[ATTR4]] // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK2: .untied.jmp.7.i: -// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[REF_TMP_I]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP50:%.*]] = bitcast %struct.S* [[TMP17]] to i8* // CHECK2-NEXT: [[TMP51:%.*]] = bitcast %struct.S* [[REF_TMP_I]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i64 4, i1 false) #[[ATTR4]] -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP_I]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] // CHECK2-NEXT: [[A9_I:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP19]], i32 0, i32 0 // CHECK2-NEXT: store i32 10, i32* [[A9_I]], align 4 // CHECK2-NEXT: [[TMP52:%.*]] = load i32, i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112 @@ -2288,11 +2288,11 @@ void xxxx() { // CHECK2-NEXT: [[TMP57:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP55]], i8* [[TMP56]]) #[[ATTR4]] // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK2: .untied.jmp.10.i: -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[TMP19]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP19]]) #[[ATTR4]] // CHECK2-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112 // CHECK2-NEXT: [[TMP59:%.*]] = bitcast %struct.S* [[TMP19]] to i8* // CHECK2-NEXT: call void @__kmpc_free(i32 [[TMP58]], i8* [[TMP59]], i8* inttoptr (i64 7 to i8*)) #[[ATTR4]] -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[TMP17]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]]) #[[ATTR4]] // CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112 // CHECK2-NEXT: br label [[CLEANUP_I]] // CHECK2: cleanup.i: @@ -2303,7 +2303,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2314,7 +2314,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2325,32 +2325,32 @@ void xxxx() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR7]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN2S1C1Ev(%struct.S1* noundef @s1) +// CHECK2-NEXT: call void @_ZN2S1C1Ev(%struct.S1* nonnull align 4 dereferenceable(4) @s1) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1C1Ev -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2S1C2Ev(%struct.S1* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN2S1C2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1C2Ev -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2S18taskinitEv(%struct.S1* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN2S18taskinitEv(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S18taskinitEv -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR8:[0-9]+]] align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR8:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_21:%.*]], align 8 @@ -2371,7 +2371,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..23 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.22* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.22* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2425,7 +2425,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..24 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR9:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR9:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2464,7 +2464,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map..26 -// CHECK2-SAME: (%struct..kmp_privates.t.25* noalias noundef [[TMP0:%.*]], double** noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK2-SAME: (%struct..kmp_privates.t.25* noalias [[TMP0:%.*]], double** noalias [[TMP1:%.*]]) #[[ATTR7]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t.25*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca double**, align 8 @@ -2478,7 +2478,7 @@ void xxxx() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..27 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.24* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.24* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2569,7 +2569,7 @@ void xxxx() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] @@ -2846,7 +2846,7 @@ void xxxx() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP169]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE52:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done52: @@ -2855,17 +2855,17 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2911,7 +2911,7 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..2 -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2952,7 +2952,7 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..4 -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -3015,7 +3015,7 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..6 -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -3075,7 +3075,7 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..8 -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -3135,7 +3135,7 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..10 -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -3171,7 +3171,7 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..12 -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -3207,7 +3207,7 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..14 -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -3243,7 +3243,7 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..16 -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -3282,7 +3282,7 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK3-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -3296,7 +3296,7 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..19 -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.18* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.18* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -3341,17 +3341,17 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map..20 -// CHECK3-SAME: (%struct..kmp_privates.t.20* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]], %struct.S** noalias noundef [[TMP2:%.*]], %struct.S** noalias noundef [[TMP3:%.*]]) #[[ATTR7]] { +// CHECK3-SAME: (%struct..kmp_privates.t.20* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]], %struct.S** noalias [[TMP2:%.*]], %struct.S** noalias [[TMP3:%.*]]) #[[ATTR7]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t.20*, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -3375,7 +3375,7 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..21 -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -3442,8 +3442,8 @@ void xxxx() { // CHECK3-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP22]]) #[[ATTR4]] // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]] // CHECK3: .untied.jmp.2.i: -// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[S1_I]]) #[[ATTR4]] -// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[S2_I]]) #[[ATTR4]] +// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]] +// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]] // CHECK3-NEXT: [[A_I:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[S2_I]], i32 0, i32 0 // CHECK3-NEXT: store i32 0, i32* [[A_I]], align 4, !noalias !112 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM3_I:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB23:[0-9]+]]) #[[ATTR4]] @@ -3472,11 +3472,11 @@ void xxxx() { // CHECK3-NEXT: [[TMP37:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9_I]], i8* [[TMP36]]) #[[ATTR4]] // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK3: .untied.jmp.10.i: -// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[REF_TMP_I]]) #[[ATTR4]] +// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] // CHECK3-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[S1_I]] to i8* // CHECK3-NEXT: [[TMP39:%.*]] = bitcast %struct.S* [[REF_TMP_I]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP38]], i8* align 4 [[TMP39]], i64 4, i1 false) #[[ATTR4]], !noalias !112 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP_I]]) #[[ATTR4]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] // CHECK3-NEXT: [[A12_I:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[S2_I]], i32 0, i32 0 // CHECK3-NEXT: store i32 10, i32* [[A12_I]], align 4, !noalias !112 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM13_I:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) #[[ATTR4]] @@ -3488,8 +3488,8 @@ void xxxx() { // CHECK3-NEXT: [[TMP43:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM14_I]], i8* [[TMP42]]) #[[ATTR4]] // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK3: .untied.jmp.15.i: -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S2_I]]) #[[ATTR4]] -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S1_I]]) #[[ATTR4]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]] // CHECK3-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112 // CHECK3-NEXT: br label [[CLEANUP_I]] // CHECK3: cleanup.i: @@ -3500,7 +3500,7 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3511,7 +3511,7 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3522,32 +3522,32 @@ void xxxx() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR7]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN2S1C1Ev(%struct.S1* noundef @s1) +// CHECK3-NEXT: call void @_ZN2S1C1Ev(%struct.S1* nonnull align 4 dereferenceable(4) @s1) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2S1C1Ev -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN2S1C2Ev(%struct.S1* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN2S1C2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2S1C2Ev -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN2S18taskinitEv(%struct.S1* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN2S18taskinitEv(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2S18taskinitEv -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR8:[0-9]+]] align 2 { +// CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR8:[0-9]+]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_21:%.*]], align 8 @@ -3569,7 +3569,7 @@ void xxxx() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..23 -// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.22* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.22* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -3648,7 +3648,7 @@ void xxxx() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] @@ -3925,7 +3925,7 @@ void xxxx() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP169]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE52:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done52: @@ -3934,17 +3934,17 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -3990,7 +3990,7 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..2 -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -4031,7 +4031,7 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..4 -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -4094,7 +4094,7 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..6 -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -4154,7 +4154,7 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..8 -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -4214,7 +4214,7 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..10 -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -4250,7 +4250,7 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..12 -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -4286,7 +4286,7 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..14 -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -4322,7 +4322,7 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..16 -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -4361,7 +4361,7 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK4-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK4-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -4375,7 +4375,7 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..19 -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.18* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.18* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -4420,17 +4420,17 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map..20 -// CHECK4-SAME: (%struct..kmp_privates.t.20* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]], %struct.S** noalias noundef [[TMP2:%.*]], %struct.S** noalias noundef [[TMP3:%.*]]) #[[ATTR7]] { +// CHECK4-SAME: (%struct..kmp_privates.t.20* noalias [[TMP0:%.*]], i32** noalias [[TMP1:%.*]], %struct.S** noalias [[TMP2:%.*]], %struct.S** noalias [[TMP3:%.*]]) #[[ATTR7]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t.20*, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 @@ -4454,7 +4454,7 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..21 -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -4521,8 +4521,8 @@ void xxxx() { // CHECK4-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP22]]) #[[ATTR4]] // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]] // CHECK4: .untied.jmp.2.i: -// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[S1_I]]) #[[ATTR4]] -// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[S2_I]]) #[[ATTR4]] +// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]] +// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]] // CHECK4-NEXT: [[A_I:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[S2_I]], i32 0, i32 0 // CHECK4-NEXT: store i32 0, i32* [[A_I]], align 4, !noalias !112 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM3_I:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB23:[0-9]+]]) #[[ATTR4]] @@ -4551,11 +4551,11 @@ void xxxx() { // CHECK4-NEXT: [[TMP37:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9_I]], i8* [[TMP36]]) #[[ATTR4]] // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK4: .untied.jmp.10.i: -// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef [[REF_TMP_I]]) #[[ATTR4]] +// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] // CHECK4-NEXT: [[TMP38:%.*]] = bitcast %struct.S* [[S1_I]] to i8* // CHECK4-NEXT: [[TMP39:%.*]] = bitcast %struct.S* [[REF_TMP_I]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP38]], i8* align 4 [[TMP39]], i64 4, i1 false) #[[ATTR4]], !noalias !112 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP_I]]) #[[ATTR4]] +// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] // CHECK4-NEXT: [[A12_I:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[S2_I]], i32 0, i32 0 // CHECK4-NEXT: store i32 10, i32* [[A12_I]], align 4, !noalias !112 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM13_I:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) #[[ATTR4]] @@ -4567,8 +4567,8 @@ void xxxx() { // CHECK4-NEXT: [[TMP43:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM14_I]], i8* [[TMP42]]) #[[ATTR4]] // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK4: .untied.jmp.15.i: -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S2_I]]) #[[ATTR4]] -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S1_I]]) #[[ATTR4]] +// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]] +// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]] // CHECK4-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112 // CHECK4-NEXT: br label [[CLEANUP_I]] // CHECK4: cleanup.i: @@ -4579,7 +4579,7 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4590,7 +4590,7 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4601,32 +4601,32 @@ void xxxx() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR7]] section "__TEXT,__StaticInit,regular,pure_instructions" { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN2S1C1Ev(%struct.S1* noundef @s1) +// CHECK4-NEXT: call void @_ZN2S1C1Ev(%struct.S1* nonnull align 4 dereferenceable(4) @s1) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2S1C1Ev -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN2S1C2Ev(%struct.S1* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN2S1C2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2S1C2Ev -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN2S18taskinitEv(%struct.S1* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN2S18taskinitEv(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2S18taskinitEv -// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]]) #[[ATTR8:[0-9]+]] align 2 { +// CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR8:[0-9]+]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_21:%.*]], align 8 @@ -4648,7 +4648,7 @@ void xxxx() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..23 -// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.22* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.22* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/task_firstprivate_codegen.cpp b/clang/test/OpenMP/task_firstprivate_codegen.cpp index 7aed172a55dec5b5ddfe1c74b50dad771ae74e98..1953b1ebf8556d8257311d241554122b425b4d2b 100644 --- a/clang/test/OpenMP/task_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/task_firstprivate_codegen.cpp @@ -89,7 +89,7 @@ int main() { // LAMBDA: store volatile double 2.0{{.+}}, double* [[G_REF]] // LAMBDA: store double* %{{.+}}, double** %{{.+}}, - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -138,7 +138,7 @@ int main() { // BLOCKS: store double* %{{.+}}, double** %{{.+}}, // BLOCKS: store i{{[0-9]+}}* %{{.+}}, i{{[0-9]+}}** %{{.+}}, - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -234,7 +234,7 @@ int main() { // Start task. // CHECK: call i32 @__kmpc_omp_task([[LOC]], i32 [[GTID]], i8* [[RES]]) -// CHECK: = call noundef i{{.+}} [[TMAIN_INT:@.+]]() +// CHECK: = call i{{.+}} [[TMAIN_INT:@.+]]() // No destructors must be called for private copies of s_arr and var. // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 @@ -245,7 +245,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x [[S_DOUBLE_TY]]]** noalias noundef %2, [2 x i32]** noalias noundef %3, i32** noalias noundef %4, [[S_DOUBLE_TY]]** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, i32** noalias %1, [2 x [[S_DOUBLE_TY]]]** noalias %2, [2 x i32]** noalias %3, i32** noalias %4, [[S_DOUBLE_TY]]** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -264,7 +264,7 @@ int main() { // CHECK: store i{{[0-9]+}}* [[PRIV_SIVAR]], i{{[0-9]+}}** [[ARG5]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -293,7 +293,7 @@ int main() { // CHECK: ret -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -372,7 +372,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -388,7 +388,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, // CHECK-DAG: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*, @@ -411,7 +411,7 @@ int main() { // CHECK: ret -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/task_if_codegen.cpp b/clang/test/OpenMP/task_if_codegen.cpp index 23562061948e539a7644480042e8d6463201aab8..41a0dab8affec91ebc61efc533319a040c6d9127 100644 --- a/clang/test/OpenMP/task_if_codegen.cpp +++ b/clang/test/OpenMP/task_if_codegen.cpp @@ -95,7 +95,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -114,7 +114,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -213,12 +213,12 @@ int main() { // CHECK1-NEXT: br label [[OMP_IF_END7]] // CHECK1: omp_if.end7: // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* @Arg, align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP27]]) +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP27]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..3 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -254,7 +254,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..5 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -290,7 +290,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..7 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -326,7 +326,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..9 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -362,7 +362,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK1-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 @@ -489,7 +489,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..11 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -525,7 +525,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..13 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -561,7 +561,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..15 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -597,7 +597,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..17 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -633,7 +633,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..19 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.17* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.17* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -669,7 +669,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..21 -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -712,7 +712,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -731,7 +731,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -830,12 +830,12 @@ int main() { // CHECK2-NEXT: br label [[OMP_IF_END7]] // CHECK2: omp_if.end7: // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* @Arg, align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP27]]) +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP27]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..3 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -871,7 +871,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..5 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -907,7 +907,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..7 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -943,7 +943,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..9 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -979,7 +979,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK2-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 @@ -1106,7 +1106,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..11 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1142,7 +1142,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..13 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1178,7 +1178,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..15 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1214,7 +1214,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..17 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1250,7 +1250,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..19 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.17* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.17* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1286,7 +1286,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..21 -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1329,7 +1329,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1348,7 +1348,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK5-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1447,12 +1447,12 @@ int main() { // CHECK5-NEXT: br label [[OMP_IF_END7]] // CHECK5: omp_if.end7: // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* @Arg, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP27]]) +// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP27]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..3 -// CHECK5-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1488,7 +1488,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..5 -// CHECK5-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1524,7 +1524,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..7 -// CHECK5-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1560,7 +1560,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..9 -// CHECK5-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1596,7 +1596,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK5-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 @@ -1723,7 +1723,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..11 -// CHECK5-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1759,7 +1759,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..13 -// CHECK5-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1795,7 +1795,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..15 -// CHECK5-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1831,7 +1831,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..17 -// CHECK5-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1867,7 +1867,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..19 -// CHECK5-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.17* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.17* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1903,7 +1903,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..21 -// CHECK5-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK5-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1946,7 +1946,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1965,7 +1965,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2064,12 +2064,12 @@ int main() { // CHECK6-NEXT: br label [[OMP_IF_END7]] // CHECK6: omp_if.end7: // CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* @Arg, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP27]]) +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP27]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..3 -// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.1* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2105,7 +2105,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..5 -// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.3* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2141,7 +2141,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..7 -// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.5* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2177,7 +2177,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..9 -// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.7* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2213,7 +2213,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK6-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 @@ -2340,7 +2340,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..11 -// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.9* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2376,7 +2376,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..13 -// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.11* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2412,7 +2412,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..15 -// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.13* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2448,7 +2448,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..17 -// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.15* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2484,7 +2484,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..19 -// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.17* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.17* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -2520,7 +2520,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..21 -// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias noundef [[TMP1:%.*]]) #[[ATTR2]] { +// CHECK6-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates.19* noalias [[TMP1:%.*]]) #[[ATTR2]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/task_in_reduction_codegen.cpp b/clang/test/OpenMP/task_in_reduction_codegen.cpp index 3cd91d2e6356bb8a9897bf1a14bfe6bb4c73fd1d..9f8bf1ce15476e7a397b9f4b1b5d8f11e93d7e82 100644 --- a/clang/test/OpenMP/task_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/task_in_reduction_codegen.cpp @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -disable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/task_private_codegen.cpp b/clang/test/OpenMP/task_private_codegen.cpp index 819e539a4a022c7e8d4e7dc745a3a502ef0cd596..f582e89d0a36ab9740717affac1694bf3e4704cf 100644 --- a/clang/test/OpenMP/task_private_codegen.cpp +++ b/clang/test/OpenMP/task_private_codegen.cpp @@ -77,7 +77,7 @@ int main() { // LAMBDA: [[SIVAR_REF:%.+]] = load i{{[0-9]+}}*, i{{[0-9]+}}** [[SIVAR_PTR_REF]] // LAMBDA: store i{{[0-9]+}} 3, i{{[0-9]+}}* [[SIVAR_REF]] - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 2; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -113,7 +113,7 @@ int main() { // BLOCKS-NOT: [[SIVAR]]{{[[^:word:]]}} // BLOCKS: ret - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 3; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -195,7 +195,7 @@ int main() { // CHECK: call i32 @__kmpc_omp_task([[LOC]], i32 [[GTID]], i8* [[RES]]) // CHECK: call i32 @__kmpc_omp_task([[LOC]], i32 [[GTID]], i8* -// CHECK: = call noundef i{{.+}} [[TMAIN_INT:@.+]]() +// CHECK: = call i{{.+}} [[TMAIN_INT:@.+]]() // No destructors must be called for private copies of s_arr and var. // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 @@ -206,7 +206,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -222,7 +222,7 @@ int main() { // CHECK: store [2 x i32]* [[PRIV_VEC]], [2 x i32]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -248,7 +248,7 @@ int main() { // CHECK: ret -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -318,7 +318,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -334,7 +334,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -358,7 +358,7 @@ int main() { // CHECK: ret -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/taskgroup_codegen.cpp b/clang/test/OpenMP/taskgroup_codegen.cpp index c3d61d12aadb503466498186531ef84a581bae77..27aea98e945f94471048b2d30979d16117923e40 100644 --- a/clang/test/OpenMP/taskgroup_codegen.cpp +++ b/clang/test/OpenMP/taskgroup_codegen.cpp @@ -86,7 +86,7 @@ void parallel_taskgroup() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR7:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR7:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -174,7 +174,7 @@ void parallel_taskgroup() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR7:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR7:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -206,14 +206,14 @@ void parallel_taskgroup() { // // // DEBUG1-LABEL: define {{[^@]+}}@_Z3foov -// DEBUG1-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG7:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG10:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG11:![0-9]+]] +// DEBUG1-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG9:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG10:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@main -// DEBUG1-SAME: () #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG12:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR2:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG11:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: [[A:%.*]] = alloca i8, align 1 @@ -221,30 +221,30 @@ void parallel_taskgroup() { // DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) // DEBUG1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// DEBUG1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !dbg [[DBG13:![0-9]+]] -// DEBUG1-NEXT: store i8 2, i8* [[A]], align 1, !dbg [[DBG14:![0-9]+]] -// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !dbg [[DBG15:![0-9]+]] -// DEBUG1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG16:![0-9]+]] +// DEBUG1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !dbg [[DBG12:![0-9]+]] +// DEBUG1-NEXT: store i8 2, i8* [[A]], align 1, !dbg [[DBG13:![0-9]+]] +// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !dbg [[DBG14:![0-9]+]] +// DEBUG1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG15:![0-9]+]] // DEBUG1-NEXT: invoke void @_Z3foov() -// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG17:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG16:![0-9]+]] // DEBUG1: invoke.cont: -// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]), !dbg [[DBG17]] -// DEBUG1-NEXT: [[TMP1:%.*]] = load i8, i8* [[A]], align 1, !dbg [[DBG18:![0-9]+]] -// DEBUG1-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32, !dbg [[DBG18]] -// DEBUG1-NEXT: ret i32 [[CONV]], !dbg [[DBG19:![0-9]+]] +// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]), !dbg [[DBG16]] +// DEBUG1-NEXT: [[TMP1:%.*]] = load i8, i8* [[A]], align 1, !dbg [[DBG17:![0-9]+]] +// DEBUG1-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32, !dbg [[DBG17]] +// DEBUG1-NEXT: ret i32 [[CONV]], !dbg [[DBG18:![0-9]+]] // DEBUG1: lpad: // DEBUG1-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// DEBUG1-NEXT: catch i8* null, !dbg [[DBG20:![0-9]+]] -// DEBUG1-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0, !dbg [[DBG20]] -// DEBUG1-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG20]] -// DEBUG1-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1, !dbg [[DBG20]] -// DEBUG1-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG20]] -// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]), !dbg [[DBG17]] -// DEBUG1-NEXT: br label [[TERMINATE_HANDLER:%.*]], !dbg [[DBG17]] +// DEBUG1-NEXT: catch i8* null, !dbg [[DBG19:![0-9]+]] +// DEBUG1-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0, !dbg [[DBG19]] +// DEBUG1-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG19]] +// DEBUG1-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1, !dbg [[DBG19]] +// DEBUG1-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG19]] +// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]]), !dbg [[DBG16]] +// DEBUG1-NEXT: br label [[TERMINATE_HANDLER:%.*]], !dbg [[DBG16]] // DEBUG1: terminate.handler: -// DEBUG1-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG17]] -// DEBUG1-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR8:[0-9]+]], !dbg [[DBG17]] -// DEBUG1-NEXT: unreachable, !dbg [[DBG17]] +// DEBUG1-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG16]] +// DEBUG1-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR8:[0-9]+]], !dbg [[DBG16]] +// DEBUG1-NEXT: unreachable, !dbg [[DBG16]] // // // DEBUG1-LABEL: define {{[^@]+}}@__clang_call_terminate @@ -255,14 +255,14 @@ void parallel_taskgroup() { // // // DEBUG1-LABEL: define {{[^@]+}}@_Z18parallel_taskgroupv -// DEBUG1-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG21:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG20:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB7:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)), !dbg [[DBG22:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG23:![0-9]+]] +// DEBUG1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB7:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)), !dbg [[DBG21:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG22:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@.omp_outlined. -// DEBUG1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR7:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG24:![0-9]+]] { +// DEBUG1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR7:[0-9]+]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG23:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // DEBUG1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -270,25 +270,25 @@ void parallel_taskgroup() { // DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 // DEBUG1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG25:![0-9]+]] -// DEBUG1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4, !dbg [[DBG25]] -// DEBUG1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB5:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG25]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG24:![0-9]+]] +// DEBUG1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4, !dbg [[DBG24]] +// DEBUG1-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB5:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG24]] // DEBUG1-NEXT: invoke void @_Z3foov() -// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG26:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG25:![0-9]+]] // DEBUG1: invoke.cont: -// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB5]], i32 [[TMP1]]), !dbg [[DBG26]] -// DEBUG1-NEXT: ret void, !dbg [[DBG27:![0-9]+]] +// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB5]], i32 [[TMP1]]), !dbg [[DBG25]] +// DEBUG1-NEXT: ret void, !dbg [[DBG26:![0-9]+]] // DEBUG1: lpad: // DEBUG1-NEXT: [[TMP2:%.*]] = landingpad { i8*, i32 } -// DEBUG1-NEXT: catch i8* null, !dbg [[DBG28:![0-9]+]] -// DEBUG1-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0, !dbg [[DBG28]] -// DEBUG1-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG28]] -// DEBUG1-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1, !dbg [[DBG28]] -// DEBUG1-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG28]] -// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB5]], i32 [[TMP1]]), !dbg [[DBG26]] -// DEBUG1-NEXT: br label [[TERMINATE_HANDLER:%.*]], !dbg [[DBG26]] +// DEBUG1-NEXT: catch i8* null, !dbg [[DBG27:![0-9]+]] +// DEBUG1-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 0, !dbg [[DBG27]] +// DEBUG1-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG27]] +// DEBUG1-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1, !dbg [[DBG27]] +// DEBUG1-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG27]] +// DEBUG1-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB5]], i32 [[TMP1]]), !dbg [[DBG25]] +// DEBUG1-NEXT: br label [[TERMINATE_HANDLER:%.*]], !dbg [[DBG25]] // DEBUG1: terminate.handler: -// DEBUG1-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG26]] -// DEBUG1-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR8]], !dbg [[DBG26]] -// DEBUG1-NEXT: unreachable, !dbg [[DBG26]] +// DEBUG1-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG25]] +// DEBUG1-NEXT: call void @__clang_call_terminate(i8* [[EXN]]) #[[ATTR8]], !dbg [[DBG25]] +// DEBUG1-NEXT: unreachable, !dbg [[DBG25]] // diff --git a/clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp b/clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp index fc14f536a3927db9fc77a3e4c4defb070d4bab43..64db70a0283147af3bde6b3135580c5d47b885e0 100644 --- a/clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp @@ -165,54 +165,54 @@ int main(int argc, char **argv) { // CHECK: call void @__kmpc_end_taskgroup(%struct.ident_t* {{[^,]+}}, i32 [[GTID]]) // CHECK: call void @__kmpc_end_taskgroup(%struct.ident_t* {{[^,]+}}, i32 [[GTID]]) -// CHECK-DAG: define internal void @[[AINIT]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK-DAG: define internal void @[[AINIT]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK-DAG: store i32 0, i32* % // CHECK-DAG: ret void // CHECK-DAG: } -// CHECK-DAG: define internal void @[[ACOMB]](i8* noundef %0, i8* noundef %1) +// CHECK-DAG: define internal void @[[ACOMB]](i8* %0, i8* %1) // CHECK-DAG: add nsw i32 % // CHECK-DAG: store i32 % // CHECK-DAG: ret void // CHECK-DAG: } -// CHECK-DAG: define internal void @[[BINIT]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK-DAG: define internal void @[[BINIT]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK-DAG: store float 0.000000e+00, float* % // CHECK-DAG: ret void // CHECK-DAG: } -// CHECK-DAG: define internal void @[[BCOMB]](i8* noundef %0, i8* noundef %1) +// CHECK-DAG: define internal void @[[BCOMB]](i8* %0, i8* %1) // CHECK-DAG: fadd float % // CHECK-DAG: store float % // CHECK-DAG: ret void // CHECK-DAG: } -// CHECK-DAG: define internal void @[[ARGCINIT]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK-DAG: define internal void @[[ARGCINIT]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK-DAG: store i32 0, i32* % // CHECK-DAG: ret void // CHECK-DAG: } -// CHECK-DAG: define internal void @[[ARGCCOMB]](i8* noundef %0, i8* noundef %1) +// CHECK-DAG: define internal void @[[ARGCCOMB]](i8* %0, i8* %1) // CHECK-DAG: add nsw i32 % // CHECK-DAG: store i32 % // CHECK-DAG: ret void // CHECK-DAG: } -// CHECK-DAG: define internal void @[[CINIT]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK-DAG: define internal void @[[CINIT]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK-DAG: phi %struct.S* [ // CHECK-DAG: call {{.+}}(%struct.S* {{.+}}) // CHECK-DAG: br i1 % // CHECK-DAG: ret void // CHECK-DAG: } -// CHECK-DAG: define internal void @[[CFINI]](i8* noundef %0) +// CHECK-DAG: define internal void @[[CFINI]](i8* %0) // CHECK-DAG: phi %struct.S* [ // CHECK-DAG: call {{.+}}(%struct.S* {{.+}}) // CHECK-DAG: br i1 % // CHECK-DAG: ret void // CHECK-DAG: } -// CHECK-DAG: define internal void @[[CCOMB]](i8* noundef %0, i8* noundef %1) +// CHECK-DAG: define internal void @[[CCOMB]](i8* %0, i8* %1) // CHECK-DAG: phi %struct.S* [ // CHECK-DAG: phi %struct.S* [ // CHECK-DAG: call {{.+}}(%struct.S* {{.+}}, %struct.S* {{.+}}, %struct.S* {{.+}}) @@ -222,7 +222,7 @@ int main(int argc, char **argv) { // CHECK-DAG: ret void // CHECK_DAG: } -// CHECK-DAG: define internal void @[[VLAINIT]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK-DAG: define internal void @[[VLAINIT]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK-DAG: call i32 @__kmpc_global_thread_num(%struct.ident_t* {{[^,]+}}) // CHECK-DAG: call i8* @__kmpc_threadprivate_cached(%struct.ident_t* // CHECK-DAG: phi i16* [ @@ -231,7 +231,7 @@ int main(int argc, char **argv) { // CHECK-DAG: ret void // CHECK-DAG: } -// CHECK-DAG: define internal void @[[VLACOMB]](i8* noundef %0, i8* noundef %1) +// CHECK-DAG: define internal void @[[VLACOMB]](i8* %0, i8* %1) // CHECK-DAG: call i32 @__kmpc_global_thread_num(%struct.ident_t* {{[^,]+}}) // CHECK-DAG: call i8* @__kmpc_threadprivate_cached(%struct.ident_t* // CHECK-DAG: phi i16* [ diff --git a/clang/test/OpenMP/taskloop_codegen.cpp b/clang/test/OpenMP/taskloop_codegen.cpp index 0b84ccc8012bd7896f5484f5f5cbcb577a380704..7402c2ad65ebaaf43a0546ced976f32e580c0d2a 100644 --- a/clang/test/OpenMP/taskloop_codegen.cpp +++ b/clang/test/OpenMP/taskloop_codegen.cpp @@ -79,7 +79,7 @@ int main(int argc, char **argv) { } } -// CHECK: define internal noundef i32 [[TASK1]]( +// CHECK: define internal i32 [[TASK1]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 @@ -109,7 +109,7 @@ int main(int argc, char **argv) { // CHECK: br label % // CHECK: ret i32 0 -// CHECK: define internal noundef i32 [[TASK2]]( +// CHECK: define internal i32 [[TASK2]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 @@ -139,7 +139,7 @@ int main(int argc, char **argv) { // CHECK: br label % // CHECK: ret i32 0 -// CHECK: define internal noundef i32 [[TASK3]]( +// CHECK: define internal i32 [[TASK3]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 @@ -157,7 +157,7 @@ int main(int argc, char **argv) { // CHECK: br label // CHECK: ret i32 0 -// CHECK: define internal noundef i32 [[TASK_CANCEL]]( +// CHECK: define internal i32 [[TASK_CANCEL]]( // CHECK: [[RES:%.+]] = call i32 @__kmpc_cancel(%struct.ident_t* @{{.+}}, i32 %{{.+}}, i32 4) // CHECK: [[IS_CANCEL:%.+]] = icmp ne i32 [[RES]], 0 // CHECK: br i1 [[IS_CANCEL]], label %[[EXIT:.+]], label %[[CONTINUE:[^,]+]] @@ -199,7 +199,7 @@ struct S { } } s(1); -// CHECK: define internal noundef i32 [[TASK4]]( +// CHECK: define internal i32 [[TASK4]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 diff --git a/clang/test/OpenMP/taskloop_firstprivate_codegen.cpp b/clang/test/OpenMP/taskloop_firstprivate_codegen.cpp index 0fcc151b5edef2e41b504f5fda72aa91ff61b007..dc0a5600d1bb92bc87c0cd4067fbc9cae50de37a 100644 --- a/clang/test/OpenMP/taskloop_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/taskloop_firstprivate_codegen.cpp @@ -86,7 +86,7 @@ int main() { // LAMBDA: store volatile double 2.0{{.+}}, double* [[G_REF]] // LAMBDA: store double* %{{.+}}, double** %{{.+}}, - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -131,7 +131,7 @@ int main() { // BLOCKS: store double* %{{.+}}, double** %{{.+}}, // BLOCKS: store i{{[0-9]+}}* %{{.+}}, i{{[0-9]+}}** %{{.+}}, - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -238,7 +238,7 @@ int main() { // Start task. // CHECK: call void @__kmpc_taskloop([[LOC]], i32 [[GTID]], i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* bitcast (void ([[KMP_TASK_MAIN_TY]]*, [[KMP_TASK_MAIN_TY]]*, i32)* [[MAIN_DUP:@.+]] to i8*)) -// CHECK: = call noundef i{{.+}} [[TMAIN_INT:@.+]]() +// CHECK: = call i{{.+}} [[TMAIN_INT:@.+]]() // No destructors must be called for private copies of s_arr and var. // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 @@ -249,7 +249,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -268,7 +268,7 @@ int main() { // CHECK: store i{{[0-9]+}}* [[PRIV_SIVAR]], i{{[0-9]+}}** [[ARG5]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -296,7 +296,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0 @@ -313,7 +313,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_COPY_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -404,7 +404,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -420,7 +420,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, // CHECK-DAG: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*, @@ -443,7 +443,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* %{{.+}}, i32 0, i32 0 @@ -460,7 +460,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_COPY_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp b/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp index 8b5546cc69e1fb24a1d5aa6786f9c9b21e64aea7..12804d1b7959aba2b31a0bd008d6a5566d72a8db 100644 --- a/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -disable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/taskloop_lastprivate_codegen.cpp b/clang/test/OpenMP/taskloop_lastprivate_codegen.cpp index f905955607ad675a65590e92adea38e7cb98180b..80d94ffcf3b3c2c6ce96e87c01c0548e298224a6 100644 --- a/clang/test/OpenMP/taskloop_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/taskloop_lastprivate_codegen.cpp @@ -81,7 +81,7 @@ int main() { // LAMBDA: store double 2.0{{.+}}, double* [[G_REF]] // LAMBDA: store double* %{{.+}}, double** %{{.+}}, - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -125,7 +125,7 @@ int main() { // BLOCKS: store double* %{{.+}}, double** %{{.+}}, // BLOCKS: store i{{[0-9]+}}* %{{.+}}, i{{[0-9]+}}** %{{.+}}, - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -230,7 +230,7 @@ int main() { // Start task. // CHECK: call void @__kmpc_taskloop([[LOC]], i32 [[GTID]], i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* bitcast (void ([[KMP_TASK_MAIN_TY]]*, [[KMP_TASK_MAIN_TY]]*, i32)* [[MAIN_DUP:@.+]] to i8*)) -// CHECK: = call noundef i{{.+}} [[TMAIN_INT:@.+]]() +// CHECK: = call i{{.+}} [[TMAIN_INT:@.+]]() // No destructors must be called for private copies of s_arr and var. // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 @@ -241,7 +241,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -260,7 +260,7 @@ int main() { // CHECK: store i{{[0-9]+}}* [[PRIV_SIVAR]], i{{[0-9]+}}** [[ARG5]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -307,7 +307,7 @@ int main() { // CHECK: br label // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* %{{.+}}, i32 0, i32 8 // CHECK: load i32, i32* % @@ -328,7 +328,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -414,7 +414,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -430,7 +430,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, // CHECK-DAG: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*, @@ -470,7 +470,7 @@ int main() { // CHECK: br label // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* %{{.+}}, i32 0, i32 8 // CHECK: load i32, i32* % @@ -491,7 +491,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/taskloop_private_codegen.cpp b/clang/test/OpenMP/taskloop_private_codegen.cpp index 29f949f7b580a810a9752b7d6503e73444ae6a91..2815bd71afaf1b9dfb109bb05723b10ee4f8a28f 100644 --- a/clang/test/OpenMP/taskloop_private_codegen.cpp +++ b/clang/test/OpenMP/taskloop_private_codegen.cpp @@ -77,7 +77,7 @@ int main() { // LAMBDA: [[SIVAR_REF:%.+]] = load i{{[0-9]+}}*, i{{[0-9]+}}** [[SIVAR_PTR_REF]] // LAMBDA: store i{{[0-9]+}} 3, i{{[0-9]+}}* [[SIVAR_REF]] - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 2; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -113,7 +113,7 @@ int main() { // BLOCKS-NOT: [[SIVAR]]{{[[^:word:]]}} // BLOCKS: ret - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 3; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -195,7 +195,7 @@ int main() { // CHECK: call void @__kmpc_taskloop([[LOC]], i32 [[GTID]], i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* bitcast (void ([[KMP_TASK_MAIN_TY]]*, [[KMP_TASK_MAIN_TY]]*, i32)* [[MAIN_DUP:@.+]] to i8*)) // CHECK: call i32 @__kmpc_omp_task([[LOC]], i32 [[GTID]], i8* -// CHECK: = call noundef i{{.+}} [[TMAIN_INT:@.+]]() +// CHECK: = call i{{.+}} [[TMAIN_INT:@.+]]() // No destructors must be called for private copies of s_arr and var. // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 @@ -206,7 +206,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -222,7 +222,7 @@ int main() { // CHECK: store [2 x i32]* [[PRIV_VEC]], [2 x i32]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -248,7 +248,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0 @@ -265,7 +265,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_DEF_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -335,7 +335,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -351,7 +351,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -375,7 +375,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* %{{.+}}, i32 0, i32 0 @@ -392,7 +392,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_DEF_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/taskloop_reduction_codegen.cpp b/clang/test/OpenMP/taskloop_reduction_codegen.cpp index 915c4f8599ff5269def1228f3621dea8f27b3db9..aae07d20b836423ee047982ebf3722d2a1075773 100644 --- a/clang/test/OpenMP/taskloop_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskloop_reduction_codegen.cpp @@ -166,50 +166,50 @@ sum = 0.0; // CHECK: ret i32 -// CHECK: define internal void @[[RED_INIT1]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT1]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB1]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB1]](i8* %0, i8* %1) // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_INIT2]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT2]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: call void [[OMP_INIT1:@.+]](%struct.S* // CHECK: ret void -// CHECK: define internal void [[OMP_COMB1:@.+]](%struct.S* noalias noundef %0, %struct.S* noalias noundef %1) +// CHECK: define internal void [[OMP_COMB1:@.+]](%struct.S* noalias %0, %struct.S* noalias %1) // CHECK: fadd float % -// CHECK: define internal void [[OMP_INIT1]](%struct.S* noalias noundef %0, %struct.S* noalias noundef %1) +// CHECK: define internal void [[OMP_INIT1]](%struct.S* noalias %0, %struct.S* noalias %1) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64( -// CHECK: define internal void @[[RED_FINI2]](i8* noundef %0) +// CHECK: define internal void @[[RED_FINI2]](i8* %0) // CHECK: load i64, i64* [[RED_SIZE1]] // CHECK: call void @ // CHECK: ret void -// CHECK: define internal void @[[RED_COMB2]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB2]](i8* %0, i8* %1) // CHECK: load i64, i64* [[RED_SIZE1]] // CHECK: call void [[OMP_COMB1]]( // CHECK: ret void -// CHECK: define internal void @[[RED_INIT3]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT3]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB3]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB3]](i8* %0, i8* %1) // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_INIT4]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT4]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: load i64, i64* [[RED_SIZE2]] // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB4]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB4]](i8* %0, i8* %1) // CHECK: load i64, i64* [[RED_SIZE2]] // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % diff --git a/clang/test/OpenMP/taskloop_simd_codegen.cpp b/clang/test/OpenMP/taskloop_simd_codegen.cpp index 36f7c4674389b8c130c7b0416ee43ecd664776fb..8791dba20249a9e92a23ad5bb21fdc3bcd86a1c9 100644 --- a/clang/test/OpenMP/taskloop_simd_codegen.cpp +++ b/clang/test/OpenMP/taskloop_simd_codegen.cpp @@ -75,7 +75,7 @@ int main(int argc, char **argv) { ; } -// CHECK: define internal noundef i32 [[TASK1]]( +// CHECK: define internal i32 [[TASK1]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 @@ -105,7 +105,7 @@ int main(int argc, char **argv) { // CHECK: br label %{{.*}}!llvm.loop // CHECK: ret i32 0 -// CHECK: define internal noundef i32 [[TASK2]]( +// CHECK: define internal i32 [[TASK2]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 @@ -135,7 +135,7 @@ int main(int argc, char **argv) { // CHECK: br label %{{.*}}!llvm.loop // CHECK: ret i32 0 -// CHECK: define internal noundef i32 [[TASK3]]( +// CHECK: define internal i32 [[TASK3]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 @@ -178,7 +178,7 @@ struct S { } } s(1); -// CHECK: define internal noundef i32 [[TASK4]]( +// CHECK: define internal i32 [[TASK4]]( // CHECK: [[DOWN:%.+]] = getelementptr inbounds [[TD_TY:%.+]], [[TD_TY]]* %{{.+}}, i32 0, i32 5 // CHECK: [[DOWN_VAL:%.+]] = load i64, i64* [[DOWN]], // CHECK: [[UP:%.+]] = getelementptr inbounds [[TD_TY]], [[TD_TY]]* %{{.+}}, i32 0, i32 6 diff --git a/clang/test/OpenMP/taskloop_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/taskloop_simd_firstprivate_codegen.cpp index 438cab33e416430de70867e048f5e074563a45c8..27c02df50d3c3309359afda556be4fb383972cc0 100644 --- a/clang/test/OpenMP/taskloop_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/taskloop_simd_firstprivate_codegen.cpp @@ -86,7 +86,7 @@ int main() { // LAMBDA: store volatile double 2.0{{.+}}, double* [[G_REF]] // LAMBDA: store double* %{{.+}}, double** %{{.+}}, - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -131,7 +131,7 @@ int main() { // BLOCKS: store double* %{{.+}}, double** %{{.+}}, // BLOCKS: store i{{[0-9]+}}* %{{.+}}, i{{[0-9]+}}** %{{.+}}, - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -238,7 +238,7 @@ int main() { // Start task. // CHECK: call void @__kmpc_taskloop([[LOC]], i32 [[GTID]], i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* bitcast (void ([[KMP_TASK_MAIN_TY]]*, [[KMP_TASK_MAIN_TY]]*, i32)* [[MAIN_DUP:@.+]] to i8*)) -// CHECK: = call noundef i{{.+}} [[TMAIN_INT:@.+]]() +// CHECK: = call i{{.+}} [[TMAIN_INT:@.+]]() // No destructors must be called for private copies of s_arr and var. // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 @@ -249,7 +249,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -268,7 +268,7 @@ int main() { // CHECK: store i{{[0-9]+}}* [[PRIV_SIVAR]], i{{[0-9]+}}** [[ARG5]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -296,7 +296,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0 @@ -313,7 +313,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_COPY_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -404,7 +404,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -420,7 +420,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, // CHECK-DAG: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*, @@ -443,7 +443,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* %{{.+}}, i32 0, i32 0 @@ -460,7 +460,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_COPY_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp b/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp index c82ae72c53b318bffb7b1f92fc0b4ae7ca1bed89..71799c9842b0d883251feffe8750843bf49e4ce2 100644 --- a/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -disable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/taskloop_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/taskloop_simd_lastprivate_codegen.cpp index 6a89a7e9158310e1fb4be53b313c817a6d9a148d..0718fb261c9e8171f6a9e861abdce4c90f70e464 100644 --- a/clang/test/OpenMP/taskloop_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/taskloop_simd_lastprivate_codegen.cpp @@ -79,7 +79,7 @@ int main() { // LAMBDA: store double 2.0{{.+}}, double* [[G_REF]] // LAMBDA: store double* %{{.+}}, double** %{{.+}}, - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -123,7 +123,7 @@ int main() { // BLOCKS: store double* %{{.+}}, double** %{{.+}}, // BLOCKS: store i{{[0-9]+}}* %{{.+}}, i{{[0-9]+}}** %{{.+}}, - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 11; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -228,7 +228,7 @@ int main() { // Start task. // CHECK: call void @__kmpc_taskloop([[LOC]], i32 [[GTID]], i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* bitcast (void ([[KMP_TASK_MAIN_TY]]*, [[KMP_TASK_MAIN_TY]]*, i32)* [[MAIN_DUP:@.+]] to i8*)) -// CHECK: = call noundef i{{.+}} [[TMAIN_INT:@.+]]() +// CHECK: = call i{{.+}} [[TMAIN_INT:@.+]]() // No destructors must be called for private copies of s_arr and var. // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 @@ -239,7 +239,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -258,7 +258,7 @@ int main() { // CHECK: store i{{[0-9]+}}* [[PRIV_SIVAR]], i{{[0-9]+}}** [[ARG5]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -305,7 +305,7 @@ int main() { // CHECK: br label // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* %{{.+}}, i32 0, i32 8 // CHECK: load i32, i32* % @@ -326,7 +326,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -412,7 +412,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -428,7 +428,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, // CHECK-DAG: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*, @@ -468,7 +468,7 @@ int main() { // CHECK: br label // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* %{{.+}}, i32 0, i32 8 // CHECK: load i32, i32* % @@ -489,7 +489,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/taskloop_simd_private_codegen.cpp b/clang/test/OpenMP/taskloop_simd_private_codegen.cpp index ecc3be5331a47ffe8d58857563e55e992898ca9d..223a7c4cca217cff2dbe2144ff180e5866365d97 100644 --- a/clang/test/OpenMP/taskloop_simd_private_codegen.cpp +++ b/clang/test/OpenMP/taskloop_simd_private_codegen.cpp @@ -77,7 +77,7 @@ int main() { // LAMBDA: [[SIVAR_REF:%.+]] = load i{{[0-9]+}}*, i{{[0-9]+}}** [[SIVAR_PTR_REF]] // LAMBDA: store i{{[0-9]+}} 3, i{{[0-9]+}}* [[SIVAR_REF]] - // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // LAMBDA: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 2; // LAMBDA: store double 1.0{{.+}}, double* %{{.+}}, @@ -113,7 +113,7 @@ int main() { // BLOCKS-NOT: [[SIVAR]]{{[[^:word:]]}} // BLOCKS: ret - // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1) + // BLOCKS: define internal i32 [[TASK_ENTRY]](i32 %0, %{{.+}}* noalias %1) g = 1; sivar = 3; // BLOCKS: store double 1.0{{.+}}, double* %{{.+}}, @@ -195,7 +195,7 @@ int main() { // CHECK: call void @__kmpc_taskloop([[LOC]], i32 [[GTID]], i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* bitcast (void ([[KMP_TASK_MAIN_TY]]*, [[KMP_TASK_MAIN_TY]]*, i32)* [[MAIN_DUP:@.+]] to i8*)) // CHECK: call i32 @__kmpc_omp_task([[LOC]], i32 [[GTID]], i8* -// CHECK: = call noundef i{{.+}} [[TMAIN_INT:@.+]]() +// CHECK: = call i{{.+}} [[TMAIN_INT:@.+]]() // No destructors must be called for private copies of s_arr and var. // CHECK-NOT: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 @@ -206,7 +206,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias %0, [[S_DOUBLE_TY]]** noalias %1, i32** noalias %2, [2 x [[S_DOUBLE_TY]]]** noalias %3, [2 x i32]** noalias %4, i32** noalias %5) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]** // CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}}, @@ -222,7 +222,7 @@ int main() { // CHECK: store [2 x i32]* [[PRIV_VEC]], [2 x i32]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*, // CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -248,7 +248,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* %0, [[KMP_TASK_MAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0 @@ -265,7 +265,7 @@ int main() { // CHECK: call {{.*}} [[S_DOUBLE_TY_DEF_CONSTR]]([[S_DOUBLE_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_MAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1 @@ -335,7 +335,7 @@ int main() { // CHECK: ret // -// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %0, i32** noalias noundef %1, [2 x i32]** noalias noundef %2, [2 x [[S_INT_TY]]]** noalias noundef %3, [[S_INT_TY]]** noalias noundef %4) +// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias %0, i32** noalias %1, [2 x i32]** noalias %2, [2 x [[S_INT_TY]]]** noalias %3, [[S_INT_TY]]** noalias %4) // CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]** // CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0 // CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}}, @@ -351,7 +351,7 @@ int main() { // CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]], // CHECK: ret void -// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[TASK_ENTRY]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: alloca i32*, // CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*, @@ -375,7 +375,7 @@ int main() { // CHECK: ret -// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2) +// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* %0, [[KMP_TASK_TMAIN_TY]]* %1, i32 %2) // CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 2 // CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* %{{.+}}, i32 0, i32 0 @@ -392,7 +392,7 @@ int main() { // CHECK: call {{.*}} [[S_INT_TY_DEF_CONSTR]]([[S_INT_TY]]* // CHECK: ret void -// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1) +// CHECK: define internal i32 [[DESTRUCTORS]](i32 %0, [[KMP_TASK_TMAIN_TY]]* noalias %1) // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3 diff --git a/clang/test/OpenMP/taskloop_simd_reduction_codegen.cpp b/clang/test/OpenMP/taskloop_simd_reduction_codegen.cpp index 513cfb86ea1900479e02e398a68324c7925dd22f..235eab1afa73fd9cd2917468f8be7b845cab12c4 100644 --- a/clang/test/OpenMP/taskloop_simd_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskloop_simd_reduction_codegen.cpp @@ -163,51 +163,51 @@ sum = 0.0; // CHECK: ret i32 -// CHECK: define internal void @[[RED_INIT1]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT1]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB1]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB1]](i8* %0, i8* %1) // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_INIT2]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT2]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: call void [[OMP_INIT1:@.+]](%struct.S* // CHECK: ret void -// CHECK: define internal void [[OMP_COMB1:@.+]](%struct.S* noalias noundef %0, %struct.S* noalias noundef %1) +// CHECK: define internal void [[OMP_COMB1:@.+]](%struct.S* noalias %0, %struct.S* noalias %1) // CHECK: fadd float % -// CHECK: define internal void [[OMP_INIT1]](%struct.S* noalias noundef %0, %struct.S* noalias noundef %1) +// CHECK: define internal void [[OMP_INIT1]](%struct.S* noalias %0, %struct.S* noalias %1) // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64( -// CHECK: define internal void @[[RED_FINI2]](i8* noundef %0) +// CHECK: define internal void @[[RED_FINI2]](i8* %0) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: call void @ // CHECK: ret void -// CHECK: define internal void @[[RED_COMB2]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB2]](i8* %0, i8* %1) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: call void [[OMP_COMB1]]( // CHECK: ret void -// CHECK: define internal void @[[RED_INIT3]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT3]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB3]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB3]](i8* %0, i8* %1) // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_INIT4]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}}) +// CHECK: define internal void @[[RED_INIT4]](i8* noalias %{{.+}}, i8* noalias %{{.+}}) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: store float 0.000000e+00, float* % // CHECK: ret void -// CHECK: define internal void @[[RED_COMB4]](i8* noundef %0, i8* noundef %1) +// CHECK: define internal void @[[RED_COMB4]](i8* %0, i8* %1) // CHECK: call i8* @__kmpc_threadprivate_cached( // CHECK: fadd float % // CHECK: store float %{{.+}}, float* % diff --git a/clang/test/OpenMP/taskloop_with_atomic_codegen.cpp b/clang/test/OpenMP/taskloop_with_atomic_codegen.cpp index d4d4419d1f563aed4b0689b4ca30c902e1f36afa..077908f5bc77f8ec9252349b5494b001e9ece864 100644 --- a/clang/test/OpenMP/taskloop_with_atomic_codegen.cpp +++ b/clang/test/OpenMP/taskloop_with_atomic_codegen.cpp @@ -23,7 +23,7 @@ int main() { } } -// CHECK: define internal noundef i32 @{{.+}}( +// CHECK: define internal i32 @{{.+}}( // Check that occupanices var is firstprivatized. // CHECK-DAG: atomicrmw add i32* [[FP_OCCUP:%.+]], i32 1 monotonic, align 4 // CHECK-DAG: [[FP_OCCUP]] = load i32*, i32** [[FP_OCCUP_ADDR:%[^,]+]], diff --git a/clang/test/OpenMP/teams_codegen.cpp b/clang/test/OpenMP/teams_codegen.cpp index 3a1b84cc48f610d9d91b1dd3a41db05fc208671d..37a87fc250035b05617406365dbf66091e211a20 100644 --- a/clang/test/OpenMP/teams_codegen.cpp +++ b/clang/test/OpenMP/teams_codegen.cpp @@ -299,7 +299,7 @@ void foo() { #endif // CHECK1-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali -// CHECK1-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[COMP:%.*]] = alloca i32, align 4 @@ -577,7 +577,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31 -// CHECK1-SAME: (i64 noundef [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 @@ -587,7 +587,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -603,7 +603,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37 -// CHECK1-SAME: (i64 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[COMP:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 @@ -613,7 +613,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -629,7 +629,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46 -// CHECK1-SAME: (i64 noundef [[LA:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 @@ -645,7 +645,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -661,7 +661,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53 -// CHECK1-SAME: (i64 noundef [[LA:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 @@ -677,7 +677,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -693,7 +693,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62 -// CHECK1-SAME: (i64 noundef [[GBLA:%.*]], i64 noundef [[A:%.*]], i64 noundef [[GBLB:%.*]], i64 noundef [[LC:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[GBLA:%.*]], i64 [[A:%.*]], i64 [[GBLB:%.*]], i64 [[LC:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[GBLA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -724,7 +724,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -740,7 +740,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71 -// CHECK1-SAME: (i64 noundef [[GBLC:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[GBLC:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[GBLC_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 @@ -762,7 +762,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -791,7 +791,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali -// CHECK2-SAME: (i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[COMP:%.*]] = alloca i32, align 4 @@ -1069,7 +1069,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31 -// CHECK2-SAME: (i64 noundef [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 @@ -1079,7 +1079,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1095,7 +1095,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37 -// CHECK2-SAME: (i64 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[COMP:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 @@ -1105,7 +1105,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1121,7 +1121,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46 -// CHECK2-SAME: (i64 noundef [[LA:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 @@ -1137,7 +1137,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1153,7 +1153,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53 -// CHECK2-SAME: (i64 noundef [[LA:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 @@ -1169,7 +1169,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1185,7 +1185,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62 -// CHECK2-SAME: (i64 noundef [[GBLA:%.*]], i64 noundef [[A:%.*]], i64 noundef [[GBLB:%.*]], i64 noundef [[LC:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[GBLA:%.*]], i64 [[A:%.*]], i64 [[GBLB:%.*]], i64 [[LC:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[GBLA_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -1216,7 +1216,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1232,7 +1232,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71 -// CHECK2-SAME: (i64 noundef [[GBLC:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[GBLC:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[GBLC_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 @@ -1254,7 +1254,7 @@ void foo() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1283,7 +1283,7 @@ void foo() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali -// CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[COMP:%.*]] = alloca i32, align 4 @@ -1546,7 +1546,7 @@ void foo() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31 -// CHECK3-SAME: (i32 noundef [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 @@ -1555,7 +1555,7 @@ void foo() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1571,7 +1571,7 @@ void foo() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37 -// CHECK3-SAME: (i32 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[COMP:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 @@ -1580,7 +1580,7 @@ void foo() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1596,7 +1596,7 @@ void foo() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46 -// CHECK3-SAME: (i32 noundef [[LA:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[LA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 @@ -1610,7 +1610,7 @@ void foo() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1626,7 +1626,7 @@ void foo() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53 -// CHECK3-SAME: (i32 noundef [[LA:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[LA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 @@ -1640,7 +1640,7 @@ void foo() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1656,7 +1656,7 @@ void foo() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62 -// CHECK3-SAME: (i32 noundef [[GBLA:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[GBLB:%.*]], i32 noundef [[LC:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[GBLA:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[GBLB:%.*]], i32 [[LC:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[GBLA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1688,7 +1688,7 @@ void foo() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1704,7 +1704,7 @@ void foo() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71 -// CHECK3-SAME: (i32 noundef [[GBLC:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[GBLC:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[GBLC_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 @@ -1724,7 +1724,7 @@ void foo() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1753,7 +1753,7 @@ void foo() { // // // CHECK4-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali -// CHECK4-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[COMP:%.*]] = alloca i32, align 4 @@ -2016,7 +2016,7 @@ void foo() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31 -// CHECK4-SAME: (i32 noundef [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 @@ -2025,7 +2025,7 @@ void foo() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2041,7 +2041,7 @@ void foo() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37 -// CHECK4-SAME: (i32 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[COMP:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 @@ -2050,7 +2050,7 @@ void foo() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2066,7 +2066,7 @@ void foo() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46 -// CHECK4-SAME: (i32 noundef [[LA:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[LA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 @@ -2080,7 +2080,7 @@ void foo() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2096,7 +2096,7 @@ void foo() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53 -// CHECK4-SAME: (i32 noundef [[LA:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[LA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 @@ -2110,7 +2110,7 @@ void foo() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2126,7 +2126,7 @@ void foo() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62 -// CHECK4-SAME: (i32 noundef [[GBLA:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[GBLB:%.*]], i32 noundef [[LC:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[GBLA:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[GBLB:%.*]], i32 [[LC:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[GBLA_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2158,7 +2158,7 @@ void foo() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2174,7 +2174,7 @@ void foo() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71 -// CHECK4-SAME: (i32 noundef [[GBLC:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[GBLC:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[GBLC_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 @@ -2194,7 +2194,7 @@ void foo() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2327,7 +2327,7 @@ void foo() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 -// CHECK9-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* noundef nonnull align 4 dereferenceable(8) [[LA:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK9-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK9-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 8 @@ -2351,7 +2351,7 @@ void foo() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2367,7 +2367,7 @@ void foo() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 -// CHECK9-SAME: (%struct.SS.0* noundef nonnull align 8 dereferenceable(16) [[LB:%.*]], %struct.SS.0* noundef nonnull align 8 dereferenceable(16) [[GBLB:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (%struct.SS.0* nonnull align 8 dereferenceable(16) [[LB:%.*]], %struct.SS.0* nonnull align 8 dereferenceable(16) [[GBLB:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 // CHECK9-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 @@ -2392,7 +2392,7 @@ void foo() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2519,7 +2519,7 @@ void foo() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 -// CHECK10-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* noundef nonnull align 4 dereferenceable(8) [[LA:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK10-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK10-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 8 @@ -2543,7 +2543,7 @@ void foo() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2559,7 +2559,7 @@ void foo() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 -// CHECK10-SAME: (%struct.SS.0* noundef nonnull align 8 dereferenceable(16) [[LB:%.*]], %struct.SS.0* noundef nonnull align 8 dereferenceable(16) [[GBLB:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (%struct.SS.0* nonnull align 8 dereferenceable(16) [[LB:%.*]], %struct.SS.0* nonnull align 8 dereferenceable(16) [[GBLB:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 // CHECK10-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 @@ -2584,7 +2584,7 @@ void foo() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2709,7 +2709,7 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 -// CHECK11-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* noundef nonnull align 4 dereferenceable(8) [[LA:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK11-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK11-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 4 @@ -2732,7 +2732,7 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2748,7 +2748,7 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 -// CHECK11-SAME: (%struct.SS.0* noundef nonnull align 4 dereferenceable(12) [[LB:%.*]], %struct.SS.0* noundef nonnull align 4 dereferenceable(12) [[GBLB:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (%struct.SS.0* nonnull align 4 dereferenceable(12) [[LB:%.*]], %struct.SS.0* nonnull align 4 dereferenceable(12) [[GBLB:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 // CHECK11-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 @@ -2772,7 +2772,7 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2897,7 +2897,7 @@ void foo() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 -// CHECK12-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* noundef nonnull align 4 dereferenceable(8) [[LA:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK12-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK12-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 4 @@ -2920,7 +2920,7 @@ void foo() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2936,7 +2936,7 @@ void foo() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 -// CHECK12-SAME: (%struct.SS.0* noundef nonnull align 4 dereferenceable(12) [[LB:%.*]], %struct.SS.0* noundef nonnull align 4 dereferenceable(12) [[GBLB:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (%struct.SS.0* nonnull align 4 dereferenceable(12) [[LB:%.*]], %struct.SS.0* nonnull align 4 dereferenceable(12) [[GBLB:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 // CHECK12-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 @@ -2960,7 +2960,7 @@ void foo() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2986,12 +2986,12 @@ void foo() { // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(8) [[V]]) // CHECK17-NEXT: ret i32 [[CALL]] // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK17-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK17-NEXT: [[COMP:%.*]] = alloca i32, align 4 @@ -3077,7 +3077,7 @@ void foo() { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 -// CHECK17-SAME: (%struct.SS* noundef [[THIS:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK17-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 @@ -3094,7 +3094,7 @@ void foo() { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3110,7 +3110,7 @@ void foo() { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 -// CHECK17-SAME: (%struct.SS* noundef [[THIS:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK17-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK17-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 @@ -3129,7 +3129,7 @@ void foo() { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3155,12 +3155,12 @@ void foo() { // CHECK18-SAME: () #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(8) [[V]]) // CHECK18-NEXT: ret i32 [[CALL]] // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK18-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK18-NEXT: [[COMP:%.*]] = alloca i32, align 4 @@ -3246,7 +3246,7 @@ void foo() { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 -// CHECK18-SAME: (%struct.SS* noundef [[THIS:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK18-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 @@ -3263,7 +3263,7 @@ void foo() { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3279,7 +3279,7 @@ void foo() { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 -// CHECK18-SAME: (%struct.SS* noundef [[THIS:%.*]], i64 noundef [[COMP:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK18-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK18-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 @@ -3298,7 +3298,7 @@ void foo() { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3324,12 +3324,12 @@ void foo() { // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(8) [[V]]) // CHECK19-NEXT: ret i32 [[CALL]] // // // CHECK19-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK19-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK19-NEXT: [[COMP:%.*]] = alloca i32, align 4 @@ -3413,7 +3413,7 @@ void foo() { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 -// CHECK19-SAME: (%struct.SS* noundef [[THIS:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK19-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 @@ -3429,7 +3429,7 @@ void foo() { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3445,7 +3445,7 @@ void foo() { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 -// CHECK19-SAME: (%struct.SS* noundef [[THIS:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK19-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK19-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 @@ -3463,7 +3463,7 @@ void foo() { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3489,12 +3489,12 @@ void foo() { // CHECK20-SAME: () #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(8) [[V]]) // CHECK20-NEXT: ret i32 [[CALL]] // // // CHECK20-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK20-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK20-NEXT: [[COMP:%.*]] = alloca i32, align 4 @@ -3578,7 +3578,7 @@ void foo() { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 -// CHECK20-SAME: (%struct.SS* noundef [[THIS:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK20-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 @@ -3594,7 +3594,7 @@ void foo() { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3610,7 +3610,7 @@ void foo() { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 -// CHECK20-SAME: (%struct.SS* noundef [[THIS:%.*]], i32 noundef [[COMP:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK20-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK20-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 @@ -3628,7 +3628,7 @@ void foo() { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3651,7 +3651,7 @@ void foo() { // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 -// CHECK25-SAME: (i64 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 @@ -3661,7 +3661,7 @@ void foo() { // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3675,7 +3675,7 @@ void foo() { // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 -// CHECK25-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 // CHECK25-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 @@ -3684,7 +3684,7 @@ void foo() { // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3698,7 +3698,7 @@ void foo() { // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 -// CHECK26-SAME: (i64 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 @@ -3708,7 +3708,7 @@ void foo() { // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3722,7 +3722,7 @@ void foo() { // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 -// CHECK26-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 // CHECK26-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 @@ -3731,7 +3731,7 @@ void foo() { // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3745,7 +3745,7 @@ void foo() { // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 -// CHECK27-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 @@ -3754,7 +3754,7 @@ void foo() { // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3768,7 +3768,7 @@ void foo() { // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 -// CHECK27-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 // CHECK27-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 @@ -3777,7 +3777,7 @@ void foo() { // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3791,7 +3791,7 @@ void foo() { // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 -// CHECK28-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 @@ -3800,7 +3800,7 @@ void foo() { // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3814,7 +3814,7 @@ void foo() { // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 -// CHECK28-SAME: (i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 // CHECK28-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 @@ -3823,7 +3823,7 @@ void foo() { // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3837,7 +3837,7 @@ void foo() { // // // CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 -// CHECK33-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK33-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3857,7 +3857,7 @@ void foo() { // // // CHECK33-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK33-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3871,7 +3871,7 @@ void foo() { // // // CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 -// CHECK33-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK33-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3890,7 +3890,7 @@ void foo() { // // // CHECK33-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK33-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3904,7 +3904,7 @@ void foo() { // // // CHECK34-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 -// CHECK34-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK34-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK34-NEXT: entry: // CHECK34-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK34-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3924,7 +3924,7 @@ void foo() { // // // CHECK34-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK34-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK34-NEXT: entry: // CHECK34-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK34-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3938,7 +3938,7 @@ void foo() { // // // CHECK34-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 -// CHECK34-SAME: (i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK34-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK34-NEXT: entry: // CHECK34-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK34-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 @@ -3957,7 +3957,7 @@ void foo() { // // // CHECK34-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK34-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK34-NEXT: entry: // CHECK34-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK34-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3971,7 +3971,7 @@ void foo() { // // // CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 -// CHECK35-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK35-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK35-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -3988,7 +3988,7 @@ void foo() { // // // CHECK35-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK35-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK35-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK35-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4002,7 +4002,7 @@ void foo() { // // // CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 -// CHECK35-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK35-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK35-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4019,7 +4019,7 @@ void foo() { // // // CHECK35-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK35-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK35-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK35-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4033,7 +4033,7 @@ void foo() { // // // CHECK36-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 -// CHECK36-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK36-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK36-NEXT: entry: // CHECK36-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK36-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4050,7 +4050,7 @@ void foo() { // // // CHECK36-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK36-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK36-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK36-NEXT: entry: // CHECK36-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK36-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4064,7 +4064,7 @@ void foo() { // // // CHECK36-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 -// CHECK36-SAME: (i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i8** noundef [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK36-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { // CHECK36-NEXT: entry: // CHECK36-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK36-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -4081,7 +4081,7 @@ void foo() { // // // CHECK36-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK36-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i8*** noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { +// CHECK36-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { // CHECK36-NEXT: entry: // CHECK36-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK36-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4102,7 +4102,7 @@ void foo() { // // // CHECK41-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK41-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK41-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK41-NEXT: entry: // CHECK41-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK41-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4119,7 +4119,7 @@ void foo() { // // // CHECK42-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK42-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK42-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK42-NEXT: entry: // CHECK42-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK42-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4136,7 +4136,7 @@ void foo() { // // // CHECK43-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK43-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK43-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK43-NEXT: entry: // CHECK43-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK43-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4153,7 +4153,7 @@ void foo() { // // // CHECK44-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK44-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK44-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK44-NEXT: entry: // CHECK44-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK44-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4161,3 +4161,4 @@ void foo() { // CHECK44-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 // CHECK44-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_codegen.cpp b/clang/test/OpenMP/teams_distribute_codegen.cpp index 2727e8e7b5b3e70b078607b3471048f6f8d7dd6a..d2e99882fd11b4750b6748a75ad7a211b561deef 100644 --- a/clang/test/OpenMP/teams_distribute_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_codegen.cpp @@ -176,7 +176,7 @@ int main (int argc, char **argv) { #endif // CK4 #endif // CHECK1-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -313,7 +313,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l29 -// CHECK1-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], i64 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], i64 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -336,7 +336,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -428,7 +428,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l35 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 8 @@ -441,7 +441,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -540,7 +540,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -677,7 +677,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l29 -// CHECK2-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], i64 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], i64 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -700,7 +700,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -792,7 +792,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l35 -// CHECK2-SAME: (i64 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 8 @@ -805,7 +805,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -904,7 +904,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -1037,7 +1037,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l29 -// CHECK3-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], i32 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], i32 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -1057,7 +1057,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1148,7 +1148,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l35 -// CHECK3-SAME: (i32 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 4 @@ -1160,7 +1160,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1258,7 +1258,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -1391,7 +1391,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l29 -// CHECK4-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], i32 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], i32 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -1411,7 +1411,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1502,7 +1502,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l35 -// CHECK4-SAME: (i32 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 4 @@ -1514,7 +1514,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1696,7 +1696,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -1712,7 +1712,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1898,7 +1898,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -1914,7 +1914,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2099,7 +2099,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -2114,7 +2114,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2298,7 +2298,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -2313,7 +2313,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2417,12 +2417,12 @@ int main (int argc, char **argv) { // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK17-NEXT: ret i32 [[CALL]] // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK17-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -2457,7 +2457,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK17-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -2467,7 +2467,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2545,12 +2545,12 @@ int main (int argc, char **argv) { // CHECK18-SAME: () #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK18-NEXT: ret i32 [[CALL]] // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK18-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -2585,7 +2585,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK18-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -2595,7 +2595,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2673,12 +2673,12 @@ int main (int argc, char **argv) { // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK19-NEXT: ret i32 [[CALL]] // // // CHECK19-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK19-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -2713,7 +2713,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK19-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2723,7 +2723,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2800,12 +2800,12 @@ int main (int argc, char **argv) { // CHECK20-SAME: () #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK20-NEXT: ret i32 [[CALL]] // // // CHECK20-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK20-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -2840,7 +2840,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK20-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2850,7 +2850,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2924,7 +2924,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@main -// CHECK25-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3007,7 +3007,7 @@ int main (int argc, char **argv) { // CHECK25-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK25: omp_offload.cont: // CHECK25-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP33]]) +// CHECK25-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP33]]) // CHECK25-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK25-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK25-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) @@ -3016,7 +3016,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK25-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK25-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -3032,7 +3032,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3127,7 +3127,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK25-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK25-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -3190,7 +3190,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK25-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK25-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -3210,7 +3210,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3284,7 +3284,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@main -// CHECK26-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3367,7 +3367,7 @@ int main (int argc, char **argv) { // CHECK26-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK26: omp_offload.cont: // CHECK26-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK26-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP33]]) +// CHECK26-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP33]]) // CHECK26-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK26-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK26-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) @@ -3376,7 +3376,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK26-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK26-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -3392,7 +3392,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3487,7 +3487,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK26-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK26-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -3550,7 +3550,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK26-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK26-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -3570,7 +3570,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3644,7 +3644,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@main -// CHECK27-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3726,7 +3726,7 @@ int main (int argc, char **argv) { // CHECK27-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK27: omp_offload.cont: // CHECK27-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP33]]) +// CHECK27-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP33]]) // CHECK27-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK27-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK27-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) @@ -3735,7 +3735,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK27-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK27-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -3750,7 +3750,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3844,7 +3844,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK27-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK27-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -3905,7 +3905,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK27-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK27-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -3923,7 +3923,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3996,7 +3996,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@main -// CHECK28-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4078,7 +4078,7 @@ int main (int argc, char **argv) { // CHECK28-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK28: omp_offload.cont: // CHECK28-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK28-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP33]]) +// CHECK28-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP33]]) // CHECK28-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK28-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK28-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) @@ -4087,7 +4087,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK28-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK28-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -4102,7 +4102,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4196,7 +4196,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK28-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK28-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -4257,7 +4257,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK28-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK28-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -4275,7 +4275,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4346,3 +4346,4 @@ int main (int argc, char **argv) { // CHECK28-NEXT: call void @__tgt_register_requires(i64 1) // CHECK28-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp b/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp index 722e5b31549525ec152753829d3e04055128c98e..981d86837eea8e689aa1f6d22f3c76f05eb2d79a 100644 --- a/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_collapse_codegen.cpp @@ -101,12 +101,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -143,7 +143,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -153,7 +153,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -245,12 +245,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -287,7 +287,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -297,7 +297,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -389,12 +389,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -431,7 +431,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -441,7 +441,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -531,12 +531,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -573,7 +573,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -583,7 +583,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -670,7 +670,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -795,7 +795,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -804,7 +804,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -826,7 +826,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -974,7 +974,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -1006,7 +1006,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK9-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -1016,7 +1016,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1104,7 +1104,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1229,7 +1229,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: // CHECK10-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -1238,7 +1238,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -1260,7 +1260,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1408,7 +1408,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -1440,7 +1440,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK10-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -1450,7 +1450,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1538,7 +1538,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1660,7 +1660,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -1669,7 +1669,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -1689,7 +1689,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1835,7 +1835,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -1867,7 +1867,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK11-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -1877,7 +1877,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1963,7 +1963,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2085,7 +2085,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: // CHECK12-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -2094,7 +2094,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -2114,7 +2114,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2260,7 +2260,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -2292,7 +2292,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l68 -// CHECK12-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -2302,7 +2302,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2386,3 +2386,4 @@ int main (int argc, char **argv) { // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp index c96c33af7ede85c8af23fda2f140d381e1de304b..a16577e47b56609bed1b0b86ff42fdebd9ec1405 100644 --- a/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp @@ -135,12 +135,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -221,7 +221,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -231,7 +231,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -299,7 +299,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -309,7 +309,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -377,7 +377,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -387,7 +387,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -482,12 +482,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -568,7 +568,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -578,7 +578,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -646,7 +646,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -656,7 +656,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -724,7 +724,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -734,7 +734,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -829,12 +829,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -915,7 +915,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -925,7 +925,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -992,7 +992,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1002,7 +1002,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1069,7 +1069,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1079,7 +1079,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1173,12 +1173,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -1259,7 +1259,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1269,7 +1269,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1336,7 +1336,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1346,7 +1346,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1413,7 +1413,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1423,7 +1423,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1514,7 +1514,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1725,7 +1725,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT32]] // CHECK9: omp_offload.cont32: // CHECK9-NEXT: [[TMP93:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP93]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP93]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP94:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP94]]) @@ -1734,7 +1734,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -1750,7 +1750,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1845,7 +1845,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -1861,7 +1861,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1956,7 +1956,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -1980,7 +1980,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2096,7 +2096,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -2171,7 +2171,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -2181,7 +2181,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2248,7 +2248,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -2258,7 +2258,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2325,7 +2325,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -2335,7 +2335,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2426,7 +2426,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2637,7 +2637,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT32]] // CHECK10: omp_offload.cont32: // CHECK10-NEXT: [[TMP93:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP93]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP93]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP94:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP94]]) @@ -2646,7 +2646,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2662,7 +2662,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2757,7 +2757,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2773,7 +2773,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2868,7 +2868,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2892,7 +2892,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3008,7 +3008,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -3083,7 +3083,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3093,7 +3093,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3160,7 +3160,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3170,7 +3170,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3237,7 +3237,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3247,7 +3247,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3338,7 +3338,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3548,7 +3548,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT30]] // CHECK11: omp_offload.cont30: // CHECK11-NEXT: [[TMP95:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP95]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP95]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP96:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP96]]) @@ -3557,7 +3557,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -3572,7 +3572,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3666,7 +3666,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -3681,7 +3681,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3775,7 +3775,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -3797,7 +3797,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3911,7 +3911,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -3986,7 +3986,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -3996,7 +3996,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4062,7 +4062,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -4072,7 +4072,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4138,7 +4138,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -4148,7 +4148,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4238,7 +4238,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4448,7 +4448,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT30]] // CHECK12: omp_offload.cont30: // CHECK12-NEXT: [[TMP95:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP95]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP95]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP96:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP96]]) @@ -4457,7 +4457,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -4472,7 +4472,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4566,7 +4566,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -4581,7 +4581,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4675,7 +4675,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -4697,7 +4697,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4811,7 +4811,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -4886,7 +4886,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -4896,7 +4896,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4962,7 +4962,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -4972,7 +4972,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5038,7 +5038,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -5048,7 +5048,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp index 3fe88b5ed3e5ee6db6fcffd260c9d09af68a1a72..79626ef5333f542a3670cd67bc521a098ead2600 100644 --- a/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp @@ -145,33 +145,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -184,7 +184,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -195,14 +195,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -210,12 +210,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -223,7 +223,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -231,7 +231,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -250,7 +250,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -324,12 +324,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -361,7 +361,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -409,17 +409,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -478,14 +478,14 @@ int main() { // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -493,17 +493,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -511,17 +511,17 @@ int main() { // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -540,14 +540,14 @@ int main() { // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -607,17 +607,17 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP32]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -630,7 +630,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -650,7 +650,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -659,17 +659,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -677,12 +677,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -709,7 +709,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -757,18 +757,18 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -825,14 +825,14 @@ int main() { // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -840,7 +840,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -848,22 +848,22 @@ int main() { // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -875,7 +875,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -891,7 +891,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -910,7 +910,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -937,33 +937,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -976,7 +976,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -987,14 +987,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1002,12 +1002,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1015,7 +1015,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1023,7 +1023,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1042,7 +1042,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -1116,12 +1116,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK2-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1153,7 +1153,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1201,17 +1201,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1270,14 +1270,14 @@ int main() { // CHECK2-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done13: @@ -1285,17 +1285,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1303,17 +1303,17 @@ int main() { // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // @@ -1332,14 +1332,14 @@ int main() { // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1399,17 +1399,17 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP32]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1422,7 +1422,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1442,7 +1442,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1451,17 +1451,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1469,12 +1469,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK2-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1501,7 +1501,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1549,18 +1549,18 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -1617,14 +1617,14 @@ int main() { // CHECK2-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done13: @@ -1632,7 +1632,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1640,22 +1640,22 @@ int main() { // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1667,7 +1667,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1683,7 +1683,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1702,7 +1702,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1729,33 +1729,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1768,7 +1768,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1779,14 +1779,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1794,12 +1794,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1807,7 +1807,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1815,7 +1815,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1834,7 +1834,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -1906,12 +1906,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -1939,7 +1939,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1985,17 +1985,17 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done3: -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2052,14 +2052,14 @@ int main() { // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -2067,17 +2067,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2085,17 +2085,17 @@ int main() { // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -2114,14 +2114,14 @@ int main() { // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2180,17 +2180,17 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP32]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2203,7 +2203,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2223,7 +2223,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2232,17 +2232,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2250,12 +2250,12 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2280,7 +2280,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2327,18 +2327,18 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done4: // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -2393,14 +2393,14 @@ int main() { // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -2408,7 +2408,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -2416,22 +2416,22 @@ int main() { // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2443,7 +2443,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2459,7 +2459,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -2478,7 +2478,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2505,33 +2505,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2544,7 +2544,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2555,14 +2555,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2570,12 +2570,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -2583,7 +2583,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -2591,7 +2591,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2610,7 +2610,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -2682,12 +2682,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK4-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2715,7 +2715,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2761,17 +2761,17 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done3: -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2828,14 +2828,14 @@ int main() { // CHECK4-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done11: @@ -2843,17 +2843,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2861,17 +2861,17 @@ int main() { // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // @@ -2890,14 +2890,14 @@ int main() { // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2956,17 +2956,17 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP32]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2979,7 +2979,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2999,7 +2999,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -3008,17 +3008,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3026,12 +3026,12 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK4-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3056,7 +3056,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3103,18 +3103,18 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done4: // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -3169,14 +3169,14 @@ int main() { // CHECK4-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done12: @@ -3184,7 +3184,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3192,22 +3192,22 @@ int main() { // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3219,7 +3219,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3235,7 +3235,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3254,7 +3254,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3281,33 +3281,33 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3320,7 +3320,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3331,14 +3331,14 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3346,12 +3346,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3359,7 +3359,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -3367,7 +3367,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3386,7 +3386,7 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // @@ -3397,12 +3397,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 @@ -3436,7 +3436,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3503,7 +3503,7 @@ int main() { // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3538,33 +3538,33 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3577,7 +3577,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3588,14 +3588,14 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3603,12 +3603,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3616,7 +3616,7 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: @@ -3624,7 +3624,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3643,7 +3643,7 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // @@ -3654,12 +3654,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK10-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK10-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 @@ -3693,7 +3693,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3760,7 +3760,7 @@ int main() { // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3791,3 +3791,4 @@ int main() { // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp index 72ba06295cec79727365a5f9613f4fa37d25ec86..4ab3029b6156fda2dbf0c0714da205e9567e5ba2 100644 --- a/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp @@ -151,12 +151,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -178,7 +178,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -258,7 +258,7 @@ int main() { // CHECK1-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -310,12 +310,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK2-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -337,7 +337,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -417,7 +417,7 @@ int main() { // CHECK2-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -469,12 +469,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -504,7 +504,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -584,7 +584,7 @@ int main() { // CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -636,12 +636,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -671,7 +671,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -751,7 +751,7 @@ int main() { // CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -810,14 +810,14 @@ int main() { // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -882,7 +882,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -890,27 +890,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP39]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -918,12 +918,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -948,7 +948,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -993,13 +993,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -1089,14 +1089,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -1104,12 +1104,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1128,14 +1128,14 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1195,17 +1195,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP32]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1216,7 +1216,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1230,7 +1230,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1239,17 +1239,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1257,12 +1257,12 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1284,7 +1284,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1325,13 +1325,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -1419,14 +1419,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done14: @@ -1434,17 +1434,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1455,7 +1455,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1469,7 +1469,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1505,14 +1505,14 @@ int main() { // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1577,7 +1577,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1585,27 +1585,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP39]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1613,12 +1613,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1643,7 +1643,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1688,13 +1688,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK10-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -1784,14 +1784,14 @@ int main() { // CHECK10-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done15: @@ -1799,12 +1799,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -1823,14 +1823,14 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1890,17 +1890,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP32]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1911,7 +1911,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1925,7 +1925,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1934,17 +1934,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1952,12 +1952,12 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1979,7 +1979,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2020,13 +2020,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK10-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -2114,14 +2114,14 @@ int main() { // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i64 4, i1 false) // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done14: @@ -2129,17 +2129,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2150,7 +2150,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2164,7 +2164,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2200,14 +2200,14 @@ int main() { // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -2270,7 +2270,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2278,27 +2278,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP39]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2306,12 +2306,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2334,7 +2334,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2379,13 +2379,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -2473,14 +2473,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -2488,12 +2488,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2512,14 +2512,14 @@ int main() { // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2578,17 +2578,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP32]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2599,7 +2599,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2613,7 +2613,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2622,17 +2622,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2640,12 +2640,12 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2666,7 +2666,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2707,13 +2707,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -2799,14 +2799,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -2814,17 +2814,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2835,7 +2835,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2849,7 +2849,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2885,14 +2885,14 @@ int main() { // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -2955,7 +2955,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2963,27 +2963,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP39]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2991,12 +2991,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3019,7 +3019,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3064,13 +3064,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -3158,14 +3158,14 @@ int main() { // CHECK12-NEXT: store i32 [[TMP35]], i32* [[TMP4]], align 4 // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done14: @@ -3173,12 +3173,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // @@ -3197,14 +3197,14 @@ int main() { // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3263,17 +3263,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP32]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3284,7 +3284,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3298,7 +3298,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3307,17 +3307,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3325,12 +3325,12 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3351,7 +3351,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3392,13 +3392,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -3484,14 +3484,14 @@ int main() { // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP32]], i8* align 4 [[TMP33]], i32 4, i1 false) // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done13: @@ -3499,17 +3499,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3520,7 +3520,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3534,7 +3534,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3548,3 +3548,4 @@ int main() { // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp index 6911d953212cc2a18099f1cff4164b627ea2888a..c31965a4c645723b13f18553b41bea7328518dd8 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp @@ -176,7 +176,7 @@ int main (int argc, char **argv) { #endif // CK4 #endif // CHECK1-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -312,7 +312,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28 -// CHECK1-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], i64 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], i64 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -335,7 +335,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -423,7 +423,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -540,7 +540,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l35 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 8 @@ -553,7 +553,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -641,7 +641,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -750,7 +750,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -886,7 +886,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28 -// CHECK2-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], i64 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], i64 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -909,7 +909,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -997,7 +997,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1114,7 +1114,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l35 -// CHECK2-SAME: (i64 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 8 @@ -1127,7 +1127,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1215,7 +1215,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1324,7 +1324,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -1456,7 +1456,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28 -// CHECK3-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], i32 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], i32 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -1476,7 +1476,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1562,7 +1562,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1676,7 +1676,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l35 -// CHECK3-SAME: (i32 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 4 @@ -1688,7 +1688,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1774,7 +1774,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1880,7 +1880,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -2012,7 +2012,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28 -// CHECK4-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], i32 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], i32 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -2032,7 +2032,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2118,7 +2118,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2232,7 +2232,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l35 -// CHECK4-SAME: (i32 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 4 @@ -2244,7 +2244,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2330,7 +2330,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2520,7 +2520,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2536,7 +2536,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2627,7 +2627,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2823,7 +2823,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2839,7 +2839,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2930,7 +2930,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3125,7 +3125,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -3140,7 +3140,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3229,7 +3229,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3421,7 +3421,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -3436,7 +3436,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3525,7 +3525,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3637,12 +3637,12 @@ int main (int argc, char **argv) { // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK17-NEXT: ret i32 [[CALL]] // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK17-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -3677,7 +3677,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK17-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -3687,7 +3687,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3750,7 +3750,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3838,12 +3838,12 @@ int main (int argc, char **argv) { // CHECK18-SAME: () #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK18-NEXT: ret i32 [[CALL]] // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK18-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -3878,7 +3878,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK18-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -3888,7 +3888,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3951,7 +3951,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4039,12 +4039,12 @@ int main (int argc, char **argv) { // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK19-NEXT: ret i32 [[CALL]] // // // CHECK19-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK19-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -4079,7 +4079,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK19-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -4089,7 +4089,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4150,7 +4150,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4235,12 +4235,12 @@ int main (int argc, char **argv) { // CHECK20-SAME: () #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK20-NEXT: ret i32 [[CALL]] // // // CHECK20-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK20-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -4275,7 +4275,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l109 -// CHECK20-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -4285,7 +4285,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4346,7 +4346,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4428,7 +4428,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@main -// CHECK25-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4511,7 +4511,7 @@ int main (int argc, char **argv) { // CHECK25-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK25: omp_offload.cont: // CHECK25-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP33]]) +// CHECK25-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP33]]) // CHECK25-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK25-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK25-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) @@ -4520,7 +4520,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK25-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK25-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -4536,7 +4536,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4627,7 +4627,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4732,7 +4732,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK25-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK25-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -4794,7 +4794,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK25-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK25-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -4814,7 +4814,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4877,7 +4877,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4961,7 +4961,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@main -// CHECK26-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -5044,7 +5044,7 @@ int main (int argc, char **argv) { // CHECK26-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK26: omp_offload.cont: // CHECK26-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK26-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP33]]) +// CHECK26-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP33]]) // CHECK26-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK26-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK26-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) @@ -5053,7 +5053,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK26-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK26-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -5069,7 +5069,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5160,7 +5160,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5265,7 +5265,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK26-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK26-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -5327,7 +5327,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK26-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK26-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -5347,7 +5347,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5410,7 +5410,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5494,7 +5494,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@main -// CHECK27-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -5576,7 +5576,7 @@ int main (int argc, char **argv) { // CHECK27-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK27: omp_offload.cont: // CHECK27-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP33]]) +// CHECK27-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP33]]) // CHECK27-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK27-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK27-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) @@ -5585,7 +5585,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK27-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK27-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -5600,7 +5600,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5689,7 +5689,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5791,7 +5791,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK27-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK27-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -5851,7 +5851,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK27-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK27-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -5869,7 +5869,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5930,7 +5930,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6011,7 +6011,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@main -// CHECK28-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -6093,7 +6093,7 @@ int main (int argc, char **argv) { // CHECK28-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK28: omp_offload.cont: // CHECK28-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK28-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP33]]) +// CHECK28-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP33]]) // CHECK28-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK28-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK28-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) @@ -6102,7 +6102,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 -// CHECK28-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK28-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -6117,7 +6117,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6206,7 +6206,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6308,7 +6308,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK28-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK28-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -6368,7 +6368,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l151 -// CHECK28-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK28-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -6386,7 +6386,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6447,7 +6447,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp index 0bf3dc9bf20930ba4eb8aca6d4615249be36c3b3..e30c9ac1daea3b802175013496c84a81611f0a6c 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp @@ -106,12 +106,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -148,7 +148,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -158,7 +158,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -223,7 +223,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -325,12 +325,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -367,7 +367,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -377,7 +377,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -442,7 +442,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -544,12 +544,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -586,7 +586,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -596,7 +596,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -659,7 +659,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -757,12 +757,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -799,7 +799,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -809,7 +809,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -872,7 +872,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -967,7 +967,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1092,7 +1092,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -1101,7 +1101,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -1123,7 +1123,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1235,7 +1235,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1391,7 +1391,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -1423,7 +1423,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 -// CHECK9-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -1433,7 +1433,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1498,7 +1498,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1596,7 +1596,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1721,7 +1721,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: // CHECK10-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -1730,7 +1730,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -1752,7 +1752,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1864,7 +1864,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2020,7 +2020,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -2052,7 +2052,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 -// CHECK10-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -2062,7 +2062,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2127,7 +2127,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2225,7 +2225,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2347,7 +2347,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -2356,7 +2356,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -2376,7 +2376,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2490,7 +2490,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2646,7 +2646,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -2678,7 +2678,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 -// CHECK11-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -2688,7 +2688,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2751,7 +2751,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2845,7 +2845,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2967,7 +2967,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: // CHECK12-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -2976,7 +2976,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -2996,7 +2996,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3110,7 +3110,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3266,7 +3266,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -3298,7 +3298,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 -// CHECK12-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -3308,7 +3308,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3371,7 +3371,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3463,3 +3463,4 @@ int main (int argc, char **argv) { // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp index b9da52f3fe1403d1391569fc27fa64a6ee233f26..af03148b7feaed049f2822c36e118168003ccd0c 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp @@ -133,12 +133,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i64 [[TMP1]], [2 x i32]* [[A]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 -// CHECK1-SAME: (i64 noundef [[X:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[X:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -151,7 +151,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -217,7 +217,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -340,7 +340,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l34 -// CHECK1-SAME: (i64 noundef [[X:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[X:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -353,7 +353,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -419,7 +419,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -552,12 +552,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i64 [[TMP1]], [2 x i32]* [[A]]) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 -// CHECK2-SAME: (i64 noundef [[X:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[X:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -570,7 +570,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -636,7 +636,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -759,7 +759,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l34 -// CHECK2-SAME: (i64 noundef [[X:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[X:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -772,7 +772,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -838,7 +838,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -970,12 +970,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i32 [[TMP1]], [2 x i32]* [[A]]) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 -// CHECK3-SAME: (i32 noundef [[X:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 [[X:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -987,7 +987,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1051,7 +1051,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1170,7 +1170,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l34 -// CHECK3-SAME: (i32 noundef [[X:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[X:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -1182,7 +1182,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1246,7 +1246,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1375,12 +1375,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i32 [[TMP1]], [2 x i32]* [[A]]) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 -// CHECK4-SAME: (i32 noundef [[X:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32 [[X:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -1392,7 +1392,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1456,7 +1456,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1575,7 +1575,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l34 -// CHECK4-SAME: (i32 noundef [[X:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[X:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -1587,7 +1587,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1651,7 +1651,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1749,12 +1749,12 @@ int main() { // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[TMP0]], align 8 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46 -// CHECK9-SAME: (i64 noundef [[X:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[X:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1767,7 +1767,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1833,7 +1833,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1905,7 +1905,7 @@ int main() { // CHECK9-NEXT: store i32* [[I]], i32** [[TMP15]], align 8 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: store i32* [[TMP1]], i32** [[TMP16]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1942,12 +1942,12 @@ int main() { // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 // CHECK10-NEXT: store [2 x i32]* [[A]], [2 x i32]** [[TMP0]], align 8 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46 -// CHECK10-SAME: (i64 noundef [[X:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[X:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1960,7 +1960,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2026,7 +2026,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[A:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], i32* nonnull align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2098,7 +2098,7 @@ int main() { // CHECK10-NEXT: store i32* [[I]], i32** [[TMP15]], align 8 // CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK10-NEXT: store i32* [[TMP1]], i32** [[TMP16]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2125,3 +2125,4 @@ int main() { // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp index 9f90265dda7ad9fc4df9aefb6e7e33a7e4112d91..025ea7585edddf4edd591a00a9411560c68f1315 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp @@ -147,12 +147,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -233,7 +233,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -243,7 +243,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -306,7 +306,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -384,7 +384,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -394,7 +394,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -457,7 +457,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -535,7 +535,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -545,7 +545,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -628,7 +628,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -716,12 +716,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -802,7 +802,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -812,7 +812,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -875,7 +875,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -953,7 +953,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -963,7 +963,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1026,7 +1026,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1104,7 +1104,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1114,7 +1114,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1197,7 +1197,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1285,12 +1285,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -1371,7 +1371,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1381,7 +1381,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1442,7 +1442,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1517,7 +1517,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1527,7 +1527,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1588,7 +1588,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1663,7 +1663,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1673,7 +1673,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1754,7 +1754,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1839,12 +1839,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -1925,7 +1925,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1935,7 +1935,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1996,7 +1996,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2071,7 +2071,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2081,7 +2081,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2142,7 +2142,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2217,7 +2217,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2227,7 +2227,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2308,7 +2308,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2390,7 +2390,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2618,7 +2618,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK9: omp_offload.cont33: // CHECK9-NEXT: [[TMP101:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP101]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP101]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP102:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP102]]) @@ -2627,7 +2627,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2643,7 +2643,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2734,7 +2734,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2839,7 +2839,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2855,7 +2855,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2946,7 +2946,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3051,7 +3051,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK9-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -3078,7 +3078,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3202,7 +3202,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3310,7 +3310,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -3400,7 +3400,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3410,7 +3410,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3473,7 +3473,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3550,7 +3550,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3560,7 +3560,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3623,7 +3623,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3700,7 +3700,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94 -// CHECK9-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -3721,7 +3721,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3813,7 +3813,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3900,7 +3900,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4128,7 +4128,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK10: omp_offload.cont33: // CHECK10-NEXT: [[TMP101:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP101]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP101]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP102:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP102]]) @@ -4137,7 +4137,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -4153,7 +4153,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4244,7 +4244,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4349,7 +4349,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -4365,7 +4365,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4456,7 +4456,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4561,7 +4561,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK10-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -4588,7 +4588,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4712,7 +4712,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4820,7 +4820,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -4910,7 +4910,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -4920,7 +4920,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4983,7 +4983,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5060,7 +5060,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -5070,7 +5070,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5133,7 +5133,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5210,7 +5210,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94 -// CHECK10-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -5231,7 +5231,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5323,7 +5323,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5410,7 +5410,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -5636,7 +5636,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT30]] // CHECK11: omp_offload.cont30: // CHECK11-NEXT: [[TMP103:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP103]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP103]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP104:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP104]]) @@ -5645,7 +5645,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -5660,7 +5660,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5749,7 +5749,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5851,7 +5851,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -5866,7 +5866,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5955,7 +5955,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6057,7 +6057,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK11-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -6081,7 +6081,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6201,7 +6201,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6305,7 +6305,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -6394,7 +6394,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -6404,7 +6404,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6465,7 +6465,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6539,7 +6539,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -6549,7 +6549,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6610,7 +6610,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6684,7 +6684,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94 -// CHECK11-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -6703,7 +6703,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6791,7 +6791,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6874,7 +6874,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -7100,7 +7100,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT30]] // CHECK12: omp_offload.cont30: // CHECK12-NEXT: [[TMP103:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP103]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP103]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP104:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP104]]) @@ -7109,7 +7109,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -7124,7 +7124,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7213,7 +7213,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7315,7 +7315,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l111 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -7330,7 +7330,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7419,7 +7419,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7521,7 +7521,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 -// CHECK12-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -7545,7 +7545,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7665,7 +7665,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7769,7 +7769,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -7858,7 +7858,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -7868,7 +7868,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7929,7 +7929,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8003,7 +8003,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -8013,7 +8013,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8074,7 +8074,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8148,7 +8148,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l94 -// CHECK12-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -8167,7 +8167,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8255,7 +8255,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8336,3 +8336,4 @@ int main (int argc, char **argv) { // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp index 282c3640c1b3a9047d2ee7553b7a6f0cc88f905e..cb8e73661ba8b98cb54834f93457181c144c2570 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp @@ -179,33 +179,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -218,7 +218,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -229,14 +229,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -244,12 +244,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -257,7 +257,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -265,7 +265,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -284,7 +284,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -358,12 +358,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -395,7 +395,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -445,17 +445,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -507,14 +507,14 @@ int main() { // CHECK1-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done11: @@ -522,17 +522,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -540,22 +540,22 @@ int main() { // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -613,17 +613,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done6: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -682,14 +682,14 @@ int main() { // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done15: @@ -711,14 +711,14 @@ int main() { // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -778,17 +778,17 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP32]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -801,7 +801,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -821,7 +821,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -830,17 +830,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -848,12 +848,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -880,7 +880,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -929,18 +929,18 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -990,14 +990,14 @@ int main() { // CHECK1-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done11: @@ -1005,7 +1005,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1013,12 +1013,12 @@ int main() { // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1076,18 +1076,18 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done6: // CHECK1-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK1-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -1144,14 +1144,14 @@ int main() { // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done15: @@ -1159,17 +1159,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1181,7 +1181,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1197,7 +1197,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1216,7 +1216,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1243,33 +1243,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1282,7 +1282,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1293,14 +1293,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1308,12 +1308,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1321,7 +1321,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1329,7 +1329,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1348,7 +1348,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -1422,12 +1422,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK2-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1459,7 +1459,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1509,17 +1509,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1571,14 +1571,14 @@ int main() { // CHECK2-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done11: @@ -1586,17 +1586,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1604,22 +1604,22 @@ int main() { // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1677,17 +1677,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done6: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1746,14 +1746,14 @@ int main() { // CHECK2-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done15: @@ -1775,14 +1775,14 @@ int main() { // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1842,17 +1842,17 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP32]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1865,7 +1865,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1885,7 +1885,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1894,17 +1894,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1912,12 +1912,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK2-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1944,7 +1944,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1993,18 +1993,18 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -2054,14 +2054,14 @@ int main() { // CHECK2-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done11: @@ -2069,7 +2069,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -2077,12 +2077,12 @@ int main() { // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2140,18 +2140,18 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done6: // CHECK2-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK2-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -2208,14 +2208,14 @@ int main() { // CHECK2-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done15: @@ -2223,17 +2223,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2245,7 +2245,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2261,7 +2261,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -2280,7 +2280,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2307,33 +2307,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2346,7 +2346,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2357,14 +2357,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2372,12 +2372,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -2385,7 +2385,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -2393,7 +2393,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2412,7 +2412,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -2484,12 +2484,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2517,7 +2517,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2565,17 +2565,17 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done3: -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2623,14 +2623,14 @@ int main() { // CHECK3-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done8: @@ -2638,17 +2638,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2656,22 +2656,22 @@ int main() { // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2725,17 +2725,17 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done3: -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2792,14 +2792,14 @@ int main() { // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -2821,14 +2821,14 @@ int main() { // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2887,17 +2887,17 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP32]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2910,7 +2910,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2930,7 +2930,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2939,17 +2939,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2957,12 +2957,12 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2987,7 +2987,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3035,18 +3035,18 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done4: // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -3093,14 +3093,14 @@ int main() { // CHECK3-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done10: @@ -3108,7 +3108,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3116,12 +3116,12 @@ int main() { // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3176,18 +3176,18 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done4: // CHECK3-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -3242,14 +3242,14 @@ int main() { // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -3257,17 +3257,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3279,7 +3279,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3295,7 +3295,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3314,7 +3314,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3341,33 +3341,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3380,7 +3380,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3391,14 +3391,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3406,12 +3406,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -3419,7 +3419,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -3427,7 +3427,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3446,7 +3446,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -3518,12 +3518,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99 -// CHECK4-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3551,7 +3551,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3599,17 +3599,17 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done3: -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3657,14 +3657,14 @@ int main() { // CHECK4-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done8: @@ -3672,17 +3672,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -3690,22 +3690,22 @@ int main() { // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3759,17 +3759,17 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done3: -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3826,14 +3826,14 @@ int main() { // CHECK4-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done11: @@ -3855,14 +3855,14 @@ int main() { // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3921,17 +3921,17 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP32]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -3944,7 +3944,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -3964,7 +3964,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -3973,17 +3973,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3991,12 +3991,12 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK4-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -4021,7 +4021,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4069,18 +4069,18 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done4: // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -4127,14 +4127,14 @@ int main() { // CHECK4-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done10: @@ -4142,7 +4142,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -4150,12 +4150,12 @@ int main() { // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4210,18 +4210,18 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done4: // CHECK4-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -4276,14 +4276,14 @@ int main() { // CHECK4-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done12: @@ -4291,17 +4291,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4313,7 +4313,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4329,7 +4329,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -4348,7 +4348,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4375,33 +4375,33 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4414,7 +4414,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4425,14 +4425,14 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4440,12 +4440,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4453,7 +4453,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -4461,7 +4461,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4480,7 +4480,7 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // @@ -4491,12 +4491,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 @@ -4530,7 +4530,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4617,7 +4617,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4694,7 +4694,7 @@ int main() { // CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -4729,33 +4729,33 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4768,7 +4768,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4779,14 +4779,14 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4794,12 +4794,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4807,7 +4807,7 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: @@ -4815,7 +4815,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4834,7 +4834,7 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // @@ -4845,12 +4845,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK10-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK10-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 @@ -4884,7 +4884,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4971,7 +4971,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5048,7 +5048,7 @@ int main() { // CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -5079,3 +5079,4 @@ int main() { // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp index 173e904adddff3f95b10b8ad6b4ecbfbba384d86..77700887dab514aeeaa733c5f66cc4d82fe35c09 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp @@ -145,7 +145,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -205,7 +205,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -282,7 +282,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -347,7 +347,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -476,7 +476,7 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK1: omp_offload.cont7: // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -488,7 +488,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -548,7 +548,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -626,7 +626,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -691,7 +691,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -762,7 +762,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 -// CHECK1-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -784,7 +784,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -861,7 +861,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -932,7 +932,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK1-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1000,7 +1000,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1060,7 +1060,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1138,7 +1138,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1203,7 +1203,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1274,7 +1274,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 -// CHECK1-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -1296,7 +1296,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1373,7 +1373,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1482,7 +1482,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1542,7 +1542,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1619,7 +1619,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1684,7 +1684,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1813,7 +1813,7 @@ int main() { // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK2: omp_offload.cont7: // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -1825,7 +1825,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1885,7 +1885,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1963,7 +1963,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2028,7 +2028,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2099,7 +2099,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 -// CHECK2-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -2121,7 +2121,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2198,7 +2198,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2269,7 +2269,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK2-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -2337,7 +2337,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2397,7 +2397,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2475,7 +2475,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2540,7 +2540,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2611,7 +2611,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 -// CHECK2-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -2633,7 +2633,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2710,7 +2710,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2819,7 +2819,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2879,7 +2879,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2956,7 +2956,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3021,7 +3021,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3150,7 +3150,7 @@ int main() { // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK5: omp_offload.cont7: // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK5-NEXT: ret i32 [[CALL]] // // @@ -3162,7 +3162,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3222,7 +3222,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3300,7 +3300,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3365,7 +3365,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3436,7 +3436,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 -// CHECK5-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -3458,7 +3458,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3535,7 +3535,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3606,7 +3606,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK5-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK5-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -3674,7 +3674,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3734,7 +3734,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3812,7 +3812,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3877,7 +3877,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3948,7 +3948,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 -// CHECK5-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -3970,7 +3970,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4047,7 +4047,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4156,7 +4156,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4216,7 +4216,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4293,7 +4293,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4358,7 +4358,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4487,7 +4487,7 @@ int main() { // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK6: omp_offload.cont7: // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK6-NEXT: ret i32 [[CALL]] // // @@ -4499,7 +4499,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4559,7 +4559,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4637,7 +4637,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4702,7 +4702,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4773,7 +4773,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 -// CHECK6-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -4795,7 +4795,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4872,7 +4872,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4943,7 +4943,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK6-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK6-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -5011,7 +5011,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5071,7 +5071,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5149,7 +5149,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5214,7 +5214,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5285,7 +5285,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 -// CHECK6-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -5307,7 +5307,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5384,7 +5384,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5493,7 +5493,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5553,7 +5553,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5630,7 +5630,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5695,7 +5695,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5824,7 +5824,7 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK9: omp_offload.cont7: // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK9-NEXT: ret i32 [[CALL]] // // @@ -5836,7 +5836,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5896,7 +5896,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5974,7 +5974,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6039,7 +6039,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6110,7 +6110,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 -// CHECK9-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -6132,7 +6132,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6209,7 +6209,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6280,7 +6280,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK9-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK9-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -6348,7 +6348,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6408,7 +6408,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6486,7 +6486,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6551,7 +6551,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6622,7 +6622,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 -// CHECK9-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -6644,7 +6644,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6721,7 +6721,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6830,7 +6830,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6890,7 +6890,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6967,7 +6967,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7032,7 +7032,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7161,7 +7161,7 @@ int main() { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK10: omp_offload.cont7: // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK10-NEXT: ret i32 [[CALL]] // // @@ -7173,7 +7173,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7233,7 +7233,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7311,7 +7311,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7376,7 +7376,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7447,7 +7447,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 -// CHECK10-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -7469,7 +7469,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7546,7 +7546,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7617,7 +7617,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK10-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK10-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -7685,7 +7685,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7745,7 +7745,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7823,7 +7823,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7888,7 +7888,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7959,7 +7959,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 -// CHECK10-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -7981,7 +7981,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8058,7 +8058,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8167,7 +8167,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8227,7 +8227,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8304,7 +8304,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8369,7 +8369,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8498,7 +8498,7 @@ int main() { // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK13: omp_offload.cont7: // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK13-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK13-NEXT: ret i32 [[CALL]] // // @@ -8510,7 +8510,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8570,7 +8570,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8648,7 +8648,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8713,7 +8713,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8784,7 +8784,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 -// CHECK13-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -8806,7 +8806,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8883,7 +8883,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8954,7 +8954,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK13-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK13-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -9022,7 +9022,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9082,7 +9082,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9160,7 +9160,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9225,7 +9225,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9296,7 +9296,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 -// CHECK13-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -9318,7 +9318,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9395,7 +9395,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9504,7 +9504,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9564,7 +9564,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9641,7 +9641,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9706,7 +9706,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9835,7 +9835,7 @@ int main() { // CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK14: omp_offload.cont7: // CHECK14-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK14-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK14-NEXT: ret i32 [[CALL]] // // @@ -9847,7 +9847,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9907,7 +9907,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9985,7 +9985,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10050,7 +10050,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10121,7 +10121,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l97 -// CHECK14-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -10143,7 +10143,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10220,7 +10220,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10291,7 +10291,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK14-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK14-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -10359,7 +10359,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10419,7 +10419,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10497,7 +10497,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10562,7 +10562,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10633,7 +10633,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l72 -// CHECK14-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -10655,7 +10655,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10732,7 +10732,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp index 5146e8b44f38e4e6cc3b06c92db61b1f4d166c82..6c454a91df19ae4491ebcf8674920015a9e7dbb7 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp @@ -189,12 +189,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -216,7 +216,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -313,7 +313,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -403,7 +403,7 @@ int main() { // CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -455,12 +455,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK2-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -482,7 +482,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -579,7 +579,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -669,7 +669,7 @@ int main() { // CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -721,12 +721,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -756,7 +756,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -851,7 +851,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -939,7 +939,7 @@ int main() { // CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -991,12 +991,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -1026,7 +1026,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1121,7 +1121,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1209,7 +1209,7 @@ int main() { // CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1268,14 +1268,14 @@ int main() { // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1340,7 +1340,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1348,27 +1348,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP39]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1376,12 +1376,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1406,7 +1406,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1451,13 +1451,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -1536,14 +1536,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP34]], i32* [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done12: @@ -1551,7 +1551,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1606,13 +1606,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -1702,14 +1702,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done16: @@ -1717,12 +1717,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1741,14 +1741,14 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1808,17 +1808,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP32]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1829,7 +1829,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1843,7 +1843,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1852,17 +1852,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1870,12 +1870,12 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1897,7 +1897,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1938,13 +1938,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -2021,14 +2021,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done11: @@ -2036,7 +2036,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2087,13 +2087,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -2181,14 +2181,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -2196,17 +2196,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2217,7 +2217,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2231,7 +2231,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2267,14 +2267,14 @@ int main() { // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -2339,7 +2339,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -2347,27 +2347,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP39]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2375,12 +2375,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2405,7 +2405,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2450,13 +2450,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK10-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -2535,14 +2535,14 @@ int main() { // CHECK10-NEXT: store i32 [[TMP34]], i32* [[TMP4]], align 4 // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done12: @@ -2550,7 +2550,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2605,13 +2605,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -2701,14 +2701,14 @@ int main() { // CHECK10-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done16: @@ -2716,12 +2716,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -2740,14 +2740,14 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -2807,17 +2807,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP32]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2828,7 +2828,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2842,7 +2842,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2851,17 +2851,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2869,12 +2869,12 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2896,7 +2896,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2937,13 +2937,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK10-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -3020,14 +3020,14 @@ int main() { // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i64 4, i1 false) // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done11: @@ -3035,7 +3035,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3086,13 +3086,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -3180,14 +3180,14 @@ int main() { // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done15: @@ -3195,17 +3195,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3216,7 +3216,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3230,7 +3230,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3266,14 +3266,14 @@ int main() { // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -3336,7 +3336,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -3344,27 +3344,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP39]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3372,12 +3372,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3400,7 +3400,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3445,13 +3445,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -3528,14 +3528,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP32]], i32* [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done12: @@ -3543,7 +3543,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3596,13 +3596,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -3690,14 +3690,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -3705,12 +3705,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -3729,14 +3729,14 @@ int main() { // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3795,17 +3795,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP32]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3816,7 +3816,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3830,7 +3830,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3839,17 +3839,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3857,12 +3857,12 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3883,7 +3883,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3924,13 +3924,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -4005,14 +4005,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done11: @@ -4020,7 +4020,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4069,13 +4069,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -4161,14 +4161,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -4176,17 +4176,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4197,7 +4197,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4211,7 +4211,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4247,14 +4247,14 @@ int main() { // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -4317,7 +4317,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -4325,27 +4325,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP39]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4353,12 +4353,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -4381,7 +4381,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4426,13 +4426,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -4509,14 +4509,14 @@ int main() { // CHECK12-NEXT: store i32 [[TMP32]], i32* [[TMP4]], align 4 // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done12: @@ -4524,7 +4524,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4577,13 +4577,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -4671,14 +4671,14 @@ int main() { // CHECK12-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done14: @@ -4686,12 +4686,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // @@ -4710,14 +4710,14 @@ int main() { // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4776,17 +4776,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP32]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4797,7 +4797,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4811,7 +4811,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4820,17 +4820,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4838,12 +4838,12 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -4864,7 +4864,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4905,13 +4905,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -4986,14 +4986,14 @@ int main() { // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done11: @@ -5001,7 +5001,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5050,13 +5050,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -5142,14 +5142,14 @@ int main() { // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done13: @@ -5157,17 +5157,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5178,7 +5178,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5192,7 +5192,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5206,3 +5206,4 @@ int main() { // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp index d8ae9808a1835b81117821624f4af85289490a87..0b8ebc471a9e2bade0a24f308a7a4c3456d72d0e 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp @@ -89,8 +89,8 @@ int main() { // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK1-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK1-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK1-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -108,7 +108,7 @@ int main() { // CHECK1-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK1-NEXT: br label [[EH_RESUME:%.*]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -139,16 +139,16 @@ int main() { // CHECK1: omp_offload.cont3: // CHECK1-NEXT: [[TMP19:%.*]] = load i8, i8* [[A]], align 1 // CHECK1-NEXT: [[CONV4:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK1-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() +// CHECK1-NEXT: [[CALL6:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() // CHECK1-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK1: invoke.cont5: // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK1-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() +// CHECK1-NEXT: [[CALL8:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() // CHECK1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK1: invoke.cont7: // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK1-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP20]] // CHECK1: eh.resume: @@ -160,7 +160,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -168,12 +168,12 @@ int main() { // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -192,7 +192,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -253,7 +253,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -339,7 +339,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -357,7 +357,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -423,7 +423,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -540,11 +540,11 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK1-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK1-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32 @@ -566,17 +566,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -590,7 +590,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -606,7 +606,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -667,7 +667,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -753,7 +753,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -814,7 +814,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -900,7 +900,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -961,7 +961,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1047,11 +1047,11 @@ int main() { // CHECK1-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK1: invoke.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK1-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK1-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* @@ -1074,7 +1074,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1140,7 +1140,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1241,8 +1241,8 @@ int main() { // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK2-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK2-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK2-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -1260,7 +1260,7 @@ int main() { // CHECK2-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK2-NEXT: br label [[EH_RESUME:%.*]] // CHECK2: omp_offload.cont: // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -1291,16 +1291,16 @@ int main() { // CHECK2: omp_offload.cont3: // CHECK2-NEXT: [[TMP19:%.*]] = load i8, i8* [[A]], align 1 // CHECK2-NEXT: [[CONV4:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK2-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() +// CHECK2-NEXT: [[CALL6:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() // CHECK2-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK2: invoke.cont5: // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK2-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() +// CHECK2-NEXT: [[CALL8:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() // CHECK2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK2: invoke.cont7: // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK2-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP20]] // CHECK2: eh.resume: @@ -1312,7 +1312,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -1320,12 +1320,12 @@ int main() { // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1344,7 +1344,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1405,7 +1405,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1491,7 +1491,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 -// CHECK2-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -1509,7 +1509,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1575,7 +1575,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1692,11 +1692,11 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK2-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK2-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK2-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32 @@ -1718,17 +1718,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -1742,7 +1742,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1758,7 +1758,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1819,7 +1819,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1905,7 +1905,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1966,7 +1966,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2052,7 +2052,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2113,7 +2113,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2199,11 +2199,11 @@ int main() { // CHECK2-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK2-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK2-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK2: invoke.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK2-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK2-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* @@ -2226,7 +2226,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2292,7 +2292,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2393,8 +2393,8 @@ int main() { // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK5-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK5-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK5-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -2412,7 +2412,7 @@ int main() { // CHECK5-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK5-NEXT: br label [[EH_RESUME:%.*]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -2443,16 +2443,16 @@ int main() { // CHECK5: omp_offload.cont3: // CHECK5-NEXT: [[TMP19:%.*]] = load i8, i8* [[A]], align 1 // CHECK5-NEXT: [[CONV4:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK5-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() +// CHECK5-NEXT: [[CALL6:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() // CHECK5-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK5: invoke.cont5: // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK5-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() +// CHECK5-NEXT: [[CALL8:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() // CHECK5-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK5: invoke.cont7: // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK5-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP20]] // CHECK5: eh.resume: @@ -2464,7 +2464,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -2472,12 +2472,12 @@ int main() { // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2496,7 +2496,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2557,7 +2557,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2643,7 +2643,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 -// CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -2661,7 +2661,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2727,7 +2727,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2844,11 +2844,11 @@ int main() { // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: -// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK5-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK5-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32 @@ -2870,17 +2870,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK5-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -2901,7 +2901,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2962,7 +2962,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3048,7 +3048,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3109,7 +3109,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3195,7 +3195,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3256,7 +3256,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3342,11 +3342,11 @@ int main() { // CHECK5-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK5: invoke.cont: -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK5-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK5-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* @@ -3369,7 +3369,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3435,7 +3435,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3514,7 +3514,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3545,8 +3545,8 @@ int main() { // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK6-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK6-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK6-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -3564,7 +3564,7 @@ int main() { // CHECK6-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK6-NEXT: br label [[EH_RESUME:%.*]] // CHECK6: omp_offload.cont: // CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -3595,16 +3595,16 @@ int main() { // CHECK6: omp_offload.cont3: // CHECK6-NEXT: [[TMP19:%.*]] = load i8, i8* [[A]], align 1 // CHECK6-NEXT: [[CONV4:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK6-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() +// CHECK6-NEXT: [[CALL6:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() // CHECK6-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK6: invoke.cont5: // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK6-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() +// CHECK6-NEXT: [[CALL8:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() // CHECK6-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK6: invoke.cont7: // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK6-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP20]] // CHECK6: eh.resume: @@ -3616,7 +3616,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -3624,12 +3624,12 @@ int main() { // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3648,7 +3648,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3709,7 +3709,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3795,7 +3795,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 -// CHECK6-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -3813,7 +3813,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3879,7 +3879,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3996,11 +3996,11 @@ int main() { // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]] // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK6: omp_offload.cont: -// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK6-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK6-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32 @@ -4022,17 +4022,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK6-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -4053,7 +4053,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4114,7 +4114,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4200,7 +4200,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4261,7 +4261,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4347,7 +4347,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4408,7 +4408,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4494,11 +4494,11 @@ int main() { // CHECK6-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK6: invoke.cont: -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK6-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK6-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* @@ -4521,7 +4521,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4587,7 +4587,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4666,7 +4666,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4680,3 +4680,4 @@ int main() { // CHECK6-NEXT: call void @__tgt_register_requires(i64 1) // CHECK6-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp index 41fa1c3e222467bbf343d866d5ff766e7e9003ee..47548ae90c504cfef8c0316d0d372d3d08a6bf68 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp @@ -145,33 +145,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -184,7 +184,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -195,14 +195,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -210,12 +210,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -223,7 +223,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -231,7 +231,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -250,7 +250,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -269,7 +269,7 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -281,7 +281,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -308,12 +308,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -357,14 +357,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -372,7 +372,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -409,12 +409,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -473,14 +473,14 @@ int main() { // CHECK1-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -498,14 +498,14 @@ int main() { // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -523,27 +523,27 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP4]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -551,7 +551,7 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // @@ -563,7 +563,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -592,12 +592,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -642,14 +642,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done5: @@ -657,7 +657,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -696,12 +696,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -758,14 +758,14 @@ int main() { // CHECK1-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done9: @@ -773,17 +773,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -795,7 +795,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -811,7 +811,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -838,33 +838,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -877,7 +877,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -888,14 +888,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -903,12 +903,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -916,7 +916,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -924,7 +924,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -943,7 +943,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -962,7 +962,7 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -974,7 +974,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1001,12 +1001,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1050,14 +1050,14 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done3: @@ -1065,7 +1065,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1102,12 +1102,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1166,14 +1166,14 @@ int main() { // CHECK2-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done8: @@ -1191,14 +1191,14 @@ int main() { // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -1216,27 +1216,27 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP4]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1244,7 +1244,7 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // @@ -1256,7 +1256,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1285,12 +1285,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1335,14 +1335,14 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done5: @@ -1350,7 +1350,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1389,12 +1389,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -1451,14 +1451,14 @@ int main() { // CHECK2-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done9: @@ -1466,17 +1466,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1488,7 +1488,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1504,7 +1504,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1531,33 +1531,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1570,7 +1570,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1581,14 +1581,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1596,12 +1596,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1609,7 +1609,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1617,7 +1617,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1636,7 +1636,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -1655,7 +1655,7 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -1667,7 +1667,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1694,12 +1694,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1741,14 +1741,14 @@ int main() { // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done3: @@ -1756,7 +1756,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1791,12 +1791,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1853,14 +1853,14 @@ int main() { // CHECK3-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -1878,14 +1878,14 @@ int main() { // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -1903,27 +1903,27 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP4]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1931,7 +1931,7 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // @@ -1943,7 +1943,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1972,12 +1972,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2020,14 +2020,14 @@ int main() { // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done5: @@ -2035,7 +2035,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2072,12 +2072,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2132,14 +2132,14 @@ int main() { // CHECK3-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -2147,17 +2147,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2169,7 +2169,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2185,7 +2185,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2212,33 +2212,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2251,7 +2251,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2262,14 +2262,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2277,12 +2277,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -2290,7 +2290,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -2298,7 +2298,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2317,7 +2317,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -2336,7 +2336,7 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // @@ -2348,7 +2348,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2375,12 +2375,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2422,14 +2422,14 @@ int main() { // CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done3: @@ -2437,7 +2437,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2472,12 +2472,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2534,14 +2534,14 @@ int main() { // CHECK4-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done6: @@ -2559,14 +2559,14 @@ int main() { // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -2584,27 +2584,27 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP4]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2612,7 +2612,7 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // @@ -2624,7 +2624,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2653,12 +2653,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2701,14 +2701,14 @@ int main() { // CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done5: @@ -2716,7 +2716,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2753,12 +2753,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2813,14 +2813,14 @@ int main() { // CHECK4-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done7: @@ -2828,17 +2828,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2850,7 +2850,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2866,7 +2866,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2893,33 +2893,33 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2932,7 +2932,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2943,14 +2943,14 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2958,12 +2958,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2971,7 +2971,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -2979,7 +2979,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2998,7 +2998,7 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // @@ -3009,12 +3009,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 @@ -3026,7 +3026,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3093,7 +3093,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3166,7 +3166,7 @@ int main() { // CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3201,33 +3201,33 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3240,7 +3240,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3251,14 +3251,14 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3266,12 +3266,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3279,7 +3279,7 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: @@ -3287,7 +3287,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3306,7 +3306,7 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // @@ -3317,12 +3317,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK10-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK10-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 @@ -3334,7 +3334,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3401,7 +3401,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3474,7 +3474,7 @@ int main() { // CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -3505,3 +3505,4 @@ int main() { // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp index 7367e4ba941a6055d65079c90faf4409f4ca1e94..972f023da238aaf73fe47d4eca44b7a82e881b28 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp @@ -73,7 +73,7 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l39() #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT3]] // CHECK1: omp_offload.cont3: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -85,7 +85,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -146,7 +146,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -223,7 +223,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -284,7 +284,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -376,7 +376,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -437,7 +437,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -536,7 +536,7 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l39() #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT3]] // CHECK2: omp_offload.cont3: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -548,7 +548,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -609,7 +609,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -686,7 +686,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -747,7 +747,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -839,7 +839,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -900,7 +900,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -975,3 +975,4 @@ int main() { // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) // CHECK2-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp index e71fab7d71d648d0a278f3237160372c0b05b691..ffd779f1d0e2b1463e4721c51b44e9a7da2d7ba1 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp @@ -125,12 +125,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -140,7 +140,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -227,7 +227,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -328,7 +328,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -352,7 +352,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -414,7 +414,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 @@ -424,7 +424,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -511,7 +511,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -612,7 +612,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -636,7 +636,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -698,12 +698,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK2-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -713,7 +713,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -800,7 +800,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -901,7 +901,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -925,7 +925,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -987,7 +987,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK2-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 @@ -997,7 +997,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1084,7 +1084,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1185,7 +1185,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1209,7 +1209,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1270,12 +1270,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 @@ -1284,7 +1284,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1369,7 +1369,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1468,7 +1468,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1492,7 +1492,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1553,7 +1553,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 @@ -1562,7 +1562,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1647,7 +1647,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1746,7 +1746,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1770,7 +1770,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1831,12 +1831,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 -// CHECK4-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 @@ -1845,7 +1845,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1930,7 +1930,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2029,7 +2029,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2053,7 +2053,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2114,7 +2114,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK4-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 @@ -2123,7 +2123,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2208,7 +2208,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2307,7 +2307,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2331,7 +2331,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2367,12 +2367,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 -// CHECK9-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -2382,7 +2382,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2469,7 +2469,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2536,7 +2536,7 @@ int main() { // CHECK9-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2574,7 +2574,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2598,7 +2598,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2634,12 +2634,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 -// CHECK10-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -2649,7 +2649,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2736,7 +2736,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2803,7 +2803,7 @@ int main() { // CHECK10-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 // CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK10-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2841,7 +2841,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2865,7 +2865,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2894,3 +2894,4 @@ int main() { // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp index 489ff2f8a2927d9297cd61030472f51dbe1c85ca..4b239f9447a7b242e757421f89840fc27dad76d0 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp @@ -37,7 +37,7 @@ int main(int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -54,7 +54,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14 -// CHECK1-SAME: (i64 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -67,7 +67,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -321,7 +321,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init. -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -334,7 +334,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -352,7 +352,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -374,7 +374,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -405,7 +405,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -694,7 +694,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init..4 -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -707,7 +707,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb..5 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -725,7 +725,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_init..6 -// CHECK1-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -747,7 +747,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.red_comb..7 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -778,7 +778,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -792,7 +792,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK1-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -876,7 +876,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -925,7 +925,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -974,7 +974,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@main -// CHECK2-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -991,7 +991,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14 -// CHECK2-SAME: (i64 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 @@ -1004,7 +1004,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1258,7 +1258,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init. -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1271,7 +1271,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1289,7 +1289,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init..1 -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1311,7 +1311,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb..2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1342,7 +1342,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1631,7 +1631,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init..4 -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1644,7 +1644,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb..5 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1662,7 +1662,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_init..6 -// CHECK2-SAME: (i8* noalias noundef [[TMP0:%.*]], i8* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* noalias [[TMP0:%.*]], i8* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1684,7 +1684,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.red_comb..7 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1715,7 +1715,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i8*** noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i8*** noalias [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8***, align 8 @@ -1729,7 +1729,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK2-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 @@ -1813,7 +1813,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1862,7 +1862,7 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.9 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp index 0cbe86ff09273e6a407eb6b459d2d2282843ed63..b1a46f0dfbb58fd8037849d1ee8edf9c70b3fa9c 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp @@ -212,12 +212,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -344,7 +344,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l35 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -354,7 +354,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -417,7 +417,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -495,7 +495,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -505,7 +505,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -568,7 +568,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -646,7 +646,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l45 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -656,7 +656,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -719,7 +719,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -818,7 +818,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l51 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -828,7 +828,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -891,7 +891,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -967,7 +967,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l57 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -977,7 +977,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1040,7 +1040,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1126,12 +1126,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -1258,7 +1258,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l35 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1268,7 +1268,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1331,7 +1331,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1409,7 +1409,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1419,7 +1419,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1482,7 +1482,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1560,7 +1560,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l45 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1570,7 +1570,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1633,7 +1633,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1732,7 +1732,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l51 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1742,7 +1742,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1805,7 +1805,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1881,7 +1881,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l57 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1891,7 +1891,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1954,7 +1954,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2040,12 +2040,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -2172,7 +2172,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l35 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2182,7 +2182,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2243,7 +2243,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2318,7 +2318,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2328,7 +2328,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2389,7 +2389,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2464,7 +2464,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l45 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2474,7 +2474,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2535,7 +2535,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2629,7 +2629,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l51 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2639,7 +2639,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2700,7 +2700,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2773,7 +2773,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l57 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2783,7 +2783,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2844,7 +2844,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2927,12 +2927,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -3059,7 +3059,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l35 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3069,7 +3069,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3130,7 +3130,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3205,7 +3205,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3215,7 +3215,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3276,7 +3276,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3351,7 +3351,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l45 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3361,7 +3361,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3422,7 +3422,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3516,7 +3516,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l51 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3526,7 +3526,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3587,7 +3587,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3660,7 +3660,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l57 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3670,7 +3670,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3731,7 +3731,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3814,12 +3814,12 @@ int main (int argc, char **argv) { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -3946,7 +3946,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l35 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -3956,7 +3956,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4019,7 +4019,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4097,7 +4097,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -4107,7 +4107,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4170,7 +4170,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4248,7 +4248,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l45 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -4258,7 +4258,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4321,7 +4321,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4420,7 +4420,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l51 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -4430,7 +4430,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4493,7 +4493,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4569,7 +4569,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l57 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -4579,7 +4579,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4642,7 +4642,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4728,12 +4728,12 @@ int main (int argc, char **argv) { // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -4860,7 +4860,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l35 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -4870,7 +4870,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4933,7 +4933,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5011,7 +5011,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -5021,7 +5021,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5084,7 +5084,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5162,7 +5162,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l45 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -5172,7 +5172,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5235,7 +5235,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5334,7 +5334,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l51 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -5344,7 +5344,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5407,7 +5407,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5483,7 +5483,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l57 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -5493,7 +5493,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5556,7 +5556,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5642,12 +5642,12 @@ int main (int argc, char **argv) { // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -5774,7 +5774,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l35 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -5784,7 +5784,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5845,7 +5845,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5920,7 +5920,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -5930,7 +5930,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5991,7 +5991,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6066,7 +6066,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l45 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6076,7 +6076,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6137,7 +6137,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6231,7 +6231,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l51 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6241,7 +6241,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6302,7 +6302,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6375,7 +6375,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l57 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6385,7 +6385,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6446,7 +6446,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6529,12 +6529,12 @@ int main (int argc, char **argv) { // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK8-NEXT: ret i32 [[CALL]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -6661,7 +6661,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l35 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6671,7 +6671,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6732,7 +6732,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6807,7 +6807,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l40 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6817,7 +6817,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6878,7 +6878,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6953,7 +6953,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l45 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6963,7 +6963,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7024,7 +7024,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7118,7 +7118,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l51 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -7128,7 +7128,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7189,7 +7189,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7262,7 +7262,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l57 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -7272,7 +7272,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7333,7 +7333,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7413,7 +7413,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -7784,7 +7784,7 @@ int main (int argc, char **argv) { // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK13: omp_offload.cont65: // CHECK13-NEXT: [[TMP169:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP169]]) +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP169]]) // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP170:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP170]]) @@ -7793,7 +7793,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -7809,7 +7809,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7900,7 +7900,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8005,7 +8005,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -8021,7 +8021,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8112,7 +8112,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8217,7 +8217,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 -// CHECK13-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -8244,7 +8244,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8368,7 +8368,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8476,7 +8476,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -8492,7 +8492,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8583,7 +8583,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8684,7 +8684,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 -// CHECK13-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -8711,7 +8711,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8810,7 +8810,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8915,7 +8915,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -9062,7 +9062,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -9072,7 +9072,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9135,7 +9135,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9212,7 +9212,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -9222,7 +9222,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9285,7 +9285,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9362,7 +9362,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 -// CHECK13-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -9383,7 +9383,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9454,7 +9454,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9556,7 +9556,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -9566,7 +9566,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9629,7 +9629,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9704,7 +9704,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 -// CHECK13-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -9725,7 +9725,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9796,7 +9796,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9882,7 +9882,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -10253,7 +10253,7 @@ int main (int argc, char **argv) { // CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK14: omp_offload.cont65: // CHECK14-NEXT: [[TMP169:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP169]]) +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP169]]) // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[TMP170:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP170]]) @@ -10262,7 +10262,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -10278,7 +10278,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10369,7 +10369,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10474,7 +10474,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -10490,7 +10490,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10581,7 +10581,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10686,7 +10686,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 -// CHECK14-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -10713,7 +10713,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10837,7 +10837,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10945,7 +10945,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -10961,7 +10961,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11052,7 +11052,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11153,7 +11153,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 -// CHECK14-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -11180,7 +11180,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11279,7 +11279,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11384,7 +11384,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -11531,7 +11531,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -11541,7 +11541,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11604,7 +11604,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11681,7 +11681,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -11691,7 +11691,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11754,7 +11754,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11831,7 +11831,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 -// CHECK14-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -11852,7 +11852,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11923,7 +11923,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12025,7 +12025,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -12035,7 +12035,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12098,7 +12098,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12173,7 +12173,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 -// CHECK14-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -12194,7 +12194,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12265,7 +12265,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12351,7 +12351,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -12719,7 +12719,7 @@ int main (int argc, char **argv) { // CHECK15-NEXT: br label [[OMP_OFFLOAD_CONT59]] // CHECK15: omp_offload.cont59: // CHECK15-NEXT: [[TMP173:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP173]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP173]]) // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP174:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP174]]) @@ -12728,7 +12728,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 -// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -12743,7 +12743,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12832,7 +12832,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -12934,7 +12934,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 -// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -12949,7 +12949,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13038,7 +13038,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13140,7 +13140,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 -// CHECK15-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -13164,7 +13164,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13284,7 +13284,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13388,7 +13388,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 -// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -13403,7 +13403,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13492,7 +13492,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13590,7 +13590,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 -// CHECK15-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -13614,7 +13614,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13709,7 +13709,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -13810,7 +13810,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -13955,7 +13955,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -13965,7 +13965,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14026,7 +14026,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14100,7 +14100,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -14110,7 +14110,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14171,7 +14171,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14245,7 +14245,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 -// CHECK15-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -14264,7 +14264,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14331,7 +14331,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14427,7 +14427,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -14437,7 +14437,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14498,7 +14498,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14570,7 +14570,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 -// CHECK15-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -14589,7 +14589,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14656,7 +14656,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -14738,7 +14738,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -15106,7 +15106,7 @@ int main (int argc, char **argv) { // CHECK16-NEXT: br label [[OMP_OFFLOAD_CONT59]] // CHECK16: omp_offload.cont59: // CHECK16-NEXT: [[TMP173:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP173]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP173]]) // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[TMP174:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP174]]) @@ -15115,7 +15115,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 -// CHECK16-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -15130,7 +15130,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15219,7 +15219,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15321,7 +15321,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 -// CHECK16-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -15336,7 +15336,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15425,7 +15425,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15527,7 +15527,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 -// CHECK16-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -15551,7 +15551,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15671,7 +15671,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15775,7 +15775,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 -// CHECK16-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -15790,7 +15790,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15879,7 +15879,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -15977,7 +15977,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 -// CHECK16-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -16001,7 +16001,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16096,7 +16096,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16197,7 +16197,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -16342,7 +16342,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -16352,7 +16352,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16413,7 +16413,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16487,7 +16487,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -16497,7 +16497,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16558,7 +16558,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16632,7 +16632,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 -// CHECK16-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -16651,7 +16651,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16718,7 +16718,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16814,7 +16814,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -16824,7 +16824,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16885,7 +16885,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -16957,7 +16957,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 -// CHECK16-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -16976,7 +16976,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17043,7 +17043,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -17125,7 +17125,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@main -// CHECK17-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -17496,7 +17496,7 @@ int main (int argc, char **argv) { // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK17: omp_offload.cont65: // CHECK17-NEXT: [[TMP169:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP169]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP169]]) // CHECK17-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK17-NEXT: [[TMP170:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP170]]) @@ -17505,7 +17505,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 -// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -17521,7 +17521,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17612,7 +17612,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17717,7 +17717,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 -// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -17733,7 +17733,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17824,7 +17824,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17929,7 +17929,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 -// CHECK17-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -17956,7 +17956,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18080,7 +18080,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18188,7 +18188,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 -// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -18204,7 +18204,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18295,7 +18295,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18396,7 +18396,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 -// CHECK17-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -18423,7 +18423,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18522,7 +18522,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18627,7 +18627,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK17-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK17-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -18774,7 +18774,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -18784,7 +18784,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18847,7 +18847,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18924,7 +18924,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -18934,7 +18934,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18997,7 +18997,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19074,7 +19074,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 -// CHECK17-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -19095,7 +19095,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19166,7 +19166,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19268,7 +19268,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -19278,7 +19278,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19341,7 +19341,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19416,7 +19416,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 -// CHECK17-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -19437,7 +19437,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19508,7 +19508,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19594,7 +19594,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@main -// CHECK18-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -19965,7 +19965,7 @@ int main (int argc, char **argv) { // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK18: omp_offload.cont65: // CHECK18-NEXT: [[TMP169:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP169]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP169]]) // CHECK18-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK18-NEXT: [[TMP170:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP170]]) @@ -19974,7 +19974,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 -// CHECK18-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -19990,7 +19990,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20081,7 +20081,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20186,7 +20186,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 -// CHECK18-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -20202,7 +20202,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20293,7 +20293,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20398,7 +20398,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 -// CHECK18-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -20425,7 +20425,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20549,7 +20549,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20657,7 +20657,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 -// CHECK18-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -20673,7 +20673,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20764,7 +20764,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20865,7 +20865,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 -// CHECK18-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -20892,7 +20892,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -20991,7 +20991,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21096,7 +21096,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK18-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK18-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -21243,7 +21243,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -21253,7 +21253,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21316,7 +21316,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21393,7 +21393,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -21403,7 +21403,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21466,7 +21466,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21543,7 +21543,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 -// CHECK18-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -21564,7 +21564,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21635,7 +21635,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21737,7 +21737,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -21747,7 +21747,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21810,7 +21810,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21885,7 +21885,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 -// CHECK18-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -21906,7 +21906,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -21977,7 +21977,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -22063,7 +22063,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@main -// CHECK19-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -22431,7 +22431,7 @@ int main (int argc, char **argv) { // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT59]] // CHECK19: omp_offload.cont59: // CHECK19-NEXT: [[TMP173:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP173]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP173]]) // CHECK19-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK19-NEXT: [[TMP174:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP174]]) @@ -22440,7 +22440,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -22455,7 +22455,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22544,7 +22544,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22646,7 +22646,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -22661,7 +22661,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22750,7 +22750,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22852,7 +22852,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 -// CHECK19-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -22876,7 +22876,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22996,7 +22996,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23100,7 +23100,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -23115,7 +23115,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23204,7 +23204,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23302,7 +23302,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 -// CHECK19-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -23326,7 +23326,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23421,7 +23421,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23522,7 +23522,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK19-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK19-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -23667,7 +23667,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -23677,7 +23677,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23738,7 +23738,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23812,7 +23812,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -23822,7 +23822,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23883,7 +23883,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23957,7 +23957,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 -// CHECK19-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -23976,7 +23976,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24043,7 +24043,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24139,7 +24139,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -24149,7 +24149,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24210,7 +24210,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24282,7 +24282,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 -// CHECK19-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -24301,7 +24301,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24368,7 +24368,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24450,7 +24450,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@main -// CHECK20-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -24818,7 +24818,7 @@ int main (int argc, char **argv) { // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT59]] // CHECK20: omp_offload.cont59: // CHECK20-NEXT: [[TMP173:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP173]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP173]]) // CHECK20-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK20-NEXT: [[TMP174:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP174]]) @@ -24827,7 +24827,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -24842,7 +24842,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24931,7 +24931,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25033,7 +25033,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l153 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -25048,7 +25048,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25137,7 +25137,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25239,7 +25239,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l158 -// CHECK20-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -25263,7 +25263,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25383,7 +25383,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25487,7 +25487,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l163 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -25502,7 +25502,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25591,7 +25591,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25689,7 +25689,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168 -// CHECK20-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -25713,7 +25713,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25808,7 +25808,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25909,7 +25909,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK20-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK20-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -26054,7 +26054,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l116 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -26064,7 +26064,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26125,7 +26125,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26199,7 +26199,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l121 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -26209,7 +26209,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26270,7 +26270,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26344,7 +26344,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l126 -// CHECK20-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -26363,7 +26363,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26430,7 +26430,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26526,7 +26526,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l131 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -26536,7 +26536,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26597,7 +26597,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26669,7 +26669,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l136 -// CHECK20-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -26688,7 +26688,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26755,7 +26755,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp index 9dd392c3d2b28bf12e83f5bf6a322e9692dc7f2d..4a89c664740c5591a2f8fb6cec9308409f189536 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp @@ -182,7 +182,7 @@ int main (int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -332,7 +332,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l29 -// CHECK1-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], i64 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], i64 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -355,7 +355,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -414,23 +414,23 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, [100 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i32* [[TMP0]], [100 x i32]* [[TMP1]]), !llvm.access.group !5 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, [100 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i32* [[TMP0]], [100 x i32]* [[TMP1]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -455,7 +455,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -524,27 +524,27 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !10 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* [[TMP1]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -569,7 +569,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l36 -// CHECK1-SAME: ([100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: ([100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]], i64 [[I:%.*]], i64 [[N:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 8 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 @@ -585,7 +585,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -665,7 +665,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -690,7 +690,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -791,7 +791,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -829,7 +829,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -979,7 +979,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l29 -// CHECK2-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], i64 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], i64 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -1002,7 +1002,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1061,23 +1061,23 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, [100 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i32* [[TMP0]], [100 x i32]* [[TMP1]]), !llvm.access.group !5 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, [100 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], i32* [[TMP0]], [100 x i32]* [[TMP1]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1102,7 +1102,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1171,27 +1171,27 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !10 -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I4]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* [[TMP1]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1216,7 +1216,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l36 -// CHECK2-SAME: ([100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: ([100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]], i64 [[I:%.*]], i64 [[N:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 8 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 @@ -1232,7 +1232,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1312,7 +1312,7 @@ int main (int argc, char **argv) { // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1337,7 +1337,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1438,7 +1438,7 @@ int main (int argc, char **argv) { // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1476,7 +1476,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -1621,7 +1621,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l29 -// CHECK3-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], i32 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], i32 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -1641,7 +1641,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1700,21 +1700,21 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, [100 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32* [[TMP0]], [100 x i32]* [[TMP1]]), !llvm.access.group !6 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, [100 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32* [[TMP0]], [100 x i32]* [[TMP1]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1739,7 +1739,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1806,26 +1806,26 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !11 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* [[TMP1]], i32 0, i32 [[TMP18]] -// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1850,7 +1850,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l36 -// CHECK3-SAME: ([100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: ([100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]], i32 [[I:%.*]], i32 [[N:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 4 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 @@ -1864,7 +1864,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1942,7 +1942,7 @@ int main (int argc, char **argv) { // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1967,7 +1967,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2065,7 +2065,7 @@ int main (int argc, char **argv) { // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2103,7 +2103,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -2248,7 +2248,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l29 -// CHECK4-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], i32 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], i32 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -2268,7 +2268,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2327,21 +2327,21 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, [100 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32* [[TMP0]], [100 x i32]* [[TMP1]]), !llvm.access.group !6 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, [100 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], i32* [[TMP0]], [100 x i32]* [[TMP1]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2366,7 +2366,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2433,26 +2433,26 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !11 -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I3]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* [[TMP1]], i32 0, i32 [[TMP18]] -// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK4-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2477,7 +2477,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l36 -// CHECK4-SAME: ([100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: ([100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]], i32 [[I:%.*]], i32 [[N:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 4 // CHECK4-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 @@ -2491,7 +2491,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2569,7 +2569,7 @@ int main (int argc, char **argv) { // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2594,7 +2594,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2692,7 +2692,7 @@ int main (int argc, char **argv) { // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2730,7 +2730,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -2865,7 +2865,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK6-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -3000,7 +3000,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -3133,7 +3133,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK8-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[TE:%.*]] = alloca i32, align 4 @@ -3366,7 +3366,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l74 -// CHECK9-SAME: (i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[I:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -3385,7 +3385,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3467,7 +3467,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] // CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3492,7 +3492,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3595,7 +3595,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3733,7 +3733,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l74 -// CHECK10-SAME: (i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[I:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -3752,7 +3752,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3834,7 +3834,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] // CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -3859,7 +3859,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3962,7 +3962,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -4098,7 +4098,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l74 -// CHECK11-SAME: (i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[I:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -4115,7 +4115,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4195,7 +4195,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] // CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -4220,7 +4220,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4320,7 +4320,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -4456,7 +4456,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l74 -// CHECK12-SAME: (i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[I:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -4473,7 +4473,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4553,7 +4553,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] // CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -4578,7 +4578,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4678,7 +4678,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -5047,12 +5047,12 @@ int main (int argc, char **argv) { // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK17-NEXT: ret i32 [[CALL]] // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK17-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -5101,7 +5101,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l112 -// CHECK17-SAME: (%struct.SS* noundef [[THIS:%.*]], i64 noundef [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (%struct.SS* [[THIS:%.*]], i64 [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK17-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 @@ -5114,7 +5114,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5174,7 +5174,7 @@ int main (int argc, char **argv) { // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] // CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -5190,7 +5190,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5270,7 +5270,7 @@ int main (int argc, char **argv) { // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK17-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: @@ -5302,12 +5302,12 @@ int main (int argc, char **argv) { // CHECK18-SAME: () #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK18-NEXT: ret i32 [[CALL]] // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK18-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -5356,7 +5356,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l112 -// CHECK18-SAME: (%struct.SS* noundef [[THIS:%.*]], i64 noundef [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-SAME: (%struct.SS* [[THIS:%.*]], i64 [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK18-NEXT: [[I_ADDR:%.*]] = alloca i64, align 8 @@ -5369,7 +5369,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5429,7 +5429,7 @@ int main (int argc, char **argv) { // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] // CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK18: omp.inner.for.end: // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK18: omp.loop.exit: @@ -5445,7 +5445,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5525,7 +5525,7 @@ int main (int argc, char **argv) { // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK18-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 -// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK18: omp.inner.for.end: // CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK18: omp.loop.exit: @@ -5557,12 +5557,12 @@ int main (int argc, char **argv) { // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK19-NEXT: ret i32 [[CALL]] // // // CHECK19-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK19-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -5610,7 +5610,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l112 -// CHECK19-SAME: (%struct.SS* noundef [[THIS:%.*]], i32 noundef [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (%struct.SS* [[THIS:%.*]], i32 [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK19-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 @@ -5622,7 +5622,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5680,7 +5680,7 @@ int main (int argc, char **argv) { // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] // CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK19: omp.loop.exit: @@ -5696,7 +5696,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5773,7 +5773,7 @@ int main (int argc, char **argv) { // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK19: omp.loop.exit: @@ -5805,12 +5805,12 @@ int main (int argc, char **argv) { // CHECK20-SAME: () #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK20-NEXT: ret i32 [[CALL]] // // // CHECK20-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK20-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -5858,7 +5858,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l112 -// CHECK20-SAME: (%struct.SS* noundef [[THIS:%.*]], i32 noundef [[I:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-SAME: (%struct.SS* [[THIS:%.*]], i32 [[I:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK20-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 @@ -5870,7 +5870,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5928,7 +5928,7 @@ int main (int argc, char **argv) { // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] // CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK20: omp.inner.for.end: // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK20: omp.loop.exit: @@ -5944,7 +5944,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6021,7 +6021,7 @@ int main (int argc, char **argv) { // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 -// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK20: omp.inner.for.end: // CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK20: omp.loop.exit: @@ -6053,12 +6053,12 @@ int main (int argc, char **argv) { // CHECK21-SAME: () #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK21-NEXT: ret i32 [[CALL]] // // // CHECK21-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK21-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK21-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -6116,12 +6116,12 @@ int main (int argc, char **argv) { // CHECK22-SAME: () #[[ATTR0:[0-9]+]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK22-NEXT: ret i32 [[CALL]] // // // CHECK22-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK22-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK22-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK22-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -6179,12 +6179,12 @@ int main (int argc, char **argv) { // CHECK23-SAME: () #[[ATTR0:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK23-NEXT: ret i32 [[CALL]] // // // CHECK23-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK23-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK23-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -6241,12 +6241,12 @@ int main (int argc, char **argv) { // CHECK24-SAME: () #[[ATTR0:[0-9]+]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK24-NEXT: ret i32 [[CALL]] // // // CHECK24-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK24-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK24-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK24-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -6300,7 +6300,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@main -// CHECK25-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK25-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -6399,7 +6399,7 @@ int main (int argc, char **argv) { // CHECK25-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK25: omp_offload.cont: // CHECK25-NEXT: [[TMP41:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP41]]) +// CHECK25-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP41]]) // CHECK25-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK25-NEXT: [[TMP42:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK25-NEXT: call void @llvm.stackrestore(i8* [[TMP42]]) @@ -6408,7 +6408,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l166 -// CHECK25-SAME: (i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK25-SAME: (i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[I:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -6427,7 +6427,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6509,7 +6509,7 @@ int main (int argc, char **argv) { // CHECK25-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] // CHECK25-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK25: omp.inner.for.end: // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK25: omp.loop.exit: @@ -6534,7 +6534,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6637,7 +6637,7 @@ int main (int argc, char **argv) { // CHECK25-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK25-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK25: omp.inner.for.end: // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK25: omp.loop.exit: @@ -6668,7 +6668,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK25-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { +// CHECK25-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -6730,7 +6730,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l155 -// CHECK25-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK25-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -6750,7 +6750,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6788,23 +6788,23 @@ int main (int argc, char **argv) { // CHECK25-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK25-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK25-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK25-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK25-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]), !llvm.access.group !11 +// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !11 +// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK25-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK25: omp.inner.for.end: // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK25: omp.loop.exit: @@ -6820,7 +6820,7 @@ int main (int argc, char **argv) { // // // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6868,27 +6868,27 @@ int main (int argc, char **argv) { // CHECK25-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK25: omp.inner.for.cond: -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 -// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK25-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK25: omp.body.continue: // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK25-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK25-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK25: omp.inner.for.end: // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK25: omp.loop.exit: @@ -6911,7 +6911,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@main -// CHECK26-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK26-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -7010,7 +7010,7 @@ int main (int argc, char **argv) { // CHECK26-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK26: omp_offload.cont: // CHECK26-NEXT: [[TMP41:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK26-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP41]]) +// CHECK26-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP41]]) // CHECK26-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK26-NEXT: [[TMP42:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK26-NEXT: call void @llvm.stackrestore(i8* [[TMP42]]) @@ -7019,7 +7019,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l166 -// CHECK26-SAME: (i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK26-SAME: (i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[I:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -7038,7 +7038,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7120,7 +7120,7 @@ int main (int argc, char **argv) { // CHECK26-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] // CHECK26-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK26: omp.inner.for.end: // CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK26: omp.loop.exit: @@ -7145,7 +7145,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7248,7 +7248,7 @@ int main (int argc, char **argv) { // CHECK26-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK26-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK26: omp.inner.for.end: // CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK26: omp.loop.exit: @@ -7279,7 +7279,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK26-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { +// CHECK26-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK26-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -7341,7 +7341,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l155 -// CHECK26-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK26-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK26-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -7361,7 +7361,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7399,23 +7399,23 @@ int main (int argc, char **argv) { // CHECK26-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK26-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK26-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK26-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK26-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]), !llvm.access.group !11 +// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !11 +// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK26-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK26: omp.inner.for.end: // CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK26: omp.loop.exit: @@ -7431,7 +7431,7 @@ int main (int argc, char **argv) { // // // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7479,27 +7479,27 @@ int main (int argc, char **argv) { // CHECK26-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK26: omp.inner.for.cond: -// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK26: omp.inner.for.body: -// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 -// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK26-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK26-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK26: omp.body.continue: // CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK26: omp.inner.for.inc: -// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK26-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK26-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK26: omp.inner.for.end: // CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK26: omp.loop.exit: @@ -7522,7 +7522,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@main -// CHECK27-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK27-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -7619,7 +7619,7 @@ int main (int argc, char **argv) { // CHECK27-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK27: omp_offload.cont: // CHECK27-NEXT: [[TMP41:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP41]]) +// CHECK27-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP41]]) // CHECK27-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK27-NEXT: [[TMP42:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK27-NEXT: call void @llvm.stackrestore(i8* [[TMP42]]) @@ -7628,7 +7628,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l166 -// CHECK27-SAME: (i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK27-SAME: (i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[I:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -7645,7 +7645,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7725,7 +7725,7 @@ int main (int argc, char **argv) { // CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] // CHECK27-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK27: omp.inner.for.end: // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK27: omp.loop.exit: @@ -7750,7 +7750,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7850,7 +7850,7 @@ int main (int argc, char **argv) { // CHECK27-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK27-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK27: omp.inner.for.end: // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK27: omp.loop.exit: @@ -7881,7 +7881,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK27-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { +// CHECK27-SAME: (i32 [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -7941,7 +7941,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l155 -// CHECK27-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK27-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -7959,7 +7959,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7997,21 +7997,21 @@ int main (int argc, char **argv) { // CHECK27-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]), !llvm.access.group !12 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !12 +// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK27-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK27: omp.inner.for.end: // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK27: omp.loop.exit: @@ -8027,7 +8027,7 @@ int main (int argc, char **argv) { // // // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8073,26 +8073,26 @@ int main (int argc, char **argv) { // CHECK27-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK27: omp.inner.for.cond: -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16 -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK27-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK27: omp.body.continue: // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK27-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK27-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK27: omp.inner.for.end: // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK27: omp.loop.exit: @@ -8115,7 +8115,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@main -// CHECK28-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK28-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -8212,7 +8212,7 @@ int main (int argc, char **argv) { // CHECK28-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK28: omp_offload.cont: // CHECK28-NEXT: [[TMP41:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK28-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP41]]) +// CHECK28-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP41]]) // CHECK28-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK28-NEXT: [[TMP42:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK28-NEXT: call void @llvm.stackrestore(i8* [[TMP42]]) @@ -8221,7 +8221,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l166 -// CHECK28-SAME: (i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK28-SAME: (i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[I:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 @@ -8238,7 +8238,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8318,7 +8318,7 @@ int main (int argc, char **argv) { // CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] // CHECK28-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK28: omp.inner.for.end: // CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK28: omp.loop.exit: @@ -8343,7 +8343,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8443,7 +8443,7 @@ int main (int argc, char **argv) { // CHECK28-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK28-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK28: omp.inner.for.end: // CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK28: omp.loop.exit: @@ -8474,7 +8474,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK28-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { +// CHECK28-SAME: (i32 [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -8534,7 +8534,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l155 -// CHECK28-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK28-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK28-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -8552,7 +8552,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8590,21 +8590,21 @@ int main (int argc, char **argv) { // CHECK28-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 +// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]), !llvm.access.group !12 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !12 +// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK28-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK28: omp.inner.for.end: // CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK28: omp.loop.exit: @@ -8620,7 +8620,7 @@ int main (int argc, char **argv) { // // // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8666,26 +8666,26 @@ int main (int argc, char **argv) { // CHECK28-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK28: omp.inner.for.cond: -// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK28: omp.inner.for.body: -// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16 -// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK28-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK28: omp.body.continue: // CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK28: omp.inner.for.inc: -// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 +// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK28-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK28-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK28: omp.inner.for.end: // CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK28: omp.loop.exit: @@ -8708,7 +8708,7 @@ int main (int argc, char **argv) { // // // CHECK29-LABEL: define {{[^@]+}}@main -// CHECK29-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK29-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -8790,7 +8790,7 @@ int main (int argc, char **argv) { // CHECK29-NEXT: br label [[SIMD_IF_END]] // CHECK29: simd.if.end: // CHECK29-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP15]]) +// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP15]]) // CHECK29-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK29-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) @@ -8799,7 +8799,7 @@ int main (int argc, char **argv) { // // // CHECK29-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK29-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat { +// CHECK29-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -8846,7 +8846,7 @@ int main (int argc, char **argv) { // // // CHECK30-LABEL: define {{[^@]+}}@main -// CHECK30-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK30-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -8928,7 +8928,7 @@ int main (int argc, char **argv) { // CHECK30-NEXT: br label [[SIMD_IF_END]] // CHECK30: simd.if.end: // CHECK30-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP15]]) +// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP15]]) // CHECK30-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK30-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) @@ -8937,7 +8937,7 @@ int main (int argc, char **argv) { // // // CHECK30-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK30-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat { +// CHECK30-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK30-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -8984,7 +8984,7 @@ int main (int argc, char **argv) { // // // CHECK31-LABEL: define {{[^@]+}}@main -// CHECK31-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK31-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -9064,7 +9064,7 @@ int main (int argc, char **argv) { // CHECK31-NEXT: br label [[SIMD_IF_END]] // CHECK31: simd.if.end: // CHECK31-NEXT: [[TMP14:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP14]]) +// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP14]]) // CHECK31-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK31-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) @@ -9073,7 +9073,7 @@ int main (int argc, char **argv) { // // // CHECK31-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK31-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat { +// CHECK31-SAME: (i32 [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK31-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -9119,7 +9119,7 @@ int main (int argc, char **argv) { // // // CHECK32-LABEL: define {{[^@]+}}@main -// CHECK32-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK32-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -9199,7 +9199,7 @@ int main (int argc, char **argv) { // CHECK32-NEXT: br label [[SIMD_IF_END]] // CHECK32: simd.if.end: // CHECK32-NEXT: [[TMP14:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP14]]) +// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP14]]) // CHECK32-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK32-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) @@ -9208,7 +9208,7 @@ int main (int argc, char **argv) { // // // CHECK32-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK32-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat { +// CHECK32-SAME: (i32 [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK32-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp index 9e381ac1d934c6ab61d29cb1a4040974d38de901..a0917e160d9179dce26aab9b8b13d3b872b44aaa 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp @@ -111,12 +111,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -153,7 +153,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -163,7 +163,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -203,23 +203,23 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]), !llvm.access.group !4 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -236,7 +236,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -286,40 +286,40 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 456 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 456 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] // CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK1-NEXT: store i32 [[ADD7]], i32* [[J]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] -// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -346,12 +346,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -388,7 +388,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -398,7 +398,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -438,23 +438,23 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]), !llvm.access.group !4 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -471,7 +471,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -521,40 +521,40 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 456 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 456 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] // CHECK2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK2-NEXT: store i32 [[ADD7]], i32* [[J]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] -// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -581,12 +581,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -623,7 +623,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -633,7 +633,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -673,21 +673,21 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]), !llvm.access.group !5 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -704,7 +704,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -752,38 +752,38 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP13]] -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] -// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -810,12 +810,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -852,7 +852,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -862,7 +862,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -902,21 +902,21 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]), !llvm.access.group !5 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -933,7 +933,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -981,38 +981,38 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456 // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] // CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP13]] -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] -// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1039,12 +1039,12 @@ int main (int argc, char **argv) { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1110,12 +1110,12 @@ int main (int argc, char **argv) { // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1181,12 +1181,12 @@ int main (int argc, char **argv) { // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1250,12 +1250,12 @@ int main (int argc, char **argv) { // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK8-NEXT: ret i32 [[CALL]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1316,7 +1316,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1441,7 +1441,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -1450,7 +1450,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -1472,7 +1472,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1557,21 +1557,21 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP22]], i32* [[TMP0]], i32* [[TMP1]], i64 [[TMP2]], i64 [[TMP3]], i32* [[TMP4]]), !llvm.access.group !5 +// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP22]], i32* [[TMP0]], i32* [[TMP1]], i64 [[TMP2]], i64 [[TMP3]], i32* [[TMP4]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP23]], [[TMP24]] -// CHECK9-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK9-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1602,7 +1602,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1695,13 +1695,13 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] // CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP24]], 0 // CHECK9-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 // CHECK9-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] @@ -1710,16 +1710,16 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] // CHECK9-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK9-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 +// CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK9-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP27]], 0 // CHECK9-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 // CHECK9-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] // CHECK9-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 // CHECK9-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP26]], [[CONV25]] -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP28]], 0 // CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 // CHECK9-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] @@ -1729,23 +1729,23 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 // CHECK9-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] // CHECK9-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 -// CHECK9-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[I11]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP29]] to i64 // CHECK9-NEXT: [[TMP30:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP30]] -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[J12]], align 4 // CHECK9-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64 // CHECK9-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK9-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP32]], 1 -// CHECK9-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK9-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1776,7 +1776,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -1808,7 +1808,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72 -// CHECK9-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -1818,7 +1818,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1858,23 +1858,23 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]), !llvm.access.group !14 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1891,7 +1891,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1941,39 +1941,39 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2 // CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] // CHECK9-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[J]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 // CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1997,7 +1997,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2122,7 +2122,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: // CHECK10-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -2131,7 +2131,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -2153,7 +2153,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2238,21 +2238,21 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK10-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP22]], i32* [[TMP0]], i32* [[TMP1]], i64 [[TMP2]], i64 [[TMP3]], i32* [[TMP4]]), !llvm.access.group !5 +// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP21]], i64 [[TMP22]], i32* [[TMP0]], i32* [[TMP1]], i64 [[TMP2]], i64 [[TMP3]], i32* [[TMP4]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP23]], [[TMP24]] -// CHECK10-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK10-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2283,7 +2283,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2376,13 +2376,13 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK10-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] // CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK10-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP24]], 0 // CHECK10-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 // CHECK10-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] @@ -2391,16 +2391,16 @@ int main (int argc, char **argv) { // CHECK10-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] // CHECK10-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK10-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 +// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK10-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP27]], 0 // CHECK10-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 // CHECK10-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] // CHECK10-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 // CHECK10-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP26]], [[CONV25]] -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK10-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP28]], 0 // CHECK10-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 // CHECK10-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] @@ -2410,23 +2410,23 @@ int main (int argc, char **argv) { // CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 // CHECK10-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] // CHECK10-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 -// CHECK10-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[I11]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP29]] to i64 // CHECK10-NEXT: [[TMP30:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP30]] -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[J12]], align 4 // CHECK10-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64 // CHECK10-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK10-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP32]], 1 -// CHECK10-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !9 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK10-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2457,7 +2457,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -2489,7 +2489,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72 -// CHECK10-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -2499,7 +2499,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2539,23 +2539,23 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]), !llvm.access.group !14 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x [2 x i32]]* [[TMP0]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2572,7 +2572,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2622,39 +2622,39 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2 // CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] // CHECK10-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[J]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: store i32 [[ADD7]], i32* [[J]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 // CHECK10-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX9]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2678,7 +2678,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2800,7 +2800,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -2809,7 +2809,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -2829,7 +2829,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2914,23 +2914,23 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 // CHECK11-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32 -// CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK11-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP24]], i32* [[TMP0]], i32* [[TMP1]], i32 [[TMP2]], i32 [[TMP3]], i32* [[TMP4]]), !llvm.access.group !6 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP24]], i32* [[TMP0]], i32* [[TMP1]], i32 [[TMP2]], i32 [[TMP3]], i32* [[TMP4]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]] -// CHECK11-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK11-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -2961,7 +2961,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3056,13 +3056,13 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK11-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] // CHECK11-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK11-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP24]], 0 // CHECK11-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 // CHECK11-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] @@ -3071,16 +3071,16 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] // CHECK11-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK11-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK11-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP27]], 0 // CHECK11-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 // CHECK11-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] // CHECK11-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 // CHECK11-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP26]], [[CONV27]] -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK11-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP28]], 0 // CHECK11-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 // CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] @@ -3090,21 +3090,21 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 // CHECK11-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] // CHECK11-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 -// CHECK11-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[I13]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[I13]], align 4 // CHECK11-NEXT: [[TMP30:%.*]] = mul nsw i32 [[TMP29]], [[TMP3]] // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP30]] -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[J14]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[J14]], align 4 // CHECK11-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP31]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK11-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP32]], 1 -// CHECK11-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK11-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -3135,7 +3135,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -3167,7 +3167,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72 -// CHECK11-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -3177,7 +3177,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3217,21 +3217,21 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]), !llvm.access.group !15 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -3248,7 +3248,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3296,37 +3296,37 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP13]] -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -3350,7 +3350,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3472,7 +3472,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: // CHECK12-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -3481,7 +3481,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -3501,7 +3501,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3586,23 +3586,23 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_COMB_LB]], align 8 // CHECK12-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32 -// CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_COMB_UB]], align 8 // CHECK12-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP24]], i32* [[TMP0]], i32* [[TMP1]], i32 [[TMP2]], i32 [[TMP3]], i32* [[TMP4]]), !llvm.access.group !6 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP22]], i32 [[TMP24]], i32* [[TMP0]], i32* [[TMP1]], i32 [[TMP2]], i32 [[TMP3]], i32* [[TMP4]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]] -// CHECK12-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK12-NEXT: store i64 [[ADD]], i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3633,7 +3633,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3728,13 +3728,13 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i64 [[TMP20]], i64* [[DOTOMP_IV]], align 8 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK12-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] // CHECK12-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK12-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP24]], 0 // CHECK12-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 // CHECK12-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] @@ -3743,16 +3743,16 @@ int main (int argc, char **argv) { // CHECK12-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] // CHECK12-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK12-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK12-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP27]], 0 // CHECK12-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 // CHECK12-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] // CHECK12-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 // CHECK12-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP26]], [[CONV27]] -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK12-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP28]], 0 // CHECK12-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 // CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] @@ -3762,21 +3762,21 @@ int main (int argc, char **argv) { // CHECK12-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 // CHECK12-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] // CHECK12-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 -// CHECK12-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[I13]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[I13]], align 4 // CHECK12-NEXT: [[TMP30:%.*]] = mul nsw i32 [[TMP29]], [[TMP3]] // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP30]] -// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[J14]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[J14]], align 4 // CHECK12-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP31]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX38]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK12-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP32]], 1 -// CHECK12-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK12-NEXT: store i64 [[ADD39]], i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3807,7 +3807,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -3839,7 +3839,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l72 -// CHECK12-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -3849,7 +3849,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3889,21 +3889,21 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]), !llvm.access.group !15 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x [2 x i32]]*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x [2 x i32]]* [[TMP0]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3920,7 +3920,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3968,37 +3968,37 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 // CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] // CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP13]] -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[J]], align 4 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP14]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -4022,7 +4022,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4158,7 +4158,7 @@ int main (int argc, char **argv) { // CHECK13-NEXT: br label [[SIMD_IF_END]] // CHECK13: simd.if.end: // CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP28]]) // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) @@ -4167,7 +4167,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -4225,7 +4225,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4361,7 +4361,7 @@ int main (int argc, char **argv) { // CHECK14-NEXT: br label [[SIMD_IF_END]] // CHECK14: simd.if.end: // CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP28]]) // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) @@ -4370,7 +4370,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -4428,7 +4428,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4560,7 +4560,7 @@ int main (int argc, char **argv) { // CHECK15-NEXT: br label [[SIMD_IF_END]] // CHECK15: simd.if.end: // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP26]]) // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP27]]) @@ -4569,7 +4569,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -4625,7 +4625,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4757,7 +4757,7 @@ int main (int argc, char **argv) { // CHECK16-NEXT: br label [[SIMD_IF_END]] // CHECK16: simd.if.end: // CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP26]]) // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP27]]) @@ -4766,7 +4766,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp index 9c3f8841bb135d042fba72a5b7d9aadc21313d36..0d8917b3a4e24ebc1eaa52396ffa1d7250a54ed6 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp @@ -150,12 +150,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -236,7 +236,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -246,7 +246,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -284,23 +284,23 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]), !llvm.access.group !6 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -316,7 +316,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -364,28 +364,28 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -401,7 +401,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -411,7 +411,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -449,23 +449,23 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]), !llvm.access.group !15 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -481,7 +481,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -529,28 +529,28 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -566,7 +566,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -576,7 +576,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -614,43 +614,43 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 123 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], %struct.SS* [[TMP0]]), !llvm.access.group !21 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], %struct.SS* [[TMP0]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP17]], 122 // CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] // CHECK1: cond.true5: // CHECK1-NEXT: br label [[COND_END7:%.*]] // CHECK1: cond.false6: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: br label [[COND_END7]] // CHECK1: cond.end7: // CHECK1-NEXT: [[COND8:%.*]] = phi i32 [ 122, [[COND_TRUE5]] ], [ [[TMP18]], [[COND_FALSE6]] ] -// CHECK1-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK1-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -666,7 +666,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -714,28 +714,28 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -761,12 +761,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -847,7 +847,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -857,7 +857,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -895,23 +895,23 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]), !llvm.access.group !6 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -927,7 +927,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -975,28 +975,28 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1012,7 +1012,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1022,7 +1022,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1060,23 +1060,23 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]), !llvm.access.group !15 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], %struct.SS* [[TMP0]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1092,7 +1092,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1140,28 +1140,28 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1177,7 +1177,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1187,7 +1187,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1225,43 +1225,43 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 123 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], %struct.SS* [[TMP0]]), !llvm.access.group !21 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], %struct.SS* [[TMP0]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP17]], 122 // CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] // CHECK2: cond.true5: // CHECK2-NEXT: br label [[COND_END7:%.*]] // CHECK2: cond.false6: -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: br label [[COND_END7]] // CHECK2: cond.end7: // CHECK2-NEXT: [[COND8:%.*]] = phi i32 [ 122, [[COND_TRUE5]] ], [ [[TMP18]], [[COND_FALSE6]] ] -// CHECK2-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK2-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1277,7 +1277,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1325,28 +1325,28 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1372,12 +1372,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -1458,7 +1458,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1468,7 +1468,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1506,21 +1506,21 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !7 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]), !llvm.access.group !7 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !7 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1536,7 +1536,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1582,27 +1582,27 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1618,7 +1618,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1628,7 +1628,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1666,21 +1666,21 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !16 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]), !llvm.access.group !16 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !16 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1696,7 +1696,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1742,27 +1742,27 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1778,7 +1778,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1788,7 +1788,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1826,41 +1826,41 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 123 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]], %struct.SS* [[TMP0]]), !llvm.access.group !22 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]], %struct.SS* [[TMP0]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP15]], 122 // CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] // CHECK3: cond.true5: // CHECK3-NEXT: br label [[COND_END7:%.*]] // CHECK3: cond.false6: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: br label [[COND_END7]] // CHECK3: cond.end7: // CHECK3-NEXT: [[COND8:%.*]] = phi i32 [ 122, [[COND_TRUE5]] ], [ [[TMP16]], [[COND_FALSE6]] ] -// CHECK3-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK3-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1876,7 +1876,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1922,27 +1922,27 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1968,12 +1968,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -2054,7 +2054,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2064,7 +2064,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2102,21 +2102,21 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !7 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !7 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]), !llvm.access.group !7 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !7 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2132,7 +2132,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2178,27 +2178,27 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2214,7 +2214,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2224,7 +2224,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2262,21 +2262,21 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !16 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !16 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]), !llvm.access.group !16 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], %struct.SS* [[TMP0]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !16 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2292,7 +2292,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2338,27 +2338,27 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !19 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19 +// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2374,7 +2374,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2384,7 +2384,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2422,41 +2422,41 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 123 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]], %struct.SS* [[TMP0]]), !llvm.access.group !22 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, %struct.SS*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]], %struct.SS* [[TMP0]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22 +// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP15]], 122 // CHECK4-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] // CHECK4: cond.true5: // CHECK4-NEXT: br label [[COND_END7:%.*]] // CHECK4: cond.false6: -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: br label [[COND_END7]] // CHECK4: cond.end7: // CHECK4-NEXT: [[COND8:%.*]] = phi i32 [ 122, [[COND_TRUE5]] ], [ [[TMP16]], [[COND_FALSE6]] ] -// CHECK4-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK4-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2472,7 +2472,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2518,27 +2518,27 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !25 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], [123 x i32]* [[A]], i32 0, i32 [[TMP11]] -// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 +// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2564,12 +2564,12 @@ int main (int argc, char **argv) { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -2689,12 +2689,12 @@ int main (int argc, char **argv) { // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -2814,12 +2814,12 @@ int main (int argc, char **argv) { // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -2936,12 +2936,12 @@ int main (int argc, char **argv) { // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK8-NEXT: ret i32 [[CALL]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -3055,7 +3055,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3283,7 +3283,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK9: omp_offload.cont33: // CHECK9-NEXT: [[TMP101:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP101]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP101]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP102:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP102]]) @@ -3292,7 +3292,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -3308,7 +3308,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3370,23 +3370,23 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !9 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3411,7 +3411,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3483,27 +3483,27 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !13 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3528,7 +3528,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l113 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -3544,7 +3544,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3606,23 +3606,23 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !18 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3647,7 +3647,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3719,27 +3719,27 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !21 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !21 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3764,7 +3764,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l118 -// CHECK9-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -3791,7 +3791,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3858,51 +3858,51 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK9-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !24 +// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] // CHECK9-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] // CHECK9: cond.true12: -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK9-NEXT: br label [[COND_END14:%.*]] // CHECK9: cond.false13: -// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: br label [[COND_END14]] // CHECK9: cond.end14: // CHECK9-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE12]] ], [ [[TMP32]], [[COND_FALSE13]] ] -// CHECK9-NEXT: store i32 [[COND15]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK9-NEXT: store i32 [[COND15]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3927,7 +3927,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4002,27 +4002,27 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4047,7 +4047,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -4137,7 +4137,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l86 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -4147,7 +4147,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4185,23 +4185,23 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]), !llvm.access.group !30 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4217,7 +4217,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4265,27 +4265,27 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4301,7 +4301,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l91 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -4311,7 +4311,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4349,23 +4349,23 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]), !llvm.access.group !36 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4381,7 +4381,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4429,27 +4429,27 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4465,7 +4465,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l96 -// CHECK9-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -4486,7 +4486,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4529,47 +4529,47 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42 +// CHECK9-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP20]], 9 // CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] // CHECK9: cond.true6: // CHECK9-NEXT: br label [[COND_END8:%.*]] // CHECK9: cond.false7: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: br label [[COND_END8]] // CHECK9: cond.end8: // CHECK9-NEXT: [[COND9:%.*]] = phi i32 [ 9, [[COND_TRUE6]] ], [ [[TMP21]], [[COND_FALSE7]] ] -// CHECK9-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK9-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK9-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4585,7 +4585,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4636,27 +4636,27 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4679,7 +4679,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4907,7 +4907,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK10: omp_offload.cont33: // CHECK10-NEXT: [[TMP101:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP101]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP101]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP102:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP102]]) @@ -4916,7 +4916,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -4932,7 +4932,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4994,23 +4994,23 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !9 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5035,7 +5035,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5107,27 +5107,27 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5152,7 +5152,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l113 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -5168,7 +5168,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5230,23 +5230,23 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !18 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP17]], i64 [[TMP19]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5271,7 +5271,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5343,27 +5343,27 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !21 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !21 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5388,7 +5388,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l118 -// CHECK10-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -5415,7 +5415,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5482,51 +5482,51 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK10-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !24 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]), !llvm.access.group !24 +// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV7]], align 4 +// CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*, i64, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP18]], i64 [[TMP20]], i32* [[TMP0]], i64 [[TMP1]], i32* [[TMP2]], i64 [[TMP22]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], [[TMP30]] // CHECK10-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] // CHECK10: cond.true12: -// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK10-NEXT: br label [[COND_END14:%.*]] // CHECK10: cond.false13: -// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: br label [[COND_END14]] // CHECK10: cond.end14: // CHECK10-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE12]] ], [ [[TMP32]], [[COND_FALSE13]] ] -// CHECK10-NEXT: store i32 [[COND15]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK10-NEXT: store i32 [[COND15]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5551,7 +5551,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5626,27 +5626,27 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I6]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I6]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5671,7 +5671,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -5761,7 +5761,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l86 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -5771,7 +5771,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5809,23 +5809,23 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]), !llvm.access.group !30 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5841,7 +5841,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5889,27 +5889,27 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5925,7 +5925,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l91 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -5935,7 +5935,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5973,23 +5973,23 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]), !llvm.access.group !36 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -6005,7 +6005,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6053,27 +6053,27 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -6089,7 +6089,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l96 -// CHECK10-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -6110,7 +6110,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6153,47 +6153,47 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !42 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]), !llvm.access.group !42 +// CHECK10-NEXT: store i32 [[TMP12]], i32* [[CONV2]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], [10 x i32]* [[TMP0]], i64 [[TMP13]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP20]], 9 // CHECK10-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] // CHECK10: cond.true6: // CHECK10-NEXT: br label [[COND_END8:%.*]] // CHECK10: cond.false7: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: br label [[COND_END8]] // CHECK10: cond.end8: // CHECK10-NEXT: [[COND9:%.*]] = phi i32 [ 9, [[COND_TRUE6]] ], [ [[TMP21]], [[COND_FALSE7]] ] -// CHECK10-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK10-NEXT: store i32 [[COND9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK10-NEXT: store i32 [[TMP22]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -6209,7 +6209,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6260,27 +6260,27 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -6303,7 +6303,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -6529,7 +6529,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT30]] // CHECK11: omp_offload.cont30: // CHECK11-NEXT: [[TMP103:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP103]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP103]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP104:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP104]]) @@ -6538,7 +6538,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -6553,7 +6553,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6615,21 +6615,21 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !10 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -6654,7 +6654,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6724,26 +6724,26 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !14 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -6768,7 +6768,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l113 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -6783,7 +6783,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6845,21 +6845,21 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !19 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !19 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -6884,7 +6884,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6954,26 +6954,26 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !22 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -6998,7 +6998,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l118 -// CHECK11-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -7022,7 +7022,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7088,48 +7088,48 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !25 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK11-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP20]]), !llvm.access.group !25 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP20]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25 +// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25 +// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !25 +// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK11-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] // CHECK11-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] // CHECK11: cond.true11: -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !25 +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK11-NEXT: br label [[COND_END13:%.*]] // CHECK11: cond.false12: -// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 +// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: br label [[COND_END13]] // CHECK11: cond.end13: // CHECK11-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE11]] ], [ [[TMP30]], [[COND_FALSE12]] ] -// CHECK11-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK11-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7154,7 +7154,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7226,26 +7226,26 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7270,7 +7270,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -7359,7 +7359,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l86 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -7369,7 +7369,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7407,21 +7407,21 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !31 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]), !llvm.access.group !31 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !31 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7437,7 +7437,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7483,26 +7483,26 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !34 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !34 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !34 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7518,7 +7518,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l91 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -7528,7 +7528,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7566,21 +7566,21 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !37 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !37 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !37 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]), !llvm.access.group !37 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !37 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7596,7 +7596,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7642,26 +7642,26 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !40 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !40 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !40 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !40 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7677,7 +7677,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l96 -// CHECK11-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -7696,7 +7696,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7738,44 +7738,44 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]), !llvm.access.group !43 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9 // CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] // CHECK11: cond.true5: // CHECK11-NEXT: br label [[COND_END7:%.*]] // CHECK11: cond.false6: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: br label [[COND_END7]] // CHECK11: cond.end7: // CHECK11-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ] -// CHECK11-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] +// CHECK11-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7791,7 +7791,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7839,26 +7839,26 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !46 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !46 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !46 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !46 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -7881,7 +7881,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -8107,7 +8107,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT30]] // CHECK12: omp_offload.cont30: // CHECK12-NEXT: [[TMP103:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP103]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP103]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP104:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP104]]) @@ -8116,7 +8116,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -8131,7 +8131,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8193,21 +8193,21 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !10 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -8232,7 +8232,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8302,26 +8302,26 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -8346,7 +8346,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l113 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -8361,7 +8361,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8423,21 +8423,21 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]), !llvm.access.group !19 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP16]], i32 [[TMP17]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !19 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -8462,7 +8462,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8532,26 +8532,26 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4, !llvm.access.group !22 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -8576,7 +8576,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l118 -// CHECK12-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -8600,7 +8600,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8666,48 +8666,48 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !25 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK12-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] // CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP20]]), !llvm.access.group !25 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP19]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*, i32, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP17]], i32 [[TMP18]], i32* [[TMP0]], i32 [[TMP1]], i32* [[TMP2]], i32 [[TMP20]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25 +// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25 +// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !25 +// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK12-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP27]], [[TMP28]] // CHECK12-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] // CHECK12: cond.true11: -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !25 +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 // CHECK12-NEXT: br label [[COND_END13:%.*]] // CHECK12: cond.false12: -// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 +// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: br label [[COND_END13]] // CHECK12: cond.end13: // CHECK12-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP29]], [[COND_TRUE11]] ], [ [[TMP30]], [[COND_FALSE12]] ] -// CHECK12-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK12-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -8732,7 +8732,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8804,26 +8804,26 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] // CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4, !llvm.access.group !28 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I4]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP19]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -8848,7 +8848,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -8937,7 +8937,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l86 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -8947,7 +8947,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8985,21 +8985,21 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !31 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !31 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]), !llvm.access.group !31 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !31 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -9015,7 +9015,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9061,26 +9061,26 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !34 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !34 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !34 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -9096,7 +9096,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l91 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -9106,7 +9106,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9144,21 +9144,21 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !37 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !37 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !37 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]), !llvm.access.group !37 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !37 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -9174,7 +9174,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9220,26 +9220,26 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !40 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !40 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !40 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !40 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -9255,7 +9255,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l96 -// CHECK12-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -9274,7 +9274,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9316,44 +9316,44 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP7]], 10 // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]), !llvm.access.group !43 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 +// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], [10 x i32]* [[TMP0]], i32 [[TMP11]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9 // CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]] // CHECK12: cond.true5: // CHECK12-NEXT: br label [[COND_END7:%.*]] // CHECK12: cond.false6: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: br label [[COND_END7]] // CHECK12: cond.end7: // CHECK12-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ] -// CHECK12-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] +// CHECK12-NEXT: store i32 [[COND8]], i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -9369,7 +9369,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -9417,26 +9417,26 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !46 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !46 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !46 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !46 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -9459,7 +9459,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -9654,7 +9654,7 @@ int main (int argc, char **argv) { // CHECK13-NEXT: br label [[SIMD_IF_END68]] // CHECK13: simd.if.end68: // CHECK13-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]]) +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP37]]) // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP38:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP38]]) @@ -9663,7 +9663,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -9779,7 +9779,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -9974,7 +9974,7 @@ int main (int argc, char **argv) { // CHECK14-NEXT: br label [[SIMD_IF_END68]] // CHECK14: simd.if.end68: // CHECK14-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]]) +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP37]]) // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[TMP38:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP38]]) @@ -9983,7 +9983,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -10099,7 +10099,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -10290,7 +10290,7 @@ int main (int argc, char **argv) { // CHECK15-NEXT: br label [[SIMD_IF_END66]] // CHECK15: simd.if.end66: // CHECK15-NEXT: [[TMP36:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP36]]) // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP37:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP37]]) @@ -10299,7 +10299,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -10412,7 +10412,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -10603,7 +10603,7 @@ int main (int argc, char **argv) { // CHECK16-NEXT: br label [[SIMD_IF_END66]] // CHECK16: simd.if.end66: // CHECK16-NEXT: [[TMP36:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP36]]) // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[TMP37:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP37]]) @@ -10612,7 +10612,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp index b7dc69c2994241ac287bcdcb5a6eca46abe9da27..80291b5a3aa6bfaa0707a13869a73e2360a3de6e 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp @@ -182,33 +182,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -221,7 +221,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -232,14 +232,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -247,12 +247,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -260,7 +260,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -268,7 +268,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -287,7 +287,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -361,12 +361,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -398,7 +398,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -448,17 +448,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -477,33 +477,33 @@ int main() { // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5 +// CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5 +// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -517,14 +517,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done11: @@ -532,17 +532,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -550,22 +550,22 @@ int main() { // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -623,17 +623,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done6: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -652,40 +652,40 @@ int main() { // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9 -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !9 +// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -699,14 +699,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done15: @@ -728,14 +728,14 @@ int main() { // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -795,17 +795,17 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP32]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -818,7 +818,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -838,7 +838,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -847,17 +847,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -865,12 +865,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -897,7 +897,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -946,18 +946,18 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -977,30 +977,30 @@ int main() { // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14 +// CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 +// CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1014,14 +1014,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done11: @@ -1029,7 +1029,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1037,12 +1037,12 @@ int main() { // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1100,18 +1100,18 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done6: // CHECK1-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK1-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -1131,37 +1131,37 @@ int main() { // CHECK1-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK1-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8* // CHECK1-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false), !llvm.access.group !17 +// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1175,14 +1175,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done15: @@ -1190,17 +1190,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1212,7 +1212,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1228,7 +1228,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1247,7 +1247,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1274,33 +1274,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1313,7 +1313,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1324,14 +1324,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1339,12 +1339,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1352,7 +1352,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1360,7 +1360,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1379,7 +1379,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -1453,12 +1453,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101 -// CHECK2-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1490,7 +1490,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1540,17 +1540,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1569,33 +1569,33 @@ int main() { // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5 +// CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4 +// CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !5 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]), !llvm.access.group !5 +// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4 +// CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1609,14 +1609,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done11: @@ -1624,17 +1624,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1642,22 +1642,22 @@ int main() { // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1715,17 +1715,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done6: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR7]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1744,40 +1744,40 @@ int main() { // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9 -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !9 +// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1791,14 +1791,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR7]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done15: @@ -1820,14 +1820,14 @@ int main() { // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1887,17 +1887,17 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP32]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1910,7 +1910,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1930,7 +1930,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1939,17 +1939,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1957,12 +1957,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK2-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1989,7 +1989,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2038,18 +2038,18 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -2069,30 +2069,30 @@ int main() { // CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !14 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]), !llvm.access.group !14 +// CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4 +// CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 +// CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2106,14 +2106,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done11: @@ -2121,7 +2121,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -2129,12 +2129,12 @@ int main() { // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2192,18 +2192,18 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done6: // CHECK2-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR7]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP8]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP8]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK2-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -2223,37 +2223,37 @@ int main() { // CHECK2-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8 +// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK2-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8* // CHECK2-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false), !llvm.access.group !17 +// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2267,14 +2267,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR7]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done15: @@ -2282,17 +2282,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2304,7 +2304,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2320,7 +2320,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -2339,7 +2339,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2366,33 +2366,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2405,7 +2405,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2416,14 +2416,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2431,12 +2431,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -2444,7 +2444,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -2452,7 +2452,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2471,7 +2471,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -2543,12 +2543,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2576,7 +2576,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2624,17 +2624,17 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done3: -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2653,29 +2653,29 @@ int main() { // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]), !llvm.access.group !6 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2689,14 +2689,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done8: @@ -2704,17 +2704,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2722,22 +2722,22 @@ int main() { // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2791,17 +2791,17 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done3: -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2820,38 +2820,38 @@ int main() { // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]] -// CHECK3-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]] // CHECK3-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* // CHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !10 -// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) +// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2865,14 +2865,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -2894,14 +2894,14 @@ int main() { // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2960,17 +2960,17 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP32]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2983,7 +2983,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -3003,7 +3003,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -3012,17 +3012,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3030,12 +3030,12 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3060,7 +3060,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3108,18 +3108,18 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done4: // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -3139,27 +3139,27 @@ int main() { // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]), !llvm.access.group !15 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -3173,14 +3173,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done10: @@ -3188,7 +3188,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3196,12 +3196,12 @@ int main() { // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3256,18 +3256,18 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done4: // CHECK3-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -3287,35 +3287,35 @@ int main() { // CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]] -// CHECK3-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]] // CHECK3-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* // CHECK3-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false), !llvm.access.group !18 +// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -3329,14 +3329,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -3344,17 +3344,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3366,7 +3366,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3382,7 +3382,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3401,7 +3401,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3428,33 +3428,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3467,7 +3467,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3478,14 +3478,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3493,12 +3493,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -3506,7 +3506,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -3514,7 +3514,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3533,7 +3533,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -3605,12 +3605,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101 -// CHECK4-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3638,7 +3638,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3686,17 +3686,17 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done3: -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3715,29 +3715,29 @@ int main() { // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]), !llvm.access.group !6 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -3751,14 +3751,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done8: @@ -3766,17 +3766,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -3784,22 +3784,22 @@ int main() { // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3853,17 +3853,17 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done3: -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3882,38 +3882,38 @@ int main() { // CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]] -// CHECK4-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]] // CHECK4-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* // CHECK4-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !10 -// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) +// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -// CHECK4-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -3927,14 +3927,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done11: @@ -3956,14 +3956,14 @@ int main() { // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4022,17 +4022,17 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP32]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -4045,7 +4045,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -4065,7 +4065,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -4074,17 +4074,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4092,12 +4092,12 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK4-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -4122,7 +4122,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4170,18 +4170,18 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done4: // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -4201,27 +4201,27 @@ int main() { // CHECK4-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]), !llvm.access.group !15 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK4-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -4235,14 +4235,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done10: @@ -4250,7 +4250,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -4258,12 +4258,12 @@ int main() { // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4318,18 +4318,18 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done4: // CHECK4-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 @@ -4349,35 +4349,35 @@ int main() { // CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]] -// CHECK4-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]] // CHECK4-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* // CHECK4-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8* -// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false), !llvm.access.group !18 +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1 -// CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -4391,14 +4391,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done12: @@ -4406,17 +4406,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4428,7 +4428,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4444,7 +4444,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -4463,7 +4463,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4490,42 +4490,42 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4533,12 +4533,12 @@ int main() { // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4546,7 +4546,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -4556,7 +4556,7 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // @@ -4610,7 +4610,7 @@ int main() { // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK5-NEXT: ret i32 [[CALL]] // // @@ -4630,14 +4630,14 @@ int main() { // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -4689,17 +4689,17 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done6: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP17]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4712,7 +4712,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4721,7 +4721,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4738,17 +4738,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4756,22 +4756,22 @@ int main() { // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4783,7 +4783,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4799,7 +4799,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4819,42 +4819,42 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4862,12 +4862,12 @@ int main() { // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4875,7 +4875,7 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: @@ -4885,7 +4885,7 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // @@ -4939,7 +4939,7 @@ int main() { // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK6-NEXT: ret i32 [[CALL]] // // @@ -4959,14 +4959,14 @@ int main() { // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -5018,17 +5018,17 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done6: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP17]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5041,7 +5041,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5050,7 +5050,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5067,17 +5067,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5085,22 +5085,22 @@ int main() { // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5112,7 +5112,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5128,7 +5128,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5148,42 +5148,42 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5191,12 +5191,12 @@ int main() { // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -5204,7 +5204,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -5214,7 +5214,7 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // @@ -5266,7 +5266,7 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK7-NEXT: ret i32 [[CALL]] // // @@ -5286,14 +5286,14 @@ int main() { // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -5343,17 +5343,17 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done5: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP17]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5366,7 +5366,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5375,7 +5375,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5392,17 +5392,17 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5410,22 +5410,22 @@ int main() { // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5437,7 +5437,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5453,7 +5453,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5473,42 +5473,42 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5516,12 +5516,12 @@ int main() { // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -5529,7 +5529,7 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done1: @@ -5539,7 +5539,7 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // @@ -5591,7 +5591,7 @@ int main() { // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK8-NEXT: ret i32 [[CALL]] // // @@ -5611,14 +5611,14 @@ int main() { // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -5668,17 +5668,17 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done5: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP17]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5691,7 +5691,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5700,7 +5700,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5717,17 +5717,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5735,22 +5735,22 @@ int main() { // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5762,7 +5762,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5778,7 +5778,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5798,33 +5798,33 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5837,7 +5837,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5848,14 +5848,14 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5863,12 +5863,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -5876,7 +5876,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -5884,7 +5884,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5903,7 +5903,7 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // @@ -5914,12 +5914,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 @@ -5953,7 +5953,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6002,36 +6002,36 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8, !llvm.access.group !4 +// CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4 +// CHECK9-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -6047,7 +6047,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6104,35 +6104,35 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 -// CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8 -// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8 +// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 -// CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -6166,33 +6166,33 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6205,7 +6205,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6216,14 +6216,14 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6231,12 +6231,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -6244,7 +6244,7 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: @@ -6252,7 +6252,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6271,7 +6271,7 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // @@ -6282,12 +6282,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK10-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK10-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 @@ -6321,7 +6321,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6370,36 +6370,36 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK10-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4 // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8, !llvm.access.group !4 +// CHECK10-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8 // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group !4 +// CHECK10-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -6415,7 +6415,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6472,35 +6472,35 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !8 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 -// CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8 -// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !8 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8, !llvm.access.group !8 +// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !8 -// CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8, !llvm.access.group !8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8 +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -6534,42 +6534,42 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6577,12 +6577,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -6590,7 +6590,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -6600,7 +6600,7 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // @@ -6611,12 +6611,12 @@ int main() { // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: ret i32 0 // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6629,7 +6629,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6638,7 +6638,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6666,42 +6666,42 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6709,12 +6709,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -6722,7 +6722,7 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done1: @@ -6732,7 +6732,7 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // @@ -6743,12 +6743,12 @@ int main() { // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK12-NEXT: ret i32 0 // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6761,7 +6761,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6770,7 +6770,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp index c6cdbe83f21ea55b1531824e9377ad34698c50dc..265e94c21ed3c6eedaf2a854ec2f79936509c353 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp @@ -142,7 +142,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -177,22 +177,22 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !11 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -209,7 +209,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -254,22 +254,22 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -293,7 +293,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -329,26 +329,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !20 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !20 -// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !20 -// CHECK1-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !20 -// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 +// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK1-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !20 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -365,7 +365,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -410,23 +410,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 -// CHECK1-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !23 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: call void @_Z9gtid_testv() // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -501,7 +501,7 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK1: omp_offload.cont7: // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -513,7 +513,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -548,22 +548,22 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !26 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !26 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !26 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -580,7 +580,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -625,23 +625,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29 -// CHECK1-NEXT: call void @_Z3fn4v(), !llvm.access.group !29 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: call void @_Z3fn4v() // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -665,7 +665,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -701,26 +701,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !32 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !32 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !32 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !32 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !32 -// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !32 -// CHECK1-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !32 -// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !32 +// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK1-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !32 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -737,7 +737,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -782,23 +782,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35 -// CHECK1-NEXT: call void @_Z3fn5v(), !llvm.access.group !35 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: call void @_Z3fn5v() // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -815,7 +815,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK1-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -837,7 +837,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -876,35 +876,35 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !38 +// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1: omp_if.then: -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !38 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38 -// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !38 -// CHECK1-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !38 -// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38 +// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK1-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !38 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -921,7 +921,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -966,23 +966,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !41 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !41 -// CHECK1-NEXT: call void @_Z3fn6v(), !llvm.access.group !41 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: call void @_Z3fn6v() // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -999,7 +999,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK1-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1067,7 +1067,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1102,22 +1102,22 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !44 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !44 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !44 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !44 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !44 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1134,7 +1134,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1179,23 +1179,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47 -// CHECK1-NEXT: call void @_Z3fn1v(), !llvm.access.group !47 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: call void @_Z3fn1v() // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1219,7 +1219,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1255,26 +1255,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !50 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !50 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !50 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !50 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !50 -// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !50 -// CHECK1-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !50 -// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !50 +// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK1-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !50 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP51:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1291,7 +1291,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1336,23 +1336,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !53 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !53 -// CHECK1-NEXT: call void @_Z3fn2v(), !llvm.access.group !53 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: call void @_Z3fn2v() // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP54:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1369,7 +1369,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 -// CHECK1-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -1391,7 +1391,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1430,35 +1430,35 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !56 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !56 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !56 +// CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1: omp_if.then: -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !56 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !56 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !56 -// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !56 -// CHECK1-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !56 -// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !56 +// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK1-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !56 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !56 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !56 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP57:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1475,7 +1475,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1520,23 +1520,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !59 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !59 -// CHECK1-NEXT: call void @_Z3fn3v(), !llvm.access.group !59 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: call void @_Z3fn3v() // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP60:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1591,7 +1591,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1626,22 +1626,22 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !11 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1658,7 +1658,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1703,22 +1703,22 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1742,7 +1742,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1778,26 +1778,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !20 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !20 -// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !20 -// CHECK2-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !20 -// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 +// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK2-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !20 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1814,7 +1814,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1859,23 +1859,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 -// CHECK2-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !23 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: call void @_Z9gtid_testv() // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1950,7 +1950,7 @@ int main() { // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK2: omp_offload.cont7: // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -1962,7 +1962,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1997,22 +1997,22 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !26 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !26 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !26 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2029,7 +2029,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2074,23 +2074,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29 -// CHECK2-NEXT: call void @_Z3fn4v(), !llvm.access.group !29 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: call void @_Z3fn4v() // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2114,7 +2114,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2150,26 +2150,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !32 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !32 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !32 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !32 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !32 -// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !32 -// CHECK2-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !32 -// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !32 +// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK2-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !32 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2186,7 +2186,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2231,23 +2231,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35 -// CHECK2-NEXT: call void @_Z3fn5v(), !llvm.access.group !35 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: call void @_Z3fn5v() // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2264,7 +2264,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK2-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -2286,7 +2286,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2325,35 +2325,35 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !38 +// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2: omp_if.then: -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !38 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2: omp_if.else: -// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38 -// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !38 -// CHECK2-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !38 -// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38 +// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK2-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK2-NEXT: br label [[OMP_IF_END]] // CHECK2: omp_if.end: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !38 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2370,7 +2370,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2415,23 +2415,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !41 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !41 -// CHECK2-NEXT: call void @_Z3fn6v(), !llvm.access.group !41 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: call void @_Z3fn6v() // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2448,7 +2448,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK2-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK2-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -2516,7 +2516,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2551,22 +2551,22 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !44 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !44 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !44 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !44 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !44 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2583,7 +2583,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2628,23 +2628,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47 -// CHECK2-NEXT: call void @_Z3fn1v(), !llvm.access.group !47 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: call void @_Z3fn1v() // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2668,7 +2668,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2704,26 +2704,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !50 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !50 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !50 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !50 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !50 -// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !50 -// CHECK2-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !50 -// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !50 +// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK2-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !50 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP51:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2740,7 +2740,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2785,23 +2785,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !53 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !53 -// CHECK2-NEXT: call void @_Z3fn2v(), !llvm.access.group !53 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: call void @_Z3fn2v() // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP54:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2818,7 +2818,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 -// CHECK2-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -2840,7 +2840,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2879,35 +2879,35 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !56 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !56 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !56 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !56 +// CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK2: omp_if.then: -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !56 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] // CHECK2: omp_if.else: -// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !56 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !56 -// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !56 -// CHECK2-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !56 -// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !56 +// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK2-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK2-NEXT: br label [[OMP_IF_END]] // CHECK2: omp_if.end: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !56 -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !56 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !56 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP57:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2924,7 +2924,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2969,23 +2969,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !59 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !59 -// CHECK2-NEXT: call void @_Z3fn3v(), !llvm.access.group !59 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: call void @_Z3fn3v() // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP60:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -3040,7 +3040,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3075,22 +3075,22 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !11 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -3107,7 +3107,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3152,22 +3152,22 @@ int main() { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -3191,7 +3191,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3227,26 +3227,26 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !20 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !20 -// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !20 -// CHECK3-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !20 -// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !20 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -3263,7 +3263,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3308,23 +3308,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 -// CHECK3-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !23 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: call void @_Z9gtid_testv() // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -3399,7 +3399,7 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK3: omp_offload.cont7: // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -3411,7 +3411,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3446,22 +3446,22 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !26 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !26 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !26 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -3478,7 +3478,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3523,23 +3523,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29 -// CHECK3-NEXT: call void @_Z3fn4v(), !llvm.access.group !29 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: call void @_Z3fn4v() // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -3563,7 +3563,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3635,7 +3635,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3713,7 +3713,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK3-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -3735,7 +3735,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3781,41 +3781,41 @@ int main() { // CHECK3: omp_if.then: // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !35 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK3-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !35 +// CHECK3-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8 -// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !35 -// CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !35 -// CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !35 +// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 +// CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK3-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3: omp_if.then5: -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !35 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !35 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !35 -// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !35 -// CHECK3-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]], !llvm.access.group !35 -// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !35 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !35 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_IF_END22:%.*]] @@ -3875,7 +3875,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3927,23 +3927,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 -// CHECK3-NEXT: call void @_Z3fn6v(), !llvm.access.group !39 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: call void @_Z3fn6v() // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] @@ -4003,7 +4003,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4055,23 +4055,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !43 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43 -// CHECK3-NEXT: call void @_Z3fn6v(), !llvm.access.group !43 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: call void @_Z3fn6v() // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] @@ -4131,7 +4131,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK3-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK3-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -4199,7 +4199,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4234,22 +4234,22 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !47 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !47 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !47 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !47 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !47 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4266,7 +4266,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4311,23 +4311,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !50 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !50 -// CHECK3-NEXT: call void @_Z3fn1v(), !llvm.access.group !50 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: call void @_Z3fn1v() // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP51:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4351,7 +4351,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4423,7 +4423,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4501,7 +4501,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 -// CHECK3-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -4523,7 +4523,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4562,35 +4562,35 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !55 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !55 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !55 +// CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK3: omp_if.then: -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !55 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] // CHECK3: omp_if.else: -// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !55 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !55 -// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !55 -// CHECK3-NEXT: call void @.omp_outlined..16(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !55 -// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !55 +// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK3-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK3-NEXT: call void @.omp_outlined..16(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK3-NEXT: br label [[OMP_IF_END]] // CHECK3: omp_if.end: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !55 -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !55 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !55 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP56:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4607,7 +4607,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4652,23 +4652,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !58 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !58 -// CHECK3-NEXT: call void @_Z3fn3v(), !llvm.access.group !58 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: call void @_Z3fn3v() // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP59:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4723,7 +4723,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4758,22 +4758,22 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !11 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4790,7 +4790,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4835,22 +4835,22 @@ int main() { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4874,7 +4874,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4910,26 +4910,26 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !20 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !20 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !20 -// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !20 -// CHECK4-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !20 -// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !20 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !20 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4946,7 +4946,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4991,23 +4991,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 -// CHECK4-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !23 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: call void @_Z9gtid_testv() // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -5082,7 +5082,7 @@ int main() { // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK4: omp_offload.cont7: // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK4-NEXT: ret i32 [[CALL]] // // @@ -5094,7 +5094,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5129,22 +5129,22 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !26 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !26 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !26 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !26 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -5161,7 +5161,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5206,23 +5206,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29 -// CHECK4-NEXT: call void @_Z3fn4v(), !llvm.access.group !29 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: call void @_Z3fn4v() // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -5246,7 +5246,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5318,7 +5318,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5396,7 +5396,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK4-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -5418,7 +5418,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5464,41 +5464,41 @@ int main() { // CHECK4: omp_if.then: // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !35 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !35 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK4-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !35 +// CHECK4-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8 -// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !35 -// CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !35 -// CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !35 +// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 +// CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK4-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4: omp_if.then5: -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !35 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] // CHECK4: omp_if.else: -// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !35 -// CHECK4-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !35 -// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !35 -// CHECK4-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]], !llvm.access.group !35 -// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !35 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK4-NEXT: br label [[OMP_IF_END]] // CHECK4: omp_if.end: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !35 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_IF_END22:%.*]] @@ -5558,7 +5558,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5610,23 +5610,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 -// CHECK4-NEXT: call void @_Z3fn6v(), !llvm.access.group !39 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: call void @_Z3fn6v() // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] @@ -5686,7 +5686,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5738,23 +5738,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !43 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43 -// CHECK4-NEXT: call void @_Z3fn6v(), !llvm.access.group !43 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: call void @_Z3fn6v() // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] @@ -5814,7 +5814,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK4-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK4-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -5882,7 +5882,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5917,22 +5917,22 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !47 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !47 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !47 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !47 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !47 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -5949,7 +5949,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5994,23 +5994,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !50 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !50 -// CHECK4-NEXT: call void @_Z3fn1v(), !llvm.access.group !50 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: call void @_Z3fn1v() // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP51:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -6034,7 +6034,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6106,7 +6106,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6184,7 +6184,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 -// CHECK4-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -6206,7 +6206,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6245,35 +6245,35 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !55 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !55 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !55 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !55 +// CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK4: omp_if.then: -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !55 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] // CHECK4: omp_if.else: -// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !55 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !55 -// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !55 -// CHECK4-NEXT: call void @.omp_outlined..16(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !55 -// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !55 +// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK4-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK4-NEXT: call void @.omp_outlined..16(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK4-NEXT: br label [[OMP_IF_END]] // CHECK4: omp_if.end: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !55 -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !55 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !55 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP56:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -6290,7 +6290,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6335,23 +6335,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !58 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !58 -// CHECK4-NEXT: call void @_Z3fn3v(), !llvm.access.group !58 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: call void @_Z3fn3v() // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP59:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -6393,22 +6393,22 @@ int main() { // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK5-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 100, i32* [[I]], align 4 @@ -6418,23 +6418,23 @@ int main() { // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK5: omp.inner.for.cond7: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !6 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK5: omp.inner.for.body9: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK5-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !6 -// CHECK5-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !6 +// CHECK5-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK5-NEXT: call void @_Z9gtid_testv() // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK5: omp.body.continue12: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK5: omp.inner.for.inc13: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK5: omp.inner.for.end15: // CHECK5-NEXT: store i32 100, i32* [[I6]], align 4 @@ -6468,23 +6468,23 @@ int main() { // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK5-NEXT: call void @_Z3fn4v(), !llvm.access.group !9 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: call void @_Z3fn4v() // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 100, i32* [[I]], align 4 @@ -6494,23 +6494,23 @@ int main() { // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK5: omp.inner.for.cond7: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !12 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK5: omp.inner.for.body9: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK5-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !12 -// CHECK5-NEXT: call void @_Z3fn5v(), !llvm.access.group !12 +// CHECK5-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK5-NEXT: call void @_Z3fn5v() // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK5: omp.body.continue12: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK5: omp.inner.for.inc13: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 +// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK5: omp.inner.for.end15: // CHECK5-NEXT: store i32 100, i32* [[I6]], align 4 @@ -6524,33 +6524,33 @@ int main() { // CHECK5-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK5: omp.inner.for.cond21: -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !15 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK5-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK5-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK5: omp.inner.for.body23: -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK5-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !15 -// CHECK5-NEXT: call void @_Z3fn6v(), !llvm.access.group !15 +// CHECK5-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK5-NEXT: call void @_Z3fn6v() // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK5: omp.body.continue26: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK5: omp.inner.for.inc27: -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK5-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 +// CHECK5-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK5: omp.inner.for.end29: // CHECK5-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* @Arg, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP16]]) +// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP16]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK5-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK5-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -6576,23 +6576,23 @@ int main() { // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK5-NEXT: call void @_Z3fn1v(), !llvm.access.group !18 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK5-NEXT: call void @_Z3fn1v() // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK5-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 100, i32* [[I]], align 4 @@ -6602,23 +6602,23 @@ int main() { // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK5: omp.inner.for.cond7: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK5: omp.inner.for.body9: -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK5-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !21 -// CHECK5-NEXT: call void @_Z3fn2v(), !llvm.access.group !21 +// CHECK5-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK5-NEXT: call void @_Z3fn2v() // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK5: omp.body.continue12: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK5: omp.inner.for.inc13: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK5: omp.inner.for.end15: // CHECK5-NEXT: store i32 100, i32* [[I6]], align 4 @@ -6632,23 +6632,23 @@ int main() { // CHECK5-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK5: omp.inner.for.cond21: -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK5-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK5-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK5: omp.inner.for.body23: -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK5-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !24 -// CHECK5-NEXT: call void @_Z3fn3v(), !llvm.access.group !24 +// CHECK5-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK5-NEXT: call void @_Z3fn3v() // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK5: omp.body.continue26: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK5: omp.inner.for.inc27: -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK5-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK5: omp.inner.for.end29: // CHECK5-NEXT: store i32 100, i32* [[I20]], align 4 @@ -6674,22 +6674,22 @@ int main() { // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK6-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: store i32 100, i32* [[I]], align 4 @@ -6699,23 +6699,23 @@ int main() { // CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK6: omp.inner.for.cond7: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !6 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK6: omp.inner.for.body9: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK6-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !6 -// CHECK6-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !6 +// CHECK6-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK6-NEXT: call void @_Z9gtid_testv() // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK6: omp.body.continue12: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK6: omp.inner.for.inc13: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK6: omp.inner.for.end15: // CHECK6-NEXT: store i32 100, i32* [[I6]], align 4 @@ -6749,23 +6749,23 @@ int main() { // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK6-NEXT: call void @_Z3fn4v(), !llvm.access.group !9 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: call void @_Z3fn4v() // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: store i32 100, i32* [[I]], align 4 @@ -6775,23 +6775,23 @@ int main() { // CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK6: omp.inner.for.cond7: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !12 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK6: omp.inner.for.body9: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK6-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !12 -// CHECK6-NEXT: call void @_Z3fn5v(), !llvm.access.group !12 +// CHECK6-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK6-NEXT: call void @_Z3fn5v() // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK6: omp.body.continue12: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK6: omp.inner.for.inc13: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !12 +// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK6: omp.inner.for.end15: // CHECK6-NEXT: store i32 100, i32* [[I6]], align 4 @@ -6805,33 +6805,33 @@ int main() { // CHECK6-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK6: omp.inner.for.cond21: -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !15 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK6-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK6-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK6: omp.inner.for.body23: -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK6-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK6-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !15 -// CHECK6-NEXT: call void @_Z3fn6v(), !llvm.access.group !15 +// CHECK6-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK6-NEXT: call void @_Z3fn6v() // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK6: omp.body.continue26: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK6: omp.inner.for.inc27: -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK6-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !15 +// CHECK6-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK6: omp.inner.for.end29: // CHECK6-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* @Arg, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP16]]) +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP16]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK6-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK6-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -6857,23 +6857,23 @@ int main() { // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK6-NEXT: call void @_Z3fn1v(), !llvm.access.group !18 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK6-NEXT: call void @_Z3fn1v() // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK6-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: store i32 100, i32* [[I]], align 4 @@ -6883,23 +6883,23 @@ int main() { // CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK6: omp.inner.for.cond7: -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK6: omp.inner.for.body9: -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK6-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !21 -// CHECK6-NEXT: call void @_Z3fn2v(), !llvm.access.group !21 +// CHECK6-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK6-NEXT: call void @_Z3fn2v() // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK6: omp.body.continue12: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK6: omp.inner.for.inc13: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK6: omp.inner.for.end15: // CHECK6-NEXT: store i32 100, i32* [[I6]], align 4 @@ -6913,23 +6913,23 @@ int main() { // CHECK6-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK6: omp.inner.for.cond21: -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK6-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK6-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK6: omp.inner.for.body23: -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK6-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK6-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !24 -// CHECK6-NEXT: call void @_Z3fn3v(), !llvm.access.group !24 +// CHECK6-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK6-NEXT: call void @_Z3fn3v() // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK6: omp.body.continue26: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK6: omp.inner.for.inc27: -// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK6-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK6: omp.inner.for.end29: // CHECK6-NEXT: store i32 100, i32* [[I20]], align 4 @@ -6955,22 +6955,22 @@ int main() { // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 100, i32* [[I]], align 4 @@ -6980,23 +6980,23 @@ int main() { // CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK7: omp.inner.for.cond7: -// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !6 +// CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK7: omp.inner.for.body9: -// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK7-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK7-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK7-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !6 -// CHECK7-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !6 +// CHECK7-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK7-NEXT: call void @_Z9gtid_testv() // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK7: omp.body.continue12: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK7: omp.inner.for.inc13: -// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK7-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK7-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK7: omp.inner.for.end15: // CHECK7-NEXT: store i32 100, i32* [[I6]], align 4 @@ -7030,23 +7030,23 @@ int main() { // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK7-NEXT: call void @_Z3fn4v(), !llvm.access.group !9 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: call void @_Z3fn4v() // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 100, i32* [[I]], align 4 @@ -7090,23 +7090,23 @@ int main() { // CHECK7: omp_if.then: // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND22:%.*]] // CHECK7: omp.inner.for.cond22: -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK7-NEXT: [[CMP23:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK7-NEXT: br i1 [[CMP23]], label [[OMP_INNER_FOR_BODY24:%.*]], label [[OMP_INNER_FOR_END30:%.*]] // CHECK7: omp.inner.for.body24: -// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK7-NEXT: [[MUL25:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK7-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]] -// CHECK7-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4, !llvm.access.group !14 -// CHECK7-NEXT: call void @_Z3fn6v(), !llvm.access.group !14 +// CHECK7-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4 +// CHECK7-NEXT: call void @_Z3fn6v() // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]] // CHECK7: omp.body.continue27: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]] // CHECK7: omp.inner.for.inc28: -// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK7-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK7-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 +// CHECK7-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND22]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK7: omp.inner.for.end30: // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] @@ -7136,12 +7136,12 @@ int main() { // CHECK7: omp_if.end: // CHECK7-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, i32* @Arg, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP21]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP21]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK7-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK7-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -7167,23 +7167,23 @@ int main() { // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: -// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK7: omp.inner.for.body: -// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK7-NEXT: call void @_Z3fn1v(), !llvm.access.group !18 +// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK7-NEXT: call void @_Z3fn1v() // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: -// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 100, i32* [[I]], align 4 @@ -7223,23 +7223,23 @@ int main() { // CHECK7-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV19]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK7: omp.inner.for.cond21: -// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 -// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK7-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK7-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK7: omp.inner.for.body23: -// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK7-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK7-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !22 -// CHECK7-NEXT: call void @_Z3fn3v(), !llvm.access.group !22 +// CHECK7-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK7-NEXT: call void @_Z3fn3v() // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK7: omp.body.continue26: // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK7: omp.inner.for.inc27: -// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK7-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK7-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 +// CHECK7-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK7: omp.inner.for.end29: // CHECK7-NEXT: store i32 100, i32* [[I20]], align 4 @@ -7265,22 +7265,22 @@ int main() { // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 +// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 100, i32* [[I]], align 4 @@ -7290,23 +7290,23 @@ int main() { // CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK8: omp.inner.for.cond7: -// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !6 +// CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK8: omp.inner.for.body9: -// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK8-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK8-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK8-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !6 -// CHECK8-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !6 +// CHECK8-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK8-NEXT: call void @_Z9gtid_testv() // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK8: omp.body.continue12: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK8: omp.inner.for.inc13: -// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK8-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK8-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !6 +// CHECK8-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK8: omp.inner.for.end15: // CHECK8-NEXT: store i32 100, i32* [[I6]], align 4 @@ -7340,23 +7340,23 @@ int main() { // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK8-NEXT: call void @_Z3fn4v(), !llvm.access.group !9 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: call void @_Z3fn4v() // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 100, i32* [[I]], align 4 @@ -7400,23 +7400,23 @@ int main() { // CHECK8: omp_if.then: // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND22:%.*]] // CHECK8: omp.inner.for.cond22: -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK8-NEXT: [[CMP23:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK8-NEXT: br i1 [[CMP23]], label [[OMP_INNER_FOR_BODY24:%.*]], label [[OMP_INNER_FOR_END30:%.*]] // CHECK8: omp.inner.for.body24: -// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK8-NEXT: [[MUL25:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK8-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]] -// CHECK8-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4, !llvm.access.group !14 -// CHECK8-NEXT: call void @_Z3fn6v(), !llvm.access.group !14 +// CHECK8-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4 +// CHECK8-NEXT: call void @_Z3fn6v() // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]] // CHECK8: omp.body.continue27: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]] // CHECK8: omp.inner.for.inc28: -// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK8-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK8-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !14 +// CHECK8-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND22]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK8: omp.inner.for.end30: // CHECK8-NEXT: br label [[OMP_IF_END:%.*]] @@ -7446,12 +7446,12 @@ int main() { // CHECK8: omp_if.end: // CHECK8-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, i32* @Arg, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP21]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP21]]) // CHECK8-NEXT: ret i32 [[CALL]] // // // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK8-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK8-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -7477,23 +7477,23 @@ int main() { // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: -// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK8: omp.inner.for.body: -// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK8-NEXT: call void @_Z3fn1v(), !llvm.access.group !18 +// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK8-NEXT: call void @_Z3fn1v() // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: -// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 100, i32* [[I]], align 4 @@ -7533,23 +7533,23 @@ int main() { // CHECK8-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV19]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK8: omp.inner.for.cond21: -// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 -// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK8-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK8-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK8: omp.inner.for.body23: -// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK8-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK8-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !22 -// CHECK8-NEXT: call void @_Z3fn3v(), !llvm.access.group !22 +// CHECK8-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK8-NEXT: call void @_Z3fn3v() // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK8: omp.body.continue26: // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK8: omp.inner.for.inc27: -// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK8-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK8-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !22 +// CHECK8-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK8: omp.inner.for.end29: // CHECK8-NEXT: store i32 100, i32* [[I20]], align 4 @@ -7588,7 +7588,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7623,22 +7623,22 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -7655,7 +7655,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7700,22 +7700,22 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -7739,7 +7739,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7775,26 +7775,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !24 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !24 -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 +// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK9-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -7811,7 +7811,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7856,23 +7856,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 -// CHECK9-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !27 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: call void @_Z9gtid_testv() // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -7947,7 +7947,7 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK9: omp_offload.cont7: // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK9-NEXT: ret i32 [[CALL]] // // @@ -7959,7 +7959,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7994,22 +7994,22 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8026,7 +8026,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8071,23 +8071,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 -// CHECK9-NEXT: call void @_Z3fn4v(), !llvm.access.group !33 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: call void @_Z3fn4v() // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8111,7 +8111,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8147,26 +8147,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !36 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !36 -// CHECK9-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !36 -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36 +// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK9-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8183,7 +8183,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8228,23 +8228,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 -// CHECK9-NEXT: call void @_Z3fn5v(), !llvm.access.group !39 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: call void @_Z3fn5v() // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8261,7 +8261,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK9-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -8283,7 +8283,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8322,35 +8322,35 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9: omp_if.then: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !42 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9: omp_if.else: -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !42 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !42 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !42 -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !42 +// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK9-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK9-NEXT: br label [[OMP_IF_END]] // CHECK9: omp_if.end: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8367,7 +8367,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8412,23 +8412,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 -// CHECK9-NEXT: call void @_Z3fn6v(), !llvm.access.group !45 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: call void @_Z3fn6v() // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8445,7 +8445,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK9-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK9-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -8513,7 +8513,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8548,22 +8548,22 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !48 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !48 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !48 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !48 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !48 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8580,7 +8580,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8625,23 +8625,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !51 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !51 -// CHECK9-NEXT: call void @_Z3fn1v(), !llvm.access.group !51 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: call void @_Z3fn1v() // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8665,7 +8665,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8701,26 +8701,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !54 -// CHECK9-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !54 -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54 +// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK9-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !54 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8737,7 +8737,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8782,23 +8782,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !57 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !57 -// CHECK9-NEXT: call void @_Z3fn2v(), !llvm.access.group !57 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: call void @_Z3fn2v() // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP58:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8815,7 +8815,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 -// CHECK9-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -8837,7 +8837,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8876,35 +8876,35 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !60 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !60 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !60 +// CHECK9-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK9: omp_if.then: -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !60 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: br label [[OMP_IF_END:%.*]] // CHECK9: omp_if.else: -// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !60 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !60 -// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !60 -// CHECK9-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !60 -// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !60 +// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK9-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK9-NEXT: br label [[OMP_IF_END]] // CHECK9: omp_if.end: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !60 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !60 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !60 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP61:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -8921,7 +8921,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8966,23 +8966,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !63 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !63 -// CHECK9-NEXT: call void @_Z3fn3v(), !llvm.access.group !63 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: call void @_Z3fn3v() // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP64:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9037,7 +9037,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9072,22 +9072,22 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9104,7 +9104,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9149,22 +9149,22 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9188,7 +9188,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9224,26 +9224,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !24 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !24 -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 +// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK10-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9260,7 +9260,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9305,23 +9305,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 -// CHECK10-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !27 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: call void @_Z9gtid_testv() // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9396,7 +9396,7 @@ int main() { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK10: omp_offload.cont7: // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK10-NEXT: ret i32 [[CALL]] // // @@ -9408,7 +9408,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9443,22 +9443,22 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9475,7 +9475,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9520,23 +9520,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 -// CHECK10-NEXT: call void @_Z3fn4v(), !llvm.access.group !33 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: call void @_Z3fn4v() // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9560,7 +9560,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9596,26 +9596,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !36 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !36 -// CHECK10-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !36 -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36 +// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK10-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9632,7 +9632,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9677,23 +9677,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 -// CHECK10-NEXT: call void @_Z3fn5v(), !llvm.access.group !39 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: call void @_Z3fn5v() // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9710,7 +9710,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK10-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -9732,7 +9732,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9771,35 +9771,35 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10: omp_if.then: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !42 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10: omp_if.else: -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !42 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !42 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !42 -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !42 +// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK10-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK10-NEXT: br label [[OMP_IF_END]] // CHECK10: omp_if.end: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9816,7 +9816,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9861,23 +9861,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 -// CHECK10-NEXT: call void @_Z3fn6v(), !llvm.access.group !45 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: call void @_Z3fn6v() // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -9894,7 +9894,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK10-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK10-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -9962,7 +9962,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9997,22 +9997,22 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !48 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !48 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !48 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !48 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !48 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10029,7 +10029,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10074,23 +10074,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !51 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !51 -// CHECK10-NEXT: call void @_Z3fn1v(), !llvm.access.group !51 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: call void @_Z3fn1v() // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10114,7 +10114,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10150,26 +10150,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !54 -// CHECK10-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !54 -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54 +// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK10-NEXT: call void @.omp_outlined..13(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !54 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10186,7 +10186,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10231,23 +10231,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !57 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !57 -// CHECK10-NEXT: call void @_Z3fn2v(), !llvm.access.group !57 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: call void @_Z3fn2v() // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP58:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10264,7 +10264,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 -// CHECK10-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -10286,7 +10286,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10325,35 +10325,35 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !60 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !60 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !60 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !60 +// CHECK10-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK10: omp_if.then: -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !60 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: br label [[OMP_IF_END:%.*]] // CHECK10: omp_if.else: -// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !60 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !60 -// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !60 -// CHECK10-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !60 -// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !60 +// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK10-NEXT: call void @.omp_outlined..15(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK10-NEXT: br label [[OMP_IF_END]] // CHECK10: omp_if.end: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !60 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !60 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !60 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP61:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10370,7 +10370,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10415,23 +10415,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !63 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !63 -// CHECK10-NEXT: call void @_Z3fn3v(), !llvm.access.group !63 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: call void @_Z3fn3v() // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !63 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP64:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10486,7 +10486,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10521,22 +10521,22 @@ int main() { // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10553,7 +10553,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10598,22 +10598,22 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10637,7 +10637,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10673,26 +10673,26 @@ int main() { // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !24 -// CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !24 -// CHECK11-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !24 -// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 +// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK11-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10709,7 +10709,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10754,23 +10754,23 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 -// CHECK11-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !27 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: call void @_Z9gtid_testv() // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10845,7 +10845,7 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK11: omp_offload.cont7: // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK11-NEXT: ret i32 [[CALL]] // // @@ -10857,7 +10857,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10892,22 +10892,22 @@ int main() { // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -10924,7 +10924,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10969,23 +10969,23 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 -// CHECK11-NEXT: call void @_Z3fn4v(), !llvm.access.group !33 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: call void @_Z3fn4v() // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -11009,7 +11009,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11081,7 +11081,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11159,7 +11159,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK11-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -11181,7 +11181,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11227,41 +11227,41 @@ int main() { // CHECK11: omp_if.then: // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !39 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK11-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !39 +// CHECK11-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8 -// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !39 -// CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !39 -// CHECK11-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !39 +// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 +// CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK11-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK11-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11: omp_if.then5: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !39 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11: omp_if.else: -// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !39 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !39 -// CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !39 -// CHECK11-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]], !llvm.access.group !39 -// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !39 +// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK11-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]] +// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK11-NEXT: br label [[OMP_IF_END]] // CHECK11: omp_if.end: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !39 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_IF_END22:%.*]] @@ -11321,7 +11321,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11373,23 +11373,23 @@ int main() { // CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43 -// CHECK11-NEXT: call void @_Z3fn6v(), !llvm.access.group !43 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: call void @_Z3fn6v() // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] @@ -11449,7 +11449,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11501,23 +11501,23 @@ int main() { // CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47 -// CHECK11-NEXT: call void @_Z3fn6v(), !llvm.access.group !47 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: call void @_Z3fn6v() // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] @@ -11577,7 +11577,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK11-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK11-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -11645,7 +11645,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11680,22 +11680,22 @@ int main() { // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !51 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !51 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !51 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !51 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !51 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -11712,7 +11712,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11757,23 +11757,23 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !54 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !54 -// CHECK11-NEXT: call void @_Z3fn1v(), !llvm.access.group !54 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: call void @_Z3fn1v() // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -11797,7 +11797,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11869,7 +11869,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11947,7 +11947,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 -// CHECK11-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -11969,7 +11969,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12008,35 +12008,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59 +// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !59 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK11-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !59 +// CHECK11-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK11: omp_if.then: -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !59 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] // CHECK11: omp_if.else: -// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !59 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !59 -// CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !59 -// CHECK11-NEXT: call void @.omp_outlined..16(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !59 -// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !59 +// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK11-NEXT: call void @.omp_outlined..16(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK11-NEXT: br label [[OMP_IF_END]] // CHECK11: omp_if.end: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !59 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP60:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -12053,7 +12053,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12098,23 +12098,23 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !62 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !62 -// CHECK11-NEXT: call void @_Z3fn3v(), !llvm.access.group !62 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: call void @_Z3fn3v() // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 +// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP63:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -12169,7 +12169,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12204,22 +12204,22 @@ int main() { // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -12236,7 +12236,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12281,22 +12281,22 @@ int main() { // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -12320,7 +12320,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12356,26 +12356,26 @@ int main() { // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !24 -// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !24 -// CHECK12-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !24 -// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !24 +// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK12-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -12392,7 +12392,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12437,23 +12437,23 @@ int main() { // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 -// CHECK12-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !27 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: call void @_Z9gtid_testv() // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -12528,7 +12528,7 @@ int main() { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK12: omp_offload.cont7: // CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* @Arg, align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP18]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP18]]) // CHECK12-NEXT: ret i32 [[CALL]] // // @@ -12540,7 +12540,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12575,22 +12575,22 @@ int main() { // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -12607,7 +12607,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12652,23 +12652,23 @@ int main() { // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 -// CHECK12-NEXT: call void @_Z3fn4v(), !llvm.access.group !33 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: call void @_Z3fn4v() // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -12692,7 +12692,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12764,7 +12764,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12842,7 +12842,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 -// CHECK12-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -12864,7 +12864,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12910,41 +12910,41 @@ int main() { // CHECK12: omp_if.then: // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !39 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !39 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK12-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !39 +// CHECK12-NEXT: [[TMP12:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1 // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* // CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8 -// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !39 -// CHECK12-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !39 -// CHECK12-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !39 +// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 +// CHECK12-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK12-NEXT: [[TMP14:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1 // CHECK12-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12: omp_if.then5: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !39 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) // CHECK12-NEXT: br label [[OMP_IF_END:%.*]] // CHECK12: omp_if.else: -// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !39 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !39 -// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !39 -// CHECK12-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]], !llvm.access.group !39 -// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !39 +// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK12-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]] +// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK12-NEXT: br label [[OMP_IF_END]] // CHECK12: omp_if.end: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !39 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_IF_END22:%.*]] @@ -13004,7 +13004,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13056,23 +13056,23 @@ int main() { // CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43 -// CHECK12-NEXT: call void @_Z3fn6v(), !llvm.access.group !43 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: call void @_Z3fn6v() // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43 +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_IF_END:%.*]] @@ -13132,7 +13132,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13184,23 +13184,23 @@ int main() { // CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47 -// CHECK12-NEXT: call void @_Z3fn6v(), !llvm.access.group !47 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: call void @_Z3fn6v() // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 +// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_IF_END:%.*]] @@ -13260,7 +13260,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK12-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK12-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -13328,7 +13328,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13363,22 +13363,22 @@ int main() { // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !51 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !51 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !51 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !51 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !51 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -13395,7 +13395,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13440,23 +13440,23 @@ int main() { // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !54 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !54 -// CHECK12-NEXT: call void @_Z3fn1v(), !llvm.access.group !54 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: call void @_Z3fn1v() // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -13480,7 +13480,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..13 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13552,7 +13552,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13630,7 +13630,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l67 -// CHECK12-SAME: (i64 noundef [[ARG:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i64 [[ARG:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARG_ADDR:%.*]] = alloca i64, align 8 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -13652,7 +13652,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13691,35 +13691,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59 +// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !59 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !59 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK12-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !59 +// CHECK12-NEXT: [[TMP11:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK12: omp_if.then: -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !59 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK12-NEXT: br label [[OMP_IF_END:%.*]] // CHECK12: omp_if.else: -// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !59 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !59 -// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4, !llvm.access.group !59 -// CHECK12-NEXT: call void @.omp_outlined..16(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !59 -// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !59 +// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) +// CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 +// CHECK12-NEXT: call void @.omp_outlined..16(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] +// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]) // CHECK12-NEXT: br label [[OMP_IF_END]] // CHECK12: omp_if.end: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !59 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !59 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP60:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -13736,7 +13736,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..16 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13781,23 +13781,23 @@ int main() { // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !62 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !62 -// CHECK12-NEXT: call void @_Z3fn3v(), !llvm.access.group !62 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: call void @_Z3fn3v() // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !62 +// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP63:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -13839,22 +13839,22 @@ int main() { // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK13-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 100, i32* [[I]], align 4 @@ -13864,23 +13864,23 @@ int main() { // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK13: omp.inner.for.cond7: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK13: omp.inner.for.body9: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK13-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK13-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !10 -// CHECK13-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !10 +// CHECK13-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK13-NEXT: call void @_Z9gtid_testv() // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK13: omp.body.continue12: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK13: omp.inner.for.inc13: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK13-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK13: omp.inner.for.end15: // CHECK13-NEXT: store i32 100, i32* [[I6]], align 4 @@ -13914,23 +13914,23 @@ int main() { // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 -// CHECK13-NEXT: call void @_Z3fn4v(), !llvm.access.group !13 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK13-NEXT: call void @_Z3fn4v() // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK13-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 100, i32* [[I]], align 4 @@ -13940,23 +13940,23 @@ int main() { // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK13: omp.inner.for.cond7: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !16 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK13: omp.inner.for.body9: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK13-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK13-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !16 -// CHECK13-NEXT: call void @_Z3fn5v(), !llvm.access.group !16 +// CHECK13-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK13-NEXT: call void @_Z3fn5v() // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK13: omp.body.continue12: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK13: omp.inner.for.inc13: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 +// CHECK13-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK13: omp.inner.for.end15: // CHECK13-NEXT: store i32 100, i32* [[I6]], align 4 @@ -13970,33 +13970,33 @@ int main() { // CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK13: omp.inner.for.cond21: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !19 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK13-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK13-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK13: omp.inner.for.body23: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK13-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK13-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !19 -// CHECK13-NEXT: call void @_Z3fn6v(), !llvm.access.group !19 +// CHECK13-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK13-NEXT: call void @_Z3fn6v() // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK13: omp.body.continue26: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK13: omp.inner.for.inc27: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK13-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 +// CHECK13-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK13: omp.inner.for.end29: // CHECK13-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* @Arg, align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP16]]) +// CHECK13-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP16]]) // CHECK13-NEXT: ret i32 [[CALL]] // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK13-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK13-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -14022,23 +14022,23 @@ int main() { // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 -// CHECK13-NEXT: call void @_Z3fn1v(), !llvm.access.group !22 +// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK13-NEXT: call void @_Z3fn1v() // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK13-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK13-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 100, i32* [[I]], align 4 @@ -14048,23 +14048,23 @@ int main() { // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK13: omp.inner.for.cond7: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !25 +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK13: omp.inner.for.body9: -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK13-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK13-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !25 -// CHECK13-NEXT: call void @_Z3fn2v(), !llvm.access.group !25 +// CHECK13-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK13-NEXT: call void @_Z3fn2v() // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK13: omp.body.continue12: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK13: omp.inner.for.inc13: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 +// CHECK13-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK13: omp.inner.for.end15: // CHECK13-NEXT: store i32 100, i32* [[I6]], align 4 @@ -14078,23 +14078,23 @@ int main() { // CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK13: omp.inner.for.cond21: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !28 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK13-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK13-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK13: omp.inner.for.body23: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK13-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK13-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !28 -// CHECK13-NEXT: call void @_Z3fn3v(), !llvm.access.group !28 +// CHECK13-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK13-NEXT: call void @_Z3fn3v() // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK13: omp.body.continue26: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK13: omp.inner.for.inc27: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK13-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 +// CHECK13-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP29:![0-9]+]] // CHECK13: omp.inner.for.end29: // CHECK13-NEXT: store i32 100, i32* [[I20]], align 4 @@ -14120,22 +14120,22 @@ int main() { // CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK14-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: store i32 100, i32* [[I]], align 4 @@ -14145,23 +14145,23 @@ int main() { // CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK14: omp.inner.for.cond7: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK14-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK14: omp.inner.for.body9: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK14-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK14-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !10 -// CHECK14-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !10 +// CHECK14-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK14-NEXT: call void @_Z9gtid_testv() // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK14: omp.body.continue12: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK14: omp.inner.for.inc13: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK14-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK14: omp.inner.for.end15: // CHECK14-NEXT: store i32 100, i32* [[I6]], align 4 @@ -14195,23 +14195,23 @@ int main() { // CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 -// CHECK14-NEXT: call void @_Z3fn4v(), !llvm.access.group !13 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: call void @_Z3fn4v() // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK14-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: store i32 100, i32* [[I]], align 4 @@ -14221,23 +14221,23 @@ int main() { // CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK14: omp.inner.for.cond7: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !16 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK14-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK14: omp.inner.for.body9: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK14-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK14-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !16 -// CHECK14-NEXT: call void @_Z3fn5v(), !llvm.access.group !16 +// CHECK14-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK14-NEXT: call void @_Z3fn5v() // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK14: omp.body.continue12: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK14: omp.inner.for.inc13: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !16 +// CHECK14-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK14: omp.inner.for.end15: // CHECK14-NEXT: store i32 100, i32* [[I6]], align 4 @@ -14251,33 +14251,33 @@ int main() { // CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK14: omp.inner.for.cond21: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !19 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK14-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK14-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK14: omp.inner.for.body23: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK14-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK14-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !19 -// CHECK14-NEXT: call void @_Z3fn6v(), !llvm.access.group !19 +// CHECK14-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK14-NEXT: call void @_Z3fn6v() // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK14: omp.body.continue26: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK14: omp.inner.for.inc27: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK14-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !19 +// CHECK14-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK14: omp.inner.for.end29: // CHECK14-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK14-NEXT: [[TMP16:%.*]] = load i32, i32* @Arg, align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP16]]) +// CHECK14-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP16]]) // CHECK14-NEXT: ret i32 [[CALL]] // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK14-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK14-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -14303,23 +14303,23 @@ int main() { // CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: -// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK14: omp.inner.for.body: -// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 -// CHECK14-NEXT: call void @_Z3fn1v(), !llvm.access.group !22 +// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK14-NEXT: call void @_Z3fn1v() // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK14: omp.inner.for.inc: -// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK14-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK14-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK14: omp.inner.for.end: // CHECK14-NEXT: store i32 100, i32* [[I]], align 4 @@ -14329,23 +14329,23 @@ int main() { // CHECK14-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK14: omp.inner.for.cond7: -// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 -// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !25 +// CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK14-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK14: omp.inner.for.body9: -// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 +// CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK14-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK14-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !25 -// CHECK14-NEXT: call void @_Z3fn2v(), !llvm.access.group !25 +// CHECK14-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK14-NEXT: call void @_Z3fn2v() // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK14: omp.body.continue12: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK14: omp.inner.for.inc13: -// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 +// CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK14-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !25 +// CHECK14-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK14: omp.inner.for.end15: // CHECK14-NEXT: store i32 100, i32* [[I6]], align 4 @@ -14359,23 +14359,23 @@ int main() { // CHECK14-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK14: omp.inner.for.cond21: -// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 -// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !28 +// CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK14-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK14-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK14-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK14: omp.inner.for.body23: -// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 +// CHECK14-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK14-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK14-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !28 -// CHECK14-NEXT: call void @_Z3fn3v(), !llvm.access.group !28 +// CHECK14-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK14-NEXT: call void @_Z3fn3v() // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK14: omp.body.continue26: // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK14: omp.inner.for.inc27: -// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 +// CHECK14-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK14-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !28 +// CHECK14-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP29:![0-9]+]] // CHECK14: omp.inner.for.end29: // CHECK14-NEXT: store i32 100, i32* [[I20]], align 4 @@ -14401,22 +14401,22 @@ int main() { // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 100, i32* [[I]], align 4 @@ -14426,23 +14426,23 @@ int main() { // CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK15: omp.inner.for.cond7: -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !10 +// CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK15-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK15-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK15: omp.inner.for.body9: -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK15-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK15-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK15-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !10 -// CHECK15-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !10 +// CHECK15-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK15-NEXT: call void @_Z9gtid_testv() // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK15: omp.body.continue12: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK15: omp.inner.for.inc13: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK15-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK15-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK15-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK15: omp.inner.for.end15: // CHECK15-NEXT: store i32 100, i32* [[I6]], align 4 @@ -14476,23 +14476,23 @@ int main() { // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 -// CHECK15-NEXT: call void @_Z3fn4v(), !llvm.access.group !13 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK15-NEXT: call void @_Z3fn4v() // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 100, i32* [[I]], align 4 @@ -14536,23 +14536,23 @@ int main() { // CHECK15: omp_if.then: // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND22:%.*]] // CHECK15: omp.inner.for.cond22: -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !18 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK15-NEXT: [[CMP23:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK15-NEXT: br i1 [[CMP23]], label [[OMP_INNER_FOR_BODY24:%.*]], label [[OMP_INNER_FOR_END30:%.*]] // CHECK15: omp.inner.for.body24: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK15-NEXT: [[MUL25:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK15-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]] -// CHECK15-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4, !llvm.access.group !18 -// CHECK15-NEXT: call void @_Z3fn6v(), !llvm.access.group !18 +// CHECK15-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4 +// CHECK15-NEXT: call void @_Z3fn6v() // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]] // CHECK15: omp.body.continue27: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]] // CHECK15: omp.inner.for.inc28: -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 +// CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK15-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK15-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 +// CHECK15-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND22]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK15: omp.inner.for.end30: // CHECK15-NEXT: br label [[OMP_IF_END:%.*]] @@ -14582,12 +14582,12 @@ int main() { // CHECK15: omp_if.end: // CHECK15-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* @Arg, align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP21]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP21]]) // CHECK15-NEXT: ret i32 [[CALL]] // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK15-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK15-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -14613,23 +14613,23 @@ int main() { // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 -// CHECK15-NEXT: call void @_Z3fn1v(), !llvm.access.group !22 +// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK15-NEXT: call void @_Z3fn1v() // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 100, i32* [[I]], align 4 @@ -14669,23 +14669,23 @@ int main() { // CHECK15-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV19]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK15: omp.inner.for.cond21: -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !26 +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK15-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK15-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK15: omp.inner.for.body23: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK15-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK15-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK15-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !26 -// CHECK15-NEXT: call void @_Z3fn3v(), !llvm.access.group !26 +// CHECK15-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK15-NEXT: call void @_Z3fn3v() // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK15: omp.body.continue26: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK15: omp.inner.for.inc27: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK15-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK15-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 +// CHECK15-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK15: omp.inner.for.end29: // CHECK15-NEXT: store i32 100, i32* [[I20]], align 4 @@ -14711,22 +14711,22 @@ int main() { // CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK16: omp.body.continue: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: store i32 100, i32* [[I]], align 4 @@ -14736,23 +14736,23 @@ int main() { // CHECK16-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV5]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] // CHECK16: omp.inner.for.cond7: -// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 -// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4, !llvm.access.group !10 +// CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 +// CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB4]], align 4 // CHECK16-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK16-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] // CHECK16: omp.inner.for.body9: -// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK16-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK16-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] -// CHECK16-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4, !llvm.access.group !10 -// CHECK16-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !10 +// CHECK16-NEXT: store i32 [[ADD11]], i32* [[I6]], align 4 +// CHECK16-NEXT: call void @_Z9gtid_testv() // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK16: omp.body.continue12: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] // CHECK16: omp.inner.for.inc13: -// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV5]], align 4 // CHECK16-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 -// CHECK16-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4, !llvm.access.group !10 +// CHECK16-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV5]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK16: omp.inner.for.end15: // CHECK16-NEXT: store i32 100, i32* [[I6]], align 4 @@ -14786,23 +14786,23 @@ int main() { // CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 -// CHECK16-NEXT: call void @_Z3fn4v(), !llvm.access.group !13 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: call void @_Z3fn4v() // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK16: omp.body.continue: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: store i32 100, i32* [[I]], align 4 @@ -14846,23 +14846,23 @@ int main() { // CHECK16: omp_if.then: // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND22:%.*]] // CHECK16: omp.inner.for.cond22: -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !18 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK16-NEXT: [[CMP23:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK16-NEXT: br i1 [[CMP23]], label [[OMP_INNER_FOR_BODY24:%.*]], label [[OMP_INNER_FOR_END30:%.*]] // CHECK16: omp.inner.for.body24: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK16-NEXT: [[MUL25:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK16-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]] -// CHECK16-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4, !llvm.access.group !18 -// CHECK16-NEXT: call void @_Z3fn6v(), !llvm.access.group !18 +// CHECK16-NEXT: store i32 [[ADD26]], i32* [[I20]], align 4 +// CHECK16-NEXT: call void @_Z3fn6v() // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]] // CHECK16: omp.body.continue27: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]] // CHECK16: omp.inner.for.inc28: -// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 +// CHECK16-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK16-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK16-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !18 +// CHECK16-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_IV19]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND22]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK16: omp.inner.for.end30: // CHECK16-NEXT: br label [[OMP_IF_END:%.*]] @@ -14892,12 +14892,12 @@ int main() { // CHECK16: omp_if.end: // CHECK16-NEXT: store i32 100, i32* [[I20]], align 4 // CHECK16-NEXT: [[TMP21:%.*]] = load i32, i32* @Arg, align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiEiT_(i32 noundef [[TMP21]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP21]]) // CHECK16-NEXT: ret i32 [[CALL]] // // // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK16-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { +// CHECK16-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -14923,23 +14923,23 @@ int main() { // CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: -// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 -// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 +// CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] // CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK16: omp.inner.for.body: -// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 -// CHECK16-NEXT: call void @_Z3fn1v(), !llvm.access.group !22 +// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK16-NEXT: call void @_Z3fn1v() // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK16: omp.body.continue: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK16: omp.inner.for.inc: -// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 +// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK16: omp.inner.for.end: // CHECK16-NEXT: store i32 100, i32* [[I]], align 4 @@ -14979,23 +14979,23 @@ int main() { // CHECK16-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV19]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND21:%.*]] // CHECK16: omp.inner.for.cond21: -// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 -// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4, !llvm.access.group !26 +// CHECK16-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 +// CHECK16-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB18]], align 4 // CHECK16-NEXT: [[CMP22:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK16-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY23:%.*]], label [[OMP_INNER_FOR_END29:%.*]] // CHECK16: omp.inner.for.body23: -// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 +// CHECK16-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK16-NEXT: [[MUL24:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK16-NEXT: [[ADD25:%.*]] = add nsw i32 0, [[MUL24]] -// CHECK16-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4, !llvm.access.group !26 -// CHECK16-NEXT: call void @_Z3fn3v(), !llvm.access.group !26 +// CHECK16-NEXT: store i32 [[ADD25]], i32* [[I20]], align 4 +// CHECK16-NEXT: call void @_Z3fn3v() // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE26:%.*]] // CHECK16: omp.body.continue26: // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC27:%.*]] // CHECK16: omp.inner.for.inc27: -// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 +// CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV19]], align 4 // CHECK16-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK16-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4, !llvm.access.group !26 +// CHECK16-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV19]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND21]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK16: omp.inner.for.end29: // CHECK16-NEXT: store i32 100, i32* [[I20]], align 4 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp index 5c66b7a3c30fff124c272664bf239329df180650..7d94bf71cab2da210e6206c84514b75cb915b55a 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp @@ -198,12 +198,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -225,7 +225,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -281,24 +281,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP13]], i64 [[TMP15]], double* [[G2]], double* [[TMP16]], i32* [[SVAR5]], float* [[SFVAR6]]), !llvm.access.group !4 +// CHECK1-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 8 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP13]], i64 [[TMP15]], double* [[G2]], double* [[TMP16]], i32* [[SVAR5]], float* [[SFVAR6]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -329,7 +329,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -396,38 +396,38 @@ int main() { // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: store double 1.000000e+00, double* [[G3]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8 +// CHECK1-NEXT: store i32 3, i32* [[SVAR6]], align 4 +// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK1-NEXT: store double* [[G3]], double** [[TMP16]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: store double* [[G3]], double** [[TMP16]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK1-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8, !llvm.access.group !8 +// CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8, !llvm.access.group !8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -478,12 +478,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK2-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -505,7 +505,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -561,24 +561,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK2-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP13]], i64 [[TMP15]], double* [[G2]], double* [[TMP16]], i32* [[SVAR5]], float* [[SFVAR6]]), !llvm.access.group !4 +// CHECK2-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 8 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP13]], i64 [[TMP15]], double* [[G2]], double* [[TMP16]], i32* [[SVAR5]], float* [[SFVAR6]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -609,7 +609,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -676,38 +676,38 @@ int main() { // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: store double 1.000000e+00, double* [[G3]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store i32 3, i32* [[SVAR6]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: store double 1.000000e+00, double* [[G3]], align 8 +// CHECK2-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 8 +// CHECK2-NEXT: store i32 3, i32* [[SVAR6]], align 4 +// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR7]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK2-NEXT: store double* [[G3]], double** [[TMP16]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: store double* [[G3]], double** [[TMP16]], align 8 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP5]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP5]], align 8 +// CHECK2-NEXT: store double* [[TMP18]], double** [[TMP17]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8, !llvm.access.group !8 +// CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP19]], align 8 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8, !llvm.access.group !8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP20]], align 8 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -758,12 +758,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -793,7 +793,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -849,22 +849,22 @@ int main() { // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP12]], i32 [[TMP13]], double* [[G2]], double* [[TMP14]], i32* [[SVAR5]], float* [[SFVAR6]]), !llvm.access.group !5 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP12]], i32 [[TMP13]], double* [[G2]], double* [[TMP14]], i32* [[SVAR5]], float* [[SFVAR6]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -895,7 +895,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -960,38 +960,38 @@ int main() { // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !9 -// CHECK3-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: store double 1.000000e+00, double* [[G2]], align 8 +// CHECK3-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4 +// CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4 +// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK3-NEXT: store double* [[G2]], double** [[TMP16]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store double* [[G2]], double** [[TMP16]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK3-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !9 +// CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1042,12 +1042,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -1077,7 +1077,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1133,22 +1133,22 @@ int main() { // CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP12]], i32 [[TMP13]], double* [[G2]], double* [[TMP14]], i32* [[SVAR5]], float* [[SFVAR6]]), !llvm.access.group !5 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, double*, double*, i32*, float*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP12]], i32 [[TMP13]], double* [[G2]], double* [[TMP14]], i32* [[SVAR5]], float* [[SFVAR6]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1179,7 +1179,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1244,38 +1244,38 @@ int main() { // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !9 -// CHECK4-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: store double 1.000000e+00, double* [[G2]], align 8 +// CHECK4-NEXT: [[TMP15:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP15]], align 4 +// CHECK4-NEXT: store i32 3, i32* [[SVAR5]], align 4 +// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK4-NEXT: store double* [[G2]], double** [[TMP16]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store double* [[G2]], double** [[TMP16]], align 4 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP18:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK4-NEXT: store double* [[TMP18]], double** [[TMP17]], align 4 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP19]], align 4 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !9 +// CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP20]], align 4 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1326,7 +1326,7 @@ int main() { // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // @@ -1344,7 +1344,7 @@ int main() { // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // @@ -1362,7 +1362,7 @@ int main() { // CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK7-NEXT: ret i32 0 // // @@ -1380,7 +1380,7 @@ int main() { // CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK8-NEXT: ret i32 0 // // @@ -1405,14 +1405,14 @@ int main() { // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1477,7 +1477,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1485,27 +1485,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP39]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1513,12 +1513,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1543,7 +1543,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1588,13 +1588,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -1614,26 +1614,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP17]], i32* [[SVAR7]]), !llvm.access.group !5 +// CHECK9-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP17]], i32* [[SVAR7]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1680,14 +1680,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP36]], i32* [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done12: @@ -1695,7 +1695,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1750,13 +1750,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -1776,37 +1776,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8, !llvm.access.group !9 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK9-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1853,14 +1853,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP39]], i32* [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP40]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done16: @@ -1868,12 +1868,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1892,14 +1892,14 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1959,17 +1959,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP32]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1980,7 +1980,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1994,7 +1994,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2003,17 +2003,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2021,12 +2021,12 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2048,7 +2048,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2089,13 +2089,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -2115,26 +2115,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !14 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP13]], i64 [[TMP15]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP16]]), !llvm.access.group !14 +// CHECK9-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP13]], i64 [[TMP15]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP16]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -2179,14 +2179,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done11: @@ -2194,7 +2194,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2245,13 +2245,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -2271,37 +2271,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !17 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 // CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* // CHECK9-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group !17 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -2346,14 +2346,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP36]], i8* align 4 [[TMP37]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -2361,17 +2361,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2382,7 +2382,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2396,7 +2396,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2432,14 +2432,14 @@ int main() { // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -2504,7 +2504,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -2512,27 +2512,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP39]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2540,12 +2540,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2570,7 +2570,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2615,13 +2615,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK10-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -2641,26 +2641,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK10-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP17]], i32* [[SVAR7]]), !llvm.access.group !5 +// CHECK10-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP14]], i64 [[TMP16]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP17]], i32* [[SVAR7]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2707,14 +2707,14 @@ int main() { // CHECK10-NEXT: store i32 [[TMP36]], i32* [[TMP4]], align 4 // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK10-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP37]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done12: @@ -2722,7 +2722,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2777,13 +2777,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -2803,37 +2803,37 @@ int main() { // CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8, !llvm.access.group !9 -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP7]], align 8 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 // CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK10-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* // CHECK10-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !9 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2880,14 +2880,14 @@ int main() { // CHECK10-NEXT: store i32 [[TMP39]], i32* [[TMP4]], align 4 // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP40]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done16: @@ -2895,12 +2895,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -2919,14 +2919,14 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -2986,17 +2986,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP32]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3007,7 +3007,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3021,7 +3021,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3030,17 +3030,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3048,12 +3048,12 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -3075,7 +3075,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3116,13 +3116,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK10-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -3142,26 +3142,26 @@ int main() { // CHECK10-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK10-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !14 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP13]], i64 [[TMP15]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP16]]), !llvm.access.group !14 +// CHECK10-NEXT: [[TMP16:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP13]], i64 [[TMP15]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP16]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -3206,14 +3206,14 @@ int main() { // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP33]], i8* align 4 [[TMP34]], i64 4, i1 false) // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done11: @@ -3221,7 +3221,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3272,13 +3272,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK10-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -3298,37 +3298,37 @@ int main() { // CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR3]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !17 -// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 // CHECK10-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK10-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* // CHECK10-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group !17 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -3373,14 +3373,14 @@ int main() { // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP36]], i8* align 4 [[TMP37]], i64 4, i1 false) // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done15: @@ -3388,17 +3388,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3409,7 +3409,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3423,7 +3423,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3459,14 +3459,14 @@ int main() { // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -3529,7 +3529,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -3537,27 +3537,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP39]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3565,12 +3565,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3593,7 +3593,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3638,13 +3638,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -3664,24 +3664,24 @@ int main() { // CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP15:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32* [[SVAR7]]), !llvm.access.group !6 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32* [[SVAR7]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -3728,14 +3728,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP34]], i32* [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done12: @@ -3743,7 +3743,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3796,13 +3796,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -3822,35 +3822,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP17]] -// CHECK11-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP19]] // CHECK11-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK11-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !10 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -3897,14 +3897,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP39]], i32* [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP40]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -3912,12 +3912,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -3936,14 +3936,14 @@ int main() { // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4002,17 +4002,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP32]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4023,7 +4023,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4037,7 +4037,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4046,17 +4046,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4064,12 +4064,12 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -4090,7 +4090,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4131,13 +4131,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -4157,24 +4157,24 @@ int main() { // CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP12]], i32 [[TMP13]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP14]]), !llvm.access.group !15 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP12]], i32 [[TMP13]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP14]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -4219,14 +4219,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done11: @@ -4234,7 +4234,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4283,13 +4283,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -4309,35 +4309,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP16]] -// CHECK11-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP18]] // CHECK11-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* // CHECK11-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group !18 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -4382,14 +4382,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP36]], i8* align 4 [[TMP37]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -4397,17 +4397,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4418,7 +4418,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4432,7 +4432,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4468,14 +4468,14 @@ int main() { // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -4538,7 +4538,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -4546,27 +4546,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP39]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4574,12 +4574,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -4602,7 +4602,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4647,13 +4647,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -4673,24 +4673,24 @@ int main() { // CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP15:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32* [[SVAR7]]), !llvm.access.group !6 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP13]], i32 [[TMP14]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S]* [[S_ARR4]], %struct.S* [[TMP15]], i32* [[SVAR7]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -4737,14 +4737,14 @@ int main() { // CHECK12-NEXT: store i32 [[TMP34]], i32* [[TMP4]], align 4 // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN11]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP35]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done12: @@ -4752,7 +4752,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4805,13 +4805,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -4831,35 +4831,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP17]] -// CHECK12-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP19]] // CHECK12-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK12-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[TMP18]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !10 +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -4906,14 +4906,14 @@ int main() { // CHECK12-NEXT: store i32 [[TMP39]], i32* [[TMP4]], align 4 // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP40]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done14: @@ -4921,12 +4921,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // @@ -4945,14 +4945,14 @@ int main() { // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -5011,17 +5011,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP32]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5032,7 +5032,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5046,7 +5046,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5055,17 +5055,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5073,12 +5073,12 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -5099,7 +5099,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5140,13 +5140,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -5166,24 +5166,24 @@ int main() { // CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP12]], i32 [[TMP13]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP14]]), !llvm.access.group !15 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP12]], i32 [[TMP13]], [2 x i32]* [[VEC3]], i32* [[T_VAR2]], [2 x %struct.S.0]* [[S_ARR4]], %struct.S.0* [[TMP14]]) // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -5228,14 +5228,14 @@ int main() { // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP31]], i8* align 4 [[TMP32]], i32 4, i1 false) // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP33]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done11: @@ -5243,7 +5243,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5292,13 +5292,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 @@ -5318,35 +5318,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP16]] -// CHECK12-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP18]] // CHECK12-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* // CHECK12-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[TMP17]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group !18 +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i32 4, i1 false) // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -5391,14 +5391,14 @@ int main() { // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP36]], i8* align 4 [[TMP37]], i32 4, i1 false) // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done13: @@ -5406,17 +5406,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5427,7 +5427,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5441,7 +5441,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5483,14 +5483,14 @@ int main() { // CHECK13-NEXT: [[I15:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -5507,13 +5507,13 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: // CHECK13-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK13-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -5577,18 +5577,18 @@ int main() { // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) // CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK13-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4:[0-9]+]] // CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done14: -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN16]], i64 2 @@ -5596,27 +5596,27 @@ int main() { // CHECK13: arraydestroy.body17: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK13: arraydestroy.done21: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP30]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5624,17 +5624,17 @@ int main() { // CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // @@ -5659,14 +5659,14 @@ int main() { // CHECK13-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -5683,13 +5683,13 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: // CHECK13-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK13-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -5751,14 +5751,14 @@ int main() { // CHECK13-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK13-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done14: @@ -5769,17 +5769,17 @@ int main() { // CHECK13: arraydestroy.body16: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST17]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK13: arraydestroy.done20: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP29]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5790,7 +5790,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5799,7 +5799,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5813,17 +5813,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5831,22 +5831,22 @@ int main() { // CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5857,7 +5857,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5871,7 +5871,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -5906,14 +5906,14 @@ int main() { // CHECK14-NEXT: [[I15:%.*]] = alloca i32, align 4 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -5930,13 +5930,13 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: // CHECK14-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK14-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -6000,18 +6000,18 @@ int main() { // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) // CHECK14-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK14-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4:[0-9]+]] // CHECK14-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK14-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done14: -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN16]], i64 2 @@ -6019,27 +6019,27 @@ int main() { // CHECK14: arraydestroy.body17: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK14: arraydestroy.done21: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP30]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6047,17 +6047,17 @@ int main() { // CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // @@ -6082,14 +6082,14 @@ int main() { // CHECK14-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK14-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK14-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -6106,13 +6106,13 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: // CHECK14-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK14-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -6174,14 +6174,14 @@ int main() { // CHECK14-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK14-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i64 4, i1 false) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK14-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done14: @@ -6192,17 +6192,17 @@ int main() { // CHECK14: arraydestroy.body16: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST17]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK14: arraydestroy.done20: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP29]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6213,7 +6213,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6222,7 +6222,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6236,17 +6236,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6254,22 +6254,22 @@ int main() { // CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -6280,7 +6280,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6294,7 +6294,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -6329,14 +6329,14 @@ int main() { // CHECK15-NEXT: [[I14:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -6353,13 +6353,13 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: // CHECK15-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK15-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -6421,18 +6421,18 @@ int main() { // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) // CHECK15-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK15-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4:[0-9]+]] // CHECK15-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK15-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done13: -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i32 2 @@ -6440,27 +6440,27 @@ int main() { // CHECK15: arraydestroy.body16: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST17]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK15: arraydestroy.done20: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP30]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6468,17 +6468,17 @@ int main() { // CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // @@ -6503,14 +6503,14 @@ int main() { // CHECK15-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK15-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -6527,13 +6527,13 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: // CHECK15-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK15-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -6593,14 +6593,14 @@ int main() { // CHECK15-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK15-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK15-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done13: @@ -6611,17 +6611,17 @@ int main() { // CHECK15: arraydestroy.body15: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST16]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK15: arraydestroy.done19: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP29]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -6632,7 +6632,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -6641,7 +6641,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6655,17 +6655,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6673,22 +6673,22 @@ int main() { // CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -6699,7 +6699,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6713,7 +6713,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -6748,14 +6748,14 @@ int main() { // CHECK16-NEXT: [[I14:%.*]] = alloca i32, align 4 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -6772,13 +6772,13 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: // CHECK16-NEXT: [[TMP6:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK16-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -6840,18 +6840,18 @@ int main() { // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) // CHECK16-NEXT: [[TMP27:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK16-NEXT: store i32 [[TMP27]], i32* @_ZZ4mainE4svar, align 4 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4:[0-9]+]] // CHECK16-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK16-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done13: -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i32 2 @@ -6859,27 +6859,27 @@ int main() { // CHECK16: arraydestroy.body16: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S* [ [[TMP29]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST17]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK16: arraydestroy.done20: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP30]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -6887,17 +6887,17 @@ int main() { // CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // @@ -6922,14 +6922,14 @@ int main() { // CHECK16-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK16-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK16-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -6946,13 +6946,13 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: // CHECK16-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK16-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -7012,14 +7012,14 @@ int main() { // CHECK16-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP6]] to i8* // CHECK16-NEXT: [[TMP26:%.*]] = bitcast %struct.S.0* [[TMP24]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP25]], i8* align 4 [[TMP26]], i32 4, i1 false) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK16-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done13: @@ -7030,17 +7030,17 @@ int main() { // CHECK16: arraydestroy.body15: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi %struct.S.0* [ [[TMP28]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST16]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK16: arraydestroy.done19: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP29]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -7051,7 +7051,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -7060,7 +7060,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -7074,17 +7074,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7092,22 +7092,22 @@ int main() { // CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -7118,7 +7118,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7132,7 +7132,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp index d05cd4bba44c13f8eecbd2afd2fcc17ebe4e99d0..36fb55d14161ea0ac24dd510951b2b7a9756096c 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp @@ -91,8 +91,8 @@ int main() { // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK1-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK1-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK1-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -110,7 +110,7 @@ int main() { // CHECK1-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK1-NEXT: br label [[EH_RESUME:%.*]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -141,16 +141,16 @@ int main() { // CHECK1: omp_offload.cont3: // CHECK1-NEXT: [[TMP19:%.*]] = load i8, i8* [[A]], align 1 // CHECK1-NEXT: [[CONV4:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK1-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() +// CHECK1-NEXT: [[CALL6:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() // CHECK1-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK1: invoke.cont5: // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK1-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() +// CHECK1-NEXT: [[CALL8:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() // CHECK1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK1: invoke.cont7: // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK1-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP20]] // CHECK1: eh.resume: @@ -162,7 +162,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -170,12 +170,12 @@ int main() { // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -194,7 +194,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -229,24 +229,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !9 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !9 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -262,7 +262,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -307,26 +307,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !13 +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -343,7 +343,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK1-NEXT: catch i8* null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9:[0-9]+]], !llvm.access.group !13 +// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9:[0-9]+]] // CHECK1-NEXT: unreachable // // @@ -355,7 +355,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 -// CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -373,7 +373,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -411,26 +411,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -446,7 +446,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -491,26 +491,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !21 +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -527,7 +527,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK1-NEXT: catch i8* null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !21 +// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK1-NEXT: unreachable // // @@ -570,11 +570,11 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK1-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK1-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32 @@ -596,17 +596,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK1-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -620,7 +620,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -636,7 +636,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -671,24 +671,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !24 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -704,7 +704,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -749,26 +749,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !27 +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -785,7 +785,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK1-NEXT: catch i8* null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !27 +// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK1-NEXT: unreachable // // @@ -797,7 +797,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -832,24 +832,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !30 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -865,7 +865,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -910,26 +910,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !33 +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -946,7 +946,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK1-NEXT: catch i8* null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !33 +// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK1-NEXT: unreachable // // @@ -958,7 +958,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -993,24 +993,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !36 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1026,7 +1026,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1071,26 +1071,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !39 +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1107,7 +1107,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK1-NEXT: catch i8* null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !39 +// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK1-NEXT: unreachable // // @@ -1119,11 +1119,11 @@ int main() { // CHECK1-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK1-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK1: invoke.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK1-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK1-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* @@ -1146,7 +1146,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1184,26 +1184,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42 +// CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1219,7 +1219,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1264,26 +1264,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !45 +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1300,7 +1300,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK1-NEXT: catch i8* null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !45 +// CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK1-NEXT: unreachable // // @@ -1327,8 +1327,8 @@ int main() { // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK2-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK2-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK2-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -1346,7 +1346,7 @@ int main() { // CHECK2-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK2-NEXT: br label [[EH_RESUME:%.*]] // CHECK2: omp_offload.cont: // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -1377,16 +1377,16 @@ int main() { // CHECK2: omp_offload.cont3: // CHECK2-NEXT: [[TMP19:%.*]] = load i8, i8* [[A]], align 1 // CHECK2-NEXT: [[CONV4:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK2-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() +// CHECK2-NEXT: [[CALL6:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() // CHECK2-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK2: invoke.cont5: // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK2-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() +// CHECK2-NEXT: [[CALL8:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() // CHECK2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK2: invoke.cont7: // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK2-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP20]] // CHECK2: eh.resume: @@ -1398,7 +1398,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -1406,12 +1406,12 @@ int main() { // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1430,7 +1430,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1465,24 +1465,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !9 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !9 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1498,7 +1498,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1543,26 +1543,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: invoke void @_Z3foov() -// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !13 +// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1579,7 +1579,7 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK2-NEXT: catch i8* null // CHECK2-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9:[0-9]+]], !llvm.access.group !13 +// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9:[0-9]+]] // CHECK2-NEXT: unreachable // // @@ -1591,7 +1591,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 -// CHECK2-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -1609,7 +1609,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1647,26 +1647,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1682,7 +1682,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1727,26 +1727,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: invoke void @_Z3foov() -// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !21 +// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1763,7 +1763,7 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK2-NEXT: catch i8* null // CHECK2-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !21 +// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK2-NEXT: unreachable // // @@ -1806,11 +1806,11 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK2-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK2-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK2-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32 @@ -1832,17 +1832,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK2-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -1856,7 +1856,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1872,7 +1872,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1907,24 +1907,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !24 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1940,7 +1940,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1985,26 +1985,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: invoke void @_Z3foov() -// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !27 +// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2021,7 +2021,7 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK2-NEXT: catch i8* null // CHECK2-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !27 +// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK2-NEXT: unreachable // // @@ -2033,7 +2033,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2068,24 +2068,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !30 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2101,7 +2101,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2146,26 +2146,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: invoke void @_Z3foov() -// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !33 +// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2182,7 +2182,7 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK2-NEXT: catch i8* null // CHECK2-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !33 +// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK2-NEXT: unreachable // // @@ -2194,7 +2194,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2229,24 +2229,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !36 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2262,7 +2262,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2307,26 +2307,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: invoke void @_Z3foov() -// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !39 +// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2343,7 +2343,7 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK2-NEXT: catch i8* null // CHECK2-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !39 +// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK2-NEXT: unreachable // // @@ -2355,11 +2355,11 @@ int main() { // CHECK2-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK2-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK2-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK2: invoke.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK2-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK2-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* @@ -2382,7 +2382,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2420,26 +2420,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42 +// CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2455,7 +2455,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2500,26 +2500,26 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: invoke void @_Z3foov() -// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !45 +// CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -2536,7 +2536,7 @@ int main() { // CHECK2-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK2-NEXT: catch i8* null // CHECK2-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !45 +// CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK2-NEXT: unreachable // // @@ -2567,8 +2567,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I7:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK3-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK3-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK3-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK3: invoke.cont: // CHECK3-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -2605,7 +2605,7 @@ int main() { // CHECK3-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8 // CHECK3-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6:[0-9]+]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6:[0-9]+]] // CHECK3-NEXT: br label [[EH_RESUME:%.*]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: store i32 100, i32* [[I]], align 4 @@ -2641,16 +2641,16 @@ int main() { // CHECK3-NEXT: store i32 100, i32* [[I7]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[A]], align 1 // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32 -// CHECK3-NEXT: [[CALL19:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() +// CHECK3-NEXT: [[CALL19:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() // CHECK3-NEXT: to label [[INVOKE_CONT18:%.*]] unwind label [[LPAD]] // CHECK3: invoke.cont18: // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV]], [[CALL19]] -// CHECK3-NEXT: [[CALL22:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() +// CHECK3-NEXT: [[CALL22:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() // CHECK3-NEXT: to label [[INVOKE_CONT21:%.*]] unwind label [[LPAD]] // CHECK3: invoke.cont21: // CHECK3-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] // CHECK3-NEXT: store i32 [[ADD23]], i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP15]] // CHECK3: eh.resume: @@ -2668,7 +2668,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -2676,12 +2676,12 @@ int main() { // CHECK3-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2820,11 +2820,11 @@ int main() { // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK3-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK3-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK3-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]] // CHECK3: invoke.cont2: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK3-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK3-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB5]], align 4 @@ -2864,17 +2864,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK3-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -2888,7 +2888,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2916,8 +2916,8 @@ int main() { // CHECK4-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[I7:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK4-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK4-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK4-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK4: invoke.cont: // CHECK4-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -2954,7 +2954,7 @@ int main() { // CHECK4-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8 // CHECK4-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6:[0-9]+]] +// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6:[0-9]+]] // CHECK4-NEXT: br label [[EH_RESUME:%.*]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: store i32 100, i32* [[I]], align 4 @@ -2990,16 +2990,16 @@ int main() { // CHECK4-NEXT: store i32 100, i32* [[I7]], align 4 // CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[A]], align 1 // CHECK4-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32 -// CHECK4-NEXT: [[CALL19:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() +// CHECK4-NEXT: [[CALL19:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() // CHECK4-NEXT: to label [[INVOKE_CONT18:%.*]] unwind label [[LPAD]] // CHECK4: invoke.cont18: // CHECK4-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV]], [[CALL19]] -// CHECK4-NEXT: [[CALL22:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() +// CHECK4-NEXT: [[CALL22:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() // CHECK4-NEXT: to label [[INVOKE_CONT21:%.*]] unwind label [[LPAD]] // CHECK4: invoke.cont21: // CHECK4-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] // CHECK4-NEXT: store i32 [[ADD23]], i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP15]] // CHECK4: eh.resume: @@ -3017,7 +3017,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -3025,12 +3025,12 @@ int main() { // CHECK4-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3169,11 +3169,11 @@ int main() { // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK4-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK4-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK4-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]] // CHECK4: invoke.cont2: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK4-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK4-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK4-NEXT: store i32 99, i32* [[DOTOMP_UB5]], align 4 @@ -3213,17 +3213,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK4-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -3237,7 +3237,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3261,8 +3261,8 @@ int main() { // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK5-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK5-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK5-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -3280,7 +3280,7 @@ int main() { // CHECK5-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK5-NEXT: br label [[EH_RESUME:%.*]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -3311,16 +3311,16 @@ int main() { // CHECK5: omp_offload.cont3: // CHECK5-NEXT: [[TMP19:%.*]] = load i8, i8* [[A]], align 1 // CHECK5-NEXT: [[CONV4:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK5-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() +// CHECK5-NEXT: [[CALL6:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() // CHECK5-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK5: invoke.cont5: // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK5-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() +// CHECK5-NEXT: [[CALL8:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() // CHECK5-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK5: invoke.cont7: // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK5-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP20]] // CHECK5: eh.resume: @@ -3332,7 +3332,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -3340,12 +3340,12 @@ int main() { // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3364,7 +3364,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3399,24 +3399,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !9 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !9 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3432,7 +3432,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3477,26 +3477,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !13 +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3513,7 +3513,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK5-NEXT: catch i8* null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9:[0-9]+]], !llvm.access.group !13 +// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9:[0-9]+]] // CHECK5-NEXT: unreachable // // @@ -3525,7 +3525,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 -// CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -3543,7 +3543,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3581,26 +3581,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3616,7 +3616,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3661,26 +3661,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !21 +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3697,7 +3697,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK5-NEXT: catch i8* null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !21 +// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK5-NEXT: unreachable // // @@ -3740,11 +3740,11 @@ int main() { // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]] // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: -// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK5-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK5-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32 @@ -3766,17 +3766,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK5-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -3797,7 +3797,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3832,24 +3832,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !24 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3865,7 +3865,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3910,26 +3910,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !27 +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3946,7 +3946,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK5-NEXT: catch i8* null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !27 +// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK5-NEXT: unreachable // // @@ -3958,7 +3958,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3993,24 +3993,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !30 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4026,7 +4026,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4071,26 +4071,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !33 +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4107,7 +4107,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK5-NEXT: catch i8* null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !33 +// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK5-NEXT: unreachable // // @@ -4119,7 +4119,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4154,24 +4154,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !36 -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4187,7 +4187,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4232,26 +4232,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !39 +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4268,7 +4268,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK5-NEXT: catch i8* null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !39 +// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK5-NEXT: unreachable // // @@ -4280,11 +4280,11 @@ int main() { // CHECK5-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK5-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK5: invoke.cont: -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK5-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK5-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK5-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* @@ -4307,7 +4307,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4345,26 +4345,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42 +// CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK5-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42 +// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4380,7 +4380,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4425,26 +4425,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 +// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !45 +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -4461,12 +4461,12 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK5-NEXT: catch i8* null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !45 +// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK5-NEXT: unreachable // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4497,8 +4497,8 @@ int main() { // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK6-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK6-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK6-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -4516,7 +4516,7 @@ int main() { // CHECK6-NEXT: store i8* [[TMP3]], i8** [[EXN_SLOT]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = extractvalue { i8*, i32 } [[TMP2]], 1 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK6-NEXT: br label [[EH_RESUME:%.*]] // CHECK6: omp_offload.cont: // CHECK6-NEXT: [[TMP5:%.*]] = load i8, i8* [[A]], align 1 @@ -4547,16 +4547,16 @@ int main() { // CHECK6: omp_offload.cont3: // CHECK6-NEXT: [[TMP19:%.*]] = load i8, i8* [[A]], align 1 // CHECK6-NEXT: [[CONV4:%.*]] = sext i8 [[TMP19]] to i32 -// CHECK6-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() +// CHECK6-NEXT: [[CALL6:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() // CHECK6-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK6: invoke.cont5: // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV4]], [[CALL6]] -// CHECK6-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() +// CHECK6-NEXT: [[CALL8:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() // CHECK6-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] // CHECK6: invoke.cont7: // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK6-NEXT: store i32 [[ADD9]], i32* [[RETVAL]], align 4 -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP20]] // CHECK6: eh.resume: @@ -4568,7 +4568,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -4576,12 +4576,12 @@ int main() { // CHECK6-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4600,7 +4600,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4635,24 +4635,24 @@ int main() { // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !9 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !9 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -4668,7 +4668,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4713,26 +4713,26 @@ int main() { // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !13 +// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -4749,7 +4749,7 @@ int main() { // CHECK6-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK6-NEXT: catch i8* null // CHECK6-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9:[0-9]+]], !llvm.access.group !13 +// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9:[0-9]+]] // CHECK6-NEXT: unreachable // // @@ -4761,7 +4761,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 -// CHECK6-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -4779,7 +4779,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4817,26 +4817,26 @@ int main() { // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !18 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !18 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -4852,7 +4852,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4897,26 +4897,26 @@ int main() { // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !21 +// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -4933,7 +4933,7 @@ int main() { // CHECK6-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK6-NEXT: catch i8* null // CHECK6-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !21 +// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK6-NEXT: unreachable // // @@ -4976,11 +4976,11 @@ int main() { // CHECK6-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]] // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK6: omp_offload.cont: -// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK6-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK6-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32 @@ -5002,17 +5002,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK6-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -5033,7 +5033,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5068,24 +5068,24 @@ int main() { // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group !24 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 5) +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5101,7 +5101,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5146,26 +5146,26 @@ int main() { // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !27 +// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5182,7 +5182,7 @@ int main() { // CHECK6-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK6-NEXT: catch i8* null // CHECK6-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !27 +// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK6-NEXT: unreachable // // @@ -5194,7 +5194,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5229,24 +5229,24 @@ int main() { // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group !30 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 23) +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !30 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5262,7 +5262,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5307,26 +5307,26 @@ int main() { // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !33 +// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5343,7 +5343,7 @@ int main() { // CHECK6-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK6-NEXT: catch i8* null // CHECK6-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !33 +// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK6-NEXT: unreachable // // @@ -5355,7 +5355,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5390,24 +5390,24 @@ int main() { // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group !36 -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 1) +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5423,7 +5423,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5468,26 +5468,26 @@ int main() { // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !39 +// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5504,7 +5504,7 @@ int main() { // CHECK6-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK6-NEXT: catch i8* null // CHECK6-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !39 +// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK6-NEXT: unreachable // // @@ -5516,11 +5516,11 @@ int main() { // CHECK6-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 -// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK6-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK6: invoke.cont: -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK6-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK6-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK6-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* @@ -5543,7 +5543,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5581,26 +5581,26 @@ int main() { // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8, !llvm.access.group !42 +// CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 8 // CHECK6-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group !42 -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42 +// CHECK6-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]) +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK6-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42 +// CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !42 +// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP10]], i64 [[TMP12]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42 +// CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5616,7 +5616,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5661,26 +5661,26 @@ int main() { // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: -// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 +// CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK6: omp.inner.for.body: -// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 +// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK6-NEXT: invoke void @_Z3foov() -// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group !45 +// CHECK6-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK6: invoke.cont: // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK6: omp.inner.for.inc: -// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK6: omp.loop.exit: @@ -5697,12 +5697,12 @@ int main() { // CHECK6-NEXT: [[TMP13:%.*]] = landingpad { i8*, i32 } // CHECK6-NEXT: catch i8* null // CHECK6-NEXT: [[TMP14:%.*]] = extractvalue { i8*, i32 } [[TMP13]], 0 -// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]], !llvm.access.group !45 +// CHECK6-NEXT: call void @__clang_call_terminate(i8* [[TMP14]]) #[[ATTR9]] // CHECK6-NEXT: unreachable // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5737,8 +5737,8 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I7:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK7-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK7-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK7-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK7: invoke.cont: // CHECK7-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -5775,7 +5775,7 @@ int main() { // CHECK7-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8 // CHECK7-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1 // CHECK7-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6:[0-9]+]] +// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6:[0-9]+]] // CHECK7-NEXT: br label [[EH_RESUME:%.*]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 100, i32* [[I]], align 4 @@ -5811,16 +5811,16 @@ int main() { // CHECK7-NEXT: store i32 100, i32* [[I7]], align 4 // CHECK7-NEXT: [[TMP14:%.*]] = load i8, i8* [[A]], align 1 // CHECK7-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32 -// CHECK7-NEXT: [[CALL19:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() +// CHECK7-NEXT: [[CALL19:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() // CHECK7-NEXT: to label [[INVOKE_CONT18:%.*]] unwind label [[LPAD]] // CHECK7: invoke.cont18: // CHECK7-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV]], [[CALL19]] -// CHECK7-NEXT: [[CALL22:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() +// CHECK7-NEXT: [[CALL22:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() // CHECK7-NEXT: to label [[INVOKE_CONT21:%.*]] unwind label [[LPAD]] // CHECK7: invoke.cont21: // CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] // CHECK7-NEXT: store i32 [[ADD23]], i32* [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP15]] // CHECK7: eh.resume: @@ -5838,7 +5838,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -5846,12 +5846,12 @@ int main() { // CHECK7-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5990,11 +5990,11 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK7-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK7-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK7-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]] // CHECK7: invoke.cont2: -// CHECK7-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK7-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK7-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK7-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK7-NEXT: store i32 99, i32* [[DOTOMP_UB5]], align 4 @@ -6034,17 +6034,17 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK7-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -6058,7 +6058,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6086,8 +6086,8 @@ int main() { // CHECK8-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I7:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SC1El(%struct.S* noundef [[S]], i64 noundef 0) -// CHECK8-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[S]]) +// CHECK8-NEXT: call void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[S]], i64 0) +// CHECK8-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) // CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK8: invoke.cont: // CHECK8-NEXT: store i8 [[CALL]], i8* [[A]], align 1 @@ -6124,7 +6124,7 @@ int main() { // CHECK8-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8 // CHECK8-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1 // CHECK8-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4 -// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6:[0-9]+]] +// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6:[0-9]+]] // CHECK8-NEXT: br label [[EH_RESUME:%.*]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 100, i32* [[I]], align 4 @@ -6160,16 +6160,16 @@ int main() { // CHECK8-NEXT: store i32 100, i32* [[I7]], align 4 // CHECK8-NEXT: [[TMP14:%.*]] = load i8, i8* [[A]], align 1 // CHECK8-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32 -// CHECK8-NEXT: [[CALL19:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() +// CHECK8-NEXT: [[CALL19:%.*]] = invoke signext i32 @_Z5tmainIcLi5EEiv() // CHECK8-NEXT: to label [[INVOKE_CONT18:%.*]] unwind label [[LPAD]] // CHECK8: invoke.cont18: // CHECK8-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV]], [[CALL19]] -// CHECK8-NEXT: [[CALL22:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() +// CHECK8-NEXT: [[CALL22:%.*]] = invoke signext i32 @_Z5tmainI1SLi1EEiv() // CHECK8-NEXT: to label [[INVOKE_CONT21:%.*]] unwind label [[LPAD]] // CHECK8: invoke.cont21: // CHECK8-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] // CHECK8-NEXT: store i32 [[ADD23]], i32* [[RETVAL]], align 4 -// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[S]]) #[[ATTR6]] +// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] // CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP15]] // CHECK8: eh.resume: @@ -6187,7 +6187,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SC1El -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -6195,12 +6195,12 @@ int main() { // CHECK8-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SC2El(%struct.S* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SC2El(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]], i64 [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1ScvcEv -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -6339,11 +6339,11 @@ int main() { // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 100, i32* [[I]], align 4 -// CHECK8-NEXT: invoke void @_ZN1SC1El(%struct.S* noundef [[REF_TMP]], i64 noundef 23) +// CHECK8-NEXT: invoke void @_ZN1SC1El(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) // CHECK8-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]] // CHECK8: invoke.cont2: -// CHECK8-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(%struct.S* noundef [[REF_TMP]]) -// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* noundef [[REF_TMP]]) #[[ATTR6]] +// CHECK8-NEXT: [[CALL:%.*]] = call signext i8 @_ZN1ScvcEv(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK8-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] // CHECK8-NEXT: store i8 [[CALL]], i8* [[DOTCAPTURE_EXPR_]], align 1 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 // CHECK8-NEXT: store i32 99, i32* [[DOTOMP_UB5]], align 4 @@ -6383,17 +6383,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SD2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR6]] +// CHECK8-NEXT: call void @_ZN1SD2Ev(%struct.S* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SC2El -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 @@ -6407,7 +6407,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp index 0704b945241852f395134bea0407653a138da0b0..70aab1a2a1b0ecf37d4860abb403c4fc594756d3 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp @@ -147,33 +147,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -186,7 +186,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -197,14 +197,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -212,12 +212,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -225,7 +225,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -233,7 +233,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -252,7 +252,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -271,7 +271,7 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98() #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -283,7 +283,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -310,12 +310,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -334,25 +334,25 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !5 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -366,14 +366,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -381,7 +381,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -418,12 +418,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -442,40 +442,40 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false), !llvm.access.group !9 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK1-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -489,14 +489,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -514,14 +514,14 @@ int main() { // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -539,27 +539,27 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP4]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -567,7 +567,7 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // @@ -579,7 +579,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -608,12 +608,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -633,25 +633,25 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !14 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -665,14 +665,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done5: @@ -680,7 +680,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -719,12 +719,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -744,37 +744,37 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* // CHECK1-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !17 +// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -788,14 +788,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done9: @@ -803,17 +803,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -825,7 +825,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -841,7 +841,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -868,33 +868,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -907,7 +907,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -918,14 +918,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -933,12 +933,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -946,7 +946,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -954,7 +954,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -973,7 +973,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -992,7 +992,7 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98() #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -1004,7 +1004,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1031,12 +1031,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1055,25 +1055,25 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !5 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1087,14 +1087,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done3: @@ -1102,7 +1102,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1139,12 +1139,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1163,40 +1163,40 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false), !llvm.access.group !9 -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK2-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1210,14 +1210,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done8: @@ -1235,14 +1235,14 @@ int main() { // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -1260,27 +1260,27 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP4]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1288,7 +1288,7 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // @@ -1300,7 +1300,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1329,12 +1329,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1354,25 +1354,25 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !14 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1386,14 +1386,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done5: @@ -1401,7 +1401,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1440,12 +1440,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -1465,37 +1465,37 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* // CHECK2-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group !17 +// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1509,14 +1509,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done9: @@ -1524,17 +1524,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1546,7 +1546,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1562,7 +1562,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1589,33 +1589,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1628,7 +1628,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1639,14 +1639,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1654,12 +1654,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1667,7 +1667,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1675,7 +1675,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1694,7 +1694,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -1713,7 +1713,7 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98() #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -1725,7 +1725,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1752,12 +1752,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1776,23 +1776,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !6 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1806,14 +1806,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done3: @@ -1821,7 +1821,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1856,12 +1856,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1880,38 +1880,38 @@ int main() { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]] // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* // CHECK3-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false), !llvm.access.group !10 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1925,14 +1925,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -1950,14 +1950,14 @@ int main() { // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -1975,27 +1975,27 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP4]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2003,7 +2003,7 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // @@ -2015,7 +2015,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2044,12 +2044,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2069,23 +2069,23 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !15 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2099,14 +2099,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done5: @@ -2114,7 +2114,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2151,12 +2151,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2176,35 +2176,35 @@ int main() { // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK3-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* // CHECK3-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !18 +// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2218,14 +2218,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -2233,17 +2233,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2255,7 +2255,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2271,7 +2271,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2298,33 +2298,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2337,7 +2337,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2348,14 +2348,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2363,12 +2363,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -2376,7 +2376,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -2384,7 +2384,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2403,7 +2403,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -2422,7 +2422,7 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98() #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // @@ -2434,7 +2434,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2461,12 +2461,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2485,23 +2485,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !6 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2515,14 +2515,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done3: @@ -2530,7 +2530,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2565,12 +2565,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2589,38 +2589,38 @@ int main() { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK4-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]] // CHECK4-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* // CHECK4-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false), !llvm.access.group !10 -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2634,14 +2634,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done6: @@ -2659,14 +2659,14 @@ int main() { // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) @@ -2684,27 +2684,27 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP4]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2712,7 +2712,7 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // @@ -2724,7 +2724,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2753,12 +2753,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2778,23 +2778,23 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group !15 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2808,14 +2808,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done5: @@ -2823,7 +2823,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2860,12 +2860,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -2885,35 +2885,35 @@ int main() { // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] -// CHECK4-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK4-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* // CHECK4-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* -// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group !18 +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 -// CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2927,14 +2927,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP21]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done7: @@ -2942,17 +2942,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2964,7 +2964,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2980,7 +2980,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3007,42 +3007,42 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3050,12 +3050,12 @@ int main() { // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3063,7 +3063,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -3073,7 +3073,7 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // @@ -3102,12 +3102,12 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 @@ -3146,18 +3146,18 @@ int main() { // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done6: -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK5-NEXT: ret i32 [[CALL]] // // @@ -3181,14 +3181,14 @@ int main() { // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3200,12 +3200,12 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: @@ -3242,14 +3242,14 @@ int main() { // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done11: @@ -3260,17 +3260,17 @@ int main() { // CHECK5: arraydestroy.body13: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK5: arraydestroy.done17: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP14]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3283,7 +3283,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3292,7 +3292,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3309,17 +3309,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3327,22 +3327,22 @@ int main() { // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3354,7 +3354,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3370,7 +3370,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3390,42 +3390,42 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3433,12 +3433,12 @@ int main() { // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3446,7 +3446,7 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: @@ -3456,7 +3456,7 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // @@ -3485,12 +3485,12 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 @@ -3529,18 +3529,18 @@ int main() { // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done6: -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK6-NEXT: ret i32 [[CALL]] // // @@ -3564,14 +3564,14 @@ int main() { // CHECK6-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK6-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK6-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3583,12 +3583,12 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK6-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: @@ -3625,14 +3625,14 @@ int main() { // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done11: @@ -3643,17 +3643,17 @@ int main() { // CHECK6: arraydestroy.body13: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK6: arraydestroy.done17: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP14]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3666,7 +3666,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3675,7 +3675,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3692,17 +3692,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3710,22 +3710,22 @@ int main() { // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3737,7 +3737,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3753,7 +3753,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3773,42 +3773,42 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3816,12 +3816,12 @@ int main() { // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -3829,7 +3829,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -3839,7 +3839,7 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // @@ -3868,12 +3868,12 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 @@ -3910,18 +3910,18 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done5: -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK7-NEXT: ret i32 [[CALL]] // // @@ -3945,14 +3945,14 @@ int main() { // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3964,12 +3964,12 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: @@ -4004,14 +4004,14 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done10: @@ -4022,17 +4022,17 @@ int main() { // CHECK7: arraydestroy.body12: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK7: arraydestroy.done16: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP14]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4045,7 +4045,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4054,7 +4054,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4071,17 +4071,17 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4089,22 +4089,22 @@ int main() { // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4116,7 +4116,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4132,7 +4132,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4152,42 +4152,42 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4195,12 +4195,12 @@ int main() { // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -4208,7 +4208,7 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done1: @@ -4218,7 +4218,7 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // @@ -4247,12 +4247,12 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 @@ -4289,18 +4289,18 @@ int main() { // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done5: -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK8-NEXT: ret i32 [[CALL]] // // @@ -4324,14 +4324,14 @@ int main() { // CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK8-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -4343,12 +4343,12 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: @@ -4383,14 +4383,14 @@ int main() { // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done10: @@ -4401,17 +4401,17 @@ int main() { // CHECK8: arraydestroy.body12: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK8: arraydestroy.done16: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP14]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4424,7 +4424,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4433,7 +4433,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4450,17 +4450,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4468,22 +4468,22 @@ int main() { // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4495,7 +4495,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4511,7 +4511,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4531,33 +4531,33 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4570,7 +4570,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4581,14 +4581,14 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4596,12 +4596,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4609,7 +4609,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -4617,7 +4617,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4636,7 +4636,7 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // @@ -4647,12 +4647,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 @@ -4664,7 +4664,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4706,23 +4706,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !4 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4738,7 +4738,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4791,35 +4791,35 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK9-NEXT: store i32 1, i32* [[G]], align 4, !llvm.access.group !8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8, !llvm.access.group !8 -// CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8 -// CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4, !llvm.access.group !8 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[G]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[G]], i32** [[TMP11]], align 8, !llvm.access.group !8 +// CHECK9-NEXT: store i32* [[G]], i32** [[TMP11]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8, !llvm.access.group !8 -// CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8, !llvm.access.group !8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4853,33 +4853,33 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4892,7 +4892,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4903,14 +4903,14 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4918,12 +4918,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4931,7 +4931,7 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: @@ -4939,7 +4939,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4958,7 +4958,7 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // @@ -4969,12 +4969,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK10-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK10-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 @@ -4986,7 +4986,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5028,23 +5028,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !4 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5060,7 +5060,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5113,35 +5113,35 @@ int main() { // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK10-NEXT: store i32 1, i32* [[G]], align 4, !llvm.access.group !8 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8, !llvm.access.group !8 -// CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4, !llvm.access.group !8 -// CHECK10-NEXT: store i32 2, i32* [[SIVAR]], align 4, !llvm.access.group !8 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[G]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 +// CHECK10-NEXT: store i32 2, i32* [[SIVAR]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[G]], i32** [[TMP11]], align 8, !llvm.access.group !8 +// CHECK10-NEXT: store i32* [[G]], i32** [[TMP11]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8, !llvm.access.group !8 -// CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8, !llvm.access.group !8 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8 +// CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8, !llvm.access.group !8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5175,42 +5175,42 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5218,12 +5218,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -5231,7 +5231,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -5241,7 +5241,7 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // @@ -5252,12 +5252,12 @@ int main() { // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: ret i32 0 // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5270,7 +5270,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5279,7 +5279,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5307,42 +5307,42 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5350,12 +5350,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -5363,7 +5363,7 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done1: @@ -5373,7 +5373,7 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // @@ -5384,12 +5384,12 @@ int main() { // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK12-NEXT: ret i32 0 // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5402,7 +5402,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5411,7 +5411,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_proc_bind_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_proc_bind_codegen.cpp index b621208c3d3b31391b234745110c8d3ef450247c..9fbe2624c0ffd1c40781112b3b8f1b4d848287d7 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_proc_bind_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_proc_bind_codegen.cpp @@ -75,7 +75,7 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l39() #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT3]] // CHECK1: omp_offload.cont3: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -87,7 +87,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -122,24 +122,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group !6 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !6 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -155,7 +155,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -200,23 +200,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -239,7 +239,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -274,24 +274,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group !15 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -307,7 +307,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -352,23 +352,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -406,7 +406,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -441,24 +441,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !21 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !21 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -474,7 +474,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -519,23 +519,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -580,7 +580,7 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l39() #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT3]] // CHECK2: omp_offload.cont3: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -592,7 +592,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -627,24 +627,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4), !llvm.access.group !6 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 4) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !6 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -660,7 +660,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -705,23 +705,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -744,7 +744,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -779,24 +779,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3), !llvm.access.group !15 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 3) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !15 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -812,7 +812,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -857,23 +857,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -911,7 +911,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -946,24 +946,24 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group !21 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: call void @__kmpc_push_proc_bind(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]], i32 2) +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !21 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !21 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -979,7 +979,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1024,23 +1024,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1127,7 +1127,7 @@ int main() { // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK3: omp.inner.for.end15: // CHECK3-NEXT: store i32 1000, i32* [[I6]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -1232,7 +1232,7 @@ int main() { // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK4: omp.inner.for.end15: // CHECK4-NEXT: store i32 1000, i32* [[I6]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_codegen.cpp index f0cb75cad40fa4a1725716937b3aeef710d8ee58..9ffb3b44aedaf3754a9bf0c3113429b82c970265 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_codegen.cpp @@ -129,12 +129,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70 -// CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -144,7 +144,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -185,23 +185,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]), !llvm.access.group !5 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -238,7 +238,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -289,27 +289,27 @@ int main() { // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -346,7 +346,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -370,7 +370,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -432,7 +432,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 @@ -442,7 +442,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -483,23 +483,23 @@ int main() { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[T_VAR1]]), !llvm.access.group !14 +// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[T_VAR1]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -536,7 +536,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -587,27 +587,27 @@ int main() { // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK1-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -644,7 +644,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -668,7 +668,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -730,12 +730,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70 -// CHECK2-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -745,7 +745,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -786,23 +786,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]), !llvm.access.group !5 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -839,7 +839,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -890,27 +890,27 @@ int main() { // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK2-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -947,7 +947,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -971,7 +971,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1033,7 +1033,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK2-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 @@ -1043,7 +1043,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1084,23 +1084,23 @@ int main() { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[T_VAR1]]), !llvm.access.group !14 +// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[T_VAR1]]) // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !14 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1137,7 +1137,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1188,27 +1188,27 @@ int main() { // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR2]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK2-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: store i32 [[ADD4]], i32* [[T_VAR2]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1245,7 +1245,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1269,7 +1269,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1330,12 +1330,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70 -// CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 @@ -1344,7 +1344,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1385,21 +1385,21 @@ int main() { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[SIVAR1]]), !llvm.access.group !6 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[SIVAR1]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1436,7 +1436,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1485,27 +1485,27 @@ int main() { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1542,7 +1542,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1566,7 +1566,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1627,7 +1627,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 @@ -1636,7 +1636,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1677,21 +1677,21 @@ int main() { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[T_VAR1]]), !llvm.access.group !15 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[T_VAR1]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1728,7 +1728,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1777,27 +1777,27 @@ int main() { // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR1]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1834,7 +1834,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1858,7 +1858,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1919,12 +1919,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l70 -// CHECK4-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 @@ -1933,7 +1933,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1974,21 +1974,21 @@ int main() { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[SIVAR1]]), !llvm.access.group !6 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[SIVAR1]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2025,7 +2025,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2074,27 +2074,27 @@ int main() { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2131,7 +2131,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2155,7 +2155,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2216,7 +2216,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK4-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 @@ -2225,7 +2225,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2266,21 +2266,21 @@ int main() { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[T_VAR1]]), !llvm.access.group !15 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 +// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP8]], i32 [[TMP9]], i32* [[T_VAR1]]) // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !15 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2317,7 +2317,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2366,27 +2366,27 @@ int main() { // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR1]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2423,7 +2423,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.5 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2447,7 +2447,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.6 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -2522,7 +2522,7 @@ int main() { // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK5-NEXT: ret i32 [[CALL]] // // @@ -2622,7 +2622,7 @@ int main() { // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK6-NEXT: ret i32 [[CALL]] // // @@ -2722,7 +2722,7 @@ int main() { // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK7-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK7-NEXT: ret i32 [[CALL]] // // @@ -2822,7 +2822,7 @@ int main() { // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK8-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK8-NEXT: ret i32 [[CALL]] // // @@ -2883,12 +2883,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 -// CHECK9-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -2898,7 +2898,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2939,23 +2939,23 @@ int main() { // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]), !llvm.access.group !4 +// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -2992,7 +2992,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3044,30 +3044,30 @@ int main() { // CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4, !llvm.access.group !8 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !8 +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8, !llvm.access.group !8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK9-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8 +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3104,7 +3104,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3128,7 +3128,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3164,12 +3164,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 -// CHECK10-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -3179,7 +3179,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3220,23 +3220,23 @@ int main() { // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]), !llvm.access.group !4 +// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP9]], i64 [[TMP11]], i32* [[SIVAR1]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -3273,7 +3273,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3325,30 +3325,30 @@ int main() { // CHECK10-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !8 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4, !llvm.access.group !8 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[SIVAR2]], align 4 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4, !llvm.access.group !8 +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[SIVAR2]], align 4 // CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8, !llvm.access.group !8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !8 +// CHECK10-NEXT: store i32* [[SIVAR2]], i32** [[TMP13]], align 8 +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -3385,7 +3385,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3409,7 +3409,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -3445,7 +3445,7 @@ int main() { // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: ret i32 0 // // @@ -3455,6 +3455,6 @@ int main() { // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK12-NEXT: ret i32 0 // diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp index 54091b3f5260489ddfcdb29b557d5a7ff636e9ce..c62b4386594ff8b9cad1aecedfcef7cedb5d9782 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp @@ -222,12 +222,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -354,7 +354,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -364,7 +364,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -434,7 +434,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -519,7 +519,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l41 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -529,7 +529,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -599,7 +599,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -684,7 +684,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l46 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -694,7 +694,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -764,7 +764,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -870,7 +870,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l52 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -880,7 +880,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -950,7 +950,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1033,7 +1033,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l58 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1043,7 +1043,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1113,7 +1113,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1206,12 +1206,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -1338,7 +1338,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1348,7 +1348,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1418,7 +1418,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1503,7 +1503,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l41 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1513,7 +1513,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1583,7 +1583,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1668,7 +1668,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l46 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1678,7 +1678,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1748,7 +1748,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1854,7 +1854,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l52 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1864,7 +1864,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1934,7 +1934,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2017,7 +2017,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l58 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -2027,7 +2027,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2097,7 +2097,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2190,12 +2190,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -2322,7 +2322,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -2332,7 +2332,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2402,7 +2402,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2487,7 +2487,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l41 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -2497,7 +2497,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2567,7 +2567,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2652,7 +2652,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l46 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -2662,7 +2662,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2732,7 +2732,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2838,7 +2838,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l52 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -2848,7 +2848,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2918,7 +2918,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3001,7 +3001,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l58 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -3011,7 +3011,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3081,7 +3081,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3174,12 +3174,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -3306,7 +3306,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -3316,7 +3316,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3386,7 +3386,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3471,7 +3471,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l41 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -3481,7 +3481,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3551,7 +3551,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3636,7 +3636,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l46 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -3646,7 +3646,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3716,7 +3716,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3822,7 +3822,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l52 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -3832,7 +3832,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3902,7 +3902,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3985,7 +3985,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l58 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -3995,7 +3995,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4065,7 +4065,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4158,12 +4158,12 @@ int main (int argc, char **argv) { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -4290,7 +4290,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -4300,7 +4300,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4368,7 +4368,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4450,7 +4450,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l41 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -4460,7 +4460,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4528,7 +4528,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4610,7 +4610,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l46 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -4620,7 +4620,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4688,7 +4688,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4789,7 +4789,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l52 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -4799,7 +4799,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4867,7 +4867,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4947,7 +4947,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l58 -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -4957,7 +4957,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5025,7 +5025,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5115,12 +5115,12 @@ int main (int argc, char **argv) { // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK6-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -5247,7 +5247,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -5257,7 +5257,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5325,7 +5325,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5407,7 +5407,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l41 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -5417,7 +5417,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5485,7 +5485,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5567,7 +5567,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l46 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -5577,7 +5577,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5645,7 +5645,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5746,7 +5746,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l52 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -5756,7 +5756,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5824,7 +5824,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5904,7 +5904,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l58 -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -5914,7 +5914,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5982,7 +5982,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6072,12 +6072,12 @@ int main (int argc, char **argv) { // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -6204,7 +6204,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6214,7 +6214,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6282,7 +6282,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6364,7 +6364,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l41 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6374,7 +6374,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6442,7 +6442,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6524,7 +6524,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l46 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6534,7 +6534,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6602,7 +6602,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6703,7 +6703,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l52 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6713,7 +6713,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6781,7 +6781,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6861,7 +6861,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l58 -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -6871,7 +6871,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6939,7 +6939,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7029,12 +7029,12 @@ int main (int argc, char **argv) { // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK8-NEXT: ret i32 [[CALL]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -7161,7 +7161,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l36 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -7171,7 +7171,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7239,7 +7239,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7321,7 +7321,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l41 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -7331,7 +7331,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7399,7 +7399,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7481,7 +7481,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l46 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -7491,7 +7491,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7559,7 +7559,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7660,7 +7660,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l52 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -7670,7 +7670,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7738,7 +7738,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7818,7 +7818,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l58 -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -7828,7 +7828,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7896,7 +7896,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7986,12 +7986,12 @@ int main (int argc, char **argv) { // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK9-NEXT: ret i32 [[CALL]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK9-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK9-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -8181,12 +8181,12 @@ int main (int argc, char **argv) { // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK10-NEXT: ret i32 [[CALL]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK10-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK10-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -8376,12 +8376,12 @@ int main (int argc, char **argv) { // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK11-NEXT: ret i32 [[CALL]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK11-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK11-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -8566,12 +8566,12 @@ int main (int argc, char **argv) { // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK12-NEXT: ret i32 [[CALL]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK12-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK12-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -8753,7 +8753,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -9124,7 +9124,7 @@ int main (int argc, char **argv) { // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK13: omp_offload.cont65: // CHECK13-NEXT: [[TMP169:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP169]]) +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP169]]) // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP170:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP170]]) @@ -9133,7 +9133,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -9149,7 +9149,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9252,7 +9252,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9369,7 +9369,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l159 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -9385,7 +9385,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9488,7 +9488,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9605,7 +9605,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l164 -// CHECK13-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -9632,7 +9632,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9768,7 +9768,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -9888,7 +9888,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l169 -// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -9904,7 +9904,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10007,7 +10007,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10120,7 +10120,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174 -// CHECK13-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -10147,7 +10147,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10258,7 +10258,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10375,7 +10375,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -10522,7 +10522,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l122 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -10532,7 +10532,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10602,7 +10602,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10686,7 +10686,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l127 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -10696,7 +10696,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10766,7 +10766,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10850,7 +10850,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l132 -// CHECK13-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -10871,7 +10871,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -10949,7 +10949,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11058,7 +11058,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l137 -// CHECK13-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK13-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -11068,7 +11068,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11138,7 +11138,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11220,7 +11220,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l142 -// CHECK13-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -11241,7 +11241,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11319,7 +11319,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK13-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11412,7 +11412,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -11783,7 +11783,7 @@ int main (int argc, char **argv) { // CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK14: omp_offload.cont65: // CHECK14-NEXT: [[TMP169:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP169]]) +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP169]]) // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[TMP170:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP170]]) @@ -11792,7 +11792,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -11808,7 +11808,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -11911,7 +11911,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12028,7 +12028,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l159 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -12044,7 +12044,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12147,7 +12147,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12264,7 +12264,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l164 -// CHECK14-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -12291,7 +12291,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12427,7 +12427,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12547,7 +12547,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l169 -// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -12563,7 +12563,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12666,7 +12666,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12779,7 +12779,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174 -// CHECK14-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -12806,7 +12806,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -12917,7 +12917,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13034,7 +13034,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -13181,7 +13181,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l122 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -13191,7 +13191,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13261,7 +13261,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13345,7 +13345,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l127 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -13355,7 +13355,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13425,7 +13425,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13509,7 +13509,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l132 -// CHECK14-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -13530,7 +13530,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13608,7 +13608,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13717,7 +13717,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l137 -// CHECK14-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK14-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -13727,7 +13727,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13797,7 +13797,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13879,7 +13879,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l142 -// CHECK14-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -13900,7 +13900,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -13978,7 +13978,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK14-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK14-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14071,7 +14071,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -14442,7 +14442,7 @@ int main (int argc, char **argv) { // CHECK15-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK15: omp_offload.cont65: // CHECK15-NEXT: [[TMP169:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP169]]) +// CHECK15-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP169]]) // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP170:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP170]]) @@ -14451,7 +14451,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154 -// CHECK15-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK15-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -14467,7 +14467,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14570,7 +14570,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14687,7 +14687,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l159 -// CHECK15-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -14703,7 +14703,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14806,7 +14806,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -14923,7 +14923,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l164 -// CHECK15-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -14950,7 +14950,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15086,7 +15086,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15206,7 +15206,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l169 -// CHECK15-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK15-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -15222,7 +15222,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15325,7 +15325,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15438,7 +15438,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174 -// CHECK15-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -15465,7 +15465,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15576,7 +15576,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15693,7 +15693,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK15-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -15840,7 +15840,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l122 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -15850,7 +15850,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -15920,7 +15920,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16004,7 +16004,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l127 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -16014,7 +16014,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16084,7 +16084,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16168,7 +16168,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l132 -// CHECK15-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -16189,7 +16189,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16267,7 +16267,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16376,7 +16376,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l137 -// CHECK15-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK15-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -16386,7 +16386,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16456,7 +16456,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16538,7 +16538,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l142 -// CHECK15-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -16559,7 +16559,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16637,7 +16637,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK15-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -16730,7 +16730,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -17101,7 +17101,7 @@ int main (int argc, char **argv) { // CHECK16-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK16: omp_offload.cont65: // CHECK16-NEXT: [[TMP169:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP169]]) +// CHECK16-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP169]]) // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[TMP170:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP170]]) @@ -17110,7 +17110,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154 -// CHECK16-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK16-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -17126,7 +17126,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17229,7 +17229,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17346,7 +17346,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l159 -// CHECK16-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -17362,7 +17362,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17465,7 +17465,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17582,7 +17582,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l164 -// CHECK16-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -17609,7 +17609,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17745,7 +17745,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17865,7 +17865,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l169 -// CHECK16-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK16-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -17881,7 +17881,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -17984,7 +17984,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18097,7 +18097,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174 -// CHECK16-SAME: (i64 noundef [[M:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i64 [[M:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -18124,7 +18124,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18235,7 +18235,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18352,7 +18352,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK16-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -18499,7 +18499,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l122 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -18509,7 +18509,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18579,7 +18579,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18663,7 +18663,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l127 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -18673,7 +18673,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18743,7 +18743,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18827,7 +18827,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l132 -// CHECK16-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -18848,7 +18848,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -18926,7 +18926,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19035,7 +19035,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l137 -// CHECK16-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK16-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -19045,7 +19045,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19115,7 +19115,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19197,7 +19197,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l142 -// CHECK16-SAME: (i64 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i64 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 @@ -19218,7 +19218,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19296,7 +19296,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK16-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK16-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -19389,7 +19389,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@main -// CHECK17-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK17-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -19757,7 +19757,7 @@ int main (int argc, char **argv) { // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT59]] // CHECK17: omp_offload.cont59: // CHECK17-NEXT: [[TMP173:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP173]]) +// CHECK17-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP173]]) // CHECK17-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK17-NEXT: [[TMP174:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP174]]) @@ -19766,7 +19766,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154 -// CHECK17-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK17-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -19781,7 +19781,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19882,7 +19882,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -19996,7 +19996,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l159 -// CHECK17-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -20011,7 +20011,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20112,7 +20112,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20226,7 +20226,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l164 -// CHECK17-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -20250,7 +20250,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20382,7 +20382,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20498,7 +20498,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l169 -// CHECK17-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -20513,7 +20513,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20614,7 +20614,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20724,7 +20724,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174 -// CHECK17-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -20748,7 +20748,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20855,7 +20855,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -20968,7 +20968,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK17-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK17-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -21113,7 +21113,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l122 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -21123,7 +21123,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21191,7 +21191,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21272,7 +21272,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l127 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -21282,7 +21282,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21350,7 +21350,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21431,7 +21431,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l132 -// CHECK17-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -21450,7 +21450,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21524,7 +21524,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21627,7 +21627,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l137 -// CHECK17-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK17-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -21637,7 +21637,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21705,7 +21705,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21784,7 +21784,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l142 -// CHECK17-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -21803,7 +21803,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21877,7 +21877,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -21966,7 +21966,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@main -// CHECK18-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK18-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -22334,7 +22334,7 @@ int main (int argc, char **argv) { // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT59]] // CHECK18: omp_offload.cont59: // CHECK18-NEXT: [[TMP173:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP173]]) +// CHECK18-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP173]]) // CHECK18-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK18-NEXT: [[TMP174:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP174]]) @@ -22343,7 +22343,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154 -// CHECK18-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK18-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -22358,7 +22358,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22459,7 +22459,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22573,7 +22573,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l159 -// CHECK18-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -22588,7 +22588,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22689,7 +22689,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22803,7 +22803,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l164 -// CHECK18-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -22827,7 +22827,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -22959,7 +22959,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23075,7 +23075,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l169 -// CHECK18-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -23090,7 +23090,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23191,7 +23191,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23301,7 +23301,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174 -// CHECK18-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -23325,7 +23325,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23432,7 +23432,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23545,7 +23545,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK18-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK18-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -23690,7 +23690,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l122 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -23700,7 +23700,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23768,7 +23768,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23849,7 +23849,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l127 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -23859,7 +23859,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -23927,7 +23927,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24008,7 +24008,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l132 -// CHECK18-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -24027,7 +24027,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24101,7 +24101,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24204,7 +24204,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l137 -// CHECK18-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK18-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -24214,7 +24214,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24282,7 +24282,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24361,7 +24361,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l142 -// CHECK18-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -24380,7 +24380,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24454,7 +24454,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -24543,7 +24543,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@main -// CHECK19-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK19-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -24911,7 +24911,7 @@ int main (int argc, char **argv) { // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT59]] // CHECK19: omp_offload.cont59: // CHECK19-NEXT: [[TMP173:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP173]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP173]]) // CHECK19-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK19-NEXT: [[TMP174:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP174]]) @@ -24920,7 +24920,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -24935,7 +24935,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25036,7 +25036,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25150,7 +25150,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l159 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -25165,7 +25165,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25266,7 +25266,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25380,7 +25380,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l164 -// CHECK19-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -25404,7 +25404,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25536,7 +25536,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25652,7 +25652,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l169 -// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -25667,7 +25667,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25768,7 +25768,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -25878,7 +25878,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174 -// CHECK19-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -25902,7 +25902,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26009,7 +26009,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26122,7 +26122,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK19-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK19-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -26267,7 +26267,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l122 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -26277,7 +26277,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26345,7 +26345,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26426,7 +26426,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l127 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -26436,7 +26436,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26504,7 +26504,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26585,7 +26585,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l132 -// CHECK19-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -26604,7 +26604,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26678,7 +26678,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26781,7 +26781,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l137 -// CHECK19-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK19-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -26791,7 +26791,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26859,7 +26859,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -26938,7 +26938,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l142 -// CHECK19-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -26957,7 +26957,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27031,7 +27031,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27120,7 +27120,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@main -// CHECK20-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK20-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -27488,7 +27488,7 @@ int main (int argc, char **argv) { // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT59]] // CHECK20: omp_offload.cont59: // CHECK20-NEXT: [[TMP173:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP173]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP173]]) // CHECK20-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK20-NEXT: [[TMP174:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP174]]) @@ -27497,7 +27497,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -27512,7 +27512,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27613,7 +27613,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27727,7 +27727,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l159 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -27742,7 +27742,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27843,7 +27843,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -27957,7 +27957,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l164 -// CHECK20-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -27981,7 +27981,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28113,7 +28113,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28229,7 +28229,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l169 -// CHECK20-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -28244,7 +28244,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..8 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28345,7 +28345,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28455,7 +28455,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174 -// CHECK20-SAME: (i32 noundef [[M:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[M:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -28479,7 +28479,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28586,7 +28586,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..12 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28699,7 +28699,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK20-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK20-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -28844,7 +28844,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l122 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -28854,7 +28854,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -28922,7 +28922,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..15 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29003,7 +29003,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l127 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -29013,7 +29013,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..17 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29081,7 +29081,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..18 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29162,7 +29162,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l132 -// CHECK20-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -29181,7 +29181,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..21 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29255,7 +29255,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..22 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29358,7 +29358,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l137 -// CHECK20-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK20-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -29368,7 +29368,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..25 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29436,7 +29436,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..26 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29515,7 +29515,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l142 -// CHECK20-SAME: (i32 noundef [[M:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32 [[M:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 @@ -29534,7 +29534,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..29 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29608,7 +29608,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..30 -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -29697,7 +29697,7 @@ int main (int argc, char **argv) { // // // CHECK21-LABEL: define {{[^@]+}}@main -// CHECK21-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK21-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -30009,7 +30009,7 @@ int main (int argc, char **argv) { // CHECK21-NEXT: br label [[SIMD_IF_END127]] // CHECK21: simd.if.end127: // CHECK21-NEXT: [[TMP60:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP60]]) +// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP60]]) // CHECK21-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK21-NEXT: [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP61]]) @@ -30018,7 +30018,7 @@ int main (int argc, char **argv) { // // // CHECK21-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK21-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK21-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -30205,7 +30205,7 @@ int main (int argc, char **argv) { // // // CHECK22-LABEL: define {{[^@]+}}@main -// CHECK22-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK22-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK22-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -30517,7 +30517,7 @@ int main (int argc, char **argv) { // CHECK22-NEXT: br label [[SIMD_IF_END127]] // CHECK22: simd.if.end127: // CHECK22-NEXT: [[TMP60:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP60]]) +// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP60]]) // CHECK22-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK22-NEXT: [[TMP61:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP61]]) @@ -30526,7 +30526,7 @@ int main (int argc, char **argv) { // // // CHECK22-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK22-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK22-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK22-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -30713,7 +30713,7 @@ int main (int argc, char **argv) { // // // CHECK23-LABEL: define {{[^@]+}}@main -// CHECK23-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK23-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -31019,7 +31019,7 @@ int main (int argc, char **argv) { // CHECK23-NEXT: br label [[SIMD_IF_END123]] // CHECK23: simd.if.end123: // CHECK23-NEXT: [[TMP59:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP59]]) +// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP59]]) // CHECK23-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK23-NEXT: [[TMP60:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP60]]) @@ -31028,7 +31028,7 @@ int main (int argc, char **argv) { // // // CHECK23-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK23-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK23-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -31210,7 +31210,7 @@ int main (int argc, char **argv) { // // // CHECK24-LABEL: define {{[^@]+}}@main -// CHECK24-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK24-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -31516,7 +31516,7 @@ int main (int argc, char **argv) { // CHECK24-NEXT: br label [[SIMD_IF_END123]] // CHECK24: simd.if.end123: // CHECK24-NEXT: [[TMP59:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP59]]) +// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP59]]) // CHECK24-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK24-NEXT: [[TMP60:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP60]]) @@ -31525,7 +31525,7 @@ int main (int argc, char **argv) { // // // CHECK24-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK24-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK24-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK24-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 diff --git a/clang/test/OpenMP/teams_distribute_private_codegen.cpp b/clang/test/OpenMP/teams_distribute_private_codegen.cpp index b99a8788dee00399d98f1393fb35cd3e2449a7d2..01f76e7bf2bf75af3539563f170022184f4fc2ef 100644 --- a/clang/test/OpenMP/teams_distribute_private_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_private_codegen.cpp @@ -125,33 +125,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -164,7 +164,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -175,14 +175,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -190,12 +190,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -203,7 +203,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -211,7 +211,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -230,7 +230,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -249,7 +249,7 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -261,7 +261,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -288,12 +288,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -352,14 +352,14 @@ int main() { // CHECK1-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done7: @@ -377,14 +377,14 @@ int main() { // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -402,27 +402,27 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP4]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -430,7 +430,7 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // @@ -442,7 +442,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -471,12 +471,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -533,14 +533,14 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -548,17 +548,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -570,7 +570,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -586,7 +586,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -613,33 +613,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -652,7 +652,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -663,14 +663,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -678,12 +678,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -691,7 +691,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -699,7 +699,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -718,7 +718,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -737,7 +737,7 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -749,7 +749,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -776,12 +776,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -840,14 +840,14 @@ int main() { // CHECK2-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done7: @@ -865,14 +865,14 @@ int main() { // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -890,27 +890,27 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP4]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -918,7 +918,7 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // @@ -930,7 +930,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -959,12 +959,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1021,14 +1021,14 @@ int main() { // CHECK2-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done8: @@ -1036,17 +1036,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1058,7 +1058,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1074,7 +1074,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1101,33 +1101,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1140,7 +1140,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1151,14 +1151,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1166,12 +1166,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1179,7 +1179,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1187,7 +1187,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1206,7 +1206,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -1225,7 +1225,7 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -1237,7 +1237,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1264,12 +1264,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1326,14 +1326,14 @@ int main() { // CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -1351,14 +1351,14 @@ int main() { // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -1376,27 +1376,27 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP4]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1404,7 +1404,7 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // @@ -1416,7 +1416,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1445,12 +1445,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1505,14 +1505,14 @@ int main() { // CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -1520,17 +1520,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -1542,7 +1542,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1558,7 +1558,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -1585,33 +1585,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1624,7 +1624,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1635,14 +1635,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1650,12 +1650,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1663,7 +1663,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -1671,7 +1671,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1690,7 +1690,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -1709,7 +1709,7 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // @@ -1721,7 +1721,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1748,12 +1748,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1810,14 +1810,14 @@ int main() { // CHECK4-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done6: @@ -1835,14 +1835,14 @@ int main() { // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -1860,27 +1860,27 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP4]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1888,7 +1888,7 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // @@ -1900,7 +1900,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1929,12 +1929,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1989,14 +1989,14 @@ int main() { // CHECK4-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done7: @@ -2004,17 +2004,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2026,7 +2026,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2042,7 +2042,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2069,33 +2069,33 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2108,7 +2108,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2119,14 +2119,14 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2134,12 +2134,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2147,7 +2147,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -2155,7 +2155,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2174,7 +2174,7 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // @@ -2185,12 +2185,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 @@ -2202,7 +2202,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2265,7 +2265,7 @@ int main() { // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2300,33 +2300,33 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2339,7 +2339,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2350,14 +2350,14 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2365,12 +2365,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2378,7 +2378,7 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: @@ -2386,7 +2386,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2405,7 +2405,7 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // @@ -2416,12 +2416,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK10-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK10-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 @@ -2433,7 +2433,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2496,7 +2496,7 @@ int main() { // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -2527,3 +2527,4 @@ int main() { // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_reduction_codegen.cpp b/clang/test/OpenMP/teams_distribute_reduction_codegen.cpp index 59d5aac41fd7cdc6af26bf1be61979f91814e506..4421d295693d8764ac9e439565067c8c2f724c1b 100644 --- a/clang/test/OpenMP/teams_distribute_reduction_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_reduction_codegen.cpp @@ -114,12 +114,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63 -// CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -129,7 +129,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -221,7 +221,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -283,7 +283,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 @@ -293,7 +293,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -385,7 +385,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -447,12 +447,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63 -// CHECK2-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -462,7 +462,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -554,7 +554,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -616,7 +616,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK2-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 @@ -626,7 +626,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -718,7 +718,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -779,12 +779,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63 -// CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 @@ -793,7 +793,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -885,7 +885,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -946,7 +946,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 @@ -955,7 +955,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1047,7 +1047,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1108,12 +1108,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63 -// CHECK4-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 @@ -1122,7 +1122,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1214,7 +1214,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1275,7 +1275,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK4-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 @@ -1284,7 +1284,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1376,7 +1376,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1412,12 +1412,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 -// CHECK9-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -1427,7 +1427,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1484,7 +1484,7 @@ int main() { // CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1523,7 +1523,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1559,12 +1559,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 -// CHECK10-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -1574,7 +1574,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1631,7 +1631,7 @@ int main() { // CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 // CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1670,7 +1670,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -1699,3 +1699,4 @@ int main() { // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) // CHECK10-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/teams_distribute_simd_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_codegen.cpp index c5edbadcae85b970b4fc10a7cebfe50b61e91a71..7e95a42396ea5076d1fc4c654e414ab4a765f139 100644 --- a/clang/test/OpenMP/teams_distribute_simd_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_codegen.cpp @@ -212,7 +212,7 @@ int main (int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -362,7 +362,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l30 -// CHECK1-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]], i64 [[I:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -388,7 +388,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -497,7 +497,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l36 -// CHECK1-SAME: (i64 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 8 @@ -510,7 +510,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -621,7 +621,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -771,7 +771,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l30 -// CHECK2-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]], i64 [[I:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -797,7 +797,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -906,7 +906,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l36 -// CHECK2-SAME: (i64 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 8 @@ -919,7 +919,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1030,7 +1030,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1175,7 +1175,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l30 -// CHECK3-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]], i32 [[I:%.*]], i32 [[N:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -1197,7 +1197,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1305,7 +1305,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l36 -// CHECK3-SAME: (i32 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 4 @@ -1317,7 +1317,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1427,7 +1427,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1572,7 +1572,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l30 -// CHECK4-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]], i32 [[I:%.*]], i32 [[N:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -1594,7 +1594,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1702,7 +1702,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l36 -// CHECK4-SAME: (i32 noundef [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [100 x i32]*, align 4 @@ -1714,7 +1714,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], [100 x i32]* nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1824,7 +1824,7 @@ int main (int argc, char **argv) { // // // CHECK5-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1959,7 +1959,7 @@ int main (int argc, char **argv) { // // // CHECK6-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK6-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2094,7 +2094,7 @@ int main (int argc, char **argv) { // // // CHECK7-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2227,7 +2227,7 @@ int main (int argc, char **argv) { // // // CHECK8-LABEL: define {{[^@]+}}@_Z21teams_argument_globali -// CHECK8-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2444,7 +2444,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2460,7 +2460,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2658,7 +2658,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2674,7 +2674,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2871,7 +2871,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -2886,7 +2886,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3082,7 +3082,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -3097,7 +3097,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3517,12 +3517,12 @@ int main (int argc, char **argv) { // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK17-NEXT: ret i32 [[CALL]] // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK17-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK17-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 @@ -3589,7 +3589,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123 -// CHECK17-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK17-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -3599,7 +3599,7 @@ int main (int argc, char **argv) { // // // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3687,12 +3687,12 @@ int main (int argc, char **argv) { // CHECK18-SAME: () #[[ATTR0:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK18-NEXT: ret i32 [[CALL]] // // // CHECK18-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK18-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK18-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 @@ -3759,7 +3759,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123 -// CHECK18-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK18-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -3769,7 +3769,7 @@ int main (int argc, char **argv) { // // // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK18-NEXT: entry: // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3857,12 +3857,12 @@ int main (int argc, char **argv) { // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK19-NEXT: ret i32 [[CALL]] // // // CHECK19-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK19-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK19-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 @@ -3929,7 +3929,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123 -// CHECK19-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK19-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -3939,7 +3939,7 @@ int main (int argc, char **argv) { // // // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK19-NEXT: entry: // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4026,12 +4026,12 @@ int main (int argc, char **argv) { // CHECK20-SAME: () #[[ATTR0:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK20-NEXT: ret i32 [[CALL]] // // // CHECK20-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK20-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK20-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 @@ -4098,7 +4098,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123 -// CHECK20-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK20-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -4108,7 +4108,7 @@ int main (int argc, char **argv) { // // // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK20-NEXT: entry: // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4195,12 +4195,12 @@ int main (int argc, char **argv) { // CHECK21-SAME: () #[[ATTR0:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK21-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK21-NEXT: ret i32 [[CALL]] // // // CHECK21-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK21-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK21-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK21-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 @@ -4267,7 +4267,7 @@ int main (int argc, char **argv) { // // // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123 -// CHECK21-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK21-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -4290,7 +4290,7 @@ int main (int argc, char **argv) { // // // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK21-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK21-NEXT: entry: // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4417,12 +4417,12 @@ int main (int argc, char **argv) { // CHECK22-SAME: () #[[ATTR0:[0-9]+]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK22-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK22-NEXT: ret i32 [[CALL]] // // // CHECK22-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK22-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK22-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK22-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 @@ -4489,7 +4489,7 @@ int main (int argc, char **argv) { // // // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123 -// CHECK22-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK22-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -4512,7 +4512,7 @@ int main (int argc, char **argv) { // // // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK22-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK22-NEXT: entry: // CHECK22-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK22-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4639,12 +4639,12 @@ int main (int argc, char **argv) { // CHECK23-SAME: () #[[ATTR0:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK23-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK23-NEXT: ret i32 [[CALL]] // // // CHECK23-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK23-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK23-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK23-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 @@ -4711,7 +4711,7 @@ int main (int argc, char **argv) { // // // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123 -// CHECK23-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK23-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -4734,7 +4734,7 @@ int main (int argc, char **argv) { // // // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK23-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK23-NEXT: entry: // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4859,12 +4859,12 @@ int main (int argc, char **argv) { // CHECK24-SAME: () #[[ATTR0:[0-9]+]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK24-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK24-NEXT: ret i32 [[CALL]] // // // CHECK24-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK24-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK24-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK24-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 @@ -4931,7 +4931,7 @@ int main (int argc, char **argv) { // // // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l123 -// CHECK24-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK24-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -4954,7 +4954,7 @@ int main (int argc, char **argv) { // // // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { +// CHECK24-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK24-NEXT: entry: // CHECK24-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK24-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5079,12 +5079,12 @@ int main (int argc, char **argv) { // CHECK25-SAME: () #[[ATTR0:[0-9]+]] { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK25-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK25-NEXT: ret i32 [[CALL]] // // // CHECK25-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK25-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK25-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK25-NEXT: entry: // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -5137,12 +5137,12 @@ int main (int argc, char **argv) { // CHECK26-SAME: () #[[ATTR0:[0-9]+]] { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK26-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK26-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK26-NEXT: ret i32 [[CALL]] // // // CHECK26-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK26-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK26-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK26-NEXT: entry: // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -5195,12 +5195,12 @@ int main (int argc, char **argv) { // CHECK27-SAME: () #[[ATTR0:[0-9]+]] { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK27-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK27-NEXT: ret i32 [[CALL]] // // // CHECK27-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK27-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK27-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK27-NEXT: entry: // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -5252,12 +5252,12 @@ int main (int argc, char **argv) { // CHECK28-SAME: () #[[ATTR0:[0-9]+]] { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK28-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK28-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK28-NEXT: ret i32 [[CALL]] // // // CHECK28-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK28-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK28-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK28-NEXT: entry: // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -5309,12 +5309,12 @@ int main (int argc, char **argv) { // CHECK29-SAME: () #[[ATTR0:[0-9]+]] { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK29-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK29-NEXT: ret i32 [[CALL]] // // // CHECK29-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK29-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK29-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK29-NEXT: entry: // CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -5409,12 +5409,12 @@ int main (int argc, char **argv) { // CHECK30-SAME: () #[[ATTR0:[0-9]+]] { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK30-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK30-NEXT: ret i32 [[CALL]] // // // CHECK30-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK30-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK30-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK30-NEXT: entry: // CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -5509,12 +5509,12 @@ int main (int argc, char **argv) { // CHECK31-SAME: () #[[ATTR0:[0-9]+]] { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK31-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK31-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK31-NEXT: ret i32 [[CALL]] // // // CHECK31-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK31-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK31-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK31-NEXT: entry: // CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -5607,12 +5607,12 @@ int main (int argc, char **argv) { // CHECK32-SAME: () #[[ATTR0:[0-9]+]] { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK32-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK32-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK32-NEXT: ret i32 [[CALL]] // // // CHECK32-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK32-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK32-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK32-NEXT: entry: // CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 @@ -5702,7 +5702,7 @@ int main (int argc, char **argv) { // // // CHECK33-LABEL: define {{[^@]+}}@main -// CHECK33-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK33-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -5785,7 +5785,7 @@ int main (int argc, char **argv) { // CHECK33-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK33: omp_offload.cont: // CHECK33-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK33-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP33]]) +// CHECK33-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP33]]) // CHECK33-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK33-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK33-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) @@ -5794,7 +5794,7 @@ int main (int argc, char **argv) { // // // CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192 -// CHECK33-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK33-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK33-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -5810,7 +5810,7 @@ int main (int argc, char **argv) { // // // CHECK33-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK33-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5917,7 +5917,7 @@ int main (int argc, char **argv) { // // // CHECK33-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK33-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK33-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK33-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -5979,7 +5979,7 @@ int main (int argc, char **argv) { // // // CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181 -// CHECK33-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK33-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK33-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -5999,7 +5999,7 @@ int main (int argc, char **argv) { // // // CHECK33-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK33-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK33-NEXT: entry: // CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6080,7 +6080,7 @@ int main (int argc, char **argv) { // // // CHECK34-LABEL: define {{[^@]+}}@main -// CHECK34-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK34-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK34-NEXT: entry: // CHECK34-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -6163,7 +6163,7 @@ int main (int argc, char **argv) { // CHECK34-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK34: omp_offload.cont: // CHECK34-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK34-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP33]]) +// CHECK34-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP33]]) // CHECK34-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK34-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK34-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) @@ -6172,7 +6172,7 @@ int main (int argc, char **argv) { // // // CHECK34-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192 -// CHECK34-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK34-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK34-NEXT: entry: // CHECK34-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK34-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -6188,7 +6188,7 @@ int main (int argc, char **argv) { // // // CHECK34-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK34-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK34-NEXT: entry: // CHECK34-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK34-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6295,7 +6295,7 @@ int main (int argc, char **argv) { // // // CHECK34-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK34-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK34-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK34-NEXT: entry: // CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK34-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -6357,7 +6357,7 @@ int main (int argc, char **argv) { // // // CHECK34-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181 -// CHECK34-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK34-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK34-NEXT: entry: // CHECK34-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK34-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -6377,7 +6377,7 @@ int main (int argc, char **argv) { // // // CHECK34-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK34-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK34-NEXT: entry: // CHECK34-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK34-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -6458,7 +6458,7 @@ int main (int argc, char **argv) { // // // CHECK35-LABEL: define {{[^@]+}}@main -// CHECK35-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK35-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -6540,7 +6540,7 @@ int main (int argc, char **argv) { // CHECK35-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK35: omp_offload.cont: // CHECK35-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK35-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP33]]) +// CHECK35-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP33]]) // CHECK35-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK35-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK35-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) @@ -6549,7 +6549,7 @@ int main (int argc, char **argv) { // // // CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192 -// CHECK35-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK35-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK35-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -6564,7 +6564,7 @@ int main (int argc, char **argv) { // // // CHECK35-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK35-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK35-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK35-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6670,7 +6670,7 @@ int main (int argc, char **argv) { // // // CHECK35-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK35-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK35-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK35-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -6730,7 +6730,7 @@ int main (int argc, char **argv) { // // // CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181 -// CHECK35-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK35-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK35-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -6748,7 +6748,7 @@ int main (int argc, char **argv) { // // // CHECK35-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK35-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK35-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK35-NEXT: entry: // CHECK35-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK35-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -6828,7 +6828,7 @@ int main (int argc, char **argv) { // // // CHECK36-LABEL: define {{[^@]+}}@main -// CHECK36-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK36-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK36-NEXT: entry: // CHECK36-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -6910,7 +6910,7 @@ int main (int argc, char **argv) { // CHECK36-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK36: omp_offload.cont: // CHECK36-NEXT: [[TMP33:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK36-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP33]]) +// CHECK36-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP33]]) // CHECK36-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK36-NEXT: [[TMP34:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK36-NEXT: call void @llvm.stackrestore(i8* [[TMP34]]) @@ -6919,7 +6919,7 @@ int main (int argc, char **argv) { // // // CHECK36-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192 -// CHECK36-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK36-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK36-NEXT: entry: // CHECK36-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK36-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -6934,7 +6934,7 @@ int main (int argc, char **argv) { // // // CHECK36-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK36-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK36-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK36-NEXT: entry: // CHECK36-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK36-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7040,7 +7040,7 @@ int main (int argc, char **argv) { // // // CHECK36-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK36-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK36-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK36-NEXT: entry: // CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK36-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -7100,7 +7100,7 @@ int main (int argc, char **argv) { // // // CHECK36-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181 -// CHECK36-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK36-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK36-NEXT: entry: // CHECK36-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK36-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -7118,7 +7118,7 @@ int main (int argc, char **argv) { // // // CHECK36-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK36-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK36-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK36-NEXT: entry: // CHECK36-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK36-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -7198,7 +7198,7 @@ int main (int argc, char **argv) { // // // CHECK37-LABEL: define {{[^@]+}}@main -// CHECK37-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK37-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK37-NEXT: entry: // CHECK37-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK37-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -7296,7 +7296,7 @@ int main (int argc, char **argv) { // CHECK37-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK37: omp_offload.cont: // CHECK37-NEXT: [[TMP41:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK37-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP41]]) +// CHECK37-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP41]]) // CHECK37-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK37-NEXT: [[TMP42:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK37-NEXT: call void @llvm.stackrestore(i8* [[TMP42]]) @@ -7305,7 +7305,7 @@ int main (int argc, char **argv) { // // // CHECK37-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192 -// CHECK37-SAME: (i64 noundef [[ARGC:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK37-SAME: (i64 [[ARGC:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK37-NEXT: entry: // CHECK37-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK37-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -7336,7 +7336,7 @@ int main (int argc, char **argv) { // // // CHECK37-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK37-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK37-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK37-NEXT: entry: // CHECK37-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK37-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7478,7 +7478,7 @@ int main (int argc, char **argv) { // // // CHECK37-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK37-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK37-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK37-NEXT: entry: // CHECK37-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK37-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -7540,7 +7540,7 @@ int main (int argc, char **argv) { // // // CHECK37-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181 -// CHECK37-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK37-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK37-NEXT: entry: // CHECK37-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK37-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -7560,7 +7560,7 @@ int main (int argc, char **argv) { // // // CHECK37-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK37-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK37-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK37-NEXT: entry: // CHECK37-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK37-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7641,7 +7641,7 @@ int main (int argc, char **argv) { // // // CHECK38-LABEL: define {{[^@]+}}@main -// CHECK38-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK38-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK38-NEXT: entry: // CHECK38-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK38-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -7739,7 +7739,7 @@ int main (int argc, char **argv) { // CHECK38-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK38: omp_offload.cont: // CHECK38-NEXT: [[TMP41:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK38-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP41]]) +// CHECK38-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP41]]) // CHECK38-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK38-NEXT: [[TMP42:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK38-NEXT: call void @llvm.stackrestore(i8* [[TMP42]]) @@ -7748,7 +7748,7 @@ int main (int argc, char **argv) { // // // CHECK38-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192 -// CHECK38-SAME: (i64 noundef [[ARGC:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK38-SAME: (i64 [[ARGC:%.*]], i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK38-NEXT: entry: // CHECK38-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK38-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 @@ -7779,7 +7779,7 @@ int main (int argc, char **argv) { // // // CHECK38-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK38-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK38-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK38-NEXT: entry: // CHECK38-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK38-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -7921,7 +7921,7 @@ int main (int argc, char **argv) { // // // CHECK38-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK38-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK38-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK38-NEXT: entry: // CHECK38-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK38-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -7983,7 +7983,7 @@ int main (int argc, char **argv) { // // // CHECK38-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181 -// CHECK38-SAME: (i64 noundef [[TE:%.*]], i64 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK38-SAME: (i64 [[TE:%.*]], i64 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK38-NEXT: entry: // CHECK38-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK38-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 @@ -8003,7 +8003,7 @@ int main (int argc, char **argv) { // // // CHECK38-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK38-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK38-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK38-NEXT: entry: // CHECK38-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK38-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -8084,7 +8084,7 @@ int main (int argc, char **argv) { // // // CHECK39-LABEL: define {{[^@]+}}@main -// CHECK39-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK39-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK39-NEXT: entry: // CHECK39-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK39-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -8180,7 +8180,7 @@ int main (int argc, char **argv) { // CHECK39-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK39: omp_offload.cont: // CHECK39-NEXT: [[TMP41:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK39-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP41]]) +// CHECK39-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP41]]) // CHECK39-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK39-NEXT: [[TMP42:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK39-NEXT: call void @llvm.stackrestore(i8* [[TMP42]]) @@ -8189,7 +8189,7 @@ int main (int argc, char **argv) { // // // CHECK39-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192 -// CHECK39-SAME: (i32 noundef [[ARGC:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK39-SAME: (i32 [[ARGC:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK39-NEXT: entry: // CHECK39-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK39-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -8218,7 +8218,7 @@ int main (int argc, char **argv) { // // // CHECK39-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK39-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK39-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK39-NEXT: entry: // CHECK39-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK39-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8358,7 +8358,7 @@ int main (int argc, char **argv) { // // // CHECK39-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK39-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK39-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK39-NEXT: entry: // CHECK39-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK39-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -8418,7 +8418,7 @@ int main (int argc, char **argv) { // // // CHECK39-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181 -// CHECK39-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK39-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK39-NEXT: entry: // CHECK39-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK39-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -8436,7 +8436,7 @@ int main (int argc, char **argv) { // // // CHECK39-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK39-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK39-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK39-NEXT: entry: // CHECK39-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK39-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8516,7 +8516,7 @@ int main (int argc, char **argv) { // // // CHECK40-LABEL: define {{[^@]+}}@main -// CHECK40-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK40-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK40-NEXT: entry: // CHECK40-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK40-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -8612,7 +8612,7 @@ int main (int argc, char **argv) { // CHECK40-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK40: omp_offload.cont: // CHECK40-NEXT: [[TMP41:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK40-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP41]]) +// CHECK40-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP41]]) // CHECK40-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK40-NEXT: [[TMP42:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK40-NEXT: call void @llvm.stackrestore(i8* [[TMP42]]) @@ -8621,7 +8621,7 @@ int main (int argc, char **argv) { // // // CHECK40-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192 -// CHECK40-SAME: (i32 noundef [[ARGC:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK40-SAME: (i32 [[ARGC:%.*]], i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK40-NEXT: entry: // CHECK40-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK40-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 @@ -8650,7 +8650,7 @@ int main (int argc, char **argv) { // // // CHECK40-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK40-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK40-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK40-NEXT: entry: // CHECK40-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK40-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8790,7 +8790,7 @@ int main (int argc, char **argv) { // // // CHECK40-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK40-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK40-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK40-NEXT: entry: // CHECK40-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK40-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -8850,7 +8850,7 @@ int main (int argc, char **argv) { // // // CHECK40-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l181 -// CHECK40-SAME: (i32 noundef [[TE:%.*]], i32 noundef [[TH:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK40-SAME: (i32 [[TE:%.*]], i32 [[TH:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK40-NEXT: entry: // CHECK40-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK40-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 @@ -8868,7 +8868,7 @@ int main (int argc, char **argv) { // // // CHECK40-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK40-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK40-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK40-NEXT: entry: // CHECK40-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK40-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -8948,7 +8948,7 @@ int main (int argc, char **argv) { // // // CHECK41-LABEL: define {{[^@]+}}@main -// CHECK41-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK41-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK41-NEXT: entry: // CHECK41-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK41-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -9024,7 +9024,7 @@ int main (int argc, char **argv) { // CHECK41-NEXT: br label [[SIMD_IF_END]] // CHECK41: simd.if.end: // CHECK41-NEXT: [[TMP14:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK41-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP14]]) +// CHECK41-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP14]]) // CHECK41-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK41-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK41-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) @@ -9033,7 +9033,7 @@ int main (int argc, char **argv) { // // // CHECK41-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK41-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK41-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK41-NEXT: entry: // CHECK41-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK41-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -9080,7 +9080,7 @@ int main (int argc, char **argv) { // // // CHECK42-LABEL: define {{[^@]+}}@main -// CHECK42-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK42-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK42-NEXT: entry: // CHECK42-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK42-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -9156,7 +9156,7 @@ int main (int argc, char **argv) { // CHECK42-NEXT: br label [[SIMD_IF_END]] // CHECK42: simd.if.end: // CHECK42-NEXT: [[TMP14:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK42-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP14]]) +// CHECK42-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP14]]) // CHECK42-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK42-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK42-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) @@ -9165,7 +9165,7 @@ int main (int argc, char **argv) { // // // CHECK42-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK42-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK42-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK42-NEXT: entry: // CHECK42-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK42-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -9212,7 +9212,7 @@ int main (int argc, char **argv) { // // // CHECK43-LABEL: define {{[^@]+}}@main -// CHECK43-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK43-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK43-NEXT: entry: // CHECK43-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK43-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -9286,7 +9286,7 @@ int main (int argc, char **argv) { // CHECK43-NEXT: br label [[SIMD_IF_END]] // CHECK43: simd.if.end: // CHECK43-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK43-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP13]]) +// CHECK43-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP13]]) // CHECK43-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK43-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK43-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) @@ -9295,7 +9295,7 @@ int main (int argc, char **argv) { // // // CHECK43-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK43-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK43-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK43-NEXT: entry: // CHECK43-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK43-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -9341,7 +9341,7 @@ int main (int argc, char **argv) { // // // CHECK44-LABEL: define {{[^@]+}}@main -// CHECK44-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK44-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK44-NEXT: entry: // CHECK44-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK44-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -9415,7 +9415,7 @@ int main (int argc, char **argv) { // CHECK44-NEXT: br label [[SIMD_IF_END]] // CHECK44: simd.if.end: // CHECK44-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK44-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP13]]) +// CHECK44-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP13]]) // CHECK44-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK44-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK44-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) @@ -9424,7 +9424,7 @@ int main (int argc, char **argv) { // // // CHECK44-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK44-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK44-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK44-NEXT: entry: // CHECK44-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK44-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -9470,7 +9470,7 @@ int main (int argc, char **argv) { // // // CHECK45-LABEL: define {{[^@]+}}@main -// CHECK45-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK45-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK45-NEXT: entry: // CHECK45-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK45-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -9583,7 +9583,7 @@ int main (int argc, char **argv) { // CHECK45-NEXT: br label [[SIMD_IF_END]] // CHECK45: simd.if.end: // CHECK45-NEXT: [[TMP21:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK45-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP21]]) +// CHECK45-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP21]]) // CHECK45-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK45-NEXT: [[TMP22:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK45-NEXT: call void @llvm.stackrestore(i8* [[TMP22]]) @@ -9592,7 +9592,7 @@ int main (int argc, char **argv) { // // // CHECK45-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK45-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK45-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK45-NEXT: entry: // CHECK45-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK45-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -9639,7 +9639,7 @@ int main (int argc, char **argv) { // // // CHECK46-LABEL: define {{[^@]+}}@main -// CHECK46-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK46-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK46-NEXT: entry: // CHECK46-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK46-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -9752,7 +9752,7 @@ int main (int argc, char **argv) { // CHECK46-NEXT: br label [[SIMD_IF_END]] // CHECK46: simd.if.end: // CHECK46-NEXT: [[TMP21:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK46-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP21]]) +// CHECK46-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP21]]) // CHECK46-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK46-NEXT: [[TMP22:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK46-NEXT: call void @llvm.stackrestore(i8* [[TMP22]]) @@ -9761,7 +9761,7 @@ int main (int argc, char **argv) { // // // CHECK46-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK46-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK46-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK46-NEXT: entry: // CHECK46-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK46-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -9808,7 +9808,7 @@ int main (int argc, char **argv) { // // // CHECK47-LABEL: define {{[^@]+}}@main -// CHECK47-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK47-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK47-NEXT: entry: // CHECK47-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK47-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -9918,7 +9918,7 @@ int main (int argc, char **argv) { // CHECK47-NEXT: br label [[SIMD_IF_END]] // CHECK47: simd.if.end: // CHECK47-NEXT: [[TMP20:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK47-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP20]]) +// CHECK47-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP20]]) // CHECK47-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK47-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK47-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) @@ -9927,7 +9927,7 @@ int main (int argc, char **argv) { // // // CHECK47-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK47-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK47-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK47-NEXT: entry: // CHECK47-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK47-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -9973,7 +9973,7 @@ int main (int argc, char **argv) { // // // CHECK48-LABEL: define {{[^@]+}}@main -// CHECK48-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK48-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK48-NEXT: entry: // CHECK48-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK48-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -10083,7 +10083,7 @@ int main (int argc, char **argv) { // CHECK48-NEXT: br label [[SIMD_IF_END]] // CHECK48: simd.if.end: // CHECK48-NEXT: [[TMP20:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK48-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP20]]) +// CHECK48-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP20]]) // CHECK48-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK48-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK48-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) @@ -10092,7 +10092,7 @@ int main (int argc, char **argv) { // // // CHECK48-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK48-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK48-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK48-NEXT: entry: // CHECK48-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK48-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 diff --git a/clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp index 22c78b045a76d5445f25e55e5cdd656f3ee8d4f2..93f678abb6727e49bad625e63464f67831d364ed 100644 --- a/clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp @@ -102,12 +102,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -144,7 +144,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -154,7 +154,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -194,40 +194,40 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK1-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] -// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -254,12 +254,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -296,7 +296,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -306,7 +306,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -346,40 +346,40 @@ int main (int argc, char **argv) { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK2-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 // CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] -// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -406,12 +406,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -448,7 +448,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -458,7 +458,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -498,38 +498,38 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]] -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] -// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -556,12 +556,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -598,7 +598,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -608,7 +608,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -648,38 +648,38 @@ int main (int argc, char **argv) { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] // CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]] -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] -// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -706,12 +706,12 @@ int main (int argc, char **argv) { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -777,12 +777,12 @@ int main (int argc, char **argv) { // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -848,12 +848,12 @@ int main (int argc, char **argv) { // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -917,12 +917,12 @@ int main (int argc, char **argv) { // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(224352) [[V]]) // CHECK8-NEXT: ret i32 [[CALL]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -983,7 +983,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1108,7 +1108,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -1117,7 +1117,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -1139,7 +1139,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1224,13 +1224,13 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 // CHECK9-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 // CHECK9-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] @@ -1239,16 +1239,16 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] // CHECK9-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK9-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 +// CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK9-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 // CHECK9-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 // CHECK9-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] // CHECK9-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 // CHECK9-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 // CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 // CHECK9-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] @@ -1258,23 +1258,23 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 // CHECK9-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] // CHECK9-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 -// CHECK9-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 +// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 // CHECK9-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP28]] -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 // CHECK9-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64 // CHECK9-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK9-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK9-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK9-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1305,7 +1305,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -1337,7 +1337,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 -// CHECK9-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -1347,7 +1347,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1387,39 +1387,39 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 // CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] // CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK9-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] -// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1443,7 +1443,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -1568,7 +1568,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: // CHECK10-NEXT: [[TMP52:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP52]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP52]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) @@ -1577,7 +1577,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 @@ -1599,7 +1599,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1684,13 +1684,13 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK10-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK10-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 // CHECK10-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 // CHECK10-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] @@ -1699,16 +1699,16 @@ int main (int argc, char **argv) { // CHECK10-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] // CHECK10-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK10-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 +// CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK10-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 // CHECK10-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 // CHECK10-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] // CHECK10-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 // CHECK10-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] -// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK10-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 // CHECK10-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 // CHECK10-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] @@ -1718,23 +1718,23 @@ int main (int argc, char **argv) { // CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 // CHECK10-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] // CHECK10-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 -// CHECK10-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 +// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 // CHECK10-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP28]] -// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 // CHECK10-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64 // CHECK10-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK10-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK10-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK10-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -1765,7 +1765,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -1797,7 +1797,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 -// CHECK10-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 @@ -1807,7 +1807,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1847,39 +1847,39 @@ int main (int argc, char **argv) { // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 // CHECK10-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] // CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK10-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 // CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] -// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -1903,7 +1903,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2025,7 +2025,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -2034,7 +2034,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -2054,7 +2054,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2139,13 +2139,13 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 // CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 // CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] @@ -2154,16 +2154,16 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] // CHECK11-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK11-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 +// CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK11-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 // CHECK11-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 // CHECK11-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] // CHECK11-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 // CHECK11-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] -// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 // CHECK11-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 // CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] @@ -2173,21 +2173,21 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 // CHECK11-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] // CHECK11-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 -// CHECK11-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 // CHECK11-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]] // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP28]] -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 // CHECK11-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK11-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK11-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK11-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -2218,7 +2218,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -2250,7 +2250,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 -// CHECK11-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -2260,7 +2260,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2300,37 +2300,37 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] -// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -2354,7 +2354,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2476,7 +2476,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: // CHECK12-NEXT: [[TMP51:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP51]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP51]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP52:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP52]]) @@ -2485,7 +2485,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 @@ -2505,7 +2505,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32* nonnull align 4 dereferenceable(4) [[M:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2590,13 +2590,13 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 // CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK12-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 // CHECK12-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 // CHECK12-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] @@ -2605,16 +2605,16 @@ int main (int argc, char **argv) { // CHECK12-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] // CHECK12-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK12-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 +// CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK12-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 // CHECK12-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 // CHECK12-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] // CHECK12-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 // CHECK12-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] -// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 // CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 // CHECK12-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 // CHECK12-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] @@ -2624,21 +2624,21 @@ int main (int argc, char **argv) { // CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 // CHECK12-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] // CHECK12-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 -// CHECK12-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 +// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4 // CHECK12-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]] // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP28]] -// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4 // CHECK12-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 // CHECK12-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1 -// CHECK12-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK12-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -2669,7 +2669,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -2701,7 +2701,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 -// CHECK12-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 @@ -2711,7 +2711,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2751,37 +2751,37 @@ int main (int argc, char **argv) { // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 // CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] // CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] -// CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] -// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -2805,7 +2805,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2941,7 +2941,7 @@ int main (int argc, char **argv) { // CHECK13-NEXT: br label [[SIMD_IF_END]] // CHECK13: simd.if.end: // CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP28]]) // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) @@ -2950,7 +2950,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -3008,7 +3008,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3144,7 +3144,7 @@ int main (int argc, char **argv) { // CHECK14-NEXT: br label [[SIMD_IF_END]] // CHECK14: simd.if.end: // CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 signext [[TMP28]]) // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) @@ -3153,7 +3153,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -3211,7 +3211,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3343,7 +3343,7 @@ int main (int argc, char **argv) { // CHECK15-NEXT: br label [[SIMD_IF_END]] // CHECK15: simd.if.end: // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP26]]) // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP27]]) @@ -3352,7 +3352,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 @@ -3408,7 +3408,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3540,7 +3540,7 @@ int main (int argc, char **argv) { // CHECK16-NEXT: br label [[SIMD_IF_END]] // CHECK16: simd.if.end: // CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10ELi2EEiT_(i32 [[TMP26]]) // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP27]]) @@ -3549,7 +3549,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 diff --git a/clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp index 335f7ad8d5ffb874b180e844bdb493cff4702cda..fbf312e5e312638fd6905e21f5812c34988679fb 100644 --- a/clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp @@ -135,12 +135,12 @@ int main (int argc, char **argv) { // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -221,7 +221,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -231,7 +231,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -306,7 +306,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -316,7 +316,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -391,7 +391,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -401,7 +401,7 @@ int main (int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -503,12 +503,12 @@ int main (int argc, char **argv) { // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -589,7 +589,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -599,7 +599,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -674,7 +674,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -684,7 +684,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -759,7 +759,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -769,7 +769,7 @@ int main (int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -871,12 +871,12 @@ int main (int argc, char **argv) { // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -957,7 +957,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -967,7 +967,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1041,7 +1041,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1051,7 +1051,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1125,7 +1125,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1135,7 +1135,7 @@ int main (int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1236,12 +1236,12 @@ int main (int argc, char **argv) { // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -1322,7 +1322,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1332,7 +1332,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1406,7 +1406,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l33 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1416,7 +1416,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1490,7 +1490,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l38 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -1500,7 +1500,7 @@ int main (int argc, char **argv) { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1601,12 +1601,12 @@ int main (int argc, char **argv) { // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK5-NEXT: ret i32 [[CALL]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK5-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK5-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1726,12 +1726,12 @@ int main (int argc, char **argv) { // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK6-NEXT: ret i32 [[CALL]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK6-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK6-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1851,12 +1851,12 @@ int main (int argc, char **argv) { // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK7-NEXT: ret i32 [[CALL]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK7-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK7-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1973,12 +1973,12 @@ int main (int argc, char **argv) { // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef [[V]]) +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull align 4 dereferenceable(496) [[V]]) // CHECK8-NEXT: ret i32 [[CALL]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv -// CHECK8-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK8-SAME: (%struct.SS* nonnull align 4 dereferenceable(496) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -2092,7 +2092,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@main -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -2303,7 +2303,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT32]] // CHECK9: omp_offload.cont32: // CHECK9-NEXT: [[TMP93:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP93]]) +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP93]]) // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP94:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP94]]) @@ -2312,7 +2312,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2328,7 +2328,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2435,7 +2435,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2451,7 +2451,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2558,7 +2558,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -2582,7 +2582,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2710,7 +2710,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK9-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -2785,7 +2785,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -2795,7 +2795,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2869,7 +2869,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -2879,7 +2879,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2953,7 +2953,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK9-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK9-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -2963,7 +2963,7 @@ int main (int argc, char **argv) { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3061,7 +3061,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@main -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -3272,7 +3272,7 @@ int main (int argc, char **argv) { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT32]] // CHECK10: omp_offload.cont32: // CHECK10-NEXT: [[TMP93:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP93]]) +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP93]]) // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[TMP94:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP94]]) @@ -3281,7 +3281,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -3297,7 +3297,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3404,7 +3404,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -3420,7 +3420,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3527,7 +3527,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i64 [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 @@ -3551,7 +3551,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3679,7 +3679,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK10-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -3754,7 +3754,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3764,7 +3764,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3838,7 +3838,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3848,7 +3848,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3922,7 +3922,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK10-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 8 // CHECK10-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 8 @@ -3932,7 +3932,7 @@ int main (int argc, char **argv) { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4030,7 +4030,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@main -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK11-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -4240,7 +4240,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT30]] // CHECK11: omp_offload.cont30: // CHECK11-NEXT: [[TMP95:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP95]]) +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP95]]) // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP96:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP96]]) @@ -4249,7 +4249,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -4264,7 +4264,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4370,7 +4370,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -4385,7 +4385,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4491,7 +4491,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -4513,7 +4513,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4639,7 +4639,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK11-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -4714,7 +4714,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -4724,7 +4724,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4797,7 +4797,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -4807,7 +4807,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4880,7 +4880,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK11-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK11-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -4890,7 +4890,7 @@ int main (int argc, char **argv) { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -4987,7 +4987,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@main -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK12-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -5197,7 +5197,7 @@ int main (int argc, char **argv) { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT30]] // CHECK12: omp_offload.cont30: // CHECK12-NEXT: [[TMP95:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP95]]) +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP95]]) // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[TMP96:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP96]]) @@ -5206,7 +5206,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -5221,7 +5221,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5327,7 +5327,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l105 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -5342,7 +5342,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5448,7 +5448,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110 -// CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32 [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 @@ -5470,7 +5470,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5596,7 +5596,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { +// CHECK12-SAME: (i32 [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -5671,7 +5671,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l79 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -5681,7 +5681,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5754,7 +5754,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l84 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -5764,7 +5764,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5837,7 +5837,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l89 -// CHECK12-SAME: ([10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: ([10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x i32]*, align 4 // CHECK12-NEXT: store [10 x i32]* [[A]], [10 x i32]** [[A_ADDR]], align 4 @@ -5847,7 +5847,7 @@ int main (int argc, char **argv) { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -5944,7 +5944,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@main -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -6137,7 +6137,7 @@ int main (int argc, char **argv) { // CHECK13-NEXT: br label [[SIMD_IF_END68]] // CHECK13: simd.if.end68: // CHECK13-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]]) +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP37]]) // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP38:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP38]]) @@ -6146,7 +6146,7 @@ int main (int argc, char **argv) { // // // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK13-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -6257,7 +6257,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@main -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -6450,7 +6450,7 @@ int main (int argc, char **argv) { // CHECK14-NEXT: br label [[SIMD_IF_END68]] // CHECK14: simd.if.end68: // CHECK14-NEXT: [[TMP37:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]]) +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiLi10EEiT_(i32 signext [[TMP37]]) // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[TMP38:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP38]]) @@ -6459,7 +6459,7 @@ int main (int argc, char **argv) { // // // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK14-SAME: (i32 signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -6570,7 +6570,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@main -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK15-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -6759,7 +6759,7 @@ int main (int argc, char **argv) { // CHECK15-NEXT: br label [[SIMD_IF_END66]] // CHECK15: simd.if.end66: // CHECK15-NEXT: [[TMP36:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]]) +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP36]]) // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP37:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP37]]) @@ -6768,7 +6768,7 @@ int main (int argc, char **argv) { // // // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK15-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 @@ -6876,7 +6876,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@main -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK16-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 @@ -7065,7 +7065,7 @@ int main (int argc, char **argv) { // CHECK16-NEXT: br label [[SIMD_IF_END66]] // CHECK16: simd.if.end66: // CHECK16-NEXT: [[TMP36:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]]) +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiLi10EEiT_(i32 [[TMP36]]) // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[TMP37:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP37]]) @@ -7074,7 +7074,7 @@ int main (int argc, char **argv) { // // // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ -// CHECK16-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { +// CHECK16-SAME: (i32 [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x i32], align 4 diff --git a/clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp index 194c774806e994f0f65a337bcfc5f6845206a723..9f432be90370ad0bc10bf1f50f0ba304c2f87618 100644 --- a/clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp @@ -145,33 +145,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -184,7 +184,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -195,14 +195,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -210,12 +210,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -223,7 +223,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -231,7 +231,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -250,7 +250,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -324,12 +324,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -361,7 +361,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -409,17 +409,17 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -438,40 +438,40 @@ int main() { // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5 -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5 +// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] -// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8, !llvm.access.group !5 +// CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -485,14 +485,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -500,17 +500,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -518,17 +518,17 @@ int main() { // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -547,14 +547,14 @@ int main() { // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -614,17 +614,17 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP32]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -637,7 +637,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -657,7 +657,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -666,17 +666,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -684,12 +684,12 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -716,7 +716,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -764,18 +764,18 @@ int main() { // CHECK1: omp.arraycpy.body: // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK1: omp.arraycpy.done4: // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -795,37 +795,37 @@ int main() { // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !11 +// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -839,14 +839,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -854,7 +854,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -862,22 +862,22 @@ int main() { // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -889,7 +889,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -905,7 +905,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -924,7 +924,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -951,33 +951,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -990,7 +990,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1001,14 +1001,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1016,12 +1016,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1029,7 +1029,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1037,7 +1037,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1056,7 +1056,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -1130,12 +1130,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK2-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1167,7 +1167,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1215,17 +1215,17 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1244,40 +1244,40 @@ int main() { // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK2-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5 -// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8, !llvm.access.group !5 +// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) +// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] -// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8, !llvm.access.group !5 +// CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1291,14 +1291,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done13: @@ -1306,17 +1306,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1324,17 +1324,17 @@ int main() { // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // @@ -1353,14 +1353,14 @@ int main() { // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1420,17 +1420,17 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP32]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1443,7 +1443,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 @@ -1463,7 +1463,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 @@ -1472,17 +1472,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1490,12 +1490,12 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK2-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1522,7 +1522,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1570,18 +1570,18 @@ int main() { // CHECK2: omp.arraycpy.body: // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK2: omp.arraycpy.done4: // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK2-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -1601,37 +1601,37 @@ int main() { // CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] // CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* // CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !11 +// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1645,14 +1645,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done13: @@ -1660,7 +1660,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1668,22 +1668,22 @@ int main() { // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1695,7 +1695,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1711,7 +1711,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 @@ -1730,7 +1730,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1757,33 +1757,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1796,7 +1796,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1807,14 +1807,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1822,12 +1822,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1835,7 +1835,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1843,7 +1843,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1862,7 +1862,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -1934,12 +1934,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -1967,7 +1967,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2013,17 +2013,17 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done3: -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2042,38 +2042,38 @@ int main() { // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP16]] -// CHECK3-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP17]] // CHECK3-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* // CHECK3-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !6 -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) +// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] -// CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2087,14 +2087,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -2102,17 +2102,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2120,17 +2120,17 @@ int main() { // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -2149,14 +2149,14 @@ int main() { // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2215,17 +2215,17 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP32]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2238,7 +2238,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2258,7 +2258,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -2267,17 +2267,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2285,12 +2285,12 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2315,7 +2315,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2362,18 +2362,18 @@ int main() { // CHECK3: omp.arraycpy.body: // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK3: omp.arraycpy.done4: // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -2393,35 +2393,35 @@ int main() { // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP17]] -// CHECK3-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP19]] // CHECK3-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* // CHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !12 +// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -2435,14 +2435,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -2450,7 +2450,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -2458,22 +2458,22 @@ int main() { // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2485,7 +2485,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2501,7 +2501,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -2520,7 +2520,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2547,33 +2547,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2586,7 +2586,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2597,14 +2597,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2612,12 +2612,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -2625,7 +2625,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -2633,7 +2633,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2652,7 +2652,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -2724,12 +2724,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 -// CHECK4-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2757,7 +2757,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2803,17 +2803,17 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done3: -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2832,38 +2832,38 @@ int main() { // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP16]] -// CHECK4-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP17]] // CHECK4-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* // CHECK4-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR4]] to i8* -// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !6 -// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) +// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] -// CHECK4-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2877,14 +2877,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done11: @@ -2892,17 +2892,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -2910,17 +2910,17 @@ int main() { // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // @@ -2939,14 +2939,14 @@ int main() { // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3005,17 +3005,17 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP32]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -3028,7 +3028,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 @@ -3048,7 +3048,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 @@ -3057,17 +3057,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3075,12 +3075,12 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 -// CHECK4-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3105,7 +3105,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3152,18 +3152,18 @@ int main() { // CHECK4: omp.arraycpy.body: // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK4: omp.arraycpy.done4: // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) -// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) +// CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 @@ -3183,35 +3183,35 @@ int main() { // CHECK4-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP17]] -// CHECK4-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP19]] // CHECK4-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* // CHECK4-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* -// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !12 +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -3225,14 +3225,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done12: @@ -3240,7 +3240,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3248,22 +3248,22 @@ int main() { // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3275,7 +3275,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3291,7 +3291,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 @@ -3310,7 +3310,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3337,42 +3337,42 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3380,12 +3380,12 @@ int main() { // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3393,7 +3393,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -3403,7 +3403,7 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // @@ -3457,7 +3457,7 @@ int main() { // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK5-NEXT: ret i32 [[CALL]] // // @@ -3477,14 +3477,14 @@ int main() { // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -3535,17 +3535,17 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done6: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP16]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3558,7 +3558,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3567,7 +3567,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3584,17 +3584,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3602,22 +3602,22 @@ int main() { // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3629,7 +3629,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3645,7 +3645,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3665,42 +3665,42 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3708,12 +3708,12 @@ int main() { // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3721,7 +3721,7 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: @@ -3731,7 +3731,7 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // @@ -3785,7 +3785,7 @@ int main() { // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK6-NEXT: ret i32 [[CALL]] // // @@ -3805,14 +3805,14 @@ int main() { // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -3863,17 +3863,17 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done6: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP16]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3886,7 +3886,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3895,7 +3895,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3912,17 +3912,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3930,22 +3930,22 @@ int main() { // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3957,7 +3957,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3973,7 +3973,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -3993,42 +3993,42 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4036,12 +4036,12 @@ int main() { // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -4049,7 +4049,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -4059,7 +4059,7 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // @@ -4111,7 +4111,7 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK7-NEXT: ret i32 [[CALL]] // // @@ -4131,14 +4131,14 @@ int main() { // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4187,17 +4187,17 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done5: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP16]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4210,7 +4210,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4219,7 +4219,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4236,17 +4236,17 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4254,22 +4254,22 @@ int main() { // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4281,7 +4281,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4297,7 +4297,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4317,42 +4317,42 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4360,12 +4360,12 @@ int main() { // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -4373,7 +4373,7 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done1: @@ -4383,7 +4383,7 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // @@ -4435,7 +4435,7 @@ int main() { // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK8-NEXT: ret i32 [[CALL]] // // @@ -4455,14 +4455,14 @@ int main() { // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4511,17 +4511,17 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done5: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP16]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4534,7 +4534,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4543,7 +4543,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4560,17 +4560,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4578,22 +4578,22 @@ int main() { // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4605,7 +4605,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4621,7 +4621,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4641,33 +4641,33 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4680,7 +4680,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4691,14 +4691,14 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4706,12 +4706,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4719,7 +4719,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -4727,7 +4727,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4746,7 +4746,7 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // @@ -4757,12 +4757,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 @@ -4796,7 +4796,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4843,35 +4843,35 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !4 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 +// CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4 +// CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4905,33 +4905,33 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4944,7 +4944,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4955,14 +4955,14 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4970,12 +4970,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4983,7 +4983,7 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: @@ -4991,7 +4991,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5010,7 +5010,7 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // @@ -5021,12 +5021,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK10-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK10-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 @@ -5060,7 +5060,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -5107,35 +5107,35 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8, !llvm.access.group !4 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 +// CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4 +// CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 +// CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -5169,42 +5169,42 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5212,12 +5212,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -5225,7 +5225,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -5235,7 +5235,7 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // @@ -5246,12 +5246,12 @@ int main() { // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: ret i32 0 // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5264,7 +5264,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5273,7 +5273,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5301,42 +5301,42 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5344,12 +5344,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -5357,7 +5357,7 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done1: @@ -5367,7 +5367,7 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // @@ -5378,12 +5378,12 @@ int main() { // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK12-NEXT: ret i32 0 // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5396,7 +5396,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -5405,7 +5405,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 diff --git a/clang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp index a3c9a1daed04ee71ba10ecf1c5beb99fb9dc1cf5..05a9b64a8bdcdaebb7a5fa4dbf9ff3ed6aee5b69 100644 --- a/clang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp @@ -151,12 +151,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -178,7 +178,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -235,38 +235,38 @@ int main() { // CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP4]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: store double 1.000000e+00, double* [[G2]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP4]], align 8 +// CHECK1-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 8 +// CHECK1-NEXT: store i32 3, i32* [[SVAR5]], align 4 +// CHECK1-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK1-NEXT: store double* [[G2]], double** [[TMP14]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: store double* [[G2]], double** [[TMP14]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: store double* [[TMP16]], double** [[TMP15]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 8 +// CHECK1-NEXT: store double* [[TMP16]], double** [[TMP15]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK1-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 8, !llvm.access.group !4 +// CHECK1-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK1-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 8, !llvm.access.group !4 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK1-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 8 +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -317,12 +317,12 @@ int main() { // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK2-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 @@ -344,7 +344,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -401,38 +401,38 @@ int main() { // CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP4]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: store double 1.000000e+00, double* [[G2]], align 8 +// CHECK2-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP4]], align 8 +// CHECK2-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 8 +// CHECK2-NEXT: store i32 3, i32* [[SVAR5]], align 4 +// CHECK2-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK2-NEXT: store double* [[G2]], double** [[TMP14]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: store double* [[G2]], double** [[TMP14]], align 8 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: store double* [[TMP16]], double** [[TMP15]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 8 +// CHECK2-NEXT: store double* [[TMP16]], double** [[TMP15]], align 8 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK2-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 8, !llvm.access.group !4 +// CHECK2-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK2-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 8, !llvm.access.group !4 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK2-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 8 +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -483,12 +483,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK3-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -518,7 +518,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -575,38 +575,38 @@ int main() { // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !5 -// CHECK3-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: store double 1.000000e+00, double* [[G2]], align 8 +// CHECK3-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK3-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 4 +// CHECK3-NEXT: store i32 3, i32* [[SVAR5]], align 4 +// CHECK3-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK3-NEXT: store double* [[G2]], double** [[TMP14]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store double* [[G2]], double** [[TMP14]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: store double* [[TMP16]], double** [[TMP15]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK3-NEXT: store double* [[TMP16]], double** [[TMP15]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !5 +// CHECK3-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4 +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -657,12 +657,12 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67 -// CHECK4-SAME: (double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 @@ -692,7 +692,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -749,38 +749,38 @@ int main() { // CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store double 1.000000e+00, double* [[G2]], align 8, !llvm.access.group !5 -// CHECK4-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store i32 3, i32* [[SVAR5]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: store double 1.000000e+00, double* [[G2]], align 8 +// CHECK4-NEXT: [[TMP13:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK4-NEXT: store volatile double 1.000000e+00, double* [[TMP13]], align 4 +// CHECK4-NEXT: store i32 3, i32* [[SVAR5]], align 4 +// CHECK4-NEXT: store float 4.000000e+00, float* [[SFVAR6]], align 4 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK4-NEXT: store double* [[G2]], double** [[TMP14]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store double* [[G2]], double** [[TMP14]], align 4 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: store double* [[TMP16]], double** [[TMP15]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP16:%.*]] = load double*, double** [[_TMP4]], align 4 +// CHECK4-NEXT: store double* [[TMP16]], double** [[TMP15]], align 4 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: store i32* [[SVAR5]], i32** [[TMP17]], align 4 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 -// CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !5 +// CHECK4-NEXT: store float* [[SFVAR6]], float** [[TMP18]], align 4 +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -831,7 +831,7 @@ int main() { // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK5-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK5-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK5-NEXT: ret i32 0 // // @@ -849,7 +849,7 @@ int main() { // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK6-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 // CHECK6-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 -// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK6-NEXT: ret i32 0 // // @@ -867,7 +867,7 @@ int main() { // CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK7-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK7-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK7-NEXT: ret i32 0 // // @@ -885,7 +885,7 @@ int main() { // CHECK8-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 // CHECK8-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 // CHECK8-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 -// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK8-NEXT: ret i32 0 // // @@ -910,14 +910,14 @@ int main() { // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -982,7 +982,7 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -990,27 +990,27 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP39]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1018,12 +1018,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1048,7 +1048,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1093,13 +1093,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -1119,37 +1119,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8, !llvm.access.group !5 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 // CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX10]] to i8* // CHECK9-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1196,14 +1196,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -1211,12 +1211,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1235,14 +1235,14 @@ int main() { // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -1302,17 +1302,17 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP32]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1323,7 +1323,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1337,7 +1337,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1346,17 +1346,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1364,12 +1364,12 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1391,7 +1391,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1432,13 +1432,13 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: // CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -1458,37 +1458,37 @@ int main() { // CHECK9-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK9: omp.inner.for.cond.cleanup: // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !11 -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4 +// CHECK9-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 // CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM8]] // CHECK9-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* // CHECK9-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[TMP15]] to i8* -// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i64 4, i1 false), !llvm.access.group !11 +// CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1533,14 +1533,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done14: @@ -1548,17 +1548,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1569,7 +1569,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1583,7 +1583,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1619,14 +1619,14 @@ int main() { // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -1691,7 +1691,7 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 @@ -1699,27 +1699,27 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done3: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP39]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1727,12 +1727,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -1757,7 +1757,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1802,13 +1802,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK10-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -1828,37 +1828,37 @@ int main() { // CHECK10-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8, !llvm.access.group !5 -// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 8 +// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 // CHECK10-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i64 0, i64 [[IDXPROM9]] // CHECK10-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX10]] to i8* // CHECK10-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -1905,14 +1905,14 @@ int main() { // CHECK10-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done15: @@ -1920,12 +1920,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -1944,14 +1944,14 @@ int main() { // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -2011,17 +2011,17 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP32]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2032,7 +2032,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2046,7 +2046,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2055,17 +2055,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2073,12 +2073,12 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK10-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 @@ -2100,7 +2100,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2141,13 +2141,13 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: // CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK10-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -2167,37 +2167,37 @@ int main() { // CHECK10-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK10: omp.inner.for.cond.cleanup: // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]] -// CHECK10-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !11 -// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4 +// CHECK10-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8 +// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 // CHECK10-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM8]] // CHECK10-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* // CHECK10-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[TMP15]] to i8* -// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i64 4, i1 false), !llvm.access.group !11 +// CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i64 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2242,14 +2242,14 @@ int main() { // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i64 4, i1 false) // CHECK10-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK10: .omp.lastprivate.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done14: @@ -2257,17 +2257,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2278,7 +2278,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2292,7 +2292,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2328,14 +2328,14 @@ int main() { // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -2398,7 +2398,7 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -2406,27 +2406,27 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP39]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2434,12 +2434,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2462,7 +2462,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2507,13 +2507,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -2533,35 +2533,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]] -// CHECK11-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP17]] // CHECK11-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK11-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !6 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -2608,14 +2608,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -2623,12 +2623,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2647,14 +2647,14 @@ int main() { // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -2713,17 +2713,17 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP32]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2734,7 +2734,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2748,7 +2748,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2757,17 +2757,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2775,12 +2775,12 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -2801,7 +2801,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2842,13 +2842,13 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: // CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -2868,35 +2868,35 @@ int main() { // CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK11: omp.inner.for.cond: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK11: omp.inner.for.cond.cleanup: // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP14]] -// CHECK11-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP16]] // CHECK11-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* // CHECK11-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[TMP15]] to i8* -// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i32 4, i1 false), !llvm.access.group !12 +// CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: @@ -2941,14 +2941,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -2956,17 +2956,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2977,7 +2977,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2991,7 +2991,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3027,14 +3027,14 @@ int main() { // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -3097,7 +3097,7 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 @@ -3105,27 +3105,27 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP39]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3133,12 +3133,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3161,7 +3161,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3206,13 +3206,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S* [[VAR5]], %struct.S** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 @@ -3232,35 +3232,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] // CHECK12-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP15]] -// CHECK12-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load %struct.S*, %struct.S** [[_TMP6]], align 4 +// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 [[TMP17]] // CHECK12-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* // CHECK12-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[TMP16]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !6 +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3307,14 +3307,14 @@ int main() { // CHECK12-NEXT: store i32 [[TMP37]], i32* [[TMP4]], align 4 // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done14: @@ -3322,12 +3322,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // @@ -3346,14 +3346,14 @@ int main() { // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -3412,17 +3412,17 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done2: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP32]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3433,7 +3433,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3447,7 +3447,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3456,17 +3456,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3474,12 +3474,12 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 -// CHECK12-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 @@ -3500,7 +3500,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -3541,13 +3541,13 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: // CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK12-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 @@ -3567,35 +3567,35 @@ int main() { // CHECK12-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK12: omp.inner.for.cond: -// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] // CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK12: omp.inner.for.cond.cleanup: // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK12: omp.inner.for.body: -// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[T_VAR2]], align 4 +// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP14]] -// CHECK12-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: store i32 [[TMP13]], i32* [[ARRAYIDX]], align 4 +// CHECK12-NEXT: [[TMP15:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4 +// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 // CHECK12-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP16]] // CHECK12-NEXT: [[TMP17:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* // CHECK12-NEXT: [[TMP18:%.*]] = bitcast %struct.S.0* [[TMP15]] to i8* -// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i32 4, i1 false), !llvm.access.group !12 +// CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP17]], i8* align 4 [[TMP18]], i32 4, i1 false) // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK12: omp.inner.for.inc: -// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 +// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK12: omp.inner.for.end: // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK12: omp.loop.exit: @@ -3640,14 +3640,14 @@ int main() { // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP34]], i8* align 4 [[TMP35]], i32 4, i1 false) // CHECK12-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK12: .omp.lastprivate.done: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP36]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done13: @@ -3655,17 +3655,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3676,7 +3676,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3690,7 +3690,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3732,14 +3732,14 @@ int main() { // CHECK13-NEXT: [[I15:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK13-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK13-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -3755,13 +3755,13 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: // CHECK13-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK13-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -3825,18 +3825,18 @@ int main() { // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 4, i1 false) // CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK13-NEXT: store i32 [[TMP26]], i32* @_ZZ4mainE4svar, align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4:[0-9]+]] // CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done14: -// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK13-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN16]], i64 2 @@ -3844,27 +3844,27 @@ int main() { // CHECK13: arraydestroy.body17: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S* [ [[TMP28]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK13: arraydestroy.done21: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP29]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3872,17 +3872,17 @@ int main() { // CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // @@ -3907,14 +3907,14 @@ int main() { // CHECK13-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK13-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK13-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -3930,13 +3930,13 @@ int main() { // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK13: arrayctor.cont: // CHECK13-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK13-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: @@ -3998,14 +3998,14 @@ int main() { // CHECK13-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* // CHECK13-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 4, i1 false) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done14: @@ -4016,17 +4016,17 @@ int main() { // CHECK13: arraydestroy.body16: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S.0* [ [[TMP27]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST17]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK13: arraydestroy.done20: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP28]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4037,7 +4037,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4046,7 +4046,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK13-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4060,17 +4060,17 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4078,22 +4078,22 @@ int main() { // CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK13-NEXT: ret void // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4104,7 +4104,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4118,7 +4118,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4153,14 +4153,14 @@ int main() { // CHECK14-NEXT: [[I15:%.*]] = alloca i32, align 4 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK14-NEXT: store double* [[G]], double** [[G1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK14-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 @@ -4176,13 +4176,13 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: // CHECK14-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK14-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -4246,18 +4246,18 @@ int main() { // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 4, i1 false) // CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK14-NEXT: store i32 [[TMP26]], i32* @_ZZ4mainE4svar, align 4 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4:[0-9]+]] // CHECK14-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK14-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done14: -// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK14-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN16]], i64 2 @@ -4265,27 +4265,27 @@ int main() { // CHECK14: arraydestroy.body17: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S* [ [[TMP28]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK14: arraydestroy.done21: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP29]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4293,17 +4293,17 @@ int main() { // CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // @@ -4328,14 +4328,14 @@ int main() { // CHECK14-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK14-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK14-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK14-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 // CHECK14-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 @@ -4351,13 +4351,13 @@ int main() { // CHECK14-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK14: arrayctor.loop: // CHECK14-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK14-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK14-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK14-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK14: arrayctor.cont: // CHECK14-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK14-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 8 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK14: omp.inner.for.cond: @@ -4419,14 +4419,14 @@ int main() { // CHECK14-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* // CHECK14-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 4, i1 false) -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK14-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done14: @@ -4437,17 +4437,17 @@ int main() { // CHECK14: arraydestroy.body16: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S.0* [ [[TMP27]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST17]], i64 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK14: arraydestroy.done20: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP28]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4458,7 +4458,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4467,7 +4467,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK14-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4481,17 +4481,17 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4499,22 +4499,22 @@ int main() { // CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK14-NEXT: ret void // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4525,7 +4525,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4539,7 +4539,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -4574,14 +4574,14 @@ int main() { // CHECK15-NEXT: [[I14:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK15-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK15-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -4597,13 +4597,13 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: // CHECK15-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK15-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -4665,18 +4665,18 @@ int main() { // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 4, i1 false) // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK15-NEXT: store i32 [[TMP26]], i32* @_ZZ4mainE4svar, align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4:[0-9]+]] // CHECK15-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK15-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done13: -// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK15-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i32 2 @@ -4684,27 +4684,27 @@ int main() { // CHECK15: arraydestroy.body16: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S* [ [[TMP28]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST17]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK15: arraydestroy.done20: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP29]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4712,17 +4712,17 @@ int main() { // CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // @@ -4747,14 +4747,14 @@ int main() { // CHECK15-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK15-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK15-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK15-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -4770,13 +4770,13 @@ int main() { // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK15: arrayctor.cont: // CHECK15-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK15-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK15: omp.inner.for.cond: @@ -4836,14 +4836,14 @@ int main() { // CHECK15-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* // CHECK15-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 4, i1 false) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK15-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done13: @@ -4854,17 +4854,17 @@ int main() { // CHECK15: arraydestroy.body15: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi %struct.S.0* [ [[TMP27]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST16]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK15: arraydestroy.done19: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP28]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4875,7 +4875,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -4884,7 +4884,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK15-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4898,17 +4898,17 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4916,22 +4916,22 @@ int main() { // CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK15-NEXT: ret void // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4942,7 +4942,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4956,7 +4956,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -4991,14 +4991,14 @@ int main() { // CHECK16-NEXT: [[I14:%.*]] = alloca i32, align 4 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK16-NEXT: store double* [[G]], double** [[G1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) // CHECK16-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 @@ -5014,13 +5014,13 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: // CHECK16-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR6]]) +// CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK16-NEXT: store %struct.S* [[VAR6]], %struct.S** [[_TMP7]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -5082,18 +5082,18 @@ int main() { // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 4, i1 false) // CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[SVAR]], align 4 // CHECK16-NEXT: store i32 [[TMP26]], i32* @_ZZ4mainE4svar, align 4 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR6]]) #[[ATTR4:[0-9]+]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4:[0-9]+]] // CHECK16-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 // CHECK16-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done13: -// CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 // CHECK16-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK16-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN15]], i32 2 @@ -5101,27 +5101,27 @@ int main() { // CHECK16: arraydestroy.body16: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi %struct.S* [ [[TMP28]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST17]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK16: arraydestroy.done20: -// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP29:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP29]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5129,17 +5129,17 @@ int main() { // CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // @@ -5164,14 +5164,14 @@ int main() { // CHECK16-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK16-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK16-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK16-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 // CHECK16-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 @@ -5187,13 +5187,13 @@ int main() { // CHECK16-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK16: arrayctor.loop: // CHECK16-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK16-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK16-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK16-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK16: arrayctor.cont: // CHECK16-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR6]]) +// CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK16-NEXT: store %struct.S.0* [[VAR6]], %struct.S.0** [[_TMP7]], align 4 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK16: omp.inner.for.cond: @@ -5253,14 +5253,14 @@ int main() { // CHECK16-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[TMP5]] to i8* // CHECK16-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[TMP23]] to i8* // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i32 4, i1 false) -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR6]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 // CHECK16-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK16: arraydestroy.body: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK16: arraydestroy.done13: @@ -5271,17 +5271,17 @@ int main() { // CHECK16: arraydestroy.body15: // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi %struct.S.0* [ [[TMP27]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST16]], i32 -1 -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR4]] // CHECK16-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK16: arraydestroy.done19: -// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK16-NEXT: ret i32 [[TMP28]] // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5292,7 +5292,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -5301,7 +5301,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK16-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -5315,17 +5315,17 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5333,22 +5333,22 @@ int main() { // CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK16-NEXT: ret void // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -5359,7 +5359,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5373,7 +5373,7 @@ int main() { // // // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK16-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp index bebb9df097f829f9d1f06f87a6fba9e96b1cbb94..1af206060597d8c91a0365dfd4ce93e4699293af 100644 --- a/clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp @@ -126,33 +126,33 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -165,7 +165,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -176,14 +176,14 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -191,12 +191,12 @@ int main() { // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -204,7 +204,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -212,7 +212,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -231,7 +231,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK1-NEXT: ret void // @@ -250,7 +250,7 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // @@ -262,7 +262,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -289,12 +289,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -313,40 +313,40 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group !5 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -360,14 +360,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done7: @@ -385,14 +385,14 @@ int main() { // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -410,27 +410,27 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP4]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -438,7 +438,7 @@ int main() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK1-NEXT: ret void // // @@ -450,7 +450,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -479,12 +479,12 @@ int main() { // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -504,37 +504,37 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !11 +// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -548,14 +548,14 @@ int main() { // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -563,17 +563,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -585,7 +585,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -601,7 +601,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -628,33 +628,33 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -667,7 +667,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -678,14 +678,14 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -693,12 +693,12 @@ int main() { // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -706,7 +706,7 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -714,7 +714,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -733,7 +733,7 @@ int main() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK2-NEXT: ret void // @@ -752,7 +752,7 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // @@ -764,7 +764,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -791,12 +791,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -815,40 +815,40 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] // CHECK2-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* // CHECK2-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group !5 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] -// CHECK2-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -862,14 +862,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done7: @@ -887,14 +887,14 @@ int main() { // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -912,27 +912,27 @@ int main() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done2: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK2-NEXT: ret i32 [[TMP4]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -940,7 +940,7 @@ int main() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK2-NEXT: ret void // // @@ -952,7 +952,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -981,12 +981,12 @@ int main() { // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2: arrayctor.cont: -// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1006,37 +1006,37 @@ int main() { // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK2: omp.inner.for.cond.cleanup: // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK2-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 // CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK2-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !11 +// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -1050,14 +1050,14 @@ int main() { // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK2: .omp.final.done: -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done8: @@ -1065,17 +1065,17 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1087,7 +1087,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1103,7 +1103,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1130,33 +1130,33 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1169,7 +1169,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1180,14 +1180,14 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1195,12 +1195,12 @@ int main() { // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1208,7 +1208,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1216,7 +1216,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1235,7 +1235,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK3-SAME: () #[[ATTR0]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK3-NEXT: ret void // @@ -1254,7 +1254,7 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // @@ -1266,7 +1266,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1293,12 +1293,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1317,38 +1317,38 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] -// CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]] // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group !6 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1362,14 +1362,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -1387,14 +1387,14 @@ int main() { // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -1412,27 +1412,27 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP4]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1440,7 +1440,7 @@ int main() { // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK3-NEXT: ret void // // @@ -1452,7 +1452,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1481,12 +1481,12 @@ int main() { // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -1506,35 +1506,35 @@ int main() { // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] -// CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !12 +// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1548,14 +1548,14 @@ int main() { // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -1563,17 +1563,17 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -1585,7 +1585,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1601,7 +1601,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -1628,33 +1628,33 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1667,7 +1667,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -1678,14 +1678,14 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1693,12 +1693,12 @@ int main() { // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -1706,7 +1706,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -1714,7 +1714,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1733,7 +1733,7 @@ int main() { // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK4-SAME: () #[[ATTR0]] { // CHECK4-NEXT: entry: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK4-NEXT: ret void // @@ -1752,7 +1752,7 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // @@ -1764,7 +1764,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1791,12 +1791,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1815,38 +1815,38 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] -// CHECK4-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]] // CHECK4-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* // CHECK4-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group !6 -// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) +// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1860,14 +1860,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done6: @@ -1885,14 +1885,14 @@ int main() { // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) @@ -1910,27 +1910,27 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done2: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK4-NEXT: ret i32 [[TMP4]] // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1938,7 +1938,7 @@ int main() { // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK4-NEXT: ret void // // @@ -1950,7 +1950,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1979,12 +1979,12 @@ int main() { // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4: arrayctor.cont: -// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -2004,35 +2004,35 @@ int main() { // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] // CHECK4: omp.inner.for.cond.cleanup: // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] -// CHECK4-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK4-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* // CHECK4-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* -// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !12 +// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -2046,14 +2046,14 @@ int main() { // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK4: .omp.final.done: -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done7: @@ -2061,17 +2061,17 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2083,7 +2083,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2099,7 +2099,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2126,42 +2126,42 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2169,12 +2169,12 @@ int main() { // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2182,7 +2182,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -2192,7 +2192,7 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK5-NEXT: ret void // @@ -2221,12 +2221,12 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 @@ -2265,18 +2265,18 @@ int main() { // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done6: -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK5-NEXT: ret i32 [[CALL]] // // @@ -2300,14 +2300,14 @@ int main() { // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -2319,12 +2319,12 @@ int main() { // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: -// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: @@ -2361,14 +2361,14 @@ int main() { // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done11: @@ -2379,17 +2379,17 @@ int main() { // CHECK5: arraydestroy.body13: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK5: arraydestroy.done17: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP14]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2402,7 +2402,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2411,7 +2411,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2428,17 +2428,17 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2446,22 +2446,22 @@ int main() { // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2473,7 +2473,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2489,7 +2489,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2509,42 +2509,42 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2552,12 +2552,12 @@ int main() { // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK6-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2565,7 +2565,7 @@ int main() { // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done1: @@ -2575,7 +2575,7 @@ int main() { // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK6-SAME: () #[[ATTR0]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK6-NEXT: ret void // @@ -2604,12 +2604,12 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 @@ -2648,18 +2648,18 @@ int main() { // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done6: -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK6-NEXT: ret i32 [[CALL]] // // @@ -2683,14 +2683,14 @@ int main() { // CHECK6-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK6-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 // CHECK6-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -2702,12 +2702,12 @@ int main() { // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK6: arrayctor.cont: -// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK6-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK6: omp.inner.for.cond: @@ -2744,14 +2744,14 @@ int main() { // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK6: omp.inner.for.end: // CHECK6-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done11: @@ -2762,17 +2762,17 @@ int main() { // CHECK6: arraydestroy.body13: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK6: arraydestroy.done17: -// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK6-NEXT: ret i32 [[TMP14]] // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2785,7 +2785,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -2794,7 +2794,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2811,17 +2811,17 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2829,22 +2829,22 @@ int main() { // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK6-NEXT: ret void // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2856,7 +2856,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2872,7 +2872,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -2892,42 +2892,42 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2935,12 +2935,12 @@ int main() { // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -2948,7 +2948,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -2958,7 +2958,7 @@ int main() { // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK7-SAME: () #[[ATTR0]] { // CHECK7-NEXT: entry: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK7-NEXT: ret void // @@ -2987,12 +2987,12 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 @@ -3029,18 +3029,18 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done5: -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK7-NEXT: ret i32 [[CALL]] // // @@ -3064,14 +3064,14 @@ int main() { // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3083,12 +3083,12 @@ int main() { // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: -// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK7: omp.inner.for.cond: @@ -3123,14 +3123,14 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done10: @@ -3141,17 +3141,17 @@ int main() { // CHECK7: arraydestroy.body12: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK7: arraydestroy.done16: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP14]] // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3164,7 +3164,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3173,7 +3173,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3190,17 +3190,17 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3208,22 +3208,22 @@ int main() { // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3235,7 +3235,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3251,7 +3251,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3271,42 +3271,42 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3314,12 +3314,12 @@ int main() { // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK8-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 @@ -3327,7 +3327,7 @@ int main() { // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done1: @@ -3337,7 +3337,7 @@ int main() { // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK8-SAME: () #[[ATTR0]] { // CHECK8-NEXT: entry: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK8-NEXT: ret void // @@ -3366,12 +3366,12 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 @@ -3408,18 +3408,18 @@ int main() { // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done5: -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK8-NEXT: ret i32 [[CALL]] // // @@ -3443,14 +3443,14 @@ int main() { // CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 // CHECK8-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 @@ -3462,12 +3462,12 @@ int main() { // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK8: arrayctor.loop: // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK8: arrayctor.cont: -// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR5]]) +// CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK8: omp.inner.for.cond: @@ -3502,14 +3502,14 @@ int main() { // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK8: omp.inner.for.end: // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done10: @@ -3520,17 +3520,17 @@ int main() { // CHECK8: arraydestroy.body12: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK8: arraydestroy.done16: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP14]] // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3543,7 +3543,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -3552,7 +3552,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3569,17 +3569,17 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3587,22 +3587,22 @@ int main() { // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK8-NEXT: ret void // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3614,7 +3614,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3630,7 +3630,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -3650,33 +3650,33 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3689,7 +3689,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3700,14 +3700,14 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3715,12 +3715,12 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3728,7 +3728,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -3736,7 +3736,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3755,7 +3755,7 @@ int main() { // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK9-SAME: () #[[ATTR0]] { // CHECK9-NEXT: entry: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK9-NEXT: ret void // @@ -3766,12 +3766,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK9-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 @@ -3783,7 +3783,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -3826,35 +3826,35 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: store i32 1, i32* [[G]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: store i32 1, i32* [[G]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8 +// CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 +// CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[G]], i32** [[TMP9]], align 8, !llvm.access.group !4 +// CHECK9-NEXT: store i32* [[G]], i32** [[TMP9]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8 +// CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3888,33 +3888,33 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3927,7 +3927,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -3938,14 +3938,14 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3953,12 +3953,12 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3966,7 +3966,7 @@ int main() { // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: @@ -3974,7 +3974,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3993,7 +3993,7 @@ int main() { // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK10-SAME: () #[[ATTR0]] { // CHECK10-NEXT: entry: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK10-NEXT: ret void // @@ -4004,12 +4004,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 -// CHECK10-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK10-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 @@ -4021,7 +4021,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -4064,35 +4064,35 @@ int main() { // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: store i32 1, i32* [[G]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: store i32 2, i32* [[SIVAR]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: store i32 1, i32* [[G]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8 +// CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 +// CHECK10-NEXT: store i32 2, i32* [[SIVAR]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[G]], i32** [[TMP9]], align 8, !llvm.access.group !4 +// CHECK10-NEXT: store i32* [[G]], i32** [[TMP9]], align 8 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 -// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8 +// CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 -// CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -4126,42 +4126,42 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4169,12 +4169,12 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4182,7 +4182,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -4192,7 +4192,7 @@ int main() { // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK11-SAME: () #[[ATTR0]] { // CHECK11-NEXT: entry: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK11-NEXT: ret void // @@ -4203,12 +4203,12 @@ int main() { // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: ret i32 0 // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4221,7 +4221,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4230,7 +4230,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4258,42 +4258,42 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -4301,12 +4301,12 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK12-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4314,7 +4314,7 @@ int main() { // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done1: @@ -4324,7 +4324,7 @@ int main() { // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK12-SAME: () #[[ATTR0]] { // CHECK12-NEXT: entry: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] // CHECK12-NEXT: ret void // @@ -4335,12 +4335,12 @@ int main() { // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK12-NEXT: ret i32 0 // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4353,7 +4353,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -4362,7 +4362,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 diff --git a/clang/test/OpenMP/teams_distribute_simd_reduction_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_reduction_codegen.cpp index 5114fd49f5457f5fe79b2edc547fc4cc4daa2613..19f57c391248a6ee59a0b5fa12b5d8acfa2af282 100644 --- a/clang/test/OpenMP/teams_distribute_simd_reduction_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_reduction_codegen.cpp @@ -114,12 +114,12 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK1-NEXT: ret i32 [[CALL]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63 -// CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -129,7 +129,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -170,27 +170,27 @@ int main() { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -228,7 +228,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -290,7 +290,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 @@ -300,7 +300,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -341,27 +341,27 @@ int main() { // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK1-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -399,7 +399,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -461,12 +461,12 @@ int main() { // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK2-NEXT: ret i32 [[CALL]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63 -// CHECK2-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -476,7 +476,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -517,27 +517,27 @@ int main() { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -575,7 +575,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -637,7 +637,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK2-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 @@ -647,7 +647,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -688,27 +688,27 @@ int main() { // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK2-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: @@ -746,7 +746,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -807,12 +807,12 @@ int main() { // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK3-NEXT: ret i32 [[CALL]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63 -// CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-SAME: (i32 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 @@ -821,7 +821,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -862,27 +862,27 @@ int main() { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -920,7 +920,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -981,7 +981,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 @@ -990,7 +990,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1031,27 +1031,27 @@ int main() { // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK3: omp.inner.for.cond: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: @@ -1089,7 +1089,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1150,12 +1150,12 @@ int main() { // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK4: omp_offload.cont: -// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK4-NEXT: ret i32 [[CALL]] // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l63 -// CHECK4-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK4-SAME: (i32 [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 @@ -1164,7 +1164,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1205,27 +1205,27 @@ int main() { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1263,7 +1263,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1324,7 +1324,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 -// CHECK4-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 @@ -1333,7 +1333,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1374,27 +1374,27 @@ int main() { // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK4: omp.inner.for.cond: -// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK4: omp.inner.for.body: -// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK4: omp.inner.for.inc: -// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK4: omp.inner.for.end: // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK4: omp.loop.exit: @@ -1432,7 +1432,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 @@ -1507,7 +1507,7 @@ int main() { // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK5-NEXT: ret i32 [[CALL]] // // @@ -1607,7 +1607,7 @@ int main() { // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK6-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK6-NEXT: ret i32 [[CALL]] // // @@ -1707,7 +1707,7 @@ int main() { // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK7-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK7-NEXT: ret i32 [[CALL]] // // @@ -1807,7 +1807,7 @@ int main() { // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] // CHECK8-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 -// CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK8-NEXT: ret i32 [[CALL]] // // @@ -1868,12 +1868,12 @@ int main() { // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK9-NEXT: ret i32 0 // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 -// CHECK9-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK9-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -1883,7 +1883,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1925,30 +1925,30 @@ int main() { // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4 -// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 +// CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -1986,7 +1986,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK9-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK9-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2022,12 +2022,12 @@ int main() { // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK10-NEXT: ret i32 0 // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45 -// CHECK10-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK10-SAME: (i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 @@ -2037,7 +2037,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -2079,30 +2079,30 @@ int main() { // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK10: omp.inner.for.cond: -// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK10: omp.inner.for.body: -// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 +// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] -// CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 -// CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4 -// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 +// CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8 +// CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: -// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 +// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 -// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 +// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK10: omp.inner.for.end: // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK10: omp.loop.exit: @@ -2140,7 +2140,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// CHECK10-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK10-SAME: (i8* [[TMP0:%.*]], i8* [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 @@ -2176,7 +2176,7 @@ int main() { // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK11-NEXT: ret i32 0 // // @@ -2186,6 +2186,6 @@ int main() { // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK12-NEXT: ret i32 0 // diff --git a/clang/test/OpenMP/teams_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_firstprivate_codegen.cpp index 699f73dc8ee3bba03ca9a73cac44b6af5051c53b..1866f264dea7bd8e31b79c2974d84e6d4a8aadbc 100644 --- a/clang/test/OpenMP/teams_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_firstprivate_codegen.cpp @@ -1,46 +1,46 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test host codegen. -// RUN: %clang_cc1 -disable-noundef-analysis -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 -// RUN: %clang_cc1 -disable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -disable-noundef-analysis -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK2 -// RUN: %clang_cc1 -disable-noundef-analysis -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 -// RUN: %clang_cc1 -disable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -disable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK2 +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping +// RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 -// RUN: %clang_cc1 -disable-noundef-analysis -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -disable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -disable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping +// RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -disable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 -// RUN: %clang_cc1 -disable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -disable-noundef-analysis -DARRAY -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK18 -// RUN: %clang_cc1 -disable-noundef-analysis -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK19 -// RUN: %clang_cc1 -disable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -disable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK20 +// RUN: %clang_cc1 -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 +// RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping +// RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK18 +// RUN: %clang_cc1 -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK19 +// RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping +// RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK20 -// RUN: %clang_cc1 -disable-noundef-analysis -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -disable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" -// RUN: %clang_cc1 -disable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping -// RUN: %clang_cc1 -disable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping +// RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" +// RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping +// RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" // expected-no-diagnostics #ifndef HEADER #define HEADER diff --git a/clang/test/OpenMP/teams_private_codegen.cpp b/clang/test/OpenMP/teams_private_codegen.cpp index b42c8be3b357f695ef7035e1d9513f06895ec5e2..9848b3a295761df4d333e694744f823d1fffea4d 100644 --- a/clang/test/OpenMP/teams_private_codegen.cpp +++ b/clang/test/OpenMP/teams_private_codegen.cpp @@ -170,13 +170,13 @@ int main() { // CHECK1-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -184,12 +184,12 @@ int main() { // CHECK1-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -229,7 +229,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 -// CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -239,7 +239,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -266,12 +266,12 @@ int main() { // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK1-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP1]], align 8 // CHECK1-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 8 -// CHECK1-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK1-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { +// CHECK1-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK1-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 @@ -304,7 +304,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -319,7 +319,7 @@ int main() { // CHECK1-NEXT: store i32* [[G]], i32** [[TMP0]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[TMP1]], align 8 -// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* noundef [[REF_TMP]]) +// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret void // // @@ -337,13 +337,13 @@ int main() { // CHECK2-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK2-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -351,12 +351,12 @@ int main() { // CHECK2-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK2-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -396,7 +396,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 -// CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK2-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -406,7 +406,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -433,12 +433,12 @@ int main() { // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK2-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP1]], align 8 // CHECK2-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 8 -// CHECK2-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK2-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { +// CHECK2-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 // CHECK2-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 @@ -471,7 +471,7 @@ int main() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -486,7 +486,7 @@ int main() { // CHECK2-NEXT: store i32* [[G]], i32** [[TMP0]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: store i32* [[SIVAR]], i32** [[TMP1]], align 8 -// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* noundef [[REF_TMP]]) +// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret void // // @@ -504,13 +504,13 @@ int main() { // CHECK3-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 @@ -518,12 +518,12 @@ int main() { // CHECK3-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 @@ -563,7 +563,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 -// CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -573,7 +573,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -600,12 +600,12 @@ int main() { // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK3-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP1]], align 4 // CHECK3-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 4 -// CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK3-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { +// CHECK3-SAME: (%class.anon.0* nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 4 // CHECK3-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 4 @@ -638,7 +638,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -653,7 +653,7 @@ int main() { // CHECK3-NEXT: store i32* [[G]], i32** [[TMP0]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[TMP1]], align 4 -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* noundef [[REF_TMP]]) +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret void // // @@ -671,13 +671,13 @@ int main() { // CHECK4-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 @@ -685,12 +685,12 @@ int main() { // CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 @@ -730,7 +730,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 -// CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -740,7 +740,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -767,12 +767,12 @@ int main() { // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: [[TMP6:%.*]] = load i32*, i32** [[_TMP1]], align 4 // CHECK4-NEXT: store i32* [[TMP6]], i32** [[TMP5]], align 4 -// CHECK4-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK4-SAME: (%class.anon.0* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { +// CHECK4-SAME: (%class.anon.0* nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 4 // CHECK4-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 4 @@ -805,7 +805,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -820,7 +820,7 @@ int main() { // CHECK4-NEXT: store i32* [[G]], i32** [[TMP0]], align 4 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: store i32* [[SIVAR]], i32** [[TMP1]], align 4 -// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* noundef [[REF_TMP]]) +// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK4-NEXT: ret void // // @@ -842,16 +842,16 @@ int main() { // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK9-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK9-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) // CHECK9-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 // CHECK9-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] @@ -859,26 +859,26 @@ int main() { // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: -// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP4]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK9-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK9-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -886,22 +886,22 @@ int main() { // CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK9-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -909,7 +909,7 @@ int main() { // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK9-NEXT: ret void // // @@ -921,7 +921,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -937,12 +937,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 @@ -951,14 +951,14 @@ int main() { // CHECK9-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 4, i1 false) // CHECK9-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: @@ -966,12 +966,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -985,16 +985,16 @@ int main() { // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK9-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef [[SST]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK9-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) -// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef signext 3) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3) // CHECK9-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) // CHECK9-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 // CHECK9-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] @@ -1003,24 +1003,24 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP4]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK9-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -1060,7 +1060,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 -// CHECK9-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1070,7 +1070,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1101,7 +1101,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1112,7 +1112,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1126,7 +1126,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1135,27 +1135,27 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK9-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK9-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1163,7 +1163,7 @@ int main() { // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK9-NEXT: ret void // // @@ -1175,7 +1175,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1190,12 +1190,12 @@ int main() { // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 @@ -1203,14 +1203,14 @@ int main() { // CHECK9-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* // CHECK9-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i64 4, i1 false) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: @@ -1218,17 +1218,17 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1239,7 +1239,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK9-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -1270,7 +1270,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 -// CHECK9-SAME: (%struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (%struct.SST* [[THIS:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 @@ -1280,7 +1280,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1300,7 +1300,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1314,7 +1314,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1340,16 +1340,16 @@ int main() { // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK10-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK10-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) // CHECK10-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 // CHECK10-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] @@ -1357,26 +1357,26 @@ int main() { // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: -// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() +// CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP4]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK10-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK10-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -1384,22 +1384,22 @@ int main() { // CHECK10-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK10-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(16) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1407,7 +1407,7 @@ int main() { // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK10-NEXT: ret void // // @@ -1419,7 +1419,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1435,12 +1435,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 @@ -1449,14 +1449,14 @@ int main() { // CHECK10-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 4, i1 false) // CHECK10-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done3: @@ -1464,12 +1464,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -1483,16 +1483,16 @@ int main() { // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 // CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK10-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef [[SST]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK10-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) -// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef signext 3) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3) // CHECK10-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) // CHECK10-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 // CHECK10-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] @@ -1501,24 +1501,24 @@ int main() { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done1: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP4]] // // // CHECK10-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK10-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.SS* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 @@ -1558,7 +1558,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 -// CHECK10-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 // CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 @@ -1568,7 +1568,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1599,7 +1599,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1610,7 +1610,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1624,7 +1624,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 @@ -1633,27 +1633,27 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK10-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK10-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1661,7 +1661,7 @@ int main() { // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) +// CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) // CHECK10-NEXT: ret void // // @@ -1673,7 +1673,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1688,12 +1688,12 @@ int main() { // CHECK10-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK10: arrayctor.loop: // CHECK10-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK10-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 // CHECK10-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK10-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK10: arrayctor.cont: -// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 @@ -1701,14 +1701,14 @@ int main() { // CHECK10-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* // CHECK10-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i64 4, i1 false) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i64 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done3: @@ -1716,17 +1716,17 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1737,7 +1737,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK10-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 @@ -1768,7 +1768,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 -// CHECK10-SAME: (%struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (%struct.SST* [[THIS:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 // CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 @@ -1778,7 +1778,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1798,7 +1798,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1812,7 +1812,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 @@ -1838,16 +1838,16 @@ int main() { // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK11-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK11-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) // CHECK11-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 // CHECK11-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] @@ -1855,26 +1855,26 @@ int main() { // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: -// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP4]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK11-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK11-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 @@ -1882,22 +1882,22 @@ int main() { // CHECK11-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK11-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -1905,7 +1905,7 @@ int main() { // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK11-NEXT: ret void // // @@ -1917,7 +1917,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -1933,12 +1933,12 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 @@ -1947,14 +1947,14 @@ int main() { // CHECK11-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 4, i1 false) // CHECK11-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done3: @@ -1962,12 +1962,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1981,16 +1981,16 @@ int main() { // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK11-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef [[SST]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK11-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK11-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) // CHECK11-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 // CHECK11-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] @@ -1999,24 +1999,24 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP4]] // // // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK11-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 @@ -2056,7 +2056,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 -// CHECK11-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2066,7 +2066,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2097,7 +2097,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2108,7 +2108,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2122,7 +2122,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2131,27 +2131,27 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK11-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 // CHECK11-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK11-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2159,7 +2159,7 @@ int main() { // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK11-NEXT: ret void // // @@ -2171,7 +2171,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2186,12 +2186,12 @@ int main() { // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 @@ -2199,14 +2199,14 @@ int main() { // CHECK11-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* // CHECK11-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i32 4, i1 false) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done3: @@ -2214,17 +2214,17 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2235,7 +2235,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK11-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -2266,7 +2266,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 -// CHECK11-SAME: (%struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (%struct.SST* [[THIS:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 // CHECK11-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 @@ -2276,7 +2276,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2296,7 +2296,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2310,7 +2310,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2336,16 +2336,16 @@ int main() { // CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 // CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN2SSC1ERi(%struct.SS* noundef [[SS]], i32* noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[TEST]]) +// CHECK12-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) -// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef [[VAR]], float noundef 3.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) // CHECK12-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) // CHECK12-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 // CHECK12-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] @@ -2353,26 +2353,26 @@ int main() { // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l136() #[[ATTR4:[0-9]+]] // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: -// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() +// CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done1: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP4]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC1ERi -// CHECK12-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK12-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 @@ -2380,22 +2380,22 @@ int main() { // CHECK12-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN2SSC2ERi(%struct.SS* noundef [[THIS1]], i32* noundef nonnull align 4 dereferenceable(4) [[TMP0]]) +// CHECK12-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(12) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2403,7 +2403,7 @@ int main() { // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) // CHECK12-NEXT: ret void // // @@ -2415,7 +2415,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2431,12 +2431,12 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) +// CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 4 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 4 @@ -2445,14 +2445,14 @@ int main() { // CHECK12-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[VAR]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 4, i1 false) // CHECK12-NEXT: store i32 3, i32* [[SIVAR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done3: @@ -2460,12 +2460,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // @@ -2479,16 +2479,16 @@ int main() { // CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 // CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 // CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) -// CHECK12-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* noundef [[SST]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) +// CHECK12-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 128 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[VAR]], i32 noundef 3) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK12-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l86.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) // CHECK12-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 // CHECK12-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] @@ -2497,24 +2497,24 @@ int main() { // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK12: omp_offload.cont: // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done1: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP4]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK12-SAME: (%struct.SS* noundef [[THIS:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.SS* nonnull align 4 dereferenceable(12) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 @@ -2554,7 +2554,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSC1ERi_l48 -// CHECK12-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (%struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 // CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 @@ -2564,7 +2564,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2595,7 +2595,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2606,7 +2606,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -2620,7 +2620,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 @@ -2629,27 +2629,27 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev -// CHECK12-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 // CHECK12-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* noundef [[THIS1]]) +// CHECK12-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2657,7 +2657,7 @@ int main() { // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK12-NEXT: ret void // // @@ -2669,7 +2669,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2684,12 +2684,12 @@ int main() { // CHECK12-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK12: arrayctor.loop: // CHECK12-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK12-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 // CHECK12-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK12-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK12: arrayctor.cont: -// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) +// CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR]], align 128 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[ARRAYIDX]], align 128 @@ -2697,14 +2697,14 @@ int main() { // CHECK12-NEXT: [[TMP1:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* // CHECK12-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP1]], i8* align 128 [[TMP2]], i32 4, i1 false) -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN2]], i32 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done3: @@ -2712,17 +2712,17 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR4]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK12-NEXT: ret void // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2733,7 +2733,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev -// CHECK12-SAME: (%struct.SST* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 @@ -2764,7 +2764,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIiEC1Ev_l64 -// CHECK12-SAME: (%struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (%struct.SST* [[THIS:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 // CHECK12-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 @@ -2774,7 +2774,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 -// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SST* noundef [[THIS:%.*]]) #[[ATTR3]] { +// CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]]) #[[ATTR3]] { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 @@ -2794,7 +2794,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2808,7 +2808,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 @@ -2822,3 +2822,4 @@ int main() { // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) // CHECK12-NEXT: ret void // +// \ No newline at end of file diff --git a/clang/test/OpenMP/threadprivate_codegen.cpp b/clang/test/OpenMP/threadprivate_codegen.cpp index a7b8eeee4c10fe3d42ec9998a51df013410e9359..f1ccb80cb3ab409a3075f24362d7bcbacd94e263 100644 --- a/clang/test/OpenMP/threadprivate_codegen.cpp +++ b/clang/test/OpenMP/threadprivate_codegen.cpp @@ -1019,19 +1019,19 @@ int foobar() { // CHECK-TLS-DAG: declare {{.*}} void [[GS3_TLS_INIT]] // CHECK-TLS-DAG: declare {{.*}} void [[STATIC_S_TLS_INIT]] // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S1* -// CHECK1-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef [[TMP2]], i32 noundef 5) +// CHECK1-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[TMP2]], i32 5) // CHECK1-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: ret i8* [[TMP3]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1039,28 +1039,28 @@ int foobar() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN2S1C2Ei(%struct.S1* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN2S1C2Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S1* -// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[TMP2]]) #[[ATTR3:[0-9]+]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2S1D2Ev(%struct.S1* noundef [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // @@ -1073,7 +1073,7 @@ int foobar() { // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca [3 x %struct.S1]*, align 8 @@ -1088,34 +1088,34 @@ int foobar() { // CHECK1-NEXT: store [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // CHECK1-NEXT: [[ARRAYINIT_BEGIN1:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], i64 0, i64 0 // CHECK1-NEXT: store %struct.S1* [[ARRAYINIT_BEGIN1]], %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8 -// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_BEGIN1]], i32 noundef 1) +// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN1]], i32 1) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYINIT_BEGIN1]], i64 1 // CHECK1-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT]], %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8 -// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] // CHECK1: invoke.cont3: // CHECK1-NEXT: [[ARRAYINIT_ELEMENT4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYINIT_ELEMENT]], i64 1 // CHECK1-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT4]], %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8 -// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT4]], i32 noundef 3) +// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT4]], i32 3) // CHECK1-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK1: invoke.cont5: // CHECK1-NEXT: [[ARRAYINIT_ELEMENT7:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], i64 1 // CHECK1-NEXT: store [3 x %struct.S1]* [[ARRAYINIT_ELEMENT7]], [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // CHECK1-NEXT: [[ARRAYINIT_BEGIN8:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_ELEMENT7]], i64 0, i64 0 // CHECK1-NEXT: store %struct.S1* [[ARRAYINIT_BEGIN8]], %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8 -// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_BEGIN8]], i32 noundef 4) +// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN8]], i32 4) // CHECK1-NEXT: to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD10:%.*]] // CHECK1: invoke.cont11: // CHECK1-NEXT: [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYINIT_BEGIN8]], i64 1 // CHECK1-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT12]], %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8 -// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT12]], i32 noundef 5) +// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT12]], i32 5) // CHECK1-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD10]] // CHECK1: invoke.cont13: // CHECK1-NEXT: [[ARRAYINIT_ELEMENT14:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYINIT_ELEMENT12]], i64 1 // CHECK1-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT14]], %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8 -// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT14]], i32 noundef 6) +// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT14]], i32 6) // CHECK1-NEXT: to label [[INVOKE_CONT15:%.*]] unwind label [[LPAD10]] // CHECK1: invoke.cont15: // CHECK1-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 @@ -1133,7 +1133,7 @@ int foobar() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP7]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], [[ARRAYINIT_BEGIN1]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done6: @@ -1151,7 +1151,7 @@ int foobar() { // CHECK1: arraydestroy.body17: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[TMP11]], [[LPAD10]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], [[ARRAYINIT_BEGIN8]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] // CHECK1: arraydestroy.done21: @@ -1165,7 +1165,7 @@ int foobar() { // CHECK1: arraydestroy.body23: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST24:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT25:%.*]], [[ARRAYDESTROY_BODY23]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT25]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST24]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT25]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT25]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE26:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT25]], [[PAD_ARRAYBEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE26]], label [[ARRAYDESTROY_DONE27]], label [[ARRAYDESTROY_BODY23]] // CHECK1: arraydestroy.done27: @@ -1179,7 +1179,7 @@ int foobar() { // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1190,7 +1190,7 @@ int foobar() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -1208,13 +1208,13 @@ int foobar() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef @_ZL3gs1, i32 noundef 5) +// CHECK1-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 5) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S1*)* @_ZN2S1D1Ev to void (i8*)*), i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* @__dso_handle) #[[ATTR3]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1228,7 +1228,7 @@ int foobar() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 @@ -1241,13 +1241,13 @@ int foobar() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.4 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN2S2C1Ei(%struct.S2* noundef @_ZL3gs2, i32 noundef 27) +// CHECK1-NEXT: call void @_ZN2S2C1Ei(%struct.S2* nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 27) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S2*)* @_ZN2S2D1Ev to void (i8*)*), i8* bitcast (%struct.S2* @_ZL3gs2 to i8*), i8* @__dso_handle) #[[ATTR3]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// CHECK1-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1255,22 +1255,22 @@ int foobar() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN2S2C2Ei(%struct.S2* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN2S2C2Ei(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// CHECK1-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK1-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2S2D2Ev(%struct.S2* noundef [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S2D2Ev(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// CHECK1-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1284,7 +1284,7 @@ int foobar() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// CHECK1-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK1-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 @@ -1304,28 +1304,28 @@ int foobar() { // CHECK1-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca %struct.S1*, align 8 // CHECK1-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // CHECK1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 noundef 1) +// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 1) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 noundef 2) +// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 2) // CHECK1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]] // CHECK1: invoke.cont2: // CHECK1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 noundef 3) +// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 3) // CHECK1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] // CHECK1: invoke.cont3: // CHECK1-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // CHECK1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 noundef 4) +// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 4) // CHECK1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] // CHECK1: invoke.cont7: // CHECK1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 noundef 5) +// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 5) // CHECK1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] // CHECK1: invoke.cont8: // CHECK1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 noundef 6) +// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 6) // CHECK1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] // CHECK1: invoke.cont9: // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] @@ -1343,7 +1343,7 @@ int foobar() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done4: @@ -1361,7 +1361,7 @@ int foobar() { // CHECK1: arraydestroy.body11: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi %struct.S1* [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] // CHECK1: arraydestroy.done15: @@ -1374,7 +1374,7 @@ int foobar() { // CHECK1: arraydestroy.body17: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] // CHECK1: arraydestroy.done21: @@ -1388,7 +1388,7 @@ int foobar() { // // // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1396,7 +1396,7 @@ int foobar() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -1414,7 +1414,7 @@ int foobar() { // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE2sm to i8*) acquire, align 8 // CHECK1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0 -// CHECK1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] +// CHECK1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] // CHECK1: init.check: // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE2sm) #[[ATTR3]] // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 @@ -1426,7 +1426,7 @@ int foobar() { // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to %struct.S1* // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK1-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef @_ZZ4mainE2sm, i32 noundef [[TMP6]]) +// CHECK1-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 [[TMP6]]) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.Smain*)* @_ZZ4mainEN5SmainD1Ev to void (i8*)*), i8* bitcast (%struct.Smain* @_ZZ4mainE2sm to i8*), i8* @__dso_handle) #[[ATTR3]] @@ -1512,7 +1512,7 @@ int foobar() { // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..6 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -1523,13 +1523,13 @@ int foobar() { // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to %struct.S1* // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK1-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef [[TMP3]], i32 noundef [[TMP6]]) +// CHECK1-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[TMP3]], i32 [[TMP6]]) // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: ret i8* [[TMP7]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// CHECK1-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1537,33 +1537,33 @@ int foobar() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..7 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.Smain* -// CHECK1-NEXT: call void @_ZZ4mainEN5SmainD1Ev(%struct.Smain* noundef [[TMP2]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZZ4mainEN5SmainD1Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[TMP2]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// CHECK1-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK1-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* noundef [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// CHECK1-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1577,7 +1577,7 @@ int foobar() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// CHECK1-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK1-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 @@ -1657,7 +1657,7 @@ int foobar() { // CHECK1: init.check: // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK1-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* (i8*)* @.__kmpc_global_ctor_..9, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..10) -// CHECK1-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef @_ZN2STI2S4E2stE, i32 noundef 23) +// CHECK1-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 23) // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S4*)* @_ZN2S4D1Ev to void (i8*)*), i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* @__dso_handle) #[[ATTR3]] // CHECK1-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8 // CHECK1-NEXT: br label [[INIT_END]] @@ -1666,19 +1666,19 @@ int foobar() { // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..9 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S4* -// CHECK1-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef [[TMP2]], i32 noundef 23) +// CHECK1-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[TMP2]], i32 23) // CHECK1-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: ret i8* [[TMP3]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// CHECK1-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1686,33 +1686,33 @@ int foobar() { // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN2S4C2Ei(%struct.S4* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK1-NEXT: call void @_ZN2S4C2Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..10 -// CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S4* -// CHECK1-NEXT: call void @_ZN2S4D1Ev(%struct.S4* noundef [[TMP2]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S4D1Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// CHECK1-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK1-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2S4D2Ev(%struct.S4* noundef [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S4D2Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// CHECK1-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1726,7 +1726,7 @@ int foobar() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// CHECK1-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK1-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 @@ -1750,13 +1750,13 @@ int foobar() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef @_ZL3gs1, i32 noundef 5) +// CHECK2-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 5) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S1*)* @_ZN2S1D1Ev to void (i8*)*), i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1764,40 +1764,40 @@ int foobar() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN2S1C2Ei(%struct.S1* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN2S1C2Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2S1D2Ev(%struct.S1* noundef [[THIS1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S1* -// CHECK2-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef [[TMP2]], i32 noundef 5) +// CHECK2-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[TMP2]], i32 5) // CHECK2-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: ret i8* [[TMP3]] // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S1* -// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[TMP2]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // @@ -1812,13 +1812,13 @@ int foobar() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK2-SAME: () #[[ATTR0]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN2S2C1Ei(%struct.S2* noundef @_ZL3gs2, i32 noundef 27) +// CHECK2-NEXT: call void @_ZN2S2C1Ei(%struct.S2* nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 27) // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S2*)* @_ZN2S2D1Ev to void (i8*)*), i8* bitcast (%struct.S2* @_ZL3gs2 to i8*), i8* @__dso_handle) #[[ATTR3]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// CHECK2-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -1826,17 +1826,17 @@ int foobar() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN2S2C2Ei(%struct.S2* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN2S2C2Ei(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// CHECK2-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK2-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2S2D2Ev(%struct.S2* noundef [[THIS1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S2D2Ev(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // @@ -1850,28 +1850,28 @@ int foobar() { // CHECK2-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // CHECK2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 noundef 1) +// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 1) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 noundef 2) +// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 2) // CHECK2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]] // CHECK2: invoke.cont2: // CHECK2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 noundef 3) +// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 3) // CHECK2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] // CHECK2: invoke.cont3: // CHECK2-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // CHECK2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 noundef 4) +// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 4) // CHECK2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] // CHECK2: invoke.cont7: // CHECK2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 noundef 5) +// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 5) // CHECK2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] // CHECK2: invoke.cont8: // CHECK2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 noundef 6) +// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 6) // CHECK2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] // CHECK2: invoke.cont9: // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] @@ -1889,7 +1889,7 @@ int foobar() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done4: @@ -1907,7 +1907,7 @@ int foobar() { // CHECK2: arraydestroy.body11: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi %struct.S1* [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] // CHECK2: arraydestroy.done15: @@ -1920,7 +1920,7 @@ int foobar() { // CHECK2: arraydestroy.body17: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] // CHECK2: arraydestroy.done21: @@ -1934,7 +1934,7 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -1942,7 +1942,7 @@ int foobar() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1950,7 +1950,7 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..3 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca [3 x %struct.S1]*, align 8 @@ -1965,34 +1965,34 @@ int foobar() { // CHECK2-NEXT: store [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // CHECK2-NEXT: [[ARRAYINIT_BEGIN1:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], i64 0, i64 0 // CHECK2-NEXT: store %struct.S1* [[ARRAYINIT_BEGIN1]], %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8 -// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_BEGIN1]], i32 noundef 1) +// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN1]], i32 1) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYINIT_BEGIN1]], i64 1 // CHECK2-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT]], %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8 -// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // CHECK2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] // CHECK2: invoke.cont3: // CHECK2-NEXT: [[ARRAYINIT_ELEMENT4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYINIT_ELEMENT]], i64 1 // CHECK2-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT4]], %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8 -// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT4]], i32 noundef 3) +// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT4]], i32 3) // CHECK2-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] // CHECK2: invoke.cont5: // CHECK2-NEXT: [[ARRAYINIT_ELEMENT7:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], i64 1 // CHECK2-NEXT: store [3 x %struct.S1]* [[ARRAYINIT_ELEMENT7]], [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // CHECK2-NEXT: [[ARRAYINIT_BEGIN8:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_ELEMENT7]], i64 0, i64 0 // CHECK2-NEXT: store %struct.S1* [[ARRAYINIT_BEGIN8]], %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8 -// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_BEGIN8]], i32 noundef 4) +// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN8]], i32 4) // CHECK2-NEXT: to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD10:%.*]] // CHECK2: invoke.cont11: // CHECK2-NEXT: [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYINIT_BEGIN8]], i64 1 // CHECK2-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT12]], %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8 -// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT12]], i32 noundef 5) +// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT12]], i32 5) // CHECK2-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD10]] // CHECK2: invoke.cont13: // CHECK2-NEXT: [[ARRAYINIT_ELEMENT14:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYINIT_ELEMENT12]], i64 1 // CHECK2-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT14]], %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8 -// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT14]], i32 noundef 6) +// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT14]], i32 6) // CHECK2-NEXT: to label [[INVOKE_CONT15:%.*]] unwind label [[LPAD10]] // CHECK2: invoke.cont15: // CHECK2-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 @@ -2010,7 +2010,7 @@ int foobar() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP7]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], [[ARRAYINIT_BEGIN1]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done6: @@ -2028,7 +2028,7 @@ int foobar() { // CHECK2: arraydestroy.body17: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[TMP11]], [[LPAD10]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], [[ARRAYINIT_BEGIN8]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] // CHECK2: arraydestroy.done21: @@ -2042,7 +2042,7 @@ int foobar() { // CHECK2: arraydestroy.body23: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST24:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT25:%.*]], [[ARRAYDESTROY_BODY23]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT25]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST24]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT25]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT25]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE26:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT25]], [[PAD_ARRAYBEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE26]], label [[ARRAYDESTROY_DONE27]], label [[ARRAYDESTROY_BODY23]] // CHECK2: arraydestroy.done27: @@ -2056,7 +2056,7 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..4 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2067,7 +2067,7 @@ int foobar() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -2093,7 +2093,7 @@ int foobar() { // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE2sm to i8*) acquire, align 8 // CHECK2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0 -// CHECK2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] +// CHECK2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] // CHECK2: init.check: // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE2sm) #[[ATTR3]] // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 @@ -2105,7 +2105,7 @@ int foobar() { // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to %struct.S1* // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP5]], i32 0, i32 0 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK2-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef @_ZZ4mainE2sm, i32 noundef [[TMP6]]) +// CHECK2-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 [[TMP6]]) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK2: invoke.cont: // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.Smain*)* @_ZZ4mainEN5SmainD1Ev to void (i8*)*), i8* bitcast (%struct.Smain* @_ZZ4mainE2sm to i8*), i8* @__dso_handle) #[[ATTR3]] @@ -2191,7 +2191,7 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..6 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) @@ -2202,13 +2202,13 @@ int foobar() { // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to %struct.S1* // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP5]], i32 0, i32 0 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK2-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef [[TMP3]], i32 noundef [[TMP6]]) +// CHECK2-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[TMP3]], i32 [[TMP6]]) // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: ret i8* [[TMP7]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// CHECK2-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2216,28 +2216,28 @@ int foobar() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..7 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.Smain* -// CHECK2-NEXT: call void @_ZZ4mainEN5SmainD1Ev(%struct.Smain* noundef [[TMP2]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZZ4mainEN5SmainD1Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[TMP2]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// CHECK2-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK2-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* noundef [[THIS1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // @@ -2311,7 +2311,7 @@ int foobar() { // CHECK2: init.check: // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) // CHECK2-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* (i8*)* @.__kmpc_global_ctor_..9, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..10) -// CHECK2-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef @_ZN2STI2S4E2stE, i32 noundef 23) +// CHECK2-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 23) // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S4*)* @_ZN2S4D1Ev to void (i8*)*), i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* @__dso_handle) #[[ATTR3]] // CHECK2-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8 // CHECK2-NEXT: br label [[INIT_END]] @@ -2320,19 +2320,19 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..9 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S4* -// CHECK2-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef [[TMP2]], i32 noundef 23) +// CHECK2-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[TMP2]], i32 23) // CHECK2-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: ret i8* [[TMP3]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// CHECK2-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2340,33 +2340,33 @@ int foobar() { // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: call void @_ZN2S4C2Ei(%struct.S4* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK2-NEXT: call void @_ZN2S4C2Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..10 -// CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S4* -// CHECK2-NEXT: call void @_ZN2S4D1Ev(%struct.S4* noundef [[TMP2]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S4D1Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// CHECK2-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK2-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2S4D2Ev(%struct.S4* noundef [[THIS1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S4D2Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2380,7 +2380,7 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 @@ -2391,7 +2391,7 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// CHECK2-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2405,7 +2405,7 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// CHECK2-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK2-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 @@ -2416,7 +2416,7 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// CHECK2-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2430,7 +2430,7 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// CHECK2-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK2-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 @@ -2441,7 +2441,7 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// CHECK2-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2455,7 +2455,7 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// CHECK2-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK2-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 @@ -2479,13 +2479,13 @@ int foobar() { // SIMD1-LABEL: define {{[^@]+}}@__cxx_global_var_init // SIMD1-SAME: () #[[ATTR0:[0-9]+]] { // SIMD1-NEXT: entry: -// SIMD1-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef @_ZL3gs1, i32 noundef 5) +// SIMD1-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 5) // SIMD1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S1*)* @_ZN2S1D1Ev to void (i8*)*), i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]] // SIMD1-NEXT: ret void // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// SIMD1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// SIMD1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2493,30 +2493,30 @@ int foobar() { // SIMD1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // SIMD1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // SIMD1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD1-NEXT: call void @_ZN2S1C2Ei(%struct.S1* noundef [[THIS1]], i32 noundef [[TMP0]]) +// SIMD1-NEXT: call void @_ZN2S1C2Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // SIMD1-NEXT: ret void // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// SIMD1-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// SIMD1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // SIMD1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// SIMD1-NEXT: call void @_ZN2S1D2Ev(%struct.S1* noundef [[THIS1]]) #[[ATTR3]] +// SIMD1-NEXT: call void @_ZN2S1D2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // SIMD1-NEXT: ret void // // // SIMD1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // SIMD1-SAME: () #[[ATTR0]] { // SIMD1-NEXT: entry: -// SIMD1-NEXT: call void @_ZN2S2C1Ei(%struct.S2* noundef @_ZL3gs2, i32 noundef 27) +// SIMD1-NEXT: call void @_ZN2S2C1Ei(%struct.S2* nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 27) // SIMD1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S2*)* @_ZN2S2D1Ev to void (i8*)*), i8* bitcast (%struct.S2* @_ZL3gs2 to i8*), i8* @__dso_handle) #[[ATTR3]] // SIMD1-NEXT: ret void // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// SIMD1-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// SIMD1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2524,17 +2524,17 @@ int foobar() { // SIMD1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // SIMD1-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 // SIMD1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD1-NEXT: call void @_ZN2S2C2Ei(%struct.S2* noundef [[THIS1]], i32 noundef [[TMP0]]) +// SIMD1-NEXT: call void @_ZN2S2C2Ei(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]], i32 [[TMP0]]) // SIMD1-NEXT: ret void // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// SIMD1-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD1-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 // SIMD1-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// SIMD1-NEXT: call void @_ZN2S2D2Ev(%struct.S2* noundef [[THIS1]]) #[[ATTR3]] +// SIMD1-NEXT: call void @_ZN2S2D2Ev(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]] // SIMD1-NEXT: ret void // // @@ -2548,28 +2548,28 @@ int foobar() { // SIMD1-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca %struct.S1*, align 8 // SIMD1-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // SIMD1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 noundef 1) +// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 1) // SIMD1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // SIMD1: invoke.cont: // SIMD1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 noundef 2) +// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 2) // SIMD1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]] // SIMD1: invoke.cont2: // SIMD1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 noundef 3) +// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 3) // SIMD1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] // SIMD1: invoke.cont3: // SIMD1-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // SIMD1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 noundef 4) +// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 4) // SIMD1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] // SIMD1: invoke.cont7: // SIMD1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 noundef 5) +// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 5) // SIMD1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] // SIMD1: invoke.cont8: // SIMD1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 noundef 6) +// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 6) // SIMD1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] // SIMD1: invoke.cont9: // SIMD1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] @@ -2587,7 +2587,7 @@ int foobar() { // SIMD1: arraydestroy.body: // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0) // SIMD1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] // SIMD1: arraydestroy.done4: @@ -2605,7 +2605,7 @@ int foobar() { // SIMD1: arraydestroy.body11: // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi %struct.S1* [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 -// SIMD1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] +// SIMD1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] // SIMD1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0) // SIMD1-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] // SIMD1: arraydestroy.done15: @@ -2618,7 +2618,7 @@ int foobar() { // SIMD1: arraydestroy.body17: // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// SIMD1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// SIMD1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // SIMD1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0) // SIMD1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] // SIMD1: arraydestroy.done21: @@ -2632,7 +2632,7 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// SIMD1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// SIMD1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // SIMD1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -2640,7 +2640,7 @@ int foobar() { // SIMD1: arraydestroy.body: // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0) // SIMD1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD1: arraydestroy.done1: @@ -2664,7 +2664,7 @@ int foobar() { // SIMD1-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] // SIMD1: init: // SIMD1-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* @_ZL3gs1, i32 0, i32 0), align 4 -// SIMD1-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef @_ZZ4mainE2sm, i32 noundef [[TMP2]]) +// SIMD1-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 [[TMP2]]) // SIMD1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // SIMD1: invoke.cont: // SIMD1-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.Smain*)* @_ZZ4mainEN5SmainD1Ev to void (i8*)*), i8* bitcast (%struct.Smain* @_ZZ4mainE2sm to i8*), i8* @__dso_handle) #[[ATTR3]] @@ -2726,7 +2726,7 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// SIMD1-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2734,17 +2734,17 @@ int foobar() { // SIMD1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // SIMD1-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 // SIMD1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* noundef [[THIS1]], i32 noundef [[TMP0]]) +// SIMD1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]], i32 [[TMP0]]) // SIMD1-NEXT: ret void // // // SIMD1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// SIMD1-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// SIMD1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD1-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 // SIMD1-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* noundef [[THIS1]]) #[[ATTR3]] +// SIMD1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] // SIMD1-NEXT: ret void // // @@ -2794,7 +2794,7 @@ int foobar() { // SIMD1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 // SIMD1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]] // SIMD1: init.check: -// SIMD1-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef @_ZN2STI2S4E2stE, i32 noundef 23) +// SIMD1-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 23) // SIMD1-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S4*)* @_ZN2S4D1Ev to void (i8*)*), i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* @__dso_handle) #[[ATTR3]] // SIMD1-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8 // SIMD1-NEXT: br label [[INIT_END]] @@ -2803,7 +2803,7 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// SIMD1-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// SIMD1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2811,22 +2811,22 @@ int foobar() { // SIMD1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // SIMD1-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 // SIMD1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD1-NEXT: call void @_ZN2S4C2Ei(%struct.S4* noundef [[THIS1]], i32 noundef [[TMP0]]) +// SIMD1-NEXT: call void @_ZN2S4C2Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]], i32 [[TMP0]]) // SIMD1-NEXT: ret void // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// SIMD1-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD1-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 // SIMD1-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// SIMD1-NEXT: call void @_ZN2S4D2Ev(%struct.S4* noundef [[THIS1]]) #[[ATTR3]] +// SIMD1-NEXT: call void @_ZN2S4D2Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] // SIMD1-NEXT: ret void // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// SIMD1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2840,7 +2840,7 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// SIMD1-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 @@ -2851,7 +2851,7 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// SIMD1-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2865,7 +2865,7 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// SIMD1-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD1-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 @@ -2876,7 +2876,7 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// SIMD1-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// SIMD1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2890,7 +2890,7 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// SIMD1-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// SIMD1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD1-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 @@ -2901,7 +2901,7 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// SIMD1-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -2915,7 +2915,7 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// SIMD1-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD1-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 @@ -2937,179 +2937,179 @@ int foobar() { // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init // SIMD2-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG115:![0-9]+]] { // SIMD2-NEXT: entry: -// SIMD2-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef @_ZL3gs1, i32 noundef 5), !dbg [[DBG118:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S1*)* @_ZN2S1D1Ev to void (i8*)*), i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG120:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG121:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 5), !dbg [[DBG119:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S1*)* @_ZN2S1D1Ev to void (i8*)*), i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG121:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG122:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// SIMD2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG122:![0-9]+]] { +// SIMD2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG123:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META123:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META124:![0-9]+]], metadata !DIExpression()), !dbg [[DBG126:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG128:![0-9]+]] -// SIMD2-NEXT: call void @_ZN2S1C2Ei(%struct.S1* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG128]] -// SIMD2-NEXT: ret void, !dbg [[DBG129:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S1C2Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG129]] +// SIMD2-NEXT: ret void, !dbg [[DBG130:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// SIMD2-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG130:![0-9]+]] { +// SIMD2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META131:![0-9]+]], metadata !DIExpression()), !dbg [[DBG132:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG133:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @_ZN2S1D2Ev(%struct.S1* noundef [[THIS1]]) #[[ATTR3]], !dbg [[DBG133:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG134:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S1D2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG134:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG135:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG135:![0-9]+]] { +// SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG136:![0-9]+]] { // SIMD2-NEXT: entry: -// SIMD2-NEXT: call void @_ZN2S2C1Ei(%struct.S2* noundef @_ZL3gs2, i32 noundef 27), !dbg [[DBG136:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S2*)* @_ZN2S2D1Ev to void (i8*)*), i8* bitcast (%struct.S2* @_ZL3gs2 to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG138:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG139:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S2C1Ei(%struct.S2* nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 27), !dbg [[DBG137:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S2*)* @_ZN2S2D1Ev to void (i8*)*), i8* bitcast (%struct.S2* @_ZL3gs2 to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG139:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG140:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// SIMD2-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG140:![0-9]+]] { +// SIMD2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG141:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META141:![0-9]+]], metadata !DIExpression()), !dbg [[DBG143:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META142:![0-9]+]], metadata !DIExpression()), !dbg [[DBG144:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META144:![0-9]+]], metadata !DIExpression()), !dbg [[DBG145:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META145:![0-9]+]], metadata !DIExpression()), !dbg [[DBG146:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG146:![0-9]+]] -// SIMD2-NEXT: call void @_ZN2S2C2Ei(%struct.S2* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG146]] -// SIMD2-NEXT: ret void, !dbg [[DBG147:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG147:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S2C2Ei(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG147]] +// SIMD2-NEXT: ret void, !dbg [[DBG148:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// SIMD2-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG148:![0-9]+]] { +// SIMD2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG149:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD2-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META149:![0-9]+]], metadata !DIExpression()), !dbg [[DBG150:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META150:![0-9]+]], metadata !DIExpression()), !dbg [[DBG151:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @_ZN2S2D2Ev(%struct.S2* noundef [[THIS1]]) #[[ATTR3]], !dbg [[DBG151:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG152:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S2D2Ev(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG152:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG153:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// SIMD2-SAME: () #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG153:![0-9]+]] { +// SIMD2-SAME: () #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG154:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca [3 x %struct.S1]*, align 8 // SIMD2-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca %struct.S1*, align 8 // SIMD2-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // SIMD2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // SIMD2-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca %struct.S1*, align 8 -// SIMD2-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154:![0-9]+]] -// SIMD2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156:![0-9]+]] -// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 noundef 1) -// SIMD2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG157:![0-9]+]] +// SIMD2-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155:![0-9]+]] +// SIMD2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157:![0-9]+]] +// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 1) +// SIMD2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG158:![0-9]+]] // SIMD2: invoke.cont: -// SIMD2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] -// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 noundef 2) -// SIMD2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG158:![0-9]+]] +// SIMD2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] +// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 2) +// SIMD2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]] // SIMD2: invoke.cont2: -// SIMD2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] -// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 noundef 3) -// SIMD2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]] +// SIMD2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] +// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 3) +// SIMD2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG160:![0-9]+]] // SIMD2: invoke.cont3: -// SIMD2-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] -// SIMD2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160:![0-9]+]] -// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 noundef 4) -// SIMD2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG161:![0-9]+]] +// SIMD2-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]] +// SIMD2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161:![0-9]+]] +// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 4) +// SIMD2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG162:![0-9]+]] // SIMD2: invoke.cont7: -// SIMD2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] -// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 noundef 5) -// SIMD2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG162:![0-9]+]] +// SIMD2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] +// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 5) +// SIMD2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]] // SIMD2: invoke.cont8: -// SIMD2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] -// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 noundef 6) -// SIMD2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]] +// SIMD2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] +// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 6) +// SIMD2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG164:![0-9]+]] // SIMD2: invoke.cont9: -// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG164:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG164]] +// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG165:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG165]] // SIMD2: lpad: // SIMD2-NEXT: [[TMP1:%.*]] = landingpad { i8*, i32 } -// SIMD2-NEXT: cleanup, !dbg [[DBG165:![0-9]+]] -// SIMD2-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0, !dbg [[DBG165]] -// SIMD2-NEXT: store i8* [[TMP2]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG165]] -// SIMD2-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 1, !dbg [[DBG165]] -// SIMD2-NEXT: store i32 [[TMP3]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] -// SIMD2-NEXT: [[TMP4:%.*]] = load %struct.S1*, %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] -// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), [[TMP4]], !dbg [[DBG156]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG156]] +// SIMD2-NEXT: cleanup, !dbg [[DBG166:![0-9]+]] +// SIMD2-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0, !dbg [[DBG166]] +// SIMD2-NEXT: store i8* [[TMP2]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG166]] +// SIMD2-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 1, !dbg [[DBG166]] +// SIMD2-NEXT: store i32 [[TMP3]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]] +// SIMD2-NEXT: [[TMP4:%.*]] = load %struct.S1*, %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] +// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), [[TMP4]], !dbg [[DBG157]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG157]] // SIMD2: arraydestroy.body: -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG156]] -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG156]] -// SIMD2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG156]] -// SIMD2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG156]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG156]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG157]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG157]] +// SIMD2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG157]] +// SIMD2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG157]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG157]] // SIMD2: arraydestroy.done4: -// SIMD2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG156]] +// SIMD2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG157]] // SIMD2: lpad6: // SIMD2-NEXT: [[TMP5:%.*]] = landingpad { i8*, i32 } -// SIMD2-NEXT: cleanup, !dbg [[DBG165]] -// SIMD2-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 0, !dbg [[DBG165]] -// SIMD2-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG165]] -// SIMD2-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1, !dbg [[DBG165]] -// SIMD2-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] -// SIMD2-NEXT: [[TMP8:%.*]] = load %struct.S1*, %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] -// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), [[TMP8]], !dbg [[DBG160]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG160]] +// SIMD2-NEXT: cleanup, !dbg [[DBG166]] +// SIMD2-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 0, !dbg [[DBG166]] +// SIMD2-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG166]] +// SIMD2-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1, !dbg [[DBG166]] +// SIMD2-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]] +// SIMD2-NEXT: [[TMP8:%.*]] = load %struct.S1*, %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] +// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), [[TMP8]], !dbg [[DBG161]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG161]] // SIMD2: arraydestroy.body11: -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi %struct.S1* [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG160]] -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG160]] -// SIMD2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG160]] -// SIMD2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), !dbg [[DBG160]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG160]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi %struct.S1* [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG161]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG161]] +// SIMD2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG161]] +// SIMD2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), !dbg [[DBG161]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG161]] // SIMD2: arraydestroy.done15: -// SIMD2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG160]] +// SIMD2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG161]] // SIMD2: ehcleanup: -// SIMD2-NEXT: [[TMP9:%.*]] = load [3 x %struct.S1]*, [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] -// SIMD2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[TMP9]], i64 0, i64 0, !dbg [[DBG154]] -// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), [[PAD_ARRAYEND]], !dbg [[DBG154]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG154]] +// SIMD2-NEXT: [[TMP9:%.*]] = load [3 x %struct.S1]*, [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]] +// SIMD2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[TMP9]], i64 0, i64 0, !dbg [[DBG155]] +// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), [[PAD_ARRAYEND]], !dbg [[DBG155]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG155]] // SIMD2: arraydestroy.body17: -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG154]] -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG154]] -// SIMD2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG154]] -// SIMD2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG154]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG154]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG155]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG155]] +// SIMD2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG155]] +// SIMD2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG155]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG155]] // SIMD2: arraydestroy.done21: -// SIMD2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG154]] +// SIMD2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG155]] // SIMD2: eh.resume: -// SIMD2-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG154]] -// SIMD2-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG154]] -// SIMD2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0, !dbg [[DBG154]] -// SIMD2-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG154]] -// SIMD2-NEXT: resume { i8*, i32 } [[LPAD_VAL22]], !dbg [[DBG154]] +// SIMD2-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG155]] +// SIMD2-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG155]] +// SIMD2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0, !dbg [[DBG155]] +// SIMD2-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG155]] +// SIMD2-NEXT: resume { i8*, i32 } [[LPAD_VAL22]], !dbg [[DBG155]] // // // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// SIMD2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG166:![0-9]+]] { +// SIMD2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG167:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // SIMD2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG171:![0-9]+]] -// SIMD2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG171]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG172:![0-9]+]] +// SIMD2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG172]] // SIMD2: arraydestroy.body: -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG171]] -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG171]] -// SIMD2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG171]] -// SIMD2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), !dbg [[DBG171]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG171]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG172]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG172]] +// SIMD2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG172]] +// SIMD2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), !dbg [[DBG172]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG172]] // SIMD2: arraydestroy.done1: -// SIMD2-NEXT: ret void, !dbg [[DBG171]] +// SIMD2-NEXT: ret void, !dbg [[DBG172]] // // // SIMD2-LABEL: define {{[^@]+}}@main @@ -3120,315 +3120,315 @@ int foobar() { // SIMD2-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // SIMD2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[RES]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG173:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE2sm to i8*) acquire, align 8, !dbg [[DBG174:![0-9]+]] -// SIMD2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG174]] -// SIMD2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG174]], !prof [[PROF175:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[RES]], metadata [[META173:![0-9]+]], metadata !DIExpression()), !dbg [[DBG174:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE2sm to i8*) acquire, align 8, !dbg [[DBG175:![0-9]+]] +// SIMD2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG175]] +// SIMD2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG175]], !prof [[PROF176:![0-9]+]] // SIMD2: init.check: -// SIMD2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG174]] -// SIMD2-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG174]] +// SIMD2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG175]] +// SIMD2-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG175]] // SIMD2: init: -// SIMD2-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* @_ZL3gs1, i32 0, i32 0), align 4, !dbg [[DBG176:![0-9]+]] -// SIMD2-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef @_ZZ4mainE2sm, i32 noundef [[TMP2]]) -// SIMD2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG177:![0-9]+]] +// SIMD2-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* @_ZL3gs1, i32 0, i32 0), align 4, !dbg [[DBG177:![0-9]+]] +// SIMD2-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 [[TMP2]]) +// SIMD2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG178:![0-9]+]] // SIMD2: invoke.cont: -// SIMD2-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.Smain*)* @_ZZ4mainEN5SmainD1Ev to void (i8*)*), i8* bitcast (%struct.Smain* @_ZZ4mainE2sm to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG174]] -// SIMD2-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD2-NEXT: br label [[INIT_END]], !dbg [[DBG174]] +// SIMD2-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.Smain*)* @_ZZ4mainEN5SmainD1Ev to void (i8*)*), i8* bitcast (%struct.Smain* @_ZZ4mainE2sm to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG175]] +// SIMD2-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD2-NEXT: br label [[INIT_END]], !dbg [[DBG175]] // SIMD2: init.end: -// SIMD2-NEXT: [[TMP4:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S3:%.*]], %struct.S3* @_ZN6Static1sE, i32 0, i32 0), align 4, !dbg [[DBG178:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP4]], i32* [[RES]], align 4, !dbg [[DBG179:![0-9]+]] -// SIMD2-NEXT: [[TMP5:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SMAIN:%.*]], %struct.Smain* @_ZZ4mainE2sm, i32 0, i32 0), align 8, !dbg [[DBG180:![0-9]+]] -// SIMD2-NEXT: [[TMP6:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG181:![0-9]+]] -// SIMD2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG181]] -// SIMD2-NEXT: store i32 [[ADD]], i32* [[RES]], align 4, !dbg [[DBG181]] -// SIMD2-NEXT: [[TMP7:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1]], %struct.S1* @_ZL3gs1, i32 0, i32 0), align 4, !dbg [[DBG182:![0-9]+]] -// SIMD2-NEXT: [[TMP8:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG183:![0-9]+]] -// SIMD2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG183]] -// SIMD2-NEXT: store i32 [[ADD1]], i32* [[RES]], align 4, !dbg [[DBG183]] -// SIMD2-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S2:%.*]], %struct.S2* @_ZL3gs2, i32 0, i32 0), align 8, !dbg [[DBG184:![0-9]+]] -// SIMD2-NEXT: [[TMP10:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG185:![0-9]+]] -// SIMD2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG185]] -// SIMD2-NEXT: store i32 [[ADD2]], i32* [[RES]], align 4, !dbg [[DBG185]] -// SIMD2-NEXT: [[TMP11:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S5:%.*]], %struct.S5* @gs3, i32 0, i32 0), align 4, !dbg [[DBG186:![0-9]+]] -// SIMD2-NEXT: [[TMP12:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG187:![0-9]+]] -// SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG187]] -// SIMD2-NEXT: store i32 [[ADD3]], i32* [[RES]], align 4, !dbg [[DBG187]] -// SIMD2-NEXT: [[TMP13:%.*]] = load i32, i32* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1, i32 0), align 4, !dbg [[DBG188:![0-9]+]] -// SIMD2-NEXT: [[TMP14:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG189:![0-9]+]] -// SIMD2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG189]] -// SIMD2-NEXT: store i32 [[ADD4]], i32* [[RES]], align 4, !dbg [[DBG189]] -// SIMD2-NEXT: [[TMP15:%.*]] = load i32, i32* @_ZN2STIiE2stE, align 4, !dbg [[DBG190:![0-9]+]] -// SIMD2-NEXT: [[TMP16:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG191:![0-9]+]] -// SIMD2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG191]] -// SIMD2-NEXT: store i32 [[ADD5]], i32* [[RES]], align 4, !dbg [[DBG191]] -// SIMD2-NEXT: [[TMP17:%.*]] = load float, float* @_ZN2STIfE2stE, align 4, !dbg [[DBG192:![0-9]+]] -// SIMD2-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG192]] -// SIMD2-NEXT: [[TMP18:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG193:![0-9]+]] -// SIMD2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG193]] -// SIMD2-NEXT: store i32 [[ADD6]], i32* [[RES]], align 4, !dbg [[DBG193]] -// SIMD2-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S4:%.*]], %struct.S4* @_ZN2STI2S4E2stE, i32 0, i32 0), align 4, !dbg [[DBG194:![0-9]+]] -// SIMD2-NEXT: [[TMP20:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG195:![0-9]+]] -// SIMD2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG195]] -// SIMD2-NEXT: store i32 [[ADD7]], i32* [[RES]], align 4, !dbg [[DBG195]] -// SIMD2-NEXT: [[TMP21:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG196:![0-9]+]] -// SIMD2-NEXT: ret i32 [[TMP21]], !dbg [[DBG197:![0-9]+]] +// SIMD2-NEXT: [[TMP4:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S3:%.*]], %struct.S3* @_ZN6Static1sE, i32 0, i32 0), align 4, !dbg [[DBG179:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP4]], i32* [[RES]], align 4, !dbg [[DBG180:![0-9]+]] +// SIMD2-NEXT: [[TMP5:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SMAIN:%.*]], %struct.Smain* @_ZZ4mainE2sm, i32 0, i32 0), align 8, !dbg [[DBG181:![0-9]+]] +// SIMD2-NEXT: [[TMP6:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG182:![0-9]+]] +// SIMD2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG182]] +// SIMD2-NEXT: store i32 [[ADD]], i32* [[RES]], align 4, !dbg [[DBG182]] +// SIMD2-NEXT: [[TMP7:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1]], %struct.S1* @_ZL3gs1, i32 0, i32 0), align 4, !dbg [[DBG183:![0-9]+]] +// SIMD2-NEXT: [[TMP8:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG184:![0-9]+]] +// SIMD2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG184]] +// SIMD2-NEXT: store i32 [[ADD1]], i32* [[RES]], align 4, !dbg [[DBG184]] +// SIMD2-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S2:%.*]], %struct.S2* @_ZL3gs2, i32 0, i32 0), align 8, !dbg [[DBG185:![0-9]+]] +// SIMD2-NEXT: [[TMP10:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG186:![0-9]+]] +// SIMD2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG186]] +// SIMD2-NEXT: store i32 [[ADD2]], i32* [[RES]], align 4, !dbg [[DBG186]] +// SIMD2-NEXT: [[TMP11:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S5:%.*]], %struct.S5* @gs3, i32 0, i32 0), align 4, !dbg [[DBG187:![0-9]+]] +// SIMD2-NEXT: [[TMP12:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG188:![0-9]+]] +// SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG188]] +// SIMD2-NEXT: store i32 [[ADD3]], i32* [[RES]], align 4, !dbg [[DBG188]] +// SIMD2-NEXT: [[TMP13:%.*]] = load i32, i32* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1, i32 0), align 4, !dbg [[DBG189:![0-9]+]] +// SIMD2-NEXT: [[TMP14:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG190:![0-9]+]] +// SIMD2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG190]] +// SIMD2-NEXT: store i32 [[ADD4]], i32* [[RES]], align 4, !dbg [[DBG190]] +// SIMD2-NEXT: [[TMP15:%.*]] = load i32, i32* @_ZN2STIiE2stE, align 4, !dbg [[DBG191:![0-9]+]] +// SIMD2-NEXT: [[TMP16:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG192:![0-9]+]] +// SIMD2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG192]] +// SIMD2-NEXT: store i32 [[ADD5]], i32* [[RES]], align 4, !dbg [[DBG192]] +// SIMD2-NEXT: [[TMP17:%.*]] = load float, float* @_ZN2STIfE2stE, align 4, !dbg [[DBG193:![0-9]+]] +// SIMD2-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG193]] +// SIMD2-NEXT: [[TMP18:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG194:![0-9]+]] +// SIMD2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG194]] +// SIMD2-NEXT: store i32 [[ADD6]], i32* [[RES]], align 4, !dbg [[DBG194]] +// SIMD2-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S4:%.*]], %struct.S4* @_ZN2STI2S4E2stE, i32 0, i32 0), align 4, !dbg [[DBG195:![0-9]+]] +// SIMD2-NEXT: [[TMP20:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG196:![0-9]+]] +// SIMD2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG196]] +// SIMD2-NEXT: store i32 [[ADD7]], i32* [[RES]], align 4, !dbg [[DBG196]] +// SIMD2-NEXT: [[TMP21:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG197:![0-9]+]] +// SIMD2-NEXT: ret i32 [[TMP21]], !dbg [[DBG198:![0-9]+]] // SIMD2: lpad: // SIMD2-NEXT: [[TMP22:%.*]] = landingpad { i8*, i32 } -// SIMD2-NEXT: cleanup, !dbg [[DBG198:![0-9]+]] -// SIMD2-NEXT: [[TMP23:%.*]] = extractvalue { i8*, i32 } [[TMP22]], 0, !dbg [[DBG198]] -// SIMD2-NEXT: store i8* [[TMP23]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG198]] -// SIMD2-NEXT: [[TMP24:%.*]] = extractvalue { i8*, i32 } [[TMP22]], 1, !dbg [[DBG198]] -// SIMD2-NEXT: store i32 [[TMP24]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG198]] -// SIMD2-NEXT: call void @__cxa_guard_abort(i64* @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG174]] +// SIMD2-NEXT: cleanup, !dbg [[DBG199:![0-9]+]] +// SIMD2-NEXT: [[TMP23:%.*]] = extractvalue { i8*, i32 } [[TMP22]], 0, !dbg [[DBG199]] +// SIMD2-NEXT: store i8* [[TMP23]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG199]] +// SIMD2-NEXT: [[TMP24:%.*]] = extractvalue { i8*, i32 } [[TMP22]], 1, !dbg [[DBG199]] +// SIMD2-NEXT: store i32 [[TMP24]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG199]] +// SIMD2-NEXT: call void @__cxa_guard_abort(i64* @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG175]] // SIMD2: eh.resume: -// SIMD2-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG174]] -// SIMD2-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG174]] -// SIMD2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0, !dbg [[DBG174]] -// SIMD2-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG174]] -// SIMD2-NEXT: resume { i8*, i32 } [[LPAD_VAL8]], !dbg [[DBG174]] +// SIMD2-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG175]] +// SIMD2-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG175]] +// SIMD2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0, !dbg [[DBG175]] +// SIMD2-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG175]] +// SIMD2-NEXT: resume { i8*, i32 } [[LPAD_VAL8]], !dbg [[DBG175]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// SIMD2-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG199:![0-9]+]] { +// SIMD2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG200:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META200:![0-9]+]], metadata !DIExpression()), !dbg [[DBG202:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META201:![0-9]+]], metadata !DIExpression()), !dbg [[DBG203:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META203:![0-9]+]], metadata !DIExpression()), !dbg [[DBG204:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META204:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG205:![0-9]+]] -// SIMD2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG205]] -// SIMD2-NEXT: ret void, !dbg [[DBG206:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG206:![0-9]+]] +// SIMD2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG206]] +// SIMD2-NEXT: ret void, !dbg [[DBG207:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// SIMD2-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG207:![0-9]+]] { +// SIMD2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG208:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD2-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META208:![0-9]+]], metadata !DIExpression()), !dbg [[DBG209:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META209:![0-9]+]], metadata !DIExpression()), !dbg [[DBG210:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* noundef [[THIS1]]) #[[ATTR3]], !dbg [[DBG210:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG211:![0-9]+]] +// SIMD2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG211:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG212:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_Z6foobarv -// SIMD2-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG212:![0-9]+]] { +// SIMD2-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG213:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[RES:%.*]] = alloca i32, align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[RES]], metadata [[META213:![0-9]+]], metadata !DIExpression()), !dbg [[DBG214:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S3:%.*]], %struct.S3* @_ZN6Static1sE, i32 0, i32 0), align 4, !dbg [[DBG215:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP0]], i32* [[RES]], align 4, !dbg [[DBG216:![0-9]+]] -// SIMD2-NEXT: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* @_ZL3gs1, i32 0, i32 0), align 4, !dbg [[DBG217:![0-9]+]] -// SIMD2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG218:![0-9]+]] -// SIMD2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG218]] -// SIMD2-NEXT: store i32 [[ADD]], i32* [[RES]], align 4, !dbg [[DBG218]] -// SIMD2-NEXT: [[TMP3:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S2:%.*]], %struct.S2* @_ZL3gs2, i32 0, i32 0), align 8, !dbg [[DBG219:![0-9]+]] -// SIMD2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG220:![0-9]+]] -// SIMD2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG220]] -// SIMD2-NEXT: store i32 [[ADD1]], i32* [[RES]], align 4, !dbg [[DBG220]] -// SIMD2-NEXT: [[TMP5:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S5:%.*]], %struct.S5* @gs3, i32 0, i32 0), align 4, !dbg [[DBG221:![0-9]+]] -// SIMD2-NEXT: [[TMP6:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG222:![0-9]+]] -// SIMD2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG222]] -// SIMD2-NEXT: store i32 [[ADD2]], i32* [[RES]], align 4, !dbg [[DBG222]] -// SIMD2-NEXT: [[TMP7:%.*]] = load i32, i32* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1, i32 0), align 4, !dbg [[DBG223:![0-9]+]] -// SIMD2-NEXT: [[TMP8:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG224:![0-9]+]] -// SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG224]] -// SIMD2-NEXT: store i32 [[ADD3]], i32* [[RES]], align 4, !dbg [[DBG224]] -// SIMD2-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZN2STIiE2stE, align 4, !dbg [[DBG225:![0-9]+]] -// SIMD2-NEXT: [[TMP10:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG226:![0-9]+]] -// SIMD2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG226]] -// SIMD2-NEXT: store i32 [[ADD4]], i32* [[RES]], align 4, !dbg [[DBG226]] -// SIMD2-NEXT: [[TMP11:%.*]] = load float, float* @_ZN2STIfE2stE, align 4, !dbg [[DBG227:![0-9]+]] -// SIMD2-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG227]] -// SIMD2-NEXT: [[TMP12:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG228:![0-9]+]] -// SIMD2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG228]] -// SIMD2-NEXT: store i32 [[ADD5]], i32* [[RES]], align 4, !dbg [[DBG228]] -// SIMD2-NEXT: [[TMP13:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S4:%.*]], %struct.S4* @_ZN2STI2S4E2stE, i32 0, i32 0), align 4, !dbg [[DBG229:![0-9]+]] -// SIMD2-NEXT: [[TMP14:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG230:![0-9]+]] -// SIMD2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG230]] -// SIMD2-NEXT: store i32 [[ADD6]], i32* [[RES]], align 4, !dbg [[DBG230]] -// SIMD2-NEXT: [[TMP15:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG231:![0-9]+]] -// SIMD2-NEXT: ret i32 [[TMP15]], !dbg [[DBG232:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[RES]], metadata [[META214:![0-9]+]], metadata !DIExpression()), !dbg [[DBG215:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S3:%.*]], %struct.S3* @_ZN6Static1sE, i32 0, i32 0), align 4, !dbg [[DBG216:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP0]], i32* [[RES]], align 4, !dbg [[DBG217:![0-9]+]] +// SIMD2-NEXT: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* @_ZL3gs1, i32 0, i32 0), align 4, !dbg [[DBG218:![0-9]+]] +// SIMD2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG219:![0-9]+]] +// SIMD2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG219]] +// SIMD2-NEXT: store i32 [[ADD]], i32* [[RES]], align 4, !dbg [[DBG219]] +// SIMD2-NEXT: [[TMP3:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S2:%.*]], %struct.S2* @_ZL3gs2, i32 0, i32 0), align 8, !dbg [[DBG220:![0-9]+]] +// SIMD2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG221:![0-9]+]] +// SIMD2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG221]] +// SIMD2-NEXT: store i32 [[ADD1]], i32* [[RES]], align 4, !dbg [[DBG221]] +// SIMD2-NEXT: [[TMP5:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S5:%.*]], %struct.S5* @gs3, i32 0, i32 0), align 4, !dbg [[DBG222:![0-9]+]] +// SIMD2-NEXT: [[TMP6:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG223:![0-9]+]] +// SIMD2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG223]] +// SIMD2-NEXT: store i32 [[ADD2]], i32* [[RES]], align 4, !dbg [[DBG223]] +// SIMD2-NEXT: [[TMP7:%.*]] = load i32, i32* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1, i32 0), align 4, !dbg [[DBG224:![0-9]+]] +// SIMD2-NEXT: [[TMP8:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG225:![0-9]+]] +// SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG225]] +// SIMD2-NEXT: store i32 [[ADD3]], i32* [[RES]], align 4, !dbg [[DBG225]] +// SIMD2-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZN2STIiE2stE, align 4, !dbg [[DBG226:![0-9]+]] +// SIMD2-NEXT: [[TMP10:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG227:![0-9]+]] +// SIMD2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG227]] +// SIMD2-NEXT: store i32 [[ADD4]], i32* [[RES]], align 4, !dbg [[DBG227]] +// SIMD2-NEXT: [[TMP11:%.*]] = load float, float* @_ZN2STIfE2stE, align 4, !dbg [[DBG228:![0-9]+]] +// SIMD2-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG228]] +// SIMD2-NEXT: [[TMP12:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG229:![0-9]+]] +// SIMD2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG229]] +// SIMD2-NEXT: store i32 [[ADD5]], i32* [[RES]], align 4, !dbg [[DBG229]] +// SIMD2-NEXT: [[TMP13:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S4:%.*]], %struct.S4* @_ZN2STI2S4E2stE, i32 0, i32 0), align 4, !dbg [[DBG230:![0-9]+]] +// SIMD2-NEXT: [[TMP14:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG231:![0-9]+]] +// SIMD2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG231]] +// SIMD2-NEXT: store i32 [[ADD6]], i32* [[RES]], align 4, !dbg [[DBG231]] +// SIMD2-NEXT: [[TMP15:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG232:![0-9]+]] +// SIMD2-NEXT: ret i32 [[TMP15]], !dbg [[DBG233:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 -// SIMD2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG233:![0-9]+]] { +// SIMD2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG234:![0-9]+]] { // SIMD2-NEXT: entry: -// SIMD2-NEXT: [[TMP0:%.*]] = load i8, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8, !dbg [[DBG234:![0-9]+]] -// SIMD2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG234]] -// SIMD2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG234]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i8, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8, !dbg [[DBG235:![0-9]+]] +// SIMD2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG235]] +// SIMD2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG235]] // SIMD2: init.check: -// SIMD2-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG235:![0-9]+]] -// SIMD2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S4*)* @_ZN2S4D1Ev to void (i8*)*), i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG234]] -// SIMD2-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8, !dbg [[DBG234]] -// SIMD2-NEXT: br label [[INIT_END]], !dbg [[DBG234]] +// SIMD2-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 23), !dbg [[DBG236:![0-9]+]] +// SIMD2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S4*)* @_ZN2S4D1Ev to void (i8*)*), i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG235]] +// SIMD2-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8, !dbg [[DBG235]] +// SIMD2-NEXT: br label [[INIT_END]], !dbg [[DBG235]] // SIMD2: init.end: -// SIMD2-NEXT: ret void, !dbg [[DBG237:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG238:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// SIMD2-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG238:![0-9]+]] { +// SIMD2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG239:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META239:![0-9]+]], metadata !DIExpression()), !dbg [[DBG241:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META240:![0-9]+]], metadata !DIExpression()), !dbg [[DBG242:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META242:![0-9]+]], metadata !DIExpression()), !dbg [[DBG243:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META243:![0-9]+]], metadata !DIExpression()), !dbg [[DBG244:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG244:![0-9]+]] -// SIMD2-NEXT: call void @_ZN2S4C2Ei(%struct.S4* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG244]] -// SIMD2-NEXT: ret void, !dbg [[DBG245:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG245:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S4C2Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG245]] +// SIMD2-NEXT: ret void, !dbg [[DBG246:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// SIMD2-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG246:![0-9]+]] { +// SIMD2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG247:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD2-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META247:![0-9]+]], metadata !DIExpression()), !dbg [[DBG248:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META248:![0-9]+]], metadata !DIExpression()), !dbg [[DBG249:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @_ZN2S4D2Ev(%struct.S4* noundef [[THIS1]]) #[[ATTR3]], !dbg [[DBG249:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG250:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S4D2Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG250:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG251:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// SIMD2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG251:![0-9]+]] { +// SIMD2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG252:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META252:![0-9]+]], metadata !DIExpression()), !dbg [[DBG253:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META253:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META254:![0-9]+]], metadata !DIExpression()), !dbg [[DBG255:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META255:![0-9]+]], metadata !DIExpression()), !dbg [[DBG256:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0, !dbg [[DBG256:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG257:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP0]], i32* [[A2]], align 4, !dbg [[DBG256]] -// SIMD2-NEXT: ret void, !dbg [[DBG258:![0-9]+]] +// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0, !dbg [[DBG257:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG258:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP0]], i32* [[A2]], align 4, !dbg [[DBG257]] +// SIMD2-NEXT: ret void, !dbg [[DBG259:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// SIMD2-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG259:![0-9]+]] { +// SIMD2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG260:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META260:![0-9]+]], metadata !DIExpression()), !dbg [[DBG261:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META261:![0-9]+]], metadata !DIExpression()), !dbg [[DBG262:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0, !dbg [[DBG262:![0-9]+]] -// SIMD2-NEXT: store i32 0, i32* [[A]], align 4, !dbg [[DBG264:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG265:![0-9]+]] +// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0, !dbg [[DBG263:![0-9]+]] +// SIMD2-NEXT: store i32 0, i32* [[A]], align 4, !dbg [[DBG265:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG266:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// SIMD2-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG266:![0-9]+]] { +// SIMD2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG267:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META267:![0-9]+]], metadata !DIExpression()), !dbg [[DBG268:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META268:![0-9]+]], metadata !DIExpression()), !dbg [[DBG269:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META269:![0-9]+]], metadata !DIExpression()), !dbg [[DBG270:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META270:![0-9]+]], metadata !DIExpression()), !dbg [[DBG271:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], %struct.S2* [[THIS1]], i32 0, i32 0, !dbg [[DBG271:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG272:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP0]], i32* [[A2]], align 8, !dbg [[DBG271]] -// SIMD2-NEXT: ret void, !dbg [[DBG273:![0-9]+]] +// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], %struct.S2* [[THIS1]], i32 0, i32 0, !dbg [[DBG272:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG273:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP0]], i32* [[A2]], align 8, !dbg [[DBG272]] +// SIMD2-NEXT: ret void, !dbg [[DBG274:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// SIMD2-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG274:![0-9]+]] { +// SIMD2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG275:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD2-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META275:![0-9]+]], metadata !DIExpression()), !dbg [[DBG276:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META276:![0-9]+]], metadata !DIExpression()), !dbg [[DBG277:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], %struct.S2* [[THIS1]], i32 0, i32 0, !dbg [[DBG277:![0-9]+]] -// SIMD2-NEXT: store i32 0, i32* [[A]], align 8, !dbg [[DBG279:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG280:![0-9]+]] +// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], %struct.S2* [[THIS1]], i32 0, i32 0, !dbg [[DBG278:![0-9]+]] +// SIMD2-NEXT: store i32 0, i32* [[A]], align 8, !dbg [[DBG280:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG281:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// SIMD2-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG281:![0-9]+]] { +// SIMD2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG282:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META282:![0-9]+]], metadata !DIExpression()), !dbg [[DBG283:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META283:![0-9]+]], metadata !DIExpression()), !dbg [[DBG284:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META284:![0-9]+]], metadata !DIExpression()), !dbg [[DBG285:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META285:![0-9]+]], metadata !DIExpression()), !dbg [[DBG286:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], %struct.Smain* [[THIS1]], i32 0, i32 0, !dbg [[DBG286:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG287:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP0]], i32* [[A2]], align 8, !dbg [[DBG286]] -// SIMD2-NEXT: ret void, !dbg [[DBG288:![0-9]+]] +// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], %struct.Smain* [[THIS1]], i32 0, i32 0, !dbg [[DBG287:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG288:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP0]], i32* [[A2]], align 8, !dbg [[DBG287]] +// SIMD2-NEXT: ret void, !dbg [[DBG289:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// SIMD2-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG289:![0-9]+]] { +// SIMD2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG290:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD2-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META290:![0-9]+]], metadata !DIExpression()), !dbg [[DBG291:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META291:![0-9]+]], metadata !DIExpression()), !dbg [[DBG292:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], %struct.Smain* [[THIS1]], i32 0, i32 0, !dbg [[DBG292:![0-9]+]] -// SIMD2-NEXT: store i32 0, i32* [[A]], align 8, !dbg [[DBG294:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG295:![0-9]+]] +// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], %struct.Smain* [[THIS1]], i32 0, i32 0, !dbg [[DBG293:![0-9]+]] +// SIMD2-NEXT: store i32 0, i32* [[A]], align 8, !dbg [[DBG295:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG296:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// SIMD2-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG296:![0-9]+]] { +// SIMD2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG297:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META297:![0-9]+]], metadata !DIExpression()), !dbg [[DBG298:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META298:![0-9]+]], metadata !DIExpression()), !dbg [[DBG299:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META299:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META300:![0-9]+]], metadata !DIExpression()), !dbg [[DBG301:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], %struct.S4* [[THIS1]], i32 0, i32 0, !dbg [[DBG301:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG302:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP0]], i32* [[A2]], align 4, !dbg [[DBG301]] -// SIMD2-NEXT: ret void, !dbg [[DBG303:![0-9]+]] +// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], %struct.S4* [[THIS1]], i32 0, i32 0, !dbg [[DBG302:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG303:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP0]], i32* [[A2]], align 4, !dbg [[DBG302]] +// SIMD2-NEXT: ret void, !dbg [[DBG304:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// SIMD2-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG304:![0-9]+]] { +// SIMD2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG305:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD2-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META305:![0-9]+]], metadata !DIExpression()), !dbg [[DBG306:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META306:![0-9]+]], metadata !DIExpression()), !dbg [[DBG307:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], %struct.S4* [[THIS1]], i32 0, i32 0, !dbg [[DBG307:![0-9]+]] -// SIMD2-NEXT: store i32 0, i32* [[A]], align 4, !dbg [[DBG309:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG310:![0-9]+]] +// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], %struct.S4* [[THIS1]], i32 0, i32 0, !dbg [[DBG308:![0-9]+]] +// SIMD2-NEXT: store i32 0, i32* [[A]], align 4, !dbg [[DBG310:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG311:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp -// SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG311:![0-9]+]] { +// SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG312:![0-9]+]] { // SIMD2-NEXT: entry: -// SIMD2-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG313:![0-9]+]] -// SIMD2-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG313]] -// SIMD2-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG313]] +// SIMD2-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG314:![0-9]+]] +// SIMD2-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG314]] +// SIMD2-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG314]] // SIMD2-NEXT: ret void // // // CHECK-TLS1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK-TLS1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK-TLS1-NEXT: entry: -// CHECK-TLS1-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef @_ZL3gs1, i32 noundef 5) +// CHECK-TLS1-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 5) // CHECK-TLS1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S1*)* @_ZN2S1D1Ev to void (i8*)*), i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]] // CHECK-TLS1-NEXT: ret void // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// CHECK-TLS1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK-TLS1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3436,22 +3436,22 @@ int foobar() { // CHECK-TLS1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK-TLS1-NEXT: call void @_ZN2S1C2Ei(%struct.S1* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK-TLS1-NEXT: call void @_ZN2S1C2Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK-TLS1-NEXT: ret void // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// CHECK-TLS1-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK-TLS1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK-TLS1-NEXT: call void @_ZN2S1D2Ev(%struct.S1* noundef [[THIS1]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: call void @_ZN2S1D2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK-TLS1-NEXT: ret void // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// CHECK-TLS1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3465,7 +3465,7 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// CHECK-TLS1-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 @@ -3478,13 +3478,13 @@ int foobar() { // CHECK-TLS1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK-TLS1-SAME: () #[[ATTR0]] { // CHECK-TLS1-NEXT: entry: -// CHECK-TLS1-NEXT: call void @_ZN2S2C1Ei(%struct.S2* noundef @_ZL3gs2, i32 noundef 27) +// CHECK-TLS1-NEXT: call void @_ZN2S2C1Ei(%struct.S2* nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 27) // CHECK-TLS1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S2*)* @_ZN2S2D1Ev to void (i8*)*), i8* bitcast (%struct.S2* @_ZL3gs2 to i8*), i8* @__dso_handle) #[[ATTR3]] // CHECK-TLS1-NEXT: ret void // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// CHECK-TLS1-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK-TLS1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3492,22 +3492,22 @@ int foobar() { // CHECK-TLS1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK-TLS1-NEXT: call void @_ZN2S2C2Ei(%struct.S2* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK-TLS1-NEXT: call void @_ZN2S2C2Ei(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]], i32 [[TMP0]]) // CHECK-TLS1-NEXT: ret void // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// CHECK-TLS1-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS1-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// CHECK-TLS1-NEXT: call void @_ZN2S2D2Ev(%struct.S2* noundef [[THIS1]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: call void @_ZN2S2D2Ev(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]] // CHECK-TLS1-NEXT: ret void // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// CHECK-TLS1-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3521,7 +3521,7 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// CHECK-TLS1-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS1-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 @@ -3541,28 +3541,28 @@ int foobar() { // CHECK-TLS1-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS1-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // CHECK-TLS1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 noundef 1) +// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 1) // CHECK-TLS1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK-TLS1: invoke.cont: // CHECK-TLS1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 noundef 2) +// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 2) // CHECK-TLS1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]] // CHECK-TLS1: invoke.cont2: // CHECK-TLS1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 noundef 3) +// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 3) // CHECK-TLS1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] // CHECK-TLS1: invoke.cont3: // CHECK-TLS1-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // CHECK-TLS1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 noundef 4) +// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 4) // CHECK-TLS1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] // CHECK-TLS1: invoke.cont7: // CHECK-TLS1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 noundef 5) +// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 5) // CHECK-TLS1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] // CHECK-TLS1: invoke.cont8: // CHECK-TLS1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 noundef 6) +// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 6) // CHECK-TLS1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] // CHECK-TLS1: invoke.cont9: // CHECK-TLS1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] @@ -3580,7 +3580,7 @@ int foobar() { // CHECK-TLS1: arraydestroy.body: // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK-TLS1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0) // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] // CHECK-TLS1: arraydestroy.done4: @@ -3598,7 +3598,7 @@ int foobar() { // CHECK-TLS1: arraydestroy.body11: // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi %struct.S1* [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 -// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] // CHECK-TLS1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0) // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] // CHECK-TLS1: arraydestroy.done15: @@ -3611,7 +3611,7 @@ int foobar() { // CHECK-TLS1: arraydestroy.body17: // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // CHECK-TLS1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0) // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] // CHECK-TLS1: arraydestroy.done21: @@ -3625,7 +3625,7 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK-TLS1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// CHECK-TLS1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK-TLS1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -3633,7 +3633,7 @@ int foobar() { // CHECK-TLS1: arraydestroy.body: // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK-TLS1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0) // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK-TLS1: arraydestroy.done1: @@ -3648,12 +3648,12 @@ int foobar() { // CHECK-TLS1-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i8, i8* @_ZGVZ4mainE2sm, align 1 // CHECK-TLS1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK-TLS1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] +// CHECK-TLS1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] // CHECK-TLS1: init.check: // CHECK-TLS1-NEXT: [[TMP1:%.*]] = call %struct.S1* @_ZTWL3gs1() // CHECK-TLS1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP1]], i32 0, i32 0 // CHECK-TLS1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK-TLS1-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef @_ZZ4mainE2sm, i32 noundef [[TMP2]]) +// CHECK-TLS1-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 [[TMP2]]) // CHECK-TLS1-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.Smain*)* @_ZZ4mainEN5SmainD1Ev to void (i8*)*), i8* bitcast (%struct.Smain* @_ZZ4mainE2sm to i8*), i8* @__dso_handle) #[[ATTR3]] // CHECK-TLS1-NEXT: store i8 1, i8* @_ZGVZ4mainE2sm, align 1 // CHECK-TLS1-NEXT: br label [[INIT_END]] @@ -3716,7 +3716,7 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// CHECK-TLS1-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-TLS1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3724,17 +3724,17 @@ int foobar() { // CHECK-TLS1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK-TLS1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK-TLS1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]], i32 [[TMP0]]) // CHECK-TLS1-NEXT: ret void // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// CHECK-TLS1-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK-TLS1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS1-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// CHECK-TLS1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* noundef [[THIS1]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] // CHECK-TLS1-NEXT: ret void // // @@ -3771,7 +3771,7 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// CHECK-TLS1-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK-TLS1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3785,7 +3785,7 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// CHECK-TLS1-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK-TLS1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS1-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 @@ -3853,7 +3853,7 @@ int foobar() { // CHECK-TLS1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 // CHECK-TLS1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]] // CHECK-TLS1: init.check: -// CHECK-TLS1-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef @_ZN2STI2S4E2stE, i32 noundef 23) +// CHECK-TLS1-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 23) // CHECK-TLS1-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S4*)* @_ZN2S4D1Ev to void (i8*)*), i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* @__dso_handle) #[[ATTR3]] // CHECK-TLS1-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8 // CHECK-TLS1-NEXT: br label [[INIT_END]] @@ -3862,7 +3862,7 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// CHECK-TLS1-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK-TLS1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3870,22 +3870,22 @@ int foobar() { // CHECK-TLS1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK-TLS1-NEXT: call void @_ZN2S4C2Ei(%struct.S4* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK-TLS1-NEXT: call void @_ZN2S4C2Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]], i32 [[TMP0]]) // CHECK-TLS1-NEXT: ret void // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// CHECK-TLS1-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS1-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// CHECK-TLS1-NEXT: call void @_ZN2S4D2Ev(%struct.S4* noundef [[THIS1]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: call void @_ZN2S4D2Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK-TLS1-NEXT: ret void // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// CHECK-TLS1-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3899,7 +3899,7 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// CHECK-TLS1-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS1-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 @@ -3921,7 +3921,7 @@ int foobar() { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[TMP0:%.*]] = load i8, i8* @__tls_guard, align 1 // CHECK-TLS1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK-TLS1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF3]] +// CHECK-TLS1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF2]] // CHECK-TLS1: init: // CHECK-TLS1-NEXT: store i8 1, i8* @__tls_guard, align 1 // CHECK-TLS1-NEXT: call void @__cxx_global_var_init() @@ -3939,12 +3939,12 @@ int foobar() { // CHECK-TLS2-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i8, i8* @_ZGVZ4mainE2sm, align 1 // CHECK-TLS2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK-TLS2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] +// CHECK-TLS2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]] // CHECK-TLS2: init.check: // CHECK-TLS2-NEXT: [[TMP1:%.*]] = call %struct.S1* @_ZTWL3gs1() // CHECK-TLS2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP1]], i32 0, i32 0 // CHECK-TLS2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 -// CHECK-TLS2-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef @_ZZ4mainE2sm, i32 noundef [[TMP2]]) +// CHECK-TLS2-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 [[TMP2]]) // CHECK-TLS2-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.Smain*)* @_ZZ4mainEN5SmainD1Ev to void (i8*)*), i8* bitcast (%struct.Smain* @_ZZ4mainE2sm to i8*), i8* @__dso_handle) #[[ATTR4:[0-9]+]] // CHECK-TLS2-NEXT: store i8 1, i8* @_ZGVZ4mainE2sm, align 1 // CHECK-TLS2-NEXT: br label [[INIT_END]] @@ -4009,7 +4009,7 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// CHECK-TLS2-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { +// CHECK-TLS2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4017,17 +4017,17 @@ int foobar() { // CHECK-TLS2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK-TLS2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK-TLS2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]], i32 [[TMP0]]) // CHECK-TLS2-NEXT: ret void // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// CHECK-TLS2-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 { +// CHECK-TLS2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS2-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// CHECK-TLS2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* noundef [[THIS1]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]] // CHECK-TLS2-NEXT: ret void // // @@ -4129,13 +4129,13 @@ int foobar() { // CHECK-TLS2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK-TLS2-SAME: () #[[ATTR6:[0-9]+]] { // CHECK-TLS2-NEXT: entry: -// CHECK-TLS2-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef @_ZL3gs1, i32 noundef 5) +// CHECK-TLS2-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 5) // CHECK-TLS2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S1*)* @_ZN2S1D1Ev to void (i8*)*), i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* @__dso_handle) #[[ATTR4]] // CHECK-TLS2-NEXT: ret void // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// CHECK-TLS2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4143,22 +4143,22 @@ int foobar() { // CHECK-TLS2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK-TLS2-NEXT: call void @_ZN2S1C2Ei(%struct.S1* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK-TLS2-NEXT: call void @_ZN2S1C2Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK-TLS2-NEXT: ret void // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// CHECK-TLS2-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { +// CHECK-TLS2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK-TLS2-NEXT: call void @_ZN2S1D2Ev(%struct.S1* noundef [[THIS1]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: call void @_ZN2S1D2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK-TLS2-NEXT: ret void // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// CHECK-TLS2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { +// CHECK-TLS2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4172,7 +4172,7 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// CHECK-TLS2-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { +// CHECK-TLS2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 @@ -4185,13 +4185,13 @@ int foobar() { // CHECK-TLS2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK-TLS2-SAME: () #[[ATTR6]] { // CHECK-TLS2-NEXT: entry: -// CHECK-TLS2-NEXT: call void @_ZN2S2C1Ei(%struct.S2* noundef @_ZL3gs2, i32 noundef 27) +// CHECK-TLS2-NEXT: call void @_ZN2S2C1Ei(%struct.S2* nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 27) // CHECK-TLS2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S2*)* @_ZN2S2D1Ev to void (i8*)*), i8* bitcast (%struct.S2* @_ZL3gs2 to i8*), i8* @__dso_handle) #[[ATTR4]] // CHECK-TLS2-NEXT: ret void // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// CHECK-TLS2-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4199,22 +4199,22 @@ int foobar() { // CHECK-TLS2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK-TLS2-NEXT: call void @_ZN2S2C2Ei(%struct.S2* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK-TLS2-NEXT: call void @_ZN2S2C2Ei(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]], i32 [[TMP0]]) // CHECK-TLS2-NEXT: ret void // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// CHECK-TLS2-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { +// CHECK-TLS2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS2-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// CHECK-TLS2-NEXT: call void @_ZN2S2D2Ev(%struct.S2* noundef [[THIS1]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: call void @_ZN2S2D2Ev(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR4]] // CHECK-TLS2-NEXT: ret void // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// CHECK-TLS2-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { +// CHECK-TLS2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4228,7 +4228,7 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// CHECK-TLS2-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { +// CHECK-TLS2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS2-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 @@ -4248,28 +4248,28 @@ int foobar() { // CHECK-TLS2-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS2-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // CHECK-TLS2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 noundef 1) +// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 1) // CHECK-TLS2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // CHECK-TLS2: invoke.cont: // CHECK-TLS2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 noundef 2) +// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 2) // CHECK-TLS2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]] // CHECK-TLS2: invoke.cont2: // CHECK-TLS2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 noundef 3) +// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 3) // CHECK-TLS2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] // CHECK-TLS2: invoke.cont3: // CHECK-TLS2-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // CHECK-TLS2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 noundef 4) +// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 4) // CHECK-TLS2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] // CHECK-TLS2: invoke.cont7: // CHECK-TLS2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 noundef 5) +// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 5) // CHECK-TLS2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] // CHECK-TLS2: invoke.cont8: // CHECK-TLS2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 noundef 6) +// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 6) // CHECK-TLS2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] // CHECK-TLS2: invoke.cont9: // CHECK-TLS2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR4]] @@ -4287,7 +4287,7 @@ int foobar() { // CHECK-TLS2: arraydestroy.body: // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK-TLS2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0) // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] // CHECK-TLS2: arraydestroy.done4: @@ -4305,7 +4305,7 @@ int foobar() { // CHECK-TLS2: arraydestroy.body11: // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi %struct.S1* [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 -// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]] // CHECK-TLS2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0) // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] // CHECK-TLS2: arraydestroy.done15: @@ -4318,7 +4318,7 @@ int foobar() { // CHECK-TLS2: arraydestroy.body17: // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] // CHECK-TLS2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0) // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] // CHECK-TLS2: arraydestroy.done21: @@ -4332,7 +4332,7 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK-TLS2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR6]] { +// CHECK-TLS2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6]] { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK-TLS2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4340,7 +4340,7 @@ int foobar() { // CHECK-TLS2: arraydestroy.body: // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK-TLS2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0) // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK-TLS2: arraydestroy.done1: @@ -4348,7 +4348,7 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// CHECK-TLS2-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 { +// CHECK-TLS2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4362,7 +4362,7 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// CHECK-TLS2-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 { +// CHECK-TLS2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS2-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 @@ -4379,7 +4379,7 @@ int foobar() { // CHECK-TLS2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 // CHECK-TLS2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]] // CHECK-TLS2: init.check: -// CHECK-TLS2-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef @_ZN2STI2S4E2stE, i32 noundef 23) +// CHECK-TLS2-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 23) // CHECK-TLS2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S4*)* @_ZN2S4D1Ev to void (i8*)*), i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* @__dso_handle) #[[ATTR4]] // CHECK-TLS2-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8 // CHECK-TLS2-NEXT: br label [[INIT_END]] @@ -4388,7 +4388,7 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// CHECK-TLS2-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4396,22 +4396,22 @@ int foobar() { // CHECK-TLS2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK-TLS2-NEXT: call void @_ZN2S4C2Ei(%struct.S4* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK-TLS2-NEXT: call void @_ZN2S4C2Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]], i32 [[TMP0]]) // CHECK-TLS2-NEXT: ret void // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// CHECK-TLS2-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { +// CHECK-TLS2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS2-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// CHECK-TLS2-NEXT: call void @_ZN2S4D2Ev(%struct.S4* noundef [[THIS1]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: call void @_ZN2S4D2Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK-TLS2-NEXT: ret void // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// CHECK-TLS2-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { +// CHECK-TLS2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4425,7 +4425,7 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// CHECK-TLS2-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { +// CHECK-TLS2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS2-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 @@ -4447,7 +4447,7 @@ int foobar() { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[TMP0:%.*]] = load i8, i8* @__tls_guard, align 1 // CHECK-TLS2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK-TLS2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF3]] +// CHECK-TLS2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF2]] // CHECK-TLS2: init: // CHECK-TLS2-NEXT: store i8 1, i8* @__tls_guard, align 1 // CHECK-TLS2-NEXT: call void @__cxx_global_var_init() @@ -4458,15 +4458,15 @@ int foobar() { // // // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK-TLS3-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG116:![0-9]+]] { +// CHECK-TLS3-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG115:![0-9]+]] { // CHECK-TLS3-NEXT: entry: -// CHECK-TLS3-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef @_ZL3gs1, i32 noundef 5), !dbg [[DBG119:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 5), !dbg [[DBG119:![0-9]+]] // CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S1*)* @_ZN2S1D1Ev to void (i8*)*), i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG121:![0-9]+]] // CHECK-TLS3-NEXT: ret void, !dbg [[DBG122:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// CHECK-TLS3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG123:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG123:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4476,23 +4476,23 @@ int foobar() { // CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]] -// CHECK-TLS3-NEXT: call void @_ZN2S1C2Ei(%struct.S1* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG129]] +// CHECK-TLS3-NEXT: call void @_ZN2S1C2Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG129]] // CHECK-TLS3-NEXT: ret void, !dbg [[DBG130:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// CHECK-TLS3-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG133:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @_ZN2S1D2Ev(%struct.S1* noundef [[THIS1]]) #[[ATTR3]], !dbg [[DBG134:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S1D2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG134:![0-9]+]] // CHECK-TLS3-NEXT: ret void, !dbg [[DBG135:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// CHECK-TLS3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG136:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG136:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4508,7 +4508,7 @@ int foobar() { // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// CHECK-TLS3-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG144:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG144:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 @@ -4522,13 +4522,13 @@ int foobar() { // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG151:![0-9]+]] { // CHECK-TLS3-NEXT: entry: -// CHECK-TLS3-NEXT: call void @_ZN2S2C1Ei(%struct.S2* noundef @_ZL3gs2, i32 noundef 27), !dbg [[DBG152:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S2C1Ei(%struct.S2* nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 27), !dbg [[DBG152:![0-9]+]] // CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S2*)* @_ZN2S2D1Ev to void (i8*)*), i8* bitcast (%struct.S2* @_ZL3gs2 to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG154:![0-9]+]] // CHECK-TLS3-NEXT: ret void, !dbg [[DBG155:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// CHECK-TLS3-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG156:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG156:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4538,23 +4538,23 @@ int foobar() { // CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META160:![0-9]+]], metadata !DIExpression()), !dbg [[DBG161:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG162:![0-9]+]] -// CHECK-TLS3-NEXT: call void @_ZN2S2C2Ei(%struct.S2* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG162]] +// CHECK-TLS3-NEXT: call void @_ZN2S2C2Ei(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG162]] // CHECK-TLS3-NEXT: ret void, !dbg [[DBG163:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// CHECK-TLS3-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG164:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG164:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS3-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 // CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META165:![0-9]+]], metadata !DIExpression()), !dbg [[DBG166:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @_ZN2S2D2Ev(%struct.S2* noundef [[THIS1]]) #[[ATTR3]], !dbg [[DBG167:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S2D2Ev(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG167:![0-9]+]] // CHECK-TLS3-NEXT: ret void, !dbg [[DBG168:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// CHECK-TLS3-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG169:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG169:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4570,7 +4570,7 @@ int foobar() { // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// CHECK-TLS3-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG177:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG177:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS3-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 @@ -4591,28 +4591,28 @@ int foobar() { // CHECK-TLS3-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS3-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG185:![0-9]+]] // CHECK-TLS3-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG187:![0-9]+]] -// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 noundef 1) +// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 1) // CHECK-TLS3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG188:![0-9]+]] // CHECK-TLS3: invoke.cont: // CHECK-TLS3-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG187]] -// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 noundef 2) +// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 2) // CHECK-TLS3-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG189:![0-9]+]] // CHECK-TLS3: invoke.cont2: // CHECK-TLS3-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG187]] -// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 noundef 3) +// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 3) // CHECK-TLS3-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG190:![0-9]+]] // CHECK-TLS3: invoke.cont3: // CHECK-TLS3-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG185]] // CHECK-TLS3-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG191:![0-9]+]] -// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 noundef 4) +// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 4) // CHECK-TLS3-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG192:![0-9]+]] // CHECK-TLS3: invoke.cont7: // CHECK-TLS3-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG191]] -// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 noundef 5) +// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 5) // CHECK-TLS3-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG193:![0-9]+]] // CHECK-TLS3: invoke.cont8: // CHECK-TLS3-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG191]] -// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 noundef 6) +// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 6) // CHECK-TLS3-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG194:![0-9]+]] // CHECK-TLS3: invoke.cont9: // CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG195:![0-9]+]] @@ -4630,7 +4630,7 @@ int foobar() { // CHECK-TLS3: arraydestroy.body: // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG187]] // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG187]] -// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG187]] +// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG187]] // CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG187]] // CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG187]] // CHECK-TLS3: arraydestroy.done4: @@ -4648,7 +4648,7 @@ int foobar() { // CHECK-TLS3: arraydestroy.body11: // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi %struct.S1* [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG191]] // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG191]] -// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG191]] +// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG191]] // CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), !dbg [[DBG191]] // CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG191]] // CHECK-TLS3: arraydestroy.done15: @@ -4661,7 +4661,7 @@ int foobar() { // CHECK-TLS3: arraydestroy.body17: // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG185]] // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG185]] +// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG185]] // CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG185]] // CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG185]] // CHECK-TLS3: arraydestroy.done21: @@ -4675,7 +4675,7 @@ int foobar() { // // // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK-TLS3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG197:![0-9]+]] { +// CHECK-TLS3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG197:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK-TLS3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -4684,7 +4684,7 @@ int foobar() { // CHECK-TLS3: arraydestroy.body: // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG202]] // CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG202]] -// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG202]] +// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG202]] // CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), !dbg [[DBG202]] // CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG202]] // CHECK-TLS3: arraydestroy.done1: @@ -4705,7 +4705,7 @@ int foobar() { // CHECK-TLS3-NEXT: [[TMP1:%.*]] = call %struct.S1* @_ZTWL3gs1(), !dbg [[DBG207:![0-9]+]] // CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP1]], i32 0, i32 0, !dbg [[DBG208:![0-9]+]] // CHECK-TLS3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG208]] -// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef @_ZZ4mainE2sm, i32 noundef [[TMP2]]), !dbg [[DBG209:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 [[TMP2]]), !dbg [[DBG209:![0-9]+]] // CHECK-TLS3-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.Smain*)* @_ZZ4mainEN5SmainD1Ev to void (i8*)*), i8* bitcast (%struct.Smain* @_ZZ4mainE2sm to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG205]] // CHECK-TLS3-NEXT: store i8 1, i8* @_ZGVZ4mainE2sm, align 1, !dbg [[DBG205]] // CHECK-TLS3-NEXT: br label [[INIT_END]], !dbg [[DBG205]] @@ -4768,7 +4768,7 @@ int foobar() { // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// CHECK-TLS3-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG235:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG235:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4778,18 +4778,18 @@ int foobar() { // CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META239:![0-9]+]], metadata !DIExpression()), !dbg [[DBG240:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG241:![0-9]+]] -// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG241]] +// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG241]] // CHECK-TLS3-NEXT: ret void, !dbg [[DBG242:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// CHECK-TLS3-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG243:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG243:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS3-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 // CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META244:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* noundef [[THIS1]]) #[[ATTR3]], !dbg [[DBG246:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG246:![0-9]+]] // CHECK-TLS3-NEXT: ret void, !dbg [[DBG247:![0-9]+]] // // @@ -4826,7 +4826,7 @@ int foobar() { // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// CHECK-TLS3-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG248:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG248:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4842,7 +4842,7 @@ int foobar() { // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// CHECK-TLS3-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG256:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG256:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS3-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 @@ -4912,7 +4912,7 @@ int foobar() { // CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG290]] // CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG290]] // CHECK-TLS3: init.check: -// CHECK-TLS3-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG291:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 23), !dbg [[DBG291:![0-9]+]] // CHECK-TLS3-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S4*)* @_ZN2S4D1Ev to void (i8*)*), i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG290]] // CHECK-TLS3-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8, !dbg [[DBG290]] // CHECK-TLS3-NEXT: br label [[INIT_END]], !dbg [[DBG290]] @@ -4921,7 +4921,7 @@ int foobar() { // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// CHECK-TLS3-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG294:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG294:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4931,23 +4931,23 @@ int foobar() { // CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META298:![0-9]+]], metadata !DIExpression()), !dbg [[DBG299:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 // CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG300:![0-9]+]] -// CHECK-TLS3-NEXT: call void @_ZN2S4C2Ei(%struct.S4* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG300]] +// CHECK-TLS3-NEXT: call void @_ZN2S4C2Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG300]] // CHECK-TLS3-NEXT: ret void, !dbg [[DBG301:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// CHECK-TLS3-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG302:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG302:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS3-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 // CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META303:![0-9]+]], metadata !DIExpression()), !dbg [[DBG304:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @_ZN2S4D2Ev(%struct.S4* noundef [[THIS1]]) #[[ATTR3]], !dbg [[DBG305:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S4D2Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG305:![0-9]+]] // CHECK-TLS3-NEXT: ret void, !dbg [[DBG306:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// CHECK-TLS3-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG307:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG307:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4963,7 +4963,7 @@ int foobar() { // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// CHECK-TLS3-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG315:![0-9]+]] { +// CHECK-TLS3-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG315:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS3-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 @@ -5002,70 +5002,70 @@ int foobar() { // CHECK-TLS4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: [[RES:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata i32* [[RES]], metadata [[META116:![0-9]+]], metadata !DIExpression()), !dbg [[DBG117:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i8, i8* @_ZGVZ4mainE2sm, align 1, !dbg [[DBG118:![0-9]+]] -// CHECK-TLS4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG118]] -// CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG118]], !prof [[PROF119:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata i32* [[RES]], metadata [[META115:![0-9]+]], metadata !DIExpression()), !dbg [[DBG116:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i8, i8* @_ZGVZ4mainE2sm, align 1, !dbg [[DBG117:![0-9]+]] +// CHECK-TLS4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG117]] +// CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG117]], !prof [[PROF118:![0-9]+]] // CHECK-TLS4: init.check: -// CHECK-TLS4-NEXT: [[TMP1:%.*]] = call %struct.S1* @_ZTWL3gs1(), !dbg [[DBG120:![0-9]+]] -// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP1]], i32 0, i32 0, !dbg [[DBG121:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG121]] -// CHECK-TLS4-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef @_ZZ4mainE2sm, i32 noundef [[TMP2]]), !dbg [[DBG122:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.Smain*)* @_ZZ4mainEN5SmainD1Ev to void (i8*)*), i8* bitcast (%struct.Smain* @_ZZ4mainE2sm to i8*), i8* @__dso_handle) #[[ATTR5:[0-9]+]], !dbg [[DBG118]] -// CHECK-TLS4-NEXT: store i8 1, i8* @_ZGVZ4mainE2sm, align 1, !dbg [[DBG118]] -// CHECK-TLS4-NEXT: br label [[INIT_END]], !dbg [[DBG118]] +// CHECK-TLS4-NEXT: [[TMP1:%.*]] = call %struct.S1* @_ZTWL3gs1(), !dbg [[DBG119:![0-9]+]] +// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP1]], i32 0, i32 0, !dbg [[DBG120:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG120]] +// CHECK-TLS4-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 [[TMP2]]), !dbg [[DBG121:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.Smain*)* @_ZZ4mainEN5SmainD1Ev to void (i8*)*), i8* bitcast (%struct.Smain* @_ZZ4mainE2sm to i8*), i8* @__dso_handle) #[[ATTR5:[0-9]+]], !dbg [[DBG117]] +// CHECK-TLS4-NEXT: store i8 1, i8* @_ZGVZ4mainE2sm, align 1, !dbg [[DBG117]] +// CHECK-TLS4-NEXT: br label [[INIT_END]], !dbg [[DBG117]] // CHECK-TLS4: init.end: -// CHECK-TLS4-NEXT: [[TMP4:%.*]] = call %struct.S3* @_ZTWN6Static1sE(), !dbg [[DBG123:![0-9]+]] -// CHECK-TLS4-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], %struct.S3* [[TMP4]], i32 0, i32 0, !dbg [[DBG124:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A1]], align 4, !dbg [[DBG124]] -// CHECK-TLS4-NEXT: store i32 [[TMP5]], i32* [[RES]], align 4, !dbg [[DBG125:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP6:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SMAIN:%.*]], %struct.Smain* @_ZZ4mainE2sm, i32 0, i32 0), align 8, !dbg [[DBG126:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP7:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG127:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]], !dbg [[DBG127]] -// CHECK-TLS4-NEXT: store i32 [[ADD]], i32* [[RES]], align 4, !dbg [[DBG127]] -// CHECK-TLS4-NEXT: [[TMP8:%.*]] = call %struct.S1* @_ZTWL3gs1(), !dbg [[DBG128:![0-9]+]] -// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP8]], i32 0, i32 0, !dbg [[DBG129:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A2]], align 4, !dbg [[DBG129]] -// CHECK-TLS4-NEXT: [[TMP10:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG130:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG130]] -// CHECK-TLS4-NEXT: store i32 [[ADD3]], i32* [[RES]], align 4, !dbg [[DBG130]] -// CHECK-TLS4-NEXT: [[TMP11:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S2:%.*]], %struct.S2* @_ZL3gs2, i32 0, i32 0), align 8, !dbg [[DBG131:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP12:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG132:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG132]] -// CHECK-TLS4-NEXT: store i32 [[ADD4]], i32* [[RES]], align 4, !dbg [[DBG132]] -// CHECK-TLS4-NEXT: [[TMP13:%.*]] = call %struct.S5* @_ZTW3gs3(), !dbg [[DBG133:![0-9]+]] -// CHECK-TLS4-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], %struct.S5* [[TMP13]], i32 0, i32 0, !dbg [[DBG134:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP14:%.*]] = load i32, i32* [[A5]], align 4, !dbg [[DBG134]] -// CHECK-TLS4-NEXT: [[TMP15:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG135:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP15]], [[TMP14]], !dbg [[DBG135]] -// CHECK-TLS4-NEXT: store i32 [[ADD6]], i32* [[RES]], align 4, !dbg [[DBG135]] -// CHECK-TLS4-NEXT: [[TMP16:%.*]] = call [2 x [3 x %struct.S1]]* @_ZTW5arr_x(), !dbg [[DBG136:![0-9]+]] -// CHECK-TLS4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* [[TMP16]], i64 0, i64 1, !dbg [[DBG136]] -// CHECK-TLS4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG136]] -// CHECK-TLS4-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYIDX7]], i32 0, i32 0, !dbg [[DBG137:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP17:%.*]] = load i32, i32* [[A8]], align 4, !dbg [[DBG137]] -// CHECK-TLS4-NEXT: [[TMP18:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG138:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[TMP17]], !dbg [[DBG138]] -// CHECK-TLS4-NEXT: store i32 [[ADD9]], i32* [[RES]], align 4, !dbg [[DBG138]] -// CHECK-TLS4-NEXT: [[TMP19:%.*]] = call i32* @_ZTWN2STIiE2stE(), !dbg [[DBG139:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4, !dbg [[DBG139]] -// CHECK-TLS4-NEXT: [[TMP21:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG140:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]], !dbg [[DBG140]] -// CHECK-TLS4-NEXT: store i32 [[ADD10]], i32* [[RES]], align 4, !dbg [[DBG140]] -// CHECK-TLS4-NEXT: [[TMP22:%.*]] = call float* @_ZTWN2STIfE2stE(), !dbg [[DBG141:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP23:%.*]] = load float, float* [[TMP22]], align 4, !dbg [[DBG141]] -// CHECK-TLS4-NEXT: [[CONV:%.*]] = fptosi float [[TMP23]] to i32, !dbg [[DBG141]] -// CHECK-TLS4-NEXT: [[TMP24:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG142:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP24]], [[CONV]], !dbg [[DBG142]] -// CHECK-TLS4-NEXT: store i32 [[ADD11]], i32* [[RES]], align 4, !dbg [[DBG142]] -// CHECK-TLS4-NEXT: [[TMP25:%.*]] = call %struct.S4* @_ZTWN2STI2S4E2stE(), !dbg [[DBG143:![0-9]+]] -// CHECK-TLS4-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], %struct.S4* [[TMP25]], i32 0, i32 0, !dbg [[DBG144:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP26:%.*]] = load i32, i32* [[A12]], align 4, !dbg [[DBG144]] -// CHECK-TLS4-NEXT: [[TMP27:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG145:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP27]], [[TMP26]], !dbg [[DBG145]] -// CHECK-TLS4-NEXT: store i32 [[ADD13]], i32* [[RES]], align 4, !dbg [[DBG145]] -// CHECK-TLS4-NEXT: [[TMP28:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG146:![0-9]+]] -// CHECK-TLS4-NEXT: ret i32 [[TMP28]], !dbg [[DBG147:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP4:%.*]] = call %struct.S3* @_ZTWN6Static1sE(), !dbg [[DBG122:![0-9]+]] +// CHECK-TLS4-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], %struct.S3* [[TMP4]], i32 0, i32 0, !dbg [[DBG123:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A1]], align 4, !dbg [[DBG123]] +// CHECK-TLS4-NEXT: store i32 [[TMP5]], i32* [[RES]], align 4, !dbg [[DBG124:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP6:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SMAIN:%.*]], %struct.Smain* @_ZZ4mainE2sm, i32 0, i32 0), align 8, !dbg [[DBG125:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP7:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG126:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]], !dbg [[DBG126]] +// CHECK-TLS4-NEXT: store i32 [[ADD]], i32* [[RES]], align 4, !dbg [[DBG126]] +// CHECK-TLS4-NEXT: [[TMP8:%.*]] = call %struct.S1* @_ZTWL3gs1(), !dbg [[DBG127:![0-9]+]] +// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP8]], i32 0, i32 0, !dbg [[DBG128:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A2]], align 4, !dbg [[DBG128]] +// CHECK-TLS4-NEXT: [[TMP10:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG129:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG129]] +// CHECK-TLS4-NEXT: store i32 [[ADD3]], i32* [[RES]], align 4, !dbg [[DBG129]] +// CHECK-TLS4-NEXT: [[TMP11:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S2:%.*]], %struct.S2* @_ZL3gs2, i32 0, i32 0), align 8, !dbg [[DBG130:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP12:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG131:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG131]] +// CHECK-TLS4-NEXT: store i32 [[ADD4]], i32* [[RES]], align 4, !dbg [[DBG131]] +// CHECK-TLS4-NEXT: [[TMP13:%.*]] = call %struct.S5* @_ZTW3gs3(), !dbg [[DBG132:![0-9]+]] +// CHECK-TLS4-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], %struct.S5* [[TMP13]], i32 0, i32 0, !dbg [[DBG133:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP14:%.*]] = load i32, i32* [[A5]], align 4, !dbg [[DBG133]] +// CHECK-TLS4-NEXT: [[TMP15:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG134:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP15]], [[TMP14]], !dbg [[DBG134]] +// CHECK-TLS4-NEXT: store i32 [[ADD6]], i32* [[RES]], align 4, !dbg [[DBG134]] +// CHECK-TLS4-NEXT: [[TMP16:%.*]] = call [2 x [3 x %struct.S1]]* @_ZTW5arr_x(), !dbg [[DBG135:![0-9]+]] +// CHECK-TLS4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* [[TMP16]], i64 0, i64 1, !dbg [[DBG135]] +// CHECK-TLS4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG135]] +// CHECK-TLS4-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYIDX7]], i32 0, i32 0, !dbg [[DBG136:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP17:%.*]] = load i32, i32* [[A8]], align 4, !dbg [[DBG136]] +// CHECK-TLS4-NEXT: [[TMP18:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG137:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[TMP17]], !dbg [[DBG137]] +// CHECK-TLS4-NEXT: store i32 [[ADD9]], i32* [[RES]], align 4, !dbg [[DBG137]] +// CHECK-TLS4-NEXT: [[TMP19:%.*]] = call i32* @_ZTWN2STIiE2stE(), !dbg [[DBG138:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4, !dbg [[DBG138]] +// CHECK-TLS4-NEXT: [[TMP21:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG139:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]], !dbg [[DBG139]] +// CHECK-TLS4-NEXT: store i32 [[ADD10]], i32* [[RES]], align 4, !dbg [[DBG139]] +// CHECK-TLS4-NEXT: [[TMP22:%.*]] = call float* @_ZTWN2STIfE2stE(), !dbg [[DBG140:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP23:%.*]] = load float, float* [[TMP22]], align 4, !dbg [[DBG140]] +// CHECK-TLS4-NEXT: [[CONV:%.*]] = fptosi float [[TMP23]] to i32, !dbg [[DBG140]] +// CHECK-TLS4-NEXT: [[TMP24:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG141:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP24]], [[CONV]], !dbg [[DBG141]] +// CHECK-TLS4-NEXT: store i32 [[ADD11]], i32* [[RES]], align 4, !dbg [[DBG141]] +// CHECK-TLS4-NEXT: [[TMP25:%.*]] = call %struct.S4* @_ZTWN2STI2S4E2stE(), !dbg [[DBG142:![0-9]+]] +// CHECK-TLS4-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], %struct.S4* [[TMP25]], i32 0, i32 0, !dbg [[DBG143:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP26:%.*]] = load i32, i32* [[A12]], align 4, !dbg [[DBG143]] +// CHECK-TLS4-NEXT: [[TMP27:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG144:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP27]], [[TMP26]], !dbg [[DBG144]] +// CHECK-TLS4-NEXT: store i32 [[ADD13]], i32* [[RES]], align 4, !dbg [[DBG144]] +// CHECK-TLS4-NEXT: [[TMP28:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG145:![0-9]+]] +// CHECK-TLS4-NEXT: ret i32 [[TMP28]], !dbg [[DBG146:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTWL3gs1 @@ -5075,29 +5075,29 @@ int foobar() { // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// CHECK-TLS4-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 !dbg [[DBG148:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 !dbg [[DBG147:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META149:![0-9]+]], metadata !DIExpression()), !dbg [[DBG151:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META148:![0-9]+]], metadata !DIExpression()), !dbg [[DBG150:![0-9]+]] // CHECK-TLS4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META152:![0-9]+]], metadata !DIExpression()), !dbg [[DBG153:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META151:![0-9]+]], metadata !DIExpression()), !dbg [[DBG152:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG154:![0-9]+]] -// CHECK-TLS4-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG154]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG155:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG153:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG153]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG154:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// CHECK-TLS4-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] align 2 !dbg [[DBG156:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] align 2 !dbg [[DBG155:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS4-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META157:![0-9]+]], metadata !DIExpression()), !dbg [[DBG158:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META156:![0-9]+]], metadata !DIExpression()), !dbg [[DBG157:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* noundef [[THIS1]]) #[[ATTR5]], !dbg [[DBG159:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG160:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR5]], !dbg [[DBG158:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG159:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTWN6Static1sE @@ -5143,69 +5143,69 @@ int foobar() { // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_Z6foobarv -// CHECK-TLS4-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG161:![0-9]+]] { +// CHECK-TLS4-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG160:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[RES:%.*]] = alloca i32, align 4 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata i32* [[RES]], metadata [[META162:![0-9]+]], metadata !DIExpression()), !dbg [[DBG163:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call %struct.S3* @_ZTWN6Static1sE(), !dbg [[DBG164:![0-9]+]] -// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], %struct.S3* [[TMP0]], i32 0, i32 0, !dbg [[DBG165:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG165]] -// CHECK-TLS4-NEXT: store i32 [[TMP1]], i32* [[RES]], align 4, !dbg [[DBG166:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP2:%.*]] = call %struct.S1* @_ZTWL3gs1(), !dbg [[DBG167:![0-9]+]] -// CHECK-TLS4-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP2]], i32 0, i32 0, !dbg [[DBG168:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A1]], align 4, !dbg [[DBG168]] -// CHECK-TLS4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG169:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG169]] -// CHECK-TLS4-NEXT: store i32 [[ADD]], i32* [[RES]], align 4, !dbg [[DBG169]] -// CHECK-TLS4-NEXT: [[TMP5:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S2:%.*]], %struct.S2* @_ZL3gs2, i32 0, i32 0), align 8, !dbg [[DBG170:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP6:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG171:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG171]] -// CHECK-TLS4-NEXT: store i32 [[ADD2]], i32* [[RES]], align 4, !dbg [[DBG171]] -// CHECK-TLS4-NEXT: [[TMP7:%.*]] = call %struct.S5* @_ZTW3gs3(), !dbg [[DBG172:![0-9]+]] -// CHECK-TLS4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], %struct.S5* [[TMP7]], i32 0, i32 0, !dbg [[DBG173:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A3]], align 4, !dbg [[DBG173]] -// CHECK-TLS4-NEXT: [[TMP9:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG174:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]], !dbg [[DBG174]] -// CHECK-TLS4-NEXT: store i32 [[ADD4]], i32* [[RES]], align 4, !dbg [[DBG174]] -// CHECK-TLS4-NEXT: [[TMP10:%.*]] = call [2 x [3 x %struct.S1]]* @_ZTW5arr_x(), !dbg [[DBG175:![0-9]+]] -// CHECK-TLS4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* [[TMP10]], i64 0, i64 1, !dbg [[DBG175]] -// CHECK-TLS4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG175]] -// CHECK-TLS4-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG176:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP11:%.*]] = load i32, i32* [[A6]], align 4, !dbg [[DBG176]] -// CHECK-TLS4-NEXT: [[TMP12:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG177:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG177]] -// CHECK-TLS4-NEXT: store i32 [[ADD7]], i32* [[RES]], align 4, !dbg [[DBG177]] -// CHECK-TLS4-NEXT: [[TMP13:%.*]] = call i32* @_ZTWN2STIiE2stE(), !dbg [[DBG178:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4, !dbg [[DBG178]] -// CHECK-TLS4-NEXT: [[TMP15:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG179:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]], !dbg [[DBG179]] -// CHECK-TLS4-NEXT: store i32 [[ADD8]], i32* [[RES]], align 4, !dbg [[DBG179]] -// CHECK-TLS4-NEXT: [[TMP16:%.*]] = call float* @_ZTWN2STIfE2stE(), !dbg [[DBG180:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP17:%.*]] = load float, float* [[TMP16]], align 4, !dbg [[DBG180]] -// CHECK-TLS4-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG180]] -// CHECK-TLS4-NEXT: [[TMP18:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG181:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG181]] -// CHECK-TLS4-NEXT: store i32 [[ADD9]], i32* [[RES]], align 4, !dbg [[DBG181]] -// CHECK-TLS4-NEXT: [[TMP19:%.*]] = call %struct.S4* @_ZTWN2STI2S4E2stE(), !dbg [[DBG182:![0-9]+]] -// CHECK-TLS4-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], %struct.S4* [[TMP19]], i32 0, i32 0, !dbg [[DBG183:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP20:%.*]] = load i32, i32* [[A10]], align 4, !dbg [[DBG183]] -// CHECK-TLS4-NEXT: [[TMP21:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG184:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]], !dbg [[DBG184]] -// CHECK-TLS4-NEXT: store i32 [[ADD11]], i32* [[RES]], align 4, !dbg [[DBG184]] -// CHECK-TLS4-NEXT: [[TMP22:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG185:![0-9]+]] -// CHECK-TLS4-NEXT: ret i32 [[TMP22]], !dbg [[DBG186:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata i32* [[RES]], metadata [[META161:![0-9]+]], metadata !DIExpression()), !dbg [[DBG162:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call %struct.S3* @_ZTWN6Static1sE(), !dbg [[DBG163:![0-9]+]] +// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], %struct.S3* [[TMP0]], i32 0, i32 0, !dbg [[DBG164:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG164]] +// CHECK-TLS4-NEXT: store i32 [[TMP1]], i32* [[RES]], align 4, !dbg [[DBG165:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP2:%.*]] = call %struct.S1* @_ZTWL3gs1(), !dbg [[DBG166:![0-9]+]] +// CHECK-TLS4-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP2]], i32 0, i32 0, !dbg [[DBG167:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A1]], align 4, !dbg [[DBG167]] +// CHECK-TLS4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG168:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG168]] +// CHECK-TLS4-NEXT: store i32 [[ADD]], i32* [[RES]], align 4, !dbg [[DBG168]] +// CHECK-TLS4-NEXT: [[TMP5:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S2:%.*]], %struct.S2* @_ZL3gs2, i32 0, i32 0), align 8, !dbg [[DBG169:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP6:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG170:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG170]] +// CHECK-TLS4-NEXT: store i32 [[ADD2]], i32* [[RES]], align 4, !dbg [[DBG170]] +// CHECK-TLS4-NEXT: [[TMP7:%.*]] = call %struct.S5* @_ZTW3gs3(), !dbg [[DBG171:![0-9]+]] +// CHECK-TLS4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], %struct.S5* [[TMP7]], i32 0, i32 0, !dbg [[DBG172:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A3]], align 4, !dbg [[DBG172]] +// CHECK-TLS4-NEXT: [[TMP9:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG173:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]], !dbg [[DBG173]] +// CHECK-TLS4-NEXT: store i32 [[ADD4]], i32* [[RES]], align 4, !dbg [[DBG173]] +// CHECK-TLS4-NEXT: [[TMP10:%.*]] = call [2 x [3 x %struct.S1]]* @_ZTW5arr_x(), !dbg [[DBG174:![0-9]+]] +// CHECK-TLS4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* [[TMP10]], i64 0, i64 1, !dbg [[DBG174]] +// CHECK-TLS4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG174]] +// CHECK-TLS4-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG175:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP11:%.*]] = load i32, i32* [[A6]], align 4, !dbg [[DBG175]] +// CHECK-TLS4-NEXT: [[TMP12:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG176:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG176]] +// CHECK-TLS4-NEXT: store i32 [[ADD7]], i32* [[RES]], align 4, !dbg [[DBG176]] +// CHECK-TLS4-NEXT: [[TMP13:%.*]] = call i32* @_ZTWN2STIiE2stE(), !dbg [[DBG177:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4, !dbg [[DBG177]] +// CHECK-TLS4-NEXT: [[TMP15:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG178:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]], !dbg [[DBG178]] +// CHECK-TLS4-NEXT: store i32 [[ADD8]], i32* [[RES]], align 4, !dbg [[DBG178]] +// CHECK-TLS4-NEXT: [[TMP16:%.*]] = call float* @_ZTWN2STIfE2stE(), !dbg [[DBG179:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP17:%.*]] = load float, float* [[TMP16]], align 4, !dbg [[DBG179]] +// CHECK-TLS4-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG179]] +// CHECK-TLS4-NEXT: [[TMP18:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG180:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG180]] +// CHECK-TLS4-NEXT: store i32 [[ADD9]], i32* [[RES]], align 4, !dbg [[DBG180]] +// CHECK-TLS4-NEXT: [[TMP19:%.*]] = call %struct.S4* @_ZTWN2STI2S4E2stE(), !dbg [[DBG181:![0-9]+]] +// CHECK-TLS4-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], %struct.S4* [[TMP19]], i32 0, i32 0, !dbg [[DBG182:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP20:%.*]] = load i32, i32* [[A10]], align 4, !dbg [[DBG182]] +// CHECK-TLS4-NEXT: [[TMP21:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG183:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]], !dbg [[DBG183]] +// CHECK-TLS4-NEXT: store i32 [[ADD11]], i32* [[RES]], align 4, !dbg [[DBG183]] +// CHECK-TLS4-NEXT: [[TMP22:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG184:![0-9]+]] +// CHECK-TLS4-NEXT: ret i32 [[TMP22]], !dbg [[DBG185:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK-TLS4-SAME: () #[[ATTR7:[0-9]+]] !dbg [[DBG187:![0-9]+]] { +// CHECK-TLS4-SAME: () #[[ATTR7:[0-9]+]] !dbg [[DBG186:![0-9]+]] { // CHECK-TLS4-NEXT: entry: -// CHECK-TLS4-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef @_ZL3gs1, i32 noundef 5), !dbg [[DBG190:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 5), !dbg [[DBG190:![0-9]+]] // CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S1*)* @_ZN2S1D1Ev to void (i8*)*), i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* @__dso_handle) #[[ATTR5]], !dbg [[DBG192:![0-9]+]] // CHECK-TLS4-NEXT: ret void, !dbg [[DBG193:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// CHECK-TLS4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG194:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG194:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5215,23 +5215,23 @@ int foobar() { // CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META198:![0-9]+]], metadata !DIExpression()), !dbg [[DBG199:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG200:![0-9]+]] -// CHECK-TLS4-NEXT: call void @_ZN2S1C2Ei(%struct.S1* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG200]] +// CHECK-TLS4-NEXT: call void @_ZN2S1C2Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG200]] // CHECK-TLS4-NEXT: ret void, !dbg [[DBG201:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// CHECK-TLS4-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG202:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG202:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META203:![0-9]+]], metadata !DIExpression()), !dbg [[DBG204:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @_ZN2S1D2Ev(%struct.S1* noundef [[THIS1]]) #[[ATTR5]], !dbg [[DBG205:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S1D2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]], !dbg [[DBG205:![0-9]+]] // CHECK-TLS4-NEXT: ret void, !dbg [[DBG206:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// CHECK-TLS4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG207:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG207:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5247,7 +5247,7 @@ int foobar() { // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// CHECK-TLS4-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG215:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG215:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 @@ -5261,13 +5261,13 @@ int foobar() { // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK-TLS4-SAME: () #[[ATTR7]] !dbg [[DBG222:![0-9]+]] { // CHECK-TLS4-NEXT: entry: -// CHECK-TLS4-NEXT: call void @_ZN2S2C1Ei(%struct.S2* noundef @_ZL3gs2, i32 noundef 27), !dbg [[DBG223:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S2C1Ei(%struct.S2* nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 27), !dbg [[DBG223:![0-9]+]] // CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S2*)* @_ZN2S2D1Ev to void (i8*)*), i8* bitcast (%struct.S2* @_ZL3gs2 to i8*), i8* @__dso_handle) #[[ATTR5]], !dbg [[DBG225:![0-9]+]] // CHECK-TLS4-NEXT: ret void, !dbg [[DBG226:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// CHECK-TLS4-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG227:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG227:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5277,23 +5277,23 @@ int foobar() { // CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META231:![0-9]+]], metadata !DIExpression()), !dbg [[DBG232:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG233:![0-9]+]] -// CHECK-TLS4-NEXT: call void @_ZN2S2C2Ei(%struct.S2* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG233]] +// CHECK-TLS4-NEXT: call void @_ZN2S2C2Ei(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG233]] // CHECK-TLS4-NEXT: ret void, !dbg [[DBG234:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// CHECK-TLS4-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG235:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG235:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS4-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 // CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META236:![0-9]+]], metadata !DIExpression()), !dbg [[DBG237:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @_ZN2S2D2Ev(%struct.S2* noundef [[THIS1]]) #[[ATTR5]], !dbg [[DBG238:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S2D2Ev(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR5]], !dbg [[DBG238:![0-9]+]] // CHECK-TLS4-NEXT: ret void, !dbg [[DBG239:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// CHECK-TLS4-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG240:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG240:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5309,7 +5309,7 @@ int foobar() { // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// CHECK-TLS4-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG248:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG248:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // CHECK-TLS4-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 @@ -5330,28 +5330,28 @@ int foobar() { // CHECK-TLS4-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca %struct.S1*, align 8 // CHECK-TLS4-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG256:![0-9]+]] // CHECK-TLS4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG258:![0-9]+]] -// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 noundef 1) +// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 1) // CHECK-TLS4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG259:![0-9]+]] // CHECK-TLS4: invoke.cont: // CHECK-TLS4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG258]] -// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 noundef 2) +// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 2) // CHECK-TLS4-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG260:![0-9]+]] // CHECK-TLS4: invoke.cont2: // CHECK-TLS4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG258]] -// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 noundef 3) +// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 3) // CHECK-TLS4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG261:![0-9]+]] // CHECK-TLS4: invoke.cont3: // CHECK-TLS4-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG256]] // CHECK-TLS4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG262:![0-9]+]] -// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 noundef 4) +// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 4) // CHECK-TLS4-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG263:![0-9]+]] // CHECK-TLS4: invoke.cont7: // CHECK-TLS4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG262]] -// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 noundef 5) +// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 5) // CHECK-TLS4-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG264:![0-9]+]] // CHECK-TLS4: invoke.cont8: // CHECK-TLS4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG262]] -// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 noundef 6) +// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 6) // CHECK-TLS4-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG265:![0-9]+]] // CHECK-TLS4: invoke.cont9: // CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR5]], !dbg [[DBG266:![0-9]+]] @@ -5369,7 +5369,7 @@ int foobar() { // CHECK-TLS4: arraydestroy.body: // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG258]] // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG258]] -// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]], !dbg [[DBG258]] +// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]], !dbg [[DBG258]] // CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG258]] // CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG258]] // CHECK-TLS4: arraydestroy.done4: @@ -5387,7 +5387,7 @@ int foobar() { // CHECK-TLS4: arraydestroy.body11: // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi %struct.S1* [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG262]] // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG262]] -// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR5]], !dbg [[DBG262]] +// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR5]], !dbg [[DBG262]] // CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), !dbg [[DBG262]] // CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG262]] // CHECK-TLS4: arraydestroy.done15: @@ -5400,7 +5400,7 @@ int foobar() { // CHECK-TLS4: arraydestroy.body17: // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG256]] // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG256]] -// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR5]], !dbg [[DBG256]] +// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR5]], !dbg [[DBG256]] // CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG256]] // CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG256]] // CHECK-TLS4: arraydestroy.done21: @@ -5414,7 +5414,7 @@ int foobar() { // // // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK-TLS4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR7]] !dbg [[DBG268:![0-9]+]] { +// CHECK-TLS4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR7]] !dbg [[DBG268:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // CHECK-TLS4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -5423,7 +5423,7 @@ int foobar() { // CHECK-TLS4: arraydestroy.body: // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG273]] // CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG273]] -// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]], !dbg [[DBG273]] +// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]], !dbg [[DBG273]] // CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), !dbg [[DBG273]] // CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG273]] // CHECK-TLS4: arraydestroy.done1: @@ -5431,7 +5431,7 @@ int foobar() { // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// CHECK-TLS4-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] align 2 !dbg [[DBG274:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR4]] align 2 !dbg [[DBG274:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5447,7 +5447,7 @@ int foobar() { // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// CHECK-TLS4-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR4]] align 2 !dbg [[DBG282:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] align 2 !dbg [[DBG282:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // CHECK-TLS4-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 @@ -5465,7 +5465,7 @@ int foobar() { // CHECK-TLS4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG290]] // CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG290]] // CHECK-TLS4: init.check: -// CHECK-TLS4-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG291:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 23), !dbg [[DBG291:![0-9]+]] // CHECK-TLS4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S4*)* @_ZN2S4D1Ev to void (i8*)*), i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* @__dso_handle) #[[ATTR5]], !dbg [[DBG290]] // CHECK-TLS4-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8, !dbg [[DBG290]] // CHECK-TLS4-NEXT: br label [[INIT_END]], !dbg [[DBG290]] @@ -5474,7 +5474,7 @@ int foobar() { // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// CHECK-TLS4-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG294:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG294:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5484,23 +5484,23 @@ int foobar() { // CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META298:![0-9]+]], metadata !DIExpression()), !dbg [[DBG299:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 // CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG300:![0-9]+]] -// CHECK-TLS4-NEXT: call void @_ZN2S4C2Ei(%struct.S4* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG300]] +// CHECK-TLS4-NEXT: call void @_ZN2S4C2Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG300]] // CHECK-TLS4-NEXT: ret void, !dbg [[DBG301:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// CHECK-TLS4-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG302:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG302:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS4-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 // CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META303:![0-9]+]], metadata !DIExpression()), !dbg [[DBG304:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @_ZN2S4D2Ev(%struct.S4* noundef [[THIS1]]) #[[ATTR5]], !dbg [[DBG305:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S4D2Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]], !dbg [[DBG305:![0-9]+]] // CHECK-TLS4-NEXT: ret void, !dbg [[DBG306:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// CHECK-TLS4-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG307:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG307:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5516,7 +5516,7 @@ int foobar() { // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// CHECK-TLS4-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG315:![0-9]+]] { +// CHECK-TLS4-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG315:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // CHECK-TLS4-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 @@ -5539,7 +5539,7 @@ int foobar() { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i8, i8* @__tls_guard, align 1, !dbg [[DBG326:![0-9]+]] // CHECK-TLS4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG326]] -// CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !dbg [[DBG326]], !prof [[PROF119]] +// CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !dbg [[DBG326]], !prof [[PROF118]] // CHECK-TLS4: init: // CHECK-TLS4-NEXT: store i8 1, i8* @__tls_guard, align 1, !dbg [[DBG326]] // CHECK-TLS4-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG326]] @@ -5552,13 +5552,13 @@ int foobar() { // SIMD3-LABEL: define {{[^@]+}}@__cxx_global_var_init // SIMD3-SAME: () #[[ATTR0:[0-9]+]] { // SIMD3-NEXT: entry: -// SIMD3-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef @_ZL3gs1, i32 noundef 5) +// SIMD3-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 5) // SIMD3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S1*)* @_ZN2S1D1Ev to void (i8*)*), i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]] // SIMD3-NEXT: ret void // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// SIMD3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// SIMD3-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5566,30 +5566,30 @@ int foobar() { // SIMD3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // SIMD3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // SIMD3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD3-NEXT: call void @_ZN2S1C2Ei(%struct.S1* noundef [[THIS1]], i32 noundef [[TMP0]]) +// SIMD3-NEXT: call void @_ZN2S1C2Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // SIMD3-NEXT: ret void // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// SIMD3-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// SIMD3-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // SIMD3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// SIMD3-NEXT: call void @_ZN2S1D2Ev(%struct.S1* noundef [[THIS1]]) #[[ATTR3]] +// SIMD3-NEXT: call void @_ZN2S1D2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] // SIMD3-NEXT: ret void // // // SIMD3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // SIMD3-SAME: () #[[ATTR0]] { // SIMD3-NEXT: entry: -// SIMD3-NEXT: call void @_ZN2S2C1Ei(%struct.S2* noundef @_ZL3gs2, i32 noundef 27) +// SIMD3-NEXT: call void @_ZN2S2C1Ei(%struct.S2* nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 27) // SIMD3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S2*)* @_ZN2S2D1Ev to void (i8*)*), i8* bitcast (%struct.S2* @_ZL3gs2 to i8*), i8* @__dso_handle) #[[ATTR3]] // SIMD3-NEXT: ret void // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// SIMD3-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// SIMD3-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5597,17 +5597,17 @@ int foobar() { // SIMD3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // SIMD3-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 // SIMD3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD3-NEXT: call void @_ZN2S2C2Ei(%struct.S2* noundef [[THIS1]], i32 noundef [[TMP0]]) +// SIMD3-NEXT: call void @_ZN2S2C2Ei(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]], i32 [[TMP0]]) // SIMD3-NEXT: ret void // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// SIMD3-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD3-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD3-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 // SIMD3-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// SIMD3-NEXT: call void @_ZN2S2D2Ev(%struct.S2* noundef [[THIS1]]) #[[ATTR3]] +// SIMD3-NEXT: call void @_ZN2S2D2Ev(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]] // SIMD3-NEXT: ret void // // @@ -5621,28 +5621,28 @@ int foobar() { // SIMD3-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca %struct.S1*, align 8 // SIMD3-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // SIMD3-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 noundef 1) +// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 1) // SIMD3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // SIMD3: invoke.cont: // SIMD3-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 noundef 2) +// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 2) // SIMD3-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]] // SIMD3: invoke.cont2: // SIMD3-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8 -// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 noundef 3) +// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 3) // SIMD3-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] // SIMD3: invoke.cont3: // SIMD3-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8 // SIMD3-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 noundef 4) +// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 4) // SIMD3-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] // SIMD3: invoke.cont7: // SIMD3-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 noundef 5) +// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 5) // SIMD3-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] // SIMD3: invoke.cont8: // SIMD3-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8 -// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 noundef 6) +// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 6) // SIMD3-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] // SIMD3: invoke.cont9: // SIMD3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]] @@ -5660,7 +5660,7 @@ int foobar() { // SIMD3: arraydestroy.body: // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0) // SIMD3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] // SIMD3: arraydestroy.done4: @@ -5678,7 +5678,7 @@ int foobar() { // SIMD3: arraydestroy.body11: // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi %struct.S1* [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 -// SIMD3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] +// SIMD3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] // SIMD3-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0) // SIMD3-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] // SIMD3: arraydestroy.done15: @@ -5691,7 +5691,7 @@ int foobar() { // SIMD3: arraydestroy.body17: // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// SIMD3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// SIMD3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // SIMD3-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0) // SIMD3-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] // SIMD3: arraydestroy.done21: @@ -5705,7 +5705,7 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// SIMD3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { +// SIMD3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // SIMD3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -5713,7 +5713,7 @@ int foobar() { // SIMD3: arraydestroy.body: // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD3-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0) // SIMD3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD3: arraydestroy.done1: @@ -5737,7 +5737,7 @@ int foobar() { // SIMD3-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]] // SIMD3: init: // SIMD3-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* @_ZL3gs1, i32 0, i32 0), align 4 -// SIMD3-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef @_ZZ4mainE2sm, i32 noundef [[TMP2]]) +// SIMD3-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 [[TMP2]]) // SIMD3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] // SIMD3: invoke.cont: // SIMD3-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.Smain*)* @_ZZ4mainEN5SmainD1Ev to void (i8*)*), i8* bitcast (%struct.Smain* @_ZZ4mainE2sm to i8*), i8* @__dso_handle) #[[ATTR3]] @@ -5799,7 +5799,7 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// SIMD3-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD3-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5807,17 +5807,17 @@ int foobar() { // SIMD3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // SIMD3-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 // SIMD3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD3-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* noundef [[THIS1]], i32 noundef [[TMP0]]) +// SIMD3-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]], i32 [[TMP0]]) // SIMD3-NEXT: ret void // // // SIMD3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// SIMD3-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// SIMD3-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD3-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 // SIMD3-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD3-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* noundef [[THIS1]]) #[[ATTR3]] +// SIMD3-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] // SIMD3-NEXT: ret void // // @@ -5867,7 +5867,7 @@ int foobar() { // SIMD3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 // SIMD3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]] // SIMD3: init.check: -// SIMD3-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef @_ZN2STI2S4E2stE, i32 noundef 23) +// SIMD3-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 23) // SIMD3-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S4*)* @_ZN2S4D1Ev to void (i8*)*), i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* @__dso_handle) #[[ATTR3]] // SIMD3-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8 // SIMD3-NEXT: br label [[INIT_END]] @@ -5876,7 +5876,7 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// SIMD3-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// SIMD3-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5884,22 +5884,22 @@ int foobar() { // SIMD3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 // SIMD3-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 // SIMD3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD3-NEXT: call void @_ZN2S4C2Ei(%struct.S4* noundef [[THIS1]], i32 noundef [[TMP0]]) +// SIMD3-NEXT: call void @_ZN2S4C2Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]], i32 [[TMP0]]) // SIMD3-NEXT: ret void // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// SIMD3-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD3-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD3-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 // SIMD3-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// SIMD3-NEXT: call void @_ZN2S4D2Ev(%struct.S4* noundef [[THIS1]]) #[[ATTR3]] +// SIMD3-NEXT: call void @_ZN2S4D2Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] // SIMD3-NEXT: ret void // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// SIMD3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD3-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5913,7 +5913,7 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// SIMD3-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD3-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 @@ -5924,7 +5924,7 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// SIMD3-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD3-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5938,7 +5938,7 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// SIMD3-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD3-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD3-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 @@ -5949,7 +5949,7 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// SIMD3-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// SIMD3-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5963,7 +5963,7 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// SIMD3-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// SIMD3-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD3-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 @@ -5974,7 +5974,7 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// SIMD3-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD3-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -5988,7 +5988,7 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// SIMD3-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD3-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD3-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 @@ -6010,179 +6010,179 @@ int foobar() { // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init // SIMD4-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG115:![0-9]+]] { // SIMD4-NEXT: entry: -// SIMD4-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef @_ZL3gs1, i32 noundef 5), !dbg [[DBG118:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S1*)* @_ZN2S1D1Ev to void (i8*)*), i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG120:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG121:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 5), !dbg [[DBG119:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S1*)* @_ZN2S1D1Ev to void (i8*)*), i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG121:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG122:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// SIMD4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG122:![0-9]+]] { +// SIMD4-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG123:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META123:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META124:![0-9]+]], metadata !DIExpression()), !dbg [[DBG126:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG128:![0-9]+]] -// SIMD4-NEXT: call void @_ZN2S1C2Ei(%struct.S1* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG128]] -// SIMD4-NEXT: ret void, !dbg [[DBG129:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S1C2Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG129]] +// SIMD4-NEXT: ret void, !dbg [[DBG130:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// SIMD4-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG130:![0-9]+]] { +// SIMD4-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META131:![0-9]+]], metadata !DIExpression()), !dbg [[DBG132:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG133:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @_ZN2S1D2Ev(%struct.S1* noundef [[THIS1]]) #[[ATTR3]], !dbg [[DBG133:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG134:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S1D2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG134:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG135:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG135:![0-9]+]] { +// SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG136:![0-9]+]] { // SIMD4-NEXT: entry: -// SIMD4-NEXT: call void @_ZN2S2C1Ei(%struct.S2* noundef @_ZL3gs2, i32 noundef 27), !dbg [[DBG136:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S2*)* @_ZN2S2D1Ev to void (i8*)*), i8* bitcast (%struct.S2* @_ZL3gs2 to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG138:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG139:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S2C1Ei(%struct.S2* nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 27), !dbg [[DBG137:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S2*)* @_ZN2S2D1Ev to void (i8*)*), i8* bitcast (%struct.S2* @_ZL3gs2 to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG139:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG140:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// SIMD4-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG140:![0-9]+]] { +// SIMD4-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG141:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META141:![0-9]+]], metadata !DIExpression()), !dbg [[DBG143:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META142:![0-9]+]], metadata !DIExpression()), !dbg [[DBG144:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META144:![0-9]+]], metadata !DIExpression()), !dbg [[DBG145:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META145:![0-9]+]], metadata !DIExpression()), !dbg [[DBG146:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG146:![0-9]+]] -// SIMD4-NEXT: call void @_ZN2S2C2Ei(%struct.S2* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG146]] -// SIMD4-NEXT: ret void, !dbg [[DBG147:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG147:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S2C2Ei(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG147]] +// SIMD4-NEXT: ret void, !dbg [[DBG148:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// SIMD4-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG148:![0-9]+]] { +// SIMD4-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG149:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD4-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META149:![0-9]+]], metadata !DIExpression()), !dbg [[DBG150:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META150:![0-9]+]], metadata !DIExpression()), !dbg [[DBG151:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @_ZN2S2D2Ev(%struct.S2* noundef [[THIS1]]) #[[ATTR3]], !dbg [[DBG151:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG152:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S2D2Ev(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG152:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG153:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// SIMD4-SAME: () #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG153:![0-9]+]] { +// SIMD4-SAME: () #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG154:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca [3 x %struct.S1]*, align 8 // SIMD4-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca %struct.S1*, align 8 // SIMD4-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // SIMD4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // SIMD4-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca %struct.S1*, align 8 -// SIMD4-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154:![0-9]+]] -// SIMD4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156:![0-9]+]] -// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 noundef 1) -// SIMD4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG157:![0-9]+]] +// SIMD4-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155:![0-9]+]] +// SIMD4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157:![0-9]+]] +// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 1) +// SIMD4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG158:![0-9]+]] // SIMD4: invoke.cont: -// SIMD4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] -// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 noundef 2) -// SIMD4-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG158:![0-9]+]] +// SIMD4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] +// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 2) +// SIMD4-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]] // SIMD4: invoke.cont2: -// SIMD4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] -// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 noundef 3) -// SIMD4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]] +// SIMD4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] +// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 3) +// SIMD4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG160:![0-9]+]] // SIMD4: invoke.cont3: -// SIMD4-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] -// SIMD4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160:![0-9]+]] -// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 noundef 4) -// SIMD4-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG161:![0-9]+]] +// SIMD4-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]] +// SIMD4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161:![0-9]+]] +// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 4) +// SIMD4-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG162:![0-9]+]] // SIMD4: invoke.cont7: -// SIMD4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] -// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 noundef 5) -// SIMD4-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG162:![0-9]+]] +// SIMD4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] +// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 5) +// SIMD4-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]] // SIMD4: invoke.cont8: -// SIMD4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] -// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 noundef 6) -// SIMD4-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]] +// SIMD4-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] +// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 6) +// SIMD4-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG164:![0-9]+]] // SIMD4: invoke.cont9: -// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG164:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG164]] +// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG165:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG165]] // SIMD4: lpad: // SIMD4-NEXT: [[TMP1:%.*]] = landingpad { i8*, i32 } -// SIMD4-NEXT: cleanup, !dbg [[DBG165:![0-9]+]] -// SIMD4-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0, !dbg [[DBG165]] -// SIMD4-NEXT: store i8* [[TMP2]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG165]] -// SIMD4-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 1, !dbg [[DBG165]] -// SIMD4-NEXT: store i32 [[TMP3]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] -// SIMD4-NEXT: [[TMP4:%.*]] = load %struct.S1*, %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] -// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), [[TMP4]], !dbg [[DBG156]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG156]] +// SIMD4-NEXT: cleanup, !dbg [[DBG166:![0-9]+]] +// SIMD4-NEXT: [[TMP2:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 0, !dbg [[DBG166]] +// SIMD4-NEXT: store i8* [[TMP2]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG166]] +// SIMD4-NEXT: [[TMP3:%.*]] = extractvalue { i8*, i32 } [[TMP1]], 1, !dbg [[DBG166]] +// SIMD4-NEXT: store i32 [[TMP3]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]] +// SIMD4-NEXT: [[TMP4:%.*]] = load %struct.S1*, %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] +// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), [[TMP4]], !dbg [[DBG157]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG157]] // SIMD4: arraydestroy.body: -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG156]] -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG156]] -// SIMD4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG156]] -// SIMD4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG156]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG156]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG157]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG157]] +// SIMD4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG157]] +// SIMD4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG157]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG157]] // SIMD4: arraydestroy.done4: -// SIMD4-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG156]] +// SIMD4-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG157]] // SIMD4: lpad6: // SIMD4-NEXT: [[TMP5:%.*]] = landingpad { i8*, i32 } -// SIMD4-NEXT: cleanup, !dbg [[DBG165]] -// SIMD4-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 0, !dbg [[DBG165]] -// SIMD4-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG165]] -// SIMD4-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1, !dbg [[DBG165]] -// SIMD4-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] -// SIMD4-NEXT: [[TMP8:%.*]] = load %struct.S1*, %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] -// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), [[TMP8]], !dbg [[DBG160]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG160]] +// SIMD4-NEXT: cleanup, !dbg [[DBG166]] +// SIMD4-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 0, !dbg [[DBG166]] +// SIMD4-NEXT: store i8* [[TMP6]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG166]] +// SIMD4-NEXT: [[TMP7:%.*]] = extractvalue { i8*, i32 } [[TMP5]], 1, !dbg [[DBG166]] +// SIMD4-NEXT: store i32 [[TMP7]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]] +// SIMD4-NEXT: [[TMP8:%.*]] = load %struct.S1*, %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] +// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), [[TMP8]], !dbg [[DBG161]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG161]] // SIMD4: arraydestroy.body11: -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi %struct.S1* [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG160]] -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG160]] -// SIMD4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG160]] -// SIMD4-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), !dbg [[DBG160]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG160]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi %struct.S1* [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG161]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG161]] +// SIMD4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG161]] +// SIMD4-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), !dbg [[DBG161]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG161]] // SIMD4: arraydestroy.done15: -// SIMD4-NEXT: br label [[EHCLEANUP]], !dbg [[DBG160]] +// SIMD4-NEXT: br label [[EHCLEANUP]], !dbg [[DBG161]] // SIMD4: ehcleanup: -// SIMD4-NEXT: [[TMP9:%.*]] = load [3 x %struct.S1]*, [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] -// SIMD4-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[TMP9]], i64 0, i64 0, !dbg [[DBG154]] -// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), [[PAD_ARRAYEND]], !dbg [[DBG154]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG154]] +// SIMD4-NEXT: [[TMP9:%.*]] = load [3 x %struct.S1]*, [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]] +// SIMD4-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[TMP9]], i64 0, i64 0, !dbg [[DBG155]] +// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), [[PAD_ARRAYEND]], !dbg [[DBG155]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG155]] // SIMD4: arraydestroy.body17: -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG154]] -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG154]] -// SIMD4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG154]] -// SIMD4-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG154]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG154]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG155]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG155]] +// SIMD4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG155]] +// SIMD4-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG155]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG155]] // SIMD4: arraydestroy.done21: -// SIMD4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG154]] +// SIMD4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG155]] // SIMD4: eh.resume: -// SIMD4-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG154]] -// SIMD4-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG154]] -// SIMD4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0, !dbg [[DBG154]] -// SIMD4-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG154]] -// SIMD4-NEXT: resume { i8*, i32 } [[LPAD_VAL22]], !dbg [[DBG154]] +// SIMD4-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG155]] +// SIMD4-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG155]] +// SIMD4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0, !dbg [[DBG155]] +// SIMD4-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG155]] +// SIMD4-NEXT: resume { i8*, i32 } [[LPAD_VAL22]], !dbg [[DBG155]] // // // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// SIMD4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG166:![0-9]+]] { +// SIMD4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG167:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // SIMD4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG171:![0-9]+]] -// SIMD4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG171]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG172:![0-9]+]] +// SIMD4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG172]] // SIMD4: arraydestroy.body: -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG171]] -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG171]] -// SIMD4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG171]] -// SIMD4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), !dbg [[DBG171]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG171]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG172]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG172]] +// SIMD4-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG172]] +// SIMD4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), !dbg [[DBG172]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG172]] // SIMD4: arraydestroy.done1: -// SIMD4-NEXT: ret void, !dbg [[DBG171]] +// SIMD4-NEXT: ret void, !dbg [[DBG172]] // // // SIMD4-LABEL: define {{[^@]+}}@main @@ -6193,366 +6193,366 @@ int foobar() { // SIMD4-NEXT: [[EXN_SLOT:%.*]] = alloca i8*, align 8 // SIMD4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[RES]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG173:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE2sm to i8*) acquire, align 8, !dbg [[DBG174:![0-9]+]] -// SIMD4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG174]] -// SIMD4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG174]], !prof [[PROF175:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[RES]], metadata [[META173:![0-9]+]], metadata !DIExpression()), !dbg [[DBG174:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE2sm to i8*) acquire, align 8, !dbg [[DBG175:![0-9]+]] +// SIMD4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG175]] +// SIMD4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG175]], !prof [[PROF176:![0-9]+]] // SIMD4: init.check: -// SIMD4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG174]] -// SIMD4-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG174]] +// SIMD4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG175]] +// SIMD4-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG175]] // SIMD4: init: -// SIMD4-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* @_ZL3gs1, i32 0, i32 0), align 4, !dbg [[DBG176:![0-9]+]] -// SIMD4-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef @_ZZ4mainE2sm, i32 noundef [[TMP2]]) -// SIMD4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG177:![0-9]+]] +// SIMD4-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* @_ZL3gs1, i32 0, i32 0), align 4, !dbg [[DBG177:![0-9]+]] +// SIMD4-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 [[TMP2]]) +// SIMD4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG178:![0-9]+]] // SIMD4: invoke.cont: -// SIMD4-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.Smain*)* @_ZZ4mainEN5SmainD1Ev to void (i8*)*), i8* bitcast (%struct.Smain* @_ZZ4mainE2sm to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG174]] -// SIMD4-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD4-NEXT: br label [[INIT_END]], !dbg [[DBG174]] +// SIMD4-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.Smain*)* @_ZZ4mainEN5SmainD1Ev to void (i8*)*), i8* bitcast (%struct.Smain* @_ZZ4mainE2sm to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG175]] +// SIMD4-NEXT: call void @__cxa_guard_release(i64* @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD4-NEXT: br label [[INIT_END]], !dbg [[DBG175]] // SIMD4: init.end: -// SIMD4-NEXT: [[TMP4:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S3:%.*]], %struct.S3* @_ZN6Static1sE, i32 0, i32 0), align 4, !dbg [[DBG178:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP4]], i32* [[RES]], align 4, !dbg [[DBG179:![0-9]+]] -// SIMD4-NEXT: [[TMP5:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SMAIN:%.*]], %struct.Smain* @_ZZ4mainE2sm, i32 0, i32 0), align 8, !dbg [[DBG180:![0-9]+]] -// SIMD4-NEXT: [[TMP6:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG181:![0-9]+]] -// SIMD4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG181]] -// SIMD4-NEXT: store i32 [[ADD]], i32* [[RES]], align 4, !dbg [[DBG181]] -// SIMD4-NEXT: [[TMP7:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1]], %struct.S1* @_ZL3gs1, i32 0, i32 0), align 4, !dbg [[DBG182:![0-9]+]] -// SIMD4-NEXT: [[TMP8:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG183:![0-9]+]] -// SIMD4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG183]] -// SIMD4-NEXT: store i32 [[ADD1]], i32* [[RES]], align 4, !dbg [[DBG183]] -// SIMD4-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S2:%.*]], %struct.S2* @_ZL3gs2, i32 0, i32 0), align 8, !dbg [[DBG184:![0-9]+]] -// SIMD4-NEXT: [[TMP10:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG185:![0-9]+]] -// SIMD4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG185]] -// SIMD4-NEXT: store i32 [[ADD2]], i32* [[RES]], align 4, !dbg [[DBG185]] -// SIMD4-NEXT: [[TMP11:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S5:%.*]], %struct.S5* @gs3, i32 0, i32 0), align 4, !dbg [[DBG186:![0-9]+]] -// SIMD4-NEXT: [[TMP12:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG187:![0-9]+]] -// SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG187]] -// SIMD4-NEXT: store i32 [[ADD3]], i32* [[RES]], align 4, !dbg [[DBG187]] -// SIMD4-NEXT: [[TMP13:%.*]] = load i32, i32* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1, i32 0), align 4, !dbg [[DBG188:![0-9]+]] -// SIMD4-NEXT: [[TMP14:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG189:![0-9]+]] -// SIMD4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG189]] -// SIMD4-NEXT: store i32 [[ADD4]], i32* [[RES]], align 4, !dbg [[DBG189]] -// SIMD4-NEXT: [[TMP15:%.*]] = load i32, i32* @_ZN2STIiE2stE, align 4, !dbg [[DBG190:![0-9]+]] -// SIMD4-NEXT: [[TMP16:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG191:![0-9]+]] -// SIMD4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG191]] -// SIMD4-NEXT: store i32 [[ADD5]], i32* [[RES]], align 4, !dbg [[DBG191]] -// SIMD4-NEXT: [[TMP17:%.*]] = load float, float* @_ZN2STIfE2stE, align 4, !dbg [[DBG192:![0-9]+]] -// SIMD4-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG192]] -// SIMD4-NEXT: [[TMP18:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG193:![0-9]+]] -// SIMD4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG193]] -// SIMD4-NEXT: store i32 [[ADD6]], i32* [[RES]], align 4, !dbg [[DBG193]] -// SIMD4-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S4:%.*]], %struct.S4* @_ZN2STI2S4E2stE, i32 0, i32 0), align 4, !dbg [[DBG194:![0-9]+]] -// SIMD4-NEXT: [[TMP20:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG195:![0-9]+]] -// SIMD4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG195]] -// SIMD4-NEXT: store i32 [[ADD7]], i32* [[RES]], align 4, !dbg [[DBG195]] -// SIMD4-NEXT: [[TMP21:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG196:![0-9]+]] -// SIMD4-NEXT: ret i32 [[TMP21]], !dbg [[DBG197:![0-9]+]] +// SIMD4-NEXT: [[TMP4:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S3:%.*]], %struct.S3* @_ZN6Static1sE, i32 0, i32 0), align 4, !dbg [[DBG179:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP4]], i32* [[RES]], align 4, !dbg [[DBG180:![0-9]+]] +// SIMD4-NEXT: [[TMP5:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SMAIN:%.*]], %struct.Smain* @_ZZ4mainE2sm, i32 0, i32 0), align 8, !dbg [[DBG181:![0-9]+]] +// SIMD4-NEXT: [[TMP6:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG182:![0-9]+]] +// SIMD4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG182]] +// SIMD4-NEXT: store i32 [[ADD]], i32* [[RES]], align 4, !dbg [[DBG182]] +// SIMD4-NEXT: [[TMP7:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1]], %struct.S1* @_ZL3gs1, i32 0, i32 0), align 4, !dbg [[DBG183:![0-9]+]] +// SIMD4-NEXT: [[TMP8:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG184:![0-9]+]] +// SIMD4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG184]] +// SIMD4-NEXT: store i32 [[ADD1]], i32* [[RES]], align 4, !dbg [[DBG184]] +// SIMD4-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S2:%.*]], %struct.S2* @_ZL3gs2, i32 0, i32 0), align 8, !dbg [[DBG185:![0-9]+]] +// SIMD4-NEXT: [[TMP10:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG186:![0-9]+]] +// SIMD4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG186]] +// SIMD4-NEXT: store i32 [[ADD2]], i32* [[RES]], align 4, !dbg [[DBG186]] +// SIMD4-NEXT: [[TMP11:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S5:%.*]], %struct.S5* @gs3, i32 0, i32 0), align 4, !dbg [[DBG187:![0-9]+]] +// SIMD4-NEXT: [[TMP12:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG188:![0-9]+]] +// SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG188]] +// SIMD4-NEXT: store i32 [[ADD3]], i32* [[RES]], align 4, !dbg [[DBG188]] +// SIMD4-NEXT: [[TMP13:%.*]] = load i32, i32* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1, i32 0), align 4, !dbg [[DBG189:![0-9]+]] +// SIMD4-NEXT: [[TMP14:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG190:![0-9]+]] +// SIMD4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG190]] +// SIMD4-NEXT: store i32 [[ADD4]], i32* [[RES]], align 4, !dbg [[DBG190]] +// SIMD4-NEXT: [[TMP15:%.*]] = load i32, i32* @_ZN2STIiE2stE, align 4, !dbg [[DBG191:![0-9]+]] +// SIMD4-NEXT: [[TMP16:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG192:![0-9]+]] +// SIMD4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG192]] +// SIMD4-NEXT: store i32 [[ADD5]], i32* [[RES]], align 4, !dbg [[DBG192]] +// SIMD4-NEXT: [[TMP17:%.*]] = load float, float* @_ZN2STIfE2stE, align 4, !dbg [[DBG193:![0-9]+]] +// SIMD4-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG193]] +// SIMD4-NEXT: [[TMP18:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG194:![0-9]+]] +// SIMD4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG194]] +// SIMD4-NEXT: store i32 [[ADD6]], i32* [[RES]], align 4, !dbg [[DBG194]] +// SIMD4-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S4:%.*]], %struct.S4* @_ZN2STI2S4E2stE, i32 0, i32 0), align 4, !dbg [[DBG195:![0-9]+]] +// SIMD4-NEXT: [[TMP20:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG196:![0-9]+]] +// SIMD4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG196]] +// SIMD4-NEXT: store i32 [[ADD7]], i32* [[RES]], align 4, !dbg [[DBG196]] +// SIMD4-NEXT: [[TMP21:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG197:![0-9]+]] +// SIMD4-NEXT: ret i32 [[TMP21]], !dbg [[DBG198:![0-9]+]] // SIMD4: lpad: // SIMD4-NEXT: [[TMP22:%.*]] = landingpad { i8*, i32 } -// SIMD4-NEXT: cleanup, !dbg [[DBG198:![0-9]+]] -// SIMD4-NEXT: [[TMP23:%.*]] = extractvalue { i8*, i32 } [[TMP22]], 0, !dbg [[DBG198]] -// SIMD4-NEXT: store i8* [[TMP23]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG198]] -// SIMD4-NEXT: [[TMP24:%.*]] = extractvalue { i8*, i32 } [[TMP22]], 1, !dbg [[DBG198]] -// SIMD4-NEXT: store i32 [[TMP24]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG198]] -// SIMD4-NEXT: call void @__cxa_guard_abort(i64* @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG174]] +// SIMD4-NEXT: cleanup, !dbg [[DBG199:![0-9]+]] +// SIMD4-NEXT: [[TMP23:%.*]] = extractvalue { i8*, i32 } [[TMP22]], 0, !dbg [[DBG199]] +// SIMD4-NEXT: store i8* [[TMP23]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG199]] +// SIMD4-NEXT: [[TMP24:%.*]] = extractvalue { i8*, i32 } [[TMP22]], 1, !dbg [[DBG199]] +// SIMD4-NEXT: store i32 [[TMP24]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG199]] +// SIMD4-NEXT: call void @__cxa_guard_abort(i64* @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG175]] // SIMD4: eh.resume: -// SIMD4-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG174]] -// SIMD4-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG174]] -// SIMD4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0, !dbg [[DBG174]] -// SIMD4-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG174]] -// SIMD4-NEXT: resume { i8*, i32 } [[LPAD_VAL8]], !dbg [[DBG174]] +// SIMD4-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG175]] +// SIMD4-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG175]] +// SIMD4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0, !dbg [[DBG175]] +// SIMD4-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG175]] +// SIMD4-NEXT: resume { i8*, i32 } [[LPAD_VAL8]], !dbg [[DBG175]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// SIMD4-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG199:![0-9]+]] { +// SIMD4-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG200:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META200:![0-9]+]], metadata !DIExpression()), !dbg [[DBG202:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META201:![0-9]+]], metadata !DIExpression()), !dbg [[DBG203:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META203:![0-9]+]], metadata !DIExpression()), !dbg [[DBG204:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META204:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG205:![0-9]+]] -// SIMD4-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG205]] -// SIMD4-NEXT: ret void, !dbg [[DBG206:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG206:![0-9]+]] +// SIMD4-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG206]] +// SIMD4-NEXT: ret void, !dbg [[DBG207:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// SIMD4-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG207:![0-9]+]] { +// SIMD4-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG208:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD4-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META208:![0-9]+]], metadata !DIExpression()), !dbg [[DBG209:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META209:![0-9]+]], metadata !DIExpression()), !dbg [[DBG210:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* noundef [[THIS1]]) #[[ATTR3]], !dbg [[DBG210:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG211:![0-9]+]] +// SIMD4-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG211:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG212:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_Z6foobarv -// SIMD4-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG212:![0-9]+]] { +// SIMD4-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG213:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[RES:%.*]] = alloca i32, align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[RES]], metadata [[META213:![0-9]+]], metadata !DIExpression()), !dbg [[DBG214:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S3:%.*]], %struct.S3* @_ZN6Static1sE, i32 0, i32 0), align 4, !dbg [[DBG215:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP0]], i32* [[RES]], align 4, !dbg [[DBG216:![0-9]+]] -// SIMD4-NEXT: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* @_ZL3gs1, i32 0, i32 0), align 4, !dbg [[DBG217:![0-9]+]] -// SIMD4-NEXT: [[TMP2:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG218:![0-9]+]] -// SIMD4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG218]] -// SIMD4-NEXT: store i32 [[ADD]], i32* [[RES]], align 4, !dbg [[DBG218]] -// SIMD4-NEXT: [[TMP3:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S2:%.*]], %struct.S2* @_ZL3gs2, i32 0, i32 0), align 8, !dbg [[DBG219:![0-9]+]] -// SIMD4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG220:![0-9]+]] -// SIMD4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG220]] -// SIMD4-NEXT: store i32 [[ADD1]], i32* [[RES]], align 4, !dbg [[DBG220]] -// SIMD4-NEXT: [[TMP5:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S5:%.*]], %struct.S5* @gs3, i32 0, i32 0), align 4, !dbg [[DBG221:![0-9]+]] -// SIMD4-NEXT: [[TMP6:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG222:![0-9]+]] -// SIMD4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG222]] -// SIMD4-NEXT: store i32 [[ADD2]], i32* [[RES]], align 4, !dbg [[DBG222]] -// SIMD4-NEXT: [[TMP7:%.*]] = load i32, i32* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1, i32 0), align 4, !dbg [[DBG223:![0-9]+]] -// SIMD4-NEXT: [[TMP8:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG224:![0-9]+]] -// SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG224]] -// SIMD4-NEXT: store i32 [[ADD3]], i32* [[RES]], align 4, !dbg [[DBG224]] -// SIMD4-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZN2STIiE2stE, align 4, !dbg [[DBG225:![0-9]+]] -// SIMD4-NEXT: [[TMP10:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG226:![0-9]+]] -// SIMD4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG226]] -// SIMD4-NEXT: store i32 [[ADD4]], i32* [[RES]], align 4, !dbg [[DBG226]] -// SIMD4-NEXT: [[TMP11:%.*]] = load float, float* @_ZN2STIfE2stE, align 4, !dbg [[DBG227:![0-9]+]] -// SIMD4-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG227]] -// SIMD4-NEXT: [[TMP12:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG228:![0-9]+]] -// SIMD4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG228]] -// SIMD4-NEXT: store i32 [[ADD5]], i32* [[RES]], align 4, !dbg [[DBG228]] -// SIMD4-NEXT: [[TMP13:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S4:%.*]], %struct.S4* @_ZN2STI2S4E2stE, i32 0, i32 0), align 4, !dbg [[DBG229:![0-9]+]] -// SIMD4-NEXT: [[TMP14:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG230:![0-9]+]] -// SIMD4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG230]] -// SIMD4-NEXT: store i32 [[ADD6]], i32* [[RES]], align 4, !dbg [[DBG230]] -// SIMD4-NEXT: [[TMP15:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG231:![0-9]+]] -// SIMD4-NEXT: ret i32 [[TMP15]], !dbg [[DBG232:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[RES]], metadata [[META214:![0-9]+]], metadata !DIExpression()), !dbg [[DBG215:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S3:%.*]], %struct.S3* @_ZN6Static1sE, i32 0, i32 0), align 4, !dbg [[DBG216:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP0]], i32* [[RES]], align 4, !dbg [[DBG217:![0-9]+]] +// SIMD4-NEXT: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* @_ZL3gs1, i32 0, i32 0), align 4, !dbg [[DBG218:![0-9]+]] +// SIMD4-NEXT: [[TMP2:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG219:![0-9]+]] +// SIMD4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG219]] +// SIMD4-NEXT: store i32 [[ADD]], i32* [[RES]], align 4, !dbg [[DBG219]] +// SIMD4-NEXT: [[TMP3:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S2:%.*]], %struct.S2* @_ZL3gs2, i32 0, i32 0), align 8, !dbg [[DBG220:![0-9]+]] +// SIMD4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG221:![0-9]+]] +// SIMD4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG221]] +// SIMD4-NEXT: store i32 [[ADD1]], i32* [[RES]], align 4, !dbg [[DBG221]] +// SIMD4-NEXT: [[TMP5:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S5:%.*]], %struct.S5* @gs3, i32 0, i32 0), align 4, !dbg [[DBG222:![0-9]+]] +// SIMD4-NEXT: [[TMP6:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG223:![0-9]+]] +// SIMD4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG223]] +// SIMD4-NEXT: store i32 [[ADD2]], i32* [[RES]], align 4, !dbg [[DBG223]] +// SIMD4-NEXT: [[TMP7:%.*]] = load i32, i32* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1, i32 0), align 4, !dbg [[DBG224:![0-9]+]] +// SIMD4-NEXT: [[TMP8:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG225:![0-9]+]] +// SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG225]] +// SIMD4-NEXT: store i32 [[ADD3]], i32* [[RES]], align 4, !dbg [[DBG225]] +// SIMD4-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZN2STIiE2stE, align 4, !dbg [[DBG226:![0-9]+]] +// SIMD4-NEXT: [[TMP10:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG227:![0-9]+]] +// SIMD4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG227]] +// SIMD4-NEXT: store i32 [[ADD4]], i32* [[RES]], align 4, !dbg [[DBG227]] +// SIMD4-NEXT: [[TMP11:%.*]] = load float, float* @_ZN2STIfE2stE, align 4, !dbg [[DBG228:![0-9]+]] +// SIMD4-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG228]] +// SIMD4-NEXT: [[TMP12:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG229:![0-9]+]] +// SIMD4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG229]] +// SIMD4-NEXT: store i32 [[ADD5]], i32* [[RES]], align 4, !dbg [[DBG229]] +// SIMD4-NEXT: [[TMP13:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S4:%.*]], %struct.S4* @_ZN2STI2S4E2stE, i32 0, i32 0), align 4, !dbg [[DBG230:![0-9]+]] +// SIMD4-NEXT: [[TMP14:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG231:![0-9]+]] +// SIMD4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG231]] +// SIMD4-NEXT: store i32 [[ADD6]], i32* [[RES]], align 4, !dbg [[DBG231]] +// SIMD4-NEXT: [[TMP15:%.*]] = load i32, i32* [[RES]], align 4, !dbg [[DBG232:![0-9]+]] +// SIMD4-NEXT: ret i32 [[TMP15]], !dbg [[DBG233:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 -// SIMD4-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG233:![0-9]+]] { +// SIMD4-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG234:![0-9]+]] { // SIMD4-NEXT: entry: -// SIMD4-NEXT: [[TMP0:%.*]] = load i8, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8, !dbg [[DBG234:![0-9]+]] -// SIMD4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG234]] -// SIMD4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG234]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i8, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8, !dbg [[DBG235:![0-9]+]] +// SIMD4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG235]] +// SIMD4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG235]] // SIMD4: init.check: -// SIMD4-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG235:![0-9]+]] -// SIMD4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S4*)* @_ZN2S4D1Ev to void (i8*)*), i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG234]] -// SIMD4-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8, !dbg [[DBG234]] -// SIMD4-NEXT: br label [[INIT_END]], !dbg [[DBG234]] +// SIMD4-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 23), !dbg [[DBG236:![0-9]+]] +// SIMD4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S4*)* @_ZN2S4D1Ev to void (i8*)*), i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* @__dso_handle) #[[ATTR3]], !dbg [[DBG235]] +// SIMD4-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8, !dbg [[DBG235]] +// SIMD4-NEXT: br label [[INIT_END]], !dbg [[DBG235]] // SIMD4: init.end: -// SIMD4-NEXT: ret void, !dbg [[DBG237:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG238:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// SIMD4-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG238:![0-9]+]] { +// SIMD4-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG239:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META239:![0-9]+]], metadata !DIExpression()), !dbg [[DBG241:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META240:![0-9]+]], metadata !DIExpression()), !dbg [[DBG242:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META242:![0-9]+]], metadata !DIExpression()), !dbg [[DBG243:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META243:![0-9]+]], metadata !DIExpression()), !dbg [[DBG244:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG244:![0-9]+]] -// SIMD4-NEXT: call void @_ZN2S4C2Ei(%struct.S4* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG244]] -// SIMD4-NEXT: ret void, !dbg [[DBG245:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG245:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S4C2Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG245]] +// SIMD4-NEXT: ret void, !dbg [[DBG246:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// SIMD4-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG246:![0-9]+]] { +// SIMD4-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG247:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD4-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META247:![0-9]+]], metadata !DIExpression()), !dbg [[DBG248:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META248:![0-9]+]], metadata !DIExpression()), !dbg [[DBG249:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @_ZN2S4D2Ev(%struct.S4* noundef [[THIS1]]) #[[ATTR3]], !dbg [[DBG249:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG250:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S4D2Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG250:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG251:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// SIMD4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG251:![0-9]+]] { +// SIMD4-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG252:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META252:![0-9]+]], metadata !DIExpression()), !dbg [[DBG253:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META253:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META254:![0-9]+]], metadata !DIExpression()), !dbg [[DBG255:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META255:![0-9]+]], metadata !DIExpression()), !dbg [[DBG256:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0, !dbg [[DBG256:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG257:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP0]], i32* [[A2]], align 4, !dbg [[DBG256]] -// SIMD4-NEXT: ret void, !dbg [[DBG258:![0-9]+]] +// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0, !dbg [[DBG257:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG258:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP0]], i32* [[A2]], align 4, !dbg [[DBG257]] +// SIMD4-NEXT: ret void, !dbg [[DBG259:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// SIMD4-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG259:![0-9]+]] { +// SIMD4-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG260:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // SIMD4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META260:![0-9]+]], metadata !DIExpression()), !dbg [[DBG261:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META261:![0-9]+]], metadata !DIExpression()), !dbg [[DBG262:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0, !dbg [[DBG262:![0-9]+]] -// SIMD4-NEXT: store i32 0, i32* [[A]], align 4, !dbg [[DBG264:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG265:![0-9]+]] +// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0, !dbg [[DBG263:![0-9]+]] +// SIMD4-NEXT: store i32 0, i32* [[A]], align 4, !dbg [[DBG265:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG266:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// SIMD4-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG266:![0-9]+]] { +// SIMD4-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG267:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META267:![0-9]+]], metadata !DIExpression()), !dbg [[DBG268:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META268:![0-9]+]], metadata !DIExpression()), !dbg [[DBG269:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META269:![0-9]+]], metadata !DIExpression()), !dbg [[DBG270:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META270:![0-9]+]], metadata !DIExpression()), !dbg [[DBG271:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], %struct.S2* [[THIS1]], i32 0, i32 0, !dbg [[DBG271:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG272:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP0]], i32* [[A2]], align 8, !dbg [[DBG271]] -// SIMD4-NEXT: ret void, !dbg [[DBG273:![0-9]+]] +// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], %struct.S2* [[THIS1]], i32 0, i32 0, !dbg [[DBG272:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG273:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP0]], i32* [[A2]], align 8, !dbg [[DBG272]] +// SIMD4-NEXT: ret void, !dbg [[DBG274:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// SIMD4-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG274:![0-9]+]] { +// SIMD4-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG275:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // SIMD4-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META275:![0-9]+]], metadata !DIExpression()), !dbg [[DBG276:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META276:![0-9]+]], metadata !DIExpression()), !dbg [[DBG277:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], %struct.S2* [[THIS1]], i32 0, i32 0, !dbg [[DBG277:![0-9]+]] -// SIMD4-NEXT: store i32 0, i32* [[A]], align 8, !dbg [[DBG279:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG280:![0-9]+]] +// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], %struct.S2* [[THIS1]], i32 0, i32 0, !dbg [[DBG278:![0-9]+]] +// SIMD4-NEXT: store i32 0, i32* [[A]], align 8, !dbg [[DBG280:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG281:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// SIMD4-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG281:![0-9]+]] { +// SIMD4-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG282:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META282:![0-9]+]], metadata !DIExpression()), !dbg [[DBG283:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META283:![0-9]+]], metadata !DIExpression()), !dbg [[DBG284:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META284:![0-9]+]], metadata !DIExpression()), !dbg [[DBG285:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META285:![0-9]+]], metadata !DIExpression()), !dbg [[DBG286:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], %struct.Smain* [[THIS1]], i32 0, i32 0, !dbg [[DBG286:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG287:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP0]], i32* [[A2]], align 8, !dbg [[DBG286]] -// SIMD4-NEXT: ret void, !dbg [[DBG288:![0-9]+]] +// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], %struct.Smain* [[THIS1]], i32 0, i32 0, !dbg [[DBG287:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG288:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP0]], i32* [[A2]], align 8, !dbg [[DBG287]] +// SIMD4-NEXT: ret void, !dbg [[DBG289:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// SIMD4-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG289:![0-9]+]] { +// SIMD4-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG290:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // SIMD4-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META290:![0-9]+]], metadata !DIExpression()), !dbg [[DBG291:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META291:![0-9]+]], metadata !DIExpression()), !dbg [[DBG292:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], %struct.Smain* [[THIS1]], i32 0, i32 0, !dbg [[DBG292:![0-9]+]] -// SIMD4-NEXT: store i32 0, i32* [[A]], align 8, !dbg [[DBG294:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG295:![0-9]+]] +// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], %struct.Smain* [[THIS1]], i32 0, i32 0, !dbg [[DBG293:![0-9]+]] +// SIMD4-NEXT: store i32 0, i32* [[A]], align 8, !dbg [[DBG295:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG296:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// SIMD4-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG296:![0-9]+]] { +// SIMD4-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG297:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META297:![0-9]+]], metadata !DIExpression()), !dbg [[DBG298:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META298:![0-9]+]], metadata !DIExpression()), !dbg [[DBG299:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META299:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META300:![0-9]+]], metadata !DIExpression()), !dbg [[DBG301:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], %struct.S4* [[THIS1]], i32 0, i32 0, !dbg [[DBG301:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG302:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP0]], i32* [[A2]], align 4, !dbg [[DBG301]] -// SIMD4-NEXT: ret void, !dbg [[DBG303:![0-9]+]] +// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], %struct.S4* [[THIS1]], i32 0, i32 0, !dbg [[DBG302:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG303:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP0]], i32* [[A2]], align 4, !dbg [[DBG302]] +// SIMD4-NEXT: ret void, !dbg [[DBG304:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// SIMD4-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG304:![0-9]+]] { +// SIMD4-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG305:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // SIMD4-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META305:![0-9]+]], metadata !DIExpression()), !dbg [[DBG306:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META306:![0-9]+]], metadata !DIExpression()), !dbg [[DBG307:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], %struct.S4* [[THIS1]], i32 0, i32 0, !dbg [[DBG307:![0-9]+]] -// SIMD4-NEXT: store i32 0, i32* [[A]], align 4, !dbg [[DBG309:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG310:![0-9]+]] +// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], %struct.S4* [[THIS1]], i32 0, i32 0, !dbg [[DBG308:![0-9]+]] +// SIMD4-NEXT: store i32 0, i32* [[A]], align 4, !dbg [[DBG310:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG311:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp -// SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG311:![0-9]+]] { +// SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG312:![0-9]+]] { // SIMD4-NEXT: entry: -// SIMD4-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG313:![0-9]+]] -// SIMD4-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG313]] -// SIMD4-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG313]] +// SIMD4-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG314:![0-9]+]] +// SIMD4-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG314]] +// SIMD4-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG314]] // SIMD4-NEXT: ret void // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. -// DEBUG1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG116:![0-9]+]] { +// DEBUG1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG115:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META118:![0-9]+]], metadata !DIExpression()), !dbg [[DBG120:![0-9]+]] -// DEBUG1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG121:![0-9]+]] -// DEBUG1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S1*, !dbg [[DBG121]] -// DEBUG1-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef [[TMP2]], i32 noundef 5), !dbg [[DBG122:![0-9]+]] -// DEBUG1-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG121]] -// DEBUG1-NEXT: ret i8* [[TMP3]], !dbg [[DBG121]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META117:![0-9]+]], metadata !DIExpression()), !dbg [[DBG119:![0-9]+]] +// DEBUG1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG120:![0-9]+]] +// DEBUG1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S1*, !dbg [[DBG120]] +// DEBUG1-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[TMP2]], i32 5), !dbg [[DBG121:![0-9]+]] +// DEBUG1-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG120]] +// DEBUG1-NEXT: ret i8* [[TMP3]], !dbg [[DBG120]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// DEBUG1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG123:![0-9]+]] { +// DEBUG1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG122:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META124:![0-9]+]], metadata !DIExpression()), !dbg [[DBG126:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META123:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125:![0-9]+]] // DEBUG1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]] -// DEBUG1-NEXT: call void @_ZN2S1C2Ei(%struct.S1* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG129]] -// DEBUG1-NEXT: ret void, !dbg [[DBG130:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG128:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S1C2Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG128]] +// DEBUG1-NEXT: ret void, !dbg [[DBG129:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. -// DEBUG1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG131:![0-9]+]] { +// DEBUG1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG130:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG133:![0-9]+]] -// DEBUG1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG133]] -// DEBUG1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S1*, !dbg [[DBG133]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[TMP2]]) #[[ATTR4:[0-9]+]], !dbg [[DBG133]] -// DEBUG1-NEXT: ret void, !dbg [[DBG134:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META131:![0-9]+]], metadata !DIExpression()), !dbg [[DBG132:![0-9]+]] +// DEBUG1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG132]] +// DEBUG1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S1*, !dbg [[DBG132]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR4:[0-9]+]], !dbg [[DBG132]] +// DEBUG1-NEXT: ret void, !dbg [[DBG133:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// DEBUG1-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] comdat align 2 !dbg [[DBG135:![0-9]+]] { +// DEBUG1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] comdat align 2 !dbg [[DBG134:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // DEBUG1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META136:![0-9]+]], metadata !DIExpression()), !dbg [[DBG137:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META135:![0-9]+]], metadata !DIExpression()), !dbg [[DBG136:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @_ZN2S1D2Ev(%struct.S1* noundef [[THIS1]]) #[[ATTR4]], !dbg [[DBG138:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG139:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S1D2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]], !dbg [[DBG137:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG138:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_. -// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG140:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG139:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]), !dbg [[DBG141:![0-9]+]] -// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* (i8*)* @.__kmpc_global_ctor_., i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_.), !dbg [[DBG141]] -// DEBUG1-NEXT: ret void, !dbg [[DBG141]] +// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]), !dbg [[DBG140:![0-9]+]] +// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* (i8*)* @.__kmpc_global_ctor_., i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_.), !dbg [[DBG140]] +// DEBUG1-NEXT: ret void, !dbg [[DBG140]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1 -// DEBUG1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG142:![0-9]+]] { +// DEBUG1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG141:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca [3 x %struct.S1]*, align 8 @@ -6561,141 +6561,141 @@ int foobar() { // DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT9:%.*]] = alloca %struct.S1*, align 8 // DEBUG1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META143:![0-9]+]], metadata !DIExpression()), !dbg [[DBG144:![0-9]+]] -// DEBUG1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG145:![0-9]+]] -// DEBUG1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [2 x [3 x %struct.S1]]*, !dbg [[DBG145]] -// DEBUG1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* [[TMP2]], i64 0, i64 0, !dbg [[DBG146:![0-9]+]] -// DEBUG1-NEXT: store [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG146]] -// DEBUG1-NEXT: [[ARRAYINIT_BEGIN1:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], i64 0, i64 0, !dbg [[DBG147:![0-9]+]] -// DEBUG1-NEXT: store %struct.S1* [[ARRAYINIT_BEGIN1]], %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG147]] -// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_BEGIN1]], i32 noundef 1) -// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG148:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META142:![0-9]+]], metadata !DIExpression()), !dbg [[DBG143:![0-9]+]] +// DEBUG1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG144:![0-9]+]] +// DEBUG1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [2 x [3 x %struct.S1]]*, !dbg [[DBG144]] +// DEBUG1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* [[TMP2]], i64 0, i64 0, !dbg [[DBG145:![0-9]+]] +// DEBUG1-NEXT: store [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG145]] +// DEBUG1-NEXT: [[ARRAYINIT_BEGIN1:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], i64 0, i64 0, !dbg [[DBG146:![0-9]+]] +// DEBUG1-NEXT: store %struct.S1* [[ARRAYINIT_BEGIN1]], %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG146]] +// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN1]], i32 1) +// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG147:![0-9]+]] // DEBUG1: invoke.cont: -// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYINIT_BEGIN1]], i64 1, !dbg [[DBG147]] -// DEBUG1-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT]], %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG147]] -// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// DEBUG1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG149:![0-9]+]] +// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYINIT_BEGIN1]], i64 1, !dbg [[DBG146]] +// DEBUG1-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT]], %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG146]] +// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) +// DEBUG1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG148:![0-9]+]] // DEBUG1: invoke.cont3: -// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYINIT_ELEMENT]], i64 1, !dbg [[DBG147]] -// DEBUG1-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT4]], %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG147]] -// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT4]], i32 noundef 3) -// DEBUG1-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]], !dbg [[DBG150:![0-9]+]] +// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYINIT_ELEMENT]], i64 1, !dbg [[DBG146]] +// DEBUG1-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT4]], %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG146]] +// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT4]], i32 3) +// DEBUG1-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]], !dbg [[DBG149:![0-9]+]] // DEBUG1: invoke.cont5: -// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT7:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], i64 1, !dbg [[DBG146]] -// DEBUG1-NEXT: store [3 x %struct.S1]* [[ARRAYINIT_ELEMENT7]], [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG146]] -// DEBUG1-NEXT: [[ARRAYINIT_BEGIN8:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_ELEMENT7]], i64 0, i64 0, !dbg [[DBG151:![0-9]+]] -// DEBUG1-NEXT: store %struct.S1* [[ARRAYINIT_BEGIN8]], %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG151]] -// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_BEGIN8]], i32 noundef 4) -// DEBUG1-NEXT: to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD10:%.*]], !dbg [[DBG152:![0-9]+]] +// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT7:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], i64 1, !dbg [[DBG145]] +// DEBUG1-NEXT: store [3 x %struct.S1]* [[ARRAYINIT_ELEMENT7]], [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG145]] +// DEBUG1-NEXT: [[ARRAYINIT_BEGIN8:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_ELEMENT7]], i64 0, i64 0, !dbg [[DBG150:![0-9]+]] +// DEBUG1-NEXT: store %struct.S1* [[ARRAYINIT_BEGIN8]], %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG150]] +// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN8]], i32 4) +// DEBUG1-NEXT: to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD10:%.*]], !dbg [[DBG151:![0-9]+]] // DEBUG1: invoke.cont11: -// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYINIT_BEGIN8]], i64 1, !dbg [[DBG151]] -// DEBUG1-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT12]], %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG151]] -// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT12]], i32 noundef 5) -// DEBUG1-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD10]], !dbg [[DBG153:![0-9]+]] +// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYINIT_BEGIN8]], i64 1, !dbg [[DBG150]] +// DEBUG1-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT12]], %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG150]] +// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT12]], i32 5) +// DEBUG1-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD10]], !dbg [[DBG152:![0-9]+]] // DEBUG1: invoke.cont13: -// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT14:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYINIT_ELEMENT12]], i64 1, !dbg [[DBG151]] -// DEBUG1-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT14]], %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG151]] -// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT14]], i32 noundef 6) -// DEBUG1-NEXT: to label [[INVOKE_CONT15:%.*]] unwind label [[LPAD10]], !dbg [[DBG154:![0-9]+]] +// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT14:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYINIT_ELEMENT12]], i64 1, !dbg [[DBG150]] +// DEBUG1-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT14]], %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG150]] +// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT14]], i32 6) +// DEBUG1-NEXT: to label [[INVOKE_CONT15:%.*]] unwind label [[LPAD10]], !dbg [[DBG153:![0-9]+]] // DEBUG1: invoke.cont15: -// DEBUG1-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG145]] -// DEBUG1-NEXT: ret i8* [[TMP3]], !dbg [[DBG145]] +// DEBUG1-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG144]] +// DEBUG1-NEXT: ret i8* [[TMP3]], !dbg [[DBG144]] // DEBUG1: lpad: // DEBUG1-NEXT: [[TMP4:%.*]] = landingpad { i8*, i32 } -// DEBUG1-NEXT: cleanup, !dbg [[DBG144]] -// DEBUG1-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0, !dbg [[DBG144]] -// DEBUG1-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG144]] -// DEBUG1-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1, !dbg [[DBG144]] -// DEBUG1-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG144]] -// DEBUG1-NEXT: [[TMP7:%.*]] = load %struct.S1*, %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG147]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq %struct.S1* [[ARRAYINIT_BEGIN1]], [[TMP7]], !dbg [[DBG147]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG147]] +// DEBUG1-NEXT: cleanup, !dbg [[DBG143]] +// DEBUG1-NEXT: [[TMP5:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 0, !dbg [[DBG143]] +// DEBUG1-NEXT: store i8* [[TMP5]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG143]] +// DEBUG1-NEXT: [[TMP6:%.*]] = extractvalue { i8*, i32 } [[TMP4]], 1, !dbg [[DBG143]] +// DEBUG1-NEXT: store i32 [[TMP6]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG143]] +// DEBUG1-NEXT: [[TMP7:%.*]] = load %struct.S1*, %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG146]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq %struct.S1* [[ARRAYINIT_BEGIN1]], [[TMP7]], !dbg [[DBG146]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG146]] // DEBUG1: arraydestroy.body: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP7]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG147]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG147]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG147]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], [[ARRAYINIT_BEGIN1]], !dbg [[DBG147]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG147]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP7]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG146]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG146]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG146]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], [[ARRAYINIT_BEGIN1]], !dbg [[DBG146]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG146]] // DEBUG1: arraydestroy.done6: -// DEBUG1-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG147]] +// DEBUG1-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG146]] // DEBUG1: lpad10: // DEBUG1-NEXT: [[TMP8:%.*]] = landingpad { i8*, i32 } -// DEBUG1-NEXT: cleanup, !dbg [[DBG144]] -// DEBUG1-NEXT: [[TMP9:%.*]] = extractvalue { i8*, i32 } [[TMP8]], 0, !dbg [[DBG144]] -// DEBUG1-NEXT: store i8* [[TMP9]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG144]] -// DEBUG1-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP8]], 1, !dbg [[DBG144]] -// DEBUG1-NEXT: store i32 [[TMP10]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG144]] -// DEBUG1-NEXT: [[TMP11:%.*]] = load %struct.S1*, %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG151]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq %struct.S1* [[ARRAYINIT_BEGIN8]], [[TMP11]], !dbg [[DBG151]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG151]] +// DEBUG1-NEXT: cleanup, !dbg [[DBG143]] +// DEBUG1-NEXT: [[TMP9:%.*]] = extractvalue { i8*, i32 } [[TMP8]], 0, !dbg [[DBG143]] +// DEBUG1-NEXT: store i8* [[TMP9]], i8** [[EXN_SLOT]], align 8, !dbg [[DBG143]] +// DEBUG1-NEXT: [[TMP10:%.*]] = extractvalue { i8*, i32 } [[TMP8]], 1, !dbg [[DBG143]] +// DEBUG1-NEXT: store i32 [[TMP10]], i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG143]] +// DEBUG1-NEXT: [[TMP11:%.*]] = load %struct.S1*, %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG150]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq %struct.S1* [[ARRAYINIT_BEGIN8]], [[TMP11]], !dbg [[DBG150]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG150]] // DEBUG1: arraydestroy.body17: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[TMP11]], [[LPAD10]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG151]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG151]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG151]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], [[ARRAYINIT_BEGIN8]], !dbg [[DBG151]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG151]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[TMP11]], [[LPAD10]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG150]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG150]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG150]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], [[ARRAYINIT_BEGIN8]], !dbg [[DBG150]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG150]] // DEBUG1: arraydestroy.done21: -// DEBUG1-NEXT: br label [[EHCLEANUP]], !dbg [[DBG151]] +// DEBUG1-NEXT: br label [[EHCLEANUP]], !dbg [[DBG150]] // DEBUG1: ehcleanup: -// DEBUG1-NEXT: [[TMP12:%.*]] = load [3 x %struct.S1]*, [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG146]] -// DEBUG1-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], i64 0, i64 0, !dbg [[DBG146]] -// DEBUG1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[TMP12]], i64 0, i64 0, !dbg [[DBG146]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY22:%.*]] = icmp eq %struct.S1* [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]], !dbg [[DBG146]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY22]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY23:%.*]], !dbg [[DBG146]] +// DEBUG1-NEXT: [[TMP12:%.*]] = load [3 x %struct.S1]*, [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG145]] +// DEBUG1-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], i64 0, i64 0, !dbg [[DBG145]] +// DEBUG1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[TMP12]], i64 0, i64 0, !dbg [[DBG145]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY22:%.*]] = icmp eq %struct.S1* [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]], !dbg [[DBG145]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY22]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY23:%.*]], !dbg [[DBG145]] // DEBUG1: arraydestroy.body23: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST24:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT25:%.*]], [[ARRAYDESTROY_BODY23]] ], !dbg [[DBG146]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT25]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST24]], i64 -1, !dbg [[DBG146]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT25]]) #[[ATTR4]], !dbg [[DBG146]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE26:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT25]], [[PAD_ARRAYBEGIN]], !dbg [[DBG146]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE26]], label [[ARRAYDESTROY_DONE27]], label [[ARRAYDESTROY_BODY23]], !dbg [[DBG146]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST24:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT25:%.*]], [[ARRAYDESTROY_BODY23]] ], !dbg [[DBG145]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT25]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST24]], i64 -1, !dbg [[DBG145]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT25]]) #[[ATTR4]], !dbg [[DBG145]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE26:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT25]], [[PAD_ARRAYBEGIN]], !dbg [[DBG145]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE26]], label [[ARRAYDESTROY_DONE27]], label [[ARRAYDESTROY_BODY23]], !dbg [[DBG145]] // DEBUG1: arraydestroy.done27: -// DEBUG1-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG146]] +// DEBUG1-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG145]] // DEBUG1: eh.resume: -// DEBUG1-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG146]] -// DEBUG1-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG146]] -// DEBUG1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0, !dbg [[DBG146]] -// DEBUG1-NEXT: [[LPAD_VAL28:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG146]] -// DEBUG1-NEXT: resume { i8*, i32 } [[LPAD_VAL28]], !dbg [[DBG146]] +// DEBUG1-NEXT: [[EXN:%.*]] = load i8*, i8** [[EXN_SLOT]], align 8, !dbg [[DBG145]] +// DEBUG1-NEXT: [[SEL:%.*]] = load i32, i32* [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG145]] +// DEBUG1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0, !dbg [[DBG145]] +// DEBUG1-NEXT: [[LPAD_VAL28:%.*]] = insertvalue { i8*, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG145]] +// DEBUG1-NEXT: resume { i8*, i32 } [[LPAD_VAL28]], !dbg [[DBG145]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2 -// DEBUG1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG155:![0-9]+]] { +// DEBUG1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG154:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META156:![0-9]+]], metadata !DIExpression()), !dbg [[DBG157:![0-9]+]] -// DEBUG1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG157]] -// DEBUG1-NEXT: [[ARRAY_BEGIN:%.*]] = bitcast i8* [[TMP1]] to %struct.S1*, !dbg [[DBG157]] -// DEBUG1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAY_BEGIN]], i64 6, !dbg [[DBG157]] -// DEBUG1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG157]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META155:![0-9]+]], metadata !DIExpression()), !dbg [[DBG156:![0-9]+]] +// DEBUG1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG156]] +// DEBUG1-NEXT: [[ARRAY_BEGIN:%.*]] = bitcast i8* [[TMP1]] to %struct.S1*, !dbg [[DBG156]] +// DEBUG1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAY_BEGIN]], i64 6, !dbg [[DBG156]] +// DEBUG1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG156]] // DEBUG1: arraydestroy.body: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG157]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG157]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG157]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]], !dbg [[DBG157]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG157]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG156]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG156]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG156]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]], !dbg [[DBG156]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG156]] // DEBUG1: arraydestroy.done1: -// DEBUG1-NEXT: ret void, !dbg [[DBG158:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG157:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_..3 -// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG159:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG158:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]), !dbg [[DBG160:![0-9]+]] -// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB3]], i8* bitcast ([2 x [3 x %struct.S1]]* @arr_x to i8*), i8* (i8*)* @.__kmpc_global_ctor_..1, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..2), !dbg [[DBG160]] -// DEBUG1-NEXT: ret void, !dbg [[DBG160]] +// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]), !dbg [[DBG159:![0-9]+]] +// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB3]], i8* bitcast ([2 x [3 x %struct.S1]]* @arr_x to i8*), i8* (i8*)* @.__kmpc_global_ctor_..1, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..2), !dbg [[DBG159]] +// DEBUG1-NEXT: ret void, !dbg [[DBG159]] // // // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init -// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG161:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG160:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef @_ZL3gs1, i32 noundef 5), !dbg [[DBG164:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 5), !dbg [[DBG164:![0-9]+]] // DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S1*)* @_ZN2S1D1Ev to void (i8*)*), i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* @__dso_handle) #[[ATTR4]], !dbg [[DBG166:![0-9]+]] // DEBUG1-NEXT: ret void, !dbg [[DBG167:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// DEBUG1-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG168:![0-9]+]] { +// DEBUG1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG168:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6711,7 +6711,7 @@ int foobar() { // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// DEBUG1-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG176:![0-9]+]] { +// DEBUG1-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG176:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // DEBUG1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 @@ -6725,13 +6725,13 @@ int foobar() { // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init.4 // DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG183:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: call void @_ZN2S2C1Ei(%struct.S2* noundef @_ZL3gs2, i32 noundef 27), !dbg [[DBG184:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S2C1Ei(%struct.S2* nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 27), !dbg [[DBG184:![0-9]+]] // DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S2*)* @_ZN2S2D1Ev to void (i8*)*), i8* bitcast (%struct.S2* @_ZL3gs2 to i8*), i8* @__dso_handle) #[[ATTR4]], !dbg [[DBG186:![0-9]+]] // DEBUG1-NEXT: ret void, !dbg [[DBG187:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// DEBUG1-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG188:![0-9]+]] { +// DEBUG1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG188:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6741,23 +6741,23 @@ int foobar() { // DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META192:![0-9]+]], metadata !DIExpression()), !dbg [[DBG193:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 // DEBUG1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG194:![0-9]+]] -// DEBUG1-NEXT: call void @_ZN2S2C2Ei(%struct.S2* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG194]] +// DEBUG1-NEXT: call void @_ZN2S2C2Ei(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG194]] // DEBUG1-NEXT: ret void, !dbg [[DBG195:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// DEBUG1-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG196:![0-9]+]] { +// DEBUG1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG196:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // DEBUG1-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 // DEBUG1-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META197:![0-9]+]], metadata !DIExpression()), !dbg [[DBG198:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @_ZN2S2D2Ev(%struct.S2* noundef [[THIS1]]) #[[ATTR4]], !dbg [[DBG199:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S2D2Ev(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR4]], !dbg [[DBG199:![0-9]+]] // DEBUG1-NEXT: ret void, !dbg [[DBG200:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// DEBUG1-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG201:![0-9]+]] { +// DEBUG1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG201:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -6773,7 +6773,7 @@ int foobar() { // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// DEBUG1-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG209:![0-9]+]] { +// DEBUG1-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG209:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // DEBUG1-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 @@ -6794,28 +6794,28 @@ int foobar() { // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca %struct.S1*, align 8 // DEBUG1-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG217:![0-9]+]] // DEBUG1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG219:![0-9]+]] -// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 noundef 1) +// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 1) // DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG220:![0-9]+]] // DEBUG1: invoke.cont: // DEBUG1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG219]] -// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 noundef 2) +// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 2) // DEBUG1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG221:![0-9]+]] // DEBUG1: invoke.cont2: // DEBUG1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG219]] -// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 noundef 3) +// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 3) // DEBUG1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG222:![0-9]+]] // DEBUG1: invoke.cont3: // DEBUG1-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG217]] // DEBUG1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG223:![0-9]+]] -// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 noundef 4) +// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 4) // DEBUG1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG224:![0-9]+]] // DEBUG1: invoke.cont7: // DEBUG1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG223]] -// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 noundef 5) +// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 5) // DEBUG1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG225:![0-9]+]] // DEBUG1: invoke.cont8: // DEBUG1-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG223]] -// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 noundef 6) +// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 6) // DEBUG1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG226:![0-9]+]] // DEBUG1: invoke.cont9: // DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR4]], !dbg [[DBG227:![0-9]+]] @@ -6833,7 +6833,7 @@ int foobar() { // DEBUG1: arraydestroy.body: // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG219]] // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG219]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG219]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG219]] // DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG219]] // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG219]] // DEBUG1: arraydestroy.done4: @@ -6851,7 +6851,7 @@ int foobar() { // DEBUG1: arraydestroy.body11: // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi %struct.S1* [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG223]] // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG223]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]], !dbg [[DBG223]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]], !dbg [[DBG223]] // DEBUG1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), !dbg [[DBG223]] // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG223]] // DEBUG1: arraydestroy.done15: @@ -6864,7 +6864,7 @@ int foobar() { // DEBUG1: arraydestroy.body17: // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG217]] // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG217]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG217]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG217]] // DEBUG1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG217]] // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG217]] // DEBUG1: arraydestroy.done21: @@ -6878,7 +6878,7 @@ int foobar() { // // // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// DEBUG1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG229:![0-9]+]] { +// DEBUG1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG229:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -6887,7 +6887,7 @@ int foobar() { // DEBUG1: arraydestroy.body: // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG233]] // DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG233]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG233]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG233]] // DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), !dbg [[DBG233]] // DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG233]] // DEBUG1: arraydestroy.done1: @@ -6918,7 +6918,7 @@ int foobar() { // DEBUG1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to %struct.S1*, !dbg [[DBG238]] // DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP5]], i32 0, i32 0, !dbg [[DBG239:![0-9]+]] // DEBUG1-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG239]] -// DEBUG1-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef @_ZZ4mainE2sm, i32 noundef [[TMP6]]) +// DEBUG1-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 [[TMP6]]) // DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG240:![0-9]+]] // DEBUG1: invoke.cont: // DEBUG1-NEXT: [[TMP7:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.Smain*)* @_ZZ4mainEN5SmainD1Ev to void (i8*)*), i8* bitcast (%struct.Smain* @_ZZ4mainE2sm to i8*), i8* @__dso_handle) #[[ATTR4]], !dbg [[DBG236]] @@ -7004,7 +7004,7 @@ int foobar() { // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..6 -// DEBUG1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG268:![0-9]+]] { +// DEBUG1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG268:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB5:[0-9]+]]) @@ -7016,13 +7016,13 @@ int foobar() { // DEBUG1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to %struct.S1*, !dbg [[DBG272]] // DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP5]], i32 0, i32 0, !dbg [[DBG273:![0-9]+]] // DEBUG1-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG273]] -// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef [[TMP3]], i32 noundef [[TMP6]]), !dbg [[DBG274:![0-9]+]] +// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[TMP3]], i32 [[TMP6]]), !dbg [[DBG274:![0-9]+]] // DEBUG1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG271]] // DEBUG1-NEXT: ret i8* [[TMP7]], !dbg [[DBG271]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// DEBUG1-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG275:![0-9]+]] { +// DEBUG1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG275:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7032,35 +7032,35 @@ int foobar() { // DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META279:![0-9]+]], metadata !DIExpression()), !dbg [[DBG280:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 // DEBUG1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG281:![0-9]+]] -// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG281]] +// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG281]] // DEBUG1-NEXT: ret void, !dbg [[DBG282:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..7 -// DEBUG1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG283:![0-9]+]] { +// DEBUG1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG283:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META284:![0-9]+]], metadata !DIExpression()), !dbg [[DBG285:![0-9]+]] // DEBUG1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG285]] // DEBUG1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.Smain*, !dbg [[DBG285]] -// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainD1Ev(%struct.Smain* noundef [[TMP2]]) #[[ATTR4]], !dbg [[DBG285]] +// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainD1Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[TMP2]]) #[[ATTR4]], !dbg [[DBG285]] // DEBUG1-NEXT: ret void, !dbg [[DBG286:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// DEBUG1-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG287:![0-9]+]] { +// DEBUG1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG287:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // DEBUG1-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 // DEBUG1-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META288:![0-9]+]], metadata !DIExpression()), !dbg [[DBG289:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* noundef [[THIS1]]) #[[ATTR4]], !dbg [[DBG290:![0-9]+]] +// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]], !dbg [[DBG290:![0-9]+]] // DEBUG1-NEXT: ret void, !dbg [[DBG291:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// DEBUG1-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG292:![0-9]+]] { +// DEBUG1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG292:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7076,7 +7076,7 @@ int foobar() { // // // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// DEBUG1-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG300:![0-9]+]] { +// DEBUG1-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG300:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // DEBUG1-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 @@ -7158,7 +7158,7 @@ int foobar() { // DEBUG1: init.check: // DEBUG1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB41:[0-9]+]]), !dbg [[DBG334]] // DEBUG1-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB41]], i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* (i8*)* @.__kmpc_global_ctor_..9, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..10), !dbg [[DBG334]] -// DEBUG1-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG335:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 23), !dbg [[DBG335:![0-9]+]] // DEBUG1-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S4*)* @_ZN2S4D1Ev to void (i8*)*), i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* @__dso_handle) #[[ATTR4]], !dbg [[DBG334]] // DEBUG1-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8, !dbg [[DBG334]] // DEBUG1-NEXT: br label [[INIT_END]], !dbg [[DBG334]] @@ -7167,20 +7167,20 @@ int foobar() { // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..9 -// DEBUG1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG338:![0-9]+]] { +// DEBUG1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG338:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META339:![0-9]+]], metadata !DIExpression()), !dbg [[DBG340:![0-9]+]] // DEBUG1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG341:![0-9]+]] // DEBUG1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S4*, !dbg [[DBG341]] -// DEBUG1-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef [[TMP2]], i32 noundef 23), !dbg [[DBG342:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[TMP2]], i32 23), !dbg [[DBG342:![0-9]+]] // DEBUG1-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG341]] // DEBUG1-NEXT: ret i8* [[TMP3]], !dbg [[DBG341]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// DEBUG1-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG343:![0-9]+]] { +// DEBUG1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG343:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7190,35 +7190,35 @@ int foobar() { // DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META347:![0-9]+]], metadata !DIExpression()), !dbg [[DBG348:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 // DEBUG1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG349:![0-9]+]] -// DEBUG1-NEXT: call void @_ZN2S4C2Ei(%struct.S4* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG349]] +// DEBUG1-NEXT: call void @_ZN2S4C2Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG349]] // DEBUG1-NEXT: ret void, !dbg [[DBG350:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..10 -// DEBUG1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG351:![0-9]+]] { +// DEBUG1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG351:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // DEBUG1-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META352:![0-9]+]], metadata !DIExpression()), !dbg [[DBG353:![0-9]+]] // DEBUG1-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG353]] // DEBUG1-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S4*, !dbg [[DBG353]] -// DEBUG1-NEXT: call void @_ZN2S4D1Ev(%struct.S4* noundef [[TMP2]]) #[[ATTR4]], !dbg [[DBG353]] +// DEBUG1-NEXT: call void @_ZN2S4D1Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR4]], !dbg [[DBG353]] // DEBUG1-NEXT: ret void, !dbg [[DBG354:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// DEBUG1-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG355:![0-9]+]] { +// DEBUG1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG355:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // DEBUG1-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 // DEBUG1-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META356:![0-9]+]], metadata !DIExpression()), !dbg [[DBG357:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @_ZN2S4D2Ev(%struct.S4* noundef [[THIS1]]) #[[ATTR4]], !dbg [[DBG358:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S4D2Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]], !dbg [[DBG358:![0-9]+]] // DEBUG1-NEXT: ret void, !dbg [[DBG359:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// DEBUG1-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG360:![0-9]+]] { +// DEBUG1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG360:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7234,7 +7234,7 @@ int foobar() { // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// DEBUG1-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG368:![0-9]+]] { +// DEBUG1-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG368:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // DEBUG1-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 @@ -7257,30 +7257,30 @@ int foobar() { // // // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init -// DEBUG2-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG116:![0-9]+]] { +// DEBUG2-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG115:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]), !dbg [[DBG119:![0-9]+]] // DEBUG2-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* (i8*)* @.__kmpc_global_ctor_., i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_.), !dbg [[DBG119]] -// DEBUG2-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef @_ZL3gs1, i32 noundef 5), !dbg [[DBG120:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 5), !dbg [[DBG120:![0-9]+]] // DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S1*)* @_ZN2S1D1Ev to void (i8*)*), i8* bitcast (%struct.S1* @_ZL3gs1 to i8*), i8* @__dso_handle) #[[ATTR4:[0-9]+]], !dbg [[DBG119]] // DEBUG2-NEXT: ret void, !dbg [[DBG122:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. -// DEBUG2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG123:![0-9]+]] { +// DEBUG2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG123:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // DEBUG2-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META125:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127:![0-9]+]] // DEBUG2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG128:![0-9]+]] // DEBUG2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S1*, !dbg [[DBG128]] -// DEBUG2-NEXT: call void @_ZN2S1C1Ei(%struct.S1* noundef [[TMP2]], i32 noundef 5), !dbg [[DBG129:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[TMP2]], i32 5), !dbg [[DBG129:![0-9]+]] // DEBUG2-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG128]] // DEBUG2-NEXT: ret i8* [[TMP3]], !dbg [[DBG128]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// DEBUG2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG130:![0-9]+]] { +// DEBUG2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG130:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7290,43 +7290,43 @@ int foobar() { // DEBUG2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META134:![0-9]+]], metadata !DIExpression()), !dbg [[DBG135:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 // DEBUG2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG136:![0-9]+]] -// DEBUG2-NEXT: call void @_ZN2S1C2Ei(%struct.S1* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG136]] +// DEBUG2-NEXT: call void @_ZN2S1C2Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG136]] // DEBUG2-NEXT: ret void, !dbg [[DBG137:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. -// DEBUG2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG138:![0-9]+]] { +// DEBUG2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG138:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // DEBUG2-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META139:![0-9]+]], metadata !DIExpression()), !dbg [[DBG140:![0-9]+]] // DEBUG2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG140]] // DEBUG2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S1*, !dbg [[DBG140]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[TMP2]]) #[[ATTR4]], !dbg [[DBG140]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR4]], !dbg [[DBG140]] // DEBUG2-NEXT: ret void, !dbg [[DBG141:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// DEBUG2-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] comdat align 2 !dbg [[DBG142:![0-9]+]] { +// DEBUG2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] comdat align 2 !dbg [[DBG142:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // DEBUG2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 // DEBUG2-NEXT: call void @llvm.dbg.declare(metadata %struct.S1** [[THIS_ADDR]], metadata [[META143:![0-9]+]], metadata !DIExpression()), !dbg [[DBG144:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @_ZN2S1D2Ev(%struct.S1* noundef [[THIS1]]) #[[ATTR4]], !dbg [[DBG145:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S1D2Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]], !dbg [[DBG145:![0-9]+]] // DEBUG2-NEXT: ret void, !dbg [[DBG146:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // DEBUG2-SAME: () #[[ATTR0]] !dbg [[DBG147:![0-9]+]] { // DEBUG2-NEXT: entry: -// DEBUG2-NEXT: call void @_ZN2S2C1Ei(%struct.S2* noundef @_ZL3gs2, i32 noundef 27), !dbg [[DBG148:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S2C1Ei(%struct.S2* nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 27), !dbg [[DBG148:![0-9]+]] // DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S2*)* @_ZN2S2D1Ev to void (i8*)*), i8* bitcast (%struct.S2* @_ZL3gs2 to i8*), i8* @__dso_handle) #[[ATTR4]], !dbg [[DBG150:![0-9]+]] // DEBUG2-NEXT: ret void, !dbg [[DBG151:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// DEBUG2-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG152:![0-9]+]] { +// DEBUG2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG152:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7336,18 +7336,18 @@ int foobar() { // DEBUG2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META156:![0-9]+]], metadata !DIExpression()), !dbg [[DBG157:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 // DEBUG2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG158:![0-9]+]] -// DEBUG2-NEXT: call void @_ZN2S2C2Ei(%struct.S2* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG158]] +// DEBUG2-NEXT: call void @_ZN2S2C2Ei(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG158]] // DEBUG2-NEXT: ret void, !dbg [[DBG159:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// DEBUG2-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG160:![0-9]+]] { +// DEBUG2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG160:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // DEBUG2-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 // DEBUG2-NEXT: call void @llvm.dbg.declare(metadata %struct.S2** [[THIS_ADDR]], metadata [[META161:![0-9]+]], metadata !DIExpression()), !dbg [[DBG162:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load %struct.S2*, %struct.S2** [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @_ZN2S2D2Ev(%struct.S2* noundef [[THIS1]]) #[[ATTR4]], !dbg [[DBG163:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S2D2Ev(%struct.S2* nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR4]], !dbg [[DBG163:![0-9]+]] // DEBUG2-NEXT: ret void, !dbg [[DBG164:![0-9]+]] // // @@ -7363,28 +7363,28 @@ int foobar() { // DEBUG2-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB3]], i8* bitcast ([2 x [3 x %struct.S1]]* @arr_x to i8*), i8* (i8*)* @.__kmpc_global_ctor_..3, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..4), !dbg [[DBG166]] // DEBUG2-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG167:![0-9]+]] // DEBUG2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG169:![0-9]+]] -// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 noundef 1) +// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), i32 1) // DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG170:![0-9]+]] // DEBUG2: invoke.cont: // DEBUG2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG169]] -// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 noundef 2) +// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 1), i32 2) // DEBUG2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG171:![0-9]+]] // DEBUG2: invoke.cont2: // DEBUG2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG169]] -// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 noundef 3) +// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 2), i32 3) // DEBUG2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG172:![0-9]+]] // DEBUG2: invoke.cont3: // DEBUG2-NEXT: store [3 x %struct.S1]* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1), [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG167]] // DEBUG2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG173:![0-9]+]] -// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 noundef 4) +// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), i32 4) // DEBUG2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG174:![0-9]+]] // DEBUG2: invoke.cont7: // DEBUG2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG173]] -// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 noundef 5) +// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 1), i32 5) // DEBUG2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG175:![0-9]+]] // DEBUG2: invoke.cont8: // DEBUG2-NEXT: store %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), %struct.S1** [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG173]] -// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 noundef 6) +// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 2), i32 6) // DEBUG2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG176:![0-9]+]] // DEBUG2: invoke.cont9: // DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR4]], !dbg [[DBG166]] @@ -7402,7 +7402,7 @@ int foobar() { // DEBUG2: arraydestroy.body: // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP5]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG169]] // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG169]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG169]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG169]] // DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG169]] // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG169]] // DEBUG2: arraydestroy.done4: @@ -7420,7 +7420,7 @@ int foobar() { // DEBUG2: arraydestroy.body11: // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi %struct.S1* [ [[TMP9]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG173]] // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG173]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]], !dbg [[DBG173]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]], !dbg [[DBG173]] // DEBUG2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 1, i64 0), !dbg [[DBG173]] // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG173]] // DEBUG2: arraydestroy.done15: @@ -7433,7 +7433,7 @@ int foobar() { // DEBUG2: arraydestroy.body17: // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG167]] // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG167]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG167]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG167]] // DEBUG2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i64 0, i64 0, i64 0), !dbg [[DBG167]] // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG167]] // DEBUG2: arraydestroy.done21: @@ -7447,7 +7447,7 @@ int foobar() { // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..3 -// DEBUG2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG178:![0-9]+]] { +// DEBUG2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG178:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca [3 x %struct.S1]*, align 8 @@ -7463,34 +7463,34 @@ int foobar() { // DEBUG2-NEXT: store [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG182]] // DEBUG2-NEXT: [[ARRAYINIT_BEGIN1:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], i64 0, i64 0, !dbg [[DBG183:![0-9]+]] // DEBUG2-NEXT: store %struct.S1* [[ARRAYINIT_BEGIN1]], %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG183]] -// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_BEGIN1]], i32 noundef 1) +// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN1]], i32 1) // DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG184:![0-9]+]] // DEBUG2: invoke.cont: // DEBUG2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[ARRAYINIT_BEGIN1]], i64 1, !dbg [[DBG183]] // DEBUG2-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT]], %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG183]] -// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) // DEBUG2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG185:![0-9]+]] // DEBUG2: invoke.cont3: // DEBUG2-NEXT: [[ARRAYINIT_ELEMENT4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYINIT_ELEMENT]], i64 1, !dbg [[DBG183]] // DEBUG2-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT4]], %struct.S1** [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG183]] -// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT4]], i32 noundef 3) +// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT4]], i32 3) // DEBUG2-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]], !dbg [[DBG186:![0-9]+]] // DEBUG2: invoke.cont5: // DEBUG2-NEXT: [[ARRAYINIT_ELEMENT7:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_BEGIN]], i64 1, !dbg [[DBG182]] // DEBUG2-NEXT: store [3 x %struct.S1]* [[ARRAYINIT_ELEMENT7]], [3 x %struct.S1]** [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG182]] // DEBUG2-NEXT: [[ARRAYINIT_BEGIN8:%.*]] = getelementptr inbounds [3 x %struct.S1], [3 x %struct.S1]* [[ARRAYINIT_ELEMENT7]], i64 0, i64 0, !dbg [[DBG187:![0-9]+]] // DEBUG2-NEXT: store %struct.S1* [[ARRAYINIT_BEGIN8]], %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG187]] -// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_BEGIN8]], i32 noundef 4) +// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN8]], i32 4) // DEBUG2-NEXT: to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD10:%.*]], !dbg [[DBG188:![0-9]+]] // DEBUG2: invoke.cont11: // DEBUG2-NEXT: [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYINIT_BEGIN8]], i64 1, !dbg [[DBG187]] // DEBUG2-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT12]], %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG187]] -// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT12]], i32 noundef 5) +// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT12]], i32 5) // DEBUG2-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD10]], !dbg [[DBG189:![0-9]+]] // DEBUG2: invoke.cont13: // DEBUG2-NEXT: [[ARRAYINIT_ELEMENT14:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYINIT_ELEMENT12]], i64 1, !dbg [[DBG187]] // DEBUG2-NEXT: store %struct.S1* [[ARRAYINIT_ELEMENT14]], %struct.S1** [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG187]] -// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* noundef [[ARRAYINIT_ELEMENT14]], i32 noundef 6) +// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT14]], i32 6) // DEBUG2-NEXT: to label [[INVOKE_CONT15:%.*]] unwind label [[LPAD10]], !dbg [[DBG190:![0-9]+]] // DEBUG2: invoke.cont15: // DEBUG2-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG181]] @@ -7508,7 +7508,7 @@ int foobar() { // DEBUG2: arraydestroy.body: // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP7]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG183]] // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG183]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG183]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG183]] // DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], [[ARRAYINIT_BEGIN1]], !dbg [[DBG183]] // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG183]] // DEBUG2: arraydestroy.done6: @@ -7526,7 +7526,7 @@ int foobar() { // DEBUG2: arraydestroy.body17: // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi %struct.S1* [ [[TMP11]], [[LPAD10]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG187]] // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG187]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG187]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG187]] // DEBUG2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT19]], [[ARRAYINIT_BEGIN8]], !dbg [[DBG187]] // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG187]] // DEBUG2: arraydestroy.done21: @@ -7540,7 +7540,7 @@ int foobar() { // DEBUG2: arraydestroy.body23: // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST24:%.*]] = phi %struct.S1* [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT25:%.*]], [[ARRAYDESTROY_BODY23]] ], !dbg [[DBG182]] // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT25]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST24]], i64 -1, !dbg [[DBG182]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT25]]) #[[ATTR4]], !dbg [[DBG182]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT25]]) #[[ATTR4]], !dbg [[DBG182]] // DEBUG2-NEXT: [[ARRAYDESTROY_DONE26:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT25]], [[PAD_ARRAYBEGIN]], !dbg [[DBG182]] // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE26]], label [[ARRAYDESTROY_DONE27]], label [[ARRAYDESTROY_BODY23]], !dbg [[DBG182]] // DEBUG2: arraydestroy.done27: @@ -7554,7 +7554,7 @@ int foobar() { // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..4 -// DEBUG2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG191:![0-9]+]] { +// DEBUG2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG191:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -7566,7 +7566,7 @@ int foobar() { // DEBUG2: arraydestroy.body: // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG193]] // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG193]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG193]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG193]] // DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]], !dbg [[DBG193]] // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG193]] // DEBUG2: arraydestroy.done1: @@ -7574,7 +7574,7 @@ int foobar() { // // // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// DEBUG2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG195:![0-9]+]] { +// DEBUG2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG195:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 @@ -7583,7 +7583,7 @@ int foobar() { // DEBUG2: arraydestroy.body: // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S1* [ getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG199]] // DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG199]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG199]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(%struct.S1* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG199]] // DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S1* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x [3 x %struct.S1]], [2 x [3 x %struct.S1]]* @arr_x, i32 0, i32 0, i32 0), !dbg [[DBG199]] // DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG199]] // DEBUG2: arraydestroy.done1: @@ -7614,7 +7614,7 @@ int foobar() { // DEBUG2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to %struct.S1*, !dbg [[DBG204]] // DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP5]], i32 0, i32 0, !dbg [[DBG205:![0-9]+]] // DEBUG2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG205]] -// DEBUG2-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef @_ZZ4mainE2sm, i32 noundef [[TMP6]]) +// DEBUG2-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 [[TMP6]]) // DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG206:![0-9]+]] // DEBUG2: invoke.cont: // DEBUG2-NEXT: [[TMP7:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.Smain*)* @_ZZ4mainEN5SmainD1Ev to void (i8*)*), i8* bitcast (%struct.Smain* @_ZZ4mainE2sm to i8*), i8* @__dso_handle) #[[ATTR4]], !dbg [[DBG202]] @@ -7700,7 +7700,7 @@ int foobar() { // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..5 -// DEBUG2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG234:![0-9]+]] { +// DEBUG2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG234:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB5:[0-9]+]]) @@ -7712,13 +7712,13 @@ int foobar() { // DEBUG2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to %struct.S1*, !dbg [[DBG238]] // DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP5]], i32 0, i32 0, !dbg [[DBG239:![0-9]+]] // DEBUG2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG239]] -// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* noundef [[TMP3]], i32 noundef [[TMP6]]), !dbg [[DBG240:![0-9]+]] +// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainC1Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[TMP3]], i32 [[TMP6]]), !dbg [[DBG240:![0-9]+]] // DEBUG2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG237]] // DEBUG2-NEXT: ret i8* [[TMP7]], !dbg [[DBG237]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// DEBUG2-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG241:![0-9]+]] { +// DEBUG2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG241:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7728,30 +7728,30 @@ int foobar() { // DEBUG2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META245:![0-9]+]], metadata !DIExpression()), !dbg [[DBG246:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 // DEBUG2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG247:![0-9]+]] -// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG247]] +// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG247]] // DEBUG2-NEXT: ret void, !dbg [[DBG248:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..6 -// DEBUG2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG249:![0-9]+]] { +// DEBUG2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG249:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // DEBUG2-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META250:![0-9]+]], metadata !DIExpression()), !dbg [[DBG251:![0-9]+]] // DEBUG2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG251]] // DEBUG2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.Smain*, !dbg [[DBG251]] -// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainD1Ev(%struct.Smain* noundef [[TMP2]]) #[[ATTR4]], !dbg [[DBG251]] +// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainD1Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[TMP2]]) #[[ATTR4]], !dbg [[DBG251]] // DEBUG2-NEXT: ret void, !dbg [[DBG252:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// DEBUG2-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG253:![0-9]+]] { +// DEBUG2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG253:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // DEBUG2-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 // DEBUG2-NEXT: call void @llvm.dbg.declare(metadata %struct.Smain** [[THIS_ADDR]], metadata [[META254:![0-9]+]], metadata !DIExpression()), !dbg [[DBG255:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load %struct.Smain*, %struct.Smain** [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* noundef [[THIS1]]) #[[ATTR4]], !dbg [[DBG256:![0-9]+]] +// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]], !dbg [[DBG256:![0-9]+]] // DEBUG2-NEXT: ret void, !dbg [[DBG257:![0-9]+]] // // @@ -7826,7 +7826,7 @@ int foobar() { // DEBUG2: init.check: // DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB41:[0-9]+]]), !dbg [[DBG285]] // DEBUG2-NEXT: call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB41]], i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* (i8*)* @.__kmpc_global_ctor_..8, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..9), !dbg [[DBG285]] -// DEBUG2-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG286:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 23), !dbg [[DBG286:![0-9]+]] // DEBUG2-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S4*)* @_ZN2S4D1Ev to void (i8*)*), i8* bitcast (%struct.S4* @_ZN2STI2S4E2stE to i8*), i8* @__dso_handle) #[[ATTR4]], !dbg [[DBG285]] // DEBUG2-NEXT: store i8 1, i8* bitcast (i64* @_ZGVN2STI2S4E2stE to i8*), align 8, !dbg [[DBG285]] // DEBUG2-NEXT: br label [[INIT_END]], !dbg [[DBG285]] @@ -7835,20 +7835,20 @@ int foobar() { // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..8 -// DEBUG2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG289:![0-9]+]] { +// DEBUG2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG289:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // DEBUG2-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META290:![0-9]+]], metadata !DIExpression()), !dbg [[DBG291:![0-9]+]] // DEBUG2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG292:![0-9]+]] // DEBUG2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S4*, !dbg [[DBG292]] -// DEBUG2-NEXT: call void @_ZN2S4C1Ei(%struct.S4* noundef [[TMP2]], i32 noundef 23), !dbg [[DBG293:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S4C1Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[TMP2]], i32 23), !dbg [[DBG293:![0-9]+]] // DEBUG2-NEXT: [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG292]] // DEBUG2-NEXT: ret i8* [[TMP3]], !dbg [[DBG292]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// DEBUG2-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG294:![0-9]+]] { +// DEBUG2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG294:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7858,35 +7858,35 @@ int foobar() { // DEBUG2-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META298:![0-9]+]], metadata !DIExpression()), !dbg [[DBG299:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 // DEBUG2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG300:![0-9]+]] -// DEBUG2-NEXT: call void @_ZN2S4C2Ei(%struct.S4* noundef [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG300]] +// DEBUG2-NEXT: call void @_ZN2S4C2Ei(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]], i32 [[TMP0]]), !dbg [[DBG300]] // DEBUG2-NEXT: ret void, !dbg [[DBG301:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..9 -// DEBUG2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG302:![0-9]+]] { +// DEBUG2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG302:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 // DEBUG2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 // DEBUG2-NEXT: call void @llvm.dbg.declare(metadata i8** [[DOTADDR]], metadata [[META303:![0-9]+]], metadata !DIExpression()), !dbg [[DBG304:![0-9]+]] // DEBUG2-NEXT: [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8, !dbg [[DBG304]] // DEBUG2-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S4*, !dbg [[DBG304]] -// DEBUG2-NEXT: call void @_ZN2S4D1Ev(%struct.S4* noundef [[TMP2]]) #[[ATTR4]], !dbg [[DBG304]] +// DEBUG2-NEXT: call void @_ZN2S4D1Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR4]], !dbg [[DBG304]] // DEBUG2-NEXT: ret void, !dbg [[DBG305:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// DEBUG2-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG306:![0-9]+]] { +// DEBUG2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG306:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // DEBUG2-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 // DEBUG2-NEXT: call void @llvm.dbg.declare(metadata %struct.S4** [[THIS_ADDR]], metadata [[META307:![0-9]+]], metadata !DIExpression()), !dbg [[DBG308:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load %struct.S4*, %struct.S4** [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @_ZN2S4D2Ev(%struct.S4* noundef [[THIS1]]) #[[ATTR4]], !dbg [[DBG309:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S4D2Ev(%struct.S4* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]], !dbg [[DBG309:![0-9]+]] // DEBUG2-NEXT: ret void, !dbg [[DBG310:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// DEBUG2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG311:![0-9]+]] { +// DEBUG2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG311:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7902,7 +7902,7 @@ int foobar() { // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// DEBUG2-SAME: (%struct.S1* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG319:![0-9]+]] { +// DEBUG2-SAME: (%struct.S1* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG319:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 // DEBUG2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 @@ -7914,7 +7914,7 @@ int foobar() { // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// DEBUG2-SAME: (%struct.S2* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG326:![0-9]+]] { +// DEBUG2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG326:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7930,7 +7930,7 @@ int foobar() { // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// DEBUG2-SAME: (%struct.S2* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG334:![0-9]+]] { +// DEBUG2-SAME: (%struct.S2* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG334:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S2*, align 8 // DEBUG2-NEXT: store %struct.S2* [[THIS]], %struct.S2** [[THIS_ADDR]], align 8 @@ -7942,7 +7942,7 @@ int foobar() { // // // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// DEBUG2-SAME: (%struct.Smain* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG341:![0-9]+]] { +// DEBUG2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG341:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7958,7 +7958,7 @@ int foobar() { // // // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// DEBUG2-SAME: (%struct.Smain* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG349:![0-9]+]] { +// DEBUG2-SAME: (%struct.Smain* nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG349:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Smain*, align 8 // DEBUG2-NEXT: store %struct.Smain* [[THIS]], %struct.Smain** [[THIS_ADDR]], align 8 @@ -7970,7 +7970,7 @@ int foobar() { // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// DEBUG2-SAME: (%struct.S4* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG356:![0-9]+]] { +// DEBUG2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG356:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -7986,7 +7986,7 @@ int foobar() { // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// DEBUG2-SAME: (%struct.S4* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG364:![0-9]+]] { +// DEBUG2-SAME: (%struct.S4* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG364:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S4*, align 8 // DEBUG2-NEXT: store %struct.S4* [[THIS]], %struct.S4** [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/tile_codegen.cpp b/clang/test/OpenMP/tile_codegen.cpp index d3cc5783659b34da87ca1bedb4e13ab3972fbf13..e6d956b6579d40e2fdfc18ee8dc5de2fb51b9dbb 100644 --- a/clang/test/OpenMP/tile_codegen.cpp +++ b/clang/test/OpenMP/tile_codegen.cpp @@ -93,22 +93,22 @@ extern "C" void tfoo7() { // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK1-SAME: () #[[ATTR1:[0-9]+]] section ".text.startup" { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef @s) +// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @s) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK1-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32*, align 8 @@ -152,26 +152,26 @@ extern "C" void tfoo7() { // CHECK1-NEXT: store i32 [[ADD8]], i32* [[TMP6]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[I]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP8]]) +// CHECK1-NEXT: call void (...) @body(i32 [[TMP8]]) // CHECK1-NEXT: br label [[FOR_INC:%.*]] // CHECK1: for.inc: // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP2:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC9:%.*]] // CHECK1: for.inc9: // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP10]], 5 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: for.end11: // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@foo1 -// CHECK1-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 [[START:%.*]], i32 [[END:%.*]], i32 [[STEP:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4 @@ -242,26 +242,26 @@ extern "C" void tfoo7() { // CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], [[MUL]] // CHECK1-NEXT: store i32 [[ADD15]], i32* [[I]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP18]]) +// CHECK1-NEXT: call void (...) @body(i32 [[TMP18]]) // CHECK1-NEXT: br label [[FOR_INC:%.*]] // CHECK1: for.inc: // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC16:%.*]] // CHECK1: for.inc16: // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4 // CHECK1-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 5 // CHECK1-NEXT: store i32 [[ADD17]], i32* [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK1: for.end18: // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@foo2 -// CHECK1-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 [[START:%.*]], i32 [[END:%.*]], i32 [[STEP:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4 @@ -341,34 +341,34 @@ extern "C" void tfoo7() { // CHECK1-NEXT: store i32 [[ADD21]], i32* [[J]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP12]], i32 noundef [[TMP13]]) +// CHECK1-NEXT: call void (...) @body(i32 [[TMP12]], i32 [[TMP13]]) // CHECK1-NEXT: br label [[FOR_INC:%.*]] // CHECK1: for.inc: // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC22:%.*]] // CHECK1: for.inc22: // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4 // CHECK1-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK1-NEXT: store i32 [[INC23]], i32* [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK1: for.end24: // CHECK1-NEXT: br label [[FOR_INC25:%.*]] // CHECK1: for.inc25: // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP16]], 5 // CHECK1-NEXT: store i32 [[ADD26]], i32* [[DOTFLOOR_1_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK1: for.end27: // CHECK1-NEXT: br label [[FOR_INC28:%.*]] // CHECK1: for.inc28: // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4 // CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP17]], 5 // CHECK1-NEXT: store i32 [[ADD29]], i32* [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: for.end30: // CHECK1-NEXT: ret void // @@ -477,27 +477,27 @@ extern "C" void tfoo7() { // CHECK1-NEXT: store i32 [[ADD26]], i32* [[J]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[J]], align 4 -// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP18]], i32 noundef [[TMP19]]) +// CHECK1-NEXT: call void (...) @body(i32 [[TMP18]], i32 [[TMP19]]) // CHECK1-NEXT: br label [[FOR_INC:%.*]] // CHECK1: for.inc: // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC27:%.*]] // CHECK1: for.inc27: // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4 // CHECK1-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP21]], 1 // CHECK1-NEXT: store i32 [[INC28]], i32* [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK1: for.end29: // CHECK1-NEXT: br label [[FOR_INC30:%.*]] // CHECK1: for.inc30: // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4 // CHECK1-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP22]], 5 // CHECK1-NEXT: store i32 [[ADD31]], i32* [[DOTFLOOR_1_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK1: for.end32: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -630,27 +630,27 @@ extern "C" void tfoo7() { // CHECK1-NEXT: store i32 [[ADD31]], i32* [[J]], align 4 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[J]], align 4 -// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP20]], i32 noundef [[TMP21]]) +// CHECK1-NEXT: call void (...) @body(i32 [[TMP20]], i32 [[TMP21]]) // CHECK1-NEXT: br label [[FOR_INC:%.*]] // CHECK1: for.inc: // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC32:%.*]] // CHECK1: for.inc32: // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4 // CHECK1-NEXT: [[INC33:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK1-NEXT: store i32 [[INC33]], i32* [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK1: for.end34: // CHECK1-NEXT: br label [[FOR_INC35:%.*]] // CHECK1: for.inc35: // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4 // CHECK1-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP24]], 5 // CHECK1-NEXT: store i32 [[ADD36]], i32* [[DOTFLOOR_1_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK1: for.end37: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -858,7 +858,7 @@ extern "C" void tfoo7() { // CHECK1-NEXT: store i32 [[ADD94]], i32* [[I]], align 4 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[I]], align 4 // CHECK1-NEXT: [[TMP41:%.*]] = load i32, i32* [[J13]], align 4 -// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP40]], i32 noundef [[TMP41]]) +// CHECK1-NEXT: call void (...) @body(i32 [[TMP40]], i32 [[TMP41]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -885,7 +885,7 @@ extern "C" void tfoo7() { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -957,13 +957,13 @@ extern "C" void tfoo7() { // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 7, [[MUL10]] // CHECK1-NEXT: store i32 [[ADD11]], i32* [[I]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP13]]) +// CHECK1-NEXT: call void (...) @body(i32 [[TMP13]]) // CHECK1-NEXT: br label [[FOR_INC:%.*]] // CHECK1: for.inc: // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -983,12 +983,12 @@ extern "C" void tfoo7() { // CHECK1-LABEL: define {{[^@]+}}@tfoo7 // CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void @_Z4foo7IiLi3ELi5EEvT_S0_(i32 noundef 0, i32 noundef 42) +// CHECK1-NEXT: call void @_Z4foo7IiLi3ELi5EEvT_S0_(i32 0, i32 42) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_Z4foo7IiLi3ELi5EEvT_S0_ -// CHECK1-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]]) #[[ATTR0]] comdat { +// CHECK1-SAME: (i32 [[START:%.*]], i32 [[END:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4 @@ -1053,20 +1053,20 @@ extern "C" void tfoo7() { // CHECK1-NEXT: [[ADD14:%.*]] = add i32 [[TMP13]], [[MUL]] // CHECK1-NEXT: store i32 [[ADD14]], i32* [[I]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP15]]) +// CHECK1-NEXT: call void (...) @body(i32 [[TMP15]]) // CHECK1-NEXT: br label [[FOR_INC:%.*]] // CHECK1: for.inc: // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC15:%.*]] // CHECK1: for.inc15: // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4 // CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP17]], 5 // CHECK1-NEXT: store i32 [[ADD16]], i32* [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK1: for.end17: // CHECK1-NEXT: ret void // @@ -1081,22 +1081,22 @@ extern "C" void tfoo7() { // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK2-SAME: () #[[ATTR0:[0-9]+]] section ".text.startup" { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* noundef @s) +// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @s) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC1Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SC2Ev(%struct.S* noundef [[THIS1]]) +// CHECK2-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ev -// CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 // CHECK2-NEXT: [[I:%.*]] = alloca i32*, align 8 @@ -1140,20 +1140,20 @@ extern "C" void tfoo7() { // CHECK2-NEXT: store i32 [[ADD8]], i32* [[TMP6]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[I]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 -// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP8]]) +// CHECK2-NEXT: call void (...) @body(i32 [[TMP8]]) // CHECK2-NEXT: br label [[FOR_INC:%.*]] // CHECK2: for.inc: // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP2:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC9:%.*]] // CHECK2: for.inc9: // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP10]], 5 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK2: for.end11: // CHECK2-NEXT: ret void // @@ -1165,7 +1165,7 @@ extern "C" void tfoo7() { // // // CHECK2-LABEL: define {{[^@]+}}@foo1 -// CHECK2-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32 [[START:%.*]], i32 [[END:%.*]], i32 [[STEP:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4 @@ -1236,26 +1236,26 @@ extern "C" void tfoo7() { // CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], [[MUL]] // CHECK2-NEXT: store i32 [[ADD15]], i32* [[I]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 -// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP18]]) +// CHECK2-NEXT: call void (...) @body(i32 [[TMP18]]) // CHECK2-NEXT: br label [[FOR_INC:%.*]] // CHECK2: for.inc: // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC16:%.*]] // CHECK2: for.inc16: // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4 // CHECK2-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 5 // CHECK2-NEXT: store i32 [[ADD17]], i32* [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK2: for.end18: // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@foo2 -// CHECK2-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32 [[START:%.*]], i32 [[END:%.*]], i32 [[STEP:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4 @@ -1335,34 +1335,34 @@ extern "C" void tfoo7() { // CHECK2-NEXT: store i32 [[ADD21]], i32* [[J]], align 4 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4 -// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP12]], i32 noundef [[TMP13]]) +// CHECK2-NEXT: call void (...) @body(i32 [[TMP12]], i32 [[TMP13]]) // CHECK2-NEXT: br label [[FOR_INC:%.*]] // CHECK2: for.inc: // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC22:%.*]] // CHECK2: for.inc22: // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4 // CHECK2-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK2-NEXT: store i32 [[INC23]], i32* [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK2: for.end24: // CHECK2-NEXT: br label [[FOR_INC25:%.*]] // CHECK2: for.inc25: // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4 // CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP16]], 5 // CHECK2-NEXT: store i32 [[ADD26]], i32* [[DOTFLOOR_1_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK2: for.end27: // CHECK2-NEXT: br label [[FOR_INC28:%.*]] // CHECK2: for.inc28: // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4 // CHECK2-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP17]], 5 // CHECK2-NEXT: store i32 [[ADD29]], i32* [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: for.end30: // CHECK2-NEXT: ret void // @@ -1471,27 +1471,27 @@ extern "C" void tfoo7() { // CHECK2-NEXT: store i32 [[ADD26]], i32* [[J]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[J]], align 4 -// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP18]], i32 noundef [[TMP19]]) +// CHECK2-NEXT: call void (...) @body(i32 [[TMP18]], i32 [[TMP19]]) // CHECK2-NEXT: br label [[FOR_INC:%.*]] // CHECK2: for.inc: // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC27:%.*]] // CHECK2: for.inc27: // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4 // CHECK2-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP21]], 1 // CHECK2-NEXT: store i32 [[INC28]], i32* [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK2: for.end29: // CHECK2-NEXT: br label [[FOR_INC30:%.*]] // CHECK2: for.inc30: // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4 // CHECK2-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP22]], 5 // CHECK2-NEXT: store i32 [[ADD31]], i32* [[DOTFLOOR_1_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK2: for.end32: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: @@ -1624,27 +1624,27 @@ extern "C" void tfoo7() { // CHECK2-NEXT: store i32 [[ADD31]], i32* [[J]], align 4 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[J]], align 4 -// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP20]], i32 noundef [[TMP21]]) +// CHECK2-NEXT: call void (...) @body(i32 [[TMP20]], i32 [[TMP21]]) // CHECK2-NEXT: br label [[FOR_INC:%.*]] // CHECK2: for.inc: // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP22]], 1 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC32:%.*]] // CHECK2: for.inc32: // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4 // CHECK2-NEXT: [[INC33:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK2-NEXT: store i32 [[INC33]], i32* [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK2: for.end34: // CHECK2-NEXT: br label [[FOR_INC35:%.*]] // CHECK2: for.inc35: // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4 // CHECK2-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP24]], 5 // CHECK2-NEXT: store i32 [[ADD36]], i32* [[DOTFLOOR_1_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK2: for.end37: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: @@ -1852,7 +1852,7 @@ extern "C" void tfoo7() { // CHECK2-NEXT: store i32 [[ADD94]], i32* [[I]], align 4 // CHECK2-NEXT: [[TMP40:%.*]] = load i32, i32* [[I]], align 4 // CHECK2-NEXT: [[TMP41:%.*]] = load i32, i32* [[J13]], align 4 -// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP40]], i32 noundef [[TMP41]]) +// CHECK2-NEXT: call void (...) @body(i32 [[TMP40]], i32 [[TMP41]]) // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] @@ -1879,7 +1879,7 @@ extern "C" void tfoo7() { // // // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -1951,13 +1951,13 @@ extern "C" void tfoo7() { // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 7, [[MUL10]] // CHECK2-NEXT: store i32 [[ADD11]], i32* [[I]], align 4 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 -// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP13]]) +// CHECK2-NEXT: call void (...) @body(i32 [[TMP13]]) // CHECK2-NEXT: br label [[FOR_INC:%.*]] // CHECK2: for.inc: // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: @@ -1977,12 +1977,12 @@ extern "C" void tfoo7() { // CHECK2-LABEL: define {{[^@]+}}@tfoo7 // CHECK2-SAME: () #[[ATTR2]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: call void @_Z4foo7IiLi3ELi5EEvT_S0_(i32 noundef 0, i32 noundef 42) +// CHECK2-NEXT: call void @_Z4foo7IiLi3ELi5EEvT_S0_(i32 0, i32 42) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_Z4foo7IiLi3ELi5EEvT_S0_ -// CHECK2-SAME: (i32 noundef [[START:%.*]], i32 noundef [[END:%.*]]) #[[ATTR2]] comdat { +// CHECK2-SAME: (i32 [[START:%.*]], i32 [[END:%.*]]) #[[ATTR2]] comdat { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4 @@ -2047,20 +2047,20 @@ extern "C" void tfoo7() { // CHECK2-NEXT: [[ADD14:%.*]] = add i32 [[TMP13]], [[MUL]] // CHECK2-NEXT: store i32 [[ADD14]], i32* [[I]], align 4 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 -// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP15]]) +// CHECK2-NEXT: call void (...) @body(i32 [[TMP15]]) // CHECK2-NEXT: br label [[FOR_INC:%.*]] // CHECK2: for.inc: // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC15:%.*]] // CHECK2: for.inc15: // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4 // CHECK2-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP17]], 5 // CHECK2-NEXT: store i32 [[ADD16]], i32* [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] // CHECK2: for.end17: // CHECK2-NEXT: ret void // diff --git a/clang/test/OpenMP/tile_codegen_for_dependent.cpp b/clang/test/OpenMP/tile_codegen_for_dependent.cpp index bfdbc2a240eeeb0f055fae91c0c0a5bca1a7c5c0..7bf0445b33e9998f5c888c58a259a37bddb951cf 100644 --- a/clang/test/OpenMP/tile_codegen_for_dependent.cpp +++ b/clang/test/OpenMP/tile_codegen_for_dependent.cpp @@ -151,7 +151,7 @@ extern "C" void body(...) {} // IR-NEXT: %[[TMP31:.+]] = load i32, i32* %[[END_ADDR]], align 4 // IR-NEXT: %[[TMP32:.+]] = load i32, i32* %[[STEP_ADDR]], align 4 // IR-NEXT: %[[TMP33:.+]] = load i32, i32* %[[I]], align 4 -// IR-NEXT: call void (...) @body(i32 noundef %[[TMP30]], i32 noundef %[[TMP31]], i32 noundef %[[TMP32]], i32 noundef %[[TMP33]]) +// IR-NEXT: call void (...) @body(i32 %[[TMP30]], i32 %[[TMP31]], i32 %[[TMP32]], i32 %[[TMP33]]) // IR-NEXT: br label %[[FOR_INC:.+]] // IR-EMPTY: // IR-NEXT: [[FOR_INC]]: diff --git a/clang/test/OpenMP/tile_codegen_tile_for.cpp b/clang/test/OpenMP/tile_codegen_tile_for.cpp index 7cd6a8e1a4c3cd8061f8167db11b0310f7d6dd08..e4e5548b2f93357ea1242fb20a4f3e0d7b79c0bb 100644 --- a/clang/test/OpenMP/tile_codegen_tile_for.cpp +++ b/clang/test/OpenMP/tile_codegen_tile_for.cpp @@ -196,7 +196,7 @@ extern "C" void body(...) {} // IR-NEXT: %[[TMP40:.+]] = load i32, i32* %[[END_ADDR]], align 4 // IR-NEXT: %[[TMP41:.+]] = load i32, i32* %[[STEP_ADDR]], align 4 // IR-NEXT: %[[TMP42:.+]] = load i32, i32* %[[I]], align 4 -// IR-NEXT: call void (...) @body(i32 noundef %[[TMP39]], i32 noundef %[[TMP40]], i32 noundef %[[TMP41]], i32 noundef %[[TMP42]]) +// IR-NEXT: call void (...) @body(i32 %[[TMP39]], i32 %[[TMP40]], i32 %[[TMP41]], i32 %[[TMP42]]) // IR-NEXT: br label %[[FOR_INC:.+]] // IR-EMPTY: // IR-NEXT: [[FOR_INC]]: diff --git a/clang/test/OpenMP/unroll_codegen_factor.cpp b/clang/test/OpenMP/unroll_codegen_factor.cpp index 53edaa3367627bb8b87080769a5af2867184bfa0..e5280e3439c6c9691c40234a58ddbefb2d381583 100644 --- a/clang/test/OpenMP/unroll_codegen_factor.cpp +++ b/clang/test/OpenMP/unroll_codegen_factor.cpp @@ -37,7 +37,7 @@ extern "C" void body(...) {} // IR-NEXT: %[[TMP4:.+]] = load i32, i32* %[[END_ADDR]], align 4 // IR-NEXT: %[[TMP5:.+]] = load i32, i32* %[[STEP_ADDR]], align 4 // IR-NEXT: %[[TMP6:.+]] = load i32, i32* %[[I]], align 4 -// IR-NEXT: call void (...) @body(i32 noundef %[[TMP3]], i32 noundef %[[TMP4]], i32 noundef %[[TMP5]], i32 noundef %[[TMP6]]) +// IR-NEXT: call void (...) @body(i32 %[[TMP3]], i32 %[[TMP4]], i32 %[[TMP5]], i32 %[[TMP6]]) // IR-NEXT: br label %[[FOR_INC:.+]] // IR-EMPTY: // IR-NEXT: [[FOR_INC]]: diff --git a/clang/test/OpenMP/unroll_codegen_for_collapse_outer.cpp b/clang/test/OpenMP/unroll_codegen_for_collapse_outer.cpp index 447d61a2b494ab04dc677c6c06c84b84961c1173..879db7b911dbbd07825502fcbe0f2655258c1698 100644 --- a/clang/test/OpenMP/unroll_codegen_for_collapse_outer.cpp +++ b/clang/test/OpenMP/unroll_codegen_for_collapse_outer.cpp @@ -202,7 +202,7 @@ extern "C" void body(...) {} // IR-NEXT: %[[TMP49:.+]] = load i32, i32* %[[STEP_ADDR]], align 4 // IR-NEXT: %[[TMP50:.+]] = load i32, i32* %[[I22]], align 4 // IR-NEXT: %[[TMP51:.+]] = load i32, i32* %[[J]], align 4 -// IR-NEXT: call void (...) @body(i32 noundef %[[TMP47]], i32 noundef %[[TMP48]], i32 noundef %[[TMP49]], i32 noundef %[[TMP50]], i32 noundef %[[TMP51]]) +// IR-NEXT: call void (...) @body(i32 %[[TMP47]], i32 %[[TMP48]], i32 %[[TMP49]], i32 %[[TMP50]], i32 %[[TMP51]]) // IR-NEXT: br label %[[FOR_INC:.+]] // IR-EMPTY: // IR-NEXT: [[FOR_INC]]: diff --git a/clang/test/OpenMP/unroll_codegen_for_partial.cpp b/clang/test/OpenMP/unroll_codegen_for_partial.cpp index e97f1e6708897af47bed66ee6f330428b51f21c6..9a6e480e18f4819aa74d54cda304ddae1ef8e5b0 100644 --- a/clang/test/OpenMP/unroll_codegen_for_partial.cpp +++ b/clang/test/OpenMP/unroll_codegen_for_partial.cpp @@ -139,7 +139,7 @@ extern "C" void body(...) {} // IR-NEXT: %[[TMP30:.+]] = load i32, i32* %[[END_ADDR]], align 4 // IR-NEXT: %[[TMP31:.+]] = load i32, i32* %[[STEP_ADDR]], align 4 // IR-NEXT: %[[TMP32:.+]] = load i32, i32* %[[I]], align 4 -// IR-NEXT: call void (...) @body(i32 noundef %[[TMP29]], i32 noundef %[[TMP30]], i32 noundef %[[TMP31]], i32 noundef %[[TMP32]]) +// IR-NEXT: call void (...) @body(i32 %[[TMP29]], i32 %[[TMP30]], i32 %[[TMP31]], i32 %[[TMP32]]) // IR-NEXT: br label %[[FOR_INC:.+]] // IR-EMPTY: // IR-NEXT: [[FOR_INC]]: diff --git a/clang/test/OpenMP/unroll_codegen_full.cpp b/clang/test/OpenMP/unroll_codegen_full.cpp index edc21c80aa1570f8a846b940a1b3c06d001cfa52..cf5cac94a32b6084d92547ed936cc681523899c8 100644 --- a/clang/test/OpenMP/unroll_codegen_full.cpp +++ b/clang/test/OpenMP/unroll_codegen_full.cpp @@ -26,7 +26,7 @@ extern "C" void body(...) {} // IR-EMPTY: // IR-NEXT: [[FOR_BODY]]: // IR-NEXT: %[[TMP1:.+]] = load i32, i32* %[[I]], align 4 -// IR-NEXT: call void (...) @body(i32 noundef %[[TMP1]]) +// IR-NEXT: call void (...) @body(i32 %[[TMP1]]) // IR-NEXT: br label %[[FOR_INC:.+]] // IR-EMPTY: // IR-NEXT: [[FOR_INC]]: diff --git a/clang/test/OpenMP/unroll_codegen_heuristic.cpp b/clang/test/OpenMP/unroll_codegen_heuristic.cpp index a685c387c89c17c1b68326217ce3ec12062fd4af..d66b53a118b6d490157f6c3ae5cabe4e0a246832 100644 --- a/clang/test/OpenMP/unroll_codegen_heuristic.cpp +++ b/clang/test/OpenMP/unroll_codegen_heuristic.cpp @@ -37,7 +37,7 @@ extern "C" void body(...) {} // IR-NEXT: %[[TMP4:.+]] = load i32, i32* %[[END_ADDR]], align 4 // IR-NEXT: %[[TMP5:.+]] = load i32, i32* %[[STEP_ADDR]], align 4 // IR-NEXT: %[[TMP6:.+]] = load i32, i32* %[[I]], align 4 -// IR-NEXT: call void (...) @body(i32 noundef %[[TMP3]], i32 noundef %[[TMP4]], i32 noundef %[[TMP5]], i32 noundef %[[TMP6]]) +// IR-NEXT: call void (...) @body(i32 %[[TMP3]], i32 %[[TMP4]], i32 %[[TMP5]], i32 %[[TMP6]]) // IR-NEXT: br label %[[FOR_INC:.+]] // IR-EMPTY: // IR-NEXT: [[FOR_INC]]: diff --git a/clang/test/OpenMP/unroll_codegen_parallel_for_factor.cpp b/clang/test/OpenMP/unroll_codegen_parallel_for_factor.cpp index 6a7f4b5b80a3e5ad0d7dc6bde013c86bd7554938..cee8fc212c03bd7679dfcfb9dd89cd297bb2725a 100644 --- a/clang/test/OpenMP/unroll_codegen_parallel_for_factor.cpp +++ b/clang/test/OpenMP/unroll_codegen_parallel_for_factor.cpp @@ -168,7 +168,7 @@ extern "C" void func(int start, int end, int step) { // IR-NEXT: %[[TMP35:.+]] = load i32, i32* %[[TMP0]], align 4 // IR-NEXT: %[[TMP36:.+]] = load i32, i32* %[[TMP1]], align 4 // IR-NEXT: %[[TMP37:.+]] = load i32, i32* %[[I]], align 4 -// IR-NEXT: call void (...) @body(i32 noundef %[[TMP34]], i32 noundef %[[TMP35]], i32 noundef %[[TMP36]], i32 noundef %[[TMP37]]) +// IR-NEXT: call void (...) @body(i32 %[[TMP34]], i32 %[[TMP35]], i32 %[[TMP36]], i32 %[[TMP37]]) // IR-NEXT: br label %[[FOR_INC:.+]] // IR-EMPTY: // IR-NEXT: [[FOR_INC]]: diff --git a/clang/test/OpenMP/unroll_codegen_partial.cpp b/clang/test/OpenMP/unroll_codegen_partial.cpp index cfe2fab23b954ef8e00ffe5b51443488d1170f6f..9f18d733126955bc1dcd7b1d241e91c5c5eff468 100644 --- a/clang/test/OpenMP/unroll_codegen_partial.cpp +++ b/clang/test/OpenMP/unroll_codegen_partial.cpp @@ -37,7 +37,7 @@ extern "C" void body(...) {} // IR-NEXT: %[[TMP4:.+]] = load i32, i32* %[[END_ADDR]], align 4 // IR-NEXT: %[[TMP5:.+]] = load i32, i32* %[[STEP_ADDR]], align 4 // IR-NEXT: %[[TMP6:.+]] = load i32, i32* %[[I]], align 4 -// IR-NEXT: call void (...) @body(i32 noundef %[[TMP3]], i32 noundef %[[TMP4]], i32 noundef %[[TMP5]], i32 noundef %[[TMP6]]) +// IR-NEXT: call void (...) @body(i32 %[[TMP3]], i32 %[[TMP4]], i32 %[[TMP5]], i32 %[[TMP6]]) // IR-NEXT: br label %[[FOR_INC:.+]] // IR-EMPTY: // IR-NEXT: [[FOR_INC]]: diff --git a/clang/test/OpenMP/unroll_codegen_tile_for.cpp b/clang/test/OpenMP/unroll_codegen_tile_for.cpp index 138d7171fc66614e4fc8afb26788e7717703e750..4f7bc347c3598f1190c46bb98ba26ee6f8a35f73 100644 --- a/clang/test/OpenMP/unroll_codegen_tile_for.cpp +++ b/clang/test/OpenMP/unroll_codegen_tile_for.cpp @@ -187,7 +187,7 @@ extern "C" void body(...) {} // IR-NEXT: %[[TMP40:.+]] = load i32, i32* %[[END_ADDR]], align 4 // IR-NEXT: %[[TMP41:.+]] = load i32, i32* %[[STEP_ADDR]], align 4 // IR-NEXT: %[[TMP42:.+]] = load i32, i32* %[[I]], align 4 -// IR-NEXT: call void (...) @body(i32 noundef %[[TMP39]], i32 noundef %[[TMP40]], i32 noundef %[[TMP41]], i32 noundef %[[TMP42]]) +// IR-NEXT: call void (...) @body(i32 %[[TMP39]], i32 %[[TMP40]], i32 %[[TMP41]], i32 %[[TMP42]]) // IR-NEXT: br label %[[FOR_INC:.+]] // IR-EMPTY: // IR-NEXT: [[FOR_INC]]: diff --git a/clang/test/OpenMP/unroll_codegen_unroll_for.cpp b/clang/test/OpenMP/unroll_codegen_unroll_for.cpp index 27597adbc091795d83513e6eea10d7f3ac0eb9d0..1d82b6eb77d96ddff17f3873420934b6ee534a7a 100644 --- a/clang/test/OpenMP/unroll_codegen_unroll_for.cpp +++ b/clang/test/OpenMP/unroll_codegen_unroll_for.cpp @@ -181,7 +181,7 @@ extern "C" void body(...) {} // IR-NEXT: %[[TMP40:.+]] = load i32, i32* %[[END_ADDR]], align 4 // IR-NEXT: %[[TMP41:.+]] = load i32, i32* %[[STEP_ADDR]], align 4 // IR-NEXT: %[[TMP42:.+]] = load i32, i32* %[[I]], align 4 -// IR-NEXT: call void (...) @body(i32 noundef %[[TMP39]], i32 noundef %[[TMP40]], i32 noundef %[[TMP41]], i32 noundef %[[TMP42]]) +// IR-NEXT: call void (...) @body(i32 %[[TMP39]], i32 %[[TMP40]], i32 %[[TMP41]], i32 %[[TMP42]]) // IR-NEXT: br label %[[FOR_INC:.+]] // IR-EMPTY: // IR-NEXT: [[FOR_INC]]: diff --git a/clang/test/OpenMP/unroll_codegen_unroll_for_attr.cpp b/clang/test/OpenMP/unroll_codegen_unroll_for_attr.cpp index 027bca496eb2570a84714f5b65b26f031b52bede..f431201bcf476315757224945eab6f4bbf71df08 100644 --- a/clang/test/OpenMP/unroll_codegen_unroll_for_attr.cpp +++ b/clang/test/OpenMP/unroll_codegen_unroll_for_attr.cpp @@ -181,7 +181,7 @@ extern "C" void body(...) {} // IR-NEXT: %[[TMP40:.+]] = load i32, i32* %[[END_ADDR]], align 4 // IR-NEXT: %[[TMP41:.+]] = load i32, i32* %[[STEP_ADDR]], align 4 // IR-NEXT: %[[TMP42:.+]] = load i32, i32* %[[I]], align 4 -// IR-NEXT: call void (...) @body(i32 noundef %[[TMP39]], i32 noundef %[[TMP40]], i32 noundef %[[TMP41]], i32 noundef %[[TMP42]]) +// IR-NEXT: call void (...) @body(i32 %[[TMP39]], i32 %[[TMP40]], i32 %[[TMP41]], i32 %[[TMP42]]) // IR-NEXT: br label %[[FOR_INC:.+]] // IR-EMPTY: // IR-NEXT: [[FOR_INC]]: diff --git a/clang/test/OpenMP/vla_crash.c b/clang/test/OpenMP/vla_crash.c index fdef87e4c5b5d64443a7dfb5f23cdcbdcf451ee6..0d881ed6a810d2622a355e77c5b324105f64e65a 100644 --- a/clang/test/OpenMP/vla_crash.c +++ b/clang/test/OpenMP/vla_crash.c @@ -43,7 +43,7 @@ void bar(int n, int *a) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i64 noundef [[VLA1:%.*]], i32**** noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i64 [[VLA1:%.*]], i32**** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 @@ -83,7 +83,7 @@ void bar(int n, int *a) { // // // CHECK1-LABEL: define {{[^@]+}}@bar -// CHECK1-SAME: (i32 noundef signext [[N:%.*]], i32* noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 signext [[N:%.*]], i32* [[A:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 @@ -106,7 +106,7 @@ void bar(int n, int *a) { // // // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 -// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[P:%.*]], i32** noundef nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32** nonnull align 8 dereferenceable(8) [[P:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 diff --git a/clang/test/PCH/builtin-is-constant-evaluated.cpp b/clang/test/PCH/builtin-is-constant-evaluated.cpp index e0b8957702ed4a058420f50f0d63a34a5dd7d4d8..8d2804e4ee5a704ffb97768936647dbfd6edc37b 100644 --- a/clang/test/PCH/builtin-is-constant-evaluated.cpp +++ b/clang/test/PCH/builtin-is-constant-evaluated.cpp @@ -38,9 +38,9 @@ void g(...); // CHECK: store float 0.000000e+00, float* %[[D:.*]], // CHECK: store float 0.000000e+00, float* %[[E:.*]], // CHECK: load i8, i8* %[[A]], -// CHECK: call {{.*}} @_Z1gz(i32 noundef %{{[^,]+}}, i32 noundef 1 -// CXX11-SAME: , i32 noundef 1 -// CHECK-SAME: , double noundef %{{[^,]+}}, double noundef 0.000000e+00) +// CHECK: call {{.*}} @_Z1gz(i32 %{{[^,]+}}, i32 1 +// CXX11-SAME: , i32 1 +// CHECK-SAME: , double %{{[^,]+}}, double 0.000000e+00) void f() { bool a = __builtin_is_constant_evaluated(); const bool b = __builtin_is_constant_evaluated(); diff --git a/clang/test/PCH/chain-pending-instantiations.cpp b/clang/test/PCH/chain-pending-instantiations.cpp index c9d03f3bbfec149902de9620bd74f002d7903b53..e87d3366ecb99bd2aa42775630b60bc6cac5ad96 100644 --- a/clang/test/PCH/chain-pending-instantiations.cpp +++ b/clang/test/PCH/chain-pending-instantiations.cpp @@ -1,5 +1,5 @@ // RUN: %clang_cc1 %s -emit-llvm -triple i686-pc-linux -o - -chain-include %s -chain-include %s | FileCheck %s -// CHECK: define linkonce_odr noundef %{{[^ ]+}} @_ZN1AI1BE3getEv +// CHECK: define linkonce_odr %{{[^ ]+}} @_ZN1AI1BE3getEv #if !defined(PASS1) #define PASS1 diff --git a/clang/test/PCH/dllexport-default-arg-closure.cpp b/clang/test/PCH/dllexport-default-arg-closure.cpp index 5d400acba1c4fab02e8c42086ccc063a0f9775dc..32e0a721c77527c6074090c0e89e8b7a82ee2936 100644 --- a/clang/test/PCH/dllexport-default-arg-closure.cpp +++ b/clang/test/PCH/dllexport-default-arg-closure.cpp @@ -18,7 +18,7 @@ struct __declspec(dllexport) Foo { // Demangles as: // void Foo::`default constructor closure'(void) // CHECK: define weak_odr dso_local dllexport void @"??_FFoo@@QEAAXXZ"(%struct.Foo*{{.*}}) -// CHECK: call noundef %struct.Foo* @"??0Foo@@QEAA@W4E@0@@Z"(%struct.Foo* {{.*}}, i32 noundef 0) +// CHECK: call %struct.Foo* @"??0Foo@@QEAA@W4E@0@@Z"(%struct.Foo* {{.*}}, i32 0) #else diff --git a/clang/test/PCH/no-escaping-block-tail-calls.cpp b/clang/test/PCH/no-escaping-block-tail-calls.cpp index b14b7ec24b8cb245fd7ff5091b00387f1b5a810e..bf197267d67d402d2d8aff32326ff4278e61330e 100644 --- a/clang/test/PCH/no-escaping-block-tail-calls.cpp +++ b/clang/test/PCH/no-escaping-block-tail-calls.cpp @@ -4,8 +4,8 @@ // Check that -fno-escaping-block-tail-calls doesn't disable tail-call // optimization if the block is non-escaping. -// CHECK-LABEL: define internal noundef i32 @___ZN1S1mEv_block_invoke( -// CHECK: %[[CALL:.*]] = tail call noundef i32 @_ZN1S3fooER2S0( +// CHECK-LABEL: define internal i32 @___ZN1S1mEv_block_invoke( +// CHECK: %[[CALL:.*]] = tail call i32 @_ZN1S3fooER2S0( // CHECK-NEXT: ret i32 %[[CALL]] void test() { diff --git a/clang/test/PCH/uses-seh.cpp b/clang/test/PCH/uses-seh.cpp index 430a95d211db03b4a09e72a7b57bda72f7ee74da..53ca1ef154ffd73e4fb3bac9d878bcaf548fd527 100644 --- a/clang/test/PCH/uses-seh.cpp +++ b/clang/test/PCH/uses-seh.cpp @@ -19,8 +19,8 @@ inline int f() { } int x = f(); -// CHECK: define linkonce_odr dso_local noundef i32 @"?f@@YAHXZ"() -// CHECK: define internal noundef i32 @"?filt$0@0@f@@"({{.*}}) +// CHECK: define linkonce_odr dso_local i32 @"?f@@YAHXZ"() +// CHECK: define internal i32 @"?filt$0@0@f@@"({{.*}}) #else diff --git a/clang/test/Profile/c-unprofiled-blocks.c b/clang/test/Profile/c-unprofiled-blocks.c index 65d096ffc8745bca898a2ae9681ac8bd4259224b..834a307ed770cf2f2d4b6ef24c8431b723915bfd 100644 --- a/clang/test/Profile/c-unprofiled-blocks.c +++ b/clang/test/Profile/c-unprofiled-blocks.c @@ -4,7 +4,7 @@ // RUN: llvm-profdata merge %S/Inputs/c-unprofiled-blocks.proftext -o %t.profdata // RUN: %clang_cc1 -triple x86_64-apple-macosx10.9 -main-file-name c-unprofiled-blocks.c %s -o - -emit-llvm -fprofile-instrument-use-path=%t.profdata | FileCheck -check-prefix=PGOUSE %s -// PGOUSE-LABEL: @never_called(i32 noundef %i) +// PGOUSE-LABEL: @never_called(i32 %i) int never_called(int i) { // PGOUSE: br i1 %{{[^,]*}}, label %{{[^,]*}}, label %{{[^,]*}}{{$}} if (i) {} @@ -30,7 +30,7 @@ int never_called(int i) { } } -// PGOUSE-LABEL: @dead_code(i32 noundef %i) +// PGOUSE-LABEL: @dead_code(i32 %i) int dead_code(int i) { // PGOUSE: br {{.*}}, !prof !{{[0-9]+}} if (i) { @@ -62,7 +62,7 @@ int dead_code(int i) { return 2; } -// PGOUSE-LABEL: @main(i32 noundef %argc, i8** noundef %argv) +// PGOUSE-LABEL: @main(i32 %argc, i8** %argv) int main(int argc, const char *argv[]) { dead_code(0); return 0; diff --git a/clang/test/Profile/cxx-abc-deleting-dtor.cpp b/clang/test/Profile/cxx-abc-deleting-dtor.cpp index da8acb267d5ac7dd50798ae45e3b5ff03c11db73..17cb6235009ba4a333f2673aafcd3ed4f3f8abf4 100644 --- a/clang/test/Profile/cxx-abc-deleting-dtor.cpp +++ b/clang/test/Profile/cxx-abc-deleting-dtor.cpp @@ -24,12 +24,12 @@ DerivedABC *useABCVTable() { return new DerivedABC(); } // MSVC: @"__profn_??1ABC@@{{.*}}" = // MSVC-NOT: @"__profn_??_G{{.*}}" = -// MSVC-LABEL: define linkonce_odr dso_local noundef i8* @"??_GDerivedABC@@UEAAPEAXI@Z"(%struct.DerivedABC* {{[^,]*}} %this, {{.*}}) +// MSVC-LABEL: define linkonce_odr dso_local i8* @"??_GDerivedABC@@UEAAPEAXI@Z"(%struct.DerivedABC* {{[^,]*}} %this, {{.*}}) // MSVC-NOT: call void @llvm.instrprof.increment({{.*}}) // MSVC: call void @"??1DerivedABC@@UEAA@XZ"({{.*}}) // MSVC: ret void -// MSVC-LABEL: define linkonce_odr dso_local noundef i8* @"??_GABC@@UEAAPEAXI@Z"(%struct.ABC* {{[^,]*}} %this, {{.*}}) +// MSVC-LABEL: define linkonce_odr dso_local i8* @"??_GABC@@UEAAPEAXI@Z"(%struct.ABC* {{[^,]*}} %this, {{.*}}) // MSVC-NOT: call void @llvm.instrprof.increment({{.*}}) // MSVC: call void @llvm.trap() // MSVC-NEXT: unreachable diff --git a/clang/test/Profile/cxx-lambda.cpp b/clang/test/Profile/cxx-lambda.cpp index 9dbd619acb856979887ccf504143c2149f0b27bb..4512f23e0849a190f022d5bcea95162233559824 100644 --- a/clang/test/Profile/cxx-lambda.cpp +++ b/clang/test/Profile/cxx-lambda.cpp @@ -19,8 +19,8 @@ void lambdas() { int i = 1; - // LMBGEN-LABEL: define internal{{( [0-9_a-z]*cc)?( noundef)?( zeroext)?}} i1 @"_ZZ7lambdasvENK3$_0clEi"( - // LMBUSE-LABEL: define internal{{( [0-9_a-z]*cc)?( noundef)?( zeroext)?}} i1 @"_ZZ7lambdasvENK3$_0clEi"( + // LMBGEN-LABEL: define internal{{( [0-9_a-z]*cc)?( zeroext)?}} i1 @"_ZZ7lambdasvENK3$_0clEi"( + // LMBUSE-LABEL: define internal{{( [0-9_a-z]*cc)?( zeroext)?}} i1 @"_ZZ7lambdasvENK3$_0clEi"( // LMBGEN: store {{.*}} @[[LFC]], i64 0, i64 0 auto f = [&i](int k) { // LMBGEN: store {{.*}} @[[LFC]], i64 0, i64 1 diff --git a/clang/test/Profile/gcc-flag-compatibility-aix.c b/clang/test/Profile/gcc-flag-compatibility-aix.c index 215adfc0e4a3b0bb818b494aa416ea35c592b9ec..ead654dd102fbaf5c984f996da779e4030454a18 100644 --- a/clang/test/Profile/gcc-flag-compatibility-aix.c +++ b/clang/test/Profile/gcc-flag-compatibility-aix.c @@ -9,14 +9,12 @@ // On AIX, -flto is required with -fprofile-generate -// RUN: %clang %s -c -S -o - -emit-llvm -target powerpc64-unknown-aix -flto -fprofile-generate -fno-experimental-new-pass-manager | FileCheck -check-prefix=PROFILE-GEN %s -// RUN: %clang %s -c -S -o - -emit-llvm -target powerpc64-unknown-aix -flto -fprofile-generate -fexperimental-new-pass-manager | FileCheck -check-prefix=PROFILE-GEN %s +// RUN: %clang %s -c -S -o - -emit-llvm -target powerpc64-unknown-aix -flto -fprofile-generate | FileCheck -check-prefix=PROFILE-GEN %s // PROFILE-GEN: @__profc_main = {{(private|internal)}} global [2 x i64] zeroinitializer, section // PROFILE-GEN: @__profd_main = // Check that -fprofile-generate=/path/to generates /path/to/default.profraw -// RUN: %clang %s -c -S -o - -emit-llvm -target powerpc64-unknown-aix -flto -fprofile-generate=/path/to -fno-experimental-new-pass-manager | FileCheck -check-prefixes=PROFILE-GEN,PROFILE-GEN-EQ %s -// RxUN: %clang %s -c -S -o - -emit-llvm -target powerpc64-unknown-aix -flto -fprofile-generate=/path/to -fexperimental-new-pass-manager | FileCheck -check-prefixes=PROFILE-GEN,PROFILE-GEN-EQ %s +// RxUN: %clang %s -c -S -o - -emit-llvm -target powerpc64-unknown-aix -flto -fprofile-generate=/path/to | FileCheck -check-prefixes=PROFILE-GEN,PROFILE-GEN-EQ %s // PROFILE-GEN-EQ: constant [{{.*}} x i8] c"/path/to{{/|\\\\}}{{.*}}\00" // Check that -fprofile-use=some/path reads some/path/default.profdata @@ -24,16 +22,14 @@ // RUN: rm -rf %t.dir // RUN: mkdir -p %t.dir/some/path // RUN: llvm-profdata merge %S/Inputs/gcc-flag-compatibility.proftext -o %t.dir/some/path/default.profdata -// RUN: %clang %s -o - -Xclang -disable-llvm-passes -emit-llvm -S -fprofile-use=%t.dir/some/path -fno-experimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE %s -// RUN: %clang %s -o - -Xclang -disable-llvm-passes -emit-llvm -S -fprofile-use=%t.dir/some/path -fexperimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE %s +// RUN: %clang %s -o - -Xclang -disable-llvm-passes -emit-llvm -S -fprofile-use=%t.dir/some/path | FileCheck -check-prefix=PROFILE-USE %s // Check that -fprofile-use=some/path/file.prof reads some/path/file.prof // This uses Clang FE format profile. // RUN: rm -rf %t.dir // RUN: mkdir -p %t.dir/some/path // RUN: llvm-profdata merge %S/Inputs/gcc-flag-compatibility.proftext -o %t.dir/some/path/file.prof -// RUN: %clang %s -o - -Xclang -disable-llvm-passes -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof -fno-experimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE %s -// RUN: %clang %s -o - -Xclang -disable-llvm-passes -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof -fexperimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE %s +// RUN: %clang %s -o - -Xclang -disable-llvm-passes -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof | FileCheck -check-prefix=PROFILE-USE %s // PROFILE-USE: = !{!"branch_weights", i32 101, i32 2} // Check that -fprofile-use=some/path reads some/path/default.profdata @@ -41,20 +37,17 @@ // RUN: rm -rf %t.dir // RUN: mkdir -p %t.dir/some/path // RUN: llvm-profdata merge %S/Inputs/gcc-flag-compatibility_IR.proftext -o %t.dir/some/path/default.profdata -// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path -fno-experimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE-IR %s -// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path -fexperimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE-IR %s +// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path | FileCheck -check-prefix=PROFILE-USE-IR %s // Check that -fprofile-use=some/path/file.prof reads some/path/file.prof // This uses LLVM IR format profile. // RUN: rm -rf %t.dir // RUN: mkdir -p %t.dir/some/path // RUN: llvm-profdata merge %S/Inputs/gcc-flag-compatibility_IR.proftext -o %t.dir/some/path/file.prof -// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof -fno-experimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE-IR %s -// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof -fexperimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE-IR %s +// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof | FileCheck -check-prefix=PROFILE-USE-IR %s // // RUN: llvm-profdata merge %S/Inputs/gcc-flag-compatibility_IR_entry.proftext -o %t.dir/some/path/file.prof -// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof -fno-experimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE-IR %s -// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof -fexperimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE-IR %s +// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof | FileCheck -check-prefix=PROFILE-USE-IR %s // PROFILE-USE-IR: = !{!"branch_weights", i32 100, i32 1} diff --git a/clang/test/Profile/gcc-flag-compatibility.c b/clang/test/Profile/gcc-flag-compatibility.c index 1cfd3ecd7ee06793742b58015acba44c7ae0541b..cdec997a7aaa2a29f5a24c07508e5a85cbefd1c8 100644 --- a/clang/test/Profile/gcc-flag-compatibility.c +++ b/clang/test/Profile/gcc-flag-compatibility.c @@ -9,14 +9,12 @@ // On AIX, -flto is required with -fprofile-generate. gcc-flag-compatibility-aix.c is used to do the testing on AIX with -flto // XFAIL: aix -// RUN: %clang %s -c -S -o - -emit-llvm -fprofile-generate -fno-experimental-new-pass-manager | FileCheck -check-prefix=PROFILE-GEN %s -// RUN: %clang %s -c -S -o - -emit-llvm -fprofile-generate -fexperimental-new-pass-manager | FileCheck -check-prefix=PROFILE-GEN %s +// RUN: %clang %s -c -S -o - -emit-llvm -fprofile-generate | FileCheck -check-prefix=PROFILE-GEN %s // PROFILE-GEN: @__profc_main = {{(private|internal)}} global [2 x i64] zeroinitializer, section // PROFILE-GEN: @__profd_main = // Check that -fprofile-generate=/path/to generates /path/to/default.profraw -// RUN: %clang %s -c -S -o - -emit-llvm -fprofile-generate=/path/to -fno-experimental-new-pass-manager | FileCheck -check-prefixes=PROFILE-GEN,PROFILE-GEN-EQ %s -// RxUN: %clang %s -c -S -o - -emit-llvm -fprofile-generate=/path/to -fexperimental-new-pass-manager | FileCheck -check-prefixes=PROFILE-GEN,PROFILE-GEN-EQ %s +// RxUN: %clang %s -c -S -o - -emit-llvm -fprofile-generate=/path/to | FileCheck -check-prefixes=PROFILE-GEN,PROFILE-GEN-EQ %s // PROFILE-GEN-EQ: constant [{{.*}} x i8] c"/path/to{{/|\\\\}}{{.*}}\00" // Check that -fprofile-use=some/path reads some/path/default.profdata @@ -24,16 +22,14 @@ // RUN: rm -rf %t.dir // RUN: mkdir -p %t.dir/some/path // RUN: llvm-profdata merge %S/Inputs/gcc-flag-compatibility.proftext -o %t.dir/some/path/default.profdata -// RUN: %clang %s -o - -Xclang -disable-llvm-passes -emit-llvm -S -fprofile-use=%t.dir/some/path -fno-experimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE %s -// RUN: %clang %s -o - -Xclang -disable-llvm-passes -emit-llvm -S -fprofile-use=%t.dir/some/path -fexperimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE %s +// RUN: %clang %s -o - -Xclang -disable-llvm-passes -emit-llvm -S -fprofile-use=%t.dir/some/path | FileCheck -check-prefix=PROFILE-USE %s // Check that -fprofile-use=some/path/file.prof reads some/path/file.prof // This uses Clang FE format profile. // RUN: rm -rf %t.dir // RUN: mkdir -p %t.dir/some/path // RUN: llvm-profdata merge %S/Inputs/gcc-flag-compatibility.proftext -o %t.dir/some/path/file.prof -// RUN: %clang %s -o - -Xclang -disable-llvm-passes -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof -fno-experimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE %s -// RUN: %clang %s -o - -Xclang -disable-llvm-passes -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof -fexperimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE %s +// RUN: %clang %s -o - -Xclang -disable-llvm-passes -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof | FileCheck -check-prefix=PROFILE-USE %s // PROFILE-USE: = !{!"branch_weights", i32 101, i32 2} // Check that -fprofile-use=some/path reads some/path/default.profdata @@ -41,20 +37,17 @@ // RUN: rm -rf %t.dir // RUN: mkdir -p %t.dir/some/path // RUN: llvm-profdata merge %S/Inputs/gcc-flag-compatibility_IR.proftext -o %t.dir/some/path/default.profdata -// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path -fno-experimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE-IR %s -// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path -fexperimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE-IR %s +// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path | FileCheck -check-prefix=PROFILE-USE-IR %s // Check that -fprofile-use=some/path/file.prof reads some/path/file.prof // This uses LLVM IR format profile. // RUN: rm -rf %t.dir // RUN: mkdir -p %t.dir/some/path // RUN: llvm-profdata merge %S/Inputs/gcc-flag-compatibility_IR.proftext -o %t.dir/some/path/file.prof -// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof -fno-experimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE-IR %s -// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof -fexperimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE-IR %s +// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof | FileCheck -check-prefix=PROFILE-USE-IR %s // // RUN: llvm-profdata merge %S/Inputs/gcc-flag-compatibility_IR_entry.proftext -o %t.dir/some/path/file.prof -// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof -fno-experimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE-IR %s -// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof -fexperimental-new-pass-manager | FileCheck -check-prefix=PROFILE-USE-IR %s +// RUN: %clang %s -o - -emit-llvm -S -fprofile-use=%t.dir/some/path/file.prof | FileCheck -check-prefix=PROFILE-USE-IR %s // PROFILE-USE-IR: = !{!"branch_weights", i32 100, i32 1} diff --git a/clang/test/Sema/libbuiltins-ctype-powerpc64.c b/clang/test/Sema/libbuiltins-ctype-powerpc64.c index 6a5e6031c5ee27bbfa622c9e7908c27f225e8b43..ba0efb205944b3c4fb5c38e79a155eba08617b38 100644 --- a/clang/test/Sema/libbuiltins-ctype-powerpc64.c +++ b/clang/test/Sema/libbuiltins-ctype-powerpc64.c @@ -16,50 +16,50 @@ int tolower(int); int toupper(int); void test(int x) { - // CHECK: call signext i32 @isalnum(i32 noundef signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call signext i32 @isalnum(i32 signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isalnum(x); - // CHECK: call signext i32 @isalpha(i32 noundef signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call signext i32 @isalpha(i32 signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isalpha(x); - // CHECK: call signext i32 @isblank(i32 noundef signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call signext i32 @isblank(i32 signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isblank(x); - // CHECK: call signext i32 @iscntrl(i32 noundef signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call signext i32 @iscntrl(i32 signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)iscntrl(x); - // CHECK: call signext i32 @isdigit(i32 noundef signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call signext i32 @isdigit(i32 signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isdigit(x); - // CHECK: call signext i32 @isgraph(i32 noundef signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call signext i32 @isgraph(i32 signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isgraph(x); - // CHECK: call signext i32 @islower(i32 noundef signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call signext i32 @islower(i32 signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)islower(x); - // CHECK: call signext i32 @isprint(i32 noundef signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call signext i32 @isprint(i32 signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isprint(x); - // CHECK: call signext i32 @ispunct(i32 noundef signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call signext i32 @ispunct(i32 signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)ispunct(x); - // CHECK: call signext i32 @isspace(i32 noundef signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call signext i32 @isspace(i32 signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isspace(x); - // CHECK: call signext i32 @isupper(i32 noundef signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call signext i32 @isupper(i32 signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isupper(x); - // CHECK: call signext i32 @isxdigit(i32 noundef signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call signext i32 @isxdigit(i32 signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isxdigit(x); - // CHECK: call signext i32 @tolower(i32 noundef signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call signext i32 @tolower(i32 signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)tolower(x); - // CHECK: call signext i32 @toupper(i32 noundef signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call signext i32 @toupper(i32 signext {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)toupper(x); } -// CHECK: declare signext i32 @isalnum(i32 noundef signext) [[NUW_RO:#[0-9]+]] -// CHECK: declare signext i32 @isalpha(i32 noundef signext) [[NUW_RO:#[0-9]+]] -// CHECK: declare signext i32 @isblank(i32 noundef signext) [[NUW_RO:#[0-9]+]] -// CHECK: declare signext i32 @iscntrl(i32 noundef signext) [[NUW_RO:#[0-9]+]] -// CHECK: declare signext i32 @isdigit(i32 noundef signext) [[NUW_RO:#[0-9]+]] -// CHECK: declare signext i32 @isgraph(i32 noundef signext) [[NUW_RO:#[0-9]+]] -// CHECK: declare signext i32 @islower(i32 noundef signext) [[NUW_RO:#[0-9]+]] -// CHECK: declare signext i32 @isprint(i32 noundef signext) [[NUW_RO:#[0-9]+]] -// CHECK: declare signext i32 @ispunct(i32 noundef signext) [[NUW_RO:#[0-9]+]] -// CHECK: declare signext i32 @isspace(i32 noundef signext) [[NUW_RO:#[0-9]+]] -// CHECK: declare signext i32 @isupper(i32 noundef signext) [[NUW_RO:#[0-9]+]] -// CHECK: declare signext i32 @isxdigit(i32 noundef signext) [[NUW_RO:#[0-9]+]] -// CHECK: declare signext i32 @tolower(i32 noundef signext) [[NUW_RO:#[0-9]+]] -// CHECK: declare signext i32 @toupper(i32 noundef signext) [[NUW_RO:#[0-9]+]] +// CHECK: declare signext i32 @isalnum(i32 signext) [[NUW_RO:#[0-9]+]] +// CHECK: declare signext i32 @isalpha(i32 signext) [[NUW_RO:#[0-9]+]] +// CHECK: declare signext i32 @isblank(i32 signext) [[NUW_RO:#[0-9]+]] +// CHECK: declare signext i32 @iscntrl(i32 signext) [[NUW_RO:#[0-9]+]] +// CHECK: declare signext i32 @isdigit(i32 signext) [[NUW_RO:#[0-9]+]] +// CHECK: declare signext i32 @isgraph(i32 signext) [[NUW_RO:#[0-9]+]] +// CHECK: declare signext i32 @islower(i32 signext) [[NUW_RO:#[0-9]+]] +// CHECK: declare signext i32 @isprint(i32 signext) [[NUW_RO:#[0-9]+]] +// CHECK: declare signext i32 @ispunct(i32 signext) [[NUW_RO:#[0-9]+]] +// CHECK: declare signext i32 @isspace(i32 signext) [[NUW_RO:#[0-9]+]] +// CHECK: declare signext i32 @isupper(i32 signext) [[NUW_RO:#[0-9]+]] +// CHECK: declare signext i32 @isxdigit(i32 signext) [[NUW_RO:#[0-9]+]] +// CHECK: declare signext i32 @tolower(i32 signext) [[NUW_RO:#[0-9]+]] +// CHECK: declare signext i32 @toupper(i32 signext) [[NUW_RO:#[0-9]+]] // CHECK: attributes [[NUW_RO]] = { nounwind readonly{{.*}} } // CHECK: attributes [[NUW_RO_CALL]] = { nounwind readonly willreturn } diff --git a/clang/test/Sema/libbuiltins-ctype-x86_64.c b/clang/test/Sema/libbuiltins-ctype-x86_64.c index ed6e31e73434309fdf27af1152c276b41e3a255c..b8a2c7e81584a046bceea04abcc776286e30cffe 100644 --- a/clang/test/Sema/libbuiltins-ctype-x86_64.c +++ b/clang/test/Sema/libbuiltins-ctype-x86_64.c @@ -16,50 +16,50 @@ int tolower(int); int toupper(int); void test(int x) { - // CHECK: call i32 @isalnum(i32 noundef {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call i32 @isalnum(i32 {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isalnum(x); - // CHECK: call i32 @isalpha(i32 noundef {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call i32 @isalpha(i32 {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isalpha(x); - // CHECK: call i32 @isblank(i32 noundef {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call i32 @isblank(i32 {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isblank(x); - // CHECK: call i32 @iscntrl(i32 noundef {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call i32 @iscntrl(i32 {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)iscntrl(x); - // CHECK: call i32 @isdigit(i32 noundef {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call i32 @isdigit(i32 {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isdigit(x); - // CHECK: call i32 @isgraph(i32 noundef {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call i32 @isgraph(i32 {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isgraph(x); - // CHECK: call i32 @islower(i32 noundef {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call i32 @islower(i32 {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)islower(x); - // CHECK: call i32 @isprint(i32 noundef {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call i32 @isprint(i32 {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isprint(x); - // CHECK: call i32 @ispunct(i32 noundef {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call i32 @ispunct(i32 {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)ispunct(x); - // CHECK: call i32 @isspace(i32 noundef {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call i32 @isspace(i32 {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isspace(x); - // CHECK: call i32 @isupper(i32 noundef {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call i32 @isupper(i32 {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isupper(x); - // CHECK: call i32 @isxdigit(i32 noundef {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call i32 @isxdigit(i32 {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)isxdigit(x); - // CHECK: call i32 @tolower(i32 noundef {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call i32 @tolower(i32 {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)tolower(x); - // CHECK: call i32 @toupper(i32 noundef {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] + // CHECK: call i32 @toupper(i32 {{%[0-9]+}}) [[NUW_RO_CALL:#[0-9]+]] (void)toupper(x); } -// CHECK: declare i32 @isalnum(i32 noundef) [[NUW_RO:#[0-9]+]] -// CHECK: declare i32 @isalpha(i32 noundef) [[NUW_RO:#[0-9]+]] -// CHECK: declare i32 @isblank(i32 noundef) [[NUW_RO:#[0-9]+]] -// CHECK: declare i32 @iscntrl(i32 noundef) [[NUW_RO:#[0-9]+]] -// CHECK: declare i32 @isdigit(i32 noundef) [[NUW_RO:#[0-9]+]] -// CHECK: declare i32 @isgraph(i32 noundef) [[NUW_RO:#[0-9]+]] -// CHECK: declare i32 @islower(i32 noundef) [[NUW_RO:#[0-9]+]] -// CHECK: declare i32 @isprint(i32 noundef) [[NUW_RO:#[0-9]+]] -// CHECK: declare i32 @ispunct(i32 noundef) [[NUW_RO:#[0-9]+]] -// CHECK: declare i32 @isspace(i32 noundef) [[NUW_RO:#[0-9]+]] -// CHECK: declare i32 @isupper(i32 noundef) [[NUW_RO:#[0-9]+]] -// CHECK: declare i32 @isxdigit(i32 noundef) [[NUW_RO:#[0-9]+]] -// CHECK: declare i32 @tolower(i32 noundef) [[NUW_RO:#[0-9]+]] -// CHECK: declare i32 @toupper(i32 noundef) [[NUW_RO:#[0-9]+]] +// CHECK: declare i32 @isalnum(i32) [[NUW_RO:#[0-9]+]] +// CHECK: declare i32 @isalpha(i32) [[NUW_RO:#[0-9]+]] +// CHECK: declare i32 @isblank(i32) [[NUW_RO:#[0-9]+]] +// CHECK: declare i32 @iscntrl(i32) [[NUW_RO:#[0-9]+]] +// CHECK: declare i32 @isdigit(i32) [[NUW_RO:#[0-9]+]] +// CHECK: declare i32 @isgraph(i32) [[NUW_RO:#[0-9]+]] +// CHECK: declare i32 @islower(i32) [[NUW_RO:#[0-9]+]] +// CHECK: declare i32 @isprint(i32) [[NUW_RO:#[0-9]+]] +// CHECK: declare i32 @ispunct(i32) [[NUW_RO:#[0-9]+]] +// CHECK: declare i32 @isspace(i32) [[NUW_RO:#[0-9]+]] +// CHECK: declare i32 @isupper(i32) [[NUW_RO:#[0-9]+]] +// CHECK: declare i32 @isxdigit(i32) [[NUW_RO:#[0-9]+]] +// CHECK: declare i32 @tolower(i32) [[NUW_RO:#[0-9]+]] +// CHECK: declare i32 @toupper(i32) [[NUW_RO:#[0-9]+]] // CHECK: attributes [[NUW_RO]] = { nounwind readonly{{.*}} } // CHECK: attributes [[NUW_RO_CALL]] = { nounwind readonly willreturn } diff --git a/clang/test/Sema/pr30306.cpp b/clang/test/Sema/pr30306.cpp index 77ea29f924356990ade74ab21f3086ea4dd23812..413e2f5ab559536307ab579bf6afaf426dba1d89 100644 --- a/clang/test/Sema/pr30306.cpp +++ b/clang/test/Sema/pr30306.cpp @@ -3,10 +3,10 @@ struct A { A(int); ~A(); }; int f(const A &); // CHECK: call void @_ZN1AC1Ei -// CHECK-NEXT: call noundef i32 @_Z1fRK1A +// CHECK-NEXT: call i32 @_Z1fRK1A // CHECK-NEXT: call void @_ZN1AD1Ev // CHECK: call void @_ZN1AC1Ei -// CHECK-NEXT: call noundef i32 @_Z1fRK1A +// CHECK-NEXT: call i32 @_Z1fRK1A // CHECK-NEXT: call void @_ZN1AD1Ev template void g() { int a[f(3)]; diff --git a/clang/test/SemaCXX/linkage.cpp b/clang/test/SemaCXX/linkage.cpp index b55ba6bfed8022590b939bf17bb4a3977b746bbd..fc7cbeacfb4eb2589908f11589cb57dcec1a6ede 100644 --- a/clang/test/SemaCXX/linkage.cpp +++ b/clang/test/SemaCXX/linkage.cpp @@ -13,7 +13,7 @@ namespace test0 { void *foo() { return 0; } } A; - // CHECK: define linkonce_odr noundef i8* @_ZN5test01A3fooEv( + // CHECK: define linkonce_odr i8* @_ZN5test01A3fooEv( void test(A *a) { a->foo(); @@ -94,8 +94,8 @@ extern "C" { } } -// CHECK: define linkonce_odr noundef i8* @_ZN5test11A3fooILj0EEEPvv( -// CHECK: define linkonce_odr noundef i8* @_ZN5test21A1BILj0EE3fooEv( +// CHECK: define linkonce_odr i8* @_ZN5test11A3fooILj0EEEPvv( +// CHECK: define linkonce_odr i8* @_ZN5test21A1BILj0EE3fooEv( namespace test5 { struct foo { diff --git a/clang/test/SemaCXX/new-delete-array.cpp b/clang/test/SemaCXX/new-delete-array.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fca1ec132accab35e3daaa8c3eb09ba0f482c093 --- /dev/null +++ b/clang/test/SemaCXX/new-delete-array.cpp @@ -0,0 +1,9 @@ +// RUN: %clang_cc1 -fsyntax-only -std=c++17 %s -verify=cxx17 +// RUN: %clang_cc1 -fsyntax-only -std=c++14 %s -verify=cxx14 + +namespace PR51547 { +template struct A; // cxx14-note {{template is declared here}} +auto p = new A[]{}; // cxx14-error {{use of class template 'A' requires template arguments}} \ + cxx17-error {{cannot form array of deduced class template specialization type}} +} + diff --git a/clang/test/SemaObjC/debugger-support.m b/clang/test/SemaObjC/debugger-support.m index cd274c4440244b9f5f21147a57e10d47c14b36aa..5b3e649f221c257dc8bca4fbdbfea3b7c40ab530 100644 --- a/clang/test/SemaObjC/debugger-support.m +++ b/clang/test/SemaObjC/debugger-support.m @@ -10,5 +10,5 @@ void test0(id x) { // CHECK-NEXT: store i8* {{%.*}}, i8** [[X]], // CHECK-NEXT: [[T0:%.*]] = load i8*, i8** [[X]], // CHECK-NEXT: [[T1:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_ - // CHECK-NEXT: [[T2:%.*]] = call { i64, i64 } bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to { i64, i64 } (i8*, i8*)*)(i8* noundef [[T0]], i8* noundef [[T1]]) + // CHECK-NEXT: [[T2:%.*]] = call { i64, i64 } bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to { i64, i64 } (i8*, i8*)*)(i8* [[T0]], i8* [[T1]]) } diff --git a/clang/test/utils/update_cc_test_checks/Inputs/basic-cplusplus.cpp.expected b/clang/test/utils/update_cc_test_checks/Inputs/basic-cplusplus.cpp.expected index 82c09354ff0212172e8061f870846e4935063c17..fc077a7c779838c49d110e45c1b39f168dd85a8a 100644 --- a/clang/test/utils/update_cc_test_checks/Inputs/basic-cplusplus.cpp.expected +++ b/clang/test/utils/update_cc_test_checks/Inputs/basic-cplusplus.cpp.expected @@ -35,7 +35,7 @@ public: // CHECK-NEXT: store i32 [[X:%.*]], i32* [[X_ADDR]], align 4 // CHECK-NEXT: [[THIS1:%.*]] = load %class.Foo*, %class.Foo** [[THIS_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[X_ADDR]], align 4 -// CHECK-NEXT: call void @_ZN3FooC2Ei(%class.Foo* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK-NEXT: call void @_ZN3FooC2Ei(%class.Foo* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK-NEXT: ret void // Foo::Foo(int x) : x(x) {} @@ -44,7 +44,7 @@ Foo::Foo(int x) : x(x) {} // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %class.Foo*, align 8 // CHECK-NEXT: store %class.Foo* [[THIS:%.*]], %class.Foo** [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load %class.Foo*, %class.Foo** [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN3FooD2Ev(%class.Foo* noundef [[THIS1]]) #[[ATTR3:[0-9]+]] +// CHECK-NEXT: call void @_ZN3FooD2Ev(%class.Foo* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3:[0-9]+]] // CHECK-NEXT: ret void // Foo::~Foo() {} @@ -67,10 +67,10 @@ int Foo::function_defined_out_of_line(int arg) const { return x - arg; } // CHECK-LABEL: @main( // CHECK-NEXT: entry: // CHECK-NEXT: [[F:%.*]] = alloca [[CLASS_FOO:%.*]], align 4 -// CHECK-NEXT: call void @_ZN3FooC1Ei(%class.Foo* noundef [[F]], i32 noundef 1) -// CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_ZNK3Foo23function_defined_inlineEi(%class.Foo* noundef [[F]], i32 noundef 2) -// CHECK-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZNK3Foo28function_defined_out_of_lineEi(%class.Foo* noundef [[F]], i32 noundef 3) -// CHECK-NEXT: call void @_ZN3FooD1Ev(%class.Foo* noundef [[F]]) #[[ATTR3]] +// CHECK-NEXT: call void @_ZN3FooC1Ei(%class.Foo* nonnull align 4 dereferenceable(4) [[F]], i32 1) +// CHECK-NEXT: [[CALL:%.*]] = call i32 @_ZNK3Foo23function_defined_inlineEi(%class.Foo* nonnull align 4 dereferenceable(4) [[F]], i32 2) +// CHECK-NEXT: [[CALL1:%.*]] = call i32 @_ZNK3Foo28function_defined_out_of_lineEi(%class.Foo* nonnull align 4 dereferenceable(4) [[F]], i32 3) +// CHECK-NEXT: call void @_ZN3FooD1Ev(%class.Foo* nonnull align 4 dereferenceable(4) [[F]]) #[[ATTR3]] // CHECK-NEXT: ret i32 0 // int main() { diff --git a/clang/test/utils/update_cc_test_checks/Inputs/def-and-decl.c.expected b/clang/test/utils/update_cc_test_checks/Inputs/def-and-decl.c.expected index 135f3bc28dee43ba0e34bdb41312663ad8e5ca91..855530abe303fdddbc1bd30ded9c2553736cc2e4 100644 --- a/clang/test/utils/update_cc_test_checks/Inputs/def-and-decl.c.expected +++ b/clang/test/utils/update_cc_test_checks/Inputs/def-and-decl.c.expected @@ -11,7 +11,7 @@ void empty_function(void); // CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK-NEXT: store i32 0, i32* [[RETVAL]], align 4 // CHECK-NEXT: call void @empty_function() -// CHECK-NEXT: [[CALL:%.*]] = call i32 @foo(i32 noundef 1) +// CHECK-NEXT: [[CALL:%.*]] = call i32 @foo(i32 1) // CHECK-NEXT: ret i32 [[CALL]] // int main() { diff --git a/clang/test/utils/update_cc_test_checks/Inputs/explicit-template-instantiation.cpp.expected b/clang/test/utils/update_cc_test_checks/Inputs/explicit-template-instantiation.cpp.expected index efc0fac29c4be90a4a10b9da262a33b14daf8beb..fc132c0f7fa794aa20f6dfa5e0ea954679fc27fb 100644 --- a/clang/test/utils/update_cc_test_checks/Inputs/explicit-template-instantiation.cpp.expected +++ b/clang/test/utils/update_cc_test_checks/Inputs/explicit-template-instantiation.cpp.expected @@ -44,7 +44,7 @@ public: // CHECK-NEXT: store i8 [[X:%.*]], i8* [[X_ADDR]], align 1 // CHECK-NEXT: [[THIS1:%.*]] = load %struct.Foo*, %struct.Foo** [[THIS_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[X_ADDR]], align 1 -// CHECK-NEXT: call void @_ZN3FooIcEC2Ec(%struct.Foo* noundef [[THIS1]], i8 noundef signext [[TMP0]]) +// CHECK-NEXT: call void @_ZN3FooIcEC2Ec(%struct.Foo* nonnull align 1 dereferenceable(1) [[THIS1]], i8 signext [[TMP0]]) // CHECK-NEXT: ret void // // CHECK-LABEL: @_ZN3FooIcED1Ev( @@ -52,7 +52,7 @@ public: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Foo*, align 8 // CHECK-NEXT: store %struct.Foo* [[THIS:%.*]], %struct.Foo** [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load %struct.Foo*, %struct.Foo** [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN3FooIcED2Ev(%struct.Foo* noundef [[THIS1]]) #[[ATTR2:[0-9]+]] +// CHECK-NEXT: call void @_ZN3FooIcED2Ev(%struct.Foo* nonnull align 1 dereferenceable(1) [[THIS1]]) #[[ATTR2:[0-9]+]] // CHECK-NEXT: ret void // // CHECK-LABEL: @_ZN3FooIcE3getEv( @@ -86,7 +86,7 @@ template struct Foo; // CHECK-NEXT: store i16 [[X:%.*]], i16* [[X_ADDR]], align 2 // CHECK-NEXT: [[THIS1:%.*]] = load %struct.Foo.0*, %struct.Foo.0** [[THIS_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[X_ADDR]], align 2 -// CHECK-NEXT: call void @_ZN3FooIsEC2Es(%struct.Foo.0* noundef [[THIS1]], i16 noundef signext [[TMP0]]) +// CHECK-NEXT: call void @_ZN3FooIsEC2Es(%struct.Foo.0* nonnull align 2 dereferenceable(2) [[THIS1]], i16 signext [[TMP0]]) // CHECK-NEXT: ret void // // CHECK-LABEL: @_ZN3FooIsED1Ev( @@ -94,7 +94,7 @@ template struct Foo; // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Foo.0*, align 8 // CHECK-NEXT: store %struct.Foo.0* [[THIS:%.*]], %struct.Foo.0** [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load %struct.Foo.0*, %struct.Foo.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN3FooIsED2Ev(%struct.Foo.0* noundef [[THIS1]]) #[[ATTR2]] +// CHECK-NEXT: call void @_ZN3FooIsED2Ev(%struct.Foo.0* nonnull align 2 dereferenceable(2) [[THIS1]]) #[[ATTR2]] // CHECK-NEXT: ret void // // CHECK-LABEL: @_ZN3FooIsE3getEv( @@ -131,7 +131,7 @@ template struct Foo; // CHECK-NEXT: store i32 [[X:%.*]], i32* [[X_ADDR]], align 4 // CHECK-NEXT: [[THIS1:%.*]] = load %struct.Bar*, %struct.Bar** [[THIS_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[X_ADDR]], align 4 -// CHECK-NEXT: call void @_ZN3BarIiEC2Ei(%struct.Bar* noundef [[THIS1]], i32 noundef [[TMP0]]) +// CHECK-NEXT: call void @_ZN3BarIiEC2Ei(%struct.Bar* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) // CHECK-NEXT: ret void // // CHECK-LABEL: @_ZN3BarIiED1Ev( @@ -139,7 +139,7 @@ template struct Foo; // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Bar*, align 8 // CHECK-NEXT: store %struct.Bar* [[THIS:%.*]], %struct.Bar** [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load %struct.Bar*, %struct.Bar** [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN3BarIiED2Ev(%struct.Bar* noundef [[THIS1]]) #[[ATTR2]] +// CHECK-NEXT: call void @_ZN3BarIiED2Ev(%struct.Bar* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK-NEXT: ret void // // CHECK-LABEL: @_ZN3BarIiE3getEv( @@ -148,7 +148,7 @@ template struct Foo; // CHECK-NEXT: store %struct.Bar* [[THIS:%.*]], %struct.Bar** [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load %struct.Bar*, %struct.Bar** [[THIS_ADDR]], align 8 // CHECK-NEXT: [[FOO:%.*]] = getelementptr inbounds [[STRUCT_BAR:%.*]], %struct.Bar* [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN3FooIiE3getEv(%struct.Foo.1* noundef [[FOO]]) +// CHECK-NEXT: [[CALL:%.*]] = call i32 @_ZN3FooIiE3getEv(%struct.Foo.1* nonnull align 4 dereferenceable(4) [[FOO]]) // CHECK-NEXT: ret i32 [[CALL]] // // CHECK-LABEL: @_ZN3BarIiE3setEi( @@ -160,7 +160,7 @@ template struct Foo; // CHECK-NEXT: [[THIS1:%.*]] = load %struct.Bar*, %struct.Bar** [[THIS_ADDR]], align 8 // CHECK-NEXT: [[FOO:%.*]] = getelementptr inbounds [[STRUCT_BAR:%.*]], %struct.Bar* [[THIS1]], i32 0, i32 0 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[_X_ADDR]], align 4 -// CHECK-NEXT: call void @_ZN3FooIiE3setEi(%struct.Foo.1* noundef [[FOO]], i32 noundef [[TMP0]]) +// CHECK-NEXT: call void @_ZN3FooIiE3setEi(%struct.Foo.1* nonnull align 4 dereferenceable(4) [[FOO]], i32 [[TMP0]]) // CHECK-NEXT: ret void // template struct Bar; @@ -176,7 +176,7 @@ template struct Bar; // CHECK-NEXT: store i64 [[X:%.*]], i64* [[X_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load %struct.Baz*, %struct.Baz** [[THIS_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[X_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN3BazIlEC2El(%struct.Baz* noundef [[THIS1]], i64 noundef [[TMP0]]) +// CHECK-NEXT: call void @_ZN3BazIlEC2El(%struct.Baz* nonnull align 8 dereferenceable(8) [[THIS1]], i64 [[TMP0]]) // CHECK-NEXT: ret void // // CHECK-LABEL: @_ZN3BazIlED1Ev( @@ -184,7 +184,7 @@ template struct Bar; // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.Baz*, align 8 // CHECK-NEXT: store %struct.Baz* [[THIS:%.*]], %struct.Baz** [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load %struct.Baz*, %struct.Baz** [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN3BazIlED2Ev(%struct.Baz* noundef [[THIS1]]) #[[ATTR2]] +// CHECK-NEXT: call void @_ZN3BazIlED2Ev(%struct.Baz* nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK-NEXT: ret void // template struct Baz; diff --git a/clang/test/utils/update_cc_test_checks/Inputs/generated-funcs-regex.c.expected b/clang/test/utils/update_cc_test_checks/Inputs/generated-funcs-regex.c.expected index 3c0346428d84a8d306c5f1f613c00d96ea958ed6..03e0f8ef60e0712a623fed669c94939a072540e0 100644 --- a/clang/test/utils/update_cc_test_checks/Inputs/generated-funcs-regex.c.expected +++ b/clang/test/utils/update_cc_test_checks/Inputs/generated-funcs-regex.c.expected @@ -33,6 +33,6 @@ void foo(int a) // CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 // CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 -// CHECK-NEXT: call void @use(i32 noundef [[TMP0]]) +// CHECK-NEXT: call void @use(i32 [[TMP0]]) // CHECK-NEXT: ret void // diff --git a/clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.funcsig.expected b/clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.funcsig.expected index 8a02c847a769a30cd6924b5af0a6ea56f449b589..2c29eb18db6ff6c988d35ddfeda8ea5b9e6ffa40 100644 --- a/clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.funcsig.expected +++ b/clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.funcsig.expected @@ -3,7 +3,7 @@ // RUN: %clang_cc1 -triple=x86_64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s // CHECK-LABEL: define {{[^@]+}}@test -// CHECK-SAME: (i64 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-SAME: (i64 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 @@ -21,7 +21,7 @@ long test(long a, int b) { // A function with a mangled name // CHECK-LABEL: define {{[^@]+}}@_Z4testlii -// CHECK-SAME: (i64 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[C:%.*]]) #[[ATTR0]] { +// CHECK-SAME: (i64 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 diff --git a/clang/test/utils/update_cc_test_checks/Inputs/resolve-tmp-conflict.cpp.expected b/clang/test/utils/update_cc_test_checks/Inputs/resolve-tmp-conflict.cpp.expected index 3901d2458abad35e82cad08241f63c272007cab2..9a3c4580f4c1b44d5f339319fa8b66cfee09b585 100644 --- a/clang/test/utils/update_cc_test_checks/Inputs/resolve-tmp-conflict.cpp.expected +++ b/clang/test/utils/update_cc_test_checks/Inputs/resolve-tmp-conflict.cpp.expected @@ -2,7 +2,7 @@ // RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s // CHECK-LABEL: define {{[^@]+}}@_Z3fooi -// CHECK-SAME: (i32 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[_TMP0:%.*]] = alloca i32*, align 8 diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index 0d8b2009baab57511f71f08219e22f34ad9e2a3c..462406db6a751cc10b196e06043ae273d2e37e3e 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -80,7 +80,7 @@ public: // passing to the BUILTIN() macro in Builtins.def. const std::string &getBuiltinStr() const { return BuiltinStr; } - // Return the clang buitlin type for RVV vector type which are used in the + // Return the clang builtin type for RVV vector type which are used in the // riscv_vector.h header file. const std::string &getClangBuiltinStr() const { return ClangBuiltinStr; } @@ -155,7 +155,6 @@ private: std::string IRName; bool HasSideEffects; bool IsMask; - bool HasMaskedOffOperand; bool HasVL; bool HasPolicy; bool HasNoMaskedOverloaded; @@ -182,7 +181,6 @@ public: StringRef getName() const { return Name; } StringRef getMangledName() const { return MangledName; } bool hasSideEffects() const { return HasSideEffects; } - bool hasMaskedOffOperand() const { return HasMaskedOffOperand; } bool hasVL() const { return HasVL; } bool hasPolicy() const { return HasPolicy; } bool hasNoMaskedOverloaded() const { return HasNoMaskedOverloaded; } @@ -766,9 +764,9 @@ RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix, const std::vector &NewIntrinsicTypes, StringRef RequiredExtension, unsigned NF) : IRName(IRName), HasSideEffects(HasSideEffects), IsMask(IsMask), - HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL), - HasPolicy(HasPolicy), HasNoMaskedOverloaded(HasNoMaskedOverloaded), - HasAutoDef(HasAutoDef), ManualCodegen(ManualCodegen.str()), NF(NF) { + HasVL(HasVL), HasPolicy(HasPolicy), + HasNoMaskedOverloaded(HasNoMaskedOverloaded), HasAutoDef(HasAutoDef), + ManualCodegen(ManualCodegen.str()), NF(NF) { // Init Name and MangledName Name = NewName.str(); diff --git a/cmake/Modules/HandleCompilerRT.cmake b/cmake/Modules/HandleCompilerRT.cmake new file mode 100644 index 0000000000000000000000000000000000000000..00661d102c2a402e814ca1a84ee3bc5e3bf99c2c --- /dev/null +++ b/cmake/Modules/HandleCompilerRT.cmake @@ -0,0 +1,101 @@ +# Check if compile-rt library file path exists. +# If found, cache the path in: +# COMPILER_RT_LIBRARY-- +# If err_flag is true OR path not found, emit a message and set: +# COMPILER_RT_LIBRARY-- to NOTFOUND +function(cache_compiler_rt_library err_flag name target library_file) + if(err_flag OR NOT EXISTS "${library_file}") + message(STATUS "Failed to find compiler-rt ${name} library for ${target}") + set(COMPILER_RT_LIBRARY_${name}_${target} "NOTFOUND" CACHE INTERNAL + "compiler-rt ${name} library for ${target}") + else() + message(STATUS "Found compiler-rt ${name} library: ${library_file}") + set(COMPILER_RT_LIBRARY_${name}_${target} "${library_file}" CACHE INTERNAL + "compiler-rt ${name} library for ${target}") + endif() +endfunction() + +function(get_component_name name variable) + if(APPLE) + if(NOT name MATCHES "builtins.*") + set(component_name "${name}_") + endif() + # TODO: Support ios, tvos and watchos as well. + set(component_name "${component_name}osx") + else() + set(component_name "${name}") + endif() + set(${variable} "${component_name}" PARENT_SCOPE) +endfunction() + +# Find the path to compiler-rt library `name` (e.g. "builtins") for the +# specified `TARGET` (e.g. "x86_64-linux-gnu") and return it in `variable`. +# This calls cache_compiler_rt_library that caches the path to speed up +# repeated invocations with the same `name` and `target`. +function(find_compiler_rt_library name variable) + cmake_parse_arguments(ARG "" "TARGET" "" ${ARGN}) + # While we can use compiler-rt runtimes with other compilers, we need to + # query the compiler for runtime location and thus we require Clang. + if(NOT CMAKE_CXX_COMPILER_ID MATCHES Clang) + set(${variable} "NOTFOUND" PARENT_SCOPE) + return() + endif() + set(target "${ARG_TARGET}") + if(NOT target AND CMAKE_CXX_COMPILER_TARGET) + set(target "${CMAKE_CXX_COMPILER_TARGET}") + endif() + if(NOT DEFINED COMPILER_RT_LIBRARY_builtins_${target}) + # If the cache variable is not defined, invoke Clang and then + # set it with cache_compiler_rt_library. + set(clang_command ${CMAKE_CXX_COMPILER} ${CMAKE_REQUIRED_FLAGS}) + if(target) + list(APPEND clang_command "--target=${target}") + endif() + get_property(cxx_flags CACHE CMAKE_CXX_FLAGS PROPERTY VALUE) + string(REPLACE " " ";" cxx_flags "${cxx_flags}") + list(APPEND clang_command ${cxx_flags}) + execute_process( + COMMAND ${clang_command} "--rtlib=compiler-rt" "-print-libgcc-file-name" + RESULT_VARIABLE had_error + OUTPUT_VARIABLE library_file + ) + string(STRIP "${library_file}" library_file) + file(TO_CMAKE_PATH "${library_file}" library_file) + get_filename_component(dirname ${library_file} DIRECTORY) + if(APPLE) + execute_process( + COMMAND ${clang_command} "--print-resource-dir" + RESULT_VARIABLE had_error + OUTPUT_VARIABLE resource_dir + ) + string(STRIP "${resource_dir}" resource_dir) + set(dirname "${resource_dir}/lib/darwin") + endif() + get_filename_component(basename ${library_file} NAME) + if(basename MATCHES "libclang_rt\.([a-z0-9_\-]+)\.a") + set(from_name ${CMAKE_MATCH_1}) + get_component_name(${CMAKE_MATCH_1} to_name) + string(REPLACE "${from_name}" "${to_name}" basename "${basename}") + set(library_file "${dirname}/${basename}") + cache_compiler_rt_library(${had_error} builtins "${target}" "${library_file}") + endif() + endif() + if(NOT COMPILER_RT_LIBRARY_builtins_${target}) + set(${variable} "NOTFOUND" PARENT_SCOPE) + return() + endif() + if(NOT DEFINED COMPILER_RT_LIBRARY_${name}_${target}) + # Clang gives only the builtins library path. Other library paths are + # obtained by substituting "builtins" with ${name} in the builtins + # path and then checking if the resultant path exists. The result of + # this check is also cached by cache_compiler_rt_library. + set(library_file "${COMPILER_RT_LIBRARY_builtins_${target}}") + if(library_file MATCHES ".*libclang_rt\.([a-z0-9_\-]+)\.a") + set(from_name ${CMAKE_MATCH_0}) + get_component_name(${name} to_name) + string(REPLACE "${from_name}" "${to_name}" library_file "${library_file}") + cache_compiler_rt_library(FALSE "${name}" "${target}" "${library_file}") + endif() + endif() + set(${variable} "${COMPILER_RT_LIBRARY_${name}_${target}}" PARENT_SCOPE) +endfunction() diff --git a/compiler-rt/CMakeLists.txt b/compiler-rt/CMakeLists.txt index aa14ceff495a0904482cd5ccda9cf8e90ece546c..17d7e4ffbdebf3fa3ea747514675e5afdf80e7b3 100644 --- a/compiler-rt/CMakeLists.txt +++ b/compiler-rt/CMakeLists.txt @@ -16,6 +16,8 @@ endif() list(INSERT CMAKE_MODULE_PATH 0 "${CMAKE_CURRENT_SOURCE_DIR}/cmake" "${CMAKE_CURRENT_SOURCE_DIR}/cmake/Modules" + "${CMAKE_CURRENT_SOURCE_DIR}/../cmake" + "${CMAKE_CURRENT_SOURCE_DIR}/../cmake/Modules" ) if(CMAKE_CONFIGURATION_TYPES) diff --git a/compiler-rt/cmake/Modules/AddCompilerRT.cmake b/compiler-rt/cmake/Modules/AddCompilerRT.cmake index 8b620786730b50a50c74d2ed1457246f58d04def..76e015368f5db6e3945f2ff0890fa8bb50891431 100644 --- a/compiler-rt/cmake/Modules/AddCompilerRT.cmake +++ b/compiler-rt/cmake/Modules/AddCompilerRT.cmake @@ -254,7 +254,7 @@ function(add_compiler_rt_runtime name type) if(COMPILER_RT_USE_BUILTINS_LIBRARY AND NOT type STREQUAL "OBJECT" AND NOT name STREQUAL "clang_rt.builtins") get_compiler_rt_target(${arch} target) - find_compiler_rt_library(builtins ${target} builtins_${libname}) + find_compiler_rt_library(builtins builtins_${libname} TARGET ${target}) if(builtins_${libname} STREQUAL "NOTFOUND") message(FATAL_ERROR "Cannot find builtins library for the target architecture") endif() diff --git a/compiler-rt/cmake/Modules/HandleCompilerRT.cmake b/compiler-rt/cmake/Modules/HandleCompilerRT.cmake deleted file mode 100644 index ac9e0871489da04030cd413fd95a99889109d8f8..0000000000000000000000000000000000000000 --- a/compiler-rt/cmake/Modules/HandleCompilerRT.cmake +++ /dev/null @@ -1,65 +0,0 @@ -# Check if compile-rt library file path exists. -# If found, cache the path in: -# COMPILER_RT_LIBRARY-- -# If err_flag is true OR path not found, emit a message and set: -# COMPILER_RT_LIBRARY-- to NOTFOUND -function(cache_compiler_rt_library err_flag name target library_file) - if(err_flag OR NOT EXISTS "${library_file}") - message(STATUS "Failed to find compiler-rt ${name} library for ${target}") - set(COMPILER_RT_LIBRARY-${name}-${target} "NOTFOUND" CACHE INTERNAL - "compiler-rt ${name} library for ${target}") - else() - message(STATUS "Found compiler-rt ${name} library: ${library_file}") - set(COMPILER_RT_LIBRARY-${name}-${target} "${library_file}" CACHE INTERNAL - "compiler-rt ${name} library for ${target}") - endif() -endfunction() - -# Find the path to compiler-rt library `name` (e.g. "builtins") for -# the specified `target` (e.g. "x86_64-linux") and return it in `variable`. -# This calls cache_compiler_rt_library that caches the path to speed up -# repeated invocations with the same `name` and `target`. -function(find_compiler_rt_library name target variable) - if(NOT CMAKE_CXX_COMPILER_ID MATCHES Clang) - set(${variable} "NOTFOUND" PARENT_SCOPE) - return() - endif() - if (NOT target AND CMAKE_CXX_COMPILER_TARGET) - set(target "${CMAKE_CXX_COMPILER_TARGET}") - endif() - if(NOT DEFINED COMPILER_RT_LIBRARY-builtins-${target}) - # If the cache variable is not defined, invoke clang and then - # set it with cache_compiler_rt_library. - set(CLANG_COMMAND ${CMAKE_CXX_COMPILER} ${SANITIZER_COMMON_FLAGS} - "--rtlib=compiler-rt" "-print-libgcc-file-name") - if(target) - list(APPEND CLANG_COMMAND "--target=${target}") - endif() - get_property(SANITIZER_CXX_FLAGS CACHE CMAKE_CXX_FLAGS PROPERTY VALUE) - string(REPLACE " " ";" SANITIZER_CXX_FLAGS "${SANITIZER_CXX_FLAGS}") - list(APPEND CLANG_COMMAND ${SANITIZER_CXX_FLAGS}) - execute_process( - COMMAND ${CLANG_COMMAND} - RESULT_VARIABLE HAD_ERROR - OUTPUT_VARIABLE LIBRARY_FILE - ) - string(STRIP "${LIBRARY_FILE}" LIBRARY_FILE) - file(TO_CMAKE_PATH "${LIBRARY_FILE}" LIBRARY_FILE) - cache_compiler_rt_library(${HAD_ERROR} - builtins "${target}" "${LIBRARY_FILE}") - endif() - if(NOT COMPILER_RT_LIBRARY-builtins-${target}) - set(${variable} "NOTFOUND" PARENT_SCOPE) - return() - endif() - if(NOT DEFINED COMPILER_RT_LIBRARY-${name}-${target}) - # clang gives only the builtins library path. Other library paths are - # obtained by substituting "builtins" with ${name} in the builtins - # path and then checking if the resultant path exists. The result of - # this check is also cached by cache_compiler_rt_library. - set(LIBRARY_FILE "${COMPILER_RT_LIBRARY-builtins-${target}}") - string(REPLACE "builtins" "${name}" LIBRARY_FILE "${LIBRARY_FILE}") - cache_compiler_rt_library(FALSE "${name}" "${target}" "${LIBRARY_FILE}") - endif() - set(${variable} "${COMPILER_RT_LIBRARY-${name}-${target}}" PARENT_SCOPE) -endfunction() diff --git a/compiler-rt/cmake/config-ix.cmake b/compiler-rt/cmake/config-ix.cmake index 62685f5d6c33114ab8abc96044c1fa885b48f99e..e2985dccc645fc66513e5890f1342d225fa32903 100644 --- a/compiler-rt/cmake/config-ix.cmake +++ b/compiler-rt/cmake/config-ix.cmake @@ -16,7 +16,10 @@ endfunction() check_library_exists(c fopen "" COMPILER_RT_HAS_LIBC) if (COMPILER_RT_USE_BUILTINS_LIBRARY) include(HandleCompilerRT) - find_compiler_rt_library(builtins "" COMPILER_RT_BUILTINS_LIBRARY) + cmake_push_check_state() + set(CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS} ${SANITIZER_COMMON_FLAGS}") + find_compiler_rt_library(builtins COMPILER_RT_BUILTINS_LIBRARY) + cmake_pop_check_state() # TODO(PR51389): We should check COMPILER_RT_BUILTINS_LIBRARY and report an # error if the value is NOTFOUND rather than silenty continuing but we first # need to fix find_compiler_rt_library on Darwin. diff --git a/compiler-rt/lib/builtins/CMakeLists.txt b/compiler-rt/lib/builtins/CMakeLists.txt index 116517ca9e7dd8e5613fb4e55b3af0d24f96ed7d..971e94407a2c94c0ee47a21dd9e606875d0c3d1a 100644 --- a/compiler-rt/lib/builtins/CMakeLists.txt +++ b/compiler-rt/lib/builtins/CMakeLists.txt @@ -11,7 +11,9 @@ if (CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) set(COMPILER_RT_BUILTINS_STANDALONE_BUILD TRUE) list(INSERT CMAKE_MODULE_PATH 0 "${CMAKE_SOURCE_DIR}/../../cmake" - "${CMAKE_SOURCE_DIR}/../../cmake/Modules") + "${CMAKE_SOURCE_DIR}/../../cmake/Modules" + "${CMAKE_SOURCE_DIR}/../../../cmake" + "${CMAKE_SOURCE_DIR}/../../../cmake/Modules") include(base-config-ix) include(CompilerRTUtils) diff --git a/flang/include/flang/Evaluate/type.h b/flang/include/flang/Evaluate/type.h index dcc052769b78614cea4e41d620590471d62e6d70..c413e24cf3190a2b45ce84a834e966bb10f63f6f 100644 --- a/flang/include/flang/Evaluate/type.h +++ b/flang/include/flang/Evaluate/type.h @@ -50,6 +50,7 @@ template class Type; using SubscriptInteger = Type; using CInteger = Type; +using LargestInt = Type; using LogicalResult = Type; using LargestReal = Type; using Ascii = Type; diff --git a/flang/lib/Evaluate/fold-logical.cpp b/flang/lib/Evaluate/fold-logical.cpp index 586909d3ecf83ecc63d082a0ff60661f0eb5fa74..62bc37282fe781431274b93d1a2cc2a35acf5e0f 100644 --- a/flang/lib/Evaluate/fold-logical.cpp +++ b/flang/lib/Evaluate/fold-logical.cpp @@ -40,6 +40,7 @@ Expr> FoldIntrinsicFunction( auto *intrinsic{std::get_if(&funcRef.proc().u)}; CHECK(intrinsic); std::string name{intrinsic->name}; + using SameInt = Type; if (name == "all") { return FoldAllAny( context, std::move(funcRef), &Scalar::AND, Scalar{true}); @@ -59,7 +60,6 @@ Expr> FoldIntrinsicFunction( } return gotConstant ? Expr{false} : Expr{std::move(funcRef)}; } else if (name == "bge" || name == "bgt" || name == "ble" || name == "blt") { - using LargestInt = Type; static_assert(std::is_same_v, BOZLiteralConstant>); // Arguments do not have to be of the same integer type. Convert all // arguments to the biggest integer type before comparing them to @@ -89,6 +89,26 @@ Expr> FoldIntrinsicFunction( [&fptr](const Scalar &i, const Scalar &j) { return Scalar{std::invoke(fptr, i, j)}; })); + } else if (name == "btest") { + if (const auto *ix{UnwrapExpr>(args[0])}) { + return std::visit( + [&](const auto &x) { + using IT = ResultType; + return FoldElementalIntrinsic(context, + std::move(funcRef), + ScalarFunc( + [&](const Scalar &x, const Scalar &pos) { + auto posVal{pos.ToInt64()}; + if (posVal < 0 || posVal >= x.bits) { + context.messages().Say( + "POS=%jd out of range for BTEST"_err_en_US, + static_cast(posVal)); + } + return Scalar{x.BTEST(posVal)}; + })); + }, + ix->u); + } } else if (name == "isnan" || name == "__builtin_ieee_is_nan") { // A warning about an invalid argument is discarded from converting // the argument of isnan() / IEEE_IS_NAN(). @@ -139,7 +159,7 @@ Expr> FoldIntrinsicFunction( name == "__builtin_ieee_support_underflow_control") { return Expr{true}; } - // TODO: btest, dot_product, is_iostat_end, + // TODO: dot_product, is_iostat_end, // is_iostat_eor, logical, matmul, out_of_range, // parity, transfer return Expr{std::move(funcRef)}; diff --git a/flang/test/Evaluate/fold-btest.f90 b/flang/test/Evaluate/fold-btest.f90 new file mode 100644 index 0000000000000000000000000000000000000000..e346dd0c65fac552a8371ecd3436769af98c2aeb --- /dev/null +++ b/flang/test/Evaluate/fold-btest.f90 @@ -0,0 +1,21 @@ +! RUN: %python %S/test_folding.py %s %flang_fc1 +! Tests folding of BTEST +module m1 + integer, parameter :: ia1(*) = [(j, j=0, 15)] + logical, parameter :: test_ia1a = all(btest(ia1, 0) .eqv. [(.false., .true., j=1, 8)]) + logical, parameter :: test_ia1b = all(btest(ia1, 1) .eqv. [(.false., .false., .true., .true., j=1, 4)]) + logical, parameter :: test_ia1c = all(btest(ia1, 2) .eqv. [(modulo(j/4, 2) == 1, j=0, 15)]) + logical, parameter :: test_ia1d = all(btest(ia1, 3) .eqv. [(j > 8, j=1, 16)]) + logical, parameter :: test_shft1 = all([(btest(ishft(1_1, j), j), j=0, 7)]) + logical, parameter :: test_shft2 = all([(btest(ishft(1_2, j), j), j=0, 15)]) + logical, parameter :: test_shft4 = all([(btest(ishft(1_4, j), j), j=0, 31)]) + logical, parameter :: test_shft8 = all([(btest(ishft(1_8, j), j), j=0, 63)]) + logical, parameter :: test_shft16 = all([(btest(ishft(1_16, j), j), j=0, 127)]) + logical, parameter :: test_set1 = all([(btest(ibset(0_1, j), j), j=0, 7)]) + logical, parameter :: test_set2 = all([(btest(ibset(0_2, j), j), j=0, 15)]) + logical, parameter :: test_set4 = all([(btest(ibset(0_4, j), j), j=0, 31)]) + logical, parameter :: test_set8 = all([(btest(ibset(0_8, j), j), j=0, 63)]) + logical, parameter :: test_set16 = all([(btest(ibset(0_16, j), j), j=0, 127)]) + logical, parameter :: test_z = .not. any([(btest(0_4, j), j=0, 31)]) + logical, parameter :: test_shft1e = all(btest([(ishft(1_1, j), j=0, 7)], [(j, j=0, 7)])) +end module diff --git a/flang/test/Evaluate/folding19.f90 b/flang/test/Evaluate/folding19.f90 index 8cfaeb155a150bb397ffa8962f8f4e470f7d46bb..cbd6d2082b52a0a631be12c5b5fe0ef0922d858a 100644 --- a/flang/test/Evaluate/folding19.f90 +++ b/flang/test/Evaluate/folding19.f90 @@ -50,4 +50,14 @@ module m !CHECK: error: Invalid 'vector=' argument in UNPACK: the 'mask=' argument has 3 true elements, but the vector has only 2 elements x = unpack([1,2], mask, 0) end subroutine + subroutine s6 + !CHECK: error: POS=-1 out of range for BTEST + logical, parameter :: bad1 = btest(0, -1) + !CHECK: error: POS=32 out of range for BTEST + logical, parameter :: bad2 = btest(0, 32) + !CHECK-NOT: error: POS=33 out of range for BTEST + logical, parameter :: bad3 = btest(0_8, 33) + !CHECK: error: POS=64 out of range for BTEST + logical, parameter :: bad4 = btest(0_8, 64) + end subroutine end module diff --git a/libc/config/linux/x86_64/entrypoints.txt b/libc/config/linux/x86_64/entrypoints.txt index 1f40545cde3f14c95c86b8c618ac6c790f1f7427..9ea7928faef2c0d557496dd435f673a5965851a0 100644 --- a/libc/config/linux/x86_64/entrypoints.txt +++ b/libc/config/linux/x86_64/entrypoints.txt @@ -56,6 +56,7 @@ set(TARGET_LIBC_ENTRYPOINTS # stdlib.h entrypoints libc.src.stdlib.abs libc.src.stdlib.atoi + libc.src.stdlib.atof libc.src.stdlib.atol libc.src.stdlib.atoll libc.src.stdlib.bsearch @@ -65,6 +66,8 @@ set(TARGET_LIBC_ENTRYPOINTS libc.src.stdlib.llabs libc.src.stdlib.lldiv libc.src.stdlib.qsort + libc.src.stdlib.strtod + libc.src.stdlib.strtof libc.src.stdlib.strtol libc.src.stdlib.strtoll libc.src.stdlib.strtoul diff --git a/libc/fuzzing/stdlib/CMakeLists.txt b/libc/fuzzing/stdlib/CMakeLists.txt index db827f57075f2a8cbe77980a8831e07a5e236e12..436125b6cd7adaf7ac64273011539b45bad592a8 100644 --- a/libc/fuzzing/stdlib/CMakeLists.txt +++ b/libc/fuzzing/stdlib/CMakeLists.txt @@ -6,3 +6,13 @@ add_libc_fuzzer( libc.src.stdlib.qsort ) +add_libc_fuzzer( + atof_fuzz + SRCS + atof_fuzz.cpp + HDRS + StringParserOutputDiff.h + DEPENDS + libc.src.stdlib.atof +) + diff --git a/libc/fuzzing/stdlib/StringParserOutputDiff.h b/libc/fuzzing/stdlib/StringParserOutputDiff.h new file mode 100644 index 0000000000000000000000000000000000000000..457da3b5674ba87894b7c902fade89d55e4efa15 --- /dev/null +++ b/libc/fuzzing/stdlib/StringParserOutputDiff.h @@ -0,0 +1,35 @@ +//===-- Template to diff single-input-single-output functions ---*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_FUZZING_STDLIB_STRING_PARSER_OUTPUT_DIFF_H +#define LLVM_LIBC_FUZZING_STDLIB_STRING_PARSER_OUTPUT_DIFF_H + +#include "fuzzing/math/Compare.h" + +#include +#include + +template using StringInputSingleOutputFunc = T (*)(const char *); + +template +void StringParserOutputDiff(StringInputSingleOutputFunc func1, + StringInputSingleOutputFunc func2, + const uint8_t *data, size_t size) { + if (size < sizeof(T)) + return; + + const char *x = reinterpret_cast(data); + + T result1 = func1(x); + T result2 = func2(x); + + if (!ValuesEqual(result1, result2)) + __builtin_trap(); +} + +#endif // LLVM_LIBC_FUZZING_STDLIB_STRING_PARSER_OUTPUT_DIFF_H diff --git a/libc/fuzzing/stdlib/atof_fuzz.cpp b/libc/fuzzing/stdlib/atof_fuzz.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b368129960d3b590db64e25d991d6979f7d409c4 --- /dev/null +++ b/libc/fuzzing/stdlib/atof_fuzz.cpp @@ -0,0 +1,32 @@ +//===-- atof_fuzz.cpp -----------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// Fuzzing test for llvm-libc atof implementation. +/// +//===----------------------------------------------------------------------===// +#include "src/stdlib/atof.h" +#include +#include +#include + +#include "fuzzing/stdlib/StringParserOutputDiff.h" + +extern "C" int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size) { + uint8_t *container = new uint8_t[size + 1]; + if (!container) + __builtin_trap(); + size_t i; + + for (i = 0; i < size; ++i) + container[i] = data[i]; + container[size] = '\0'; // Add null terminator to container. + + StringParserOutputDiff(&__llvm_libc::atof, &::atof, container, size); + delete[] container; + return 0; +} diff --git a/libc/spec/stdc.td b/libc/spec/stdc.td index dd5ac0a357f90da0eb6ef56dc674d7aa3bb41d59..4643154fdd8c09fa9973d6e8079cb67594f6d9b7 100644 --- a/libc/spec/stdc.td +++ b/libc/spec/stdc.td @@ -495,6 +495,7 @@ def StdC : StandardSpec<"stdc"> { FunctionSpec<"labs", RetValSpec, [ArgSpec]>, FunctionSpec<"llabs", RetValSpec, [ArgSpec]>, + FunctionSpec<"atof", RetValSpec, [ArgSpec]>, FunctionSpec<"atoi", RetValSpec, [ArgSpec]>, FunctionSpec<"atol", RetValSpec, [ArgSpec]>, FunctionSpec<"atoll", RetValSpec, [ArgSpec]>, @@ -505,6 +506,8 @@ def StdC : StandardSpec<"stdc"> { FunctionSpec<"qsort", RetValSpec, [ArgSpec, ArgSpec, ArgSpec, ArgSpec]>, + FunctionSpec<"strtod", RetValSpec, [ArgSpec, ArgSpec]>, + FunctionSpec<"strtof", RetValSpec, [ArgSpec, ArgSpec]>, FunctionSpec<"strtol", RetValSpec, [ArgSpec, ArgSpec, ArgSpec]>, FunctionSpec<"strtoll", RetValSpec, [ArgSpec, ArgSpec, ArgSpec]>, FunctionSpec<"strtoul", RetValSpec, [ArgSpec, ArgSpec, ArgSpec]>, diff --git a/libc/src/__support/CMakeLists.txt b/libc/src/__support/CMakeLists.txt index 2699b552bfa65ed6f4f14d79c74db5bf50f4bd9f..1d452067f93d18eb8dfc842a39c01de3dafffec8 100644 --- a/libc/src/__support/CMakeLists.txt +++ b/libc/src/__support/CMakeLists.txt @@ -23,12 +23,14 @@ add_header_library( str_conv_utils HDRS str_conv_utils.h + str_to_float.h DEPENDS .ctype_utils .high_precision_decimal libc.include.errno libc.src.errno.__errno_location libc.utils.CPP.standalone_cpp + libc.src.__support.FPUtil.fputil ) add_header_library( diff --git a/libc/src/__support/detailed_powers_of_ten.h b/libc/src/__support/detailed_powers_of_ten.h new file mode 100644 index 0000000000000000000000000000000000000000..e168b95b8998eb36fba8dc02715971684fcb47f2 --- /dev/null +++ b/libc/src/__support/detailed_powers_of_ten.h @@ -0,0 +1,736 @@ +//===-- detailed powers of ten ----------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LIBC_SRC_SUPPORT_DETAILED_POWERS_OF_TEN_H +#define LIBC_SRC_SUPPORT_DETAILED_POWERS_OF_TEN_H + +#include + +namespace __llvm_libc { +namespace internal { + +// TODO(michaelrj): write a script that will generate this table. + +// This table was generated by +// https://github.com/google/wuffs/blob/788479dd64f35cb6b4e998a851acb06ee962435b/script/print-mpb-powers-of-10.go +// and contains the 128 bit mantissa approximations of the powers of 10 from +// -348 to 347. The exponents are implied by a linear expression with slope +// 217706.0/65536.0 ≈ log(10)/log(2). This is used by the Eisel-Lemire algorithm +// in str_conv_utils.h. + +constexpr int32_t DETAILED_POWERS_OF_TEN_MIN_EXP_10 = -348; +constexpr int32_t DETAILED_POWERS_OF_TEN_MAX_EXP_10 = 347; + +// This rescales the base 10 exponent by a factor of log(10)/log(2). +static inline int64_t exp10ToExp2(int64_t exp10) { + return (217706 * exp10) >> 16; +} + +static const uint64_t DETAILED_POWERS_OF_TEN[696][2] = { + {0x1732C869CD60E453, 0xFA8FD5A0081C0288}, // 1e-348 + {0x0E7FBD42205C8EB4, 0x9C99E58405118195}, // 1e-347 + {0x521FAC92A873B261, 0xC3C05EE50655E1FA}, // 1e-346 + {0xE6A797B752909EF9, 0xF4B0769E47EB5A78}, // 1e-345 + {0x9028BED2939A635C, 0x98EE4A22ECF3188B}, // 1e-344 + {0x7432EE873880FC33, 0xBF29DCABA82FDEAE}, // 1e-343 + {0x113FAA2906A13B3F, 0xEEF453D6923BD65A}, // 1e-342 + {0x4AC7CA59A424C507, 0x9558B4661B6565F8}, // 1e-341 + {0x5D79BCF00D2DF649, 0xBAAEE17FA23EBF76}, // 1e-340 + {0xF4D82C2C107973DC, 0xE95A99DF8ACE6F53}, // 1e-339 + {0x79071B9B8A4BE869, 0x91D8A02BB6C10594}, // 1e-338 + {0x9748E2826CDEE284, 0xB64EC836A47146F9}, // 1e-337 + {0xFD1B1B2308169B25, 0xE3E27A444D8D98B7}, // 1e-336 + {0xFE30F0F5E50E20F7, 0x8E6D8C6AB0787F72}, // 1e-335 + {0xBDBD2D335E51A935, 0xB208EF855C969F4F}, // 1e-334 + {0xAD2C788035E61382, 0xDE8B2B66B3BC4723}, // 1e-333 + {0x4C3BCB5021AFCC31, 0x8B16FB203055AC76}, // 1e-332 + {0xDF4ABE242A1BBF3D, 0xADDCB9E83C6B1793}, // 1e-331 + {0xD71D6DAD34A2AF0D, 0xD953E8624B85DD78}, // 1e-330 + {0x8672648C40E5AD68, 0x87D4713D6F33AA6B}, // 1e-329 + {0x680EFDAF511F18C2, 0xA9C98D8CCB009506}, // 1e-328 + {0x0212BD1B2566DEF2, 0xD43BF0EFFDC0BA48}, // 1e-327 + {0x014BB630F7604B57, 0x84A57695FE98746D}, // 1e-326 + {0x419EA3BD35385E2D, 0xA5CED43B7E3E9188}, // 1e-325 + {0x52064CAC828675B9, 0xCF42894A5DCE35EA}, // 1e-324 + {0x7343EFEBD1940993, 0x818995CE7AA0E1B2}, // 1e-323 + {0x1014EBE6C5F90BF8, 0xA1EBFB4219491A1F}, // 1e-322 + {0xD41A26E077774EF6, 0xCA66FA129F9B60A6}, // 1e-321 + {0x8920B098955522B4, 0xFD00B897478238D0}, // 1e-320 + {0x55B46E5F5D5535B0, 0x9E20735E8CB16382}, // 1e-319 + {0xEB2189F734AA831D, 0xC5A890362FDDBC62}, // 1e-318 + {0xA5E9EC7501D523E4, 0xF712B443BBD52B7B}, // 1e-317 + {0x47B233C92125366E, 0x9A6BB0AA55653B2D}, // 1e-316 + {0x999EC0BB696E840A, 0xC1069CD4EABE89F8}, // 1e-315 + {0xC00670EA43CA250D, 0xF148440A256E2C76}, // 1e-314 + {0x380406926A5E5728, 0x96CD2A865764DBCA}, // 1e-313 + {0xC605083704F5ECF2, 0xBC807527ED3E12BC}, // 1e-312 + {0xF7864A44C633682E, 0xEBA09271E88D976B}, // 1e-311 + {0x7AB3EE6AFBE0211D, 0x93445B8731587EA3}, // 1e-310 + {0x5960EA05BAD82964, 0xB8157268FDAE9E4C}, // 1e-309 + {0x6FB92487298E33BD, 0xE61ACF033D1A45DF}, // 1e-308 + {0xA5D3B6D479F8E056, 0x8FD0C16206306BAB}, // 1e-307 + {0x8F48A4899877186C, 0xB3C4F1BA87BC8696}, // 1e-306 + {0x331ACDABFE94DE87, 0xE0B62E2929ABA83C}, // 1e-305 + {0x9FF0C08B7F1D0B14, 0x8C71DCD9BA0B4925}, // 1e-304 + {0x07ECF0AE5EE44DD9, 0xAF8E5410288E1B6F}, // 1e-303 + {0xC9E82CD9F69D6150, 0xDB71E91432B1A24A}, // 1e-302 + {0xBE311C083A225CD2, 0x892731AC9FAF056E}, // 1e-301 + {0x6DBD630A48AAF406, 0xAB70FE17C79AC6CA}, // 1e-300 + {0x092CBBCCDAD5B108, 0xD64D3D9DB981787D}, // 1e-299 + {0x25BBF56008C58EA5, 0x85F0468293F0EB4E}, // 1e-298 + {0xAF2AF2B80AF6F24E, 0xA76C582338ED2621}, // 1e-297 + {0x1AF5AF660DB4AEE1, 0xD1476E2C07286FAA}, // 1e-296 + {0x50D98D9FC890ED4D, 0x82CCA4DB847945CA}, // 1e-295 + {0xE50FF107BAB528A0, 0xA37FCE126597973C}, // 1e-294 + {0x1E53ED49A96272C8, 0xCC5FC196FEFD7D0C}, // 1e-293 + {0x25E8E89C13BB0F7A, 0xFF77B1FCBEBCDC4F}, // 1e-292 + {0x77B191618C54E9AC, 0x9FAACF3DF73609B1}, // 1e-291 + {0xD59DF5B9EF6A2417, 0xC795830D75038C1D}, // 1e-290 + {0x4B0573286B44AD1D, 0xF97AE3D0D2446F25}, // 1e-289 + {0x4EE367F9430AEC32, 0x9BECCE62836AC577}, // 1e-288 + {0x229C41F793CDA73F, 0xC2E801FB244576D5}, // 1e-287 + {0x6B43527578C1110F, 0xF3A20279ED56D48A}, // 1e-286 + {0x830A13896B78AAA9, 0x9845418C345644D6}, // 1e-285 + {0x23CC986BC656D553, 0xBE5691EF416BD60C}, // 1e-284 + {0x2CBFBE86B7EC8AA8, 0xEDEC366B11C6CB8F}, // 1e-283 + {0x7BF7D71432F3D6A9, 0x94B3A202EB1C3F39}, // 1e-282 + {0xDAF5CCD93FB0CC53, 0xB9E08A83A5E34F07}, // 1e-281 + {0xD1B3400F8F9CFF68, 0xE858AD248F5C22C9}, // 1e-280 + {0x23100809B9C21FA1, 0x91376C36D99995BE}, // 1e-279 + {0xABD40A0C2832A78A, 0xB58547448FFFFB2D}, // 1e-278 + {0x16C90C8F323F516C, 0xE2E69915B3FFF9F9}, // 1e-277 + {0xAE3DA7D97F6792E3, 0x8DD01FAD907FFC3B}, // 1e-276 + {0x99CD11CFDF41779C, 0xB1442798F49FFB4A}, // 1e-275 + {0x40405643D711D583, 0xDD95317F31C7FA1D}, // 1e-274 + {0x482835EA666B2572, 0x8A7D3EEF7F1CFC52}, // 1e-273 + {0xDA3243650005EECF, 0xAD1C8EAB5EE43B66}, // 1e-272 + {0x90BED43E40076A82, 0xD863B256369D4A40}, // 1e-271 + {0x5A7744A6E804A291, 0x873E4F75E2224E68}, // 1e-270 + {0x711515D0A205CB36, 0xA90DE3535AAAE202}, // 1e-269 + {0x0D5A5B44CA873E03, 0xD3515C2831559A83}, // 1e-268 + {0xE858790AFE9486C2, 0x8412D9991ED58091}, // 1e-267 + {0x626E974DBE39A872, 0xA5178FFF668AE0B6}, // 1e-266 + {0xFB0A3D212DC8128F, 0xCE5D73FF402D98E3}, // 1e-265 + {0x7CE66634BC9D0B99, 0x80FA687F881C7F8E}, // 1e-264 + {0x1C1FFFC1EBC44E80, 0xA139029F6A239F72}, // 1e-263 + {0xA327FFB266B56220, 0xC987434744AC874E}, // 1e-262 + {0x4BF1FF9F0062BAA8, 0xFBE9141915D7A922}, // 1e-261 + {0x6F773FC3603DB4A9, 0x9D71AC8FADA6C9B5}, // 1e-260 + {0xCB550FB4384D21D3, 0xC4CE17B399107C22}, // 1e-259 + {0x7E2A53A146606A48, 0xF6019DA07F549B2B}, // 1e-258 + {0x2EDA7444CBFC426D, 0x99C102844F94E0FB}, // 1e-257 + {0xFA911155FEFB5308, 0xC0314325637A1939}, // 1e-256 + {0x793555AB7EBA27CA, 0xF03D93EEBC589F88}, // 1e-255 + {0x4BC1558B2F3458DE, 0x96267C7535B763B5}, // 1e-254 + {0x9EB1AAEDFB016F16, 0xBBB01B9283253CA2}, // 1e-253 + {0x465E15A979C1CADC, 0xEA9C227723EE8BCB}, // 1e-252 + {0x0BFACD89EC191EC9, 0x92A1958A7675175F}, // 1e-251 + {0xCEF980EC671F667B, 0xB749FAED14125D36}, // 1e-250 + {0x82B7E12780E7401A, 0xE51C79A85916F484}, // 1e-249 + {0xD1B2ECB8B0908810, 0x8F31CC0937AE58D2}, // 1e-248 + {0x861FA7E6DCB4AA15, 0xB2FE3F0B8599EF07}, // 1e-247 + {0x67A791E093E1D49A, 0xDFBDCECE67006AC9}, // 1e-246 + {0xE0C8BB2C5C6D24E0, 0x8BD6A141006042BD}, // 1e-245 + {0x58FAE9F773886E18, 0xAECC49914078536D}, // 1e-244 + {0xAF39A475506A899E, 0xDA7F5BF590966848}, // 1e-243 + {0x6D8406C952429603, 0x888F99797A5E012D}, // 1e-242 + {0xC8E5087BA6D33B83, 0xAAB37FD7D8F58178}, // 1e-241 + {0xFB1E4A9A90880A64, 0xD5605FCDCF32E1D6}, // 1e-240 + {0x5CF2EEA09A55067F, 0x855C3BE0A17FCD26}, // 1e-239 + {0xF42FAA48C0EA481E, 0xA6B34AD8C9DFC06F}, // 1e-238 + {0xF13B94DAF124DA26, 0xD0601D8EFC57B08B}, // 1e-237 + {0x76C53D08D6B70858, 0x823C12795DB6CE57}, // 1e-236 + {0x54768C4B0C64CA6E, 0xA2CB1717B52481ED}, // 1e-235 + {0xA9942F5DCF7DFD09, 0xCB7DDCDDA26DA268}, // 1e-234 + {0xD3F93B35435D7C4C, 0xFE5D54150B090B02}, // 1e-233 + {0xC47BC5014A1A6DAF, 0x9EFA548D26E5A6E1}, // 1e-232 + {0x359AB6419CA1091B, 0xC6B8E9B0709F109A}, // 1e-231 + {0xC30163D203C94B62, 0xF867241C8CC6D4C0}, // 1e-230 + {0x79E0DE63425DCF1D, 0x9B407691D7FC44F8}, // 1e-229 + {0x985915FC12F542E4, 0xC21094364DFB5636}, // 1e-228 + {0x3E6F5B7B17B2939D, 0xF294B943E17A2BC4}, // 1e-227 + {0xA705992CEECF9C42, 0x979CF3CA6CEC5B5A}, // 1e-226 + {0x50C6FF782A838353, 0xBD8430BD08277231}, // 1e-225 + {0xA4F8BF5635246428, 0xECE53CEC4A314EBD}, // 1e-224 + {0x871B7795E136BE99, 0x940F4613AE5ED136}, // 1e-223 + {0x28E2557B59846E3F, 0xB913179899F68584}, // 1e-222 + {0x331AEADA2FE589CF, 0xE757DD7EC07426E5}, // 1e-221 + {0x3FF0D2C85DEF7621, 0x9096EA6F3848984F}, // 1e-220 + {0x0FED077A756B53A9, 0xB4BCA50B065ABE63}, // 1e-219 + {0xD3E8495912C62894, 0xE1EBCE4DC7F16DFB}, // 1e-218 + {0x64712DD7ABBBD95C, 0x8D3360F09CF6E4BD}, // 1e-217 + {0xBD8D794D96AACFB3, 0xB080392CC4349DEC}, // 1e-216 + {0xECF0D7A0FC5583A0, 0xDCA04777F541C567}, // 1e-215 + {0xF41686C49DB57244, 0x89E42CAAF9491B60}, // 1e-214 + {0x311C2875C522CED5, 0xAC5D37D5B79B6239}, // 1e-213 + {0x7D633293366B828B, 0xD77485CB25823AC7}, // 1e-212 + {0xAE5DFF9C02033197, 0x86A8D39EF77164BC}, // 1e-211 + {0xD9F57F830283FDFC, 0xA8530886B54DBDEB}, // 1e-210 + {0xD072DF63C324FD7B, 0xD267CAA862A12D66}, // 1e-209 + {0x4247CB9E59F71E6D, 0x8380DEA93DA4BC60}, // 1e-208 + {0x52D9BE85F074E608, 0xA46116538D0DEB78}, // 1e-207 + {0x67902E276C921F8B, 0xCD795BE870516656}, // 1e-206 + {0x00BA1CD8A3DB53B6, 0x806BD9714632DFF6}, // 1e-205 + {0x80E8A40ECCD228A4, 0xA086CFCD97BF97F3}, // 1e-204 + {0x6122CD128006B2CD, 0xC8A883C0FDAF7DF0}, // 1e-203 + {0x796B805720085F81, 0xFAD2A4B13D1B5D6C}, // 1e-202 + {0xCBE3303674053BB0, 0x9CC3A6EEC6311A63}, // 1e-201 + {0xBEDBFC4411068A9C, 0xC3F490AA77BD60FC}, // 1e-200 + {0xEE92FB5515482D44, 0xF4F1B4D515ACB93B}, // 1e-199 + {0x751BDD152D4D1C4A, 0x991711052D8BF3C5}, // 1e-198 + {0xD262D45A78A0635D, 0xBF5CD54678EEF0B6}, // 1e-197 + {0x86FB897116C87C34, 0xEF340A98172AACE4}, // 1e-196 + {0xD45D35E6AE3D4DA0, 0x9580869F0E7AAC0E}, // 1e-195 + {0x8974836059CCA109, 0xBAE0A846D2195712}, // 1e-194 + {0x2BD1A438703FC94B, 0xE998D258869FACD7}, // 1e-193 + {0x7B6306A34627DDCF, 0x91FF83775423CC06}, // 1e-192 + {0x1A3BC84C17B1D542, 0xB67F6455292CBF08}, // 1e-191 + {0x20CABA5F1D9E4A93, 0xE41F3D6A7377EECA}, // 1e-190 + {0x547EB47B7282EE9C, 0x8E938662882AF53E}, // 1e-189 + {0xE99E619A4F23AA43, 0xB23867FB2A35B28D}, // 1e-188 + {0x6405FA00E2EC94D4, 0xDEC681F9F4C31F31}, // 1e-187 + {0xDE83BC408DD3DD04, 0x8B3C113C38F9F37E}, // 1e-186 + {0x9624AB50B148D445, 0xAE0B158B4738705E}, // 1e-185 + {0x3BADD624DD9B0957, 0xD98DDAEE19068C76}, // 1e-184 + {0xE54CA5D70A80E5D6, 0x87F8A8D4CFA417C9}, // 1e-183 + {0x5E9FCF4CCD211F4C, 0xA9F6D30A038D1DBC}, // 1e-182 + {0x7647C3200069671F, 0xD47487CC8470652B}, // 1e-181 + {0x29ECD9F40041E073, 0x84C8D4DFD2C63F3B}, // 1e-180 + {0xF468107100525890, 0xA5FB0A17C777CF09}, // 1e-179 + {0x7182148D4066EEB4, 0xCF79CC9DB955C2CC}, // 1e-178 + {0xC6F14CD848405530, 0x81AC1FE293D599BF}, // 1e-177 + {0xB8ADA00E5A506A7C, 0xA21727DB38CB002F}, // 1e-176 + {0xA6D90811F0E4851C, 0xCA9CF1D206FDC03B}, // 1e-175 + {0x908F4A166D1DA663, 0xFD442E4688BD304A}, // 1e-174 + {0x9A598E4E043287FE, 0x9E4A9CEC15763E2E}, // 1e-173 + {0x40EFF1E1853F29FD, 0xC5DD44271AD3CDBA}, // 1e-172 + {0xD12BEE59E68EF47C, 0xF7549530E188C128}, // 1e-171 + {0x82BB74F8301958CE, 0x9A94DD3E8CF578B9}, // 1e-170 + {0xE36A52363C1FAF01, 0xC13A148E3032D6E7}, // 1e-169 + {0xDC44E6C3CB279AC1, 0xF18899B1BC3F8CA1}, // 1e-168 + {0x29AB103A5EF8C0B9, 0x96F5600F15A7B7E5}, // 1e-167 + {0x7415D448F6B6F0E7, 0xBCB2B812DB11A5DE}, // 1e-166 + {0x111B495B3464AD21, 0xEBDF661791D60F56}, // 1e-165 + {0xCAB10DD900BEEC34, 0x936B9FCEBB25C995}, // 1e-164 + {0x3D5D514F40EEA742, 0xB84687C269EF3BFB}, // 1e-163 + {0x0CB4A5A3112A5112, 0xE65829B3046B0AFA}, // 1e-162 + {0x47F0E785EABA72AB, 0x8FF71A0FE2C2E6DC}, // 1e-161 + {0x59ED216765690F56, 0xB3F4E093DB73A093}, // 1e-160 + {0x306869C13EC3532C, 0xE0F218B8D25088B8}, // 1e-159 + {0x1E414218C73A13FB, 0x8C974F7383725573}, // 1e-158 + {0xE5D1929EF90898FA, 0xAFBD2350644EEACF}, // 1e-157 + {0xDF45F746B74ABF39, 0xDBAC6C247D62A583}, // 1e-156 + {0x6B8BBA8C328EB783, 0x894BC396CE5DA772}, // 1e-155 + {0x066EA92F3F326564, 0xAB9EB47C81F5114F}, // 1e-154 + {0xC80A537B0EFEFEBD, 0xD686619BA27255A2}, // 1e-153 + {0xBD06742CE95F5F36, 0x8613FD0145877585}, // 1e-152 + {0x2C48113823B73704, 0xA798FC4196E952E7}, // 1e-151 + {0xF75A15862CA504C5, 0xD17F3B51FCA3A7A0}, // 1e-150 + {0x9A984D73DBE722FB, 0x82EF85133DE648C4}, // 1e-149 + {0xC13E60D0D2E0EBBA, 0xA3AB66580D5FDAF5}, // 1e-148 + {0x318DF905079926A8, 0xCC963FEE10B7D1B3}, // 1e-147 + {0xFDF17746497F7052, 0xFFBBCFE994E5C61F}, // 1e-146 + {0xFEB6EA8BEDEFA633, 0x9FD561F1FD0F9BD3}, // 1e-145 + {0xFE64A52EE96B8FC0, 0xC7CABA6E7C5382C8}, // 1e-144 + {0x3DFDCE7AA3C673B0, 0xF9BD690A1B68637B}, // 1e-143 + {0x06BEA10CA65C084E, 0x9C1661A651213E2D}, // 1e-142 + {0x486E494FCFF30A62, 0xC31BFA0FE5698DB8}, // 1e-141 + {0x5A89DBA3C3EFCCFA, 0xF3E2F893DEC3F126}, // 1e-140 + {0xF89629465A75E01C, 0x986DDB5C6B3A76B7}, // 1e-139 + {0xF6BBB397F1135823, 0xBE89523386091465}, // 1e-138 + {0x746AA07DED582E2C, 0xEE2BA6C0678B597F}, // 1e-137 + {0xA8C2A44EB4571CDC, 0x94DB483840B717EF}, // 1e-136 + {0x92F34D62616CE413, 0xBA121A4650E4DDEB}, // 1e-135 + {0x77B020BAF9C81D17, 0xE896A0D7E51E1566}, // 1e-134 + {0x0ACE1474DC1D122E, 0x915E2486EF32CD60}, // 1e-133 + {0x0D819992132456BA, 0xB5B5ADA8AAFF80B8}, // 1e-132 + {0x10E1FFF697ED6C69, 0xE3231912D5BF60E6}, // 1e-131 + {0xCA8D3FFA1EF463C1, 0x8DF5EFABC5979C8F}, // 1e-130 + {0xBD308FF8A6B17CB2, 0xB1736B96B6FD83B3}, // 1e-129 + {0xAC7CB3F6D05DDBDE, 0xDDD0467C64BCE4A0}, // 1e-128 + {0x6BCDF07A423AA96B, 0x8AA22C0DBEF60EE4}, // 1e-127 + {0x86C16C98D2C953C6, 0xAD4AB7112EB3929D}, // 1e-126 + {0xE871C7BF077BA8B7, 0xD89D64D57A607744}, // 1e-125 + {0x11471CD764AD4972, 0x87625F056C7C4A8B}, // 1e-124 + {0xD598E40D3DD89BCF, 0xA93AF6C6C79B5D2D}, // 1e-123 + {0x4AFF1D108D4EC2C3, 0xD389B47879823479}, // 1e-122 + {0xCEDF722A585139BA, 0x843610CB4BF160CB}, // 1e-121 + {0xC2974EB4EE658828, 0xA54394FE1EEDB8FE}, // 1e-120 + {0x733D226229FEEA32, 0xCE947A3DA6A9273E}, // 1e-119 + {0x0806357D5A3F525F, 0x811CCC668829B887}, // 1e-118 + {0xCA07C2DCB0CF26F7, 0xA163FF802A3426A8}, // 1e-117 + {0xFC89B393DD02F0B5, 0xC9BCFF6034C13052}, // 1e-116 + {0xBBAC2078D443ACE2, 0xFC2C3F3841F17C67}, // 1e-115 + {0xD54B944B84AA4C0D, 0x9D9BA7832936EDC0}, // 1e-114 + {0x0A9E795E65D4DF11, 0xC5029163F384A931}, // 1e-113 + {0x4D4617B5FF4A16D5, 0xF64335BCF065D37D}, // 1e-112 + {0x504BCED1BF8E4E45, 0x99EA0196163FA42E}, // 1e-111 + {0xE45EC2862F71E1D6, 0xC06481FB9BCF8D39}, // 1e-110 + {0x5D767327BB4E5A4C, 0xF07DA27A82C37088}, // 1e-109 + {0x3A6A07F8D510F86F, 0x964E858C91BA2655}, // 1e-108 + {0x890489F70A55368B, 0xBBE226EFB628AFEA}, // 1e-107 + {0x2B45AC74CCEA842E, 0xEADAB0ABA3B2DBE5}, // 1e-106 + {0x3B0B8BC90012929D, 0x92C8AE6B464FC96F}, // 1e-105 + {0x09CE6EBB40173744, 0xB77ADA0617E3BBCB}, // 1e-104 + {0xCC420A6A101D0515, 0xE55990879DDCAABD}, // 1e-103 + {0x9FA946824A12232D, 0x8F57FA54C2A9EAB6}, // 1e-102 + {0x47939822DC96ABF9, 0xB32DF8E9F3546564}, // 1e-101 + {0x59787E2B93BC56F7, 0xDFF9772470297EBD}, // 1e-100 + {0x57EB4EDB3C55B65A, 0x8BFBEA76C619EF36}, // 1e-99 + {0xEDE622920B6B23F1, 0xAEFAE51477A06B03}, // 1e-98 + {0xE95FAB368E45ECED, 0xDAB99E59958885C4}, // 1e-97 + {0x11DBCB0218EBB414, 0x88B402F7FD75539B}, // 1e-96 + {0xD652BDC29F26A119, 0xAAE103B5FCD2A881}, // 1e-95 + {0x4BE76D3346F0495F, 0xD59944A37C0752A2}, // 1e-94 + {0x6F70A4400C562DDB, 0x857FCAE62D8493A5}, // 1e-93 + {0xCB4CCD500F6BB952, 0xA6DFBD9FB8E5B88E}, // 1e-92 + {0x7E2000A41346A7A7, 0xD097AD07A71F26B2}, // 1e-91 + {0x8ED400668C0C28C8, 0x825ECC24C873782F}, // 1e-90 + {0x728900802F0F32FA, 0xA2F67F2DFA90563B}, // 1e-89 + {0x4F2B40A03AD2FFB9, 0xCBB41EF979346BCA}, // 1e-88 + {0xE2F610C84987BFA8, 0xFEA126B7D78186BC}, // 1e-87 + {0x0DD9CA7D2DF4D7C9, 0x9F24B832E6B0F436}, // 1e-86 + {0x91503D1C79720DBB, 0xC6EDE63FA05D3143}, // 1e-85 + {0x75A44C6397CE912A, 0xF8A95FCF88747D94}, // 1e-84 + {0xC986AFBE3EE11ABA, 0x9B69DBE1B548CE7C}, // 1e-83 + {0xFBE85BADCE996168, 0xC24452DA229B021B}, // 1e-82 + {0xFAE27299423FB9C3, 0xF2D56790AB41C2A2}, // 1e-81 + {0xDCCD879FC967D41A, 0x97C560BA6B0919A5}, // 1e-80 + {0x5400E987BBC1C920, 0xBDB6B8E905CB600F}, // 1e-79 + {0x290123E9AAB23B68, 0xED246723473E3813}, // 1e-78 + {0xF9A0B6720AAF6521, 0x9436C0760C86E30B}, // 1e-77 + {0xF808E40E8D5B3E69, 0xB94470938FA89BCE}, // 1e-76 + {0xB60B1D1230B20E04, 0xE7958CB87392C2C2}, // 1e-75 + {0xB1C6F22B5E6F48C2, 0x90BD77F3483BB9B9}, // 1e-74 + {0x1E38AEB6360B1AF3, 0xB4ECD5F01A4AA828}, // 1e-73 + {0x25C6DA63C38DE1B0, 0xE2280B6C20DD5232}, // 1e-72 + {0x579C487E5A38AD0E, 0x8D590723948A535F}, // 1e-71 + {0x2D835A9DF0C6D851, 0xB0AF48EC79ACE837}, // 1e-70 + {0xF8E431456CF88E65, 0xDCDB1B2798182244}, // 1e-69 + {0x1B8E9ECB641B58FF, 0x8A08F0F8BF0F156B}, // 1e-68 + {0xE272467E3D222F3F, 0xAC8B2D36EED2DAC5}, // 1e-67 + {0x5B0ED81DCC6ABB0F, 0xD7ADF884AA879177}, // 1e-66 + {0x98E947129FC2B4E9, 0x86CCBB52EA94BAEA}, // 1e-65 + {0x3F2398D747B36224, 0xA87FEA27A539E9A5}, // 1e-64 + {0x8EEC7F0D19A03AAD, 0xD29FE4B18E88640E}, // 1e-63 + {0x1953CF68300424AC, 0x83A3EEEEF9153E89}, // 1e-62 + {0x5FA8C3423C052DD7, 0xA48CEAAAB75A8E2B}, // 1e-61 + {0x3792F412CB06794D, 0xCDB02555653131B6}, // 1e-60 + {0xE2BBD88BBEE40BD0, 0x808E17555F3EBF11}, // 1e-59 + {0x5B6ACEAEAE9D0EC4, 0xA0B19D2AB70E6ED6}, // 1e-58 + {0xF245825A5A445275, 0xC8DE047564D20A8B}, // 1e-57 + {0xEED6E2F0F0D56712, 0xFB158592BE068D2E}, // 1e-56 + {0x55464DD69685606B, 0x9CED737BB6C4183D}, // 1e-55 + {0xAA97E14C3C26B886, 0xC428D05AA4751E4C}, // 1e-54 + {0xD53DD99F4B3066A8, 0xF53304714D9265DF}, // 1e-53 + {0xE546A8038EFE4029, 0x993FE2C6D07B7FAB}, // 1e-52 + {0xDE98520472BDD033, 0xBF8FDB78849A5F96}, // 1e-51 + {0x963E66858F6D4440, 0xEF73D256A5C0F77C}, // 1e-50 + {0xDDE7001379A44AA8, 0x95A8637627989AAD}, // 1e-49 + {0x5560C018580D5D52, 0xBB127C53B17EC159}, // 1e-48 + {0xAAB8F01E6E10B4A6, 0xE9D71B689DDE71AF}, // 1e-47 + {0xCAB3961304CA70E8, 0x9226712162AB070D}, // 1e-46 + {0x3D607B97C5FD0D22, 0xB6B00D69BB55C8D1}, // 1e-45 + {0x8CB89A7DB77C506A, 0xE45C10C42A2B3B05}, // 1e-44 + {0x77F3608E92ADB242, 0x8EB98A7A9A5B04E3}, // 1e-43 + {0x55F038B237591ED3, 0xB267ED1940F1C61C}, // 1e-42 + {0x6B6C46DEC52F6688, 0xDF01E85F912E37A3}, // 1e-41 + {0x2323AC4B3B3DA015, 0x8B61313BBABCE2C6}, // 1e-40 + {0xABEC975E0A0D081A, 0xAE397D8AA96C1B77}, // 1e-39 + {0x96E7BD358C904A21, 0xD9C7DCED53C72255}, // 1e-38 + {0x7E50D64177DA2E54, 0x881CEA14545C7575}, // 1e-37 + {0xDDE50BD1D5D0B9E9, 0xAA242499697392D2}, // 1e-36 + {0x955E4EC64B44E864, 0xD4AD2DBFC3D07787}, // 1e-35 + {0xBD5AF13BEF0B113E, 0x84EC3C97DA624AB4}, // 1e-34 + {0xECB1AD8AEACDD58E, 0xA6274BBDD0FADD61}, // 1e-33 + {0x67DE18EDA5814AF2, 0xCFB11EAD453994BA}, // 1e-32 + {0x80EACF948770CED7, 0x81CEB32C4B43FCF4}, // 1e-31 + {0xA1258379A94D028D, 0xA2425FF75E14FC31}, // 1e-30 + {0x096EE45813A04330, 0xCAD2F7F5359A3B3E}, // 1e-29 + {0x8BCA9D6E188853FC, 0xFD87B5F28300CA0D}, // 1e-28 + {0x775EA264CF55347D, 0x9E74D1B791E07E48}, // 1e-27 + {0x95364AFE032A819D, 0xC612062576589DDA}, // 1e-26 + {0x3A83DDBD83F52204, 0xF79687AED3EEC551}, // 1e-25 + {0xC4926A9672793542, 0x9ABE14CD44753B52}, // 1e-24 + {0x75B7053C0F178293, 0xC16D9A0095928A27}, // 1e-23 + {0x5324C68B12DD6338, 0xF1C90080BAF72CB1}, // 1e-22 + {0xD3F6FC16EBCA5E03, 0x971DA05074DA7BEE}, // 1e-21 + {0x88F4BB1CA6BCF584, 0xBCE5086492111AEA}, // 1e-20 + {0x2B31E9E3D06C32E5, 0xEC1E4A7DB69561A5}, // 1e-19 + {0x3AFF322E62439FCF, 0x9392EE8E921D5D07}, // 1e-18 + {0x09BEFEB9FAD487C2, 0xB877AA3236A4B449}, // 1e-17 + {0x4C2EBE687989A9B3, 0xE69594BEC44DE15B}, // 1e-16 + {0x0F9D37014BF60A10, 0x901D7CF73AB0ACD9}, // 1e-15 + {0x538484C19EF38C94, 0xB424DC35095CD80F}, // 1e-14 + {0x2865A5F206B06FB9, 0xE12E13424BB40E13}, // 1e-13 + {0xF93F87B7442E45D3, 0x8CBCCC096F5088CB}, // 1e-12 + {0xF78F69A51539D748, 0xAFEBFF0BCB24AAFE}, // 1e-11 + {0xB573440E5A884D1B, 0xDBE6FECEBDEDD5BE}, // 1e-10 + {0x31680A88F8953030, 0x89705F4136B4A597}, // 1e-9 + {0xFDC20D2B36BA7C3D, 0xABCC77118461CEFC}, // 1e-8 + {0x3D32907604691B4C, 0xD6BF94D5E57A42BC}, // 1e-7 + {0xA63F9A49C2C1B10F, 0x8637BD05AF6C69B5}, // 1e-6 + {0x0FCF80DC33721D53, 0xA7C5AC471B478423}, // 1e-5 + {0xD3C36113404EA4A8, 0xD1B71758E219652B}, // 1e-4 + {0x645A1CAC083126E9, 0x83126E978D4FDF3B}, // 1e-3 + {0x3D70A3D70A3D70A3, 0xA3D70A3D70A3D70A}, // 1e-2 + {0xCCCCCCCCCCCCCCCC, 0xCCCCCCCCCCCCCCCC}, // 1e-1 + {0x0000000000000000, 0x8000000000000000}, // 1e0 + {0x0000000000000000, 0xA000000000000000}, // 1e1 + {0x0000000000000000, 0xC800000000000000}, // 1e2 + {0x0000000000000000, 0xFA00000000000000}, // 1e3 + {0x0000000000000000, 0x9C40000000000000}, // 1e4 + {0x0000000000000000, 0xC350000000000000}, // 1e5 + {0x0000000000000000, 0xF424000000000000}, // 1e6 + {0x0000000000000000, 0x9896800000000000}, // 1e7 + {0x0000000000000000, 0xBEBC200000000000}, // 1e8 + {0x0000000000000000, 0xEE6B280000000000}, // 1e9 + {0x0000000000000000, 0x9502F90000000000}, // 1e10 + {0x0000000000000000, 0xBA43B74000000000}, // 1e11 + {0x0000000000000000, 0xE8D4A51000000000}, // 1e12 + {0x0000000000000000, 0x9184E72A00000000}, // 1e13 + {0x0000000000000000, 0xB5E620F480000000}, // 1e14 + {0x0000000000000000, 0xE35FA931A0000000}, // 1e15 + {0x0000000000000000, 0x8E1BC9BF04000000}, // 1e16 + {0x0000000000000000, 0xB1A2BC2EC5000000}, // 1e17 + {0x0000000000000000, 0xDE0B6B3A76400000}, // 1e18 + {0x0000000000000000, 0x8AC7230489E80000}, // 1e19 + {0x0000000000000000, 0xAD78EBC5AC620000}, // 1e20 + {0x0000000000000000, 0xD8D726B7177A8000}, // 1e21 + {0x0000000000000000, 0x878678326EAC9000}, // 1e22 + {0x0000000000000000, 0xA968163F0A57B400}, // 1e23 + {0x0000000000000000, 0xD3C21BCECCEDA100}, // 1e24 + {0x0000000000000000, 0x84595161401484A0}, // 1e25 + {0x0000000000000000, 0xA56FA5B99019A5C8}, // 1e26 + {0x0000000000000000, 0xCECB8F27F4200F3A}, // 1e27 + {0x4000000000000000, 0x813F3978F8940984}, // 1e28 + {0x5000000000000000, 0xA18F07D736B90BE5}, // 1e29 + {0xA400000000000000, 0xC9F2C9CD04674EDE}, // 1e30 + {0x4D00000000000000, 0xFC6F7C4045812296}, // 1e31 + {0xF020000000000000, 0x9DC5ADA82B70B59D}, // 1e32 + {0x6C28000000000000, 0xC5371912364CE305}, // 1e33 + {0xC732000000000000, 0xF684DF56C3E01BC6}, // 1e34 + {0x3C7F400000000000, 0x9A130B963A6C115C}, // 1e35 + {0x4B9F100000000000, 0xC097CE7BC90715B3}, // 1e36 + {0x1E86D40000000000, 0xF0BDC21ABB48DB20}, // 1e37 + {0x1314448000000000, 0x96769950B50D88F4}, // 1e38 + {0x17D955A000000000, 0xBC143FA4E250EB31}, // 1e39 + {0x5DCFAB0800000000, 0xEB194F8E1AE525FD}, // 1e40 + {0x5AA1CAE500000000, 0x92EFD1B8D0CF37BE}, // 1e41 + {0xF14A3D9E40000000, 0xB7ABC627050305AD}, // 1e42 + {0x6D9CCD05D0000000, 0xE596B7B0C643C719}, // 1e43 + {0xE4820023A2000000, 0x8F7E32CE7BEA5C6F}, // 1e44 + {0xDDA2802C8A800000, 0xB35DBF821AE4F38B}, // 1e45 + {0xD50B2037AD200000, 0xE0352F62A19E306E}, // 1e46 + {0x4526F422CC340000, 0x8C213D9DA502DE45}, // 1e47 + {0x9670B12B7F410000, 0xAF298D050E4395D6}, // 1e48 + {0x3C0CDD765F114000, 0xDAF3F04651D47B4C}, // 1e49 + {0xA5880A69FB6AC800, 0x88D8762BF324CD0F}, // 1e50 + {0x8EEA0D047A457A00, 0xAB0E93B6EFEE0053}, // 1e51 + {0x72A4904598D6D880, 0xD5D238A4ABE98068}, // 1e52 + {0x47A6DA2B7F864750, 0x85A36366EB71F041}, // 1e53 + {0x999090B65F67D924, 0xA70C3C40A64E6C51}, // 1e54 + {0xFFF4B4E3F741CF6D, 0xD0CF4B50CFE20765}, // 1e55 + {0xBFF8F10E7A8921A4, 0x82818F1281ED449F}, // 1e56 + {0xAFF72D52192B6A0D, 0xA321F2D7226895C7}, // 1e57 + {0x9BF4F8A69F764490, 0xCBEA6F8CEB02BB39}, // 1e58 + {0x02F236D04753D5B4, 0xFEE50B7025C36A08}, // 1e59 + {0x01D762422C946590, 0x9F4F2726179A2245}, // 1e60 + {0x424D3AD2B7B97EF5, 0xC722F0EF9D80AAD6}, // 1e61 + {0xD2E0898765A7DEB2, 0xF8EBAD2B84E0D58B}, // 1e62 + {0x63CC55F49F88EB2F, 0x9B934C3B330C8577}, // 1e63 + {0x3CBF6B71C76B25FB, 0xC2781F49FFCFA6D5}, // 1e64 + {0x8BEF464E3945EF7A, 0xF316271C7FC3908A}, // 1e65 + {0x97758BF0E3CBB5AC, 0x97EDD871CFDA3A56}, // 1e66 + {0x3D52EEED1CBEA317, 0xBDE94E8E43D0C8EC}, // 1e67 + {0x4CA7AAA863EE4BDD, 0xED63A231D4C4FB27}, // 1e68 + {0x8FE8CAA93E74EF6A, 0x945E455F24FB1CF8}, // 1e69 + {0xB3E2FD538E122B44, 0xB975D6B6EE39E436}, // 1e70 + {0x60DBBCA87196B616, 0xE7D34C64A9C85D44}, // 1e71 + {0xBC8955E946FE31CD, 0x90E40FBEEA1D3A4A}, // 1e72 + {0x6BABAB6398BDBE41, 0xB51D13AEA4A488DD}, // 1e73 + {0xC696963C7EED2DD1, 0xE264589A4DCDAB14}, // 1e74 + {0xFC1E1DE5CF543CA2, 0x8D7EB76070A08AEC}, // 1e75 + {0x3B25A55F43294BCB, 0xB0DE65388CC8ADA8}, // 1e76 + {0x49EF0EB713F39EBE, 0xDD15FE86AFFAD912}, // 1e77 + {0x6E3569326C784337, 0x8A2DBF142DFCC7AB}, // 1e78 + {0x49C2C37F07965404, 0xACB92ED9397BF996}, // 1e79 + {0xDC33745EC97BE906, 0xD7E77A8F87DAF7FB}, // 1e80 + {0x69A028BB3DED71A3, 0x86F0AC99B4E8DAFD}, // 1e81 + {0xC40832EA0D68CE0C, 0xA8ACD7C0222311BC}, // 1e82 + {0xF50A3FA490C30190, 0xD2D80DB02AABD62B}, // 1e83 + {0x792667C6DA79E0FA, 0x83C7088E1AAB65DB}, // 1e84 + {0x577001B891185938, 0xA4B8CAB1A1563F52}, // 1e85 + {0xED4C0226B55E6F86, 0xCDE6FD5E09ABCF26}, // 1e86 + {0x544F8158315B05B4, 0x80B05E5AC60B6178}, // 1e87 + {0x696361AE3DB1C721, 0xA0DC75F1778E39D6}, // 1e88 + {0x03BC3A19CD1E38E9, 0xC913936DD571C84C}, // 1e89 + {0x04AB48A04065C723, 0xFB5878494ACE3A5F}, // 1e90 + {0x62EB0D64283F9C76, 0x9D174B2DCEC0E47B}, // 1e91 + {0x3BA5D0BD324F8394, 0xC45D1DF942711D9A}, // 1e92 + {0xCA8F44EC7EE36479, 0xF5746577930D6500}, // 1e93 + {0x7E998B13CF4E1ECB, 0x9968BF6ABBE85F20}, // 1e94 + {0x9E3FEDD8C321A67E, 0xBFC2EF456AE276E8}, // 1e95 + {0xC5CFE94EF3EA101E, 0xEFB3AB16C59B14A2}, // 1e96 + {0xBBA1F1D158724A12, 0x95D04AEE3B80ECE5}, // 1e97 + {0x2A8A6E45AE8EDC97, 0xBB445DA9CA61281F}, // 1e98 + {0xF52D09D71A3293BD, 0xEA1575143CF97226}, // 1e99 + {0x593C2626705F9C56, 0x924D692CA61BE758}, // 1e100 + {0x6F8B2FB00C77836C, 0xB6E0C377CFA2E12E}, // 1e101 + {0x0B6DFB9C0F956447, 0xE498F455C38B997A}, // 1e102 + {0x4724BD4189BD5EAC, 0x8EDF98B59A373FEC}, // 1e103 + {0x58EDEC91EC2CB657, 0xB2977EE300C50FE7}, // 1e104 + {0x2F2967B66737E3ED, 0xDF3D5E9BC0F653E1}, // 1e105 + {0xBD79E0D20082EE74, 0x8B865B215899F46C}, // 1e106 + {0xECD8590680A3AA11, 0xAE67F1E9AEC07187}, // 1e107 + {0xE80E6F4820CC9495, 0xDA01EE641A708DE9}, // 1e108 + {0x3109058D147FDCDD, 0x884134FE908658B2}, // 1e109 + {0xBD4B46F0599FD415, 0xAA51823E34A7EEDE}, // 1e110 + {0x6C9E18AC7007C91A, 0xD4E5E2CDC1D1EA96}, // 1e111 + {0x03E2CF6BC604DDB0, 0x850FADC09923329E}, // 1e112 + {0x84DB8346B786151C, 0xA6539930BF6BFF45}, // 1e113 + {0xE612641865679A63, 0xCFE87F7CEF46FF16}, // 1e114 + {0x4FCB7E8F3F60C07E, 0x81F14FAE158C5F6E}, // 1e115 + {0xE3BE5E330F38F09D, 0xA26DA3999AEF7749}, // 1e116 + {0x5CADF5BFD3072CC5, 0xCB090C8001AB551C}, // 1e117 + {0x73D9732FC7C8F7F6, 0xFDCB4FA002162A63}, // 1e118 + {0x2867E7FDDCDD9AFA, 0x9E9F11C4014DDA7E}, // 1e119 + {0xB281E1FD541501B8, 0xC646D63501A1511D}, // 1e120 + {0x1F225A7CA91A4226, 0xF7D88BC24209A565}, // 1e121 + {0x3375788DE9B06958, 0x9AE757596946075F}, // 1e122 + {0x0052D6B1641C83AE, 0xC1A12D2FC3978937}, // 1e123 + {0xC0678C5DBD23A49A, 0xF209787BB47D6B84}, // 1e124 + {0xF840B7BA963646E0, 0x9745EB4D50CE6332}, // 1e125 + {0xB650E5A93BC3D898, 0xBD176620A501FBFF}, // 1e126 + {0xA3E51F138AB4CEBE, 0xEC5D3FA8CE427AFF}, // 1e127 + {0xC66F336C36B10137, 0x93BA47C980E98CDF}, // 1e128 + {0xB80B0047445D4184, 0xB8A8D9BBE123F017}, // 1e129 + {0xA60DC059157491E5, 0xE6D3102AD96CEC1D}, // 1e130 + {0x87C89837AD68DB2F, 0x9043EA1AC7E41392}, // 1e131 + {0x29BABE4598C311FB, 0xB454E4A179DD1877}, // 1e132 + {0xF4296DD6FEF3D67A, 0xE16A1DC9D8545E94}, // 1e133 + {0x1899E4A65F58660C, 0x8CE2529E2734BB1D}, // 1e134 + {0x5EC05DCFF72E7F8F, 0xB01AE745B101E9E4}, // 1e135 + {0x76707543F4FA1F73, 0xDC21A1171D42645D}, // 1e136 + {0x6A06494A791C53A8, 0x899504AE72497EBA}, // 1e137 + {0x0487DB9D17636892, 0xABFA45DA0EDBDE69}, // 1e138 + {0x45A9D2845D3C42B6, 0xD6F8D7509292D603}, // 1e139 + {0x0B8A2392BA45A9B2, 0x865B86925B9BC5C2}, // 1e140 + {0x8E6CAC7768D7141E, 0xA7F26836F282B732}, // 1e141 + {0x3207D795430CD926, 0xD1EF0244AF2364FF}, // 1e142 + {0x7F44E6BD49E807B8, 0x8335616AED761F1F}, // 1e143 + {0x5F16206C9C6209A6, 0xA402B9C5A8D3A6E7}, // 1e144 + {0x36DBA887C37A8C0F, 0xCD036837130890A1}, // 1e145 + {0xC2494954DA2C9789, 0x802221226BE55A64}, // 1e146 + {0xF2DB9BAA10B7BD6C, 0xA02AA96B06DEB0FD}, // 1e147 + {0x6F92829494E5ACC7, 0xC83553C5C8965D3D}, // 1e148 + {0xCB772339BA1F17F9, 0xFA42A8B73ABBF48C}, // 1e149 + {0xFF2A760414536EFB, 0x9C69A97284B578D7}, // 1e150 + {0xFEF5138519684ABA, 0xC38413CF25E2D70D}, // 1e151 + {0x7EB258665FC25D69, 0xF46518C2EF5B8CD1}, // 1e152 + {0xEF2F773FFBD97A61, 0x98BF2F79D5993802}, // 1e153 + {0xAAFB550FFACFD8FA, 0xBEEEFB584AFF8603}, // 1e154 + {0x95BA2A53F983CF38, 0xEEAABA2E5DBF6784}, // 1e155 + {0xDD945A747BF26183, 0x952AB45CFA97A0B2}, // 1e156 + {0x94F971119AEEF9E4, 0xBA756174393D88DF}, // 1e157 + {0x7A37CD5601AAB85D, 0xE912B9D1478CEB17}, // 1e158 + {0xAC62E055C10AB33A, 0x91ABB422CCB812EE}, // 1e159 + {0x577B986B314D6009, 0xB616A12B7FE617AA}, // 1e160 + {0xED5A7E85FDA0B80B, 0xE39C49765FDF9D94}, // 1e161 + {0x14588F13BE847307, 0x8E41ADE9FBEBC27D}, // 1e162 + {0x596EB2D8AE258FC8, 0xB1D219647AE6B31C}, // 1e163 + {0x6FCA5F8ED9AEF3BB, 0xDE469FBD99A05FE3}, // 1e164 + {0x25DE7BB9480D5854, 0x8AEC23D680043BEE}, // 1e165 + {0xAF561AA79A10AE6A, 0xADA72CCC20054AE9}, // 1e166 + {0x1B2BA1518094DA04, 0xD910F7FF28069DA4}, // 1e167 + {0x90FB44D2F05D0842, 0x87AA9AFF79042286}, // 1e168 + {0x353A1607AC744A53, 0xA99541BF57452B28}, // 1e169 + {0x42889B8997915CE8, 0xD3FA922F2D1675F2}, // 1e170 + {0x69956135FEBADA11, 0x847C9B5D7C2E09B7}, // 1e171 + {0x43FAB9837E699095, 0xA59BC234DB398C25}, // 1e172 + {0x94F967E45E03F4BB, 0xCF02B2C21207EF2E}, // 1e173 + {0x1D1BE0EEBAC278F5, 0x8161AFB94B44F57D}, // 1e174 + {0x6462D92A69731732, 0xA1BA1BA79E1632DC}, // 1e175 + {0x7D7B8F7503CFDCFE, 0xCA28A291859BBF93}, // 1e176 + {0x5CDA735244C3D43E, 0xFCB2CB35E702AF78}, // 1e177 + {0x3A0888136AFA64A7, 0x9DEFBF01B061ADAB}, // 1e178 + {0x088AAA1845B8FDD0, 0xC56BAEC21C7A1916}, // 1e179 + {0x8AAD549E57273D45, 0xF6C69A72A3989F5B}, // 1e180 + {0x36AC54E2F678864B, 0x9A3C2087A63F6399}, // 1e181 + {0x84576A1BB416A7DD, 0xC0CB28A98FCF3C7F}, // 1e182 + {0x656D44A2A11C51D5, 0xF0FDF2D3F3C30B9F}, // 1e183 + {0x9F644AE5A4B1B325, 0x969EB7C47859E743}, // 1e184 + {0x873D5D9F0DDE1FEE, 0xBC4665B596706114}, // 1e185 + {0xA90CB506D155A7EA, 0xEB57FF22FC0C7959}, // 1e186 + {0x09A7F12442D588F2, 0x9316FF75DD87CBD8}, // 1e187 + {0x0C11ED6D538AEB2F, 0xB7DCBF5354E9BECE}, // 1e188 + {0x8F1668C8A86DA5FA, 0xE5D3EF282A242E81}, // 1e189 + {0xF96E017D694487BC, 0x8FA475791A569D10}, // 1e190 + {0x37C981DCC395A9AC, 0xB38D92D760EC4455}, // 1e191 + {0x85BBE253F47B1417, 0xE070F78D3927556A}, // 1e192 + {0x93956D7478CCEC8E, 0x8C469AB843B89562}, // 1e193 + {0x387AC8D1970027B2, 0xAF58416654A6BABB}, // 1e194 + {0x06997B05FCC0319E, 0xDB2E51BFE9D0696A}, // 1e195 + {0x441FECE3BDF81F03, 0x88FCF317F22241E2}, // 1e196 + {0xD527E81CAD7626C3, 0xAB3C2FDDEEAAD25A}, // 1e197 + {0x8A71E223D8D3B074, 0xD60B3BD56A5586F1}, // 1e198 + {0xF6872D5667844E49, 0x85C7056562757456}, // 1e199 + {0xB428F8AC016561DB, 0xA738C6BEBB12D16C}, // 1e200 + {0xE13336D701BEBA52, 0xD106F86E69D785C7}, // 1e201 + {0xECC0024661173473, 0x82A45B450226B39C}, // 1e202 + {0x27F002D7F95D0190, 0xA34D721642B06084}, // 1e203 + {0x31EC038DF7B441F4, 0xCC20CE9BD35C78A5}, // 1e204 + {0x7E67047175A15271, 0xFF290242C83396CE}, // 1e205 + {0x0F0062C6E984D386, 0x9F79A169BD203E41}, // 1e206 + {0x52C07B78A3E60868, 0xC75809C42C684DD1}, // 1e207 + {0xA7709A56CCDF8A82, 0xF92E0C3537826145}, // 1e208 + {0x88A66076400BB691, 0x9BBCC7A142B17CCB}, // 1e209 + {0x6ACFF893D00EA435, 0xC2ABF989935DDBFE}, // 1e210 + {0x0583F6B8C4124D43, 0xF356F7EBF83552FE}, // 1e211 + {0xC3727A337A8B704A, 0x98165AF37B2153DE}, // 1e212 + {0x744F18C0592E4C5C, 0xBE1BF1B059E9A8D6}, // 1e213 + {0x1162DEF06F79DF73, 0xEDA2EE1C7064130C}, // 1e214 + {0x8ADDCB5645AC2BA8, 0x9485D4D1C63E8BE7}, // 1e215 + {0x6D953E2BD7173692, 0xB9A74A0637CE2EE1}, // 1e216 + {0xC8FA8DB6CCDD0437, 0xE8111C87C5C1BA99}, // 1e217 + {0x1D9C9892400A22A2, 0x910AB1D4DB9914A0}, // 1e218 + {0x2503BEB6D00CAB4B, 0xB54D5E4A127F59C8}, // 1e219 + {0x2E44AE64840FD61D, 0xE2A0B5DC971F303A}, // 1e220 + {0x5CEAECFED289E5D2, 0x8DA471A9DE737E24}, // 1e221 + {0x7425A83E872C5F47, 0xB10D8E1456105DAD}, // 1e222 + {0xD12F124E28F77719, 0xDD50F1996B947518}, // 1e223 + {0x82BD6B70D99AAA6F, 0x8A5296FFE33CC92F}, // 1e224 + {0x636CC64D1001550B, 0xACE73CBFDC0BFB7B}, // 1e225 + {0x3C47F7E05401AA4E, 0xD8210BEFD30EFA5A}, // 1e226 + {0x65ACFAEC34810A71, 0x8714A775E3E95C78}, // 1e227 + {0x7F1839A741A14D0D, 0xA8D9D1535CE3B396}, // 1e228 + {0x1EDE48111209A050, 0xD31045A8341CA07C}, // 1e229 + {0x934AED0AAB460432, 0x83EA2B892091E44D}, // 1e230 + {0xF81DA84D5617853F, 0xA4E4B66B68B65D60}, // 1e231 + {0x36251260AB9D668E, 0xCE1DE40642E3F4B9}, // 1e232 + {0xC1D72B7C6B426019, 0x80D2AE83E9CE78F3}, // 1e233 + {0xB24CF65B8612F81F, 0xA1075A24E4421730}, // 1e234 + {0xDEE033F26797B627, 0xC94930AE1D529CFC}, // 1e235 + {0x169840EF017DA3B1, 0xFB9B7CD9A4A7443C}, // 1e236 + {0x8E1F289560EE864E, 0x9D412E0806E88AA5}, // 1e237 + {0xF1A6F2BAB92A27E2, 0xC491798A08A2AD4E}, // 1e238 + {0xAE10AF696774B1DB, 0xF5B5D7EC8ACB58A2}, // 1e239 + {0xACCA6DA1E0A8EF29, 0x9991A6F3D6BF1765}, // 1e240 + {0x17FD090A58D32AF3, 0xBFF610B0CC6EDD3F}, // 1e241 + {0xDDFC4B4CEF07F5B0, 0xEFF394DCFF8A948E}, // 1e242 + {0x4ABDAF101564F98E, 0x95F83D0A1FB69CD9}, // 1e243 + {0x9D6D1AD41ABE37F1, 0xBB764C4CA7A4440F}, // 1e244 + {0x84C86189216DC5ED, 0xEA53DF5FD18D5513}, // 1e245 + {0x32FD3CF5B4E49BB4, 0x92746B9BE2F8552C}, // 1e246 + {0x3FBC8C33221DC2A1, 0xB7118682DBB66A77}, // 1e247 + {0x0FABAF3FEAA5334A, 0xE4D5E82392A40515}, // 1e248 + {0x29CB4D87F2A7400E, 0x8F05B1163BA6832D}, // 1e249 + {0x743E20E9EF511012, 0xB2C71D5BCA9023F8}, // 1e250 + {0x914DA9246B255416, 0xDF78E4B2BD342CF6}, // 1e251 + {0x1AD089B6C2F7548E, 0x8BAB8EEFB6409C1A}, // 1e252 + {0xA184AC2473B529B1, 0xAE9672ABA3D0C320}, // 1e253 + {0xC9E5D72D90A2741E, 0xDA3C0F568CC4F3E8}, // 1e254 + {0x7E2FA67C7A658892, 0x8865899617FB1871}, // 1e255 + {0xDDBB901B98FEEAB7, 0xAA7EEBFB9DF9DE8D}, // 1e256 + {0x552A74227F3EA565, 0xD51EA6FA85785631}, // 1e257 + {0xD53A88958F87275F, 0x8533285C936B35DE}, // 1e258 + {0x8A892ABAF368F137, 0xA67FF273B8460356}, // 1e259 + {0x2D2B7569B0432D85, 0xD01FEF10A657842C}, // 1e260 + {0x9C3B29620E29FC73, 0x8213F56A67F6B29B}, // 1e261 + {0x8349F3BA91B47B8F, 0xA298F2C501F45F42}, // 1e262 + {0x241C70A936219A73, 0xCB3F2F7642717713}, // 1e263 + {0xED238CD383AA0110, 0xFE0EFB53D30DD4D7}, // 1e264 + {0xF4363804324A40AA, 0x9EC95D1463E8A506}, // 1e265 + {0xB143C6053EDCD0D5, 0xC67BB4597CE2CE48}, // 1e266 + {0xDD94B7868E94050A, 0xF81AA16FDC1B81DA}, // 1e267 + {0xCA7CF2B4191C8326, 0x9B10A4E5E9913128}, // 1e268 + {0xFD1C2F611F63A3F0, 0xC1D4CE1F63F57D72}, // 1e269 + {0xBC633B39673C8CEC, 0xF24A01A73CF2DCCF}, // 1e270 + {0xD5BE0503E085D813, 0x976E41088617CA01}, // 1e271 + {0x4B2D8644D8A74E18, 0xBD49D14AA79DBC82}, // 1e272 + {0xDDF8E7D60ED1219E, 0xEC9C459D51852BA2}, // 1e273 + {0xCABB90E5C942B503, 0x93E1AB8252F33B45}, // 1e274 + {0x3D6A751F3B936243, 0xB8DA1662E7B00A17}, // 1e275 + {0x0CC512670A783AD4, 0xE7109BFBA19C0C9D}, // 1e276 + {0x27FB2B80668B24C5, 0x906A617D450187E2}, // 1e277 + {0xB1F9F660802DEDF6, 0xB484F9DC9641E9DA}, // 1e278 + {0x5E7873F8A0396973, 0xE1A63853BBD26451}, // 1e279 + {0xDB0B487B6423E1E8, 0x8D07E33455637EB2}, // 1e280 + {0x91CE1A9A3D2CDA62, 0xB049DC016ABC5E5F}, // 1e281 + {0x7641A140CC7810FB, 0xDC5C5301C56B75F7}, // 1e282 + {0xA9E904C87FCB0A9D, 0x89B9B3E11B6329BA}, // 1e283 + {0x546345FA9FBDCD44, 0xAC2820D9623BF429}, // 1e284 + {0xA97C177947AD4095, 0xD732290FBACAF133}, // 1e285 + {0x49ED8EABCCCC485D, 0x867F59A9D4BED6C0}, // 1e286 + {0x5C68F256BFFF5A74, 0xA81F301449EE8C70}, // 1e287 + {0x73832EEC6FFF3111, 0xD226FC195C6A2F8C}, // 1e288 + {0xC831FD53C5FF7EAB, 0x83585D8FD9C25DB7}, // 1e289 + {0xBA3E7CA8B77F5E55, 0xA42E74F3D032F525}, // 1e290 + {0x28CE1BD2E55F35EB, 0xCD3A1230C43FB26F}, // 1e291 + {0x7980D163CF5B81B3, 0x80444B5E7AA7CF85}, // 1e292 + {0xD7E105BCC332621F, 0xA0555E361951C366}, // 1e293 + {0x8DD9472BF3FEFAA7, 0xC86AB5C39FA63440}, // 1e294 + {0xB14F98F6F0FEB951, 0xFA856334878FC150}, // 1e295 + {0x6ED1BF9A569F33D3, 0x9C935E00D4B9D8D2}, // 1e296 + {0x0A862F80EC4700C8, 0xC3B8358109E84F07}, // 1e297 + {0xCD27BB612758C0FA, 0xF4A642E14C6262C8}, // 1e298 + {0x8038D51CB897789C, 0x98E7E9CCCFBD7DBD}, // 1e299 + {0xE0470A63E6BD56C3, 0xBF21E44003ACDD2C}, // 1e300 + {0x1858CCFCE06CAC74, 0xEEEA5D5004981478}, // 1e301 + {0x0F37801E0C43EBC8, 0x95527A5202DF0CCB}, // 1e302 + {0xD30560258F54E6BA, 0xBAA718E68396CFFD}, // 1e303 + {0x47C6B82EF32A2069, 0xE950DF20247C83FD}, // 1e304 + {0x4CDC331D57FA5441, 0x91D28B7416CDD27E}, // 1e305 + {0xE0133FE4ADF8E952, 0xB6472E511C81471D}, // 1e306 + {0x58180FDDD97723A6, 0xE3D8F9E563A198E5}, // 1e307 + {0x570F09EAA7EA7648, 0x8E679C2F5E44FF8F}, // 1e308 + {0x2CD2CC6551E513DA, 0xB201833B35D63F73}, // 1e309 + {0xF8077F7EA65E58D1, 0xDE81E40A034BCF4F}, // 1e310 + {0xFB04AFAF27FAF782, 0x8B112E86420F6191}, // 1e311 + {0x79C5DB9AF1F9B563, 0xADD57A27D29339F6}, // 1e312 + {0x18375281AE7822BC, 0xD94AD8B1C7380874}, // 1e313 + {0x8F2293910D0B15B5, 0x87CEC76F1C830548}, // 1e314 + {0xB2EB3875504DDB22, 0xA9C2794AE3A3C69A}, // 1e315 + {0x5FA60692A46151EB, 0xD433179D9C8CB841}, // 1e316 + {0xDBC7C41BA6BCD333, 0x849FEEC281D7F328}, // 1e317 + {0x12B9B522906C0800, 0xA5C7EA73224DEFF3}, // 1e318 + {0xD768226B34870A00, 0xCF39E50FEAE16BEF}, // 1e319 + {0xE6A1158300D46640, 0x81842F29F2CCE375}, // 1e320 + {0x60495AE3C1097FD0, 0xA1E53AF46F801C53}, // 1e321 + {0x385BB19CB14BDFC4, 0xCA5E89B18B602368}, // 1e322 + {0x46729E03DD9ED7B5, 0xFCF62C1DEE382C42}, // 1e323 + {0x6C07A2C26A8346D1, 0x9E19DB92B4E31BA9}, // 1e324 + {0xC7098B7305241885, 0xC5A05277621BE293}, // 1e325 + {0xB8CBEE4FC66D1EA7, 0xF70867153AA2DB38}, // 1e326 + {0x737F74F1DC043328, 0x9A65406D44A5C903}, // 1e327 + {0x505F522E53053FF2, 0xC0FE908895CF3B44}, // 1e328 + {0x647726B9E7C68FEF, 0xF13E34AABB430A15}, // 1e329 + {0x5ECA783430DC19F5, 0x96C6E0EAB509E64D}, // 1e330 + {0xB67D16413D132072, 0xBC789925624C5FE0}, // 1e331 + {0xE41C5BD18C57E88F, 0xEB96BF6EBADF77D8}, // 1e332 + {0x8E91B962F7B6F159, 0x933E37A534CBAAE7}, // 1e333 + {0x723627BBB5A4ADB0, 0xB80DC58E81FE95A1}, // 1e334 + {0xCEC3B1AAA30DD91C, 0xE61136F2227E3B09}, // 1e335 + {0x213A4F0AA5E8A7B1, 0x8FCAC257558EE4E6}, // 1e336 + {0xA988E2CD4F62D19D, 0xB3BD72ED2AF29E1F}, // 1e337 + {0x93EB1B80A33B8605, 0xE0ACCFA875AF45A7}, // 1e338 + {0xBC72F130660533C3, 0x8C6C01C9498D8B88}, // 1e339 + {0xEB8FAD7C7F8680B4, 0xAF87023B9BF0EE6A}, // 1e340 + {0xA67398DB9F6820E1, 0xDB68C2CA82ED2A05}, // 1e341 + {0x88083F8943A1148C, 0x892179BE91D43A43}, // 1e342 + {0x6A0A4F6B948959B0, 0xAB69D82E364948D4}, // 1e343 + {0x848CE34679ABB01C, 0xD6444E39C3DB9B09}, // 1e344 + {0xF2D80E0C0C0B4E11, 0x85EAB0E41A6940E5}, // 1e345 + {0x6F8E118F0F0E2195, 0xA7655D1D2103911F}, // 1e346 + {0x4B7195F2D2D1A9FB, 0xD13EB46469447567}, // 1e347 +}; + +} // namespace internal +} // namespace __llvm_libc + +#endif // LIBC_SRC_SUPPORT_DETAILED_POWERS_OF_TEN_H diff --git a/libc/src/__support/high_precision_decimal.h b/libc/src/__support/high_precision_decimal.h index d61ba8075037c5cb5b8388058f142144aa1d2e01..b7fe1296e86b08f705aeaa6f7e93e0e8739ff8a7 100644 --- a/libc/src/__support/high_precision_decimal.h +++ b/libc/src/__support/high_precision_decimal.h @@ -291,6 +291,7 @@ public: sawDigit = true; if (*numString == '0' && this->numDigits == 0) { --this->decimalPoint; + ++numString; continue; } if (this->numDigits < MAX_NUM_DIGITS) { @@ -311,6 +312,11 @@ public: ++numString; if (isdigit(*numString) || *numString == '+' || *numString == '-') { int32_t addToExp = strtointeger(numString, nullptr, 10); + if (addToExp > 100000) { + addToExp = 100000; + } else if (addToExp < -100000) { + addToExp = -100000; + } this->decimalPoint += addToExp; } } diff --git a/libc/src/__support/str_to_float.h b/libc/src/__support/str_to_float.h new file mode 100644 index 0000000000000000000000000000000000000000..67ebf3e769fefb168263cc3984ddb4b14a8d41af --- /dev/null +++ b/libc/src/__support/str_to_float.h @@ -0,0 +1,593 @@ +//===-- String to float conversion utils ------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LIBC_SRC_SUPPORT_STR_TO_FLOAT_H +#define LIBC_SRC_SUPPORT_STR_TO_FLOAT_H + +#include "src/__support/FPUtil/FPBits.h" +#include "src/__support/ctype_utils.h" +#include "src/__support/detailed_powers_of_ten.h" +#include "src/__support/high_precision_decimal.h" +#include "src/__support/str_conv_utils.h" +#include "utils/CPP/Limits.h" +#include + +namespace __llvm_libc { +namespace internal { + +// Shifts right and rounds according to the following rules: +// 1) If the part being cut off is more than 2^(amountToShift - 1) then round +// up +// 2) If it is less than that number then round down +// 3) If it is exactly that number, then round so that the final number will be +// even +template +static inline T shiftRightAndRound(T numToShift, unsigned int amountToShift) { + T result = numToShift >> amountToShift; + T truncated = numToShift & ((1 << amountToShift) - 1); + + if (truncated < (1 << (amountToShift - 1))) { + return result; + } else if (truncated > (1 << (amountToShift - 1))) { + return result + 1; + } else { + return result + (result & 1); // This rounds towards even. + } +} + +template uint32_t leadingZeroes(T inputNumber) { + // TODO(michaelrj): investigate the portability of using something like + // __builtin_clz for specific types. + constexpr uint32_t bitsInT = sizeof(T) * 8; + if (inputNumber == 0) { + return bitsInT; + } + uint32_t curGuess = bitsInT / 2; + uint32_t rangeSize = bitsInT / 2; + // while either shifting by curGuess does not get rid of all of the bits or + // shifting by one less also gets rid of all of the bits then we have not + // found the first bit. + while (((inputNumber >> curGuess) > 0) || + ((inputNumber >> (curGuess - 1)) == 0)) { + // Binary search for the first set bit + rangeSize /= 2; + if (rangeSize == 0) { + break; + } + if ((inputNumber >> curGuess) > 0) { + curGuess += rangeSize; + } else { + curGuess -= rangeSize; + } + } + if (inputNumber >> curGuess > 0) { + curGuess++; + } + return bitsInT - curGuess; +} + +static inline uint64_t low64(__uint128_t num) { + return static_cast(num & 0xffffffffffffffff); +} + +static inline uint64_t high64(__uint128_t num) { + return static_cast(num >> 64); +} + +// This Eisel-Lemire implementation is based on the algorithm described in the +// paper Number Parsing at a Gigabyte per Second, Software: Practice and +// Experience 51 (8), 2021 (https://arxiv.org/abs/2101.11408), as well as the +// description by Nigel Tao +// (https://nigeltao.github.io/blog/2020/eisel-lemire.html) and the golang +// implementation, also by Nigel Tao +// (https://github.com/golang/go/blob/release-branch.go1.16/src/strconv/eisel_lemire.go#L25) +// for some optimizations as well as handling 32 bit floats. +template +static inline bool +eiselLemire(typename fputil::FPBits::UIntType mantissa, int32_t exp10, + typename fputil::FPBits::UIntType *outputMantissa, + uint32_t *outputExp2) { + + using BitsType = typename fputil::FPBits::UIntType; + constexpr uint32_t BITS_IN_MANTISSA = sizeof(mantissa) * 8; + + if (sizeof(T) > 8) { // This algorithm cannot handle anything longer than a + // double, so we skip straight to the fallback. + return false; + } + + // Exp10 Range + if (exp10 < DETAILED_POWERS_OF_TEN_MIN_EXP_10 || + exp10 > DETAILED_POWERS_OF_TEN_MAX_EXP_10) { + return false; + } + + // Normalization + uint32_t clz = leadingZeroes(mantissa); + mantissa <<= clz; + + uint32_t exp2 = exp10ToExp2(exp10) + BITS_IN_MANTISSA + + fputil::FloatProperties::exponentBias - clz; + + // Multiplication + const uint64_t *powerOfTen = + DETAILED_POWERS_OF_TEN[exp10 - DETAILED_POWERS_OF_TEN_MIN_EXP_10]; + + __uint128_t firstApprox = static_cast<__uint128_t>(mantissa) * + static_cast<__uint128_t>(powerOfTen[1]); + + // Wider Approximation + __uint128_t finalApprox; + // The halfway constant is used to check if the bits that will be shifted away + // intially are all 1. For doubles this is 64 (bitstype size) - 52 (final + // mantissa size) - 3 (we shift away the last two bits separately for + // accuracy, and the most significant bit is ignored.) = 9. Similarly, it's 6 + // for floats in this case. + const uint64_t halfwayConstant = sizeof(T) == 8 ? 0x1FF : 0x3F; + if ((high64(firstApprox) & halfwayConstant) == halfwayConstant && + low64(firstApprox) + mantissa < mantissa) { + __uint128_t lowBits = static_cast<__uint128_t>(mantissa) * + static_cast<__uint128_t>(powerOfTen[0]); + __uint128_t secondApprox = + firstApprox + static_cast<__uint128_t>(high64(lowBits)); + + if ((high64(secondApprox) & halfwayConstant) == halfwayConstant && + low64(secondApprox) + 1 == 0 && low64(lowBits) + mantissa < mantissa) { + return false; + } + finalApprox = secondApprox; + } else { + finalApprox = firstApprox; + } + + // Shifting to 54 bits for doubles and 25 bits for floats + BitsType msb = high64(finalApprox) >> (BITS_IN_MANTISSA - 1); + BitsType finalMantissa = + high64(finalApprox) >> (msb + BITS_IN_MANTISSA - + (fputil::FloatProperties::mantissaWidth + 3)); + exp2 -= 1 ^ msb; // same as !msb + + // Half-way ambiguity + if (low64(finalApprox) == 0 && (high64(finalApprox) & halfwayConstant) == 0 && + (finalMantissa & 3) == 1) { + return false; + } + + // From 54 to 53 bits for doubles and 25 to 24 bits for floats + finalMantissa += finalMantissa & 1; + finalMantissa >>= 1; + if ((finalMantissa >> (fputil::FloatProperties::mantissaWidth + 1)) > 0) { + finalMantissa >>= 1; + ++exp2; + } + + // The if block is equivalent to (but has fewer branches than): + // if exp2 <= 0 || exp2 >= 0x7FF { etc } + if (exp2 - 1 >= (1 << fputil::FloatProperties::exponentWidth) - 2) { + return false; + } + + *outputMantissa = finalMantissa; + *outputExp2 = exp2; + return true; +} + +// The nth item in POWERS_OF_TWO represents the greatest power of two less than +// 10^n. This tells us how much we can safely shift without overshooting. +constexpr uint8_t POWERS_OF_TWO[19] = { + 0, 3, 6, 9, 13, 16, 19, 23, 26, 29, 33, 36, 39, 43, 46, 49, 53, 56, 59, +}; +constexpr int32_t NUM_POWERS_OF_TWO = + sizeof(POWERS_OF_TWO) / sizeof(POWERS_OF_TWO[0]); + +// Takes a mantissa and base 10 exponent and converts it into its closest +// floating point type T equivalent. This is the fallback algorithm used when +// the Eisel-Lemire algorithm fails, it's slower but more accurate. It's based +// on the Simple Decimal Conversion algorithm by Nigel Tao, described at this +// link: https://nigeltao.github.io/blog/2020/parse-number-f64-simple.html +template +static inline void +simpleDecimalConversion(const char *__restrict numStart, + typename fputil::FPBits::UIntType *outputMantissa, + uint32_t *outputExp2) { + + int32_t exp2 = 0; + HighPrecsisionDecimal hpd = HighPrecsisionDecimal(numStart); + + if (hpd.getNumDigits() == 0) { + *outputMantissa = 0; + *outputExp2 = 0; + return; + } + + // If the exponent is too large and can't be represented in this size of + // float, return inf. + if (hpd.getDecimalPoint() > 0 && + exp10ToExp2(hpd.getDecimalPoint() - 1) > + static_cast(fputil::FloatProperties::exponentBias)) { + *outputMantissa = 0; + *outputExp2 = fputil::FPBits::maxExponent; + errno = ERANGE; // NOLINT + return; + } + // If the exponent is too small even for a subnormal, return 0. + if (hpd.getDecimalPoint() < 0 && + exp10ToExp2(-hpd.getDecimalPoint()) > + static_cast(fputil::FloatProperties::exponentBias + + fputil::FloatProperties::mantissaWidth)) { + *outputMantissa = 0; + *outputExp2 = 0; + errno = ERANGE; // NOLINT + return; + } + + // Right shift until the number is smaller than 1. + while (hpd.getDecimalPoint() > 0) { + int32_t shiftAmount = 0; + if (hpd.getDecimalPoint() >= NUM_POWERS_OF_TWO) { + shiftAmount = 60; + } else { + shiftAmount = POWERS_OF_TWO[hpd.getDecimalPoint()]; + } + exp2 += shiftAmount; + hpd.shift(-shiftAmount); + } + + // Left shift until the number is between 1/2 and 1 + while (hpd.getDecimalPoint() < 0 || + (hpd.getDecimalPoint() == 0 && hpd.getDigits()[0] < 5)) { + int32_t shiftAmount = 0; + + if (-hpd.getDecimalPoint() >= NUM_POWERS_OF_TWO) { + shiftAmount = 60; + } else if (hpd.getDecimalPoint() != 0) { + shiftAmount = POWERS_OF_TWO[-hpd.getDecimalPoint()]; + } else { // This handles the case of the number being between .1 and .5 + shiftAmount = 1; + } + exp2 -= shiftAmount; + hpd.shift(shiftAmount); + } + + // Left shift once so that the number is between 1 and 2 + --exp2; + hpd.shift(1); + + // Get the biased exponent + exp2 += fputil::FloatProperties::exponentBias; + + // Handle the exponent being too large (and return inf). + if (exp2 >= fputil::FPBits::maxExponent) { + *outputMantissa = 0; + *outputExp2 = fputil::FPBits::maxExponent; + errno = ERANGE; // NOLINT + return; + } + + // Shift left to fill the mantissa + hpd.shift(fputil::FloatProperties::mantissaWidth); + typename fputil::FPBits::UIntType finalMantissa = + hpd.roundToIntegerType::UIntType>(); + + // Handle subnormals + if (exp2 <= 0) { + // Shift right until there is a valid exponent + while (exp2 < 0) { + hpd.shift(-1); + ++exp2; + } + // Shift right one more time to compensate for the left shift to get it + // between 1 and 2. + hpd.shift(-1); + finalMantissa = + hpd.roundToIntegerType::UIntType>(); + + // Check if by shifting right we've caused this to round to a normal number. + if ((finalMantissa >> fputil::FloatProperties::mantissaWidth) != 0) { + ++exp2; + } + } + + // Check if rounding added a bit, and shift down if that's the case. + if (finalMantissa == typename fputil::FPBits::UIntType(2) + << fputil::FloatProperties::mantissaWidth) { + finalMantissa >>= 1; + ++exp2; + } + + *outputMantissa = finalMantissa; + *outputExp2 = exp2; +} + +// Takes a mantissa and base 10 exponent and converts it into its closest +// floating point type T equivalient. First we try the Eisel-Lemire algorithm, +// then if that fails then we fall back to a more accurate algorithm for +// accuracy. The resulting mantissa and exponent are placed in outputMantissa +// and outputExp2. +template +static inline void +decimalExpToFloat(typename fputil::FPBits::UIntType mantissa, int32_t exp10, + const char *__restrict numStart, bool truncated, + typename fputil::FPBits::UIntType *outputMantissa, + uint32_t *outputExp2) { + + // TODO: Implement Clinger's fast path, as well as other shortcuts here. + + // Try Eisel-Lemire + if (eiselLemire(mantissa, exp10, outputMantissa, outputExp2)) { + if (!truncated) { + return; + } + // If the mantissa is truncated, then the result may be off by the LSB, so + // check if rounding the mantissa up changes the result. If not, then it's + // safe, else use the fallback. + typename fputil::FPBits::UIntType firstMantissa = *outputMantissa; + uint32_t firstExp2 = *outputExp2; + if (eiselLemire(mantissa + 1, exp10, outputMantissa, outputExp2)) { + if (*outputMantissa == firstMantissa && *outputExp2 == firstExp2) { + return; + } + } + } + + simpleDecimalConversion(numStart, outputMantissa, outputExp2); + + return; +} + +// checks if the next 4 characters of the string pointer are the start of a +// hexadecimal floating point number. Does not advance the string pointer. +static inline bool is_float_hex_start(const char *__restrict src, + const char decimalPoint) { + if (!(*src == '0' && (*(src + 1) | 32) == 'x')) { + return false; + } + if (*(src + 2) == decimalPoint) { + return isalnum(*(src + 3)) && b36_char_to_int(*(src + 3)) < 16; + } else { + return isalnum(*(src + 2)) && b36_char_to_int(*(src + 2)) < 16; + } +} + +// Takes a pointer to a string and a pointer to a string pointer. This function +// is used as the backend for all of the string to float functions. +template +static inline T strtofloatingpoint(const char *__restrict src, + char **__restrict strEnd) { + using BitsType = typename fputil::FPBits::UIntType; + fputil::FPBits result = fputil::FPBits(); + const char *originalSrc = src; + bool seenDigit = false; + src = first_non_whitespace(src); + + if (*src == '+' || *src == '-') { + if (*src == '-') { + result.setSign(true); + } + ++src; + } + + static constexpr char DECIMAL_POINT = '.'; + static const char *INF_STRING = "infinity"; + static const char *NAN_STRING = "nan"; + + bool truncated = false; + + if (isdigit(*src) || *src == DECIMAL_POINT) { // regular number + int base = 10; + char exponentMarker = 'e'; + if (is_float_hex_start(src, DECIMAL_POINT)) { + base = 16; + src += 2; + exponentMarker = 'p'; + seenDigit = true; + } + const char *__restrict numStart = src; + bool afterDecimal = false; + + BitsType mantissa = 0; + int32_t exponent = 0; + + // The goal for the first step of parsing is to convert the number in src to + // the format mantissa * (base ^ exponent) + + constexpr BitsType MANTISSA_MAX = + BitsType(1) << (fputil::FloatProperties::mantissaWidth + + 1); // The extra bit is to give space for the implicit 1 + const BitsType BITSTYPE_MAX_DIV_BY_BASE = + __llvm_libc::cpp::NumericLimits::max() / base; + while ((isalnum(*src) || *src == DECIMAL_POINT) && + mantissa < BITSTYPE_MAX_DIV_BY_BASE) { + if (*src == DECIMAL_POINT && afterDecimal) { + break; // this means that *src points to a second decimal point, ending + // the number. + } else if (*src == DECIMAL_POINT) { + afterDecimal = true; + ++src; + continue; + } + int digit = b36_char_to_int(*src); + if (digit >= base) { + break; + } + + mantissa = (mantissa * base) + digit; + seenDigit = true; + if (afterDecimal) { + --exponent; + } + + ++src; + } + + // The second loop is to run through the remaining digits after we've filled + // the mantissa. + while (isalnum(*src) || *src == DECIMAL_POINT) { + if (*src == DECIMAL_POINT && afterDecimal) { + break; // this means that *src points to a second decimal point, ending + // the number. + } else if (*src == DECIMAL_POINT) { + afterDecimal = true; + ++src; + continue; + } + int digit = b36_char_to_int(*src); + if (digit >= base) { + break; + } + + if (digit > 0) { + truncated = true; + } + + if (!afterDecimal) { + exponent++; + } + + ++src; + } + + // if our base is 16 then convert the exponent to base 2 + if (base == 16) { + exponent *= 4; + } + + if ((*src | 32) == exponentMarker) { + if (*(src + 1) == '+' || *(src + 1) == '-' || isdigit(*(src + 1))) { + ++src; + char *tempStrEnd; + int32_t add_to_exponent = strtointeger(src, &tempStrEnd, 10); + src += tempStrEnd - src; + exponent += add_to_exponent; + } + } + + if (mantissa == 0) { // if we have a 0, then also 0 the exponent. + exponent = 0; + } else if (base == 16) { + + // These two loops should normalize the number if we assume the decimal + // point is after the bit at mantissaWidth. + // For example if type T is a 32 bit float, this should result in a + // mantissa with its most significant 1 being at bit 23. + while (mantissa < (MANTISSA_MAX >> 1)) { + mantissa = mantissa << 1; + --exponent; + } + BitsType mantissaCopy = mantissa; + unsigned int amountToShift = 0; + while (mantissaCopy > MANTISSA_MAX) { + mantissaCopy = mantissaCopy >> 1; + ++amountToShift; + } + exponent += amountToShift; + mantissa = shiftRightAndRound(mantissa, amountToShift); + + // Account for the fact that the mantissa represented an integer + // previously, but now represents the fractional part of a normalized + // number. + exponent += fputil::FloatProperties::mantissaWidth; + + int32_t biasedExponent = exponent + fputil::FPBits::exponentBias; + if (biasedExponent <= 0) { + // handle subnormals here + + // the most mantissa is currently normalized, meaning that the msb is + // one bit left of where the decimal point should go. + amountToShift = 1; + mantissaCopy = mantissa >> 1; + while (biasedExponent < 0 && mantissaCopy > 0) { + mantissaCopy = mantissaCopy >> 1; + ++amountToShift; + ++biasedExponent; + } + // If we cut off any bits to fit this number into a subnormal, then it's + // out of range for this size of float. + if ((mantissa & ((1 << amountToShift) - 1)) > 0) { + errno = ERANGE; // NOLINT + } + mantissa = shiftRightAndRound(mantissa, amountToShift); + if (mantissa == 0) { + biasedExponent = 0; + } + } else if (biasedExponent > result.maxExponent) { + // This indicates an overflow, so we make the result INF and set errno. + biasedExponent = result.maxExponent; + mantissa = 0; + errno = ERANGE; // NOLINT + } + + result.setUnbiasedExponent(biasedExponent); + result.setMantissa(mantissa); + } else { // base is 10 + BitsType outputMantissa = 0; + uint32_t outputExponent = 0; + decimalExpToFloat(mantissa, exponent, numStart, truncated, + &outputMantissa, &outputExponent); + result.setMantissa(outputMantissa); + result.setUnbiasedExponent(outputExponent); + } + + } else if ((*src | 32) == 'n') { // NaN + if ((src[1] | 32) == NAN_STRING[1] && (src[2] | 32) == NAN_STRING[2]) { + seenDigit = true; + src += 3; + BitsType NaNMantissa = 0; + if (*src == '(') { + char *tempSrc = 0; + if (isdigit(*(src + 1)) || *(src + 1) == ')') { + NaNMantissa = strtointeger(src + 1, &tempSrc, 0); + if (*tempSrc != ')') { + NaNMantissa = 0; + } else { + src = tempSrc + 1; + } + } + } + NaNMantissa |= fputil::FloatProperties::quietNaNMask; + if (result.getSign()) { + result = fputil::FPBits(result.buildNaN(NaNMantissa)); + result.setSign(true); + } else { + result.setSign(false); + result = fputil::FPBits(result.buildNaN(NaNMantissa)); + } + } + } else if ((*src | 32) == 'i') { // INF + if ((src[1] | 32) == INF_STRING[1] && (src[2] | 32) == INF_STRING[2]) { + seenDigit = true; + if (result.getSign()) + result = result.negInf(); + else + result = result.inf(); + if ((src[3] | 32) == INF_STRING[3] && (src[4] | 32) == INF_STRING[4] && + (src[5] | 32) == INF_STRING[5] && (src[6] | 32) == INF_STRING[6] && + (src[7] | 32) == INF_STRING[7]) { + // if the string is "INFINITY" then strEnd needs to be set to src + 8. + src += 8; + } else { + src += 3; + } + } + } + if (!seenDigit) { // If there is nothing to actually parse, then return 0. + if (strEnd != nullptr) + *strEnd = const_cast(originalSrc); + return T(0); + } + + if (strEnd != nullptr) + *strEnd = const_cast(src); + + return T(result); +} + +} // namespace internal +} // namespace __llvm_libc + +#endif // LIBC_SRC_SUPPORT_STR_TO_FLOAT_H diff --git a/libc/src/stdlib/CMakeLists.txt b/libc/src/stdlib/CMakeLists.txt index 6fb35aaca19d8cf3f94de373c27964aab04b0fc6..ab49c2ac6be45300f4ee2cb9c3b3bc98f303b1fe 100644 --- a/libc/src/stdlib/CMakeLists.txt +++ b/libc/src/stdlib/CMakeLists.txt @@ -8,6 +8,16 @@ add_entrypoint_object( libc.src.__support.str_conv_utils ) +add_entrypoint_object( + atof + SRCS + atof.cpp + HDRS + atof.h + DEPENDS + libc.src.__support.str_conv_utils +) + add_entrypoint_object( atol SRCS @@ -28,6 +38,26 @@ add_entrypoint_object( libc.src.__support.str_conv_utils ) +add_entrypoint_object( + strtof + SRCS + strtof.cpp + HDRS + strtof.h + DEPENDS + libc.src.__support.str_conv_utils +) + +add_entrypoint_object( + strtod + SRCS + strtod.cpp + HDRS + strtod.h + DEPENDS + libc.src.__support.str_conv_utils +) + add_entrypoint_object( strtol SRCS diff --git a/libc/src/stdlib/atof.cpp b/libc/src/stdlib/atof.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5ebae79d5744d574564e6db8c2862ba387c2aa6b --- /dev/null +++ b/libc/src/stdlib/atof.cpp @@ -0,0 +1,19 @@ +//===-- Implementation of atof --------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdlib/atof.h" +#include "src/__support/common.h" +#include "src/__support/str_to_float.h" + +namespace __llvm_libc { + +LLVM_LIBC_FUNCTION(double, atof, (const char *str)) { + return internal::strtofloatingpoint(str, nullptr); +} + +} // namespace __llvm_libc diff --git a/libc/src/stdlib/atof.h b/libc/src/stdlib/atof.h new file mode 100644 index 0000000000000000000000000000000000000000..ea531cc08d438137e6a2e838c1454eada5d37f3c --- /dev/null +++ b/libc/src/stdlib/atof.h @@ -0,0 +1,18 @@ +//===-- Implementation header for atof --------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDLIB_ATOF_H +#define LLVM_LIBC_SRC_STDLIB_ATOF_H + +namespace __llvm_libc { + +double atof(const char *str); + +} // namespace __llvm_libc + +#endif // LLVM_LIBC_SRC_STDLIB_ATOI_H diff --git a/libc/src/stdlib/strtod.cpp b/libc/src/stdlib/strtod.cpp new file mode 100644 index 0000000000000000000000000000000000000000..754918c36789353d0cf5d6dbdb9ab28de07ec8f7 --- /dev/null +++ b/libc/src/stdlib/strtod.cpp @@ -0,0 +1,20 @@ +//===-- Implementation of strtod ------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdlib/strtod.h" +#include "src/__support/common.h" +#include "src/__support/str_to_float.h" + +namespace __llvm_libc { + +LLVM_LIBC_FUNCTION(double, strtod, + (const char *__restrict str, char **__restrict str_end)) { + return internal::strtofloatingpoint(str, str_end); +} + +} // namespace __llvm_libc diff --git a/libc/src/stdlib/strtod.h b/libc/src/stdlib/strtod.h new file mode 100644 index 0000000000000000000000000000000000000000..1a8b9dcc95b9990df5c92be11cd2744a86054bed --- /dev/null +++ b/libc/src/stdlib/strtod.h @@ -0,0 +1,18 @@ +//===-- Implementation header for strtod ------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDLIB_STRTOD_H +#define LLVM_LIBC_SRC_STDLIB_STRTOD_H + +namespace __llvm_libc { + +double strtod(const char *__restrict str, char **__restrict str_end); + +} // namespace __llvm_libc + +#endif // LLVM_LIBC_SRC_STDLIB_STRTOD_H diff --git a/libc/src/stdlib/strtof.cpp b/libc/src/stdlib/strtof.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bfcb0b43908726c68017f0744123bd0fd38224 --- /dev/null +++ b/libc/src/stdlib/strtof.cpp @@ -0,0 +1,20 @@ +//===-- Implementation of strtof ------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdlib/strtof.h" +#include "src/__support/common.h" +#include "src/__support/str_to_float.h" + +namespace __llvm_libc { + +LLVM_LIBC_FUNCTION(float, strtof, + (const char *__restrict str, char **__restrict str_end)) { + return internal::strtofloatingpoint(str, str_end); +} + +} // namespace __llvm_libc diff --git a/libc/src/stdlib/strtof.h b/libc/src/stdlib/strtof.h new file mode 100644 index 0000000000000000000000000000000000000000..3ebbd1112483b0ead5fcb181a6ec16754cbe93e2 --- /dev/null +++ b/libc/src/stdlib/strtof.h @@ -0,0 +1,18 @@ +//===-- Implementation header for strtof ------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDLIB_STRTOF_H +#define LLVM_LIBC_SRC_STDLIB_STRTOF_H + +namespace __llvm_libc { + +float strtof(const char *__restrict str, char **__restrict str_end); + +} // namespace __llvm_libc + +#endif // LLVM_LIBC_SRC_STDLIB_STRTOF_H diff --git a/libc/test/src/__support/CMakeLists.txt b/libc/test/src/__support/CMakeLists.txt index 7ae4d90424d168fc5ae042c5637ca894e5fda562..85b819c23ab60d38fa29f147dcbfb12e755c6d74 100644 --- a/libc/test/src/__support/CMakeLists.txt +++ b/libc/test/src/__support/CMakeLists.txt @@ -19,3 +19,32 @@ add_libc_unittest( DEPENDS libc.src.__support.high_precision_decimal ) + +add_libc_unittest( + str_to_float_test + SUITE + libc_support_unittests + SRCS + str_to_float_test.cpp + DEPENDS + libc.src.__support.str_conv_utils +) + +add_executable( + libc_str_to_float_comparison_test + str_to_float_comparison_test.cpp +) + +target_link_libraries(libc_str_to_float_comparison_test + PRIVATE + llvmlibc +) + +set(float_test_file ${CMAKE_CURRENT_SOURCE_DIR}/str_to_float_comparison_data.txt) + +add_custom_command(TARGET libc_str_to_float_comparison_test + POST_BUILD + COMMAND $ ${float_test_file} + DEPENDS ${float_test_file} + COMMENT "Test the strtof and strtod implementations against precomputed results." + VERBATIM) diff --git a/libc/test/src/__support/str_to_float_comparison_data.txt b/libc/test/src/__support/str_to_float_comparison_data.txt new file mode 100644 index 0000000000000000000000000000000000000000..b06ef252d3e5b2bdcb0a0fa7c58cc8e3aa99f62b --- /dev/null +++ b/libc/test/src/__support/str_to_float_comparison_data.txt @@ -0,0 +1,7 @@ +# This is the sample data from https://github.com/nigeltao/parse-number-fxx-test-data +3C00 3F800000 3FF0000000000000 1 +3D00 3FA00000 3FF4000000000000 1.25 +3D9A 3FB33333 3FF6666666666666 1.4 +57B7 42F6E979 405EDD2F1A9FBE77 123.456 +622A 44454000 4088A80000000000 789 +7C00 7F800000 7FF0000000000000 123.456e789 diff --git a/libc/test/src/__support/str_to_float_comparison_test.cpp b/libc/test/src/__support/str_to_float_comparison_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5f5f71cbb1e2497fa41476bd58ff974a261cc53f --- /dev/null +++ b/libc/test/src/__support/str_to_float_comparison_test.cpp @@ -0,0 +1,172 @@ +//===-- strtofloatingpoint comparison test --------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// #include "src/__support/str_float_conv_utils.h" + +#include + +// #include "src/__support/FPUtil/FPBits.h" + +#include +#include +#include + +// The intent of this test is to read in files in the format used in this test +// dataset: https://github.com/nigeltao/parse-number-fxx-test-data +// The format is as follows: +// Hexadecimal representations of IEEE754 floats in 16 bits, 32 bits, and 64 +// bits, then the string that matches to them. + +// 3C00 3F800000 3FF0000000000000 1.0 + +// By default, float_comp_in.txt is used as the test set, but once built this +// file can be run against the larger test set. To do that, clone the repository +// with the dataset, then navigate to the compiled binary of this file (it +// should be in llvm_project/build/bin). Run the following command: +// ./libc_str_to_float_comparison_test /data/* +// It will take a few seconds to run. + +static inline uint32_t hexCharToU32(char in) { + return in > '9' ? in + 10 - 'A' : in - '0'; +} + +// Fast because it assumes inStr points to exactly 8 uppercase hex chars +static inline uint32_t fastHexToU32(const char *inStr) { + uint32_t result = 0; + result = (hexCharToU32(inStr[0]) << 28) + (hexCharToU32(inStr[1]) << 24) + + (hexCharToU32(inStr[2]) << 20) + (hexCharToU32(inStr[3]) << 16) + + (hexCharToU32(inStr[4]) << 12) + (hexCharToU32(inStr[5]) << 8) + + (hexCharToU32(inStr[6]) << 4) + hexCharToU32(inStr[7]); + return result; +} + +// Fast because it assumes inStr points to exactly 8 uppercase hex chars +static inline uint64_t fastHexToU64(const char *inStr) { + uint64_t result = 0; + result = (static_cast(fastHexToU32(inStr)) << 32) + + fastHexToU32(inStr + 8); + return result; +} + +int checkFile(char *inputFileName, int *totalFails, int *totalBitDiffs, + int *detailedBitDiffs, int *total) { + int32_t curFails = 0; // Only counts actual failures, not bitdiffs. + int32_t curBitDiffs = 0; // A bitdiff is when the expected result and actual + // result are off by +/- 1 bit. + std::string line; + std::string num; + + std::ifstream fileStream(inputFileName, std::ifstream::in); + + if (!fileStream.is_open()) { + std::cout << "file '" << inputFileName << "' failed to open. Exiting.\n"; + return 1; + } + while (getline(fileStream, line)) { + if (line[0] == '#') { + continue; + } + *total = *total + 1; + uint32_t expectedFloatRaw; + uint64_t expectedDoubleRaw; + + expectedFloatRaw = fastHexToU32(line.c_str() + 5); + expectedDoubleRaw = fastHexToU64(line.c_str() + 14); + num = line.substr(31); + + float floatResult = strtof(num.c_str(), nullptr); + + double doubleResult = strtod(num.c_str(), nullptr); + + uint32_t floatRaw = *(uint32_t *)(&floatResult); + + uint64_t doubleRaw = *(uint64_t *)(&doubleResult); + + if (!(expectedFloatRaw == floatRaw)) { + if (expectedFloatRaw == floatRaw + 1 || + expectedFloatRaw == floatRaw - 1) { + curBitDiffs++; + if (expectedFloatRaw == floatRaw + 1) { + detailedBitDiffs[0] = detailedBitDiffs[0] + 1; // float low + } else { + detailedBitDiffs[1] = detailedBitDiffs[1] + 1; // float high + } + } else { + curFails++; + } + if (curFails + curBitDiffs < 10) { + std::cout << "Float fail for '" << num << "'. Expected " << std::hex + << expectedFloatRaw << " but got " << floatRaw << "\n" + << std::dec; + } + } + + if (!(expectedDoubleRaw == doubleRaw)) { + if (expectedDoubleRaw == doubleRaw + 1 || + expectedDoubleRaw == doubleRaw - 1) { + curBitDiffs++; + if (expectedDoubleRaw == doubleRaw + 1) { + detailedBitDiffs[2] = detailedBitDiffs[2] + 1; // double low + } else { + detailedBitDiffs[3] = detailedBitDiffs[3] + 1; // double high + } + } else { + curFails++; + } + if (curFails + curBitDiffs < 10) { + std::cout << "Double fail for '" << num << "'. Expected " << std::hex + << expectedDoubleRaw << " but got " << doubleRaw << "\n" + << std::dec; + } + } + } + + fileStream.close(); + + *totalBitDiffs += curBitDiffs; + *totalFails += curFails; + + if (curFails > 1 || curBitDiffs > 1) { + return 2; + } + return 0; +} + +int main(int argc, char *argv[]) { + int result = 0; + int fails = 0; + + // Bitdiffs are cases where the expected result and actual result only differ + // by +/- the least significant bit. They are tracked seperately from larger + // failures since a bitdiff is most likely the result of a rounding error, and + // splitting them off makes them easier to track down. + int bitdiffs = 0; + int detailedBitDiffs[4] = {0, 0, 0, 0}; + + int total = 0; + for (int i = 1; i < argc; i++) { + std::cout << "Starting file " << argv[i] << "\n"; + int curResult = + checkFile(argv[i], &fails, &bitdiffs, detailedBitDiffs, &total); + if (curResult == 1) { + result = 1; + break; + } else if (curResult == 2) { + result = 2; + } + } + std::cout << "Results:\n" + << "Total significant failed conversions: " << fails << "\n" + << "Total conversions off by +/- 1 bit: " << bitdiffs << "\n" + << "\t" << detailedBitDiffs[0] << "\tfloat low\n" + << "\t" << detailedBitDiffs[1] << "\tfloat high\n" + << "\t" << detailedBitDiffs[2] << "\tdouble low\n" + << "\t" << detailedBitDiffs[3] << "\tdouble high\n" + << "Total lines: " << total << "\n"; + return result; +} diff --git a/libc/test/src/__support/str_to_float_test.cpp b/libc/test/src/__support/str_to_float_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d5cffed40a423502ad7780db08c317be16888b77 --- /dev/null +++ b/libc/test/src/__support/str_to_float_test.cpp @@ -0,0 +1,200 @@ +//===-- Unittests for str_to_float ----------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/FPUtil/FPBits.h" +#include "src/__support/str_to_float.h" + +#include "utils/UnitTest/Test.h" + +class LlvmLibcStrToFloatTest : public __llvm_libc::testing::Test { +public: + template + void EiselLemireTest( + const typename __llvm_libc::fputil::FPBits::UIntType inputMantissa, + const int32_t inputExp10, + const typename __llvm_libc::fputil::FPBits::UIntType + expectedOutputMantissa, + const uint32_t expectedOutputExp2) { + typename __llvm_libc::fputil::FPBits::UIntType actualOutputMantissa = 0; + uint32_t actualOutputExp2 = 0; + + ASSERT_TRUE(__llvm_libc::internal::eiselLemire( + inputMantissa, inputExp10, &actualOutputMantissa, &actualOutputExp2)); + EXPECT_EQ(actualOutputMantissa, expectedOutputMantissa); + EXPECT_EQ(actualOutputExp2, expectedOutputExp2); + } + + template + void SimpleDecimalConversionTest( + const char *__restrict numStart, + const typename __llvm_libc::fputil::FPBits::UIntType + expectedOutputMantissa, + const uint32_t expectedOutputExp2, const int expectedErrno = 0) { + typename __llvm_libc::fputil::FPBits::UIntType actualOutputMantissa = 0; + uint32_t actualOutputExp2 = 0; + errno = 0; + + __llvm_libc::internal::simpleDecimalConversion( + numStart, &actualOutputMantissa, &actualOutputExp2); + EXPECT_EQ(actualOutputMantissa, expectedOutputMantissa); + EXPECT_EQ(actualOutputExp2, expectedOutputExp2); + EXPECT_EQ(errno, expectedErrno); + } +}; + +TEST(LlvmLibcStrToFloatTest, LeadingZeroes) { + uint64_t testNum64 = 1; + uint32_t numOfZeroes = 63; + EXPECT_EQ(__llvm_libc::internal::leadingZeroes(0), 64u); + for (; numOfZeroes < 64; testNum64 <<= 1, numOfZeroes--) { + EXPECT_EQ(__llvm_libc::internal::leadingZeroes(testNum64), + numOfZeroes); + } + + testNum64 = 3; + numOfZeroes = 62; + for (; numOfZeroes > 63; testNum64 <<= 1, numOfZeroes--) { + EXPECT_EQ(__llvm_libc::internal::leadingZeroes(testNum64), + numOfZeroes); + } + + EXPECT_EQ(__llvm_libc::internal::leadingZeroes(0xffffffffffffffff), + 0u); + + testNum64 = 1; + numOfZeroes = 63; + for (; numOfZeroes > 63; testNum64 = (testNum64 << 1) + 1, numOfZeroes--) { + EXPECT_EQ(__llvm_libc::internal::leadingZeroes(testNum64), + numOfZeroes); + } + + uint64_t testNum32 = 1; + numOfZeroes = 31; + EXPECT_EQ(__llvm_libc::internal::leadingZeroes(0), 32u); + for (; numOfZeroes < 32; testNum32 <<= 1, numOfZeroes--) { + EXPECT_EQ(__llvm_libc::internal::leadingZeroes(testNum32), + numOfZeroes); + } + + EXPECT_EQ(__llvm_libc::internal::leadingZeroes(0xffffffff), 0u); +} + +TEST_F(LlvmLibcStrToFloatTest, EiselLemireFloat64Simple) { + EiselLemireTest(12345678901234567890u, 1, 0x1AC53A7E04BCDA, 1089); + EiselLemireTest(123, 0, 0x1EC00000000000, 1029); + EiselLemireTest(12345678901234568192u, 0, 0x156A95319D63E2, 1086); +} + +TEST_F(LlvmLibcStrToFloatTest, EiselLemireFloat64SpecificFailures) { + // These test cases have caused failures in the past. + EiselLemireTest(358416272, -33, 0x1BBB2A68C9D0B9, 941); + EiselLemireTest(2166568064000000238u, -9, 0x10246690000000, 1054); + EiselLemireTest(2794967654709307187u, 1, 0x183e132bc608c8, 1087); + EiselLemireTest(2794967654709307188u, 1, 0x183e132bc608c9, 1087); +} + +TEST_F(LlvmLibcStrToFloatTest, EiselLemireFallbackStates) { + // Check the fallback states for the algorithm: + uint32_t floatOutputMantissa = 0; + uint64_t doubleOutputMantissa = 0; + __uint128_t tooLongMantissa = 0; + uint32_t outputExp2 = 0; + + // This Eisel-Lemire implementation doesn't support long doubles yet. + ASSERT_FALSE(__llvm_libc::internal::eiselLemire( + tooLongMantissa, 0, &tooLongMantissa, &outputExp2)); + + // This number can't be evaluated by Eisel-Lemire since it's exactly 1024 away + // from both of its closest floating point approximations + // (12345678901234548736 and 12345678901234550784) + ASSERT_FALSE(__llvm_libc::internal::eiselLemire( + 12345678901234549760u, 0, &doubleOutputMantissa, &outputExp2)); + + ASSERT_FALSE(__llvm_libc::internal::eiselLemire( + 20040229, 0, &floatOutputMantissa, &outputExp2)); +} + +TEST_F(LlvmLibcStrToFloatTest, SimpleDecimalConversion64BasicWholeNumbers) { + SimpleDecimalConversionTest("123456789012345678900", 0x1AC53A7E04BCDA, + 1089); + SimpleDecimalConversionTest("123", 0x1EC00000000000, 1029); + SimpleDecimalConversionTest("12345678901234549760", 0x156A95319D63D8, + 1086); +} + +TEST_F(LlvmLibcStrToFloatTest, SimpleDecimalConversion64BasicDecimals) { + SimpleDecimalConversionTest("1.2345", 0x13c083126e978d, 1023); + SimpleDecimalConversionTest(".2345", 0x1e04189374bc6a, 1020); + SimpleDecimalConversionTest(".299792458", 0x132fccb4aca314, 1021); +} + +TEST_F(LlvmLibcStrToFloatTest, SimpleDecimalConversion64BasicExponents) { + SimpleDecimalConversionTest("1e10", 0x12a05f20000000, 1056); + SimpleDecimalConversionTest("1e-10", 0x1b7cdfd9d7bdbb, 989); + SimpleDecimalConversionTest("1e300", 0x17e43c8800759c, 2019); + SimpleDecimalConversionTest("1e-300", 0x156e1fc2f8f359, 26); +} + +TEST_F(LlvmLibcStrToFloatTest, SimpleDecimalConversion64BasicSubnormals) { + SimpleDecimalConversionTest("1e-320", 0x7e8, 0); + SimpleDecimalConversionTest("1e-308", 0x730d67819e8d2, 0); + SimpleDecimalConversionTest("2.9e-308", 0x14da6df5e4bcc8, 1); +} + +TEST_F(LlvmLibcStrToFloatTest, SimpleDecimalConversion64SubnormalRounding) { + + // Technically you can keep adding digits until you hit the truncation limit, + // but this is the shortest string that results in the maximum subnormal that + // I found. + SimpleDecimalConversionTest("2.225073858507201e-308", 0xfffffffffffff, + 0); + + // Same here, if you were to extend the max subnormal out for another 800 + // digits, incrementing any one of those digits would create a normal number. + SimpleDecimalConversionTest("2.2250738585072012e-308", + 0x10000000000000, 1); +} + +TEST_F(LlvmLibcStrToFloatTest, SimpleDecimalConversion32SpecificFailures) { + SimpleDecimalConversionTest( + "1.4012984643248170709237295832899161312802619418765e-45", 0x1, 0); +} + +TEST(LlvmLibcStrToFloatTest, SimpleDecimalConversionExtraTypes) { + uint32_t floatOutputMantissa = 0; + uint32_t outputExp2 = 0; + + errno = 0; + __llvm_libc::internal::simpleDecimalConversion( + "123456789012345678900", &floatOutputMantissa, &outputExp2); + EXPECT_EQ(floatOutputMantissa, uint32_t(0xd629d4)); + EXPECT_EQ(outputExp2, uint32_t(193)); + EXPECT_EQ(errno, 0); + + uint64_t doubleOutputMantissa = 0; + outputExp2 = 0; + + errno = 0; + __llvm_libc::internal::simpleDecimalConversion( + "123456789012345678900", &doubleOutputMantissa, &outputExp2); + EXPECT_EQ(doubleOutputMantissa, uint64_t(0x1AC53A7E04BCDA)); + EXPECT_EQ(outputExp2, uint32_t(1089)); + EXPECT_EQ(errno, 0); + + // TODO(michaelrj): Get long double support working. + + // __uint128_t longDoubleOutputMantissa = 0; + // outputExp2 = 0; + + // errno = 0; + // __llvm_libc::internal::simpleDecimalConversion( + // "123456789012345678900", &longDoubleOutputMantissa, &outputExp2); + // EXPECT_EQ(longDoubleOutputMantissa, __uint128_t(0x1AC53A7E04BCDA)); + // EXPECT_EQ(outputExp2, uint32_t(1089)); + // EXPECT_EQ(errno, 0); +} diff --git a/libc/test/src/stdlib/CMakeLists.txt b/libc/test/src/stdlib/CMakeLists.txt index ce66488bb3405c8cf4fb7818fc1c1ddf01178cbc..230f245b25608f061be878994b5c2474808de1aa 100644 --- a/libc/test/src/stdlib/CMakeLists.txt +++ b/libc/test/src/stdlib/CMakeLists.txt @@ -1,5 +1,15 @@ add_libc_testsuite(libc_stdlib_unittests) +add_libc_unittest( + atof_test + SUITE + libc_stdlib_unittests + SRCS + atof_test.cpp + DEPENDS + libc.src.stdlib.atof +) + add_libc_unittest( atoi_test SUITE @@ -30,6 +40,26 @@ add_libc_unittest( libc.src.stdlib.atoll ) +add_libc_unittest( + strtod_test + SUITE + libc_stdlib_unittests + SRCS + strtod_test.cpp + DEPENDS + libc.src.stdlib.strtod +) + +add_libc_unittest( + strtof_test + SUITE + libc_stdlib_unittests + SRCS + strtof_test.cpp + DEPENDS + libc.src.stdlib.strtof +) + add_libc_unittest( strtol_test SUITE diff --git a/libc/test/src/stdlib/atof_test.cpp b/libc/test/src/stdlib/atof_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e5de03f72cd3c9da93725e8e3c74c7615315ba1d --- /dev/null +++ b/libc/test/src/stdlib/atof_test.cpp @@ -0,0 +1,52 @@ +//===-- Unittests for atof ------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/FPUtil/FPBits.h" +#include "src/stdlib/atof.h" + +#include "utils/UnitTest/Test.h" + +#include +#include +#include + +// This is just a simple test to make sure that this function works at all. It's +// functionally identical to strtod so the bulk of the testing is there. +TEST(LlvmLibcAToFTest, SimpleTest) { + __llvm_libc::fputil::FPBits expectedFP = + __llvm_libc::fputil::FPBits(uint64_t(0x405ec00000000000)); + + errno = 0; + double result = __llvm_libc::atof("123"); + + __llvm_libc::fputil::FPBits actualFP = + __llvm_libc::fputil::FPBits(result); + + EXPECT_EQ(actualFP.bits, expectedFP.bits); + EXPECT_EQ(actualFP.getSign(), expectedFP.getSign()); + EXPECT_EQ(actualFP.getExponent(), expectedFP.getExponent()); + EXPECT_EQ(actualFP.getMantissa(), expectedFP.getMantissa()); + EXPECT_EQ(errno, 0); +} + +TEST(LlvmLibcAToFTest, FailedParsingTest) { + __llvm_libc::fputil::FPBits expectedFP = + __llvm_libc::fputil::FPBits(uint64_t(0)); + + errno = 0; + double result = __llvm_libc::atof("???"); + + __llvm_libc::fputil::FPBits actualFP = + __llvm_libc::fputil::FPBits(result); + + EXPECT_EQ(actualFP.bits, expectedFP.bits); + EXPECT_EQ(actualFP.getSign(), expectedFP.getSign()); + EXPECT_EQ(actualFP.getExponent(), expectedFP.getExponent()); + EXPECT_EQ(actualFP.getMantissa(), expectedFP.getMantissa()); + EXPECT_EQ(errno, 0); +} diff --git a/libc/test/src/stdlib/strtod_test.cpp b/libc/test/src/stdlib/strtod_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48c960d06e0cbab27cb83b927d855fe2ebd2eb2f --- /dev/null +++ b/libc/test/src/stdlib/strtod_test.cpp @@ -0,0 +1,90 @@ +//===-- Unittests for strtod ---------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/FPUtil/FPBits.h" +#include "src/stdlib/strtod.h" + +#include "utils/UnitTest/Test.h" + +#include +#include +#include + +class LlvmLibcStrToDTest : public __llvm_libc::testing::Test { +public: + void runTest(const char *inputString, const ptrdiff_t expectedStrLen, + const uint64_t expectedRawData, const int expectedErrno = 0) { + // expectedRawData is the expected double result as a uint64_t, organized + // according to IEEE754: + // + // +-- 1 Sign Bit +-- 52 Mantissa bits + // | | + // | +-------------------------+------------------------+ + // | | | + // SEEEEEEEEEEEMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM + // | | + // +----+----+ + // | + // +-- 11 Exponent Bits + // + // This is so that the result can be compared in parts. + char *strEnd = nullptr; + + __llvm_libc::fputil::FPBits expectedFP = + __llvm_libc::fputil::FPBits(expectedRawData); + + errno = 0; + double result = __llvm_libc::strtod(inputString, &strEnd); + + __llvm_libc::fputil::FPBits actualFP = + __llvm_libc::fputil::FPBits(result); + + EXPECT_EQ(strEnd - inputString, expectedStrLen); + + EXPECT_EQ(actualFP.bits, expectedFP.bits); + EXPECT_EQ(actualFP.getSign(), expectedFP.getSign()); + EXPECT_EQ(actualFP.getExponent(), expectedFP.getExponent()); + EXPECT_EQ(actualFP.getMantissa(), expectedFP.getMantissa()); + EXPECT_EQ(errno, expectedErrno); + } +}; + +TEST_F(LlvmLibcStrToDTest, SimpleTest) { + runTest("123", 3, uint64_t(0x405ec00000000000)); + + // This should fail on Eisel-Lemire, forcing a fallback to simple decimal + // conversion. + runTest("12345678901234549760", 20, uint64_t(0x43e56a95319d63d8)); + + // Found while looking for difficult test cases here: + // https://github.com/nigeltao/parse-number-fxx-test-data/blob/main/more-test-cases/golang-org-issue-36657.txt + runTest("1090544144181609348835077142190", 31, uint64_t(0x462b8779f2474dfb)); + + runTest("0x123", 5, uint64_t(0x4072300000000000)); +} + +// These are tests that have caused problems in the past. +TEST_F(LlvmLibcStrToDTest, SpecificFailures) { + runTest("3E70000000000000", 16, uint64_t(0x7FF0000000000000), ERANGE); + runTest("358416272e-33", 13, uint64_t(0x3adbbb2a68c9d0b9)); + runTest("2.16656806400000023841857910156251e9", 36, + uint64_t(0x41e0246690000001)); + runTest("27949676547093071875", 20, uint64_t(0x43f83e132bc608c9)); +} + +TEST_F(LlvmLibcStrToDTest, FuzzFailures) { + runTest("-\xff\xff\xff\xff\xff\xff\xff\x01", 0, uint64_t(0)); + runTest("-.????", 0, uint64_t(0)); + runTest("44444444444444444444444444444444444444444444444444A44444444444444444" + "44444444444*\x99\xff\xff\xff\xff", + 50, uint64_t(0x4a3e68fdd0e0b2d8)); + runTest("-NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNKNNNNNNNNNNNNNNNNNN?" + "NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN?", + 0, uint64_t(0)); + runTest("0x.666E40", 9, uint64_t(0x3fd99b9000000000)); +} diff --git a/libc/test/src/stdlib/strtof_test.cpp b/libc/test/src/stdlib/strtof_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f20cc0dfff5be57038edea655740a4d7ec64bf93 --- /dev/null +++ b/libc/test/src/stdlib/strtof_test.cpp @@ -0,0 +1,158 @@ +//===-- Unittests for strtof ---------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/FPUtil/FPBits.h" +#include "src/stdlib/strtof.h" + +#include "utils/UnitTest/Test.h" + +#include +#include +#include + +class LlvmLibcStrToFTest : public __llvm_libc::testing::Test { +public: + void runTest(const char *inputString, const ptrdiff_t expectedStrLen, + const uint32_t expectedRawData, const int expectedErrno = 0) { + // expectedRawData is the expected float result as a uint32_t, organized + // according to IEEE754: + // + // +-- 1 Sign Bit +-- 23 Mantissa bits + // | | + // | +----------+----------+ + // | | | + // SEEEEEEEEMMMMMMMMMMMMMMMMMMMMMMM + // | | + // +--+---+ + // | + // +-- 8 Exponent Bits + // + // This is so that the result can be compared in parts. + char *strEnd = nullptr; + + __llvm_libc::fputil::FPBits expectedFP = + __llvm_libc::fputil::FPBits(expectedRawData); + + errno = 0; + float result = __llvm_libc::strtof(inputString, &strEnd); + + __llvm_libc::fputil::FPBits actualFP = + __llvm_libc::fputil::FPBits(result); + + EXPECT_EQ(strEnd - inputString, expectedStrLen); + + EXPECT_EQ(actualFP.bits, expectedFP.bits); + EXPECT_EQ(actualFP.getSign(), expectedFP.getSign()); + EXPECT_EQ(actualFP.getExponent(), expectedFP.getExponent()); + EXPECT_EQ(actualFP.getMantissa(), expectedFP.getMantissa()); + EXPECT_EQ(errno, expectedErrno); + } +}; + +// This is the set of tests that I have working (verified correct when compared +// to system libc). This is here so I don't break more things when I try to fix +// them. + +TEST_F(LlvmLibcStrToFTest, BasicDecimalTests) { + runTest("1", 1, 0x3f800000); + runTest("123", 3, 0x42f60000); + runTest("1234567890", 10, 0x4e932c06u); + runTest("123456789012345678901", 21, 0x60d629d4); + runTest("0.1", 3, 0x3dcccccdu); + runTest(".1", 2, 0x3dcccccdu); + runTest("-0.123456789", 12, 0xbdfcd6eau); + runTest("0.11111111111111111111", 22, 0x3de38e39u); + runTest("0.0000000000000000000000001", 27, 0x15f79688u); +} + +TEST_F(LlvmLibcStrToFTest, DecimalOutOfRangeTests) { + runTest("555E36", 6, 0x7f800000, ERANGE); + runTest("1e-10000", 8, 0x0, ERANGE); +} + +TEST_F(LlvmLibcStrToFTest, DecimalsWithRoundingProblems) { + runTest("20040229", 8, 0x4b98e512); + runTest("20040401", 8, 0x4b98e568); + runTest("9E9", 3, 0x50061c46); +} + +TEST_F(LlvmLibcStrToFTest, DecimalSubnormals) { + runTest("1.4012984643248170709237295832899161312802619418765e-45", 55, 0x1); +} + +TEST_F(LlvmLibcStrToFTest, DecimalWithLongExponent) { + runTest("1e2147483648", 12, 0x7f800000, ERANGE); + runTest("1e2147483646", 12, 0x7f800000, ERANGE); + runTest("100e2147483646", 14, 0x7f800000, ERANGE); + runTest("1e-2147483647", 13, 0x0, ERANGE); + runTest("1e-2147483649", 13, 0x0, ERANGE); +} + +TEST_F(LlvmLibcStrToFTest, BasicHexadecimalTests) { + runTest("0x1", 3, 0x3f800000); + runTest("0x10", 4, 0x41800000); + runTest("0x11", 4, 0x41880000); + runTest("0x0.1234", 8, 0x3d91a000); +} + +TEST_F(LlvmLibcStrToFTest, HexadecimalSubnormalTests) { + runTest("0x0.0000000000000000000000000000000002", 38, 0x4000); + + // This is the largest subnormal number as represented in hex + runTest("0x0.00000000000000000000000000000003fffff8", 42, 0x7fffff); +} + +TEST_F(LlvmLibcStrToFTest, HexadecimalSubnormalRoundingTests) { + // This is the largest subnormal number that gets rounded down to 0 (as a + // float) + runTest("0x0.00000000000000000000000000000000000004", 42, 0x0, ERANGE); + + // This is slightly larger, and thus rounded up + runTest("0x0.000000000000000000000000000000000000041", 43, 0x00000001, + ERANGE); + + // These check that we're rounding to even properly + runTest("0x0.0000000000000000000000000000000000000b", 42, 0x00000001, ERANGE); + runTest("0x0.0000000000000000000000000000000000000c", 42, 0x00000002, ERANGE); +} + +TEST_F(LlvmLibcStrToFTest, HexadecimalNormalRoundingTests) { + // This also checks the round to even behavior by checking three adjacent + // numbers. + // This gets rounded down to even + runTest("0x123456500", 11, 0x4f91a2b2); + // This doesn't get rounded at all + runTest("0x123456600", 11, 0x4f91a2b3); + // This gets rounded up to even + runTest("0x123456700", 11, 0x4f91a2b4); +} + +TEST_F(LlvmLibcStrToFTest, HexadecimalOutOfRangeTests) { + runTest("0x123456789123456789123456789123456789", 38, 0x7f800000, ERANGE); + runTest("-0x123456789123456789123456789123456789", 39, 0xff800000, ERANGE); + runTest("0x0.00000000000000000000000000000000000001", 42, 0x0, ERANGE); +} + +TEST_F(LlvmLibcStrToFTest, InfTests) { + runTest("INF", 3, 0x7f800000); + runTest("INFinity", 8, 0x7f800000); + runTest("infnity", 3, 0x7f800000); + runTest("infinit", 3, 0x7f800000); + runTest("infinfinit", 3, 0x7f800000); + runTest("innf", 0, 0x0); + runTest("-inf", 4, 0xff800000); + runTest("-iNfInItY", 9, 0xff800000); +} + +TEST_F(LlvmLibcStrToFTest, NaNTests) { + runTest("NaN", 3, 0x7fc00000); + runTest("-nAn", 4, 0xffc00000); + runTest("NaN()", 5, 0x7fc00000); + runTest("NaN(1234)", 9, 0x7fc004d2); + runTest("NaN( 1234)", 3, 0x7fc00000); +} diff --git a/libcxx/CMakeLists.txt b/libcxx/CMakeLists.txt index 9bc955b741f769be6d226ed103c9e5e31c249feb..51951e50e16a6c86835485b14fd2c652e460f1a4 100644 --- a/libcxx/CMakeLists.txt +++ b/libcxx/CMakeLists.txt @@ -14,6 +14,8 @@ cmake_minimum_required(VERSION 3.13.4) set(CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake" "${CMAKE_CURRENT_SOURCE_DIR}/cmake/Modules" + "${CMAKE_CURRENT_SOURCE_DIR}/../cmake" + "${CMAKE_CURRENT_SOURCE_DIR}/../cmake/Modules" ${CMAKE_MODULE_PATH} ) diff --git a/libcxx/cmake/Modules/HandleCompilerRT.cmake b/libcxx/cmake/Modules/HandleCompilerRT.cmake deleted file mode 100644 index 1ce2565749418f3239b3bcc2269a692afb74852d..0000000000000000000000000000000000000000 --- a/libcxx/cmake/Modules/HandleCompilerRT.cmake +++ /dev/null @@ -1,64 +0,0 @@ -function(find_compiler_rt_library name dest) - if (NOT DEFINED LIBCXX_COMPILE_FLAGS) - message(FATAL_ERROR "LIBCXX_COMPILE_FLAGS must be defined when using this function") - endif() - set(dest "" PARENT_SCOPE) - set(CLANG_COMMAND ${CMAKE_CXX_COMPILER} ${LIBCXX_COMPILE_FLAGS} - "--rtlib=compiler-rt" "--print-libgcc-file-name") - if (CMAKE_CXX_COMPILER_ID MATCHES Clang AND CMAKE_CXX_COMPILER_TARGET) - list(APPEND CLANG_COMMAND "--target=${CMAKE_CXX_COMPILER_TARGET}") - endif() - get_property(LIBCXX_CXX_FLAGS CACHE CMAKE_CXX_FLAGS PROPERTY VALUE) - string(REPLACE " " ";" LIBCXX_CXX_FLAGS "${LIBCXX_CXX_FLAGS}") - list(APPEND CLANG_COMMAND ${LIBCXX_CXX_FLAGS}) - execute_process( - COMMAND ${CLANG_COMMAND} - RESULT_VARIABLE HAD_ERROR - OUTPUT_VARIABLE LIBRARY_FILE - ) - string(STRIP "${LIBRARY_FILE}" LIBRARY_FILE) - file(TO_CMAKE_PATH "${LIBRARY_FILE}" LIBRARY_FILE) - string(REPLACE "builtins" "${name}" LIBRARY_FILE "${LIBRARY_FILE}") - if (NOT HAD_ERROR AND EXISTS "${LIBRARY_FILE}") - message(STATUS "Found compiler-rt library: ${LIBRARY_FILE}") - set(${dest} "${LIBRARY_FILE}" PARENT_SCOPE) - else() - message(STATUS "Failed to find compiler-rt library") - endif() -endfunction() - -function(find_compiler_rt_dir dest) - if (NOT DEFINED LIBCXX_COMPILE_FLAGS) - message(FATAL_ERROR "LIBCXX_COMPILE_FLAGS must be defined when using this function") - endif() - set(dest "" PARENT_SCOPE) - if (APPLE) - set(CLANG_COMMAND ${CMAKE_CXX_COMPILER} ${LIBCXX_COMPILE_FLAGS} - "-print-file-name=lib") - execute_process( - COMMAND ${CLANG_COMMAND} - RESULT_VARIABLE HAD_ERROR - OUTPUT_VARIABLE LIBRARY_DIR - ) - string(STRIP "${LIBRARY_DIR}" LIBRARY_DIR) - file(TO_CMAKE_PATH "${LIBRARY_DIR}" LIBRARY_DIR) - set(LIBRARY_DIR "${LIBRARY_DIR}/darwin") - else() - set(CLANG_COMMAND ${CMAKE_CXX_COMPILER} ${LIBCXX_COMPILE_FLAGS} - "--rtlib=compiler-rt" "--print-libgcc-file-name") - execute_process( - COMMAND ${CLANG_COMMAND} - RESULT_VARIABLE HAD_ERROR - OUTPUT_VARIABLE LIBRARY_FILE - ) - string(STRIP "${LIBRARY_FILE}" LIBRARY_FILE) - file(TO_CMAKE_PATH "${LIBRARY_FILE}" LIBRARY_FILE) - get_filename_component(LIBRARY_DIR "${LIBRARY_FILE}" DIRECTORY) - endif() - if (NOT HAD_ERROR AND EXISTS "${LIBRARY_DIR}") - message(STATUS "Found compiler-rt directory: ${LIBRARY_DIR}") - set(${dest} "${LIBRARY_DIR}" PARENT_SCOPE) - else() - message(STATUS "Failed to find compiler-rt directory") - endif() -endfunction() diff --git a/libcxx/cmake/config-ix.cmake b/libcxx/cmake/config-ix.cmake index a85e3b8db173f4432f35e4b8b639728337c84e49..ce8ae1bae97fbc4cbf9fca74d03cc056dd402137 100644 --- a/libcxx/cmake/config-ix.cmake +++ b/libcxx/cmake/config-ix.cmake @@ -48,8 +48,10 @@ if (LIBCXX_SUPPORTS_NOSTDLIBXX_FLAG OR LIBCXX_SUPPORTS_NODEFAULTLIBS_FLAG) list(APPEND CMAKE_REQUIRED_LIBRARIES c) endif () if (LIBCXX_USE_COMPILER_RT) - set(CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS} -rtlib=compiler-rt") + cmake_push_check_state() + set(CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS} ${LIBCXX_COMPILE_FLAGS}") find_compiler_rt_library(builtins LIBCXX_BUILTINS_LIBRARY) + cmake_pop_check_state() list(APPEND CMAKE_REQUIRED_LIBRARIES "${LIBCXX_BUILTINS_LIBRARY}") elseif (LIBCXX_HAS_GCC_LIB) list(APPEND CMAKE_REQUIRED_LIBRARIES gcc) diff --git a/libcxx/docs/BuildingLibcxx.rst b/libcxx/docs/BuildingLibcxx.rst index a0128b84eeb4354b050b153719e9e050804c1a95..32727c92e21b8dd6006583a4a110aa6bd038cc25 100644 --- a/libcxx/docs/BuildingLibcxx.rst +++ b/libcxx/docs/BuildingLibcxx.rst @@ -25,50 +25,58 @@ libc++ :ref:`here `. The default build ================= -By default, libc++ and libc++abi are built as sub-projects of the LLVM project. -This can be achieved with the usual CMake invocation: +The default way of building libc++, libc++abi and libunwind is to root the CMake +invocation at ``/runtimes``. While those projects are under the LLVM +umbrella, they are different in nature from other build tools, so it makes sense +to treat them as a separate set of entities. The default build can be achieved +with the following CMake invocation: .. code-block:: bash $ git clone https://github.com/llvm/llvm-project.git $ cd llvm-project $ mkdir build - $ cmake -G Ninja -S llvm -B build -DLLVM_ENABLE_PROJECTS="libcxx;libcxxabi" # Configure - $ ninja -C build cxx cxxabi # Build - $ ninja -C build check-cxx check-cxxabi # Test - $ ninja -C build install-cxx install-cxxabi # Install + $ cmake -G Ninja -S runtimes -B build -DLLVM_ENABLE_RUNTIMES="libcxx;libcxxabi;libunwind" # Configure + $ ninja -C build cxx cxxabi unwind # Build + $ ninja -C build check-cxx check-cxxabi check-unwind # Test + $ ninja -C build install-cxx install-cxxabi install-unwind # Install .. note:: See :ref:`CMake Options` below for more configuration options. -After building the ``install-cxx`` and ``install-cxxabi`` targets, shared libraries -for libc++ and libc++abi should now be present in ``/lib``, and -headers in ``/include/c++/v1``. See :ref:`using an alternate -libc++ installation ` for information on how to use this libc++ over -the default one. +After building the various ``install-XXX`` targets, shared libraries for libc++, libc++abi and +libunwind should now be present in ``/lib``, and headers in +``/include/c++/v1``. See :ref:`using an alternate libc++ installation +` for information on how to use this libc++ over the default one. -In the default configuration, libc++ and libc++abi will be built using the compiler available -by default on your system. It is also possible to bootstrap Clang and build libc++ with it. +In the default configuration, the runtimes will be built using the compiler available by default +on your system. Of course, you can change what compiler is being used with the usual CMake +variables. If you wish to build the runtimes from a just-built Clang, the bootstrapping build +explained below makes this task easy. Bootstrapping build =================== -It is also possible to build Clang and then build libc++ and libc++abi using that -just-built compiler. This is the correct way to build libc++ when putting together -a toolchain, or when the system compiler is not adequate to build libc++ (too old, -unsupported, etc.). This type of build is also commonly called a "Runtimes build": +It is possible to build Clang and then build the runtimes using that just-built compiler in a +single CMake invocation. This is usually the correct way to build the runtimes when putting together +a toolchain, or when the system compiler is not adequate to build them (too old, unsupported, etc.). +To do this, use the following CMake invocation, and in particular notice how we're now rooting the +CMake invocation at ``/llvm``: .. code-block:: bash $ mkdir build - $ cmake -G Ninja -S llvm -B build -DLLVM_ENABLE_PROJECTS="clang" \ # Configure - -DLLVM_ENABLE_RUNTIMES="libcxx;libcxxabi" \ + $ cmake -G Ninja -S llvm -B build -DLLVM_ENABLE_PROJECTS="clang" \ # Configure + -DLLVM_ENABLE_RUNTIMES="libcxx;libcxxabi;libunwind" \ -DLLVM_RUNTIME_TARGETS="" - $ ninja -C build runtimes # Build - $ ninja -C build check-runtimes # Test - $ ninja -C build install-runtimes # Install + $ ninja -C build runtimes # Build + $ ninja -C build check-runtimes # Test + $ ninja -C build install-runtimes # Install +.. note:: + This type of build is also commonly called a "Runtimes build", but we would like to move + away from that terminology, which is too confusing. Support for Windows =================== diff --git a/libcxx/docs/ReleaseNotes.rst b/libcxx/docs/ReleaseNotes.rst index 1ffd5b4e332fcf9fe1a87d0b5c43e622476a68c4..7ad192361b09c927a675ed9c15dac76b93633cdc 100644 --- a/libcxx/docs/ReleaseNotes.rst +++ b/libcxx/docs/ReleaseNotes.rst @@ -42,23 +42,17 @@ New Features is incomplete. Some functions are known to be inefficient; both in memory usage and performance. The implementation is considered experimental and isn't considered ABI stable. + - There's a new CMake option ``LIBCXX_ENABLE_UNICODE`` to disable Unicode support in the ```` header. This only affects the estimation of the output width of the format functions. -API Changes ------------ - - Support for building libc++ on top of a C Standard Library that does not support ``wchar_t`` was added. This is useful for building libc++ in an embedded setting, and it adds itself to the various freestanding-friendly options provided by libc++. -Build System Changes --------------------- - -- Building the libc++ shared or static library requires a C++ 20 capable compiler. - Use ``-DLLVM_ENABLE_PROJECTS='clang;compiler-rt' -DLLVM_ENABLE_RUNTIMES='libcxx;libcxxabi'`` - to build libc++ using a fresh build of Clang. +API Changes +----------- - The functions ``std::atomic::fetch_(add|sub)`` and ``std::atomic_fetch_(add|sub)`` no longer accept a function pointer. While @@ -77,3 +71,48 @@ Build System Changes Calls to these functions where the template argument was deduced by the compiler are unaffected by this change. + +- The functions ``std::allocator::allocate`` and + ``std::experimental::pmr::polymorphic_allocator::allocate`` now throw + an exception of type ``std::bad_array_new_length`` when the requested size + exceeds the maximum supported size, as required by the C++ standard. + Previously the type ``std::length_error`` was used. + +Build System Changes +-------------------- + +- Building the libc++ shared or static library requires a C++ 20 capable compiler. + Consider using a Bootstrapping build to build libc++ with a fresh Clang if you + can't use the system compiler to build libc++ anymore. + +- Historically, there has been numerous ways of building libc++ and libc++abi. This has + culminated in over 5 different ways to build the runtimes, which made it impossible to + maintain with a good level of support. Starting with this release, the runtimes support + exactly two ways of being built, which should cater to all use-cases. Furthermore, + these builds are as lightweight as possible and will work consistently even when targetting + embedded platforms, which used not to be the case. Please see the documentation on building + libc++ to see those two ways of building and migrate over to the appropriate build instructions + as soon as possible. + + All other ways to build are deprecated and will not be supported in the next release. + We understand that making these changes can be daunting. For that reason, here's a + summary of how to migrate from the two most common ways to build: + + - If you were rooting your CMake invocation at ``/llvm`` and passing ``-DLLVM_ENABLE_PROJECTS=<...>`` + (which was the previously advertised way to build the runtimes), please simply root your CMake invocation at + ``/runtimes`` and pass ``-DLLVM_ENABLE_RUNTIMES=<...>``. + + - If you were doing two CMake invocations, one rooted at ``/libcxx`` and one rooted at + ``/libcxxabi`` (this used to be called a "Standalone build"), please move them to a + single invocation like so: + + .. code-block:: bash + + $ cmake -S /libcxx -B libcxx-build + $ cmake -S /libcxxabi -B libcxxabi-build + + should become + + .. code-block:: bash + + $ cmake -S /runtimes -B build -DLLVM_ENABLE_RUNTIMES="libcxx;libcxxabi" diff --git a/libcxx/docs/Status/Cxx20Issues.csv b/libcxx/docs/Status/Cxx20Issues.csv index e2c994019424c30f861390f6eb820b7078317e42..410cedcaa53ded55b308991babc1103c9c25688c 100644 --- a/libcxx/docs/Status/Cxx20Issues.csv +++ b/libcxx/docs/Status/Cxx20Issues.csv @@ -108,7 +108,7 @@ "`3025 `__","Map-like container deduction guides should use ``pair``\ , not ``pair``\ ","San Diego","|Complete|","" "`3031 `__","Algorithms and predicates with non-const reference arguments","San Diego","","" "`3037 `__","``polymorphic_allocator``\ and incomplete types","San Diego","","" -"`3038 `__","``polymorphic_allocator::allocate``\ should not allow integer overflow to create vulnerabilities","San Diego","","" +"`3038 `__","``polymorphic_allocator::allocate``\ should not allow integer overflow to create vulnerabilities","San Diego","|Complete|","14.0" "`3054 `__","``uninitialized_copy``\ appears to not be able to meet its exception-safety guarantee","San Diego","","" "`3065 `__","LWG 2989 missed that all ``path``\ 's other operators should be hidden friends as well","San Diego","|Complete|","" "`3096 `__","``path::lexically_relative``\ is confused by trailing slashes","San Diego","|Complete|","" @@ -162,7 +162,7 @@ "","","","","" "`3231 `__","``year_month_day_last::day``\ specification does not cover ``!ok()``\ values","Belfast","|Nothing To Do|","" "`3225 `__","``zoned_time``\ converting constructor shall not be ``noexcept``\ ","Belfast","","","|chrono|" -"`3190 `__","``std::allocator::allocate``\ sometimes returns too little storage","Belfast","","" +"`3190 `__","``std::allocator::allocate``\ sometimes returns too little storage","Belfast","|Complete|","14.0" "`3218 `__","Modifier for ``%d``\ parse flag does not match POSIX and ``format``\ specification","Belfast","","","|chrono| |format|" "`3224 `__","``zoned_time``\ constructor from ``TimeZonePtr``\ does not specify initialization of ``tp_``\ ","Belfast","","","|chrono|" "`3230 `__","Format specifier ``%y/%Y``\ is missing locale alternative versions","Belfast","","","|chrono| |format|" @@ -200,7 +200,7 @@ "`3201 `__","``lerp``\ should be marked as ``noexcept``\ ","Prague","|Complete|","" "`3226 `__","``zoned_time``\ constructor from ``string_view``\ should accept ``zoned_time``\ ","Prague","","","|chrono|" "`3233 `__","Broken requirements for ``shared_ptr``\ converting constructors","Prague","","" -"`3237 `__","LWG 3038 and 3190 have inconsistent PRs","Prague","","" +"`3237 `__","LWG 3038 and 3190 have inconsistent PRs","Prague","|Complete|","14.0" "`3238 `__","Insufficiently-defined behavior of ``std::function``\ deduction guides","Prague","","" "`3242 `__","``std::format``\ : missing rules for ``arg-id``\ in ``width``\ and ``precision``\ ","Prague","|Complete|","Clang 14","|format|" "`3243 `__","``std::format``\ and negative zeroes","Prague","","","|format|" diff --git a/libcxx/include/__memory/allocator.h b/libcxx/include/__memory/allocator.h index f99bee2b8f1b9691effe9dd76d12eb815bb5ecf8..283212fb703dd15658a7f358ed2e2c4ad9dec05f 100644 --- a/libcxx/include/__memory/allocator.h +++ b/libcxx/include/__memory/allocator.h @@ -98,8 +98,7 @@ public: _LIBCPP_NODISCARD_AFTER_CXX17 _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17 _Tp* allocate(size_t __n) { if (__n > allocator_traits::max_size(*this)) - __throw_length_error("allocator::allocate(size_t n)" - " 'n' exceeds maximum supported size"); + __throw_bad_array_new_length(); if (__libcpp_is_constant_evaluated()) { return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp))); } else { @@ -181,8 +180,7 @@ public: _LIBCPP_NODISCARD_AFTER_CXX17 _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17 const _Tp* allocate(size_t __n) { if (__n > allocator_traits::max_size(*this)) - __throw_length_error("allocator::allocate(size_t n)" - " 'n' exceeds maximum supported size"); + __throw_bad_array_new_length(); if (__libcpp_is_constant_evaluated()) { return static_cast(::operator new(__n * sizeof(_Tp))); } else { diff --git a/libcxx/include/__ranges/reverse_view.h b/libcxx/include/__ranges/reverse_view.h index ad88dc71380531adcc90ba44ad55dbc5b779efdb..618be80457b6e0e12ac8a1d6335e8bbe99dc28aa 100644 --- a/libcxx/include/__ranges/reverse_view.h +++ b/libcxx/include/__ranges/reverse_view.h @@ -19,8 +19,11 @@ #include <__ranges/concepts.h> #include <__ranges/enable_borrowed_range.h> #include <__ranges/non_propagating_cache.h> +#include <__ranges/range_adaptor.h> #include <__ranges/size.h> +#include <__ranges/subrange.h> #include <__ranges/view_interface.h> +#include <__utility/forward.h> #include <__utility/move.h> #include @@ -104,6 +107,80 @@ namespace ranges { template inline constexpr bool enable_borrowed_range> = enable_borrowed_range<_Tp>; + + namespace views { + namespace __reverse { + template + constexpr bool __is_reverse_view = false; + + template + constexpr bool __is_reverse_view> = true; + + template + constexpr bool __is_sized_reverse_subrange = false; + + template + constexpr bool __is_sized_reverse_subrange, reverse_iterator<_Iter>, subrange_kind::sized>> = true; + + template + constexpr bool __is_unsized_reverse_subrange = false; + + template + constexpr bool __is_unsized_reverse_subrange, reverse_iterator<_Iter>, _Kind>> = _Kind == subrange_kind::unsized; + + template + struct __unwrapped_reverse_subrange { + using type = void; // avoid SFINAE-ing out the overload below -- let the concept requirements do it for better diagnostics + }; + + template + struct __unwrapped_reverse_subrange, reverse_iterator<_Iter>, _Kind>> { + using type = subrange<_Iter, _Iter, _Kind>; + }; + + struct __fn : __range_adaptor_closure<__fn> { + template + requires __is_reverse_view> + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI + constexpr auto operator()(_Range&& __range) const + noexcept(noexcept(_VSTD::forward<_Range>(__range).base())) + -> decltype( _VSTD::forward<_Range>(__range).base()) + { return _VSTD::forward<_Range>(__range).base(); } + + template>::type> + requires __is_sized_reverse_subrange> + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI + constexpr auto operator()(_Range&& __range) const + noexcept(noexcept(_UnwrappedSubrange(__range.end().base(), __range.begin().base(), __range.size()))) + -> decltype( _UnwrappedSubrange(__range.end().base(), __range.begin().base(), __range.size())) + { return _UnwrappedSubrange(__range.end().base(), __range.begin().base(), __range.size()); } + + template>::type> + requires __is_unsized_reverse_subrange> + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI + constexpr auto operator()(_Range&& __range) const + noexcept(noexcept(_UnwrappedSubrange(__range.end().base(), __range.begin().base()))) + -> decltype( _UnwrappedSubrange(__range.end().base(), __range.begin().base())) + { return _UnwrappedSubrange(__range.end().base(), __range.begin().base()); } + + template + requires (!__is_reverse_view> && + !__is_sized_reverse_subrange> && + !__is_unsized_reverse_subrange>) + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI + constexpr auto operator()(_Range&& __range) const + noexcept(noexcept(reverse_view{_VSTD::forward<_Range>(__range)})) + -> decltype( reverse_view{_VSTD::forward<_Range>(__range)}) + { return reverse_view{_VSTD::forward<_Range>(__range)}; } + }; + } + + inline namespace __cpo { + inline constexpr auto reverse = __reverse::__fn{}; + } + } // namespace views } // namespace ranges #endif // !defined(_LIBCPP_HAS_NO_RANGES) diff --git a/libcxx/include/experimental/memory_resource b/libcxx/include/experimental/memory_resource index 816d21f513681df9f1059c18b4c4d5dafcb49994..75e502d78c2db4ab1792711906b500490f7d77cf 100644 --- a/libcxx/include/experimental/memory_resource +++ b/libcxx/include/experimental/memory_resource @@ -183,11 +183,8 @@ public: // 8.6.3, memory.polymorphic.allocator.mem _LIBCPP_INLINE_VISIBILITY _ValueType* allocate(size_t __n) { - if (__n > __max_size()) { - __throw_length_error( - "std::experimental::pmr::polymorphic_allocator::allocate(size_t n)" - " 'n' exceeds maximum supported size"); - } + if (__n > __max_size()) + __throw_bad_array_new_length(); return static_cast<_ValueType*>( __res_->allocate(__n * sizeof(_ValueType), _LIBCPP_ALIGNOF(_ValueType)) ); @@ -384,11 +381,8 @@ public: private: virtual void * do_allocate(size_t __bytes, size_t) { - if (__bytes > __max_size()) { - __throw_length_error( - "std::experimental::pmr::resource_adaptor::do_allocate(size_t bytes, size_t align)" - " 'bytes' exceeds maximum supported size"); - } + if (__bytes > __max_size()) + __throw_bad_array_new_length(); size_t __s = __aligned_allocation_size(__bytes, _MaxAlign) / _MaxAlign; return __alloc_.allocate(__s); } diff --git a/libcxx/include/new b/libcxx/include/new index 2d1417a97586d1ada8454e8820085ebc43dd36bd..711b3ccd225fda5654d3fd43f88de4c81847f3cc 100644 --- a/libcxx/include/new +++ b/libcxx/include/new @@ -149,6 +149,16 @@ _LIBCPP_FUNC_VIS new_handler get_new_handler() _NOEXCEPT; _LIBCPP_NORETURN _LIBCPP_FUNC_VIS void __throw_bad_alloc(); // not in C++ spec +_LIBCPP_NORETURN inline _LIBCPP_INLINE_VISIBILITY +void __throw_bad_array_new_length() +{ +#ifndef _LIBCPP_NO_EXCEPTIONS + throw bad_array_new_length(); +#else + _VSTD::abort(); +#endif +} + #if !defined(_LIBCPP_HAS_NO_LIBRARY_ALIGNED_ALLOCATION) && \ !defined(_LIBCPP_ABI_VCRUNTIME) #ifndef _LIBCPP_CXX03_LANG diff --git a/libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist b/libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist index 927b36f59451166526640908f2b3d6232a134554..fd20a7d97fda118db1f711b6285ef407b12f59d3 100644 --- a/libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist +++ b/libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist @@ -7,6 +7,8 @@ {'is_defined': False, 'name': '_ZNSt13runtime_errorD2Ev', 'type': 'FUNC'} {'is_defined': False, 'name': '_ZNSt14overflow_errorD1Ev', 'type': 'FUNC'} {'is_defined': False, 'name': '_ZNSt16invalid_argumentD1Ev', 'type': 'FUNC'} +{'is_defined': False, 'name': '_ZNSt20bad_array_new_lengthC1Ev', 'type': 'FUNC'} +{'is_defined': False, 'name': '_ZNSt20bad_array_new_lengthD1Ev', 'type': 'FUNC'} {'is_defined': False, 'name': '_ZNSt8bad_castC1Ev', 'type': 'FUNC'} {'is_defined': False, 'name': '_ZNSt8bad_castD1Ev', 'type': 'FUNC'} {'is_defined': False, 'name': '_ZNSt8bad_castD2Ev', 'type': 'FUNC'} @@ -20,6 +22,7 @@ {'is_defined': False, 'name': '_ZTISt13runtime_error', 'size': 0, 'type': 'OBJECT'} {'is_defined': False, 'name': '_ZTISt14overflow_error', 'size': 0, 'type': 'OBJECT'} {'is_defined': False, 'name': '_ZTISt16invalid_argument', 'size': 0, 'type': 'OBJECT'} +{'is_defined': False, 'name': '_ZTISt20bad_array_new_length', 'size': 0, 'type': 'OBJECT'} {'is_defined': False, 'name': '_ZTISt8bad_cast', 'size': 0, 'type': 'OBJECT'} {'is_defined': False, 'name': '_ZTISt9bad_alloc', 'size': 0, 'type': 'OBJECT'} {'is_defined': False, 'name': '_ZTISt9exception', 'size': 0, 'type': 'OBJECT'} diff --git a/libcxx/src/CMakeLists.txt b/libcxx/src/CMakeLists.txt index 0bcfb1776271caa7945724c8caede9fb55201649..b5a870a5a499236ff71cf1609f30e353924cbc3f 100644 --- a/libcxx/src/CMakeLists.txt +++ b/libcxx/src/CMakeLists.txt @@ -163,7 +163,8 @@ if (APPLE AND LLVM_USE_SANITIZER) message(WARNING "LLVM_USE_SANITIZER=${LLVM_USE_SANITIZER} is not supported on OS X") endif() if (LIBFILE) - find_compiler_rt_dir(LIBDIR) + find_compiler_rt_library(builtins LIBCXX_BUILTINS_LIBRARY) + get_filename_component(LIBDIR "${LIBCXX_BUILTINS_LIBRARY}" DIRECTORY) if (NOT IS_DIRECTORY "${LIBDIR}") message(FATAL_ERROR "Cannot find compiler-rt directory on OS X required for LLVM_USE_SANITIZER") endif() diff --git a/libcxx/test/std/experimental/memory/memory.polymorphic.allocator.class/memory.polymorphic.allocator.mem/allocate.pass.cpp b/libcxx/test/std/experimental/memory/memory.polymorphic.allocator.class/memory.polymorphic.allocator.mem/allocate.pass.cpp index 53c7c31443d34492ccb9f73067c97aec398de193..779c0eb231c64284edcfbebeac7fe719682fa0a6 100644 --- a/libcxx/test/std/experimental/memory/memory.polymorphic.allocator.class/memory.polymorphic.allocator.mem/allocate.pass.cpp +++ b/libcxx/test/std/experimental/memory/memory.polymorphic.allocator.class/memory.polymorphic.allocator.mem/allocate.pass.cpp @@ -61,11 +61,11 @@ void testAllocForSizeThrows() { size_t sizeTypeMax = std::numeric_limits::max(); if (maxSize != sizeTypeMax) { - // Test that allocating size_t(~0) throws bad alloc. + // Test that allocating size_t(~0) throws bad_array_new_length. try { a.allocate(sizeTypeMax); assert(false); - } catch (std::exception const&) { + } catch (std::bad_array_new_length const&) { } // Test that allocating even one more than the max size does throw. @@ -73,7 +73,7 @@ void testAllocForSizeThrows() { try { a.allocate(overSize); assert(false); - } catch (std::exception const&) { + } catch (std::bad_array_new_length const&) { } } } diff --git a/libcxx/test/std/experimental/memory/memory.resource.adaptor/memory.resource.adaptor.mem/do_allocate_and_deallocate.pass.cpp b/libcxx/test/std/experimental/memory/memory.resource.adaptor/memory.resource.adaptor.mem/do_allocate_and_deallocate.pass.cpp index 40ffbb1cbdbb1c91fa224aab65769513df5897ea..3c17520aeff2e97878d28b090471c96fb6ed4514 100644 --- a/libcxx/test/std/experimental/memory/memory.resource.adaptor/memory.resource.adaptor.mem/do_allocate_and_deallocate.pass.cpp +++ b/libcxx/test/std/experimental/memory/memory.resource.adaptor/memory.resource.adaptor.mem/do_allocate_and_deallocate.pass.cpp @@ -99,7 +99,7 @@ void check_alloc_max_size() { try { m1.allocate(size); assert(false); - } catch (std::exception const&) { + } catch (std::bad_array_new_length const&) { } } #endif diff --git a/libcxx/test/std/ranges/range.adaptors/range.reverse/adaptor.nodiscard.verify.cpp b/libcxx/test/std/ranges/range.adaptors/range.reverse/adaptor.nodiscard.verify.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1a854446d010fead1cb2ba29eda80db6fd8b02f1 --- /dev/null +++ b/libcxx/test/std/ranges/range.adaptors/range.reverse/adaptor.nodiscard.verify.cpp @@ -0,0 +1,25 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17 +// UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges +// REQUIRES: libc++ + +// Test the libc++ extension that std::views::reverse is marked as [[nodiscard]] to avoid +// the potential for user mistakenly thinking they're calling an algorithm. + +#include + +void test() { + int range[] = {1, 2, 3}; + + std::views::reverse(range); // expected-warning {{ignoring return value of function declared with 'nodiscard' attribute}} + range | std::views::reverse; // expected-warning {{ignoring return value of function declared with 'nodiscard' attribute}} + std::views::reverse | std::views::reverse; // expected-warning {{ignoring return value of function declared with 'nodiscard' attribute}} +} diff --git a/libcxx/test/std/ranges/range.adaptors/range.reverse/adaptor.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.reverse/adaptor.pass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9534e0f70dd5edb0059d872c5cf5f8b7b2e67bf4 --- /dev/null +++ b/libcxx/test/std/ranges/range.adaptors/range.reverse/adaptor.pass.cpp @@ -0,0 +1,181 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17 +// UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges + +// std::views::reverse + +#include + +#include +#include +#include +#include + +#include "types.h" + +template +concept CanBePiped = requires (View&& view, T&& t) { + { std::forward(view) | std::forward(t) }; +}; + +constexpr bool test() { + int buf[] = {1, 2, 3}; + + // views::reverse(x) is equivalent to x.base() if x is a reverse_view + { + { + BidirRange view(buf, buf + 3); + std::ranges::reverse_view reversed(view); + std::same_as auto result = std::views::reverse(reversed); + assert(result.begin_ == buf); + assert(result.end_ == buf + 3); + } + { + // Common use case is worth testing + BidirRange view(buf, buf + 3); + std::same_as auto result = std::views::reverse(std::views::reverse(view)); + assert(result.begin_ == buf); + assert(result.end_ == buf + 3); + } + } + + // views::reverse(x) is equivalent to subrange{end, begin, size} if x is a + // sized subrange over reverse iterators + { + using It = bidirectional_iterator; + using Subrange = std::ranges::subrange; + + using ReverseIt = std::reverse_iterator; + using ReverseSubrange = std::ranges::subrange; + + { + BidirRange view(buf, buf + 3); + ReverseSubrange subrange(ReverseIt(std::ranges::end(view)), ReverseIt(std::ranges::begin(view)), /* size */3); + std::same_as auto result = std::views::reverse(subrange); + assert(result.begin().base() == buf); + assert(result.end().base() == buf + 3); + } + { + // std::move into views::reverse + BidirRange view(buf, buf + 3); + ReverseSubrange subrange(ReverseIt(std::ranges::end(view)), ReverseIt(std::ranges::begin(view)), /* size */3); + std::same_as auto result = std::views::reverse(std::move(subrange)); + assert(result.begin().base() == buf); + assert(result.end().base() == buf + 3); + } + { + // with a const subrange + BidirRange view(buf, buf + 3); + ReverseSubrange const subrange(ReverseIt(std::ranges::end(view)), ReverseIt(std::ranges::begin(view)), /* size */3); + std::same_as auto result = std::views::reverse(subrange); + assert(result.begin().base() == buf); + assert(result.end().base() == buf + 3); + } + } + + // views::reverse(x) is equivalent to subrange{end, begin} if x is an + // unsized subrange over reverse iterators + { + using It = bidirectional_iterator; + using Subrange = std::ranges::subrange; + + using ReverseIt = std::reverse_iterator; + using ReverseSubrange = std::ranges::subrange; + + { + BidirRange view(buf, buf + 3); + ReverseSubrange subrange(ReverseIt(std::ranges::end(view)), ReverseIt(std::ranges::begin(view))); + std::same_as auto result = std::views::reverse(subrange); + assert(result.begin().base() == buf); + assert(result.end().base() == buf + 3); + } + { + // std::move into views::reverse + BidirRange view(buf, buf + 3); + ReverseSubrange subrange(ReverseIt(std::ranges::end(view)), ReverseIt(std::ranges::begin(view))); + std::same_as auto result = std::views::reverse(std::move(subrange)); + assert(result.begin().base() == buf); + assert(result.end().base() == buf + 3); + } + { + // with a const subrange + BidirRange view(buf, buf + 3); + ReverseSubrange const subrange(ReverseIt(std::ranges::end(view)), ReverseIt(std::ranges::begin(view))); + std::same_as auto result = std::views::reverse(subrange); + assert(result.begin().base() == buf); + assert(result.end().base() == buf + 3); + } + } + + // Otherwise, views::reverse(x) is equivalent to ranges::reverse_view{x} + { + BidirRange view(buf, buf + 3); + std::same_as> auto result = std::views::reverse(view); + assert(result.begin().base().base() == buf + 3); + assert(result.end().base().base() == buf); + } + + // Test that std::views::reverse is a range adaptor + { + // Test `v | views::reverse` + { + BidirRange view(buf, buf + 3); + std::same_as> auto result = view | std::views::reverse; + assert(result.begin().base().base() == buf + 3); + assert(result.end().base().base() == buf); + } + + // Test `adaptor | views::reverse` + { + BidirRange view(buf, buf + 3); + auto f = [](int i) { return i; }; + auto const partial = std::views::transform(f) | std::views::reverse; + using Result = std::ranges::reverse_view>; + std::same_as auto result = partial(view); + assert(result.begin().base().base().base() == buf + 3); + assert(result.end().base().base().base() == buf); + } + + // Test `views::reverse | adaptor` + { + BidirRange view(buf, buf + 3); + auto f = [](int i) { return i; }; + auto const partial = std::views::reverse | std::views::transform(f); + using Result = std::ranges::transform_view, decltype(f)>; + std::same_as auto result = partial(view); + assert(result.begin().base().base().base() == buf + 3); + assert(result.end().base().base().base() == buf); + } + + // Check SFINAE friendliness + { + struct NotABidirRange { }; + static_assert(!std::is_invocable_v); + static_assert(!std::is_invocable_v); + static_assert( CanBePiped); + static_assert( CanBePiped); + static_assert(!CanBePiped); + } + } + + { + static_assert(std::same_as); + } + + return true; +} + +int main(int, char**) { + test(); + static_assert(test()); + + return 0; +} diff --git a/libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.size.pass.cpp b/libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.size.pass.cpp index 42013de1ccdf6c6ae1fb30a8b30f79d1c5ae0f3e..6b9b12c822424b9ee7e6be85dc0faa9f775adea3 100644 --- a/libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.size.pass.cpp +++ b/libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.size.pass.cpp @@ -24,7 +24,7 @@ void test_max(size_t count) try { TEST_IGNORE_NODISCARD a.allocate(count); assert(false); - } catch (const std::exception &) { + } catch (const std::bad_array_new_length &) { } } diff --git a/libcxx/test/std/utilities/time/time.cal/time.cal.year/time.cal.year.members/is_leap.pass.cpp b/libcxx/test/std/utilities/time/time.cal/time.cal.year/time.cal.year.members/is_leap.pass.cpp index 10c006a0dcafdceb9c5209a64fcc67c310d748bd..32ebbad71ea9dfa26c8366fb38517196216ac1cb 100644 --- a/libcxx/test/std/utilities/time/time.cal/time.cal.year/time.cal.year.members/is_leap.pass.cpp +++ b/libcxx/test/std/utilities/time/time.cal/time.cal.year/time.cal.year.members/is_leap.pass.cpp @@ -10,7 +10,7 @@ // // class year; -// constexpr bool is_is_leap() const noexcept; +// constexpr bool is_leap() const noexcept; // y_ % 4 == 0 && (y_ % 100 != 0 || y_ % 400 == 0) // diff --git a/libcxx/utils/ci/buildkite-pipeline.yml b/libcxx/utils/ci/buildkite-pipeline.yml index 7aff330180a73653a7dc3ea30f03bddc24a6870a..ef69a6dafa03c74463903e7c99e8f70d7da20da6 100644 --- a/libcxx/utils/ci/buildkite-pipeline.yml +++ b/libcxx/utils/ci/buildkite-pipeline.yml @@ -267,8 +267,8 @@ steps: limit: 2 timeout_in_minutes: 120 - - label: "New standalone runtimes build" - command: "libcxx/utils/ci/run-buildbot new-standalone" + - label: "Legacy LLVM_ENABLE_PROJECTS build" + command: "libcxx/utils/ci/run-buildbot legacy-project-build" artifact_paths: - "**/test-results.xml" agents: diff --git a/libcxx/utils/ci/run-buildbot b/libcxx/utils/ci/run-buildbot index aeda4c0a26b9cf8947e8b12937d0613adc270494..71177b979b8d0db7895211206a1fb2bba47a03d5 100755 --- a/libcxx/utils/ci/run-buildbot +++ b/libcxx/utils/ci/run-buildbot @@ -78,6 +78,7 @@ function clean() { function generate-cmake-base() { echo "--- Generating CMake" ${CMAKE} \ + -S "${MONOREPO_ROOT}/runtimes" \ -B "${BUILD_DIR}" \ -GNinja -DCMAKE_MAKE_PROGRAM="${NINJA}" \ -DCMAKE_BUILD_TYPE=RelWithDebInfo \ @@ -88,8 +89,7 @@ function generate-cmake-base() { function generate-cmake() { generate-cmake-base \ - -S "${MONOREPO_ROOT}/llvm" \ - -DLLVM_ENABLE_PROJECTS="libcxx;libunwind;libcxxabi" \ + -DLLVM_ENABLE_RUNTIMES="libcxx;libcxxabi;libunwind" \ -DLIBCXX_CXX_ABI=libcxxabi \ "${@}" } @@ -104,7 +104,7 @@ function generate-cmake-libcxx-win() { # even if it uses a non-permanent ABI. generate-cmake-base \ - -S "${MONOREPO_ROOT}/libcxx" \ + -DLLVM_ENABLE_RUNTIMES="libcxx" \ -DCMAKE_C_COMPILER=clang-cl \ -DCMAKE_CXX_COMPILER=clang-cl \ -DLIBCXX_ENABLE_FILESYSTEM=YES \ @@ -437,21 +437,6 @@ documentation) echo "+++ Generating documentation" ${NINJA} -vC "${BUILD_DIR}" docs-libcxx-html ;; -new-standalone) - clean - - echo "--- Generating CMake" - ${CMAKE} \ - -S "${MONOREPO_ROOT}/runtimes" \ - -B "${BUILD_DIR}" \ - -GNinja -DCMAKE_MAKE_PROGRAM="${NINJA}" \ - -DCMAKE_BUILD_TYPE=RelWithDebInfo \ - -DCMAKE_INSTALL_PREFIX="${INSTALL_DIR}" \ - -DLLVM_ENABLE_RUNTIMES="libcxx;libcxxabi;libunwind" \ - -DLIBCXX_TEST_CONFIG="llvm-libc++-shared.cfg.in" - - check-runtimes -;; runtimes-build) clean @@ -484,6 +469,21 @@ legacy-test-config) generate-cmake -DLIBCXX_TEST_CONFIG="legacy.cfg.in" check-runtimes ;; +legacy-project-build) + clean + + echo "--- Generating CMake" + ${CMAKE} \ + -S "${MONOREPO_ROOT}/llvm" \ + -B "${BUILD_DIR}" \ + -DLLVM_ENABLE_PROJECTS="libcxx;libunwind;libcxxabi" \ + -GNinja -DCMAKE_MAKE_PROGRAM="${NINJA}" \ + -DCMAKE_BUILD_TYPE=RelWithDebInfo \ + -DCMAKE_INSTALL_PREFIX="${INSTALL_DIR}" \ + -DLLVM_LIT_ARGS="-sv --show-unsupported --xunit-xml-output test-results.xml" \ + -DLIBCXX_CXX_ABI=libcxxabi + check-runtimes +;; legacy-standalone) clean diff --git a/libcxxabi/CMakeLists.txt b/libcxxabi/CMakeLists.txt index ea6ac11a53a4d31a672d15c16d9b9057f7df6f9c..cc1c395b14d1181e4a7f5d00f637e616eb932057 100644 --- a/libcxxabi/CMakeLists.txt +++ b/libcxxabi/CMakeLists.txt @@ -14,6 +14,8 @@ cmake_minimum_required(VERSION 3.13.4) set(CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake" "${CMAKE_CURRENT_SOURCE_DIR}/cmake/Modules" + "${CMAKE_CURRENT_SOURCE_DIR}/../cmake" + "${CMAKE_CURRENT_SOURCE_DIR}/../cmake/Modules" ${CMAKE_MODULE_PATH} ) diff --git a/libcxxabi/cmake/Modules/HandleCompilerRT.cmake b/libcxxabi/cmake/Modules/HandleCompilerRT.cmake deleted file mode 100644 index 1f953276df00da62a703db6eb3532d7b3e4ea80f..0000000000000000000000000000000000000000 --- a/libcxxabi/cmake/Modules/HandleCompilerRT.cmake +++ /dev/null @@ -1,64 +0,0 @@ -function(find_compiler_rt_library name dest) - if (NOT DEFINED LIBCXXABI_COMPILE_FLAGS) - message(FATAL_ERROR "LIBCXXABI_COMPILE_FLAGS must be defined when using this function") - endif() - set(dest "" PARENT_SCOPE) - set(CLANG_COMMAND ${CMAKE_CXX_COMPILER} ${LIBCXXABI_COMPILE_FLAGS} - "--rtlib=compiler-rt" "--print-libgcc-file-name") - if (CMAKE_CXX_COMPILER_ID MATCHES Clang AND CMAKE_CXX_COMPILER_TARGET) - list(APPEND CLANG_COMMAND "--target=${CMAKE_CXX_COMPILER_TARGET}") - endif() - get_property(LIBCXXABI_CXX_FLAGS CACHE CMAKE_CXX_FLAGS PROPERTY VALUE) - string(REPLACE " " ";" LIBCXXABI_CXX_FLAGS "${LIBCXXABI_CXX_FLAGS}") - list(APPEND CLANG_COMMAND ${LIBCXXABI_CXX_FLAGS}) - execute_process( - COMMAND ${CLANG_COMMAND} - RESULT_VARIABLE HAD_ERROR - OUTPUT_VARIABLE LIBRARY_FILE - ) - string(STRIP "${LIBRARY_FILE}" LIBRARY_FILE) - file(TO_CMAKE_PATH "${LIBRARY_FILE}" LIBRARY_FILE) - string(REPLACE "builtins" "${name}" LIBRARY_FILE "${LIBRARY_FILE}") - if (NOT HAD_ERROR AND EXISTS "${LIBRARY_FILE}") - message(STATUS "Found compiler-rt library: ${LIBRARY_FILE}") - set(${dest} "${LIBRARY_FILE}" PARENT_SCOPE) - else() - message(STATUS "Failed to find compiler-rt library") - endif() -endfunction() - -function(find_compiler_rt_dir dest) - if (NOT DEFINED LIBCXXABI_COMPILE_FLAGS) - message(FATAL_ERROR "LIBCXXABI_COMPILE_FLAGS must be defined when using this function") - endif() - set(dest "" PARENT_SCOPE) - if (APPLE) - set(CLANG_COMMAND ${CMAKE_CXX_COMPILER} ${LIBCXXABI_COMPILE_FLAGS} - "-print-file-name=lib") - execute_process( - COMMAND ${CLANG_COMMAND} - RESULT_VARIABLE HAD_ERROR - OUTPUT_VARIABLE LIBRARY_DIR - ) - string(STRIP "${LIBRARY_DIR}" LIBRARY_DIR) - file(TO_CMAKE_PATH "${LIBRARY_DIR}" LIBRARY_DIR) - set(LIBRARY_DIR "${LIBRARY_DIR}/darwin") - else() - set(CLANG_COMMAND ${CMAKE_CXX_COMPILER} ${LIBCXXABI_COMPILE_FLAGS} - "--rtlib=compiler-rt" "--print-libgcc-file-name") - execute_process( - COMMAND ${CLANG_COMMAND} - RESULT_VARIABLE HAD_ERROR - OUTPUT_VARIABLE LIBRARY_FILE - ) - string(STRIP "${LIBRARY_FILE}" LIBRARY_FILE) - file(TO_CMAKE_PATH "${LIBRARY_FILE}" LIBRARY_FILE) - get_filename_component(LIBRARY_DIR "${LIBRARY_FILE}" DIRECTORY) - endif() - if (NOT HAD_ERROR AND EXISTS "${LIBRARY_DIR}") - message(STATUS "Found compiler-rt directory: ${LIBRARY_DIR}") - set(${dest} "${LIBRARY_DIR}" PARENT_SCOPE) - else() - message(STATUS "Failed to find compiler-rt directory") - endif() -endfunction() diff --git a/libcxxabi/cmake/config-ix.cmake b/libcxxabi/cmake/config-ix.cmake index 998e25415ed1bbfd96f1d5421cbc0194560cd96a..62e6aeceb859a7f3a7e645648c481b6eceb37b00 100644 --- a/libcxxabi/cmake/config-ix.cmake +++ b/libcxxabi/cmake/config-ix.cmake @@ -38,8 +38,10 @@ if (LIBCXXABI_SUPPORTS_NOSTDLIBXX_FLAG OR LIBCXXABI_SUPPORTS_NODEFAULTLIBS_FLAG) list(APPEND CMAKE_REQUIRED_LIBRARIES c) endif () if (LIBCXXABI_USE_COMPILER_RT) - set(CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS} -rtlib=compiler-rt") + cmake_push_check_state() + set(CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS} ${LIBCXXABI_COMPILE_FLAGS}") find_compiler_rt_library(builtins LIBCXXABI_BUILTINS_LIBRARY) + cmake_pop_check_state() list(APPEND CMAKE_REQUIRED_LIBRARIES "${LIBCXXABI_BUILTINS_LIBRARY}") else () if (LIBCXXABI_HAS_GCC_S_LIB) diff --git a/libcxxabi/src/CMakeLists.txt b/libcxxabi/src/CMakeLists.txt index 94182dccba5e3130da9d4d716bac7a7e316c9310..c237fb19f84f95a849745520edc2e76660afc277 100644 --- a/libcxxabi/src/CMakeLists.txt +++ b/libcxxabi/src/CMakeLists.txt @@ -136,7 +136,8 @@ if ( APPLE ) message(WARNING "LLVM_USE_SANITIZER=${LLVM_USE_SANITIZER} is not supported on OS X") endif() if (LIBFILE) - find_compiler_rt_dir(LIBDIR) + find_compiler_rt_library(builtins LIBCXXABI_BUILTINS_LIBRARY) + get_filename_component(LIBDIR "${LIBCXXABI_BUILTINS_LIBRARY}" DIRECTORY) if (NOT IS_DIRECTORY "${LIBDIR}") message(FATAL_ERROR "Cannot find compiler-rt directory on OS X required for LLVM_USE_SANITIZER") endif() diff --git a/libunwind/CMakeLists.txt b/libunwind/CMakeLists.txt index 9b55195b83986ee62e5fe8f88b0eed61c0dc10fb..7a8bfae7cca405c09612bb333e633f242a2a1104 100644 --- a/libunwind/CMakeLists.txt +++ b/libunwind/CMakeLists.txt @@ -12,6 +12,8 @@ cmake_minimum_required(VERSION 3.13.4) set(CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake" "${CMAKE_CURRENT_SOURCE_DIR}/cmake/Modules" + "${CMAKE_CURRENT_SOURCE_DIR}/../cmake" + "${CMAKE_CURRENT_SOURCE_DIR}/../cmake/Modules" ${CMAKE_MODULE_PATH} ) diff --git a/libunwind/cmake/Modules/HandleCompilerRT.cmake b/libunwind/cmake/Modules/HandleCompilerRT.cmake deleted file mode 100644 index 77168e599466ed0c3087cc565db537e31cc7b3de..0000000000000000000000000000000000000000 --- a/libunwind/cmake/Modules/HandleCompilerRT.cmake +++ /dev/null @@ -1,64 +0,0 @@ -function(find_compiler_rt_library name dest) - if (NOT DEFINED LIBUNWIND_COMPILE_FLAGS) - message(FATAL_ERROR "LIBUNWIND_COMPILE_FLAGS must be defined when using this function") - endif() - set(dest "" PARENT_SCOPE) - set(CLANG_COMMAND ${CMAKE_CXX_COMPILER} ${LIBUNWIND_COMPILE_FLAGS} - "--rtlib=compiler-rt" "--print-libgcc-file-name") - if (CMAKE_CXX_COMPILER_ID MATCHES Clang AND CMAKE_CXX_COMPILER_TARGET) - list(APPEND CLANG_COMMAND "--target=${CMAKE_CXX_COMPILER_TARGET}") - endif() - get_property(LIBUNWIND_CXX_FLAGS CACHE CMAKE_CXX_FLAGS PROPERTY VALUE) - string(REPLACE " " ";" LIBUNWIND_CXX_FLAGS "${LIBUNWIND_CXX_FLAGS}") - list(APPEND CLANG_COMMAND ${LIBUNWIND_CXX_FLAGS}) - execute_process( - COMMAND ${CLANG_COMMAND} - RESULT_VARIABLE HAD_ERROR - OUTPUT_VARIABLE LIBRARY_FILE - ) - string(STRIP "${LIBRARY_FILE}" LIBRARY_FILE) - file(TO_CMAKE_PATH "${LIBRARY_FILE}" LIBRARY_FILE) - string(REPLACE "builtins" "${name}" LIBRARY_FILE "${LIBRARY_FILE}") - if (NOT HAD_ERROR AND EXISTS "${LIBRARY_FILE}") - message(STATUS "Found compiler-rt library: ${LIBRARY_FILE}") - set(${dest} "${LIBRARY_FILE}" PARENT_SCOPE) - else() - message(STATUS "Failed to find compiler-rt library") - endif() -endfunction() - -function(find_compiler_rt_dir dest) - if (NOT DEFINED LIBUNWIND_COMPILE_FLAGS) - message(FATAL_ERROR "LIBUNWIND_COMPILE_FLAGS must be defined when using this function") - endif() - set(dest "" PARENT_SCOPE) - if (APPLE) - set(CLANG_COMMAND ${CMAKE_CXX_COMPILER} ${LIBUNWIND_COMPILE_FLAGS} - "-print-file-name=lib") - execute_process( - COMMAND ${CLANG_COMMAND} - RESULT_VARIABLE HAD_ERROR - OUTPUT_VARIABLE LIBRARY_DIR - ) - string(STRIP "${LIBRARY_DIR}" LIBRARY_DIR) - file(TO_CMAKE_PATH "${LIBRARY_DIR}" LIBRARY_DIR) - set(LIBRARY_DIR "${LIBRARY_DIR}/darwin") - else() - set(CLANG_COMMAND ${CMAKE_CXX_COMPILER} ${LIBUNWIND_COMPILE_FLAGS} - "--rtlib=compiler-rt" "--print-libgcc-file-name") - execute_process( - COMMAND ${CLANG_COMMAND} - RESULT_VARIABLE HAD_ERROR - OUTPUT_VARIABLE LIBRARY_FILE - ) - string(STRIP "${LIBRARY_FILE}" LIBRARY_FILE) - file(TO_CMAKE_PATH "${LIBRARY_FILE}" LIBRARY_FILE) - get_filename_component(LIBRARY_DIR "${LIBRARY_FILE}" DIRECTORY) - endif() - if (NOT HAD_ERROR AND EXISTS "${LIBRARY_DIR}") - message(STATUS "Found compiler-rt directory: ${LIBRARY_DIR}") - set(${dest} "${LIBRARY_DIR}" PARENT_SCOPE) - else() - message(STATUS "Failed to find compiler-rt directory") - endif() -endfunction() diff --git a/libunwind/cmake/config-ix.cmake b/libunwind/cmake/config-ix.cmake index 4ca6bdd8e95dff17a8912259d51e7b7ec4fc2691..a7ad72fde7fd2b0ff82e794cb65ececd2317916a 100644 --- a/libunwind/cmake/config-ix.cmake +++ b/libunwind/cmake/config-ix.cmake @@ -40,7 +40,10 @@ if (LIBUNWIND_SUPPORTS_NOSTDLIBXX_FLAG OR LIBUNWIND_SUPPORTS_NODEFAULTLIBS_FLAG) list(APPEND CMAKE_REQUIRED_LIBRARIES c) endif () if (LIBUNWIND_USE_COMPILER_RT) + cmake_push_check_state() + set(CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS} ${LIBUNWIND_COMPILE_FLAGS}") find_compiler_rt_library(builtins LIBUNWIND_BUILTINS_LIBRARY) + cmake_pop_check_state() list(APPEND CMAKE_REQUIRED_LIBRARIES "${LIBUNWIND_BUILTINS_LIBRARY}") else () if (LIBUNWIND_HAS_GCC_S_LIB) diff --git a/lld/COFF/LTO.cpp b/lld/COFF/LTO.cpp index ce9c4fd0d51b237317659dd1da662b929a82945d..505360663f4f9472ebd09eeabfb51bff759f9ec0 100644 --- a/lld/COFF/LTO.cpp +++ b/lld/COFF/LTO.cpp @@ -20,10 +20,10 @@ #include "llvm/ADT/Twine.h" #include "llvm/Bitcode/BitcodeWriter.h" #include "llvm/IR/DiagnosticPrinter.h" -#include "llvm/LTO/Caching.h" #include "llvm/LTO/Config.h" #include "llvm/LTO/LTO.h" #include "llvm/Object/SymbolicFile.h" +#include "llvm/Support/Caching.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/Error.h" #include "llvm/Support/FileSystem.h" @@ -164,16 +164,17 @@ std::vector BitcodeCompiler::compile(COFFLinkerContext &ctx) { // The /lldltocache option specifies the path to a directory in which to cache // native object files for ThinLTO incremental builds. If a path was // specified, configure LTO to use it as the cache directory. - lto::NativeObjectCache cache; + NativeObjectCache cache; if (!config->ltoCache.empty()) - cache = check(lto::localCache( - config->ltoCache, [&](size_t task, std::unique_ptr mb) { - files[task] = std::move(mb); - })); + cache = + check(localCache("ThinLTO", "Thin", config->ltoCache, + [&](size_t task, std::unique_ptr mb) { + files[task] = std::move(mb); + })); checkError(ltoObj->run( [&](size_t task) { - return std::make_unique( + return std::make_unique( std::make_unique(buf[task])); }, cache)); diff --git a/lld/COFF/Writer.cpp b/lld/COFF/Writer.cpp index 6641db119064f4c3f932fbf18f2d9315a616d2cb..600d14034dea879edbe7a47f9d2a191b3096d71a 100644 --- a/lld/COFF/Writer.cpp +++ b/lld/COFF/Writer.cpp @@ -1090,18 +1090,14 @@ void Writer::removeUnusedSections() { // later. Only remove sections that have no Chunks at all. return s->chunks.empty(); }; - ctx.outputSections.erase(std::remove_if(ctx.outputSections.begin(), - ctx.outputSections.end(), isUnused), - ctx.outputSections.end()); + llvm::erase_if(ctx.outputSections, isUnused); } // The Windows loader doesn't seem to like empty sections, // so we remove them if any. void Writer::removeEmptySections() { auto isEmpty = [](OutputSection *s) { return s->getVirtualSize() == 0; }; - ctx.outputSections.erase(std::remove_if(ctx.outputSections.begin(), - ctx.outputSections.end(), isEmpty), - ctx.outputSections.end()); + llvm::erase_if(ctx.outputSections, isEmpty); } void Writer::assignOutputSectionIndices() { diff --git a/lld/ELF/LTO.cpp b/lld/ELF/LTO.cpp index fb354f81d49d6091ea8d828cf19a0f7526ae10b1..5f206fc97b3cadef94f887948d33a0d45f7703ab 100644 --- a/lld/ELF/LTO.cpp +++ b/lld/ELF/LTO.cpp @@ -23,10 +23,10 @@ #include "llvm/Bitcode/BitcodeReader.h" #include "llvm/Bitcode/BitcodeWriter.h" #include "llvm/IR/DiagnosticPrinter.h" -#include "llvm/LTO/Caching.h" #include "llvm/LTO/Config.h" #include "llvm/LTO/LTO.h" #include "llvm/Object/SymbolicFile.h" +#include "llvm/Support/Caching.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/Error.h" #include "llvm/Support/FileSystem.h" @@ -304,18 +304,18 @@ std::vector BitcodeCompiler::compile() { // The --thinlto-cache-dir option specifies the path to a directory in which // to cache native object files for ThinLTO incremental builds. If a path was // specified, configure LTO to use it as the cache directory. - lto::NativeObjectCache cache; + NativeObjectCache cache; if (!config->thinLTOCacheDir.empty()) - cache = check( - lto::localCache(config->thinLTOCacheDir, - [&](size_t task, std::unique_ptr mb) { - files[task] = std::move(mb); - })); + cache = + check(localCache("ThinLTO", "Thin", config->thinLTOCacheDir, + [&](size_t task, std::unique_ptr mb) { + files[task] = std::move(mb); + })); if (!bitcodeFiles.empty()) checkError(ltoObj->run( [&](size_t task) { - return std::make_unique( + return std::make_unique( std::make_unique(buf[task])); }, cache)); diff --git a/lld/MachO/LTO.cpp b/lld/MachO/LTO.cpp index 09b05ed0dffeeb13a255b6d63e557d60824f2a48..d1eef6a6f8f82d685eb862ea267cd048656fa43a 100644 --- a/lld/MachO/LTO.cpp +++ b/lld/MachO/LTO.cpp @@ -17,9 +17,9 @@ #include "lld/Common/ErrorHandler.h" #include "lld/Common/Strings.h" #include "lld/Common/TargetOptionsCommandFlags.h" -#include "llvm/LTO/Caching.h" #include "llvm/LTO/Config.h" #include "llvm/LTO/LTO.h" +#include "llvm/Support/Caching.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/Path.h" #include "llvm/Support/raw_ostream.h" @@ -105,17 +105,17 @@ std::vector BitcodeCompiler::compile() { // The -cache_path_lto option specifies the path to a directory in which // to cache native object files for ThinLTO incremental builds. If a path was // specified, configure LTO to use it as the cache directory. - lto::NativeObjectCache cache; + NativeObjectCache cache; if (!config->thinLTOCacheDir.empty()) - cache = check( - lto::localCache(config->thinLTOCacheDir, - [&](size_t task, std::unique_ptr mb) { - files[task] = std::move(mb); - })); + cache = + check(localCache("ThinLTO", "Thin", config->thinLTOCacheDir, + [&](size_t task, std::unique_ptr mb) { + files[task] = std::move(mb); + })); checkError(ltoObj->run( [&](size_t task) { - return std::make_unique( + return std::make_unique( std::make_unique(buf[task])); }, cache)); diff --git a/lld/lib/Core/Resolver.cpp b/lld/lib/Core/Resolver.cpp index 17a46056f00c1e50867abc3bf82238bdc635d2ad..1ed0b1c6e618b0589f4bf7de925ce8b2f4ec9532 100644 --- a/lld/lib/Core/Resolver.cpp +++ b/lld/lib/Core/Resolver.cpp @@ -380,11 +380,9 @@ void Resolver::deadStripOptimize() { markLive(dsrAtom); // now remove all non-live atoms from _atoms - _atoms.erase(std::remove_if(_atoms.begin(), _atoms.end(), - [&](OwningAtomPtr &a) { - return _liveAtoms.count(a.get()) == 0; - }), - _atoms.end()); + llvm::erase_if(_atoms, [&](OwningAtomPtr &a) { + return _liveAtoms.count(a.get()) == 0; + }); } // error out if some undefines remain @@ -396,10 +394,8 @@ bool Resolver::checkUndefines() { std::vector undefinedAtoms = _symbolTable.undefines(); if (_ctx.deadStrip()) { // When dead code stripping, we don't care if dead atoms are undefined. - undefinedAtoms.erase( - std::remove_if(undefinedAtoms.begin(), undefinedAtoms.end(), - [&](const Atom *a) { return _liveAtoms.count(a) == 0; }), - undefinedAtoms.end()); + llvm::erase_if(undefinedAtoms, + [&](const Atom *a) { return _liveAtoms.count(a) == 0; }); } if (undefinedAtoms.empty()) @@ -440,12 +436,9 @@ void Resolver::removeCoalescedAwayAtoms() { DEBUG_WITH_TYPE("resolver", llvm::dbgs() << "******** Removing coalesced away atoms:\n"); ScopedTask task(getDefaultDomain(), "removeCoalescedAwayAtoms"); - _atoms.erase(std::remove_if(_atoms.begin(), _atoms.end(), - [&](OwningAtomPtr &a) { - return _symbolTable.isCoalescedAway(a.get()) || - _deadAtoms.count(a.get()); - }), - _atoms.end()); + llvm::erase_if(_atoms, [&](OwningAtomPtr &a) { + return _symbolTable.isCoalescedAway(a.get()) || _deadAtoms.count(a.get()); + }); } bool Resolver::resolve() { diff --git a/lld/test/ELF/x86-64-reloc-32-fpic.s b/lld/test/ELF/x86-64-reloc-32-fpic.s deleted file mode 100644 index 1c4754f1e2c662b5c7911b503bbf7d8d585469f9..0000000000000000000000000000000000000000 --- a/lld/test/ELF/x86-64-reloc-32-fpic.s +++ /dev/null @@ -1,10 +0,0 @@ -# REQUIRES: x86 -# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o -# RUN: not ld.lld -shared %t.o -o /dev/null 2>&1 | FileCheck %s - -# CHECK: relocation R_X86_64_32 cannot be used against symbol _shared; recompile with -fPIC -# CHECK: >>> defined in {{.*}} -# CHECK: >>> referenced by {{.*}}:(.data+0x0) - -.data -.long _shared diff --git a/lld/test/ELF/x86-64-reloc-32.s b/lld/test/ELF/x86-64-reloc-32.s new file mode 100644 index 0000000000000000000000000000000000000000..e2871914725f7fdbbd1d09ff07e12ca7a22debc2 --- /dev/null +++ b/lld/test/ELF/x86-64-reloc-32.s @@ -0,0 +1,27 @@ +# REQUIRES: x86 +# RUN: rm -rf %t && split-file %s %t + +## Check recompile with -fPIC error message +# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %t/shared.s -o %t/shared.o +# RUN: not ld.lld -shared %t/shared.o -o /dev/null 2>&1 | FileCheck %s + +# CHECK: relocation R_X86_64_32 cannot be used against symbol _shared; recompile with -fPIC +# CHECK: >>> defined in {{.*}} +# CHECK: >>> referenced by {{.*}}:(.data+0x0) + +## Check patching of negative addends +# RUN: llvm-mc -filetype=obj -triple=x86_64 %t/addend.s -o %t/addend.o +# RUN: not ld.lld --section-start=.text=0x0 %t/addend.o -o /dev/null 2>&1 | FileCheck %s --check-prefix RANGE + +# RANGE: relocation R_X86_64_32 out of range + +#--- shared.s +.data +.long _shared + +#--- addend.s +.text +.globl _start +_start: + .reloc ., R_X86_64_32, .text-1 + .space 4 diff --git a/lld/test/ELF/x86-64-reloc-pc32-fpic.s b/lld/test/ELF/x86-64-reloc-pc32-fpic.s deleted file mode 100644 index 2dfd1bfb444c931e2624e156d9772a74beb40870..0000000000000000000000000000000000000000 --- a/lld/test/ELF/x86-64-reloc-pc32-fpic.s +++ /dev/null @@ -1,11 +0,0 @@ -# REQUIRES: x86 -# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o -# RUN: not ld.lld -shared %t.o -o /dev/null 2>&1 | FileCheck %s - -# CHECK: relocation R_X86_64_PC32 cannot be used against symbol _shared; recompile with -fPIC -# CHECK: >>> defined in {{.*}} -# CHECK: >>> referenced by {{.*}}:(.data+0x1) - -.data - .byte 0xe8 - .long _shared - . diff --git a/lld/test/ELF/x86-64-reloc-pc32.s b/lld/test/ELF/x86-64-reloc-pc32.s new file mode 100644 index 0000000000000000000000000000000000000000..ba66a51b81b496a3fbc134faf2058c74a804043a --- /dev/null +++ b/lld/test/ELF/x86-64-reloc-pc32.s @@ -0,0 +1,39 @@ +# REQUIRES: x86 +# RUN: rm -rf %t && split-file %s %t + +## Check recompile with -fPIC error message +# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %t/shared.s -o %t/shared.o +# RUN: not ld.lld -shared %t/shared.o -o /dev/null 2>&1 | FileCheck %s + +# CHECK: relocation R_X86_64_PC32 cannot be used against symbol _shared; recompile with -fPIC +# CHECK: >>> defined in {{.*}} +# CHECK: >>> referenced by {{.*}}:(.data+0x1) + +## Check patching of negative addends + +# RUN: llvm-mc -filetype=obj -triple=x86_64 -defsym ADDEND=1 %t/addend.s -o %t/1.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 -defsym ADDEND=2147483648 %t/addend.s -o %t/2.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 -defsym ADDEND=2147483649 %t/addend.s -o %t/3.o + +# RUN: ld.lld --section-start=.text=0x0 %t/1.o -o %t/1out +# RUN: ld.lld --section-start=.text=0x0 %t/2.o -o %t/2out +# RUN: not ld.lld --section-start=.text=0x0 %t/3.o -o /dev/null 2>&1 | FileCheck %s --check-prefix RANGE + +# RANGE: relocation R_X86_64_PC32 out of range + +# RUN: llvm-readelf --hex-dump=.text %t/1out | FileCheck %s -DADDEND=ffffffff --check-prefix DUMP +# RUN: llvm-readelf --hex-dump=.text %t/2out | FileCheck %s -DADDEND=00000080 --check-prefix DUMP + +# DUMP: 0x00000000 [[ADDEND]] + +#--- shared.s +.data + .byte 0xe8 + .long _shared - . + +#--- addend.s +.text +.globl _start +_start: + .reloc ., R_X86_64_PC32, .text-ADDEND + .space 4 diff --git a/lld/wasm/LTO.cpp b/lld/wasm/LTO.cpp index 4f76fc0dccdb54129f976f52a378814a4f4e6cd5..4659278be753590abb87b12a53698cb9267bd2b5 100644 --- a/lld/wasm/LTO.cpp +++ b/lld/wasm/LTO.cpp @@ -19,10 +19,10 @@ #include "llvm/ADT/StringRef.h" #include "llvm/ADT/Twine.h" #include "llvm/IR/DiagnosticPrinter.h" -#include "llvm/LTO/Caching.h" #include "llvm/LTO/Config.h" #include "llvm/LTO/LTO.h" #include "llvm/Object/SymbolicFile.h" +#include "llvm/Support/Caching.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/Error.h" #include "llvm/Support/FileSystem.h" @@ -127,17 +127,17 @@ std::vector BitcodeCompiler::compile() { // The --thinlto-cache-dir option specifies the path to a directory in which // to cache native object files for ThinLTO incremental builds. If a path was // specified, configure LTO to use it as the cache directory. - lto::NativeObjectCache cache; + NativeObjectCache cache; if (!config->thinLTOCacheDir.empty()) - cache = check( - lto::localCache(config->thinLTOCacheDir, - [&](size_t task, std::unique_ptr mb) { - files[task] = std::move(mb); - })); + cache = + check(localCache("ThinLTO", "Thin", config->thinLTOCacheDir, + [&](size_t task, std::unique_ptr mb) { + files[task] = std::move(mb); + })); checkError(ltoObj->run( [&](size_t task) { - return std::make_unique( + return std::make_unique( std::make_unique(buf[task])); }, cache)); diff --git a/lldb/include/lldb/Interpreter/CommandCompletions.h b/lldb/include/lldb/Interpreter/CommandCompletions.h index c80bde0e719bfa02d817500c4aa9ec57adc86dcb..c13bc4997ff3e6212bd2eb305a111bd300f03c54 100644 --- a/lldb/include/lldb/Interpreter/CommandCompletions.h +++ b/lldb/include/lldb/Interpreter/CommandCompletions.h @@ -13,6 +13,7 @@ #include "lldb/Core/FileSpecList.h" #include "lldb/Core/SearchFilter.h" +#include "lldb/Interpreter/Options.h" #include "lldb/Utility/CompletionRequest.h" #include "lldb/Utility/RegularExpression.h" #include "lldb/lldb-private.h" @@ -151,6 +152,15 @@ public: static void TypeCategoryNames(CommandInterpreter &interpreter, CompletionRequest &request, SearchFilter *searcher); + + /// This completer works for commands whose only arguments are a command path. + /// It isn't tied to an argument type because it completes not on a single + /// argument but on the sequence of arguments, so you have to invoke it by + /// hand. + static void + CompleteModifiableCmdPathArgs(CommandInterpreter &interpreter, + CompletionRequest &request, + OptionElementVector &opt_element_vector); }; } // namespace lldb_private diff --git a/lldb/include/lldb/Interpreter/CommandInterpreter.h b/lldb/include/lldb/Interpreter/CommandInterpreter.h index 3b3daced3e336e7dcab4c66d59118da68950108a..e6f0d5f9c4d431390a001d6616375f8f7d861c35 100644 --- a/lldb/include/lldb/Interpreter/CommandInterpreter.h +++ b/lldb/include/lldb/Interpreter/CommandInterpreter.h @@ -231,11 +231,12 @@ public: }; enum CommandTypes { - eCommandTypesBuiltin = 0x0001, // native commands such as "frame" - eCommandTypesUserDef = 0x0002, // scripted commands - eCommandTypesAliases = 0x0004, // aliases such as "po" - eCommandTypesHidden = 0x0008, // commands prefixed with an underscore - eCommandTypesAllThem = 0xFFFF // all commands + eCommandTypesBuiltin = 0x0001, //< native commands such as "frame" + eCommandTypesUserDef = 0x0002, //< scripted commands + eCommandTypesUserMW = 0x0004, //< multiword commands (command containers) + eCommandTypesAliases = 0x0008, //< aliases such as "po" + eCommandTypesHidden = 0x0010, //< commands prefixed with an underscore + eCommandTypesAllThem = 0xFFFF //< all commands }; CommandInterpreter(Debugger &debugger, bool synchronous_execution); @@ -256,8 +257,8 @@ public: bool AddCommand(llvm::StringRef name, const lldb::CommandObjectSP &cmd_sp, bool can_replace); - bool AddUserCommand(llvm::StringRef name, const lldb::CommandObjectSP &cmd_sp, - bool can_replace); + Status AddUserCommand(llvm::StringRef name, + const lldb::CommandObjectSP &cmd_sp, bool can_replace); lldb::CommandObjectSP GetCommandSPExact(llvm::StringRef cmd, bool include_aliases = false) const; @@ -266,12 +267,49 @@ public: StringList *matches = nullptr, StringList *descriptions = nullptr) const; + CommandObject *GetUserCommandObject(llvm::StringRef cmd, + StringList *matches = nullptr, + StringList *descriptions = nullptr) const; + + /// Determine whether a root level, built-in command with this name exists. bool CommandExists(llvm::StringRef cmd) const; + /// Determine whether an alias command with this name exists bool AliasExists(llvm::StringRef cmd) const; + /// Determine whether a root-level user command with this name exists. bool UserCommandExists(llvm::StringRef cmd) const; + /// Determine whether a root-level user multiword command with this name + /// exists. + bool UserMultiwordCommandExists(llvm::StringRef cmd) const; + + /// Look up the command pointed to by path encoded in the arguments of + /// the incoming command object. If all the path components exist + /// and are all actual commands - not aliases, and the leaf command is a + /// multiword command, return the command. Otherwise return nullptr, and put + /// a useful diagnostic in the Status object. + /// + /// \param[in] path + /// An Args object holding the path in its arguments + /// \param[in] leaf_is_command + /// If true, return the container of the leaf name rather than looking up + /// the whole path as a leaf command. The leaf needn't exist in this case. + /// \param[in,out] result + /// If the path is not found, this error shows where we got off track. + /// \return + /// If found, a pointer to the CommandObjectMultiword pointed to by path, + /// or to the container of the leaf element is is_leaf_command. + /// Returns nullptr under two circumstances: + /// 1) The command in not found (check error.Fail) + /// 2) is_leaf is true and the path has only a leaf. We don't have a + /// dummy "contains everything MWC, so we return null here, but + /// in this case error.Success is true. + + CommandObjectMultiword *VerifyUserMultiwordCmdPath(Args &path, + bool leaf_is_command, + Status &result); + CommandAlias *AddAlias(llvm::StringRef alias_name, lldb::CommandObjectSP &command_obj_sp, llvm::StringRef args_string = llvm::StringRef()); @@ -283,6 +321,11 @@ public: bool GetAliasFullName(llvm::StringRef cmd, std::string &full_name) const; + bool RemoveUserMultiword(llvm::StringRef multiword_name); + + // Do we want to allow top-level user multiword commands to be deleted? + void RemoveAllUserMultiword() { m_user_mw_dict.clear(); } + bool RemoveUser(llvm::StringRef alias_name); void RemoveAllUser() { m_user_dict.clear(); } @@ -414,6 +457,8 @@ public: bool HasUserCommands() const; + bool HasUserMultiwordCommands() const; + bool HasAliasOptions() const; void BuildAliasCommandArgs(CommandObject *alias_cmd_obj, @@ -421,6 +466,7 @@ public: std::string &raw_input_string, CommandReturnObject &result); + /// Picks the number out of a string of the form "%NNN", otherwise return 0. int GetOptionArgumentPosition(const char *in_string); void SkipLLDBInitFiles(bool skip_lldbinit_files) { @@ -437,7 +483,8 @@ public: StringList &commands_help, bool search_builtin_commands, bool search_user_commands, - bool search_alias_commands); + bool search_alias_commands, + bool search_user_mw_commands); bool GetBatchCommandMode() { return m_batch_command_mode; } @@ -506,6 +553,10 @@ public: return m_user_dict; } + const CommandObject::CommandMap &GetUserMultiwordCommands() const { + return m_user_mw_dict; + } + const CommandObject::CommandMap &GetCommands() const { return m_command_dict; } @@ -636,6 +687,8 @@ private: CommandObject::CommandMap m_alias_dict; // Stores user aliases/abbreviations for commands CommandObject::CommandMap m_user_dict; // Stores user-defined commands + CommandObject::CommandMap + m_user_mw_dict; // Stores user-defined multiword commands CommandHistory m_command_history; std::string m_repeat_command; // Stores the command that will be executed for // an empty command string. diff --git a/lldb/include/lldb/Interpreter/CommandObject.h b/lldb/include/lldb/Interpreter/CommandObject.h index 8bc5d3e22355d241497e984fb31f787f39daf3e1..89cc161993a9fb4a27c3a9656bdd42aad828b7ab 100644 --- a/lldb/include/lldb/Interpreter/CommandObject.h +++ b/lldb/include/lldb/Interpreter/CommandObject.h @@ -145,6 +145,10 @@ public: virtual bool IsMultiwordObject() { return false; } + bool IsUserCommand() { return m_is_user_command; } + + void SetIsUserCommand(bool is_user) { m_is_user_command = is_user; } + virtual CommandObjectMultiword *GetAsMultiwordCommand() { return nullptr; } virtual bool IsAlias() { return false; } @@ -159,6 +163,10 @@ public: return lldb::CommandObjectSP(); } + virtual lldb::CommandObjectSP GetSubcommandSPExact(llvm::StringRef sub_cmd) { + return lldb::CommandObjectSP(); + } + virtual CommandObject *GetSubcommandObject(llvm::StringRef sub_cmd, StringList *matches = nullptr) { return nullptr; @@ -183,6 +191,13 @@ public: return false; } + virtual llvm::Error LoadUserSubcommand(llvm::StringRef cmd_name, + const lldb::CommandObjectSP &command_obj, + bool can_replace) { + return llvm::createStringError(llvm::inconvertibleErrorCode(), + "can only add commands to container commands"); + } + virtual bool WantsRawCommandString() = 0; // By default, WantsCompletion = !WantsRawCommandString. Subclasses who want @@ -367,6 +382,7 @@ protected: lldb::CommandOverrideCallback m_deprecated_command_override_callback; lldb::CommandOverrideCallbackWithResult m_command_override_callback; void *m_command_override_baton; + bool m_is_user_command = false; // Helper function to populate IDs or ID ranges as the command argument data // to the specified command argument entry. diff --git a/lldb/include/lldb/Interpreter/CommandObjectMultiword.h b/lldb/include/lldb/Interpreter/CommandObjectMultiword.h index f330a745f9bd2e41b44c860363f400a621391216..a0e8d163c4b6d9adef2235fe4b0a733a442d2861 100644 --- a/lldb/include/lldb/Interpreter/CommandObjectMultiword.h +++ b/lldb/include/lldb/Interpreter/CommandObjectMultiword.h @@ -35,11 +35,19 @@ public: bool LoadSubCommand(llvm::StringRef cmd_name, const lldb::CommandObjectSP &command_obj) override; + llvm::Error LoadUserSubcommand(llvm::StringRef cmd_name, + const lldb::CommandObjectSP &command_obj, + bool can_replace) override; + + llvm::Error RemoveUserSubcommand(llvm::StringRef cmd_name, bool multiword_okay); + void GenerateHelpText(Stream &output_stream) override; lldb::CommandObjectSP GetSubcommandSP(llvm::StringRef sub_cmd, StringList *matches = nullptr) override; + lldb::CommandObjectSP GetSubcommandSPExact(llvm::StringRef sub_cmd) override; + CommandObject *GetSubcommandObject(llvm::StringRef sub_cmd, StringList *matches = nullptr) override; diff --git a/lldb/packages/Python/lldbsuite/test/lldbutil.py b/lldb/packages/Python/lldbsuite/test/lldbutil.py index 20a6d28274b3d8f9c1cc19219abe04488cff4478..2ab372d82b72dac4175a7b9c714989fe14afb1e8 100644 --- a/lldb/packages/Python/lldbsuite/test/lldbutil.py +++ b/lldb/packages/Python/lldbsuite/test/lldbutil.py @@ -953,7 +953,8 @@ def run_to_source_breakpoint(test, bkpt_pattern, source_spec, bkpt_module = None, in_cwd = True, only_one_thread = True, - extra_images = None): + extra_images = None, + has_locations_before_run = True): """Start up a target, using exe_name as the executable, and run it to a breakpoint set by source regex bkpt_pattern. @@ -964,9 +965,10 @@ def run_to_source_breakpoint(test, bkpt_pattern, source_spec, # Set the breakpoints breakpoint = target.BreakpointCreateBySourceRegex( bkpt_pattern, source_spec, bkpt_module) - test.assertTrue(breakpoint.GetNumLocations() > 0, - 'No locations found for source breakpoint: "%s", file: "%s", dir: "%s"' - %(bkpt_pattern, source_spec.GetFilename(), source_spec.GetDirectory())) + if has_locations_before_run: + test.assertTrue(breakpoint.GetNumLocations() > 0, + 'No locations found for source breakpoint: "%s", file: "%s", dir: "%s"' + %(bkpt_pattern, source_spec.GetFilename(), source_spec.GetDirectory())) return run_to_breakpoint_do_run(test, target, breakpoint, launch_info, only_one_thread, extra_images) diff --git a/lldb/source/API/SBCommandInterpreter.cpp b/lldb/source/API/SBCommandInterpreter.cpp index b4a69c3e972a460233c6fc8c538838a524126a17..3830f6ed80bafd6173f153c7eb3d9ba065370c17 100644 --- a/lldb/source/API/SBCommandInterpreter.cpp +++ b/lldb/source/API/SBCommandInterpreter.cpp @@ -574,12 +574,11 @@ lldb::SBCommand SBCommandInterpreter::AddMultiwordCommand(const char *name, LLDB_RECORD_METHOD(lldb::SBCommand, SBCommandInterpreter, AddMultiwordCommand, (const char *, const char *), name, help); - CommandObjectMultiword *new_command = - new CommandObjectMultiword(*m_opaque_ptr, name, help); - new_command->SetRemovable(true); - lldb::CommandObjectSP new_command_sp(new_command); - if (new_command_sp && - m_opaque_ptr->AddUserCommand(name, new_command_sp, true)) + lldb::CommandObjectSP new_command_sp( + new CommandObjectMultiword(*m_opaque_ptr, name, help)); + new_command_sp->GetAsMultiwordCommand()->SetRemovable(true); + Status add_error = m_opaque_ptr->AddUserCommand(name, new_command_sp, true); + if (add_error.Success()) return LLDB_RECORD_RESULT(lldb::SBCommand(new_command_sp)); return LLDB_RECORD_RESULT(lldb::SBCommand()); } @@ -620,8 +619,8 @@ lldb::SBCommand SBCommandInterpreter::AddCommand( *m_opaque_ptr, name, impl, help, syntax, /*flags=*/0, auto_repeat_command); - if (new_command_sp && - m_opaque_ptr->AddUserCommand(name, new_command_sp, true)) + Status add_error = m_opaque_ptr->AddUserCommand(name, new_command_sp, true); + if (add_error.Success()) return LLDB_RECORD_RESULT(lldb::SBCommand(new_command_sp)); return LLDB_RECORD_RESULT(lldb::SBCommand()); } diff --git a/lldb/source/Breakpoint/BreakpointList.cpp b/lldb/source/Breakpoint/BreakpointList.cpp index a00f6bed6181633bdede1d8756de7ea2cd0ba57a..ca181ee306a4ee940834e81d83eda7b95ed474e2 100644 --- a/lldb/source/Breakpoint/BreakpointList.cpp +++ b/lldb/source/Breakpoint/BreakpointList.cpp @@ -101,10 +101,8 @@ void BreakpointList::RemoveAllowed(bool notify) { NotifyChange(bp_sp, eBreakpointEventTypeRemoved); } - m_breakpoints.erase( - std::remove_if(m_breakpoints.begin(), m_breakpoints.end(), - [&](const BreakpointSP &bp) { return bp->AllowDelete(); }), - m_breakpoints.end()); + llvm::erase_if(m_breakpoints, + [&](const BreakpointSP &bp) { return bp->AllowDelete(); }); } BreakpointList::bp_collection::iterator diff --git a/lldb/source/Commands/CommandCompletions.cpp b/lldb/source/Commands/CommandCompletions.cpp index 191c25f5e677174a454b3ff050d6eac09915868b..42b0bac717bd43224ae472d821a661e1eb9b3428 100644 --- a/lldb/source/Commands/CommandCompletions.cpp +++ b/lldb/source/Commands/CommandCompletions.cpp @@ -17,6 +17,8 @@ #include "lldb/Host/FileSystem.h" #include "lldb/Interpreter/CommandCompletions.h" #include "lldb/Interpreter/CommandInterpreter.h" +#include "lldb/Interpreter/CommandObject.h" +#include "lldb/Interpreter/CommandObjectMultiword.h" #include "lldb/Interpreter/OptionValueProperties.h" #include "lldb/Symbol/CompileUnit.h" #include "lldb/Symbol/Variable.h" @@ -792,3 +794,60 @@ void CommandCompletions::TypeCategoryNames(CommandInterpreter &interpreter, return true; }); } + +void CommandCompletions::CompleteModifiableCmdPathArgs( + CommandInterpreter &interpreter, CompletionRequest &request, + OptionElementVector &opt_element_vector) { + // The only arguments constitute a command path, however, there might be + // options interspersed among the arguments, and we need to skip those. Do that + // by copying the args vector, and just dropping all the option bits: + Args args = request.GetParsedLine(); + std::vector to_delete; + for (auto &elem : opt_element_vector) { + to_delete.push_back(elem.opt_pos); + if (elem.opt_arg_pos != 0) + to_delete.push_back(elem.opt_arg_pos); + } + sort(to_delete.begin(), to_delete.end(), std::greater()); + for (size_t idx : to_delete) + args.DeleteArgumentAtIndex(idx); + + // At this point, we should only have args, so now lookup the command up to + // the cursor element. + + // There's nothing here but options. It doesn't seem very useful here to + // dump all the commands, so just return. + size_t num_args = args.GetArgumentCount(); + if (num_args == 0) + return; + + // There's just one argument, so we should complete its name: + StringList matches; + if (num_args == 1) { + interpreter.GetUserCommandObject(args.GetArgumentAtIndex(0), &matches, + nullptr); + request.AddCompletions(matches); + return; + } + + // There was more than one path element, lets find the containing command: + Status error; + CommandObjectMultiword *mwc = + interpreter.VerifyUserMultiwordCmdPath(args, true, error); + + // Something was wrong somewhere along the path, but I don't think there's + // a good way to go back and fill in the missing elements: + if (error.Fail()) + return; + + // This should never happen. We already handled the case of one argument + // above, and we can only get Success & nullptr back if there's a one-word + // leaf. + assert(mwc != nullptr); + + mwc->GetSubcommandObject(args.GetArgumentAtIndex(num_args - 1), &matches); + if (matches.GetSize() == 0) + return; + + request.AddCompletions(matches); +} diff --git a/lldb/source/Commands/CommandObjectApropos.cpp b/lldb/source/Commands/CommandObjectApropos.cpp index 656487169a34d7ad6b13c7a47183e318516e020a..c6680f8b140d16b821e9239228c60ef1c9209ecb 100644 --- a/lldb/source/Commands/CommandObjectApropos.cpp +++ b/lldb/source/Commands/CommandObjectApropos.cpp @@ -49,8 +49,8 @@ bool CommandObjectApropos::DoExecute(Args &args, CommandReturnObject &result) { StringList commands_found; StringList commands_help; - m_interpreter.FindCommandsForApropos(search_word, commands_found, - commands_help, true, true, true); + m_interpreter.FindCommandsForApropos( + search_word, commands_found, commands_help, true, true, true, true); if (commands_found.GetSize() == 0) { result.AppendMessageWithFormat("No commands found pertaining to '%s'. " diff --git a/lldb/source/Commands/CommandObjectCommands.cpp b/lldb/source/Commands/CommandObjectCommands.cpp index 639279875e7155b526f207eae98dfa8db2b9a5a5..1ec54cf7ededa24137f9e4aa3e751408ec7f671d 100644 --- a/lldb/source/Commands/CommandObjectCommands.cpp +++ b/lldb/source/Commands/CommandObjectCommands.cpp @@ -443,6 +443,14 @@ protected: return false; } + if (m_interpreter.UserMultiwordCommandExists(alias_command)) { + result.AppendErrorWithFormat( + "'%s' is a user container command and cannot be overwritten.\n" + "Delete it first with 'command container delete'\n", + args[0].c_str()); + return false; + } + // Get CommandObject that is being aliased. The command name is read from // the front of raw_command_string. raw_command_string is returned with the // name of the command object stripped off the front. @@ -528,6 +536,14 @@ protected: return false; } + if (m_interpreter.UserMultiwordCommandExists(alias_command)) { + result.AppendErrorWithFormat( + "'%s' is user container command and cannot be overwritten.\n" + "Delete it first with 'command container delete'", + alias_command.c_str()); + return false; + } + CommandObjectSP command_obj_sp( m_interpreter.GetCommandSPExact(actual_command, true)); CommandObjectSP subcommand_obj_sp; @@ -1371,14 +1387,21 @@ public: CommandObjectCommandsScriptAdd(CommandInterpreter &interpreter) : CommandObjectParsed(interpreter, "command script add", "Add a scripted function as an LLDB command.", - nullptr), + "Add a scripted function as an lldb command. " + "If you provide a single argument, the command " + "will be added at the root level of the command " + "hierarchy. If there are more arguments they " + "must be a path to a user-added container " + "command, and the last element will be the new " + "command name."), IOHandlerDelegateMultiline("DONE"), m_options() { CommandArgumentEntry arg1; CommandArgumentData cmd_arg; - // Define the first (and only) variant of this arg. - cmd_arg.arg_type = eArgTypeCommandName; - cmd_arg.arg_repetition = eArgRepeatPlain; + // This is one or more command names, which form the path to the command + // you want to add. + cmd_arg.arg_type = eArgTypeCommand; + cmd_arg.arg_repetition = eArgRepeatPlus; // There is only one variant this argument could be; put it into the // argument entry. @@ -1392,6 +1415,13 @@ public: Options *GetOptions() override { return &m_options; } + void + HandleArgumentCompletion(CompletionRequest &request, + OptionElementVector &opt_element_vector) override { + CommandCompletions::CompleteModifiableCmdPathArgs(m_interpreter, request, + opt_element_vector); + } + protected: class CommandOptions : public Options { public: @@ -1418,6 +1448,9 @@ protected: if (!option_arg.empty()) m_short_help = std::string(option_arg); break; + case 'o': + m_overwrite = true; + break; case 's': m_synchronicity = (ScriptedCommandSynchronicity)OptionArgParser::ToOptionEnum( @@ -1438,6 +1471,7 @@ protected: m_class_name.clear(); m_funct_name.clear(); m_short_help.clear(); + m_overwrite = false; m_synchronicity = eScriptedCommandSynchronicitySynchronous; } @@ -1450,6 +1484,7 @@ protected: std::string m_class_name; std::string m_funct_name; std::string m_short_help; + bool m_overwrite; ScriptedCommandSynchronicity m_synchronicity = eScriptedCommandSynchronicitySynchronous; }; @@ -1484,26 +1519,36 @@ protected: CommandObjectSP command_obj_sp(new CommandObjectPythonFunction( m_interpreter, m_cmd_name, funct_name_str, m_short_help, m_synchronicity)); - - if (!m_interpreter.AddUserCommand(m_cmd_name, command_obj_sp, - true)) { - error_sp->Printf("error: unable to add selected command, didn't " - "add python command.\n"); - error_sp->Flush(); + if (!m_container) { + Status error = m_interpreter.AddUserCommand( + m_cmd_name, command_obj_sp, m_overwrite); + if (error.Fail()) { + error_sp->Printf("error: unable to add selected command: '%s'", + error.AsCString()); + error_sp->Flush(); + } + } else { + llvm::Error llvm_error = m_container->LoadUserSubcommand( + m_cmd_name, command_obj_sp, m_overwrite); + if (llvm_error) { + error_sp->Printf("error: unable to add selected command: '%s'", + llvm::toString(std::move(llvm_error)).c_str()); + error_sp->Flush(); + } } } } else { error_sp->Printf( - "error: unable to create function, didn't add python command.\n"); + "error: unable to create function, didn't add python command\n"); error_sp->Flush(); } } else { - error_sp->Printf("error: empty function, didn't add python command.\n"); + error_sp->Printf("error: empty function, didn't add python command\n"); error_sp->Flush(); } } else { error_sp->Printf( - "error: script interpreter missing, didn't add python command.\n"); + "error: script interpreter missing, didn't add python command\n"); error_sp->Flush(); } @@ -1517,31 +1562,45 @@ protected: return false; } - if (command.GetArgumentCount() != 1) { - result.AppendError("'command script add' requires one argument"); + if (command.GetArgumentCount() == 0) { + result.AppendError("'command script add' requires at least one argument"); return false; } - // Store the options in case we get multi-line input - m_cmd_name = std::string(command[0].ref()); + m_overwrite = m_options.m_overwrite; + Status path_error; + m_container = GetCommandInterpreter().VerifyUserMultiwordCmdPath( + command, true, path_error); + + if (path_error.Fail()) { + result.AppendErrorWithFormat("error in command path: %s", + path_error.AsCString()); + return false; + } + + if (!m_container) { + // This is getting inserted into the root of the interpreter. + m_cmd_name = std::string(command[0].ref()); + } else { + size_t num_args = command.GetArgumentCount(); + m_cmd_name = std::string(command[num_args - 1].ref()); + } + m_short_help.assign(m_options.m_short_help); m_synchronicity = m_options.m_synchronicity; + // Handle the case where we prompt for the script code first: + if (m_options.m_class_name.empty() && m_options.m_funct_name.empty()) { + m_interpreter.GetPythonCommandsFromIOHandler(" ", // Prompt + *this); // IOHandlerDelegate + return result.Succeeded(); + } + + CommandObjectSP new_cmd_sp; if (m_options.m_class_name.empty()) { - if (m_options.m_funct_name.empty()) { - m_interpreter.GetPythonCommandsFromIOHandler( - " ", // Prompt - *this); // IOHandlerDelegate - } else { - CommandObjectSP new_cmd(new CommandObjectPythonFunction( - m_interpreter, m_cmd_name, m_options.m_funct_name, - m_options.m_short_help, m_synchronicity)); - if (m_interpreter.AddUserCommand(m_cmd_name, new_cmd, true)) { - result.SetStatus(eReturnStatusSuccessFinishNoResult); - } else { - result.AppendError("cannot add command"); - } - } + new_cmd_sp.reset(new CommandObjectPythonFunction( + m_interpreter, m_cmd_name, m_options.m_funct_name, + m_options.m_short_help, m_synchronicity)); } else { ScriptInterpreter *interpreter = GetDebugger().GetScriptInterpreter(); if (!interpreter) { @@ -1556,21 +1615,33 @@ protected: return false; } - CommandObjectSP new_cmd(new CommandObjectScriptingObject( + new_cmd_sp.reset(new CommandObjectScriptingObject( m_interpreter, m_cmd_name, cmd_obj_sp, m_synchronicity)); - if (m_interpreter.AddUserCommand(m_cmd_name, new_cmd, true)) { - result.SetStatus(eReturnStatusSuccessFinishNoResult); - } else { - result.AppendError("cannot add command"); - } } - + + // Assume we're going to succeed... + result.SetStatus(eReturnStatusSuccessFinishNoResult); + if (!m_container) { + Status add_error = + m_interpreter.AddUserCommand(m_cmd_name, new_cmd_sp, m_overwrite); + if (add_error.Fail()) + result.AppendErrorWithFormat("cannot add command: %s", + add_error.AsCString()); + } else { + llvm::Error llvm_error = + m_container->LoadUserSubcommand(m_cmd_name, new_cmd_sp, m_overwrite); + if (llvm_error) + result.AppendErrorWithFormat("cannot add command: %s", + llvm::toString(std::move(llvm_error)).c_str()); + } return result.Succeeded(); } CommandOptions m_options; std::string m_cmd_name; + CommandObjectMultiword *m_container = nullptr; std::string m_short_help; + bool m_overwrite; ScriptedCommandSynchronicity m_synchronicity; }; @@ -1580,7 +1651,8 @@ class CommandObjectCommandsScriptList : public CommandObjectParsed { public: CommandObjectCommandsScriptList(CommandInterpreter &interpreter) : CommandObjectParsed(interpreter, "command script list", - "List defined scripted commands.", nullptr) {} + "List defined top-level scripted commands.", + nullptr) {} ~CommandObjectCommandsScriptList() override = default; @@ -1628,14 +1700,17 @@ protected: class CommandObjectCommandsScriptDelete : public CommandObjectParsed { public: CommandObjectCommandsScriptDelete(CommandInterpreter &interpreter) - : CommandObjectParsed(interpreter, "command script delete", - "Delete a scripted command.", nullptr) { + : CommandObjectParsed( + interpreter, "command script delete", + "Delete a scripted command by specifying the path to the command.", + nullptr) { CommandArgumentEntry arg1; CommandArgumentData cmd_arg; - // Define the first (and only) variant of this arg. - cmd_arg.arg_type = eArgTypeCommandName; - cmd_arg.arg_repetition = eArgRepeatPlain; + // This is a list of command names forming the path to the command + // to be deleted. + cmd_arg.arg_type = eArgTypeCommand; + cmd_arg.arg_repetition = eArgRepeatPlus; // There is only one variant this argument could be; put it into the // argument entry. @@ -1650,30 +1725,86 @@ public: void HandleArgumentCompletion(CompletionRequest &request, OptionElementVector &opt_element_vector) override { - if (!m_interpreter.HasCommands() || request.GetCursorIndex() != 0) - return; - - for (const auto &c : m_interpreter.GetUserCommands()) - request.TryCompleteCurrentArg(c.first, c.second->GetHelp()); + CommandCompletions::CompleteModifiableCmdPathArgs(m_interpreter, request, + opt_element_vector); } protected: bool DoExecute(Args &command, CommandReturnObject &result) override { - if (command.GetArgumentCount() != 1) { - result.AppendError("'command script delete' requires one argument"); + llvm::StringRef root_cmd = command[0].ref(); + size_t num_args = command.GetArgumentCount(); + + if (root_cmd.empty()) { + result.AppendErrorWithFormat("empty root command name"); + return false; + } + if (!m_interpreter.HasUserCommands() && + !m_interpreter.HasUserMultiwordCommands()) { + result.AppendErrorWithFormat("can only delete user defined commands, " + "but no user defined commands found"); return false; } - auto cmd_name = command[0].ref(); + CommandObjectSP cmd_sp = m_interpreter.GetCommandSPExact(root_cmd); + if (!cmd_sp) { + result.AppendErrorWithFormat("command '%s' not found.", + command[0].c_str()); + return false; + } + if (!cmd_sp->IsUserCommand()) { + result.AppendErrorWithFormat("command '%s' is not a user command.", + command[0].c_str()); + return false; + } + if (cmd_sp->GetAsMultiwordCommand() && num_args == 1) { + result.AppendErrorWithFormat("command '%s' is a multi-word command.\n " + "Delete with \"command container delete\"", + command[0].c_str()); + return false; + } - if (cmd_name.empty() || !m_interpreter.HasUserCommands() || - !m_interpreter.UserCommandExists(cmd_name)) { - result.AppendErrorWithFormat("command %s not found", command[0].c_str()); + if (command.GetArgumentCount() == 1) { + m_interpreter.RemoveUser(root_cmd); + result.SetStatus(eReturnStatusSuccessFinishResult); + return true; + } + // We're deleting a command from a multiword command. Verify the command + // path: + Status error; + CommandObjectMultiword *container = + GetCommandInterpreter().VerifyUserMultiwordCmdPath(command, true, + error); + if (error.Fail()) { + result.AppendErrorWithFormat("could not resolve command path: %s", + error.AsCString()); + return false; + } + if (!container) { + // This means that command only had a leaf command, so the container is + // the root. That should have been handled above. + result.AppendErrorWithFormat("could not find a container for '%s'", + command[0].c_str()); + return false; + } + const char *leaf_cmd = command[num_args - 1].c_str(); + llvm::Error llvm_error = container->RemoveUserSubcommand(leaf_cmd, + /* multiword not okay */ false); + if (llvm_error) { + result.AppendErrorWithFormat("could not delete command '%s': %s", + leaf_cmd, + llvm::toString(std::move(llvm_error)).c_str()); return false; } - m_interpreter.RemoveUser(cmd_name); + Stream &out_stream = result.GetOutputStream(); + + out_stream << "Deleted command:"; + for (size_t idx = 0; idx < num_args; idx++) { + out_stream << ' '; + out_stream << command[idx].c_str(); + } + out_stream << '\n'; result.SetStatus(eReturnStatusSuccessFinishResult); return true; } @@ -1710,6 +1841,271 @@ public: ~CommandObjectMultiwordCommandsScript() override = default; }; +#pragma mark CommandObjectCommandContainer +#define LLDB_OPTIONS_container_add +#include "CommandOptions.inc" + +class CommandObjectCommandsContainerAdd : public CommandObjectParsed { +public: + CommandObjectCommandsContainerAdd(CommandInterpreter &interpreter) + : CommandObjectParsed( + interpreter, "command container add", + "Add a container command to lldb. Adding to built-" + "in container commands is not allowed.", + "command container add [[path1]...] container-name") { + CommandArgumentEntry arg1; + CommandArgumentData cmd_arg; + + // This is one or more command names, which form the path to the command + // you want to add. + cmd_arg.arg_type = eArgTypeCommand; + cmd_arg.arg_repetition = eArgRepeatPlus; + + // There is only one variant this argument could be; put it into the + // argument entry. + arg1.push_back(cmd_arg); + + // Push the data for the first argument into the m_arguments vector. + m_arguments.push_back(arg1); + } + + ~CommandObjectCommandsContainerAdd() override = default; + + Options *GetOptions() override { return &m_options; } + + void + HandleArgumentCompletion(CompletionRequest &request, + OptionElementVector &opt_element_vector) override { + CommandCompletions::CompleteModifiableCmdPathArgs(m_interpreter, request, + opt_element_vector); + } + +protected: + class CommandOptions : public Options { + public: + CommandOptions() : Options(), m_short_help(), m_long_help() {} + + ~CommandOptions() override = default; + + Status SetOptionValue(uint32_t option_idx, llvm::StringRef option_arg, + ExecutionContext *execution_context) override { + Status error; + const int short_option = m_getopt_table[option_idx].val; + + switch (short_option) { + case 'h': + if (!option_arg.empty()) + m_short_help = std::string(option_arg); + break; + case 'o': + m_overwrite = true; + break; + case 'H': + if (!option_arg.empty()) + m_long_help = std::string(option_arg); + break; + default: + llvm_unreachable("Unimplemented option"); + } + + return error; + } + + void OptionParsingStarting(ExecutionContext *execution_context) override { + m_short_help.clear(); + m_long_help.clear(); + m_overwrite = false; + } + + llvm::ArrayRef GetDefinitions() override { + return llvm::makeArrayRef(g_container_add_options); + } + + // Instance variables to hold the values for command options. + + std::string m_short_help; + std::string m_long_help; + bool m_overwrite = false; + }; + bool DoExecute(Args &command, CommandReturnObject &result) override { + size_t num_args = command.GetArgumentCount(); + + if (num_args == 0) { + result.AppendError("no command was specified"); + return false; + } + + if (num_args == 1) { + // We're adding this as a root command, so use the interpreter. + const char *cmd_name = command.GetArgumentAtIndex(0); + auto cmd_sp = CommandObjectSP(new CommandObjectMultiword( + GetCommandInterpreter(), cmd_name, m_options.m_short_help.c_str(), + m_options.m_long_help.c_str())); + cmd_sp->GetAsMultiwordCommand()->SetRemovable(true); + Status add_error = GetCommandInterpreter().AddUserCommand( + cmd_name, cmd_sp, m_options.m_overwrite); + if (add_error.Fail()) { + result.AppendErrorWithFormat("error adding command: %s", + add_error.AsCString()); + return false; + } + result.SetStatus(eReturnStatusSuccessFinishNoResult); + return true; + } + + // We're adding this to a subcommand, first find the subcommand: + Status path_error; + CommandObjectMultiword *add_to_me = + GetCommandInterpreter().VerifyUserMultiwordCmdPath(command, true, + path_error); + + if (!add_to_me) { + result.AppendErrorWithFormat("error adding command: %s", + path_error.AsCString()); + return false; + } + + const char *cmd_name = command.GetArgumentAtIndex(num_args - 1); + auto cmd_sp = CommandObjectSP(new CommandObjectMultiword( + GetCommandInterpreter(), cmd_name, m_options.m_short_help.c_str(), + m_options.m_long_help.c_str())); + llvm::Error llvm_error = + add_to_me->LoadUserSubcommand(cmd_name, cmd_sp, m_options.m_overwrite); + if (llvm_error) { + result.AppendErrorWithFormat("error adding subcommand: %s", + llvm::toString(std::move(llvm_error)).c_str()); + return false; + } + + result.SetStatus(eReturnStatusSuccessFinishNoResult); + return true; + } + +private: + CommandOptions m_options; +}; + +#define LLDB_OPTIONS_multiword_delete +#include "CommandOptions.inc" +class CommandObjectCommandsContainerDelete : public CommandObjectParsed { +public: + CommandObjectCommandsContainerDelete(CommandInterpreter &interpreter) + : CommandObjectParsed( + interpreter, "command container delete", + "Delete a container command previously added to " + "lldb.", + "command container delete [[path1] ...] container-cmd") { + CommandArgumentEntry arg1; + CommandArgumentData cmd_arg; + + // This is one or more command names, which form the path to the command + // you want to add. + cmd_arg.arg_type = eArgTypeCommand; + cmd_arg.arg_repetition = eArgRepeatPlus; + + // There is only one variant this argument could be; put it into the + // argument entry. + arg1.push_back(cmd_arg); + + // Push the data for the first argument into the m_arguments vector. + m_arguments.push_back(arg1); + } + + ~CommandObjectCommandsContainerDelete() override = default; + + void + HandleArgumentCompletion(CompletionRequest &request, + OptionElementVector &opt_element_vector) override { + CommandCompletions::CompleteModifiableCmdPathArgs(m_interpreter, request, + opt_element_vector); + } + +protected: + bool DoExecute(Args &command, CommandReturnObject &result) override { + size_t num_args = command.GetArgumentCount(); + + if (num_args == 0) { + result.AppendError("No command was specified."); + return false; + } + + if (num_args == 1) { + // We're removing a root command, so we need to delete it from the + // interpreter. + const char *cmd_name = command.GetArgumentAtIndex(0); + // Let's do a little more work here so we can do better error reporting. + CommandInterpreter &interp = GetCommandInterpreter(); + CommandObjectSP cmd_sp = interp.GetCommandSPExact(cmd_name); + if (!cmd_sp) { + result.AppendErrorWithFormat("container command %s doesn't exist.", + cmd_name); + return false; + } + if (!cmd_sp->IsUserCommand()) { + result.AppendErrorWithFormat( + "container command %s is not a user command", cmd_name); + return false; + } + if (!cmd_sp->GetAsMultiwordCommand()) { + result.AppendErrorWithFormat("command %s is not a container command", + cmd_name); + return false; + } + + bool did_remove = GetCommandInterpreter().RemoveUserMultiword(cmd_name); + if (!did_remove) { + result.AppendErrorWithFormat("error removing command %s.", cmd_name); + return false; + } + + result.SetStatus(eReturnStatusSuccessFinishNoResult); + return true; + } + + // We're removing a subcommand, first find the subcommand's owner: + Status path_error; + CommandObjectMultiword *container = + GetCommandInterpreter().VerifyUserMultiwordCmdPath(command, true, + path_error); + + if (!container) { + result.AppendErrorWithFormat("error removing container command: %s", + path_error.AsCString()); + return false; + } + const char *leaf = command.GetArgumentAtIndex(num_args - 1); + llvm::Error llvm_error = + container->RemoveUserSubcommand(leaf, /* multiword okay */ true); + if (llvm_error) { + result.AppendErrorWithFormat("error removing container command: %s", + llvm::toString(std::move(llvm_error)).c_str()); + return false; + } + result.SetStatus(eReturnStatusSuccessFinishNoResult); + return true; + } +}; + +class CommandObjectCommandContainer : public CommandObjectMultiword { +public: + CommandObjectCommandContainer(CommandInterpreter &interpreter) + : CommandObjectMultiword( + interpreter, "command container", + "Commands for adding container commands to lldb. " + "Container commands are containers for other commands. You can" + "add nested container commands by specifying a command path, but " + "but you can't add commands into the built-in command hierarchy.", + "command container []") { + LoadSubCommand("add", CommandObjectSP(new CommandObjectCommandsContainerAdd( + interpreter))); + LoadSubCommand( + "delete", + CommandObjectSP(new CommandObjectCommandsContainerDelete(interpreter))); + } + + ~CommandObjectCommandContainer() override = default; +}; + #pragma mark CommandObjectMultiwordCommands // CommandObjectMultiwordCommands @@ -1727,6 +2123,8 @@ CommandObjectMultiwordCommands::CommandObjectMultiwordCommands( new CommandObjectCommandsUnalias(interpreter))); LoadSubCommand("delete", CommandObjectSP(new CommandObjectCommandsDelete(interpreter))); + LoadSubCommand("container", CommandObjectSP(new CommandObjectCommandContainer( + interpreter))); LoadSubCommand( "regex", CommandObjectSP(new CommandObjectCommandsAddRegex(interpreter))); LoadSubCommand( diff --git a/lldb/source/Commands/CommandObjectHelp.cpp b/lldb/source/Commands/CommandObjectHelp.cpp index 4643ee30f0f9bf94bd442ec247e0b966ade5f2be..8c24efaa08ee3cf0700a98b019e48de51b272de0 100644 --- a/lldb/source/Commands/CommandObjectHelp.cpp +++ b/lldb/source/Commands/CommandObjectHelp.cpp @@ -51,8 +51,9 @@ CommandObjectHelp::CommandObjectHelp(CommandInterpreter &interpreter) CommandArgumentEntry arg; CommandArgumentData command_arg; - // Define the first (and only) variant of this arg. - command_arg.arg_type = eArgTypeCommandName; + // A list of command names forming a path to the command we want help on. + // No names is allowed - in which case we dump the top-level help. + command_arg.arg_type = eArgTypeCommand; command_arg.arg_repetition = eArgRepeatStar; // There is only one variant this argument could be; put it into the argument @@ -85,8 +86,10 @@ bool CommandObjectHelp::DoExecute(Args &command, CommandReturnObject &result) { uint32_t cmd_types = CommandInterpreter::eCommandTypesBuiltin; if (m_options.m_show_aliases) cmd_types |= CommandInterpreter::eCommandTypesAliases; - if (m_options.m_show_user_defined) + if (m_options.m_show_user_defined) { cmd_types |= CommandInterpreter::eCommandTypesUserDef; + cmd_types |= CommandInterpreter::eCommandTypesUserMW; + } if (m_options.m_show_hidden) cmd_types |= CommandInterpreter::eCommandTypesHidden; diff --git a/lldb/source/Commands/CommandObjectMultiword.cpp b/lldb/source/Commands/CommandObjectMultiword.cpp index a523fd0b1560cffe06d80d3cf6abe1a0ed29e074..e800bcc12bd36641a08ea89712a5f1aaf0ffa435 100644 --- a/lldb/source/Commands/CommandObjectMultiword.cpp +++ b/lldb/source/Commands/CommandObjectMultiword.cpp @@ -26,36 +26,48 @@ CommandObjectMultiword::CommandObjectMultiword(CommandInterpreter &interpreter, CommandObjectMultiword::~CommandObjectMultiword() = default; +CommandObjectSP +CommandObjectMultiword::GetSubcommandSPExact(llvm::StringRef sub_cmd) { + if (m_subcommand_dict.empty()) + return {}; + + auto pos = m_subcommand_dict.find(std::string(sub_cmd)); + if (pos == m_subcommand_dict.end()) + return {}; + + return pos->second; +} + CommandObjectSP CommandObjectMultiword::GetSubcommandSP(llvm::StringRef sub_cmd, StringList *matches) { - CommandObjectSP return_cmd_sp; + if (m_subcommand_dict.empty()) + return {}; + + CommandObjectSP return_cmd_sp = GetSubcommandSPExact(sub_cmd); + if (return_cmd_sp) { + if (matches) + matches->AppendString(sub_cmd); + return return_cmd_sp; + } + CommandObject::CommandMap::iterator pos; - if (!m_subcommand_dict.empty()) { + StringList local_matches; + if (matches == nullptr) + matches = &local_matches; + int num_matches = + AddNamesMatchingPartialString(m_subcommand_dict, sub_cmd, *matches); + + if (num_matches == 1) { + // Cleaner, but slightly less efficient would be to call back into this + // function, since I now know I have an exact match... + + sub_cmd = matches->GetStringAtIndex(0); pos = m_subcommand_dict.find(std::string(sub_cmd)); - if (pos != m_subcommand_dict.end()) { - // An exact match; append the sub_cmd to the 'matches' string list. - if (matches) - matches->AppendString(sub_cmd); + if (pos != m_subcommand_dict.end()) return_cmd_sp = pos->second; - } else { - StringList local_matches; - if (matches == nullptr) - matches = &local_matches; - int num_matches = - AddNamesMatchingPartialString(m_subcommand_dict, sub_cmd, *matches); - - if (num_matches == 1) { - // Cleaner, but slightly less efficient would be to call back into this - // function, since I now know I have an exact match... - - sub_cmd = matches->GetStringAtIndex(0); - pos = m_subcommand_dict.find(std::string(sub_cmd)); - if (pos != m_subcommand_dict.end()) - return_cmd_sp = pos->second; - } - } } + return return_cmd_sp; } @@ -66,9 +78,9 @@ CommandObjectMultiword::GetSubcommandObject(llvm::StringRef sub_cmd, } bool CommandObjectMultiword::LoadSubCommand(llvm::StringRef name, - const CommandObjectSP &cmd_obj) { - if (cmd_obj) - assert((&GetCommandInterpreter() == &cmd_obj->GetCommandInterpreter()) && + const CommandObjectSP &cmd_obj_sp) { + if (cmd_obj_sp) + lldbassert((&GetCommandInterpreter() == &cmd_obj_sp->GetCommandInterpreter()) && "tried to add a CommandObject from a different interpreter"); CommandMap::iterator pos; @@ -76,13 +88,76 @@ bool CommandObjectMultiword::LoadSubCommand(llvm::StringRef name, pos = m_subcommand_dict.find(std::string(name)); if (pos == m_subcommand_dict.end()) { - m_subcommand_dict[std::string(name)] = cmd_obj; + m_subcommand_dict[std::string(name)] = cmd_obj_sp; } else success = false; return success; } +llvm::Error CommandObjectMultiword::LoadUserSubcommand( + llvm::StringRef name, const CommandObjectSP &cmd_obj_sp, bool can_replace) { + Status result; + if (cmd_obj_sp) + lldbassert((&GetCommandInterpreter() == &cmd_obj_sp->GetCommandInterpreter()) && + "tried to add a CommandObject from a different interpreter"); + if (!IsUserCommand()) { + return llvm::createStringError(llvm::inconvertibleErrorCode(), + "can't add a user subcommand to a builtin container command."); + } + // Make sure this a user command if it isn't already: + cmd_obj_sp->SetIsUserCommand(true); + + std::string str_name(name); + + auto pos = m_subcommand_dict.find(str_name); + if (pos == m_subcommand_dict.end()) { + m_subcommand_dict[str_name] = cmd_obj_sp; + return llvm::Error::success(); + } + + const char *error_str = nullptr; + if (!can_replace) + error_str = "sub-command already exists"; + if (!(*pos).second->IsUserCommand()) + error_str = "can't replace a builtin subcommand"; + + if (error_str) { + return llvm::createStringError(llvm::inconvertibleErrorCode(), error_str); + } + m_subcommand_dict[str_name] = cmd_obj_sp; + return llvm::Error::success(); +} + +llvm::Error CommandObjectMultiword::RemoveUserSubcommand(llvm::StringRef cmd_name, + bool must_be_multiword) { + CommandMap::iterator pos; + std::string str_name(cmd_name); + + pos = m_subcommand_dict.find(str_name); + if (pos == m_subcommand_dict.end()) { + return llvm::createStringError(llvm::inconvertibleErrorCode(),"subcommand '%s' not found.", + str_name.c_str()); + } + if (!(*pos).second->IsUserCommand()) { + return llvm::createStringError(llvm::inconvertibleErrorCode(),"subcommand '%s' not a user command.", + str_name.c_str()); + } + + if (must_be_multiword && !(*pos).second->IsMultiwordObject()) { + return llvm::createStringError(llvm::inconvertibleErrorCode(),"subcommand '%s' is not a container command", + str_name.c_str()); + } + if (!must_be_multiword && (*pos).second->IsMultiwordObject()) { + return llvm::createStringError(llvm::inconvertibleErrorCode(),"subcommand '%s' is not a user command", + str_name.c_str()); + } + + m_subcommand_dict.erase(pos); + + return llvm::Error::success(); +} + bool CommandObjectMultiword::Execute(const char *args_string, CommandReturnObject &result) { Args args(args_string); diff --git a/lldb/source/Commands/Options.td b/lldb/source/Commands/Options.td index 3d69bb8ad8d05127f64248237beaca21ada83e5c..b9f8950d2cace6c1e7539f5445fee18b260c3cb2 100644 --- a/lldb/source/Commands/Options.td +++ b/lldb/source/Commands/Options.td @@ -787,12 +787,23 @@ let Command = "script add" in { Desc<"Name of the Python class to bind to this command name.">; def script_add_help : Option<"help", "h">, Group<1>, Arg<"HelpText">, Desc<"The help text to display for this command.">; + def script_add_overwrite : Option<"overwrite", "o">, Groups<[1,2]>, + Desc<"Overwrite an existing command at this node.">; def script_add_synchronicity : Option<"synchronicity", "s">, EnumArg<"ScriptedCommandSynchronicity", "ScriptSynchroType()">, Desc<"Set the synchronicity of this command's executions with regard to " "LLDB event system.">; } +let Command = "container add" in { + def container_add_help : Option<"help", "h">, Arg<"HelpText">, + Desc<"Help text for this command">; + def container_add_long_help : Option<"long-help", "H">, Arg<"HelpText">, + Desc<"Long help text for this command">; + def container_add_overwrite : Option<"overwrite", "o">, Group<1>, + Desc<"Overwrite an existing command at this node.">; +} + let Command = "script" in { def script_language : Option<"language", "l">, EnumArg<"ScriptLang", "ScriptOptionEnum()">, Desc<"Specify the scripting " diff --git a/lldb/source/Interpreter/CommandInterpreter.cpp b/lldb/source/Interpreter/CommandInterpreter.cpp index 223cccf28d74b3daf3c4764019af2782f5f226e7..1c43ea15af01b79c0227dc0245396033af9e4517 100644 --- a/lldb/source/Interpreter/CommandInterpreter.cpp +++ b/lldb/source/Interpreter/CommandInterpreter.cpp @@ -897,6 +897,63 @@ int CommandInterpreter::GetCommandNamesMatchingPartialString( return matches.GetSize(); } +CommandObjectMultiword *CommandInterpreter::VerifyUserMultiwordCmdPath( + Args &path, bool leaf_is_command, Status &result) { + result.Clear(); + + auto get_multi_or_report_error = + [&result](CommandObjectSP cmd_sp, + const char *name) -> CommandObjectMultiword * { + if (!cmd_sp) { + result.SetErrorStringWithFormat("Path component: '%s' not found", name); + return nullptr; + } + if (!cmd_sp->IsUserCommand()) { + result.SetErrorStringWithFormat("Path component: '%s' is not a user " + "command", + name); + return nullptr; + } + CommandObjectMultiword *cmd_as_multi = cmd_sp->GetAsMultiwordCommand(); + if (!cmd_as_multi) { + result.SetErrorStringWithFormat("Path component: '%s' is not a container " + "command", + name); + return nullptr; + } + return cmd_as_multi; + }; + + size_t num_args = path.GetArgumentCount(); + if (num_args == 0) { + result.SetErrorString("empty command path"); + return nullptr; + } + + if (num_args == 1 && leaf_is_command) { + // We just got a leaf command to be added to the root. That's not an error, + // just return null for the container. + return nullptr; + } + + // Start by getting the root command from the interpreter. + const char *cur_name = path.GetArgumentAtIndex(0); + CommandObjectSP cur_cmd_sp = GetCommandSPExact(cur_name); + CommandObjectMultiword *cur_as_multi = + get_multi_or_report_error(cur_cmd_sp, cur_name); + if (cur_as_multi == nullptr) + return nullptr; + + size_t num_path_elements = num_args - (leaf_is_command ? 1 : 0); + for (size_t cursor = 1; cursor < num_path_elements && cur_as_multi != nullptr; + cursor++) { + cur_name = path.GetArgumentAtIndex(cursor); + cur_cmd_sp = cur_as_multi->GetSubcommandSPExact(cur_name); + cur_as_multi = get_multi_or_report_error(cur_cmd_sp, cur_name); + } + return cur_as_multi; +} + CommandObjectSP CommandInterpreter::GetCommandSP(llvm::StringRef cmd_str, bool include_aliases, bool exact, StringList *matches, @@ -923,10 +980,17 @@ CommandInterpreter::GetCommandSP(llvm::StringRef cmd_str, bool include_aliases, command_sp = pos->second; } + if (HasUserMultiwordCommands()) { + auto pos = m_user_mw_dict.find(cmd); + if (pos != m_user_mw_dict.end()) + command_sp = pos->second; + } + if (!exact && !command_sp) { // We will only get into here if we didn't find any exact matches. - CommandObjectSP user_match_sp, alias_match_sp, real_match_sp; + CommandObjectSP user_match_sp, user_mw_match_sp, alias_match_sp, + real_match_sp; StringList local_matches; if (matches == nullptr) @@ -935,6 +999,7 @@ CommandInterpreter::GetCommandSP(llvm::StringRef cmd_str, bool include_aliases, unsigned int num_cmd_matches = 0; unsigned int num_alias_matches = 0; unsigned int num_user_matches = 0; + unsigned int num_user_mw_matches = 0; // Look through the command dictionaries one by one, and if we get only one // match from any of them in toto, then return that, otherwise return an @@ -978,14 +1043,32 @@ CommandInterpreter::GetCommandSP(llvm::StringRef cmd_str, bool include_aliases, user_match_sp = pos->second; } + if (HasUserMultiwordCommands()) { + num_user_mw_matches = AddNamesMatchingPartialString( + m_user_mw_dict, cmd_str, *matches, descriptions); + } + + if (num_user_mw_matches == 1) { + cmd.assign(matches->GetStringAtIndex(num_cmd_matches + num_alias_matches + + num_user_matches)); + + auto pos = m_user_mw_dict.find(cmd); + if (pos != m_user_mw_dict.end()) + user_mw_match_sp = pos->second; + } + // If we got exactly one match, return that, otherwise return the match // list. - if (num_user_matches + num_cmd_matches + num_alias_matches == 1) { + if (num_user_matches + num_user_mw_matches + num_cmd_matches + + num_alias_matches == + 1) { if (num_cmd_matches) return real_match_sp; else if (num_alias_matches) return alias_match_sp; + else if (num_user_mw_matches) + return user_mw_match_sp; else return user_match_sp; } @@ -1008,6 +1091,8 @@ bool CommandInterpreter::AddCommand(llvm::StringRef name, if (name.empty()) return false; + cmd_sp->SetIsUserCommand(false); + std::string name_sstr(name); auto name_iter = m_command_dict.find(name_sstr); if (name_iter != m_command_dict.end()) { @@ -1020,33 +1105,49 @@ bool CommandInterpreter::AddCommand(llvm::StringRef name, return true; } -bool CommandInterpreter::AddUserCommand(llvm::StringRef name, - const lldb::CommandObjectSP &cmd_sp, - bool can_replace) { +Status CommandInterpreter::AddUserCommand(llvm::StringRef name, + const lldb::CommandObjectSP &cmd_sp, + bool can_replace) { + Status result; if (cmd_sp.get()) lldbassert((this == &cmd_sp->GetCommandInterpreter()) && "tried to add a CommandObject from a different interpreter"); - - if (!name.empty()) { - // do not allow replacement of internal commands - if (CommandExists(name)) { - if (!can_replace) - return false; - if (!m_command_dict[std::string(name)]->IsRemovable()) - return false; + if (name.empty()) { + result.SetErrorString("can't use the empty string for a command name"); + return result; + } + // do not allow replacement of internal commands + if (CommandExists(name)) { + result.SetErrorString("can't replace builtin command"); + return result; + } + + if (UserCommandExists(name)) { + if (!can_replace) { + result.SetErrorString("user command exists and force replace not set"); + return result; + } + if (cmd_sp->IsMultiwordObject()) { + if (!m_user_mw_dict[std::string(name)]->IsRemovable()) { + result.SetErrorString( + "can't replace explicitly non-removable multi-word command"); + return result; + } + } else { + if (!m_user_dict[std::string(name)]->IsRemovable()) { + result.SetErrorString("can't replace explicitly non-removable command"); + return result; + } } + } - if (UserCommandExists(name)) { - if (!can_replace) - return false; - if (!m_user_dict[std::string(name)]->IsRemovable()) - return false; - } + cmd_sp->SetIsUserCommand(true); + if (cmd_sp->IsMultiwordObject()) + m_user_mw_dict[std::string(name)] = cmd_sp; + else m_user_dict[std::string(name)] = cmd_sp; - return true; - } - return false; + return result; } CommandObjectSP @@ -1127,6 +1228,44 @@ CommandInterpreter::GetCommandObject(llvm::StringRef cmd_str, return GetCommandSP(cmd_str, true, false, matches, descriptions).get(); } +CommandObject *CommandInterpreter::GetUserCommandObject( + llvm::StringRef cmd, StringList *matches, StringList *descriptions) const { + std::string cmd_str(cmd); + auto find_exact = [&](const CommandObject::CommandMap &map) { + auto found_elem = map.find(std::string(cmd)); + if (found_elem == map.end()) + return (CommandObject *)nullptr; + CommandObject *exact_cmd = found_elem->second.get(); + if (exact_cmd) { + if (matches) + matches->AppendString(exact_cmd->GetCommandName()); + if (descriptions) + descriptions->AppendString(exact_cmd->GetHelp()); + return exact_cmd; + } + return (CommandObject *)nullptr; + }; + + CommandObject *exact_cmd = find_exact(GetUserCommands()); + if (exact_cmd) + return exact_cmd; + + exact_cmd = find_exact(GetUserMultiwordCommands()); + if (exact_cmd) + return exact_cmd; + + // We didn't have an exact command, so now look for partial matches. + size_t num_found; + StringList tmp_list; + StringList *matches_ptr = matches ? matches : &tmp_list; + num_found = + AddNamesMatchingPartialString(GetUserCommands(), cmd_str, *matches_ptr); + num_found += AddNamesMatchingPartialString(GetUserMultiwordCommands(), + cmd_str, *matches_ptr); + + return {}; +} + bool CommandInterpreter::CommandExists(llvm::StringRef cmd) const { return m_command_dict.find(std::string(cmd)) != m_command_dict.end(); } @@ -1169,6 +1308,10 @@ bool CommandInterpreter::UserCommandExists(llvm::StringRef cmd) const { return m_user_dict.find(std::string(cmd)) != m_user_dict.end(); } +bool CommandInterpreter::UserMultiwordCommandExists(llvm::StringRef cmd) const { + return m_user_mw_dict.find(std::string(cmd)) != m_user_mw_dict.end(); +} + CommandAlias * CommandInterpreter::AddAlias(llvm::StringRef alias_name, lldb::CommandObjectSP &command_obj_sp, @@ -1209,9 +1352,10 @@ bool CommandInterpreter::RemoveCommand(llvm::StringRef cmd) { } return false; } -bool CommandInterpreter::RemoveUser(llvm::StringRef alias_name) { + +bool CommandInterpreter::RemoveUser(llvm::StringRef user_name) { CommandObject::CommandMap::iterator pos = - m_user_dict.find(std::string(alias_name)); + m_user_dict.find(std::string(user_name)); if (pos != m_user_dict.end()) { m_user_dict.erase(pos); return true; @@ -1219,6 +1363,16 @@ bool CommandInterpreter::RemoveUser(llvm::StringRef alias_name) { return false; } +bool CommandInterpreter::RemoveUserMultiword(llvm::StringRef multi_name) { + CommandObject::CommandMap::iterator pos = + m_user_mw_dict.find(std::string(multi_name)); + if (pos != m_user_mw_dict.end()) { + m_user_mw_dict.erase(pos); + return true; + } + return false; +} + void CommandInterpreter::GetHelp(CommandReturnObject &result, uint32_t cmd_types) { llvm::StringRef help_prologue(GetDebugger().GetIOHandlerHelpPrologue()); @@ -1274,6 +1428,18 @@ void CommandInterpreter::GetHelp(CommandReturnObject &result, result.AppendMessage(""); } + if (!m_user_mw_dict.empty() && + ((cmd_types & eCommandTypesUserMW) == eCommandTypesUserMW)) { + result.AppendMessage("Current user-defined container commands:"); + result.AppendMessage(""); + max_len = FindLongestCommandWord(m_user_mw_dict); + for (pos = m_user_dict.begin(); pos != m_user_mw_dict.end(); ++pos) { + OutputFormattedHelpText(result.GetOutputStream(), pos->first, "--", + pos->second->GetHelp(), max_len); + } + result.AppendMessage(""); + } + result.AppendMessageWithFormat( "For more information on any command, type '%shelp '.\n", GetCommandPrefix()); @@ -1931,6 +2097,10 @@ bool CommandInterpreter::HasAliases() const { return (!m_alias_dict.empty()); } bool CommandInterpreter::HasUserCommands() const { return (!m_user_dict.empty()); } +bool CommandInterpreter::HasUserMultiwordCommands() const { + return (!m_user_mw_dict.empty()); +} + bool CommandInterpreter::HasAliasOptions() const { return HasAliases(); } void CommandInterpreter::BuildAliasCommandArgs(CommandObject *alias_cmd_obj, @@ -2581,6 +2751,9 @@ void CommandInterpreter::OutputFormattedHelpText(Stream &strm, strm.IndentMore(prefix.size()); bool prefixed_yet = false; + // Even if we have no help text we still want to emit the command name. + if (help_text.empty()) + help_text = "No help text"; while (!help_text.empty()) { // Prefix the first line, indent subsequent lines to line up if (!prefixed_yet) { @@ -2700,7 +2873,8 @@ void CommandInterpreter::FindCommandsForApropos(llvm::StringRef search_word, StringList &commands_help, bool search_builtin_commands, bool search_user_commands, - bool search_alias_commands) { + bool search_alias_commands, + bool search_user_mw_commands) { CommandObject::CommandMap::const_iterator pos; if (search_builtin_commands) @@ -2711,6 +2885,10 @@ void CommandInterpreter::FindCommandsForApropos(llvm::StringRef search_word, FindCommandsForApropos(search_word, commands_found, commands_help, m_user_dict); + if (search_user_mw_commands) + FindCommandsForApropos(search_word, commands_found, commands_help, + m_user_mw_dict); + if (search_alias_commands) FindCommandsForApropos(search_word, commands_found, commands_help, m_alias_dict); diff --git a/lldb/source/Interpreter/CommandObject.cpp b/lldb/source/Interpreter/CommandObject.cpp index a7dcd5682701794a1b01b7835f5bfa2530ff5d10..64b23d04abea30c5d018507bf94b979cb8a2adea 100644 --- a/lldb/source/Interpreter/CommandObject.cpp +++ b/lldb/source/Interpreter/CommandObject.cpp @@ -1120,7 +1120,7 @@ CommandObject::ArgumentTableEntry CommandObject::g_arguments_data[] = { { eArgTypeWatchpointIDRange, "watchpt-id-list", CommandCompletions::eNoCompletion, { nullptr, false }, "For example, '1-3' or '1 to 3'." }, { eArgTypeWatchType, "watch-type", CommandCompletions::eNoCompletion, { nullptr, false }, "Specify the type for a watchpoint." }, { eArgRawInput, "raw-input", CommandCompletions::eNoCompletion, { nullptr, false }, "Free-form text passed to a command without prior interpretation, allowing spaces without requiring quotes. To pass arguments and free form text put two dashes ' -- ' between the last argument and any raw input." }, - { eArgTypeCommand, "command", CommandCompletions::eNoCompletion, { nullptr, false }, "An LLDB Command line command." }, + { eArgTypeCommand, "command", CommandCompletions::eNoCompletion, { nullptr, false }, "An LLDB Command line command element." }, { eArgTypeColumnNum, "column", CommandCompletions::eNoCompletion, { nullptr, false }, "Column number in a source file." }, { eArgTypeModuleUUID, "module-uuid", CommandCompletions::eModuleUUIDCompletion, { nullptr, false }, "A module UUID value." }, { eArgTypeSaveCoreStyle, "corefile-style", CommandCompletions::eNoCompletion, { nullptr, false }, "The type of corefile that lldb will try to create, dependant on this target's capabilities." } diff --git a/lldb/test/API/commands/command/container/TestContainerCommands.py b/lldb/test/API/commands/command/container/TestContainerCommands.py new file mode 100644 index 0000000000000000000000000000000000000000..408303dd43a5428615472bb45c09475d89637203 --- /dev/null +++ b/lldb/test/API/commands/command/container/TestContainerCommands.py @@ -0,0 +1,127 @@ +""" +Test user added container commands +""" + + +import sys +import lldb +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * + + +class TestCmdContainer(TestBase): + + mydir = TestBase.compute_mydir(__file__) + NO_DEBUG_INFO_TESTCASE = True + + def test_container_add(self): + self.container_add() + + def check_command_tree_exists(self): + """This makes sure we can still run the command tree we added.""" + self.runCmd("test-multi") + self.runCmd("test-multi test-multi-sub") + self.runCmd("test-multi test-multi-sub welcome") + + def container_add(self): + # Make sure we can't overwrite built-in commands: + self.expect("command container add process", "Can't replace builtin container command", + substrs=["can't replace builtin command"], error=True) + self.expect("command container add process non_such_subcommand", "Can't add to built-in subcommand", + substrs=["Path component: 'process' is not a user command"], error=True) + self.expect("command container add process launch", "Can't replace builtin subcommand", + substrs=["Path component: 'process' is not a user command"], error=True) + + # Now lets make a container command: + self.runCmd("command container add -h 'A test container command' test-multi") + # Make sure the help works: + self.expect("help test-multi", "Help works for top-level multi", + substrs=["A test container command"]) + # Add a subcommand: + self.runCmd("command container add -h 'A test container sub-command' test-multi test-multi-sub") + # Make sure the help works: + self.expect("help test-multi", "Help shows sub-multi", + substrs=["A test container command", "test-multi-sub -- A test container sub-command"]) + self.expect("help test-multi test-multi-sub", "Help shows sub-multi", + substrs=["A test container sub-command"]) + + # Now add a script based command to the container command: + self.runCmd("command script import welcome.py") + self.runCmd("command script add -c welcome.WelcomeCommand test-multi test-multi-sub welcome") + # Make sure the help still works: + self.expect("help test-multi test-multi-sub", "Listing subcommands works", + substrs=["A test container sub-command", "welcome -- Just a docstring for Welcome"]) + self.expect("help test-multi test-multi-sub welcome", "Subcommand help works", + substrs=["Just a docstring for Welcome"]) + # And make sure it actually works: + self.expect("test-multi test-multi-sub welcome friend", "Test command works", + substrs=["Hello friend, welcome to LLDB"]) + + # Make sure overwriting works, first the leaf command: + # We should not be able to remove extant commands by default: + self.expect("command script add -c welcome.WelcomeCommand2 test-multi test-multi-sub welcome", + "overwrite command w/o -o", + substrs=["cannot add command: sub-command already exists"], error=True) + # But we can with the -o option: + self.runCmd("command script add -c welcome.WelcomeCommand2 -o test-multi test-multi-sub welcome") + # Make sure we really did overwrite: + self.expect("test-multi test-multi-sub welcome friend", "Used the new command class", + substrs=["Hello friend, welcome again to LLDB"]) + + self.expect("apropos welcome", "welcome should show up in apropos", substrs=["Just a docstring for the second Welcome"]) + + # Make sure we give good errors when the input is wrong: + self.expect("command script delete test-mult test-multi-sub welcome", "Delete script command - wrong first path component", + substrs=["'test-mult' not found"], error=True) + + self.expect("command script delete test-multi test-multi-su welcome", "Delete script command - wrong second path component", + substrs=["'test-multi-su' not found"], error=True) + self.check_command_tree_exists() + + self.expect("command script delete test-multi test-multi-sub welcom", "Delete script command - wrong leaf component", + substrs=["'welcom' not found"], error=True) + self.check_command_tree_exists() + + self.expect("command script delete test-multi test-multi-sub", "Delete script command - no leaf component", + substrs=["subcommand 'test-multi-sub' is not a user command"], error=True) + self.check_command_tree_exists() + + # You can't use command script delete to delete container commands: + self.expect("command script delete test-multi", "Delete script - can't delete container", + substrs=["command 'test-multi' is a multi-word command."], error=True) + self.expect("command script delete test-multi test-multi-sub", "Delete script - can't delete container", + substrs=["subcommand 'test-multi-sub' is not a user command"], error = True) + + # You can't use command container delete to delete scripted commands: + self.expect("command container delete test-multi test-multi-sub welcome", "command container can't delete user commands", + substrs=["subcommand 'welcome' is not a container command"], error = True) + + # Also make sure you can't alias on top of container commands: + self.expect("command alias test-multi process launch", "Tried to alias on top of a container command", + substrs=["'test-multi' is a user container command and cannot be overwritten."], error=True) + self.check_command_tree_exists() + + # Also assert that we can't delete builtin commands: + self.expect("command script delete process launch", "Delete builtin command fails", substrs=["command 'process' is not a user command"], error=True) + # Now let's do the version that works + self.expect("command script delete test-multi test-multi-sub welcome", "Delete script command by path", substrs=["Deleted command: test-multi test-multi-sub welcome"]) + + # Now overwrite the sub-command, it should end up empty: + self.runCmd("command container add -h 'A different help string' -o test-multi test-multi-sub") + # welcome should be gone: + self.expect("test-multi test-multi-sub welcome friend", "did remove subcommand", + substrs=["'test-multi-sub' does not have any subcommands."], error=True) + # We should have the new help: + self.expect("help test-multi test-multi-sub", "help changed", + substrs=["A different help string"]) + + # Now try deleting commands. + self.runCmd("command container delete test-multi test-multi-sub") + self.expect("test-multi test-multi-sub", "Command is not active", error=True, + substrs = ["'test-multi' does not have any subcommands"]) + self.expect("help test-multi", matching=False, substrs=["test-multi-sub"]) + + + # Next the root command: + self.runCmd("command container delete test-multi") + self.expect("test-multi", "Root command gone", substrs=["'test-multi' is not a valid command."], error=True) diff --git a/lldb/test/API/commands/command/container/welcome.py b/lldb/test/API/commands/command/container/welcome.py new file mode 100644 index 0000000000000000000000000000000000000000..6283e695640069e13ce7437732500fc6613d94c6 --- /dev/null +++ b/lldb/test/API/commands/command/container/welcome.py @@ -0,0 +1,28 @@ +from __future__ import print_function +import lldb +import sys + + +class WelcomeCommand(object): + + def __init__(self, debugger, session_dict): + pass + + def get_short_help(self): + return "Just a docstring for Welcome\nA command that says hello to LLDB users" + + def __call__(self, debugger, args, exe_ctx, result): + print('Hello ' + args + ', welcome to LLDB', file=result) + return None + +class WelcomeCommand2(object): + + def __init__(self, debugger, session_dict): + pass + + def get_short_help(self): + return "Just a docstring for the second Welcome\nA command that says hello to LLDB users" + + def __call__(self, debugger, args, exe_ctx, result): + print('Hello ' + args + ', welcome again to LLDB', file=result) + return None diff --git a/lldb/test/API/commands/command/invalid-args/TestInvalidArgsCommand.py b/lldb/test/API/commands/command/invalid-args/TestInvalidArgsCommand.py index 47d77b0e5696260bf61bee32d8e4ed9267951061..3a9a4a39d89d8508eb725dfe94662070299f5b9c 100644 --- a/lldb/test/API/commands/command/invalid-args/TestInvalidArgsCommand.py +++ b/lldb/test/API/commands/command/invalid-args/TestInvalidArgsCommand.py @@ -9,10 +9,10 @@ class InvalidArgsCommandTestCase(TestBase): @no_debug_info_test def test_script_add(self): self.expect("command script add 1 2", error=True, - substrs=["'command script add' requires one argument"]) + substrs=["Path component: '1' not found"]) self.expect("command script add", error=True, - substrs=["'command script add' requires one argument"]) + substrs=["'command script add' requires at least one argument"]) @no_debug_info_test def test_script_clear(self): diff --git a/lldb/test/API/commands/command/script/TestCommandScript.py b/lldb/test/API/commands/command/script/TestCommandScript.py index b103298f24e101e59bd2c5b8b9b0b5df30a819cf..975a0a538ed67156af4e620f45ce182aa6e168be 100644 --- a/lldb/test/API/commands/command/script/TestCommandScript.py +++ b/lldb/test/API/commands/command/script/TestCommandScript.py @@ -147,7 +147,7 @@ class CmdPythonTestCase(TestBase): self.expect('my_command Blah', substrs=['Hello Blah, welcome to LLDB']) self.runCmd( - 'command script add my_command --class welcome.TargetnameCommand') + 'command script add my_command -o --class welcome.TargetnameCommand') self.expect('my_command', substrs=['a.out']) self.runCmd("command script clear") diff --git a/lldb/test/API/commands/expression/char/main.cpp b/lldb/test/API/commands/expression/char/main.cpp index c8b0beb1b3553a8c541305a9d4345efea6ceb64c..9ff4436d88a08ae13b354eeab846e3628c06e52c 100644 --- a/lldb/test/API/commands/expression/char/main.cpp +++ b/lldb/test/API/commands/expression/char/main.cpp @@ -1,3 +1,5 @@ +#include + int foo(char c) { return 1; } int foo(signed char c) { return 2; } int foo(unsigned char c) { return 3; } @@ -6,5 +8,6 @@ int main() { char c = 0; signed char sc = 0; unsigned char uc = 0; + printf("%d %d %d\n", foo(c), foo(sc), foo(uc)); return 0; // Break here } diff --git a/lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/Makefile b/lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..0f3fb37bdadf3cf0a787c1fc95e59e59ab68f1cb --- /dev/null +++ b/lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/Makefile @@ -0,0 +1,9 @@ +CXX_SOURCES := main.cpp +USE_LIBDL := 1 + +lib_b: + $(MAKE) -f $(MAKEFILE_RULES) \ + DYLIB_ONLY=YES DYLIB_CXX_SOURCES=b.cpp DYLIB_NAME=lib_b +all: lib_b + +include Makefile.rules diff --git a/lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/TestBreakInLoadedDylib.py b/lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/TestBreakInLoadedDylib.py new file mode 100644 index 0000000000000000000000000000000000000000..e203511cd49c74eb5c14694ea4d1f06ffab03ec5 --- /dev/null +++ b/lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/TestBreakInLoadedDylib.py @@ -0,0 +1,61 @@ +import lldb +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +from lldbsuite.test import lldbutil + +class TestBreakInLoadedDylib(TestBase): + """ Test that we can set a source regex breakpoint that will take in + a dlopened library that hasn't loaded when we set the breakpoint.""" + + mydir = TestBase.compute_mydir(__file__) + NO_DEBUG_INFO_TESTCASE = True + + @skipIfRemote + def common_setup(self): + self.build() + ctx = self.platformContext + self.main_spec = lldb.SBFileSpec("main.cpp") + self.b_spec = lldb.SBFileSpec("b.cpp") + self.lib_shortname = 'lib_b' + self.lib_fullname = ctx.shlib_prefix + self.lib_shortname + '.' + ctx.shlib_extension + self.lib_spec = lldb.SBFileSpec(self.lib_fullname) + + def test_break_in_dlopen_dylib_using_lldbutils(self): + self.common_setup() + lldbutil.run_to_source_breakpoint(self, "Break here in dylib", self.b_spec, + bkpt_module=self.lib_fullname, + extra_images = [self.lib_shortname], + has_locations_before_run = False) + + @skipIfRemote + def test_break_in_dlopen_dylib_using_target(self): + self.common_setup() + + target, process, _, _ = lldbutil.run_to_source_breakpoint(self, "Break here before we dlopen", self.main_spec, + extra_images = [self.lib_shortname]) + + # Now set some breakpoints that won't take till the library is loaded: + # This one is currently how lldbutils does it but test here in case that changes: + bkpt1 = target.BreakpointCreateBySourceRegex("Break here in dylib", self.b_spec, self.lib_fullname) + + # Try the file list API as well. Put in some bogus entries too, to make sure those + # don't trip us up: + + files_list = lldb.SBFileSpecList() + files_list.Append(self.b_spec) + files_list.Append(self.main_spec) + files_list.Append(lldb.SBFileSpec("I_bet_nobody_has_this_file.cpp")) + + modules_list = lldb.SBFileSpecList() + modules_list.Append(self.lib_spec) + modules_list.Append(lldb.SBFileSpec("libI_bet_not_this_one_either.dylib")) + + bkpt2 = target.BreakpointCreateBySourceRegex("Break here in dylib", modules_list, files_list) + + lldbutil.continue_to_breakpoint(process, bkpt1) + self.assertEqual(bkpt1.GetHitCount(), 1, "Hit breakpoint 1") + self.assertEqual(bkpt2.GetHitCount(), 1, "Hit breakpoint 2") + + + + diff --git a/lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/b.cpp b/lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/b.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5bfb3104910ba088346c8af0d670b412ad1c9113 --- /dev/null +++ b/lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/b.cpp @@ -0,0 +1,3 @@ +extern "C" int LLDB_DYLIB_EXPORT b_function() { + return 500; // Break here in dylib +} diff --git a/lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/main.cpp b/lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/main.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3b00c6eb250f4be19315370a2327592b83842f54 --- /dev/null +++ b/lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/main.cpp @@ -0,0 +1,15 @@ +#include "dylib.h" +#include +#include +#include +#include + +int main(int argc, char* argv[]) { + // Break here before we dlopen the 'liblib_b.so' shared library. + void* dylib_handle = dylib_open("lib_b"); + assert(dylib_handle && "dlopen failed"); + void (*func_handle)() = (void (*)()) dylib_get_symbol(dylib_handle, "b_function"); + assert(func_handle && "dlsym failed"); + func_handle(); + return 0; +} diff --git a/lldb/test/API/functionalities/breakpoint/breakpoint_command/TestBreakpointCommandsFromPython.py b/lldb/test/API/functionalities/breakpoint/breakpoint_command/TestBreakpointCommandsFromPython.py index b5ff89a6fd06054de22adeec01d8b4a939011c20..35e19c888355fb147ff6e5f9136a88b3e817bf25 100644 --- a/lldb/test/API/functionalities/breakpoint/breakpoint_command/TestBreakpointCommandsFromPython.py +++ b/lldb/test/API/functionalities/breakpoint/breakpoint_command/TestBreakpointCommandsFromPython.py @@ -54,6 +54,17 @@ class PythonBreakpointCommandSettingTestCase(TestBase): "Set break point at this line.", self.main_source_spec) self.assertTrue(fancier_bkpt, VALID_BREAKPOINT) + # Also test the list version of this: + file_list = lldb.SBFileSpecList() + file_list.Append(self.main_source_spec) + module_list = lldb.SBFileSpecList() + module_list.Append(self.target.GetExecutable()) + + list_bkpt = self.target.BreakpointCreateBySourceRegex( + "Set break point at this line.", module_list, file_list) + self.assertTrue(list_bkpt, VALID_BREAKPOINT) + + not_so_fancy_bkpt = self.target.BreakpointCreateBySourceRegex( "Set break point at this line.", self.main_source_spec) self.assertTrue(not_so_fancy_bkpt, VALID_BREAKPOINT) @@ -114,13 +125,21 @@ class PythonBreakpointCommandSettingTestCase(TestBase): error = not_so_fancy_bkpt.SetScriptCallbackFunction("bktptcmd.empty_extra_args", empty_args) self.assertTrue(error.Success(), "Failed to add callback %s"%(error.GetCString())) + # Do list breakpoint like fancy: + stream.Clear() + stream.Print('{"side_effect" : "I come from list input"}') + extra_args.SetFromJSON(stream) + error = list_bkpt.SetScriptCallbackFunction("bktptcmd.a_list_function", extra_args) + self.assertTrue(error.Success(), "Failed to add callback %s"%(error.GetCString())) + # Clear out canary variables side_effect.bktptcmd = None side_effect.callback = None side_effect.fancy = None side_effect.fancier = None side_effect.not_so_fancy = None - + side_effect.a_list_function = None + # Now launch the process, and do not stop at entry point. self.process = self.target.LaunchSimple( None, None, self.get_process_working_directory()) @@ -133,11 +152,13 @@ class PythonBreakpointCommandSettingTestCase(TestBase): self.assertEquals(len(threads), 1, "Stopped at inner breakpoint.") self.thread = threads[0] + print("* Num Locations: {0} ; Hit Count {1}".format(list_bkpt.GetNumLocations(), list_bkpt.GetHitCount())) self.assertEquals("callback was here", side_effect.callback) self.assertEquals("function was here", side_effect.bktptcmd) self.assertEquals("I am fancy", side_effect.fancy) self.assertEquals("I am fancier", side_effect.fancier) self.assertEquals("Not so fancy", side_effect.not_so_fancy) + self.assertEquals("I come from list input", side_effect.from_list) def do_bad_args_to_python_command(self): error = lldb.SBError() diff --git a/lldb/test/API/functionalities/breakpoint/breakpoint_command/bktptcmd.py b/lldb/test/API/functionalities/breakpoint/breakpoint_command/bktptcmd.py index e839de57fb7a5e16bc08d60dd49ed92e3c3c092e..d635ae45c7c8051e58936ce0548c8bfdfbbd9f90 100644 --- a/lldb/test/API/functionalities/breakpoint/breakpoint_command/bktptcmd.py +++ b/lldb/test/API/functionalities/breakpoint/breakpoint_command/bktptcmd.py @@ -17,6 +17,12 @@ def a_third_function(frame, bp_loc, extra_args, dict): se_string = se_value.GetStringValue(100) side_effect.fancier = se_string +def a_list_function(frame, bp_loc, extra_args, dict): + se_value = extra_args.GetValueForKey("side_effect") + se_string = se_value.GetStringValue(100) + side_effect.from_list = se_string + + def empty_extra_args(frame, bp_loc, extra_args, dict): if extra_args.IsValid(): side_effect.not_so_fancy = "Extra args should not be valid" diff --git a/lldb/test/API/functionalities/completion/TestCompletion.py b/lldb/test/API/functionalities/completion/TestCompletion.py index 1688612c578542b4c4c0c548c1b0e66d3647e911..ed901890f7dfe2fc41868db7769a036cc2b49e29 100644 --- a/lldb/test/API/functionalities/completion/TestCompletion.py +++ b/lldb/test/API/functionalities/completion/TestCompletion.py @@ -510,7 +510,7 @@ class CommandLineCompletionTestCase(TestBase): def test_command_script_delete(self): self.runCmd("command script add -h test_desc -f none -s current usercmd1") - self.check_completion_with_desc('command script delete ', [['usercmd1', 'test_desc']]) + self.check_completion_with_desc('command script delete ', [['usercmd1', '']]) def test_command_delete(self): self.runCmd(r"command regex test_command s/^$/finish/ 's/([0-9]+)/frame select %1/'") diff --git a/lldb/unittests/Interpreter/CMakeLists.txt b/lldb/unittests/Interpreter/CMakeLists.txt index 6ea5996e2b0368be25e685503aee427eff13add4..2080ce9085400419a2ffd3ef65c1f95e6e10c450 100644 --- a/lldb/unittests/Interpreter/CMakeLists.txt +++ b/lldb/unittests/Interpreter/CMakeLists.txt @@ -1,10 +1,17 @@ add_lldb_unittest(InterpreterTests + TestCommandPaths.cpp TestCompletion.cpp TestOptionArgParser.cpp TestOptionValue.cpp TestOptionValueFileColonLine.cpp LINK_LIBS - lldbInterpreter - lldbUtilityHelpers - ) + lldbCore + lldbHost + lldbTarget + lldbSymbol + lldbUtility + lldbUtilityHelpers + lldbInterpreter + lldbPluginPlatformMacOSX +) diff --git a/lldb/unittests/Interpreter/TestCommandPaths.cpp b/lldb/unittests/Interpreter/TestCommandPaths.cpp new file mode 100644 index 0000000000000000000000000000000000000000..13bb4e54b5ba32e1d0f58177be11572258583988 --- /dev/null +++ b/lldb/unittests/Interpreter/TestCommandPaths.cpp @@ -0,0 +1,164 @@ +//===-- ProcessEventDataTest.cpp ------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "Plugins/Platform/MacOSX/PlatformMacOSX.h" +#include "Plugins/Platform/MacOSX/PlatformRemoteMacOSX.h" +#include "lldb/Core/Debugger.h" +#include "lldb/Host/FileSystem.h" +#include "lldb/Host/HostInfo.h" +#include "lldb/Interpreter/CommandInterpreter.h" +#include "lldb/Interpreter/CommandObject.h" +#include "lldb/Interpreter/CommandObjectMultiword.h" +#include "lldb/Interpreter/CommandReturnObject.h" +#include "lldb/Utility/Args.h" +#include "lldb/Utility/Reproducer.h" +#include "lldb/Utility/Status.h" + +#include "gtest/gtest.h" + +using namespace lldb_private; +using namespace lldb_private::repro; +using namespace lldb; + +namespace { +class VerifyUserMultiwordCmdPathTest : public ::testing::Test { + void SetUp() override { + llvm::cantFail(Reproducer::Initialize(ReproducerMode::Off, llvm::None)); + FileSystem::Initialize(); + HostInfo::Initialize(); + PlatformMacOSX::Initialize(); + } + void TearDown() override { + PlatformMacOSX::Terminate(); + HostInfo::Terminate(); + FileSystem::Terminate(); + Reproducer::Terminate(); + } +}; +} // namespace + +class CommandObjectLeaf : public CommandObjectParsed { +public: + CommandObjectLeaf(CommandInterpreter &interpreter) + : CommandObjectParsed(interpreter, "dummy subcommand leaf", + "Does nothing", "dummy subcommand leaf") { + SetIsUserCommand(true); + } + +protected: + virtual bool DoExecute(Args &command, CommandReturnObject &result) { + result.SetStatus(eReturnStatusSuccessFinishResult); + result.AppendMessage("I did nothing"); + return true; + } +}; + +class CommandObjectMultiwordSubDummy : public CommandObjectMultiword { +public: + CommandObjectMultiwordSubDummy(CommandInterpreter &interpreter) + : CommandObjectMultiword(interpreter, "dummy subcommand", "Does nothing", + "dummy subcommand") { + SetIsUserCommand(true); + LoadSubCommand("leaf", CommandObjectSP(new CommandObjectLeaf(interpreter))); + } + + ~CommandObjectMultiwordSubDummy() override = default; +}; + +class CommandObjectMultiwordDummy : public CommandObjectMultiword { +public: + CommandObjectMultiwordDummy(CommandInterpreter &interpreter) + : CommandObjectMultiword(interpreter, "dummy", "Does nothing", "dummy") { + SetIsUserCommand(true); + LoadSubCommand( + "subcommand", + CommandObjectSP(new CommandObjectMultiwordSubDummy(interpreter))); + } + + ~CommandObjectMultiwordDummy() override = default; +}; + +// Pass in the command path to args. If success is true, we make sure the MWC +// returned matches the test string. If success is false, we make sure the +// lookup error matches test_str. +void RunTest(CommandInterpreter &interp, const char *args, bool is_leaf, + bool success, const char *test_str) { + CommandObjectMultiword *multi_word_cmd = nullptr; + Args test_args(args); + Status error; + multi_word_cmd = + interp.VerifyUserMultiwordCmdPath(test_args, is_leaf, error); + if (success) { + ASSERT_NE(multi_word_cmd, nullptr); + ASSERT_TRUE(error.Success()); + ASSERT_STREQ(multi_word_cmd->GetCommandName().str().c_str(), test_str); + } else { + ASSERT_EQ(multi_word_cmd, nullptr); + ASSERT_TRUE(error.Fail()); + ASSERT_STREQ(error.AsCString(), test_str); + } +} + +TEST_F(VerifyUserMultiwordCmdPathTest, TestErrors) { + ArchSpec arch("x86_64-apple-macosx-"); + + Platform::SetHostPlatform(PlatformRemoteMacOSX::CreateInstance(true, &arch)); + + DebuggerSP debugger_sp = Debugger::CreateInstance(); + ASSERT_TRUE(debugger_sp); + + CommandInterpreter &interp = debugger_sp->GetCommandInterpreter(); + + Status error; + bool success; + bool is_leaf; + + // Test that we reject non-user path components: + success = false; + is_leaf = true; + RunTest(interp, "process launch", is_leaf, success, + "Path component: 'process' is not a user command"); + + // Test that we reject non-existent commands: + is_leaf = true; + success = false; + RunTest(interp, "wewouldnevernameacommandthis subcommand", is_leaf, success, + "Path component: 'wewouldnevernameacommandthis' not found"); + + // Now we have to add a multiword command, and then probe it. + error = interp.AddUserCommand( + "dummy", CommandObjectSP(new CommandObjectMultiwordDummy(interp)), true); + ASSERT_TRUE(error.Success()); + + // Now pass the correct path, and make sure we get back the right MWC. + is_leaf = false; + success = true; + RunTest(interp, "dummy subcommand", is_leaf, success, "dummy subcommand"); + + is_leaf = true; + RunTest(interp, "dummy subcommand", is_leaf, success, "dummy"); + + // If you tell us the last node is a leaf, we don't check that. Make sure + // that is true: + is_leaf = true; + success = true; + RunTest(interp, "dummy subcommand leaf", is_leaf, success, + "dummy subcommand"); + // But we should fail if we say the last component is a multiword: + + is_leaf = false; + success = false; + RunTest(interp, "dummy subcommand leaf", is_leaf, success, + "Path component: 'leaf' is not a container command"); + + // We should fail if we get the second path component wrong: + is_leaf = false; + success = false; + RunTest(interp, "dummy not-subcommand", is_leaf, success, + "Path component: 'not-subcommand' not found"); +} diff --git a/llvm/examples/IRTransforms/SimplifyCFG.cpp b/llvm/examples/IRTransforms/SimplifyCFG.cpp index 82368d74942126a0d42105db32c49caa8d6abdc9..111d4538fae0fed8de37a04cbbb7a74c91ba87a9 100644 --- a/llvm/examples/IRTransforms/SimplifyCFG.cpp +++ b/llvm/examples/IRTransforms/SimplifyCFG.cpp @@ -354,17 +354,17 @@ static bool mergeIntoSinglePredecessor_v2(Function &F, DominatorTree &DT) { } static bool doSimplify_v1(Function &F) { - return eliminateCondBranches_v1(F) | mergeIntoSinglePredecessor_v1(F) | + return (int)eliminateCondBranches_v1(F) | mergeIntoSinglePredecessor_v1(F) | removeDeadBlocks_v1(F); } static bool doSimplify_v2(Function &F, DominatorTree &DT) { - return eliminateCondBranches_v2(F, DT) | + return (int)eliminateCondBranches_v2(F, DT) | mergeIntoSinglePredecessor_v2(F, DT) | removeDeadBlocks_v2(F, DT); } static bool doSimplify_v3(Function &F, DominatorTree &DT) { - return eliminateCondBranches_v3(F, DT) | + return (int)eliminateCondBranches_v3(F, DT) | mergeIntoSinglePredecessor_v2(F, DT) | removeDeadBlocks_v2(F, DT); } diff --git a/llvm/include/llvm/Analysis/InlineAdvisor.h b/llvm/include/llvm/Analysis/InlineAdvisor.h index fa4006bd760444fd04700404eea14b405c486bb4..595e8f777b46b0387d6d2e15e7a7c2a9c897f2ac 100644 --- a/llvm/include/llvm/Analysis/InlineAdvisor.h +++ b/llvm/include/llvm/Analysis/InlineAdvisor.h @@ -38,6 +38,9 @@ class OptimizationRemarkEmitter; /// training. enum class InliningAdvisorMode : int { Default, Release, Development }; +/// For Replay Inliner initialization +enum class ReplayInlineScope : int { Function, Module }; + class InlineAdvisor; /// Capture state between an inlining decision having had been made, and /// its impact being observable. When collecting model training data, this @@ -143,7 +146,11 @@ public: /// be up-to-date wrt previous inlining decisions. \p MandatoryOnly indicates /// only mandatory (always-inline) call sites should be recommended - this /// allows the InlineAdvisor track such inlininings. - /// Returns an InlineAdvice with the inlining recommendation. + /// Returns: + /// - An InlineAdvice with the inlining recommendation. + /// - Null when no recommendation is made (https://reviews.llvm.org/D110658). + /// TODO: Consider removing the Null return scenario by incorporating the + /// SampleProfile inliner into an InlineAdvisor std::unique_ptr getAdvice(CallBase &CB, bool MandatoryOnly = false); @@ -227,7 +234,7 @@ public: return !PAC.preservedWhenStateless(); } bool tryCreate(InlineParams Params, InliningAdvisorMode Mode, - StringRef ReplayFile); + StringRef ReplayFile, ReplayInlineScope ReplayScope); InlineAdvisor *getAdvisor() const { return Advisor.get(); } private: @@ -250,6 +257,11 @@ getDevelopmentModeAdvisor(Module &M, ModuleAnalysisManager &MAM, std::function GetDefaultAdvice); #endif +std::unique_ptr getReplayInlineAdvisor( + Module &M, FunctionAnalysisManager &FAM, LLVMContext &Context, + std::unique_ptr OriginalAdvisor, StringRef RemarksFile, + ReplayInlineScope Scope, bool EmitRemarks); + // Default (manual policy) decision making helper APIs. Shared with the legacy // pass manager inliner. diff --git a/llvm/include/llvm/Analysis/InlineOrder.h b/llvm/include/llvm/Analysis/InlineOrder.h index a2de8469cb0a6185c3276cd57d79c6acff12357f..def3192356f48867435ce3a609332717e5afdaef 100644 --- a/llvm/include/llvm/Analysis/InlineOrder.h +++ b/llvm/include/llvm/Analysis/InlineOrder.h @@ -160,8 +160,7 @@ public: auto PredWrapper = [=](HeapT P) -> bool { return Pred(std::make_pair(P.first, 0)); }; - Heap.erase(std::remove_if(Heap.begin(), Heap.end(), PredWrapper), - Heap.end()); + llvm::erase_if(Heap, PredWrapper); std::make_heap(Heap.begin(), Heap.end(), cmp); } diff --git a/llvm/include/llvm/Analysis/ReplayInlineAdvisor.h b/llvm/include/llvm/Analysis/ReplayInlineAdvisor.h index 3018bcc241d852c50cb495a5f12dffe449c5cf69..7ae40c10ef93c27b579ab85a6bb3195cdcad704f 100644 --- a/llvm/include/llvm/Analysis/ReplayInlineAdvisor.h +++ b/llvm/include/llvm/Analysis/ReplayInlineAdvisor.h @@ -27,15 +27,19 @@ public: ReplayInlineAdvisor(Module &M, FunctionAnalysisManager &FAM, LLVMContext &Context, std::unique_ptr OriginalAdvisor, - StringRef RemarksFile, bool EmitRemarks); + StringRef RemarksFile, ReplayInlineScope Scope, + bool EmitRemarks); std::unique_ptr getAdviceImpl(CallBase &CB) override; bool areReplayRemarksLoaded() const { return HasReplayRemarks; } private: - StringSet<> InlineSitesFromRemarks; std::unique_ptr OriginalAdvisor; bool HasReplayRemarks = false; + ReplayInlineScope Scope; bool EmitRemarks = false; + + StringMap InlineSitesFromRemarks; + StringSet<> CallersToReplay; }; } // namespace llvm #endif // LLVM_ANALYSIS_REPLAYINLINEADVISOR_H diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h index f9b9ded11ba847f0526c15c5cb678cf17bee9e0a..cc07b8e7042d5e113acbf88b53d0368ca9560816 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h @@ -583,6 +583,9 @@ public: /// Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width bool matchBitfieldExtractFromShr(MachineInstr &MI, BuildFnTy &MatchInfo); + /// Match: shr (and x, n), k -> ubfx x, pos, width + bool matchBitfieldExtractFromShrAnd(MachineInstr &MI, BuildFnTy &MatchInfo); + // Helpers for reassociation: bool matchReassocConstantInnerRHS(GPtrAdd &MI, MachineInstr *RHS, BuildFnTy &MatchInfo); diff --git a/llvm/lib/ExecutionEngine/JITLink/TableManager.h b/llvm/include/llvm/ExecutionEngine/JITLink/TableManager.h similarity index 79% rename from llvm/lib/ExecutionEngine/JITLink/TableManager.h rename to llvm/include/llvm/ExecutionEngine/JITLink/TableManager.h index e03948b49b2196fe91c9537d1d8eaebfbd8143f6..2b502397a8dd926bf2741cab198a26cd369ec2d1 100644 --- a/llvm/lib/ExecutionEngine/JITLink/TableManager.h +++ b/llvm/include/llvm/ExecutionEngine/JITLink/TableManager.h @@ -16,24 +16,16 @@ #include "llvm/ExecutionEngine/JITLink/JITLink.h" #include "llvm/Support/Debug.h" -#define DEBUG_TYPE "jitlink" - namespace llvm { namespace jitlink { -/// Table like section manager +/// A CRTP base for tables that are built on demand, e.g. Global Offset Tables +/// and Procedure Linkage Tables. +/// The getEntyrForTarget function returns the table entry corresponding to the +/// given target, calling down to the implementation class to build an entry if +/// one does not already exist. template class TableManager { public: - /// Visit edge, return true if the edge was dealt with, otherwise return - /// false(let other managers to visit). - bool visitEdge(LinkGraph &G, Block *B, Edge &E) { - if (impl().fixEdgeKind(G, B, E)) { - fixTarget(G, E); - return true; - } - return false; - } - /// Return the constructed entry /// /// Use parameter G to construct the entry for target symbol @@ -45,7 +37,7 @@ public: // Build the entry if it doesn't exist. if (EntryI == Entries.end()) { auto &Entry = impl().createEntry(G, Target); - LLVM_DEBUG({ + DEBUG_WITH_TYPE("jitlink", { dbgs() << " Created" << impl().getTableName() << "entry for " << Target.getName() << ": " << Entry << "\n"; }); @@ -53,7 +45,7 @@ public: } assert(EntryI != Entries.end() && "Could not get entry symbol"); - LLVM_DEBUG({ + DEBUG_WITH_TYPE("jitlink", { dbgs() << " Using " << impl().getTableName() << " entry " << *EntryI->second << "\n"; }); @@ -61,10 +53,6 @@ public: } private: - void fixTarget(LinkGraph &G, Edge &E) { - E.setTarget(getEntryForTarget(G, E.getTarget())); - } - TableManagerImplT &impl() { return static_cast(*this); } DenseMap Entries; }; diff --git a/llvm/include/llvm/IR/ProfileSummary.h b/llvm/include/llvm/IR/ProfileSummary.h index 889568e7946bb0637f75645c044840b8e76ddd40..d00bfae897117d76be4b6083d55d623428e91219 100644 --- a/llvm/include/llvm/IR/ProfileSummary.h +++ b/llvm/include/llvm/IR/ProfileSummary.h @@ -31,9 +31,9 @@ class raw_ostream; // number of counts needed to reach this target and the minimum among these // counts. struct ProfileSummaryEntry { - uint32_t Cutoff; ///< The required percentile of counts. - uint64_t MinCount; ///< The minimum count for this percentile. - uint64_t NumCounts; ///< Number of counts >= the minimum count. + const uint32_t Cutoff; ///< The required percentile of counts. + const uint64_t MinCount; ///< The minimum count for this percentile. + const uint64_t NumCounts; ///< Number of counts >= the minimum count. ProfileSummaryEntry(uint32_t TheCutoff, uint64_t TheMinCount, uint64_t TheNumCounts) @@ -61,7 +61,7 @@ private: /// of the program being built to the number of profile counters in the /// partial sample profile. When 'Partial' is false, it is undefined. This is /// currently only available under thin LTO mode. - double PartialProfileRatio = 0; + double PartialProfileRatio = 0.0; /// Return detailed summary as metadata. Metadata *getDetailedSummaryMD(LLVMContext &Context); @@ -86,21 +86,21 @@ public: /// Construct profile summary from metdata. static ProfileSummary *getFromMD(Metadata *MD); SummaryEntryVector &getDetailedSummary() { return DetailedSummary; } - uint32_t getNumFunctions() { return NumFunctions; } - uint64_t getMaxFunctionCount() { return MaxFunctionCount; } - uint32_t getNumCounts() { return NumCounts; } - uint64_t getTotalCount() { return TotalCount; } - uint64_t getMaxCount() { return MaxCount; } - uint64_t getMaxInternalCount() { return MaxInternalCount; } + uint32_t getNumFunctions() const { return NumFunctions; } + uint64_t getMaxFunctionCount() const { return MaxFunctionCount; } + uint32_t getNumCounts() const { return NumCounts; } + uint64_t getTotalCount() const { return TotalCount; } + uint64_t getMaxCount() const { return MaxCount; } + uint64_t getMaxInternalCount() const { return MaxInternalCount; } void setPartialProfile(bool PP) { Partial = PP; } - bool isPartialProfile() { return Partial; } - double getPartialProfileRatio() { return PartialProfileRatio; } + bool isPartialProfile() const { return Partial; } + double getPartialProfileRatio() const { return PartialProfileRatio; } void setPartialProfileRatio(double R) { assert(isPartialProfile() && "Unexpected when not partial profile"); PartialProfileRatio = R; } - void printSummary(raw_ostream &OS); - void printDetailedSummary(raw_ostream &OS); + void printSummary(raw_ostream &OS) const; + void printDetailedSummary(raw_ostream &OS) const; }; } // end namespace llvm diff --git a/llvm/include/llvm/LTO/Caching.h b/llvm/include/llvm/LTO/Caching.h deleted file mode 100644 index 43b978328b747c93652eb166df9851794829af41..0000000000000000000000000000000000000000 --- a/llvm/include/llvm/LTO/Caching.h +++ /dev/null @@ -1,38 +0,0 @@ -//===- Caching.h - LLVM Link Time Optimizer Configuration -----------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file defines the localCache function, which allows clients to add a -// filesystem cache to ThinLTO. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LTO_CACHING_H -#define LLVM_LTO_CACHING_H - -#include "llvm/LTO/LTO.h" - -namespace llvm { -namespace lto { - -/// This type defines the callback to add a pre-existing native object file -/// (e.g. in a cache). -/// -/// Buffer callbacks must be thread safe. -using AddBufferFn = - std::function MB)>; - -/// Create a local file system cache which uses the given cache directory and -/// file callback. This function also creates the cache directory if it does not -/// already exist. -Expected localCache(StringRef CacheDirectoryPath, - AddBufferFn AddBuffer); - -} // namespace lto -} // namespace llvm - -#endif diff --git a/llvm/include/llvm/LTO/LTO.h b/llvm/include/llvm/LTO/LTO.h index 0d08856abaceef6b3f317497d81c8aacbcfd55f6..d87cb76c422aaab9e2feda96ce50302dea7f5ee4 100644 --- a/llvm/include/llvm/LTO/LTO.h +++ b/llvm/include/llvm/LTO/LTO.h @@ -21,6 +21,7 @@ #include "llvm/IR/ModuleSummaryIndex.h" #include "llvm/LTO/Config.h" #include "llvm/Object/IRSymtab.h" +#include "llvm/Support/Caching.h" #include "llvm/Support/Error.h" #include "llvm/Support/thread.h" #include "llvm/Transforms/IPO/FunctionAttrs.h" @@ -187,40 +188,6 @@ private: } }; -/// This class wraps an output stream for a native object. Most clients should -/// just be able to return an instance of this base class from the stream -/// callback, but if a client needs to perform some action after the stream is -/// written to, that can be done by deriving from this class and overriding the -/// destructor. -class NativeObjectStream { -public: - NativeObjectStream(std::unique_ptr OS) : OS(std::move(OS)) {} - std::unique_ptr OS; - virtual ~NativeObjectStream() = default; -}; - -/// This type defines the callback to add a native object that is generated on -/// the fly. -/// -/// Stream callbacks must be thread safe. -using AddStreamFn = - std::function(unsigned Task)>; - -/// This is the type of a native object cache. To request an item from the -/// cache, pass a unique string as the Key. For hits, the cached file will be -/// added to the link and this function will return AddStreamFn(). For misses, -/// the cache will return a stream callback which must be called at most once to -/// produce content for the stream. The native object stream produced by the -/// stream callback will add the file to the link after the stream is written -/// to. -/// -/// Clients generally look like this: -/// -/// if (AddStreamFn AddStream = Cache(Task, Key)) -/// ProduceContent(AddStream); -using NativeObjectCache = - std::function; - /// A ThinBackend defines what happens after the thin-link phase during ThinLTO. /// The details of this type definition aren't important; clients can only /// create a ThinBackend using one of the create*ThinBackend() functions below. diff --git a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h index 31688e43e1747023434317f9c1fd2ce17dcf6827..333f483f29c54c6bd8de67e3f06d3ce50f911382 100644 --- a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h +++ b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h @@ -176,7 +176,7 @@ struct LTOCodeGenerator { /// created using the \p AddStream callback. Returns true on success. /// /// Calls \a verifyMergedModuleOnce(). - bool compileOptimized(lto::AddStreamFn AddStream, unsigned ParallelismLevel); + bool compileOptimized(AddStreamFn AddStream, unsigned ParallelismLevel); /// Enable the Freestanding mode: indicate that the optimizer should not /// assume builtins are present on the target. diff --git a/llvm/include/llvm/Support/Caching.h b/llvm/include/llvm/Support/Caching.h new file mode 100644 index 0000000000000000000000000000000000000000..819165212b0c73d6809d44ba34b590841675caca --- /dev/null +++ b/llvm/include/llvm/Support/Caching.h @@ -0,0 +1,76 @@ +//===- Caching.h - LLVM File Cache Handling Configuration -------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the localCache function, which allows clients to add a +// filesystem cache. This is used by ThinLTO. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_SUPPORT_CACHING_H +#define LLVM_SUPPORT_CACHING_H + +#include "llvm/Support/Error.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/thread.h" + +namespace llvm { + +/// This class wraps an output stream for a native object. Most clients should +/// just be able to return an instance of this base class from the stream +/// callback, but if a client needs to perform some action after the stream is +/// written to, that can be done by deriving from this class and overriding the +/// destructor. +class NativeObjectStream { +public: + NativeObjectStream(std::unique_ptr OS) + : OS(std::move(OS)) {} + std::unique_ptr OS; + virtual ~NativeObjectStream() = default; +}; + +/// This type defines the callback to add a native object that is generated on +/// the fly. +/// +/// Stream callbacks must be thread safe. +using AddStreamFn = + std::function(unsigned Task)>; + +/// This is the type of a native object cache. To request an item from the +/// cache, pass a unique string as the Key. For hits, the cached file will be +/// added to the link and this function will return AddStreamFn(). For misses, +/// the cache will return a stream callback which must be called at most once to +/// produce content for the stream. The native object stream produced by the +/// stream callback will add the file to the link after the stream is written +/// to. +/// +/// Clients generally look like this: +/// +/// if (AddStreamFn AddStream = Cache(Task, Key)) +/// ProduceContent(AddStream); +using NativeObjectCache = + std::function; + +/// This type defines the callback to add a pre-existing native object file +/// (e.g. in a cache). +/// +/// Buffer callbacks must be thread safe. +using AddBufferFn = + std::function MB)>; + +/// Create a local file system cache which uses the given cache name, temporary +/// file prefix, cache directory and file callback. This function also creates +/// the cache directory if it does not already exist. The cache name appears in +/// error messages for errors during caching. The temporary file prefix is used +/// in the temporary file naming scheme used when writing files atomically. +Expected localCache(Twine CacheNameRef, + Twine TempFilePrefixRef, + Twine CacheDirectoryPathRef, + AddBufferFn AddBuffer); +} // namespace llvm + +#endif diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h b/llvm/include/llvm/Support/RISCVISAInfo.h index fe8599e1e04bee8aba50d5b24ad0692dfd830b82..7110de601123ff674a6f640a29181d81c6c6cd66 100644 --- a/llvm/include/llvm/Support/RISCVISAInfo.h +++ b/llvm/include/llvm/Support/RISCVISAInfo.h @@ -19,9 +19,6 @@ #include namespace llvm { -namespace opt { -class ArgList; -} struct RISCVExtensionInfo { std::string ExtName; unsigned MajorVersion; @@ -57,8 +54,8 @@ public: parseFeatures(unsigned XLen, const std::vector &Features); /// Convert RISCV ISA info to a feature vector. - void toFeatures(const llvm::opt::ArgList &Args, - std::vector &Features) const; + void toFeatures(std::vector &Features, + std::function StrAlloc) const; const OrderedExtensionMap &getExtensions() const { return Exts; }; diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td index 9087c136bb02f64fe59baab92304b83bc2401d41..87e827dca304776747ba1189994962f10dcb53c9 100644 --- a/llvm/include/llvm/Target/GlobalISel/Combine.td +++ b/llvm/include/llvm/Target/GlobalISel/Combine.td @@ -691,9 +691,16 @@ def bitfield_extract_from_shr : GICombineRule< [{ return Helper.matchBitfieldExtractFromShr(*${root}, ${info}); }]), (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>; +def bitfield_extract_from_shr_and : GICombineRule< + (defs root:$root, build_fn_matchinfo:$info), + (match (wip_match_opcode G_ASHR, G_LSHR):$root, + [{ return Helper.matchBitfieldExtractFromShrAnd(*${root}, ${info}); }]), + (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>; + def form_bitfield_extract : GICombineGroup<[bitfield_extract_from_sext_inreg, bitfield_extract_from_and, - bitfield_extract_from_shr]>; + bitfield_extract_from_shr, + bitfield_extract_from_shr_and]>; def udiv_by_const : GICombineRule< (defs root:$root), diff --git a/llvm/include/llvm/Target/TargetLoweringObjectFile.h b/llvm/include/llvm/Target/TargetLoweringObjectFile.h index 93bfdd20e082e9570a8f60896c77f955d989c5d8..752032d3d04df997711fb9e9f7988939712b19b8 100644 --- a/llvm/include/llvm/Target/TargetLoweringObjectFile.h +++ b/llvm/include/llvm/Target/TargetLoweringObjectFile.h @@ -15,6 +15,7 @@ #define LLVM_TARGET_TARGETLOWERINGOBJECTFILE_H #include "llvm/MC/MCObjectFileInfo.h" +#include "llvm/MC/MCRegister.h" #include namespace llvm { @@ -219,6 +220,14 @@ public: return SupportDebugThreadLocalLocation; } + /// Returns the register used as static base in RWPI variants. + virtual const MCRegister getStaticBase() const { return MCRegister::NoRegister; } + + /// Get the target specific RWPI relocation. + virtual const MCExpr *getIndirectSymViaRWPI(const MCSymbol *Sym) const { + return nullptr; + } + /// Get the target specific PC relative GOT entry relocation virtual const MCExpr *getIndirectSymViaGOTPCRel(const GlobalValue *GV, const MCSymbol *Sym, diff --git a/llvm/include/llvm/Transforms/IPO/Inliner.h b/llvm/include/llvm/Transforms/IPO/Inliner.h index a44af135480d6e351c1bb5aedcc173abbdfe35a9..2d99a25f68fe3a1fff6a77dc7a39d8fbc498e49a 100644 --- a/llvm/include/llvm/Transforms/IPO/Inliner.h +++ b/llvm/include/llvm/Transforms/IPO/Inliner.h @@ -14,7 +14,6 @@ #include "llvm/Analysis/InlineAdvisor.h" #include "llvm/Analysis/InlineCost.h" #include "llvm/Analysis/LazyCallGraph.h" -#include "llvm/Analysis/ReplayInlineAdvisor.h" #include "llvm/Analysis/Utils/ImportedFunctionsInliningStatistics.h" #include "llvm/IR/PassManager.h" #include diff --git a/llvm/include/llvm/Transforms/Utils/LoopUtils.h b/llvm/include/llvm/Transforms/Utils/LoopUtils.h index eaf72a361d26da7ffc0d39e3a089fa8553f0b522..30c3f71e094772e2430028f47cf089c265c0cc1c 100644 --- a/llvm/include/llvm/Transforms/Utils/LoopUtils.h +++ b/llvm/include/llvm/Transforms/Utils/LoopUtils.h @@ -495,12 +495,8 @@ Loop *cloneLoop(Loop *L, Loop *PL, ValueToValueMapTy &VM, LoopInfo *LI, LPPassManager *LPM); /// Add code that checks at runtime if the accessed arrays in \p PointerChecks -/// overlap. -/// -/// Returns a pair of instructions where the first element is the first -/// instruction generated in possibly a sequence of instructions and the -/// second value is the final comparator value or NULL if no check is needed. -std::pair +/// overlap. Returns the final comparator value or NULL if no check is needed. +Value * addRuntimeChecks(Instruction *Loc, Loop *TheLoop, const SmallVectorImpl &PointerChecks, SCEVExpander &Expander); diff --git a/llvm/lib/Analysis/CGSCCPassManager.cpp b/llvm/lib/Analysis/CGSCCPassManager.cpp index 5573ad13d96dd5313febb30b79f3b9fa2e7a0985..c2ba3d662bf37f6d234d5b2b9d93ac816c94380b 100644 --- a/llvm/lib/Analysis/CGSCCPassManager.cpp +++ b/llvm/lib/Analysis/CGSCCPassManager.cpp @@ -38,6 +38,7 @@ using namespace llvm; // Explicit template instantiations and specialization definitions for core // template typedefs. namespace llvm { +extern cl::opt EagerlyInvalidateAnalyses; static cl::opt AbortOnMaxDevirtIterationsReached( "abort-on-max-devirt-iterations-reached", @@ -556,7 +557,8 @@ PreservedAnalyses CGSCCToFunctionPassAdaptor::run(LazyCallGraph::SCC &C, // We know that the function pass couldn't have invalidated any other // function's analyses (that's the contract of a function pass), so // directly handle the function analysis manager's invalidation here. - FAM.invalidate(F, PassPA); + FAM.invalidate(F, EagerlyInvalidateAnalyses ? PreservedAnalyses::none() + : PassPA); // Then intersect the preserved set so that invalidation of module // analyses will eventually occur when the module pass completes. diff --git a/llvm/lib/Analysis/InlineAdvisor.cpp b/llvm/lib/Analysis/InlineAdvisor.cpp index f1695db6117c15f1d77753bbd2fff55ba92f5b46..c08d8d58c903729da28469a1df48d0d4ff0ae815 100644 --- a/llvm/lib/Analysis/InlineAdvisor.cpp +++ b/llvm/lib/Analysis/InlineAdvisor.cpp @@ -16,7 +16,6 @@ #include "llvm/Analysis/InlineCost.h" #include "llvm/Analysis/OptimizationRemarkEmitter.h" #include "llvm/Analysis/ProfileSummaryInfo.h" -#include "llvm/Analysis/ReplayInlineAdvisor.h" #include "llvm/Analysis/TargetLibraryInfo.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/IR/DebugInfoMetadata.h" @@ -189,7 +188,8 @@ AnalysisKey InlineAdvisorAnalysis::Key; bool InlineAdvisorAnalysis::Result::tryCreate(InlineParams Params, InliningAdvisorMode Mode, - StringRef ReplayFile) { + StringRef ReplayFile, + ReplayInlineScope ReplayScope) { auto &FAM = MAM.getResult(M).getManager(); switch (Mode) { case InliningAdvisorMode::Default: @@ -198,8 +198,8 @@ bool InlineAdvisorAnalysis::Result::tryCreate(InlineParams Params, // Restrict replay to default advisor, ML advisors are stateful so // replay will need augmentations to interleave with them correctly. if (!ReplayFile.empty()) { - Advisor = std::make_unique( - M, FAM, M.getContext(), std::move(Advisor), ReplayFile, + Advisor = llvm::getReplayInlineAdvisor( + M, FAM, M.getContext(), std::move(Advisor), ReplayFile, ReplayScope, /* EmitRemarks =*/true); } break; diff --git a/llvm/lib/Analysis/InlineCost.cpp b/llvm/lib/Analysis/InlineCost.cpp index 4b5c1bf46a628ee30f2102f5cdd2690b281f04c7..a77dd32f1816eac5b5b24f15452910e07e4cd896 100644 --- a/llvm/lib/Analysis/InlineCost.cpp +++ b/llvm/lib/Analysis/InlineCost.cpp @@ -1013,7 +1013,7 @@ public: // Prints the same analysis as dump(), but its definition is not dependent // on the build. - void print(); + void print(raw_ostream &OS); Optional getCostDetails(const Instruction *I) { if (InstructionCostDetailMap.find(I) != InstructionCostDetailMap.end()) @@ -2711,10 +2711,10 @@ InlineResult CallAnalyzer::analyze() { return finalizeAnalysis(); } -void InlineCostCallAnalyzer::print() { -#define DEBUG_PRINT_STAT(x) dbgs() << " " #x ": " << x << "\n" +void InlineCostCallAnalyzer::print(raw_ostream &OS) { +#define DEBUG_PRINT_STAT(x) OS << " " #x ": " << x << "\n" if (PrintInstructionComments) - F.print(dbgs(), &Writer); + F.print(OS, &Writer); DEBUG_PRINT_STAT(NumConstantArgs); DEBUG_PRINT_STAT(NumConstantOffsetPtrArgs); DEBUG_PRINT_STAT(NumAllocaArgs); @@ -2733,7 +2733,7 @@ void InlineCostCallAnalyzer::print() { #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) /// Dump stats about this call's analysis. -LLVM_DUMP_METHOD void InlineCostCallAnalyzer::dump() { print(); } +LLVM_DUMP_METHOD void InlineCostCallAnalyzer::dump() { print(dbgs()); } #endif /// Test that there are no attribute conflicts between Caller and Callee @@ -3127,7 +3127,8 @@ InlineCostAnnotationPrinterPass::run(Function &F, ICCA.analyze(); OS << " Analyzing call of " << CalledFunction->getName() << "... (caller:" << CI->getCaller()->getName() << ")\n"; - ICCA.print(); + ICCA.print(OS); + OS << "\n"; } } } diff --git a/llvm/lib/Analysis/ReplayInlineAdvisor.cpp b/llvm/lib/Analysis/ReplayInlineAdvisor.cpp index c4e1d3fad3bba5b24d1d65480639a9ef9f8f9acd..ed4668c79f66a926e0084a57de02d714d245cab4 100644 --- a/llvm/lib/Analysis/ReplayInlineAdvisor.cpp +++ b/llvm/lib/Analysis/ReplayInlineAdvisor.cpp @@ -17,17 +17,19 @@ #include "llvm/IR/DebugInfoMetadata.h" #include "llvm/IR/Instructions.h" #include "llvm/Support/LineIterator.h" +#include using namespace llvm; -#define DEBUG_TYPE "inline-replay" +#define DEBUG_TYPE "replay-inline" ReplayInlineAdvisor::ReplayInlineAdvisor( Module &M, FunctionAnalysisManager &FAM, LLVMContext &Context, std::unique_ptr OriginalAdvisor, StringRef RemarksFile, - bool EmitRemarks) + ReplayInlineScope Scope, bool EmitRemarks) : InlineAdvisor(M, FAM), OriginalAdvisor(std::move(OriginalAdvisor)), - HasReplayRemarks(false), EmitRemarks(EmitRemarks) { + HasReplayRemarks(false), Scope(Scope), EmitRemarks(EmitRemarks) { + auto BufferOrErr = MemoryBuffer::getFileOrSTDIN(RemarksFile); std::error_code EC = BufferOrErr.getError(); if (EC) { @@ -36,46 +38,70 @@ ReplayInlineAdvisor::ReplayInlineAdvisor( } // Example for inline remarks to parse: - // main:3:1.1: '_Z3subii' inlined into 'main' at callsite sum:1 @ main:3:1.1 + // main:3:1.1: '_Z3subii' inlined into 'main' at callsite sum:1 @ + // main:3:1.1; // We use the callsite string after `at callsite` to replay inlining. line_iterator LineIt(*BufferOrErr.get(), /*SkipBlanks=*/true); for (; !LineIt.is_at_eof(); ++LineIt) { StringRef Line = *LineIt; auto Pair = Line.split(" at callsite "); - StringRef Callee = Pair.first.split(" inlined into") - .first.rsplit(": '") - .second.drop_back(); + auto CalleeCaller = Pair.first.split("' inlined into '"); + + StringRef Callee = CalleeCaller.first.rsplit(": '").second; + StringRef Caller = CalleeCaller.second.rsplit("'").first; + auto CallSite = Pair.second.split(";").first; - if (Callee.empty() || CallSite.empty()) - continue; + if (Callee.empty() || Caller.empty() || CallSite.empty()) { + Context.emitError("Invalid remark format: " + Line); + return; + } std::string Combined = (Callee + CallSite).str(); - InlineSitesFromRemarks.insert(Combined); + InlineSitesFromRemarks[Combined] = false; + if (Scope == ReplayInlineScope::Function) + CallersToReplay.insert(Caller); } HasReplayRemarks = true; } +std::unique_ptr llvm::getReplayInlineAdvisor( + Module &M, FunctionAnalysisManager &FAM, LLVMContext &Context, + std::unique_ptr OriginalAdvisor, StringRef RemarksFile, + ReplayInlineScope Scope, bool EmitRemarks) { + auto Advisor = std::make_unique( + M, FAM, Context, std::move(OriginalAdvisor), RemarksFile, Scope, + EmitRemarks); + if (!Advisor->areReplayRemarksLoaded()) + Advisor.reset(); + return Advisor; +} + std::unique_ptr ReplayInlineAdvisor::getAdviceImpl(CallBase &CB) { assert(HasReplayRemarks); Function &Caller = *CB.getCaller(); auto &ORE = FAM.getResult(Caller); - if (InlineSitesFromRemarks.empty()) - return std::make_unique(this, CB, None, ORE, - EmitRemarks); + Optional InlineRecommended; - std::string CallSiteLoc = getCallSiteLocation(CB.getDebugLoc()); - StringRef Callee = CB.getCalledFunction()->getName(); - std::string Combined = (Callee + CallSiteLoc).str(); - auto Iter = InlineSitesFromRemarks.find(Combined); + if (Scope == ReplayInlineScope::Module || + CallersToReplay.count(CB.getFunction()->getName())) { + std::string CallSiteLoc = getCallSiteLocation(CB.getDebugLoc()); + StringRef Callee = CB.getCalledFunction()->getName(); + std::string Combined = (Callee + CallSiteLoc).str(); - Optional InlineRecommended = None; - if (Iter != InlineSitesFromRemarks.end()) { - InlineRecommended = llvm::InlineCost::getAlways("found in replay"); + auto Iter = InlineSitesFromRemarks.find(Combined); + if (Iter != InlineSitesFromRemarks.end()) { + InlineSitesFromRemarks[Combined] = true; + InlineRecommended = llvm::InlineCost::getAlways("previously inlined"); + } + } else if (Scope == ReplayInlineScope::Function) { + if (OriginalAdvisor) + return OriginalAdvisor->getAdvice(CB); + return {}; } return std::make_unique(this, CB, InlineRecommended, ORE, diff --git a/llvm/lib/Analysis/StackSafetyAnalysis.cpp b/llvm/lib/Analysis/StackSafetyAnalysis.cpp index fa7dfd6b9900f056cc2d2804d40276fa52d219f3..74cc39b7f2c0d39c968242ab66cec583b1298b6d 100644 --- a/llvm/lib/Analysis/StackSafetyAnalysis.cpp +++ b/llvm/lib/Analysis/StackSafetyAnalysis.cpp @@ -154,7 +154,7 @@ raw_ostream &operator<<(raw_ostream &OS, const UseInfo &U) { ConstantRange getStaticAllocaSizeRange(const AllocaInst &AI) { const DataLayout &DL = AI.getModule()->getDataLayout(); TypeSize TS = DL.getTypeAllocSize(AI.getAllocatedType()); - unsigned PointerSize = DL.getMaxPointerSizeInBits(); + unsigned PointerSize = DL.getPointerTypeSizeInBits(AI.getType()); // Fallback to empty range for alloca size. ConstantRange R = ConstantRange::getEmpty(PointerSize); if (TS.isScalable()) @@ -752,10 +752,8 @@ GVToSSI createGlobalStackSafetyInfo( KV.second.Calls.clear(); } - uint32_t PointerSize = Copy.begin() - ->first->getParent() - ->getDataLayout() - .getMaxPointerSizeInBits(); + uint32_t PointerSize = + Copy.begin()->first->getParent()->getDataLayout().getPointerSizeInBits(); StackSafetyDataFlowAnalysis SSDFA(PointerSize, std::move(Copy)); for (auto &F : SSDFA.run()) { diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp index 08ec8c99d5737da3d22cbf11ae7e3e9a976307d4..b4c27dc86d8d81c189f04a150aba61810d263614 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp @@ -262,14 +262,14 @@ void DwarfCompileUnit::addLocationAttribute( if (Global) { const MCSymbol *Sym = Asm->getSymbol(Global); + unsigned PointerSize = Asm->getDataLayout().getPointerSize(); + assert((PointerSize == 4 || PointerSize == 8) && + "Add support for other sizes if necessary"); if (Global->isThreadLocal()) { if (Asm->TM.useEmulatedTLS()) { // TODO: add debug info for emulated thread local mode. } else { // FIXME: Make this work with -gsplit-dwarf. - unsigned PointerSize = Asm->getDataLayout().getPointerSize(); - assert((PointerSize == 4 || PointerSize == 8) && - "Add support for other sizes if necessary"); // Based on GCC's support for TLS: if (!DD->useSplitDwarf()) { // 1) Start with a constNu of the appropriate pointer size @@ -292,6 +292,24 @@ void DwarfCompileUnit::addLocationAttribute( DD->useGNUTLSOpcode() ? dwarf::DW_OP_GNU_push_tls_address : dwarf::DW_OP_form_tls_address); } + } else if (Asm->TM.getRelocationModel() == Reloc::RWPI || + Asm->TM.getRelocationModel() == Reloc::ROPI_RWPI) { + // Constant + addUInt(*Loc, dwarf::DW_FORM_data1, + PointerSize == 4 ? dwarf::DW_OP_const4u + : dwarf::DW_OP_const8u); + // Relocation offset + addExpr(*Loc, PointerSize == 4 ? dwarf::DW_FORM_data4 + : dwarf::DW_FORM_data8, + Asm->getObjFileLowering().getIndirectSymViaRWPI(Sym)); + // Base register + Register BaseReg = Asm->getObjFileLowering().getStaticBase(); + BaseReg = Asm->TM.getMCRegisterInfo()->getDwarfRegNum(BaseReg, false); + addUInt(*Loc, dwarf::DW_FORM_data1, dwarf::DW_OP_breg0 + BaseReg); + // Offset from base register + addSInt(*Loc, dwarf::DW_FORM_sdata, 0); + // Operation + addUInt(*Loc, dwarf::DW_FORM_data1, dwarf::DW_OP_plus); } else { DD->addArangeLabel(SymbolCU(this, Sym)); addOpAddress(*Loc, Sym); diff --git a/llvm/lib/CodeGen/ExpandMemCmp.cpp b/llvm/lib/CodeGen/ExpandMemCmp.cpp index 50fdc2114780b4208929b3f1273259336f88e643..d0c2b8c267ff20836d492dd53bceea66191e64b9 100644 --- a/llvm/lib/CodeGen/ExpandMemCmp.cpp +++ b/llvm/lib/CodeGen/ExpandMemCmp.cpp @@ -348,17 +348,17 @@ void MemCmpExpansion::emitLoadCompareByteBlock(unsigned BlockIndex, ConstantInt::get(Diff->getType(), 0)); BranchInst *CmpBr = BranchInst::Create(EndBlock, LoadCmpBlocks[BlockIndex + 1], Cmp); + Builder.Insert(CmpBr); if (DTU) DTU->applyUpdates( {{DominatorTree::Insert, BB, EndBlock}, {DominatorTree::Insert, BB, LoadCmpBlocks[BlockIndex + 1]}}); - Builder.Insert(CmpBr); } else { // The last block has an unconditional branch to EndBlock. BranchInst *CmpBr = BranchInst::Create(EndBlock); + Builder.Insert(CmpBr); if (DTU) DTU->applyUpdates({{DominatorTree::Insert, BB, EndBlock}}); - Builder.Insert(CmpBr); } } diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp index a3b2cc4dcd989f3b72ea6b615cb25159be355fa4..92cc28797a1a0a5e195095e1323dc70e1d3bfa01 100644 --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp @@ -4124,6 +4124,55 @@ bool CombinerHelper::matchBitfieldExtractFromShr( return true; } +bool CombinerHelper::matchBitfieldExtractFromShrAnd( + MachineInstr &MI, std::function &MatchInfo) { + const unsigned Opcode = MI.getOpcode(); + assert(Opcode == TargetOpcode::G_LSHR || Opcode == TargetOpcode::G_ASHR); + + const Register Dst = MI.getOperand(0).getReg(); + LLT Ty = MRI.getType(Dst); + if (!getTargetLowering().isConstantUnsignedBitfieldExtactLegal( + TargetOpcode::G_UBFX, Ty, Ty)) + return false; + + // Try to match shr (and x, c1), c2 + Register AndSrc; + int64_t ShrAmt; + int64_t SMask; + if (!mi_match(Dst, MRI, + m_BinOp(Opcode, + m_OneNonDBGUse(m_GAnd(m_Reg(AndSrc), m_ICst(SMask))), + m_ICst(ShrAmt)))) + return false; + + const unsigned Size = Ty.getScalarSizeInBits(); + if (ShrAmt < 0 || ShrAmt >= Size) + return false; + + // Check that ubfx can do the extraction, with no holes in the mask. + uint64_t UMask = SMask; + UMask |= maskTrailingOnes(ShrAmt); + UMask &= maskTrailingOnes(Size); + if (!isMask_64(UMask)) + return false; + + // Calculate start position and width of the extract. + const int64_t Pos = ShrAmt; + const int64_t Width = countTrailingOnes(UMask) - ShrAmt; + + // It's preferable to keep the shift, rather than form G_SBFX. + // TODO: remove the G_AND via demanded bits analysis. + if (Opcode == TargetOpcode::G_ASHR && Width + ShrAmt == Size) + return false; + + MatchInfo = [=](MachineIRBuilder &B) { + auto WidthCst = B.buildConstant(Ty, Width); + auto PosCst = B.buildConstant(Ty, Pos); + B.buildInstr(TargetOpcode::G_UBFX, {Dst}, {AndSrc, PosCst, WidthCst}); + }; + return true; +} + bool CombinerHelper::reassociationCanBreakAddressingModePattern( MachineInstr &PtrAdd) { assert(PtrAdd.getOpcode() == TargetOpcode::G_PTR_ADD); diff --git a/llvm/lib/CodeGen/LiveInterval.cpp b/llvm/lib/CodeGen/LiveInterval.cpp index 1eed0ec5bbbe82869c19e49f1034b6a9c1017ad8..1ff9813c992a5b5c6d506e82d5c947c50785896f 100644 --- a/llvm/lib/CodeGen/LiveInterval.cpp +++ b/llvm/lib/CodeGen/LiveInterval.cpp @@ -631,9 +631,8 @@ void LiveRange::removeSegment(SlotIndex Start, SlotIndex End, /// Also remove the value# from value# list. void LiveRange::removeValNo(VNInfo *ValNo) { if (empty()) return; - segments.erase(remove_if(*this, [ValNo](const Segment &S) { - return S.valno == ValNo; - }), end()); + llvm::erase_if(segments, + [ValNo](const Segment &S) { return S.valno == ValNo; }); // Now that ValNo is dead, remove it. markValNoForDeletion(ValNo); } diff --git a/llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp b/llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp index 191588e3f2b4dbb4326367616df688c9c61a5142..7153a3feccf4c32c1498b1f012ee5b7ba8d8db2f 100644 --- a/llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp +++ b/llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp @@ -12,6 +12,7 @@ #include "llvm/ExecutionEngine/JITLink/ELF_x86_64.h" #include "llvm/ExecutionEngine/JITLink/JITLink.h" +#include "llvm/ExecutionEngine/JITLink/TableManager.h" #include "llvm/ExecutionEngine/JITLink/x86_64.h" #include "llvm/Object/ELFObjectFile.h" #include "llvm/Support/Endian.h" @@ -21,7 +22,6 @@ #include "ELFLinkGraphBuilder.h" #include "JITLinkGeneric.h" #include "PerGraphGOTAndPLTStubsBuilder.h" -#include "TableManager.h" #define DEBUG_TYPE "jitlink" @@ -43,8 +43,8 @@ public: // Nice name for table StringRef getTableName() { return "GOT"; } - bool fixEdgeKind(LinkGraph &G, Block *B, Edge &E) { - Edge::Kind KindToSet = E.getKind(); + bool visitEdge(LinkGraph &G, Block *B, Edge &E) { + Edge::Kind KindToSet = Edge::Invalid; switch (E.getKind()) { case x86_64::Delta64FromGOT: { // we need to make sure that the GOT section exists, but don't otherwise @@ -70,6 +70,8 @@ public: default: return false; } + assert(KindToSet != Edge::Invalid && + "Fell through switch, but no new kind to set"); LLVM_DEBUG({ dbgs() << " Fixing " << G.getEdgeKindName(E.getKind()) << " edge at " << formatv("{0:x}", B->getFixupAddress(E)) << " (" @@ -77,6 +79,7 @@ public: << formatv("{0:x}", E.getOffset()) << ")\n"; }); E.setKind(KindToSet); + E.setTarget(getEntryForTarget(G, E.getTarget())); return true; } @@ -111,7 +114,7 @@ public: StringRef getTableName() { return "PLT"; } static const uint8_t StubContent[6]; - bool fixEdgeKind(LinkGraph &G, Block *B, Edge &E) { + bool visitEdge(LinkGraph &G, Block *B, Edge &E) { if (E.getKind() == x86_64::BranchPCRel32 && !E.getTarget().isDefined()) { LLVM_DEBUG({ dbgs() << " Fixing " << G.getEdgeKindName(E.getKind()) << " edge at " @@ -122,6 +125,7 @@ public: // Set the edge kind to Branch32ToPtrJumpStubBypassable to enable it to // be optimized when the target is in-range. E.setKind(x86_64::BranchPCRel32ToPtrJumpStubBypassable); + E.setTarget(getEntryForTarget(G, E.getTarget())); return true; } return false; @@ -161,7 +165,7 @@ public: StringRef getTableName() { return "TLSInfo"; } - bool fixEdgeKind(LinkGraph &G, Block *B, Edge &E) { + bool visitEdge(LinkGraph &G, Block *B, Edge &E) { if (E.getKind() == x86_64::RequestTLSDescInGOTAndTransformToDelta32) { LLVM_DEBUG({ dbgs() << " Fixing " << G.getEdgeKindName(E.getKind()) << " edge at " @@ -170,6 +174,7 @@ public: << formatv("{0:x}", E.getOffset()) << ")\n"; }); E.setKind(x86_64::Delta32); + E.setTarget(getEntryForTarget(G, E.getTarget())); return true; } return false; diff --git a/llvm/lib/IR/PassManager.cpp b/llvm/lib/IR/PassManager.cpp index bb8885a5e152daf84da4b0d78620160c8545270a..4965a7d53343733dcd2fbe18ffb486997fc73c88 100644 --- a/llvm/lib/IR/PassManager.cpp +++ b/llvm/lib/IR/PassManager.cpp @@ -10,12 +10,24 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/IR/LLVMContext.h" #include "llvm/IR/PassManagerImpl.h" +#include "llvm/Support/CommandLine.h" using namespace llvm; +namespace llvm { +// Experimental option to eagerly invalidate more analyses. This has the +// potential to decrease max memory usage in exchange for more compile time. +// This may affect codegen due to either passes using analyses only when +// cached, or invalidating and recalculating an analysis that was +// stale/imprecise but still valid. Currently this invalidates all function +// analyses after a module->function or cgscc->function adaptor. +// TODO: make this a PipelineTuningOption. +cl::opt EagerlyInvalidateAnalyses( + "eagerly-invalidate-analyses", cl::init(false), cl::Hidden, + cl::desc("Eagerly invalidate more analyses in default pipelines")); + // Explicit template instantiations and specialization defininitions for core // template typedefs. -namespace llvm { template class AllAnalysesOn; template class AllAnalysesOn; template class PassManager; @@ -129,7 +141,8 @@ PreservedAnalyses ModuleToFunctionPassAdaptor::run(Module &M, // We know that the function pass couldn't have invalidated any other // function's analyses (that's the contract of a function pass), so // directly handle the function analysis manager's invalidation here. - FAM.invalidate(F, PassPA); + FAM.invalidate(F, EagerlyInvalidateAnalyses ? PreservedAnalyses::none() + : PassPA); // Then intersect the preserved set so that invalidation of module // analyses will eventually occur when the module pass completes. diff --git a/llvm/lib/IR/ProfileSummary.cpp b/llvm/lib/IR/ProfileSummary.cpp index 453a278a7f3f7a49d2c8a21c178ba0d1452b5faa..05d5ac2c5ddf66e3688f84cbdafb10ef784f0346 100644 --- a/llvm/lib/IR/ProfileSummary.cpp +++ b/llvm/lib/IR/ProfileSummary.cpp @@ -249,7 +249,7 @@ ProfileSummary *ProfileSummary::getFromMD(Metadata *MD) { PartialProfileRatio); } -void ProfileSummary::printSummary(raw_ostream &OS) { +void ProfileSummary::printSummary(raw_ostream &OS) const { OS << "Total functions: " << NumFunctions << "\n"; OS << "Maximum function count: " << MaxFunctionCount << "\n"; OS << "Maximum block count: " << MaxCount << "\n"; @@ -257,7 +257,7 @@ void ProfileSummary::printSummary(raw_ostream &OS) { OS << "Total count: " << TotalCount << "\n"; } -void ProfileSummary::printDetailedSummary(raw_ostream &OS) { +void ProfileSummary::printDetailedSummary(raw_ostream &OS) const { OS << "Detailed summary:\n"; for (const auto &Entry : DetailedSummary) { OS << Entry.NumCounts << " blocks with count >= " << Entry.MinCount diff --git a/llvm/lib/LTO/CMakeLists.txt b/llvm/lib/LTO/CMakeLists.txt index 824e2e4e84c75ccdae6357a9c99be4be5a7e0e74..3abeceab055c81ae42260148465cb293e4a6323d 100644 --- a/llvm/lib/LTO/CMakeLists.txt +++ b/llvm/lib/LTO/CMakeLists.txt @@ -1,5 +1,4 @@ add_llvm_component_library(LLVMLTO - Caching.cpp LTO.cpp LTOBackend.cpp LTOModule.cpp diff --git a/llvm/lib/LTO/LTOCodeGenerator.cpp b/llvm/lib/LTO/LTOCodeGenerator.cpp index 412d6f31265035202dbde51ee2be27dc3aaca6ec..7dca994e735c480960085a1e2696213f55b0234d 100644 --- a/llvm/lib/LTO/LTOCodeGenerator.cpp +++ b/llvm/lib/LTO/LTOCodeGenerator.cpp @@ -245,8 +245,7 @@ bool LTOCodeGenerator::compileOptimizedToFile(const char **Name) { // make unique temp output file to put generated code SmallString<128> Filename; - auto AddStream = - [&](size_t Task) -> std::unique_ptr { + auto AddStream = [&](size_t Task) -> std::unique_ptr { StringRef Extension(Config.CGFileType == CGFT_AssemblyFile ? "s" : "o"); int FD; @@ -255,7 +254,7 @@ bool LTOCodeGenerator::compileOptimizedToFile(const char **Name) { if (EC) emitError(EC.message()); - return std::make_unique( + return std::make_unique( std::make_unique(FD, true)); }; @@ -557,7 +556,7 @@ bool LTOCodeGenerator::optimize() { return true; } -bool LTOCodeGenerator::compileOptimized(lto::AddStreamFn AddStream, +bool LTOCodeGenerator::compileOptimized(AddStreamFn AddStream, unsigned ParallelismLevel) { if (!this->determineTarget()) return false; diff --git a/llvm/lib/Support/CMakeLists.txt b/llvm/lib/Support/CMakeLists.txt index 771b7366e695a21ba4d84f7d4d707bcd2dab2adb..e6ec9684515b0632bd9ff17e020abbddacbe2755 100644 --- a/llvm/lib/Support/CMakeLists.txt +++ b/llvm/lib/Support/CMakeLists.txt @@ -123,6 +123,7 @@ add_llvm_component_library(LLVMSupport BranchProbability.cpp BuryPointer.cpp CachePruning.cpp + Caching.cpp circular_raw_ostream.cpp Chrono.cpp COM.cpp diff --git a/llvm/lib/LTO/Caching.cpp b/llvm/lib/Support/Caching.cpp similarity index 86% rename from llvm/lib/LTO/Caching.cpp rename to llvm/lib/Support/Caching.cpp index 75a89e729f43ca6e2f80043ebd4c718d22d4bd58..b4a50ede093bbddfa7cc6d760cf601bb243fe8f1 100644 --- a/llvm/lib/LTO/Caching.cpp +++ b/llvm/lib/Support/Caching.cpp @@ -1,4 +1,4 @@ -//===-Caching.cpp - LLVM Link Time Optimizer Cache Handling ---------------===// +//===-Caching.cpp - LLVM File Cache Handling ------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,11 +6,11 @@ // //===----------------------------------------------------------------------===// // -// This file implements the Caching for ThinLTO. +// This file implements the Caching used by ThinLTO. // //===----------------------------------------------------------------------===// -#include "llvm/LTO/Caching.h" +#include "llvm/Support/Caching.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Support/Errc.h" #include "llvm/Support/FileSystem.h" @@ -26,13 +26,20 @@ #endif using namespace llvm; -using namespace llvm::lto; -Expected lto::localCache(StringRef CacheDirectoryPath, - AddBufferFn AddBuffer) { - if (std::error_code EC = sys::fs::create_directories(CacheDirectoryPath)) +Expected llvm::localCache(Twine CacheNameRef, + Twine TempFilePrefixRef, + Twine CacheDirectoryPathRef, + AddBufferFn AddBuffer) { + if (std::error_code EC = sys::fs::create_directories(CacheDirectoryPathRef)) return errorCodeToError(EC); + // Create local copies which are safely captured-by-copy in lambdas + SmallString<64> CacheName, TempFilePrefix, CacheDirectoryPath; + CacheNameRef.toVector(CacheName); + TempFilePrefixRef.toVector(TempFilePrefix); + CacheDirectoryPathRef.toVector(CacheDirectoryPath); + return [=](unsigned Task, StringRef Key) -> AddStreamFn { // This choice of file name allows the cache to be pruned (see pruneCache() // in include/llvm/Support/CachePruning.h). @@ -134,12 +141,13 @@ Expected lto::localCache(StringRef CacheDirectoryPath, return [=](size_t Task) -> std::unique_ptr { // Write to a temporary to avoid race condition SmallString<64> TempFilenameModel; - sys::path::append(TempFilenameModel, CacheDirectoryPath, "Thin-%%%%%%.tmp.o"); + sys::path::append(TempFilenameModel, CacheDirectoryPath, + TempFilePrefix + "-%%%%%%.tmp.o"); Expected Temp = sys::fs::TempFile::create( TempFilenameModel, sys::fs::owner_read | sys::fs::owner_write); if (!Temp) { errs() << "Error: " << toString(Temp.takeError()) << "\n"; - report_fatal_error("ThinLTO: Can't get a temporary file"); + report_fatal_error(CacheName + ": Can't get a temporary file"); } // This CacheStream will move the temporary file into the cache when done. diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 795d77defc984170b0ee0c40da1d13d4758bd0c6..8bbfc757f07556db2a8bcbfaf447df6ba422022e 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -11,7 +11,6 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" -#include "llvm/Option/ArgList.h" #include "llvm/Support/Errc.h" #include "llvm/Support/Error.h" #include "llvm/Support/raw_ostream.h" @@ -252,8 +251,9 @@ bool RISCVISAInfo::compareExtension(const std::string &LHS, return LHS < RHS; } -void RISCVISAInfo::toFeatures(const llvm::opt::ArgList &Args, - std::vector &Features) const { +void RISCVISAInfo::toFeatures( + std::vector &Features, + std::function StrAlloc) const { for (auto &Ext : Exts) { StringRef ExtName = Ext.first; @@ -268,9 +268,9 @@ void RISCVISAInfo::toFeatures(const llvm::opt::ArgList &Args, Features.push_back("+experimental-zvlsseg"); Features.push_back("+experimental-zvamo"); } else if (isExperimentalExtension(ExtName)) { - Features.push_back(Args.MakeArgString("+experimental-" + ExtName)); + Features.push_back(StrAlloc("+experimental-" + ExtName)); } else { - Features.push_back(Args.MakeArgString("+" + ExtName)); + Features.push_back(StrAlloc("+" + ExtName)); } } } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp index 7ff24d1e9c62b37774b9143d3f377ae7fe5aa94e..2e24e9f929d2a6039263c25d79fcc1426ffdbfd7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp @@ -15,6 +15,7 @@ #include "AMDGPU.h" #include "AMDGPUTargetMachine.h" #include "Utils/AMDGPUBaseInfo.h" +#include "llvm/CodeGen/CommandFlags.h" #include "llvm/IR/Module.h" #include "llvm/Pass.h" #include "llvm/Support/CommandLine.h" @@ -90,9 +91,13 @@ static bool alwaysInlineImpl(Module &M, bool GlobalOpt) { SmallPtrSet FuncsToAlwaysInline; SmallPtrSet FuncsToNoInline; + Triple TT(M.getTargetTriple()); for (GlobalAlias &A : M.aliases()) { if (Function* F = dyn_cast(A.getAliasee())) { + if (TT.getArch() == Triple::amdgcn && + A.getLinkage() != GlobalValue::InternalLinkage) + continue; A.replaceAllUsesWith(F); AliasesToRemove.push_back(&A); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUReplaceLDSUseWithPointer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUReplaceLDSUseWithPointer.cpp index 08e1dacf7bad649193aa89971a9caccddbccd7aa..d55bf3917e9c1bd2c48bd8fd057c79eaf1beeea1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUReplaceLDSUseWithPointer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUReplaceLDSUseWithPointer.cpp @@ -130,11 +130,9 @@ class ReplaceLDSUseImpl { std::vector LDSGlobals = AMDGPU::findVariablesToLower(M); // Remove LDS which don't qualify for replacement. - LDSGlobals.erase(std::remove_if(LDSGlobals.begin(), LDSGlobals.end(), - [&](GlobalVariable *GV) { - return shouldIgnorePointerReplacement(GV); - }), - LDSGlobals.end()); + llvm::erase_if(LDSGlobals, [&](GlobalVariable *GV) { + return shouldIgnorePointerReplacement(GV); + }); return LDSGlobals; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp b/llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp index e841e939ef34bca9f72fa70be7bd7a7139edb27c..3c5cb6e1908506e0bddd2ae1d7093fa79179f9d6 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp @@ -29,6 +29,8 @@ #include "SIMachineFunctionInfo.h" #include "llvm/Analysis/CallGraph.h" #include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/IR/GlobalAlias.h" +#include "llvm/IR/GlobalValue.h" #include "llvm/Target/TargetMachine.h" using namespace llvm; @@ -61,7 +63,8 @@ static const Function *getCalleeFunction(const MachineOperand &Op) { assert(Op.getImm() == 0); return nullptr; } - + if (auto *GA = dyn_cast(Op.getGlobal())) + return cast(GA->getOperand(0)); return cast(Op.getGlobal()); } diff --git a/llvm/lib/Target/ARM/ARMTargetObjectFile.cpp b/llvm/lib/Target/ARM/ARMTargetObjectFile.cpp index b03bff92f373bf90c6d5bd1e33e63f166393a568..8c5438f7093be0bb07bbc4aa16eb5fa436ff9f4a 100644 --- a/llvm/lib/Target/ARM/ARMTargetObjectFile.cpp +++ b/llvm/lib/Target/ARM/ARMTargetObjectFile.cpp @@ -54,6 +54,16 @@ void ARMElfTargetObjectFile::Initialize(MCContext &Ctx, } } +const MCRegister ARMElfTargetObjectFile::getStaticBase() const { + return ARM::R9; +} + +const MCExpr *ARMElfTargetObjectFile:: +getIndirectSymViaRWPI(const MCSymbol *Sym) const { + return MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_ARM_SBREL, + getContext()); +} + const MCExpr *ARMElfTargetObjectFile::getTTypeGlobalReference( const GlobalValue *GV, unsigned Encoding, const TargetMachine &TM, MachineModuleInfo *MMI, MCStreamer &Streamer) const { diff --git a/llvm/lib/Target/ARM/ARMTargetObjectFile.h b/llvm/lib/Target/ARM/ARMTargetObjectFile.h index 7b15dcc61f566aaf081fa9c6cc4648fee9b40a51..8b13198fe144fd7385d48863fc19b76f6894b3ba 100644 --- a/llvm/lib/Target/ARM/ARMTargetObjectFile.h +++ b/llvm/lib/Target/ARM/ARMTargetObjectFile.h @@ -11,6 +11,7 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCRegister.h" namespace llvm { @@ -23,6 +24,10 @@ public: void Initialize(MCContext &Ctx, const TargetMachine &TM) override; + const MCRegister getStaticBase() const override; + + const MCExpr *getIndirectSymViaRWPI(const MCSymbol *Sym) const override; + const MCExpr *getTTypeGlobalReference(const GlobalValue *GV, unsigned Encoding, const TargetMachine &TM, diff --git a/llvm/lib/Target/BPF/BPF.h b/llvm/lib/Target/BPF/BPF.h index a98a3e08d5de7e516f84f95aa5f3613966d4c279..89990f7e15c28491f70609513b09262a3fe35b88 100644 --- a/llvm/lib/Target/BPF/BPF.h +++ b/llvm/lib/Target/BPF/BPF.h @@ -21,6 +21,7 @@ ModulePass *createBPFCheckAndAdjustIR(); FunctionPass *createBPFAbstractMemberAccess(BPFTargetMachine *TM); FunctionPass *createBPFPreserveDIType(); +FunctionPass *createBPFIRPeephole(); FunctionPass *createBPFISelDag(BPFTargetMachine &TM); FunctionPass *createBPFMISimplifyPatchablePass(); FunctionPass *createBPFMIPeepholePass(); @@ -33,6 +34,7 @@ void initializeBPFCheckAndAdjustIRPass(PassRegistry&); void initializeBPFAbstractMemberAccessLegacyPassPass(PassRegistry &); void initializeBPFPreserveDITypePass(PassRegistry&); +void initializeBPFIRPeepholePass(PassRegistry&); void initializeBPFMISimplifyPatchablePass(PassRegistry&); void initializeBPFMIPeepholePass(PassRegistry&); void initializeBPFMIPeepholeTruncElimPass(PassRegistry&); @@ -57,6 +59,13 @@ public: static bool isRequired() { return true; } }; +class BPFIRPeepholePass : public PassInfoMixin { +public: + PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); + + static bool isRequired() { return true; } +}; + class BPFAdjustOptPass : public PassInfoMixin { public: PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); diff --git a/llvm/lib/Target/BPF/BPFIRPeephole.cpp b/llvm/lib/Target/BPF/BPFIRPeephole.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d6a70012dca044aca11fdf8ef662bbc4c2400919 --- /dev/null +++ b/llvm/lib/Target/BPF/BPFIRPeephole.cpp @@ -0,0 +1,118 @@ +//===------------ BPFIRPeephole.cpp - IR Peephole Transformation ----------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// IR level peephole optimization, specifically removing @llvm.stacksave() and +// @llvm.stackrestore(). +// +//===----------------------------------------------------------------------===// + +#include "BPF.h" +#include "llvm/IR/Instruction.h" +#include "llvm/IR/Instructions.h" +#include "llvm/IR/Module.h" +#include "llvm/IR/PassManager.h" +#include "llvm/IR/Type.h" +#include "llvm/IR/User.h" +#include "llvm/IR/Value.h" +#include "llvm/Pass.h" + +#define DEBUG_TYPE "bpf-ir-peephole" + +using namespace llvm; + +namespace { + +static bool BPFIRPeepholeImpl(Function &F) { + LLVM_DEBUG(dbgs() << "******** BPF IR Peephole ********\n"); + + bool Changed = false; + Instruction *ToErase = nullptr; + for (auto &BB : F) { + for (auto &I : BB) { + // The following code pattern is handled: + // %3 = call i8* @llvm.stacksave() + // store i8* %3, i8** %saved_stack, align 8 + // ... + // %4 = load i8*, i8** %saved_stack, align 8 + // call void @llvm.stackrestore(i8* %4) + // ... + // The goal is to remove the above four instructions, + // so we won't have instructions with r11 (stack pointer) + // if eventually there is no variable length stack allocation. + // InstrCombine also tries to remove the above instructions, + // if it is proven safe (constant alloca etc.), but depending + // on code pattern, it may still miss some. + // + // With unconditionally removing these instructions, if alloca is + // constant, we are okay then. Otherwise, SelectionDag will complain + // since BPF does not support dynamic allocation yet. + if (ToErase) { + ToErase->eraseFromParent(); + ToErase = nullptr; + } + + if (auto *Call = dyn_cast(&I)) { + if (auto *GV = dyn_cast(Call->getCalledOperand())) { + if (!GV->getName().equals("llvm.stacksave")) + continue; + if (!Call->hasOneUser()) + continue; + auto *Inst = cast(*Call->user_begin()); + LLVM_DEBUG(dbgs() << "Remove:"; I.dump()); + LLVM_DEBUG(dbgs() << "Remove:"; Inst->dump(); dbgs() << '\n'); + Changed = true; + Inst->eraseFromParent(); + ToErase = &I; + } + continue; + } + + if (auto *LD = dyn_cast(&I)) { + if (!LD->hasOneUser()) + continue; + auto *Call = dyn_cast(*LD->user_begin()); + if (!Call) + continue; + auto *GV = dyn_cast(Call->getCalledOperand()); + if (!GV) + continue; + if (!GV->getName().equals("llvm.stackrestore")) + continue; + LLVM_DEBUG(dbgs() << "Remove:"; I.dump()); + LLVM_DEBUG(dbgs() << "Remove:"; Call->dump(); dbgs() << '\n'); + Changed = true; + Call->eraseFromParent(); + ToErase = &I; + } + } + } + + return Changed; +} + +class BPFIRPeephole final : public FunctionPass { + bool runOnFunction(Function &F) override; + +public: + static char ID; + BPFIRPeephole() : FunctionPass(ID) {} +}; +} // End anonymous namespace + +char BPFIRPeephole::ID = 0; +INITIALIZE_PASS(BPFIRPeephole, DEBUG_TYPE, "BPF IR Peephole", false, false) + +FunctionPass *llvm::createBPFIRPeephole() { return new BPFIRPeephole(); } + +bool BPFIRPeephole::runOnFunction(Function &F) { return BPFIRPeepholeImpl(F); } + +PreservedAnalyses BPFIRPeepholePass::run(Function &F, + FunctionAnalysisManager &AM) { + return BPFIRPeepholeImpl(F) ? PreservedAnalyses::none() + : PreservedAnalyses::all(); +} diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp index b383e4cace9e5057a735932b3215ef724197e45e..2fb76ab5c440ec17a32918344f89be2fdf742dbe 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp +++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp @@ -43,6 +43,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeBPFTarget() { PassRegistry &PR = *PassRegistry::getPassRegistry(); initializeBPFAbstractMemberAccessLegacyPassPass(PR); initializeBPFPreserveDITypePass(PR); + initializeBPFIRPeepholePass(PR); initializeBPFAdjustOptPass(PR); initializeBPFCheckAndAdjustIRPass(PR); initializeBPFMIPeepholePass(PR); @@ -107,6 +108,7 @@ void BPFTargetMachine::adjustPassManager(PassManagerBuilder &Builder) { [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) { PM.add(createBPFAbstractMemberAccess(this)); PM.add(createBPFPreserveDIType()); + PM.add(createBPFIRPeephole()); }); Builder.addExtension( @@ -128,6 +130,7 @@ void BPFTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { FunctionPassManager FPM; FPM.addPass(BPFAbstractMemberAccessPass(this)); FPM.addPass(BPFPreserveDITypePass()); + FPM.addPass(BPFIRPeepholePass()); MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM))); }); PB.registerPeepholeEPCallback([=](FunctionPassManager &FPM, diff --git a/llvm/lib/Target/BPF/BTF.h b/llvm/lib/Target/BPF/BTF.h index 59ba982b36b241e297d4858c177fa40a746c181c..95a64609ae389eb694dd367a00c552505f2b26d9 100644 --- a/llvm/lib/Target/BPF/BTF.h +++ b/llvm/lib/Target/BPF/BTF.h @@ -106,7 +106,7 @@ struct CommonType { /// Bits 24-27: kind (e.g. int, ptr, array...etc) /// Bits 28-30: unused /// Bit 31: kind_flag, currently used by - /// struct, union, fwd and decl_tag + /// struct, union and fwd uint32_t Info; /// "Size" is used by INT, ENUM, STRUCT and UNION. diff --git a/llvm/lib/Target/BPF/BTFDebug.cpp b/llvm/lib/Target/BPF/BTFDebug.cpp index 233397533511f94d141f85cc14a584775a370df1..738d472f6efec716fb738e7cdb806fd6d0642229 100644 --- a/llvm/lib/Target/BPF/BTFDebug.cpp +++ b/llvm/lib/Target/BPF/BTFDebug.cpp @@ -497,8 +497,9 @@ void BTFDebug::visitSubroutineType( } } -void BTFDebug::processAnnotations(DINodeArray Annotations, uint32_t BaseTypeId, - int ComponentIdx) { +void BTFDebug::processDeclAnnotations(DINodeArray Annotations, + uint32_t BaseTypeId, + int ComponentIdx) { if (!Annotations) return; @@ -539,14 +540,14 @@ void BTFDebug::visitStructType(const DICompositeType *CTy, bool IsStruct, TypeId = addType(std::move(TypeEntry), CTy); // Check struct/union annotations - processAnnotations(CTy->getAnnotations(), TypeId, -1); + processDeclAnnotations(CTy->getAnnotations(), TypeId, -1); // Visit all struct members. int FieldNo = 0; for (const auto *Element : Elements) { const auto Elem = cast(Element); visitTypeEntry(Elem); - processAnnotations(Elem->getAnnotations(), TypeId, FieldNo); + processDeclAnnotations(Elem->getAnnotations(), TypeId, FieldNo); FieldNo++; } } @@ -1017,11 +1018,11 @@ void BTFDebug::beginFunctionImpl(const MachineFunction *MF) { if (const auto *DV = dyn_cast(DN)) { uint32_t Arg = DV->getArg(); if (Arg) - processAnnotations(DV->getAnnotations(), FuncTypeId, Arg - 1); + processDeclAnnotations(DV->getAnnotations(), FuncTypeId, Arg - 1); } } - processAnnotations(SP->getAnnotations(), FuncTypeId, -1); + processDeclAnnotations(SP->getAnnotations(), FuncTypeId, -1); for (const auto &TypeEntry : TypeEntries) TypeEntry->completeType(*this); @@ -1273,7 +1274,7 @@ void BTFDebug::processGlobals(bool ProcessingMapDef) { std::make_unique(Global.getName(), GVTypeId, GVarInfo); uint32_t VarId = addType(std::move(VarEntry)); - processAnnotations(DIGlobal->getAnnotations(), VarId, -1); + processDeclAnnotations(DIGlobal->getAnnotations(), VarId, -1); // An empty SecName means an extern variable without section attribute. if (SecName.empty()) @@ -1370,7 +1371,7 @@ void BTFDebug::processFuncPrototypes(const Function *F) { std::make_unique(SP->getName(), ProtoTypeId, Scope); uint32_t FuncId = addType(std::move(FuncTypeEntry)); - processAnnotations(SP->getAnnotations(), FuncId, -1); + processDeclAnnotations(SP->getAnnotations(), FuncId, -1); if (F->hasSection()) { StringRef SecName = F->getSection(); diff --git a/llvm/lib/Target/BPF/BTFDebug.h b/llvm/lib/Target/BPF/BTFDebug.h index 30f9d9abaec99ce5ddf346248e351bfce6e071ff..9e0203f292b265c6a6eed923ca2f24ad5f192d3e 100644 --- a/llvm/lib/Target/BPF/BTFDebug.h +++ b/llvm/lib/Target/BPF/BTFDebug.h @@ -204,7 +204,7 @@ public: void completeType(BTFDebug &BDebug) override; }; -/// Handle tags. +/// Handle decl tags. class BTFTypeDeclTag : public BTFTypeBase { uint32_t Info; StringRef Tag; @@ -325,9 +325,9 @@ class BTFDebug : public DebugHandlerBase { /// Generate types for function prototypes. void processFuncPrototypes(const Function *); - /// Generate types for annotations. - void processAnnotations(DINodeArray Annotations, uint32_t BaseTypeId, - int ComponentId); + /// Generate types for decl annotations. + void processDeclAnnotations(DINodeArray Annotations, uint32_t BaseTypeId, + int ComponentId); /// Generate one field relocation record. void generatePatchImmReloc(const MCSymbol *ORSym, uint32_t RootId, diff --git a/llvm/lib/Target/BPF/CMakeLists.txt b/llvm/lib/Target/BPF/CMakeLists.txt index 2d804ca8a73ebd640f2ec1abd0cec1251f26e175..6ad0127e0dfe71b4b269a3bc888fbcc131c37b55 100644 --- a/llvm/lib/Target/BPF/CMakeLists.txt +++ b/llvm/lib/Target/BPF/CMakeLists.txt @@ -21,6 +21,7 @@ add_llvm_target(BPFCodeGen BPFCheckAndAdjustIR.cpp BPFFrameLowering.cpp BPFInstrInfo.cpp + BPFIRPeephole.cpp BPFISelDAGToDAG.cpp BPFISelLowering.cpp BPFMCInstLower.cpp diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 5dfcd02fdb0083128b9df66e2748db018973dcc4..3f5dbb67407f1084f980f583718b16880130e14f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -170,9 +170,7 @@ unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, static bool forwardCopyWillClobberTuple(unsigned DstReg, unsigned SrcReg, unsigned NumRegs) { - // We really want the positive remainder mod 32 here, that happens to be - // easily obtainable with a mask. - return ((DstReg - SrcReg) & 0x1f) < NumRegs; + return DstReg > SrcReg && (DstReg - SrcReg) < NumRegs; } void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index d941de91957e6e31aede18a24f89ac3c5703061f..400bb3adf7dae28a28a3525136eedf354a52e5a5 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -487,8 +487,7 @@ def VR : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t, vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t, vbool64_t, vbool32_t, vbool16_t, vbool8_t, vbool4_t, vbool2_t, vbool1_t], - (add (sequence "V%u", 25, 31), - (sequence "V%u", 8, 24), + (add (sequence "V%u", 8, 31), (sequence "V%u", 0, 7)), 1>; def VRNoV0 : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t, @@ -498,27 +497,26 @@ def VRNoV0 : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t, vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t, vbool64_t, vbool32_t, vbool16_t, vbool8_t, vbool4_t, vbool2_t, vbool1_t], - (add (sequence "V%u", 25, 31), - (sequence "V%u", 8, 24), + (add (sequence "V%u", 8, 31), (sequence "V%u", 1, 7)), 1>; def VRM2 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t, vfloat16m2_t, vfloat32m2_t, vfloat64m2_t], - (add V26M2, V28M2, V30M2, V8M2, V10M2, V12M2, V14M2, V16M2, - V18M2, V20M2, V22M2, V24M2, V0M2, V2M2, V4M2, V6M2), 2>; + (add (sequence "V%uM2", 8, 31, 2), + (sequence "V%uM2", 0, 7, 2)), 2>; def VRM2NoV0 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t, vfloat16m2_t, vfloat32m2_t, vfloat64m2_t], - (add V26M2, V28M2, V30M2, V8M2, V10M2, V12M2, V14M2, V16M2, - V18M2, V20M2, V22M2, V24M2, V2M2, V4M2, V6M2), 2>; + (add (sequence "V%uM2", 8, 31, 2), + (sequence "V%uM2", 2, 7, 2)), 2>; def VRM4 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t, vfloat16m4_t, vfloat32m4_t, vfloat64m4_t], - (add V28M4, V8M4, V12M4, V16M4, V20M4, V24M4, V0M4, V4M4), 4>; + (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V0M4, V4M4), 4>; def VRM4NoV0 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t, vfloat16m4_t, vfloat32m4_t, vfloat64m4_t], - (add V28M4, V8M4, V12M4, V16M4, V20M4, V24M4, V4M4), 4>; + (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V4M4), 4>; def VRM8 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t, vfloat16m8_t, vfloat32m8_t, vfloat64m8_t], @@ -526,7 +524,7 @@ def VRM8 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t, def VRM8NoV0 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t, vfloat16m8_t, vfloat32m8_t, vfloat64m8_t], - (add V8M8, V16M8, V24M8), 8>; + (add V8M8, V16M8, V24M8), 8>; defvar VMaskVTs = [vbool64_t, vbool32_t, vbool16_t, vbool8_t, vbool4_t, vbool2_t, vbool1_t]; @@ -539,8 +537,7 @@ def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> { // The register class is added for inline assembly for vector mask types. def VM : VReg<[vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t, vbool32_t, vbool64_t], - (add (sequence "V%u", 25, 31), - (sequence "V%u", 8, 24), + (add (sequence "V%u", 8, 31), (sequence "V%u", 0, 7)), 1>; foreach m = LMULList.m in { diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index 7bc8ebcdcdb74fa949ac83d2709a7d5df08f3aa9..8cf96f64d9d543c894862edfaddf1b1101411fbf 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -2027,12 +2027,8 @@ SDValue WebAssemblyTargetLowering::LowerBUILD_VECTOR(SDValue Op, size_t NumShuffleLanes = 0; if (ShuffleCounts.size()) { std::tie(ShuffleSrc1, NumShuffleLanes) = GetMostCommon(ShuffleCounts); - ShuffleCounts.erase(std::remove_if(ShuffleCounts.begin(), - ShuffleCounts.end(), - [&](const auto &Pair) { - return Pair.first == ShuffleSrc1; - }), - ShuffleCounts.end()); + llvm::erase_if(ShuffleCounts, + [&](const auto &Pair) { return Pair.first == ShuffleSrc1; }); } if (ShuffleCounts.size()) { size_t AdditionalShuffleLanes; diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 2d7d4dd14c1adab5019170e30ca72d5bd1e5b93b..32f8ade5f9b6da6a43003e24b25d251ce0133e77 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -374,6 +374,13 @@ def FeatureLVILoadHardening "Insert LFENCE instructions to prevent data speculatively injected " "into loads from being used maliciously.">; +def FeatureTaggedGlobals + : SubtargetFeature< + "tagged-globals", "AllowTaggedGlobals", "true", + "Use an instruction sequence for taking the address of a global " + "that allows a memory tag in the upper address bits. Currently " + "also requires -mrelax-relocations=no to work properly.">; + //===----------------------------------------------------------------------===// // X86 Subtarget Tuning features //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 22824004877cbb43620de1bddf9b4b77cc31b55e..85ff029cf4c56a657c190951cfc1dfe963a937d0 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -44463,6 +44463,12 @@ static SDValue combineMulToPMADDWD(SDNode *N, SelectionDAG &DAG, if (Src.getScalarValueSizeInBits() == 16) return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(N), VT, Src); } + // Convert VSRAI(Op, 16) to VSRLI(Op, 16). + if (Op.getOpcode() == X86ISD::VSRAI && Op.getConstantOperandVal(1) == 16 && + N->isOnlyUserOf(Op.getNode())) { + return DAG.getNode(X86ISD::VSRLI, SDLoc(N), VT, Op.getOperand(0), + Op.getOperand(1)); + } return SDValue(); }; SDValue ZeroN0 = GetZeroableOp(N0); diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp index b985a3aa52102d2a79232d475d9b79b7f4dfd8c6..45732fafdcc2b3168bf388aa0d69ee50d8de1748 100644 --- a/llvm/lib/Target/X86/X86Subtarget.cpp +++ b/llvm/lib/Target/X86/X86Subtarget.cpp @@ -67,6 +67,13 @@ X86Subtarget::classifyGlobalReference(const GlobalValue *GV) const { unsigned char X86Subtarget::classifyLocalReference(const GlobalValue *GV) const { + // Tagged globals have non-zero upper bits, which makes direct references + // require a 64-bit immediate. On the small code model this causes relocation + // errors, so we go through the GOT instead. + if (AllowTaggedGlobals && TM.getCodeModel() == CodeModel::Small && + !isa_and_nonnull(GV)) + return X86II::MO_GOTPCREL; + // If we're not PIC, it's not very interesting. if (!isPositionIndependent()) return X86II::MO_NO_FLAG; diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h index 796bd83f2a273602e295c70181d8a24b6f7158f2..455e947c7b67ebd5a0acc8f4bb309f6ada940885 100644 --- a/llvm/lib/Target/X86/X86Subtarget.h +++ b/llvm/lib/Target/X86/X86Subtarget.h @@ -476,6 +476,10 @@ class X86Subtarget final : public X86GenSubtargetInfo { /// loads from being used maliciously. bool UseLVILoadHardening = false; + /// Use an instruction sequence for taking the address of a global that allows + /// a memory tag in the upper address bits. + bool AllowTaggedGlobals = false; + /// Use software floating point for code generation. bool UseSoftFloat = false; @@ -795,6 +799,7 @@ public: bool preferMaskRegisters() const { return PreferMaskRegisters; } bool useGLMDivSqrtCosts() const { return UseGLMDivSqrtCosts; } bool useLVIControlFlowIntegrity() const { return UseLVIControlFlowIntegrity; } + bool allowTaggedGlobals() const { return AllowTaggedGlobals; } bool useLVILoadHardening() const { return UseLVILoadHardening; } bool useSpeculativeExecutionSideEffectSuppression() const { return UseSpeculativeExecutionSideEffectSuppression; diff --git a/llvm/lib/Transforms/IPO/Inliner.cpp b/llvm/lib/Transforms/IPO/Inliner.cpp index f2ca1b2516dd21c6f63b6eb0cc682d86a1e6d6ea..d9059911e534c9718319e8852c1707412b98d87f 100644 --- a/llvm/lib/Transforms/IPO/Inliner.cpp +++ b/llvm/lib/Transforms/IPO/Inliner.cpp @@ -97,7 +97,19 @@ static cl::opt CGSCCInlineReplayFile( "cgscc-inline-replay", cl::init(""), cl::value_desc("filename"), cl::desc( "Optimization remarks file containing inline remarks to be replayed " - "by inlining from cgscc inline remarks."), + "by cgscc inlining."), + cl::Hidden); + +static cl::opt CGSCCInlineReplayScope( + "cgscc-inline-replay-scope", cl::init(ReplayInlineScope::Function), + cl::values(clEnumValN(ReplayInlineScope::Function, "Function", + "Replay on functions that have remarks associated " + "with them (default)"), + clEnumValN(ReplayInlineScope::Module, "Module", + "Replay on the entire module")), + cl::desc("Whether inline replay should be applied to the entire " + "Module or just the Functions (default) that are present as " + "callers in remarks during cgscc inlining."), cl::Hidden); static cl::opt InlineEnablePriorityOrder( @@ -662,9 +674,9 @@ InlinerPass::getAdvisor(const ModuleAnalysisManagerCGSCCProxy::Result &MAM, std::make_unique(M, FAM, getInlineParams()); if (!CGSCCInlineReplayFile.empty()) - OwnedAdvisor = std::make_unique( + OwnedAdvisor = getReplayInlineAdvisor( M, FAM, M.getContext(), std::move(OwnedAdvisor), - CGSCCInlineReplayFile, + CGSCCInlineReplayFile, CGSCCInlineReplayScope, /*EmitRemarks=*/true); return *OwnedAdvisor; @@ -827,8 +839,9 @@ PreservedAnalyses InlinerPass::run(LazyCallGraph::SCC &InitialC, } auto Advice = Advisor.getAdvice(*CB, OnlyMandatory); + // Check whether we want to inline this callsite. - if (!Advice->isInliningRecommended()) { + if (!Advice || !Advice->isInliningRecommended()) { Advice->recordUnattemptedInlining(); continue; } @@ -1027,7 +1040,8 @@ ModuleInlinerWrapperPass::ModuleInlinerWrapperPass(InlineParams Params, PreservedAnalyses ModuleInlinerWrapperPass::run(Module &M, ModuleAnalysisManager &MAM) { auto &IAA = MAM.getResult(M); - if (!IAA.tryCreate(Params, Mode, CGSCCInlineReplayFile)) { + if (!IAA.tryCreate(Params, Mode, CGSCCInlineReplayFile, + CGSCCInlineReplayScope)) { M.getContext().emitError( "Could not setup Inlining Advisor for the requested " "mode and/or options"); diff --git a/llvm/lib/Transforms/IPO/SampleProfile.cpp b/llvm/lib/Transforms/IPO/SampleProfile.cpp index 90cc38d80e0ec2316b7cfc7b649542121dfa26ea..a0b351249d25b2b6f96d52c329db6a8f74f449d4 100644 --- a/llvm/lib/Transforms/IPO/SampleProfile.cpp +++ b/llvm/lib/Transforms/IPO/SampleProfile.cpp @@ -45,7 +45,6 @@ #include "llvm/Analysis/OptimizationRemarkEmitter.h" #include "llvm/Analysis/PostDominators.h" #include "llvm/Analysis/ProfileSummaryInfo.h" -#include "llvm/Analysis/ReplayInlineAdvisor.h" #include "llvm/Analysis/TargetLibraryInfo.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/IR/BasicBlock.h" @@ -237,6 +236,18 @@ static cl::opt ProfileInlineReplayFile( "by inlining from sample profile loader."), cl::Hidden); +static cl::opt ProfileInlineReplayScope( + "sample-profile-inline-replay-scope", cl::init(ReplayInlineScope::Function), + cl::values(clEnumValN(ReplayInlineScope::Function, "Function", + "Replay on functions that have remarks associated " + "with them (default)"), + clEnumValN(ReplayInlineScope::Module, "Module", + "Replay on the entire module")), + cl::desc("Whether inline replay should be applied to the entire " + "Module or just the Functions (default) that are present as " + "callers in remarks during sample profile inlining."), + cl::Hidden); + static cl::opt MaxNumPromotions("sample-profile-icp-max-prom", cl::init(3), cl::Hidden, cl::ZeroOrMore, @@ -477,7 +488,7 @@ protected: bool ProfAccForSymsInList; // External inline advisor used to replay inline decision from remarks. - std::unique_ptr ExternalInlineAdvisor; + std::unique_ptr ExternalInlineAdvisor; // A pseudo probe helper to correlate the imported sample counts. std::unique_ptr ProbeManager; @@ -1272,12 +1283,14 @@ SampleProfileLoader::shouldInlineCandidate(InlineCandidate &Candidate) { std::unique_ptr Advice = nullptr; if (ExternalInlineAdvisor) { Advice = ExternalInlineAdvisor->getAdvice(*Candidate.CallInstr); - if (!Advice->isInliningRecommended()) { - Advice->recordUnattemptedInlining(); - return InlineCost::getNever("not previously inlined"); + if (Advice) { + if (!Advice->isInliningRecommended()) { + Advice->recordUnattemptedInlining(); + return InlineCost::getNever("not previously inlined"); + } + Advice->recordInlining(); + return InlineCost::getAlways("previously inlined"); } - Advice->recordInlining(); - return InlineCost::getAlways("previously inlined"); } // Adjust threshold based on call site hotness, only do this for callsite @@ -1833,11 +1846,9 @@ bool SampleProfileLoader::doInitialization(Module &M, } if (FAM && !ProfileInlineReplayFile.empty()) { - ExternalInlineAdvisor = std::make_unique( + ExternalInlineAdvisor = getReplayInlineAdvisor( M, *FAM, Ctx, /*OriginalAdvisor=*/nullptr, ProfileInlineReplayFile, - /*EmitRemarks=*/false); - if (!ExternalInlineAdvisor->areReplayRemarksLoaded()) - ExternalInlineAdvisor.reset(); + ProfileInlineReplayScope, /*EmitRemarks=*/false); } // Apply tweaks if context-sensitive profile is available. diff --git a/llvm/lib/Transforms/Utils/LoopUtils.cpp b/llvm/lib/Transforms/Utils/LoopUtils.cpp index 5db1a6dc275d175f80823570705ed5175fe31c0c..a034efceaf50894ddf97d3aece53e565440b6be8 100644 --- a/llvm/lib/Transforms/Utils/LoopUtils.cpp +++ b/llvm/lib/Transforms/Utils/LoopUtils.cpp @@ -1565,7 +1565,7 @@ expandBounds(const SmallVectorImpl &PointerChecks, Loop *L, return ChecksWithBounds; } -std::pair llvm::addRuntimeChecks( +Value *llvm::addRuntimeChecks( Instruction *Loc, Loop *TheLoop, const SmallVectorImpl &PointerChecks, SCEVExpander &Exp) { @@ -1574,22 +1574,10 @@ std::pair llvm::addRuntimeChecks( auto ExpandedChecks = expandBounds(PointerChecks, TheLoop, Loc, Exp); LLVMContext &Ctx = Loc->getContext(); - Instruction *FirstInst = nullptr; IRBuilder<> ChkBuilder(Loc); // Our instructions might fold to a constant. Value *MemoryRuntimeCheck = nullptr; - // FIXME: this helper is currently a duplicate of the one in - // LoopVectorize.cpp. - auto GetFirstInst = [](Instruction *FirstInst, Value *V, - Instruction *Loc) -> Instruction * { - if (FirstInst) - return FirstInst; - if (Instruction *I = dyn_cast(V)) - return I->getParent() == Loc->getParent() ? I : nullptr; - return nullptr; - }; - for (const auto &Check : ExpandedChecks) { const PointerBounds &A = Check.first, &B = Check.second; // Check if two pointers (A and B) conflict where conflict is computed as: @@ -1618,30 +1606,16 @@ std::pair llvm::addRuntimeChecks( // bound1 = (A.Start < B.End) // IsConflict = bound0 & bound1 Value *Cmp0 = ChkBuilder.CreateICmpULT(Start0, End1, "bound0"); - FirstInst = GetFirstInst(FirstInst, Cmp0, Loc); Value *Cmp1 = ChkBuilder.CreateICmpULT(Start1, End0, "bound1"); - FirstInst = GetFirstInst(FirstInst, Cmp1, Loc); Value *IsConflict = ChkBuilder.CreateAnd(Cmp0, Cmp1, "found.conflict"); - FirstInst = GetFirstInst(FirstInst, IsConflict, Loc); if (MemoryRuntimeCheck) { IsConflict = ChkBuilder.CreateOr(MemoryRuntimeCheck, IsConflict, "conflict.rdx"); - FirstInst = GetFirstInst(FirstInst, IsConflict, Loc); } MemoryRuntimeCheck = IsConflict; } - if (!MemoryRuntimeCheck) - return std::make_pair(nullptr, nullptr); - - // We have to do this trickery because the IRBuilder might fold the check to a - // constant expression in which case there is no Instruction anchored in a - // the block. - Instruction *Check = - BinaryOperator::CreateAnd(MemoryRuntimeCheck, ConstantInt::getTrue(Ctx)); - ChkBuilder.Insert(Check, "memcheck.conflict"); - FirstInst = GetFirstInst(FirstInst, Check, Loc); - return std::make_pair(FirstInst, Check); + return MemoryRuntimeCheck; } Optional llvm::hasPartialIVCondition(Loop &L, diff --git a/llvm/lib/Transforms/Utils/LoopVersioning.cpp b/llvm/lib/Transforms/Utils/LoopVersioning.cpp index 3498f2926d4f6ab8a59e7490a0ca630bf661cdf7..771b7d25b0f20aa79e72dbc7c9956db816c73ba9 100644 --- a/llvm/lib/Transforms/Utils/LoopVersioning.cpp +++ b/llvm/lib/Transforms/Utils/LoopVersioning.cpp @@ -52,8 +52,7 @@ void LoopVersioning::versionLoop( assert(VersionedLoop->isLoopSimplifyForm() && "Loop is not in loop-simplify form"); - Instruction *FirstCheckInst; - Instruction *MemRuntimeCheck; + Value *MemRuntimeCheck; Value *SCEVRuntimeCheck; Value *RuntimeCheck = nullptr; @@ -64,8 +63,8 @@ void LoopVersioning::versionLoop( SCEVExpander Exp2(*RtPtrChecking.getSE(), VersionedLoop->getHeader()->getModule()->getDataLayout(), "induction"); - std::tie(FirstCheckInst, MemRuntimeCheck) = addRuntimeChecks( - RuntimeCheckBB->getTerminator(), VersionedLoop, AliasChecks, Exp2); + MemRuntimeCheck = addRuntimeChecks(RuntimeCheckBB->getTerminator(), + VersionedLoop, AliasChecks, Exp2); SCEVExpander Exp(*SE, RuntimeCheckBB->getModule()->getDataLayout(), "scev.check"); diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 9d8229fd95bdfa9afc4f894857fe37273ba5b4b6..3bfd62a1a703546949f795b08630d0ec3a5aaf53 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -569,6 +569,7 @@ public: void vectorizeMemoryInstruction(Instruction *Instr, VPTransformState &State, VPValue *Def, VPValue *Addr, VPValue *StoredValue, VPValue *BlockInMask, + bool ConsecutiveStride, bool Reverse, VPValue *EVL); /// Set the debug location in the builder \p Ptr using the debug location in @@ -2058,7 +2059,7 @@ class GeneratedRTChecks { /// The value representing the result of the generated memory runtime checks. /// If it is nullptr, either no memory runtime checks have been generated or /// they have been used. - Instruction *MemRuntimeCheckCond = nullptr; + Value *MemRuntimeCheckCond = nullptr; DominatorTree *DT; LoopInfo *LI; @@ -2101,7 +2102,7 @@ public: MemCheckBlock = SplitBlock(Pred, Pred->getTerminator(), DT, LI, nullptr, "vector.memcheck"); - std::tie(std::ignore, MemRuntimeCheckCond) = + MemRuntimeCheckCond = addRuntimeChecks(MemCheckBlock->getTerminator(), L, RtPtrChecking.getChecks(), MemCheckExp); assert(MemRuntimeCheckCond && @@ -3124,7 +3125,8 @@ InnerLoopVectorizer::computeStrideAddressing(VPTransformState &State, void InnerLoopVectorizer::vectorizeMemoryInstruction( Instruction *Instr, VPTransformState &State, VPValue *Def, VPValue *Addr, - VPValue *StoredValue, VPValue *BlockInMask, VPValue *EVL) { + VPValue *StoredValue, VPValue *BlockInMask, bool ConsecutiveStride, + bool Reverse, VPValue *EVL) { // Attempt to issue a wide load. LoadInst *LI = dyn_cast(Instr); StoreInst *SI = dyn_cast(Instr); @@ -3133,6 +3135,12 @@ void InnerLoopVectorizer::vectorizeMemoryInstruction( assert((!SI || StoredValue) && "No stored value provided for widened store"); assert((!LI || !StoredValue) && "Stored value provided for widened load"); + Type *ScalarDataTy = getLoadStoreType(Instr); + + auto *DataTy = VectorType::get(ScalarDataTy, VF); + const Align Alignment = getLoadStoreAlignment(Instr); + bool CreateGatherScatter = !ConsecutiveStride; + LoopVectorizationCostModel::InstWidening Decision = Cost->getWideningDecision(Instr, VF); assert((Decision == LoopVectorizationCostModel::CM_Widen || @@ -3140,27 +3148,8 @@ void InnerLoopVectorizer::vectorizeMemoryInstruction( Decision == LoopVectorizationCostModel::CM_GatherScatter || Decision == LoopVectorizationCostModel::CM_Strided) && "CM decision is not to widen the memory instruction"); - - Type *ScalarDataTy = getLoadStoreType(Instr); - - auto *DataTy = VectorType::get(ScalarDataTy, VF); - const Align Alignment = getLoadStoreAlignment(Instr); - - // Determine if the pointer operand of the access is either consecutive or - // reverse consecutive. - bool Reverse = (Decision == LoopVectorizationCostModel::CM_Widen_Reverse); - bool ConsecutiveStride = - Reverse || (Decision == LoopVectorizationCostModel::CM_Widen); - bool NonConsecutiveStride = (Decision == LoopVectorizationCostModel::CM_Strided); - bool CreateGatherScatter = - (Decision == LoopVectorizationCostModel::CM_GatherScatter) || - NonConsecutiveStride; - - // Either Ptr feeds a vector load/store, or a vector GEP should feed a vector - // gather/scatter. Otherwise Decision should have been to Scalarize. - assert((ConsecutiveStride || CreateGatherScatter) && - "The instruction should be scalarized"); - (void)ConsecutiveStride; + bool NonUnitStride = + (Decision == LoopVectorizationCostModel::CM_Strided); VectorParts BlockInMaskParts(UF); bool isMaskRequired = BlockInMask; @@ -3236,7 +3225,7 @@ void InnerLoopVectorizer::vectorizeMemoryInstruction( Value *BlockInMaskPart = isMaskRequired ? MaskValue(Part, NumElts) : Builder.getTrueVector(NumElts); - if (NonConsecutiveStride) { + if (NonUnitStride) { LLVM_DEBUG(llvm::dbgs() << "It should be possible to stride this store!\n"); LLVM_DEBUG(llvm::dbgs() << "Addr = " << *Addr << "\n"); @@ -3329,7 +3318,7 @@ void InnerLoopVectorizer::vectorizeMemoryInstruction( Value *BlockInMaskPart = isMaskRequired ? MaskValue(Part, NumElts) : Builder.getTrueVector(NumElts); - if (NonConsecutiveStride) { + if (NonUnitStride) { LLVM_DEBUG(llvm::dbgs() << "It should be possible to stride this load!\n"); LLVM_DEBUG(llvm::dbgs() << "Addr = " << *Addr << "\n"); @@ -9936,12 +9925,21 @@ VPRecipeBase *VPRecipeBuilder::tryToWidenMemory(Instruction *I, if (Legal->isMaskRequired(I)) Mask = createBlockInMask(I->getParent(), Plan); + // Determine if the pointer operand of the access is either consecutive or + // reverse consecutive. + LoopVectorizationCostModel::InstWidening Decision = + CM.getWideningDecision(I, Range.Start); + bool Reverse = Decision == LoopVectorizationCostModel::CM_Widen_Reverse; + bool Consecutive = + Reverse || Decision == LoopVectorizationCostModel::CM_Widen; + if (LoadInst *Load = dyn_cast(I)) - return new VPWidenMemoryInstructionRecipe(*Load, Operands[0], Mask); + return new VPWidenMemoryInstructionRecipe(*Load, Operands[0], Mask, + Consecutive, Reverse); StoreInst *Store = cast(I); return new VPWidenMemoryInstructionRecipe(*Store, Operands[1], Operands[0], - Mask); + Mask, Consecutive, Reverse); } VPRecipeBase * @@ -9951,15 +9949,21 @@ VPRecipeBuilder::tryToPredicatedWidenMemory(Instruction *I, if (!validateWidenMemory(I, Range)) return nullptr; + LoopVectorizationCostModel::InstWidening Decision = + CM.getWideningDecision(I, Range.Start); + bool Reverse = Decision == LoopVectorizationCostModel::CM_Widen_Reverse; + bool Consecutive = + Reverse || Decision == LoopVectorizationCostModel::CM_Widen; + VPValue *Mask = createBlockInMask(I->getParent(), Plan); VPValue *EVL = getOrCreateEVL(Plan); if (LoadInst *Load = dyn_cast(I)) - return new VPPredicatedWidenMemoryInstructionRecipe(*Load, Operands[0], - Mask, EVL); + return new VPPredicatedWidenMemoryInstructionRecipe( + *Load, Operands[0], Mask, Consecutive, Reverse, EVL); StoreInst *Store = cast(I); - return new VPPredicatedWidenMemoryInstructionRecipe(*Store, Operands[1], - Operands[0], Mask, EVL); + return new VPPredicatedWidenMemoryInstructionRecipe( + *Store, Operands[1], Operands[0], Mask, Consecutive, Reverse, EVL); } VPWidenIntOrFpInductionRecipe * @@ -11201,7 +11205,7 @@ void VPWidenMemoryInstructionRecipe::execute(VPTransformState &State) { VPValue *StoredValue = isStore() ? getStoredValue() : nullptr; State.ILV->vectorizeMemoryInstruction( &Ingredient, State, StoredValue ? nullptr : getVPSingleValue(), getAddr(), - StoredValue, getMask(), /* EVL */ nullptr); + StoredValue, getMask(), Consecutive, Reverse, /* EVL */ nullptr); } void VPPredicatedWidenMemoryInstructionRecipe::execute( @@ -11209,7 +11213,7 @@ void VPPredicatedWidenMemoryInstructionRecipe::execute( VPValue *StoredValue = isStore() ? getStoredValue() : nullptr; State.ILV->vectorizeMemoryInstruction( &Ingredient, State, StoredValue ? nullptr : getVPSingleValue(), getAddr(), - StoredValue, getMask(), getEVL()); + StoredValue, getMask(), Consecutive, Reverse, getEVL()); } // Determine how to lower the scalar epilogue, which depends on 1) optimising diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index ac60690d4c3e03fcfc8953df43ccc12ad60efea9..bd59f92a4f88bb3cf210099f20c93c011e3fefe2 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -5671,17 +5671,18 @@ Value *BoUpSLP::vectorizeTree(ArrayRef VL) { // block: // %phi = phi <2 x > { .., %entry} {%shuffle, %block} - // %2 = shuffle <2 x > %phi, %poison, <4 x > <0, 0, 1, 1> + // %2 = shuffle <2 x > %phi, poison, <4 x > <1, 1, 0, 0> // ... (use %2) - // %shuffle = shuffle <2 x> %2, poison, <2 x> {0, 2} + // %shuffle = shuffle <2 x> %2, poison, <2 x> {2, 0} // br %block - SmallVector UniqueIdxs; + SmallVector UniqueIdxs(VF, UndefMaskElem); SmallSet UsedIdxs; int Pos = 0; int Sz = VL.size(); for (int Idx : E->ReuseShuffleIndices) { - if (Idx != Sz && UsedIdxs.insert(Idx).second) - UniqueIdxs.emplace_back(Pos); + if (Idx != Sz && Idx != UndefMaskElem && + UsedIdxs.insert(Idx).second) + UniqueIdxs[Idx] = Pos; ++Pos; } assert(VF >= UsedIdxs.size() && "Expected vectorization factor " diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h index 647f23f4647d64a2689dbe6cd3689e036ea91798..94eb19f16503d2e44d7565ed5f0747132ee1dc79 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -1652,29 +1652,41 @@ class VPWidenMemoryInstructionRecipe : public VPRecipeBase { protected: Instruction &Ingredient; + // Whether the loaded-from / stored-to addresses are consecutive. + bool Consecutive; + + // Whether the consecutive loaded/stored addresses are in reverse order. + bool Reverse; + VPWidenMemoryInstructionRecipe(LoadInst &Load, VPValue *Addr, + bool Consecutive, bool Reverse, const unsigned char RecipeSC, const unsigned char ValueSC) - : VPRecipeBase(RecipeSC, {Addr}), Ingredient(Load) { + : VPRecipeBase(RecipeSC, {Addr}), Ingredient(Load), + Consecutive(Consecutive), Reverse(Reverse) { new VPValue(ValueSC, &Load, this); } VPWidenMemoryInstructionRecipe(StoreInst &Store, VPValue *Addr, - VPValue *StoredValue, - const unsigned char RecipeSC) - : VPRecipeBase(RecipeSC, {Addr, StoredValue}), Ingredient(Store) {} + VPValue *StoredValue, bool Consecutive, + bool Reverse, const unsigned char RecipeSC) + : VPRecipeBase(RecipeSC, {Addr, StoredValue}), Ingredient(Store), + Consecutive(Consecutive), Reverse(Reverse) {} public: - VPWidenMemoryInstructionRecipe(LoadInst &Load, VPValue *Addr, VPValue *Mask) - : VPWidenMemoryInstructionRecipe(Load, Addr, VPWidenMemoryInstructionSC, + VPWidenMemoryInstructionRecipe(LoadInst &Load, VPValue *Addr, VPValue *Mask, + bool Consecutive, bool Reverse) + : VPWidenMemoryInstructionRecipe(Load, Addr, Consecutive, Reverse, + VPWidenMemoryInstructionSC, VPValue::VPVMemoryInstructionSC) { setMask(Mask); } VPWidenMemoryInstructionRecipe(StoreInst &Store, VPValue *Addr, - VPValue *StoredValue, VPValue *Mask) - : VPWidenMemoryInstructionRecipe(Store, Addr, StoredValue, - VPWidenMemoryInstructionSC) { + VPValue *StoredValue, VPValue *Mask, + bool Consecutive, bool Reverse) + : VPWidenMemoryInstructionRecipe(Store, Addr, StoredValue, Consecutive, + Reverse, VPWidenMemoryInstructionSC) { setMask(Mask); } @@ -1704,6 +1716,13 @@ public: return getOperand(1); // Stored value is the 2nd, mandatory operand. } + // Return whether the loaded-from / stored-to addresses are consecutive. + bool isConsecutive() const { return Consecutive; } + + // Return whether the consecutive loaded/stored addresses are in reverse + // order. + bool isReverse() const { return Reverse; } + /// Generate the wide load/store. void execute(VPTransformState &State) override; @@ -1723,9 +1742,11 @@ class VPPredicatedWidenMemoryInstructionRecipe public: VPPredicatedWidenMemoryInstructionRecipe(LoadInst &Load, VPValue *Addr, - VPValue *Mask, VPValue *EVL) + VPValue *Mask, bool Consecutive, + bool Reverse, VPValue *EVL) : VPWidenMemoryInstructionRecipe( - Load, Addr, VPPredicatedWidenMemoryInstructionSC, + Load, Addr, Consecutive, Reverse, + VPPredicatedWidenMemoryInstructionSC, VPValue::VPVPredicatedMemoryInstructionSC) { addOperand(Mask); addOperand(EVL); @@ -1733,8 +1754,10 @@ public: VPPredicatedWidenMemoryInstructionRecipe(StoreInst &Store, VPValue *Addr, VPValue *StoredValue, VPValue *Mask, + bool Consecutive, bool Reverse, VPValue *EVL) - : VPWidenMemoryInstructionRecipe(Store, Addr, StoredValue, + : VPWidenMemoryInstructionRecipe(Store, Addr, StoredValue, Consecutive, + Reverse, VPPredicatedWidenMemoryInstructionSC) { addOperand(Mask); addOperand(EVL); diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp index efad9ae29efe21341dfa54380feaffeb860ca887..ded5bc04beb5bb5d190beb322a74c33a2487e7e0 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp @@ -61,12 +61,12 @@ void VPlanTransforms::VPInstructionsToVPRecipes( if (LoadInst *Load = dyn_cast(Inst)) { NewRecipe = new VPWidenMemoryInstructionRecipe( *Load, Plan->getOrAddVPValue(getLoadStorePointerOperand(Inst)), - nullptr /*Mask*/); + nullptr /*Mask*/, false /*Consecutive*/, false /*Reverse*/); } else if (StoreInst *Store = dyn_cast(Inst)) { NewRecipe = new VPWidenMemoryInstructionRecipe( *Store, Plan->getOrAddVPValue(getLoadStorePointerOperand(Inst)), - Plan->getOrAddVPValue(Store->getValueOperand()), - nullptr /*Mask*/); + Plan->getOrAddVPValue(Store->getValueOperand()), nullptr /*Mask*/, + false /*Consecutive*/, false /*Reverse*/); } else if (GetElementPtrInst *GEP = dyn_cast(Inst)) { NewRecipe = new VPWidenGEPRecipe( GEP, Plan->mapToVPValues(GEP->operands()), OrigLoop); diff --git a/llvm/test/Analysis/StackSafetyAnalysis/i386-bug-fix.ll b/llvm/test/Analysis/StackSafetyAnalysis/i386-bug-fix.ll new file mode 100644 index 0000000000000000000000000000000000000000..b6e65f94d0d1fbf60d48f4336812292e497c941f --- /dev/null +++ b/llvm/test/Analysis/StackSafetyAnalysis/i386-bug-fix.ll @@ -0,0 +1,24 @@ +; REQUIRES: i386-pc-linux-gnu + +; RUN: opt passes="print-stack-safety" -disable-output -mtriple=i386-pc-linux-gnu %s 2>&1 | FileCheck %s --check-prefixes=CHECK + +; CHECK: @main +; CHECK-NEXT: args uses: +; CHECK-NEXT: argv[]: empty-set +; CHECK-NEXT: allocas uses: +; CHECK-NEXT: [4]: [0,4) +; CHECK-NEXT: [32]: full-set +; CHECK-NEXT: safe accesses: + +target datalayout = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-f64:32:64-f80:32-n8:16:32-S128" +target triple = "i386-pc-linux-gnu" + +; Function Attrs: mustprogress norecurse sanitize_address uwtable +define dso_local i32 @main(i32 %argc, i8** %argv) { +entry: + %0 = alloca i32, align 4 + %1 = alloca i8, i64 32, align 32 + %2 = ptrtoint i8* %1 to i32 + store i32 %2, i32* %0, align 4 + ret i32 0 +} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-shr-and.mir b/llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-shr-and.mir new file mode 100644 index 0000000000000000000000000000000000000000..55a75b1d03fda799954bb7896f18f09765ce434a --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-shr-and.mir @@ -0,0 +1,190 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s + +# Check that we can fold a G_ASHR/G_LSHR fed by a G_AND into a G_SBFX/G_UBFX. + +--- +name: mask_extract_unsigned_32 +legalized: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: mask_extract_unsigned_32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY]], [[C]](s32), [[C]] + ; CHECK-NEXT: $w0 = COPY [[UBFX]](s32) + %0:_(s32) = COPY $w0 + %1:_(s32) = G_CONSTANT i32 12 + %2:_(s32) = G_CONSTANT i32 2 + %3:_(s32) = G_AND %0, %1 + %4:_(s32) = G_LSHR %3, %2 + $w0 = COPY %4(s32) +... +--- +name: mask_extract_unsigned_64 +legalized: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: mask_extract_unsigned_64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[UBFX:%[0-9]+]]:_(s64) = G_UBFX [[COPY]], [[C]](s64), [[C1]] + ; CHECK-NEXT: $x0 = COPY [[UBFX]](s64) + %0:_(s64) = COPY $x0 + %1:_(s64) = G_CONSTANT i64 1080863910568919040 + %2:_(s64) = G_CONSTANT i64 56 + %3:_(s64) = G_AND %0, %1 + %4:_(s64) = G_LSHR %3, %2 + $x0 = COPY %4(s64) +... +--- +name: no_mask_extract_unsigned_128 +legalized: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: no_mask_extract_unsigned_128 + ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $q0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 1080863910568919040 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s128) = G_CONSTANT i128 56 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s128) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s128) = G_LSHR [[AND]], [[C1]](s128) + ; CHECK-NEXT: $q0 = COPY [[LSHR]](s128) + %0:_(s128) = COPY $q0 + %1:_(s128) = G_CONSTANT i128 1080863910568919040 + %2:_(s128) = G_CONSTANT i128 56 + %3:_(s128) = G_AND %0, %1 + %4:_(s128) = G_LSHR %3, %2 + $q0 = COPY %4(s128) +... +--- +name: mask_extract_asr +legalized: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: mask_extract_asr + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 29 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY]], [[C]](s32), [[C1]] + ; CHECK-NEXT: $w0 = COPY [[UBFX]](s32) + %0:_(s32) = COPY $w0 + %1:_(s32) = G_CONSTANT i32 1610612736 + %2:_(s32) = G_CONSTANT i32 29 + %3:_(s32) = G_AND %0, %1 + %4:_(s32) = G_ASHR %3, %2 + $w0 = COPY %4(s32) +... +--- +name: no_mask_extract_asr +legalized: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: no_mask_extract_asr + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1073741824 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 30 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[AND]], [[C1]](s32) + ; CHECK-NEXT: $w0 = COPY [[ASHR]](s32) + %0:_(s32) = COPY $w0 + %1:_(s32) = G_CONSTANT i32 3221225472 + %2:_(s32) = G_CONSTANT i32 30 + %3:_(s32) = G_AND %0, %1 + %4:_(s32) = G_ASHR %3, %2 + $w0 = COPY %4(s32) +... +--- +name: mask_extract_signed_nonneg +legalized: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: mask_extract_signed_nonneg + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 29 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY]], [[C]](s32), [[C1]] + ; CHECK-NEXT: $w0 = COPY [[UBFX]](s32) + %0:_(s32) = COPY $w0 + %1:_(s32) = G_CONSTANT i32 2147483647 + %2:_(s32) = G_CONSTANT i32 29 + %3:_(s32) = G_AND %0, %1 + %4:_(s32) = G_ASHR %3, %2 + $w0 = COPY %4(s32) +... +--- +name: no_mask_extract_large_shift +legalized: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: no_mask_extract_large_shift + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32) + ; CHECK-NEXT: $w0 = COPY [[LSHR]](s32) + %0:_(s32) = COPY $w0 + %1:_(s32) = G_CONSTANT i32 12 + %2:_(s32) = G_CONSTANT i32 33 + %3:_(s32) = G_AND %0, %1 + %4:_(s32) = G_LSHR %3, %2 + $w0 = COPY %4(s32) +... +--- +name: no_mask_extract_negative_shift +legalized: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: no_mask_extract_negative_shift + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32) + ; CHECK-NEXT: $w0 = COPY [[LSHR]](s32) + %0:_(s32) = COPY $w0 + %1:_(s32) = G_CONSTANT i32 12 + %2:_(s32) = G_CONSTANT i32 -1 + %3:_(s32) = G_AND %0, %1 + %4:_(s32) = G_LSHR %3, %2 + $w0 = COPY %4(s32) +... +--- +name: no_mask_extract_disjoint +legalized: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: no_mask_extract_disjoint + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 26 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32) + ; CHECK-NEXT: $w0 = COPY [[LSHR]](s32) + %0:_(s32) = COPY $w0 + %1:_(s32) = G_CONSTANT i32 26 + %2:_(s32) = G_CONSTANT i32 1 + %3:_(s32) = G_AND %0, %1 + %4:_(s32) = G_LSHR %3, %2 + $w0 = COPY %4(s32) +... +--- +name: no_mask_extract_extra_bits +legalized: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: no_mask_extract_extra_bits + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32) + ; CHECK-NEXT: $w0 = COPY [[LSHR]](s32) + %0:_(s32) = COPY $w0 + %1:_(s32) = G_CONSTANT i32 25 + %2:_(s32) = G_CONSTANT i32 2 + %3:_(s32) = G_AND %0, %1 + %4:_(s32) = G_LSHR %3, %2 + $w0 = COPY %4(s32) +... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/merge-stores-truncating.ll b/llvm/test/CodeGen/AArch64/GlobalISel/merge-stores-truncating.ll index 8c05f36722f275a9a0fc7745120fc74c084115e0..80e7ab94575f888589cc2ec04b85aadffe86d0ef 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/merge-stores-truncating.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/merge-stores-truncating.ll @@ -277,9 +277,8 @@ define dso_local i32 @load_between_stores(i32 %x, i16* %p, i32 *%ptr) { define dso_local void @invalid_shift(i16 %x, i8* %p) { ; CHECK-LABEL: invalid_shift: ; CHECK: ; %bb.0: -; CHECK-NEXT: and w8, w0, #0xffff +; CHECK-NEXT: ubfx w8, w0, #4, #12 ; CHECK-NEXT: strb w0, [x1] -; CHECK-NEXT: lsr w8, w8, #4 ; CHECK-NEXT: strb w8, [x1, #1] ; CHECK-NEXT: ret %t1 = trunc i16 %x to i8 @@ -316,9 +315,8 @@ define dso_local void @missing_store(i32 %x, i8* %p) { define dso_local void @different_base_reg(i16 %x, i8* %p, i8 *%p2) { ; CHECK-LABEL: different_base_reg: ; CHECK: ; %bb.0: -; CHECK-NEXT: and w8, w0, #0xffff +; CHECK-NEXT: ubfx w8, w0, #8, #8 ; CHECK-NEXT: strb w0, [x1] -; CHECK-NEXT: lsr w8, w8, #8 ; CHECK-NEXT: strb w8, [x2, #1] ; CHECK-NEXT: ret %t1 = trunc i16 %x to i8 @@ -333,9 +331,8 @@ define dso_local void @different_base_reg(i16 %x, i8* %p, i8 *%p2) { define dso_local void @second_store_is_volatile(i16 %x, i8* %p) { ; CHECK-LABEL: second_store_is_volatile: ; CHECK: ; %bb.0: -; CHECK-NEXT: and w8, w0, #0xffff +; CHECK-NEXT: ubfx w8, w0, #8, #8 ; CHECK-NEXT: strb w0, [x1] -; CHECK-NEXT: lsr w8, w8, #8 ; CHECK-NEXT: strb w8, [x1, #1] ; CHECK-NEXT: ret %t1 = trunc i16 %x to i8 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll index 3e70221e1a6902717f4fbdc28796ce7a22d1978f..1a18d7f138cd69f86c70625fabaca5846ccbd91a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll @@ -392,8 +392,7 @@ define amdgpu_ps i16 @s_bswap_i16(i16 inreg %src) { ; GFX7-LABEL: s_bswap_i16: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_lshl_b32 s1, s0, 8 -; GFX7-NEXT: s_and_b32 s0, s0, 0xffff -; GFX7-NEXT: s_lshr_b32 s0, s0, 8 +; GFX7-NEXT: s_bfe_u32 s0, s0, 0x80008 ; GFX7-NEXT: s_or_b32 s0, s0, s1 ; GFX7-NEXT: ; return to shader part epilog ; @@ -427,8 +426,7 @@ define i16 @v_bswap_i16(i16 %src) { ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v0 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 8, v0 +; GFX7-NEXT: v_bfe_u32 v0, v0, 8, 8 ; GFX7-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; @@ -459,14 +457,12 @@ define i16 @v_bswap_i16(i16 %src) { define amdgpu_ps i32 @s_bswap_v2i16(<2 x i16> inreg %src) { ; GFX7-LABEL: s_bswap_v2i16: ; GFX7: ; %bb.0: -; GFX7-NEXT: s_mov_b32 s3, 0xffff +; GFX7-NEXT: s_mov_b32 s3, 0x80008 ; GFX7-NEXT: s_lshl_b32 s2, s0, 8 -; GFX7-NEXT: s_and_b32 s0, s0, s3 -; GFX7-NEXT: s_lshr_b32 s0, s0, 8 +; GFX7-NEXT: s_bfe_u32 s0, s0, s3 ; GFX7-NEXT: s_or_b32 s0, s0, s2 ; GFX7-NEXT: s_lshl_b32 s2, s1, 8 -; GFX7-NEXT: s_and_b32 s1, s1, s3 -; GFX7-NEXT: s_lshr_b32 s1, s1, 8 +; GFX7-NEXT: s_bfe_u32 s1, s1, s3 ; GFX7-NEXT: s_or_b32 s1, s1, s2 ; GFX7-NEXT: s_bfe_u32 s1, s1, 0x100000 ; GFX7-NEXT: s_bfe_u32 s0, s0, 0x100000 @@ -505,8 +501,7 @@ define i32 @v_bswap_i16_zext_to_i32(i16 %src) { ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v0 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 8, v0 +; GFX7-NEXT: v_bfe_u32 v0, v0, 8, 8 ; GFX7-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX7-NEXT: v_bfe_u32 v0, v0, 0, 16 ; GFX7-NEXT: s_setpc_b64 s[30:31] @@ -541,8 +536,7 @@ define i32 @v_bswap_i16_sext_to_i32(i16 %src) { ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v0 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 8, v0 +; GFX7-NEXT: v_bfe_u32 v0, v0, 8, 8 ; GFX7-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX7-NEXT: v_bfe_i32 v0, v0, 0, 16 ; GFX7-NEXT: s_setpc_b64 s[30:31] @@ -579,14 +573,11 @@ define <2 x i16> @v_bswap_v2i16(<2 x i16> %src) { ; GFX7-LABEL: v_bswap_v2i16: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: s_mov_b32 s4, 0xffff ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 8, v0 -; GFX7-NEXT: v_and_b32_e32 v0, s4, v0 -; GFX7-NEXT: v_lshrrev_b32_e32 v0, 8, v0 +; GFX7-NEXT: v_bfe_u32 v0, v0, 8, 8 ; GFX7-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX7-NEXT: v_lshlrev_b32_e32 v2, 8, v1 -; GFX7-NEXT: v_and_b32_e32 v1, s4, v1 -; GFX7-NEXT: v_lshrrev_b32_e32 v1, 8, v1 +; GFX7-NEXT: v_bfe_u32 v1, v1, 8, 8 ; GFX7-NEXT: v_or_b32_e32 v1, v1, v2 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll index 8ec1cc5a8fa32df99c497e15749a8c687e62ad7f..d0aec6ca18531cdcef56792a848e14e2e72500e2 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll @@ -687,8 +687,8 @@ define amdgpu_kernel void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias ; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b64 s[6:7], s[2:3] ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v0, 0xff00, v0 -; SI-NEXT: v_cvt_f32_ubyte1_e32 v0, v0 +; SI-NEXT: v_bfe_u32 v0, v0, 8, 8 +; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: s_endpgm ; @@ -704,8 +704,7 @@ define amdgpu_kernel void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_and_b32_e32 v0, 0xff00, v0 -; VI-NEXT: v_cvt_f32_ubyte1_e32 v2, v0 +; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 ; VI-NEXT: v_mov_b32_e32 v0, s2 ; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: flat_store_dword v[0:1], v2 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll index eea38ac3b061f9aa734e344fb5ca8a3a618b7770..3db1fa678de42c36eba6729ad6b7d8dce194ffce 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll @@ -11,10 +11,9 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) { ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX6-NEXT: s_movk_i32 s3, 0x7f ; GFX6-NEXT: s_and_b32 s2, s2, s3 -; GFX6-NEXT: s_and_b32 s1, s1, s3 +; GFX6-NEXT: s_bfe_u32 s1, s1, 0x60001 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX6-NEXT: s_lshr_b32 s1, s1, 1 ; GFX6-NEXT: v_mul_lo_u32 v1, -7, v0 ; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 @@ -142,6 +141,7 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) { ; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v3, 7 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; GFX6-NEXT: v_and_b32_e32 v2, 0x7f, v2 +; GFX6-NEXT: v_bfe_u32 v1, v1, 1, 6 ; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX6-NEXT: v_mul_lo_u32 v4, -7, v3 @@ -149,8 +149,6 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) { ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3 ; GFX6-NEXT: v_mov_b32_e32 v4, 0x7f -; GFX6-NEXT: v_and_b32_e32 v1, v1, v4 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1 ; GFX6-NEXT: v_mul_lo_u32 v3, v3, 7 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 7, v2 @@ -267,10 +265,9 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) { define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) { ; GFX6-LABEL: s_fshl_i8: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_and_b32 s1, s1, 0xff ; GFX6-NEXT: s_and_b32 s3, s2, 7 ; GFX6-NEXT: s_andn2_b32 s2, 7, s2 -; GFX6-NEXT: s_lshr_b32 s1, s1, 1 +; GFX6-NEXT: s_bfe_u32 s1, s1, 0x70001 ; GFX6-NEXT: s_lshl_b32 s0, s0, s3 ; GFX6-NEXT: s_lshr_b32 s1, s1, s2 ; GFX6-NEXT: s_or_b32 s0, s0, s1 @@ -321,9 +318,8 @@ define i8 @v_fshl_i8(i8 %lhs, i8 %rhs, i8 %amt) { ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: v_and_b32_e32 v3, 7, v2 ; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2 -; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1 ; GFX6-NEXT: v_and_b32_e32 v2, 7, v2 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1 +; GFX6-NEXT: v_bfe_u32 v1, v1, 1, 7 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, v3, v0 ; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 @@ -375,9 +371,8 @@ define i8 @v_fshl_i8(i8 %lhs, i8 %rhs, i8 %amt) { define amdgpu_ps i8 @s_fshl_i8_4(i8 inreg %lhs, i8 inreg %rhs) { ; GFX6-LABEL: s_fshl_i8_4: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_and_b32 s1, s1, 0xff ; GFX6-NEXT: s_lshl_b32 s0, s0, 4 -; GFX6-NEXT: s_lshr_b32 s1, s1, 4 +; GFX6-NEXT: s_bfe_u32 s1, s1, 0x40004 ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: ; return to shader part epilog ; @@ -415,9 +410,8 @@ define i8 @v_fshl_i8_4(i8 %lhs, i8 %rhs) { ; GFX6-LABEL: v_fshl_i8_4: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 4, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 4, v1 +; GFX6-NEXT: v_bfe_u32 v1, v1, 4, 4 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; @@ -455,9 +449,8 @@ define i8 @v_fshl_i8_4(i8 %lhs, i8 %rhs) { define amdgpu_ps i8 @s_fshl_i8_5(i8 inreg %lhs, i8 inreg %rhs) { ; GFX6-LABEL: s_fshl_i8_5: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_and_b32 s1, s1, 0xff ; GFX6-NEXT: s_lshl_b32 s0, s0, 5 -; GFX6-NEXT: s_lshr_b32 s1, s1, 3 +; GFX6-NEXT: s_bfe_u32 s1, s1, 0x50003 ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: ; return to shader part epilog ; @@ -495,9 +488,8 @@ define i8 @v_fshl_i8_5(i8 %lhs, i8 %rhs) { ; GFX6-LABEL: v_fshl_i8_5: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 5, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 3, v1 +; GFX6-NEXT: v_bfe_u32 v1, v1, 3, 5 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; @@ -536,13 +528,11 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in ; GFX6-LABEL: s_fshl_v2i8: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_and_b32 s5, s2, 7 -; GFX6-NEXT: s_movk_i32 s6, 0xff ; GFX6-NEXT: s_lshr_b32 s3, s0, 8 -; GFX6-NEXT: s_lshl_b32 s0, s0, s5 -; GFX6-NEXT: s_and_b32 s5, s1, s6 ; GFX6-NEXT: s_lshr_b32 s4, s2, 8 ; GFX6-NEXT: s_andn2_b32 s2, 7, s2 -; GFX6-NEXT: s_lshr_b32 s5, s5, 1 +; GFX6-NEXT: s_lshl_b32 s0, s0, s5 +; GFX6-NEXT: s_bfe_u32 s5, s1, 0x70001 ; GFX6-NEXT: s_lshr_b32 s2, s5, s2 ; GFX6-NEXT: s_bfe_u32 s1, s1, 0x80008 ; GFX6-NEXT: s_or_b32 s0, s0, s2 @@ -551,6 +541,7 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in ; GFX6-NEXT: s_lshr_b32 s1, s1, 1 ; GFX6-NEXT: s_lshl_b32 s2, s3, s2 ; GFX6-NEXT: s_lshr_b32 s1, s1, s4 +; GFX6-NEXT: s_movk_i32 s6, 0xff ; GFX6-NEXT: s_or_b32 s1, s2, s1 ; GFX6-NEXT: s_and_b32 s1, s1, s6 ; GFX6-NEXT: s_and_b32 s0, s0, s6 @@ -656,15 +647,13 @@ define i16 @v_fshl_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) { ; GFX6-LABEL: v_fshl_v2i8: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_and_b32_e32 v5, 7, v2 -; GFX6-NEXT: s_movk_i32 s4, 0xff -; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v0 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, 8, v2 +; GFX6-NEXT: v_and_b32_e32 v5, 7, v2 ; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2 -; GFX6-NEXT: v_lshlrev_b32_e32 v0, v5, v0 -; GFX6-NEXT: v_and_b32_e32 v5, s4, v1 +; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v0 ; GFX6-NEXT: v_and_b32_e32 v2, 7, v2 -; GFX6-NEXT: v_lshrrev_b32_e32 v5, 1, v5 +; GFX6-NEXT: v_lshlrev_b32_e32 v0, v5, v0 +; GFX6-NEXT: v_bfe_u32 v5, v1, 1, 7 ; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v5 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX6-NEXT: v_and_b32_e32 v2, 7, v4 @@ -675,8 +664,9 @@ define i16 @v_fshl_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) { ; GFX6-NEXT: v_lshlrev_b32_e32 v2, v2, v3 ; GFX6-NEXT: v_lshrrev_b32_e32 v1, v4, v1 ; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 -; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 -; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0 +; GFX6-NEXT: v_mov_b32_e32 v2, 0xff +; GFX6-NEXT: v_and_b32_e32 v1, v1, v2 +; GFX6-NEXT: v_and_b32_e32 v0, v0, v2 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] @@ -772,17 +762,15 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in ; GFX6-LABEL: s_fshl_v4i8: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_and_b32 s9, s2, 7 -; GFX6-NEXT: s_movk_i32 s10, 0xff ; GFX6-NEXT: s_lshr_b32 s3, s0, 8 ; GFX6-NEXT: s_lshr_b32 s4, s0, 16 ; GFX6-NEXT: s_lshr_b32 s5, s0, 24 -; GFX6-NEXT: s_lshl_b32 s0, s0, s9 -; GFX6-NEXT: s_and_b32 s9, s1, s10 ; GFX6-NEXT: s_lshr_b32 s6, s2, 8 ; GFX6-NEXT: s_lshr_b32 s7, s2, 16 ; GFX6-NEXT: s_lshr_b32 s8, s2, 24 ; GFX6-NEXT: s_andn2_b32 s2, 7, s2 -; GFX6-NEXT: s_lshr_b32 s9, s9, 1 +; GFX6-NEXT: s_lshl_b32 s0, s0, s9 +; GFX6-NEXT: s_bfe_u32 s9, s1, 0x70001 ; GFX6-NEXT: s_lshr_b32 s2, s9, s2 ; GFX6-NEXT: s_or_b32 s0, s0, s2 ; GFX6-NEXT: s_and_b32 s2, s6, 7 @@ -797,6 +785,7 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in ; GFX6-NEXT: s_bfe_u32 s4, s1, 0x80010 ; GFX6-NEXT: s_andn2_b32 s6, 7, s7 ; GFX6-NEXT: s_lshr_b32 s4, s4, 1 +; GFX6-NEXT: s_movk_i32 s10, 0xff ; GFX6-NEXT: s_lshr_b32 s4, s4, s6 ; GFX6-NEXT: s_or_b32 s3, s3, s4 ; GFX6-NEXT: s_and_b32 s4, s8, 7 @@ -995,14 +984,13 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) { ; GFX6-NEXT: v_lshrrev_b32_e32 v8, 24, v2 ; GFX6-NEXT: v_and_b32_e32 v9, 7, v2 ; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2 -; GFX6-NEXT: v_and_b32_e32 v10, 0xff, v1 -; GFX6-NEXT: v_and_b32_e32 v2, 7, v2 -; GFX6-NEXT: v_lshrrev_b32_e32 v10, 1, v10 ; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v0 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v0 ; GFX6-NEXT: v_lshrrev_b32_e32 v5, 24, v0 +; GFX6-NEXT: v_and_b32_e32 v2, 7, v2 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, v9, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v10 +; GFX6-NEXT: v_bfe_u32 v9, v1, 1, 7 +; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v9 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX6-NEXT: v_and_b32_e32 v2, 7, v6 ; GFX6-NEXT: v_xor_b32_e32 v6, -1, v6 @@ -1018,23 +1006,23 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) { ; GFX6-NEXT: v_bfe_u32 v4, v1, 16, 8 ; GFX6-NEXT: v_and_b32_e32 v6, 7, v6 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4 -; GFX6-NEXT: v_mov_b32_e32 v9, 0xff +; GFX6-NEXT: s_movk_i32 s4, 0xff ; GFX6-NEXT: v_lshrrev_b32_e32 v4, v6, v4 ; GFX6-NEXT: v_xor_b32_e32 v6, -1, v8 ; GFX6-NEXT: v_or_b32_e32 v3, v3, v4 ; GFX6-NEXT: v_and_b32_e32 v4, 7, v8 ; GFX6-NEXT: v_and_b32_e32 v6, 7, v6 ; GFX6-NEXT: v_lshrrev_b32_e32 v1, 25, v1 -; GFX6-NEXT: v_and_b32_e32 v2, v2, v9 +; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 ; GFX6-NEXT: v_lshlrev_b32_e32 v4, v4, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v1, v6, v1 -; GFX6-NEXT: v_and_b32_e32 v0, v0, v9 +; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 8, v2 ; GFX6-NEXT: v_or_b32_e32 v1, v4, v1 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 -; GFX6-NEXT: v_and_b32_e32 v2, v3, v9 +; GFX6-NEXT: v_and_b32_e32 v2, s4, v3 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX6-NEXT: v_and_b32_e32 v1, v1, v9 +; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 @@ -1215,8 +1203,7 @@ define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt) ; GFX6-NEXT: s_and_b32 s2, s2, s3 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX6-NEXT: s_and_b32 s1, s1, s3 -; GFX6-NEXT: s_lshr_b32 s1, s1, 1 +; GFX6-NEXT: s_bfe_u32 s1, s1, 0x170001 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, v0 ; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 @@ -1247,8 +1234,7 @@ define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt) ; GFX8-NEXT: s_and_b32 s2, s2, s3 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX8-NEXT: s_and_b32 s1, s1, s3 -; GFX8-NEXT: s_lshr_b32 s1, s1, 1 +; GFX8-NEXT: s_bfe_u32 s1, s1, 0x170001 ; GFX8-NEXT: v_mul_lo_u32 v1, v1, v0 ; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1 @@ -1279,8 +1265,7 @@ define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt) ; GFX9-NEXT: s_and_b32 s2, s2, s3 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX9-NEXT: s_and_b32 s1, s1, s3 -; GFX9-NEXT: s_lshr_b32 s1, s1, 1 +; GFX9-NEXT: s_bfe_u32 s1, s1, 0x170001 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, v0 ; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 @@ -1305,10 +1290,9 @@ define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt) ; GFX10: ; %bb.0: ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24 ; GFX10-NEXT: s_mov_b32 s3, 0xffffff +; GFX10-NEXT: s_bfe_u32 s1, s1, 0x170001 ; GFX10-NEXT: s_and_b32 s2, s2, s3 -; GFX10-NEXT: s_and_b32 s1, s1, s3 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 -; GFX10-NEXT: s_lshr_b32 s1, s1, 1 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_mul_lo_u32 v1, 0xffffffe8, v0 @@ -1342,6 +1326,7 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) { ; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffffe8 ; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2 +; GFX6-NEXT: v_bfe_u32 v1, v1, 1, 23 ; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX6-NEXT: v_mul_lo_u32 v4, v4, v3 @@ -1349,8 +1334,6 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) { ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3 ; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffff -; GFX6-NEXT: v_and_b32_e32 v1, v1, v4 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1 ; GFX6-NEXT: v_mul_lo_u32 v3, v3, 24 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v2 @@ -1374,6 +1357,7 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) { ; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffffe8 ; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2 +; GFX8-NEXT: v_bfe_u32 v1, v1, 1, 23 ; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX8-NEXT: v_mul_lo_u32 v4, v4, v3 @@ -1381,8 +1365,6 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) { ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v4 ; GFX8-NEXT: v_mul_hi_u32 v3, v2, v3 ; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffff -; GFX8-NEXT: v_and_b32_e32 v1, v1, v4 -; GFX8-NEXT: v_lshrrev_b32_e32 v1, 1, v1 ; GFX8-NEXT: v_mul_lo_u32 v3, v3, 24 ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v3 ; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v2 @@ -1406,6 +1388,7 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) { ; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; GFX9-NEXT: v_mov_b32_e32 v4, 0xffffffe8 ; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2 +; GFX9-NEXT: v_bfe_u32 v1, v1, 1, 23 ; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX9-NEXT: v_mul_lo_u32 v4, v4, v3 @@ -1413,8 +1396,6 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) { ; GFX9-NEXT: v_add_u32_e32 v3, v3, v4 ; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3 ; GFX9-NEXT: v_mov_b32_e32 v4, 0xffffff -; GFX9-NEXT: v_and_b32_e32 v1, v1, v4 -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 1, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, v3, 24 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v3 ; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v2 @@ -1436,16 +1417,14 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) { ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, 24 ; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2 +; GFX10-NEXT: v_bfe_u32 v1, v1, 1, 23 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 ; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX10-NEXT: v_mul_lo_u32 v4, 0xffffffe8, v3 ; GFX10-NEXT: v_mul_hi_u32 v4, v3, v4 ; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v4 -; GFX10-NEXT: v_mov_b32_e32 v4, 0xffffff ; GFX10-NEXT: v_mul_hi_u32 v3, v2, v3 -; GFX10-NEXT: v_and_b32_e32 v1, v1, v4 -; GFX10-NEXT: v_lshrrev_b32_e32 v1, 1, v1 ; GFX10-NEXT: v_mul_lo_u32 v3, v3, 24 ; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v3 ; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v2 @@ -1454,10 +1433,11 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) { ; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v2 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo -; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v2 -; GFX10-NEXT: v_and_b32_e32 v2, v2, v4 -; GFX10-NEXT: v_and_b32_e32 v3, v3, v4 -; GFX10-NEXT: v_lshrrev_b32_e32 v1, v3, v1 +; GFX10-NEXT: v_mov_b32_e32 v3, 0xffffff +; GFX10-NEXT: v_sub_nc_u32_e32 v4, 23, v2 +; GFX10-NEXT: v_and_b32_e32 v2, v2, v3 +; GFX10-NEXT: v_and_b32_e32 v4, v4, v3 +; GFX10-NEXT: v_lshrrev_b32_e32 v1, v4, v1 ; GFX10-NEXT: v_lshl_or_b32 v0, v0, v2, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i24 @llvm.fshl.i24(i24 %lhs, i24 %rhs, i24 %amt) @@ -1998,41 +1978,40 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) { ; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v6, 24 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v6 ; GFX6-NEXT: v_mov_b32_e32 v7, 0xffffffe8 -; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4 ; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v9, 24 +; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4 ; GFX6-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6 ; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6 +; GFX6-NEXT: v_bfe_u32 v2, v2, 1, 23 ; GFX6-NEXT: v_mul_lo_u32 v8, v7, v6 ; GFX6-NEXT: v_mul_hi_u32 v8, v6, v8 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; GFX6-NEXT: v_mul_hi_u32 v6, v4, v6 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v8, v9 +; GFX6-NEXT: v_mul_hi_u32 v6, v4, v6 ; GFX6-NEXT: v_mov_b32_e32 v9, 0xffffff -; GFX6-NEXT: v_and_b32_e32 v2, v2, v9 -; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24 +; GFX6-NEXT: v_and_b32_e32 v5, v5, v9 ; GFX6-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8 ; GFX6-NEXT: v_cvt_u32_f32_e32 v8, v8 -; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2 +; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24 +; GFX6-NEXT: v_mul_lo_u32 v7, v7, v8 ; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6 ; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4 +; GFX6-NEXT: v_mul_hi_u32 v7, v8, v7 ; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4 ; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc -; GFX6-NEXT: v_mul_lo_u32 v6, v7, v8 -; GFX6-NEXT: v_sub_i32_e32 v7, vcc, 23, v4 +; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GFX6-NEXT: v_mul_hi_u32 v7, v5, v7 +; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 23, v4 ; GFX6-NEXT: v_and_b32_e32 v4, v4, v9 -; GFX6-NEXT: v_mul_hi_u32 v6, v8, v6 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, v4, v0 -; GFX6-NEXT: v_and_b32_e32 v4, v5, v9 -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v6 -; GFX6-NEXT: v_mul_hi_u32 v5, v4, v5 -; GFX6-NEXT: v_and_b32_e32 v6, v7, v9 -; GFX6-NEXT: v_lshrrev_b32_e32 v2, v6, v2 +; GFX6-NEXT: v_and_b32_e32 v4, v6, v9 +; GFX6-NEXT: v_mul_lo_u32 v6, v7, 24 +; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 -; GFX6-NEXT: v_mul_lo_u32 v5, v5, 24 -; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v4, v5 +; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v5, v6 ; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 24, v2 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc @@ -2042,8 +2021,7 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) { ; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 23, v2 ; GFX6-NEXT: v_and_b32_e32 v2, v2, v9 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, v2, v1 -; GFX6-NEXT: v_and_b32_e32 v2, v3, v9 -; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2 +; GFX6-NEXT: v_bfe_u32 v2, v3, 1, 23 ; GFX6-NEXT: v_and_b32_e32 v3, v4, v9 ; GFX6-NEXT: v_lshrrev_b32_e32 v2, v3, v2 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 @@ -2055,41 +2033,40 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) { ; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v6, 24 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6 ; GFX8-NEXT: v_mov_b32_e32 v7, 0xffffffe8 -; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4 ; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v9, 24 +; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4 ; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6 ; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6 +; GFX8-NEXT: v_bfe_u32 v2, v2, 1, 23 ; GFX8-NEXT: v_mul_lo_u32 v8, v7, v6 ; GFX8-NEXT: v_mul_hi_u32 v8, v6, v8 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8 -; GFX8-NEXT: v_mul_hi_u32 v6, v4, v6 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v8, v9 +; GFX8-NEXT: v_mul_hi_u32 v6, v4, v6 ; GFX8-NEXT: v_mov_b32_e32 v9, 0xffffff -; GFX8-NEXT: v_and_b32_e32 v2, v2, v9 -; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24 +; GFX8-NEXT: v_and_b32_e32 v5, v5, v9 ; GFX8-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8 ; GFX8-NEXT: v_cvt_u32_f32_e32 v8, v8 -; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v2 +; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24 +; GFX8-NEXT: v_mul_lo_u32 v7, v7, v8 ; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v6 ; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4 +; GFX8-NEXT: v_mul_hi_u32 v7, v8, v7 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc -; GFX8-NEXT: v_mul_lo_u32 v6, v7, v8 -; GFX8-NEXT: v_sub_u32_e32 v7, vcc, 23, v4 +; GFX8-NEXT: v_add_u32_e32 v7, vcc, v8, v7 +; GFX8-NEXT: v_mul_hi_u32 v7, v5, v7 +; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 23, v4 ; GFX8-NEXT: v_and_b32_e32 v4, v4, v9 -; GFX8-NEXT: v_mul_hi_u32 v6, v8, v6 ; GFX8-NEXT: v_lshlrev_b32_e32 v0, v4, v0 -; GFX8-NEXT: v_and_b32_e32 v4, v5, v9 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v8, v6 -; GFX8-NEXT: v_mul_hi_u32 v5, v4, v5 -; GFX8-NEXT: v_and_b32_e32 v6, v7, v9 -; GFX8-NEXT: v_lshrrev_b32_e32 v2, v6, v2 +; GFX8-NEXT: v_and_b32_e32 v4, v6, v9 +; GFX8-NEXT: v_mul_lo_u32 v6, v7, 24 +; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v2 -; GFX8-NEXT: v_mul_lo_u32 v5, v5, 24 -; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v4, v5 +; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v5, v6 ; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 24, v2 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc @@ -2099,8 +2076,7 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) { ; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 23, v2 ; GFX8-NEXT: v_and_b32_e32 v2, v2, v9 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, v2, v1 -; GFX8-NEXT: v_and_b32_e32 v2, v3, v9 -; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v2 +; GFX8-NEXT: v_bfe_u32 v2, v3, 1, 23 ; GFX8-NEXT: v_and_b32_e32 v3, v4, v9 ; GFX8-NEXT: v_lshrrev_b32_e32 v2, v3, v2 ; GFX8-NEXT: v_or_b32_e32 v1, v1, v2 @@ -2118,7 +2094,9 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) { ; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4 ; GFX9-NEXT: v_mul_f32_e32 v9, 0x4f7ffffe, v9 +; GFX9-NEXT: v_bfe_u32 v2, v2, 1, 23 ; GFX9-NEXT: v_mul_lo_u32 v8, v7, v6 +; GFX9-NEXT: v_bfe_u32 v3, v3, 1, 23 ; GFX9-NEXT: v_mul_hi_u32 v8, v6, v8 ; GFX9-NEXT: v_add_u32_e32 v6, v6, v8 ; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v9 @@ -2127,25 +2105,23 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) { ; GFX9-NEXT: v_and_b32_e32 v5, v5, v9 ; GFX9-NEXT: v_mul_lo_u32 v7, v7, v8 ; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24 -; GFX9-NEXT: v_and_b32_e32 v2, v2, v9 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, v8, v7 ; GFX9-NEXT: v_sub_u32_e32 v4, v4, v6 ; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4 -; GFX9-NEXT: v_add_u32_e32 v7, v8, v7 -; GFX9-NEXT: v_mul_hi_u32 v7, v5, v7 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc -; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24 -; GFX9-NEXT: v_sub_u32_e32 v6, 23, v4 -; GFX9-NEXT: v_and_b32_e32 v6, v6, v9 +; GFX9-NEXT: v_add_u32_e32 v6, v8, v7 +; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6 +; GFX9-NEXT: v_sub_u32_e32 v7, 23, v4 +; GFX9-NEXT: v_and_b32_e32 v7, v7, v9 ; GFX9-NEXT: v_and_b32_e32 v4, v4, v9 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, v6, v2 +; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24 +; GFX9-NEXT: v_lshrrev_b32_e32 v2, v7, v2 ; GFX9-NEXT: v_lshl_or_b32 v0, v0, v4, v2 -; GFX9-NEXT: v_sub_u32_e32 v2, v5, v7 +; GFX9-NEXT: v_sub_u32_e32 v2, v5, v6 ; GFX9-NEXT: v_subrev_u32_e32 v4, 24, v2 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc @@ -2153,8 +2129,6 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) { ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_sub_u32_e32 v4, 23, v2 -; GFX9-NEXT: v_and_b32_e32 v3, v3, v9 -; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v3 ; GFX9-NEXT: v_and_b32_e32 v4, v4, v9 ; GFX9-NEXT: v_and_b32_e32 v2, v2, v9 ; GFX9-NEXT: v_lshrrev_b32_e32 v3, v4, v3 @@ -2169,13 +2143,11 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) { ; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v7, 24 ; GFX10-NEXT: v_mov_b32_e32 v10, 0xffffff ; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4 +; GFX10-NEXT: v_bfe_u32 v2, v2, 1, 23 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v7, v7 ; GFX10-NEXT: v_and_b32_e32 v5, v5, v10 -; GFX10-NEXT: v_and_b32_e32 v2, v2, v10 -; GFX10-NEXT: v_and_b32_e32 v3, v3, v10 -; GFX10-NEXT: v_lshrrev_b32_e32 v2, 1, v2 -; GFX10-NEXT: v_lshrrev_b32_e32 v3, 1, v3 +; GFX10-NEXT: v_bfe_u32 v3, v3, 1, 23 ; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6 ; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7 ; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6 @@ -2773,9 +2745,8 @@ define amdgpu_ps i16 @s_fshl_i16(i16 inreg %lhs, i16 inreg %rhs, i16 inreg %amt) ; GFX6: ; %bb.0: ; GFX6-NEXT: s_and_b32 s3, s2, 15 ; GFX6-NEXT: s_andn2_b32 s2, 15, s2 -; GFX6-NEXT: s_and_b32 s1, s1, 0xffff ; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX6-NEXT: s_lshr_b32 s1, s1, 1 +; GFX6-NEXT: s_bfe_u32 s1, s1, 0xf0001 ; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000 ; GFX6-NEXT: s_lshl_b32 s0, s0, s3 ; GFX6-NEXT: s_lshr_b32 s1, s1, s2 @@ -2830,9 +2801,8 @@ define amdgpu_ps i16 @s_fshl_i16(i16 inreg %lhs, i16 inreg %rhs, i16 inreg %amt) define amdgpu_ps i16 @s_fshl_i16_4(i16 inreg %lhs, i16 inreg %rhs) { ; GFX6-LABEL: s_fshl_i16_4: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_and_b32 s1, s1, 0xffff ; GFX6-NEXT: s_lshl_b32 s0, s0, 4 -; GFX6-NEXT: s_lshr_b32 s1, s1, 12 +; GFX6-NEXT: s_bfe_u32 s1, s1, 0x4000c ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: ; return to shader part epilog ; @@ -2872,9 +2842,8 @@ define amdgpu_ps i16 @s_fshl_i16_4(i16 inreg %lhs, i16 inreg %rhs) { define amdgpu_ps i16 @s_fshl_i16_5(i16 inreg %lhs, i16 inreg %rhs) { ; GFX6-LABEL: s_fshl_i16_5: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_and_b32 s1, s1, 0xffff ; GFX6-NEXT: s_lshl_b32 s0, s0, 5 -; GFX6-NEXT: s_lshr_b32 s1, s1, 11 +; GFX6-NEXT: s_bfe_u32 s1, s1, 0x5000b ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: ; return to shader part epilog ; @@ -2918,9 +2887,8 @@ define i16 @v_fshl_i16(i16 %lhs, i16 %rhs, i16 %amt) { ; GFX6-NEXT: v_and_b32_e32 v3, 15, v2 ; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2 ; GFX6-NEXT: v_and_b32_e32 v2, 15, v2 -; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX6-NEXT: v_bfe_u32 v3, v3, 0, 16 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1 +; GFX6-NEXT: v_bfe_u32 v1, v1, 1, 15 ; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, v3, v0 ; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1 @@ -2971,9 +2939,8 @@ define i16 @v_fshl_i16_4(i16 %lhs, i16 %rhs) { ; GFX6-LABEL: v_fshl_i16_4: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 4, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 12, v1 +; GFX6-NEXT: v_bfe_u32 v1, v1, 12, 4 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; @@ -3009,9 +2976,8 @@ define i16 @v_fshl_i16_5(i16 %lhs, i16 %rhs) { ; GFX6-LABEL: v_fshl_i16_5: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 5, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 11, v1 +; GFX6-NEXT: v_bfe_u32 v1, v1, 11, 5 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; @@ -3048,11 +3014,10 @@ define amdgpu_ps half @v_fshl_i16_ssv(i16 inreg %lhs, i16 inreg %rhs, i16 %amt) ; GFX6: ; %bb.0: ; GFX6-NEXT: v_and_b32_e32 v1, 15, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0 -; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16 ; GFX6-NEXT: v_and_b32_e32 v0, 15, v0 +; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16 ; GFX6-NEXT: v_lshl_b32_e32 v1, s0, v1 -; GFX6-NEXT: s_and_b32 s0, s1, 0xffff -; GFX6-NEXT: s_lshr_b32 s0, s0, 1 +; GFX6-NEXT: s_bfe_u32 s0, s1, 0xf0001 ; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 ; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 ; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 @@ -3106,9 +3071,8 @@ define amdgpu_ps half @v_fshl_i16_svs(i16 inreg %lhs, i16 %rhs, i16 inreg %amt) ; GFX6: ; %bb.0: ; GFX6-NEXT: s_and_b32 s2, s1, 15 ; GFX6-NEXT: s_andn2_b32 s1, 15, s1 -; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX6-NEXT: v_lshrrev_b32_e32 v0, 1, v0 +; GFX6-NEXT: v_bfe_u32 v0, v0, 1, 15 ; GFX6-NEXT: s_bfe_u32 s1, s1, 0x100000 ; GFX6-NEXT: s_lshl_b32 s0, s0, s2 ; GFX6-NEXT: v_lshrrev_b32_e32 v0, s1, v0 @@ -3157,9 +3121,8 @@ define amdgpu_ps half @v_fshl_i16_vss(i16 %lhs, i16 inreg %rhs, i16 inreg %amt) ; GFX6: ; %bb.0: ; GFX6-NEXT: s_and_b32 s2, s1, 15 ; GFX6-NEXT: s_andn2_b32 s1, 15, s1 -; GFX6-NEXT: s_and_b32 s0, s0, 0xffff ; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX6-NEXT: s_lshr_b32 s0, s0, 1 +; GFX6-NEXT: s_bfe_u32 s0, s0, 0xf0001 ; GFX6-NEXT: s_bfe_u32 s1, s1, 0x100000 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, s2, v0 ; GFX6-NEXT: s_lshr_b32 s0, s0, s1 @@ -3214,20 +3177,18 @@ define amdgpu_ps i32 @s_fshl_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, < ; GFX6: ; %bb.0: ; GFX6-NEXT: s_and_b32 s6, s4, 15 ; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000 -; GFX6-NEXT: s_lshl_b32 s0, s0, s6 -; GFX6-NEXT: s_mov_b32 s6, 0xffff ; GFX6-NEXT: s_andn2_b32 s4, 15, s4 -; GFX6-NEXT: s_and_b32 s2, s2, s6 -; GFX6-NEXT: s_lshr_b32 s2, s2, 1 +; GFX6-NEXT: s_lshl_b32 s0, s0, s6 +; GFX6-NEXT: s_mov_b32 s6, 0xf0001 +; GFX6-NEXT: s_bfe_u32 s2, s2, s6 ; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000 ; GFX6-NEXT: s_lshr_b32 s2, s2, s4 ; GFX6-NEXT: s_or_b32 s0, s0, s2 ; GFX6-NEXT: s_and_b32 s2, s5, 15 -; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000 ; GFX6-NEXT: s_andn2_b32 s4, 15, s5 +; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000 ; GFX6-NEXT: s_lshl_b32 s1, s1, s2 -; GFX6-NEXT: s_and_b32 s2, s3, s6 -; GFX6-NEXT: s_lshr_b32 s2, s2, 1 +; GFX6-NEXT: s_bfe_u32 s2, s3, s6 ; GFX6-NEXT: s_bfe_u32 s3, s4, 0x100000 ; GFX6-NEXT: s_lshr_b32 s2, s2, s3 ; GFX6-NEXT: s_or_b32 s1, s1, s2 @@ -3328,22 +3289,19 @@ define <2 x i16> @v_fshl_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) { ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: v_and_b32_e32 v6, 15, v4 ; GFX6-NEXT: v_xor_b32_e32 v4, -1, v4 -; GFX6-NEXT: s_mov_b32 s4, 0xffff ; GFX6-NEXT: v_and_b32_e32 v4, 15, v4 -; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 ; GFX6-NEXT: v_bfe_u32 v6, v6, 0, 16 -; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2 +; GFX6-NEXT: v_bfe_u32 v2, v2, 1, 15 ; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, v6, v0 ; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX6-NEXT: v_and_b32_e32 v2, 15, v5 ; GFX6-NEXT: v_xor_b32_e32 v4, -1, v5 -; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16 ; GFX6-NEXT: v_and_b32_e32 v4, 15, v4 +; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, v2, v1 -; GFX6-NEXT: v_and_b32_e32 v2, s4, v3 -; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2 +; GFX6-NEXT: v_bfe_u32 v2, v3, 1, 15 ; GFX6-NEXT: v_bfe_u32 v3, v4, 0, 16 ; GFX6-NEXT: v_lshrrev_b32_e32 v2, v3, v2 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 @@ -3409,14 +3367,15 @@ define <2 x i16> @v_fshl_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) { ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_bfe_u32 s4, 4, 0x100000 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0 -; GFX6-NEXT: s_mov_b32 s4, 0xffff -; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 -; GFX6-NEXT: v_lshrrev_b32_e32 v2, 12, v2 +; GFX6-NEXT: v_bfe_u32 v2, v2, 1, 15 +; GFX6-NEXT: s_bfe_u32 s4, 11, 0x100000 +; GFX6-NEXT: v_lshrrev_b32_e32 v2, s4, v2 +; GFX6-NEXT: s_bfe_u32 s4, 8, 0x100000 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 -; GFX6-NEXT: s_bfe_u32 s5, 8, 0x100000 -; GFX6-NEXT: v_and_b32_e32 v2, s4, v3 -; GFX6-NEXT: v_lshlrev_b32_e32 v1, s5, v1 -; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v2 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, s4, v1 +; GFX6-NEXT: v_bfe_u32 v2, v3, 1, 15 +; GFX6-NEXT: s_bfe_u32 s4, 7, 0x100000 +; GFX6-NEXT: v_lshrrev_b32_e32 v2, s4, v2 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; @@ -3462,22 +3421,20 @@ define amdgpu_ps float @v_fshl_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg % ; GFX6-LABEL: v_fshl_v2i16_ssv: ; GFX6: ; %bb.0: ; GFX6-NEXT: v_and_b32_e32 v2, 15, v0 -; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16 ; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0 -; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2 -; GFX6-NEXT: s_mov_b32 s0, 0xffff +; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16 ; GFX6-NEXT: v_and_b32_e32 v0, 15, v0 -; GFX6-NEXT: s_and_b32 s2, s2, s0 -; GFX6-NEXT: s_lshr_b32 s2, s2, 1 +; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2 +; GFX6-NEXT: s_mov_b32 s0, 0xf0001 +; GFX6-NEXT: s_bfe_u32 s2, s2, s0 ; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 ; GFX6-NEXT: v_lshr_b32_e32 v0, s2, v0 ; GFX6-NEXT: v_or_b32_e32 v0, v2, v0 ; GFX6-NEXT: v_and_b32_e32 v2, 15, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, -1, v1 ; GFX6-NEXT: v_and_b32_e32 v1, 15, v1 -; GFX6-NEXT: s_and_b32 s0, s3, s0 ; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16 -; GFX6-NEXT: s_lshr_b32 s0, s0, 1 +; GFX6-NEXT: s_bfe_u32 s0, s3, s0 ; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16 ; GFX6-NEXT: v_lshl_b32_e32 v2, s1, v2 ; GFX6-NEXT: v_lshr_b32_e32 v1, s0, v1 @@ -3554,21 +3511,18 @@ define amdgpu_ps float @v_fshl_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, < ; GFX6-LABEL: v_fshl_v2i16_svs: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_and_b32 s4, s2, 15 -; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX6-NEXT: s_lshl_b32 s0, s0, s4 -; GFX6-NEXT: s_mov_b32 s4, 0xffff ; GFX6-NEXT: s_andn2_b32 s2, 15, s2 -; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v0, 1, v0 +; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000 +; GFX6-NEXT: v_bfe_u32 v0, v0, 1, 15 ; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000 +; GFX6-NEXT: s_lshl_b32 s0, s0, s4 ; GFX6-NEXT: v_lshrrev_b32_e32 v0, s2, v0 ; GFX6-NEXT: v_or_b32_e32 v0, s0, v0 ; GFX6-NEXT: s_and_b32 s0, s3, 15 ; GFX6-NEXT: s_andn2_b32 s2, 15, s3 ; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 ; GFX6-NEXT: s_lshl_b32 s0, s1, s0 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1 +; GFX6-NEXT: v_bfe_u32 v1, v1, 1, 15 ; GFX6-NEXT: s_bfe_u32 s1, s2, 0x100000 ; GFX6-NEXT: v_lshrrev_b32_e32 v1, s1, v1 ; GFX6-NEXT: v_or_b32_e32 v1, s0, v1 @@ -3641,20 +3595,18 @@ define amdgpu_ps float @v_fshl_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, < ; GFX6: ; %bb.0: ; GFX6-NEXT: s_and_b32 s4, s2, 15 ; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0 -; GFX6-NEXT: s_mov_b32 s4, 0xffff ; GFX6-NEXT: s_andn2_b32 s2, 15, s2 -; GFX6-NEXT: s_and_b32 s0, s0, s4 -; GFX6-NEXT: s_lshr_b32 s0, s0, 1 +; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0 +; GFX6-NEXT: s_mov_b32 s4, 0xf0001 +; GFX6-NEXT: s_bfe_u32 s0, s0, s4 ; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000 ; GFX6-NEXT: s_lshr_b32 s0, s0, s2 ; GFX6-NEXT: v_or_b32_e32 v0, s0, v0 ; GFX6-NEXT: s_and_b32 s0, s3, 15 -; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000 ; GFX6-NEXT: s_andn2_b32 s2, 15, s3 +; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, s0, v1 -; GFX6-NEXT: s_and_b32 s0, s1, s4 -; GFX6-NEXT: s_lshr_b32 s0, s0, 1 +; GFX6-NEXT: s_bfe_u32 s0, s1, s4 ; GFX6-NEXT: s_bfe_u32 s1, s2, 0x100000 ; GFX6-NEXT: s_lshr_b32 s0, s0, s1 ; GFX6-NEXT: v_or_b32_e32 v1, s0, v1 @@ -3757,38 +3709,34 @@ define amdgpu_ps <2 x i32> @s_fshl_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg % ; GFX6: ; %bb.0: ; GFX6-NEXT: s_and_b32 s12, s8, 15 ; GFX6-NEXT: s_bfe_u32 s12, s12, 0x100000 -; GFX6-NEXT: s_lshl_b32 s0, s0, s12 -; GFX6-NEXT: s_mov_b32 s12, 0xffff ; GFX6-NEXT: s_andn2_b32 s8, 15, s8 -; GFX6-NEXT: s_and_b32 s4, s4, s12 -; GFX6-NEXT: s_lshr_b32 s4, s4, 1 +; GFX6-NEXT: s_lshl_b32 s0, s0, s12 +; GFX6-NEXT: s_mov_b32 s12, 0xf0001 +; GFX6-NEXT: s_bfe_u32 s4, s4, s12 ; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000 ; GFX6-NEXT: s_lshr_b32 s4, s4, s8 ; GFX6-NEXT: s_or_b32 s0, s0, s4 ; GFX6-NEXT: s_and_b32 s4, s9, 15 -; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000 ; GFX6-NEXT: s_andn2_b32 s8, 15, s9 +; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000 ; GFX6-NEXT: s_lshl_b32 s1, s1, s4 -; GFX6-NEXT: s_and_b32 s4, s5, s12 -; GFX6-NEXT: s_lshr_b32 s4, s4, 1 +; GFX6-NEXT: s_bfe_u32 s4, s5, s12 ; GFX6-NEXT: s_bfe_u32 s5, s8, 0x100000 ; GFX6-NEXT: s_lshr_b32 s4, s4, s5 ; GFX6-NEXT: s_or_b32 s1, s1, s4 ; GFX6-NEXT: s_and_b32 s4, s10, 15 -; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000 ; GFX6-NEXT: s_andn2_b32 s5, 15, s10 +; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000 ; GFX6-NEXT: s_lshl_b32 s2, s2, s4 -; GFX6-NEXT: s_and_b32 s4, s6, s12 -; GFX6-NEXT: s_lshr_b32 s4, s4, 1 +; GFX6-NEXT: s_bfe_u32 s4, s6, s12 ; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100000 ; GFX6-NEXT: s_lshr_b32 s4, s4, s5 ; GFX6-NEXT: s_or_b32 s2, s2, s4 ; GFX6-NEXT: s_and_b32 s4, s11, 15 -; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000 ; GFX6-NEXT: s_andn2_b32 s5, 15, s11 +; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000 ; GFX6-NEXT: s_lshl_b32 s3, s3, s4 -; GFX6-NEXT: s_and_b32 s4, s7, s12 -; GFX6-NEXT: s_lshr_b32 s4, s4, 1 +; GFX6-NEXT: s_bfe_u32 s4, s7, s12 ; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100000 ; GFX6-NEXT: s_lshr_b32 s4, s4, s5 ; GFX6-NEXT: s_bfe_u32 s1, s1, 0x100000 @@ -3957,43 +3905,37 @@ define <4 x half> @v_fshl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: v_and_b32_e32 v12, 15, v8 ; GFX6-NEXT: v_xor_b32_e32 v8, -1, v8 -; GFX6-NEXT: s_mov_b32 s4, 0xffff ; GFX6-NEXT: v_and_b32_e32 v8, 15, v8 -; GFX6-NEXT: v_and_b32_e32 v4, s4, v4 ; GFX6-NEXT: v_bfe_u32 v12, v12, 0, 16 -; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4 +; GFX6-NEXT: v_bfe_u32 v4, v4, 1, 15 ; GFX6-NEXT: v_bfe_u32 v8, v8, 0, 16 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, v12, v0 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, v8, v4 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v4 ; GFX6-NEXT: v_and_b32_e32 v4, 15, v9 ; GFX6-NEXT: v_xor_b32_e32 v8, -1, v9 -; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16 ; GFX6-NEXT: v_and_b32_e32 v8, 15, v8 +; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, v4, v1 -; GFX6-NEXT: v_and_b32_e32 v4, s4, v5 -; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4 +; GFX6-NEXT: v_bfe_u32 v4, v5, 1, 15 ; GFX6-NEXT: v_bfe_u32 v5, v8, 0, 16 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX6-NEXT: v_and_b32_e32 v4, 15, v10 -; GFX6-NEXT: v_mov_b32_e32 v12, 0xffff ; GFX6-NEXT: v_xor_b32_e32 v5, -1, v10 -; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16 ; GFX6-NEXT: v_and_b32_e32 v5, 15, v5 +; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, v4, v2 -; GFX6-NEXT: v_and_b32_e32 v4, v6, v12 -; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4 +; GFX6-NEXT: v_bfe_u32 v4, v6, 1, 15 ; GFX6-NEXT: v_bfe_u32 v5, v5, 0, 16 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4 ; GFX6-NEXT: v_or_b32_e32 v2, v2, v4 ; GFX6-NEXT: v_and_b32_e32 v4, 15, v11 ; GFX6-NEXT: v_xor_b32_e32 v5, -1, v11 -; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16 ; GFX6-NEXT: v_and_b32_e32 v5, 15, v5 +; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16 ; GFX6-NEXT: v_lshlrev_b32_e32 v3, v4, v3 -; GFX6-NEXT: v_and_b32_e32 v4, v7, v12 -; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4 +; GFX6-NEXT: v_bfe_u32 v4, v7, 1, 15 ; GFX6-NEXT: v_bfe_u32 v5, v5, 0, 16 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4 ; GFX6-NEXT: v_or_b32_e32 v3, v3, v4 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll index f76ccdf2f2d2ed6e0d37b46b0d28f0a2065cb7f1..766d9cdc60e604c513d376ee9e009ff7f2530fa5 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll @@ -370,9 +370,8 @@ define i8 @v_fshr_i8(i8 %lhs, i8 %rhs, i8 %amt) { define amdgpu_ps i8 @s_fshr_i8_4(i8 inreg %lhs, i8 inreg %rhs) { ; GFX6-LABEL: s_fshr_i8_4: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_and_b32 s1, s1, 0xff ; GFX6-NEXT: s_lshl_b32 s0, s0, 4 -; GFX6-NEXT: s_lshr_b32 s1, s1, 4 +; GFX6-NEXT: s_bfe_u32 s1, s1, 0x40004 ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: ; return to shader part epilog ; @@ -410,9 +409,8 @@ define i8 @v_fshr_i8_4(i8 %lhs, i8 %rhs) { ; GFX6-LABEL: v_fshr_i8_4: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 4, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 4, v1 +; GFX6-NEXT: v_bfe_u32 v1, v1, 4, 4 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; @@ -450,9 +448,8 @@ define i8 @v_fshr_i8_4(i8 %lhs, i8 %rhs) { define amdgpu_ps i8 @s_fshr_i8_5(i8 inreg %lhs, i8 inreg %rhs) { ; GFX6-LABEL: s_fshr_i8_5: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_and_b32 s1, s1, 0xff ; GFX6-NEXT: s_lshl_b32 s0, s0, 3 -; GFX6-NEXT: s_lshr_b32 s1, s1, 5 +; GFX6-NEXT: s_bfe_u32 s1, s1, 0x30005 ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: ; return to shader part epilog ; @@ -490,9 +487,8 @@ define i8 @v_fshr_i8_5(i8 %lhs, i8 %rhs) { ; GFX6-LABEL: v_fshr_i8_5: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 5, v1 +; GFX6-NEXT: v_bfe_u32 v1, v1, 5, 3 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; @@ -2657,9 +2653,8 @@ define amdgpu_ps i16 @s_fshr_i16(i16 inreg %lhs, i16 inreg %rhs, i16 inreg %amt) define amdgpu_ps i16 @s_fshr_i16_4(i16 inreg %lhs, i16 inreg %rhs) { ; GFX6-LABEL: s_fshr_i16_4: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_and_b32 s1, s1, 0xffff ; GFX6-NEXT: s_lshl_b32 s0, s0, 12 -; GFX6-NEXT: s_lshr_b32 s1, s1, 4 +; GFX6-NEXT: s_bfe_u32 s1, s1, 0xc0004 ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: ; return to shader part epilog ; @@ -2699,9 +2694,8 @@ define amdgpu_ps i16 @s_fshr_i16_4(i16 inreg %lhs, i16 inreg %rhs) { define amdgpu_ps i16 @s_fshr_i16_5(i16 inreg %lhs, i16 inreg %rhs) { ; GFX6-LABEL: s_fshr_i16_5: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_and_b32 s1, s1, 0xffff ; GFX6-NEXT: s_lshl_b32 s0, s0, 11 -; GFX6-NEXT: s_lshr_b32 s1, s1, 5 +; GFX6-NEXT: s_bfe_u32 s1, s1, 0xb0005 ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: ; return to shader part epilog ; @@ -2798,9 +2792,8 @@ define i16 @v_fshr_i16_4(i16 %lhs, i16 %rhs) { ; GFX6-LABEL: v_fshr_i16_4: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 12, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 4, v1 +; GFX6-NEXT: v_bfe_u32 v1, v1, 4, 12 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; @@ -2836,9 +2829,8 @@ define i16 @v_fshr_i16_5(i16 %lhs, i16 %rhs) { ; GFX6-LABEL: v_fshr_i16_5: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 11, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 5, v1 +; GFX6-NEXT: v_bfe_u32 v1, v1, 5, 11 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; @@ -3036,38 +3028,37 @@ define amdgpu_ps half @v_fshr_i16_vss(i16 %lhs, i16 inreg %rhs, i16 inreg %amt) define amdgpu_ps i32 @s_fshr_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <2 x i16> inreg %amt) { ; GFX6-LABEL: s_fshr_v2i16: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_mov_b32 s6, 0xffff ; GFX6-NEXT: s_lshl_b32 s5, s5, 16 -; GFX6-NEXT: s_and_b32 s4, s4, s6 +; GFX6-NEXT: s_and_b32 s4, s4, 0xffff ; GFX6-NEXT: s_or_b32 s4, s5, s4 ; GFX6-NEXT: s_bfe_u32 s5, 1, 0x100000 +; GFX6-NEXT: s_mov_b32 s6, 0xf0001 ; GFX6-NEXT: s_lshl_b32 s0, s0, s5 -; GFX6-NEXT: s_and_b32 s7, s2, s6 +; GFX6-NEXT: s_bfe_u32 s7, s2, s6 +; GFX6-NEXT: s_bfe_u32 s8, 14, 0x100000 ; GFX6-NEXT: s_lshl_b32 s1, s1, s5 -; GFX6-NEXT: s_and_b32 s5, s3, s6 -; GFX6-NEXT: s_lshr_b32 s7, s7, 15 -; GFX6-NEXT: s_lshr_b32 s5, s5, 15 -; GFX6-NEXT: s_lshl_b32 s2, s2, 1 +; GFX6-NEXT: s_bfe_u32 s5, s3, s6 +; GFX6-NEXT: s_lshr_b32 s7, s7, s8 +; GFX6-NEXT: s_lshr_b32 s5, s5, s8 ; GFX6-NEXT: s_xor_b32 s4, s4, -1 ; GFX6-NEXT: s_or_b32 s0, s0, s7 ; GFX6-NEXT: s_or_b32 s1, s1, s5 +; GFX6-NEXT: s_lshl_b32 s2, s2, 1 ; GFX6-NEXT: s_lshr_b32 s5, s4, 16 ; GFX6-NEXT: s_and_b32 s7, s4, 15 ; GFX6-NEXT: s_andn2_b32 s4, 15, s4 -; GFX6-NEXT: s_and_b32 s2, s2, s6 ; GFX6-NEXT: s_bfe_u32 s7, s7, 0x100000 -; GFX6-NEXT: s_lshr_b32 s2, s2, 1 +; GFX6-NEXT: s_bfe_u32 s2, s2, s6 ; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000 ; GFX6-NEXT: s_lshl_b32 s0, s0, s7 ; GFX6-NEXT: s_lshr_b32 s2, s2, s4 ; GFX6-NEXT: s_or_b32 s0, s0, s2 ; GFX6-NEXT: s_and_b32 s2, s5, 15 ; GFX6-NEXT: s_lshl_b32 s3, s3, 1 -; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000 ; GFX6-NEXT: s_andn2_b32 s4, 15, s5 +; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000 ; GFX6-NEXT: s_lshl_b32 s1, s1, s2 -; GFX6-NEXT: s_and_b32 s2, s3, s6 -; GFX6-NEXT: s_lshr_b32 s2, s2, 1 +; GFX6-NEXT: s_bfe_u32 s2, s3, s6 ; GFX6-NEXT: s_bfe_u32 s3, s4, 0x100000 ; GFX6-NEXT: s_lshr_b32 s2, s2, s3 ; GFX6-NEXT: s_or_b32 s1, s1, s2 @@ -3176,41 +3167,38 @@ define <2 x i16> @v_fshr_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) { ; GFX6-LABEL: v_fshr_v2i16: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_mov_b32_e32 v6, 0xffff ; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX6-NEXT: v_and_b32_e32 v4, v4, v6 -; GFX6-NEXT: s_mov_b32 s5, 0xffff +; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4 ; GFX6-NEXT: v_or_b32_e32 v4, v5, v4 ; GFX6-NEXT: s_bfe_u32 s4, 1, 0x100000 -; GFX6-NEXT: v_and_b32_e32 v5, s5, v2 +; GFX6-NEXT: v_bfe_u32 v5, v2, 1, 15 +; GFX6-NEXT: s_bfe_u32 s5, 14, 0x100000 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v5, 15, v5 +; GFX6-NEXT: v_lshrrev_b32_e32 v5, s5, v5 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v5 -; GFX6-NEXT: v_and_b32_e32 v5, s5, v3 +; GFX6-NEXT: v_bfe_u32 v5, v3, 1, 15 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, s4, v1 -; GFX6-NEXT: v_lshrrev_b32_e32 v5, 15, v5 +; GFX6-NEXT: v_lshrrev_b32_e32 v5, s5, v5 ; GFX6-NEXT: v_xor_b32_e32 v4, -1, v4 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v5 -; GFX6-NEXT: v_lshlrev_b32_e32 v2, 1, v2 ; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v4 -; GFX6-NEXT: v_and_b32_e32 v7, 15, v4 +; GFX6-NEXT: v_and_b32_e32 v6, 15, v4 ; GFX6-NEXT: v_xor_b32_e32 v4, -1, v4 +; GFX6-NEXT: v_lshlrev_b32_e32 v2, 1, v2 ; GFX6-NEXT: v_and_b32_e32 v4, 15, v4 -; GFX6-NEXT: v_and_b32_e32 v2, v2, v6 -; GFX6-NEXT: v_bfe_u32 v7, v7, 0, 16 -; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2 +; GFX6-NEXT: v_bfe_u32 v6, v6, 0, 16 +; GFX6-NEXT: v_bfe_u32 v2, v2, 1, 15 ; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16 -; GFX6-NEXT: v_lshlrev_b32_e32 v0, v7, v0 +; GFX6-NEXT: v_lshlrev_b32_e32 v0, v6, v0 ; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX6-NEXT: v_and_b32_e32 v2, 15, v5 -; GFX6-NEXT: v_lshlrev_b32_e32 v3, 1, v3 ; GFX6-NEXT: v_xor_b32_e32 v4, -1, v5 -; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16 +; GFX6-NEXT: v_lshlrev_b32_e32 v3, 1, v3 ; GFX6-NEXT: v_and_b32_e32 v4, 15, v4 +; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, v2, v1 -; GFX6-NEXT: v_and_b32_e32 v2, v3, v6 -; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2 +; GFX6-NEXT: v_bfe_u32 v2, v3, 1, 15 ; GFX6-NEXT: v_bfe_u32 v3, v4, 0, 16 ; GFX6-NEXT: v_lshrrev_b32_e32 v2, v3, v2 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 @@ -3286,14 +3274,15 @@ define <2 x i16> @v_fshr_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) { ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_bfe_u32 s4, 12, 0x100000 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0 -; GFX6-NEXT: s_mov_b32 s4, 0xffff -; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 -; GFX6-NEXT: v_lshrrev_b32_e32 v2, 4, v2 +; GFX6-NEXT: v_bfe_u32 v2, v2, 1, 15 +; GFX6-NEXT: s_bfe_u32 s4, 3, 0x100000 +; GFX6-NEXT: v_lshrrev_b32_e32 v2, s4, v2 +; GFX6-NEXT: s_bfe_u32 s4, 8, 0x100000 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v2 -; GFX6-NEXT: s_bfe_u32 s5, 8, 0x100000 -; GFX6-NEXT: v_and_b32_e32 v2, s4, v3 -; GFX6-NEXT: v_lshlrev_b32_e32 v1, s5, v1 -; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v2 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, s4, v1 +; GFX6-NEXT: v_bfe_u32 v2, v3, 1, 15 +; GFX6-NEXT: s_bfe_u32 s4, 7, 0x100000 +; GFX6-NEXT: v_lshrrev_b32_e32 v2, s4, v2 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; @@ -3341,36 +3330,35 @@ define amdgpu_ps float @v_fshr_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg % ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 -; GFX6-NEXT: s_mov_b32 s5, 0xffff +; GFX6-NEXT: s_mov_b32 s5, 0xf0001 ; GFX6-NEXT: s_bfe_u32 s4, 1, 0x100000 -; GFX6-NEXT: s_and_b32 s6, s2, s5 +; GFX6-NEXT: s_bfe_u32 s6, s2, s5 +; GFX6-NEXT: s_bfe_u32 s7, 14, 0x100000 ; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0 ; GFX6-NEXT: s_lshl_b32 s0, s0, s4 -; GFX6-NEXT: s_lshr_b32 s6, s6, 15 +; GFX6-NEXT: s_lshr_b32 s6, s6, s7 +; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; GFX6-NEXT: v_and_b32_e32 v2, 15, v0 +; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0 ; GFX6-NEXT: s_or_b32 s0, s0, s6 ; GFX6-NEXT: s_lshl_b32 s2, s2, 1 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 -; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0 -; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16 ; GFX6-NEXT: v_and_b32_e32 v0, 15, v0 +; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16 ; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2 -; GFX6-NEXT: s_and_b32 s0, s2, s5 -; GFX6-NEXT: s_lshr_b32 s0, s0, 1 +; GFX6-NEXT: s_bfe_u32 s0, s2, s5 ; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 ; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0 ; GFX6-NEXT: s_lshl_b32 s1, s1, s4 -; GFX6-NEXT: s_and_b32 s4, s3, s5 -; GFX6-NEXT: s_lshl_b32 s3, s3, 1 +; GFX6-NEXT: s_bfe_u32 s4, s3, s5 ; GFX6-NEXT: v_or_b32_e32 v0, v2, v0 ; GFX6-NEXT: v_and_b32_e32 v2, 15, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, -1, v1 -; GFX6-NEXT: s_lshr_b32 s4, s4, 15 +; GFX6-NEXT: s_lshr_b32 s4, s4, s7 +; GFX6-NEXT: s_lshl_b32 s3, s3, 1 ; GFX6-NEXT: v_and_b32_e32 v1, 15, v1 -; GFX6-NEXT: s_and_b32 s0, s3, s5 ; GFX6-NEXT: s_or_b32 s1, s1, s4 ; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16 -; GFX6-NEXT: s_lshr_b32 s0, s0, 1 +; GFX6-NEXT: s_bfe_u32 s0, s3, s5 ; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16 ; GFX6-NEXT: v_lshl_b32_e32 v2, s1, v2 ; GFX6-NEXT: v_lshr_b32_e32 v1, s0, v1 @@ -3456,38 +3444,36 @@ define amdgpu_ps float @v_fshr_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg % define amdgpu_ps float @v_fshr_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, <2 x i16> inreg %amt) { ; GFX6-LABEL: v_fshr_v2i16_svs: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_mov_b32 s4, 0xffff ; GFX6-NEXT: s_lshl_b32 s3, s3, 16 -; GFX6-NEXT: s_and_b32 s2, s2, s4 +; GFX6-NEXT: s_and_b32 s2, s2, 0xffff ; GFX6-NEXT: s_or_b32 s2, s3, s2 ; GFX6-NEXT: s_bfe_u32 s3, 1, 0x100000 -; GFX6-NEXT: v_and_b32_e32 v2, s4, v0 +; GFX6-NEXT: v_bfe_u32 v2, v0, 1, 15 +; GFX6-NEXT: s_bfe_u32 s4, 14, 0x100000 ; GFX6-NEXT: s_lshl_b32 s0, s0, s3 -; GFX6-NEXT: v_lshrrev_b32_e32 v2, 15, v2 -; GFX6-NEXT: v_and_b32_e32 v3, s4, v1 +; GFX6-NEXT: v_lshrrev_b32_e32 v2, s4, v2 +; GFX6-NEXT: v_bfe_u32 v3, v1, 1, 15 ; GFX6-NEXT: v_or_b32_e32 v2, s0, v2 ; GFX6-NEXT: s_lshl_b32 s0, s1, s3 -; GFX6-NEXT: v_lshrrev_b32_e32 v3, 15, v3 +; GFX6-NEXT: v_lshrrev_b32_e32 v3, s4, v3 ; GFX6-NEXT: v_or_b32_e32 v3, s0, v3 -; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX6-NEXT: s_xor_b32 s0, s2, -1 +; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX6-NEXT: s_lshr_b32 s1, s0, 16 ; GFX6-NEXT: s_and_b32 s2, s0, 15 ; GFX6-NEXT: s_andn2_b32 s0, 15, s0 -; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v0, 1, v0 +; GFX6-NEXT: v_bfe_u32 v0, v0, 1, 15 ; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX6-NEXT: v_lshlrev_b32_e32 v1, 1, v1 ; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000 ; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0 ; GFX6-NEXT: s_and_b32 s0, s1, 15 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 1, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, s2, v2 ; GFX6-NEXT: s_andn2_b32 s1, 15, s1 ; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 ; GFX6-NEXT: v_or_b32_e32 v0, v2, v0 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, s0, v3 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1 +; GFX6-NEXT: v_bfe_u32 v1, v1, 1, 15 ; GFX6-NEXT: s_bfe_u32 s0, s1, 0x100000 ; GFX6-NEXT: v_lshrrev_b32_e32 v1, s0, v1 ; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 @@ -3573,38 +3559,37 @@ define amdgpu_ps float @v_fshr_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, < define amdgpu_ps float @v_fshr_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <2 x i16> inreg %amt) { ; GFX6-LABEL: v_fshr_v2i16_vss: ; GFX6: ; %bb.0: -; GFX6-NEXT: s_mov_b32 s4, 0xffff ; GFX6-NEXT: s_lshl_b32 s3, s3, 16 -; GFX6-NEXT: s_and_b32 s2, s2, s4 +; GFX6-NEXT: s_and_b32 s2, s2, 0xffff ; GFX6-NEXT: s_or_b32 s2, s3, s2 ; GFX6-NEXT: s_bfe_u32 s3, 1, 0x100000 +; GFX6-NEXT: s_mov_b32 s4, 0xf0001 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, s3, v0 -; GFX6-NEXT: s_and_b32 s5, s0, s4 +; GFX6-NEXT: s_bfe_u32 s5, s0, s4 +; GFX6-NEXT: s_bfe_u32 s6, 14, 0x100000 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, s3, v1 -; GFX6-NEXT: s_and_b32 s3, s1, s4 -; GFX6-NEXT: s_lshr_b32 s5, s5, 15 -; GFX6-NEXT: s_lshr_b32 s3, s3, 15 -; GFX6-NEXT: s_lshl_b32 s0, s0, 1 +; GFX6-NEXT: s_bfe_u32 s3, s1, s4 +; GFX6-NEXT: s_lshr_b32 s5, s5, s6 +; GFX6-NEXT: s_lshr_b32 s3, s3, s6 ; GFX6-NEXT: s_xor_b32 s2, s2, -1 ; GFX6-NEXT: v_or_b32_e32 v0, s5, v0 ; GFX6-NEXT: v_or_b32_e32 v1, s3, v1 +; GFX6-NEXT: s_lshl_b32 s0, s0, 1 ; GFX6-NEXT: s_lshr_b32 s3, s2, 16 ; GFX6-NEXT: s_and_b32 s5, s2, 15 ; GFX6-NEXT: s_andn2_b32 s2, 15, s2 -; GFX6-NEXT: s_and_b32 s0, s0, s4 ; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100000 -; GFX6-NEXT: s_lshr_b32 s0, s0, 1 +; GFX6-NEXT: s_bfe_u32 s0, s0, s4 ; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, s5, v0 ; GFX6-NEXT: s_lshr_b32 s0, s0, s2 ; GFX6-NEXT: v_or_b32_e32 v0, s0, v0 ; GFX6-NEXT: s_and_b32 s0, s3, 15 ; GFX6-NEXT: s_lshl_b32 s1, s1, 1 -; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000 ; GFX6-NEXT: s_andn2_b32 s2, 15, s3 +; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, s0, v1 -; GFX6-NEXT: s_and_b32 s0, s1, s4 -; GFX6-NEXT: s_lshr_b32 s0, s0, 1 +; GFX6-NEXT: s_bfe_u32 s0, s1, s4 ; GFX6-NEXT: s_bfe_u32 s1, s2, 0x100000 ; GFX6-NEXT: s_lshr_b32 s0, s0, s1 ; GFX6-NEXT: v_or_b32_e32 v1, s0, v1 @@ -3715,35 +3700,35 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg % ; GFX6-NEXT: s_or_b32 s8, s9, s8 ; GFX6-NEXT: s_lshl_b32 s9, s11, 16 ; GFX6-NEXT: s_and_b32 s10, s10, s12 +; GFX6-NEXT: s_mov_b32 s11, 0xf0001 ; GFX6-NEXT: s_or_b32 s9, s9, s10 ; GFX6-NEXT: s_bfe_u32 s10, 1, 0x100000 -; GFX6-NEXT: s_and_b32 s11, s4, s12 +; GFX6-NEXT: s_bfe_u32 s12, s4, s11 +; GFX6-NEXT: s_bfe_u32 s13, 14, 0x100000 ; GFX6-NEXT: s_lshl_b32 s0, s0, s10 -; GFX6-NEXT: s_lshr_b32 s11, s11, 15 -; GFX6-NEXT: s_or_b32 s0, s0, s11 -; GFX6-NEXT: s_and_b32 s11, s5, s12 +; GFX6-NEXT: s_lshr_b32 s12, s12, s13 +; GFX6-NEXT: s_or_b32 s0, s0, s12 +; GFX6-NEXT: s_bfe_u32 s12, s5, s11 ; GFX6-NEXT: s_lshl_b32 s1, s1, s10 -; GFX6-NEXT: s_lshr_b32 s11, s11, 15 -; GFX6-NEXT: s_lshl_b32 s4, s4, 1 +; GFX6-NEXT: s_lshr_b32 s12, s12, s13 ; GFX6-NEXT: s_xor_b32 s8, s8, -1 -; GFX6-NEXT: s_or_b32 s1, s1, s11 -; GFX6-NEXT: s_lshr_b32 s11, s8, 16 -; GFX6-NEXT: s_and_b32 s13, s8, 15 +; GFX6-NEXT: s_or_b32 s1, s1, s12 +; GFX6-NEXT: s_lshl_b32 s4, s4, 1 +; GFX6-NEXT: s_lshr_b32 s12, s8, 16 +; GFX6-NEXT: s_and_b32 s14, s8, 15 ; GFX6-NEXT: s_andn2_b32 s8, 15, s8 -; GFX6-NEXT: s_and_b32 s4, s4, s12 -; GFX6-NEXT: s_bfe_u32 s13, s13, 0x100000 -; GFX6-NEXT: s_lshr_b32 s4, s4, 1 +; GFX6-NEXT: s_bfe_u32 s14, s14, 0x100000 +; GFX6-NEXT: s_bfe_u32 s4, s4, s11 ; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000 -; GFX6-NEXT: s_lshl_b32 s0, s0, s13 +; GFX6-NEXT: s_lshl_b32 s0, s0, s14 ; GFX6-NEXT: s_lshr_b32 s4, s4, s8 ; GFX6-NEXT: s_or_b32 s0, s0, s4 -; GFX6-NEXT: s_and_b32 s4, s11, 15 +; GFX6-NEXT: s_and_b32 s4, s12, 15 ; GFX6-NEXT: s_lshl_b32 s5, s5, 1 +; GFX6-NEXT: s_andn2_b32 s8, 15, s12 ; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX6-NEXT: s_andn2_b32 s8, 15, s11 ; GFX6-NEXT: s_lshl_b32 s1, s1, s4 -; GFX6-NEXT: s_and_b32 s4, s5, s12 -; GFX6-NEXT: s_lshr_b32 s4, s4, 1 +; GFX6-NEXT: s_bfe_u32 s4, s5, s11 ; GFX6-NEXT: s_bfe_u32 s5, s8, 0x100000 ; GFX6-NEXT: s_lshr_b32 s4, s4, s5 ; GFX6-NEXT: s_or_b32 s1, s1, s4 @@ -3752,32 +3737,30 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg % ; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_lshl_b32 s1, s2, s10 -; GFX6-NEXT: s_and_b32 s2, s6, s12 -; GFX6-NEXT: s_lshr_b32 s2, s2, 15 +; GFX6-NEXT: s_bfe_u32 s2, s6, s11 +; GFX6-NEXT: s_lshr_b32 s2, s2, s13 ; GFX6-NEXT: s_or_b32 s1, s1, s2 ; GFX6-NEXT: s_lshl_b32 s2, s3, s10 -; GFX6-NEXT: s_and_b32 s3, s7, s12 -; GFX6-NEXT: s_lshr_b32 s3, s3, 15 +; GFX6-NEXT: s_bfe_u32 s3, s7, s11 +; GFX6-NEXT: s_lshr_b32 s3, s3, s13 +; GFX6-NEXT: s_xor_b32 s5, s9, -1 ; GFX6-NEXT: s_or_b32 s2, s2, s3 ; GFX6-NEXT: s_lshl_b32 s3, s6, 1 -; GFX6-NEXT: s_xor_b32 s5, s9, -1 ; GFX6-NEXT: s_lshl_b32 s4, s7, 1 ; GFX6-NEXT: s_lshr_b32 s6, s5, 16 ; GFX6-NEXT: s_and_b32 s7, s5, 15 ; GFX6-NEXT: s_andn2_b32 s5, 15, s5 -; GFX6-NEXT: s_and_b32 s3, s3, s12 ; GFX6-NEXT: s_bfe_u32 s7, s7, 0x100000 -; GFX6-NEXT: s_lshr_b32 s3, s3, 1 +; GFX6-NEXT: s_bfe_u32 s3, s3, s11 ; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100000 ; GFX6-NEXT: s_lshl_b32 s1, s1, s7 ; GFX6-NEXT: s_lshr_b32 s3, s3, s5 ; GFX6-NEXT: s_or_b32 s1, s1, s3 ; GFX6-NEXT: s_and_b32 s3, s6, 15 -; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100000 ; GFX6-NEXT: s_andn2_b32 s5, 15, s6 +; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100000 ; GFX6-NEXT: s_lshl_b32 s2, s2, s3 -; GFX6-NEXT: s_and_b32 s3, s4, s12 -; GFX6-NEXT: s_lshr_b32 s3, s3, 1 +; GFX6-NEXT: s_bfe_u32 s3, s4, s11 ; GFX6-NEXT: s_bfe_u32 s4, s5, 0x100000 ; GFX6-NEXT: s_lshr_b32 s3, s3, s4 ; GFX6-NEXT: s_or_b32 s2, s2, s3 @@ -3967,48 +3950,46 @@ define <4 x half> @v_fshr_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt) ; GFX6-NEXT: v_or_b32_e32 v8, v9, v8 ; GFX6-NEXT: v_lshlrev_b32_e32 v9, 16, v11 ; GFX6-NEXT: v_and_b32_e32 v10, v10, v12 -; GFX6-NEXT: s_mov_b32 s5, 0xffff ; GFX6-NEXT: v_or_b32_e32 v9, v9, v10 ; GFX6-NEXT: s_bfe_u32 s4, 1, 0x100000 -; GFX6-NEXT: v_and_b32_e32 v10, s5, v4 +; GFX6-NEXT: v_bfe_u32 v10, v4, 1, 15 +; GFX6-NEXT: s_bfe_u32 s5, 14, 0x100000 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v10, 15, v10 +; GFX6-NEXT: v_lshrrev_b32_e32 v10, s5, v10 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v10 -; GFX6-NEXT: v_and_b32_e32 v10, s5, v5 +; GFX6-NEXT: v_bfe_u32 v10, v5, 1, 15 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, s4, v1 -; GFX6-NEXT: v_lshrrev_b32_e32 v10, 15, v10 +; GFX6-NEXT: v_lshrrev_b32_e32 v10, s5, v10 ; GFX6-NEXT: v_xor_b32_e32 v8, -1, v8 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v10 -; GFX6-NEXT: v_lshlrev_b32_e32 v4, 1, v4 ; GFX6-NEXT: v_lshrrev_b32_e32 v10, 16, v8 ; GFX6-NEXT: v_and_b32_e32 v11, 15, v8 ; GFX6-NEXT: v_xor_b32_e32 v8, -1, v8 +; GFX6-NEXT: v_lshlrev_b32_e32 v4, 1, v4 ; GFX6-NEXT: v_and_b32_e32 v8, 15, v8 -; GFX6-NEXT: v_and_b32_e32 v4, v4, v12 ; GFX6-NEXT: v_bfe_u32 v11, v11, 0, 16 -; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4 +; GFX6-NEXT: v_bfe_u32 v4, v4, 1, 15 ; GFX6-NEXT: v_bfe_u32 v8, v8, 0, 16 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, v11, v0 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, v8, v4 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v4 ; GFX6-NEXT: v_and_b32_e32 v4, 15, v10 -; GFX6-NEXT: v_lshlrev_b32_e32 v5, 1, v5 ; GFX6-NEXT: v_xor_b32_e32 v8, -1, v10 -; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16 +; GFX6-NEXT: v_lshlrev_b32_e32 v5, 1, v5 ; GFX6-NEXT: v_and_b32_e32 v8, 15, v8 +; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, v4, v1 -; GFX6-NEXT: v_and_b32_e32 v4, v5, v12 -; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4 +; GFX6-NEXT: v_bfe_u32 v4, v5, 1, 15 ; GFX6-NEXT: v_bfe_u32 v5, v8, 0, 16 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v4 -; GFX6-NEXT: v_and_b32_e32 v4, v6, v12 +; GFX6-NEXT: v_bfe_u32 v4, v6, 1, 15 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, s4, v2 -; GFX6-NEXT: v_lshrrev_b32_e32 v4, 15, v4 +; GFX6-NEXT: v_lshrrev_b32_e32 v4, s5, v4 ; GFX6-NEXT: v_or_b32_e32 v2, v2, v4 -; GFX6-NEXT: v_and_b32_e32 v4, v7, v12 +; GFX6-NEXT: v_bfe_u32 v4, v7, 1, 15 ; GFX6-NEXT: v_lshlrev_b32_e32 v3, s4, v3 -; GFX6-NEXT: v_lshrrev_b32_e32 v4, 15, v4 +; GFX6-NEXT: v_lshrrev_b32_e32 v4, s5, v4 ; GFX6-NEXT: v_or_b32_e32 v3, v3, v4 ; GFX6-NEXT: v_lshlrev_b32_e32 v4, 1, v6 ; GFX6-NEXT: v_xor_b32_e32 v6, -1, v9 @@ -4017,20 +3998,18 @@ define <4 x half> @v_fshr_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt) ; GFX6-NEXT: v_and_b32_e32 v8, 15, v6 ; GFX6-NEXT: v_xor_b32_e32 v6, -1, v6 ; GFX6-NEXT: v_and_b32_e32 v6, 15, v6 -; GFX6-NEXT: v_and_b32_e32 v4, v4, v12 ; GFX6-NEXT: v_bfe_u32 v8, v8, 0, 16 -; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4 +; GFX6-NEXT: v_bfe_u32 v4, v4, 1, 15 ; GFX6-NEXT: v_bfe_u32 v6, v6, 0, 16 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, v8, v2 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, v6, v4 ; GFX6-NEXT: v_or_b32_e32 v2, v2, v4 ; GFX6-NEXT: v_and_b32_e32 v4, 15, v7 ; GFX6-NEXT: v_xor_b32_e32 v6, -1, v7 -; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16 ; GFX6-NEXT: v_and_b32_e32 v6, 15, v6 +; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16 ; GFX6-NEXT: v_lshlrev_b32_e32 v3, v4, v3 -; GFX6-NEXT: v_and_b32_e32 v4, v5, v12 -; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4 +; GFX6-NEXT: v_bfe_u32 v4, v5, 1, 15 ; GFX6-NEXT: v_bfe_u32 v5, v6, 0, 16 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4 ; GFX6-NEXT: v_or_b32_e32 v3, v3, v4 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll index a87e8f8e3a27a7b8ec2daf110ff7cfc4d0da810c..900f53ba38713ab242f33b6641e19dc9593607bf 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll @@ -1020,8 +1020,7 @@ define amdgpu_kernel void @and_lshr(i32 addrspace(1)* %out, i32 %a) #0 { ; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) -; GFX6-NEXT: s_and_b32 s0, s0, 0x1c0 -; GFX6-NEXT: s_lshr_b32 s0, s0, 6 +; GFX6-NEXT: s_bfe_u32 s0, s0, 0x30006 ; GFX6-NEXT: v_mov_b32_e32 v0, s0 ; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX6-NEXT: s_endpgm @@ -1039,8 +1038,7 @@ define amdgpu_kernel void @and_lshr2(i32 addrspace(1)* %out, i32 %a) #0 { ; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) -; GFX6-NEXT: s_and_b32 s0, s0, 0x1ff -; GFX6-NEXT: s_lshr_b32 s0, s0, 6 +; GFX6-NEXT: s_bfe_u32 s0, s0, 0x30006 ; GFX6-NEXT: v_mov_b32_e32 v0, s0 ; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GFX6-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll index 4b3fc2e1a61022aab7f8158568c5cb5748b0fd13..d0e71fb9ecc25409f6ec037426d53ea760ebd8c0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll @@ -42,8 +42,7 @@ define i8 @v_lshr_i8_7(i8 %value) { ; GFX6-LABEL: v_lshr_i8_7: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v0, 7, v0 +; GFX6-NEXT: v_bfe_u32 v0, v0, 7, 1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_lshr_i8_7: @@ -110,14 +109,12 @@ define amdgpu_ps i8 @s_lshr_i8(i8 inreg %value, i8 inreg %amount) { define amdgpu_ps i8 @s_lshr_i8_7(i8 inreg %value) { ; GCN-LABEL: s_lshr_i8_7: ; GCN: ; %bb.0: -; GCN-NEXT: s_and_b32 s0, s0, 0xff -; GCN-NEXT: s_lshr_b32 s0, s0, 7 +; GCN-NEXT: s_bfe_u32 s0, s0, 0x10007 ; GCN-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_lshr_i8_7: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_and_b32 s0, s0, 0xff -; GFX10-NEXT: s_lshr_b32 s0, s0, 7 +; GFX10-NEXT: s_bfe_u32 s0, s0, 0x10007 ; GFX10-NEXT: ; return to shader part epilog %result = lshr i8 %value, 7 ret i8 %result @@ -151,16 +148,14 @@ define i24 @v_lshr_i24_7(i24 %value) { ; GCN-LABEL: v_lshr_i24_7: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GCN-NEXT: v_lshrrev_b32_e32 v0, 7, v0 +; GCN-NEXT: v_bfe_u32 v0, v0, 7, 17 ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_lshr_i24_7: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GFX10-NEXT: v_lshrrev_b32_e32 v0, 7, v0 +; GFX10-NEXT: v_bfe_u32 v0, v0, 7, 17 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = lshr i24 %value, 7 ret i24 %result @@ -189,14 +184,12 @@ define amdgpu_ps i24 @s_lshr_i24(i24 inreg %value, i24 inreg %amount) { define amdgpu_ps i24 @s_lshr_i24_7(i24 inreg %value) { ; GCN-LABEL: s_lshr_i24_7: ; GCN: ; %bb.0: -; GCN-NEXT: s_and_b32 s0, s0, 0xffffff -; GCN-NEXT: s_lshr_b32 s0, s0, 7 +; GCN-NEXT: s_bfe_u32 s0, s0, 0x110007 ; GCN-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_lshr_i24_7: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_and_b32 s0, s0, 0xffffff -; GFX10-NEXT: s_lshr_b32 s0, s0, 7 +; GFX10-NEXT: s_bfe_u32 s0, s0, 0x110007 ; GFX10-NEXT: ; return to shader part epilog %result = lshr i24 %value, 7 ret i24 %result @@ -664,14 +657,12 @@ define amdgpu_ps i16 @s_lshr_i16(i16 inreg %value, i16 inreg %amount) { define amdgpu_ps i16 @s_lshr_i16_15(i16 inreg %value) { ; GCN-LABEL: s_lshr_i16_15: ; GCN: ; %bb.0: -; GCN-NEXT: s_and_b32 s0, s0, 0xffff -; GCN-NEXT: s_lshr_b32 s0, s0, 15 +; GCN-NEXT: s_bfe_u32 s0, s0, 0x1000f ; GCN-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_lshr_i16_15: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_and_b32 s0, s0, 0xffff -; GFX10-NEXT: s_lshr_b32 s0, s0, 15 +; GFX10-NEXT: s_bfe_u32 s0, s0, 0x1000f ; GFX10-NEXT: ; return to shader part epilog %result = lshr i16 %value, 15 ret i16 %result @@ -774,11 +765,8 @@ define <2 x i16> @v_lshr_v2i16_15(<2 x i16> %value) { ; GFX6-LABEL: v_lshr_v2i16_15: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX6-NEXT: s_mov_b32 s4, 0xffff -; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 -; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 -; GFX6-NEXT: v_lshrrev_b32_e32 v0, 15, v0 -; GFX6-NEXT: v_lshrrev_b32_e32 v1, 15, v1 +; GFX6-NEXT: v_bfe_u32 v0, v0, 15, 1 +; GFX6-NEXT: v_bfe_u32 v1, v1, 15, 1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_lshr_v2i16_15: diff --git a/llvm/test/CodeGen/AMDGPU/extra-sroa-after-unroll.ll b/llvm/test/CodeGen/AMDGPU/extra-sroa-after-unroll.ll index db704a8bcbbfc8f06f5368f7bb1c4d6b0287ecd6..6f50abc58fa5dc0eec2e081dc4ec3e4066d098b8 100644 --- a/llvm/test/CodeGen/AMDGPU/extra-sroa-after-unroll.ll +++ b/llvm/test/CodeGen/AMDGPU/extra-sroa-after-unroll.ll @@ -1,6 +1,6 @@ -; RUN: opt -instnamer -O1 -mtriple=amdgcn-- -S -o - %s | FileCheck -check-prefixes=GCN,O1 %s -; RUN: opt -instnamer -O2 -mtriple=amdgcn-- -S -o - %s | FileCheck -check-prefixes=GCN,O2 %s -; RUN: opt -instnamer -O3 -mtriple=amdgcn-- -S -o - %s | FileCheck -check-prefixes=GCN,O3 %s +; RUN: opt -passes='default,instnamer' -mtriple=amdgcn-- -S -o - %s | FileCheck -check-prefixes=GCN,O1 %s +; RUN: opt -passes='default,instnamer' -mtriple=amdgcn-- -S -o - %s | FileCheck -check-prefixes=GCN,O2 %s +; RUN: opt -passes='default,instnamer' -mtriple=amdgcn-- -S -o - %s | FileCheck -check-prefixes=GCN,O3 %s target datalayout = "A5" ; GCN-LABEL: t0 diff --git a/llvm/test/CodeGen/AMDGPU/inline-calls.ll b/llvm/test/CodeGen/AMDGPU/inline-calls.ll index 233485a2020572611f80c85584cf1462284922da..134cd301b974331522d7f6ac0f374178fc755aa8 100644 --- a/llvm/test/CodeGen/AMDGPU/inline-calls.ll +++ b/llvm/test/CodeGen/AMDGPU/inline-calls.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple amdgcn-unknown-linux-gnu -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple amdgcn-unknown-linux-gnu -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple r600-unknown-linux-gnu -mcpu=redwood -verify-machineinstrs < %s | FileCheck %s --check-prefix=R600 ; ALL-NOT: {{^}}func: define internal i32 @func(i32 %a) { @@ -9,7 +9,7 @@ entry: ret i32 %tmp0 } -; ALL: {{^}}kernel: +; CHECK: {{^}}kernel: ; GCN-NOT: s_swappc_b64 define amdgpu_kernel void @kernel(i32 addrspace(1)* %out) { entry: @@ -18,12 +18,13 @@ entry: ret void } -; CHECK-NOT: func_alias -; ALL-NOT: func_alias +; CHECK: func_alias +; R600-NOT: func_alias @func_alias = alias i32 (i32), i32 (i32)* @func -; ALL: {{^}}kernel3: +; CHECK-NOT: {{^}}kernel3: ; GCN-NOT: s_swappc_b64 +; R600: {{^}}kernel3: define amdgpu_kernel void @kernel3(i32 addrspace(1)* %out) { entry: %tmp0 = call i32 @func_alias(i32 1) diff --git a/llvm/test/CodeGen/AMDGPU/r600.amdgpu-alias-analysis.ll b/llvm/test/CodeGen/AMDGPU/r600.amdgpu-alias-analysis.ll index 9199e9b8414de50d76a568ed1f90c7e7f7b25345..32dd8e5f0ca6288d79787beb2096af06a67e684b 100644 --- a/llvm/test/CodeGen/AMDGPU/r600.amdgpu-alias-analysis.ll +++ b/llvm/test/CodeGen/AMDGPU/r600.amdgpu-alias-analysis.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=r600-- -O3 -aa-eval -print-all-alias-modref-info -disable-output < %s 2>&1 | FileCheck %s +; RUN: opt -mtriple=r600-- -passes='default,aa-eval' -print-all-alias-modref-info -disable-output < %s 2>&1 | FileCheck %s ; CHECK: MayAlias: i8 addrspace(5)* %p, i8 addrspace(999)* %p1 define amdgpu_kernel void @test(i8 addrspace(5)* %p, i8 addrspace(999)* %p1) { diff --git a/llvm/test/CodeGen/BPF/vla.ll b/llvm/test/CodeGen/BPF/vla.ll new file mode 100644 index 0000000000000000000000000000000000000000..71eedb1d223bdaa70f5c790852ef1bf893c6e03c --- /dev/null +++ b/llvm/test/CodeGen/BPF/vla.ll @@ -0,0 +1,115 @@ +; RUN: opt --bpf-ir-peephole -mtriple=bpf-pc-linux -S %s | FileCheck %s +; Source: +; #define AA 40 +; struct t { +; char a[20]; +; }; +; void foo(void *); +; +; int test1() { +; const int a = 8; +; char tmp[AA + sizeof(struct t) + a]; +; foo(tmp); +; return 0; +; } +; +; int test2(int b) { +; const int a = 8; +; char tmp[a + b]; +; foo(tmp); +; return 0; +; } +; Compilation flag: +; clang -target bpf -O2 -S -emit-llvm t.c -Xclang -disable-llvm-passes + +source_filename = "t.c" +target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" +target triple = "bpf" + +; Function Attrs: nounwind +define dso_local i32 @test1() #0 { +entry: + %a = alloca i32, align 4 + %saved_stack = alloca i8*, align 8 + %0 = bitcast i32* %a to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #4 + store i32 8, i32* %a, align 4, !tbaa !3 + %1 = call i8* @llvm.stacksave() + store i8* %1, i8** %saved_stack, align 8 + %vla = alloca i8, i64 68, align 1 + call void @foo(i8* %vla) + %2 = load i8*, i8** %saved_stack, align 8 + call void @llvm.stackrestore(i8* %2) + %3 = bitcast i32* %a to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %3) #4 + ret i32 0 +} + +; CHECK: define dso_local i32 @test1 +; CHECK-NOT: %[[#]] = call i8* @llvm.stacksave() +; CHECK-NOT: store i8* %[[#]], i8** %saved_stack, align 8 +; CHECK-NOT: %[[#]] = load i8*, i8** %saved_stack, align 8 +; CHECK-NOT: call void @llvm.stackrestore(i8* %[[#]]) + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1 + +; Function Attrs: nofree nosync nounwind willreturn +declare i8* @llvm.stacksave() #2 + +declare dso_local void @foo(i8*) #3 + +; Function Attrs: nofree nosync nounwind willreturn +declare void @llvm.stackrestore(i8*) #2 + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1 + +; Function Attrs: nounwind +define dso_local i32 @test2(i32 %b) #0 { +entry: + %b.addr = alloca i32, align 4 + %a = alloca i32, align 4 + %saved_stack = alloca i8*, align 8 + %__vla_expr0 = alloca i64, align 8 + store i32 %b, i32* %b.addr, align 4, !tbaa !3 + %0 = bitcast i32* %a to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #4 + store i32 8, i32* %a, align 4, !tbaa !3 + %1 = load i32, i32* %b.addr, align 4, !tbaa !3 + %add = add nsw i32 8, %1 + %2 = zext i32 %add to i64 + %3 = call i8* @llvm.stacksave() + store i8* %3, i8** %saved_stack, align 8 + %vla = alloca i8, i64 %2, align 1 + store i64 %2, i64* %__vla_expr0, align 8 + call void @foo(i8* %vla) + %4 = load i8*, i8** %saved_stack, align 8 + call void @llvm.stackrestore(i8* %4) + %5 = bitcast i32* %a to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %5) #4 + ret i32 0 +} + +; CHECK: define dso_local i32 @test2 +; CHECK-NOT: %[[#]] = call i8* @llvm.stacksave() +; CHECK-NOT: store i8* %[[#]], i8** %saved_stack, align 8 +; CHECK-NOT: %[[#]] = load i8*, i8** %saved_stack, align 8 +; CHECK-NOT: call void @llvm.stackrestore(i8* %[[#]]) + +attributes #0 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { argmemonly nofree nosync nounwind willreturn } +attributes #2 = { nofree nosync nounwind willreturn } +attributes #3 = { "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #4 = { nounwind } + +!llvm.module.flags = !{!0, !1} +!llvm.ident = !{!2} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 7, !"frame-pointer", i32 2} +!2 = !{!"clang version 14.0.0 (https://github.com/llvm/llvm-project.git 64c5d5c671fb5b5f25c464652a4eec2cf743af0d)"} +!3 = !{!4, !4, i64 0} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll b/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll index 8e8d866504de5e4895bc16a59bf03f7dcc8b3985..7e7cde8a90f3942f836ca74d7a0447ecb6e3a735 100644 --- a/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll +++ b/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll @@ -1,9 +1,9 @@ ; Libdevice in recent CUDA versions relies on __CUDA_ARCH reflecting GPU type. ; Verify that __nvvm_reflect() is replaced with an appropriate value. ; -; RUN: opt %s -S -nvvm-reflect -O2 -mtriple=nvptx64 \ +; RUN: opt %s -S -passes='default' -mtriple=nvptx64 \ ; RUN: | FileCheck %s --check-prefixes=COMMON,SM20 -; RUN: opt %s -S -nvvm-reflect -O2 -mtriple=nvptx64 -mcpu=sm_35 \ +; RUN: opt %s -S -passes='default' -mtriple=nvptx64 -mcpu=sm_35 \ ; RUN: | FileCheck %s --check-prefixes=COMMON,SM35 @"$str" = private addrspace(1) constant [12 x i8] c"__CUDA_ARCH\00" diff --git a/llvm/test/CodeGen/NVPTX/nvvm-reflect.ll b/llvm/test/CodeGen/NVPTX/nvvm-reflect.ll index f7403df2cd462d5b8335779eb3eb97bd49c95b5c..ec0c787852cb12c7fdb8cf31ecb717b499f3c8bd 100644 --- a/llvm/test/CodeGen/NVPTX/nvvm-reflect.ll +++ b/llvm/test/CodeGen/NVPTX/nvvm-reflect.ll @@ -3,12 +3,12 @@ ; RUN: cat %s > %t.noftz ; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 0}' >> %t.noftz -; RUN: opt %t.noftz -S -mtriple=nvptx-nvidia-cuda -nvvm-reflect -O2 \ +; RUN: opt %t.noftz -S -mtriple=nvptx-nvidia-cuda -passes='default' \ ; RUN: | FileCheck %s --check-prefix=USE_FTZ_0 --check-prefix=CHECK ; RUN: cat %s > %t.ftz ; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 1}' >> %t.ftz -; RUN: opt %t.ftz -S -mtriple=nvptx-nvidia-cuda -nvvm-reflect -O2 \ +; RUN: opt %t.ftz -S -mtriple=nvptx-nvidia-cuda -passes='default' \ ; RUN: | FileCheck %s --check-prefix=USE_FTZ_1 --check-prefix=CHECK @str = private unnamed_addr addrspace(4) constant [11 x i8] c"__CUDA_FTZ\00" diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll b/llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll index 44438c1cc210c2f588e1af37cba3b4ad61b5860a..6a7f04b6304eb06da383f9308f7d34eeb586d9da 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll @@ -5,13 +5,14 @@ ; RUN: | FileCheck -check-prefix=RV64I %s define void @foo() { - ; RV32I-LABEL: foo - ; RV32I: # %bb.0: # %entry - ; RV32I: ret +; RV32I-LABEL: foo: +; RV32I: # %bb.0: # %entry +; RV32I-NEXT: ret +; +; RV64I-LABEL: foo: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: ret - ; RV64I-LABEL: foo - ; RV64I: # %bb.0: # %entry - ; RV64I: ret entry: ret void } diff --git a/llvm/test/CodeGen/RISCV/byval.ll b/llvm/test/CodeGen/RISCV/byval.ll index 684d3a8aab96b72b598026b516d284267c904ad0..113d5f468625d92d4a750723864d45d3d47ec7b4 100644 --- a/llvm/test/CodeGen/RISCV/byval.ll +++ b/llvm/test/CodeGen/RISCV/byval.ll @@ -33,7 +33,7 @@ define void @caller() nounwind { ; RV32I-NEXT: lw a0, 4(a0) ; RV32I-NEXT: sw a0, 16(sp) ; RV32I-NEXT: addi a0, sp, 12 -; RV32I-NEXT: call callee +; RV32I-NEXT: call callee@plt ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/calls.ll b/llvm/test/CodeGen/RISCV/calls.ll index a54d08dbbde61f0fc5f60e5aa350d881f1697806..7a964ebb4222155c1f9ed5c5e2f15085c2a71f87 100644 --- a/llvm/test/CodeGen/RISCV/calls.ll +++ b/llvm/test/CodeGen/RISCV/calls.ll @@ -71,7 +71,7 @@ define i32 @test_call_defined(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call defined_function +; RV32I-NEXT: call defined_function@plt ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -178,7 +178,7 @@ define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: call fastcc_function +; RV32I-NEXT: call fastcc_function@plt ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -282,7 +282,7 @@ define i32 @test_call_defined_many_args(i32 %a) nounwind { ; RV32I-NEXT: mv a5, a0 ; RV32I-NEXT: mv a6, a0 ; RV32I-NEXT: mv a7, a0 -; RV32I-NEXT: call defined_many_args +; RV32I-NEXT: call defined_many_args@plt ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/copy-frameindex.mir b/llvm/test/CodeGen/RISCV/copy-frameindex.mir index be86a1af8b5085ec04260b03db0c445dbfb93da0..6280874c80441a514490d5df8b5f77eec0d38d50 100644 --- a/llvm/test/CodeGen/RISCV/copy-frameindex.mir +++ b/llvm/test/CodeGen/RISCV/copy-frameindex.mir @@ -39,15 +39,19 @@ stack: body: | ; CHECK-LABEL: name: sink_addi_fi ; CHECK: bb.0: - ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) - ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10 - ; CHECK: BEQ killed [[COPY]], $x0, %bb.2 - ; CHECK: bb.1: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0, 0 - ; CHECK: SW $x0, killed [[ADDI]], 0 :: (volatile store (s32) into %stack.0) - ; CHECK: bb.2: - ; CHECK: PseudoRET + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: BEQ killed [[COPY]], $x0, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0, 0 + ; CHECK-NEXT: SW $x0, killed [[ADDI]], 0 :: (volatile store (s32) into %stack.0) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: PseudoRET bb.0: liveins: $x10 %0:gpr = COPY $x10 diff --git a/llvm/test/CodeGen/RISCV/double-calling-conv.ll b/llvm/test/CodeGen/RISCV/double-calling-conv.ll index b956611744197d33f68125d0df87307b6371e8de..5731216ba53bf810c3f1b106f1d83663fb68638d 100644 --- a/llvm/test/CodeGen/RISCV/double-calling-conv.ll +++ b/llvm/test/CodeGen/RISCV/double-calling-conv.ll @@ -41,7 +41,7 @@ define double @caller_double_inreg() nounwind { ; RV32IFD-NEXT: lui a2, 262364 ; RV32IFD-NEXT: addi a3, a2, 655 ; RV32IFD-NEXT: mv a2, a0 -; RV32IFD-NEXT: call callee_double_inreg +; RV32IFD-NEXT: call callee_double_inreg@plt ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -88,7 +88,7 @@ define double @caller_double_split_reg_stack() nounwind { ; RV32IFD-NEXT: mv a2, zero ; RV32IFD-NEXT: mv a4, zero ; RV32IFD-NEXT: mv a7, a5 -; RV32IFD-NEXT: call callee_double_split_reg_stack +; RV32IFD-NEXT: call callee_double_split_reg_stack@plt ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -135,7 +135,7 @@ define double @caller_double_stack() nounwind { ; RV32IFD-NEXT: mv a3, zero ; RV32IFD-NEXT: mv a5, zero ; RV32IFD-NEXT: mv a7, zero -; RV32IFD-NEXT: call callee_double_stack +; RV32IFD-NEXT: call callee_double_stack@plt ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll index b6969745d85456744468c7ee589a2ad05c2794d7..d3c20db19716a390a7662d9d2364907badbb6771 100644 --- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll +++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll @@ -19,7 +19,7 @@ define i32 @main() nounwind { ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: lui a1, 262144 ; RV32IFD-NEXT: mv a0, zero -; RV32IFD-NEXT: call test +; RV32IFD-NEXT: call test@plt ; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: fld ft0, 0(sp) diff --git a/llvm/test/CodeGen/RISCV/epi-alloca-gep-tuples.ll b/llvm/test/CodeGen/RISCV/epi-alloca-gep-tuples.ll index 81cba08bb4804ec888c0d02d2a7f5ed318cd4569..78b1c8656d5ce931496c03a5ddb790529ff36163 100644 --- a/llvm/test/CodeGen/RISCV/epi-alloca-gep-tuples.ll +++ b/llvm/test/CodeGen/RISCV/epi-alloca-gep-tuples.ll @@ -42,19 +42,19 @@ define @n1fv6_1() nounwind { ; CHECK-NEXT: addi a0, zero, 2 ; CHECK-NEXT: addi a1, zero, 64 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: addi a0, sp, 16 -; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: vs1r.v v8, (a0) ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: add a2, a1, a0 -; CHECK-NEXT: vs1r.v v25, (a2) +; CHECK-NEXT: vs1r.v v8, (a2) ; CHECK-NEXT: slli a2, a0, 1 ; CHECK-NEXT: add a3, a1, a2 -; CHECK-NEXT: vs1r.v v25, (a3) +; CHECK-NEXT: vs1r.v v8, (a3) ; CHECK-NEXT: add a0, a0, a2 ; CHECK-NEXT: add a0, a0, a1 -; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: vs1r.v v8, (a0) ; CHECK-NEXT: vl1re64.v v8, (a3) ; CHECK-NEXT: addi sp, sp, 48 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/epi-bitcast-vectors.ll b/llvm/test/CodeGen/RISCV/epi-bitcast-vectors.ll index ae77c9b087dc6224ecdf29d88c27765050b5f415..93a0151525570125fbf9462acd3913e04a2b3a03 100644 --- a/llvm/test/CodeGen/RISCV/epi-bitcast-vectors.ll +++ b/llvm/test/CodeGen/RISCV/epi-bitcast-vectors.ll @@ -13,9 +13,9 @@ define void @foo_1(i64 %gvl, * %src, * %d ; CHECK-LABEL: foo_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vse64.v v25, (a2) +; CHECK-NEXT: vse64.v v8, (a2) ; CHECK-NEXT: ret %a = call @llvm.epi.vload.v2i32( *%src, i64 %gvl) %b = bitcast %a to @@ -28,8 +28,8 @@ define void @foo_2(i64 %gvl, * %src, * %ds ; CHECK-LABEL: foo_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a1) -; CHECK-NEXT: vse32.v v25, (a2) +; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %a = call @llvm.epi.vload.v2i32( *%src, i64 %gvl) %b = bitcast %a to @@ -41,8 +41,8 @@ define void @foo_3(i64 %gvl, * %src, * %ds ; CHECK-LABEL: foo_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vse32.v v26, (a2) +; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %a = call @llvm.epi.vload.v4i32( *%src, i64 %gvl) %b = bitcast %a to @@ -56,8 +56,8 @@ define void @foo_3(i64 %gvl, * %src, * %ds define void @foo_5(* %src, * %dst) nounwind { ; CHECK-LABEL: foo_5: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re32.v v25, (a0) -; CHECK-NEXT: vs1r.v v25, (a1) +; CHECK-NEXT: vl1re32.v v8, (a0) +; CHECK-NEXT: vs1r.v v8, (a1) ; CHECK-NEXT: ret %a = load , *%src %b = bitcast %a to diff --git a/llvm/test/CodeGen/RISCV/epi-conversion-mixed-sew.ll b/llvm/test/CodeGen/RISCV/epi-conversion-mixed-sew.ll index 2ccee9145c3c0f1c4a03caa5745b097a7745afe4..e15677537db97cad462740d7be14e70303a61b49 100644 --- a/llvm/test/CodeGen/RISCV/epi-conversion-mixed-sew.ll +++ b/llvm/test/CodeGen/RISCV/epi-conversion-mixed-sew.ll @@ -11,8 +11,8 @@ define @test_widen_float_to_uint( %parm0, ; CHECK-LABEL: test_widen_float_to_uint: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.xu.f.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.xu.f.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.epi.vfwcvt.xu.f.nxv2i64.nxv2f32( @@ -28,8 +28,8 @@ define @test_widen_float_to_int( %parm0, ; CHECK-LABEL: test_widen_float_to_int: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.x.f.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.x.f.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.epi.vfwcvt.x.f.nxv2i64.nxv2f32( @@ -45,8 +45,8 @@ define @test_widen_uint_to_float( %parm0 ; CHECK-LABEL: test_widen_uint_to_float: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.xu.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.f.xu.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.epi.vfwcvt.f.xu.nxv2f64.nxv2i32( @@ -63,8 +63,8 @@ define @test_widen_int_to_float( %parm0, ; CHECK-LABEL: test_widen_int_to_float: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.x.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.f.x.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.epi.vfwcvt.f.x.nxv2f64.nxv2i32( @@ -81,8 +81,8 @@ define @test_widen_float_to_float( %pa ; CHECK-LABEL: test_widen_float_to_float: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.f.f.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.epi.vfwcvt.f.f.nxv2f64.nxv2f32( @@ -99,8 +99,8 @@ define @test_widen_int_to_uint( %parm0, i64 ; CHECK-LABEL: test_widen_int_to_uint: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vwcvtu.x.x.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vwcvtu.x.x.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.epi.vwcvtu.x.x.nxv2i64.nxv2i32( @@ -117,8 +117,8 @@ define @test_widen_int_to_int( %parm0, i64 ; CHECK-LABEL: test_widen_int_to_int: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vwcvt.x.x.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vwcvt.x.x.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.epi.vwcvt.x.x.nxv2i64.nxv2i32( @@ -135,8 +135,8 @@ define @test_narrow_float_to_uint( %parm ; CHECK-LABEL: test_narrow_float_to_uint: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.xu.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.xu.f.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.epi.vfncvt.xu.f.nxv2i32.nxv2f64( @@ -152,8 +152,8 @@ define @test_narrow_float_to_int( %parm0 ; CHECK-LABEL: test_narrow_float_to_int: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.x.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.x.f.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.epi.vfncvt.x.f.nxv2i32.nxv2f64( @@ -169,8 +169,8 @@ define @test_narrow_uint_to_float( %parm0 ; CHECK-LABEL: test_narrow_uint_to_float: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.xu.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.epi.vfncvt.f.xu.nxv2f32.nxv2i64( @@ -187,8 +187,8 @@ define @test_narrow_int_to_float( %parm0, ; CHECK-LABEL: test_narrow_int_to_float: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.x.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.epi.vfncvt.f.x.nxv2f32.nxv2i64( @@ -205,8 +205,8 @@ define @test_narrow_float_to_float( %p ; CHECK-LABEL: test_narrow_float_to_float: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.f.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.f.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.epi.vfncvt.f.f.nxv2f32.nxv2f64( @@ -223,8 +223,8 @@ define @test_narrow_int_to_int( %parm0, i64 ; CHECK-LABEL: test_narrow_int_to_int: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vncvt.x.x.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vncvt.x.x.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.epi.vncvt.x.x.nxv2i32.nxv2i64( diff --git a/llvm/test/CodeGen/RISCV/epi-dead-object-epivr-spill.ll b/llvm/test/CodeGen/RISCV/epi-dead-object-epivr-spill.ll index edae5054ea33a0c348a8ed537bfecd13a4045f81..5753d2357ee397cf5bbb24fb359531c0bcf3e900 100644 --- a/llvm/test/CodeGen/RISCV/epi-dead-object-epivr-spill.ll +++ b/llvm/test/CodeGen/RISCV/epi-dead-object-epivr-spill.ll @@ -22,260 +22,260 @@ define void @n1fv_32(double* %ri, double* %ii, double* %ro, double* %io, i64 %is ; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: addi s4, zero, 8 ; CHECK-NEXT: vsetvli zero, s4, e64, m1, ta, mu -; CHECK-NEXT: vid.v v26 +; CHECK-NEXT: vid.v v10 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a0, a0, 16 -; CHECK-NEXT: vs1r.v v26, (a0) # Unknown-size Folded Spill -; CHECK-NEXT: vsrl.vi v25, v26, 1 +; CHECK-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill +; CHECK-NEXT: vsrl.vi v8, v10, 1 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a1, a0, 1 ; CHECK-NEXT: add a0, a1, a0 ; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a0, a0, 16 -; CHECK-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill -; CHECK-NEXT: vmul.vx v25, v25, a0 -; CHECK-NEXT: vand.vi v8, v26, 1 +; CHECK-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill +; CHECK-NEXT: vmul.vx v9, v8, a0 +; CHECK-NEXT: vand.vi v8, v10, 1 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill -; CHECK-NEXT: vmul.vv v26, v8, v25 +; CHECK-NEXT: vmul.vv v10, v8, v8 ; CHECK-NEXT: addi a0, sp, 16 -; CHECK-NEXT: vs1r.v v26, (a0) # Unknown-size Folded Spill -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a0, a0, 16 -; CHECK-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill +; CHECK-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: call llvm.epi.mask.cast.nxv1i1.nxv1i64@plt ; CHECK-NEXT: vsetvli zero, s4, e64, m1, ta, mu ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a0, a0, 16 -; CHECK-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload -; CHECK-NEXT: vxor.vi v26, v25, 1 +; CHECK-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload +; CHECK-NEXT: vxor.vi v9, v8, 1 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a1, a0, 1 ; CHECK-NEXT: add a0, a1, a0 ; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a0, a0, 16 -; CHECK-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload -; CHECK-NEXT: vmul.vv v25, v25, v25 +; CHECK-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload +; CHECK-NEXT: vmul.vv v8, v8, v8 ; CHECK-NEXT: addi a0, sp, 16 -; CHECK-NEXT: vl1r.v v27, (a0) # Unknown-size Folded Reload -; CHECK-NEXT: vadd.vv v25, v25, v27 +; CHECK-NEXT: vl1r.v v10, (a0) # Unknown-size Folded Reload +; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a0, a0, 16 -; CHECK-NEXT: vl1r.v v21, (a0) # Unknown-size Folded Reload -; CHECK-NEXT: vluxei64.v v12, (a0), v21 +; CHECK-NEXT: vl1r.v v28, (a0) # Unknown-size Folded Reload +; CHECK-NEXT: vluxei64.v v19, (a0), v28 ; CHECK-NEXT: slli a0, s0, 7 ; CHECK-NEXT: add a0, s1, a0 -; CHECK-NEXT: vluxei64.v v27, (a0), v21 +; CHECK-NEXT: vluxei64.v v10, (a0), v28 ; CHECK-NEXT: addi a0, zero, 192 ; CHECK-NEXT: mul a0, s0, a0 ; CHECK-NEXT: add a0, s1, a0 -; CHECK-NEXT: vluxei64.v v28, (a0), v21 +; CHECK-NEXT: vluxei64.v v11, (a0), v28 ; CHECK-NEXT: slli a1, s0, 4 -; CHECK-NEXT: vfsub.vv v29, v12, v27 -; CHECK-NEXT: vfadd.vv v30, v12, v27 -; CHECK-NEXT: vfsub.vv v27, v25, v28 +; CHECK-NEXT: vfsub.vv v12, v19, v10 +; CHECK-NEXT: vfadd.vv v13, v19, v10 +; CHECK-NEXT: vfsub.vv v10, v8, v11 ; CHECK-NEXT: slli a0, s0, 5 ; CHECK-NEXT: add a0, s1, a0 -; CHECK-NEXT: vluxei64.v v31, (a0), v21 +; CHECK-NEXT: vluxei64.v v14, (a0), v28 ; CHECK-NEXT: addi a0, zero, 160 ; CHECK-NEXT: mul a0, s0, a0 ; CHECK-NEXT: add a0, s1, a0 -; CHECK-NEXT: vluxei64.v v8, (a0), v21 +; CHECK-NEXT: vluxei64.v v15, (a0), v28 ; CHECK-NEXT: addi a0, zero, 224 ; CHECK-NEXT: mul a0, s0, a0 ; CHECK-NEXT: add a0, s1, a0 -; CHECK-NEXT: vluxei64.v v9, (a0), v21 +; CHECK-NEXT: vluxei64.v v16, (a0), v28 ; CHECK-NEXT: addi a0, zero, 96 ; CHECK-NEXT: mul a0, s0, a0 ; CHECK-NEXT: add a0, s1, a0 -; CHECK-NEXT: vluxei64.v v10, (a0), v21 -; CHECK-NEXT: vfadd.vv v28, v25, v28 -; CHECK-NEXT: vfsub.vv v11, v31, v8 -; CHECK-NEXT: vfadd.vv v31, v31, v8 -; CHECK-NEXT: vfsub.vv v8, v9, v10 -; CHECK-NEXT: vfadd.vv v13, v9, v10 -; CHECK-NEXT: vfadd.vv v9, v30, v28 -; CHECK-NEXT: vfadd.vv v10, v31, v13 -; CHECK-NEXT: vfsub.vv v30, v13, v31 -; CHECK-NEXT: vfsub.vv v28, v8, v11 -; CHECK-NEXT: vfmacc.vv v27, v25, v28 -; CHECK-NEXT: vfmsac.vv v29, v25, v25 -; CHECK-NEXT: vfneg.v v28, v29 -; CHECK-NEXT: vfadd.vv v31, v25, v12 -; CHECK-NEXT: vfadd.vv v8, v12, v12 -; CHECK-NEXT: vfadd.vv v11, v25, v25 -; CHECK-NEXT: vfmsac.vv v29, v25, v25 -; CHECK-NEXT: vfneg.v v29, v29 -; CHECK-NEXT: vfadd.vv v13, v8, v11 +; CHECK-NEXT: vluxei64.v v17, (a0), v28 +; CHECK-NEXT: vfadd.vv v11, v8, v11 +; CHECK-NEXT: vfsub.vv v18, v14, v15 +; CHECK-NEXT: vfadd.vv v14, v14, v15 +; CHECK-NEXT: vfsub.vv v15, v16, v17 +; CHECK-NEXT: vfadd.vv v20, v16, v17 +; CHECK-NEXT: vfadd.vv v16, v13, v11 +; CHECK-NEXT: vfadd.vv v17, v14, v20 +; CHECK-NEXT: vfsub.vv v13, v20, v14 +; CHECK-NEXT: vfsub.vv v11, v15, v18 +; CHECK-NEXT: vfmacc.vv v10, v8, v11 +; CHECK-NEXT: vfmsac.vv v12, v8, v8 +; CHECK-NEXT: vfneg.v v11, v12 +; CHECK-NEXT: vfadd.vv v14, v8, v19 +; CHECK-NEXT: vfadd.vv v15, v19, v19 +; CHECK-NEXT: vfadd.vv v18, v8, v8 +; CHECK-NEXT: vfmsac.vv v12, v8, v8 +; CHECK-NEXT: vfneg.v v12, v12 +; CHECK-NEXT: vfadd.vv v20, v15, v18 ; CHECK-NEXT: lui a0, %hi(.LCPI0_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI0_0)(a0) -; CHECK-NEXT: vfsub.vv v16, v25, v13 -; CHECK-NEXT: vfsub.vv v31, v25, v31 -; CHECK-NEXT: vfsub.vv v8, v11, v8 -; CHECK-NEXT: vmv1r.v v11, v31 -; CHECK-NEXT: vfmsac.vf v11, ft0, v8 -; CHECK-NEXT: vfneg.v v11, v11 +; CHECK-NEXT: vfsub.vv v23, v8, v20 +; CHECK-NEXT: vfsub.vv v14, v8, v14 +; CHECK-NEXT: vfsub.vv v15, v18, v15 +; CHECK-NEXT: vmv1r.v v18, v14 +; CHECK-NEXT: vfmsac.vf v18, ft0, v15 +; CHECK-NEXT: vfneg.v v18, v18 ; CHECK-NEXT: addi a0, zero, 136 ; CHECK-NEXT: mul a0, s0, a0 ; CHECK-NEXT: add a0, s1, a0 -; CHECK-NEXT: vluxei64.v v13, (a0), v21 -; CHECK-NEXT: vluxei64.v v14, (s1), v21 +; CHECK-NEXT: vluxei64.v v20, (a0), v28 +; CHECK-NEXT: vluxei64.v v21, (s1), v28 ; CHECK-NEXT: addi a0, zero, 104 ; CHECK-NEXT: mul a2, s0, a0 ; CHECK-NEXT: add a2, s1, a2 -; CHECK-NEXT: vluxei64.v v15, (a2), v21 -; CHECK-NEXT: vfmacc.vf v8, ft0, v31 -; CHECK-NEXT: vfsub.vv v31, v12, v13 -; CHECK-NEXT: vfadd.vv v13, v12, v13 -; CHECK-NEXT: vfsub.vv v17, v14, v15 -; CHECK-NEXT: vfadd.vv v14, v14, v15 -; CHECK-NEXT: vfadd.vv v15, v25, v17 -; CHECK-NEXT: vfmsac.vv v31, v25, v15 -; CHECK-NEXT: vfneg.v v31, v31 -; CHECK-NEXT: vfsub.vv v15, v13, v25 -; CHECK-NEXT: vfsub.vv v13, v25, v14 -; CHECK-NEXT: vmv1r.v v14, v15 -; CHECK-NEXT: vfmsac.vf v14, ft0, v13 +; CHECK-NEXT: vluxei64.v v22, (a2), v28 +; CHECK-NEXT: vfmacc.vf v15, ft0, v14 +; CHECK-NEXT: vfsub.vv v14, v19, v20 +; CHECK-NEXT: vfadd.vv v20, v19, v20 +; CHECK-NEXT: vfsub.vv v24, v21, v22 +; CHECK-NEXT: vfadd.vv v21, v21, v22 +; CHECK-NEXT: vfadd.vv v22, v8, v24 +; CHECK-NEXT: vfmsac.vv v14, v8, v22 ; CHECK-NEXT: vfneg.v v14, v14 +; CHECK-NEXT: vfsub.vv v22, v20, v8 +; CHECK-NEXT: vfsub.vv v20, v8, v21 +; CHECK-NEXT: vmv1r.v v21, v22 +; CHECK-NEXT: vfmsac.vf v21, ft0, v20 +; CHECK-NEXT: vfneg.v v21, v21 ; CHECK-NEXT: add a1, s1, a1 -; CHECK-NEXT: vluxei64.v v17, (a1), v21 +; CHECK-NEXT: vluxei64.v v24, (a1), v28 ; CHECK-NEXT: addi a1, zero, 48 ; CHECK-NEXT: mul a1, s0, a1 ; CHECK-NEXT: add a1, s1, a1 -; CHECK-NEXT: vluxei64.v v18, (a1), v21 -; CHECK-NEXT: vfmacc.vf v13, ft0, v15 -; CHECK-NEXT: vfsub.vv v15, v17, v12 -; CHECK-NEXT: vfadd.vv v17, v17, v12 -; CHECK-NEXT: vfsub.vv v19, v25, v18 +; CHECK-NEXT: vluxei64.v v25, (a1), v28 +; CHECK-NEXT: vfmacc.vf v20, ft0, v22 +; CHECK-NEXT: vfsub.vv v22, v24, v19 +; CHECK-NEXT: vfadd.vv v24, v24, v19 +; CHECK-NEXT: vfsub.vv v26, v8, v25 ; CHECK-NEXT: addi a1, zero, 80 ; CHECK-NEXT: mul a1, s0, a1 ; CHECK-NEXT: add a1, s1, a1 -; CHECK-NEXT: vluxei64.v v20, (a1), v21 +; CHECK-NEXT: vluxei64.v v27, (a1), v28 ; CHECK-NEXT: addi a1, zero, 240 ; CHECK-NEXT: mul a1, s0, a1 ; CHECK-NEXT: add a1, s1, a1 -; CHECK-NEXT: vluxei64.v v21, (a1), v21 -; CHECK-NEXT: vfadd.vv v18, v18, v25 -; CHECK-NEXT: vfsub.vv v22, v20, v25 -; CHECK-NEXT: vfadd.vv v20, v20, v25 -; CHECK-NEXT: vfsub.vv v23, v21, v12 -; CHECK-NEXT: vfadd.vv v12, v21, v12 -; CHECK-NEXT: vfadd.vv v18, v12, v18 -; CHECK-NEXT: vfadd.vv v21, v17, v20 -; CHECK-NEXT: vmv1r.v v12, v15 -; CHECK-NEXT: vfmsac.vf v12, ft0, v22 -; CHECK-NEXT: vfneg.v v12, v12 -; CHECK-NEXT: vmv1r.v v24, v23 -; CHECK-NEXT: vfmsac.vf v24, ft0, v19 -; CHECK-NEXT: vfneg.v v24, v24 -; CHECK-NEXT: vfsub.vv v12, v24, v12 -; CHECK-NEXT: vfmacc.vf v22, ft0, v15 -; CHECK-NEXT: vfmacc.vf v19, ft0, v23 -; CHECK-NEXT: vfadd.vv v15, v22, v19 -; CHECK-NEXT: vfsub.vv v17, v17, v20 -; CHECK-NEXT: vfsub.vv v19, v9, v10 -; CHECK-NEXT: vfsub.vv v17, v25, v17 -; CHECK-NEXT: vmv1r.v v20, v19 -; CHECK-NEXT: vfmsac.vv v20, v25, v25 -; CHECK-NEXT: vfneg.v v20, v20 -; CHECK-NEXT: vfmacc.vv v19, v25, v25 -; CHECK-NEXT: vfsub.vv v22, v18, v21 -; CHECK-NEXT: vfsub.vv v16, v16, v25 -; CHECK-NEXT: vmv1r.v v23, v22 -; CHECK-NEXT: vfmsac.vv v23, v25, v16 -; CHECK-NEXT: vfneg.v v23, v23 -; CHECK-NEXT: vfmacc.vv v22, v25, v16 -; CHECK-NEXT: vfneg.v v23, v23, v0.t -; CHECK-NEXT: vrgather.vv v16, v23, v26 -; CHECK-NEXT: vfsub.vv v23, v20, v16 +; CHECK-NEXT: vluxei64.v v28, (a1), v28 +; CHECK-NEXT: vfadd.vv v25, v25, v8 +; CHECK-NEXT: vfsub.vv v29, v27, v8 +; CHECK-NEXT: vfadd.vv v27, v27, v8 +; CHECK-NEXT: vfsub.vv v30, v28, v19 +; CHECK-NEXT: vfadd.vv v19, v28, v19 +; CHECK-NEXT: vfadd.vv v25, v19, v25 +; CHECK-NEXT: vfadd.vv v28, v24, v27 +; CHECK-NEXT: vmv1r.v v19, v22 +; CHECK-NEXT: vfmsac.vf v19, ft0, v29 +; CHECK-NEXT: vfneg.v v19, v19 +; CHECK-NEXT: vmv1r.v v31, v30 +; CHECK-NEXT: vfmsac.vf v31, ft0, v26 +; CHECK-NEXT: vfneg.v v31, v31 +; CHECK-NEXT: vfsub.vv v19, v31, v19 +; CHECK-NEXT: vfmacc.vf v29, ft0, v22 +; CHECK-NEXT: vfmacc.vf v26, ft0, v30 +; CHECK-NEXT: vfadd.vv v22, v29, v26 +; CHECK-NEXT: vfsub.vv v24, v24, v27 +; CHECK-NEXT: vfsub.vv v26, v16, v17 +; CHECK-NEXT: vfsub.vv v24, v8, v24 +; CHECK-NEXT: vmv1r.v v27, v26 +; CHECK-NEXT: vfmsac.vv v27, v8, v8 +; CHECK-NEXT: vfneg.v v27, v27 +; CHECK-NEXT: vfmacc.vv v26, v8, v8 +; CHECK-NEXT: vfsub.vv v29, v25, v28 +; CHECK-NEXT: vfsub.vv v23, v23, v8 +; CHECK-NEXT: vmv1r.v v30, v29 +; CHECK-NEXT: vfmsac.vv v30, v8, v23 +; CHECK-NEXT: vfneg.v v30, v30 +; CHECK-NEXT: vfmacc.vv v29, v8, v23 +; CHECK-NEXT: vfneg.v v30, v30, v0.t +; CHECK-NEXT: vrgather.vv v23, v30, v9 +; CHECK-NEXT: vfsub.vv v30, v27, v23 ; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: slli a1, a1, 2 ; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: vl1r.v v1, (a1) # Unknown-size Folded Reload -; CHECK-NEXT: vrgather.vv v24, v23, v1 -; CHECK-NEXT: vsuxei64.v v24, (a0), v25 +; CHECK-NEXT: vrgather.vv v31, v30, v1 +; CHECK-NEXT: vsuxei64.v v31, (a0), v8 ; CHECK-NEXT: slli a1, s2, 5 ; CHECK-NEXT: add a1, s3, a1 -; CHECK-NEXT: vfneg.v v22, v22, v0.t -; CHECK-NEXT: vrgather.vv v23, v22, v26 -; CHECK-NEXT: vfadd.vv v22, v19, v23 -; CHECK-NEXT: vrgather.vv v24, v22, v1 -; CHECK-NEXT: vsuxei64.v v24, (a1), v25 -; CHECK-NEXT: vfadd.vv v16, v20, v16 -; CHECK-NEXT: vrgather.vv v20, v16, v1 -; CHECK-NEXT: vsuxei64.v v20, (a0), v25 -; CHECK-NEXT: vfsub.vv v16, v19, v23 -; CHECK-NEXT: vrgather.vv v19, v16, v1 -; CHECK-NEXT: vsuxei64.v v19, (a0), v25 -; CHECK-NEXT: vfadd.vv v9, v9, v10 -; CHECK-NEXT: vfadd.vv v10, v21, v18 -; CHECK-NEXT: vfadd.vv v9, v9, v10 -; CHECK-NEXT: vrgather.vv v10, v25, v1 -; CHECK-NEXT: vsuxei64.v v25, (a0), v25 -; CHECK-NEXT: vfadd.vv v9, v9, v25 -; CHECK-NEXT: vrgather.vv v16, v9, v1 -; CHECK-NEXT: vsuxei64.v v16, (a0), v25 -; CHECK-NEXT: vsuxei64.v v10, (a0), v25 -; CHECK-NEXT: vsuxei64.v v25, (a0), v25 +; CHECK-NEXT: vfneg.v v29, v29, v0.t +; CHECK-NEXT: vrgather.vv v30, v29, v9 +; CHECK-NEXT: vfadd.vv v29, v26, v30 +; CHECK-NEXT: vrgather.vv v31, v29, v1 +; CHECK-NEXT: vsuxei64.v v31, (a1), v8 +; CHECK-NEXT: vfadd.vv v23, v27, v23 +; CHECK-NEXT: vrgather.vv v27, v23, v1 +; CHECK-NEXT: vsuxei64.v v27, (a0), v8 +; CHECK-NEXT: vfsub.vv v23, v26, v30 +; CHECK-NEXT: vrgather.vv v26, v23, v1 +; CHECK-NEXT: vsuxei64.v v26, (a0), v8 +; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v17, v28, v25 +; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vrgather.vv v17, v8, v1 +; CHECK-NEXT: vsuxei64.v v8, (a0), v8 +; CHECK-NEXT: vfadd.vv v16, v16, v8 +; CHECK-NEXT: vrgather.vv v23, v16, v1 +; CHECK-NEXT: vsuxei64.v v23, (a0), v8 +; CHECK-NEXT: vsuxei64.v v17, (a0), v8 +; CHECK-NEXT: vsuxei64.v v8, (a0), v8 ; CHECK-NEXT: addi a1, zero, 208 ; CHECK-NEXT: mul a1, s2, a1 ; CHECK-NEXT: lui a2, %hi(.LCPI0_1) ; CHECK-NEXT: fld ft0, %lo(.LCPI0_1)(a2) ; CHECK-NEXT: add a1, s3, a1 -; CHECK-NEXT: vsuxei64.v v10, (a1), v25 -; CHECK-NEXT: vfadd.vv v9, v14, v11 -; CHECK-NEXT: vfmsac.vf v9, ft0, v9 -; CHECK-NEXT: vfneg.v v9, v9 -; CHECK-NEXT: vfmacc.vv v30, v25, v17 -; CHECK-NEXT: vfsub.vv v8, v8, v13 -; CHECK-NEXT: vfmacc.vf v30, ft0, v8 +; CHECK-NEXT: vsuxei64.v v17, (a1), v8 +; CHECK-NEXT: vfadd.vv v16, v21, v18 +; CHECK-NEXT: vfmsac.vf v16, ft0, v16 +; CHECK-NEXT: vfneg.v v16, v16 +; CHECK-NEXT: vfmacc.vv v13, v8, v24 +; CHECK-NEXT: vfsub.vv v15, v15, v20 +; CHECK-NEXT: vfmacc.vf v13, ft0, v15 ; CHECK-NEXT: addi a1, zero, 112 ; CHECK-NEXT: mul a1, s2, a1 ; CHECK-NEXT: add a1, s3, a1 -; CHECK-NEXT: vrgather.vv v8, v25, v26 -; CHECK-NEXT: vfsub.vv v8, v9, v8 -; CHECK-NEXT: vrgather.vv v9, v8, v1 -; CHECK-NEXT: vsuxei64.v v9, (a1), v25 -; CHECK-NEXT: vfneg.v v30, v30, v0.t -; CHECK-NEXT: vrgather.vv v8, v30, v26 -; CHECK-NEXT: vfadd.vv v30, v25, v8 -; CHECK-NEXT: vrgather.vv v8, v30, v1 -; CHECK-NEXT: vfmacc.vf v28, ft0, v15 -; CHECK-NEXT: vfmacc.vf v27, ft0, v12 +; CHECK-NEXT: vrgather.vv v15, v8, v9 +; CHECK-NEXT: vfsub.vv v15, v16, v15 +; CHECK-NEXT: vrgather.vv v16, v15, v1 +; CHECK-NEXT: vsuxei64.v v16, (a1), v8 +; CHECK-NEXT: vfneg.v v13, v13, v0.t +; CHECK-NEXT: vrgather.vv v15, v13, v9 +; CHECK-NEXT: vfadd.vv v13, v8, v15 +; CHECK-NEXT: vrgather.vv v15, v13, v1 +; CHECK-NEXT: vfmacc.vf v11, ft0, v22 +; CHECK-NEXT: vfmacc.vf v10, ft0, v19 ; CHECK-NEXT: lui a1, %hi(.LCPI0_2) ; CHECK-NEXT: fld ft0, %lo(.LCPI0_2)(a1) -; CHECK-NEXT: vsuxei64.v v8, (a0), v25 -; CHECK-NEXT: vsuxei64.v v25, (a0), v25 -; CHECK-NEXT: vfneg.v v30, v25 -; CHECK-NEXT: vfmsac.vf v29, ft0, v25 -; CHECK-NEXT: vfmacc.vf v31, ft0, v25 +; CHECK-NEXT: vsuxei64.v v15, (a0), v8 +; CHECK-NEXT: vsuxei64.v v8, (a0), v8 +; CHECK-NEXT: vfneg.v v13, v8 +; CHECK-NEXT: vfmsac.vf v12, ft0, v8 +; CHECK-NEXT: vfmacc.vf v14, ft0, v8 ; CHECK-NEXT: lui a1, %hi(.LCPI0_3) ; CHECK-NEXT: fld ft0, %lo(.LCPI0_3)(a1) -; CHECK-NEXT: vfneg.v v29, v29 -; CHECK-NEXT: vfsub.vv v29, v30, v29 -; CHECK-NEXT: vfadd.vv v30, v31, v25 -; CHECK-NEXT: vfmsac.vf v28, ft0, v30 -; CHECK-NEXT: vfneg.v v28, v28 -; CHECK-NEXT: vfmsac.vf v27, ft0, v29 -; CHECK-NEXT: vfneg.v v27, v27 +; CHECK-NEXT: vfneg.v v12, v12 +; CHECK-NEXT: vfsub.vv v12, v13, v12 +; CHECK-NEXT: vfadd.vv v13, v14, v8 +; CHECK-NEXT: vfmsac.vf v11, ft0, v13 +; CHECK-NEXT: vfneg.v v11, v11 +; CHECK-NEXT: vfmsac.vf v10, ft0, v12 +; CHECK-NEXT: vfneg.v v10, v10 ; CHECK-NEXT: mul a0, s2, a0 ; CHECK-NEXT: add a0, s3, a0 -; CHECK-NEXT: vfneg.v v27, v27, v0.t -; CHECK-NEXT: vrgather.vv v29, v27, v26 -; CHECK-NEXT: vfsub.vv v26, v28, v29 -; CHECK-NEXT: vrgather.vv v27, v26, v1 -; CHECK-NEXT: vsuxei64.v v27, (a0), v25 +; CHECK-NEXT: vfneg.v v10, v10, v0.t +; CHECK-NEXT: vrgather.vv v12, v10, v9 +; CHECK-NEXT: vfsub.vv v9, v11, v12 +; CHECK-NEXT: vrgather.vv v10, v9, v1 +; CHECK-NEXT: vsuxei64.v v10, (a0), v8 entry: %0 = tail call @llvm.epi.vfmv.v.f.nxv1f64.f64(double 0x3FEA9B66290EA1A3, i64 8) %1 = tail call @llvm.epi.vfmv.v.f.nxv1f64.f64(double 0x3FE561B82AB7F990, i64 8) diff --git a/llvm/test/CodeGen/RISCV/epi-fp-scalar.ll b/llvm/test/CodeGen/RISCV/epi-fp-scalar.ll index f0a8ea8452e7b3dd46f079af13fade1747b0b1a9..ad3e8f916707b1a41cc8f3516a4f9542605ef84a 100644 --- a/llvm/test/CodeGen/RISCV/epi-fp-scalar.ll +++ b/llvm/test/CodeGen/RISCV/epi-fp-scalar.ll @@ -9,8 +9,8 @@ define float @test_fp_ret_f32( %a) nounwind { ; CHECK-LABEL: test_fp_ret_f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfadd.vv v25, v8, v8 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfadd.vv v8, v8, v8 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: # kill: def $f10_f killed $f10_f killed $f10_d ; CHECK-NEXT: ret %add = fadd %a, %a @@ -22,8 +22,8 @@ define double @test_fp_ret_f64( %a) nounwind { ; CHECK-LABEL: test_fp_ret_f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfadd.vv v25, v8, v8 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfadd.vv v8, v8, v8 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %add = fadd %a, %a %first = call double @llvm.epi.vfmv.f.s.f64.nxv1f64( %add) diff --git a/llvm/test/CodeGen/RISCV/epi-full-vector-logical.ll b/llvm/test/CodeGen/RISCV/epi-full-vector-logical.ll index 8d183e7b05a1c87ab39b5be038be418c0b777c5e..e6c5573a3ed7658007bbe4cb2f9e5ab0a30337cb 100644 --- a/llvm/test/CodeGen/RISCV/epi-full-vector-logical.ll +++ b/llvm/test/CodeGen/RISCV/epi-full-vector-logical.ll @@ -9,12 +9,12 @@ define void @nxv1i1( %a, %b) nounwind { ; CHECK-NEXT: lui a0, %hi(scratch) ; CHECK-NEXT: addi a0, a0, %lo(scratch) ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmand.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmor.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmxor.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmand.mm v9, v0, v8 +; CHECK-NEXT: vsm.v v9, (a0) +; CHECK-NEXT: vmor.mm v9, v0, v8 +; CHECK-NEXT: vsm.v v9, (a0) +; CHECK-NEXT: vmxor.mm v8, v0, v8 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -36,12 +36,12 @@ define void @nxv2i1( %a, %b) nounwind { ; CHECK-NEXT: lui a0, %hi(scratch) ; CHECK-NEXT: addi a0, a0, %lo(scratch) ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmand.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmor.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmxor.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmand.mm v9, v0, v8 +; CHECK-NEXT: vsm.v v9, (a0) +; CHECK-NEXT: vmor.mm v9, v0, v8 +; CHECK-NEXT: vsm.v v9, (a0) +; CHECK-NEXT: vmxor.mm v8, v0, v8 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -63,12 +63,12 @@ define void @nxv4i1( %a, %b) nounwind { ; CHECK-NEXT: lui a0, %hi(scratch) ; CHECK-NEXT: addi a0, a0, %lo(scratch) ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmand.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmor.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmxor.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmand.mm v9, v0, v8 +; CHECK-NEXT: vsm.v v9, (a0) +; CHECK-NEXT: vmor.mm v9, v0, v8 +; CHECK-NEXT: vsm.v v9, (a0) +; CHECK-NEXT: vmxor.mm v8, v0, v8 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -90,12 +90,12 @@ define void @nxv8i1( %a, %b) nounwind { ; CHECK-NEXT: lui a0, %hi(scratch) ; CHECK-NEXT: addi a0, a0, %lo(scratch) ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmand.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmor.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmxor.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmand.mm v9, v0, v8 +; CHECK-NEXT: vsm.v v9, (a0) +; CHECK-NEXT: vmor.mm v9, v0, v8 +; CHECK-NEXT: vsm.v v9, (a0) +; CHECK-NEXT: vmxor.mm v8, v0, v8 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -117,12 +117,12 @@ define void @nxv16i1( %a, %b) nounwind { ; CHECK-NEXT: lui a0, %hi(scratch) ; CHECK-NEXT: addi a0, a0, %lo(scratch) ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmand.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmor.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmxor.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmand.mm v9, v0, v8 +; CHECK-NEXT: vsm.v v9, (a0) +; CHECK-NEXT: vmor.mm v9, v0, v8 +; CHECK-NEXT: vsm.v v9, (a0) +; CHECK-NEXT: vmxor.mm v8, v0, v8 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -144,12 +144,12 @@ define void @nxv32i1( %a, %b) nounwind { ; CHECK-NEXT: lui a0, %hi(scratch) ; CHECK-NEXT: addi a0, a0, %lo(scratch) ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmand.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmor.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmxor.mm v25, v0, v8 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmand.mm v9, v0, v8 +; CHECK-NEXT: vsm.v v9, (a0) +; CHECK-NEXT: vmor.mm v9, v0, v8 +; CHECK-NEXT: vsm.v v9, (a0) +; CHECK-NEXT: vmxor.mm v8, v0, v8 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to * diff --git a/llvm/test/CodeGen/RISCV/epi-full-vector-rel.ll b/llvm/test/CodeGen/RISCV/epi-full-vector-rel.ll index d9702665cf8240907ec5a3b5d0e9dc3b2004c068..8beb6594ead70c53ccca0ad44a27479eb2fb0529 100644 --- a/llvm/test/CodeGen/RISCV/epi-full-vector-rel.ll +++ b/llvm/test/CodeGen/RISCV/epi-full-vector-rel.ll @@ -9,26 +9,26 @@ define void @lmul_1( %a, %b) nounwind { ; CHECK-NEXT: lui a0, %hi(scratch) ; CHECK-NEXT: addi a0, a0, %lo(scratch) ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vmseq.vv v25, v8, v9 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsne.vv v25, v8, v9 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsltu.vv v25, v9, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsleu.vv v25, v9, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsltu.vv v25, v8, v9 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsleu.vv v25, v8, v9 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmslt.vv v25, v9, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsle.vv v25, v9, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmslt.vv v25, v8, v9 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsle.vv v25, v8, v9 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmseq.vv v10, v8, v9 +; CHECK-NEXT: vsm.v v10, (a0) +; CHECK-NEXT: vmsne.vv v10, v8, v9 +; CHECK-NEXT: vsm.v v10, (a0) +; CHECK-NEXT: vmsltu.vv v10, v9, v8 +; CHECK-NEXT: vsm.v v10, (a0) +; CHECK-NEXT: vmsleu.vv v10, v9, v8 +; CHECK-NEXT: vsm.v v10, (a0) +; CHECK-NEXT: vmsltu.vv v10, v8, v9 +; CHECK-NEXT: vsm.v v10, (a0) +; CHECK-NEXT: vmsleu.vv v10, v8, v9 +; CHECK-NEXT: vsm.v v10, (a0) +; CHECK-NEXT: vmslt.vv v10, v9, v8 +; CHECK-NEXT: vsm.v v10, (a0) +; CHECK-NEXT: vmsle.vv v10, v9, v8 +; CHECK-NEXT: vsm.v v10, (a0) +; CHECK-NEXT: vmslt.vv v10, v8, v9 +; CHECK-NEXT: vsm.v v10, (a0) +; CHECK-NEXT: vmsle.vv v8, v8, v9 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -71,26 +71,26 @@ define void @lmul_2( %a, %b) nounwind { ; CHECK-NEXT: lui a0, %hi(scratch) ; CHECK-NEXT: addi a0, a0, %lo(scratch) ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vmseq.vv v25, v8, v10 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsne.vv v25, v8, v10 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsltu.vv v25, v10, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsleu.vv v25, v10, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsltu.vv v25, v8, v10 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsleu.vv v25, v8, v10 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmslt.vv v25, v10, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsle.vv v25, v10, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmslt.vv v25, v8, v10 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsle.vv v25, v8, v10 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmseq.vv v12, v8, v10 +; CHECK-NEXT: vsm.v v12, (a0) +; CHECK-NEXT: vmsne.vv v12, v8, v10 +; CHECK-NEXT: vsm.v v12, (a0) +; CHECK-NEXT: vmsltu.vv v12, v10, v8 +; CHECK-NEXT: vsm.v v12, (a0) +; CHECK-NEXT: vmsleu.vv v12, v10, v8 +; CHECK-NEXT: vsm.v v12, (a0) +; CHECK-NEXT: vmsltu.vv v12, v8, v10 +; CHECK-NEXT: vsm.v v12, (a0) +; CHECK-NEXT: vmsleu.vv v12, v8, v10 +; CHECK-NEXT: vsm.v v12, (a0) +; CHECK-NEXT: vmslt.vv v12, v10, v8 +; CHECK-NEXT: vsm.v v12, (a0) +; CHECK-NEXT: vmsle.vv v12, v10, v8 +; CHECK-NEXT: vsm.v v12, (a0) +; CHECK-NEXT: vmslt.vv v12, v8, v10 +; CHECK-NEXT: vsm.v v12, (a0) +; CHECK-NEXT: vmsle.vv v12, v8, v10 +; CHECK-NEXT: vsm.v v12, (a0) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -133,26 +133,26 @@ define void @lmul_4( %a, %b) nounwind { ; CHECK-NEXT: lui a0, %hi(scratch) ; CHECK-NEXT: addi a0, a0, %lo(scratch) ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vmseq.vv v25, v8, v12 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsne.vv v25, v8, v12 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsltu.vv v25, v12, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsleu.vv v25, v12, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsltu.vv v25, v8, v12 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsleu.vv v25, v8, v12 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmslt.vv v25, v12, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsle.vv v25, v12, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmslt.vv v25, v8, v12 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsle.vv v25, v8, v12 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmseq.vv v16, v8, v12 +; CHECK-NEXT: vsm.v v16, (a0) +; CHECK-NEXT: vmsne.vv v16, v8, v12 +; CHECK-NEXT: vsm.v v16, (a0) +; CHECK-NEXT: vmsltu.vv v16, v12, v8 +; CHECK-NEXT: vsm.v v16, (a0) +; CHECK-NEXT: vmsleu.vv v16, v12, v8 +; CHECK-NEXT: vsm.v v16, (a0) +; CHECK-NEXT: vmsltu.vv v16, v8, v12 +; CHECK-NEXT: vsm.v v16, (a0) +; CHECK-NEXT: vmsleu.vv v16, v8, v12 +; CHECK-NEXT: vsm.v v16, (a0) +; CHECK-NEXT: vmslt.vv v16, v12, v8 +; CHECK-NEXT: vsm.v v16, (a0) +; CHECK-NEXT: vmsle.vv v16, v12, v8 +; CHECK-NEXT: vsm.v v16, (a0) +; CHECK-NEXT: vmslt.vv v16, v8, v12 +; CHECK-NEXT: vsm.v v16, (a0) +; CHECK-NEXT: vmsle.vv v16, v8, v12 +; CHECK-NEXT: vsm.v v16, (a0) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -195,26 +195,26 @@ define void @lmul_8( %a, %b) nounwind { ; CHECK-NEXT: lui a0, %hi(scratch) ; CHECK-NEXT: addi a0, a0, %lo(scratch) ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu -; CHECK-NEXT: vmseq.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsne.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsltu.vv v25, v16, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsleu.vv v25, v16, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsltu.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsleu.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmslt.vv v25, v16, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsle.vv v25, v16, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmslt.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsle.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmseq.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsne.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsltu.vv v24, v16, v8 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsleu.vv v24, v16, v8 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsltu.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsleu.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmslt.vv v24, v16, v8 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsle.vv v24, v16, v8 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmslt.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsle.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -257,26 +257,26 @@ define void @lmul_8_i32( %a, %b) nounwind ; CHECK-NEXT: lui a0, %hi(scratch) ; CHECK-NEXT: addi a0, a0, %lo(scratch) ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu -; CHECK-NEXT: vmseq.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsne.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsltu.vv v25, v16, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsleu.vv v25, v16, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsltu.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsleu.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmslt.vv v25, v16, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsle.vv v25, v16, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmslt.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsle.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmseq.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsne.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsltu.vv v24, v16, v8 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsleu.vv v24, v16, v8 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsltu.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsleu.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmslt.vv v24, v16, v8 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsle.vv v24, v16, v8 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmslt.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsle.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -319,26 +319,26 @@ define void @lmul_8_i16( %a, %b) nounwind ; CHECK-NEXT: lui a0, %hi(scratch) ; CHECK-NEXT: addi a0, a0, %lo(scratch) ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu -; CHECK-NEXT: vmseq.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsne.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsltu.vv v25, v16, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsleu.vv v25, v16, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsltu.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsleu.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmslt.vv v25, v16, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsle.vv v25, v16, v8 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmslt.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) -; CHECK-NEXT: vmsle.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmseq.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsne.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsltu.vv v24, v16, v8 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsleu.vv v24, v16, v8 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsltu.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsleu.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmslt.vv v24, v16, v8 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsle.vv v24, v16, v8 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmslt.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) +; CHECK-NEXT: vmsle.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a0) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to * %store_addr_2 = bitcast i8* @scratch to * diff --git a/llvm/test/CodeGen/RISCV/epi-full-vector-select.ll b/llvm/test/CodeGen/RISCV/epi-full-vector-select.ll index 209ac393f955cab014bc6aa3da1f923935bdf32d..811c819af3afa7f9ef461340374287a31bef16c9 100644 --- a/llvm/test/CodeGen/RISCV/epi-full-vector-select.ll +++ b/llvm/test/CodeGen/RISCV/epi-full-vector-select.ll @@ -12,8 +12,8 @@ define void @test_select_int( %a, %b, %a, %b, * @@ -38,8 +38,8 @@ define void @test_select_int_2( %a, %b, %a, %b, * @@ -64,8 +64,8 @@ define void @test_select_int_3( %a, %b, %a, %b, * @@ -90,8 +90,8 @@ define void @test_select_fp( %a, %b, ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-O0-NEXT: vmerge.vvm v25, v9, v8, v0 -; CHECK-O0-NEXT: vs1r.v v25, (a0) +; CHECK-O0-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-O0-NEXT: vs1r.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_select_fp: @@ -99,8 +99,8 @@ define void @test_select_fp( %a, %b, ; CHECK-O2-NEXT: lui a0, %hi(scratch) ; CHECK-O2-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O2-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-O2-NEXT: vmerge.vvm v25, v9, v8, v0 -; CHECK-O2-NEXT: vs1r.v v25, (a0) +; CHECK-O2-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-O2-NEXT: vs1r.v v8, (a0) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -116,8 +116,8 @@ define void @test_select_fp_2( %a, %b, ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-O0-NEXT: vmerge.vvm v25, v9, v8, v0 -; CHECK-O0-NEXT: vs1r.v v25, (a0) +; CHECK-O0-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-O0-NEXT: vs1r.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_select_fp_2: @@ -125,8 +125,8 @@ define void @test_select_fp_2( %a, %b, ; CHECK-O2-NEXT: lui a0, %hi(scratch) ; CHECK-O2-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O2-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-O2-NEXT: vmerge.vvm v25, v9, v8, v0 -; CHECK-O2-NEXT: vs1r.v v25, (a0) +; CHECK-O2-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-O2-NEXT: vs1r.v v8, (a0) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -142,8 +142,8 @@ define void @test_select_fp_3( %a, %b ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-O0-NEXT: vmerge.vvm v26, v10, v8, v0 -; CHECK-O0-NEXT: vs2r.v v26, (a0) +; CHECK-O0-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-O0-NEXT: vs2r.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_select_fp_3: @@ -151,8 +151,8 @@ define void @test_select_fp_3( %a, %b ; CHECK-O2-NEXT: lui a0, %hi(scratch) ; CHECK-O2-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O2-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-O2-NEXT: vmerge.vvm v26, v10, v8, v0 -; CHECK-O2-NEXT: vs2r.v v26, (a0) +; CHECK-O2-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-O2-NEXT: vs2r.v v8, (a0) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -198,12 +198,12 @@ define void @test_select_scalar_int( %a, %b ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vmv.v.x v25, a1 +; CHECK-O0-NEXT: vmv.v.x v10, a1 ; CHECK-O0-NEXT: # implicit-def: $v0 -; CHECK-O0-NEXT: vmsne.vi v0, v25, 0 +; CHECK-O0-NEXT: vmsne.vi v0, v10, 0 ; CHECK-O0-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-O0-NEXT: vmerge.vvm v25, v9, v8, v0 -; CHECK-O0-NEXT: vs1r.v v25, (a0) +; CHECK-O0-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-O0-NEXT: vs1r.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_select_scalar_int: @@ -211,11 +211,11 @@ define void @test_select_scalar_int( %a, %b ; CHECK-O2-NEXT: lui a1, %hi(scratch) ; CHECK-O2-NEXT: addi a1, a1, %lo(scratch) ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vmv.v.x v25, a0 -; CHECK-O2-NEXT: vmsne.vi v0, v25, 0 +; CHECK-O2-NEXT: vmv.v.x v10, a0 +; CHECK-O2-NEXT: vmsne.vi v0, v10, 0 ; CHECK-O2-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-O2-NEXT: vmerge.vvm v25, v9, v8, v0 -; CHECK-O2-NEXT: vs1r.v v25, (a1) +; CHECK-O2-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-O2-NEXT: vs1r.v v8, (a1) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -233,12 +233,12 @@ define void @test_select_scalar_int_2( %a, ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vmv.v.x v25, a1 +; CHECK-O0-NEXT: vmv.v.x v10, a1 ; CHECK-O0-NEXT: # implicit-def: $v0 -; CHECK-O0-NEXT: vmsne.vi v0, v25, 0 +; CHECK-O0-NEXT: vmsne.vi v0, v10, 0 ; CHECK-O0-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-O0-NEXT: vmerge.vvm v25, v9, v8, v0 -; CHECK-O0-NEXT: vs1r.v v25, (a0) +; CHECK-O0-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-O0-NEXT: vs1r.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_select_scalar_int_2: @@ -246,11 +246,11 @@ define void @test_select_scalar_int_2( %a, ; CHECK-O2-NEXT: lui a1, %hi(scratch) ; CHECK-O2-NEXT: addi a1, a1, %lo(scratch) ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vmv.v.x v25, a0 -; CHECK-O2-NEXT: vmsne.vi v0, v25, 0 +; CHECK-O2-NEXT: vmv.v.x v10, a0 +; CHECK-O2-NEXT: vmsne.vi v0, v10, 0 ; CHECK-O2-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-O2-NEXT: vmerge.vvm v25, v9, v8, v0 -; CHECK-O2-NEXT: vs1r.v v25, (a1) +; CHECK-O2-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-O2-NEXT: vs1r.v v8, (a1) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -268,12 +268,12 @@ define void @test_select_scalar_int_3( %a, ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vmv.v.x v25, a1 +; CHECK-O0-NEXT: vmv.v.x v12, a1 ; CHECK-O0-NEXT: # implicit-def: $v0 -; CHECK-O0-NEXT: vmsne.vi v0, v25, 0 +; CHECK-O0-NEXT: vmsne.vi v0, v12, 0 ; CHECK-O0-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; CHECK-O0-NEXT: vmerge.vvm v26, v10, v8, v0 -; CHECK-O0-NEXT: vs2r.v v26, (a0) +; CHECK-O0-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-O0-NEXT: vs2r.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_select_scalar_int_3: @@ -281,11 +281,11 @@ define void @test_select_scalar_int_3( %a, ; CHECK-O2-NEXT: lui a1, %hi(scratch) ; CHECK-O2-NEXT: addi a1, a1, %lo(scratch) ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vmv.v.x v25, a0 -; CHECK-O2-NEXT: vmsne.vi v0, v25, 0 +; CHECK-O2-NEXT: vmv.v.x v12, a0 +; CHECK-O2-NEXT: vmsne.vi v0, v12, 0 ; CHECK-O2-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; CHECK-O2-NEXT: vmerge.vvm v26, v10, v8, v0 -; CHECK-O2-NEXT: vs2r.v v26, (a1) +; CHECK-O2-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-O2-NEXT: vs2r.v v8, (a1) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -303,9 +303,9 @@ define void @test_select_scalar_int_4( %a, ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-O0-NEXT: vmv.v.x v25, a1 +; CHECK-O0-NEXT: vmv.v.x v24, a1 ; CHECK-O0-NEXT: # implicit-def: $v0 -; CHECK-O0-NEXT: vmsne.vi v0, v25, 0 +; CHECK-O0-NEXT: vmsne.vi v0, v24, 0 ; CHECK-O0-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-O0-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-O0-NEXT: vs8r.v v8, (a0) @@ -316,8 +316,8 @@ define void @test_select_scalar_int_4( %a, ; CHECK-O2-NEXT: lui a1, %hi(scratch) ; CHECK-O2-NEXT: addi a1, a1, %lo(scratch) ; CHECK-O2-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-O2-NEXT: vmv.v.x v25, a0 -; CHECK-O2-NEXT: vmsne.vi v0, v25, 0 +; CHECK-O2-NEXT: vmv.v.x v24, a0 +; CHECK-O2-NEXT: vmsne.vi v0, v24, 0 ; CHECK-O2-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-O2-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-O2-NEXT: vs8r.v v8, (a1) @@ -338,9 +338,9 @@ define void @test_select_scalar_int_5( %a, %a, %a, %a, %a, %a, * @@ -453,12 +453,12 @@ define void @test_select_scalar_fp_2( %a, %a, * @@ -488,12 +488,12 @@ define void @test_select_scalar_fp_3( %a, %a, * diff --git a/llvm/test/CodeGen/RISCV/epi-intrinsics-uimm.ll b/llvm/test/CodeGen/RISCV/epi-intrinsics-uimm.ll index 2310a41847e2463f7f44e7533d59b4c2cb061906..c207b642653b8648a32dadafa7495749e4b6f5e2 100644 --- a/llvm/test/CodeGen/RISCV/epi-intrinsics-uimm.ll +++ b/llvm/test/CodeGen/RISCV/epi-intrinsics-uimm.ll @@ -25,40 +25,40 @@ define @foo( %v, %w, i64 ; CHECK-LABEL: foo: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vsll.vi v25, v8, 0 -; CHECK-NEXT: vsll.vi v25, v25, 31 +; CHECK-NEXT: vsll.vi v8, v8, 0 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: addi a0, zero, -1 -; CHECK-NEXT: vsll.vx v25, v25, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vsrl.vi v25, v25, 0 -; CHECK-NEXT: vsrl.vi v25, v25, 31 -; CHECK-NEXT: vsrl.vx v25, v25, a0 -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vsra.vi v25, v25, 0 -; CHECK-NEXT: vsra.vi v25, v25, 31 -; CHECK-NEXT: vsra.vx v25, v25, a0 -; CHECK-NEXT: vsra.vx v25, v25, a1 -; CHECK-NEXT: vssrl.vi v25, v25, 0 -; CHECK-NEXT: vssrl.vi v25, v25, 31 -; CHECK-NEXT: vssrl.vx v25, v25, a0 -; CHECK-NEXT: vssrl.vx v25, v25, a1 -; CHECK-NEXT: vssra.vi v25, v25, 0 -; CHECK-NEXT: vssra.vi v25, v25, 31 -; CHECK-NEXT: vssra.vx v25, v25, a0 -; CHECK-NEXT: vssra.vx v25, v25, a1 -; CHECK-NEXT: vslideup.vi v26, v25, 0 -; CHECK-NEXT: vslideup.vi v25, v26, 31 -; CHECK-NEXT: vslideup.vx v26, v25, a0 -; CHECK-NEXT: vslideup.vx v25, v26, a1 -; CHECK-NEXT: vslidedown.vi v25, v25, 0 -; CHECK-NEXT: vslidedown.vi v25, v25, 31 -; CHECK-NEXT: vslidedown.vx v25, v25, a0 -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vrgather.vi v26, v25, 0 -; CHECK-NEXT: vrgather.vi v25, v26, 31 -; CHECK-NEXT: vrgather.vx v26, v25, a0 -; CHECK-NEXT: vrgather.vx v8, v26, a1 +; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsrl.vi v8, v8, 0 +; CHECK-NEXT: vsrl.vi v8, v8, 31 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vsra.vi v8, v8, 0 +; CHECK-NEXT: vsra.vi v8, v8, 31 +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: vsra.vx v8, v8, a1 +; CHECK-NEXT: vssrl.vi v8, v8, 0 +; CHECK-NEXT: vssrl.vi v8, v8, 31 +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: vssrl.vx v8, v8, a1 +; CHECK-NEXT: vssra.vi v8, v8, 0 +; CHECK-NEXT: vssra.vi v8, v8, 31 +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: vssra.vx v8, v8, a1 +; CHECK-NEXT: vslideup.vi v9, v8, 0 +; CHECK-NEXT: vslideup.vi v8, v9, 31 +; CHECK-NEXT: vslideup.vx v9, v8, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a1 +; CHECK-NEXT: vslidedown.vi v8, v8, 0 +; CHECK-NEXT: vslidedown.vi v8, v8, 31 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vrgather.vi v9, v8, 0 +; CHECK-NEXT: vrgather.vi v8, v9, 31 +; CHECK-NEXT: vrgather.vx v9, v8, a0 +; CHECK-NEXT: vrgather.vx v8, v9, a1 ; CHECK-NEXT: ret { %1 = call @llvm.epi.vsll.nxv1i64( %v, i64 0, i64 %gvl) diff --git a/llvm/test/CodeGen/RISCV/epi-intrinsics.ll b/llvm/test/CodeGen/RISCV/epi-intrinsics.ll index 777529637cbcf9048af3b2b02a5b398cc8f99dc8..ec76dde9be6b1de17cdd3af5f191918f1a36628d 100644 --- a/llvm/test/CodeGen/RISCV/epi-intrinsics.ll +++ b/llvm/test/CodeGen/RISCV/epi-intrinsics.ll @@ -39,29 +39,29 @@ define void @test_load_stores() nounwind ; CHECK-LABEL: test_load_stores: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret { %a1 = call @llvm.epi.vload.nxv8i8(* undef, i64 undef) @@ -108,25 +108,25 @@ define void @test_greater_comparisons(* %pia, ; CHECK-LABEL: test_greater_comparisons: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a5, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vmslt.vv v27, v26, v25 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vmslt.vv v10, v9, v8 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vsm.v v27, (a2) +; CHECK-NEXT: vsm.v v10, (a2) ; CHECK-NEXT: vsetvli zero, a5, e64, m1, ta, mu -; CHECK-NEXT: vmsltu.vv v25, v26, v25 +; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: vsetvli zero, a5, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a3) -; CHECK-NEXT: vle64.v v26, (a4) -; CHECK-NEXT: vmflt.vv v27, v26, v25 +; CHECK-NEXT: vle64.v v8, (a3) +; CHECK-NEXT: vle64.v v9, (a4) +; CHECK-NEXT: vmflt.vv v10, v9, v8 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vsm.v v27, (a2) +; CHECK-NEXT: vsm.v v10, (a2) ; CHECK-NEXT: vsetvli zero, a5, e64, m1, ta, mu -; CHECK-NEXT: vmfle.vv v25, v26, v25 +; CHECK-NEXT: vmfle.vv v8, v9, v8 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret * %pib, * %pm, diff --git a/llvm/test/CodeGen/RISCV/epi-load-store-alignment.ll b/llvm/test/CodeGen/RISCV/epi-load-store-alignment.ll index 6300fb46602b24647082b861016ababc448a8954..9f707d3d08b423b0858a4206991186548f3bd0e2 100644 --- a/llvm/test/CodeGen/RISCV/epi-load-store-alignment.ll +++ b/llvm/test/CodeGen/RISCV/epi-load-store-alignment.ll @@ -16,10 +16,10 @@ define void @foo(i32* %p, i64 %gvl) nounwind optnone noinline ; CHECK-NEXT: sub a2, sp, a2 ; CHECK-NEXT: mv sp, a2 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vs1r.v v25, (a2) -; CHECK-NEXT: vl1re32.v v25, (a2) -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vs1r.v v8, (a2) +; CHECK-NEXT: vl1re32.v v8, (a2) +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi sp, s0, -16 ; CHECK-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/epi-mask-argument.ll b/llvm/test/CodeGen/RISCV/epi-mask-argument.ll index 836885d49229c0607941ae6d4bd3b83675e3213d..8b58c03044f6444ca7ea94e795b59b34c525d837 100644 --- a/llvm/test/CodeGen/RISCV/epi-mask-argument.ll +++ b/llvm/test/CodeGen/RISCV/epi-mask-argument.ll @@ -5,11 +5,11 @@ define @indirect_register_param( %a, %b, %merge, %m, i64 %gvl) nounwind { ; CHECK-LABEL: indirect_register_param: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v17, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v16 -; CHECK-NEXT: vmseq.vv v25, v8, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vv v17, v8, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v17 ; CHECK-NEXT: ret entry: %0 = tail call @llvm.epi.vmseq.mask.nxv8i1.nxv8i32.nxv8i32( %merge, %a, %b, %m, i64 %gvl) @@ -34,11 +34,11 @@ define void @indirect_register_argument( %a, define @indirect_stack_param( ; CHECK-LABEL: indirect_stack_param: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v17, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v16 -; CHECK-NEXT: vmseq.vv v25, v8, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vv v17, v8, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v17 ; CHECK-NEXT: ret i64 %gvl, i64 %_2, i64 %_3, i64 %_4, i64 %_5, i64 %_6, i64 %_7, i64 %_8, %a, %b, %merge, %m) nounwind { diff --git a/llvm/test/CodeGen/RISCV/epi-mask-trunc-zext.ll b/llvm/test/CodeGen/RISCV/epi-mask-trunc-zext.ll index 566dec3810b7b29018e066f1970cb1e1fc83c1cf..bb1d52cd8e3af86c5907e1d1257ad6e2526b993f 100644 --- a/llvm/test/CodeGen/RISCV/epi-mask-trunc-zext.ll +++ b/llvm/test/CodeGen/RISCV/epi-mask-trunc-zext.ll @@ -9,12 +9,12 @@ define @mtrunc_1( %a, %b, ; CHECK-LABEL: mtrunc_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v25, v25, 0 -; CHECK-NEXT: vand.vi v26, v9, 1 -; CHECK-NEXT: vmsne.vi v26, v26, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v8, v8, 0 +; CHECK-NEXT: vand.vi v9, v9, 1 +; CHECK-NEXT: vmsne.vi v9, v9, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmand.mm v0, v25, v26 +; CHECK-NEXT: vmand.mm v0, v8, v9 ; CHECK-NEXT: ret { %ma = trunc %a to @@ -31,12 +31,12 @@ define @mzext_1( %ma, %mb, ; CHECK-LABEL: mzext_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v26, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v10, v9, 1, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v9, 1, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vand.vv v8, v26, v25 +; CHECK-NEXT: vand.vv v8, v10, v8 ; CHECK-NEXT: ret { %a = zext %ma to @@ -53,12 +53,12 @@ define @mtrunc_2( %a, %b, ; CHECK-LABEL: mtrunc_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vand.vi v26, v8, 1 -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vand.vi v26, v10, 1 -; CHECK-NEXT: vmsne.vi v28, v26, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v12, v8, 0 +; CHECK-NEXT: vand.vi v8, v10, 1 +; CHECK-NEXT: vmsne.vi v10, v8, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmand.mm v0, v25, v28 +; CHECK-NEXT: vmand.mm v0, v12, v10 ; CHECK-NEXT: ret { %ma = trunc %a to @@ -75,12 +75,12 @@ define @mzext_2( %ma, %mb, ; CHECK-LABEL: mzext_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v28, v26, 1, v0 +; CHECK-NEXT: vmv.v.i v10, 0 +; CHECK-NEXT: vmerge.vim v12, v10, 1, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vand.vv v8, v28, v26 +; CHECK-NEXT: vand.vv v8, v12, v8 ; CHECK-NEXT: ret { %a = zext %ma to diff --git a/llvm/test/CodeGen/RISCV/epi-masked-gather.ll b/llvm/test/CodeGen/RISCV/epi-masked-gather.ll index bd7340e656515e9cd00e6a45f8073dbc4d0d0d1b..9dae1736e1c9feeb57dbc7a3cee1d2109bfb7735 100644 --- a/llvm/test/CodeGen/RISCV/epi-masked-gather.ll +++ b/llvm/test/CodeGen/RISCV/epi-masked-gather.ll @@ -6,8 +6,8 @@ define @nxv1i64(i64* %ptr, %indices, %indices @@ -52,9 +52,9 @@ define @nxv2xi32(i32* %ptr, %indices, %indices diff --git a/llvm/test/CodeGen/RISCV/epi-masked-scatter.ll b/llvm/test/CodeGen/RISCV/epi-masked-scatter.ll index c5a7abed95ef2f628db1bb22e9ff39e5a9ef4f82..4ae36714136f771522cfc0f3577866810209ecbc 100644 --- a/llvm/test/CodeGen/RISCV/epi-masked-scatter.ll +++ b/llvm/test/CodeGen/RISCV/epi-masked-scatter.ll @@ -6,8 +6,8 @@ define void @nxv1i64( %data, i64* %ptr, %in ; CHECK-LABEL: nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vsll.vi v25, v9, 3 -; CHECK-NEXT: vsoxei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsll.vi v9, v9, 3 +; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret %1 = getelementptr i64, i64* %ptr, %indices call void @llvm.masked.scatter.nxv1i64.nxv1p0i64( %data, %1, i32 8, %mask) @@ -50,9 +50,9 @@ define void @nxv2i32( %data, i32* %ptr, %in ; CHECK-LABEL: nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vsll.vi v26, v10, 2 +; CHECK-NEXT: vsll.vi v10, v10, 2 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret %1 = getelementptr i32, i32* %ptr, %indices call void @llvm.masked.scatter.nxv2i32.nxv2p0i32( %data, %1, i32 4, %mask) diff --git a/llvm/test/CodeGen/RISCV/epi-merge-mask.ll b/llvm/test/CodeGen/RISCV/epi-merge-mask.ll index 0bbc9a11a02e7f809b24d0c5e8dbe6220b1646ec..8a054ddb1442342d81143997e3d6084562f73f0e 100644 --- a/llvm/test/CodeGen/RISCV/epi-merge-mask.ll +++ b/llvm/test/CodeGen/RISCV/epi-merge-mask.ll @@ -31,24 +31,24 @@ define void @merge_mask(i64 %vl, double* %c, double* %a, double* %b) nounwind { ; CHECK-O0-LABEL: merge_mask: ; CHECK-O0: # %bb.0: # %entry ; CHECK-O0-NEXT: vsetvli a0, a0, e64, m1, ta, mu -; CHECK-O0-NEXT: # implicit-def: $v26 -; CHECK-O0-NEXT: vle64.v v26, (a2) -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vle64.v v25, (a3) +; CHECK-O0-NEXT: # implicit-def: $v9 +; CHECK-O0-NEXT: vle64.v v9, (a2) +; CHECK-O0-NEXT: # implicit-def: $v8 +; CHECK-O0-NEXT: vle64.v v8, (a3) ; CHECK-O0-NEXT: # implicit-def: $v0 -; CHECK-O0-NEXT: vmflt.vv v0, v26, v25 -; CHECK-O0-NEXT: vfsub.vv v25, v25, v26, v0.t -; CHECK-O0-NEXT: vse64.v v25, (a1) +; CHECK-O0-NEXT: vmflt.vv v0, v9, v8 +; CHECK-O0-NEXT: vfsub.vv v8, v8, v9, v0.t +; CHECK-O0-NEXT: vse64.v v8, (a1) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: merge_mask: ; CHECK-O2: # %bb.0: # %entry ; CHECK-O2-NEXT: vsetvli a0, a0, e64, m1, ta, mu -; CHECK-O2-NEXT: vle64.v v25, (a2) -; CHECK-O2-NEXT: vle64.v v26, (a3) -; CHECK-O2-NEXT: vmflt.vv v0, v25, v26 -; CHECK-O2-NEXT: vfsub.vv v26, v26, v25, v0.t -; CHECK-O2-NEXT: vse64.v v26, (a1) +; CHECK-O2-NEXT: vle64.v v8, (a2) +; CHECK-O2-NEXT: vle64.v v9, (a3) +; CHECK-O2-NEXT: vmflt.vv v0, v8, v9 +; CHECK-O2-NEXT: vfsub.vv v9, v9, v8, v0.t +; CHECK-O2-NEXT: vse64.v v9, (a1) ; CHECK-O2-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/epi-predicated-vectorization.ll b/llvm/test/CodeGen/RISCV/epi-predicated-vectorization.ll index ea5a3d633ae15f31f57223154ff4637ed79c6ab9..d9babb244c0452d08a8106c36b433db7f47ee9da 100644 --- a/llvm/test/CodeGen/RISCV/epi-predicated-vectorization.ll +++ b/llvm/test/CodeGen/RISCV/epi-predicated-vectorization.ll @@ -21,22 +21,22 @@ define void @vec_add(i32 signext %N, double* noalias nocapture %c, double* noali ; CHECK-NEXT: slli a0, t1, 32 ; CHECK-NEXT: srli t2, a0, 32 ; CHECK-NEXT: vsetvli zero, t2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a7) -; CHECK-NEXT: vmflt.vf v25, v25, ft0 +; CHECK-NEXT: vle64.v v8, (a7) +; CHECK-NEXT: vmflt.vf v8, v8, ft0 ; CHECK-NEXT: add a0, a2, t0 -; CHECK-NEXT: vle64.v v26, (a0) +; CHECK-NEXT: vle64.v v9, (a0) ; CHECK-NEXT: add a0, a3, t0 -; CHECK-NEXT: vle64.v v27, (a0) +; CHECK-NEXT: vle64.v v10, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: vsetvli zero, t2, e64, m1, ta, mu -; CHECK-NEXT: vfmul.vv v28, v26, v27, v0.t +; CHECK-NEXT: vfmul.vv v11, v9, v10, v0.t ; CHECK-NEXT: add a0, a4, t0 -; CHECK-NEXT: vse64.v v28, (a0), v0.t -; CHECK-NEXT: vmv1r.v v0, v25 -; CHECK-NEXT: vfadd.vv v26, v26, v27, v0.t +; CHECK-NEXT: vse64.v v11, (a0), v0.t +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vfadd.vv v9, v9, v10, v0.t ; CHECK-NEXT: add a5, a5, t1 -; CHECK-NEXT: vse64.v v26, (a7), v0.t +; CHECK-NEXT: vse64.v v9, (a7), v0.t ; CHECK-NEXT: bne a5, a6, .LBB0_2 ; CHECK-NEXT: .LBB0_3: # %for.cond.cleanup ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/epi-reductions.ll b/llvm/test/CodeGen/RISCV/epi-reductions.ll index 5d0bb4da3d1ecd1e15abc30073601eba347771c9..dde8b3a00ce917e24005a8d90a204edb2b31e568 100644 --- a/llvm/test/CodeGen/RISCV/epi-reductions.ll +++ b/llvm/test/CodeGen/RISCV/epi-reductions.ll @@ -6,28 +6,28 @@ define i32 @red_nxv2i32( %a) nounwind { ; CHECK-LABEL: red_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredsum.vs v26, v8, v25 -; CHECK-NEXT: vmv.x.s a6, v26 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredsum.vs v10, v8, v9 +; CHECK-NEXT: vmv.x.s a6, v10 ; CHECK-NEXT: lui a1, 524288 -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: vredmax.vs v26, v8, v26 -; CHECK-NEXT: vmv.x.s a7, v26 +; CHECK-NEXT: vmv.v.x v10, a1 +; CHECK-NEXT: vredmax.vs v10, v8, v10 +; CHECK-NEXT: vmv.x.s a7, v10 ; CHECK-NEXT: addiw a1, a1, -1 -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: vredmin.vs v26, v8, v26 -; CHECK-NEXT: vmv.x.s t0, v26 -; CHECK-NEXT: vredmaxu.vs v26, v8, v25 -; CHECK-NEXT: vmv.x.s a3, v26 -; CHECK-NEXT: vmv.v.i v26, -1 -; CHECK-NEXT: vredminu.vs v27, v8, v26 -; CHECK-NEXT: vmv.x.s a4, v27 -; CHECK-NEXT: vredand.vs v26, v8, v26 -; CHECK-NEXT: vmv.x.s a5, v26 -; CHECK-NEXT: vredor.vs v26, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v26 -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a2, v25 +; CHECK-NEXT: vmv.v.x v10, a1 +; CHECK-NEXT: vredmin.vs v10, v8, v10 +; CHECK-NEXT: vmv.x.s t0, v10 +; CHECK-NEXT: vredmaxu.vs v10, v8, v9 +; CHECK-NEXT: vmv.x.s a3, v10 +; CHECK-NEXT: vmv.v.i v10, -1 +; CHECK-NEXT: vredminu.vs v11, v8, v10 +; CHECK-NEXT: vmv.x.s a4, v11 +; CHECK-NEXT: vredand.vs v10, v8, v10 +; CHECK-NEXT: vmv.x.s a5, v10 +; CHECK-NEXT: vredor.vs v10, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v10 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a2, v8 ; CHECK-NEXT: addw a1, a6, a7 ; CHECK-NEXT: addw a1, a1, t0 ; CHECK-NEXT: addw a1, a1, a3 @@ -63,29 +63,29 @@ define i64 @red_nxv1i64( %a) nounwind { ; CHECK-LABEL: red_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredsum.vs v26, v8, v25 -; CHECK-NEXT: vmv.x.s a6, v26 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredsum.vs v10, v8, v9 +; CHECK-NEXT: vmv.x.s a6, v10 ; CHECK-NEXT: addi a1, zero, -1 ; CHECK-NEXT: slli a2, a1, 63 -; CHECK-NEXT: vmv.v.x v26, a2 -; CHECK-NEXT: vredmax.vs v26, v8, v26 -; CHECK-NEXT: vmv.x.s a7, v26 +; CHECK-NEXT: vmv.v.x v10, a2 +; CHECK-NEXT: vredmax.vs v10, v8, v10 +; CHECK-NEXT: vmv.x.s a7, v10 ; CHECK-NEXT: srli a1, a1, 1 -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: vredmin.vs v26, v8, v26 -; CHECK-NEXT: vmv.x.s t0, v26 -; CHECK-NEXT: vredmaxu.vs v26, v8, v25 -; CHECK-NEXT: vmv.x.s a3, v26 -; CHECK-NEXT: vmv.v.i v26, -1 -; CHECK-NEXT: vredminu.vs v27, v8, v26 -; CHECK-NEXT: vmv.x.s a4, v27 -; CHECK-NEXT: vredand.vs v26, v8, v26 -; CHECK-NEXT: vmv.x.s a5, v26 -; CHECK-NEXT: vredor.vs v26, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v26 -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a2, v25 +; CHECK-NEXT: vmv.v.x v10, a1 +; CHECK-NEXT: vredmin.vs v10, v8, v10 +; CHECK-NEXT: vmv.x.s t0, v10 +; CHECK-NEXT: vredmaxu.vs v10, v8, v9 +; CHECK-NEXT: vmv.x.s a3, v10 +; CHECK-NEXT: vmv.v.i v10, -1 +; CHECK-NEXT: vredminu.vs v11, v8, v10 +; CHECK-NEXT: vmv.x.s a4, v11 +; CHECK-NEXT: vredand.vs v10, v8, v10 +; CHECK-NEXT: vmv.x.s a5, v10 +; CHECK-NEXT: vredor.vs v10, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v10 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a2, v8 ; CHECK-NEXT: add a1, a6, a7 ; CHECK-NEXT: add a1, a1, t0 ; CHECK-NEXT: add a1, a1, a3 @@ -121,36 +121,36 @@ define i64 @red_nxv2i64( %a) nounwind { ; CHECK-LABEL: red_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredsum.vs v26, v8, v25 -; CHECK-NEXT: vmv.x.s a6, v26 +; CHECK-NEXT: vredsum.vs v11, v8, v10 +; CHECK-NEXT: vmv.x.s a6, v11 ; CHECK-NEXT: addi a1, zero, -1 ; CHECK-NEXT: slli a2, a1, 63 ; CHECK-NEXT: vsetvli a3, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, a2 +; CHECK-NEXT: vmv.v.x v11, a2 ; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu -; CHECK-NEXT: vredmax.vs v26, v8, v26 -; CHECK-NEXT: vmv.x.s a7, v26 +; CHECK-NEXT: vredmax.vs v11, v8, v11 +; CHECK-NEXT: vmv.x.s a7, v11 ; CHECK-NEXT: srli a1, a1, 1 ; CHECK-NEXT: vsetvli a3, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, a1 +; CHECK-NEXT: vmv.v.x v11, a1 ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vredmin.vs v26, v8, v26 -; CHECK-NEXT: vmv.x.s t0, v26 -; CHECK-NEXT: vredmaxu.vs v26, v8, v25 -; CHECK-NEXT: vmv.x.s a3, v26 +; CHECK-NEXT: vredmin.vs v11, v8, v11 +; CHECK-NEXT: vmv.x.s t0, v11 +; CHECK-NEXT: vredmaxu.vs v11, v8, v10 +; CHECK-NEXT: vmv.x.s a3, v11 ; CHECK-NEXT: vsetvli a4, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v11, -1 ; CHECK-NEXT: vsetvli a4, zero, e64, m2, ta, mu -; CHECK-NEXT: vredminu.vs v27, v8, v26 -; CHECK-NEXT: vmv.x.s a4, v27 -; CHECK-NEXT: vredand.vs v26, v8, v26 -; CHECK-NEXT: vmv.x.s a5, v26 -; CHECK-NEXT: vredor.vs v26, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v26 -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a2, v25 +; CHECK-NEXT: vredminu.vs v12, v8, v11 +; CHECK-NEXT: vmv.x.s a4, v12 +; CHECK-NEXT: vredand.vs v11, v8, v11 +; CHECK-NEXT: vmv.x.s a5, v11 +; CHECK-NEXT: vredor.vs v11, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v11 +; CHECK-NEXT: vredxor.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a2, v8 ; CHECK-NEXT: add a1, a6, a7 ; CHECK-NEXT: add a1, a1, t0 ; CHECK-NEXT: add a1, a1, a3 @@ -190,23 +190,23 @@ define float @red_nxv2f32( %a) nounwind { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI3_1) ; CHECK-NEXT: flw ft1, %lo(.LCPI3_1)(a0) -; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft2, v25 -; CHECK-NEXT: vfmv.v.f v25, ft1 -; CHECK-NEXT: vfredusum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft1, v25 +; CHECK-NEXT: vfmv.v.f v9, ft0 +; CHECK-NEXT: vfredosum.vs v9, v8, v9 +; CHECK-NEXT: vfmv.f.s ft2, v9 +; CHECK-NEXT: vfmv.v.f v9, ft1 +; CHECK-NEXT: vfredusum.vs v9, v8, v9 +; CHECK-NEXT: vfmv.f.s ft1, v9 ; CHECK-NEXT: lui a0, %hi(.LCPI3_2) ; CHECK-NEXT: flw ft3, %lo(.LCPI3_2)(a0) ; CHECK-NEXT: fadd.s ft0, ft1, ft0 ; CHECK-NEXT: lui a0, %hi(.LCPI3_3) ; CHECK-NEXT: flw ft1, %lo(.LCPI3_3)(a0) -; CHECK-NEXT: vfmv.v.f v25, ft3 -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft3, v25 -; CHECK-NEXT: vfmv.v.f v25, ft1 -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft1, v25 +; CHECK-NEXT: vfmv.v.f v9, ft3 +; CHECK-NEXT: vfredmax.vs v9, v8, v9 +; CHECK-NEXT: vfmv.f.s ft3, v9 +; CHECK-NEXT: vfmv.v.f v9, ft1 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s ft1, v8 ; CHECK-NEXT: fadd.s ft0, ft2, ft0 ; CHECK-NEXT: fadd.s ft0, ft0, ft3 ; CHECK-NEXT: fadd.s ft0, ft0, ft1 @@ -235,23 +235,23 @@ define double @red_nxv1f64( %a) nounwind { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI4_1) ; CHECK-NEXT: fld ft1, %lo(.LCPI4_1)(a0) -; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft2, v25 -; CHECK-NEXT: vfmv.v.f v25, ft1 -; CHECK-NEXT: vfredusum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft1, v25 +; CHECK-NEXT: vfmv.v.f v9, ft0 +; CHECK-NEXT: vfredosum.vs v9, v8, v9 +; CHECK-NEXT: vfmv.f.s ft2, v9 +; CHECK-NEXT: vfmv.v.f v9, ft1 +; CHECK-NEXT: vfredusum.vs v9, v8, v9 +; CHECK-NEXT: vfmv.f.s ft1, v9 ; CHECK-NEXT: lui a0, %hi(.LCPI4_2) ; CHECK-NEXT: fld ft3, %lo(.LCPI4_2)(a0) ; CHECK-NEXT: fadd.d ft0, ft1, ft0 ; CHECK-NEXT: lui a0, %hi(.LCPI4_3) ; CHECK-NEXT: fld ft1, %lo(.LCPI4_3)(a0) -; CHECK-NEXT: vfmv.v.f v25, ft3 -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft3, v25 -; CHECK-NEXT: vfmv.v.f v25, ft1 -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft1, v25 +; CHECK-NEXT: vfmv.v.f v9, ft3 +; CHECK-NEXT: vfredmax.vs v9, v8, v9 +; CHECK-NEXT: vfmv.f.s ft3, v9 +; CHECK-NEXT: vfmv.v.f v9, ft1 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s ft1, v8 ; CHECK-NEXT: fadd.d ft0, ft2, ft0 ; CHECK-NEXT: fadd.d ft0, ft0, ft3 ; CHECK-NEXT: fadd.d ft0, ft0, ft1 @@ -278,32 +278,32 @@ define double @red_nxv2f64( %a) nounwind { ; CHECK-NEXT: lui a0, %hi(.LCPI5_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI5_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI5_1) ; CHECK-NEXT: fld ft1, %lo(.LCPI5_1)(a0) -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft2, v25 +; CHECK-NEXT: vfredosum.vs v10, v8, v10 +; CHECK-NEXT: vfmv.f.s ft2, v10 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft1 +; CHECK-NEXT: vfmv.v.f v10, ft1 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25 +; CHECK-NEXT: vfredusum.vs v10, v8, v10 ; CHECK-NEXT: lui a0, %hi(.LCPI5_2) ; CHECK-NEXT: fld ft1, %lo(.LCPI5_2)(a0) -; CHECK-NEXT: vfmv.f.s ft3, v25 +; CHECK-NEXT: vfmv.f.s ft3, v10 ; CHECK-NEXT: fadd.d ft0, ft3, ft0 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft1 +; CHECK-NEXT: vfmv.v.f v10, ft1 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI5_3) ; CHECK-NEXT: fld ft1, %lo(.LCPI5_3)(a0) -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft3, v25 +; CHECK-NEXT: vfredmax.vs v10, v8, v10 +; CHECK-NEXT: vfmv.f.s ft3, v10 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft1 +; CHECK-NEXT: vfmv.v.f v10, ft1 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft1, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s ft1, v8 ; CHECK-NEXT: fadd.d ft0, ft2, ft0 ; CHECK-NEXT: fadd.d ft0, ft0, ft3 ; CHECK-NEXT: fadd.d ft0, ft0, ft1 diff --git a/llvm/test/CodeGen/RISCV/epi-setcc-zext.ll b/llvm/test/CodeGen/RISCV/epi-setcc-zext.ll index 45fef266f7b567b15273cb0a5d0dcc590d04a1b3..4b5d9aba3318c566e1c9ed4c59ec02e952f65bc5 100644 --- a/llvm/test/CodeGen/RISCV/epi-setcc-zext.ll +++ b/llvm/test/CodeGen/RISCV/epi-setcc-zext.ll @@ -18,8 +18,8 @@ define @sext_i64( %a, %b ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vmsleu.vv v0, v8, v9 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret { %cmp = icmp ule %a, %b diff --git a/llvm/test/CodeGen/RISCV/epi-sext-illegal-vectors.ll b/llvm/test/CodeGen/RISCV/epi-sext-illegal-vectors.ll index 4b34b5e7fe838780ab93e4a0b5ff6842b85e8112..82f1a1ba648e8cdf5a9de8c94e193e1116129cd8 100644 --- a/llvm/test/CodeGen/RISCV/epi-sext-illegal-vectors.ll +++ b/llvm/test/CodeGen/RISCV/epi-sext-illegal-vectors.ll @@ -24,8 +24,8 @@ define @sext_nxv1i8( %v) ; CHECK-LABEL: sext_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf8 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf8 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %sv = sext %v to @@ -35,8 +35,8 @@ define @sext_nxv2i8( %v) ; CHECK-LABEL: sext_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %sv = sext %v to @@ -46,8 +46,8 @@ define @sext_nxv4i8( %v) ; CHECK-LABEL: sext_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %sv = sext %v to @@ -59,8 +59,8 @@ define @sext_nxv1i16( %v) ; CHECK-LABEL: sext_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %sv = sext %v to @@ -70,8 +70,8 @@ define @sext_nxv2i16( %v) ; CHECK-LABEL: sext_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %sv = sext %v to @@ -83,8 +83,8 @@ define @sext_nxv1i32( %v) ; CHECK-LABEL: sext_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %sv = sext %v to diff --git a/llvm/test/CodeGen/RISCV/epi-sext-quad-octa.ll b/llvm/test/CodeGen/RISCV/epi-sext-quad-octa.ll index f3d848397eec03fbf5b7df423030dbeba0ae156b..bea385e3201ae38fb6ff4bfd1e4e853c1efd55b2 100644 --- a/llvm/test/CodeGen/RISCV/epi-sext-quad-octa.ll +++ b/llvm/test/CodeGen/RISCV/epi-sext-quad-octa.ll @@ -7,8 +7,8 @@ define @test_sext_i8_i32_m1( %a) nounwind ; CHECK-LABEL: test_sext_i8_i32_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret { %b = sext %a to @@ -33,8 +33,8 @@ define @test_sext_i16_i64_m1( %a) nounwind ; CHECK-LABEL: test_sext_i16_i64_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret { %b = sext %a to diff --git a/llvm/test/CodeGen/RISCV/epi-sext.ll b/llvm/test/CodeGen/RISCV/epi-sext.ll index ab274c2493be607ce5b699546cea58d5a599ebe3..91d49bf7309c7195b3ef20c74895e798007a31c3 100644 --- a/llvm/test/CodeGen/RISCV/epi-sext.ll +++ b/llvm/test/CodeGen/RISCV/epi-sext.ll @@ -7,8 +7,8 @@ define @test_sext_i32_i64_m1( %a) nounwind ; CHECK-LABEL: test_sext_i32_i64_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret { %b = sext %a to @@ -19,8 +19,8 @@ define @test_sext_i32_i64_m2( %a) nounwind ; CHECK-LABEL: test_sext_i32_i64_m2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret { %b = sext %a to @@ -44,8 +44,8 @@ define @test_sext_i16_i32_m1( %a) nounwind ; CHECK-LABEL: test_sext_i16_i32_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret { %b = sext %a to @@ -56,8 +56,8 @@ define @test_sext_i16_i32_m2( %a) nounwind ; CHECK-LABEL: test_sext_i16_i32_m2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret { %b = sext %a to @@ -81,8 +81,8 @@ define @test_sext_i8_i16_m1( %a) nounwind ; CHECK-LABEL: test_sext_i8_i16_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret { %b = sext %a to @@ -93,8 +93,8 @@ define @test_sext_i8_i16_m2( %a) nounwind ; CHECK-LABEL: test_sext_i8_i16_m2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret { %b = sext %a to diff --git a/llvm/test/CodeGen/RISCV/epi-slideleft.ll b/llvm/test/CodeGen/RISCV/epi-slideleft.ll index c2b74554df957f0d08745a3f77840d69bd5e4a9f..609239b8e9d6f86152ff0d99793e5ede18e8f72d 100644 --- a/llvm/test/CodeGen/RISCV/epi-slideleft.ll +++ b/llvm/test/CodeGen/RISCV/epi-slideleft.ll @@ -8,12 +8,12 @@ define @nxv1i64( %va, %v ; CHECK-LABEL: nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: sub a0, a1, a0 -; CHECK-NEXT: vid.v v26 -; CHECK-NEXT: vmsltu.vx v0, v26, a0 -; CHECK-NEXT: vslideup.vx v26, v9, a0 -; CHECK-NEXT: vmerge.vvm v8, v26, v25, v0 +; CHECK-NEXT: vid.v v10 +; CHECK-NEXT: vmsltu.vx v0, v10, a0 +; CHECK-NEXT: vslideup.vx v10, v9, a0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = call @llvm.experimental.vector.slideleftfill.nxv1i64( %va, @@ -30,12 +30,12 @@ define @nxv2i32( %va, %v ; CHECK-LABEL: nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: sub a0, a1, a0 -; CHECK-NEXT: vid.v v26 -; CHECK-NEXT: vmsltu.vx v0, v26, a0 -; CHECK-NEXT: vslideup.vx v26, v9, a0 -; CHECK-NEXT: vmerge.vvm v8, v26, v25, v0 +; CHECK-NEXT: vid.v v10 +; CHECK-NEXT: vmsltu.vx v0, v10, a0 +; CHECK-NEXT: vslideup.vx v10, v9, a0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = call @llvm.experimental.vector.slideleftfill.nxv2i32( %va, @@ -52,12 +52,12 @@ define @nxv1f64( %va, @llvm.experimental.vector.slideleftfill.nxv1f64( %va, @@ -74,12 +74,12 @@ define @nxv2f32( %va, @llvm.experimental.vector.slideleftfill.nxv2f32( %va, @@ -96,12 +96,12 @@ define @nxv2i64( %va, %v ; CHECK-LABEL: nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: sub a0, a1, a0 -; CHECK-NEXT: vid.v v28 -; CHECK-NEXT: vmsltu.vx v0, v28, a0 -; CHECK-NEXT: vslideup.vx v28, v10, a0 -; CHECK-NEXT: vmerge.vvm v8, v28, v26, v0 +; CHECK-NEXT: vid.v v12 +; CHECK-NEXT: vmsltu.vx v0, v12, a0 +; CHECK-NEXT: vslideup.vx v12, v10, a0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = call @llvm.experimental.vector.slideleftfill.nxv2i64( %va, diff --git a/llvm/test/CodeGen/RISCV/epi-spill-vector-csr.ll b/llvm/test/CodeGen/RISCV/epi-spill-vector-csr.ll index ce25c356bee13f0a9affc387c26cf5364942f4db..472efd5ca0b00f8a16193a699a5ac7fb311fa599 100644 --- a/llvm/test/CodeGen/RISCV/epi-spill-vector-csr.ll +++ b/llvm/test/CodeGen/RISCV/epi-spill-vector-csr.ll @@ -15,29 +15,31 @@ define @foo( %a, @foo( %a, @foo( %a, @test_trunc_i32_i8_m1( %a) nounwind ; CHECK-LABEL: test_trunc_i32_i8_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: ret { %b = trunc %a to @@ -21,11 +21,11 @@ define @test_trunc_i64_i8_m1( %a) nounwind ; CHECK-LABEL: test_trunc_i64_i8_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v28, 0 +; CHECK-NEXT: vnsrl.wi v10, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret { %b = trunc %a to @@ -37,9 +37,9 @@ define @test_trunc_i64_i16_m1( %a) nounwind ; CHECK-LABEL: test_trunc_i64_i16_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: ret { %b = trunc %a to @@ -50,9 +50,9 @@ define @test_trunc_i64_i16_m2( %a) nounwind ; CHECK-LABEL: test_trunc_i64_i16_m2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v28, 0 +; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: ret { %b = trunc %a to diff --git a/llvm/test/CodeGen/RISCV/epi-trunc.ll b/llvm/test/CodeGen/RISCV/epi-trunc.ll index 3598c4afaf3aee817317bba660b85551fa58b185..9d60f3a4fd5bd2a4cd1a6d91ca0cb8af4d1f24d8 100644 --- a/llvm/test/CodeGen/RISCV/epi-trunc.ll +++ b/llvm/test/CodeGen/RISCV/epi-trunc.ll @@ -7,8 +7,8 @@ define @test_zext_i64_i32_m1( %a) nounwind ; CHECK-LABEL: test_zext_i64_i32_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret { %b = trunc %a to @@ -19,8 +19,8 @@ define @test_zext_i64_i32_m2( %a) nounwind ; CHECK-LABEL: test_zext_i64_i32_m2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret { %b = trunc %a to @@ -31,8 +31,8 @@ define @test_zext_i64_i32_m4( %a) nounwind ; CHECK-LABEL: test_zext_i64_i32_m4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret { %b = trunc %a to @@ -44,8 +44,8 @@ define @test_zext_i32_i16_m1( %a) nounwind ; CHECK-LABEL: test_zext_i32_i16_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret { %b = trunc %a to @@ -56,8 +56,8 @@ define @test_zext_i32_i16_m2( %a) nounwind ; CHECK-LABEL: test_zext_i32_i16_m2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret { %b = trunc %a to @@ -68,8 +68,8 @@ define @test_zext_i32_i16_m4( %a) nounwin ; CHECK-LABEL: test_zext_i32_i16_m4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret { %b = trunc %a to @@ -81,8 +81,8 @@ define @test_zext_i16_i8_m1( %a) nounwind ; CHECK-LABEL: test_zext_i16_i8_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret { %b = trunc %a to @@ -93,8 +93,8 @@ define @test_zext_i16_i8_m2( %a) nounwind ; CHECK-LABEL: test_zext_i16_i8_m2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret { %b = trunc %a to @@ -105,8 +105,8 @@ define @test_zext_i16_i8_m4( %a) nounwind ; CHECK-LABEL: test_zext_i16_i8_m4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret { %b = trunc %a to diff --git a/llvm/test/CodeGen/RISCV/epi-vector-axpy.ll b/llvm/test/CodeGen/RISCV/epi-vector-axpy.ll index 5860bfd6daca07416f555b1005ca5632d71db7fe..3e33f230815516d0b8e9e57a5e15cefcadbd756c 100644 --- a/llvm/test/CodeGen/RISCV/epi-vector-axpy.ll +++ b/llvm/test/CodeGen/RISCV/epi-vector-axpy.ll @@ -24,12 +24,12 @@ define void @saxpy(i32 signext %N, float* noalias nocapture %y, float* noalias n ; CHECK-NEXT: .LBB0_4: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: add a3, a2, a0 -; CHECK-NEXT: vl1re32.v v25, (a3) +; CHECK-NEXT: vl1re32.v v8, (a3) ; CHECK-NEXT: add a3, a1, a0 -; CHECK-NEXT: vl1re32.v v26, (a3) +; CHECK-NEXT: vl1re32.v v9, (a3) ; CHECK-NEXT: vsetvli a5, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmacc.vf v26, ft0, v25 -; CHECK-NEXT: vs1r.v v26, (a3) +; CHECK-NEXT: vfmacc.vf v9, ft0, v8 +; CHECK-NEXT: vs1r.v v9, (a3) ; CHECK-NEXT: add a4, a4, t2 ; CHECK-NEXT: add a0, a0, t0 ; CHECK-NEXT: bne a4, t1, .LBB0_4 @@ -137,12 +137,12 @@ define void @daxpy(i32 signext %N, double* noalias nocapture %y, double* noalias ; CHECK-NEXT: .LBB1_4: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: add a3, a2, a0 -; CHECK-NEXT: vl1re64.v v25, (a3) +; CHECK-NEXT: vl1re64.v v8, (a3) ; CHECK-NEXT: add a3, a1, a0 -; CHECK-NEXT: vl1re64.v v26, (a3) +; CHECK-NEXT: vl1re64.v v9, (a3) ; CHECK-NEXT: vsetvli a5, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmacc.vf v26, ft0, v25 -; CHECK-NEXT: vs1r.v v26, (a3) +; CHECK-NEXT: vfmacc.vf v9, ft0, v8 +; CHECK-NEXT: vs1r.v v9, (a3) ; CHECK-NEXT: add a4, a4, t2 ; CHECK-NEXT: add a0, a0, t0 ; CHECK-NEXT: bne a4, t1, .LBB1_4 diff --git a/llvm/test/CodeGen/RISCV/epi-vector-cc.ll b/llvm/test/CodeGen/RISCV/epi-vector-cc.ll index 83d3a8df5b1d0c02272d7af0964e29a9918e2114..2652dbe90107acaa182b835eabf7b126cddc498d 100644 --- a/llvm/test/CodeGen/RISCV/epi-vector-cc.ll +++ b/llvm/test/CodeGen/RISCV/epi-vector-cc.ll @@ -29,12 +29,12 @@ define @max_registers( ; CHECK-LABEL: max_registers: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfadd.vv v25, v8, v9 -; CHECK-NEXT: vfadd.vv v25, v25, v11 -; CHECK-NEXT: vfadd.vv v25, v25, v12 -; CHECK-NEXT: vfadd.vv v25, v25, v13 -; CHECK-NEXT: vfadd.vv v25, v25, v14 -; CHECK-NEXT: vfadd.vv v8, v25, v15 +; CHECK-NEXT: vfadd.vv v8, v8, v9 +; CHECK-NEXT: vfadd.vv v8, v8, v11 +; CHECK-NEXT: vfadd.vv v8, v8, v12 +; CHECK-NEXT: vfadd.vv v8, v8, v13 +; CHECK-NEXT: vfadd.vv v8, v8, v14 +; CHECK-NEXT: vfadd.vv v8, v8, v15 ; CHECK-NEXT: ret %v0, %v1, diff --git a/llvm/test/CodeGen/RISCV/epi-vector-iaxpy.ll b/llvm/test/CodeGen/RISCV/epi-vector-iaxpy.ll index ba6dc4d336fad0ce47fdca1dbe56ebd8da79ee8f..ba4abd533850dfd08b64933e334e2ef6e6dba41d 100644 --- a/llvm/test/CodeGen/RISCV/epi-vector-iaxpy.ll +++ b/llvm/test/CodeGen/RISCV/epi-vector-iaxpy.ll @@ -24,12 +24,12 @@ define void @s16axpy(i16 signext %N, i16* noalias nocapture %y, i16* noalias noc ; CHECK-NEXT: .LBB0_4: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: add a0, a2, a4 -; CHECK-NEXT: vl1re16.v v25, (a0) +; CHECK-NEXT: vl1re16.v v8, (a0) ; CHECK-NEXT: add t3, a1, a4 -; CHECK-NEXT: vl1re16.v v26, (t3) +; CHECK-NEXT: vl1re16.v v9, (t3) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmacc.vx v26, a3, v25 -; CHECK-NEXT: vs1r.v v26, (t3) +; CHECK-NEXT: vmacc.vx v9, a3, v8 +; CHECK-NEXT: vs1r.v v9, (t3) ; CHECK-NEXT: add a5, a5, t2 ; CHECK-NEXT: add a4, a4, t0 ; CHECK-NEXT: bne a5, t1, .LBB0_4 @@ -137,12 +137,12 @@ define void @s32axpy(i32 signext %N, i32* noalias nocapture %y, i32* noalias noc ; CHECK-NEXT: .LBB1_4: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: add a0, a2, a4 -; CHECK-NEXT: vl1re32.v v25, (a0) +; CHECK-NEXT: vl1re32.v v8, (a0) ; CHECK-NEXT: add t3, a1, a4 -; CHECK-NEXT: vl1re32.v v26, (t3) +; CHECK-NEXT: vl1re32.v v9, (t3) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmacc.vx v26, a3, v25 -; CHECK-NEXT: vs1r.v v26, (t3) +; CHECK-NEXT: vmacc.vx v9, a3, v8 +; CHECK-NEXT: vs1r.v v9, (t3) ; CHECK-NEXT: add a5, a5, t2 ; CHECK-NEXT: add a4, a4, t0 ; CHECK-NEXT: bne a5, t1, .LBB1_4 @@ -249,12 +249,12 @@ define void @s64axpy(i64 %N, i64* noalias nocapture %y, i64* noalias nocapture r ; CHECK-NEXT: .LBB2_4: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: add a4, a2, a5 -; CHECK-NEXT: vl1re64.v v25, (a4) +; CHECK-NEXT: vl1re64.v v8, (a4) ; CHECK-NEXT: add t3, a1, a5 -; CHECK-NEXT: vl1re64.v v26, (t3) +; CHECK-NEXT: vl1re64.v v9, (t3) ; CHECK-NEXT: vsetvli a4, zero, e64, m1, ta, mu -; CHECK-NEXT: vmacc.vx v26, a3, v25 -; CHECK-NEXT: vs1r.v v26, (t3) +; CHECK-NEXT: vmacc.vx v9, a3, v8 +; CHECK-NEXT: vs1r.v v9, (t3) ; CHECK-NEXT: add t2, t2, t1 ; CHECK-NEXT: add a5, a5, a6 ; CHECK-NEXT: bne t2, t0, .LBB2_4 diff --git a/llvm/test/CodeGen/RISCV/epi-vector-insert.ll b/llvm/test/CodeGen/RISCV/epi-vector-insert.ll index 8c411476c63b1853ab21cea707b9fb9809dc56e3..71acc37b9415b5bdde41d890d0af47d0288c1a83 100644 --- a/llvm/test/CodeGen/RISCV/epi-vector-insert.ll +++ b/llvm/test/CodeGen/RISCV/epi-vector-insert.ll @@ -6,10 +6,10 @@ define @insert_nxv1i64( %merge, i64 %e, i64 ; CHECK-LABEL: insert_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret { %v = insertelement %merge, i64 %e, i64 %idx @@ -20,10 +20,10 @@ define @insert_nxv2i32( %merge, i32 %e, i64 ; CHECK-LABEL: insert_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret { %v = insertelement %merge, i32 %e, i64 %idx @@ -34,10 +34,10 @@ define @insert_nxv2i64( %merge, i64 %e, i64 ; CHECK-LABEL: insert_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a1 +; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: ret { %v = insertelement %merge, i64 %e, i64 %idx @@ -48,10 +48,10 @@ define @insert_nxv1f64( %merge, doubl ; CHECK-LABEL: insert_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret { %v = insertelement %merge, double %e, i64 %idx @@ -62,10 +62,10 @@ define @insert_nxv2f32( %merge, float % ; CHECK-LABEL: insert_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret { %v = insertelement %merge, float %e, i64 %idx @@ -76,10 +76,10 @@ define @insert_nxv2f64( %merge, doubl ; CHECK-LABEL: insert_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.s.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret { %v = insertelement %merge, double %e, i64 %idx @@ -90,10 +90,10 @@ define @insert_nxv4f32( %merge, float % ; CHECK-LABEL: insert_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.s.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret { %v = insertelement %merge, float %e, i64 %idx diff --git a/llvm/test/CodeGen/RISCV/epi-vector-regalloc-v0.ll b/llvm/test/CodeGen/RISCV/epi-vector-regalloc-v0.ll index 9cae7594a85a41609f088f75c45e2b940c4dd707..8a218e1fe6f1c85b046ef082969fb4e29fbdce8a 100644 --- a/llvm/test/CodeGen/RISCV/epi-vector-regalloc-v0.ll +++ b/llvm/test/CodeGen/RISCV/epi-vector-regalloc-v0.ll @@ -5,11 +5,11 @@ define dso_local @foo( %a, %b, %merge, %m, i64 %gvl) nounwind { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vv v25, v8, v9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vv v11, v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %0 = tail call @llvm.epi.vmseq.mask.nxv1i1.nxv1i64.nxv1i64( %merge, %a, %b, %m, i64 %gvl) diff --git a/llvm/test/CodeGen/RISCV/epi-vector-reverse.ll b/llvm/test/CodeGen/RISCV/epi-vector-reverse.ll index b22ee794b71383b6577e2c5aea26be8625a45f50..66917b3b25563decb101b4b5e59554f4fbcc2f1f 100644 --- a/llvm/test/CodeGen/RISCV/epi-vector-reverse.ll +++ b/llvm/test/CodeGen/RISCV/epi-vector-reverse.ll @@ -9,10 +9,10 @@ define @nxv1i64( %a) nounwind { ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vx v26, v25, a0 -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vrsub.vx v10, v9, a0 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %b = call @llvm.experimental.vector.reverse.nxv1i64( %a) ret %b @@ -25,10 +25,10 @@ define @nxv2i32( %a) nounwind { ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vx v26, v25, a0 -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vrsub.vx v10, v9, a0 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %b = call @llvm.experimental.vector.reverse.nxv2i32( %a) ret %b @@ -41,10 +41,10 @@ define @nxv2i64( %a) nounwind { ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vid.v v26 -; CHECK-NEXT: vrsub.vx v28, v26, a0 -; CHECK-NEXT: vrgather.vv v26, v8, v28 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vid.v v10 +; CHECK-NEXT: vrsub.vx v12, v10, a0 +; CHECK-NEXT: vrgather.vv v10, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %b = call @llvm.experimental.vector.reverse.nxv2i64( %a) ret %b diff --git a/llvm/test/CodeGen/RISCV/epi-vector-tuple-spill-emergency.ll b/llvm/test/CodeGen/RISCV/epi-vector-tuple-spill-emergency.ll index 38ec3c7a982a0b22c9a342d69a93482987108c1f..ef3f8fc4ee20c1765e2d906b05bbd6ad522ce7a1 100644 --- a/llvm/test/CodeGen/RISCV/epi-vector-tuple-spill-emergency.ll +++ b/llvm/test/CodeGen/RISCV/epi-vector-tuple-spill-emergency.ll @@ -23,7 +23,7 @@ define void @t3fv_16(double* nocapture %ri, double* nocapture readnone %ii, doub ; CHECK-NEXT: sd s10, 80(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s11, 72(sp) # 8-byte Folded Spill ; CHECK-NEXT: csrr a1, vlenb -; CHECK-NEXT: slli a7, a1, 2 +; CHECK-NEXT: slli a7, a1, 1 ; CHECK-NEXT: add a1, a1, a7 ; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: bge a4, a5, .LBB0_3 @@ -32,11 +32,11 @@ define void @t3fv_16(double* nocapture %ri, double* nocapture readnone %ii, doub ; CHECK-NEXT: add a1, a1, a2 ; CHECK-NEXT: addi a2, zero, 2 ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vand.vi v25, v25, 1 +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: sub s10, a5, a4 ; CHECK-NEXT: addi a2, zero, 24 ; CHECK-NEXT: mul a2, a3, a2 @@ -82,338 +82,313 @@ define void @t3fv_16(double* nocapture %ri, double* nocapture readnone %ii, doub ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: addi a2, zero, 2 ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a1) +; CHECK-NEXT: vle64.v v8, (a1) ; CHECK-NEXT: addi a2, a1, 16 -; CHECK-NEXT: vle64.v v26, (a2) -; CHECK-NEXT: vtrn.vv v3, v25, v25 -; CHECK-NEXT: vfmul.vv v25, v26, v3 -; CHECK-NEXT: vtrn.vv v1, v26, v26 -; CHECK-NEXT: vfneg.v v26, v26, v0.t -; CHECK-NEXT: vtrn.vv v5, v26, v26 +; CHECK-NEXT: vle64.v v9, (a2) +; CHECK-NEXT: vtrn.vv v3, v8, v8 +; CHECK-NEXT: vfmul.vv v8, v9, v3 +; CHECK-NEXT: vtrn.vv v1, v9, v9 +; CHECK-NEXT: vfneg.v v9, v9, v0.t +; CHECK-NEXT: vtrn.vv v5, v9, v9 ; CHECK-NEXT: addi a2, a1, 48 -; CHECK-NEXT: vle64.v v28, (a2) -; CHECK-NEXT: vtrn.vv v5, v6, v26 -; CHECK-NEXT: vmv1r.v v27, v25 -; CHECK-NEXT: vfmacc.vv v27, v4, v5 -; CHECK-NEXT: vfnmsac.vv v25, v4, v5 -; CHECK-NEXT: vfmul.vv v26, v28, v3 -; CHECK-NEXT: vtrn.vv v5, v28, v28 -; CHECK-NEXT: vfneg.v v28, v28, v0.t +; CHECK-NEXT: vle64.v v11, (a2) +; CHECK-NEXT: vtrn.vv v5, v6, v9 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vfmacc.vv v10, v4, v5 +; CHECK-NEXT: vfnmsac.vv v8, v4, v5 +; CHECK-NEXT: vfmul.vv v9, v11, v3 +; CHECK-NEXT: vtrn.vv v5, v11, v11 +; CHECK-NEXT: vfneg.v v11, v11, v0.t ; CHECK-NEXT: addi a2, a1, 32 -; CHECK-NEXT: vle64.v v29, (a2) -; CHECK-NEXT: vtrn.vv v7, v28, v28 -; CHECK-NEXT: vtrn.vv v7, v8, v28 -; CHECK-NEXT: vfnmsac.vv v26, v4, v7 -; CHECK-NEXT: vfmul.vv v31, v29, v3 -; CHECK-NEXT: vfmul.vv v8, v29, v1 -; CHECK-NEXT: vtrn.vv v9, v27, v27 -; CHECK-NEXT: vfmul.vv v11, v29, v9 -; CHECK-NEXT: vtrn.vv v19, v25, v25 -; CHECK-NEXT: vfmul.vv v18, v29, v19 -; CHECK-NEXT: vtrn.vv v21, v29, v29 -; CHECK-NEXT: vfneg.v v29, v29, v0.t -; CHECK-NEXT: vtrn.vv v12, v29, v29 -; CHECK-NEXT: vtrn.vv v12, v13, v29 -; CHECK-NEXT: vmv1r.v v25, v31 -; CHECK-NEXT: vfnmsac.vv v25, v4, v12 -; CHECK-NEXT: vmv1r.v v14, v8 -; CHECK-NEXT: addi a2, sp, 72 -; CHECK-NEXT: csrr a3, vlenb -; CHECK-NEXT: vs1r.v v1, (a2) # Unknown-size Folded Spill -; CHECK-NEXT: add a2, a2, a3 -; CHECK-NEXT: vs1r.v v2, (a2) # Unknown-size Folded Spill -; CHECK-NEXT: vfnmsac.vv v14, v2, v12 -; CHECK-NEXT: vfmacc.vv v31, v4, v12 -; CHECK-NEXT: vfmacc.vv v8, v2, v12 -; CHECK-NEXT: vmv1r.v v23, v11 -; CHECK-NEXT: vfnmsac.vv v23, v10, v12 -; CHECK-NEXT: vmv1r.v v16, v18 -; CHECK-NEXT: vfnmsac.vv v16, v20, v12 -; CHECK-NEXT: vfmacc.vv v18, v20, v12 +; CHECK-NEXT: vle64.v v12, (a2) +; CHECK-NEXT: vtrn.vv v13, v11, v11 +; CHECK-NEXT: vtrn.vv v13, v14, v11 +; CHECK-NEXT: vfnmsac.vv v9, v4, v13 +; CHECK-NEXT: vfmul.vv v14, v12, v3 +; CHECK-NEXT: vfmul.vv v15, v12, v1 +; CHECK-NEXT: vtrn.vv v16, v10, v10 +; CHECK-NEXT: vfmul.vv v18, v12, v16 +; CHECK-NEXT: vtrn.vv v26, v8, v8 +; CHECK-NEXT: vfmul.vv v25, v12, v26 +; CHECK-NEXT: vtrn.vv v28, v12, v12 +; CHECK-NEXT: vfneg.v v12, v12, v0.t +; CHECK-NEXT: vtrn.vv v7, v12, v12 +; CHECK-NEXT: vtrn.vv v7, v8, v12 +; CHECK-NEXT: vmv1r.v v10, v14 +; CHECK-NEXT: vfnmsac.vv v10, v4, v7 +; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vfnmsac.vv v19, v2, v7 +; CHECK-NEXT: vfmacc.vv v14, v4, v7 +; CHECK-NEXT: vfmacc.vv v15, v2, v7 +; CHECK-NEXT: vmv1r.v v30, v18 +; CHECK-NEXT: vfnmsac.vv v30, v17, v7 +; CHECK-NEXT: vmv1r.v v23, v25 +; CHECK-NEXT: vfnmsac.vv v23, v27, v7 +; CHECK-NEXT: vfmacc.vv v25, v27, v7 ; CHECK-NEXT: add t5, a0, s9 -; CHECK-NEXT: vle64.v v27, (t5) -; CHECK-NEXT: vfmacc.vv v11, v10, v12 -; CHECK-NEXT: vle64.v v28, (a0) +; CHECK-NEXT: vle64.v v13, (t5) +; CHECK-NEXT: vfmacc.vv v18, v17, v7 +; CHECK-NEXT: vle64.v v11, (a0) ; CHECK-NEXT: csrr a2, vlenb -; CHECK-NEXT: slli a2, a2, 2 +; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: add a2, a2, sp ; CHECK-NEXT: addi a2, a2, 72 -; CHECK-NEXT: vs1r.v v28, (a2) # Unknown-size Folded Spill -; CHECK-NEXT: vtrn.vv v12, v25, v25 -; CHECK-NEXT: vfmul.vv v29, v27, v12 -; CHECK-NEXT: vfneg.v v27, v27, v0.t -; CHECK-NEXT: vtrn.vv v24, v27, v27 +; CHECK-NEXT: vs1r.v v11, (a2) # Unknown-size Folded Spill +; CHECK-NEXT: vtrn.vv v7, v10, v10 +; CHECK-NEXT: vfmul.vv v12, v13, v7 +; CHECK-NEXT: vfneg.v v13, v13, v0.t +; CHECK-NEXT: vtrn.vv v20, v13, v13 ; CHECK-NEXT: add ra, a0, s8 -; CHECK-NEXT: vle64.v v15, (ra) -; CHECK-NEXT: vtrn.vv v24, v25, v27 -; CHECK-NEXT: vfnmsac.vv v29, v13, v24 -; CHECK-NEXT: vfadd.vv v28, v28, v29 -; CHECK-NEXT: vfmul.vv v30, v15, v9 -; CHECK-NEXT: vfneg.v v15, v15, v0.t -; CHECK-NEXT: vtrn.vv v12, v15, v15 +; CHECK-NEXT: vle64.v v10, (ra) +; CHECK-NEXT: vtrn.vv v20, v21, v13 +; CHECK-NEXT: vfnmsac.vv v12, v8, v20 +; CHECK-NEXT: vfadd.vv v31, v11, v12 +; CHECK-NEXT: vfmul.vv v13, v10, v16 +; CHECK-NEXT: vfneg.v v10, v10, v0.t +; CHECK-NEXT: vtrn.vv v20, v10, v10 ; CHECK-NEXT: add s0, a0, s7 -; CHECK-NEXT: vle64.v v27, (s0) -; CHECK-NEXT: vtrn.vv v12, v13, v15 -; CHECK-NEXT: vfnmsac.vv v30, v10, v12 -; CHECK-NEXT: vtrn.vv v9, v8, v8 -; CHECK-NEXT: vfmul.vv v8, v27, v9 -; CHECK-NEXT: vfneg.v v27, v27, v0.t -; CHECK-NEXT: vtrn.vv v12, v27, v27 -; CHECK-NEXT: vtrn.vv v12, v13, v27 +; CHECK-NEXT: vle64.v v22, (s0) +; CHECK-NEXT: vtrn.vv v20, v21, v10 +; CHECK-NEXT: vfnmsac.vv v13, v17, v20 +; CHECK-NEXT: vtrn.vv v16, v15, v15 +; CHECK-NEXT: vfmul.vv v15, v22, v16 +; CHECK-NEXT: vfneg.v v22, v22, v0.t +; CHECK-NEXT: vtrn.vv v20, v22, v22 +; CHECK-NEXT: vtrn.vv v20, v21, v22 ; CHECK-NEXT: add a7, a0, s6 -; CHECK-NEXT: vle64.v v15, (a7) -; CHECK-NEXT: vfnmsac.vv v8, v10, v12 -; CHECK-NEXT: vfadd.vv v27, v30, v8 -; CHECK-NEXT: vtrn.vv v12, v26, v26 -; CHECK-NEXT: vfmul.vv v9, v15, v12 -; CHECK-NEXT: vfneg.v v15, v15, v0.t -; CHECK-NEXT: vtrn.vv v24, v15, v15 +; CHECK-NEXT: vle64.v v22, (a7) +; CHECK-NEXT: vfnmsac.vv v15, v17, v20 +; CHECK-NEXT: vfadd.vv v10, v13, v15 +; CHECK-NEXT: vtrn.vv v20, v9, v9 +; CHECK-NEXT: vfmul.vv v16, v22, v20 +; CHECK-NEXT: vfneg.v v22, v22, v0.t +; CHECK-NEXT: vtrn.vv v7, v22, v22 ; CHECK-NEXT: add t0, a0, s5 -; CHECK-NEXT: vle64.v v26, (t0) -; CHECK-NEXT: vtrn.vv v24, v25, v15 -; CHECK-NEXT: vfnmsac.vv v9, v13, v24 -; CHECK-NEXT: vtrn.vv v12, v31, v31 -; CHECK-NEXT: vfmul.vv v10, v26, v12 -; CHECK-NEXT: vfneg.v v26, v26, v0.t -; CHECK-NEXT: vtrn.vv v24, v26, v26 +; CHECK-NEXT: vle64.v v9, (t0) +; CHECK-NEXT: vtrn.vv v7, v8, v22 +; CHECK-NEXT: vfnmsac.vv v16, v21, v7 +; CHECK-NEXT: vtrn.vv v7, v14, v14 +; CHECK-NEXT: vfmul.vv v17, v9, v7 +; CHECK-NEXT: vfneg.v v9, v9, v0.t +; CHECK-NEXT: vtrn.vv v20, v9, v9 ; CHECK-NEXT: add t2, a0, s4 -; CHECK-NEXT: vle64.v v31, (t2) -; CHECK-NEXT: vtrn.vv v24, v25, v26 -; CHECK-NEXT: vfnmsac.vv v10, v13, v24 -; CHECK-NEXT: vtrn.vv v14, v14, v14 -; CHECK-NEXT: vfmul.vv v13, v31, v14 -; CHECK-NEXT: vfneg.v v31, v31, v0.t +; CHECK-NEXT: vle64.v v14, (t2) +; CHECK-NEXT: vtrn.vv v20, v21, v9 +; CHECK-NEXT: vfnmsac.vv v17, v8, v20 +; CHECK-NEXT: vtrn.vv v7, v19, v19 +; CHECK-NEXT: vfmul.vv v20, v14, v7 +; CHECK-NEXT: vfneg.v v14, v14, v0.t ; CHECK-NEXT: add t1, a0, s3 -; CHECK-NEXT: vle64.v v25, (t1) -; CHECK-NEXT: vtrn.vv v1, v31, v31 -; CHECK-NEXT: vtrn.vv v1, v2, v31 -; CHECK-NEXT: vfnmsac.vv v13, v15, v1 -; CHECK-NEXT: vfmul.vv v14, v25, v19 -; CHECK-NEXT: vfneg.v v25, v25, v0.t -; CHECK-NEXT: vtrn.vv v1, v25, v25 -; CHECK-NEXT: vtrn.vv v1, v2, v25 +; CHECK-NEXT: vle64.v v9, (t1) +; CHECK-NEXT: vtrn.vv v21, v14, v14 +; CHECK-NEXT: vtrn.vv v21, v22, v14 +; CHECK-NEXT: vfnmsac.vv v20, v8, v21 +; CHECK-NEXT: vfmul.vv v21, v9, v26 +; CHECK-NEXT: vfneg.v v9, v9, v0.t +; CHECK-NEXT: vtrn.vv v7, v9, v9 +; CHECK-NEXT: vtrn.vv v7, v8, v9 ; CHECK-NEXT: add s11, a0, s2 -; CHECK-NEXT: vle64.v v25, (s11) -; CHECK-NEXT: vfnmsac.vv v14, v20, v1 -; CHECK-NEXT: vfadd.vv v26, v9, v13 -; CHECK-NEXT: vfadd.vv v7, v14, v10 -; CHECK-NEXT: vfmul.vv v15, v25, v3 -; CHECK-NEXT: vfneg.v v25, v25, v0.t -; CHECK-NEXT: vtrn.vv v1, v25, v25 +; CHECK-NEXT: vle64.v v19, (s11) +; CHECK-NEXT: vfnmsac.vv v21, v27, v7 +; CHECK-NEXT: vfadd.vv v14, v16, v20 +; CHECK-NEXT: vfadd.vv v9, v21, v17 +; CHECK-NEXT: vfmul.vv v22, v19, v3 +; CHECK-NEXT: vfneg.v v19, v19, v0.t +; CHECK-NEXT: vtrn.vv v7, v19, v19 ; CHECK-NEXT: add a5, a0, t6 -; CHECK-NEXT: vle64.v v12, (a5) -; CHECK-NEXT: vtrn.vv v1, v2, v25 -; CHECK-NEXT: vfnmsac.vv v15, v4, v1 -; CHECK-NEXT: vtrn.vv v1, v11, v11 -; CHECK-NEXT: vfmul.vv v17, v12, v1 -; CHECK-NEXT: vfneg.v v12, v12, v0.t +; CHECK-NEXT: vle64.v v26, (a5) +; CHECK-NEXT: vtrn.vv v7, v8, v19 +; CHECK-NEXT: vfnmsac.vv v22, v4, v7 +; CHECK-NEXT: vtrn.vv v3, v18, v18 +; CHECK-NEXT: vfmul.vv v24, v26, v3 +; CHECK-NEXT: vfneg.v v26, v26, v0.t ; CHECK-NEXT: ld a2, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: add a3, a0, a2 -; CHECK-NEXT: vle64.v v25, (a3) -; CHECK-NEXT: vtrn.vv v3, v12, v12 -; CHECK-NEXT: vtrn.vv v3, v4, v12 -; CHECK-NEXT: vfnmsac.vv v17, v2, v3 -; CHECK-NEXT: vfmul.vv v19, v25, v21 -; CHECK-NEXT: vfneg.v v25, v25, v0.t -; CHECK-NEXT: vtrn.vv v1, v25, v25 +; CHECK-NEXT: vle64.v v8, (a3) +; CHECK-NEXT: vtrn.vv v18, v26, v26 +; CHECK-NEXT: vtrn.vv v18, v19, v26 +; CHECK-NEXT: vfnmsac.vv v24, v4, v18 +; CHECK-NEXT: vfmul.vv v26, v8, v28 +; CHECK-NEXT: vfneg.v v8, v8, v0.t +; CHECK-NEXT: vtrn.vv v3, v8, v8 ; CHECK-NEXT: ld a2, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: add a6, a0, a2 -; CHECK-NEXT: vle64.v v11, (a6) -; CHECK-NEXT: vtrn.vv v1, v2, v25 -; CHECK-NEXT: vfnmsac.vv v19, v22, v1 -; CHECK-NEXT: vtrn.vv v1, v23, v23 -; CHECK-NEXT: vfmul.vv v25, v11, v1 -; CHECK-NEXT: vfneg.v v11, v11, v0.t -; CHECK-NEXT: vtrn.vv v3, v11, v11 -; CHECK-NEXT: vtrn.vv v3, v4, v11 -; CHECK-NEXT: vfnmsac.vv v25, v2, v3 +; CHECK-NEXT: vle64.v v18, (a6) +; CHECK-NEXT: vtrn.vv v3, v4, v8 +; CHECK-NEXT: vfnmsac.vv v26, v29, v3 +; CHECK-NEXT: vtrn.vv v3, v30, v30 +; CHECK-NEXT: vfmul.vv v8, v18, v3 +; CHECK-NEXT: vfneg.v v18, v18, v0.t +; CHECK-NEXT: vtrn.vv v27, v18, v18 +; CHECK-NEXT: vtrn.vv v18, v28, v18 +; CHECK-NEXT: vfnmsac.vv v8, v4, v18 ; CHECK-NEXT: ld a2, 32(sp) # 8-byte Folded Reload ; CHECK-NEXT: add a4, a0, a2 -; CHECK-NEXT: vle64.v v20, (a4) -; CHECK-NEXT: vfadd.vv v11, v15, v19 -; CHECK-NEXT: csrr a2, vlenb -; CHECK-NEXT: slli a2, a2, 1 -; CHECK-NEXT: add a2, a2, sp -; CHECK-NEXT: addi a2, a2, 72 -; CHECK-NEXT: vs1r.v v11, (a2) # Unknown-size Folded Spill -; CHECK-NEXT: vfadd.vv v31, v25, v17 +; CHECK-NEXT: vle64.v v27, (a4) +; CHECK-NEXT: vfadd.vv v19, v22, v26 ; CHECK-NEXT: csrr a2, vlenb -; CHECK-NEXT: slli t3, a2, 1 -; CHECK-NEXT: add a2, a2, t3 ; CHECK-NEXT: add a2, a2, sp ; CHECK-NEXT: addi a2, a2, 72 -; CHECK-NEXT: vs1r.v v31, (a2) # Unknown-size Folded Spill -; CHECK-NEXT: vfsub.vv v21, v11, v31 -; CHECK-NEXT: vfmul.vv v22, v20, v5 -; CHECK-NEXT: vfneg.v v20, v20, v0.t -; CHECK-NEXT: vtrn.vv v1, v20, v20 +; CHECK-NEXT: vs1r.v v19, (a2) # Unknown-size Folded Spill +; CHECK-NEXT: vfadd.vv v18, v8, v24 +; CHECK-NEXT: addi a2, sp, 72 +; CHECK-NEXT: vs1r.v v18, (a2) # Unknown-size Folded Spill +; CHECK-NEXT: vfsub.vv v28, v19, v18 +; CHECK-NEXT: vfmul.vv v29, v27, v5 +; CHECK-NEXT: vfneg.v v27, v27, v0.t +; CHECK-NEXT: vtrn.vv v3, v27, v27 ; CHECK-NEXT: ld a2, 40(sp) # 8-byte Folded Reload ; CHECK-NEXT: add t3, a0, a2 -; CHECK-NEXT: vle64.v v23, (t3) -; CHECK-NEXT: vtrn.vv v1, v2, v20 -; CHECK-NEXT: vfnmsac.vv v22, v6, v1 -; CHECK-NEXT: vtrn.vv v1, v18, v18 -; CHECK-NEXT: vfmul.vv v18, v23, v1 -; CHECK-NEXT: vfneg.v v23, v23, v0.t -; CHECK-NEXT: vtrn.vv v3, v23, v23 +; CHECK-NEXT: vle64.v v30, (t3) +; CHECK-NEXT: vtrn.vv v3, v4, v27 +; CHECK-NEXT: vfnmsac.vv v29, v6, v3 +; CHECK-NEXT: vtrn.vv v3, v25, v25 +; CHECK-NEXT: vfmul.vv v25, v30, v3 +; CHECK-NEXT: vfneg.v v30, v30, v0.t +; CHECK-NEXT: vtrn.vv v5, v30, v30 ; CHECK-NEXT: ld a2, 48(sp) # 8-byte Folded Reload ; CHECK-NEXT: add s1, a0, a2 -; CHECK-NEXT: vle64.v v20, (s1) -; CHECK-NEXT: vtrn.vv v3, v4, v23 -; CHECK-NEXT: vfnmsac.vv v18, v2, v3 -; CHECK-NEXT: vtrn.vv v1, v16, v16 -; CHECK-NEXT: vfmul.vv v16, v20, v1 -; CHECK-NEXT: vfneg.v v20, v20, v0.t +; CHECK-NEXT: vle64.v v27, (s1) +; CHECK-NEXT: vtrn.vv v5, v6, v30 +; CHECK-NEXT: vfnmsac.vv v25, v4, v5 +; CHECK-NEXT: vtrn.vv v3, v23, v23 +; CHECK-NEXT: vfmul.vv v23, v27, v3 +; CHECK-NEXT: vfneg.v v27, v27, v0.t ; CHECK-NEXT: ld a2, 64(sp) # 8-byte Folded Reload ; CHECK-NEXT: add t4, a0, a2 -; CHECK-NEXT: vle64.v v23, (t4) -; CHECK-NEXT: vtrn.vv v3, v20, v20 -; CHECK-NEXT: vtrn.vv v3, v4, v20 -; CHECK-NEXT: vfnmsac.vv v16, v2, v3 -; CHECK-NEXT: addi a2, sp, 72 -; CHECK-NEXT: sd a1, 8(sp) -; CHECK-NEXT: csrr a1, vlenb -; CHECK-NEXT: vl1r.v v3, (a2) # Unknown-size Folded Reload -; CHECK-NEXT: add a2, a2, a1 -; CHECK-NEXT: vl1r.v v4, (a2) # Unknown-size Folded Reload -; CHECK-NEXT: ld a1, 8(sp) -; CHECK-NEXT: vfmul.vv v20, v23, v3 -; CHECK-NEXT: vfneg.v v23, v23, v0.t -; CHECK-NEXT: vtrn.vv v1, v23, v23 -; CHECK-NEXT: vtrn.vv v1, v2, v23 -; CHECK-NEXT: vfnmsac.vv v20, v4, v1 -; CHECK-NEXT: vfadd.vv v23, v22, v16 -; CHECK-NEXT: vfadd.vv v24, v20, v18 -; CHECK-NEXT: vfsub.vv v1, v23, v24 -; CHECK-NEXT: vfsub.vv v2, v28, v27 -; CHECK-NEXT: vmv1r.v v12, v27 -; CHECK-NEXT: vmv1r.v v11, v28 -; CHECK-NEXT: vfadd.vv v3, v21, v1 -; CHECK-NEXT: vmv1r.v v4, v2 -; CHECK-NEXT: vfnmsac.vf v4, ft1, v3 -; CHECK-NEXT: vfsub.vv v5, v26, v7 -; CHECK-NEXT: vmv1r.v v31, v26 -; CHECK-NEXT: vmv1r.v v26, v7 -; CHECK-NEXT: vfsub.vv v21, v1, v21 -; CHECK-NEXT: vmv1r.v v1, v5 -; CHECK-NEXT: vfnmsac.vf v1, ft1, v21 -; CHECK-NEXT: vfneg.v v1, v1, v0.t -; CHECK-NEXT: vtrn.vv v6, v1, v1 -; CHECK-NEXT: vtrn.vv v6, v7, v1 -; CHECK-NEXT: vfsub.vv v1, v4, v6 -; CHECK-NEXT: vse64.v v1, (t2) -; CHECK-NEXT: vfmacc.vf v2, ft1, v3 -; CHECK-NEXT: vfmacc.vf v5, ft1, v21 -; CHECK-NEXT: vfneg.v v5, v5, v0.t -; CHECK-NEXT: vtrn.vv v27, v5, v5 -; CHECK-NEXT: vtrn.vv v27, v28, v5 -; CHECK-NEXT: vfadd.vv v21, v2, v27 -; CHECK-NEXT: vse64.v v21, (t1) -; CHECK-NEXT: vfadd.vv v21, v4, v6 -; CHECK-NEXT: vse64.v v21, (t0) -; CHECK-NEXT: vfsub.vv v27, v2, v27 -; CHECK-NEXT: vse64.v v27, (a7) -; CHECK-NEXT: csrr a2, vlenb -; CHECK-NEXT: slli a2, a2, 2 -; CHECK-NEXT: add a2, a2, sp -; CHECK-NEXT: addi a2, a2, 72 -; CHECK-NEXT: vl1r.v v27, (a2) # Unknown-size Folded Reload -; CHECK-NEXT: vfsub.vv v28, v27, v29 -; CHECK-NEXT: vfsub.vv v27, v30, v8 -; CHECK-NEXT: vfsub.vv v29, v14, v10 -; CHECK-NEXT: vfsub.vv v30, v9, v13 -; CHECK-NEXT: vfadd.vv v8, v29, v30 -; CHECK-NEXT: vfsub.vv v29, v30, v29 -; CHECK-NEXT: vfsub.vv v30, v15, v19 -; CHECK-NEXT: vfsub.vv v25, v25, v17 -; CHECK-NEXT: vmv1r.v v9, v30 -; CHECK-NEXT: vfnmsac.vf v9, ft0, v25 -; CHECK-NEXT: vfmacc.vf v25, ft0, v30 -; CHECK-NEXT: vfsub.vv v30, v22, v16 -; CHECK-NEXT: vfsub.vv v10, v18, v20 -; CHECK-NEXT: vmv1r.v v13, v30 -; CHECK-NEXT: vfnmsac.vf v13, ft0, v10 -; CHECK-NEXT: vfmacc.vf v10, ft0, v30 -; CHECK-NEXT: vmv1r.v v30, v28 -; CHECK-NEXT: vfnmsac.vf v30, ft1, v8 -; CHECK-NEXT: vfadd.vv v14, v25, v10 -; CHECK-NEXT: vmv1r.v v15, v30 -; CHECK-NEXT: vfnmsac.vf v15, ft2, v14 -; CHECK-NEXT: vmv1r.v v16, v27 -; CHECK-NEXT: vfmacc.vf v16, ft1, v29 -; CHECK-NEXT: vfsub.vv v17, v13, v9 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vfnmsac.vf v18, ft2, v17 -; CHECK-NEXT: vfneg.v v18, v18, v0.t -; CHECK-NEXT: vtrn.vv v1, v18, v18 -; CHECK-NEXT: vtrn.vv v1, v2, v18 -; CHECK-NEXT: vfsub.vv v18, v15, v1 -; CHECK-NEXT: vse64.v v18, (a6) -; CHECK-NEXT: vfmacc.vf v30, ft2, v14 -; CHECK-NEXT: vfmacc.vf v16, ft2, v17 -; CHECK-NEXT: vfneg.v v16, v16, v0.t -; CHECK-NEXT: vtrn.vv v3, v16, v16 -; CHECK-NEXT: vtrn.vv v3, v4, v16 -; CHECK-NEXT: vfsub.vv v14, v30, v3 -; CHECK-NEXT: vse64.v v14, (a5) -; CHECK-NEXT: vfadd.vv v14, v15, v1 -; CHECK-NEXT: vse64.v v14, (t3) -; CHECK-NEXT: vfadd.vv v30, v30, v3 -; CHECK-NEXT: vse64.v v30, (t4) -; CHECK-NEXT: vfadd.vv v30, v11, v12 -; CHECK-NEXT: vfadd.vv v26, v26, v31 -; CHECK-NEXT: vfadd.vv v31, v30, v26 +; CHECK-NEXT: vle64.v v30, (t4) +; CHECK-NEXT: vtrn.vv v5, v27, v27 +; CHECK-NEXT: vtrn.vv v5, v6, v27 +; CHECK-NEXT: vfnmsac.vv v23, v4, v5 +; CHECK-NEXT: vfmul.vv v27, v30, v1 +; CHECK-NEXT: vfneg.v v30, v30, v0.t +; CHECK-NEXT: vtrn.vv v3, v30, v30 +; CHECK-NEXT: vtrn.vv v3, v4, v30 +; CHECK-NEXT: vfnmsac.vv v27, v2, v3 +; CHECK-NEXT: vfadd.vv v30, v29, v23 +; CHECK-NEXT: vfadd.vv v1, v27, v25 +; CHECK-NEXT: vfsub.vv v2, v30, v1 +; CHECK-NEXT: vfsub.vv v3, v31, v10 +; CHECK-NEXT: vmv1r.v v7, v10 +; CHECK-NEXT: vfadd.vv v4, v28, v2 +; CHECK-NEXT: vmv1r.v v5, v3 +; CHECK-NEXT: vfnmsac.vf v5, ft1, v4 +; CHECK-NEXT: vfsub.vv v6, v14, v9 +; CHECK-NEXT: vfsub.vv v28, v2, v28 +; CHECK-NEXT: vmv1r.v v2, v6 +; CHECK-NEXT: vfnmsac.vf v2, ft1, v28 +; CHECK-NEXT: vfneg.v v2, v2, v0.t +; CHECK-NEXT: vtrn.vv v10, v2, v2 +; CHECK-NEXT: vtrn.vv v10, v11, v2 +; CHECK-NEXT: vfsub.vv v2, v5, v10 +; CHECK-NEXT: vse64.v v2, (t2) +; CHECK-NEXT: vfmacc.vf v3, ft1, v4 +; CHECK-NEXT: vfmacc.vf v6, ft1, v28 +; CHECK-NEXT: vfneg.v v6, v6, v0.t +; CHECK-NEXT: vtrn.vv v18, v6, v6 +; CHECK-NEXT: vtrn.vv v18, v19, v6 +; CHECK-NEXT: vfadd.vv v28, v3, v18 +; CHECK-NEXT: vse64.v v28, (t1) +; CHECK-NEXT: vfadd.vv v10, v5, v10 +; CHECK-NEXT: vse64.v v10, (t0) +; CHECK-NEXT: vfsub.vv v10, v3, v18 +; CHECK-NEXT: vse64.v v10, (a7) ; CHECK-NEXT: csrr a2, vlenb -; CHECK-NEXT: slli a5, a2, 1 -; CHECK-NEXT: add a2, a2, a5 +; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: add a2, a2, sp ; CHECK-NEXT: addi a2, a2, 72 -; CHECK-NEXT: vl1r.v v11, (a2) # Unknown-size Folded Reload +; CHECK-NEXT: vl1r.v v10, (a2) # Unknown-size Folded Reload +; CHECK-NEXT: vfsub.vv v11, v10, v12 +; CHECK-NEXT: vfsub.vv v10, v13, v15 +; CHECK-NEXT: vfsub.vv v12, v21, v17 +; CHECK-NEXT: vfsub.vv v13, v16, v20 +; CHECK-NEXT: vfadd.vv v15, v12, v13 +; CHECK-NEXT: vfsub.vv v12, v13, v12 +; CHECK-NEXT: vfsub.vv v13, v22, v26 +; CHECK-NEXT: vfsub.vv v8, v8, v24 +; CHECK-NEXT: vmv1r.v v16, v13 +; CHECK-NEXT: vfnmsac.vf v16, ft0, v8 +; CHECK-NEXT: vfmacc.vf v8, ft0, v13 +; CHECK-NEXT: vfsub.vv v13, v29, v23 +; CHECK-NEXT: vfsub.vv v17, v25, v27 +; CHECK-NEXT: vmv1r.v v18, v13 +; CHECK-NEXT: vfnmsac.vf v18, ft0, v17 +; CHECK-NEXT: vfmacc.vf v17, ft0, v13 +; CHECK-NEXT: vmv1r.v v13, v11 +; CHECK-NEXT: vfnmsac.vf v13, ft1, v15 +; CHECK-NEXT: vfadd.vv v19, v8, v17 +; CHECK-NEXT: vmv1r.v v20, v13 +; CHECK-NEXT: vfnmsac.vf v20, ft2, v19 +; CHECK-NEXT: vmv1r.v v21, v10 +; CHECK-NEXT: vfmacc.vf v21, ft1, v12 +; CHECK-NEXT: vfsub.vv v22, v18, v16 +; CHECK-NEXT: vmv1r.v v23, v21 +; CHECK-NEXT: vfnmsac.vf v23, ft2, v22 +; CHECK-NEXT: vfneg.v v23, v23, v0.t +; CHECK-NEXT: vtrn.vv v2, v23, v23 +; CHECK-NEXT: vtrn.vv v2, v3, v23 +; CHECK-NEXT: vfsub.vv v23, v20, v2 +; CHECK-NEXT: vse64.v v23, (a6) +; CHECK-NEXT: vfmacc.vf v13, ft2, v19 +; CHECK-NEXT: vfmacc.vf v21, ft2, v22 +; CHECK-NEXT: vfneg.v v21, v21, v0.t +; CHECK-NEXT: vtrn.vv v4, v21, v21 +; CHECK-NEXT: vtrn.vv v4, v5, v21 +; CHECK-NEXT: vfsub.vv v19, v13, v4 +; CHECK-NEXT: vse64.v v19, (a5) +; CHECK-NEXT: vfadd.vv v19, v20, v2 +; CHECK-NEXT: vse64.v v19, (t3) +; CHECK-NEXT: vfadd.vv v13, v13, v4 +; CHECK-NEXT: vse64.v v13, (t4) +; CHECK-NEXT: vfadd.vv v13, v31, v7 +; CHECK-NEXT: vfadd.vv v14, v9, v14 +; CHECK-NEXT: vfadd.vv v19, v13, v14 ; CHECK-NEXT: csrr a2, vlenb -; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: add a2, a2, sp ; CHECK-NEXT: addi a2, a2, 72 -; CHECK-NEXT: vl1r.v v12, (a2) # Unknown-size Folded Reload -; CHECK-NEXT: vfadd.vv v11, v12, v11 -; CHECK-NEXT: vfadd.vv v12, v23, v24 -; CHECK-NEXT: vfadd.vv v14, v11, v12 -; CHECK-NEXT: vfsub.vv v15, v31, v14 -; CHECK-NEXT: vse64.v v15, (t5) -; CHECK-NEXT: vfsub.vv v26, v30, v26 -; CHECK-NEXT: vfsub.vv v30, v12, v11 -; CHECK-NEXT: vfneg.v v30, v30, v0.t -; CHECK-NEXT: vtrn.vv v1, v30, v30 -; CHECK-NEXT: vtrn.vv v1, v2, v30 -; CHECK-NEXT: vfadd.vv v30, v26, v1 -; CHECK-NEXT: vse64.v v30, (ra) -; CHECK-NEXT: vfadd.vv v30, v31, v14 -; CHECK-NEXT: vse64.v v30, (a0) -; CHECK-NEXT: vfsub.vv v26, v26, v1 -; CHECK-NEXT: vse64.v v26, (s0) -; CHECK-NEXT: vfmacc.vf v28, ft1, v8 -; CHECK-NEXT: vfadd.vv v26, v9, v13 -; CHECK-NEXT: vmv1r.v v30, v28 -; CHECK-NEXT: vfnmsac.vf v30, ft2, v26 -; CHECK-NEXT: vfnmsac.vf v27, ft1, v29 -; CHECK-NEXT: vfsub.vv v25, v25, v10 -; CHECK-NEXT: vmv1r.v v29, v27 -; CHECK-NEXT: vfnmsac.vf v29, ft2, v25 -; CHECK-NEXT: vfneg.v v29, v29, v0.t -; CHECK-NEXT: vtrn.vv v1, v29, v29 -; CHECK-NEXT: vtrn.vv v1, v2, v29 -; CHECK-NEXT: vfsub.vv v29, v30, v1 -; CHECK-NEXT: vse64.v v29, (a3) -; CHECK-NEXT: vfmacc.vf v28, ft2, v26 -; CHECK-NEXT: vfmacc.vf v27, ft2, v25 -; CHECK-NEXT: vfneg.v v27, v27, v0.t -; CHECK-NEXT: vtrn.vv v3, v27, v27 -; CHECK-NEXT: vtrn.vv v3, v4, v27 -; CHECK-NEXT: vfadd.vv v25, v28, v3 -; CHECK-NEXT: vse64.v v25, (a4) -; CHECK-NEXT: vfadd.vv v25, v30, v1 -; CHECK-NEXT: vse64.v v25, (s1) -; CHECK-NEXT: vfsub.vv v25, v28, v3 -; CHECK-NEXT: vse64.v v25, (s11) +; CHECK-NEXT: vl1r.v v9, (a2) # Unknown-size Folded Reload +; CHECK-NEXT: addi a2, sp, 72 +; CHECK-NEXT: vl1r.v v20, (a2) # Unknown-size Folded Reload +; CHECK-NEXT: vfadd.vv v9, v9, v20 +; CHECK-NEXT: vfadd.vv v20, v30, v1 +; CHECK-NEXT: vfadd.vv v21, v9, v20 +; CHECK-NEXT: vfsub.vv v22, v19, v21 +; CHECK-NEXT: vse64.v v22, (t5) +; CHECK-NEXT: vfsub.vv v13, v13, v14 +; CHECK-NEXT: vfsub.vv v9, v20, v9 +; CHECK-NEXT: vfneg.v v9, v9, v0.t +; CHECK-NEXT: vtrn.vv v1, v9, v9 +; CHECK-NEXT: vtrn.vv v1, v2, v9 +; CHECK-NEXT: vfadd.vv v9, v13, v1 +; CHECK-NEXT: vse64.v v9, (ra) +; CHECK-NEXT: vfadd.vv v9, v19, v21 +; CHECK-NEXT: vse64.v v9, (a0) +; CHECK-NEXT: vfsub.vv v9, v13, v1 +; CHECK-NEXT: vse64.v v9, (s0) +; CHECK-NEXT: vfmacc.vf v11, ft1, v15 +; CHECK-NEXT: vfadd.vv v9, v16, v18 +; CHECK-NEXT: vmv1r.v v13, v11 +; CHECK-NEXT: vfnmsac.vf v13, ft2, v9 +; CHECK-NEXT: vfnmsac.vf v10, ft1, v12 +; CHECK-NEXT: vfsub.vv v8, v8, v17 +; CHECK-NEXT: vmv1r.v v12, v10 +; CHECK-NEXT: vfnmsac.vf v12, ft2, v8 +; CHECK-NEXT: vfneg.v v12, v12, v0.t +; CHECK-NEXT: vtrn.vv v1, v12, v12 +; CHECK-NEXT: vtrn.vv v1, v2, v12 +; CHECK-NEXT: vfsub.vv v12, v13, v1 +; CHECK-NEXT: vse64.v v12, (a3) +; CHECK-NEXT: vfmacc.vf v11, ft2, v9 +; CHECK-NEXT: vfmacc.vf v10, ft2, v8 +; CHECK-NEXT: vfneg.v v10, v10, v0.t +; CHECK-NEXT: vtrn.vv v3, v10, v10 +; CHECK-NEXT: vtrn.vv v3, v4, v10 +; CHECK-NEXT: vfadd.vv v8, v11, v3 +; CHECK-NEXT: vse64.v v8, (a4) +; CHECK-NEXT: vfadd.vv v8, v13, v1 +; CHECK-NEXT: vse64.v v8, (s1) +; CHECK-NEXT: vfsub.vv v8, v11, v3 +; CHECK-NEXT: vse64.v v8, (s11) ; CHECK-NEXT: addi s10, s10, -1 ; CHECK-NEXT: ld a2, 56(sp) # 8-byte Folded Reload ; CHECK-NEXT: add a0, a0, a2 @@ -421,7 +396,7 @@ define void @t3fv_16(double* nocapture %ri, double* nocapture readnone %ii, doub ; CHECK-NEXT: bnez s10, .LBB0_2 ; CHECK-NEXT: .LBB0_3: # %for.end ; CHECK-NEXT: csrr a0, vlenb -; CHECK-NEXT: slli a1, a0, 2 +; CHECK-NEXT: slli a1, a0, 1 ; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: ld s11, 72(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/epi-vmadc-constraint.ll b/llvm/test/CodeGen/RISCV/epi-vmadc-constraint.ll index fc35fae5fc9f10b6fdd8da88c59bde03d3409eb8..7bb5a460aeaba46fb3dd6c716e37b37335a8f140 100644 --- a/llvm/test/CodeGen/RISCV/epi-vmadc-constraint.ll +++ b/llvm/test/CodeGen/RISCV/epi-vmadc-constraint.ll @@ -56,94 +56,94 @@ define dso_local void @foo(%struct.crypto_stream_chacha20_dolbeau_riscv_v_ECRYPT ; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, mu ; CHECK-NEXT: lwu a6, 0(a0) ; CHECK-NEXT: lwu a7, 4(a0) -; CHECK-NEXT: vmv.v.x v25, a6 +; CHECK-NEXT: vmv.v.x v8, a6 ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: addi a4, zero, 10 ; CHECK-NEXT: mul a3, a3, a4 ; CHECK-NEXT: add a3, a3, sp ; CHECK-NEXT: addi a3, a3, 168 -; CHECK-NEXT: vs1r.v v25, (a3) # Unknown-size Folded Spill -; CHECK-NEXT: vmv.v.x v25, a7 +; CHECK-NEXT: vs1r.v v8, (a3) # Unknown-size Folded Spill +; CHECK-NEXT: vmv.v.x v8, a7 ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: slli a4, a3, 3 ; CHECK-NEXT: add a3, a3, a4 ; CHECK-NEXT: add a3, a3, sp ; CHECK-NEXT: addi a3, a3, 168 -; CHECK-NEXT: vs1r.v v25, (a3) # Unknown-size Folded Spill +; CHECK-NEXT: vs1r.v v8, (a3) # Unknown-size Folded Spill ; CHECK-NEXT: lwu t0, 8(a0) ; CHECK-NEXT: lwu t1, 12(a0) ; CHECK-NEXT: lwu t2, 16(a0) ; CHECK-NEXT: lwu t3, 20(a0) -; CHECK-NEXT: vmv.v.x v25, t0 +; CHECK-NEXT: vmv.v.x v8, t0 ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: slli a3, a3, 3 ; CHECK-NEXT: add a3, a3, sp ; CHECK-NEXT: addi a3, a3, 168 -; CHECK-NEXT: vs1r.v v25, (a3) # Unknown-size Folded Spill -; CHECK-NEXT: vmv.v.x v25, t1 +; CHECK-NEXT: vs1r.v v8, (a3) # Unknown-size Folded Spill +; CHECK-NEXT: vmv.v.x v8, t1 ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: slli a4, a3, 3 ; CHECK-NEXT: sub a3, a4, a3 ; CHECK-NEXT: add a3, a3, sp ; CHECK-NEXT: addi a3, a3, 168 -; CHECK-NEXT: vs1r.v v25, (a3) # Unknown-size Folded Spill -; CHECK-NEXT: vmv.v.x v25, t2 +; CHECK-NEXT: vs1r.v v8, (a3) # Unknown-size Folded Spill +; CHECK-NEXT: vmv.v.x v8, t2 ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: addi a4, zero, 6 ; CHECK-NEXT: mul a3, a3, a4 ; CHECK-NEXT: add a3, a3, sp ; CHECK-NEXT: addi a3, a3, 168 -; CHECK-NEXT: vs1r.v v25, (a3) # Unknown-size Folded Spill -; CHECK-NEXT: vmv.v.x v25, t3 +; CHECK-NEXT: vs1r.v v8, (a3) # Unknown-size Folded Spill +; CHECK-NEXT: vmv.v.x v8, t3 ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: slli a4, a3, 2 ; CHECK-NEXT: add a3, a3, a4 ; CHECK-NEXT: add a3, a3, sp ; CHECK-NEXT: addi a3, a3, 168 -; CHECK-NEXT: vs1r.v v25, (a3) # Unknown-size Folded Spill +; CHECK-NEXT: vs1r.v v8, (a3) # Unknown-size Folded Spill ; CHECK-NEXT: lwu t4, 24(a0) ; CHECK-NEXT: lwu t5, 28(a0) ; CHECK-NEXT: lwu t6, 32(a0) ; CHECK-NEXT: lwu s2, 36(a0) -; CHECK-NEXT: vmv.v.x v25, t4 +; CHECK-NEXT: vmv.v.x v8, t4 ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: slli a3, a3, 2 ; CHECK-NEXT: add a3, a3, sp ; CHECK-NEXT: addi a3, a3, 168 -; CHECK-NEXT: vs1r.v v25, (a3) # Unknown-size Folded Spill -; CHECK-NEXT: vmv.v.x v25, t5 +; CHECK-NEXT: vs1r.v v8, (a3) # Unknown-size Folded Spill +; CHECK-NEXT: vmv.v.x v8, t5 ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: slli a4, a3, 1 ; CHECK-NEXT: add a3, a3, a4 ; CHECK-NEXT: add a3, a3, sp ; CHECK-NEXT: addi a3, a3, 168 -; CHECK-NEXT: vs1r.v v25, (a3) # Unknown-size Folded Spill -; CHECK-NEXT: vmv.v.x v25, t6 +; CHECK-NEXT: vs1r.v v8, (a3) # Unknown-size Folded Spill +; CHECK-NEXT: vmv.v.x v8, t6 ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: add a3, a3, sp ; CHECK-NEXT: addi a3, a3, 168 -; CHECK-NEXT: vs1r.v v25, (a3) # Unknown-size Folded Spill -; CHECK-NEXT: vmv.v.x v25, s2 +; CHECK-NEXT: vs1r.v v8, (a3) # Unknown-size Folded Spill +; CHECK-NEXT: vmv.v.x v8, s2 ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: add a3, a3, sp ; CHECK-NEXT: addi a3, a3, 168 -; CHECK-NEXT: vs1r.v v25, (a3) # Unknown-size Folded Spill +; CHECK-NEXT: vs1r.v v8, (a3) # Unknown-size Folded Spill ; CHECK-NEXT: lwu s3, 40(a0) ; CHECK-NEXT: lwu s6, 44(a0) ; CHECK-NEXT: lwu s7, 56(a0) ; CHECK-NEXT: lwu s8, 60(a0) -; CHECK-NEXT: vmv.v.x v25, s3 +; CHECK-NEXT: vmv.v.x v8, s3 ; CHECK-NEXT: addi a3, sp, 168 -; CHECK-NEXT: vs1r.v v25, (a3) # Unknown-size Folded Spill -; CHECK-NEXT: vmv.v.x v15, s6 -; CHECK-NEXT: vmv.v.x v16, s7 -; CHECK-NEXT: vmv.v.x v17, s8 +; CHECK-NEXT: vs1r.v v8, (a3) # Unknown-size Folded Spill +; CHECK-NEXT: vmv.v.x v22, s6 +; CHECK-NEXT: vmv.v.x v23, s7 +; CHECK-NEXT: vmv.v.x v24, s8 ; CHECK-NEXT: addi a4, zero, 18 ; CHECK-NEXT: addi a3, zero, -1 ; CHECK-NEXT: srli s4, a3, 1 ; CHECK-NEXT: addi s5, zero, 255 -; CHECK-NEXT: # implicit-def: $v25 +; CHECK-NEXT: # implicit-def: $v8 ; CHECK-NEXT: .LBB0_3: # %while.body ; CHECK-NEXT: # =>This Loop Header: Depth=1 ; CHECK-NEXT: # Child Loop BB0_4 Depth 2 @@ -157,14 +157,14 @@ define dso_local void @foo(%struct.crypto_stream_chacha20_dolbeau_riscv_v_ECRYPT ; CHECK-NEXT: slli s1, a3, 32 ; CHECK-NEXT: or s1, s1, s0 ; CHECK-NEXT: vsetvli zero, s10, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, s0 -; CHECK-NEXT: vmxor.mm v0, v25, v25 -; CHECK-NEXT: vid.v v27 -; CHECK-NEXT: vadc.vvm v18, v26, v27, v0 -; CHECK-NEXT: vmadc.vvm v25, v26, v27, v0 -; CHECK-NEXT: vmv.v.x v26, a3 -; CHECK-NEXT: vmv1r.v v0, v25 -; CHECK-NEXT: vadc.vim v19, v26, 0, v0 +; CHECK-NEXT: vmv.v.x v9, s0 +; CHECK-NEXT: vmxor.mm v0, v8, v8 +; CHECK-NEXT: vid.v v10 +; CHECK-NEXT: vadc.vvm v25, v9, v10, v0 +; CHECK-NEXT: vmadc.vvm v8, v9, v10, v0 +; CHECK-NEXT: vmv.v.x v9, a3 +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vadc.vim v26, v9, 0, v0 ; CHECK-NEXT: add a3, s1, s10 ; CHECK-NEXT: sw a3, 48(a0) ; CHECK-NEXT: srli a3, a3, 32 @@ -174,30 +174,30 @@ define dso_local void @foo(%struct.crypto_stream_chacha20_dolbeau_riscv_v_ECRYPT ; CHECK-NEXT: mul a3, a3, s0 ; CHECK-NEXT: add a3, a3, sp ; CHECK-NEXT: addi a3, a3, 168 -; CHECK-NEXT: vl1r.v v28, (a3) # Unknown-size Folded Reload +; CHECK-NEXT: vl1r.v v11, (a3) # Unknown-size Folded Reload ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: slli s0, a3, 3 ; CHECK-NEXT: add a3, a3, s0 ; CHECK-NEXT: add a3, a3, sp ; CHECK-NEXT: addi a3, a3, 168 -; CHECK-NEXT: vl1r.v v31, (a3) # Unknown-size Folded Reload +; CHECK-NEXT: vl1r.v v14, (a3) # Unknown-size Folded Reload ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: slli a3, a3, 3 ; CHECK-NEXT: add a3, a3, sp ; CHECK-NEXT: addi a3, a3, 168 -; CHECK-NEXT: vl1r.v v30, (a3) # Unknown-size Folded Reload +; CHECK-NEXT: vl1r.v v13, (a3) # Unknown-size Folded Reload ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: slli s0, a3, 3 ; CHECK-NEXT: sub a3, s0, a3 ; CHECK-NEXT: add a3, a3, sp ; CHECK-NEXT: addi a3, a3, 168 -; CHECK-NEXT: vl1r.v v29, (a3) # Unknown-size Folded Reload +; CHECK-NEXT: vl1r.v v12, (a3) # Unknown-size Folded Reload ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: addi s0, zero, 6 ; CHECK-NEXT: mul a3, a3, s0 ; CHECK-NEXT: add a3, a3, sp ; CHECK-NEXT: addi a3, a3, 168 -; CHECK-NEXT: vl1r.v v8, (a3) # Unknown-size Folded Reload +; CHECK-NEXT: vl1r.v v15, (a3) # Unknown-size Folded Reload ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: slli s0, a3, 2 ; CHECK-NEXT: add a3, a3, s0 @@ -225,37 +225,37 @@ define dso_local void @foo(%struct.crypto_stream_chacha20_dolbeau_riscv_v_ECRYPT ; CHECK-NEXT: addi a3, a3, 168 ; CHECK-NEXT: vl1r.v v7, (a3) # Unknown-size Folded Reload ; CHECK-NEXT: addi a3, sp, 168 -; CHECK-NEXT: vl1r.v v22, (a3) # Unknown-size Folded Reload -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v23, v18 -; CHECK-NEXT: vmv1r.v v1, v19 -; CHECK-NEXT: vmv1r.v v24, v16 -; CHECK-NEXT: vmv1r.v v20, v17 +; CHECK-NEXT: vl1r.v v29, (a3) # Unknown-size Folded Reload +; CHECK-NEXT: vmv1r.v v28, v22 +; CHECK-NEXT: vmv1r.v v30, v25 +; CHECK-NEXT: vmv1r.v v1, v26 +; CHECK-NEXT: vmv1r.v v31, v23 +; CHECK-NEXT: vmv1r.v v27, v24 ; CHECK-NEXT: .LBB0_4: # %for.body ; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 -; CHECK-NEXT: vadd.vv v26, v28, v8 -; CHECK-NEXT: vxor.vv v28, v23, v26 -; CHECK-NEXT: vsll.vi v23, v28, 16 -; CHECK-NEXT: vsrl.vi v28, v28, 16 -; CHECK-NEXT: vxor.vv v23, v23, v28 -; CHECK-NEXT: vadd.vv v0, v3, v23 -; CHECK-NEXT: vxor.vv v28, v8, v0 -; CHECK-NEXT: vsll.vi v8, v28, 12 -; CHECK-NEXT: vsrl.vi v28, v28, 20 -; CHECK-NEXT: vxor.vv v2, v8, v28 -; CHECK-NEXT: vadd.vv v28, v26, v2 -; CHECK-NEXT: vxor.vv v26, v23, v28 -; CHECK-NEXT: vsll.vi v8, v26, 8 -; CHECK-NEXT: vsrl.vi v26, v26, 24 -; CHECK-NEXT: vxor.vv v23, v8, v26 -; CHECK-NEXT: vadd.vv v8, v0, v23 -; CHECK-NEXT: vxor.vv v26, v2, v8 -; CHECK-NEXT: vsll.vi v0, v26, 7 -; CHECK-NEXT: vsrl.vi v26, v26, 25 -; CHECK-NEXT: vxor.vv v26, v0, v26 -; CHECK-NEXT: vadd.vv v31, v31, v6 -; CHECK-NEXT: vxor.vv v0, v1, v31 +; CHECK-NEXT: vadd.vv v9, v11, v15 +; CHECK-NEXT: vxor.vv v11, v30, v9 +; CHECK-NEXT: vsll.vi v30, v11, 16 +; CHECK-NEXT: vsrl.vi v11, v11, 16 +; CHECK-NEXT: vxor.vv v30, v30, v11 +; CHECK-NEXT: vadd.vv v0, v3, v30 +; CHECK-NEXT: vxor.vv v11, v15, v0 +; CHECK-NEXT: vsll.vi v15, v11, 12 +; CHECK-NEXT: vsrl.vi v11, v11, 20 +; CHECK-NEXT: vxor.vv v2, v15, v11 +; CHECK-NEXT: vadd.vv v11, v9, v2 +; CHECK-NEXT: vxor.vv v9, v30, v11 +; CHECK-NEXT: vsll.vi v15, v9, 8 +; CHECK-NEXT: vsrl.vi v9, v9, 24 +; CHECK-NEXT: vxor.vv v30, v15, v9 +; CHECK-NEXT: vadd.vv v15, v0, v30 +; CHECK-NEXT: vxor.vv v9, v2, v15 +; CHECK-NEXT: vsll.vi v0, v9, 7 +; CHECK-NEXT: vsrl.vi v9, v9, 25 +; CHECK-NEXT: vxor.vv v9, v0, v9 +; CHECK-NEXT: vadd.vv v14, v14, v6 +; CHECK-NEXT: vxor.vv v0, v1, v14 ; CHECK-NEXT: vsll.vi v1, v0, 16 ; CHECK-NEXT: vsrl.vi v0, v0, 16 ; CHECK-NEXT: vxor.vv v0, v1, v0 @@ -264,8 +264,8 @@ define dso_local void @foo(%struct.crypto_stream_chacha20_dolbeau_riscv_v_ECRYPT ; CHECK-NEXT: vsll.vi v3, v1, 12 ; CHECK-NEXT: vsrl.vi v1, v1, 20 ; CHECK-NEXT: vxor.vv v3, v3, v1 -; CHECK-NEXT: vadd.vv v31, v31, v3 -; CHECK-NEXT: vxor.vv v0, v0, v31 +; CHECK-NEXT: vadd.vv v14, v14, v3 +; CHECK-NEXT: vxor.vv v0, v0, v14 ; CHECK-NEXT: vsll.vi v1, v0, 8 ; CHECK-NEXT: vsrl.vi v0, v0, 24 ; CHECK-NEXT: vxor.vv v1, v1, v0 @@ -274,361 +274,361 @@ define dso_local void @foo(%struct.crypto_stream_chacha20_dolbeau_riscv_v_ECRYPT ; CHECK-NEXT: vsll.vi v3, v2, 7 ; CHECK-NEXT: vsrl.vi v2, v2, 25 ; CHECK-NEXT: vxor.vv v2, v3, v2 -; CHECK-NEXT: vadd.vv v30, v30, v5 -; CHECK-NEXT: vxor.vv v24, v24, v30 -; CHECK-NEXT: vsll.vi v3, v24, 16 -; CHECK-NEXT: vsrl.vi v24, v24, 16 -; CHECK-NEXT: vxor.vv v24, v3, v24 -; CHECK-NEXT: vadd.vv v22, v22, v24 -; CHECK-NEXT: vxor.vv v3, v5, v22 +; CHECK-NEXT: vadd.vv v13, v13, v5 +; CHECK-NEXT: vxor.vv v31, v31, v13 +; CHECK-NEXT: vsll.vi v3, v31, 16 +; CHECK-NEXT: vsrl.vi v31, v31, 16 +; CHECK-NEXT: vxor.vv v31, v3, v31 +; CHECK-NEXT: vadd.vv v29, v29, v31 +; CHECK-NEXT: vxor.vv v3, v5, v29 ; CHECK-NEXT: vsll.vi v5, v3, 12 ; CHECK-NEXT: vsrl.vi v3, v3, 20 ; CHECK-NEXT: vxor.vv v3, v5, v3 -; CHECK-NEXT: vadd.vv v30, v30, v3 -; CHECK-NEXT: vxor.vv v24, v24, v30 -; CHECK-NEXT: vsll.vi v5, v24, 8 -; CHECK-NEXT: vsrl.vi v24, v24, 24 -; CHECK-NEXT: vxor.vv v24, v5, v24 -; CHECK-NEXT: vadd.vv v22, v22, v24 -; CHECK-NEXT: vxor.vv v3, v3, v22 +; CHECK-NEXT: vadd.vv v13, v13, v3 +; CHECK-NEXT: vxor.vv v31, v31, v13 +; CHECK-NEXT: vsll.vi v5, v31, 8 +; CHECK-NEXT: vsrl.vi v31, v31, 24 +; CHECK-NEXT: vxor.vv v31, v5, v31 +; CHECK-NEXT: vadd.vv v29, v29, v31 +; CHECK-NEXT: vxor.vv v3, v3, v29 ; CHECK-NEXT: vsll.vi v5, v3, 7 ; CHECK-NEXT: vsrl.vi v3, v3, 25 ; CHECK-NEXT: vxor.vv v3, v5, v3 -; CHECK-NEXT: vadd.vv v29, v29, v4 -; CHECK-NEXT: vxor.vv v20, v20, v29 -; CHECK-NEXT: vsll.vi v5, v20, 16 -; CHECK-NEXT: vsrl.vi v20, v20, 16 -; CHECK-NEXT: vxor.vv v20, v5, v20 -; CHECK-NEXT: vadd.vv v21, v21, v20 -; CHECK-NEXT: vxor.vv v4, v4, v21 +; CHECK-NEXT: vadd.vv v12, v12, v4 +; CHECK-NEXT: vxor.vv v27, v27, v12 +; CHECK-NEXT: vsll.vi v5, v27, 16 +; CHECK-NEXT: vsrl.vi v27, v27, 16 +; CHECK-NEXT: vxor.vv v27, v5, v27 +; CHECK-NEXT: vadd.vv v28, v28, v27 +; CHECK-NEXT: vxor.vv v4, v4, v28 ; CHECK-NEXT: vsll.vi v5, v4, 12 ; CHECK-NEXT: vsrl.vi v4, v4, 20 ; CHECK-NEXT: vxor.vv v4, v5, v4 -; CHECK-NEXT: vadd.vv v29, v29, v4 -; CHECK-NEXT: vxor.vv v20, v20, v29 -; CHECK-NEXT: vsll.vi v5, v20, 8 -; CHECK-NEXT: vsrl.vi v20, v20, 24 -; CHECK-NEXT: vxor.vv v20, v5, v20 -; CHECK-NEXT: vadd.vv v21, v21, v20 -; CHECK-NEXT: vxor.vv v4, v4, v21 +; CHECK-NEXT: vadd.vv v12, v12, v4 +; CHECK-NEXT: vxor.vv v27, v27, v12 +; CHECK-NEXT: vsll.vi v5, v27, 8 +; CHECK-NEXT: vsrl.vi v27, v27, 24 +; CHECK-NEXT: vxor.vv v27, v5, v27 +; CHECK-NEXT: vadd.vv v28, v28, v27 +; CHECK-NEXT: vxor.vv v4, v4, v28 ; CHECK-NEXT: vsll.vi v5, v4, 7 ; CHECK-NEXT: vsrl.vi v4, v4, 25 ; CHECK-NEXT: vxor.vv v4, v5, v4 -; CHECK-NEXT: vadd.vv v28, v28, v2 -; CHECK-NEXT: vxor.vv v20, v20, v28 -; CHECK-NEXT: vsll.vi v5, v20, 16 -; CHECK-NEXT: vsrl.vi v20, v20, 16 -; CHECK-NEXT: vxor.vv v20, v5, v20 -; CHECK-NEXT: vadd.vv v22, v22, v20 -; CHECK-NEXT: vxor.vv v2, v2, v22 +; CHECK-NEXT: vadd.vv v11, v11, v2 +; CHECK-NEXT: vxor.vv v27, v27, v11 +; CHECK-NEXT: vsll.vi v5, v27, 16 +; CHECK-NEXT: vsrl.vi v27, v27, 16 +; CHECK-NEXT: vxor.vv v27, v5, v27 +; CHECK-NEXT: vadd.vv v29, v29, v27 +; CHECK-NEXT: vxor.vv v2, v2, v29 ; CHECK-NEXT: vsll.vi v5, v2, 12 ; CHECK-NEXT: vsrl.vi v2, v2, 20 ; CHECK-NEXT: vxor.vv v2, v5, v2 -; CHECK-NEXT: vadd.vv v28, v28, v2 -; CHECK-NEXT: vxor.vv v20, v20, v28 -; CHECK-NEXT: vsll.vi v5, v20, 8 -; CHECK-NEXT: vsrl.vi v20, v20, 24 -; CHECK-NEXT: vxor.vv v20, v5, v20 -; CHECK-NEXT: vadd.vv v22, v22, v20 -; CHECK-NEXT: vxor.vv v2, v2, v22 +; CHECK-NEXT: vadd.vv v11, v11, v2 +; CHECK-NEXT: vxor.vv v27, v27, v11 +; CHECK-NEXT: vsll.vi v5, v27, 8 +; CHECK-NEXT: vsrl.vi v27, v27, 24 +; CHECK-NEXT: vxor.vv v27, v5, v27 +; CHECK-NEXT: vadd.vv v29, v29, v27 +; CHECK-NEXT: vxor.vv v2, v2, v29 ; CHECK-NEXT: vsll.vi v5, v2, 7 ; CHECK-NEXT: vsrl.vi v2, v2, 25 ; CHECK-NEXT: vxor.vv v6, v5, v2 -; CHECK-NEXT: vadd.vv v31, v31, v3 -; CHECK-NEXT: vxor.vv v23, v23, v31 -; CHECK-NEXT: vsll.vi v2, v23, 16 -; CHECK-NEXT: vsrl.vi v23, v23, 16 -; CHECK-NEXT: vxor.vv v23, v2, v23 -; CHECK-NEXT: vadd.vv v21, v21, v23 -; CHECK-NEXT: vxor.vv v2, v3, v21 +; CHECK-NEXT: vadd.vv v14, v14, v3 +; CHECK-NEXT: vxor.vv v30, v30, v14 +; CHECK-NEXT: vsll.vi v2, v30, 16 +; CHECK-NEXT: vsrl.vi v30, v30, 16 +; CHECK-NEXT: vxor.vv v30, v2, v30 +; CHECK-NEXT: vadd.vv v28, v28, v30 +; CHECK-NEXT: vxor.vv v2, v3, v28 ; CHECK-NEXT: vsll.vi v3, v2, 12 ; CHECK-NEXT: vsrl.vi v2, v2, 20 ; CHECK-NEXT: vxor.vv v2, v3, v2 -; CHECK-NEXT: vadd.vv v31, v31, v2 -; CHECK-NEXT: vxor.vv v23, v23, v31 -; CHECK-NEXT: vsll.vi v3, v23, 8 -; CHECK-NEXT: vsrl.vi v23, v23, 24 -; CHECK-NEXT: vxor.vv v23, v3, v23 -; CHECK-NEXT: vadd.vv v21, v21, v23 -; CHECK-NEXT: vxor.vv v2, v2, v21 +; CHECK-NEXT: vadd.vv v14, v14, v2 +; CHECK-NEXT: vxor.vv v30, v30, v14 +; CHECK-NEXT: vsll.vi v3, v30, 8 +; CHECK-NEXT: vsrl.vi v30, v30, 24 +; CHECK-NEXT: vxor.vv v30, v3, v30 +; CHECK-NEXT: vadd.vv v28, v28, v30 +; CHECK-NEXT: vxor.vv v2, v2, v28 ; CHECK-NEXT: vsll.vi v3, v2, 7 ; CHECK-NEXT: vsrl.vi v2, v2, 25 ; CHECK-NEXT: vxor.vv v5, v3, v2 -; CHECK-NEXT: vadd.vv v30, v30, v4 -; CHECK-NEXT: vxor.vv v1, v1, v30 +; CHECK-NEXT: vadd.vv v13, v13, v4 +; CHECK-NEXT: vxor.vv v1, v1, v13 ; CHECK-NEXT: vsll.vi v2, v1, 16 ; CHECK-NEXT: vsrl.vi v1, v1, 16 ; CHECK-NEXT: vxor.vv v1, v2, v1 -; CHECK-NEXT: vadd.vv v8, v8, v1 -; CHECK-NEXT: vxor.vv v2, v4, v8 +; CHECK-NEXT: vadd.vv v15, v15, v1 +; CHECK-NEXT: vxor.vv v2, v4, v15 ; CHECK-NEXT: vsll.vi v3, v2, 12 ; CHECK-NEXT: vsrl.vi v2, v2, 20 ; CHECK-NEXT: vxor.vv v2, v3, v2 -; CHECK-NEXT: vadd.vv v30, v30, v2 -; CHECK-NEXT: vxor.vv v1, v1, v30 +; CHECK-NEXT: vadd.vv v13, v13, v2 +; CHECK-NEXT: vxor.vv v1, v1, v13 ; CHECK-NEXT: vsll.vi v3, v1, 8 ; CHECK-NEXT: vsrl.vi v1, v1, 24 ; CHECK-NEXT: vxor.vv v1, v3, v1 -; CHECK-NEXT: vadd.vv v3, v8, v1 -; CHECK-NEXT: vxor.vv v8, v2, v3 -; CHECK-NEXT: vsll.vi v2, v8, 7 -; CHECK-NEXT: vsrl.vi v8, v8, 25 -; CHECK-NEXT: vxor.vv v4, v2, v8 -; CHECK-NEXT: vadd.vv v29, v29, v26 -; CHECK-NEXT: vxor.vv v8, v24, v29 -; CHECK-NEXT: vsll.vi v24, v8, 16 -; CHECK-NEXT: vsrl.vi v8, v8, 16 -; CHECK-NEXT: vxor.vv v8, v24, v8 -; CHECK-NEXT: vadd.vv v0, v0, v8 -; CHECK-NEXT: vxor.vv v26, v26, v0 -; CHECK-NEXT: vsll.vi v24, v26, 12 -; CHECK-NEXT: vsrl.vi v26, v26, 20 -; CHECK-NEXT: vxor.vv v26, v24, v26 -; CHECK-NEXT: vadd.vv v29, v29, v26 -; CHECK-NEXT: vxor.vv v8, v8, v29 -; CHECK-NEXT: vsll.vi v24, v8, 8 -; CHECK-NEXT: vsrl.vi v8, v8, 24 -; CHECK-NEXT: vxor.vv v24, v24, v8 -; CHECK-NEXT: vadd.vv v7, v0, v24 -; CHECK-NEXT: vxor.vv v26, v26, v7 -; CHECK-NEXT: vsll.vi v8, v26, 7 -; CHECK-NEXT: vsrl.vi v26, v26, 25 +; CHECK-NEXT: vadd.vv v3, v15, v1 +; CHECK-NEXT: vxor.vv v15, v2, v3 +; CHECK-NEXT: vsll.vi v2, v15, 7 +; CHECK-NEXT: vsrl.vi v15, v15, 25 +; CHECK-NEXT: vxor.vv v4, v2, v15 +; CHECK-NEXT: vadd.vv v12, v12, v9 +; CHECK-NEXT: vxor.vv v15, v31, v12 +; CHECK-NEXT: vsll.vi v31, v15, 16 +; CHECK-NEXT: vsrl.vi v15, v15, 16 +; CHECK-NEXT: vxor.vv v15, v31, v15 +; CHECK-NEXT: vadd.vv v0, v0, v15 +; CHECK-NEXT: vxor.vv v9, v9, v0 +; CHECK-NEXT: vsll.vi v31, v9, 12 +; CHECK-NEXT: vsrl.vi v9, v9, 20 +; CHECK-NEXT: vxor.vv v9, v31, v9 +; CHECK-NEXT: vadd.vv v12, v12, v9 +; CHECK-NEXT: vxor.vv v15, v15, v12 +; CHECK-NEXT: vsll.vi v31, v15, 8 +; CHECK-NEXT: vsrl.vi v15, v15, 24 +; CHECK-NEXT: vxor.vv v31, v31, v15 +; CHECK-NEXT: vadd.vv v7, v0, v31 +; CHECK-NEXT: vxor.vv v9, v9, v7 +; CHECK-NEXT: vsll.vi v15, v9, 7 +; CHECK-NEXT: vsrl.vi v9, v9, 25 ; CHECK-NEXT: sext.w a3, a5 ; CHECK-NEXT: addiw a5, a5, 2 -; CHECK-NEXT: vxor.vv v8, v8, v26 +; CHECK-NEXT: vxor.vv v15, v15, v9 ; CHECK-NEXT: bltu a3, a4, .LBB0_4 ; CHECK-NEXT: # %bb.5: # %for.end ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: and a5, s9, s4 ; CHECK-NEXT: vsetvli zero, a5, e64, m1, ta, mu -; CHECK-NEXT: vid.v v26 -; CHECK-NEXT: vsll.vi v0, v26, 8 -; CHECK-NEXT: vsrl.vi v9, v26, 1 -; CHECK-NEXT: vrgather.vv v2, v0, v9 -; CHECK-NEXT: vadd.vi v10, v2, 8 -; CHECK-NEXT: vand.vi v26, v26, 1 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vsll.vi v0, v9, 8 +; CHECK-NEXT: vsrl.vi v16, v9, 1 +; CHECK-NEXT: vrgather.vv v2, v0, v16 +; CHECK-NEXT: vadd.vi v17, v2, 8 +; CHECK-NEXT: vand.vi v9, v9, 1 ; CHECK-NEXT: vsetvli a3, zero, e64, m1, ta, mu -; CHECK-NEXT: vand.vi v26, v26, 1 -; CHECK-NEXT: vmsne.vi v26, v26, 0 +; CHECK-NEXT: vand.vi v9, v9, 1 +; CHECK-NEXT: vmsne.vi v9, v9, 0 ; CHECK-NEXT: vsetvli zero, a5, e64, m1, ta, mu -; CHECK-NEXT: vmv1r.v v0, v26 -; CHECK-NEXT: vmerge.vvm v2, v2, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmerge.vvm v2, v2, v17, v0 ; CHECK-NEXT: vsetvli zero, s10, e32, m1, ta, mu -; CHECK-NEXT: vadd.vx v28, v28, a6 -; CHECK-NEXT: vadd.vx v31, v31, a7 -; CHECK-NEXT: vadd.vx v10, v30, t0 -; CHECK-NEXT: vadd.vx v11, v29, t1 -; CHECK-NEXT: vsrl.vi v29, v27, 1 -; CHECK-NEXT: vsll.vi v29, v29, 1 -; CHECK-NEXT: vrgather.vv v30, v28, v29 -; CHECK-NEXT: vrgather.vv v12, v31, v29 -; CHECK-NEXT: vand.vi v27, v27, 1 +; CHECK-NEXT: vadd.vx v11, v11, a6 +; CHECK-NEXT: vadd.vx v14, v14, a7 +; CHECK-NEXT: vadd.vx v17, v13, t0 +; CHECK-NEXT: vadd.vx v18, v12, t1 +; CHECK-NEXT: vsrl.vi v12, v10, 1 +; CHECK-NEXT: vsll.vi v12, v12, 1 +; CHECK-NEXT: vrgather.vv v13, v11, v12 +; CHECK-NEXT: vrgather.vv v19, v14, v12 +; CHECK-NEXT: vand.vi v10, v10, 1 ; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, mu -; CHECK-NEXT: vand.vi v27, v27, 1 -; CHECK-NEXT: vmsne.vi v27, v27, 0 +; CHECK-NEXT: vand.vi v10, v10, 1 +; CHECK-NEXT: vmsne.vi v10, v10, 0 ; CHECK-NEXT: vsetvli zero, s10, e32, m1, ta, mu -; CHECK-NEXT: vmv1r.v v0, v27 -; CHECK-NEXT: vmerge.vvm v12, v30, v12, v0 -; CHECK-NEXT: vadd.vi v30, v29, 1 -; CHECK-NEXT: vrgather.vv v13, v28, v30 -; CHECK-NEXT: vrgather.vv v28, v31, v30 -; CHECK-NEXT: vmerge.vvm v13, v13, v28, v0 -; CHECK-NEXT: vrgather.vv v28, v10, v29 -; CHECK-NEXT: vrgather.vv v31, v11, v29 -; CHECK-NEXT: vmerge.vvm v14, v28, v31, v0 -; CHECK-NEXT: vrgather.vv v28, v10, v30 -; CHECK-NEXT: vrgather.vv v31, v11, v30 -; CHECK-NEXT: vmerge.vvm v10, v28, v31, v0 +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmerge.vvm v19, v13, v19, v0 +; CHECK-NEXT: vadd.vi v13, v12, 1 +; CHECK-NEXT: vrgather.vv v20, v11, v13 +; CHECK-NEXT: vrgather.vv v11, v14, v13 +; CHECK-NEXT: vmerge.vvm v20, v20, v11, v0 +; CHECK-NEXT: vrgather.vv v11, v17, v12 +; CHECK-NEXT: vrgather.vv v14, v18, v12 +; CHECK-NEXT: vmerge.vvm v21, v11, v14, v0 +; CHECK-NEXT: vrgather.vv v11, v17, v13 +; CHECK-NEXT: vrgather.vv v14, v18, v13 +; CHECK-NEXT: vmerge.vvm v17, v11, v14, v0 ; CHECK-NEXT: vsetvli zero, a5, e64, m1, ta, mu -; CHECK-NEXT: vsll.vi v28, v9, 1 -; CHECK-NEXT: vrgather.vv v31, v12, v28 -; CHECK-NEXT: vluxei64.v v9, (a1), v2 -; CHECK-NEXT: vrgather.vv v11, v14, v28 -; CHECK-NEXT: vmv1r.v v0, v26 -; CHECK-NEXT: vmerge.vvm v31, v31, v11, v0 -; CHECK-NEXT: vrgather.vv v11, v13, v28 -; CHECK-NEXT: vxor.vv v31, v31, v9 -; CHECK-NEXT: vsuxei64.v v31, (a2), v2 +; CHECK-NEXT: vsll.vi v11, v16, 1 +; CHECK-NEXT: vrgather.vv v14, v19, v11 +; CHECK-NEXT: vluxei64.v v16, (a1), v2 +; CHECK-NEXT: vrgather.vv v18, v21, v11 +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmerge.vvm v14, v14, v18, v0 +; CHECK-NEXT: vrgather.vv v18, v20, v11 +; CHECK-NEXT: vxor.vv v14, v14, v16 +; CHECK-NEXT: vsuxei64.v v14, (a2), v2 ; CHECK-NEXT: addi a3, a1, 64 -; CHECK-NEXT: vluxei64.v v9, (a3), v2 -; CHECK-NEXT: vrgather.vv v31, v10, v28 -; CHECK-NEXT: vmerge.vvm v11, v11, v31, v0 -; CHECK-NEXT: vadd.vi v31, v28, 1 -; CHECK-NEXT: vxor.vv v9, v11, v9 +; CHECK-NEXT: vluxei64.v v16, (a3), v2 +; CHECK-NEXT: vrgather.vv v14, v17, v11 +; CHECK-NEXT: vmerge.vvm v18, v18, v14, v0 +; CHECK-NEXT: vadd.vi v14, v11, 1 +; CHECK-NEXT: vxor.vv v16, v18, v16 ; CHECK-NEXT: addi a3, a2, 64 -; CHECK-NEXT: vsuxei64.v v9, (a3), v2 +; CHECK-NEXT: vsuxei64.v v16, (a3), v2 ; CHECK-NEXT: addi a3, a1, 128 -; CHECK-NEXT: vluxei64.v v9, (a3), v2 -; CHECK-NEXT: vrgather.vv v11, v12, v31 -; CHECK-NEXT: vrgather.vv v12, v14, v31 -; CHECK-NEXT: vmerge.vvm v11, v11, v12, v0 -; CHECK-NEXT: vxor.vv v9, v11, v9 +; CHECK-NEXT: vluxei64.v v16, (a3), v2 +; CHECK-NEXT: vrgather.vv v18, v19, v14 +; CHECK-NEXT: vrgather.vv v19, v21, v14 +; CHECK-NEXT: vmerge.vvm v18, v18, v19, v0 +; CHECK-NEXT: vxor.vv v16, v18, v16 ; CHECK-NEXT: addi a3, a2, 128 -; CHECK-NEXT: vsuxei64.v v9, (a3), v2 +; CHECK-NEXT: vsuxei64.v v16, (a3), v2 ; CHECK-NEXT: addi a3, a1, 192 -; CHECK-NEXT: vluxei64.v v9, (a3), v2 -; CHECK-NEXT: vrgather.vv v11, v13, v31 -; CHECK-NEXT: vrgather.vv v12, v10, v31 -; CHECK-NEXT: vmerge.vvm v10, v11, v12, v0 -; CHECK-NEXT: vxor.vv v9, v10, v9 +; CHECK-NEXT: vluxei64.v v16, (a3), v2 +; CHECK-NEXT: vrgather.vv v18, v20, v14 +; CHECK-NEXT: vrgather.vv v19, v17, v14 +; CHECK-NEXT: vmerge.vvm v17, v18, v19, v0 +; CHECK-NEXT: vxor.vv v16, v17, v16 ; CHECK-NEXT: addi a3, a2, 192 -; CHECK-NEXT: vsuxei64.v v9, (a3), v2 +; CHECK-NEXT: vsuxei64.v v16, (a3), v2 ; CHECK-NEXT: addi a3, a1, 16 ; CHECK-NEXT: addi s0, a2, 16 ; CHECK-NEXT: vsetvli zero, s10, e32, m1, ta, mu -; CHECK-NEXT: vadd.vx v8, v8, t2 -; CHECK-NEXT: vadd.vx v9, v6, t3 -; CHECK-NEXT: vadd.vx v10, v5, t4 -; CHECK-NEXT: vadd.vx v11, v4, t5 -; CHECK-NEXT: vrgather.vv v12, v8, v29 -; CHECK-NEXT: vrgather.vv v13, v9, v29 -; CHECK-NEXT: vmv1r.v v0, v27 -; CHECK-NEXT: vmerge.vvm v12, v12, v13, v0 -; CHECK-NEXT: vrgather.vv v13, v8, v30 -; CHECK-NEXT: vrgather.vv v8, v9, v30 -; CHECK-NEXT: vmerge.vvm v8, v13, v8, v0 -; CHECK-NEXT: vrgather.vv v9, v10, v29 -; CHECK-NEXT: vrgather.vv v13, v11, v29 -; CHECK-NEXT: vmerge.vvm v9, v9, v13, v0 -; CHECK-NEXT: vrgather.vv v13, v10, v30 -; CHECK-NEXT: vrgather.vv v10, v11, v30 -; CHECK-NEXT: vmerge.vvm v10, v13, v10, v0 +; CHECK-NEXT: vadd.vx v15, v15, t2 +; CHECK-NEXT: vadd.vx v16, v6, t3 +; CHECK-NEXT: vadd.vx v17, v5, t4 +; CHECK-NEXT: vadd.vx v18, v4, t5 +; CHECK-NEXT: vrgather.vv v19, v15, v12 +; CHECK-NEXT: vrgather.vv v20, v16, v12 +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmerge.vvm v19, v19, v20, v0 +; CHECK-NEXT: vrgather.vv v20, v15, v13 +; CHECK-NEXT: vrgather.vv v15, v16, v13 +; CHECK-NEXT: vmerge.vvm v15, v20, v15, v0 +; CHECK-NEXT: vrgather.vv v16, v17, v12 +; CHECK-NEXT: vrgather.vv v20, v18, v12 +; CHECK-NEXT: vmerge.vvm v16, v16, v20, v0 +; CHECK-NEXT: vrgather.vv v20, v17, v13 +; CHECK-NEXT: vrgather.vv v17, v18, v13 +; CHECK-NEXT: vmerge.vvm v17, v20, v17, v0 ; CHECK-NEXT: vsetvli zero, a5, e64, m1, ta, mu -; CHECK-NEXT: vluxei64.v v11, (a3), v2 -; CHECK-NEXT: vrgather.vv v13, v12, v28 -; CHECK-NEXT: vrgather.vv v14, v9, v28 -; CHECK-NEXT: vmv1r.v v0, v26 -; CHECK-NEXT: vmerge.vvm v13, v13, v14, v0 -; CHECK-NEXT: vxor.vv v11, v13, v11 -; CHECK-NEXT: vsuxei64.v v11, (s0), v2 +; CHECK-NEXT: vluxei64.v v18, (a3), v2 +; CHECK-NEXT: vrgather.vv v20, v19, v11 +; CHECK-NEXT: vrgather.vv v21, v16, v11 +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmerge.vvm v20, v20, v21, v0 +; CHECK-NEXT: vxor.vv v18, v20, v18 +; CHECK-NEXT: vsuxei64.v v18, (s0), v2 ; CHECK-NEXT: addi a3, a1, 80 -; CHECK-NEXT: vluxei64.v v11, (a3), v2 -; CHECK-NEXT: vrgather.vv v13, v8, v28 -; CHECK-NEXT: vrgather.vv v14, v10, v28 -; CHECK-NEXT: vmerge.vvm v13, v13, v14, v0 -; CHECK-NEXT: vxor.vv v11, v13, v11 +; CHECK-NEXT: vluxei64.v v18, (a3), v2 +; CHECK-NEXT: vrgather.vv v20, v15, v11 +; CHECK-NEXT: vrgather.vv v21, v17, v11 +; CHECK-NEXT: vmerge.vvm v20, v20, v21, v0 +; CHECK-NEXT: vxor.vv v18, v20, v18 ; CHECK-NEXT: addi a3, a2, 80 -; CHECK-NEXT: vsuxei64.v v11, (a3), v2 +; CHECK-NEXT: vsuxei64.v v18, (a3), v2 ; CHECK-NEXT: addi a3, a1, 144 -; CHECK-NEXT: vluxei64.v v11, (a3), v2 -; CHECK-NEXT: vrgather.vv v13, v12, v31 -; CHECK-NEXT: vrgather.vv v12, v9, v31 -; CHECK-NEXT: vmerge.vvm v9, v13, v12, v0 -; CHECK-NEXT: vxor.vv v9, v9, v11 +; CHECK-NEXT: vluxei64.v v18, (a3), v2 +; CHECK-NEXT: vrgather.vv v20, v19, v14 +; CHECK-NEXT: vrgather.vv v19, v16, v14 +; CHECK-NEXT: vmerge.vvm v16, v20, v19, v0 +; CHECK-NEXT: vxor.vv v16, v16, v18 ; CHECK-NEXT: addi a3, a2, 144 -; CHECK-NEXT: vsuxei64.v v9, (a3), v2 +; CHECK-NEXT: vsuxei64.v v16, (a3), v2 ; CHECK-NEXT: addi a3, a1, 208 -; CHECK-NEXT: vluxei64.v v9, (a3), v2 -; CHECK-NEXT: vrgather.vv v11, v8, v31 -; CHECK-NEXT: vrgather.vv v8, v10, v31 -; CHECK-NEXT: vmerge.vvm v8, v11, v8, v0 -; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: vluxei64.v v16, (a3), v2 +; CHECK-NEXT: vrgather.vv v18, v15, v14 +; CHECK-NEXT: vrgather.vv v15, v17, v14 +; CHECK-NEXT: vmerge.vvm v15, v18, v15, v0 +; CHECK-NEXT: vxor.vv v15, v15, v16 ; CHECK-NEXT: addi a3, a2, 208 -; CHECK-NEXT: vsuxei64.v v8, (a3), v2 +; CHECK-NEXT: vsuxei64.v v15, (a3), v2 ; CHECK-NEXT: addi a3, a1, 32 ; CHECK-NEXT: addi s0, a2, 32 ; CHECK-NEXT: vsetvli zero, s10, e32, m1, ta, mu -; CHECK-NEXT: vadd.vx v8, v3, t6 -; CHECK-NEXT: vadd.vx v9, v7, s2 -; CHECK-NEXT: vadd.vx v10, v22, s3 -; CHECK-NEXT: vadd.vx v11, v21, s6 -; CHECK-NEXT: vrgather.vv v12, v8, v29 -; CHECK-NEXT: vrgather.vv v13, v9, v29 -; CHECK-NEXT: vmv1r.v v0, v27 -; CHECK-NEXT: vmerge.vvm v12, v12, v13, v0 -; CHECK-NEXT: vrgather.vv v13, v8, v30 -; CHECK-NEXT: vrgather.vv v8, v9, v30 -; CHECK-NEXT: vmerge.vvm v8, v13, v8, v0 -; CHECK-NEXT: vrgather.vv v9, v10, v29 -; CHECK-NEXT: vrgather.vv v13, v11, v29 -; CHECK-NEXT: vmerge.vvm v9, v9, v13, v0 -; CHECK-NEXT: vrgather.vv v13, v10, v30 -; CHECK-NEXT: vrgather.vv v10, v11, v30 -; CHECK-NEXT: vmerge.vvm v10, v13, v10, v0 +; CHECK-NEXT: vadd.vx v15, v3, t6 +; CHECK-NEXT: vadd.vx v16, v7, s2 +; CHECK-NEXT: vadd.vx v17, v29, s3 +; CHECK-NEXT: vadd.vx v18, v28, s6 +; CHECK-NEXT: vrgather.vv v19, v15, v12 +; CHECK-NEXT: vrgather.vv v20, v16, v12 +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmerge.vvm v19, v19, v20, v0 +; CHECK-NEXT: vrgather.vv v20, v15, v13 +; CHECK-NEXT: vrgather.vv v15, v16, v13 +; CHECK-NEXT: vmerge.vvm v15, v20, v15, v0 +; CHECK-NEXT: vrgather.vv v16, v17, v12 +; CHECK-NEXT: vrgather.vv v20, v18, v12 +; CHECK-NEXT: vmerge.vvm v16, v16, v20, v0 +; CHECK-NEXT: vrgather.vv v20, v17, v13 +; CHECK-NEXT: vrgather.vv v17, v18, v13 +; CHECK-NEXT: vmerge.vvm v17, v20, v17, v0 ; CHECK-NEXT: vsetvli zero, a5, e64, m1, ta, mu -; CHECK-NEXT: vluxei64.v v11, (a3), v2 -; CHECK-NEXT: vrgather.vv v13, v12, v28 -; CHECK-NEXT: vrgather.vv v14, v9, v28 -; CHECK-NEXT: vmv1r.v v0, v26 -; CHECK-NEXT: vmerge.vvm v13, v13, v14, v0 -; CHECK-NEXT: vxor.vv v11, v13, v11 -; CHECK-NEXT: vsuxei64.v v11, (s0), v2 +; CHECK-NEXT: vluxei64.v v18, (a3), v2 +; CHECK-NEXT: vrgather.vv v20, v19, v11 +; CHECK-NEXT: vrgather.vv v21, v16, v11 +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmerge.vvm v20, v20, v21, v0 +; CHECK-NEXT: vxor.vv v18, v20, v18 +; CHECK-NEXT: vsuxei64.v v18, (s0), v2 ; CHECK-NEXT: addi a3, a1, 96 -; CHECK-NEXT: vluxei64.v v11, (a3), v2 -; CHECK-NEXT: vrgather.vv v13, v8, v28 -; CHECK-NEXT: vrgather.vv v14, v10, v28 -; CHECK-NEXT: vmerge.vvm v13, v13, v14, v0 -; CHECK-NEXT: vxor.vv v11, v13, v11 +; CHECK-NEXT: vluxei64.v v18, (a3), v2 +; CHECK-NEXT: vrgather.vv v20, v15, v11 +; CHECK-NEXT: vrgather.vv v21, v17, v11 +; CHECK-NEXT: vmerge.vvm v20, v20, v21, v0 +; CHECK-NEXT: vxor.vv v18, v20, v18 ; CHECK-NEXT: addi a3, a2, 96 -; CHECK-NEXT: vsuxei64.v v11, (a3), v2 +; CHECK-NEXT: vsuxei64.v v18, (a3), v2 ; CHECK-NEXT: addi a3, a1, 160 -; CHECK-NEXT: vluxei64.v v11, (a3), v2 -; CHECK-NEXT: vrgather.vv v13, v12, v31 -; CHECK-NEXT: vrgather.vv v12, v9, v31 -; CHECK-NEXT: vmerge.vvm v9, v13, v12, v0 -; CHECK-NEXT: vxor.vv v9, v9, v11 +; CHECK-NEXT: vluxei64.v v18, (a3), v2 +; CHECK-NEXT: vrgather.vv v20, v19, v14 +; CHECK-NEXT: vrgather.vv v19, v16, v14 +; CHECK-NEXT: vmerge.vvm v16, v20, v19, v0 +; CHECK-NEXT: vxor.vv v16, v16, v18 ; CHECK-NEXT: addi a3, a2, 160 -; CHECK-NEXT: vsuxei64.v v9, (a3), v2 +; CHECK-NEXT: vsuxei64.v v16, (a3), v2 ; CHECK-NEXT: addi a3, a1, 224 -; CHECK-NEXT: vluxei64.v v9, (a3), v2 -; CHECK-NEXT: vrgather.vv v11, v8, v31 -; CHECK-NEXT: vrgather.vv v8, v10, v31 -; CHECK-NEXT: vmerge.vvm v8, v11, v8, v0 -; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: vluxei64.v v16, (a3), v2 +; CHECK-NEXT: vrgather.vv v18, v15, v14 +; CHECK-NEXT: vrgather.vv v15, v17, v14 +; CHECK-NEXT: vmerge.vvm v15, v18, v15, v0 +; CHECK-NEXT: vxor.vv v15, v15, v16 ; CHECK-NEXT: addi a3, a2, 224 -; CHECK-NEXT: vsuxei64.v v8, (a3), v2 +; CHECK-NEXT: vsuxei64.v v15, (a3), v2 ; CHECK-NEXT: addi a3, a1, 48 ; CHECK-NEXT: addi s0, a2, 48 ; CHECK-NEXT: vsetvli zero, s10, e32, m1, ta, mu -; CHECK-NEXT: vadd.vv v8, v23, v18 -; CHECK-NEXT: vadd.vv v9, v1, v19 -; CHECK-NEXT: vadd.vx v10, v24, s7 -; CHECK-NEXT: vadd.vx v11, v20, s8 -; CHECK-NEXT: vrgather.vv v12, v8, v29 -; CHECK-NEXT: vrgather.vv v13, v9, v29 -; CHECK-NEXT: vmv1r.v v0, v27 -; CHECK-NEXT: vmerge.vvm v12, v12, v13, v0 -; CHECK-NEXT: vrgather.vv v13, v8, v30 -; CHECK-NEXT: vrgather.vv v8, v9, v30 -; CHECK-NEXT: vmerge.vvm v8, v13, v8, v0 -; CHECK-NEXT: vrgather.vv v9, v10, v29 -; CHECK-NEXT: vrgather.vv v13, v11, v29 -; CHECK-NEXT: vmerge.vvm v29, v9, v13, v0 -; CHECK-NEXT: vrgather.vv v9, v10, v30 -; CHECK-NEXT: vrgather.vv v10, v11, v30 -; CHECK-NEXT: vmerge.vvm v27, v9, v10, v0 +; CHECK-NEXT: vadd.vv v15, v30, v25 +; CHECK-NEXT: vadd.vv v16, v1, v26 +; CHECK-NEXT: vadd.vx v17, v31, s7 +; CHECK-NEXT: vadd.vx v18, v27, s8 +; CHECK-NEXT: vrgather.vv v19, v15, v12 +; CHECK-NEXT: vrgather.vv v20, v16, v12 +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmerge.vvm v19, v19, v20, v0 +; CHECK-NEXT: vrgather.vv v20, v15, v13 +; CHECK-NEXT: vrgather.vv v15, v16, v13 +; CHECK-NEXT: vmerge.vvm v15, v20, v15, v0 +; CHECK-NEXT: vrgather.vv v16, v17, v12 +; CHECK-NEXT: vrgather.vv v20, v18, v12 +; CHECK-NEXT: vmerge.vvm v12, v16, v20, v0 +; CHECK-NEXT: vrgather.vv v16, v17, v13 +; CHECK-NEXT: vrgather.vv v17, v18, v13 +; CHECK-NEXT: vmerge.vvm v10, v16, v17, v0 ; CHECK-NEXT: vsetvli zero, a5, e64, m1, ta, mu -; CHECK-NEXT: vluxei64.v v30, (a3), v2 -; CHECK-NEXT: vrgather.vv v9, v12, v28 -; CHECK-NEXT: vrgather.vv v10, v29, v28 -; CHECK-NEXT: vmv1r.v v0, v26 -; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 -; CHECK-NEXT: vxor.vv v30, v9, v30 -; CHECK-NEXT: vsuxei64.v v30, (s0), v2 +; CHECK-NEXT: vluxei64.v v13, (a3), v2 +; CHECK-NEXT: vrgather.vv v16, v19, v11 +; CHECK-NEXT: vrgather.vv v17, v12, v11 +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmerge.vvm v16, v16, v17, v0 +; CHECK-NEXT: vxor.vv v13, v16, v13 +; CHECK-NEXT: vsuxei64.v v13, (s0), v2 ; CHECK-NEXT: addi a3, a1, 112 -; CHECK-NEXT: vluxei64.v v30, (a3), v2 -; CHECK-NEXT: vrgather.vv v9, v8, v28 -; CHECK-NEXT: vrgather.vv v10, v27, v28 -; CHECK-NEXT: vmerge.vvm v28, v9, v10, v0 -; CHECK-NEXT: vxor.vv v28, v28, v30 +; CHECK-NEXT: vluxei64.v v13, (a3), v2 +; CHECK-NEXT: vrgather.vv v16, v15, v11 +; CHECK-NEXT: vrgather.vv v17, v10, v11 +; CHECK-NEXT: vmerge.vvm v11, v16, v17, v0 +; CHECK-NEXT: vxor.vv v11, v11, v13 ; CHECK-NEXT: addi a3, a2, 112 -; CHECK-NEXT: vsuxei64.v v28, (a3), v2 +; CHECK-NEXT: vsuxei64.v v11, (a3), v2 ; CHECK-NEXT: addi a3, a1, 176 -; CHECK-NEXT: vluxei64.v v28, (a3), v2 -; CHECK-NEXT: vrgather.vv v30, v12, v31 -; CHECK-NEXT: vrgather.vv v9, v29, v31 -; CHECK-NEXT: vmerge.vvm v29, v30, v9, v0 -; CHECK-NEXT: vxor.vv v28, v29, v28 +; CHECK-NEXT: vluxei64.v v11, (a3), v2 +; CHECK-NEXT: vrgather.vv v13, v19, v14 +; CHECK-NEXT: vrgather.vv v16, v12, v14 +; CHECK-NEXT: vmerge.vvm v12, v13, v16, v0 +; CHECK-NEXT: vxor.vv v11, v12, v11 ; CHECK-NEXT: addi a3, a2, 176 -; CHECK-NEXT: vsuxei64.v v28, (a3), v2 +; CHECK-NEXT: vsuxei64.v v11, (a3), v2 ; CHECK-NEXT: addi a3, a1, 240 -; CHECK-NEXT: vluxei64.v v28, (a3), v2 -; CHECK-NEXT: vrgather.vv v29, v8, v31 -; CHECK-NEXT: vrgather.vv v30, v27, v31 -; CHECK-NEXT: vmerge.vvm v26, v29, v30, v0 -; CHECK-NEXT: vxor.vv v26, v26, v28 +; CHECK-NEXT: vluxei64.v v11, (a3), v2 +; CHECK-NEXT: vrgather.vv v12, v15, v14 +; CHECK-NEXT: vrgather.vv v13, v10, v14 +; CHECK-NEXT: vmerge.vvm v9, v12, v13, v0 +; CHECK-NEXT: vxor.vv v9, v9, v11 ; CHECK-NEXT: addi a3, a2, 240 -; CHECK-NEXT: vsuxei64.v v26, (a3), v2 +; CHECK-NEXT: vsuxei64.v v9, (a3), v2 ; CHECK-NEXT: slli a3, s9, 7 ; CHECK-NEXT: subw s11, s11, a3 ; CHECK-NEXT: add a2, a2, a3 diff --git a/llvm/test/CodeGen/RISCV/epi-vp-fcmp-fold-splats.ll b/llvm/test/CodeGen/RISCV/epi-vp-fcmp-fold-splats.ll index 6e3dfd2266071cff741b75fe34feca510ec57241..b08493fad78c07453171a0962879ac1fcb8d7eb8 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-fcmp-fold-splats.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-fcmp-fold-splats.ll @@ -14,36 +14,37 @@ define void @test_vp_fold_greater_splats( %a, double %b, %a, double %b, * @@ -104,38 +105,39 @@ define void @test_vp_fold_lower_splats( %a, %a, * diff --git a/llvm/test/CodeGen/RISCV/epi-vp-fcmp-unmasked.ll b/llvm/test/CodeGen/RISCV/epi-vp-fcmp-unmasked.ll index 6ae9724c60d71abce4f74470956134d004622ad9..4708b12155cd2deeae9b586e512f4accbc2d309f 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-fcmp-unmasked.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-fcmp-unmasked.ll @@ -12,93 +12,95 @@ define void @test_vp_fcmp( %a, %b, i3 ; CHECK-O0-NEXT: addi sp, sp, -16 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: sub sp, sp, a1 +; CHECK-O0-NEXT: vmv1r.v v10, v9 +; CHECK-O0-NEXT: vmv1r.v v9, v8 ; CHECK-O0-NEXT: slli a1, a0, 32 ; CHECK-O0-NEXT: srli a1, a1, 32 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vmset.m v25 -; CHECK-O0-NEXT: vmclr.m v26 -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vmset.m v8 +; CHECK-O0-NEXT: vmclr.m v11 +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmfeq.vv v26, v8, v9 +; CHECK-O0-NEXT: vmfeq.vv v11, v9, v10 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmflt.vv v26, v9, v8 +; CHECK-O0-NEXT: vmflt.vv v11, v10, v9 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmfle.vv v26, v9, v8 +; CHECK-O0-NEXT: vmfle.vv v11, v10, v9 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmflt.vv v26, v8, v9 +; CHECK-O0-NEXT: vmflt.vv v11, v9, v10 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmfle.vv v26, v8, v9 +; CHECK-O0-NEXT: vmfle.vv v11, v9, v10 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmfeq.vv v27, v9, v9 -; CHECK-O0-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-O0-NEXT: vmand.mm v0, v26, v27 +; CHECK-O0-NEXT: vmfeq.vv v12, v10, v10 +; CHECK-O0-NEXT: vmfeq.vv v11, v9, v9 +; CHECK-O0-NEXT: vmand.mm v0, v11, v12 ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vs1r.v v0, (a2) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v26 -; CHECK-O0-NEXT: vmfne.vv v26, v8, v9, v0.t +; CHECK-O0-NEXT: # implicit-def: $v11 +; CHECK-O0-NEXT: vmfne.vv v11, v9, v10, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmand.mm v26, v26, v0 +; CHECK-O0-NEXT: vmand.mm v11, v11, v0 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsm.v v0, (a0) -; CHECK-O0-NEXT: vmnand.mm v27, v0, v0 -; CHECK-O0-NEXT: vsm.v v27, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vmnand.mm v12, v0, v0 +; CHECK-O0-NEXT: vsm.v v12, (a0) +; CHECK-O0-NEXT: # implicit-def: $v11 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmfeq.vv v26, v8, v9, v0.t +; CHECK-O0-NEXT: vmfeq.vv v11, v9, v10, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v11, v11, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v11, (a0) +; CHECK-O0-NEXT: # implicit-def: $v11 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmflt.vv v26, v9, v8, v0.t +; CHECK-O0-NEXT: vmflt.vv v11, v10, v9, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v11, v11, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v11, (a0) +; CHECK-O0-NEXT: # implicit-def: $v11 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmfle.vv v26, v9, v8, v0.t +; CHECK-O0-NEXT: vmfle.vv v11, v10, v9, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v11, v11, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v11, (a0) +; CHECK-O0-NEXT: # implicit-def: $v11 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmflt.vv v26, v8, v9, v0.t +; CHECK-O0-NEXT: vmflt.vv v11, v9, v10, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v11, v11, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v11, (a0) +; CHECK-O0-NEXT: # implicit-def: $v11 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmfle.vv v26, v8, v9, v0.t -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmfle.vv v11, v9, v10, v0.t +; CHECK-O0-NEXT: vmor.mm v11, v11, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmfne.vv v26, v8, v9 +; CHECK-O0-NEXT: vmfne.vv v9, v9, v10 ; CHECK-O0-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v9, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: add sp, sp, a0 ; CHECK-O0-NEXT: addi sp, sp, 16 @@ -111,70 +113,70 @@ define void @test_vp_fcmp( %a, %b, i3 ; CHECK-O2-NEXT: lui a0, %hi(scratch) ; CHECK-O2-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vmset.m v25 -; CHECK-O2-NEXT: vmclr.m v26 -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vmset.m v10 +; CHECK-O2-NEXT: vmclr.m v11 +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vmfeq.vv v26, v8, v9 +; CHECK-O2-NEXT: vmfeq.vv v11, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vmflt.vv v26, v9, v8 +; CHECK-O2-NEXT: vmflt.vv v11, v9, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vmfle.vv v26, v9, v8 +; CHECK-O2-NEXT: vmfle.vv v11, v9, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vmflt.vv v26, v8, v9 +; CHECK-O2-NEXT: vmflt.vv v11, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vmfle.vv v26, v8, v9 +; CHECK-O2-NEXT: vmfle.vv v11, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vmfeq.vv v26, v9, v9 -; CHECK-O2-NEXT: vmfeq.vv v27, v8, v8 -; CHECK-O2-NEXT: vmand.mm v0, v27, v26 -; CHECK-O2-NEXT: vmfne.vv v26, v8, v9, v0.t -; CHECK-O2-NEXT: vmand.mm v26, v26, v0 +; CHECK-O2-NEXT: vmfeq.vv v11, v9, v9 +; CHECK-O2-NEXT: vmfeq.vv v12, v8, v8 +; CHECK-O2-NEXT: vmand.mm v0, v12, v11 +; CHECK-O2-NEXT: vmfne.vv v11, v8, v9, v0.t +; CHECK-O2-NEXT: vmand.mm v11, v11, v0 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsm.v v0, (a0) -; CHECK-O2-NEXT: vmnand.mm v26, v0, v0 -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vmnand.mm v11, v0, v0 +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vmfeq.vv v27, v8, v9, v0.t -; CHECK-O2-NEXT: vmor.mm v27, v27, v26 +; CHECK-O2-NEXT: vmfeq.vv v12, v8, v9, v0.t +; CHECK-O2-NEXT: vmor.mm v12, v12, v11 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v27, (a0) +; CHECK-O2-NEXT: vsm.v v12, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vmflt.vv v27, v9, v8, v0.t -; CHECK-O2-NEXT: vmor.mm v27, v27, v26 +; CHECK-O2-NEXT: vmflt.vv v12, v9, v8, v0.t +; CHECK-O2-NEXT: vmor.mm v12, v12, v11 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v27, (a0) +; CHECK-O2-NEXT: vsm.v v12, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vmfle.vv v27, v9, v8, v0.t -; CHECK-O2-NEXT: vmor.mm v27, v27, v26 +; CHECK-O2-NEXT: vmfle.vv v12, v9, v8, v0.t +; CHECK-O2-NEXT: vmor.mm v12, v12, v11 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v27, (a0) +; CHECK-O2-NEXT: vsm.v v12, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vmflt.vv v27, v8, v9, v0.t -; CHECK-O2-NEXT: vmor.mm v27, v27, v26 +; CHECK-O2-NEXT: vmflt.vv v12, v8, v9, v0.t +; CHECK-O2-NEXT: vmor.mm v12, v12, v11 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v27, (a0) +; CHECK-O2-NEXT: vsm.v v12, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vmfle.vv v27, v8, v9, v0.t -; CHECK-O2-NEXT: vmor.mm v26, v27, v26 +; CHECK-O2-NEXT: vmfle.vv v12, v8, v9, v0.t +; CHECK-O2-NEXT: vmor.mm v11, v12, v11 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vmfne.vv v26, v8, v9 +; CHECK-O2-NEXT: vmfne.vv v8, v8, v9 ; CHECK-O2-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) -; CHECK-O2-NEXT: vsm.v v25, (a0) +; CHECK-O2-NEXT: vsm.v v8, (a0) +; CHECK-O2-NEXT: vsm.v v10, (a0) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -238,93 +240,95 @@ define void @test_vp_fcmp_2( %a, %b, i3 ; CHECK-O0-NEXT: addi sp, sp, -16 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: sub sp, sp, a1 +; CHECK-O0-NEXT: vmv1r.v v10, v9 +; CHECK-O0-NEXT: vmv1r.v v9, v8 ; CHECK-O0-NEXT: slli a1, a0, 32 ; CHECK-O0-NEXT: srli a1, a1, 32 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vmset.m v25 -; CHECK-O0-NEXT: vmclr.m v26 -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vmset.m v8 +; CHECK-O0-NEXT: vmclr.m v11 +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmfeq.vv v26, v8, v9 +; CHECK-O0-NEXT: vmfeq.vv v11, v9, v10 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmflt.vv v26, v9, v8 +; CHECK-O0-NEXT: vmflt.vv v11, v10, v9 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmfle.vv v26, v9, v8 +; CHECK-O0-NEXT: vmfle.vv v11, v10, v9 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmflt.vv v26, v8, v9 +; CHECK-O0-NEXT: vmflt.vv v11, v9, v10 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmfle.vv v26, v8, v9 +; CHECK-O0-NEXT: vmfle.vv v11, v9, v10 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmfeq.vv v27, v9, v9 -; CHECK-O0-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-O0-NEXT: vmand.mm v0, v26, v27 +; CHECK-O0-NEXT: vmfeq.vv v12, v10, v10 +; CHECK-O0-NEXT: vmfeq.vv v11, v9, v9 +; CHECK-O0-NEXT: vmand.mm v0, v11, v12 ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vs1r.v v0, (a2) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v26 -; CHECK-O0-NEXT: vmfne.vv v26, v8, v9, v0.t +; CHECK-O0-NEXT: # implicit-def: $v11 +; CHECK-O0-NEXT: vmfne.vv v11, v9, v10, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmand.mm v26, v26, v0 +; CHECK-O0-NEXT: vmand.mm v11, v11, v0 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsm.v v0, (a0) -; CHECK-O0-NEXT: vmnand.mm v27, v0, v0 -; CHECK-O0-NEXT: vsm.v v27, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vmnand.mm v12, v0, v0 +; CHECK-O0-NEXT: vsm.v v12, (a0) +; CHECK-O0-NEXT: # implicit-def: $v11 ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmfeq.vv v26, v8, v9, v0.t +; CHECK-O0-NEXT: vmfeq.vv v11, v9, v10, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v11, v11, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v11, (a0) +; CHECK-O0-NEXT: # implicit-def: $v11 ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmflt.vv v26, v9, v8, v0.t +; CHECK-O0-NEXT: vmflt.vv v11, v10, v9, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v11, v11, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v11, (a0) +; CHECK-O0-NEXT: # implicit-def: $v11 ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmfle.vv v26, v9, v8, v0.t +; CHECK-O0-NEXT: vmfle.vv v11, v10, v9, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v11, v11, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v11, (a0) +; CHECK-O0-NEXT: # implicit-def: $v11 ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmflt.vv v26, v8, v9, v0.t +; CHECK-O0-NEXT: vmflt.vv v11, v9, v10, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v11, v11, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v11, (a0) +; CHECK-O0-NEXT: # implicit-def: $v11 ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmfle.vv v26, v8, v9, v0.t -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmfle.vv v11, v9, v10, v0.t +; CHECK-O0-NEXT: vmor.mm v11, v11, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v11, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmfne.vv v26, v8, v9 +; CHECK-O0-NEXT: vmfne.vv v9, v9, v10 ; CHECK-O0-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v9, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: add sp, sp, a0 ; CHECK-O0-NEXT: addi sp, sp, 16 @@ -337,70 +341,70 @@ define void @test_vp_fcmp_2( %a, %b, i3 ; CHECK-O2-NEXT: lui a0, %hi(scratch) ; CHECK-O2-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vmset.m v25 -; CHECK-O2-NEXT: vmclr.m v26 -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vmset.m v10 +; CHECK-O2-NEXT: vmclr.m v11 +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O2-NEXT: vmfeq.vv v26, v8, v9 +; CHECK-O2-NEXT: vmfeq.vv v11, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O2-NEXT: vmflt.vv v26, v9, v8 +; CHECK-O2-NEXT: vmflt.vv v11, v9, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O2-NEXT: vmfle.vv v26, v9, v8 +; CHECK-O2-NEXT: vmfle.vv v11, v9, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O2-NEXT: vmflt.vv v26, v8, v9 +; CHECK-O2-NEXT: vmflt.vv v11, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O2-NEXT: vmfle.vv v26, v8, v9 +; CHECK-O2-NEXT: vmfle.vv v11, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O2-NEXT: vmfeq.vv v26, v9, v9 -; CHECK-O2-NEXT: vmfeq.vv v27, v8, v8 -; CHECK-O2-NEXT: vmand.mm v0, v27, v26 -; CHECK-O2-NEXT: vmfne.vv v26, v8, v9, v0.t -; CHECK-O2-NEXT: vmand.mm v26, v26, v0 +; CHECK-O2-NEXT: vmfeq.vv v11, v9, v9 +; CHECK-O2-NEXT: vmfeq.vv v12, v8, v8 +; CHECK-O2-NEXT: vmand.mm v0, v12, v11 +; CHECK-O2-NEXT: vmfne.vv v11, v8, v9, v0.t +; CHECK-O2-NEXT: vmand.mm v11, v11, v0 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsm.v v0, (a0) -; CHECK-O2-NEXT: vmnand.mm v26, v0, v0 -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vmnand.mm v11, v0, v0 +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O2-NEXT: vmfeq.vv v27, v8, v9, v0.t -; CHECK-O2-NEXT: vmor.mm v27, v27, v26 +; CHECK-O2-NEXT: vmfeq.vv v12, v8, v9, v0.t +; CHECK-O2-NEXT: vmor.mm v12, v12, v11 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v27, (a0) +; CHECK-O2-NEXT: vsm.v v12, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O2-NEXT: vmflt.vv v27, v9, v8, v0.t -; CHECK-O2-NEXT: vmor.mm v27, v27, v26 +; CHECK-O2-NEXT: vmflt.vv v12, v9, v8, v0.t +; CHECK-O2-NEXT: vmor.mm v12, v12, v11 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v27, (a0) +; CHECK-O2-NEXT: vsm.v v12, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O2-NEXT: vmfle.vv v27, v9, v8, v0.t -; CHECK-O2-NEXT: vmor.mm v27, v27, v26 +; CHECK-O2-NEXT: vmfle.vv v12, v9, v8, v0.t +; CHECK-O2-NEXT: vmor.mm v12, v12, v11 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v27, (a0) +; CHECK-O2-NEXT: vsm.v v12, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O2-NEXT: vmflt.vv v27, v8, v9, v0.t -; CHECK-O2-NEXT: vmor.mm v27, v27, v26 +; CHECK-O2-NEXT: vmflt.vv v12, v8, v9, v0.t +; CHECK-O2-NEXT: vmor.mm v12, v12, v11 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v27, (a0) +; CHECK-O2-NEXT: vsm.v v12, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O2-NEXT: vmfle.vv v27, v8, v9, v0.t -; CHECK-O2-NEXT: vmor.mm v26, v27, v26 +; CHECK-O2-NEXT: vmfle.vv v12, v8, v9, v0.t +; CHECK-O2-NEXT: vmor.mm v11, v12, v11 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v11, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O2-NEXT: vmfne.vv v26, v8, v9 +; CHECK-O2-NEXT: vmfne.vv v8, v8, v9 ; CHECK-O2-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) -; CHECK-O2-NEXT: vsm.v v25, (a0) +; CHECK-O2-NEXT: vsm.v v8, (a0) +; CHECK-O2-NEXT: vsm.v v10, (a0) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -464,93 +468,95 @@ define void @test_vp_fcmp_3( %a, %b, ; CHECK-O0-NEXT: addi sp, sp, -16 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: sub sp, sp, a1 +; CHECK-O0-NEXT: vmv2r.v v12, v10 +; CHECK-O0-NEXT: vmv2r.v v10, v8 ; CHECK-O0-NEXT: slli a1, a0, 32 ; CHECK-O0-NEXT: srli a1, a1, 32 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vmset.m v25 -; CHECK-O0-NEXT: vmclr.m v26 -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vmset.m v8 +; CHECK-O0-NEXT: vmclr.m v9 +; CHECK-O0-NEXT: vsm.v v9, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfeq.vv v26, v8, v10 +; CHECK-O0-NEXT: vmfeq.vv v9, v10, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v9, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmflt.vv v26, v10, v8 +; CHECK-O0-NEXT: vmflt.vv v9, v12, v10 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v9, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfle.vv v26, v10, v8 +; CHECK-O0-NEXT: vmfle.vv v9, v12, v10 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v9, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmflt.vv v26, v8, v10 +; CHECK-O0-NEXT: vmflt.vv v9, v10, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v9, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfle.vv v26, v8, v10 +; CHECK-O0-NEXT: vmfle.vv v9, v10, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v9, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfeq.vv v27, v10, v10 -; CHECK-O0-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-O0-NEXT: vmand.mm v0, v26, v27 +; CHECK-O0-NEXT: vmfeq.vv v14, v12, v12 +; CHECK-O0-NEXT: vmfeq.vv v9, v10, v10 +; CHECK-O0-NEXT: vmand.mm v0, v9, v14 ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vs1r.v v0, (a2) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v26 -; CHECK-O0-NEXT: vmfne.vv v26, v8, v10, v0.t +; CHECK-O0-NEXT: # implicit-def: $v9 +; CHECK-O0-NEXT: vmfne.vv v9, v10, v12, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmand.mm v26, v26, v0 +; CHECK-O0-NEXT: vmand.mm v9, v9, v0 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v9, (a0) ; CHECK-O0-NEXT: vsm.v v0, (a0) -; CHECK-O0-NEXT: vmnand.mm v27, v0, v0 -; CHECK-O0-NEXT: vsm.v v27, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vmnand.mm v14, v0, v0 +; CHECK-O0-NEXT: vsm.v v14, (a0) +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfeq.vv v26, v8, v10, v0.t +; CHECK-O0-NEXT: vmfeq.vv v9, v10, v12, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v9, v9, v14 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v9, (a0) +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmflt.vv v26, v10, v8, v0.t +; CHECK-O0-NEXT: vmflt.vv v9, v12, v10, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v9, v9, v14 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v9, (a0) +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfle.vv v26, v10, v8, v0.t +; CHECK-O0-NEXT: vmfle.vv v9, v12, v10, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v9, v9, v14 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v9, (a0) +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmflt.vv v26, v8, v10, v0.t +; CHECK-O0-NEXT: vmflt.vv v9, v10, v12, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v9, v9, v14 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v9, (a0) +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfle.vv v26, v8, v10, v0.t -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmfle.vv v9, v10, v12, v0.t +; CHECK-O0-NEXT: vmor.mm v9, v9, v14 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) +; CHECK-O0-NEXT: vsm.v v9, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfne.vv v26, v8, v10 +; CHECK-O0-NEXT: vmfne.vv v9, v10, v12 ; CHECK-O0-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v9, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: add sp, sp, a0 ; CHECK-O0-NEXT: addi sp, sp, 16 @@ -563,70 +569,70 @@ define void @test_vp_fcmp_3( %a, %b, ; CHECK-O2-NEXT: lui a0, %hi(scratch) ; CHECK-O2-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vmset.m v25 -; CHECK-O2-NEXT: vmclr.m v26 -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vmset.m v12 +; CHECK-O2-NEXT: vmclr.m v13 +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmfeq.vv v26, v8, v10 +; CHECK-O2-NEXT: vmfeq.vv v13, v8, v10 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmflt.vv v26, v10, v8 +; CHECK-O2-NEXT: vmflt.vv v13, v10, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmfle.vv v26, v10, v8 +; CHECK-O2-NEXT: vmfle.vv v13, v10, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmflt.vv v26, v8, v10 +; CHECK-O2-NEXT: vmflt.vv v13, v8, v10 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmfle.vv v26, v8, v10 +; CHECK-O2-NEXT: vmfle.vv v13, v8, v10 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmfeq.vv v26, v10, v10 -; CHECK-O2-NEXT: vmfeq.vv v27, v8, v8 -; CHECK-O2-NEXT: vmand.mm v0, v27, v26 -; CHECK-O2-NEXT: vmfne.vv v26, v8, v10, v0.t -; CHECK-O2-NEXT: vmand.mm v26, v26, v0 +; CHECK-O2-NEXT: vmfeq.vv v13, v10, v10 +; CHECK-O2-NEXT: vmfeq.vv v14, v8, v8 +; CHECK-O2-NEXT: vmand.mm v0, v14, v13 +; CHECK-O2-NEXT: vmfne.vv v13, v8, v10, v0.t +; CHECK-O2-NEXT: vmand.mm v13, v13, v0 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsm.v v0, (a0) -; CHECK-O2-NEXT: vmnand.mm v26, v0, v0 -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vmnand.mm v13, v0, v0 +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmfeq.vv v27, v8, v10, v0.t -; CHECK-O2-NEXT: vmor.mm v27, v27, v26 +; CHECK-O2-NEXT: vmfeq.vv v14, v8, v10, v0.t +; CHECK-O2-NEXT: vmor.mm v14, v14, v13 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v27, (a0) +; CHECK-O2-NEXT: vsm.v v14, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmflt.vv v27, v10, v8, v0.t -; CHECK-O2-NEXT: vmor.mm v27, v27, v26 +; CHECK-O2-NEXT: vmflt.vv v14, v10, v8, v0.t +; CHECK-O2-NEXT: vmor.mm v14, v14, v13 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v27, (a0) +; CHECK-O2-NEXT: vsm.v v14, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmfle.vv v27, v10, v8, v0.t -; CHECK-O2-NEXT: vmor.mm v27, v27, v26 +; CHECK-O2-NEXT: vmfle.vv v14, v10, v8, v0.t +; CHECK-O2-NEXT: vmor.mm v14, v14, v13 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v27, (a0) +; CHECK-O2-NEXT: vsm.v v14, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmflt.vv v27, v8, v10, v0.t -; CHECK-O2-NEXT: vmor.mm v27, v27, v26 +; CHECK-O2-NEXT: vmflt.vv v14, v8, v10, v0.t +; CHECK-O2-NEXT: vmor.mm v14, v14, v13 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v27, (a0) +; CHECK-O2-NEXT: vsm.v v14, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmfle.vv v27, v8, v10, v0.t -; CHECK-O2-NEXT: vmor.mm v26, v27, v26 +; CHECK-O2-NEXT: vmfle.vv v14, v8, v10, v0.t +; CHECK-O2-NEXT: vmor.mm v13, v14, v13 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmfne.vv v26, v8, v10 +; CHECK-O2-NEXT: vmfne.vv v13, v8, v10 ; CHECK-O2-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) -; CHECK-O2-NEXT: vsm.v v25, (a0) +; CHECK-O2-NEXT: vsm.v v13, (a0) +; CHECK-O2-NEXT: vsm.v v12, (a0) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * diff --git a/llvm/test/CodeGen/RISCV/epi-vp-fcmp.ll b/llvm/test/CodeGen/RISCV/epi-vp-fcmp.ll index 360731481209e11ce2c2f957e887b0774eb3604c..7abe91cd1c63f287436e29881691bd5f9716d29f 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-fcmp.ll @@ -17,129 +17,131 @@ define void @test_vp_fcmp( %a, %b, %a, %b, * @@ -284,129 +286,131 @@ define void @test_vp_fcmp_2( %a, %b, %a, %b, * @@ -551,129 +555,131 @@ define void @test_vp_fcmp_3( %a, %b, ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 16 ; CHECK-O0-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vmv2r.v v12, v10 +; CHECK-O0-NEXT: vmv2r.v v10, v8 ; CHECK-O0-NEXT: slli a1, a0, 32 ; CHECK-O0-NEXT: srli a1, a1, 32 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vmclr.m v25 -; CHECK-O0-NEXT: vsm.v v25, (a0) -; CHECK-O0-NEXT: # implicit-def: $v25 +; CHECK-O0-NEXT: vmclr.m v8 +; CHECK-O0-NEXT: vsm.v v8, (a0) +; CHECK-O0-NEXT: # implicit-def: $v8 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfeq.vv v25, v8, v10, v0.t +; CHECK-O0-NEXT: vmfeq.vv v8, v10, v12, v0.t ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) -; CHECK-O0-NEXT: # implicit-def: $v25 +; CHECK-O0-NEXT: vsm.v v8, (a0) +; CHECK-O0-NEXT: # implicit-def: $v8 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmflt.vv v25, v10, v8, v0.t +; CHECK-O0-NEXT: vmflt.vv v8, v12, v10, v0.t ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) -; CHECK-O0-NEXT: # implicit-def: $v25 +; CHECK-O0-NEXT: vsm.v v8, (a0) +; CHECK-O0-NEXT: # implicit-def: $v8 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfle.vv v25, v10, v8, v0.t +; CHECK-O0-NEXT: vmfle.vv v8, v12, v10, v0.t ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) -; CHECK-O0-NEXT: # implicit-def: $v25 +; CHECK-O0-NEXT: vsm.v v8, (a0) +; CHECK-O0-NEXT: # implicit-def: $v8 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmflt.vv v25, v8, v10, v0.t +; CHECK-O0-NEXT: vmflt.vv v8, v10, v12, v0.t ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) -; CHECK-O0-NEXT: # implicit-def: $v25 +; CHECK-O0-NEXT: vsm.v v8, (a0) +; CHECK-O0-NEXT: # implicit-def: $v8 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfle.vv v25, v8, v10, v0.t +; CHECK-O0-NEXT: vmfle.vv v8, v10, v12, v0.t ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v8, (a0) +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfeq.vv v26, v10, v10, v0.t +; CHECK-O0-NEXT: vmfeq.vv v9, v12, v12, v0.t ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vmfeq.vv v25, v8, v8, v0.t -; CHECK-O0-NEXT: vmand.mm v0, v25, v26 +; CHECK-O0-NEXT: # implicit-def: $v8 +; CHECK-O0-NEXT: vmfeq.vv v8, v10, v10, v0.t +; CHECK-O0-NEXT: vmand.mm v0, v8, v9 ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vs1r.v v0, (a2) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vmfne.vv v25, v8, v10, v0.t +; CHECK-O0-NEXT: # implicit-def: $v8 +; CHECK-O0-NEXT: vmfne.vv v8, v10, v12, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmand.mm v25, v25, v0 +; CHECK-O0-NEXT: vmand.mm v8, v8, v0 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: vsm.v v0, (a0) -; CHECK-O0-NEXT: vmnand.mm v27, v0, v0 -; CHECK-O0-NEXT: vmset.m v25 -; CHECK-O0-NEXT: vsm.v v27, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vmnand.mm v14, v0, v0 +; CHECK-O0-NEXT: vmset.m v8 +; CHECK-O0-NEXT: vsm.v v14, (a0) +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfeq.vv v26, v8, v10, v0.t +; CHECK-O0-NEXT: vmfeq.vv v9, v10, v12, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v9, v9, v14 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v9, (a0) +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmflt.vv v26, v10, v8, v0.t +; CHECK-O0-NEXT: vmflt.vv v9, v12, v10, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v9, v9, v14 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v9, (a0) +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfle.vv v26, v10, v8, v0.t +; CHECK-O0-NEXT: vmfle.vv v9, v12, v10, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v9, v9, v14 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v9, (a0) +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmflt.vv v26, v8, v10, v0.t +; CHECK-O0-NEXT: vmflt.vv v9, v10, v12, v0.t ; CHECK-O0-NEXT: addi a2, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v9, v9, v14 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v9, (a0) +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfle.vv v26, v8, v10, v0.t +; CHECK-O0-NEXT: vmfle.vv v9, v10, v12, v0.t ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmor.mm v26, v26, v27 +; CHECK-O0-NEXT: vmor.mm v9, v9, v14 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: vsm.v v9, (a0) +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmfne.vv v26, v8, v10, v0.t +; CHECK-O0-NEXT: vmfne.vv v9, v10, v12, v0.t ; CHECK-O0-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v26, (a0) -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v9, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add sp, sp, a0 @@ -682,77 +688,77 @@ define void @test_vp_fcmp_3( %a, %b, ; ; CHECK-O2-LABEL: test_vp_fcmp_3: ; CHECK-O2: # %bb.0: -; CHECK-O2-NEXT: vmv1r.v v25, v0 +; CHECK-O2-NEXT: vmv1r.v v12, v0 ; CHECK-O2-NEXT: slli a0, a0, 32 ; CHECK-O2-NEXT: srli a1, a0, 32 ; CHECK-O2-NEXT: lui a0, %hi(scratch) ; CHECK-O2-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vmclr.m v26 -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vmclr.m v13 +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmfeq.vv v26, v8, v10, v0.t +; CHECK-O2-NEXT: vmfeq.vv v13, v8, v10, v0.t ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmflt.vv v26, v10, v8, v0.t +; CHECK-O2-NEXT: vmflt.vv v13, v10, v8, v0.t ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmfle.vv v26, v10, v8, v0.t +; CHECK-O2-NEXT: vmfle.vv v13, v10, v8, v0.t ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmflt.vv v26, v8, v10, v0.t +; CHECK-O2-NEXT: vmflt.vv v13, v8, v10, v0.t ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmfle.vv v26, v8, v10, v0.t +; CHECK-O2-NEXT: vmfle.vv v13, v8, v10, v0.t ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmfeq.vv v26, v10, v10, v0.t -; CHECK-O2-NEXT: vmfeq.vv v27, v8, v8, v0.t -; CHECK-O2-NEXT: vmand.mm v0, v27, v26 -; CHECK-O2-NEXT: vmfne.vv v26, v8, v10, v0.t -; CHECK-O2-NEXT: vmand.mm v26, v26, v0 +; CHECK-O2-NEXT: vmfeq.vv v13, v10, v10, v0.t +; CHECK-O2-NEXT: vmfeq.vv v14, v8, v8, v0.t +; CHECK-O2-NEXT: vmand.mm v0, v14, v13 +; CHECK-O2-NEXT: vmfne.vv v13, v8, v10, v0.t +; CHECK-O2-NEXT: vmand.mm v13, v13, v0 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsm.v v0, (a0) -; CHECK-O2-NEXT: vmnand.mm v26, v0, v0 -; CHECK-O2-NEXT: vmset.m v27 -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vmnand.mm v13, v0, v0 +; CHECK-O2-NEXT: vmset.m v14 +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmfeq.vv v28, v8, v10, v0.t -; CHECK-O2-NEXT: vmor.mm v28, v28, v26 +; CHECK-O2-NEXT: vmfeq.vv v15, v8, v10, v0.t +; CHECK-O2-NEXT: vmor.mm v15, v15, v13 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v28, (a0) +; CHECK-O2-NEXT: vsm.v v15, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmflt.vv v28, v10, v8, v0.t -; CHECK-O2-NEXT: vmor.mm v28, v28, v26 +; CHECK-O2-NEXT: vmflt.vv v15, v10, v8, v0.t +; CHECK-O2-NEXT: vmor.mm v15, v15, v13 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v28, (a0) +; CHECK-O2-NEXT: vsm.v v15, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmfle.vv v28, v10, v8, v0.t -; CHECK-O2-NEXT: vmor.mm v28, v28, v26 +; CHECK-O2-NEXT: vmfle.vv v15, v10, v8, v0.t +; CHECK-O2-NEXT: vmor.mm v15, v15, v13 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v28, (a0) +; CHECK-O2-NEXT: vsm.v v15, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmflt.vv v28, v8, v10, v0.t -; CHECK-O2-NEXT: vmor.mm v28, v28, v26 +; CHECK-O2-NEXT: vmflt.vv v15, v8, v10, v0.t +; CHECK-O2-NEXT: vmor.mm v15, v15, v13 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v28, (a0) +; CHECK-O2-NEXT: vsm.v v15, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmfle.vv v28, v8, v10, v0.t -; CHECK-O2-NEXT: vmor.mm v26, v28, v26 +; CHECK-O2-NEXT: vmfle.vv v15, v8, v10, v0.t +; CHECK-O2-NEXT: vmor.mm v13, v15, v13 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v26, (a0) +; CHECK-O2-NEXT: vsm.v v13, (a0) ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O2-NEXT: vmv1r.v v0, v25 -; CHECK-O2-NEXT: vmfne.vv v25, v8, v10, v0.t +; CHECK-O2-NEXT: vmv1r.v v0, v12 +; CHECK-O2-NEXT: vmfne.vv v12, v8, v10, v0.t ; CHECK-O2-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a0) -; CHECK-O2-NEXT: vsm.v v27, (a0) +; CHECK-O2-NEXT: vsm.v v12, (a0) +; CHECK-O2-NEXT: vsm.v v14, (a0) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * diff --git a/llvm/test/CodeGen/RISCV/epi-vp-fp.ll b/llvm/test/CodeGen/RISCV/epi-vp-fp.ll index fe56cfc8b93523a7bb8b4bdfae32107cafb0bc47..2a6771b47aed218dd9046d354b470bd2e248ed7c 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-fp.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-fp.ll @@ -36,7 +36,8 @@ define void @test_vp_fp(* %a0, * %a1, ; CHECK-O0-NEXT: addi a4, a4, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a4) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a4, vlenb -; CHECK-O0-NEXT: slli a4, a4, 1 +; CHECK-O0-NEXT: slli a5, a4, 3 +; CHECK-O0-NEXT: sub a4, a5, a4 ; CHECK-O0-NEXT: add a4, sp, a4 ; CHECK-O0-NEXT: addi a4, a4, 40 ; CHECK-O0-NEXT: vs1r.v v8, (a4) # Unknown-size Folded Spill @@ -49,8 +50,8 @@ define void @test_vp_fp(* %a0, * %a1, ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; CHECK-O0-NEXT: addi a1, sp, 40 ; CHECK-O0-NEXT: vs1r.v v9, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vle64.v v25, (a2), v0.t +; CHECK-O0-NEXT: # implicit-def: $v10 +; CHECK-O0-NEXT: vle64.v v10, (a2), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 @@ -59,184 +60,184 @@ define void @test_vp_fp(* %a0, * %a1, ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vle64.v v25, (a3), v0.t +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: # implicit-def: $v10 +; CHECK-O0-NEXT: vle64.v v10, (a3), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a1, vlenb -; CHECK-O0-NEXT: slli a2, a1, 1 -; CHECK-O0-NEXT: add a1, a2, a1 +; CHECK-O0-NEXT: slli a1, a1, 1 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vfadd.vv v25, v8, v9, v0.t +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: # implicit-def: $v10 +; CHECK-O0-NEXT: vfadd.vv v10, v8, v9, v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a1, vlenb -; CHECK-O0-NEXT: slli a1, a1, 2 +; CHECK-O0-NEXT: slli a2, a1, 1 +; CHECK-O0-NEXT: add a1, a2, a1 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vfsub.vv v25, v8, v9, v0.t +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: # implicit-def: $v10 +; CHECK-O0-NEXT: vfsub.vv v10, v8, v9, v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a1, vlenb -; CHECK-O0-NEXT: slli a2, a1, 2 -; CHECK-O0-NEXT: add a1, a2, a1 +; CHECK-O0-NEXT: slli a1, a1, 2 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vfmul.vv v25, v8, v9, v0.t +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: # implicit-def: $v10 +; CHECK-O0-NEXT: vfmul.vv v10, v8, v9, v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a1, vlenb -; CHECK-O0-NEXT: addi a2, zero, 6 -; CHECK-O0-NEXT: mul a1, a1, a2 +; CHECK-O0-NEXT: slli a2, a1, 2 +; CHECK-O0-NEXT: add a1, a2, a1 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vfdiv.vv v25, v8, v9, v0.t +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: # implicit-def: $v10 +; CHECK-O0-NEXT: vfdiv.vv v10, v8, v9, v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a1, vlenb -; CHECK-O0-NEXT: slli a2, a1, 3 -; CHECK-O0-NEXT: sub a1, a2, a1 +; CHECK-O0-NEXT: addi a2, zero, 6 +; CHECK-O0-NEXT: mul a1, a1, a2 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill ; CHECK-O0-NEXT: call __epi_vp_frem_nxv1f64@plt ; CHECK-O0-NEXT: ld a4, 24(sp) # 8-byte Folded Reload ; CHECK-O0-NEXT: addi a0, sp, 40 -; CHECK-O0-NEXT: vl1r.v v27, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl1r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl1r.v v26, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl1r.v v16, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a1, a0, 1 ; CHECK-O0-NEXT: add a0, a1, a0 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl1r.v v15, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 2 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl1r.v v31, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl1r.v v14, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a1, a0, 2 ; CHECK-O0-NEXT: add a0, a1, a0 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl1r.v v30, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl1r.v v13, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: addi a1, zero, 6 ; CHECK-O0-NEXT: mul a0, a0, a1 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl1r.v v29, (a0) # Unknown-size Folded Reload -; CHECK-O0-NEXT: csrr a0, vlenb -; CHECK-O0-NEXT: slli a1, a0, 3 -; CHECK-O0-NEXT: sub a0, a1, a0 -; CHECK-O0-NEXT: add a0, sp, a0 -; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl1r.v v28, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl1r.v v12, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 3 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: ld a0, 32(sp) # 8-byte Folded Reload +; CHECK-O0-NEXT: vmv1r.v v11, v8 +; CHECK-O0-NEXT: csrr a1, vlenb +; CHECK-O0-NEXT: slli a2, a1, 3 +; CHECK-O0-NEXT: sub a1, a2, a1 +; CHECK-O0-NEXT: add a1, sp, a1 +; CHECK-O0-NEXT: addi a1, a1, 40 +; CHECK-O0-NEXT: vl1r.v v8, (a1) # Unknown-size Folded Reload ; CHECK-O0-NEXT: vsetvli zero, a4, e64, m1, tu, mu -; CHECK-O0-NEXT: vfmadd.vv v27, v25, v26, v0.t +; CHECK-O0-NEXT: vfmadd.vv v10, v8, v9, v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-O0-NEXT: vfneg.v v26, v25, v0.t +; CHECK-O0-NEXT: vfneg.v v9, v8, v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vfcvt.f.x.v v25, v9, v0.t +; CHECK-O0-NEXT: # implicit-def: $v8 +; CHECK-O0-NEXT: vfcvt.f.x.v v8, v16, v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v31, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v15, (a0), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v30, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v14, (a0), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v29, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v13, (a0), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v28, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v12, (a0), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v8, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v11, (a0), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v27, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v10, (a0), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v26, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v9, (a0), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v25, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v8, (a0), v0.t ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a1, a0, 3 ; CHECK-O0-NEXT: add a0, a1, a0 @@ -272,46 +273,46 @@ define void @test_vp_fp(* %a0, * %a1, ; CHECK-O2-NEXT: addi a0, a0, 24 ; CHECK-O2-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill ; CHECK-O2-NEXT: addi s1, a4, %lo(scratch) -; CHECK-O2-NEXT: vle64.v v25, (a2), v0.t +; CHECK-O2-NEXT: vle64.v v10, (a2), v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 1 ; CHECK-O2-NEXT: add a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill -; CHECK-O2-NEXT: vle64.v v25, (a3), v0.t +; CHECK-O2-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vle64.v v10, (a3), v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a0, a0, 3 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill -; CHECK-O2-NEXT: vfadd.vv v25, v8, v9, v0.t +; CHECK-O2-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vfadd.vv v10, v8, v9, v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 3 ; CHECK-O2-NEXT: sub a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill -; CHECK-O2-NEXT: vfsub.vv v25, v8, v9, v0.t +; CHECK-O2-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vfsub.vv v10, v8, v9, v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: addi a1, zero, 6 ; CHECK-O2-NEXT: mul a0, a0, a1 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill -; CHECK-O2-NEXT: vfmul.vv v25, v8, v9, v0.t +; CHECK-O2-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vfmul.vv v10, v8, v9, v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 2 ; CHECK-O2-NEXT: add a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill -; CHECK-O2-NEXT: vfdiv.vv v25, v8, v9, v0.t +; CHECK-O2-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vfdiv.vv v10, v8, v9, v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a0, a0, 2 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-O2-NEXT: mv a0, s0 ; CHECK-O2-NEXT: call __epi_vp_frem_nxv1f64@plt ; CHECK-O2-NEXT: vsetvli zero, s0, e64, m1, tu, mu @@ -320,58 +321,58 @@ define void @test_vp_fp(* %a0, * %a1, ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl1r.v v27, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vl1r.v v11, (a0) # Unknown-size Folded Reload ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 1 ; CHECK-O2-NEXT: add a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a0, a0, 1 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl1r.v v26, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vfmadd.vv v27, v26, v25, v0.t +; CHECK-O2-NEXT: vl1r.v v10, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vfmadd.vv v11, v10, v9, v0.t ; CHECK-O2-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-O2-NEXT: vfneg.v v25, v26, v0.t +; CHECK-O2-NEXT: vfneg.v v9, v10, v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a0, a0, 3 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl1r.v v26, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vfcvt.f.x.v v26, v26, v0.t +; CHECK-O2-NEXT: vl1r.v v10, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vfcvt.f.x.v v10, v10, v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 3 ; CHECK-O2-NEXT: sub a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl1r.v v28, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vse64.v v28, (s1), v0.t +; CHECK-O2-NEXT: vl1r.v v12, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vse64.v v12, (s1), v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: addi a1, zero, 6 ; CHECK-O2-NEXT: mul a0, a0, a1 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl1r.v v28, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vse64.v v28, (s1), v0.t +; CHECK-O2-NEXT: vl1r.v v12, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vse64.v v12, (s1), v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 2 ; CHECK-O2-NEXT: add a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl1r.v v28, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vse64.v v28, (s1), v0.t +; CHECK-O2-NEXT: vl1r.v v12, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vse64.v v12, (s1), v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a0, a0, 2 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl1r.v v28, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vse64.v v28, (s1), v0.t +; CHECK-O2-NEXT: vl1r.v v12, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vse64.v v12, (s1), v0.t ; CHECK-O2-NEXT: vse64.v v8, (s1), v0.t -; CHECK-O2-NEXT: vse64.v v27, (s1), v0.t -; CHECK-O2-NEXT: vse64.v v25, (s1), v0.t -; CHECK-O2-NEXT: vse64.v v26, (s1), v0.t +; CHECK-O2-NEXT: vse64.v v11, (s1), v0.t +; CHECK-O2-NEXT: vse64.v v9, (s1), v0.t +; CHECK-O2-NEXT: vse64.v v10, (s1), v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 3 ; CHECK-O2-NEXT: add a0, a1, a0 @@ -436,100 +437,101 @@ define void @test_vp_fp_2(* %a0, * %a1, ; CHECK-O0-NEXT: vle32.v v9, (a1) ; CHECK-O0-NEXT: addi a1, sp, 40 ; CHECK-O0-NEXT: vs1r.v v9, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vle32.v v25, (a2) +; CHECK-O0-NEXT: vle32.v v10, (a2) ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vle32.v v25, (a3) +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vle32.v v10, (a3) +; CHECK-O0-NEXT: csrr a1, vlenb +; CHECK-O0-NEXT: slli a2, a1, 3 +; CHECK-O0-NEXT: sub a1, a2, a1 +; CHECK-O0-NEXT: add a1, sp, a1 +; CHECK-O0-NEXT: addi a1, a1, 40 +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vfadd.vv v10, v8, v9 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a2, a1, 1 ; CHECK-O0-NEXT: add a1, a2, a1 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vfadd.vv v25, v8, v9 +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vfsub.vv v10, v8, v9 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 2 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vfsub.vv v25, v8, v9 +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vfmul.vv v10, v8, v9 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a2, a1, 2 ; CHECK-O0-NEXT: add a1, a2, a1 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vfmul.vv v25, v8, v9 +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vfdiv.vv v10, v8, v9 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: addi a2, zero, 6 ; CHECK-O0-NEXT: mul a1, a1, a2 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vfdiv.vv v25, v8, v9 -; CHECK-O0-NEXT: csrr a1, vlenb -; CHECK-O0-NEXT: slli a2, a1, 3 -; CHECK-O0-NEXT: sub a1, a2, a1 -; CHECK-O0-NEXT: add a1, sp, a1 -; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill ; CHECK-O0-NEXT: call __epi_vp_frem_nxv2f32@plt ; CHECK-O0-NEXT: ld a4, 24(sp) # 8-byte Folded Reload ; CHECK-O0-NEXT: addi a0, sp, 40 -; CHECK-O0-NEXT: vl1r.v v27, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl1r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl1r.v v16, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl1r.v v26, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a1, a0, 1 ; CHECK-O0-NEXT: add a0, a1, a0 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl1r.v v15, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 2 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl1r.v v31, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl1r.v v14, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a1, a0, 2 ; CHECK-O0-NEXT: add a0, a1, a0 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl1r.v v30, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl1r.v v13, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: addi a1, zero, 6 ; CHECK-O0-NEXT: mul a0, a0, a1 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl1r.v v29, (a0) # Unknown-size Folded Reload -; CHECK-O0-NEXT: csrr a0, vlenb -; CHECK-O0-NEXT: slli a1, a0, 3 -; CHECK-O0-NEXT: sub a0, a1, a0 -; CHECK-O0-NEXT: add a0, sp, a0 -; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl1r.v v28, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl1r.v v12, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: ld a0, 32(sp) # 8-byte Folded Reload +; CHECK-O0-NEXT: vmv1r.v v11, v8 +; CHECK-O0-NEXT: csrr a1, vlenb +; CHECK-O0-NEXT: slli a2, a1, 3 +; CHECK-O0-NEXT: sub a1, a2, a1 +; CHECK-O0-NEXT: add a1, sp, a1 +; CHECK-O0-NEXT: addi a1, a1, 40 +; CHECK-O0-NEXT: vl1r.v v8, (a1) # Unknown-size Folded Reload ; CHECK-O0-NEXT: vsetvli zero, a4, e32, m1, ta, mu -; CHECK-O0-NEXT: vfmadd.vv v27, v26, v9 -; CHECK-O0-NEXT: vfneg.v v26, v26 -; CHECK-O0-NEXT: vfcvt.f.x.v v25, v25 -; CHECK-O0-NEXT: vse32.v v31, (a0) -; CHECK-O0-NEXT: vse32.v v30, (a0) -; CHECK-O0-NEXT: vse32.v v29, (a0) -; CHECK-O0-NEXT: vse32.v v28, (a0) +; CHECK-O0-NEXT: vfmadd.vv v10, v9, v16 +; CHECK-O0-NEXT: vfneg.v v9, v9 +; CHECK-O0-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-O0-NEXT: vse32.v v15, (a0) +; CHECK-O0-NEXT: vse32.v v14, (a0) +; CHECK-O0-NEXT: vse32.v v13, (a0) +; CHECK-O0-NEXT: vse32.v v12, (a0) +; CHECK-O0-NEXT: vse32.v v11, (a0) +; CHECK-O0-NEXT: vse32.v v10, (a0) +; CHECK-O0-NEXT: vse32.v v9, (a0) ; CHECK-O0-NEXT: vse32.v v8, (a0) -; CHECK-O0-NEXT: vse32.v v27, (a0) -; CHECK-O0-NEXT: vse32.v v26, (a0) -; CHECK-O0-NEXT: vse32.v v25, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 3 ; CHECK-O0-NEXT: add sp, sp, a0 @@ -560,46 +562,46 @@ define void @test_vp_fp_2(* %a0, * %a1, ; CHECK-O2-NEXT: addi a0, sp, 24 ; CHECK-O2-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill ; CHECK-O2-NEXT: addi s1, a4, %lo(scratch) -; CHECK-O2-NEXT: vle32.v v25, (a2) +; CHECK-O2-NEXT: vle32.v v10, (a2) ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a0, a0, 1 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill -; CHECK-O2-NEXT: vle32.v v25, (a3) +; CHECK-O2-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vle32.v v10, (a3) ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 3 ; CHECK-O2-NEXT: sub a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill -; CHECK-O2-NEXT: vfadd.vv v25, v8, v9 +; CHECK-O2-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vfadd.vv v10, v8, v9 ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: addi a1, zero, 6 ; CHECK-O2-NEXT: mul a0, a0, a1 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill -; CHECK-O2-NEXT: vfsub.vv v25, v8, v9 +; CHECK-O2-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vfsub.vv v10, v8, v9 ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 2 ; CHECK-O2-NEXT: add a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill -; CHECK-O2-NEXT: vfmul.vv v25, v8, v9 +; CHECK-O2-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vfmul.vv v10, v8, v9 ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a0, a0, 2 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill -; CHECK-O2-NEXT: vfdiv.vv v25, v8, v9 +; CHECK-O2-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vfdiv.vv v10, v8, v9 ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 1 ; CHECK-O2-NEXT: add a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vs1r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-O2-NEXT: mv a0, s0 ; CHECK-O2-NEXT: call __epi_vp_frem_nxv2f32@plt ; CHECK-O2-NEXT: vsetvli zero, s0, e32, m1, ta, mu @@ -607,53 +609,53 @@ define void @test_vp_fp_2(* %a0, * %a1, ; CHECK-O2-NEXT: slli a0, a0, 1 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl1r.v v27, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vl1r.v v11, (a0) # Unknown-size Folded Reload ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload ; CHECK-O2-NEXT: addi a0, sp, 24 -; CHECK-O2-NEXT: vl1r.v v26, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vfmacc.vv v27, v25, v26 -; CHECK-O2-NEXT: vfneg.v v25, v25 +; CHECK-O2-NEXT: vl1r.v v10, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vfmacc.vv v11, v9, v10 +; CHECK-O2-NEXT: vfneg.v v9, v9 ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 3 ; CHECK-O2-NEXT: sub a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl1r.v v26, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vfcvt.f.x.v v26, v26 +; CHECK-O2-NEXT: vl1r.v v10, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vfcvt.f.x.v v10, v10 ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: addi a1, zero, 6 ; CHECK-O2-NEXT: mul a0, a0, a1 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl1r.v v28, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vse32.v v28, (s1) +; CHECK-O2-NEXT: vl1r.v v12, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vse32.v v12, (s1) ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 2 ; CHECK-O2-NEXT: add a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl1r.v v28, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vse32.v v28, (s1) +; CHECK-O2-NEXT: vl1r.v v12, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vse32.v v12, (s1) ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a0, a0, 2 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl1r.v v28, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vse32.v v28, (s1) +; CHECK-O2-NEXT: vl1r.v v12, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vse32.v v12, (s1) ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 1 ; CHECK-O2-NEXT: add a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl1r.v v28, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vse32.v v28, (s1) +; CHECK-O2-NEXT: vl1r.v v12, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vse32.v v12, (s1) ; CHECK-O2-NEXT: vse32.v v8, (s1) -; CHECK-O2-NEXT: vse32.v v27, (s1) -; CHECK-O2-NEXT: vse32.v v25, (s1) -; CHECK-O2-NEXT: vse32.v v26, (s1) +; CHECK-O2-NEXT: vse32.v v11, (s1) +; CHECK-O2-NEXT: vse32.v v9, (s1) +; CHECK-O2-NEXT: vse32.v v10, (s1) ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a0, a0, 3 ; CHECK-O2-NEXT: add sp, sp, a0 @@ -723,7 +725,8 @@ define void @test_vp_fp_3(* %a0, * %a1 ; CHECK-O0-NEXT: addi a4, a4, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a4) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a4, vlenb -; CHECK-O0-NEXT: slli a4, a4, 2 +; CHECK-O0-NEXT: addi a5, zero, 14 +; CHECK-O0-NEXT: mul a4, a4, a5 ; CHECK-O0-NEXT: add a4, sp, a4 ; CHECK-O0-NEXT: addi a4, a4, 40 ; CHECK-O0-NEXT: vs2r.v v8, (a4) # Unknown-size Folded Spill @@ -736,8 +739,8 @@ define void @test_vp_fp_3(* %a0, * %a1 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; CHECK-O0-NEXT: addi a1, sp, 40 ; CHECK-O0-NEXT: vs2r.v v10, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v26m2 -; CHECK-O0-NEXT: vle64.v v26, (a2), v0.t +; CHECK-O0-NEXT: # implicit-def: $v12m2 +; CHECK-O0-NEXT: vle64.v v12, (a2), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 @@ -747,185 +750,185 @@ define void @test_vp_fp_3(* %a0, * %a1 ; CHECK-O0-NEXT: slli a1, a1, 1 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs2r.v v26, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v26m2 -; CHECK-O0-NEXT: vle64.v v26, (a3), v0.t +; CHECK-O0-NEXT: vs2r.v v12, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: # implicit-def: $v12m2 +; CHECK-O0-NEXT: vle64.v v12, (a3), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a1, vlenb -; CHECK-O0-NEXT: addi a2, zero, 6 -; CHECK-O0-NEXT: mul a1, a1, a2 +; CHECK-O0-NEXT: slli a1, a1, 2 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs2r.v v26, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v26m2 -; CHECK-O0-NEXT: vfadd.vv v26, v8, v10, v0.t +; CHECK-O0-NEXT: vs2r.v v12, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: # implicit-def: $v12m2 +; CHECK-O0-NEXT: vfadd.vv v12, v8, v10, v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a1, vlenb -; CHECK-O0-NEXT: slli a1, a1, 3 +; CHECK-O0-NEXT: addi a2, zero, 6 +; CHECK-O0-NEXT: mul a1, a1, a2 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs2r.v v26, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v26m2 -; CHECK-O0-NEXT: vfsub.vv v26, v8, v10, v0.t +; CHECK-O0-NEXT: vs2r.v v12, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: # implicit-def: $v12m2 +; CHECK-O0-NEXT: vfsub.vv v12, v8, v10, v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a1, vlenb -; CHECK-O0-NEXT: addi a2, zero, 10 -; CHECK-O0-NEXT: mul a1, a1, a2 +; CHECK-O0-NEXT: slli a1, a1, 3 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs2r.v v26, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v26m2 -; CHECK-O0-NEXT: vfmul.vv v26, v8, v10, v0.t +; CHECK-O0-NEXT: vs2r.v v12, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: # implicit-def: $v12m2 +; CHECK-O0-NEXT: vfmul.vv v12, v8, v10, v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a1, vlenb -; CHECK-O0-NEXT: addi a2, zero, 12 +; CHECK-O0-NEXT: addi a2, zero, 10 ; CHECK-O0-NEXT: mul a1, a1, a2 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs2r.v v26, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: # implicit-def: $v26m2 -; CHECK-O0-NEXT: vfdiv.vv v26, v8, v10, v0.t +; CHECK-O0-NEXT: vs2r.v v12, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: # implicit-def: $v12m2 +; CHECK-O0-NEXT: vfdiv.vv v12, v8, v10, v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a1, vlenb -; CHECK-O0-NEXT: addi a2, zero, 14 +; CHECK-O0-NEXT: addi a2, zero, 12 ; CHECK-O0-NEXT: mul a1, a1, a2 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 -; CHECK-O0-NEXT: vs2r.v v26, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vs2r.v v12, (a1) # Unknown-size Folded Spill ; CHECK-O0-NEXT: call __epi_vp_frem_nxv2f64@plt ; CHECK-O0-NEXT: ld a4, 24(sp) # 8-byte Folded Reload ; CHECK-O0-NEXT: addi a0, sp, 40 -; CHECK-O0-NEXT: vl2re8.v v30, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl2re8.v v12, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl2re8.v v28, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl2re8.v v10, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 2 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl2re8.v v26, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl2re8.v v24, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: addi a1, zero, 6 ; CHECK-O0-NEXT: mul a0, a0, a1 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl2re8.v v18, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl2re8.v v22, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 3 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl2re8.v v16, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl2re8.v v20, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: addi a1, zero, 10 ; CHECK-O0-NEXT: mul a0, a0, a1 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl2re8.v v14, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl2re8.v v18, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: addi a1, zero, 12 ; CHECK-O0-NEXT: mul a0, a0, a1 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl2re8.v v12, (a0) # Unknown-size Folded Reload -; CHECK-O0-NEXT: csrr a0, vlenb -; CHECK-O0-NEXT: addi a1, zero, 14 -; CHECK-O0-NEXT: mul a0, a0, a1 -; CHECK-O0-NEXT: add a0, sp, a0 -; CHECK-O0-NEXT: addi a0, a0, 40 -; CHECK-O0-NEXT: vl2re8.v v10, (a0) # Unknown-size Folded Reload +; CHECK-O0-NEXT: vl2re8.v v16, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 4 ; CHECK-O0-NEXT: add a0, sp, a0 ; CHECK-O0-NEXT: addi a0, a0, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload ; CHECK-O0-NEXT: ld a0, 32(sp) # 8-byte Folded Reload +; CHECK-O0-NEXT: vmv2r.v v14, v8 +; CHECK-O0-NEXT: csrr a1, vlenb +; CHECK-O0-NEXT: addi a2, zero, 14 +; CHECK-O0-NEXT: mul a1, a1, a2 +; CHECK-O0-NEXT: add a1, sp, a1 +; CHECK-O0-NEXT: addi a1, a1, 40 +; CHECK-O0-NEXT: vl2re8.v v8, (a1) # Unknown-size Folded Reload ; CHECK-O0-NEXT: vsetvli zero, a4, e64, m2, tu, mu -; CHECK-O0-NEXT: vfmadd.vv v30, v26, v28, v0.t +; CHECK-O0-NEXT: vfmadd.vv v12, v8, v10, v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: # implicit-def: $v28m2 +; CHECK-O0-NEXT: # implicit-def: $v10m2 ; CHECK-O0-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; CHECK-O0-NEXT: vfneg.v v28, v26, v0.t +; CHECK-O0-NEXT: vfneg.v v10, v8, v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: # implicit-def: $v26m2 -; CHECK-O0-NEXT: vfcvt.f.x.v v26, v18, v0.t +; CHECK-O0-NEXT: # implicit-def: $v8m2 +; CHECK-O0-NEXT: vfcvt.f.x.v v8, v24, v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v16, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v22, (a0), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v14, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v20, (a0), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v12, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v18, (a0), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v10, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v16, (a0), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v8, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v14, (a0), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v30, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v12, (a0), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v28, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v10, (a0), v0.t ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: slli a1, a1, 4 ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 40 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vse64.v v26, (a0), v0.t +; CHECK-O0-NEXT: vse64.v v8, (a0), v0.t ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a1, a0, 4 ; CHECK-O0-NEXT: add a0, a1, a0 @@ -962,48 +965,48 @@ define void @test_vp_fp_3(* %a0, * %a1 ; CHECK-O2-NEXT: addi a0, a0, 24 ; CHECK-O2-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-O2-NEXT: addi s1, a4, %lo(scratch) -; CHECK-O2-NEXT: vle64.v v26, (a2), v0.t +; CHECK-O2-NEXT: vle64.v v12, (a2), v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 2 ; CHECK-O2-NEXT: add a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs2r.v v26, (a0) # Unknown-size Folded Spill -; CHECK-O2-NEXT: vle64.v v26, (a3), v0.t +; CHECK-O2-NEXT: vs2r.v v12, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vle64.v v12, (a3), v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 4 ; CHECK-O2-NEXT: sub a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs2r.v v26, (a0) # Unknown-size Folded Spill -; CHECK-O2-NEXT: vfadd.vv v26, v8, v10, v0.t +; CHECK-O2-NEXT: vs2r.v v12, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vfadd.vv v12, v8, v10, v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: addi a1, zero, 13 ; CHECK-O2-NEXT: mul a0, a0, a1 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs2r.v v26, (a0) # Unknown-size Folded Spill -; CHECK-O2-NEXT: vfsub.vv v26, v8, v10, v0.t +; CHECK-O2-NEXT: vs2r.v v12, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vfsub.vv v12, v8, v10, v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: addi a1, zero, 11 ; CHECK-O2-NEXT: mul a0, a0, a1 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs2r.v v26, (a0) # Unknown-size Folded Spill -; CHECK-O2-NEXT: vfmul.vv v26, v8, v10, v0.t +; CHECK-O2-NEXT: vs2r.v v12, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vfmul.vv v12, v8, v10, v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 3 ; CHECK-O2-NEXT: add a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs2r.v v26, (a0) # Unknown-size Folded Spill -; CHECK-O2-NEXT: vfdiv.vv v26, v8, v10, v0.t +; CHECK-O2-NEXT: vs2r.v v12, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vfdiv.vv v12, v8, v10, v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 3 ; CHECK-O2-NEXT: sub a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vs2r.v v26, (a0) # Unknown-size Folded Spill +; CHECK-O2-NEXT: vs2r.v v12, (a0) # Unknown-size Folded Spill ; CHECK-O2-NEXT: mv a0, s0 ; CHECK-O2-NEXT: call __epi_vp_frem_nxv2f64@plt ; CHECK-O2-NEXT: vsetvli zero, s0, e64, m2, tu, mu @@ -1012,61 +1015,61 @@ define void @test_vp_fp_3(* %a0, * %a1 ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl2re8.v v30, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vl2re8.v v14, (a0) # Unknown-size Folded Reload ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 2 ; CHECK-O2-NEXT: add a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl2re8.v v26, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vl2re8.v v10, (a0) # Unknown-size Folded Reload ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 1 ; CHECK-O2-NEXT: add a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl2re8.v v28, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vfmadd.vv v30, v28, v26, v0.t +; CHECK-O2-NEXT: vl2re8.v v12, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vfmadd.vv v14, v12, v10, v0.t ; CHECK-O2-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; CHECK-O2-NEXT: vfneg.v v26, v28, v0.t +; CHECK-O2-NEXT: vfneg.v v10, v12, v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 4 ; CHECK-O2-NEXT: sub a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl2re8.v v28, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vfcvt.f.x.v v28, v28, v0.t +; CHECK-O2-NEXT: vl2re8.v v12, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vfcvt.f.x.v v12, v12, v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: addi a1, zero, 13 ; CHECK-O2-NEXT: mul a0, a0, a1 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl2re8.v v10, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vse64.v v10, (s1), v0.t +; CHECK-O2-NEXT: vl2re8.v v16, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vse64.v v16, (s1), v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: addi a1, zero, 11 ; CHECK-O2-NEXT: mul a0, a0, a1 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl2re8.v v10, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vse64.v v10, (s1), v0.t +; CHECK-O2-NEXT: vl2re8.v v16, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vse64.v v16, (s1), v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 3 ; CHECK-O2-NEXT: add a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl2re8.v v10, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vse64.v v10, (s1), v0.t +; CHECK-O2-NEXT: vl2re8.v v16, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vse64.v v16, (s1), v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 3 ; CHECK-O2-NEXT: sub a0, a1, a0 ; CHECK-O2-NEXT: add a0, sp, a0 ; CHECK-O2-NEXT: addi a0, a0, 24 -; CHECK-O2-NEXT: vl2re8.v v10, (a0) # Unknown-size Folded Reload -; CHECK-O2-NEXT: vse64.v v10, (s1), v0.t +; CHECK-O2-NEXT: vl2re8.v v16, (a0) # Unknown-size Folded Reload +; CHECK-O2-NEXT: vse64.v v16, (s1), v0.t ; CHECK-O2-NEXT: vse64.v v8, (s1), v0.t -; CHECK-O2-NEXT: vse64.v v30, (s1), v0.t -; CHECK-O2-NEXT: vse64.v v26, (s1), v0.t -; CHECK-O2-NEXT: vse64.v v28, (s1), v0.t +; CHECK-O2-NEXT: vse64.v v14, (s1), v0.t +; CHECK-O2-NEXT: vse64.v v10, (s1), v0.t +; CHECK-O2-NEXT: vse64.v v12, (s1), v0.t ; CHECK-O2-NEXT: csrr a0, vlenb ; CHECK-O2-NEXT: slli a1, a0, 4 ; CHECK-O2-NEXT: add a0, a1, a0 diff --git a/llvm/test/CodeGen/RISCV/epi-vp-fpext.ll b/llvm/test/CodeGen/RISCV/epi-vp-fpext.ll index 0e8c6ca775d19fc1b7331210c3c67b9aade1b650..77f7ba5a97ccf3dabc36098e7864c7f74f0fd828 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-fpext.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-fpext.ll @@ -6,8 +6,8 @@ define @fpext.f64.f32( %a, i32 zeroext ; CHECK-LABEL: fpext.f64.f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.f.f.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret { %b = call @llvm.vp.fpext.nxv2f64.nxv2f32( %a, @@ -20,8 +20,8 @@ define @fpext.f64.f32.mask( %a, @llvm.vp.fpext.nxv2f64.nxv2f32( diff --git a/llvm/test/CodeGen/RISCV/epi-vp-fptosi-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/epi-vp-fptosi-fixed-vectors.ll index 51972f0597fe994e79e8602b4841f58b089157f9..a083b7c6771bc6e10fbf797ee63b21e41c05c0ac 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-fptosi-fixed-vectors.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-fptosi-fixed-vectors.ll @@ -35,8 +35,8 @@ define <2 x i64> @fptosi.i64.f32(<2 x float> %a, i32 zeroext %gvl) ; CHECK-LABEL: fptosi.i64.f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %b = call <2 x i64> @llvm.vp.fptosi.v2i64.v2f32(<2 x float> %a, @@ -49,8 +49,8 @@ define <2 x i64> @fptosi.i64.f32.mask(<2 x float> %a, <2 x i1> %mask, i32 zeroex ; CHECK-LABEL: fptosi.i64.f32.mask: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %b = call <2 x i64> @llvm.vp.fptosi.v2i64.v2f32( @@ -66,8 +66,8 @@ define <2 x i32> @fptosi.i32.f64(<2 x double> %a, i32 zeroext %gvl) ; CHECK-LABEL: fptosi.i32.f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %b = call <2 x i32> @llvm.vp.fptosi.v2i32.v2f64(<2 x double> %a, @@ -80,8 +80,8 @@ define <2 x i32> @fptosi.i32.f64.mask(<2 x double> %a, <2 x i1> %mask, i32 zeroe ; CHECK-LABEL: fptosi.i32.f64.mask: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %b = call <2 x i32> @llvm.vp.fptosi.v2i32.v2f64( @@ -97,9 +97,9 @@ define <4 x i8> @test_vp_fptosi_v4i8_v4f32(<4 x float> %a, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_fptosi_v4i8_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: ret %m.first = insertelement <4 x i1> undef, i1 1, i32 0 %m.splat = shufflevector <4 x i1> %m.first, <4 x i1> undef, <4 x i32> zeroinitializer @@ -111,9 +111,9 @@ define <4 x i8> @test_vp_fptosi_v4i8_v4f32_mask(<4 x float> %a, <4 x i1> %m, i32 ; CHECK-LABEL: test_vp_fptosi_v4i8_v4f32_mask: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8, v0.t +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0, v0.t +; CHECK-NEXT: vnsrl.wi v8, v9, 0, v0.t ; CHECK-NEXT: ret %x = call <4 x i8> @llvm.vp.fptosi.v4i8.v4f32(<4 x float> %a, <4 x i1> %m, i32 %evl) ret <4 x i8> %x @@ -123,11 +123,11 @@ define <4 x i8> @test_vp_fptosi_v4i8_v4f64(<4 x double> %a, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_fptosi_v4i8_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %m.first = insertelement <4 x i1> undef, i1 1, i32 0 %m.splat = shufflevector <4 x i1> %m.first, <4 x i1> undef, <4 x i32> zeroinitializer @@ -139,11 +139,11 @@ define <4 x i8> @test_vp_fptosi_v4i8_v4f64_mask(<4 x double> %a, <4 x i1> %m, i3 ; CHECK-LABEL: test_vp_fptosi_v4i8_v4f64_mask: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8, v0.t +; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0, v0.t +; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0, v0.t +; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t ; CHECK-NEXT: ret %x = call <4 x i8> @llvm.vp.fptosi.v4i8.v4f64(<4 x double> %a, <4 x i1> %m, i32 %evl) ret <4 x i8> %x @@ -153,9 +153,9 @@ define <4 x i16> @test_vp_fptosi_v4i16_v4f64(<4 x double> %a, i32 zeroext %evl) ; CHECK-LABEL: test_vp_fptosi_v4i16_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %m.first = insertelement <4 x i1> undef, i1 1, i32 0 %m.splat = shufflevector <4 x i1> %m.first, <4 x i1> undef, <4 x i32> zeroinitializer @@ -167,9 +167,9 @@ define <4 x i16> @test_vp_fptosi_v4i16_v4f64_mask(<4 x double> %a, <4 x i1> %m, ; CHECK-LABEL: test_vp_fptosi_v4i16_v4f64_mask: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8, v0.t +; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0, v0.t +; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t ; CHECK-NEXT: ret %x = call <4 x i16> @llvm.vp.fptosi.v4i16.v4f64(<4 x double> %a, <4 x i1> %m, i32 %evl) ret <4 x i16> %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-fptosi.ll b/llvm/test/CodeGen/RISCV/epi-vp-fptosi.ll index ee6bb558b58544f9a5dea80647520dcdf8d987b5..1ad499cb6e2352f5f76ef90c1fe6f4f065e79c08 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-fptosi.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-fptosi.ll @@ -35,8 +35,8 @@ define @fptosi.i64.f32( %a, i32 zeroext % ; CHECK-LABEL: fptosi.i64.f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.rtz.x.f.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret { %b = call @llvm.vp.fptosi.nxv2i64.nxv2f32( %a, @@ -49,8 +49,8 @@ define @fptosi.i64.f32.mask( %a, @llvm.vp.fptosi.nxv2i64.nxv2f32( @@ -66,8 +66,8 @@ define @fptosi.i32.f64( %a, i32 zeroext ; CHECK-LABEL: fptosi.i32.f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret { %b = call @llvm.vp.fptosi.nxv2i32.nxv2f64( %a, @@ -80,8 +80,8 @@ define @fptosi.i32.f64.mask( %a, @llvm.vp.fptosi.nxv2i32.nxv2f64( @@ -97,9 +97,9 @@ define @test_vp_fptosi_nxv4i8_nxv4f32( %a, ; CHECK-LABEL: test_vp_fptosi_nxv4i8_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -111,9 +111,9 @@ define @test_vp_fptosi_nxv4i8_nxv4f32_mask( @llvm.vp.fptosi.nxv4i8.nxv4f32( %a, %m, i32 %evl) ret %x @@ -123,11 +123,11 @@ define @test_vp_fptosi_nxv4i8_nxv4f64( %a ; CHECK-LABEL: test_vp_fptosi_nxv4i8_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -139,11 +139,11 @@ define @test_vp_fptosi_nxv4i8_nxv4f64_mask( @llvm.vp.fptosi.nxv4i8.nxv4f64( %a, %m, i32 %evl) ret %x @@ -153,9 +153,9 @@ define @test_vp_fptosi_nxv4i16_nxv4f64( ; CHECK-LABEL: test_vp_fptosi_nxv4i16_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -167,9 +167,9 @@ define @test_vp_fptosi_nxv4i16_nxv4f64_mask( @llvm.vp.fptosi.nxv4i16.nxv4f64( %a, %m, i32 %evl) ret %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-fptoui-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/epi-vp-fptoui-fixed-vectors.ll index 490bb4f1d4076846c1a3d32c95d3358f76088ede..94110d32f9d6da439707d7d90ce06e57d17ebba9 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-fptoui-fixed-vectors.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-fptoui-fixed-vectors.ll @@ -35,8 +35,8 @@ define <2 x i64> @fptoui.i64.f32(<2 x float> %a, i32 zeroext %gvl) ; CHECK-LABEL: fptoui.i64.f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %b = call <2 x i64> @llvm.vp.fptoui.v2i64.v2f32(<2 x float> %a, @@ -49,8 +49,8 @@ define <2 x i64> @fptoui.i64.f32.mask(<2 x float> %a, <2 x i1> %mask, i32 zeroex ; CHECK-LABEL: fptoui.i64.f32.mask: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %b = call <2 x i64> @llvm.vp.fptoui.v2i64.v2f32( @@ -66,8 +66,8 @@ define <2 x i32> @fptoui.i32.f64(<2 x double> %a, i32 zeroext %gvl) ; CHECK-LABEL: fptoui.i32.f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %b = call <2 x i32> @llvm.vp.fptoui.v2i32.v2f64(<2 x double> %a, @@ -80,8 +80,8 @@ define <2 x i32> @fptoui.i32.f64.mask(<2 x double> %a, <2 x i1> %mask, i32 zeroe ; CHECK-LABEL: fptoui.i32.f64.mask: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %b = call <2 x i32> @llvm.vp.fptoui.v2i32.v2f64( @@ -97,9 +97,9 @@ define <4 x i8> @test_vp_fptoui_v4i8_v4f32(<4 x float> %a, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_fptoui_v4i8_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: ret %m.first = insertelement <4 x i1> undef, i1 1, i32 0 %m.splat = shufflevector <4 x i1> %m.first, <4 x i1> undef, <4 x i32> zeroinitializer @@ -111,9 +111,9 @@ define <4 x i8> @test_vp_fptoui_v4i8_v4f32_mask(<4 x float> %a, <4 x i1> %m, i32 ; CHECK-LABEL: test_vp_fptoui_v4i8_v4f32_mask: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8, v0.t +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0, v0.t +; CHECK-NEXT: vnsrl.wi v8, v9, 0, v0.t ; CHECK-NEXT: ret %x = call <4 x i8> @llvm.vp.fptoui.v4i8.v4f32(<4 x float> %a, <4 x i1> %m, i32 %evl) ret <4 x i8> %x @@ -123,11 +123,11 @@ define <4 x i8> @test_vp_fptoui_v4i8_v4f64(<4 x double> %a, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_fptoui_v4i8_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %m.first = insertelement <4 x i1> undef, i1 1, i32 0 %m.splat = shufflevector <4 x i1> %m.first, <4 x i1> undef, <4 x i32> zeroinitializer @@ -139,11 +139,11 @@ define <4 x i8> @test_vp_fptoui_v4i8_v4f64_mask(<4 x double> %a, <4 x i1> %m, i3 ; CHECK-LABEL: test_vp_fptoui_v4i8_v4f64_mask: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8, v0.t +; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0, v0.t +; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0, v0.t +; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t ; CHECK-NEXT: ret %x = call <4 x i8> @llvm.vp.fptoui.v4i8.v4f64(<4 x double> %a, <4 x i1> %m, i32 %evl) ret <4 x i8> %x @@ -153,9 +153,9 @@ define <4 x i16> @test_vp_fptoui_v4i16_v4f64(<4 x double> %a, i32 zeroext %evl) ; CHECK-LABEL: test_vp_fptoui_v4i16_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %m.first = insertelement <4 x i1> undef, i1 1, i32 0 %m.splat = shufflevector <4 x i1> %m.first, <4 x i1> undef, <4 x i32> zeroinitializer @@ -167,9 +167,9 @@ define <4 x i16> @test_vp_fptoui_v4i16_v4f64_mask(<4 x double> %a, <4 x i1> %m, ; CHECK-LABEL: test_vp_fptoui_v4i16_v4f64_mask: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8, v0.t +; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0, v0.t +; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t ; CHECK-NEXT: ret %x = call <4 x i16> @llvm.vp.fptoui.v4i16.v4f64(<4 x double> %a, <4 x i1> %m, i32 %evl) ret <4 x i16> %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-fptoui.ll b/llvm/test/CodeGen/RISCV/epi-vp-fptoui.ll index 4505a1325c91cd8e1690fc6421de2202513397a9..9dd53f230a5ee5a66e8cdcae4e5a7176c24aac5d 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-fptoui.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-fptoui.ll @@ -36,8 +36,8 @@ define @fptoui.i64.f32( %a, i32 zeroext % ; CHECK-LABEL: fptoui.i64.f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret { %b = call @llvm.vp.fptoui.nxv2i64.nxv2f32( %a, @@ -50,8 +50,8 @@ define @fptoui.i64.f32.mask( %a, @llvm.vp.fptoui.nxv2i64.nxv2f32( @@ -67,8 +67,8 @@ define @fptoui.i32.f64( %a, i32 zeroext ; CHECK-LABEL: fptoui.i32.f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret { %b = call @llvm.vp.fptoui.nxv2i32.nxv2f64( %a, @@ -81,8 +81,8 @@ define @fptoui.i32.f64.mask( %a, @llvm.vp.fptoui.nxv2i32.nxv2f64( @@ -98,9 +98,9 @@ define @test_vp_fptoui_nxv4i8_nxv4f32( %a, ; CHECK-LABEL: test_vp_fptoui_nxv4i8_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -112,9 +112,9 @@ define @test_vp_fptoui_nxv4i8_nxv4f32_mask( @llvm.vp.fptoui.nxv4i8.nxv4f32( %a, %m, i32 %evl) ret %x @@ -124,11 +124,11 @@ define @test_vp_fptoui_nxv4i8_nxv4f64( %a ; CHECK-LABEL: test_vp_fptoui_nxv4i8_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -140,11 +140,11 @@ define @test_vp_fptoui_nxv4i8_nxv4f64_mask( @llvm.vp.fptoui.nxv4i8.nxv4f64( %a, %m, i32 %evl) ret %x @@ -154,9 +154,9 @@ define @test_vp_fptoui_nxv4i16_nxv4f64( ; CHECK-LABEL: test_vp_fptoui_nxv4i16_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -168,9 +168,9 @@ define @test_vp_fptoui_nxv4i16_nxv4f64_mask( @llvm.vp.fptoui.nxv4i16.nxv4f64( %a, %m, i32 %evl) ret %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-fptrunc.ll b/llvm/test/CodeGen/RISCV/epi-vp-fptrunc.ll index f8299459fbd9414946becf2ca8677b3ce391324c..3b6bda676f6c282db84be1be540a92a7fdace82a 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-fptrunc.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-fptrunc.ll @@ -6,8 +6,8 @@ define @fptrunc.f32.f64( %a, i32 zeroe ; CHECK-LABEL: fptrunc.f32.f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.f.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.f.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret { %b = call @llvm.vp.fptrunc.nxv2f32.nxv2f64( %a, @@ -20,8 +20,8 @@ define @fptrunc.f32.f64.mask( %a, @llvm.vp.fptrunc.nxv2f32.nxv2f64( diff --git a/llvm/test/CodeGen/RISCV/epi-vp-gather.ll b/llvm/test/CodeGen/RISCV/epi-vp-gather.ll index dade0a91abfa8f78babade7d6f6608d1fa881f40..dba0f59c70312de1935e32d934b47b15b4ea4c0d 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-gather.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-gather.ll @@ -6,11 +6,11 @@ define @nxv1i64_1(i64* %ptr, %indices, %indices %data = call @llvm.vp.gather.nxv1i64.nxv1p0i64( %ptrs, %mask, i32 %evl) @@ -33,11 +33,11 @@ define @nxv1i64_3(i64* %ptr, %mask, i32 %ev ; CHECK-LABEL: nxv1i64_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: slli a0, a1, 32 ; CHECK-NEXT: srli a0, a0, 32 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vluxei64.v v8, (zero), v25, v0.t +; CHECK-NEXT: vluxei64.v v8, (zero), v8, v0.t ; CHECK-NEXT: ret %head = insertelement undef, i64* %ptr, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -51,10 +51,10 @@ define @nxv2f32_1(float* %ptr, %indices, ; CHECK-NEXT: slli a1, a1, 32 ; CHECK-NEXT: srli a1, a1, 32 ; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vsll.vi v26, v26, 2 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vsll.vi v10, v10, 2 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v26, v0.t +; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret %ptrs = getelementptr float, float* %ptr, %indices %data = call @llvm.vp.gather.nxv2f32.nxv2p0f32( %ptrs, %mask, i32 %evl) @@ -67,8 +67,8 @@ define @nxv2f32_2( %ptrs, @llvm.vp.gather.nxv2f32.nxv2p0f32( %ptrs, %mask, i32 %evl) ret %data @@ -78,11 +78,11 @@ define @nxv2f32_3(float* %ptr, %mask, i32 ; CHECK-LABEL: nxv2f32_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: slli a0, a1, 32 ; CHECK-NEXT: srli a0, a0, 32 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vluxei64.v v8, (zero), v26, v0.t +; CHECK-NEXT: vluxei64.v v8, (zero), v10, v0.t ; CHECK-NEXT: ret %head = insertelement undef, float* %ptr, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/epi-vp-icmp-fold-splats.ll b/llvm/test/CodeGen/RISCV/epi-vp-icmp-fold-splats.ll index c72a5b34e7a75511f617ab6cdaba35277947155f..073921ccccb84b25e4f60e7a70a490f2348d0823 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-icmp-fold-splats.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-icmp-fold-splats.ll @@ -17,38 +17,39 @@ define void @test_vp_fold_unsigned_greater( %a, i64 %b, %a, i64 %b, * @@ -114,38 +115,39 @@ define void @test_vp_fold_unsigned_lower( %a, i64 %b, %a, i64 %b, * @@ -211,38 +213,39 @@ define void @test_vp_fold_signed_greater( %a, i64 %b, %a, i64 %b, * @@ -308,38 +311,39 @@ define void @test_vp_fold_signed_lower( %a, i64 %b, %a, i64 %b, * diff --git a/llvm/test/CodeGen/RISCV/epi-vp-icmp-gt.ll b/llvm/test/CodeGen/RISCV/epi-vp-icmp-gt.ll index 9baa572e3d21a3ff3a15162636f831de00f9272f..7e1821f6b08e8949dbe1746bd3abc80a6dbf2c04 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-icmp-gt.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-icmp-gt.ll @@ -7,11 +7,12 @@ define @test_vp_icmp_gtu( %a, i64 %b, %m, i32 zeroext %evl) nounwind { ; CHECK-O0-LABEL: test_vp_icmp_gtu: ; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: vmv1r.v v9, v8 ; CHECK-O0-NEXT: # kill: def $x12 killed $x11 -; CHECK-O0-NEXT: # implicit-def: $v25 +; CHECK-O0-NEXT: # implicit-def: $v8 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-O0-NEXT: vmv1r.v v0, v25 +; CHECK-O0-NEXT: vmsgtu.vx v8, v9, a0, v0.t +; CHECK-O0-NEXT: vmv1r.v v0, v8 ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_icmp_gtu: @@ -28,11 +29,12 @@ define @test_vp_icmp_gtu( %a, i64 %b, @test_vp_icmp_gt( %a, i64 %b, %m, i32 zeroext %evl) nounwind { ; CHECK-O0-LABEL: test_vp_icmp_gt: ; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: vmv1r.v v9, v8 ; CHECK-O0-NEXT: # kill: def $x12 killed $x11 -; CHECK-O0-NEXT: # implicit-def: $v25 +; CHECK-O0-NEXT: # implicit-def: $v8 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-O0-NEXT: vmv1r.v v0, v25 +; CHECK-O0-NEXT: vmsgt.vx v8, v9, a0, v0.t +; CHECK-O0-NEXT: vmv1r.v v0, v8 ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_icmp_gt: diff --git a/llvm/test/CodeGen/RISCV/epi-vp-icmp-gt_disable-vpred-sdags.ll b/llvm/test/CodeGen/RISCV/epi-vp-icmp-gt_disable-vpred-sdags.ll index 8043d79ae213ca4c9766f2a3cac2d82d6c982429..a2312717feadb3b2985acdcfe28f5cec2a32e163 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-icmp-gt_disable-vpred-sdags.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-icmp-gt_disable-vpred-sdags.ll @@ -7,11 +7,12 @@ define @test_vp_icmp_gtu( %a, i64 %b, %m, i32 %evl) nounwind { ; CHECK-O0-LABEL: test_vp_icmp_gtu: ; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: vmv1r.v v9, v8 ; CHECK-O0-NEXT: # kill: def $x12 killed $x11 -; CHECK-O0-NEXT: # implicit-def: $v25 +; CHECK-O0-NEXT: # implicit-def: $v8 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-O0-NEXT: vmv1r.v v0, v25 +; CHECK-O0-NEXT: vmsgtu.vx v8, v9, a0, v0.t +; CHECK-O0-NEXT: vmv1r.v v0, v8 ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_icmp_gtu: @@ -28,11 +29,12 @@ define @test_vp_icmp_gtu( %a, i64 %b, @test_vp_icmp_gt( %a, i64 %b, %m, i32 %evl) nounwind { ; CHECK-O0-LABEL: test_vp_icmp_gt: ; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: vmv1r.v v9, v8 ; CHECK-O0-NEXT: # kill: def $x12 killed $x11 -; CHECK-O0-NEXT: # implicit-def: $v25 +; CHECK-O0-NEXT: # implicit-def: $v8 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-O0-NEXT: vmv1r.v v0, v25 +; CHECK-O0-NEXT: vmsgt.vx v8, v9, a0, v0.t +; CHECK-O0-NEXT: vmv1r.v v0, v8 ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_icmp_gt: diff --git a/llvm/test/CodeGen/RISCV/epi-vp-icmp-unmasked.ll b/llvm/test/CodeGen/RISCV/epi-vp-icmp-unmasked.ll index 60f00f0d2f2308a22f373109b863934937a15b30..0972a43bd455cc36cfb42cdfd7a840a8c7c5e956 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-icmp-unmasked.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-icmp-unmasked.ll @@ -14,45 +14,45 @@ define void @test_vp_icmp( %a, %b, i32 %n) ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmseq.vv v25, v8, v9 +; CHECK-O0-NEXT: vmseq.vv v10, v8, v9 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmsne.vv v25, v8, v9 +; CHECK-O0-NEXT: vmsne.vv v10, v8, v9 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmsltu.vv v25, v9, v8 +; CHECK-O0-NEXT: vmsltu.vv v10, v9, v8 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmsleu.vv v25, v9, v8 +; CHECK-O0-NEXT: vmsleu.vv v10, v9, v8 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmsltu.vv v25, v8, v9 +; CHECK-O0-NEXT: vmsltu.vv v10, v8, v9 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmsleu.vv v25, v8, v9 +; CHECK-O0-NEXT: vmsleu.vv v10, v8, v9 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmslt.vv v25, v9, v8 +; CHECK-O0-NEXT: vmslt.vv v10, v9, v8 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmsle.vv v25, v9, v8 +; CHECK-O0-NEXT: vmsle.vv v10, v9, v8 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmslt.vv v25, v8, v9 +; CHECK-O0-NEXT: vmslt.vv v10, v8, v9 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmsle.vv v25, v8, v9 +; CHECK-O0-NEXT: vmsle.vv v8, v8, v9 ; CHECK-O0-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_icmp: @@ -62,45 +62,45 @@ define void @test_vp_icmp( %a, %b, i32 %n) ; CHECK-O2-NEXT: lui a1, %hi(scratch) ; CHECK-O2-NEXT: addi a1, a1, %lo(scratch) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O2-NEXT: vmseq.vv v25, v8, v9 +; CHECK-O2-NEXT: vmseq.vv v10, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O2-NEXT: vmsne.vv v25, v8, v9 +; CHECK-O2-NEXT: vmsne.vv v10, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O2-NEXT: vmsltu.vv v25, v9, v8 +; CHECK-O2-NEXT: vmsltu.vv v10, v9, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O2-NEXT: vmsleu.vv v25, v9, v8 +; CHECK-O2-NEXT: vmsleu.vv v10, v9, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O2-NEXT: vmsltu.vv v25, v8, v9 +; CHECK-O2-NEXT: vmsltu.vv v10, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O2-NEXT: vmsleu.vv v25, v8, v9 +; CHECK-O2-NEXT: vmsleu.vv v10, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O2-NEXT: vmslt.vv v25, v9, v8 +; CHECK-O2-NEXT: vmslt.vv v10, v9, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O2-NEXT: vmsle.vv v25, v9, v8 +; CHECK-O2-NEXT: vmsle.vv v10, v9, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O2-NEXT: vmslt.vv v25, v8, v9 +; CHECK-O2-NEXT: vmslt.vv v10, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O2-NEXT: vmsle.vv v25, v8, v9 +; CHECK-O2-NEXT: vmsle.vv v8, v8, v9 ; CHECK-O2-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v8, (a1) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -148,45 +148,45 @@ define void @test_vp_icmp_2( %a, %b, i32 %n ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmseq.vv v25, v8, v9 +; CHECK-O0-NEXT: vmseq.vv v10, v8, v9 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmsne.vv v25, v8, v9 +; CHECK-O0-NEXT: vmsne.vv v10, v8, v9 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmsltu.vv v25, v9, v8 +; CHECK-O0-NEXT: vmsltu.vv v10, v9, v8 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmsleu.vv v25, v9, v8 +; CHECK-O0-NEXT: vmsleu.vv v10, v9, v8 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmsltu.vv v25, v8, v9 +; CHECK-O0-NEXT: vmsltu.vv v10, v8, v9 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmsleu.vv v25, v8, v9 +; CHECK-O0-NEXT: vmsleu.vv v10, v8, v9 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmslt.vv v25, v9, v8 +; CHECK-O0-NEXT: vmslt.vv v10, v9, v8 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmsle.vv v25, v9, v8 +; CHECK-O0-NEXT: vmsle.vv v10, v9, v8 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmslt.vv v25, v8, v9 +; CHECK-O0-NEXT: vmslt.vv v10, v8, v9 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v10, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmsle.vv v25, v8, v9 +; CHECK-O0-NEXT: vmsle.vv v8, v8, v9 ; CHECK-O0-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_icmp_2: @@ -196,45 +196,45 @@ define void @test_vp_icmp_2( %a, %b, i32 %n ; CHECK-O2-NEXT: lui a1, %hi(scratch) ; CHECK-O2-NEXT: addi a1, a1, %lo(scratch) ; CHECK-O2-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-O2-NEXT: vmseq.vv v25, v8, v9 +; CHECK-O2-NEXT: vmseq.vv v10, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-O2-NEXT: vmsne.vv v25, v8, v9 +; CHECK-O2-NEXT: vmsne.vv v10, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-O2-NEXT: vmsltu.vv v25, v9, v8 +; CHECK-O2-NEXT: vmsltu.vv v10, v9, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-O2-NEXT: vmsleu.vv v25, v9, v8 +; CHECK-O2-NEXT: vmsleu.vv v10, v9, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-O2-NEXT: vmsltu.vv v25, v8, v9 +; CHECK-O2-NEXT: vmsltu.vv v10, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-O2-NEXT: vmsleu.vv v25, v8, v9 +; CHECK-O2-NEXT: vmsleu.vv v10, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-O2-NEXT: vmslt.vv v25, v9, v8 +; CHECK-O2-NEXT: vmslt.vv v10, v9, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-O2-NEXT: vmsle.vv v25, v9, v8 +; CHECK-O2-NEXT: vmsle.vv v10, v9, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-O2-NEXT: vmslt.vv v25, v8, v9 +; CHECK-O2-NEXT: vmslt.vv v10, v8, v9 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v10, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-O2-NEXT: vmsle.vv v25, v8, v9 +; CHECK-O2-NEXT: vmsle.vv v8, v8, v9 ; CHECK-O2-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v8, (a1) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -277,50 +277,52 @@ define void @test_vp_icmp_2( %a, %b, i32 %n define void @test_vp_icmp_3( %a, %b, i32 %n) nounwind { ; CHECK-O0-LABEL: test_vp_icmp_3: ; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: vmv2r.v v12, v10 +; CHECK-O0-NEXT: vmv2r.v v10, v8 ; CHECK-O0-NEXT: slli a1, a0, 32 ; CHECK-O0-NEXT: srli a1, a1, 32 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmseq.vv v25, v8, v10 +; CHECK-O0-NEXT: vmseq.vv v8, v10, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmsne.vv v25, v8, v10 +; CHECK-O0-NEXT: vmsne.vv v8, v10, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmsltu.vv v25, v10, v8 +; CHECK-O0-NEXT: vmsltu.vv v8, v12, v10 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmsleu.vv v25, v10, v8 +; CHECK-O0-NEXT: vmsleu.vv v8, v12, v10 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmsltu.vv v25, v8, v10 +; CHECK-O0-NEXT: vmsltu.vv v8, v10, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmsleu.vv v25, v8, v10 +; CHECK-O0-NEXT: vmsleu.vv v8, v10, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmslt.vv v25, v10, v8 +; CHECK-O0-NEXT: vmslt.vv v8, v12, v10 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmsle.vv v25, v10, v8 +; CHECK-O0-NEXT: vmsle.vv v8, v12, v10 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmslt.vv v25, v8, v10 +; CHECK-O0-NEXT: vmslt.vv v8, v10, v12 ; CHECK-O0-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmsle.vv v25, v8, v10 +; CHECK-O0-NEXT: vmsle.vv v8, v10, v12 ; CHECK-O0-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_icmp_3: @@ -330,45 +332,45 @@ define void @test_vp_icmp_3( %a, %b, i32 %n ; CHECK-O2-NEXT: lui a1, %hi(scratch) ; CHECK-O2-NEXT: addi a1, a1, %lo(scratch) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-O2-NEXT: vmseq.vv v25, v8, v10 +; CHECK-O2-NEXT: vmseq.vv v12, v8, v10 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v12, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-O2-NEXT: vmsne.vv v25, v8, v10 +; CHECK-O2-NEXT: vmsne.vv v12, v8, v10 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v12, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-O2-NEXT: vmsltu.vv v25, v10, v8 +; CHECK-O2-NEXT: vmsltu.vv v12, v10, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v12, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-O2-NEXT: vmsleu.vv v25, v10, v8 +; CHECK-O2-NEXT: vmsleu.vv v12, v10, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v12, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-O2-NEXT: vmsltu.vv v25, v8, v10 +; CHECK-O2-NEXT: vmsltu.vv v12, v8, v10 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v12, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-O2-NEXT: vmsleu.vv v25, v8, v10 +; CHECK-O2-NEXT: vmsleu.vv v12, v8, v10 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v12, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-O2-NEXT: vmslt.vv v25, v10, v8 +; CHECK-O2-NEXT: vmslt.vv v12, v10, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v12, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-O2-NEXT: vmsle.vv v25, v10, v8 +; CHECK-O2-NEXT: vmsle.vv v12, v10, v8 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v12, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-O2-NEXT: vmslt.vv v25, v8, v10 +; CHECK-O2-NEXT: vmslt.vv v12, v8, v10 ; CHECK-O2-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v12, (a1) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-O2-NEXT: vmsle.vv v25, v8, v10 +; CHECK-O2-NEXT: vmsle.vv v12, v8, v10 ; CHECK-O2-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v12, (a1) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * diff --git a/llvm/test/CodeGen/RISCV/epi-vp-icmp.ll b/llvm/test/CodeGen/RISCV/epi-vp-icmp.ll index 9f15487a10ea346f57a0d5b1ec9c5f8dfc27053b..ec42971f3ac4b358409e934b39cd65765274fd7b 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-icmp.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-icmp.ll @@ -14,78 +14,80 @@ define void @test_vp_icmp( %a, %b, %a, %b, * @@ -181,78 +183,80 @@ define void @test_vp_icmp_2( %a, %b, %a, %b, * @@ -348,78 +352,80 @@ define void @test_vp_icmp_3( %a, %b, %a, %b, * diff --git a/llvm/test/CodeGen/RISCV/epi-vp-int.ll b/llvm/test/CodeGen/RISCV/epi-vp-int.ll index 92173889067b5a048a5290606cd5b2a19a36f228..ee239649975c786ca8f7d9f1dad2a8fce2df2b03 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-int.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-int.ll @@ -21,104 +21,104 @@ define void @test_vp_int(* %a0, * %a1, * %a0, * %a1, * @@ -207,34 +207,34 @@ define void @test_vp_int_2(* %a0, * %a1, i32 ; CHECK-O0-NEXT: slli a3, a3, 32 ; CHECK-O0-NEXT: srli a3, a3, 32 ; CHECK-O0-NEXT: vsetvli zero, a3, e32, m1, ta, mu -; CHECK-O0-NEXT: vle32.v v25, (a2) -; CHECK-O0-NEXT: vle32.v v14, (a1) -; CHECK-O0-NEXT: vadd.vv v13, v25, v14 -; CHECK-O0-NEXT: vsub.vv v12, v25, v14 -; CHECK-O0-NEXT: vmul.vv v11, v25, v14 -; CHECK-O0-NEXT: vdiv.vv v10, v25, v14 -; CHECK-O0-NEXT: vrem.vv v9, v25, v14 -; CHECK-O0-NEXT: vdivu.vv v8, v25, v14 -; CHECK-O0-NEXT: vremu.vv v31, v25, v14 -; CHECK-O0-NEXT: vand.vv v30, v25, v14 -; CHECK-O0-NEXT: vor.vv v29, v25, v14 -; CHECK-O0-NEXT: vxor.vv v28, v25, v14 -; CHECK-O0-NEXT: vsra.vv v27, v25, v14 -; CHECK-O0-NEXT: vsrl.vv v26, v25, v14 -; CHECK-O0-NEXT: vsll.vv v25, v25, v14 +; CHECK-O0-NEXT: vle32.v v8, (a2) +; CHECK-O0-NEXT: vle32.v v21, (a1) +; CHECK-O0-NEXT: vadd.vv v20, v8, v21 +; CHECK-O0-NEXT: vsub.vv v19, v8, v21 +; CHECK-O0-NEXT: vmul.vv v18, v8, v21 +; CHECK-O0-NEXT: vdiv.vv v17, v8, v21 +; CHECK-O0-NEXT: vrem.vv v16, v8, v21 +; CHECK-O0-NEXT: vdivu.vv v15, v8, v21 +; CHECK-O0-NEXT: vremu.vv v14, v8, v21 +; CHECK-O0-NEXT: vand.vv v13, v8, v21 +; CHECK-O0-NEXT: vor.vv v12, v8, v21 +; CHECK-O0-NEXT: vxor.vv v11, v8, v21 +; CHECK-O0-NEXT: vsra.vv v10, v8, v21 +; CHECK-O0-NEXT: vsrl.vv v9, v8, v21 +; CHECK-O0-NEXT: vsll.vv v8, v8, v21 +; CHECK-O0-NEXT: vse32.v v20, (a0) +; CHECK-O0-NEXT: vse32.v v19, (a0) +; CHECK-O0-NEXT: vse32.v v18, (a0) +; CHECK-O0-NEXT: vse32.v v17, (a0) +; CHECK-O0-NEXT: vse32.v v16, (a0) +; CHECK-O0-NEXT: vse32.v v15, (a0) +; CHECK-O0-NEXT: vse32.v v14, (a0) ; CHECK-O0-NEXT: vse32.v v13, (a0) ; CHECK-O0-NEXT: vse32.v v12, (a0) ; CHECK-O0-NEXT: vse32.v v11, (a0) ; CHECK-O0-NEXT: vse32.v v10, (a0) ; CHECK-O0-NEXT: vse32.v v9, (a0) ; CHECK-O0-NEXT: vse32.v v8, (a0) -; CHECK-O0-NEXT: vse32.v v31, (a0) -; CHECK-O0-NEXT: vse32.v v30, (a0) -; CHECK-O0-NEXT: vse32.v v29, (a0) -; CHECK-O0-NEXT: vse32.v v28, (a0) -; CHECK-O0-NEXT: vse32.v v27, (a0) -; CHECK-O0-NEXT: vse32.v v26, (a0) -; CHECK-O0-NEXT: vse32.v v25, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_int_2: @@ -242,36 +242,36 @@ define void @test_vp_int_2(* %a0, * %a1, i32 ; CHECK-O2-NEXT: slli a2, a2, 32 ; CHECK-O2-NEXT: srli a2, a2, 32 ; CHECK-O2-NEXT: vsetvli zero, a2, e32, m1, ta, mu -; CHECK-O2-NEXT: vle32.v v25, (a0) -; CHECK-O2-NEXT: vle32.v v26, (a1) +; CHECK-O2-NEXT: vle32.v v8, (a0) +; CHECK-O2-NEXT: vle32.v v9, (a1) ; CHECK-O2-NEXT: lui a0, %hi(scratch) ; CHECK-O2-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O2-NEXT: vadd.vv v27, v25, v26 -; CHECK-O2-NEXT: vsub.vv v28, v25, v26 -; CHECK-O2-NEXT: vmul.vv v29, v25, v26 -; CHECK-O2-NEXT: vdiv.vv v30, v25, v26 -; CHECK-O2-NEXT: vrem.vv v31, v25, v26 -; CHECK-O2-NEXT: vdivu.vv v8, v25, v26 -; CHECK-O2-NEXT: vremu.vv v9, v25, v26 -; CHECK-O2-NEXT: vand.vv v10, v25, v26 -; CHECK-O2-NEXT: vor.vv v11, v25, v26 -; CHECK-O2-NEXT: vxor.vv v12, v25, v26 -; CHECK-O2-NEXT: vsra.vv v13, v25, v26 -; CHECK-O2-NEXT: vsrl.vv v14, v25, v26 -; CHECK-O2-NEXT: vsll.vv v25, v25, v26 -; CHECK-O2-NEXT: vse32.v v27, (a0) -; CHECK-O2-NEXT: vse32.v v28, (a0) -; CHECK-O2-NEXT: vse32.v v29, (a0) -; CHECK-O2-NEXT: vse32.v v30, (a0) -; CHECK-O2-NEXT: vse32.v v31, (a0) -; CHECK-O2-NEXT: vse32.v v8, (a0) -; CHECK-O2-NEXT: vse32.v v9, (a0) +; CHECK-O2-NEXT: vadd.vv v10, v8, v9 +; CHECK-O2-NEXT: vsub.vv v11, v8, v9 +; CHECK-O2-NEXT: vmul.vv v12, v8, v9 +; CHECK-O2-NEXT: vdiv.vv v13, v8, v9 +; CHECK-O2-NEXT: vrem.vv v14, v8, v9 +; CHECK-O2-NEXT: vdivu.vv v15, v8, v9 +; CHECK-O2-NEXT: vremu.vv v16, v8, v9 +; CHECK-O2-NEXT: vand.vv v17, v8, v9 +; CHECK-O2-NEXT: vor.vv v18, v8, v9 +; CHECK-O2-NEXT: vxor.vv v19, v8, v9 +; CHECK-O2-NEXT: vsra.vv v20, v8, v9 +; CHECK-O2-NEXT: vsrl.vv v21, v8, v9 +; CHECK-O2-NEXT: vsll.vv v8, v8, v9 ; CHECK-O2-NEXT: vse32.v v10, (a0) ; CHECK-O2-NEXT: vse32.v v11, (a0) ; CHECK-O2-NEXT: vse32.v v12, (a0) ; CHECK-O2-NEXT: vse32.v v13, (a0) ; CHECK-O2-NEXT: vse32.v v14, (a0) -; CHECK-O2-NEXT: vse32.v v25, (a0) +; CHECK-O2-NEXT: vse32.v v15, (a0) +; CHECK-O2-NEXT: vse32.v v16, (a0) +; CHECK-O2-NEXT: vse32.v v17, (a0) +; CHECK-O2-NEXT: vse32.v v18, (a0) +; CHECK-O2-NEXT: vse32.v v19, (a0) +; CHECK-O2-NEXT: vse32.v v20, (a0) +; CHECK-O2-NEXT: vse32.v v21, (a0) +; CHECK-O2-NEXT: vse32.v v8, (a0) ; CHECK-O2-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -340,55 +340,64 @@ define void @test_vp_int_3(* %a0, * %a1, * %a0, * %a1, * %a0, * %a1, * %a0, * %a1, * diff --git a/llvm/test/CodeGen/RISCV/epi-vp-int_disable-vpred-sdags.ll b/llvm/test/CodeGen/RISCV/epi-vp-int_disable-vpred-sdags.ll index 57eb24705d6720420aeb0f40902e9eae3bbaf7c2..fcc433c08ea390fb2ee2e397365d1e64483b5569 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-int_disable-vpred-sdags.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-int_disable-vpred-sdags.ll @@ -19,104 +19,104 @@ define void @test_vp_int(* %a0, * %a1, * %a0, * %a1, * @@ -200,85 +200,85 @@ define void @test_vp_int_2(* %a0, * %a1, i32 ; CHECK-O0-NEXT: # kill: def $x10 killed $x13 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O0-NEXT: # implicit-def: $v14 +; CHECK-O0-NEXT: # implicit-def: $v21 ; CHECK-O0-NEXT: vsetvli zero, a3, e32, m1, ta, mu -; CHECK-O0-NEXT: vle32.v v14, (a2) +; CHECK-O0-NEXT: vle32.v v21, (a2) +; CHECK-O0-NEXT: # implicit-def: $v22 +; CHECK-O0-NEXT: vle32.v v22, (a1) +; CHECK-O0-NEXT: # implicit-def: $v20 +; CHECK-O0-NEXT: vadd.vv v20, v21, v22 +; CHECK-O0-NEXT: # implicit-def: $v19 +; CHECK-O0-NEXT: vsub.vv v19, v21, v22 +; CHECK-O0-NEXT: # implicit-def: $v18 +; CHECK-O0-NEXT: vmul.vv v18, v21, v22 +; CHECK-O0-NEXT: # implicit-def: $v17 +; CHECK-O0-NEXT: vdiv.vv v17, v21, v22 +; CHECK-O0-NEXT: # implicit-def: $v16 +; CHECK-O0-NEXT: vrem.vv v16, v21, v22 ; CHECK-O0-NEXT: # implicit-def: $v15 -; CHECK-O0-NEXT: vle32.v v15, (a1) +; CHECK-O0-NEXT: vdivu.vv v15, v21, v22 +; CHECK-O0-NEXT: # implicit-def: $v14 +; CHECK-O0-NEXT: vremu.vv v14, v21, v22 ; CHECK-O0-NEXT: # implicit-def: $v13 -; CHECK-O0-NEXT: vadd.vv v13, v14, v15 +; CHECK-O0-NEXT: vand.vv v13, v21, v22 ; CHECK-O0-NEXT: # implicit-def: $v12 -; CHECK-O0-NEXT: vsub.vv v12, v14, v15 +; CHECK-O0-NEXT: vor.vv v12, v21, v22 ; CHECK-O0-NEXT: # implicit-def: $v11 -; CHECK-O0-NEXT: vmul.vv v11, v14, v15 +; CHECK-O0-NEXT: vxor.vv v11, v21, v22 ; CHECK-O0-NEXT: # implicit-def: $v10 -; CHECK-O0-NEXT: vdiv.vv v10, v14, v15 +; CHECK-O0-NEXT: vsra.vv v10, v21, v22 ; CHECK-O0-NEXT: # implicit-def: $v9 -; CHECK-O0-NEXT: vrem.vv v9, v14, v15 +; CHECK-O0-NEXT: vsrl.vv v9, v21, v22 ; CHECK-O0-NEXT: # implicit-def: $v8 -; CHECK-O0-NEXT: vdivu.vv v8, v14, v15 -; CHECK-O0-NEXT: # implicit-def: $v31 -; CHECK-O0-NEXT: vremu.vv v31, v14, v15 -; CHECK-O0-NEXT: # implicit-def: $v30 -; CHECK-O0-NEXT: vand.vv v30, v14, v15 -; CHECK-O0-NEXT: # implicit-def: $v29 -; CHECK-O0-NEXT: vor.vv v29, v14, v15 -; CHECK-O0-NEXT: # implicit-def: $v28 -; CHECK-O0-NEXT: vxor.vv v28, v14, v15 -; CHECK-O0-NEXT: # implicit-def: $v27 -; CHECK-O0-NEXT: vsra.vv v27, v14, v15 -; CHECK-O0-NEXT: # implicit-def: $v26 -; CHECK-O0-NEXT: vsrl.vv v26, v14, v15 -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vsll.vv v25, v14, v15 +; CHECK-O0-NEXT: vsll.vv v8, v21, v22 +; CHECK-O0-NEXT: vse32.v v20, (a0) +; CHECK-O0-NEXT: vse32.v v19, (a0) +; CHECK-O0-NEXT: vse32.v v18, (a0) +; CHECK-O0-NEXT: vse32.v v17, (a0) +; CHECK-O0-NEXT: vse32.v v16, (a0) +; CHECK-O0-NEXT: vse32.v v15, (a0) +; CHECK-O0-NEXT: vse32.v v14, (a0) ; CHECK-O0-NEXT: vse32.v v13, (a0) ; CHECK-O0-NEXT: vse32.v v12, (a0) ; CHECK-O0-NEXT: vse32.v v11, (a0) ; CHECK-O0-NEXT: vse32.v v10, (a0) ; CHECK-O0-NEXT: vse32.v v9, (a0) ; CHECK-O0-NEXT: vse32.v v8, (a0) -; CHECK-O0-NEXT: vse32.v v31, (a0) -; CHECK-O0-NEXT: vse32.v v30, (a0) -; CHECK-O0-NEXT: vse32.v v29, (a0) -; CHECK-O0-NEXT: vse32.v v28, (a0) -; CHECK-O0-NEXT: vse32.v v27, (a0) -; CHECK-O0-NEXT: vse32.v v26, (a0) -; CHECK-O0-NEXT: vse32.v v25, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_int_2: ; CHECK-O2: # %bb.0: ; CHECK-O2-NEXT: vsetvli zero, a2, e32, m1, ta, mu -; CHECK-O2-NEXT: vle32.v v25, (a0) -; CHECK-O2-NEXT: vle32.v v26, (a1) +; CHECK-O2-NEXT: vle32.v v8, (a0) +; CHECK-O2-NEXT: vle32.v v9, (a1) ; CHECK-O2-NEXT: lui a0, %hi(scratch) ; CHECK-O2-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O2-NEXT: vadd.vv v27, v25, v26 -; CHECK-O2-NEXT: vsub.vv v28, v25, v26 -; CHECK-O2-NEXT: vmul.vv v29, v25, v26 -; CHECK-O2-NEXT: vdiv.vv v30, v25, v26 -; CHECK-O2-NEXT: vrem.vv v31, v25, v26 -; CHECK-O2-NEXT: vdivu.vv v8, v25, v26 -; CHECK-O2-NEXT: vremu.vv v9, v25, v26 -; CHECK-O2-NEXT: vand.vv v10, v25, v26 -; CHECK-O2-NEXT: vor.vv v11, v25, v26 -; CHECK-O2-NEXT: vxor.vv v12, v25, v26 -; CHECK-O2-NEXT: vsra.vv v13, v25, v26 -; CHECK-O2-NEXT: vsrl.vv v14, v25, v26 -; CHECK-O2-NEXT: vsll.vv v25, v25, v26 -; CHECK-O2-NEXT: vse32.v v27, (a0) -; CHECK-O2-NEXT: vse32.v v28, (a0) -; CHECK-O2-NEXT: vse32.v v29, (a0) -; CHECK-O2-NEXT: vse32.v v30, (a0) -; CHECK-O2-NEXT: vse32.v v31, (a0) -; CHECK-O2-NEXT: vse32.v v8, (a0) -; CHECK-O2-NEXT: vse32.v v9, (a0) +; CHECK-O2-NEXT: vadd.vv v10, v8, v9 +; CHECK-O2-NEXT: vsub.vv v11, v8, v9 +; CHECK-O2-NEXT: vmul.vv v12, v8, v9 +; CHECK-O2-NEXT: vdiv.vv v13, v8, v9 +; CHECK-O2-NEXT: vrem.vv v14, v8, v9 +; CHECK-O2-NEXT: vdivu.vv v15, v8, v9 +; CHECK-O2-NEXT: vremu.vv v16, v8, v9 +; CHECK-O2-NEXT: vand.vv v17, v8, v9 +; CHECK-O2-NEXT: vor.vv v18, v8, v9 +; CHECK-O2-NEXT: vxor.vv v19, v8, v9 +; CHECK-O2-NEXT: vsra.vv v20, v8, v9 +; CHECK-O2-NEXT: vsrl.vv v21, v8, v9 +; CHECK-O2-NEXT: vsll.vv v8, v8, v9 ; CHECK-O2-NEXT: vse32.v v10, (a0) ; CHECK-O2-NEXT: vse32.v v11, (a0) ; CHECK-O2-NEXT: vse32.v v12, (a0) ; CHECK-O2-NEXT: vse32.v v13, (a0) ; CHECK-O2-NEXT: vse32.v v14, (a0) -; CHECK-O2-NEXT: vse32.v v25, (a0) +; CHECK-O2-NEXT: vse32.v v15, (a0) +; CHECK-O2-NEXT: vse32.v v16, (a0) +; CHECK-O2-NEXT: vse32.v v17, (a0) +; CHECK-O2-NEXT: vse32.v v18, (a0) +; CHECK-O2-NEXT: vse32.v v19, (a0) +; CHECK-O2-NEXT: vse32.v v20, (a0) +; CHECK-O2-NEXT: vse32.v v21, (a0) +; CHECK-O2-NEXT: vse32.v v8, (a0) ; CHECK-O2-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -345,55 +345,64 @@ define void @test_vp_int_3(* %a0, * %a1, * %a0, * %a1, * %a0, * %a1, * %a0, * %a1, * diff --git a/llvm/test/CodeGen/RISCV/epi-vp-inttoptr-disable-vpred-sdags.ll b/llvm/test/CodeGen/RISCV/epi-vp-inttoptr-disable-vpred-sdags.ll index 30992c3261f5692b48654dbf6f659a091b3ffed3..8fbcff4658da70267433642248172a14e53506e2 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-inttoptr-disable-vpred-sdags.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-inttoptr-disable-vpred-sdags.ll @@ -6,11 +6,11 @@ define @test_llvm_vp_inttoptr_v8p0i8_v8i8( % ; CHECK-LABEL: test_llvm_vp_inttoptr_v8p0i8_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vwcvtu.x.x.v v26, v8, v0.t +; CHECK-NEXT: vwcvtu.x.x.v v10, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vwcvtu.x.x.v v28, v26, v0.t +; CHECK-NEXT: vwcvtu.x.x.v v16, v10, v0.t ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu -; CHECK-NEXT: vwcvtu.x.x.v v8, v28, v0.t +; CHECK-NEXT: vwcvtu.x.x.v v8, v16, v0.t ; CHECK-NEXT: ret %ptrs = call @llvm.vp.inttoptr.v8p0i8.v8i8( %a, %mask, i32 %evl) ret %ptrs @@ -20,9 +20,9 @@ define @test_llvm_vp_inttoptr_v4p0i16_v4i16( @llvm.vp.inttoptr.v4p0i16.v4i16( %a, %mask, i32 %evl) ret %ptrs @@ -32,8 +32,8 @@ define @test_llvm_vp_inttoptr_v2p0i32_v2i32( @llvm.vp.inttoptr.v2p0i32.v2i32( %a, %mask, i32 %evl) ret %ptrs diff --git a/llvm/test/CodeGen/RISCV/epi-vp-inttoptr.ll b/llvm/test/CodeGen/RISCV/epi-vp-inttoptr.ll index 8fe59db63f0427de40585db170676484c5179e3c..3ecf93eed4e43396b43b471c6faa8b18031df3f8 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-inttoptr.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-inttoptr.ll @@ -17,8 +17,8 @@ define @test_llvm_vp_inttoptr_v4p0i16_v4i16( @llvm.vp.inttoptr.v4p0i16.v4i16( %a, %mask, i32 %evl) ret %ptrs @@ -28,8 +28,8 @@ define @test_llvm_vp_inttoptr_v2p0i32_v2i32( @llvm.vp.inttoptr.v2p0i32.v2i32( %a, %mask, i32 %evl) ret %ptrs diff --git a/llvm/test/CodeGen/RISCV/epi-vp-logical-nosplat.ll b/llvm/test/CodeGen/RISCV/epi-vp-logical-nosplat.ll index e5aef0890ab3c9f5c0fc2b5231c545a11c57a5f3..c28673f314e0b6a57d679080ddf58a79f4260870 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-logical-nosplat.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-logical-nosplat.ll @@ -11,21 +11,21 @@ define @test_vp_logical_and( %a0, i32 %n) nou ; CHECK-O0: # %bb.0: ; CHECK-O0-NEXT: # kill: def $x11 killed $x10 ; CHECK-O0-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vmset.m v25 +; CHECK-O0-NEXT: vmset.m v8 ; CHECK-O0-NEXT: slli a0, a0, 32 ; CHECK-O0-NEXT: srli a0, a0, 32 ; CHECK-O0-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-O0-NEXT: vmand.mm v0, v0, v25 +; CHECK-O0-NEXT: vmand.mm v0, v0, v8 ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_logical_and: ; CHECK-O2: # %bb.0: ; CHECK-O2-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vmset.m v25 +; CHECK-O2-NEXT: vmset.m v8 ; CHECK-O2-NEXT: slli a0, a0, 32 ; CHECK-O2-NEXT: srli a0, a0, 32 ; CHECK-O2-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-O2-NEXT: vmand.mm v0, v0, v25 +; CHECK-O2-NEXT: vmand.mm v0, v0, v8 ; CHECK-O2-NEXT: ret %head.1 = insertelement undef, i1 1, i32 0 %allones = shufflevector %head.1, undef, zeroinitializer @@ -40,21 +40,21 @@ define @test_vp_logical_or( %a0, i32 %n) noun ; CHECK-O0: # %bb.0: ; CHECK-O0-NEXT: # kill: def $x11 killed $x10 ; CHECK-O0-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vmset.m v25 +; CHECK-O0-NEXT: vmset.m v8 ; CHECK-O0-NEXT: slli a0, a0, 32 ; CHECK-O0-NEXT: srli a0, a0, 32 ; CHECK-O0-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-O0-NEXT: vmor.mm v0, v0, v25 +; CHECK-O0-NEXT: vmor.mm v0, v0, v8 ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_logical_or: ; CHECK-O2: # %bb.0: ; CHECK-O2-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vmset.m v25 +; CHECK-O2-NEXT: vmset.m v8 ; CHECK-O2-NEXT: slli a0, a0, 32 ; CHECK-O2-NEXT: srli a0, a0, 32 ; CHECK-O2-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-O2-NEXT: vmor.mm v0, v0, v25 +; CHECK-O2-NEXT: vmor.mm v0, v0, v8 ; CHECK-O2-NEXT: ret %head.1 = insertelement undef, i1 1, i32 0 %allones = shufflevector %head.1, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/epi-vp-logical-nosplat_disable-vpred-sdags.ll b/llvm/test/CodeGen/RISCV/epi-vp-logical-nosplat_disable-vpred-sdags.ll index 7b88af1a5a976c673e3948d6bfa0519b6266e7d8..2dcfdc6f5069b7c1f60a0e919d2d6cbb894ae720 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-logical-nosplat_disable-vpred-sdags.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-logical-nosplat_disable-vpred-sdags.ll @@ -11,17 +11,17 @@ define @test_vp_logical_and( %a0, i32 %n) nou ; CHECK-O0: # %bb.0: ; CHECK-O0-NEXT: # kill: def $x11 killed $x10 ; CHECK-O0-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vmset.m v25 +; CHECK-O0-NEXT: vmset.m v8 ; CHECK-O0-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O0-NEXT: vmand.mm v0, v0, v25 +; CHECK-O0-NEXT: vmand.mm v0, v0, v8 ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_logical_and: ; CHECK-O2: # %bb.0: ; CHECK-O2-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vmset.m v25 +; CHECK-O2-NEXT: vmset.m v8 ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O2-NEXT: vmand.mm v0, v0, v25 +; CHECK-O2-NEXT: vmand.mm v0, v0, v8 ; CHECK-O2-NEXT: ret %head.1 = insertelement undef, i1 1, i32 0 %allones = shufflevector %head.1, undef, zeroinitializer @@ -36,17 +36,17 @@ define @test_vp_logical_or( %a0, i32 %n) noun ; CHECK-O0: # %bb.0: ; CHECK-O0-NEXT: # kill: def $x11 killed $x10 ; CHECK-O0-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vmset.m v25 +; CHECK-O0-NEXT: vmset.m v8 ; CHECK-O0-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O0-NEXT: vmor.mm v0, v0, v25 +; CHECK-O0-NEXT: vmor.mm v0, v0, v8 ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_logical_or: ; CHECK-O2: # %bb.0: ; CHECK-O2-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vmset.m v25 +; CHECK-O2-NEXT: vmset.m v8 ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O2-NEXT: vmor.mm v0, v0, v25 +; CHECK-O2-NEXT: vmor.mm v0, v0, v8 ; CHECK-O2-NEXT: ret %head.1 = insertelement undef, i1 1, i32 0 %allones = shufflevector %head.1, undef, zeroinitializer @@ -61,17 +61,17 @@ define @test_vp_logical_xor( %a0, i32 %n) nou ; CHECK-O0: # %bb.0: ; CHECK-O0-NEXT: # kill: def $x11 killed $x10 ; CHECK-O0-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-O0-NEXT: vmset.m v25 +; CHECK-O0-NEXT: vmset.m v8 ; CHECK-O0-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O0-NEXT: vmxor.mm v0, v0, v25 +; CHECK-O0-NEXT: vmxor.mm v0, v0, v8 ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_logical_xor: ; CHECK-O2: # %bb.0: ; CHECK-O2-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-O2-NEXT: vmset.m v25 +; CHECK-O2-NEXT: vmset.m v8 ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O2-NEXT: vmxor.mm v0, v0, v25 +; CHECK-O2-NEXT: vmxor.mm v0, v0, v8 ; CHECK-O2-NEXT: ret %head.1 = insertelement undef, i1 1, i32 0 %allones = shufflevector %head.1, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/epi-vp-logical.ll b/llvm/test/CodeGen/RISCV/epi-vp-logical.ll index 947d8251ec0cdcc8d4646dff6fe6ca530ae7aa59..9a1688a21b9a4a647e81b86560f35aea3be642c4 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-logical.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-logical.ll @@ -23,38 +23,38 @@ define void @test_vp_logical(* %a0, * %a1, i ; CHECK-O0-NEXT: slli a1, a1, 32 ; CHECK-O0-NEXT: srli a1, a1, 32 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vle64.v v25, (a3) -; CHECK-O0-NEXT: vle64.v v26, (a2) +; CHECK-O0-NEXT: vle64.v v8, (a3) +; CHECK-O0-NEXT: vle64.v v9, (a2) ; CHECK-O0-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; CHECK-O0-NEXT: vand.vi v25, v25, 1 -; CHECK-O0-NEXT: vmsne.vi v25, v25, 0 -; CHECK-O0-NEXT: vand.vi v26, v26, 1 -; CHECK-O0-NEXT: vmsne.vi v26, v26, 0 +; CHECK-O0-NEXT: vand.vi v8, v8, 1 +; CHECK-O0-NEXT: vmsne.vi v8, v8, 0 +; CHECK-O0-NEXT: vand.vi v9, v9, 1 +; CHECK-O0-NEXT: vmsne.vi v9, v9, 0 ; CHECK-O0-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-O0-NEXT: vmand.mm v0, v25, v26 -; CHECK-O0-NEXT: vmor.mm v27, v25, v26 +; CHECK-O0-NEXT: vmand.mm v0, v8, v9 +; CHECK-O0-NEXT: vmor.mm v10, v8, v9 ; CHECK-O0-NEXT: addi a2, sp, 32 -; CHECK-O0-NEXT: vs1r.v v27, (a2) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vmxor.mm v25, v25, v26 +; CHECK-O0-NEXT: vs1r.v v10, (a2) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 32 -; CHECK-O0-NEXT: vs1r.v v25, (a2) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vs1r.v v8, (a2) # Unknown-size Folded Spill ; CHECK-O0-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; CHECK-O0-NEXT: vmv.v.i v25, 0 -; CHECK-O0-NEXT: vmerge.vim v27, v25, 1, v0 +; CHECK-O0-NEXT: vmv.v.i v8, 0 +; CHECK-O0-NEXT: vmerge.vim v10, v8, 1, v0 ; CHECK-O0-NEXT: addi a2, sp, 32 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v26, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v9, v8, 1, v0 ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 32 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vse64.v v27, (a0) -; CHECK-O0-NEXT: vse64.v v26, (a0) -; CHECK-O0-NEXT: vse64.v v25, (a0) +; CHECK-O0-NEXT: vse64.v v10, (a0) +; CHECK-O0-NEXT: vse64.v v9, (a0) +; CHECK-O0-NEXT: vse64.v v8, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add sp, sp, a0 @@ -67,29 +67,29 @@ define void @test_vp_logical(* %a0, * %a1, i ; CHECK-O2-NEXT: slli a2, a2, 32 ; CHECK-O2-NEXT: srli a2, a2, 32 ; CHECK-O2-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; CHECK-O2-NEXT: vle64.v v25, (a0) +; CHECK-O2-NEXT: vle64.v v8, (a0) ; CHECK-O2-NEXT: addi a0, a3, %lo(scratch) -; CHECK-O2-NEXT: vle64.v v26, (a1) +; CHECK-O2-NEXT: vle64.v v9, (a1) ; CHECK-O2-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-O2-NEXT: vand.vi v25, v25, 1 -; CHECK-O2-NEXT: vmsne.vi v27, v25, 0 -; CHECK-O2-NEXT: vand.vi v25, v26, 1 -; CHECK-O2-NEXT: vmsne.vi v26, v25, 0 +; CHECK-O2-NEXT: vand.vi v8, v8, 1 +; CHECK-O2-NEXT: vmsne.vi v10, v8, 0 +; CHECK-O2-NEXT: vand.vi v8, v9, 1 +; CHECK-O2-NEXT: vmsne.vi v9, v8, 0 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, mf8, ta, mu -; CHECK-O2-NEXT: vmand.mm v0, v27, v26 -; CHECK-O2-NEXT: vmor.mm v25, v27, v26 -; CHECK-O2-NEXT: vmxor.mm v26, v27, v26 +; CHECK-O2-NEXT: vmand.mm v0, v10, v9 +; CHECK-O2-NEXT: vmor.mm v8, v10, v9 +; CHECK-O2-NEXT: vmxor.mm v9, v10, v9 ; CHECK-O2-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-O2-NEXT: vmv.v.i v27, 0 -; CHECK-O2-NEXT: vmerge.vim v28, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v25 -; CHECK-O2-NEXT: vmerge.vim v25, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v26 -; CHECK-O2-NEXT: vmerge.vim v26, v27, 1, v0 +; CHECK-O2-NEXT: vmv.v.i v10, 0 +; CHECK-O2-NEXT: vmerge.vim v11, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v8 +; CHECK-O2-NEXT: vmerge.vim v8, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v9 +; CHECK-O2-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-O2-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; CHECK-O2-NEXT: vse64.v v28, (a0) -; CHECK-O2-NEXT: vse64.v v25, (a0) -; CHECK-O2-NEXT: vse64.v v26, (a0) +; CHECK-O2-NEXT: vse64.v v11, (a0) +; CHECK-O2-NEXT: vse64.v v8, (a0) +; CHECK-O2-NEXT: vse64.v v9, (a0) ; CHECK-O2-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -134,38 +134,38 @@ define void @test_vp_logical_2(* %a0, * %a1, ; CHECK-O0-NEXT: slli a1, a1, 32 ; CHECK-O0-NEXT: srli a1, a1, 32 ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vle32.v v25, (a3) -; CHECK-O0-NEXT: vle32.v v26, (a2) +; CHECK-O0-NEXT: vle32.v v8, (a3) +; CHECK-O0-NEXT: vle32.v v9, (a2) ; CHECK-O0-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-O0-NEXT: vand.vi v25, v25, 1 -; CHECK-O0-NEXT: vmsne.vi v25, v25, 0 -; CHECK-O0-NEXT: vand.vi v26, v26, 1 -; CHECK-O0-NEXT: vmsne.vi v26, v26, 0 +; CHECK-O0-NEXT: vand.vi v8, v8, 1 +; CHECK-O0-NEXT: vmsne.vi v8, v8, 0 +; CHECK-O0-NEXT: vand.vi v9, v9, 1 +; CHECK-O0-NEXT: vmsne.vi v9, v9, 0 ; CHECK-O0-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-O0-NEXT: vmand.mm v0, v25, v26 -; CHECK-O0-NEXT: vmor.mm v27, v25, v26 +; CHECK-O0-NEXT: vmand.mm v0, v8, v9 +; CHECK-O0-NEXT: vmor.mm v10, v8, v9 ; CHECK-O0-NEXT: addi a2, sp, 32 -; CHECK-O0-NEXT: vs1r.v v27, (a2) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vmxor.mm v25, v25, v26 +; CHECK-O0-NEXT: vs1r.v v10, (a2) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 32 -; CHECK-O0-NEXT: vs1r.v v25, (a2) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vs1r.v v8, (a2) # Unknown-size Folded Spill ; CHECK-O0-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-O0-NEXT: vmv.v.i v25, 0 -; CHECK-O0-NEXT: vmerge.vim v27, v25, 1, v0 +; CHECK-O0-NEXT: vmv.v.i v8, 0 +; CHECK-O0-NEXT: vmerge.vim v10, v8, 1, v0 ; CHECK-O0-NEXT: addi a2, sp, 32 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v26, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v9, v8, 1, v0 ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 32 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vse32.v v27, (a0) -; CHECK-O0-NEXT: vse32.v v26, (a0) -; CHECK-O0-NEXT: vse32.v v25, (a0) +; CHECK-O0-NEXT: vse32.v v10, (a0) +; CHECK-O0-NEXT: vse32.v v9, (a0) +; CHECK-O0-NEXT: vse32.v v8, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add sp, sp, a0 @@ -178,29 +178,29 @@ define void @test_vp_logical_2(* %a0, * %a1, ; CHECK-O2-NEXT: slli a2, a2, 32 ; CHECK-O2-NEXT: srli a2, a2, 32 ; CHECK-O2-NEXT: vsetvli zero, a2, e32, m1, ta, mu -; CHECK-O2-NEXT: vle32.v v25, (a0) +; CHECK-O2-NEXT: vle32.v v8, (a0) ; CHECK-O2-NEXT: addi a0, a3, %lo(scratch) -; CHECK-O2-NEXT: vle32.v v26, (a1) +; CHECK-O2-NEXT: vle32.v v9, (a1) ; CHECK-O2-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-O2-NEXT: vand.vi v25, v25, 1 -; CHECK-O2-NEXT: vmsne.vi v27, v25, 0 -; CHECK-O2-NEXT: vand.vi v25, v26, 1 -; CHECK-O2-NEXT: vmsne.vi v26, v25, 0 +; CHECK-O2-NEXT: vand.vi v8, v8, 1 +; CHECK-O2-NEXT: vmsne.vi v10, v8, 0 +; CHECK-O2-NEXT: vand.vi v8, v9, 1 +; CHECK-O2-NEXT: vmsne.vi v9, v8, 0 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, mf4, ta, mu -; CHECK-O2-NEXT: vmand.mm v0, v27, v26 -; CHECK-O2-NEXT: vmor.mm v25, v27, v26 -; CHECK-O2-NEXT: vmxor.mm v26, v27, v26 +; CHECK-O2-NEXT: vmand.mm v0, v10, v9 +; CHECK-O2-NEXT: vmor.mm v8, v10, v9 +; CHECK-O2-NEXT: vmxor.mm v9, v10, v9 ; CHECK-O2-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-O2-NEXT: vmv.v.i v27, 0 -; CHECK-O2-NEXT: vmerge.vim v28, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v25 -; CHECK-O2-NEXT: vmerge.vim v25, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v26 -; CHECK-O2-NEXT: vmerge.vim v26, v27, 1, v0 +; CHECK-O2-NEXT: vmv.v.i v10, 0 +; CHECK-O2-NEXT: vmerge.vim v11, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v8 +; CHECK-O2-NEXT: vmerge.vim v8, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v9 +; CHECK-O2-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-O2-NEXT: vsetvli zero, a2, e32, m1, ta, mu -; CHECK-O2-NEXT: vse32.v v28, (a0) -; CHECK-O2-NEXT: vse32.v v25, (a0) -; CHECK-O2-NEXT: vse32.v v26, (a0) +; CHECK-O2-NEXT: vse32.v v11, (a0) +; CHECK-O2-NEXT: vse32.v v8, (a0) +; CHECK-O2-NEXT: vse32.v v9, (a0) ; CHECK-O2-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -245,38 +245,38 @@ define void @test_vp_logical_3(* %a0, * %a1, ; CHECK-O0-NEXT: slli a1, a1, 32 ; CHECK-O0-NEXT: srli a1, a1, 32 ; CHECK-O0-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-O0-NEXT: vle16.v v25, (a3) -; CHECK-O0-NEXT: vle16.v v26, (a2) +; CHECK-O0-NEXT: vle16.v v8, (a3) +; CHECK-O0-NEXT: vle16.v v9, (a2) ; CHECK-O0-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-O0-NEXT: vand.vi v25, v25, 1 -; CHECK-O0-NEXT: vmsne.vi v25, v25, 0 -; CHECK-O0-NEXT: vand.vi v26, v26, 1 -; CHECK-O0-NEXT: vmsne.vi v26, v26, 0 +; CHECK-O0-NEXT: vand.vi v8, v8, 1 +; CHECK-O0-NEXT: vmsne.vi v8, v8, 0 +; CHECK-O0-NEXT: vand.vi v9, v9, 1 +; CHECK-O0-NEXT: vmsne.vi v9, v9, 0 ; CHECK-O0-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-O0-NEXT: vmand.mm v0, v25, v26 -; CHECK-O0-NEXT: vmor.mm v27, v25, v26 +; CHECK-O0-NEXT: vmand.mm v0, v8, v9 +; CHECK-O0-NEXT: vmor.mm v10, v8, v9 ; CHECK-O0-NEXT: addi a2, sp, 32 -; CHECK-O0-NEXT: vs1r.v v27, (a2) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vmxor.mm v25, v25, v26 +; CHECK-O0-NEXT: vs1r.v v10, (a2) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 32 -; CHECK-O0-NEXT: vs1r.v v25, (a2) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vs1r.v v8, (a2) # Unknown-size Folded Spill ; CHECK-O0-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-O0-NEXT: vmv.v.i v25, 0 -; CHECK-O0-NEXT: vmerge.vim v27, v25, 1, v0 +; CHECK-O0-NEXT: vmv.v.i v8, 0 +; CHECK-O0-NEXT: vmerge.vim v10, v8, 1, v0 ; CHECK-O0-NEXT: addi a2, sp, 32 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v26, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v9, v8, 1, v0 ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 32 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-O0-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-O0-NEXT: vse16.v v27, (a0) -; CHECK-O0-NEXT: vse16.v v26, (a0) -; CHECK-O0-NEXT: vse16.v v25, (a0) +; CHECK-O0-NEXT: vse16.v v10, (a0) +; CHECK-O0-NEXT: vse16.v v9, (a0) +; CHECK-O0-NEXT: vse16.v v8, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add sp, sp, a0 @@ -289,29 +289,29 @@ define void @test_vp_logical_3(* %a0, * %a1, ; CHECK-O2-NEXT: slli a2, a2, 32 ; CHECK-O2-NEXT: srli a2, a2, 32 ; CHECK-O2-NEXT: vsetvli zero, a2, e16, m1, ta, mu -; CHECK-O2-NEXT: vle16.v v25, (a0) +; CHECK-O2-NEXT: vle16.v v8, (a0) ; CHECK-O2-NEXT: addi a0, a3, %lo(scratch) -; CHECK-O2-NEXT: vle16.v v26, (a1) +; CHECK-O2-NEXT: vle16.v v9, (a1) ; CHECK-O2-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-O2-NEXT: vand.vi v25, v25, 1 -; CHECK-O2-NEXT: vmsne.vi v27, v25, 0 -; CHECK-O2-NEXT: vand.vi v25, v26, 1 -; CHECK-O2-NEXT: vmsne.vi v26, v25, 0 +; CHECK-O2-NEXT: vand.vi v8, v8, 1 +; CHECK-O2-NEXT: vmsne.vi v10, v8, 0 +; CHECK-O2-NEXT: vand.vi v8, v9, 1 +; CHECK-O2-NEXT: vmsne.vi v9, v8, 0 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, mf2, ta, mu -; CHECK-O2-NEXT: vmand.mm v0, v27, v26 -; CHECK-O2-NEXT: vmor.mm v25, v27, v26 -; CHECK-O2-NEXT: vmxor.mm v26, v27, v26 +; CHECK-O2-NEXT: vmand.mm v0, v10, v9 +; CHECK-O2-NEXT: vmor.mm v8, v10, v9 +; CHECK-O2-NEXT: vmxor.mm v9, v10, v9 ; CHECK-O2-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-O2-NEXT: vmv.v.i v27, 0 -; CHECK-O2-NEXT: vmerge.vim v28, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v25 -; CHECK-O2-NEXT: vmerge.vim v25, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v26 -; CHECK-O2-NEXT: vmerge.vim v26, v27, 1, v0 +; CHECK-O2-NEXT: vmv.v.i v10, 0 +; CHECK-O2-NEXT: vmerge.vim v11, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v8 +; CHECK-O2-NEXT: vmerge.vim v8, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v9 +; CHECK-O2-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-O2-NEXT: vsetvli zero, a2, e16, m1, ta, mu -; CHECK-O2-NEXT: vse16.v v28, (a0) -; CHECK-O2-NEXT: vse16.v v25, (a0) -; CHECK-O2-NEXT: vse16.v v26, (a0) +; CHECK-O2-NEXT: vse16.v v11, (a0) +; CHECK-O2-NEXT: vse16.v v8, (a0) +; CHECK-O2-NEXT: vse16.v v9, (a0) ; CHECK-O2-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -356,38 +356,38 @@ define void @test_vp_logical_4(* %a0, * %a1, i ; CHECK-O0-NEXT: slli a1, a1, 32 ; CHECK-O0-NEXT: srli a1, a1, 32 ; CHECK-O0-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-O0-NEXT: vle8.v v25, (a3) -; CHECK-O0-NEXT: vle8.v v26, (a2) +; CHECK-O0-NEXT: vle8.v v8, (a3) +; CHECK-O0-NEXT: vle8.v v9, (a2) ; CHECK-O0-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-O0-NEXT: vand.vi v25, v25, 1 -; CHECK-O0-NEXT: vmsne.vi v25, v25, 0 -; CHECK-O0-NEXT: vand.vi v26, v26, 1 -; CHECK-O0-NEXT: vmsne.vi v26, v26, 0 +; CHECK-O0-NEXT: vand.vi v8, v8, 1 +; CHECK-O0-NEXT: vmsne.vi v8, v8, 0 +; CHECK-O0-NEXT: vand.vi v9, v9, 1 +; CHECK-O0-NEXT: vmsne.vi v9, v9, 0 ; CHECK-O0-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-O0-NEXT: vmand.mm v0, v25, v26 -; CHECK-O0-NEXT: vmor.mm v27, v25, v26 +; CHECK-O0-NEXT: vmand.mm v0, v8, v9 +; CHECK-O0-NEXT: vmor.mm v10, v8, v9 ; CHECK-O0-NEXT: addi a2, sp, 32 -; CHECK-O0-NEXT: vs1r.v v27, (a2) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vmxor.mm v25, v25, v26 +; CHECK-O0-NEXT: vs1r.v v10, (a2) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 32 -; CHECK-O0-NEXT: vs1r.v v25, (a2) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vs1r.v v8, (a2) # Unknown-size Folded Spill ; CHECK-O0-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-O0-NEXT: vmv.v.i v25, 0 -; CHECK-O0-NEXT: vmerge.vim v27, v25, 1, v0 +; CHECK-O0-NEXT: vmv.v.i v8, 0 +; CHECK-O0-NEXT: vmerge.vim v10, v8, 1, v0 ; CHECK-O0-NEXT: addi a2, sp, 32 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v26, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v9, v8, 1, v0 ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 32 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-O0-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-O0-NEXT: vse8.v v27, (a0) -; CHECK-O0-NEXT: vse8.v v26, (a0) -; CHECK-O0-NEXT: vse8.v v25, (a0) +; CHECK-O0-NEXT: vse8.v v10, (a0) +; CHECK-O0-NEXT: vse8.v v9, (a0) +; CHECK-O0-NEXT: vse8.v v8, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add sp, sp, a0 @@ -400,29 +400,29 @@ define void @test_vp_logical_4(* %a0, * %a1, i ; CHECK-O2-NEXT: slli a2, a2, 32 ; CHECK-O2-NEXT: srli a2, a2, 32 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m1, ta, mu -; CHECK-O2-NEXT: vle8.v v25, (a0) +; CHECK-O2-NEXT: vle8.v v8, (a0) ; CHECK-O2-NEXT: addi a0, a3, %lo(scratch) -; CHECK-O2-NEXT: vle8.v v26, (a1) +; CHECK-O2-NEXT: vle8.v v9, (a1) ; CHECK-O2-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-O2-NEXT: vand.vi v25, v25, 1 -; CHECK-O2-NEXT: vmsne.vi v27, v25, 0 -; CHECK-O2-NEXT: vand.vi v25, v26, 1 -; CHECK-O2-NEXT: vmsne.vi v26, v25, 0 +; CHECK-O2-NEXT: vand.vi v8, v8, 1 +; CHECK-O2-NEXT: vmsne.vi v10, v8, 0 +; CHECK-O2-NEXT: vand.vi v8, v9, 1 +; CHECK-O2-NEXT: vmsne.vi v9, v8, 0 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m1, ta, mu -; CHECK-O2-NEXT: vmand.mm v0, v27, v26 -; CHECK-O2-NEXT: vmor.mm v25, v27, v26 -; CHECK-O2-NEXT: vmxor.mm v26, v27, v26 +; CHECK-O2-NEXT: vmand.mm v0, v10, v9 +; CHECK-O2-NEXT: vmor.mm v8, v10, v9 +; CHECK-O2-NEXT: vmxor.mm v9, v10, v9 ; CHECK-O2-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-O2-NEXT: vmv.v.i v27, 0 -; CHECK-O2-NEXT: vmerge.vim v28, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v25 -; CHECK-O2-NEXT: vmerge.vim v25, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v26 -; CHECK-O2-NEXT: vmerge.vim v26, v27, 1, v0 +; CHECK-O2-NEXT: vmv.v.i v10, 0 +; CHECK-O2-NEXT: vmerge.vim v11, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v8 +; CHECK-O2-NEXT: vmerge.vim v8, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v9 +; CHECK-O2-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m1, ta, mu -; CHECK-O2-NEXT: vse8.v v28, (a0) -; CHECK-O2-NEXT: vse8.v v25, (a0) -; CHECK-O2-NEXT: vse8.v v26, (a0) +; CHECK-O2-NEXT: vse8.v v11, (a0) +; CHECK-O2-NEXT: vse8.v v8, (a0) +; CHECK-O2-NEXT: vse8.v v9, (a0) ; CHECK-O2-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -467,38 +467,38 @@ define void @test_vp_logical_5(* %a0, * %a1, ; CHECK-O0-NEXT: slli a1, a1, 32 ; CHECK-O0-NEXT: srli a1, a1, 32 ; CHECK-O0-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-O0-NEXT: vle8.v v28, (a3) -; CHECK-O0-NEXT: vle8.v v26, (a2) +; CHECK-O0-NEXT: vle8.v v8, (a3) +; CHECK-O0-NEXT: vle8.v v10, (a2) ; CHECK-O0-NEXT: vsetvli a2, zero, e8, m2, ta, mu -; CHECK-O0-NEXT: vand.vi v28, v28, 1 -; CHECK-O0-NEXT: vmsne.vi v25, v28, 0 -; CHECK-O0-NEXT: vand.vi v28, v26, 1 -; CHECK-O0-NEXT: vmsne.vi v26, v28, 0 +; CHECK-O0-NEXT: vand.vi v12, v8, 1 +; CHECK-O0-NEXT: vmsne.vi v8, v12, 0 +; CHECK-O0-NEXT: vand.vi v10, v10, 1 +; CHECK-O0-NEXT: vmsne.vi v9, v10, 0 ; CHECK-O0-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-O0-NEXT: vmand.mm v0, v25, v26 -; CHECK-O0-NEXT: vmor.mm v27, v25, v26 +; CHECK-O0-NEXT: vmand.mm v0, v8, v9 +; CHECK-O0-NEXT: vmor.mm v10, v8, v9 ; CHECK-O0-NEXT: addi a2, sp, 32 -; CHECK-O0-NEXT: vs1r.v v27, (a2) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vmxor.mm v25, v25, v26 +; CHECK-O0-NEXT: vs1r.v v10, (a2) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 32 -; CHECK-O0-NEXT: vs1r.v v25, (a2) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vs1r.v v8, (a2) # Unknown-size Folded Spill ; CHECK-O0-NEXT: vsetvli a2, zero, e8, m2, ta, mu -; CHECK-O0-NEXT: vmv.v.i v26, 0 -; CHECK-O0-NEXT: vmerge.vim v30, v26, 1, v0 +; CHECK-O0-NEXT: vmv.v.i v8, 0 +; CHECK-O0-NEXT: vmerge.vim v12, v8, 1, v0 ; CHECK-O0-NEXT: addi a2, sp, 32 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v28, v26, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v10, v8, 1, v0 ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 32 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-O0-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-O0-NEXT: vse8.v v30, (a0) -; CHECK-O0-NEXT: vse8.v v28, (a0) -; CHECK-O0-NEXT: vse8.v v26, (a0) +; CHECK-O0-NEXT: vse8.v v12, (a0) +; CHECK-O0-NEXT: vse8.v v10, (a0) +; CHECK-O0-NEXT: vse8.v v8, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add sp, sp, a0 @@ -511,29 +511,29 @@ define void @test_vp_logical_5(* %a0, * %a1, ; CHECK-O2-NEXT: slli a2, a2, 32 ; CHECK-O2-NEXT: srli a2, a2, 32 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-O2-NEXT: vle8.v v26, (a0) +; CHECK-O2-NEXT: vle8.v v8, (a0) ; CHECK-O2-NEXT: addi a0, a3, %lo(scratch) -; CHECK-O2-NEXT: vle8.v v28, (a1) +; CHECK-O2-NEXT: vle8.v v10, (a1) ; CHECK-O2-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-O2-NEXT: vand.vi v26, v26, 1 -; CHECK-O2-NEXT: vmsne.vi v30, v26, 0 -; CHECK-O2-NEXT: vand.vi v26, v28, 1 -; CHECK-O2-NEXT: vmsne.vi v28, v26, 0 +; CHECK-O2-NEXT: vand.vi v8, v8, 1 +; CHECK-O2-NEXT: vmsne.vi v12, v8, 0 +; CHECK-O2-NEXT: vand.vi v8, v10, 1 +; CHECK-O2-NEXT: vmsne.vi v10, v8, 0 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-O2-NEXT: vmand.mm v0, v30, v28 -; CHECK-O2-NEXT: vmor.mm v25, v30, v28 -; CHECK-O2-NEXT: vmxor.mm v26, v30, v28 +; CHECK-O2-NEXT: vmand.mm v0, v12, v10 +; CHECK-O2-NEXT: vmor.mm v8, v12, v10 +; CHECK-O2-NEXT: vmxor.mm v9, v12, v10 ; CHECK-O2-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-O2-NEXT: vmv.v.i v28, 0 -; CHECK-O2-NEXT: vmerge.vim v30, v28, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v25 -; CHECK-O2-NEXT: vmerge.vim v8, v28, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v26 -; CHECK-O2-NEXT: vmerge.vim v26, v28, 1, v0 +; CHECK-O2-NEXT: vmv.v.i v10, 0 +; CHECK-O2-NEXT: vmerge.vim v12, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v8 +; CHECK-O2-NEXT: vmerge.vim v14, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v9 +; CHECK-O2-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-O2-NEXT: vse8.v v30, (a0) +; CHECK-O2-NEXT: vse8.v v12, (a0) +; CHECK-O2-NEXT: vse8.v v14, (a0) ; CHECK-O2-NEXT: vse8.v v8, (a0) -; CHECK-O2-NEXT: vse8.v v26, (a0) ; CHECK-O2-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -579,37 +579,37 @@ define void @test_vp_logical_6(* %a0, * %a1, ; CHECK-O0-NEXT: srli a1, a1, 32 ; CHECK-O0-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-O0-NEXT: vle8.v v8, (a3) -; CHECK-O0-NEXT: vle8.v v28, (a2) +; CHECK-O0-NEXT: vle8.v v12, (a2) ; CHECK-O0-NEXT: vsetvli a2, zero, e8, m4, ta, mu -; CHECK-O0-NEXT: vand.vi v8, v8, 1 -; CHECK-O0-NEXT: vmsne.vi v25, v8, 0 -; CHECK-O0-NEXT: vand.vi v28, v28, 1 -; CHECK-O0-NEXT: vmsne.vi v26, v28, 0 +; CHECK-O0-NEXT: vand.vi v16, v8, 1 +; CHECK-O0-NEXT: vmsne.vi v8, v16, 0 +; CHECK-O0-NEXT: vand.vi v12, v12, 1 +; CHECK-O0-NEXT: vmsne.vi v9, v12, 0 ; CHECK-O0-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-O0-NEXT: vmand.mm v0, v25, v26 -; CHECK-O0-NEXT: vmor.mm v27, v25, v26 +; CHECK-O0-NEXT: vmand.mm v0, v8, v9 +; CHECK-O0-NEXT: vmor.mm v10, v8, v9 ; CHECK-O0-NEXT: addi a2, sp, 32 -; CHECK-O0-NEXT: vs1r.v v27, (a2) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vmxor.mm v25, v25, v26 +; CHECK-O0-NEXT: vs1r.v v10, (a2) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 32 -; CHECK-O0-NEXT: vs1r.v v25, (a2) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vs1r.v v8, (a2) # Unknown-size Folded Spill ; CHECK-O0-NEXT: vsetvli a2, zero, e8, m4, ta, mu -; CHECK-O0-NEXT: vmv.v.i v28, 0 -; CHECK-O0-NEXT: vmerge.vim v12, v28, 1, v0 +; CHECK-O0-NEXT: vmv.v.i v8, 0 +; CHECK-O0-NEXT: vmerge.vim v16, v8, 1, v0 ; CHECK-O0-NEXT: addi a2, sp, 32 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v8, v28, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v12, v8, 1, v0 ; CHECK-O0-NEXT: csrr a2, vlenb ; CHECK-O0-NEXT: add a2, sp, a2 ; CHECK-O0-NEXT: addi a2, a2, 32 ; CHECK-O0-NEXT: vl1r.v v0, (a2) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v28, v28, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-O0-NEXT: vsetvli zero, a1, e8, m4, ta, mu +; CHECK-O0-NEXT: vse8.v v16, (a0) ; CHECK-O0-NEXT: vse8.v v12, (a0) ; CHECK-O0-NEXT: vse8.v v8, (a0) -; CHECK-O0-NEXT: vse8.v v28, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add sp, sp, a0 @@ -622,29 +622,29 @@ define void @test_vp_logical_6(* %a0, * %a1, ; CHECK-O2-NEXT: slli a2, a2, 32 ; CHECK-O2-NEXT: srli a2, a2, 32 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-O2-NEXT: vle8.v v28, (a0) +; CHECK-O2-NEXT: vle8.v v8, (a0) ; CHECK-O2-NEXT: addi a0, a3, %lo(scratch) -; CHECK-O2-NEXT: vle8.v v8, (a1) +; CHECK-O2-NEXT: vle8.v v12, (a1) ; CHECK-O2-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-O2-NEXT: vand.vi v28, v28, 1 -; CHECK-O2-NEXT: vmsne.vi v26, v28, 0 -; CHECK-O2-NEXT: vand.vi v28, v8, 1 -; CHECK-O2-NEXT: vmsne.vi v27, v28, 0 +; CHECK-O2-NEXT: vand.vi v8, v8, 1 +; CHECK-O2-NEXT: vmsne.vi v16, v8, 0 +; CHECK-O2-NEXT: vand.vi v8, v12, 1 +; CHECK-O2-NEXT: vmsne.vi v12, v8, 0 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-O2-NEXT: vmand.mm v0, v26, v27 -; CHECK-O2-NEXT: vmor.mm v25, v26, v27 -; CHECK-O2-NEXT: vmxor.mm v26, v26, v27 +; CHECK-O2-NEXT: vmand.mm v0, v16, v12 +; CHECK-O2-NEXT: vmor.mm v8, v16, v12 +; CHECK-O2-NEXT: vmxor.mm v9, v16, v12 ; CHECK-O2-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-O2-NEXT: vmv.v.i v28, 0 -; CHECK-O2-NEXT: vmerge.vim v8, v28, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v25 -; CHECK-O2-NEXT: vmerge.vim v12, v28, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v26 -; CHECK-O2-NEXT: vmerge.vim v28, v28, 1, v0 +; CHECK-O2-NEXT: vmv.v.i v12, 0 +; CHECK-O2-NEXT: vmerge.vim v16, v12, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v8 +; CHECK-O2-NEXT: vmerge.vim v20, v12, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v9 +; CHECK-O2-NEXT: vmerge.vim v8, v12, 1, v0 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m4, ta, mu +; CHECK-O2-NEXT: vse8.v v16, (a0) +; CHECK-O2-NEXT: vse8.v v20, (a0) ; CHECK-O2-NEXT: vse8.v v8, (a0) -; CHECK-O2-NEXT: vse8.v v12, (a0) -; CHECK-O2-NEXT: vse8.v v28, (a0) ; CHECK-O2-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/epi-vp-logical_disable-vpred-sdags.ll b/llvm/test/CodeGen/RISCV/epi-vp-logical_disable-vpred-sdags.ll index ef8e176963d9ef584a1765221ab9fafdfa9875b4..db9e19431201a2825ebf225bbe80ddba546ba550 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-logical_disable-vpred-sdags.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-logical_disable-vpred-sdags.ll @@ -17,41 +17,41 @@ define void @test_vp_logical(* %a0, * %a1, i ; CHECK-O0-NEXT: # kill: def $x10 killed $x12 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O0-NEXT: # implicit-def: $v25 +; CHECK-O0-NEXT: # implicit-def: $v8 ; CHECK-O0-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; CHECK-O0-NEXT: vle64.v v25, (a3) -; CHECK-O0-NEXT: # implicit-def: $v26 -; CHECK-O0-NEXT: vle64.v v26, (a1) +; CHECK-O0-NEXT: vle64.v v8, (a3) +; CHECK-O0-NEXT: # implicit-def: $v9 +; CHECK-O0-NEXT: vle64.v v9, (a1) ; CHECK-O0-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-O0-NEXT: vand.vi v25, v25, 1 -; CHECK-O0-NEXT: vmsne.vi v25, v25, 0 -; CHECK-O0-NEXT: vand.vi v26, v26, 1 -; CHECK-O0-NEXT: vmsne.vi v26, v26, 0 +; CHECK-O0-NEXT: vand.vi v8, v8, 1 +; CHECK-O0-NEXT: vmsne.vi v8, v8, 0 +; CHECK-O0-NEXT: vand.vi v9, v9, 1 +; CHECK-O0-NEXT: vmsne.vi v9, v9, 0 ; CHECK-O0-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; CHECK-O0-NEXT: vmand.mm v0, v25, v26 -; CHECK-O0-NEXT: vmor.mm v27, v25, v26 +; CHECK-O0-NEXT: vmand.mm v0, v8, v9 +; CHECK-O0-NEXT: vmor.mm v10, v8, v9 ; CHECK-O0-NEXT: addi a1, sp, 16 -; CHECK-O0-NEXT: vs1r.v v27, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vmxor.mm v25, v25, v26 +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 16 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-O0-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-O0-NEXT: vmv.v.i v25, 0 -; CHECK-O0-NEXT: vmerge.vim v27, v25, 1, v0 +; CHECK-O0-NEXT: vmv.v.i v8, 0 +; CHECK-O0-NEXT: vmerge.vim v10, v8, 1, v0 ; CHECK-O0-NEXT: addi a1, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v26, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v9, v8, 1, v0 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-O0-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; CHECK-O0-NEXT: vse64.v v27, (a0) -; CHECK-O0-NEXT: vse64.v v26, (a0) -; CHECK-O0-NEXT: vse64.v v25, (a0) +; CHECK-O0-NEXT: vse64.v v10, (a0) +; CHECK-O0-NEXT: vse64.v v9, (a0) +; CHECK-O0-NEXT: vse64.v v8, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add sp, sp, a0 @@ -62,29 +62,29 @@ define void @test_vp_logical(* %a0, * %a1, i ; CHECK-O2: # %bb.0: ; CHECK-O2-NEXT: lui a3, %hi(scratch) ; CHECK-O2-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; CHECK-O2-NEXT: vle64.v v25, (a0) +; CHECK-O2-NEXT: vle64.v v8, (a0) ; CHECK-O2-NEXT: addi a0, a3, %lo(scratch) -; CHECK-O2-NEXT: vle64.v v26, (a1) +; CHECK-O2-NEXT: vle64.v v9, (a1) ; CHECK-O2-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-O2-NEXT: vand.vi v25, v25, 1 -; CHECK-O2-NEXT: vmsne.vi v27, v25, 0 -; CHECK-O2-NEXT: vand.vi v25, v26, 1 -; CHECK-O2-NEXT: vmsne.vi v26, v25, 0 +; CHECK-O2-NEXT: vand.vi v8, v8, 1 +; CHECK-O2-NEXT: vmsne.vi v10, v8, 0 +; CHECK-O2-NEXT: vand.vi v8, v9, 1 +; CHECK-O2-NEXT: vmsne.vi v9, v8, 0 ; CHECK-O2-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; CHECK-O2-NEXT: vmand.mm v0, v27, v26 -; CHECK-O2-NEXT: vmor.mm v25, v27, v26 -; CHECK-O2-NEXT: vmxor.mm v26, v27, v26 +; CHECK-O2-NEXT: vmand.mm v0, v10, v9 +; CHECK-O2-NEXT: vmor.mm v8, v10, v9 +; CHECK-O2-NEXT: vmxor.mm v9, v10, v9 ; CHECK-O2-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-O2-NEXT: vmv.v.i v27, 0 -; CHECK-O2-NEXT: vmerge.vim v28, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v25 -; CHECK-O2-NEXT: vmerge.vim v25, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v26 -; CHECK-O2-NEXT: vmerge.vim v26, v27, 1, v0 +; CHECK-O2-NEXT: vmv.v.i v10, 0 +; CHECK-O2-NEXT: vmerge.vim v11, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v8 +; CHECK-O2-NEXT: vmerge.vim v8, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v9 +; CHECK-O2-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-O2-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; CHECK-O2-NEXT: vse64.v v28, (a0) -; CHECK-O2-NEXT: vse64.v v25, (a0) -; CHECK-O2-NEXT: vse64.v v26, (a0) +; CHECK-O2-NEXT: vse64.v v11, (a0) +; CHECK-O2-NEXT: vse64.v v8, (a0) +; CHECK-O2-NEXT: vse64.v v9, (a0) ; CHECK-O2-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -123,41 +123,41 @@ define void @test_vp_logical_2(* %a0, * %a1, ; CHECK-O0-NEXT: # kill: def $x10 killed $x12 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O0-NEXT: # implicit-def: $v25 +; CHECK-O0-NEXT: # implicit-def: $v8 ; CHECK-O0-NEXT: vsetvli zero, a2, e32, m1, ta, mu -; CHECK-O0-NEXT: vle32.v v25, (a3) -; CHECK-O0-NEXT: # implicit-def: $v26 -; CHECK-O0-NEXT: vle32.v v26, (a1) +; CHECK-O0-NEXT: vle32.v v8, (a3) +; CHECK-O0-NEXT: # implicit-def: $v9 +; CHECK-O0-NEXT: vle32.v v9, (a1) ; CHECK-O0-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-O0-NEXT: vand.vi v25, v25, 1 -; CHECK-O0-NEXT: vmsne.vi v25, v25, 0 -; CHECK-O0-NEXT: vand.vi v26, v26, 1 -; CHECK-O0-NEXT: vmsne.vi v26, v26, 0 +; CHECK-O0-NEXT: vand.vi v8, v8, 1 +; CHECK-O0-NEXT: vmsne.vi v8, v8, 0 +; CHECK-O0-NEXT: vand.vi v9, v9, 1 +; CHECK-O0-NEXT: vmsne.vi v9, v9, 0 ; CHECK-O0-NEXT: vsetvli zero, a2, e32, m1, ta, mu -; CHECK-O0-NEXT: vmand.mm v0, v25, v26 -; CHECK-O0-NEXT: vmor.mm v27, v25, v26 +; CHECK-O0-NEXT: vmand.mm v0, v8, v9 +; CHECK-O0-NEXT: vmor.mm v10, v8, v9 ; CHECK-O0-NEXT: addi a1, sp, 16 -; CHECK-O0-NEXT: vs1r.v v27, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vmxor.mm v25, v25, v26 +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 16 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-O0-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-O0-NEXT: vmv.v.i v25, 0 -; CHECK-O0-NEXT: vmerge.vim v27, v25, 1, v0 +; CHECK-O0-NEXT: vmv.v.i v8, 0 +; CHECK-O0-NEXT: vmerge.vim v10, v8, 1, v0 ; CHECK-O0-NEXT: addi a1, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v26, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v9, v8, 1, v0 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-O0-NEXT: vsetvli zero, a2, e32, m1, ta, mu -; CHECK-O0-NEXT: vse32.v v27, (a0) -; CHECK-O0-NEXT: vse32.v v26, (a0) -; CHECK-O0-NEXT: vse32.v v25, (a0) +; CHECK-O0-NEXT: vse32.v v10, (a0) +; CHECK-O0-NEXT: vse32.v v9, (a0) +; CHECK-O0-NEXT: vse32.v v8, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add sp, sp, a0 @@ -168,29 +168,29 @@ define void @test_vp_logical_2(* %a0, * %a1, ; CHECK-O2: # %bb.0: ; CHECK-O2-NEXT: lui a3, %hi(scratch) ; CHECK-O2-NEXT: vsetvli zero, a2, e32, m1, ta, mu -; CHECK-O2-NEXT: vle32.v v25, (a0) +; CHECK-O2-NEXT: vle32.v v8, (a0) ; CHECK-O2-NEXT: addi a0, a3, %lo(scratch) -; CHECK-O2-NEXT: vle32.v v26, (a1) +; CHECK-O2-NEXT: vle32.v v9, (a1) ; CHECK-O2-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-O2-NEXT: vand.vi v25, v25, 1 -; CHECK-O2-NEXT: vmsne.vi v27, v25, 0 -; CHECK-O2-NEXT: vand.vi v25, v26, 1 -; CHECK-O2-NEXT: vmsne.vi v26, v25, 0 +; CHECK-O2-NEXT: vand.vi v8, v8, 1 +; CHECK-O2-NEXT: vmsne.vi v10, v8, 0 +; CHECK-O2-NEXT: vand.vi v8, v9, 1 +; CHECK-O2-NEXT: vmsne.vi v9, v8, 0 ; CHECK-O2-NEXT: vsetvli zero, a2, e32, m1, ta, mu -; CHECK-O2-NEXT: vmand.mm v0, v27, v26 -; CHECK-O2-NEXT: vmor.mm v25, v27, v26 -; CHECK-O2-NEXT: vmxor.mm v26, v27, v26 +; CHECK-O2-NEXT: vmand.mm v0, v10, v9 +; CHECK-O2-NEXT: vmor.mm v8, v10, v9 +; CHECK-O2-NEXT: vmxor.mm v9, v10, v9 ; CHECK-O2-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-O2-NEXT: vmv.v.i v27, 0 -; CHECK-O2-NEXT: vmerge.vim v28, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v25 -; CHECK-O2-NEXT: vmerge.vim v25, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v26 -; CHECK-O2-NEXT: vmerge.vim v26, v27, 1, v0 +; CHECK-O2-NEXT: vmv.v.i v10, 0 +; CHECK-O2-NEXT: vmerge.vim v11, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v8 +; CHECK-O2-NEXT: vmerge.vim v8, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v9 +; CHECK-O2-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-O2-NEXT: vsetvli zero, a2, e32, m1, ta, mu -; CHECK-O2-NEXT: vse32.v v28, (a0) -; CHECK-O2-NEXT: vse32.v v25, (a0) -; CHECK-O2-NEXT: vse32.v v26, (a0) +; CHECK-O2-NEXT: vse32.v v11, (a0) +; CHECK-O2-NEXT: vse32.v v8, (a0) +; CHECK-O2-NEXT: vse32.v v9, (a0) ; CHECK-O2-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -229,41 +229,41 @@ define void @test_vp_logical_3(* %a0, * %a1, ; CHECK-O0-NEXT: # kill: def $x10 killed $x12 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O0-NEXT: # implicit-def: $v25 +; CHECK-O0-NEXT: # implicit-def: $v8 ; CHECK-O0-NEXT: vsetvli zero, a2, e16, m1, ta, mu -; CHECK-O0-NEXT: vle16.v v25, (a3) -; CHECK-O0-NEXT: # implicit-def: $v26 -; CHECK-O0-NEXT: vle16.v v26, (a1) +; CHECK-O0-NEXT: vle16.v v8, (a3) +; CHECK-O0-NEXT: # implicit-def: $v9 +; CHECK-O0-NEXT: vle16.v v9, (a1) ; CHECK-O0-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-O0-NEXT: vand.vi v25, v25, 1 -; CHECK-O0-NEXT: vmsne.vi v25, v25, 0 -; CHECK-O0-NEXT: vand.vi v26, v26, 1 -; CHECK-O0-NEXT: vmsne.vi v26, v26, 0 +; CHECK-O0-NEXT: vand.vi v8, v8, 1 +; CHECK-O0-NEXT: vmsne.vi v8, v8, 0 +; CHECK-O0-NEXT: vand.vi v9, v9, 1 +; CHECK-O0-NEXT: vmsne.vi v9, v9, 0 ; CHECK-O0-NEXT: vsetvli zero, a2, e16, m1, ta, mu -; CHECK-O0-NEXT: vmand.mm v0, v25, v26 -; CHECK-O0-NEXT: vmor.mm v27, v25, v26 +; CHECK-O0-NEXT: vmand.mm v0, v8, v9 +; CHECK-O0-NEXT: vmor.mm v10, v8, v9 ; CHECK-O0-NEXT: addi a1, sp, 16 -; CHECK-O0-NEXT: vs1r.v v27, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vmxor.mm v25, v25, v26 +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 16 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-O0-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-O0-NEXT: vmv.v.i v25, 0 -; CHECK-O0-NEXT: vmerge.vim v27, v25, 1, v0 +; CHECK-O0-NEXT: vmv.v.i v8, 0 +; CHECK-O0-NEXT: vmerge.vim v10, v8, 1, v0 ; CHECK-O0-NEXT: addi a1, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v26, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v9, v8, 1, v0 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-O0-NEXT: vsetvli zero, a2, e16, m1, ta, mu -; CHECK-O0-NEXT: vse16.v v27, (a0) -; CHECK-O0-NEXT: vse16.v v26, (a0) -; CHECK-O0-NEXT: vse16.v v25, (a0) +; CHECK-O0-NEXT: vse16.v v10, (a0) +; CHECK-O0-NEXT: vse16.v v9, (a0) +; CHECK-O0-NEXT: vse16.v v8, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add sp, sp, a0 @@ -274,29 +274,29 @@ define void @test_vp_logical_3(* %a0, * %a1, ; CHECK-O2: # %bb.0: ; CHECK-O2-NEXT: lui a3, %hi(scratch) ; CHECK-O2-NEXT: vsetvli zero, a2, e16, m1, ta, mu -; CHECK-O2-NEXT: vle16.v v25, (a0) +; CHECK-O2-NEXT: vle16.v v8, (a0) ; CHECK-O2-NEXT: addi a0, a3, %lo(scratch) -; CHECK-O2-NEXT: vle16.v v26, (a1) +; CHECK-O2-NEXT: vle16.v v9, (a1) ; CHECK-O2-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-O2-NEXT: vand.vi v25, v25, 1 -; CHECK-O2-NEXT: vmsne.vi v27, v25, 0 -; CHECK-O2-NEXT: vand.vi v25, v26, 1 -; CHECK-O2-NEXT: vmsne.vi v26, v25, 0 +; CHECK-O2-NEXT: vand.vi v8, v8, 1 +; CHECK-O2-NEXT: vmsne.vi v10, v8, 0 +; CHECK-O2-NEXT: vand.vi v8, v9, 1 +; CHECK-O2-NEXT: vmsne.vi v9, v8, 0 ; CHECK-O2-NEXT: vsetvli zero, a2, e16, m1, ta, mu -; CHECK-O2-NEXT: vmand.mm v0, v27, v26 -; CHECK-O2-NEXT: vmor.mm v25, v27, v26 -; CHECK-O2-NEXT: vmxor.mm v26, v27, v26 +; CHECK-O2-NEXT: vmand.mm v0, v10, v9 +; CHECK-O2-NEXT: vmor.mm v8, v10, v9 +; CHECK-O2-NEXT: vmxor.mm v9, v10, v9 ; CHECK-O2-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-O2-NEXT: vmv.v.i v27, 0 -; CHECK-O2-NEXT: vmerge.vim v28, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v25 -; CHECK-O2-NEXT: vmerge.vim v25, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v26 -; CHECK-O2-NEXT: vmerge.vim v26, v27, 1, v0 +; CHECK-O2-NEXT: vmv.v.i v10, 0 +; CHECK-O2-NEXT: vmerge.vim v11, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v8 +; CHECK-O2-NEXT: vmerge.vim v8, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v9 +; CHECK-O2-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-O2-NEXT: vsetvli zero, a2, e16, m1, ta, mu -; CHECK-O2-NEXT: vse16.v v28, (a0) -; CHECK-O2-NEXT: vse16.v v25, (a0) -; CHECK-O2-NEXT: vse16.v v26, (a0) +; CHECK-O2-NEXT: vse16.v v11, (a0) +; CHECK-O2-NEXT: vse16.v v8, (a0) +; CHECK-O2-NEXT: vse16.v v9, (a0) ; CHECK-O2-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -335,41 +335,41 @@ define void @test_vp_logical_4(* %a0, * %a1, i ; CHECK-O0-NEXT: # kill: def $x10 killed $x12 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O0-NEXT: # implicit-def: $v25 +; CHECK-O0-NEXT: # implicit-def: $v8 ; CHECK-O0-NEXT: vsetvli zero, a2, e8, m1, ta, mu -; CHECK-O0-NEXT: vle8.v v25, (a3) -; CHECK-O0-NEXT: # implicit-def: $v26 -; CHECK-O0-NEXT: vle8.v v26, (a1) +; CHECK-O0-NEXT: vle8.v v8, (a3) +; CHECK-O0-NEXT: # implicit-def: $v9 +; CHECK-O0-NEXT: vle8.v v9, (a1) ; CHECK-O0-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-O0-NEXT: vand.vi v25, v25, 1 -; CHECK-O0-NEXT: vmsne.vi v25, v25, 0 -; CHECK-O0-NEXT: vand.vi v26, v26, 1 -; CHECK-O0-NEXT: vmsne.vi v26, v26, 0 +; CHECK-O0-NEXT: vand.vi v8, v8, 1 +; CHECK-O0-NEXT: vmsne.vi v8, v8, 0 +; CHECK-O0-NEXT: vand.vi v9, v9, 1 +; CHECK-O0-NEXT: vmsne.vi v9, v9, 0 ; CHECK-O0-NEXT: vsetvli zero, a2, e8, m1, ta, mu -; CHECK-O0-NEXT: vmand.mm v0, v25, v26 -; CHECK-O0-NEXT: vmor.mm v27, v25, v26 +; CHECK-O0-NEXT: vmand.mm v0, v8, v9 +; CHECK-O0-NEXT: vmor.mm v10, v8, v9 ; CHECK-O0-NEXT: addi a1, sp, 16 -; CHECK-O0-NEXT: vs1r.v v27, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vmxor.mm v25, v25, v26 +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 16 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-O0-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-O0-NEXT: vmv.v.i v25, 0 -; CHECK-O0-NEXT: vmerge.vim v27, v25, 1, v0 +; CHECK-O0-NEXT: vmv.v.i v8, 0 +; CHECK-O0-NEXT: vmerge.vim v10, v8, 1, v0 ; CHECK-O0-NEXT: addi a1, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v26, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v9, v8, 1, v0 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-O0-NEXT: vsetvli zero, a2, e8, m1, ta, mu -; CHECK-O0-NEXT: vse8.v v27, (a0) -; CHECK-O0-NEXT: vse8.v v26, (a0) -; CHECK-O0-NEXT: vse8.v v25, (a0) +; CHECK-O0-NEXT: vse8.v v10, (a0) +; CHECK-O0-NEXT: vse8.v v9, (a0) +; CHECK-O0-NEXT: vse8.v v8, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add sp, sp, a0 @@ -380,29 +380,29 @@ define void @test_vp_logical_4(* %a0, * %a1, i ; CHECK-O2: # %bb.0: ; CHECK-O2-NEXT: lui a3, %hi(scratch) ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m1, ta, mu -; CHECK-O2-NEXT: vle8.v v25, (a0) +; CHECK-O2-NEXT: vle8.v v8, (a0) ; CHECK-O2-NEXT: addi a0, a3, %lo(scratch) -; CHECK-O2-NEXT: vle8.v v26, (a1) +; CHECK-O2-NEXT: vle8.v v9, (a1) ; CHECK-O2-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-O2-NEXT: vand.vi v25, v25, 1 -; CHECK-O2-NEXT: vmsne.vi v27, v25, 0 -; CHECK-O2-NEXT: vand.vi v25, v26, 1 -; CHECK-O2-NEXT: vmsne.vi v26, v25, 0 +; CHECK-O2-NEXT: vand.vi v8, v8, 1 +; CHECK-O2-NEXT: vmsne.vi v10, v8, 0 +; CHECK-O2-NEXT: vand.vi v8, v9, 1 +; CHECK-O2-NEXT: vmsne.vi v9, v8, 0 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m1, ta, mu -; CHECK-O2-NEXT: vmand.mm v0, v27, v26 -; CHECK-O2-NEXT: vmor.mm v25, v27, v26 -; CHECK-O2-NEXT: vmxor.mm v26, v27, v26 +; CHECK-O2-NEXT: vmand.mm v0, v10, v9 +; CHECK-O2-NEXT: vmor.mm v8, v10, v9 +; CHECK-O2-NEXT: vmxor.mm v9, v10, v9 ; CHECK-O2-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-O2-NEXT: vmv.v.i v27, 0 -; CHECK-O2-NEXT: vmerge.vim v28, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v25 -; CHECK-O2-NEXT: vmerge.vim v25, v27, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v26 -; CHECK-O2-NEXT: vmerge.vim v26, v27, 1, v0 +; CHECK-O2-NEXT: vmv.v.i v10, 0 +; CHECK-O2-NEXT: vmerge.vim v11, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v8 +; CHECK-O2-NEXT: vmerge.vim v8, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v9 +; CHECK-O2-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m1, ta, mu -; CHECK-O2-NEXT: vse8.v v28, (a0) -; CHECK-O2-NEXT: vse8.v v25, (a0) -; CHECK-O2-NEXT: vse8.v v26, (a0) +; CHECK-O2-NEXT: vse8.v v11, (a0) +; CHECK-O2-NEXT: vse8.v v8, (a0) +; CHECK-O2-NEXT: vse8.v v9, (a0) ; CHECK-O2-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -441,41 +441,41 @@ define void @test_vp_logical_5(* %a0, * %a1, ; CHECK-O0-NEXT: # kill: def $x10 killed $x12 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O0-NEXT: # implicit-def: $v28m2 +; CHECK-O0-NEXT: # implicit-def: $v8m2 ; CHECK-O0-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-O0-NEXT: vle8.v v28, (a3) -; CHECK-O0-NEXT: # implicit-def: $v26m2 -; CHECK-O0-NEXT: vle8.v v26, (a1) +; CHECK-O0-NEXT: vle8.v v8, (a3) +; CHECK-O0-NEXT: # implicit-def: $v10m2 +; CHECK-O0-NEXT: vle8.v v10, (a1) ; CHECK-O0-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-O0-NEXT: vand.vi v28, v28, 1 -; CHECK-O0-NEXT: vmsne.vi v25, v28, 0 -; CHECK-O0-NEXT: vand.vi v28, v26, 1 -; CHECK-O0-NEXT: vmsne.vi v26, v28, 0 +; CHECK-O0-NEXT: vand.vi v12, v8, 1 +; CHECK-O0-NEXT: vmsne.vi v8, v12, 0 +; CHECK-O0-NEXT: vand.vi v10, v10, 1 +; CHECK-O0-NEXT: vmsne.vi v9, v10, 0 ; CHECK-O0-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-O0-NEXT: vmand.mm v0, v25, v26 -; CHECK-O0-NEXT: vmor.mm v27, v25, v26 +; CHECK-O0-NEXT: vmand.mm v0, v8, v9 +; CHECK-O0-NEXT: vmor.mm v10, v8, v9 ; CHECK-O0-NEXT: addi a1, sp, 16 -; CHECK-O0-NEXT: vs1r.v v27, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vmxor.mm v25, v25, v26 +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 16 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-O0-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-O0-NEXT: vmv.v.i v26, 0 -; CHECK-O0-NEXT: vmerge.vim v30, v26, 1, v0 +; CHECK-O0-NEXT: vmv.v.i v8, 0 +; CHECK-O0-NEXT: vmerge.vim v12, v8, 1, v0 ; CHECK-O0-NEXT: addi a1, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v28, v26, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v10, v8, 1, v0 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-O0-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-O0-NEXT: vse8.v v30, (a0) -; CHECK-O0-NEXT: vse8.v v28, (a0) -; CHECK-O0-NEXT: vse8.v v26, (a0) +; CHECK-O0-NEXT: vse8.v v12, (a0) +; CHECK-O0-NEXT: vse8.v v10, (a0) +; CHECK-O0-NEXT: vse8.v v8, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add sp, sp, a0 @@ -486,29 +486,29 @@ define void @test_vp_logical_5(* %a0, * %a1, ; CHECK-O2: # %bb.0: ; CHECK-O2-NEXT: lui a3, %hi(scratch) ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-O2-NEXT: vle8.v v26, (a0) +; CHECK-O2-NEXT: vle8.v v8, (a0) ; CHECK-O2-NEXT: addi a0, a3, %lo(scratch) -; CHECK-O2-NEXT: vle8.v v28, (a1) +; CHECK-O2-NEXT: vle8.v v10, (a1) ; CHECK-O2-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-O2-NEXT: vand.vi v26, v26, 1 -; CHECK-O2-NEXT: vmsne.vi v30, v26, 0 -; CHECK-O2-NEXT: vand.vi v26, v28, 1 -; CHECK-O2-NEXT: vmsne.vi v28, v26, 0 +; CHECK-O2-NEXT: vand.vi v8, v8, 1 +; CHECK-O2-NEXT: vmsne.vi v12, v8, 0 +; CHECK-O2-NEXT: vand.vi v8, v10, 1 +; CHECK-O2-NEXT: vmsne.vi v10, v8, 0 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-O2-NEXT: vmand.mm v0, v30, v28 -; CHECK-O2-NEXT: vmor.mm v25, v30, v28 -; CHECK-O2-NEXT: vmxor.mm v26, v30, v28 +; CHECK-O2-NEXT: vmand.mm v0, v12, v10 +; CHECK-O2-NEXT: vmor.mm v8, v12, v10 +; CHECK-O2-NEXT: vmxor.mm v9, v12, v10 ; CHECK-O2-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-O2-NEXT: vmv.v.i v28, 0 -; CHECK-O2-NEXT: vmerge.vim v30, v28, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v25 -; CHECK-O2-NEXT: vmerge.vim v8, v28, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v26 -; CHECK-O2-NEXT: vmerge.vim v26, v28, 1, v0 +; CHECK-O2-NEXT: vmv.v.i v10, 0 +; CHECK-O2-NEXT: vmerge.vim v12, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v8 +; CHECK-O2-NEXT: vmerge.vim v14, v10, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v9 +; CHECK-O2-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-O2-NEXT: vse8.v v30, (a0) +; CHECK-O2-NEXT: vse8.v v12, (a0) +; CHECK-O2-NEXT: vse8.v v14, (a0) ; CHECK-O2-NEXT: vse8.v v8, (a0) -; CHECK-O2-NEXT: vse8.v v26, (a0) ; CHECK-O2-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -550,38 +550,38 @@ define void @test_vp_logical_6(* %a0, * %a1, ; CHECK-O0-NEXT: # implicit-def: $v8m4 ; CHECK-O0-NEXT: vsetvli zero, a2, e8, m4, ta, mu ; CHECK-O0-NEXT: vle8.v v8, (a3) -; CHECK-O0-NEXT: # implicit-def: $v28m4 -; CHECK-O0-NEXT: vle8.v v28, (a1) +; CHECK-O0-NEXT: # implicit-def: $v12m4 +; CHECK-O0-NEXT: vle8.v v12, (a1) ; CHECK-O0-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-O0-NEXT: vand.vi v8, v8, 1 -; CHECK-O0-NEXT: vmsne.vi v25, v8, 0 -; CHECK-O0-NEXT: vand.vi v28, v28, 1 -; CHECK-O0-NEXT: vmsne.vi v26, v28, 0 +; CHECK-O0-NEXT: vand.vi v16, v8, 1 +; CHECK-O0-NEXT: vmsne.vi v8, v16, 0 +; CHECK-O0-NEXT: vand.vi v12, v12, 1 +; CHECK-O0-NEXT: vmsne.vi v9, v12, 0 ; CHECK-O0-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-O0-NEXT: vmand.mm v0, v25, v26 -; CHECK-O0-NEXT: vmor.mm v27, v25, v26 +; CHECK-O0-NEXT: vmand.mm v0, v8, v9 +; CHECK-O0-NEXT: vmor.mm v10, v8, v9 ; CHECK-O0-NEXT: addi a1, sp, 16 -; CHECK-O0-NEXT: vs1r.v v27, (a1) # Unknown-size Folded Spill -; CHECK-O0-NEXT: vmxor.mm v25, v25, v26 +; CHECK-O0-NEXT: vs1r.v v10, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 16 -; CHECK-O0-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill +; CHECK-O0-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-O0-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-O0-NEXT: vmv.v.i v28, 0 -; CHECK-O0-NEXT: vmerge.vim v12, v28, 1, v0 +; CHECK-O0-NEXT: vmv.v.i v8, 0 +; CHECK-O0-NEXT: vmerge.vim v16, v8, 1, v0 ; CHECK-O0-NEXT: addi a1, sp, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v8, v28, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v12, v8, 1, v0 ; CHECK-O0-NEXT: csrr a1, vlenb ; CHECK-O0-NEXT: add a1, sp, a1 ; CHECK-O0-NEXT: addi a1, a1, 16 ; CHECK-O0-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; CHECK-O0-NEXT: vmerge.vim v28, v28, 1, v0 +; CHECK-O0-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-O0-NEXT: vsetvli zero, a2, e8, m4, ta, mu +; CHECK-O0-NEXT: vse8.v v16, (a0) ; CHECK-O0-NEXT: vse8.v v12, (a0) ; CHECK-O0-NEXT: vse8.v v8, (a0) -; CHECK-O0-NEXT: vse8.v v28, (a0) ; CHECK-O0-NEXT: csrr a0, vlenb ; CHECK-O0-NEXT: slli a0, a0, 1 ; CHECK-O0-NEXT: add sp, sp, a0 @@ -592,29 +592,29 @@ define void @test_vp_logical_6(* %a0, * %a1, ; CHECK-O2: # %bb.0: ; CHECK-O2-NEXT: lui a3, %hi(scratch) ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-O2-NEXT: vle8.v v28, (a0) +; CHECK-O2-NEXT: vle8.v v8, (a0) ; CHECK-O2-NEXT: addi a0, a3, %lo(scratch) -; CHECK-O2-NEXT: vle8.v v8, (a1) +; CHECK-O2-NEXT: vle8.v v12, (a1) ; CHECK-O2-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-O2-NEXT: vand.vi v28, v28, 1 -; CHECK-O2-NEXT: vmsne.vi v26, v28, 0 -; CHECK-O2-NEXT: vand.vi v28, v8, 1 -; CHECK-O2-NEXT: vmsne.vi v27, v28, 0 +; CHECK-O2-NEXT: vand.vi v8, v8, 1 +; CHECK-O2-NEXT: vmsne.vi v16, v8, 0 +; CHECK-O2-NEXT: vand.vi v8, v12, 1 +; CHECK-O2-NEXT: vmsne.vi v12, v8, 0 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-O2-NEXT: vmand.mm v0, v26, v27 -; CHECK-O2-NEXT: vmor.mm v25, v26, v27 -; CHECK-O2-NEXT: vmxor.mm v26, v26, v27 +; CHECK-O2-NEXT: vmand.mm v0, v16, v12 +; CHECK-O2-NEXT: vmor.mm v8, v16, v12 +; CHECK-O2-NEXT: vmxor.mm v9, v16, v12 ; CHECK-O2-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-O2-NEXT: vmv.v.i v28, 0 -; CHECK-O2-NEXT: vmerge.vim v8, v28, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v25 -; CHECK-O2-NEXT: vmerge.vim v12, v28, 1, v0 -; CHECK-O2-NEXT: vmv1r.v v0, v26 -; CHECK-O2-NEXT: vmerge.vim v28, v28, 1, v0 +; CHECK-O2-NEXT: vmv.v.i v12, 0 +; CHECK-O2-NEXT: vmerge.vim v16, v12, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v8 +; CHECK-O2-NEXT: vmerge.vim v20, v12, 1, v0 +; CHECK-O2-NEXT: vmv1r.v v0, v9 +; CHECK-O2-NEXT: vmerge.vim v8, v12, 1, v0 ; CHECK-O2-NEXT: vsetvli zero, a2, e8, m4, ta, mu +; CHECK-O2-NEXT: vse8.v v16, (a0) +; CHECK-O2-NEXT: vse8.v v20, (a0) ; CHECK-O2-NEXT: vse8.v v8, (a0) -; CHECK-O2-NEXT: vse8.v v12, (a0) -; CHECK-O2-NEXT: vse8.v v28, (a0) ; CHECK-O2-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/epi-vp-ptrtoint-disable-vpred-sdags.ll b/llvm/test/CodeGen/RISCV/epi-vp-ptrtoint-disable-vpred-sdags.ll index feffda8d0391bfdbaf3a5c91bbc8ace5b4c35af5..210655b423f8a07aade204bb08e4e8b6632e7cb0 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-ptrtoint-disable-vpred-sdags.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-ptrtoint-disable-vpred-sdags.ll @@ -6,11 +6,11 @@ define @test_llvm_vp_ptrtoint_v8i8_v8p0i8( % ; CHECK-LABEL: test_llvm_vp_ptrtoint_v8i8_v8p0i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0, v0.t +; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v28, 0, v0.t +; CHECK-NEXT: vnsrl.wi v10, v16, 0, v0.t ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0, v0.t +; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t ; CHECK-NEXT: ret %x = call @llvm.vp.ptrtoint.v8i8.v8p0i8( %ptrs, %mask, i32 %evl) ret %x @@ -20,9 +20,9 @@ define @test_llvm_vp_ptrtoint_v4i16_v4p0i16( @llvm.vp.ptrtoint.v4i16.v4p0i16( %ptrs, %mask, i32 %evl) ret %x @@ -32,8 +32,8 @@ define @test_llvm_vp_ptrtoint_v2i32_v2p0i32( @llvm.vp.ptrtoint.v2i32.v2p0i32( %ptrs, %mask, i32 %evl) ret %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-ptrtoint.ll b/llvm/test/CodeGen/RISCV/epi-vp-ptrtoint.ll index 9cc1438507a58993e50eb2ef676cb509f607e28d..60e767d394bb219fa75aa16f86224fdd236499c0 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-ptrtoint.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-ptrtoint.ll @@ -6,11 +6,11 @@ define @test_llvm_vp_ptrtoint_v8i8_v8p0i8( % ; CHECK-LABEL: test_llvm_vp_ptrtoint_v8i8_v8p0i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0, v0.t +; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v28, 0, v0.t +; CHECK-NEXT: vnsrl.wi v10, v16, 0, v0.t ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0, v0.t +; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t ; CHECK-NEXT: ret %x = call @llvm.vp.ptrtoint.v8i8.v8p0i8( %ptrs, %mask, i32 %evl) ret %x @@ -20,9 +20,9 @@ define @test_llvm_vp_ptrtoint_v4i16_v4p0i16( @llvm.vp.ptrtoint.v4i16.v4p0i16( %ptrs, %mask, i32 %evl) ret %x @@ -32,8 +32,8 @@ define @test_llvm_vp_ptrtoint_v2i32_v2p0i32( @llvm.vp.ptrtoint.v2i32.v2p0i32( %ptrs, %mask, i32 %evl) ret %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-scatter.ll b/llvm/test/CodeGen/RISCV/epi-vp-scatter.ll index 2f861645859a7f866468edf0d6977ccaa75ec48f..62ccb47a603ab3177c964d0d6432c53ac427b08a 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-scatter.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-scatter.ll @@ -6,11 +6,11 @@ define void @nxv1i64_1( %data, i64* %ptr, % ; CHECK-LABEL: nxv1i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; CHECK-NEXT: vsll.vi v25, v9, 3 +; CHECK-NEXT: vsll.vi v9, v9, 3 ; CHECK-NEXT: slli a1, a1, 32 ; CHECK-NEXT: srli a1, a1, 32 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: ret %1 = getelementptr i64, i64* %ptr, %indices call void @llvm.vp.scatter.nxv1i64.nxv1p0i64( %data, %1, %mask, i32 %evl) @@ -33,11 +33,11 @@ define void @nxv1i64_3( %data, i64* %ptr, %m ; CHECK-LABEL: nxv1i64_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: slli a0, a1, 32 ; CHECK-NEXT: srli a0, a0, 32 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (zero), v25, v0.t +; CHECK-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; CHECK-NEXT: ret %head = insertelement undef, i64* %ptr, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -51,10 +51,10 @@ define void @nxv2f32_1( %data, float* %ptr, %indices call void @llvm.vp.scatter.nxv2f32.nxv2p0f32( %data, %1, %mask, i32 %evl) @@ -77,11 +77,11 @@ define void @nxv2f32_3( %data, float* %ptr, undef, float* %ptr, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/epi-vp-select-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/epi-vp-select-fixed-vectors.ll index 16dd9ca31b59b34266dc6e71c452523f624c2021..fa9b031fbcc9347d6c438c187bcc55a0fee58e4d 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-select-fixed-vectors.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-select-fixed-vectors.ll @@ -10,9 +10,9 @@ define void @test_vp_select_int_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %m, i ; CHECK-NEXT: lui a1, %hi(scratch) ; CHECK-NEXT: addi a1, a1, %lo(scratch) ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmerge.vvm v25, v9, v8, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vse32.v v25, (a1) +; CHECK-NEXT: vse32.v v8, (a1) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to <4 x i32>* @@ -28,9 +28,9 @@ define void @test_vp_select_int_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i1> %m, i ; CHECK-NEXT: lui a1, %hi(scratch) ; CHECK-NEXT: addi a1, a1, %lo(scratch) ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmerge.vvm v25, v9, v8, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vse64.v v25, (a1) +; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to <2 x i64>* @@ -46,9 +46,9 @@ define void @test_vp_select_fp_v4f32(<4 x float> %a, <4 x float> %b, <4 x i1> %m ; CHECK-NEXT: lui a1, %hi(scratch) ; CHECK-NEXT: addi a1, a1, %lo(scratch) ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmerge.vvm v25, v9, v8, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vse32.v v25, (a1) +; CHECK-NEXT: vse32.v v8, (a1) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to <4 x float>* @@ -64,9 +64,9 @@ define void @test_vp_select_fp_v2f64(<2 x double> %a, <2 x double> %b, <2 x i1> ; CHECK-NEXT: lui a1, %hi(scratch) ; CHECK-NEXT: addi a1, a1, %lo(scratch) ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmerge.vvm v25, v9, v8, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vse64.v v25, (a1) +; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: ret %store_addr = bitcast i8* @scratch to <2 x double>* diff --git a/llvm/test/CodeGen/RISCV/epi-vp-select.ll b/llvm/test/CodeGen/RISCV/epi-vp-select.ll index f6308fb3f9adc6415bad645d9ef375fcaaafd545..5529c7dc4a3fcab15803160da8bcbd947ede34e5 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-select.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-select.ll @@ -14,8 +14,8 @@ define void @test_vp_select_int( %a, %b, %a, %b, * @@ -42,8 +42,8 @@ define void @test_vp_select_int_2( %a, %b, ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmerge.vvm v25, v9, v8, v0 -; CHECK-O0-NEXT: vs1r.v v25, (a0) +; CHECK-O0-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-O0-NEXT: vs1r.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_select_int_2: @@ -51,8 +51,8 @@ define void @test_vp_select_int_2( %a, %b, ; CHECK-O2-NEXT: lui a1, %hi(scratch) ; CHECK-O2-NEXT: addi a1, a1, %lo(scratch) ; CHECK-O2-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-O2-NEXT: vmerge.vvm v25, v9, v8, v0 -; CHECK-O2-NEXT: vs1r.v v25, (a1) +; CHECK-O2-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-O2-NEXT: vs1r.v v8, (a1) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -70,8 +70,8 @@ define void @test_vp_select_int_3( %a, %b, ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmerge.vvm v26, v10, v8, v0 -; CHECK-O0-NEXT: vs2r.v v26, (a0) +; CHECK-O0-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-O0-NEXT: vs2r.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_select_int_3: @@ -79,8 +79,8 @@ define void @test_vp_select_int_3( %a, %b, ; CHECK-O2-NEXT: lui a1, %hi(scratch) ; CHECK-O2-NEXT: addi a1, a1, %lo(scratch) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-O2-NEXT: vmerge.vvm v26, v10, v8, v0 -; CHECK-O2-NEXT: vs2r.v v26, (a1) +; CHECK-O2-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-O2-NEXT: vs2r.v v8, (a1) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -98,8 +98,8 @@ define void @test_vp_select_fp( %a, % ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vmerge.vvm v25, v9, v8, v0 -; CHECK-O0-NEXT: vs1r.v v25, (a0) +; CHECK-O0-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-O0-NEXT: vs1r.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_select_fp: @@ -107,8 +107,8 @@ define void @test_vp_select_fp( %a, % ; CHECK-O2-NEXT: lui a1, %hi(scratch) ; CHECK-O2-NEXT: addi a1, a1, %lo(scratch) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-O2-NEXT: vmerge.vvm v25, v9, v8, v0 -; CHECK-O2-NEXT: vs1r.v v25, (a1) +; CHECK-O2-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-O2-NEXT: vs1r.v v8, (a1) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -126,8 +126,8 @@ define void @test_vp_select_fp_2( %a, % ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-O0-NEXT: vmerge.vvm v25, v9, v8, v0 -; CHECK-O0-NEXT: vs1r.v v25, (a0) +; CHECK-O0-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-O0-NEXT: vs1r.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_select_fp_2: @@ -135,8 +135,8 @@ define void @test_vp_select_fp_2( %a, % ; CHECK-O2-NEXT: lui a1, %hi(scratch) ; CHECK-O2-NEXT: addi a1, a1, %lo(scratch) ; CHECK-O2-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-O2-NEXT: vmerge.vvm v25, v9, v8, v0 -; CHECK-O2-NEXT: vs1r.v v25, (a1) +; CHECK-O2-NEXT: vmerge.vvm v8, v9, v8, v0 +; CHECK-O2-NEXT: vs1r.v v8, (a1) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -154,8 +154,8 @@ define void @test_vp_select_fp_3( %a, ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-O0-NEXT: vmerge.vvm v26, v10, v8, v0 -; CHECK-O0-NEXT: vs2r.v v26, (a0) +; CHECK-O0-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-O0-NEXT: vs2r.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_select_fp_3: @@ -163,8 +163,8 @@ define void @test_vp_select_fp_3( %a, ; CHECK-O2-NEXT: lui a1, %hi(scratch) ; CHECK-O2-NEXT: addi a1, a1, %lo(scratch) ; CHECK-O2-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-O2-NEXT: vmerge.vvm v26, v10, v8, v0 -; CHECK-O2-NEXT: vs2r.v v26, (a1) +; CHECK-O2-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-O2-NEXT: vs2r.v v8, (a1) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -178,15 +178,16 @@ define void @test_vp_select_mask( %a, %b, %a, %b, * @@ -212,15 +213,16 @@ define void @test_vp_select_mask_2( %a, %b, < ; CHECK-O0-LABEL: test_vp_select_mask_2: ; CHECK-O0: # %bb.0: ; CHECK-O0-NEXT: mv a1, a0 +; CHECK-O0-NEXT: vmv1r.v v10, v9 ; CHECK-O0-NEXT: # kill: def $x10 killed $x11 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-O0-NEXT: vmxor.mm v25, v8, v0 -; CHECK-O0-NEXT: vmand.mm v25, v25, v9 -; CHECK-O0-NEXT: vmxor.mm v25, v8, v25 +; CHECK-O0-NEXT: vmxor.mm v9, v8, v0 +; CHECK-O0-NEXT: vmand.mm v9, v9, v10 +; CHECK-O0-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O0-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_select_mask_2: @@ -228,11 +230,11 @@ define void @test_vp_select_mask_2( %a, %b, < ; CHECK-O2-NEXT: lui a1, %hi(scratch) ; CHECK-O2-NEXT: addi a1, a1, %lo(scratch) ; CHECK-O2-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-O2-NEXT: vmxor.mm v25, v8, v0 -; CHECK-O2-NEXT: vmand.mm v25, v25, v9 -; CHECK-O2-NEXT: vmxor.mm v25, v8, v25 +; CHECK-O2-NEXT: vmxor.mm v10, v8, v0 +; CHECK-O2-NEXT: vmand.mm v9, v10, v9 +; CHECK-O2-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O2-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v8, (a1) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * @@ -246,15 +248,16 @@ define void @test_vp_select_mask_3( %a, %b, < ; CHECK-O0-LABEL: test_vp_select_mask_3: ; CHECK-O0: # %bb.0: ; CHECK-O0-NEXT: mv a1, a0 +; CHECK-O0-NEXT: vmv1r.v v10, v9 ; CHECK-O0-NEXT: # kill: def $x10 killed $x11 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) ; CHECK-O0-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-O0-NEXT: vmxor.mm v25, v8, v0 -; CHECK-O0-NEXT: vmand.mm v25, v25, v9 -; CHECK-O0-NEXT: vmxor.mm v25, v8, v25 +; CHECK-O0-NEXT: vmxor.mm v9, v8, v0 +; CHECK-O0-NEXT: vmand.mm v9, v9, v10 +; CHECK-O0-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O0-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-O0-NEXT: vsm.v v25, (a0) +; CHECK-O0-NEXT: vsm.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vp_select_mask_3: @@ -262,11 +265,11 @@ define void @test_vp_select_mask_3( %a, %b, < ; CHECK-O2-NEXT: lui a1, %hi(scratch) ; CHECK-O2-NEXT: addi a1, a1, %lo(scratch) ; CHECK-O2-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-O2-NEXT: vmxor.mm v25, v8, v0 -; CHECK-O2-NEXT: vmand.mm v25, v25, v9 -; CHECK-O2-NEXT: vmxor.mm v25, v8, v25 +; CHECK-O2-NEXT: vmxor.mm v10, v8, v0 +; CHECK-O2-NEXT: vmand.mm v9, v10, v9 +; CHECK-O2-NEXT: vmxor.mm v8, v8, v9 ; CHECK-O2-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-O2-NEXT: vsm.v v25, (a1) +; CHECK-O2-NEXT: vsm.v v8, (a1) ; CHECK-O2-NEXT: ret %store_addr = bitcast i8* @scratch to * diff --git a/llvm/test/CodeGen/RISCV/epi-vp-sext-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/epi-vp-sext-fixed-vectors.ll index c3e2d07a26cca1bd71ff4d1966e462f7772245a1..025d0a08776bba38db6bd08f03541b0ad77b6567 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-sext-fixed-vectors.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-sext-fixed-vectors.ll @@ -6,8 +6,8 @@ define <2 x i64> @sext.i64.i32(<2 x i32> %a, i32 zeroext %gvl) ; CHECK-LABEL: sext.i64.i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %b = call <2 x i64> @llvm.vp.sext.v2i64.v2i32(<2 x i32> %a, @@ -20,8 +20,8 @@ define <2 x i64> @sext.i64.i32.mask(<2 x i32> %a, <2 x i1> %mask, i32 zeroext %g ; CHECK-LABEL: sext.i64.i32.mask: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %b = call <2 x i64> @llvm.vp.sext.v2i64.v2i32( @@ -37,8 +37,8 @@ define <4 x i32> @test_vp_sext_v4i32_v4i8(<4 x i8> %a, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_sext_v4i32_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %m.first = insertelement <4 x i1> undef, i1 1, i32 0 %m.splat = shufflevector <4 x i1> %m.first, <4 x i1> undef, <4 x i32> zeroinitializer @@ -50,8 +50,8 @@ define <4 x i32> @test_vp_sext_masked_v4i32_v4i8(<4 x i8> %a, <4 x i1> %mask, i3 ; CHECK-LABEL: test_vp_sext_masked_v4i32_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %x = call <4 x i32> @llvm.vp.sext.v4i32.v4i8(<4 x i8> %a, <4 x i1> %mask, i32 %evl) ret <4 x i32> %x @@ -61,8 +61,8 @@ define <4 x i64> @test_vp_sext_v4i64_v4i8(<4 x i8> %a, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_sext_v4i64_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf8 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf8 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %m.first = insertelement <4 x i1> undef, i1 1, i32 0 %m.splat = shufflevector <4 x i1> %m.first, <4 x i1> undef, <4 x i32> zeroinitializer @@ -74,8 +74,8 @@ define <4 x i64> @test_vp_sext_masked_v4i64_v4i8(<4 x i8> %a, <4 x i1> %mask, i3 ; CHECK-LABEL: test_vp_sext_masked_v4i64_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf8 v26, v8, v0.t -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf8 v10, v8, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %x = call <4 x i64> @llvm.vp.sext.v4i64.v4i8(<4 x i8> %a, <4 x i1> %mask, i32 %evl) ret <4 x i64> %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-sext-masks-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/epi-vp-sext-masks-fixed-vectors.ll index 71b8a3e5f4dd10a0c281e15aba620475a74f9556..68558df32e30e9e007f33f1831db9945ec6cab81 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-sext-masks-fixed-vectors.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-sext-masks-fixed-vectors.ll @@ -11,8 +11,8 @@ define <2 x i64> @test_vp_sext_v2i64_v2i1(<2 x i1> %op, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_sext_v2i64_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %head = insertelement <2 x i1> undef, i1 1, i32 0 %allones = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer @@ -25,8 +25,8 @@ define <2 x i64> @test_vp_sext_masked_v2i64_v2i1(<2 x i1> %op, <2 x i1> %mask, i ; CHECK-LABEL: test_vp_sext_masked_v2i64_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %x = call <2 x i64> @llvm.vp.sext.v2i64.v2i1(<2 x i1> %op, <2 x i1> %mask, i32 %evl) ret <2 x i64> %x @@ -36,8 +36,8 @@ define <4 x i32> @test_vp_sext_v4i32_v4i1(<4 x i1> %op, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_sext_v4i32_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %head = insertelement <4 x i1> undef, i1 1, i32 0 %allones = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer @@ -50,8 +50,8 @@ define <4 x i32> @test_vp_sext_masked_v4i32_v4i1(<4 x i1> %op, <4 x i1> %mask, i ; CHECK-LABEL: test_vp_sext_masked_v4i32_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %x = call <4 x i32> @llvm.vp.sext.v4i32.v4i1(<4 x i1> %op, <4 x i1> %mask, i32 %evl) ret <4 x i32> %x @@ -61,8 +61,8 @@ define <8 x i16> @test_vp_sext_v8i16_v8i1(<8 x i1> %op, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_sext_v8i16_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %head = insertelement <8 x i1> undef, i1 1, i32 0 %allones = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer @@ -75,8 +75,8 @@ define <8 x i16> @test_vp_sext_masked_v8i16_v8i1(<8 x i1> %op, <8 x i1> %mask, i ; CHECK-LABEL: test_vp_sext_masked_v8i16_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %x = call <8 x i16> @llvm.vp.sext.v8i16.v8i1(<8 x i1> %op, <8 x i1> %mask, i32 %evl) ret <8 x i16> %x @@ -86,8 +86,8 @@ define <16 x i8> @test_vp_sext_v16i8_v16i1(<16 x i1> %op, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_sext_v16i8_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %head = insertelement <16 x i1> undef, i1 1, i32 0 %allones = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer @@ -100,8 +100,8 @@ define <16 x i8> @test_vp_sext_masked_v16i8_v16i1(<16 x i1> %op, <16 x i1> %mask ; CHECK-LABEL: test_vp_sext_masked_v16i8_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %x = call <16 x i8> @llvm.vp.sext.v16i8.v16i1(<16 x i1> %op, <16 x i1> %mask, i32 %evl) ret <16 x i8> %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-sext-masks.ll b/llvm/test/CodeGen/RISCV/epi-vp-sext-masks.ll index 7aaef830bb2e6ba0a612b246afc44f955497ccfb..9ad83fb5c5598139d8b2da1c505ecc9281cf4e2b 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-sext-masks.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-sext-masks.ll @@ -36,8 +36,8 @@ define @test_vp_sext_nxv8i32_nxv8i1( %op, i3 ; CHECK-LABEL: test_vp_sext_nxv8i32_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -50,8 +50,8 @@ define @test_vp_sext_masked_nxv8i32_nxv8i1( ; CHECK-LABEL: test_vp_sext_masked_nxv8i32_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %x = call @llvm.vp.sext.nxv8i32.nxv8i1( %op, %mask, i32 %evl) ret %x @@ -61,8 +61,8 @@ define @test_vp_sext_nxv8i16_nxv8i1( %op, i3 ; CHECK-LABEL: test_vp_sext_nxv8i16_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -75,8 +75,8 @@ define @test_vp_sext_masked_nxv8i16_nxv8i1( ; CHECK-LABEL: test_vp_sext_masked_nxv8i16_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %x = call @llvm.vp.sext.nxv8i16.nxv8i1( %op, %mask, i32 %evl) ret %x @@ -86,8 +86,8 @@ define @test_vp_sext_nxv8i8_nxv8i1( %op, i32 ; CHECK-LABEL: test_vp_sext_nxv8i8_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -100,8 +100,8 @@ define @test_vp_sext_masked_nxv8i8_nxv8i1( %o ; CHECK-LABEL: test_vp_sext_masked_nxv8i8_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %x = call @llvm.vp.sext.nxv8i8.nxv8i1( %op, %mask, i32 %evl) ret %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-sext.ll b/llvm/test/CodeGen/RISCV/epi-vp-sext.ll index d81d66da0fa8f2773698711deceb959b4c2859c7..6163a991b321e4f648505f6df20b7744b69f12bc 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-sext.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-sext.ll @@ -6,8 +6,8 @@ define @sext.i64.i32( %a, i32 zeroext %gvl) ; CHECK-LABEL: sext.i64.i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret { %b = call @llvm.vp.sext.nxv2i64.nxv2i32( %a, @@ -20,8 +20,8 @@ define @sext.i64.i32.mask( %a, @llvm.vp.sext.nxv2i64.nxv2i32( @@ -37,8 +37,8 @@ define @test_vp_sext_nxv4i32_nxv4i8( %a, i32 ; CHECK-LABEL: test_vp_sext_nxv4i32_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -50,8 +50,8 @@ define @test_vp_sext_masked_nxv4i32_nxv4i8( ; CHECK-LABEL: test_vp_sext_masked_nxv4i32_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf4 v26, v8, v0.t -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf4 v10, v8, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %x = call @llvm.vp.sext.nxv4i32.nxv4i8( %a, %mask, i32 %evl) ret %x @@ -61,8 +61,8 @@ define @test_vp_sext_nxv4i64_nxv4i8( %a, i32 ; CHECK-LABEL: test_vp_sext_nxv4i64_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf8 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -74,8 +74,8 @@ define @test_vp_sext_masked_nxv4i64_nxv4i8( ; CHECK-LABEL: test_vp_sext_masked_nxv4i64_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v28, v8, v0.t -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf8 v12, v8, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %x = call @llvm.vp.sext.nxv4i64.nxv4i8( %a, %mask, i32 %evl) ret %x @@ -85,8 +85,8 @@ define @test_vp_sext_nxv4i64_nxv4i16( %a, i ; CHECK-LABEL: test_vp_sext_nxv4i64_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/epi-vp-sitofp.ll b/llvm/test/CodeGen/RISCV/epi-vp-sitofp.ll index 151eeb886a1ffb54b9515bdd336c5a8bff5e3ff0..b6eee1d1d8e16c4f814c104f8d1e1a0b72299e94 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-sitofp.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-sitofp.ll @@ -35,8 +35,8 @@ define @sitofp.f32.i64( %a, i32 zeroext % ; CHECK-LABEL: sitofp.f32.i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.x.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret { %b = call @llvm.vp.sitofp.nxv2f32.nxv2i64( %a, @@ -49,8 +49,8 @@ define @sitofp.f32.i64.mask( %a, @llvm.vp.sitofp.nxv2f32.nxv2i64( @@ -66,8 +66,8 @@ define @sitofp.f64.i32( %a, i32 zeroext ; CHECK-LABEL: sitofp.f64.i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.x.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.f.x.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret { %b = call @llvm.vp.sitofp.nxv2f64.nxv2i32( %a, @@ -80,8 +80,8 @@ define @sitofp.f64.i32.mask( %a, @llvm.vp.sitofp.nxv2f64.nxv2i32( @@ -97,8 +97,8 @@ define @test_vp_sitofp_nxv4f32_nxv4i8( %a, ; CHECK-LABEL: test_vp_sitofp_nxv4f32_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vfwcvt.f.x.v v8, v25 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vfwcvt.f.x.v v8, v10 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -110,8 +110,8 @@ define @test_vp_sitofp_nxv4f32_nxv4i8_mask( @llvm.vp.sitofp.nxv4f32.nxv4i8( %a, %m, i32 %evl) ret %x @@ -121,8 +121,8 @@ define @test_vp_sitofp_nxv4f64_nxv4i8( %a ; CHECK-LABEL: test_vp_sitofp_nxv4f64_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf4 v26, v8 -; CHECK-NEXT: vfwcvt.f.x.v v8, v26 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vfwcvt.f.x.v v8, v12 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -134,8 +134,8 @@ define @test_vp_sitofp_nxv4f64_nxv4i8_mask( @llvm.vp.sitofp.nxv4f64.nxv4i8( %a, %m, i32 %evl) ret %x @@ -145,8 +145,8 @@ define @test_vp_sitofp_nxv4f64_nxv4i16( ; CHECK-LABEL: test_vp_sitofp_nxv4f64_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vfwcvt.f.x.v v8, v26 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vfwcvt.f.x.v v8, v12 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -158,8 +158,8 @@ define @test_vp_sitofp_nxv4f64_nxv4i16_mask( @llvm.vp.sitofp.nxv4f64.nxv4i16( %a, %m, i32 %evl) ret %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-slideleft.ll b/llvm/test/CodeGen/RISCV/epi-vp-slideleft.ll index b289533778242568c35aaba01b497e8504d433a1..edcc3a4c6a4cacd9773e5ef231740d35042e7cb3 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-slideleft.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-slideleft.ll @@ -8,13 +8,13 @@ define @nxv1i64( %va, %v ; CHECK-LABEL: nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: sub a0, a1, a0 ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; CHECK-NEXT: vid.v v26 -; CHECK-NEXT: vmsltu.vx v0, v26, a0 -; CHECK-NEXT: vslideup.vx v26, v9, a0 -; CHECK-NEXT: vmerge.vvm v8, v26, v25, v0 +; CHECK-NEXT: vid.v v10 +; CHECK-NEXT: vmsltu.vx v0, v10, a0 +; CHECK-NEXT: vslideup.vx v10, v9, a0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = call @llvm.experimental.vector.vp.slideleftfill.nxv1i64( %va, @@ -33,13 +33,13 @@ define @nxv2i32( %va, %v ; CHECK-LABEL: nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: sub a0, a1, a0 ; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu -; CHECK-NEXT: vid.v v26 -; CHECK-NEXT: vmsltu.vx v0, v26, a0 -; CHECK-NEXT: vslideup.vx v26, v9, a0 -; CHECK-NEXT: vmerge.vvm v8, v26, v25, v0 +; CHECK-NEXT: vid.v v10 +; CHECK-NEXT: vmsltu.vx v0, v10, a0 +; CHECK-NEXT: vslideup.vx v10, v9, a0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = call @llvm.experimental.vector.vp.slideleftfill.nxv2i32( %va, @@ -58,13 +58,13 @@ define @nxv1f64( %va, @llvm.experimental.vector.vp.slideleftfill.nxv1f64( %va, @@ -83,13 +83,13 @@ define @nxv2f32( %va, @llvm.experimental.vector.vp.slideleftfill.nxv2f32( %va, @@ -108,13 +108,13 @@ define @nxv2i64( %va, %v ; CHECK-LABEL: nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: sub a0, a1, a0 ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; CHECK-NEXT: vid.v v28 -; CHECK-NEXT: vmsltu.vx v0, v28, a0 -; CHECK-NEXT: vslideup.vx v28, v10, a0 -; CHECK-NEXT: vmerge.vvm v8, v28, v26, v0 +; CHECK-NEXT: vid.v v12 +; CHECK-NEXT: vmsltu.vx v0, v12, a0 +; CHECK-NEXT: vslideup.vx v12, v10, a0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = call @llvm.experimental.vector.vp.slideleftfill.nxv2i64( %va, diff --git a/llvm/test/CodeGen/RISCV/epi-vp-trunc-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/epi-vp-trunc-fixed-vectors.ll index fea001f97d02538b59f819dca7c53a51ffd62868..b5fc35f2061e67d8572ae900d199ee73d7da66c8 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-trunc-fixed-vectors.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-trunc-fixed-vectors.ll @@ -6,8 +6,8 @@ define <4 x i32> @test_vp_trunc_v4i32_v4i64(<4 x i64> %a, i32 zeroext %gvl) { ; CHECK-LABEL: test_vp_trunc_v4i32_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %b = call <4 x i32> @llvm.vp.trunc.v4i32.v4i64(<4 x i64> %a, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), @@ -19,8 +19,8 @@ define <4 x i32> @test_vp_trunc_v4i32_v4i64_mask(<4 x i64> %a, <4 x i1> %mask, i ; CHECK-LABEL: test_vp_trunc_v4i32_v4i64_mask: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %b = call <4 x i32> @llvm.vp.trunc.v4i32.v4i64( <4 x i64> %a, @@ -33,9 +33,9 @@ define <16 x i8> @test_vp_trunc_v16i8_v16i32(<16 x i32> %a, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_trunc_v16i8_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: ret %m.first = insertelement <16 x i1> undef, i1 1, i32 0 %m.splat = shufflevector <16 x i1> %m.first, <16 x i1> undef, <16 x i32> zeroinitializer @@ -47,11 +47,11 @@ define <16 x i8> @test_vp_trunc_v16i8_v16i64(<16 x i64> %a, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_trunc_v16i8_v16i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v28, 0 +; CHECK-NEXT: vnsrl.wi v10, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %m.first = insertelement <16 x i1> undef, i1 1, i32 0 %m.splat = shufflevector <16 x i1> %m.first, <16 x i1> undef, <16 x i32> zeroinitializer @@ -63,9 +63,9 @@ define <8 x i16> @test_vp_trunc_v8i16_v8i64(<8 x i64> %a, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_trunc_v8i16_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: ret %m.first = insertelement <8 x i1> undef, i1 1, i32 0 %m.splat = shufflevector <8 x i1> %m.first, <8 x i1> undef, <8 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/epi-vp-trunc-masks-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/epi-vp-trunc-masks-fixed-vectors.ll index 7232673aa3e7db6f8464cd330449e121103da0ad..01bac9627ee2d9aabddd4a7a3204f9784ab848d6 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-trunc-masks-fixed-vectors.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-trunc-masks-fixed-vectors.ll @@ -11,8 +11,8 @@ define <2 x i1> @test_vp_trunc_v2i1_v2i64(<2 x i64> %op, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_trunc_v2i1_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement <2 x i1> undef, i1 1, i32 0 %allones = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer @@ -25,8 +25,8 @@ define <2 x i1> @test_vp_trunc_masked_v2i1_v2i64(<2 x i64> %op, <2 x i1> %mask, ; CHECK-LABEL: test_vp_trunc_masked_v2i1_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1, v0.t -; CHECK-NEXT: vmsne.vi v0, v25, 0, v0.t +; CHECK-NEXT: vand.vi v8, v8, 1, v0.t +; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t ; CHECK-NEXT: ret %x = call <2 x i1> @llvm.vp.trunc.v2i1.v2i64(<2 x i64> %op, <2 x i1> %mask, i32 %evl) ret <2 x i1> %x @@ -36,8 +36,8 @@ define <4 x i1> @test_vp_trunc_v4i1_v4i32(<4 x i32> %op, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_trunc_v4i1_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement <4 x i1> undef, i1 1, i32 0 %allones = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer @@ -50,8 +50,8 @@ define <4 x i1> @test_vp_trunc_masked_v4i1_v4i32(<4 x i32> %op, <4 x i1> %mask, ; CHECK-LABEL: test_vp_trunc_masked_v4i1_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1, v0.t -; CHECK-NEXT: vmsne.vi v0, v25, 0, v0.t +; CHECK-NEXT: vand.vi v8, v8, 1, v0.t +; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t ; CHECK-NEXT: ret %x = call <4 x i1> @llvm.vp.trunc.v4i1.v4i32(<4 x i32> %op, <4 x i1> %mask, i32 %evl) ret <4 x i1> %x @@ -61,8 +61,8 @@ define <8 x i1> @test_vp_trunc_v8i1_v8i16(<8 x i16> %op, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_trunc_v8i1_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement <8 x i1> undef, i1 1, i32 0 %allones = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer @@ -75,8 +75,8 @@ define <8 x i1> @test_vp_trunc_masked_v8i1_v8i16(<8 x i16> %op, <8 x i1> %mask, ; CHECK-LABEL: test_vp_trunc_masked_v8i1_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1, v0.t -; CHECK-NEXT: vmsne.vi v0, v25, 0, v0.t +; CHECK-NEXT: vand.vi v8, v8, 1, v0.t +; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t ; CHECK-NEXT: ret %x = call <8 x i1> @llvm.vp.trunc.v8i1.v8i16(<8 x i16> %op, <8 x i1> %mask, i32 %evl) ret <8 x i1> %x @@ -86,8 +86,8 @@ define <16 x i1> @test_vp_trunc_v16i1_v16i8(<16 x i8> %op, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_trunc_v16i1_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement <16 x i1> undef, i1 1, i32 0 %allones = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer @@ -100,8 +100,8 @@ define <16 x i1> @test_vp_trunc_masked_v16i1_v16i8(<16 x i8> %op, <16 x i1> %mas ; CHECK-LABEL: test_vp_trunc_masked_v16i1_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1, v0.t -; CHECK-NEXT: vmsne.vi v0, v25, 0, v0.t +; CHECK-NEXT: vand.vi v8, v8, 1, v0.t +; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t ; CHECK-NEXT: ret %x = call <16 x i1> @llvm.vp.trunc.v16i1.v16i8(<16 x i8> %op, <16 x i1> %mask, i32 %evl) ret <16 x i1> %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-trunc-masks.ll b/llvm/test/CodeGen/RISCV/epi-vp-trunc-masks.ll index 09cd62bfe38ac43bf5b8154225efeb7e7d0849e9..f0ef285660661da4a2c91348d9eb047f3013a91c 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-trunc-masks.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-trunc-masks.ll @@ -11,8 +11,8 @@ define @test_vp_trunc_nxv1i1_nxv1i64( %op, i ; CHECK-LABEL: test_vp_trunc_nxv1i1_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -25,8 +25,8 @@ define @test_vp_trunc_masked_nxv1i1_nxv1i64( ; CHECK-LABEL: test_vp_trunc_masked_nxv1i1_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1, v0.t -; CHECK-NEXT: vmsne.vi v0, v25, 0, v0.t +; CHECK-NEXT: vand.vi v8, v8, 1, v0.t +; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t ; CHECK-NEXT: ret %x = call @llvm.vp.trunc.nxv1i1.nxv1i64( %op, %mask, i32 %evl) ret %x @@ -36,8 +36,8 @@ define @test_vp_trunc_nxv2i1_nxv2i32( %op, i ; CHECK-LABEL: test_vp_trunc_nxv2i1_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -50,8 +50,8 @@ define @test_vp_trunc_masked_nxv2i1_nxv2i32( ; CHECK-LABEL: test_vp_trunc_masked_nxv2i1_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1, v0.t -; CHECK-NEXT: vmsne.vi v0, v25, 0, v0.t +; CHECK-NEXT: vand.vi v8, v8, 1, v0.t +; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t ; CHECK-NEXT: ret %x = call @llvm.vp.trunc.nxv2i1.nxv2i32( %op, %mask, i32 %evl) ret %x @@ -61,8 +61,8 @@ define @test_vp_trunc_nxv4i1_nxv4i16( %op, i ; CHECK-LABEL: test_vp_trunc_nxv4i1_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -75,8 +75,8 @@ define @test_vp_trunc_masked_nxv4i1_nxv4i16( ; CHECK-LABEL: test_vp_trunc_masked_nxv4i1_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1, v0.t -; CHECK-NEXT: vmsne.vi v0, v25, 0, v0.t +; CHECK-NEXT: vand.vi v8, v8, 1, v0.t +; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t ; CHECK-NEXT: ret %x = call @llvm.vp.trunc.nxv4i1.nxv4i16( %op, %mask, i32 %evl) ret %x @@ -86,8 +86,8 @@ define @test_vp_trunc_nxv8i1_nxv8i8( %op, i32 ; CHECK-LABEL: test_vp_trunc_nxv8i1_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -100,8 +100,8 @@ define @test_vp_trunc_masked_nxv8i1_nxv8i8( % ; CHECK-LABEL: test_vp_trunc_masked_nxv8i1_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1, v0.t -; CHECK-NEXT: vmsne.vi v0, v25, 0, v0.t +; CHECK-NEXT: vand.vi v8, v8, 1, v0.t +; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t ; CHECK-NEXT: ret %x = call @llvm.vp.trunc.nxv8i1.nxv8i8( %op, %mask, i32 %evl) ret %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-trunc.ll b/llvm/test/CodeGen/RISCV/epi-vp-trunc.ll index 8e4bc032c153fdab9cf5b0aabb0acd03f8938d58..07a3e7e354d1e4ff61f060e51d9a2eca8f975752 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-trunc.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-trunc.ll @@ -6,8 +6,8 @@ define @trunc.i32.i64( %a, i32 zeroext %gvl ; CHECK-LABEL: trunc.i32.i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret { %b = call @llvm.vp.trunc.nxv2i32.nxv2i64( %a, @@ -20,8 +20,8 @@ define @trunc.i32.i64.mask( %a, @llvm.vp.trunc.nxv2i32.nxv2i64( @@ -37,9 +37,9 @@ define @test_vp_trunc_nxv4i8_nxv4i32( %a, i3 ; CHECK-LABEL: test_vp_trunc_nxv4i8_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -51,11 +51,11 @@ define @test_vp_trunc_nxv4i8_nxv4i64( %a, i3 ; CHECK-LABEL: test_vp_trunc_nxv4i8_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -67,9 +67,9 @@ define @test_vp_trunc_nxv4i16_nxv4i64( %a, ; CHECK-LABEL: test_vp_trunc_nxv4i16_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/epi-vp-uitofp.ll b/llvm/test/CodeGen/RISCV/epi-vp-uitofp.ll index 763e630ebfd3297b4974b9f6239df9f7db3ae9b4..21ba6d0f58b204bee85e0bbca0a3c5320572714e 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-uitofp.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-uitofp.ll @@ -35,8 +35,8 @@ define @uitofp.f32.i64( %a, i32 zeroext % ; CHECK-LABEL: uitofp.f32.i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.xu.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret { %b = call @llvm.vp.uitofp.nxv2f32.nxv2i64( %a, @@ -49,8 +49,8 @@ define @uitofp.f32.i64.mask( %a, @llvm.vp.uitofp.nxv2f32.nxv2i64( @@ -66,8 +66,8 @@ define @uitofp.f64.i32( %a, i32 zeroext ; CHECK-LABEL: uitofp.f64.i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.xu.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.f.xu.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret { %b = call @llvm.vp.uitofp.nxv2f64.nxv2i32( %a, @@ -80,8 +80,8 @@ define @uitofp.f64.i32.mask( %a, @llvm.vp.uitofp.nxv2f64.nxv2i32( @@ -97,8 +97,8 @@ define @test_vp_uitofp_nxv4f32_nxv4i8( %a, ; CHECK-LABEL: test_vp_uitofp_nxv4f32_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vfwcvt.f.xu.v v8, v25 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vfwcvt.f.xu.v v8, v10 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -110,8 +110,8 @@ define @test_vp_uitofp_nxv4f32_nxv4i8_mask( @llvm.vp.uitofp.nxv4f32.nxv4i8( %a, %m, i32 %evl) ret %x @@ -121,8 +121,8 @@ define @test_vp_uitofp_nxv4f64_nxv4i8( %a ; CHECK-LABEL: test_vp_uitofp_nxv4f64_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf4 v26, v8 -; CHECK-NEXT: vfwcvt.f.xu.v v8, v26 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vfwcvt.f.xu.v v8, v12 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -134,8 +134,8 @@ define @test_vp_uitofp_nxv4f64_nxv4i8_mask( @llvm.vp.uitofp.nxv4f64.nxv4i8( %a, %m, i32 %evl) ret %x @@ -145,8 +145,8 @@ define @test_vp_uitofp_nxv4f64_nxv4i16( ; CHECK-LABEL: test_vp_uitofp_nxv4f64_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vfwcvt.f.xu.v v8, v26 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vfwcvt.f.xu.v v8, v12 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -158,8 +158,8 @@ define @test_vp_uitofp_nxv4f64_nxv4i16_mask( @llvm.vp.uitofp.nxv4f64.nxv4i16( %a, %m, i32 %evl) ret %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-zext-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/epi-vp-zext-fixed-vectors.ll index de0e60f8a5a6e775a1f143f6318b8159a0de7b4c..762ce22f55449e0005a823be48dab421d42ede4c 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-zext-fixed-vectors.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-zext-fixed-vectors.ll @@ -6,8 +6,8 @@ define <2 x i64> @zext.i64.i32(<2 x i32> %a, i32 zeroext %gvl) ; CHECK-LABEL: zext.i64.i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %b = call <2 x i64> @llvm.vp.zext.v2i64.v2i32(<2 x i32> %a, @@ -20,8 +20,8 @@ define <2 x i64> @zext.i64.i32.mask(<2 x i32> %a, <2 x i1> %mask, i32 zeroext %g ; CHECK-LABEL: zext.i64.i32.mask: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %b = call <2 x i64> @llvm.vp.zext.v2i64.v2i32( @@ -37,8 +37,8 @@ define <4 x i32> @test_vp_zext_v4i32_v4i8(<4 x i8> %a, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_zext_v4i32_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %m.first = insertelement <4 x i1> undef, i1 1, i32 0 %m.splat = shufflevector <4 x i1> %m.first, <4 x i1> undef, <4 x i32> zeroinitializer @@ -50,8 +50,8 @@ define <4 x i32> @test_vp_zext_masked_v4i32_v4i8(<4 x i8> %a, <4 x i1> %mask, i3 ; CHECK-LABEL: test_vp_zext_masked_v4i32_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %x = call <4 x i32> @llvm.vp.zext.v4i32.v4i8(<4 x i8> %a, <4 x i1> %mask, i32 %evl) ret <4 x i32> %x @@ -61,8 +61,8 @@ define <4 x i64> @test_vp_zext_v4i64_v4i8(<4 x i8> %a, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_zext_v4i64_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf8 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %m.first = insertelement <4 x i1> undef, i1 1, i32 0 %m.splat = shufflevector <4 x i1> %m.first, <4 x i1> undef, <4 x i32> zeroinitializer @@ -74,8 +74,8 @@ define <4 x i64> @test_vp_zext_masked_v4i64_v4i8(<4 x i8> %a, <4 x i1> %mask, i3 ; CHECK-LABEL: test_vp_zext_masked_v4i64_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf8 v26, v8, v0.t -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf8 v10, v8, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %x = call <4 x i64> @llvm.vp.zext.v4i64.v4i8(<4 x i8> %a, <4 x i1> %mask, i32 %evl) ret <4 x i64> %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-zext-masks-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/epi-vp-zext-masks-fixed-vectors.ll index 92bb50cd4d735ca114219cc550439a59c333852b..24677e91d40facf4c3c54dfc20a35c6c612ceb35 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-zext-masks-fixed-vectors.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-zext-masks-fixed-vectors.ll @@ -11,8 +11,8 @@ define <2 x i64> @test_vp_zext_v2i64_v2i1(<2 x i1> %op, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_zext_v2i64_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %head = insertelement <2 x i1> undef, i1 1, i32 0 %allones = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer @@ -25,8 +25,8 @@ define <2 x i64> @test_vp_zext_masked_v2i64_v2i1(<2 x i1> %op, <2 x i1> %mask, i ; CHECK-LABEL: test_vp_zext_masked_v2i64_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %x = call <2 x i64> @llvm.vp.zext.v2i64.v2i1(<2 x i1> %op, <2 x i1> %mask, i32 %evl) ret <2 x i64> %x @@ -36,8 +36,8 @@ define <4 x i32> @test_vp_zext_v4i32_v4i1(<4 x i1> %op, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_zext_v4i32_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %head = insertelement <4 x i1> undef, i1 1, i32 0 %allones = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer @@ -50,8 +50,8 @@ define <4 x i32> @test_vp_zext_masked_v4i32_v4i1(<4 x i1> %op, <4 x i1> %mask, i ; CHECK-LABEL: test_vp_zext_masked_v4i32_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %x = call <4 x i32> @llvm.vp.zext.v4i32.v4i1(<4 x i1> %op, <4 x i1> %mask, i32 %evl) ret <4 x i32> %x @@ -61,8 +61,8 @@ define <8 x i16> @test_vp_zext_v8i16_v8i1(<8 x i1> %op, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_zext_v8i16_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %head = insertelement <8 x i1> undef, i1 1, i32 0 %allones = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer @@ -75,8 +75,8 @@ define <8 x i16> @test_vp_zext_masked_v8i16_v8i1(<8 x i1> %op, <8 x i1> %mask, i ; CHECK-LABEL: test_vp_zext_masked_v8i16_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %x = call <8 x i16> @llvm.vp.zext.v8i16.v8i1(<8 x i1> %op, <8 x i1> %mask, i32 %evl) ret <8 x i16> %x @@ -86,8 +86,8 @@ define <16 x i8> @test_vp_zext_v16i8_v16i1(<16 x i1> %op, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_zext_v16i8_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %head = insertelement <16 x i1> undef, i1 1, i32 0 %allones = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer @@ -100,8 +100,8 @@ define <16 x i8> @test_vp_zext_masked_v16i8_v16i1(<16 x i1> %op, <16 x i1> %mask ; CHECK-LABEL: test_vp_zext_masked_v16i8_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %x = call <16 x i8> @llvm.vp.zext.v16i8.v16i1(<16 x i1> %op, <16 x i1> %mask, i32 %evl) ret <16 x i8> %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-zext-masks.ll b/llvm/test/CodeGen/RISCV/epi-vp-zext-masks.ll index c5f077fdfb80f1b5928de648fbc7bdd10c4b0034..fe6be4e289a21f67f369731f27f563ec5e0592f6 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-zext-masks.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-zext-masks.ll @@ -36,8 +36,8 @@ define @test_vp_zext_nxv8i32_nxv8i1( %op, i3 ; CHECK-LABEL: test_vp_zext_nxv8i32_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -50,8 +50,8 @@ define @test_vp_zext_masked_nxv8i32_nxv8i1( ; CHECK-LABEL: test_vp_zext_masked_nxv8i32_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %x = call @llvm.vp.zext.nxv8i32.nxv8i1( %op, %mask, i32 %evl) ret %x @@ -61,8 +61,8 @@ define @test_vp_zext_nxv8i16_nxv8i1( %op, i3 ; CHECK-LABEL: test_vp_zext_nxv8i16_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -75,8 +75,8 @@ define @test_vp_zext_masked_nxv8i16_nxv8i1( ; CHECK-LABEL: test_vp_zext_masked_nxv8i16_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %x = call @llvm.vp.zext.nxv8i16.nxv8i1( %op, %mask, i32 %evl) ret %x @@ -86,8 +86,8 @@ define @test_vp_zext_nxv8i8_nxv8i1( %op, i32 ; CHECK-LABEL: test_vp_zext_nxv8i8_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer @@ -100,8 +100,8 @@ define @test_vp_zext_masked_nxv8i8_nxv8i1( %o ; CHECK-LABEL: test_vp_zext_masked_nxv8i8_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %x = call @llvm.vp.zext.nxv8i8.nxv8i1( %op, %mask, i32 %evl) ret %x diff --git a/llvm/test/CodeGen/RISCV/epi-vp-zext.ll b/llvm/test/CodeGen/RISCV/epi-vp-zext.ll index 04b8eed5ff3834e3fc8bfc8d4471e98d193e676a..752b1052dc310702ee934cb011f10c8d3e7631e6 100644 --- a/llvm/test/CodeGen/RISCV/epi-vp-zext.ll +++ b/llvm/test/CodeGen/RISCV/epi-vp-zext.ll @@ -6,8 +6,8 @@ define @zext.i64.i32( %a, i32 zeroext %gvl) ; CHECK-LABEL: zext.i64.i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret { %b = call @llvm.vp.zext.nxv2i64.nxv2i32( %a, @@ -20,8 +20,8 @@ define @zext.i64.i32.mask( %a, @llvm.vp.zext.nxv2i64.nxv2i32( @@ -37,8 +37,8 @@ define @test_vp_zext_nxv4i32_nxv4i8( %a, i32 ; CHECK-LABEL: test_vp_zext_nxv4i32_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -50,8 +50,8 @@ define @test_vp_zext_masked_nxv4i32_nxv4i8( ; CHECK-LABEL: test_vp_zext_masked_nxv4i32_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf4 v26, v8, v0.t -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf4 v10, v8, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %x = call @llvm.vp.zext.nxv4i32.nxv4i8( %a, %mask, i32 %evl) ret %x @@ -61,8 +61,8 @@ define @test_vp_zext_nxv4i64_nxv4i8( %a, i32 ; CHECK-LABEL: test_vp_zext_nxv4i64_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf8 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer @@ -74,8 +74,8 @@ define @test_vp_zext_masked_nxv4i64_nxv4i8( ; CHECK-LABEL: test_vp_zext_masked_nxv4i64_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v28, v8, v0.t -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf8 v12, v8, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %x = call @llvm.vp.zext.nxv4i64.nxv4i8( %a, %mask, i32 %evl) ret %x @@ -85,8 +85,8 @@ define @test_vp_zext_nxv4i64_nxv4i16( %a, i ; CHECK-LABEL: test_vp_zext_nxv4i64_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %m.first = insertelement undef, i1 1, i32 0 %m.splat = shufflevector %m.first, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/epi-vsetvl-chain.ll b/llvm/test/CodeGen/RISCV/epi-vsetvl-chain.ll index 64a6faeefc220ef6f90b47b4ec4c070c36efcfe5..861a4616c8be76366d405a4528f995ebb11afd46 100644 --- a/llvm/test/CodeGen/RISCV/epi-vsetvl-chain.ll +++ b/llvm/test/CodeGen/RISCV/epi-vsetvl-chain.ll @@ -41,13 +41,13 @@ define void @test_vsetvl_chain(* %v, i64 %avl) nounwind ; CHECK-O0-NEXT: vsetvli a1, a1, e64, m1, ta, mu ; CHECK-O0-NEXT: vsetvli a1, a1, e64, m1, ta, mu ; CHECK-O0-NEXT: vsetvli a1, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: # implicit-def: $v26 -; CHECK-O0-NEXT: vle64.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vfadd.vv v25, v26, v26 +; CHECK-O0-NEXT: # implicit-def: $v9 +; CHECK-O0-NEXT: vle64.v v9, (a0) +; CHECK-O0-NEXT: # implicit-def: $v8 +; CHECK-O0-NEXT: vfadd.vv v8, v9, v9 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O0-NEXT: vse64.v v25, (a0) +; CHECK-O0-NEXT: vse64.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vsetvl_chain: @@ -62,11 +62,11 @@ define void @test_vsetvl_chain(* %v, i64 %avl) nounwind ; CHECK-O2-NEXT: vsetvli a1, a1, e64, m1, ta, mu ; CHECK-O2-NEXT: vsetvli a1, a1, e64, m1, ta, mu ; CHECK-O2-NEXT: vsetvli a1, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vle64.v v25, (a0) -; CHECK-O2-NEXT: vfadd.vv v25, v25, v25 +; CHECK-O2-NEXT: vle64.v v8, (a0) +; CHECK-O2-NEXT: vfadd.vv v8, v8, v8 ; CHECK-O2-NEXT: lui a0, %hi(scratch) ; CHECK-O2-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O2-NEXT: vse64.v v25, (a0) +; CHECK-O2-NEXT: vse64.v v8, (a0) ; CHECK-O2-NEXT: ret { %gvl1 = call i64 @llvm.epi.vsetvl(i64 %avl, i64 3, i64 0) @@ -106,13 +106,13 @@ define void @test_vsetvl_chain_2(* %v, i64 %avl) nounwind ; CHECK-O0-NEXT: vsetvli a1, a1, e64, m1, ta, mu ; CHECK-O0-NEXT: vsetvli a1, a1, e64, m1, ta, mu ; CHECK-O0-NEXT: vsetvli a1, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: # implicit-def: $v26 -; CHECK-O0-NEXT: vle64.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vfadd.vv v25, v26, v26 +; CHECK-O0-NEXT: # implicit-def: $v9 +; CHECK-O0-NEXT: vle64.v v9, (a0) +; CHECK-O0-NEXT: # implicit-def: $v8 +; CHECK-O0-NEXT: vfadd.vv v8, v9, v9 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O0-NEXT: vse64.v v25, (a0) +; CHECK-O0-NEXT: vse64.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vsetvl_chain_2: @@ -121,11 +121,11 @@ define void @test_vsetvl_chain_2(* %v, i64 %avl) nounwind ; CHECK-O2-NEXT: vsetvli a1, a1, e64, m1, ta, mu ; CHECK-O2-NEXT: vsetvli a1, a1, e64, m1, ta, mu ; CHECK-O2-NEXT: vsetvli a1, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vle64.v v25, (a0) -; CHECK-O2-NEXT: vfadd.vv v25, v25, v25 +; CHECK-O2-NEXT: vle64.v v8, (a0) +; CHECK-O2-NEXT: vfadd.vv v8, v8, v8 ; CHECK-O2-NEXT: lui a0, %hi(scratch) ; CHECK-O2-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O2-NEXT: vse64.v v25, (a0) +; CHECK-O2-NEXT: vse64.v v8, (a0) ; CHECK-O2-NEXT: ret { %gvl1 = call i64 @llvm.epi.vsetvl(i64 %avl, i64 3, i64 0) @@ -162,23 +162,23 @@ define void @test_vsetvl_chain_3(* %v, i64 %avl) nounwind ; CHECK-O0-LABEL: test_vsetvl_chain_3: ; CHECK-O0: # %bb.0: ; CHECK-O0-NEXT: vsetvli a1, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: # implicit-def: $v26 -; CHECK-O0-NEXT: vle64.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vfadd.vv v25, v26, v26 +; CHECK-O0-NEXT: # implicit-def: $v9 +; CHECK-O0-NEXT: vle64.v v9, (a0) +; CHECK-O0-NEXT: # implicit-def: $v8 +; CHECK-O0-NEXT: vfadd.vv v8, v9, v9 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O0-NEXT: vse64.v v25, (a0) +; CHECK-O0-NEXT: vse64.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vsetvl_chain_3: ; CHECK-O2: # %bb.0: ; CHECK-O2-NEXT: vsetvli a1, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vle64.v v25, (a0) -; CHECK-O2-NEXT: vfadd.vv v25, v25, v25 +; CHECK-O2-NEXT: vle64.v v8, (a0) +; CHECK-O2-NEXT: vfadd.vv v8, v8, v8 ; CHECK-O2-NEXT: lui a0, %hi(scratch) ; CHECK-O2-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O2-NEXT: vse64.v v25, (a0) +; CHECK-O2-NEXT: vse64.v v8, (a0) ; CHECK-O2-NEXT: ret { %gvl1 = call i64 @llvm.epi.vsetvl(i64 %avl, i64 1, i64 0) @@ -227,13 +227,13 @@ define void @test_vsetvl_chain_4(* %v, i64 %avl) nounwind ; CHECK-O0-NEXT: vsetvli a1, a1, e64, m2, ta, mu ; CHECK-O0-NEXT: vsetvli a1, a1, e32, m1, ta, mu ; CHECK-O0-NEXT: vsetvli a1, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: # implicit-def: $v26 -; CHECK-O0-NEXT: vle64.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vfadd.vv v25, v26, v26 +; CHECK-O0-NEXT: # implicit-def: $v9 +; CHECK-O0-NEXT: vle64.v v9, (a0) +; CHECK-O0-NEXT: # implicit-def: $v8 +; CHECK-O0-NEXT: vfadd.vv v8, v9, v9 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O0-NEXT: vse64.v v25, (a0) +; CHECK-O0-NEXT: vse64.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vsetvl_chain_4: @@ -254,11 +254,11 @@ define void @test_vsetvl_chain_4(* %v, i64 %avl) nounwind ; CHECK-O2-NEXT: vsetvli a1, a1, e64, m2, ta, mu ; CHECK-O2-NEXT: vsetvli a1, a1, e32, m1, ta, mu ; CHECK-O2-NEXT: vsetvli a1, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vle64.v v25, (a0) -; CHECK-O2-NEXT: vfadd.vv v25, v25, v25 +; CHECK-O2-NEXT: vle64.v v8, (a0) +; CHECK-O2-NEXT: vfadd.vv v8, v8, v8 ; CHECK-O2-NEXT: lui a0, %hi(scratch) ; CHECK-O2-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O2-NEXT: vse64.v v25, (a0) +; CHECK-O2-NEXT: vse64.v v8, (a0) ; CHECK-O2-NEXT: ret { ; FIXME this test case is yet to be optimized diff --git a/llvm/test/CodeGen/RISCV/epi-vsetvl-global.ll b/llvm/test/CodeGen/RISCV/epi-vsetvl-global.ll index f01ab328a4c4f668f31404bb20bfaec7ef191a75..faad0dcbbaa99fc72bf8e0413571f3c553b49ecd 100644 --- a/llvm/test/CodeGen/RISCV/epi-vsetvl-global.ll +++ b/llvm/test/CodeGen/RISCV/epi-vsetvl-global.ll @@ -61,12 +61,12 @@ define @test2(i64 %avl, i8 zeroext %cond, @test3(i64 %avl, i8 zeroext %cond, @test4(i64 %avl, i8 zeroext %cond, @test4(i64 %avl, i8 zeroext %cond, @test5(i64 %avl, i8 zeroext %cond, @test6(i64 %avl, i8 zeroext %cond, @test6(i64 %avl, i8 zeroext %cond, @test6(i64 %avl, i8 zeroext %cond, @test7(i64 %avl, i8 zeroext %cond, @test7(i64 %avl, i8 zeroext %cond, @test8(i64 %avl, float %cond, ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vsetvli a3, a0, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a2) -; CHECK-NEXT: vfmv.f.s ft1, v25 +; CHECK-NEXT: vle32.v v10, (a2) +; CHECK-NEXT: vfmv.f.s ft1, v10 ; CHECK-NEXT: j .LBB7_1 ; CHECK-NEXT: .LBB7_4: # %do.end ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/epi-vsetvl-interleave.ll b/llvm/test/CodeGen/RISCV/epi-vsetvl-interleave.ll index 61f3245dfb8b1d0d475a67c2d8ec560b74bf84f0..14e7136738332d6c823ea74ab192bea81fd6d6c9 100644 --- a/llvm/test/CodeGen/RISCV/epi-vsetvl-interleave.ll +++ b/llvm/test/CodeGen/RISCV/epi-vsetvl-interleave.ll @@ -63,24 +63,24 @@ define void @test_vsetvl_interleave_sew(* %vd, * %vd, * %vm1, * %vm1, * %v, i64 %avl) nounwind ; CHECK-O0-NEXT: rdvtype t0 ; CHECK-O0-NEXT: vsetvl zero, a2, t0 ; CHECK-O0-NEXT: #NO_APP -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O0-NEXT: vle64.v v26, (a0) -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vfadd.vv v25, v26, v26 +; CHECK-O0-NEXT: vle64.v v9, (a0) +; CHECK-O0-NEXT: # implicit-def: $v8 +; CHECK-O0-NEXT: vfadd.vv v8, v9, v9 ; CHECK-O0-NEXT: lui a0, %hi(scratch) ; CHECK-O0-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O0-NEXT: vse64.v v25, (a0) +; CHECK-O0-NEXT: vse64.v v8, (a0) ; CHECK-O0-NEXT: ret ; ; CHECK-O2-LABEL: test_vsetvl_vtype: ; CHECK-O2: # %bb.0: ; CHECK-O2-NEXT: vsetvli a1, a1, e64, m1, ta, mu ; CHECK-O2-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-O2-NEXT: vle64.v v25, (a0) +; CHECK-O2-NEXT: vle64.v v8, (a0) ; CHECK-O2-NEXT: srli a0, a1, 1 ; CHECK-O2-NEXT: #APP ; CHECK-O2-NEXT: rdvtype t0 ; CHECK-O2-NEXT: vsetvl zero, a0, t0 ; CHECK-O2-NEXT: #NO_APP -; CHECK-O2-NEXT: vfadd.vv v25, v25, v25 +; CHECK-O2-NEXT: vfadd.vv v8, v8, v8 ; CHECK-O2-NEXT: lui a0, %hi(scratch) ; CHECK-O2-NEXT: addi a0, a0, %lo(scratch) -; CHECK-O2-NEXT: vse64.v v25, (a0) +; CHECK-O2-NEXT: vse64.v v8, (a0) ; CHECK-O2-NEXT: ret { %gvl = call i64 @llvm.epi.vsetvl( diff --git a/llvm/test/CodeGen/RISCV/epi-vsetvl_ext-IR-infinite-loop.ll b/llvm/test/CodeGen/RISCV/epi-vsetvl_ext-IR-infinite-loop.ll index 938d4db488fcb69861833f1dafe0e130ade103e4..7fe9b1522bfd6cb8c7efb92258e99f1dbbac9033 100644 --- a/llvm/test/CodeGen/RISCV/epi-vsetvl_ext-IR-infinite-loop.ll +++ b/llvm/test/CodeGen/RISCV/epi-vsetvl_ext-IR-infinite-loop.ll @@ -54,15 +54,15 @@ define void @test_llvm_IR_infinite_loop(i64 %n, double* %a, double* %b, double* ; CHECK-O0-NEXT: ld a2, 24(sp) # 8-byte Folded Reload ; CHECK-O0-NEXT: ld a3, 16(sp) # 8-byte Folded Reload ; CHECK-O0-NEXT: ld a4, 8(sp) # 8-byte Folded Reload -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: ori a5, a4, 88 ; CHECK-O0-NEXT: vsetvl a4, a3, a5 -; CHECK-O0-NEXT: vle64.v v26, (a2) -; CHECK-O0-NEXT: # implicit-def: $v27 -; CHECK-O0-NEXT: vle64.v v27, (a1) -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vfadd.vv v25, v26, v27 -; CHECK-O0-NEXT: vse64.v v25, (a0) +; CHECK-O0-NEXT: vle64.v v9, (a2) +; CHECK-O0-NEXT: # implicit-def: $v10 +; CHECK-O0-NEXT: vle64.v v10, (a1) +; CHECK-O0-NEXT: # implicit-def: $v8 +; CHECK-O0-NEXT: vfadd.vv v8, v9, v10 +; CHECK-O0-NEXT: vse64.v v8, (a0) ; CHECK-O0-NEXT: slli a3, a3, 3 ; CHECK-O0-NEXT: add a2, a2, a3 ; CHECK-O0-NEXT: add a1, a1, a3 @@ -93,12 +93,12 @@ define void @test_llvm_IR_infinite_loop(i64 %n, double* %a, double* %b, double* ; CHECK-O2-NEXT: add t1, a1, a5 ; CHECK-O2-NEXT: ori a0, a6, 88 ; CHECK-O2-NEXT: vsetvl a4, a7, a0 -; CHECK-O2-NEXT: vle64.v v25, (t1) +; CHECK-O2-NEXT: vle64.v v8, (t1) ; CHECK-O2-NEXT: add a0, a2, a5 -; CHECK-O2-NEXT: vle64.v v26, (a0) -; CHECK-O2-NEXT: vfadd.vv v25, v25, v26 +; CHECK-O2-NEXT: vle64.v v9, (a0) +; CHECK-O2-NEXT: vfadd.vv v8, v8, v9 ; CHECK-O2-NEXT: add a0, a3, a5 -; CHECK-O2-NEXT: vse64.v v25, (a0) +; CHECK-O2-NEXT: vse64.v v8, (a0) ; CHECK-O2-NEXT: add a5, a5, t0 ; CHECK-O2-NEXT: j .LBB0_4 ; CHECK-O2-NEXT: .LBB0_5: # %for.cond.cleanup diff --git a/llvm/test/CodeGen/RISCV/epi-vsetvl_ext-blocks-merging.ll b/llvm/test/CodeGen/RISCV/epi-vsetvl_ext-blocks-merging.ll index 33c528bf5049b932d70eeed4981554588bc48997..34cd29ed26ffbd172ae2592af803a5b7e2161cd0 100644 --- a/llvm/test/CodeGen/RISCV/epi-vsetvl_ext-blocks-merging.ll +++ b/llvm/test/CodeGen/RISCV/epi-vsetvl_ext-blocks-merging.ll @@ -10,15 +10,15 @@ define void @test_preserve_extra(i64 %rvl, i64 %extra, i64 %x, This Inner Loop Header: Depth=1 @@ -376,20 +376,20 @@ define void @test_extra_from_gvl_from_phi_from_temp_register(i64 %n, double* %a, ; CHECK-O0-NEXT: ld a0, 24(sp) # 8-byte Folded Reload ; CHECK-O0-NEXT: slli a5, a2, 3 ; CHECK-O0-NEXT: add t0, t0, a5 -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: ori t2, a4, 88 ; CHECK-O0-NEXT: vsetvl t1, a0, t2 -; CHECK-O0-NEXT: vle64.v v26, (t0) +; CHECK-O0-NEXT: vle64.v v9, (t0) ; CHECK-O0-NEXT: vsetvli a7, a7, e64, m1, ta, mu ; CHECK-O0-NEXT: add a6, a6, a5 -; CHECK-O0-NEXT: # implicit-def: $v27 -; CHECK-O0-NEXT: vle64.v v27, (a6) -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vfadd.vv v25, v26, v27 +; CHECK-O0-NEXT: # implicit-def: $v10 +; CHECK-O0-NEXT: vle64.v v10, (a6) +; CHECK-O0-NEXT: # implicit-def: $v8 +; CHECK-O0-NEXT: vfadd.vv v8, v9, v10 ; CHECK-O0-NEXT: add a3, a3, a5 ; CHECK-O0-NEXT: ori a5, a4, 88 ; CHECK-O0-NEXT: vsetvl a4, a0, a5 -; CHECK-O0-NEXT: vse64.v v25, (a3) +; CHECK-O0-NEXT: vse64.v v8, (a3) ; CHECK-O0-NEXT: add a0, a0, a2 ; CHECK-O0-NEXT: mv a2, a0 ; CHECK-O0-NEXT: sd a2, 40(sp) # 8-byte Folded Spill @@ -416,16 +416,16 @@ define void @test_extra_from_gvl_from_phi_from_temp_register(i64 %n, double* %a, ; CHECK-O2-NEXT: add t2, a1, t3 ; CHECK-O2-NEXT: ori a5, a7, 88 ; CHECK-O2-NEXT: vsetvl a4, t1, a5 -; CHECK-O2-NEXT: vle64.v v25, (t2) +; CHECK-O2-NEXT: vle64.v v8, (t2) ; CHECK-O2-NEXT: vsetvli a4, t0, e64, m1, ta, mu ; CHECK-O2-NEXT: add a4, a2, t3 -; CHECK-O2-NEXT: vle64.v v26, (a4) -; CHECK-O2-NEXT: vfadd.vv v25, v25, v26 +; CHECK-O2-NEXT: vle64.v v9, (a4) +; CHECK-O2-NEXT: vfadd.vv v8, v8, v9 ; CHECK-O2-NEXT: add t0, a3, t3 ; CHECK-O2-NEXT: ori a4, a7, 88 ; CHECK-O2-NEXT: vsetvl a5, t1, a4 ; CHECK-O2-NEXT: add t4, t1, t4 -; CHECK-O2-NEXT: vse64.v v25, (t0) +; CHECK-O2-NEXT: vse64.v v8, (t0) ; CHECK-O2-NEXT: bge t4, a0, .LBB2_7 ; CHECK-O2-NEXT: .LBB2_5: # %for.body ; CHECK-O2-NEXT: # =>This Inner Loop Header: Depth=1 diff --git a/llvm/test/CodeGen/RISCV/epi-vsetvl_ext-nested-branching.ll b/llvm/test/CodeGen/RISCV/epi-vsetvl_ext-nested-branching.ll index bd722ce302cb8c8fc8d3bb9f9f9e60eb75e7af59..0eb8c30bb11e8e798f50833de48d66c9e101b270 100644 --- a/llvm/test/CodeGen/RISCV/epi-vsetvl_ext-nested-branching.ll +++ b/llvm/test/CodeGen/RISCV/epi-vsetvl_ext-nested-branching.ll @@ -64,15 +64,15 @@ define void @test_nested_branching(i64 %rvl, i64 %extra1, i64 %extra2, double* % ; CHECK-O0-NEXT: ld a2, 48(sp) # 8-byte Folded Reload ; CHECK-O0-NEXT: ld a5, 0(sp) # 8-byte Folded Reload ; CHECK-O0-NEXT: ld a3, 8(sp) # 8-byte Folded Reload -; CHECK-O0-NEXT: # implicit-def: $v26 +; CHECK-O0-NEXT: # implicit-def: $v9 ; CHECK-O0-NEXT: ori a4, a5, 88 ; CHECK-O0-NEXT: vsetvl a3, a3, a4 -; CHECK-O0-NEXT: vle64.v v26, (a2) -; CHECK-O0-NEXT: # implicit-def: $v27 -; CHECK-O0-NEXT: vle64.v v27, (a1) -; CHECK-O0-NEXT: # implicit-def: $v25 -; CHECK-O0-NEXT: vfadd.vv v25, v26, v27 -; CHECK-O0-NEXT: vse64.v v25, (a0) +; CHECK-O0-NEXT: vle64.v v9, (a2) +; CHECK-O0-NEXT: # implicit-def: $v10 +; CHECK-O0-NEXT: vle64.v v10, (a1) +; CHECK-O0-NEXT: # implicit-def: $v8 +; CHECK-O0-NEXT: vfadd.vv v8, v9, v10 +; CHECK-O0-NEXT: vse64.v v8, (a0) ; CHECK-O0-NEXT: addi sp, sp, 80 ; CHECK-O0-NEXT: ret ; @@ -104,10 +104,10 @@ define void @test_nested_branching(i64 %rvl, i64 %extra1, i64 %extra2, double* % ; CHECK-O2-NEXT: .LBB0_6: # %if.end4 ; CHECK-O2-NEXT: ori a1, a2, 88 ; CHECK-O2-NEXT: vsetvl a0, a0, a1 -; CHECK-O2-NEXT: vle64.v v25, (a3) -; CHECK-O2-NEXT: vle64.v v26, (a4) -; CHECK-O2-NEXT: vfadd.vv v25, v25, v26 -; CHECK-O2-NEXT: vse64.v v25, (a5) +; CHECK-O2-NEXT: vle64.v v8, (a3) +; CHECK-O2-NEXT: vle64.v v9, (a4) +; CHECK-O2-NEXT: vfadd.vv v8, v8, v9 +; CHECK-O2-NEXT: vse64.v v8, (a5) ; CHECK-O2-NEXT: ret entry: %cmp = icmp sgt i64 %rvl, 44 diff --git a/llvm/test/CodeGen/RISCV/epi-vzip2-vunzip2-vtrn.ll b/llvm/test/CodeGen/RISCV/epi-vzip2-vunzip2-vtrn.ll index f556eecf497ab71bcdedf868c553157cf387d0d7..656f33f79c8a7e9529d31245fe6bdf6579dcff0e 100644 --- a/llvm/test/CodeGen/RISCV/epi-vzip2-vunzip2-vtrn.ll +++ b/llvm/test/CodeGen/RISCV/epi-vzip2-vunzip2-vtrn.ll @@ -24,9 +24,9 @@ define void @vzip2.test.nxv1i64(i64* nocapture readonly %in_a0, i64* nocapture r ; CHECK-LABEL: vzip2.test.nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a4, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vzip2.vv v0, v25, v26 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vzip2.vv v0, v8, v9 ; CHECK-NEXT: vse64.v v0, (a2) ; CHECK-NEXT: vse64.v v1, (a3) ; CHECK-NEXT: ret @@ -49,9 +49,9 @@ define void @vunzip2.test.nxv1i64(i64* nocapture readonly %in_a0, i64* nocapture ; CHECK-LABEL: vunzip2.test.nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a4, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vunzip2.vv v0, v25, v26 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vunzip2.vv v0, v8, v9 ; CHECK-NEXT: vse64.v v0, (a2) ; CHECK-NEXT: vse64.v v1, (a3) ; CHECK-NEXT: ret @@ -74,9 +74,9 @@ define void @vtrn.test.nxv1i64(i64* nocapture readonly %in_a0, i64* nocapture re ; CHECK-LABEL: vtrn.test.nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a4, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vtrn.vv v0, v25, v26 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vtrn.vv v0, v8, v9 ; CHECK-NEXT: vse64.v v0, (a2) ; CHECK-NEXT: vse64.v v1, (a3) ; CHECK-NEXT: ret @@ -99,9 +99,9 @@ define void @vzip2.test.nxv2i32(i32* nocapture readonly %in_a0, i32* nocapture r ; CHECK-LABEL: vzip2.test.nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vzip2.vv v0, v25, v26 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vzip2.vv v0, v8, v9 ; CHECK-NEXT: vse32.v v0, (a2) ; CHECK-NEXT: vse32.v v1, (a3) ; CHECK-NEXT: ret @@ -124,9 +124,9 @@ define void @vunzip2.test.nxv2i32(i32* nocapture readonly %in_a0, i32* nocapture ; CHECK-LABEL: vunzip2.test.nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vunzip2.vv v0, v25, v26 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vunzip2.vv v0, v8, v9 ; CHECK-NEXT: vse32.v v0, (a2) ; CHECK-NEXT: vse32.v v1, (a3) ; CHECK-NEXT: ret @@ -149,9 +149,9 @@ define void @vtrn.test.nxv2i32(i32* nocapture readonly %in_a0, i32* nocapture re ; CHECK-LABEL: vtrn.test.nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vtrn.vv v0, v25, v26 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vtrn.vv v0, v8, v9 ; CHECK-NEXT: vse32.v v0, (a2) ; CHECK-NEXT: vse32.v v1, (a3) ; CHECK-NEXT: ret @@ -174,9 +174,9 @@ define void @vzip2.test.nxv1f64(double* nocapture readonly %in_a0, double* nocap ; CHECK-LABEL: vzip2.test.nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a4, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vzip2.vv v0, v25, v26 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vzip2.vv v0, v8, v9 ; CHECK-NEXT: vse64.v v0, (a2) ; CHECK-NEXT: vse64.v v1, (a3) ; CHECK-NEXT: ret @@ -199,9 +199,9 @@ define void @vunzip2.test.nxv1f64(double* nocapture readonly %in_a0, double* noc ; CHECK-LABEL: vunzip2.test.nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a4, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vunzip2.vv v0, v25, v26 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vunzip2.vv v0, v8, v9 ; CHECK-NEXT: vse64.v v0, (a2) ; CHECK-NEXT: vse64.v v1, (a3) ; CHECK-NEXT: ret @@ -224,9 +224,9 @@ define void @vtrn.test.nxv1f64(double* nocapture readonly %in_a0, double* nocapt ; CHECK-LABEL: vtrn.test.nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a4, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vtrn.vv v0, v25, v26 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vtrn.vv v0, v8, v9 ; CHECK-NEXT: vse64.v v0, (a2) ; CHECK-NEXT: vse64.v v1, (a3) ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/epi-zext-illegal-vectors.ll b/llvm/test/CodeGen/RISCV/epi-zext-illegal-vectors.ll index a295ecab80a77933098e8a024fccd6cce124b44a..573f294ff349af82d948e69dfa739b559e37b556 100644 --- a/llvm/test/CodeGen/RISCV/epi-zext-illegal-vectors.ll +++ b/llvm/test/CodeGen/RISCV/epi-zext-illegal-vectors.ll @@ -24,8 +24,8 @@ define @zext_nxv1i8( %v) ; CHECK-LABEL: zext_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf8 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf8 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %sv = zext %v to @@ -35,8 +35,8 @@ define @zext_nxv2i8( %v) ; CHECK-LABEL: zext_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %sv = zext %v to @@ -46,8 +46,8 @@ define @zext_nxv4i8( %v) ; CHECK-LABEL: zext_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %sv = zext %v to @@ -59,8 +59,8 @@ define @zext_nxv1i16( %v) ; CHECK-LABEL: zext_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %sv = zext %v to @@ -70,8 +70,8 @@ define @zext_nxv2i16( %v) ; CHECK-LABEL: zext_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %sv = zext %v to @@ -83,8 +83,8 @@ define @zext_nxv1i32( %v) ; CHECK-LABEL: zext_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret { %sv = zext %v to diff --git a/llvm/test/CodeGen/RISCV/epi-zext-quad-octa.ll b/llvm/test/CodeGen/RISCV/epi-zext-quad-octa.ll index 0a49891bc5599debe1d0d5d7c07ebaaf919dae3c..ebc239c0f42a8e0474cb8dcf98b91db538ba25c4 100644 --- a/llvm/test/CodeGen/RISCV/epi-zext-quad-octa.ll +++ b/llvm/test/CodeGen/RISCV/epi-zext-quad-octa.ll @@ -7,8 +7,8 @@ define @test_zext_i8_i32_m1( %a) nounwind ; CHECK-LABEL: test_zext_i8_i32_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret { %b = zext %a to @@ -33,8 +33,8 @@ define @test_zext_i16_i64_m1( %a) nounwind ; CHECK-LABEL: test_zext_i16_i64_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret { %b = zext %a to diff --git a/llvm/test/CodeGen/RISCV/epi-zext.ll b/llvm/test/CodeGen/RISCV/epi-zext.ll index cda7b324077cb3d1e397dd42127e0ec441d51097..6265a2a2ca46d4797bf5edc4f082ff1a028e24bb 100644 --- a/llvm/test/CodeGen/RISCV/epi-zext.ll +++ b/llvm/test/CodeGen/RISCV/epi-zext.ll @@ -7,8 +7,8 @@ define @test_zext_i32_i64_m1( %a) nounwind ; CHECK-LABEL: test_zext_i32_i64_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret { %b = zext %a to @@ -19,8 +19,8 @@ define @test_zext_i32_i64_m2( %a) nounwind ; CHECK-LABEL: test_zext_i32_i64_m2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret { %b = zext %a to @@ -44,8 +44,8 @@ define @test_zext_i16_i32_m1( %a) nounwind ; CHECK-LABEL: test_zext_i16_i32_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret { %b = zext %a to @@ -56,8 +56,8 @@ define @test_zext_i16_i32_m2( %a) nounwind ; CHECK-LABEL: test_zext_i16_i32_m2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret { %b = zext %a to @@ -81,8 +81,8 @@ define @test_zext_i8_i16_m1( %a) nounwind ; CHECK-LABEL: test_zext_i8_i16_m1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret { %b = zext %a to @@ -93,8 +93,8 @@ define @test_zext_i8_i16_m2( %a) nounwind ; CHECK-LABEL: test_zext_i8_i16_m2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret { %b = zext %a to diff --git a/llvm/test/CodeGen/RISCV/fastcc-int.ll b/llvm/test/CodeGen/RISCV/fastcc-int.ll index 8b240dc8a6355a471743aa0784bbb0156242531f..363fd5d3cc734cda1ef4b5955ee3f294009b9f8a 100644 --- a/llvm/test/CodeGen/RISCV/fastcc-int.ll +++ b/llvm/test/CodeGen/RISCV/fastcc-int.ll @@ -44,7 +44,7 @@ define i32 @caller(<16 x i32> %A) nounwind { ; RV32-NEXT: sw s0, 4(sp) ; RV32-NEXT: sw t1, 0(sp) ; RV32-NEXT: mv a0, t0 -; RV32-NEXT: call callee +; RV32-NEXT: call callee@plt ; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 32 @@ -75,7 +75,7 @@ define i32 @caller(<16 x i32> %A) nounwind { ; RV64-NEXT: sd s0, 8(sp) ; RV64-NEXT: sd t1, 0(sp) ; RV64-NEXT: mv a0, t0 -; RV64-NEXT: call callee +; RV64-NEXT: call callee@plt ; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 48 diff --git a/llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll index f7ce4ce98b5e6fe98c628e261a21905f2b41c100..575a09b7922b9e9b9063010dd1917f4688a2d37c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll @@ -8,8 +8,8 @@ define @vabs_nxv1i16( %v) { ; CHECK-LABEL: vabs_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vrsub.vi v25, v8, 0 -; CHECK-NEXT: vmax.vv v8, v8, v25 +; CHECK-NEXT: vrsub.vi v9, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv1i16( %v, i1 false) ret %r @@ -21,8 +21,8 @@ define @vabs_nxv2i16( %v) { ; CHECK-LABEL: vabs_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vrsub.vi v25, v8, 0 -; CHECK-NEXT: vmax.vv v8, v8, v25 +; CHECK-NEXT: vrsub.vi v9, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv2i16( %v, i1 false) ret %r @@ -34,8 +34,8 @@ define @vabs_nxv4i16( %v) { ; CHECK-LABEL: vabs_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vrsub.vi v25, v8, 0 -; CHECK-NEXT: vmax.vv v8, v8, v25 +; CHECK-NEXT: vrsub.vi v9, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv4i16( %v, i1 false) ret %r @@ -47,8 +47,8 @@ define @vabs_nxv8i16( %v) { ; CHECK-LABEL: vabs_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vrsub.vi v26, v8, 0 -; CHECK-NEXT: vmax.vv v8, v8, v26 +; CHECK-NEXT: vrsub.vi v10, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv8i16( %v, i1 false) ret %r @@ -60,8 +60,8 @@ define @vabs_nxv16i16( %v) { ; CHECK-LABEL: vabs_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vrsub.vi v28, v8, 0 -; CHECK-NEXT: vmax.vv v8, v8, v28 +; CHECK-NEXT: vrsub.vi v12, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv16i16( %v, i1 false) ret %r @@ -86,8 +86,8 @@ define @vabs_nxv1i32( %v) { ; CHECK-LABEL: vabs_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vrsub.vi v25, v8, 0 -; CHECK-NEXT: vmax.vv v8, v8, v25 +; CHECK-NEXT: vrsub.vi v9, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv1i32( %v, i1 false) ret %r @@ -99,8 +99,8 @@ define @vabs_nxv2i32( %v) { ; CHECK-LABEL: vabs_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vrsub.vi v25, v8, 0 -; CHECK-NEXT: vmax.vv v8, v8, v25 +; CHECK-NEXT: vrsub.vi v9, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv2i32( %v, i1 false) ret %r @@ -112,8 +112,8 @@ define @vabs_nxv4i32( %v) { ; CHECK-LABEL: vabs_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vrsub.vi v26, v8, 0 -; CHECK-NEXT: vmax.vv v8, v8, v26 +; CHECK-NEXT: vrsub.vi v10, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv4i32( %v, i1 false) ret %r @@ -125,8 +125,8 @@ define @vabs_nxv8i32( %v) { ; CHECK-LABEL: vabs_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vrsub.vi v28, v8, 0 -; CHECK-NEXT: vmax.vv v8, v8, v28 +; CHECK-NEXT: vrsub.vi v12, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv8i32( %v, i1 false) ret %r @@ -151,8 +151,8 @@ define @vabs_nxv1i64( %v) { ; CHECK-LABEL: vabs_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vrsub.vi v25, v8, 0 -; CHECK-NEXT: vmax.vv v8, v8, v25 +; CHECK-NEXT: vrsub.vi v9, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv1i64( %v, i1 false) ret %r @@ -164,8 +164,8 @@ define @vabs_nxv2i64( %v) { ; CHECK-LABEL: vabs_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vrsub.vi v26, v8, 0 -; CHECK-NEXT: vmax.vv v8, v8, v26 +; CHECK-NEXT: vrsub.vi v10, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv2i64( %v, i1 false) ret %r @@ -177,8 +177,8 @@ define @vabs_nxv4i64( %v) { ; CHECK-LABEL: vabs_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vrsub.vi v28, v8, 0 -; CHECK-NEXT: vmax.vv v8, v8, v28 +; CHECK-NEXT: vrsub.vi v12, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret %r = call @llvm.abs.nxv4i64( %v, i1 false) ret %r diff --git a/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll b/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll index f6de53441a05292500b5f0913635adee5abd983c..e46879448d6c2f00940bf71e9d80be544a7f474a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll @@ -35,12 +35,12 @@ define @access_fixed_and_vector_objects(i64 *%val) { ; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: addi a0, sp, 24 -; RV64IV-NEXT: vl1re64.v v25, (a0) +; RV64IV-NEXT: vl1re64.v v8, (a0) ; RV64IV-NEXT: ld a0, 536(sp) ; RV64IV-NEXT: addi a1, sp, 544 -; RV64IV-NEXT: vl1re64.v v26, (a1) +; RV64IV-NEXT: vl1re64.v v9, (a1) ; RV64IV-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; RV64IV-NEXT: vadd.vv v8, v25, v26 +; RV64IV-NEXT: vadd.vv v8, v8, v9 ; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: add sp, sp, a0 ; RV64IV-NEXT: addi sp, sp, 544 diff --git a/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir b/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir index 5cd831a1d3a3bee072edb7e72ee16a06dd324be3..95286316268100970c5935767d1101c57cbe9e7a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir +++ b/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir @@ -40,13 +40,13 @@ body: | ; CHECK-NEXT: $x12 = frame-setup PseudoReadVLENB ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 88, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: renamable $v25 = PseudoVLE64_V_M1 killed renamable $x10, $noreg, 6, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8) + ; CHECK-NEXT: renamable $v8 = PseudoVLE64_V_M1 killed renamable $x10, $noreg, 6, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8) ; CHECK-NEXT: $x11 = PseudoReadVLENB ; CHECK-NEXT: $x10 = LUI 1048575 ; CHECK-NEXT: $x10 = ADDIW killed $x10, 1824 ; CHECK-NEXT: $x10 = ADD $x8, killed $x10 ; CHECK-NEXT: $x10 = SUB killed $x10, killed $x11 - ; CHECK-NEXT: VS1R_V killed renamable $v25, killed renamable $x10 + ; CHECK-NEXT: VS1R_V killed renamable $v8, killed renamable $x10 ; CHECK-NEXT: $x10 = frame-destroy PseudoReadVLENB ; CHECK-NEXT: $x2 = frame-destroy ADD $x2, killed $x10 ; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 240 diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll b/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll index 468f1a0c2b3202f3451e523b446a7b0169345fc3..0aca89c978c1c82e3e5f6f132321404dd055b1a9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll +++ b/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll @@ -25,8 +25,8 @@ define @or_and_nxv2i64( %a0) { ; CHECK-LABEL: or_and_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vor.vi v26, v8, 3 -; CHECK-NEXT: vand.vi v8, v26, 7 +; CHECK-NEXT: vor.vi v8, v8, 3 +; CHECK-NEXT: vand.vi v8, v8, 7 ; CHECK-NEXT: ret %ins1 = insertelement poison, i64 7, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer @@ -61,11 +61,11 @@ define @combine_vec_shl_shl( %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 2 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: addi a0, zero, 4 -; CHECK-NEXT: vmv.s.x v28, a0 -; CHECK-NEXT: vsll.vv v26, v8, v26 -; CHECK-NEXT: vsll.vv v8, v26, v28 +; CHECK-NEXT: vmv.s.x v12, a0 +; CHECK-NEXT: vsll.vv v8, v8, v10 +; CHECK-NEXT: vsll.vv v8, v8, v12 ; CHECK-NEXT: ret %ins1 = insertelement poison, i32 2, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll b/llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll index 7b3a2bd8def7ecf6884d71c284d607c046145657..b7ef676a672587599aaddd1a6009c3a1afe125ca 100644 --- a/llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll @@ -7,8 +7,8 @@ define void @combine_fp_zero_stores_crash(float* %ptr) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, a0, 4 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %addr1 = getelementptr float, float * %ptr, i64 1 %addr2 = getelementptr float, float * %ptr, i64 2 diff --git a/llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll b/llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll index b24b747a526023110a8d30f6bbdb9c331efbcd5a..a18398c1e2419fe7268c36c12daa9538d758e434 100644 --- a/llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll +++ b/llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll @@ -7,33 +7,33 @@ target triple = "riscv64-unknown-unknown-elf" define dso_local <16 x i16> @interleave(<8 x i16> %v0, <8 x i16> %v1) { ; CHECK-LABEL: interleave: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v26, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8m2 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetivli zero, 8, e16, m2, tu, mu -; CHECK-NEXT: vmv2r.v v30, v28 -; CHECK-NEXT: vslideup.vi v30, v8, 0 +; CHECK-NEXT: vmv2r.v v14, v12 +; CHECK-NEXT: vslideup.vi v14, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, tu, mu -; CHECK-NEXT: vslideup.vi v30, v8, 8 +; CHECK-NEXT: vslideup.vi v14, v8, 8 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vid.v v10 -; CHECK-NEXT: vsrl.vi v12, v10, 1 -; CHECK-NEXT: vrgather.vv v14, v30, v12 +; CHECK-NEXT: vid.v v16 +; CHECK-NEXT: vsrl.vi v18, v16, 1 +; CHECK-NEXT: vrgather.vv v20, v14, v18 ; CHECK-NEXT: vsetivli zero, 8, e16, m2, tu, mu -; CHECK-NEXT: vslideup.vi v28, v26, 0 +; CHECK-NEXT: vslideup.vi v12, v10, 0 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, tu, mu -; CHECK-NEXT: vslideup.vi v28, v8, 8 +; CHECK-NEXT: vslideup.vi v12, v8, 8 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vrgather.vv v8, v14, v10 +; CHECK-NEXT: vrgather.vv v8, v20, v16 ; CHECK-NEXT: lui a0, 11 ; CHECK-NEXT: addiw a0, a0, -1366 ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vrgather.vv v8, v28, v12, v0.t +; CHECK-NEXT: vrgather.vv v8, v12, v18, v0.t ; CHECK-NEXT: ret entry: %v2 = shufflevector <8 x i16> %v0, <8 x i16> poison, <16 x i32> diff --git a/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll b/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll index 6e311f4f6393c032f16621eafed0b80eb2e569bb..31bde5a8953158b6a693ecd678b73b8bdd89095c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll +++ b/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll @@ -17,22 +17,22 @@ define <2 x i16> @fixedlen(<2 x i32> %x) { ; RV32-LABEL: fixedlen: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vsrl.vi v25, v8, 16 +; RV32-NEXT: vsrl.vi v8, v8, 16 ; RV32-NEXT: lui a0, 1048568 -; RV32-NEXT: vand.vx v25, v25, a0 +; RV32-NEXT: vand.vx v8, v8, a0 ; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; RV32-NEXT: vnsrl.wi v8, v25, 0 +; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: ret ; ; RV64-LABEL: fixedlen: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vsrl.vi v25, v8, 16 +; RV64-NEXT: vsrl.vi v8, v8, 16 ; RV64-NEXT: lui a0, 131071 ; RV64-NEXT: slli a0, a0, 3 -; RV64-NEXT: vand.vx v25, v25, a0 +; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; RV64-NEXT: vnsrl.wi v8, v25, 0 +; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: ret %v41 = insertelement <2 x i32> undef, i32 16, i32 0 %v42 = shufflevector <2 x i32> %v41, <2 x i32> undef, <2 x i32> zeroinitializer @@ -49,11 +49,11 @@ define @scalable( %x) { ; CHECK-LABEL: scalable: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vsrl.vi v25, v8, 16 +; CHECK-NEXT: vsrl.vi v8, v8, 16 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: lui a0, 1048568 -; CHECK-NEXT: vand.vx v8, v25, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %v41 = insertelement undef, i32 16, i32 0 %v42 = shufflevector %v41, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll b/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll index 48ebe9f8ecad96208be5948b7d3213efb2423350..bf9c21bc50fc5aaa52959f42280363ba4950f86a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll @@ -7,8 +7,8 @@ define @sextload_nxv1i1_nxv1i8(* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu ; CHECK-NEXT: vlm.v v0, (a0) -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -19,9 +19,9 @@ define @sextload_nxv1i8_nxv1i16(* %x) { ; CHECK-LABEL: sextload_nxv1i8_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: vsext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -32,9 +32,9 @@ define @zextload_nxv1i8_nxv1i16(* %x) { ; CHECK-LABEL: zextload_nxv1i8_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -45,9 +45,9 @@ define @sextload_nxv1i8_nxv1i32(* %x) { ; CHECK-LABEL: sextload_nxv1i8_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: vsext.vf4 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -58,9 +58,9 @@ define @zextload_nxv1i8_nxv1i32(* %x) { ; CHECK-LABEL: zextload_nxv1i8_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: vzext.vf4 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -71,9 +71,9 @@ define @sextload_nxv1i8_nxv1i64(* %x) { ; CHECK-LABEL: sextload_nxv1i8_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf8 v8, v25 +; CHECK-NEXT: vsext.vf8 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -84,9 +84,9 @@ define @zextload_nxv1i8_nxv1i64(* %x) { ; CHECK-LABEL: zextload_nxv1i8_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf8 v8, v25 +; CHECK-NEXT: vzext.vf8 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -97,9 +97,9 @@ define @sextload_nxv2i8_nxv2i16(* %x) { ; CHECK-LABEL: sextload_nxv2i8_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: vsext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -110,9 +110,9 @@ define @zextload_nxv2i8_nxv2i16(* %x) { ; CHECK-LABEL: zextload_nxv2i8_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -123,9 +123,9 @@ define @sextload_nxv2i8_nxv2i32(* %x) { ; CHECK-LABEL: sextload_nxv2i8_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: vsext.vf4 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -136,9 +136,9 @@ define @zextload_nxv2i8_nxv2i32(* %x) { ; CHECK-LABEL: zextload_nxv2i8_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: vzext.vf4 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -149,9 +149,9 @@ define @sextload_nxv2i8_nxv2i64(* %x) { ; CHECK-LABEL: sextload_nxv2i8_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v10, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf8 v8, v25 +; CHECK-NEXT: vsext.vf8 v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -162,9 +162,9 @@ define @zextload_nxv2i8_nxv2i64(* %x) { ; CHECK-LABEL: zextload_nxv2i8_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v10, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf8 v8, v25 +; CHECK-NEXT: vzext.vf8 v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -175,9 +175,9 @@ define @sextload_nxv4i8_nxv4i16(* %x) { ; CHECK-LABEL: sextload_nxv4i8_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: vsext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -188,9 +188,9 @@ define @zextload_nxv4i8_nxv4i16(* %x) { ; CHECK-LABEL: zextload_nxv4i8_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -201,9 +201,9 @@ define @sextload_nxv4i8_nxv4i32(* %x) { ; CHECK-LABEL: sextload_nxv4i8_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v10, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: vsext.vf4 v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -214,9 +214,9 @@ define @zextload_nxv4i8_nxv4i32(* %x) { ; CHECK-LABEL: zextload_nxv4i8_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v10, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: vzext.vf4 v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -227,9 +227,9 @@ define @sextload_nxv4i8_nxv4i64(* %x) { ; CHECK-LABEL: sextload_nxv4i8_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v12, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v8, v25 +; CHECK-NEXT: vsext.vf8 v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -240,9 +240,9 @@ define @zextload_nxv4i8_nxv4i64(* %x) { ; CHECK-LABEL: zextload_nxv4i8_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v12, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v8, v25 +; CHECK-NEXT: vzext.vf8 v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -252,9 +252,9 @@ define @zextload_nxv4i8_nxv4i64(* %x) { define @sextload_nxv8i8_nxv8i16(* %x) { ; CHECK-LABEL: sextload_nxv8i8_nxv8i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1r.v v25, (a0) +; CHECK-NEXT: vl1r.v v10, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: vsext.vf2 v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -264,9 +264,9 @@ define @sextload_nxv8i8_nxv8i16(* %x) { define @zextload_nxv8i8_nxv8i16(* %x) { ; CHECK-LABEL: zextload_nxv8i8_nxv8i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1r.v v25, (a0) +; CHECK-NEXT: vl1r.v v10, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: vzext.vf2 v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -276,9 +276,9 @@ define @zextload_nxv8i8_nxv8i16(* %x) { define @sextload_nxv8i8_nxv8i32(* %x) { ; CHECK-LABEL: sextload_nxv8i8_nxv8i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1r.v v25, (a0) +; CHECK-NEXT: vl1r.v v12, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: vsext.vf4 v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -288,9 +288,9 @@ define @sextload_nxv8i8_nxv8i32(* %x) { define @zextload_nxv8i8_nxv8i32(* %x) { ; CHECK-LABEL: zextload_nxv8i8_nxv8i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1r.v v25, (a0) +; CHECK-NEXT: vl1r.v v12, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: vzext.vf4 v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -300,9 +300,9 @@ define @zextload_nxv8i8_nxv8i32(* %x) { define @sextload_nxv8i8_nxv8i64(* %x) { ; CHECK-LABEL: sextload_nxv8i8_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1r.v v25, (a0) +; CHECK-NEXT: vl1r.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vsext.vf8 v8, v25 +; CHECK-NEXT: vsext.vf8 v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -312,9 +312,9 @@ define @sextload_nxv8i8_nxv8i64(* %x) { define @zextload_nxv8i8_nxv8i64(* %x) { ; CHECK-LABEL: zextload_nxv8i8_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1r.v v25, (a0) +; CHECK-NEXT: vl1r.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vzext.vf8 v8, v25 +; CHECK-NEXT: vzext.vf8 v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -324,9 +324,9 @@ define @zextload_nxv8i8_nxv8i64(* %x) { define @sextload_nxv16i8_nxv16i16(* %x) { ; CHECK-LABEL: sextload_nxv16i8_nxv16i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2r.v v26, (a0) +; CHECK-NEXT: vl2r.v v12, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v26 +; CHECK-NEXT: vsext.vf2 v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -336,9 +336,9 @@ define @sextload_nxv16i8_nxv16i16(* %x) { define @zextload_nxv16i8_nxv16i16(* %x) { ; CHECK-LABEL: zextload_nxv16i8_nxv16i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2r.v v26, (a0) +; CHECK-NEXT: vl2r.v v12, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v26 +; CHECK-NEXT: vzext.vf2 v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -348,9 +348,9 @@ define @zextload_nxv16i8_nxv16i16(* %x) { define @sextload_nxv16i8_nxv16i32(* %x) { ; CHECK-LABEL: sextload_nxv16i8_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2r.v v26, (a0) +; CHECK-NEXT: vl2r.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu -; CHECK-NEXT: vsext.vf4 v8, v26 +; CHECK-NEXT: vsext.vf4 v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -360,9 +360,9 @@ define @sextload_nxv16i8_nxv16i32(* %x) { define @zextload_nxv16i8_nxv16i32(* %x) { ; CHECK-LABEL: zextload_nxv16i8_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2r.v v26, (a0) +; CHECK-NEXT: vl2r.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu -; CHECK-NEXT: vzext.vf4 v8, v26 +; CHECK-NEXT: vzext.vf4 v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -372,9 +372,9 @@ define @zextload_nxv16i8_nxv16i32(* %x) { define @sextload_nxv32i8_nxv32i16(* %x) { ; CHECK-LABEL: sextload_nxv32i8_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4r.v v28, (a0) +; CHECK-NEXT: vl4r.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v28 +; CHECK-NEXT: vsext.vf2 v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -384,9 +384,9 @@ define @sextload_nxv32i8_nxv32i16(* %x) { define @zextload_nxv32i8_nxv32i16(* %x) { ; CHECK-LABEL: zextload_nxv32i8_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4r.v v28, (a0) +; CHECK-NEXT: vl4r.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v28 +; CHECK-NEXT: vzext.vf2 v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -397,9 +397,9 @@ define void @truncstore_nxv1i8_nxv1i1( %x, *% ; CHECK-LABEL: truncstore_nxv1i8_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v25, v25, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v8, v8, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -410,8 +410,8 @@ define void @truncstore_nxv1i16_nxv1i8( %x, * ; CHECK-LABEL: truncstore_nxv1i16_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -422,9 +422,9 @@ define @sextload_nxv1i16_nxv1i32(* %x) { ; CHECK-LABEL: sextload_nxv1i16_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: vsext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -435,9 +435,9 @@ define @zextload_nxv1i16_nxv1i32(* %x) { ; CHECK-LABEL: zextload_nxv1i16_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -448,9 +448,9 @@ define @sextload_nxv1i16_nxv1i64(* %x) { ; CHECK-LABEL: sextload_nxv1i16_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: vsext.vf4 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -461,9 +461,9 @@ define @zextload_nxv1i16_nxv1i64(* %x) { ; CHECK-LABEL: zextload_nxv1i16_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: vzext.vf4 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -474,8 +474,8 @@ define void @truncstore_nxv2i16_nxv2i8( %x, * ; CHECK-LABEL: truncstore_nxv2i16_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -486,9 +486,9 @@ define @sextload_nxv2i16_nxv2i32(* %x) { ; CHECK-LABEL: sextload_nxv2i16_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: vsext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -499,9 +499,9 @@ define @zextload_nxv2i16_nxv2i32(* %x) { ; CHECK-LABEL: zextload_nxv2i16_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -512,9 +512,9 @@ define @sextload_nxv2i16_nxv2i64(* %x) { ; CHECK-LABEL: sextload_nxv2i16_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v10, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: vsext.vf4 v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -525,9 +525,9 @@ define @zextload_nxv2i16_nxv2i64(* %x) { ; CHECK-LABEL: zextload_nxv2i16_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v10, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: vzext.vf4 v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -538,8 +538,8 @@ define void @truncstore_nxv4i16_nxv4i8( %x, * ; CHECK-LABEL: truncstore_nxv4i16_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -549,9 +549,9 @@ define void @truncstore_nxv4i16_nxv4i8( %x, * define @sextload_nxv4i16_nxv4i32(* %x) { ; CHECK-LABEL: sextload_nxv4i16_nxv4i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re16.v v25, (a0) +; CHECK-NEXT: vl1re16.v v10, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: vsext.vf2 v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -561,9 +561,9 @@ define @sextload_nxv4i16_nxv4i32(* %x) { define @zextload_nxv4i16_nxv4i32(* %x) { ; CHECK-LABEL: zextload_nxv4i16_nxv4i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re16.v v25, (a0) +; CHECK-NEXT: vl1re16.v v10, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: vzext.vf2 v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -573,9 +573,9 @@ define @zextload_nxv4i16_nxv4i32(* %x) { define @sextload_nxv4i16_nxv4i64(* %x) { ; CHECK-LABEL: sextload_nxv4i16_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re16.v v25, (a0) +; CHECK-NEXT: vl1re16.v v12, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: vsext.vf4 v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -585,9 +585,9 @@ define @sextload_nxv4i16_nxv4i64(* %x) { define @zextload_nxv4i16_nxv4i64(* %x) { ; CHECK-LABEL: zextload_nxv4i16_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re16.v v25, (a0) +; CHECK-NEXT: vl1re16.v v12, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: vzext.vf4 v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -598,8 +598,8 @@ define void @truncstore_nxv8i16_nxv8i8( %x, * ; CHECK-LABEL: truncstore_nxv8i16_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v10, v8, 0 +; CHECK-NEXT: vs1r.v v10, (a0) ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -609,9 +609,9 @@ define void @truncstore_nxv8i16_nxv8i8( %x, * define @sextload_nxv8i16_nxv8i32(* %x) { ; CHECK-LABEL: sextload_nxv8i16_nxv8i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2re16.v v26, (a0) +; CHECK-NEXT: vl2re16.v v12, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v26 +; CHECK-NEXT: vsext.vf2 v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -621,9 +621,9 @@ define @sextload_nxv8i16_nxv8i32(* %x) { define @zextload_nxv8i16_nxv8i32(* %x) { ; CHECK-LABEL: zextload_nxv8i16_nxv8i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2re16.v v26, (a0) +; CHECK-NEXT: vl2re16.v v12, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v26 +; CHECK-NEXT: vzext.vf2 v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -633,9 +633,9 @@ define @zextload_nxv8i16_nxv8i32(* %x) { define @sextload_nxv8i16_nxv8i64(* %x) { ; CHECK-LABEL: sextload_nxv8i16_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2re16.v v26, (a0) +; CHECK-NEXT: vl2re16.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vsext.vf4 v8, v26 +; CHECK-NEXT: vsext.vf4 v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -645,9 +645,9 @@ define @sextload_nxv8i16_nxv8i64(* %x) { define @zextload_nxv8i16_nxv8i64(* %x) { ; CHECK-LABEL: zextload_nxv8i16_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2re16.v v26, (a0) +; CHECK-NEXT: vl2re16.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vzext.vf4 v8, v26 +; CHECK-NEXT: vzext.vf4 v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -658,8 +658,8 @@ define void @truncstore_nxv16i16_nxv16i8( %x, %x to store %y, * %z @@ -669,9 +669,9 @@ define void @truncstore_nxv16i16_nxv16i8( %x, @sextload_nxv16i16_nxv16i32(* %x) { ; CHECK-LABEL: sextload_nxv16i16_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v28 +; CHECK-NEXT: vsext.vf2 v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -681,9 +681,9 @@ define @sextload_nxv16i16_nxv16i32(* %x) define @zextload_nxv16i16_nxv16i32(* %x) { ; CHECK-LABEL: zextload_nxv16i16_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v28 +; CHECK-NEXT: vzext.vf2 v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -694,8 +694,8 @@ define void @truncstore_nxv32i16_nxv32i8( %x, %x to store %y, * %z @@ -706,10 +706,10 @@ define void @truncstore_nxv1i32_nxv1i8( %x, * ; CHECK-LABEL: truncstore_nxv1i32_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -720,8 +720,8 @@ define void @truncstore_nxv1i32_nxv1i16( %x, %x to store %y, * %z @@ -732,9 +732,9 @@ define @sextload_nxv1i32_nxv1i64(* %x) { ; CHECK-LABEL: sextload_nxv1i32_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: vsext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -745,9 +745,9 @@ define @zextload_nxv1i32_nxv1i64(* %x) { ; CHECK-LABEL: zextload_nxv1i32_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -758,10 +758,10 @@ define void @truncstore_nxv2i32_nxv2i8( %x, * ; CHECK-LABEL: truncstore_nxv2i32_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -772,8 +772,8 @@ define void @truncstore_nxv2i32_nxv2i16( %x, %x to store %y, * %z @@ -783,9 +783,9 @@ define void @truncstore_nxv2i32_nxv2i16( %x, @sextload_nxv2i32_nxv2i64(* %x) { ; CHECK-LABEL: sextload_nxv2i32_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re32.v v25, (a0) +; CHECK-NEXT: vl1re32.v v10, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: vsext.vf2 v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -795,9 +795,9 @@ define @sextload_nxv2i32_nxv2i64(* %x) { define @zextload_nxv2i32_nxv2i64(* %x) { ; CHECK-LABEL: zextload_nxv2i32_nxv2i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re32.v v25, (a0) +; CHECK-NEXT: vl1re32.v v10, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: vzext.vf2 v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -808,10 +808,10 @@ define void @truncstore_nxv4i32_nxv4i8( %x, * ; CHECK-LABEL: truncstore_nxv4i32_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v10, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -822,8 +822,8 @@ define void @truncstore_nxv4i32_nxv4i16( %x, %x to store %y, * %z @@ -833,9 +833,9 @@ define void @truncstore_nxv4i32_nxv4i16( %x, @sextload_nxv4i32_nxv4i64(* %x) { ; CHECK-LABEL: sextload_nxv4i32_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2re32.v v26, (a0) +; CHECK-NEXT: vl2re32.v v12, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v26 +; CHECK-NEXT: vsext.vf2 v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -845,9 +845,9 @@ define @sextload_nxv4i32_nxv4i64(* %x) { define @zextload_nxv4i32_nxv4i64(* %x) { ; CHECK-LABEL: zextload_nxv4i32_nxv4i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2re32.v v26, (a0) +; CHECK-NEXT: vl2re32.v v12, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v26 +; CHECK-NEXT: vzext.vf2 v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -858,10 +858,10 @@ define void @truncstore_nxv8i32_nxv8i8( %x, * ; CHECK-LABEL: truncstore_nxv8i32_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v26, 0 -; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v12, 0 +; CHECK-NEXT: vs1r.v v8, (a0) ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -872,8 +872,8 @@ define void @truncstore_nxv8i32_nxv8i16( %x, %x to store %y, * %z @@ -883,9 +883,9 @@ define void @truncstore_nxv8i32_nxv8i16( %x, @sextload_nxv8i32_nxv8i64(* %x) { ; CHECK-LABEL: sextload_nxv8i32_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v28 +; CHECK-NEXT: vsext.vf2 v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = sext %y to @@ -895,9 +895,9 @@ define @sextload_nxv8i32_nxv8i64(* %x) { define @zextload_nxv8i32_nxv8i64(* %x) { ; CHECK-LABEL: zextload_nxv8i32_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v28 +; CHECK-NEXT: vzext.vf2 v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = zext %y to @@ -908,10 +908,10 @@ define void @truncstore_nxv16i32_nxv16i8( %x, %x to store %y, * %z @@ -922,8 +922,8 @@ define void @truncstore_nxv16i32_nxv16i16( %x, %x to store %y, * %z @@ -934,12 +934,12 @@ define void @truncstore_nxv1i64_nxv1i8( %x, * ; CHECK-LABEL: truncstore_nxv1i64_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -950,10 +950,10 @@ define void @truncstore_nxv1i64_nxv1i16( %x, %x to store %y, * %z @@ -964,8 +964,8 @@ define void @truncstore_nxv1i64_nxv1i32( %x, %x to store %y, * %z @@ -976,12 +976,12 @@ define void @truncstore_nxv2i64_nxv2i8( %x, * ; CHECK-LABEL: truncstore_nxv2i64_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -992,10 +992,10 @@ define void @truncstore_nxv2i64_nxv2i16( %x, %x to store %y, * %z @@ -1006,8 +1006,8 @@ define void @truncstore_nxv2i64_nxv2i32( %x, %x to store %y, * %z @@ -1018,12 +1018,12 @@ define void @truncstore_nxv4i64_nxv4i8( %x, * ; CHECK-LABEL: truncstore_nxv4i64_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -1034,10 +1034,10 @@ define void @truncstore_nxv4i64_nxv4i16( %x, %x to store %y, * %z @@ -1048,8 +1048,8 @@ define void @truncstore_nxv4i64_nxv4i32( %x, %x to store %y, * %z @@ -1060,12 +1060,12 @@ define void @truncstore_nxv8i64_nxv8i8( %x, * ; CHECK-LABEL: truncstore_nxv8i64_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v28, 0 +; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v26, 0 -; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v10, v8, 0 +; CHECK-NEXT: vs1r.v v10, (a0) ; CHECK-NEXT: ret %y = trunc %x to store %y, * %z @@ -1076,10 +1076,10 @@ define void @truncstore_nxv8i64_nxv8i16( %x, %x to store %y, * %z @@ -1090,8 +1090,8 @@ define void @truncstore_nxv8i64_nxv8i32( %x, %x to store %y, * %z @@ -1102,8 +1102,8 @@ define @extload_nxv1f16_nxv1f32(* %x) { ; CHECK-LABEL: extload_nxv1f16_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vfwcvt.f.f.v v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1114,10 +1114,10 @@ define @extload_nxv1f16_nxv1f64(* %x) { ; CHECK-LABEL: extload_nxv1f16_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfwcvt.f.f.v v26, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: vfwcvt.f.f.v v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1128,8 +1128,8 @@ define @extload_nxv2f16_nxv2f32(* %x) { ; CHECK-LABEL: extload_nxv2f16_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vfwcvt.f.f.v v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1140,10 +1140,10 @@ define @extload_nxv2f16_nxv2f64(* %x) { ; CHECK-LABEL: extload_nxv2f16_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfwcvt.f.f.v v26, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfwcvt.f.f.v v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: vfwcvt.f.f.v v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1153,9 +1153,9 @@ define @extload_nxv2f16_nxv2f64(* %x) { define @extload_nxv4f16_nxv4f32(* %x) { ; CHECK-LABEL: extload_nxv4f16_nxv4f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re16.v v25, (a0) +; CHECK-NEXT: vl1re16.v v10, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: vfwcvt.f.f.v v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1165,11 +1165,11 @@ define @extload_nxv4f16_nxv4f32(* %x) { define @extload_nxv4f16_nxv4f64(* %x) { ; CHECK-LABEL: extload_nxv4f16_nxv4f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re16.v v25, (a0) +; CHECK-NEXT: vl1re16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v26, v25 +; CHECK-NEXT: vfwcvt.f.f.v v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: vfwcvt.f.f.v v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1179,9 +1179,9 @@ define @extload_nxv4f16_nxv4f64(* %x) { define @extload_nxv8f16_nxv8f32(* %x) { ; CHECK-LABEL: extload_nxv8f16_nxv8f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2re16.v v26, (a0) +; CHECK-NEXT: vl2re16.v v12, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: vfwcvt.f.f.v v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1191,11 +1191,11 @@ define @extload_nxv8f16_nxv8f32(* %x) { define @extload_nxv8f16_nxv8f64(* %x) { ; CHECK-LABEL: extload_nxv8f16_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2re16.v v26, (a0) +; CHECK-NEXT: vl2re16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v28, v26 +; CHECK-NEXT: vfwcvt.f.f.v v16, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v28 +; CHECK-NEXT: vfwcvt.f.f.v v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1205,9 +1205,9 @@ define @extload_nxv8f16_nxv8f64(* %x) { define @extload_nxv16f16_nxv16f32(* %x) { ; CHECK-LABEL: extload_nxv16f16_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v28 +; CHECK-NEXT: vfwcvt.f.f.v v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1218,8 +1218,8 @@ define void @truncstore_nxv1f32_nxv1f16( %x, %x to store %y, * %z @@ -1230,8 +1230,8 @@ define @extload_nxv1f32_nxv1f64(* %x) ; CHECK-LABEL: extload_nxv1f32_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vfwcvt.f.f.v v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1242,8 +1242,8 @@ define void @truncstore_nxv2f32_nxv2f16( %x, %x to store %y, * %z @@ -1253,9 +1253,9 @@ define void @truncstore_nxv2f32_nxv2f16( %x, @extload_nxv2f32_nxv2f64(* %x) { ; CHECK-LABEL: extload_nxv2f32_nxv2f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re32.v v25, (a0) +; CHECK-NEXT: vl1re32.v v10, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: vfwcvt.f.f.v v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1266,8 +1266,8 @@ define void @truncstore_nxv4f32_nxv4f16( %x, %x to store %y, * %z @@ -1277,9 +1277,9 @@ define void @truncstore_nxv4f32_nxv4f16( %x, @extload_nxv4f32_nxv4f64(* %x) { ; CHECK-LABEL: extload_nxv4f32_nxv4f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2re32.v v26, (a0) +; CHECK-NEXT: vl2re32.v v12, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: vfwcvt.f.f.v v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1290,8 +1290,8 @@ define void @truncstore_nxv8f32_nxv8f16( %x, %x to store %y, * %z @@ -1301,9 +1301,9 @@ define void @truncstore_nxv8f32_nxv8f16( %x, @extload_nxv8f32_nxv8f64(* %x) { ; CHECK-LABEL: extload_nxv8f32_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v28 +; CHECK-NEXT: vfwcvt.f.f.v v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -1314,8 +1314,8 @@ define void @truncstore_nxv16f32_nxv16f16( %x, %x to store %y, * %z @@ -1326,10 +1326,10 @@ define void @truncstore_nxv1f64_nxv1f16( %x, %x to store %y, * %z @@ -1340,8 +1340,8 @@ define void @truncstore_nxv1f64_nxv1f32( %x, %x to store %y, * %z @@ -1352,10 +1352,10 @@ define void @truncstore_nxv2f64_nxv2f16( %x, %x to store %y, * %z @@ -1366,8 +1366,8 @@ define void @truncstore_nxv2f64_nxv2f32( %x, %x to store %y, * %z @@ -1378,10 +1378,10 @@ define void @truncstore_nxv4f64_nxv4f16( %x, %x to store %y, * %z @@ -1392,8 +1392,8 @@ define void @truncstore_nxv4f64_nxv4f32( %x, %x to store %y, * %z @@ -1404,10 +1404,10 @@ define void @truncstore_nxv8f64_nxv8f16( %x, %x to store %y, * %z @@ -1418,8 +1418,8 @@ define void @truncstore_nxv8f64_nxv8f32( %x, %x to store %y, * %z diff --git a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll index 79c1b7781aff9faaef7ec34f36f5689fb0b0031a..8da02c3333d6de0ca2d92b0823fdb8f1b8077842 100644 --- a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll @@ -409,9 +409,9 @@ define @extract_nxv64i1_nxv2i1_2( %mask) { ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv2i1( %mask, i64 2) ret %c @@ -429,14 +429,14 @@ define @extract_nxv4i1_nxv32i1_4( %x) { ; CHECK-LABEL: extract_nxv4i1_nxv32i1_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v28, v28, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v28, a0 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %c = call @llvm.experimental.vector.extract.nxv4i1( %x, i64 4) ret %c @@ -480,15 +480,15 @@ define @extract_nxv6f16_nxv12f16_6( %in) ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v10, a0 -; CHECK-NEXT: vslidedown.vx v26, v9, a0 +; CHECK-NEXT: vslidedown.vx v14, v10, a0 +; CHECK-NEXT: vslidedown.vx v12, v9, a0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: vslideup.vi v27, v25, 0 +; CHECK-NEXT: vslideup.vi v13, v14, 0 ; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu -; CHECK-NEXT: vslideup.vx v27, v25, a0 -; CHECK-NEXT: vslideup.vx v26, v10, a0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vslideup.vx v13, v8, a0 +; CHECK-NEXT: vslideup.vx v12, v10, a0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.extract.nxv6f16.nxv12f16( %in, i64 6) ret %res diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll index 91bbcf015143f787da7b058b57a35e82b1309456..de46a2d53bc34afa888ecdabe2a12923883e048e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll @@ -16,8 +16,8 @@ define half @extractelt_nxv1f16_imm( %v) { ; CHECK-LABEL: extractelt_nxv1f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -27,8 +27,8 @@ define half @extractelt_nxv1f16_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv1f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -48,8 +48,8 @@ define half @extractelt_nxv2f16_imm( %v) { ; CHECK-LABEL: extractelt_nxv2f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -59,8 +59,8 @@ define half @extractelt_nxv2f16_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv2f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -80,8 +80,8 @@ define half @extractelt_nxv4f16_imm( %v) { ; CHECK-LABEL: extractelt_nxv4f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -91,8 +91,8 @@ define half @extractelt_nxv4f16_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv4f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -112,8 +112,8 @@ define half @extractelt_nxv8f16_imm( %v) { ; CHECK-LABEL: extractelt_nxv8f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -123,8 +123,8 @@ define half @extractelt_nxv8f16_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv8f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -144,8 +144,8 @@ define half @extractelt_nxv16f16_imm( %v) { ; CHECK-LABEL: extractelt_nxv16f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu -; CHECK-NEXT: vslidedown.vi v28, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -155,8 +155,8 @@ define half @extractelt_nxv16f16_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv16f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -208,8 +208,8 @@ define float @extractelt_nxv1f32_imm( %v) { ; CHECK-LABEL: extractelt_nxv1f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -219,8 +219,8 @@ define float @extractelt_nxv1f32_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv1f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -240,8 +240,8 @@ define float @extractelt_nxv2f32_imm( %v) { ; CHECK-LABEL: extractelt_nxv2f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -251,8 +251,8 @@ define float @extractelt_nxv2f32_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv2f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -272,8 +272,8 @@ define float @extractelt_nxv4f32_imm( %v) { ; CHECK-LABEL: extractelt_nxv4f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -283,8 +283,8 @@ define float @extractelt_nxv4f32_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv4f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -304,8 +304,8 @@ define float @extractelt_nxv8f32_imm( %v) { ; CHECK-LABEL: extractelt_nxv8f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu -; CHECK-NEXT: vslidedown.vi v28, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -315,8 +315,8 @@ define float @extractelt_nxv8f32_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv8f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -368,8 +368,8 @@ define double @extractelt_nxv1f64_imm( %v) { ; CHECK-LABEL: extractelt_nxv1f64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret double %r @@ -379,8 +379,8 @@ define double @extractelt_nxv1f64_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv1f64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret double %r @@ -400,8 +400,8 @@ define double @extractelt_nxv2f64_imm( %v) { ; CHECK-LABEL: extractelt_nxv2f64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret double %r @@ -411,8 +411,8 @@ define double @extractelt_nxv2f64_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv2f64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret double %r @@ -432,8 +432,8 @@ define double @extractelt_nxv4f64_imm( %v) { ; CHECK-LABEL: extractelt_nxv4f64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu -; CHECK-NEXT: vslidedown.vi v28, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret double %r @@ -443,8 +443,8 @@ define double @extractelt_nxv4f64_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv4f64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret double %r diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll index 0fa1f18624d48c6e140e7bc763f2a50a83a3d2cd..935a12f81b4608bd9ff685bd262d1ff4ebcf2c10 100644 --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll @@ -16,8 +16,8 @@ define half @extractelt_nxv1f16_imm( %v) { ; CHECK-LABEL: extractelt_nxv1f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -27,8 +27,8 @@ define half @extractelt_nxv1f16_idx( %v, i32 signext %idx) { ; CHECK-LABEL: extractelt_nxv1f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -48,8 +48,8 @@ define half @extractelt_nxv2f16_imm( %v) { ; CHECK-LABEL: extractelt_nxv2f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -59,8 +59,8 @@ define half @extractelt_nxv2f16_idx( %v, i32 signext %idx) { ; CHECK-LABEL: extractelt_nxv2f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -80,8 +80,8 @@ define half @extractelt_nxv4f16_imm( %v) { ; CHECK-LABEL: extractelt_nxv4f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -91,8 +91,8 @@ define half @extractelt_nxv4f16_idx( %v, i32 signext %idx) { ; CHECK-LABEL: extractelt_nxv4f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -112,8 +112,8 @@ define half @extractelt_nxv8f16_imm( %v) { ; CHECK-LABEL: extractelt_nxv8f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -123,8 +123,8 @@ define half @extractelt_nxv8f16_idx( %v, i32 signext %idx) { ; CHECK-LABEL: extractelt_nxv8f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -144,8 +144,8 @@ define half @extractelt_nxv16f16_imm( %v) { ; CHECK-LABEL: extractelt_nxv16f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu -; CHECK-NEXT: vslidedown.vi v28, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret half %r @@ -155,8 +155,8 @@ define half @extractelt_nxv16f16_idx( %v, i32 signext %idx) ; CHECK-LABEL: extractelt_nxv16f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret half %r @@ -208,8 +208,8 @@ define float @extractelt_nxv1f32_imm( %v) { ; CHECK-LABEL: extractelt_nxv1f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -219,8 +219,8 @@ define float @extractelt_nxv1f32_idx( %v, i32 signext %idx) ; CHECK-LABEL: extractelt_nxv1f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -240,8 +240,8 @@ define float @extractelt_nxv2f32_imm( %v) { ; CHECK-LABEL: extractelt_nxv2f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -251,8 +251,8 @@ define float @extractelt_nxv2f32_idx( %v, i32 signext %idx) ; CHECK-LABEL: extractelt_nxv2f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -272,8 +272,8 @@ define float @extractelt_nxv4f32_imm( %v) { ; CHECK-LABEL: extractelt_nxv4f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -283,8 +283,8 @@ define float @extractelt_nxv4f32_idx( %v, i32 signext %idx) ; CHECK-LABEL: extractelt_nxv4f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -304,8 +304,8 @@ define float @extractelt_nxv8f32_imm( %v) { ; CHECK-LABEL: extractelt_nxv8f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu -; CHECK-NEXT: vslidedown.vi v28, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret float %r @@ -315,8 +315,8 @@ define float @extractelt_nxv8f32_idx( %v, i32 signext %idx) ; CHECK-LABEL: extractelt_nxv8f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret float %r @@ -368,8 +368,8 @@ define double @extractelt_nxv1f64_imm( %v) { ; CHECK-LABEL: extractelt_nxv1f64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret double %r @@ -379,8 +379,8 @@ define double @extractelt_nxv1f64_idx( %v, i32 signext %idx ; CHECK-LABEL: extractelt_nxv1f64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret double %r @@ -400,8 +400,8 @@ define double @extractelt_nxv2f64_imm( %v) { ; CHECK-LABEL: extractelt_nxv2f64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret double %r @@ -411,8 +411,8 @@ define double @extractelt_nxv2f64_idx( %v, i32 signext %idx ; CHECK-LABEL: extractelt_nxv2f64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret double %r @@ -432,8 +432,8 @@ define double @extractelt_nxv4f64_imm( %v) { ; CHECK-LABEL: extractelt_nxv4f64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu -; CHECK-NEXT: vslidedown.vi v28, v8, 2 -; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret double %r @@ -443,8 +443,8 @@ define double @extractelt_nxv4f64_idx( %v, i32 signext %idx ; CHECK-LABEL: extractelt_nxv4f64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v8, a0 -; CHECK-NEXT: vfmv.f.s fa0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret double %r diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll index 7e48f1c15df8743b81221f2bfba5fd2bcc0bb53a..27d609e6f8a7c23e5ac36b45e8f648530de32f97 100644 --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll @@ -6,13 +6,13 @@ define i1 @extractelt_nxv1i1(* %x, i64 %idx) nounwind { ; CHECK-LABEL: extractelt_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load , * %x %b = icmp eq %a, zeroinitializer @@ -24,13 +24,13 @@ define i1 @extractelt_nxv2i1(* %x, i64 %idx) nounwind { ; CHECK-LABEL: extractelt_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load , * %x %b = icmp eq %a, zeroinitializer @@ -42,13 +42,13 @@ define i1 @extractelt_nxv4i1(* %x, i64 %idx) nounwind { ; CHECK-LABEL: extractelt_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load , * %x %b = icmp eq %a, zeroinitializer @@ -59,14 +59,14 @@ define i1 @extractelt_nxv4i1(* %x, i64 %idx) nounwind { define i1 @extractelt_nxv8i1(* %x, i64 %idx) nounwind { ; CHECK-LABEL: extractelt_nxv8i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1r.v v25, (a0) +; CHECK-NEXT: vl1r.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load , * %x %b = icmp eq %a, zeroinitializer @@ -77,14 +77,14 @@ define i1 @extractelt_nxv8i1(* %x, i64 %idx) nounwind { define i1 @extractelt_nxv16i1(* %x, i64 %idx) nounwind { ; CHECK-LABEL: extractelt_nxv16i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2r.v v26, (a0) +; CHECK-NEXT: vl2r.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vmseq.vi v0, v26, 0 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v26, a1 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load , * %x %b = icmp eq %a, zeroinitializer @@ -95,14 +95,14 @@ define i1 @extractelt_nxv16i1(* %x, i64 %idx) nounwind { define i1 @extractelt_nxv32i1(* %x, i64 %idx) nounwind { ; CHECK-LABEL: extractelt_nxv32i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4r.v v28, (a0) +; CHECK-NEXT: vl4r.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vmseq.vi v0, v28, 0 -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v28, v28, 1, v0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v28, a1 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load , * %x %b = icmp eq %a, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll index 70e742ebd5605dc5deb1fa4ca8cc2df63dd03584..31f3c3004b19131f93b70a5962ef79f400a28e91 100644 --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll @@ -16,8 +16,8 @@ define signext i8 @extractelt_nxv1i8_imm( %v) { ; CHECK-LABEL: extractelt_nxv1i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -27,8 +27,8 @@ define signext i8 @extractelt_nxv1i8_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv1i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -48,8 +48,8 @@ define signext i8 @extractelt_nxv2i8_imm( %v) { ; CHECK-LABEL: extractelt_nxv2i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -59,8 +59,8 @@ define signext i8 @extractelt_nxv2i8_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv2i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -80,8 +80,8 @@ define signext i8 @extractelt_nxv4i8_imm( %v) { ; CHECK-LABEL: extractelt_nxv4i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -91,8 +91,8 @@ define signext i8 @extractelt_nxv4i8_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv4i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -112,8 +112,8 @@ define signext i8 @extractelt_nxv8i8_imm( %v) { ; CHECK-LABEL: extractelt_nxv8i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -123,8 +123,8 @@ define signext i8 @extractelt_nxv8i8_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv8i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -144,8 +144,8 @@ define signext i8 @extractelt_nxv16i8_imm( %v) { ; CHECK-LABEL: extractelt_nxv16i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -155,8 +155,8 @@ define signext i8 @extractelt_nxv16i8_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv16i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -176,8 +176,8 @@ define signext i8 @extractelt_nxv32i8_imm( %v) { ; CHECK-LABEL: extractelt_nxv32i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu -; CHECK-NEXT: vslidedown.vi v28, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -187,8 +187,8 @@ define signext i8 @extractelt_nxv32i8_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv32i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -240,8 +240,8 @@ define signext i16 @extractelt_nxv1i16_imm( %v) { ; CHECK-LABEL: extractelt_nxv1i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -251,8 +251,8 @@ define signext i16 @extractelt_nxv1i16_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv1i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -272,8 +272,8 @@ define signext i16 @extractelt_nxv2i16_imm( %v) { ; CHECK-LABEL: extractelt_nxv2i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -283,8 +283,8 @@ define signext i16 @extractelt_nxv2i16_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv2i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -304,8 +304,8 @@ define signext i16 @extractelt_nxv4i16_imm( %v) { ; CHECK-LABEL: extractelt_nxv4i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -315,8 +315,8 @@ define signext i16 @extractelt_nxv4i16_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv4i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -336,8 +336,8 @@ define signext i16 @extractelt_nxv8i16_imm( %v) { ; CHECK-LABEL: extractelt_nxv8i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -347,8 +347,8 @@ define signext i16 @extractelt_nxv8i16_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv8i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -368,8 +368,8 @@ define signext i16 @extractelt_nxv16i16_imm( %v) { ; CHECK-LABEL: extractelt_nxv16i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu -; CHECK-NEXT: vslidedown.vi v28, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -379,8 +379,8 @@ define signext i16 @extractelt_nxv16i16_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv16i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -432,8 +432,8 @@ define i32 @extractelt_nxv1i32_imm( %v) { ; CHECK-LABEL: extractelt_nxv1i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -443,8 +443,8 @@ define i32 @extractelt_nxv1i32_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv1i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -464,8 +464,8 @@ define i32 @extractelt_nxv2i32_imm( %v) { ; CHECK-LABEL: extractelt_nxv2i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -475,8 +475,8 @@ define i32 @extractelt_nxv2i32_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv2i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -496,8 +496,8 @@ define i32 @extractelt_nxv4i32_imm( %v) { ; CHECK-LABEL: extractelt_nxv4i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -507,8 +507,8 @@ define i32 @extractelt_nxv4i32_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv4i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -528,8 +528,8 @@ define i32 @extractelt_nxv8i32_imm( %v) { ; CHECK-LABEL: extractelt_nxv8i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu -; CHECK-NEXT: vslidedown.vi v28, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -539,8 +539,8 @@ define i32 @extractelt_nxv8i32_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv8i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -583,8 +583,8 @@ define i64 @extractelt_nxv1i64_0( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v9, v8, a0 +; CHECK-NEXT: vmv.x.s a1, v9 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 @@ -595,11 +595,11 @@ define i64 @extractelt_nxv1i64_imm( %v) { ; CHECK-LABEL: extractelt_nxv1i64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i64 %r @@ -609,11 +609,11 @@ define i64 @extractelt_nxv1i64_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv1i64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i64 %r @@ -624,8 +624,8 @@ define i64 @extractelt_nxv2i64_0( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; CHECK-NEXT: vsrl.vx v26, v8, a0 -; CHECK-NEXT: vmv.x.s a1, v26 +; CHECK-NEXT: vsrl.vx v10, v8, a0 +; CHECK-NEXT: vmv.x.s a1, v10 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 @@ -636,11 +636,11 @@ define i64 @extractelt_nxv2i64_imm( %v) { ; CHECK-LABEL: extractelt_nxv2i64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vmv.x.s a1, v26 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i64 %r @@ -650,11 +650,11 @@ define i64 @extractelt_nxv2i64_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv2i64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vmv.x.s a1, v26 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i64 %r @@ -665,8 +665,8 @@ define i64 @extractelt_nxv4i64_0( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu -; CHECK-NEXT: vsrl.vx v28, v8, a0 -; CHECK-NEXT: vmv.x.s a1, v28 +; CHECK-NEXT: vsrl.vx v12, v8, a0 +; CHECK-NEXT: vmv.x.s a1, v12 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 0 @@ -677,11 +677,11 @@ define i64 @extractelt_nxv4i64_imm( %v) { ; CHECK-LABEL: extractelt_nxv4i64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu -; CHECK-NEXT: vslidedown.vi v28, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vmv.x.s a1, v28 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i64 %r @@ -691,11 +691,11 @@ define i64 @extractelt_nxv4i64_idx( %v, i32 %idx) { ; CHECK-LABEL: extractelt_nxv4i64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsrl.vx v28, v28, a1 -; CHECK-NEXT: vmv.x.s a1, v28 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i64 %r diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll index 1c9ee97f3cd03baf51d99e02170035b836ea9c0e..1d4983f280f37bf3ab24daf132c650ca626b55c7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll @@ -16,8 +16,8 @@ define signext i8 @extractelt_nxv1i8_imm( %v) { ; CHECK-LABEL: extractelt_nxv1i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -27,8 +27,8 @@ define signext i8 @extractelt_nxv1i8_idx( %v, i32 signext %idx) ; CHECK-LABEL: extractelt_nxv1i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -48,8 +48,8 @@ define signext i8 @extractelt_nxv2i8_imm( %v) { ; CHECK-LABEL: extractelt_nxv2i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -59,8 +59,8 @@ define signext i8 @extractelt_nxv2i8_idx( %v, i32 signext %idx) ; CHECK-LABEL: extractelt_nxv2i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -80,8 +80,8 @@ define signext i8 @extractelt_nxv4i8_imm( %v) { ; CHECK-LABEL: extractelt_nxv4i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -91,8 +91,8 @@ define signext i8 @extractelt_nxv4i8_idx( %v, i32 signext %idx) ; CHECK-LABEL: extractelt_nxv4i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -112,8 +112,8 @@ define signext i8 @extractelt_nxv8i8_imm( %v) { ; CHECK-LABEL: extractelt_nxv8i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -123,8 +123,8 @@ define signext i8 @extractelt_nxv8i8_idx( %v, i32 signext %idx) ; CHECK-LABEL: extractelt_nxv8i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -144,8 +144,8 @@ define signext i8 @extractelt_nxv16i8_imm( %v) { ; CHECK-LABEL: extractelt_nxv16i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -155,8 +155,8 @@ define signext i8 @extractelt_nxv16i8_idx( %v, i32 signext %id ; CHECK-LABEL: extractelt_nxv16i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -176,8 +176,8 @@ define signext i8 @extractelt_nxv32i8_imm( %v) { ; CHECK-LABEL: extractelt_nxv32i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu -; CHECK-NEXT: vslidedown.vi v28, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i8 %r @@ -187,8 +187,8 @@ define signext i8 @extractelt_nxv32i8_idx( %v, i32 signext %id ; CHECK-LABEL: extractelt_nxv32i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i8 %r @@ -240,8 +240,8 @@ define signext i16 @extractelt_nxv1i16_imm( %v) { ; CHECK-LABEL: extractelt_nxv1i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -251,8 +251,8 @@ define signext i16 @extractelt_nxv1i16_idx( %v, i32 signext %i ; CHECK-LABEL: extractelt_nxv1i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -272,8 +272,8 @@ define signext i16 @extractelt_nxv2i16_imm( %v) { ; CHECK-LABEL: extractelt_nxv2i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -283,8 +283,8 @@ define signext i16 @extractelt_nxv2i16_idx( %v, i32 signext %i ; CHECK-LABEL: extractelt_nxv2i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -304,8 +304,8 @@ define signext i16 @extractelt_nxv4i16_imm( %v) { ; CHECK-LABEL: extractelt_nxv4i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -315,8 +315,8 @@ define signext i16 @extractelt_nxv4i16_idx( %v, i32 signext %i ; CHECK-LABEL: extractelt_nxv4i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -336,8 +336,8 @@ define signext i16 @extractelt_nxv8i16_imm( %v) { ; CHECK-LABEL: extractelt_nxv8i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -347,8 +347,8 @@ define signext i16 @extractelt_nxv8i16_idx( %v, i32 signext %i ; CHECK-LABEL: extractelt_nxv8i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -368,8 +368,8 @@ define signext i16 @extractelt_nxv16i16_imm( %v) { ; CHECK-LABEL: extractelt_nxv16i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu -; CHECK-NEXT: vslidedown.vi v28, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i16 %r @@ -379,8 +379,8 @@ define signext i16 @extractelt_nxv16i16_idx( %v, i32 signext ; CHECK-LABEL: extractelt_nxv16i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i16 %r @@ -432,8 +432,8 @@ define signext i32 @extractelt_nxv1i32_imm( %v) { ; CHECK-LABEL: extractelt_nxv1i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -443,8 +443,8 @@ define signext i32 @extractelt_nxv1i32_idx( %v, i32 signext %i ; CHECK-LABEL: extractelt_nxv1i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -464,8 +464,8 @@ define signext i32 @extractelt_nxv2i32_imm( %v) { ; CHECK-LABEL: extractelt_nxv2i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -475,8 +475,8 @@ define signext i32 @extractelt_nxv2i32_idx( %v, i32 signext %i ; CHECK-LABEL: extractelt_nxv2i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -496,8 +496,8 @@ define signext i32 @extractelt_nxv4i32_imm( %v) { ; CHECK-LABEL: extractelt_nxv4i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -507,8 +507,8 @@ define signext i32 @extractelt_nxv4i32_idx( %v, i32 signext %i ; CHECK-LABEL: extractelt_nxv4i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -528,8 +528,8 @@ define signext i32 @extractelt_nxv8i32_imm( %v) { ; CHECK-LABEL: extractelt_nxv8i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu -; CHECK-NEXT: vslidedown.vi v28, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i32 %r @@ -539,8 +539,8 @@ define signext i32 @extractelt_nxv8i32_idx( %v, i32 signext %i ; CHECK-LABEL: extractelt_nxv8i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i32 %r @@ -592,8 +592,8 @@ define i64 @extractelt_nxv1i64_imm( %v) { ; CHECK-LABEL: extractelt_nxv1i64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i64 %r @@ -603,8 +603,8 @@ define i64 @extractelt_nxv1i64_idx( %v, i32 signext %idx) { ; CHECK-LABEL: extractelt_nxv1i64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i64 %r @@ -624,8 +624,8 @@ define i64 @extractelt_nxv2i64_imm( %v) { ; CHECK-LABEL: extractelt_nxv2i64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i64 %r @@ -635,8 +635,8 @@ define i64 @extractelt_nxv2i64_idx( %v, i32 signext %idx) { ; CHECK-LABEL: extractelt_nxv2i64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i64 %r @@ -656,8 +656,8 @@ define i64 @extractelt_nxv4i64_imm( %v) { ; CHECK-LABEL: extractelt_nxv4i64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu -; CHECK-NEXT: vslidedown.vi v28, v8, 2 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 2 ret i64 %r @@ -667,8 +667,8 @@ define i64 @extractelt_nxv4i64_idx( %v, i32 signext %idx) { ; CHECK-LABEL: extractelt_nxv4i64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v8, a0 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %r = extractelement %v, i32 %idx ret i64 %r diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll index 9d8da31c6d925659af36ba8da038990886f7310a..33c68c1a882150b11940ab86392d539ab764226d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll @@ -38,11 +38,11 @@ define void @gather(i8* noalias nocapture %A, i8* noalias nocapture readonly %B) ; CHECK-ASM-NEXT: .LBB0_1: # %vector.body ; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu -; CHECK-ASM-NEXT: vlse8.v v25, (a1), a4 +; CHECK-ASM-NEXT: vlse8.v v8, (a1), a4 ; CHECK-ASM-NEXT: add a3, a0, a2 -; CHECK-ASM-NEXT: vle8.v v26, (a3) -; CHECK-ASM-NEXT: vadd.vv v25, v26, v25 -; CHECK-ASM-NEXT: vse8.v v25, (a3) +; CHECK-ASM-NEXT: vle8.v v9, (a3) +; CHECK-ASM-NEXT: vadd.vv v8, v9, v8 +; CHECK-ASM-NEXT: vse8.v v8, (a3) ; CHECK-ASM-NEXT: addi a2, a2, 32 ; CHECK-ASM-NEXT: addi a1, a1, 160 ; CHECK-ASM-NEXT: bne a2, a5, .LBB0_1 @@ -107,12 +107,12 @@ define void @gather_masked(i8* noalias nocapture %A, i8* noalias nocapture reado ; CHECK-ASM-NEXT: .LBB1_1: # %vector.body ; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu -; CHECK-ASM-NEXT: vmv1r.v v25, v8 -; CHECK-ASM-NEXT: vlse8.v v25, (a1), a4, v0.t +; CHECK-ASM-NEXT: vmv1r.v v9, v8 +; CHECK-ASM-NEXT: vlse8.v v9, (a1), a4, v0.t ; CHECK-ASM-NEXT: add a3, a0, a2 -; CHECK-ASM-NEXT: vle8.v v26, (a3) -; CHECK-ASM-NEXT: vadd.vv v25, v26, v25 -; CHECK-ASM-NEXT: vse8.v v25, (a3) +; CHECK-ASM-NEXT: vle8.v v10, (a3) +; CHECK-ASM-NEXT: vadd.vv v9, v10, v9 +; CHECK-ASM-NEXT: vse8.v v9, (a3) ; CHECK-ASM-NEXT: addi a2, a2, 32 ; CHECK-ASM-NEXT: addi a1, a1, 160 ; CHECK-ASM-NEXT: bne a2, a5, .LBB1_1 @@ -174,11 +174,11 @@ define void @gather_negative_stride(i8* noalias nocapture %A, i8* noalias nocapt ; CHECK-ASM-NEXT: .LBB2_1: # %vector.body ; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu -; CHECK-ASM-NEXT: vlse8.v v25, (a1), a4 +; CHECK-ASM-NEXT: vlse8.v v8, (a1), a4 ; CHECK-ASM-NEXT: add a3, a0, a2 -; CHECK-ASM-NEXT: vle8.v v26, (a3) -; CHECK-ASM-NEXT: vadd.vv v25, v26, v25 -; CHECK-ASM-NEXT: vse8.v v25, (a3) +; CHECK-ASM-NEXT: vle8.v v9, (a3) +; CHECK-ASM-NEXT: vadd.vv v8, v9, v8 +; CHECK-ASM-NEXT: vse8.v v8, (a3) ; CHECK-ASM-NEXT: addi a2, a2, 32 ; CHECK-ASM-NEXT: addi a1, a1, 160 ; CHECK-ASM-NEXT: bne a2, a5, .LBB2_1 @@ -238,11 +238,11 @@ define void @gather_zero_stride(i8* noalias nocapture %A, i8* noalias nocapture ; CHECK-ASM-NEXT: .LBB3_1: # %vector.body ; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: vsetvli zero, a3, e8, m1, ta, mu -; CHECK-ASM-NEXT: vlse8.v v25, (a1), zero +; CHECK-ASM-NEXT: vlse8.v v8, (a1), zero ; CHECK-ASM-NEXT: add a5, a0, a2 -; CHECK-ASM-NEXT: vle8.v v26, (a5) -; CHECK-ASM-NEXT: vadd.vv v25, v26, v25 -; CHECK-ASM-NEXT: vse8.v v25, (a5) +; CHECK-ASM-NEXT: vle8.v v9, (a5) +; CHECK-ASM-NEXT: vadd.vv v8, v9, v8 +; CHECK-ASM-NEXT: vse8.v v8, (a5) ; CHECK-ASM-NEXT: addi a2, a2, 32 ; CHECK-ASM-NEXT: addi a1, a1, 160 ; CHECK-ASM-NEXT: bne a2, a4, .LBB3_1 @@ -310,10 +310,10 @@ define void @scatter(i8* noalias nocapture %A, i8* noalias nocapture readonly %B ; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: add a3, a1, a2 ; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu -; CHECK-ASM-NEXT: vle8.v v25, (a3) -; CHECK-ASM-NEXT: vlse8.v v26, (a0), a4 -; CHECK-ASM-NEXT: vadd.vv v25, v26, v25 -; CHECK-ASM-NEXT: vsse8.v v25, (a0), a4 +; CHECK-ASM-NEXT: vle8.v v8, (a3) +; CHECK-ASM-NEXT: vlse8.v v9, (a0), a4 +; CHECK-ASM-NEXT: vadd.vv v8, v9, v8 +; CHECK-ASM-NEXT: vsse8.v v8, (a0), a4 ; CHECK-ASM-NEXT: addi a2, a2, 32 ; CHECK-ASM-NEXT: addi a0, a0, 160 ; CHECK-ASM-NEXT: bne a2, a5, .LBB4_1 @@ -380,11 +380,11 @@ define void @scatter_masked(i8* noalias nocapture %A, i8* noalias nocapture read ; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: add a3, a1, a2 ; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu -; CHECK-ASM-NEXT: vle8.v v25, (a3) -; CHECK-ASM-NEXT: vmv1r.v v26, v8 -; CHECK-ASM-NEXT: vlse8.v v26, (a0), a4, v0.t -; CHECK-ASM-NEXT: vadd.vv v25, v26, v25 -; CHECK-ASM-NEXT: vsse8.v v25, (a0), a4, v0.t +; CHECK-ASM-NEXT: vle8.v v9, (a3) +; CHECK-ASM-NEXT: vmv1r.v v10, v8 +; CHECK-ASM-NEXT: vlse8.v v10, (a0), a4, v0.t +; CHECK-ASM-NEXT: vadd.vv v9, v10, v9 +; CHECK-ASM-NEXT: vsse8.v v9, (a0), a4, v0.t ; CHECK-ASM-NEXT: addi a2, a2, 32 ; CHECK-ASM-NEXT: addi a0, a0, 160 ; CHECK-ASM-NEXT: bne a2, a5, .LBB5_1 @@ -448,13 +448,13 @@ define void @gather_pow2(i32* noalias nocapture %A, i32* noalias nocapture reado ; CHECK-ASM-NEXT: .LBB6_1: # %vector.body ; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: vsetivli zero, 8, e32, m1, ta, mu -; CHECK-ASM-NEXT: vlse32.v v25, (a1), a3 +; CHECK-ASM-NEXT: vlse32.v v8, (a1), a3 ; CHECK-ASM-NEXT: vsetvli zero, a4, e8, m1, ta, mu -; CHECK-ASM-NEXT: vle8.v v26, (a0) +; CHECK-ASM-NEXT: vle8.v v9, (a0) ; CHECK-ASM-NEXT: vsetivli zero, 8, e32, m1, ta, mu -; CHECK-ASM-NEXT: vadd.vv v25, v26, v25 +; CHECK-ASM-NEXT: vadd.vv v8, v9, v8 ; CHECK-ASM-NEXT: vsetvli zero, a4, e8, m1, ta, mu -; CHECK-ASM-NEXT: vse8.v v25, (a0) +; CHECK-ASM-NEXT: vse8.v v8, (a0) ; CHECK-ASM-NEXT: addi a2, a2, -8 ; CHECK-ASM-NEXT: addi a0, a0, 32 ; CHECK-ASM-NEXT: addi a1, a1, 128 @@ -523,11 +523,11 @@ define void @scatter_pow2(i32* noalias nocapture %A, i32* noalias nocapture read ; CHECK-ASM-NEXT: .LBB7_1: # %vector.body ; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: vsetvli zero, a3, e8, m1, ta, mu -; CHECK-ASM-NEXT: vle8.v v25, (a1) +; CHECK-ASM-NEXT: vle8.v v8, (a1) ; CHECK-ASM-NEXT: vsetivli zero, 8, e32, m1, ta, mu -; CHECK-ASM-NEXT: vlse32.v v26, (a0), a4 -; CHECK-ASM-NEXT: vadd.vv v25, v26, v25 -; CHECK-ASM-NEXT: vsse32.v v25, (a0), a4 +; CHECK-ASM-NEXT: vlse32.v v9, (a0), a4 +; CHECK-ASM-NEXT: vadd.vv v8, v9, v8 +; CHECK-ASM-NEXT: vsse32.v v8, (a0), a4 ; CHECK-ASM-NEXT: addi a2, a2, -8 ; CHECK-ASM-NEXT: addi a1, a1, 32 ; CHECK-ASM-NEXT: addi a0, a0, 128 @@ -609,15 +609,15 @@ define void @struct_gather(i32* noalias nocapture %A, %struct.foo* noalias nocap ; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: addi a4, a1, -128 ; CHECK-ASM-NEXT: vsetivli zero, 8, e32, m1, ta, mu -; CHECK-ASM-NEXT: vlse32.v v25, (a4), a3 -; CHECK-ASM-NEXT: vlse32.v v26, (a1), a3 +; CHECK-ASM-NEXT: vlse32.v v8, (a4), a3 +; CHECK-ASM-NEXT: vlse32.v v9, (a1), a3 ; CHECK-ASM-NEXT: addi a4, a0, -32 -; CHECK-ASM-NEXT: vle32.v v27, (a4) -; CHECK-ASM-NEXT: vle32.v v28, (a0) -; CHECK-ASM-NEXT: vadd.vv v25, v27, v25 -; CHECK-ASM-NEXT: vadd.vv v26, v28, v26 -; CHECK-ASM-NEXT: vse32.v v25, (a4) -; CHECK-ASM-NEXT: vse32.v v26, (a0) +; CHECK-ASM-NEXT: vle32.v v10, (a4) +; CHECK-ASM-NEXT: vle32.v v11, (a0) +; CHECK-ASM-NEXT: vadd.vv v8, v10, v8 +; CHECK-ASM-NEXT: vadd.vv v9, v11, v9 +; CHECK-ASM-NEXT: vse32.v v8, (a4) +; CHECK-ASM-NEXT: vse32.v v9, (a0) ; CHECK-ASM-NEXT: addi a2, a2, -16 ; CHECK-ASM-NEXT: addi a0, a0, 64 ; CHECK-ASM-NEXT: addi a1, a1, 256 @@ -748,28 +748,28 @@ define void @gather_unroll(i32* noalias nocapture %A, i32* noalias nocapture rea ; CHECK-ASM-NEXT: .LBB9_1: # %vector.body ; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: vsetivli zero, 8, e32, m1, ta, mu -; CHECK-ASM-NEXT: vlse32.v v25, (a1), a3 -; CHECK-ASM-NEXT: vlse32.v v26, (a0), a4 -; CHECK-ASM-NEXT: vadd.vv v25, v26, v25 -; CHECK-ASM-NEXT: vsse32.v v25, (a0), a4 +; CHECK-ASM-NEXT: vlse32.v v8, (a1), a3 +; CHECK-ASM-NEXT: vlse32.v v9, (a0), a4 +; CHECK-ASM-NEXT: vadd.vv v8, v9, v8 +; CHECK-ASM-NEXT: vsse32.v v8, (a0), a4 ; CHECK-ASM-NEXT: addi a5, a1, 16 -; CHECK-ASM-NEXT: vlse32.v v25, (a5), a3 +; CHECK-ASM-NEXT: vlse32.v v8, (a5), a3 ; CHECK-ASM-NEXT: addi a5, a0, 4 -; CHECK-ASM-NEXT: vlse32.v v26, (a5), a4 -; CHECK-ASM-NEXT: vadd.vv v25, v26, v25 -; CHECK-ASM-NEXT: vsse32.v v25, (a5), a4 +; CHECK-ASM-NEXT: vlse32.v v9, (a5), a4 +; CHECK-ASM-NEXT: vadd.vv v8, v9, v8 +; CHECK-ASM-NEXT: vsse32.v v8, (a5), a4 ; CHECK-ASM-NEXT: addi a5, a1, 32 -; CHECK-ASM-NEXT: vlse32.v v25, (a5), a3 +; CHECK-ASM-NEXT: vlse32.v v8, (a5), a3 ; CHECK-ASM-NEXT: addi a5, a0, 8 -; CHECK-ASM-NEXT: vlse32.v v26, (a5), a4 -; CHECK-ASM-NEXT: vadd.vv v25, v26, v25 -; CHECK-ASM-NEXT: vsse32.v v25, (a5), a4 +; CHECK-ASM-NEXT: vlse32.v v9, (a5), a4 +; CHECK-ASM-NEXT: vadd.vv v8, v9, v8 +; CHECK-ASM-NEXT: vsse32.v v8, (a5), a4 ; CHECK-ASM-NEXT: addi a5, a1, 48 -; CHECK-ASM-NEXT: vlse32.v v25, (a5), a3 +; CHECK-ASM-NEXT: vlse32.v v8, (a5), a3 ; CHECK-ASM-NEXT: addi a5, a0, 12 -; CHECK-ASM-NEXT: vlse32.v v26, (a5), a4 -; CHECK-ASM-NEXT: vadd.vv v25, v26, v25 -; CHECK-ASM-NEXT: vsse32.v v25, (a5), a4 +; CHECK-ASM-NEXT: vlse32.v v9, (a5), a4 +; CHECK-ASM-NEXT: vadd.vv v8, v9, v8 +; CHECK-ASM-NEXT: vsse32.v v8, (a5), a4 ; CHECK-ASM-NEXT: addi a2, a2, -8 ; CHECK-ASM-NEXT: addi a1, a1, 512 ; CHECK-ASM-NEXT: addi a0, a0, 128 @@ -863,11 +863,11 @@ define void @gather_of_pointers(i32** noalias nocapture %0, i32** noalias nocapt ; CHECK-ASM-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: addi a4, a1, 80 ; CHECK-ASM-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-ASM-NEXT: vlse64.v v25, (a1), a3 -; CHECK-ASM-NEXT: vlse64.v v26, (a4), a3 +; CHECK-ASM-NEXT: vlse64.v v8, (a1), a3 +; CHECK-ASM-NEXT: vlse64.v v9, (a4), a3 ; CHECK-ASM-NEXT: addi a4, a0, -16 -; CHECK-ASM-NEXT: vse64.v v25, (a4) -; CHECK-ASM-NEXT: vse64.v v26, (a0) +; CHECK-ASM-NEXT: vse64.v v8, (a4) +; CHECK-ASM-NEXT: vse64.v v9, (a0) ; CHECK-ASM-NEXT: addi a2, a2, -4 ; CHECK-ASM-NEXT: addi a0, a0, 32 ; CHECK-ASM-NEXT: addi a1, a1, 160 @@ -939,11 +939,11 @@ define void @scatter_of_pointers(i32** noalias nocapture %0, i32** noalias nocap ; CHECK-ASM-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: addi a4, a1, -16 ; CHECK-ASM-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-ASM-NEXT: vle64.v v25, (a4) -; CHECK-ASM-NEXT: vle64.v v26, (a1) +; CHECK-ASM-NEXT: vle64.v v8, (a4) +; CHECK-ASM-NEXT: vle64.v v9, (a1) ; CHECK-ASM-NEXT: addi a4, a0, 80 -; CHECK-ASM-NEXT: vsse64.v v25, (a0), a3 -; CHECK-ASM-NEXT: vsse64.v v26, (a4), a3 +; CHECK-ASM-NEXT: vsse64.v v8, (a0), a3 +; CHECK-ASM-NEXT: vsse64.v v9, (a4), a3 ; CHECK-ASM-NEXT: addi a2, a2, -4 ; CHECK-ASM-NEXT: addi a1, a1, 32 ; CHECK-ASM-NEXT: addi a0, a0, 160 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll index f3b380bafd1baf6a53993d9a99f4cbcd52430ef9..ce06f8faf4c34e2809425aedfdda637aac9e494d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll @@ -8,10 +8,10 @@ define void @abs_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: abs_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vrsub.vi v26, v25, 0 -; CHECK-NEXT: vmax.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vrsub.vi v9, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %a, i1 false) @@ -24,10 +24,10 @@ define void @abs_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: abs_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vrsub.vi v26, v25, 0 -; CHECK-NEXT: vmax.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vrsub.vi v9, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a, i1 false) @@ -40,10 +40,10 @@ define void @abs_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: abs_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vrsub.vi v26, v25, 0 -; CHECK-NEXT: vmax.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vrsub.vi v9, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a, i1 false) @@ -56,10 +56,10 @@ define void @abs_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: abs_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vrsub.vi v26, v25, 0 -; CHECK-NEXT: vmax.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vrsub.vi v9, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a, i1 false) @@ -73,38 +73,38 @@ define void @abs_v32i8(<32 x i8>* %x) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a1, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vrsub.vi v28, v26, 0 -; LMULMAX2-NEXT: vmax.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vrsub.vi v10, v8, 0 +; LMULMAX2-NEXT: vmax.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: abs_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v25, (a1) -; LMULMAX1-RV32-NEXT: vle8.v v26, (a0) -; LMULMAX1-RV32-NEXT: vrsub.vi v27, v25, 0 -; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vrsub.vi v27, v26, 0 -; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vse8.v v26, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a1) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a0) +; LMULMAX1-RV32-NEXT: vrsub.vi v10, v8, 0 +; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vrsub.vi v10, v9, 0 +; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vse8.v v9, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v8, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: abs_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v25, (a1) -; LMULMAX1-RV64-NEXT: vle8.v v26, (a0) -; LMULMAX1-RV64-NEXT: vrsub.vi v27, v25, 0 -; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v27 -; LMULMAX1-RV64-NEXT: vrsub.vi v27, v26, 0 -; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vse8.v v26, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v25, (a1) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a1) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a0) +; LMULMAX1-RV64-NEXT: vrsub.vi v10, v8, 0 +; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v10 +; LMULMAX1-RV64-NEXT: vrsub.vi v10, v9, 0 +; LMULMAX1-RV64-NEXT: vmax.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vse8.v v9, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v8, (a1) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %a, i1 false) @@ -117,38 +117,38 @@ define void @abs_v16i16(<16 x i16>* %x) { ; LMULMAX2-LABEL: abs_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vrsub.vi v28, v26, 0 -; LMULMAX2-NEXT: vmax.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vrsub.vi v10, v8, 0 +; LMULMAX2-NEXT: vmax.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: abs_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v25, (a1) -; LMULMAX1-RV32-NEXT: vle16.v v26, (a0) -; LMULMAX1-RV32-NEXT: vrsub.vi v27, v25, 0 -; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vrsub.vi v27, v26, 0 -; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vse16.v v26, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a1) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a0) +; LMULMAX1-RV32-NEXT: vrsub.vi v10, v8, 0 +; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vrsub.vi v10, v9, 0 +; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vse16.v v9, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v8, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: abs_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v25, (a1) -; LMULMAX1-RV64-NEXT: vle16.v v26, (a0) -; LMULMAX1-RV64-NEXT: vrsub.vi v27, v25, 0 -; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v27 -; LMULMAX1-RV64-NEXT: vrsub.vi v27, v26, 0 -; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vse16.v v26, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v25, (a1) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a1) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a0) +; LMULMAX1-RV64-NEXT: vrsub.vi v10, v8, 0 +; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v10 +; LMULMAX1-RV64-NEXT: vrsub.vi v10, v9, 0 +; LMULMAX1-RV64-NEXT: vmax.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vse16.v v9, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v8, (a1) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a, i1 false) @@ -161,38 +161,38 @@ define void @abs_v8i32(<8 x i32>* %x) { ; LMULMAX2-LABEL: abs_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vrsub.vi v28, v26, 0 -; LMULMAX2-NEXT: vmax.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vrsub.vi v10, v8, 0 +; LMULMAX2-NEXT: vmax.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: abs_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) -; LMULMAX1-RV32-NEXT: vle32.v v26, (a0) -; LMULMAX1-RV32-NEXT: vrsub.vi v27, v25, 0 -; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vrsub.vi v27, v26, 0 -; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vse32.v v26, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a0) +; LMULMAX1-RV32-NEXT: vrsub.vi v10, v8, 0 +; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vrsub.vi v10, v9, 0 +; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vse32.v v9, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: abs_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v25, (a1) -; LMULMAX1-RV64-NEXT: vle32.v v26, (a0) -; LMULMAX1-RV64-NEXT: vrsub.vi v27, v25, 0 -; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v27 -; LMULMAX1-RV64-NEXT: vrsub.vi v27, v26, 0 -; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vse32.v v26, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v25, (a1) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a0) +; LMULMAX1-RV64-NEXT: vrsub.vi v10, v8, 0 +; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v10 +; LMULMAX1-RV64-NEXT: vrsub.vi v10, v9, 0 +; LMULMAX1-RV64-NEXT: vmax.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vse32.v v9, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a, i1 false) @@ -205,38 +205,38 @@ define void @abs_v4i64(<4 x i64>* %x) { ; LMULMAX2-LABEL: abs_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vrsub.vi v28, v26, 0 -; LMULMAX2-NEXT: vmax.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vrsub.vi v10, v8, 0 +; LMULMAX2-NEXT: vmax.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: abs_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v25, (a1) -; LMULMAX1-RV32-NEXT: vle64.v v26, (a0) -; LMULMAX1-RV32-NEXT: vrsub.vi v27, v25, 0 -; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vrsub.vi v27, v26, 0 -; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vse64.v v26, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a1) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a0) +; LMULMAX1-RV32-NEXT: vrsub.vi v10, v8, 0 +; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vrsub.vi v10, v9, 0 +; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vse64.v v9, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v8, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: abs_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v25, (a1) -; LMULMAX1-RV64-NEXT: vle64.v v26, (a0) -; LMULMAX1-RV64-NEXT: vrsub.vi v27, v25, 0 -; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v27 -; LMULMAX1-RV64-NEXT: vrsub.vi v27, v26, 0 -; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v25, (a1) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a1) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a0) +; LMULMAX1-RV64-NEXT: vrsub.vi v10, v8, 0 +; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v10 +; LMULMAX1-RV64-NEXT: vrsub.vi v10, v9, 0 +; LMULMAX1-RV64-NEXT: vmax.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vse64.v v9, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v8, (a1) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a, i1 false) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll index b0a46cfaa85672c0cf0c550f235d96f9acf890cc..6d24d0b440574f676be5af3df0dffca74ef4a7b4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll @@ -79,8 +79,8 @@ define i64 @bitcast_v8i8_i64(<8 x i8> %a) { ; RV32: # %bb.0: ; RV32-NEXT: addi a0, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v8, a0 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; @@ -98,8 +98,8 @@ define i64 @bitcast_v4i16_i64(<4 x i16> %a) { ; RV32: # %bb.0: ; RV32-NEXT: addi a0, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v8, a0 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; @@ -117,8 +117,8 @@ define i64 @bitcast_v2i32_i64(<2 x i32> %a) { ; RV32: # %bb.0: ; RV32-NEXT: addi a0, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v8, a0 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; @@ -136,8 +136,8 @@ define i64 @bitcast_v1i64_i64(<1 x i64> %a) { ; RV32: # %bb.0: ; RV32-NEXT: addi a0, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v8, a0 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; @@ -205,8 +205,8 @@ define double @bitcast_v8i8_f64(<8 x i8> %a) { ; RV32: # %bb.0: ; RV32-NEXT: addi a0, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v8, a0 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; @@ -224,8 +224,8 @@ define double @bitcast_v4i16_f64(<4 x i16> %a) { ; RV32: # %bb.0: ; RV32-NEXT: addi a0, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v8, a0 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; @@ -243,8 +243,8 @@ define double @bitcast_v2i32_f64(<2 x i32> %a) { ; RV32: # %bb.0: ; RV32-NEXT: addi a0, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v8, a0 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; @@ -262,8 +262,8 @@ define double @bitcast_v1i64_f64(<1 x i64> %a) { ; RV32: # %bb.0: ; RV32-NEXT: addi a0, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v8, a0 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; @@ -322,11 +322,11 @@ define <4 x i16> @bitcast_i64_v4i16(i64 %a) { ; RV32-LABEL: bitcast_i64_v4i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 -; RV32-NEXT: vslide1up.vx v26, v25, a1 -; RV32-NEXT: vslide1up.vx v25, v26, a0 +; RV32-NEXT: vmv.v.i v8, 0 +; RV32-NEXT: vslide1up.vx v9, v8, a1 +; RV32-NEXT: vslide1up.vx v10, v9, a0 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vslideup.vi v8, v25, 0 +; RV32-NEXT: vslideup.vi v8, v10, 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_i64_v4i16: @@ -342,11 +342,11 @@ define <2 x i32> @bitcast_i64_v2i32(i64 %a) { ; RV32-LABEL: bitcast_i64_v2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 -; RV32-NEXT: vslide1up.vx v26, v25, a1 -; RV32-NEXT: vslide1up.vx v25, v26, a0 +; RV32-NEXT: vmv.v.i v8, 0 +; RV32-NEXT: vslide1up.vx v9, v8, a1 +; RV32-NEXT: vslide1up.vx v10, v9, a0 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vslideup.vi v8, v25, 0 +; RV32-NEXT: vslideup.vi v8, v10, 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_i64_v2i32: @@ -362,11 +362,11 @@ define <1 x i64> @bitcast_i64_v1i64(i64 %a) { ; RV32-LABEL: bitcast_i64_v1i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 -; RV32-NEXT: vslide1up.vx v26, v25, a1 -; RV32-NEXT: vslide1up.vx v25, v26, a0 +; RV32-NEXT: vmv.v.i v8, 0 +; RV32-NEXT: vslide1up.vx v9, v8, a1 +; RV32-NEXT: vslide1up.vx v10, v9, a0 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vslideup.vi v8, v25, 0 +; RV32-NEXT: vslideup.vi v8, v10, 0 ; RV32-NEXT: ret ; ; RV64-LABEL: bitcast_i64_v1i64: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll index c857165debd1f40ef03c304a9d0e0f4ea12e2454..ca0b59eb2672d67f4658223f177d3453b9cf8048 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll @@ -8,125 +8,125 @@ define void @bitreverse_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-LABEL: bitreverse_v8i16: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle16.v v25, (a0) -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 8 -; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 8 -; LMULMAX2-RV32-NEXT: vor.vv v25, v25, v26 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 4 +; LMULMAX2-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 8 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 8 +; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v9 +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 4 ; LMULMAX2-RV32-NEXT: lui a1, 1 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 4 -; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 2 +; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 4 +; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 2 ; LMULMAX2-RV32-NEXT: lui a1, 3 ; LMULMAX2-RV32-NEXT: addi a1, a1, 819 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 2 -; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 2 +; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX2-RV32-NEXT: lui a1, 5 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1365 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV32-NEXT: vadd.vv v25, v25, v25 -; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV32-NEXT: vse16.v v25, (a0) +; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v8 +; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bitreverse_v8i16: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle16.v v25, (a0) -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 8 -; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 8 -; LMULMAX2-RV64-NEXT: vor.vv v25, v25, v26 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 4 +; LMULMAX2-RV64-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 8 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 8 +; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v9 +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 4 ; LMULMAX2-RV64-NEXT: lui a1, 1 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -241 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 4 -; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 2 +; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4 +; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 2 ; LMULMAX2-RV64-NEXT: lui a1, 3 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 819 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 2 -; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 2 +; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX2-RV64-NEXT: lui a1, 5 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vadd.vv v25, v25, v25 -; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV64-NEXT: vse16.v v25, (a0) +; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8 +; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bitreverse_v8i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 8 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 8 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v26 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 4 +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 8 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 8 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v9 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4 ; LMULMAX1-RV32-NEXT: lui a1, 1 ; LMULMAX1-RV32-NEXT: addi a1, a1, -241 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 4 -; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 2 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4 +; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 2 ; LMULMAX1-RV32-NEXT: lui a1, 3 ; LMULMAX1-RV32-NEXT: addi a1, a1, 819 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 2 -; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2 +; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX1-RV32-NEXT: lui a1, 5 ; LMULMAX1-RV32-NEXT: addi a1, a1, 1365 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v25 -; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8 +; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bitreverse_v8i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 8 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 8 -; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v26 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 4 +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 8 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 8 +; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v9 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 4 ; LMULMAX1-RV64-NEXT: lui a1, 1 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -241 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 4 -; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 2 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4 +; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 2 ; LMULMAX1-RV64-NEXT: lui a1, 3 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 819 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 2 -; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2 +; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX1-RV64-NEXT: lui a1, 5 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 1365 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v25 -; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8 +; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -140,161 +140,161 @@ define void @bitreverse_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-LABEL: bitreverse_v4i32: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle32.v v25, (a0) -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 8 +; LMULMAX2-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 8 ; LMULMAX2-RV32-NEXT: lui a1, 16 ; LMULMAX2-RV32-NEXT: addi a1, a1, -256 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vsrl.vi v27, v25, 24 -; LMULMAX2-RV32-NEXT: vor.vv v26, v26, v27 -; LMULMAX2-RV32-NEXT: vsll.vi v27, v25, 8 +; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 24 +; LMULMAX2-RV32-NEXT: vor.vv v9, v9, v10 +; LMULMAX2-RV32-NEXT: vsll.vi v10, v8, 8 ; LMULMAX2-RV32-NEXT: lui a1, 4080 -; LMULMAX2-RV32-NEXT: vand.vx v27, v27, a1 -; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 24 -; LMULMAX2-RV32-NEXT: vor.vv v25, v25, v27 -; LMULMAX2-RV32-NEXT: vor.vv v25, v25, v26 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 4 +; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 24 +; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v9 +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 4 ; LMULMAX2-RV32-NEXT: lui a1, 61681 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 4 -; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 2 +; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 4 +; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 2 ; LMULMAX2-RV32-NEXT: lui a1, 209715 ; LMULMAX2-RV32-NEXT: addi a1, a1, 819 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 2 -; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 2 +; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX2-RV32-NEXT: lui a1, 349525 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1365 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV32-NEXT: vadd.vv v25, v25, v25 -; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v8 +; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bitreverse_v4i32: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle32.v v25, (a0) -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 8 +; LMULMAX2-RV64-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 8 ; LMULMAX2-RV64-NEXT: lui a1, 16 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -256 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vsrl.vi v27, v25, 24 -; LMULMAX2-RV64-NEXT: vor.vv v26, v26, v27 -; LMULMAX2-RV64-NEXT: vsll.vi v27, v25, 8 +; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 24 +; LMULMAX2-RV64-NEXT: vor.vv v9, v9, v10 +; LMULMAX2-RV64-NEXT: vsll.vi v10, v8, 8 ; LMULMAX2-RV64-NEXT: lui a1, 4080 -; LMULMAX2-RV64-NEXT: vand.vx v27, v27, a1 -; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 24 -; LMULMAX2-RV64-NEXT: vor.vv v25, v25, v27 -; LMULMAX2-RV64-NEXT: vor.vv v25, v25, v26 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 4 +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 24 +; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10 +; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v9 +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 4 ; LMULMAX2-RV64-NEXT: lui a1, 61681 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -241 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 4 -; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 2 +; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4 +; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 2 ; LMULMAX2-RV64-NEXT: lui a1, 209715 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 819 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 2 -; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 2 +; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX2-RV64-NEXT: lui a1, 349525 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vadd.vv v25, v25, v25 -; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV64-NEXT: vse32.v v25, (a0) +; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8 +; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bitreverse_v4i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 8 +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 8 ; LMULMAX1-RV32-NEXT: lui a1, 16 ; LMULMAX1-RV32-NEXT: addi a1, a1, -256 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 24 -; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsll.vi v27, v25, 8 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 24 +; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsll.vi v10, v8, 8 ; LMULMAX1-RV32-NEXT: lui a1, 4080 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a1 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 24 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v26 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 4 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a1 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v9 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4 ; LMULMAX1-RV32-NEXT: lui a1, 61681 ; LMULMAX1-RV32-NEXT: addi a1, a1, -241 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 4 -; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 2 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4 +; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 2 ; LMULMAX1-RV32-NEXT: lui a1, 209715 ; LMULMAX1-RV32-NEXT: addi a1, a1, 819 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 2 -; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2 +; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX1-RV32-NEXT: lui a1, 349525 ; LMULMAX1-RV32-NEXT: addi a1, a1, 1365 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v25 -; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8 +; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bitreverse_v4i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 8 +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 8 ; LMULMAX1-RV64-NEXT: lui a1, 16 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -256 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 24 -; LMULMAX1-RV64-NEXT: vor.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vsll.vi v27, v25, 8 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 24 +; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vsll.vi v10, v8, 8 ; LMULMAX1-RV64-NEXT: lui a1, 4080 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a1 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 24 -; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v27 -; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v26 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 4 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 24 +; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 +; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v9 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 4 ; LMULMAX1-RV64-NEXT: lui a1, 61681 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -241 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 4 -; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 2 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4 +; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 2 ; LMULMAX1-RV64-NEXT: lui a1, 209715 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 819 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 2 -; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2 +; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX1-RV64-NEXT: lui a1, 349525 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 1365 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v25 -; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8 +; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -308,123 +308,123 @@ define void @bitreverse_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV32-LABEL: bitreverse_v2i64: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi a1, zero, 56 -; LMULMAX2-RV32-NEXT: vsrl.vx v26, v25, a1 +; LMULMAX2-RV32-NEXT: vsrl.vx v9, v8, a1 ; LMULMAX2-RV32-NEXT: addi a2, zero, 40 -; LMULMAX2-RV32-NEXT: vsrl.vx v27, v25, a2 +; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a2 ; LMULMAX2-RV32-NEXT: lui a3, 16 ; LMULMAX2-RV32-NEXT: addi a3, a3, -256 -; LMULMAX2-RV32-NEXT: vand.vx v27, v27, a3 -; LMULMAX2-RV32-NEXT: vor.vv v26, v27, v26 -; LMULMAX2-RV32-NEXT: vsrl.vi v27, v25, 24 +; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a3 +; LMULMAX2-RV32-NEXT: vor.vv v9, v10, v9 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 24 ; LMULMAX2-RV32-NEXT: lui a4, 4080 -; LMULMAX2-RV32-NEXT: vand.vx v27, v27, a4 +; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a4 ; LMULMAX2-RV32-NEXT: addi a5, zero, 5 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a5 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.i v28, 0 +; LMULMAX2-RV32-NEXT: vmv.v.i v11, 0 ; LMULMAX2-RV32-NEXT: lui a5, 1044480 -; LMULMAX2-RV32-NEXT: vmerge.vxm v28, v28, a5, v0 +; LMULMAX2-RV32-NEXT: vmerge.vxm v11, v11, a5, v0 ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vsrl.vi v29, v25, 8 -; LMULMAX2-RV32-NEXT: vand.vv v28, v29, v28 -; LMULMAX2-RV32-NEXT: vor.vv v27, v28, v27 -; LMULMAX2-RV32-NEXT: vor.vv v26, v27, v26 +; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 8 +; LMULMAX2-RV32-NEXT: vand.vv v11, v12, v11 +; LMULMAX2-RV32-NEXT: vor.vv v10, v11, v10 +; LMULMAX2-RV32-NEXT: vor.vv v9, v10, v9 ; LMULMAX2-RV32-NEXT: addi a5, zero, 255 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v27, a5 -; LMULMAX2-RV32-NEXT: vmerge.vim v27, v27, 0, v0 +; LMULMAX2-RV32-NEXT: vmv.v.x v10, a5 +; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 0, v0 ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vsll.vi v28, v25, 8 -; LMULMAX2-RV32-NEXT: vand.vv v27, v28, v27 +; LMULMAX2-RV32-NEXT: vsll.vi v11, v8, 8 +; LMULMAX2-RV32-NEXT: vand.vv v10, v11, v10 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v28, a3 -; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 0, v0 +; LMULMAX2-RV32-NEXT: vmv.v.x v11, a3 +; LMULMAX2-RV32-NEXT: vmerge.vim v11, v11, 0, v0 ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vsll.vi v29, v25, 24 -; LMULMAX2-RV32-NEXT: vand.vv v28, v29, v28 -; LMULMAX2-RV32-NEXT: vor.vv v27, v28, v27 -; LMULMAX2-RV32-NEXT: vsll.vx v28, v25, a2 +; LMULMAX2-RV32-NEXT: vsll.vi v12, v8, 24 +; LMULMAX2-RV32-NEXT: vand.vv v11, v12, v11 +; LMULMAX2-RV32-NEXT: vor.vv v10, v11, v10 +; LMULMAX2-RV32-NEXT: vsll.vx v11, v8, a2 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v29, a4 -; LMULMAX2-RV32-NEXT: vmerge.vim v29, v29, 0, v0 +; LMULMAX2-RV32-NEXT: vmv.v.x v12, a4 +; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 0, v0 ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vand.vv v28, v28, v29 -; LMULMAX2-RV32-NEXT: vsll.vx v25, v25, a1 -; LMULMAX2-RV32-NEXT: vor.vv v25, v25, v28 -; LMULMAX2-RV32-NEXT: vor.vv v25, v25, v27 -; LMULMAX2-RV32-NEXT: vor.vv v25, v25, v26 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 4 +; LMULMAX2-RV32-NEXT: vand.vv v11, v11, v12 +; LMULMAX2-RV32-NEXT: vsll.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v11 +; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v9 +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 4 ; LMULMAX2-RV32-NEXT: lui a1, 61681 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v27, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v27 -; LMULMAX2-RV32-NEXT: vand.vv v25, v25, v27 -; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 4 -; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 2 +; LMULMAX2-RV32-NEXT: vand.vv v9, v9, v10 +; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 4 +; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 2 ; LMULMAX2-RV32-NEXT: lui a1, 209715 ; LMULMAX2-RV32-NEXT: addi a1, a1, 819 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v27, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v27 -; LMULMAX2-RV32-NEXT: vand.vv v25, v25, v27 -; LMULMAX2-RV32-NEXT: vsll.vi v25, v25, 2 -; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX2-RV32-NEXT: vand.vv v9, v9, v10 +; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 2 +; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX2-RV32-NEXT: lui a1, 349525 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1365 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v27, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v27 -; LMULMAX2-RV32-NEXT: vand.vv v25, v25, v27 -; LMULMAX2-RV32-NEXT: vadd.vv v25, v25, v25 -; LMULMAX2-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX2-RV32-NEXT: vand.vv v9, v9, v10 +; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v8 +; LMULMAX2-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bitreverse_v2i64: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi a1, zero, 56 -; LMULMAX2-RV64-NEXT: vsrl.vx v26, v25, a1 +; LMULMAX2-RV64-NEXT: vsrl.vx v9, v8, a1 ; LMULMAX2-RV64-NEXT: addi a2, zero, 40 -; LMULMAX2-RV64-NEXT: vsrl.vx v27, v25, a2 +; LMULMAX2-RV64-NEXT: vsrl.vx v10, v8, a2 ; LMULMAX2-RV64-NEXT: lui a3, 16 ; LMULMAX2-RV64-NEXT: addiw a3, a3, -256 -; LMULMAX2-RV64-NEXT: vand.vx v27, v27, a3 -; LMULMAX2-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX2-RV64-NEXT: vsrl.vi v27, v25, 24 +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a3 +; LMULMAX2-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 24 ; LMULMAX2-RV64-NEXT: lui a3, 4080 -; LMULMAX2-RV64-NEXT: vand.vx v27, v27, a3 -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v25, 8 +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a3 +; LMULMAX2-RV64-NEXT: vsrl.vi v11, v8, 8 ; LMULMAX2-RV64-NEXT: addi a3, zero, 255 ; LMULMAX2-RV64-NEXT: slli a4, a3, 24 -; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a4 -; LMULMAX2-RV64-NEXT: vor.vv v27, v28, v27 -; LMULMAX2-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX2-RV64-NEXT: vsll.vi v27, v25, 8 +; LMULMAX2-RV64-NEXT: vand.vx v11, v11, a4 +; LMULMAX2-RV64-NEXT: vor.vv v10, v11, v10 +; LMULMAX2-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX2-RV64-NEXT: vsll.vi v10, v8, 8 ; LMULMAX2-RV64-NEXT: slli a4, a3, 32 -; LMULMAX2-RV64-NEXT: vand.vx v27, v27, a4 -; LMULMAX2-RV64-NEXT: vsll.vi v28, v25, 24 +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a4 +; LMULMAX2-RV64-NEXT: vsll.vi v11, v8, 24 ; LMULMAX2-RV64-NEXT: slli a4, a3, 40 -; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a4 -; LMULMAX2-RV64-NEXT: vor.vv v27, v28, v27 -; LMULMAX2-RV64-NEXT: vsll.vx v28, v25, a1 -; LMULMAX2-RV64-NEXT: vsll.vx v25, v25, a2 +; LMULMAX2-RV64-NEXT: vand.vx v11, v11, a4 +; LMULMAX2-RV64-NEXT: vor.vv v10, v11, v10 +; LMULMAX2-RV64-NEXT: vsll.vx v11, v8, a1 +; LMULMAX2-RV64-NEXT: vsll.vx v8, v8, a2 ; LMULMAX2-RV64-NEXT: slli a1, a3, 48 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vor.vv v25, v28, v25 -; LMULMAX2-RV64-NEXT: vor.vv v25, v25, v27 -; LMULMAX2-RV64-NEXT: vor.vv v25, v25, v26 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 4 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vor.vv v8, v11, v8 +; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10 +; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v9 +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 4 ; LMULMAX2-RV64-NEXT: lui a1, 3855 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 241 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 @@ -433,11 +433,11 @@ define void @bitreverse_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV64-NEXT: addi a1, a1, 241 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 ; LMULMAX2-RV64-NEXT: addi a1, a1, -241 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 4 -; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 2 +; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4 +; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 2 ; LMULMAX2-RV64-NEXT: lui a1, 13107 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 819 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 @@ -446,11 +446,11 @@ define void @bitreverse_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV64-NEXT: addi a1, a1, 819 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 ; LMULMAX2-RV64-NEXT: addi a1, a1, 819 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vsll.vi v25, v25, 2 -; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 2 +; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX2-RV64-NEXT: lui a1, 21845 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 @@ -459,133 +459,133 @@ define void @bitreverse_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV64-NEXT: addi a1, a1, 1365 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 ; LMULMAX2-RV64-NEXT: addi a1, a1, 1365 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vadd.vv v25, v25, v25 -; LMULMAX2-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX2-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8 +; LMULMAX2-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bitreverse_v2i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a1, zero, 56 -; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a1 +; LMULMAX1-RV32-NEXT: vsrl.vx v9, v8, a1 ; LMULMAX1-RV32-NEXT: addi a2, zero, 40 -; LMULMAX1-RV32-NEXT: vsrl.vx v27, v25, a2 +; LMULMAX1-RV32-NEXT: vsrl.vx v10, v8, a2 ; LMULMAX1-RV32-NEXT: lui a3, 16 ; LMULMAX1-RV32-NEXT: addi a3, a3, -256 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a3 -; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 24 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3 +; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 24 ; LMULMAX1-RV32-NEXT: lui a4, 4080 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a4 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4 ; LMULMAX1-RV32-NEXT: addi a5, zero, 5 ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX1-RV32-NEXT: vmv.s.x v0, a5 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.i v28, 0 +; LMULMAX1-RV32-NEXT: vmv.v.i v11, 0 ; LMULMAX1-RV32-NEXT: lui a5, 1044480 -; LMULMAX1-RV32-NEXT: vmerge.vxm v28, v28, a5, v0 +; LMULMAX1-RV32-NEXT: vmerge.vxm v11, v11, a5, v0 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vsrl.vi v29, v25, 8 -; LMULMAX1-RV32-NEXT: vand.vv v28, v29, v28 -; LMULMAX1-RV32-NEXT: vor.vv v27, v28, v27 -; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26 +; LMULMAX1-RV32-NEXT: vsrl.vi v12, v8, 8 +; LMULMAX1-RV32-NEXT: vand.vv v11, v12, v11 +; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10 +; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV32-NEXT: addi a5, zero, 255 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v27, a5 -; LMULMAX1-RV32-NEXT: vmerge.vim v27, v27, 0, v0 +; LMULMAX1-RV32-NEXT: vmv.v.x v10, a5 +; LMULMAX1-RV32-NEXT: vmerge.vim v10, v10, 0, v0 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vsll.vi v28, v25, 8 -; LMULMAX1-RV32-NEXT: vand.vv v27, v28, v27 +; LMULMAX1-RV32-NEXT: vsll.vi v11, v8, 8 +; LMULMAX1-RV32-NEXT: vand.vv v10, v11, v10 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v28, a3 -; LMULMAX1-RV32-NEXT: vmerge.vim v28, v28, 0, v0 +; LMULMAX1-RV32-NEXT: vmv.v.x v11, a3 +; LMULMAX1-RV32-NEXT: vmerge.vim v11, v11, 0, v0 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vsll.vi v29, v25, 24 -; LMULMAX1-RV32-NEXT: vand.vv v28, v29, v28 -; LMULMAX1-RV32-NEXT: vor.vv v27, v28, v27 -; LMULMAX1-RV32-NEXT: vsll.vx v28, v25, a2 +; LMULMAX1-RV32-NEXT: vsll.vi v12, v8, 24 +; LMULMAX1-RV32-NEXT: vand.vv v11, v12, v11 +; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10 +; LMULMAX1-RV32-NEXT: vsll.vx v11, v8, a2 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v29, a4 -; LMULMAX1-RV32-NEXT: vmerge.vim v29, v29, 0, v0 +; LMULMAX1-RV32-NEXT: vmv.v.x v12, a4 +; LMULMAX1-RV32-NEXT: vmerge.vim v12, v12, 0, v0 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vand.vv v28, v28, v29 -; LMULMAX1-RV32-NEXT: vsll.vx v25, v25, a1 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v26 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 4 +; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v12 +; LMULMAX1-RV32-NEXT: vsll.vx v8, v8, a1 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v9 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4 ; LMULMAX1-RV32-NEXT: lui a1, 61681 ; LMULMAX1-RV32-NEXT: addi a1, a1, -241 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v27, a1 +; LMULMAX1-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 4 -; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 2 +; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4 +; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 2 ; LMULMAX1-RV32-NEXT: lui a1, 209715 ; LMULMAX1-RV32-NEXT: addi a1, a1, 819 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v27, a1 +; LMULMAX1-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 2 -; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2 +; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX1-RV32-NEXT: lui a1, 349525 ; LMULMAX1-RV32-NEXT: addi a1, a1, 1365 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v27, a1 +; LMULMAX1-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v25 -; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8 +; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bitreverse_v2i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a1, zero, 56 -; LMULMAX1-RV64-NEXT: vsrl.vx v26, v25, a1 +; LMULMAX1-RV64-NEXT: vsrl.vx v9, v8, a1 ; LMULMAX1-RV64-NEXT: addi a2, zero, 40 -; LMULMAX1-RV64-NEXT: vsrl.vx v27, v25, a2 +; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a2 ; LMULMAX1-RV64-NEXT: lui a3, 16 ; LMULMAX1-RV64-NEXT: addiw a3, a3, -256 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a3 -; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 24 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 +; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 24 ; LMULMAX1-RV64-NEXT: lui a3, 4080 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a3 -; LMULMAX1-RV64-NEXT: vsrl.vi v28, v25, 8 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 +; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 8 ; LMULMAX1-RV64-NEXT: addi a3, zero, 255 ; LMULMAX1-RV64-NEXT: slli a4, a3, 24 -; LMULMAX1-RV64-NEXT: vand.vx v28, v28, a4 -; LMULMAX1-RV64-NEXT: vor.vv v27, v28, v27 -; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsll.vi v27, v25, 8 +; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4 +; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 +; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsll.vi v10, v8, 8 ; LMULMAX1-RV64-NEXT: slli a4, a3, 32 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a4 -; LMULMAX1-RV64-NEXT: vsll.vi v28, v25, 24 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4 +; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 24 ; LMULMAX1-RV64-NEXT: slli a4, a3, 40 -; LMULMAX1-RV64-NEXT: vand.vx v28, v28, a4 -; LMULMAX1-RV64-NEXT: vor.vv v27, v28, v27 -; LMULMAX1-RV64-NEXT: vsll.vx v28, v25, a1 -; LMULMAX1-RV64-NEXT: vsll.vx v25, v25, a2 +; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4 +; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 +; LMULMAX1-RV64-NEXT: vsll.vx v11, v8, a1 +; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, a2 ; LMULMAX1-RV64-NEXT: slli a1, a3, 48 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vor.vv v25, v28, v25 -; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v27 -; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v26 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 4 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vor.vv v8, v11, v8 +; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 +; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v9 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 4 ; LMULMAX1-RV64-NEXT: lui a1, 3855 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 241 ; LMULMAX1-RV64-NEXT: slli a1, a1, 12 @@ -594,11 +594,11 @@ define void @bitreverse_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV64-NEXT: addi a1, a1, 241 ; LMULMAX1-RV64-NEXT: slli a1, a1, 12 ; LMULMAX1-RV64-NEXT: addi a1, a1, -241 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 4 -; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 2 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4 +; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 2 ; LMULMAX1-RV64-NEXT: lui a1, 13107 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 819 ; LMULMAX1-RV64-NEXT: slli a1, a1, 12 @@ -607,11 +607,11 @@ define void @bitreverse_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV64-NEXT: addi a1, a1, 819 ; LMULMAX1-RV64-NEXT: slli a1, a1, 12 ; LMULMAX1-RV64-NEXT: addi a1, a1, 819 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 2 -; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2 +; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX1-RV64-NEXT: lui a1, 21845 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 1365 ; LMULMAX1-RV64-NEXT: slli a1, a1, 12 @@ -620,11 +620,11 @@ define void @bitreverse_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV64-NEXT: addi a1, a1, 1365 ; LMULMAX1-RV64-NEXT: slli a1, a1, 12 ; LMULMAX1-RV64-NEXT: addi a1, a1, 1365 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v25 -; LMULMAX1-RV64-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8 +; LMULMAX1-RV64-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -638,167 +638,167 @@ define void @bitreverse_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-LABEL: bitreverse_v16i16: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle16.v v26, (a0) -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 8 -; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 8 -; LMULMAX2-RV32-NEXT: vor.vv v26, v26, v28 -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 4 +; LMULMAX2-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 8 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 8 +; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX2-RV32-NEXT: lui a1, 1 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241 -; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 4 -; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 2 +; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 4 +; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX2-RV32-NEXT: lui a1, 3 ; LMULMAX2-RV32-NEXT: addi a1, a1, 819 -; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 2 -; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 1 +; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 2 +; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX2-RV32-NEXT: lui a1, 5 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1365 -; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v26 -; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV32-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v8 +; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bitreverse_v16i16: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle16.v v26, (a0) -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 8 -; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 8 -; LMULMAX2-RV64-NEXT: vor.vv v26, v26, v28 -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 4 +; LMULMAX2-RV64-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 8 +; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX2-RV64-NEXT: lui a1, 1 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -241 -; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 4 -; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 2 +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4 +; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX2-RV64-NEXT: lui a1, 3 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 819 -; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 2 -; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 1 +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 2 +; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX2-RV64-NEXT: lui a1, 5 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365 -; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v26 -; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV64-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8 +; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bitreverse_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v25, (a1) -; LMULMAX1-RV32-NEXT: vle16.v v26, (a0) -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 8 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 8 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 4 +; LMULMAX1-RV32-NEXT: vle16.v v8, (a1) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a0) +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 8 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV32-NEXT: lui a2, 1 ; LMULMAX1-RV32-NEXT: addi a2, a2, -241 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a2 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 4 -; LMULMAX1-RV32-NEXT: vor.vv v25, v27, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 2 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a2 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4 +; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX1-RV32-NEXT: lui a3, 3 ; LMULMAX1-RV32-NEXT: addi a3, a3, 819 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a3 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a3 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 2 -; LMULMAX1-RV32-NEXT: vor.vv v25, v27, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 1 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a3 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2 +; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV32-NEXT: lui a4, 5 ; LMULMAX1-RV32-NEXT: addi a4, a4, 1365 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a4 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a4 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v25 -; LMULMAX1-RV32-NEXT: vor.vv v25, v27, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 8 -; LMULMAX1-RV32-NEXT: vsll.vi v26, v26, 8 -; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 4 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a2 -; LMULMAX1-RV32-NEXT: vsll.vi v26, v26, 4 -; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 2 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a3 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a3 -; LMULMAX1-RV32-NEXT: vsll.vi v26, v26, 2 -; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 1 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a4 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a4 -; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v26 -; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV32-NEXT: vse16.v v26, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v25, (a1) +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8 +; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8 +; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 8 +; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a2 +; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 4 +; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 2 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a3 +; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 2 +; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4 +; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v9 +; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV32-NEXT: vse16.v v9, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v8, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bitreverse_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v25, (a1) -; LMULMAX1-RV64-NEXT: vle16.v v26, (a0) -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 8 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 8 -; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v27 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 4 +; LMULMAX1-RV64-NEXT: vle16.v v8, (a1) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a0) +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 8 +; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV64-NEXT: lui a2, 1 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -241 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a2 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 4 -; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 2 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a2 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4 +; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX1-RV64-NEXT: lui a3, 3 ; LMULMAX1-RV64-NEXT: addiw a3, a3, 819 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a3 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a3 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 2 -; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 1 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2 +; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV64-NEXT: lui a4, 5 ; LMULMAX1-RV64-NEXT: addiw a4, a4, 1365 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a4 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a4 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v25 -; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 8 -; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 8 -; LMULMAX1-RV64-NEXT: vor.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 4 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a2 -; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 4 -; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 2 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a3 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a3 -; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 2 -; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 1 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a4 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a4 -; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v26 -; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vse16.v v26, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v25, (a1) +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8 +; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8 +; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 8 +; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a2 +; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4 +; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3 +; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2 +; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4 +; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9 +; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vse16.v v9, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v8, (a1) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -812,215 +812,215 @@ define void @bitreverse_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-LABEL: bitreverse_v8i32: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle32.v v26, (a0) -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 8 +; LMULMAX2-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX2-RV32-NEXT: lui a1, 16 ; LMULMAX2-RV32-NEXT: addi a1, a1, -256 -; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV32-NEXT: vsrl.vi v30, v26, 24 -; LMULMAX2-RV32-NEXT: vor.vv v28, v28, v30 -; LMULMAX2-RV32-NEXT: vsll.vi v30, v26, 8 +; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24 +; LMULMAX2-RV32-NEXT: vor.vv v10, v10, v12 +; LMULMAX2-RV32-NEXT: vsll.vi v12, v8, 8 ; LMULMAX2-RV32-NEXT: lui a1, 4080 -; LMULMAX2-RV32-NEXT: vand.vx v30, v30, a1 -; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 24 -; LMULMAX2-RV32-NEXT: vor.vv v26, v26, v30 -; LMULMAX2-RV32-NEXT: vor.vv v26, v26, v28 -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 4 +; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a1 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 24 +; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12 +; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX2-RV32-NEXT: lui a1, 61681 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241 -; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 4 -; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 2 +; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 4 +; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX2-RV32-NEXT: lui a1, 209715 ; LMULMAX2-RV32-NEXT: addi a1, a1, 819 -; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 2 -; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 1 +; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 2 +; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX2-RV32-NEXT: lui a1, 349525 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1365 -; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v26 -; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV32-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v8 +; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bitreverse_v8i32: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle32.v v26, (a0) -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 8 +; LMULMAX2-RV64-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX2-RV64-NEXT: lui a1, 16 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -256 -; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV64-NEXT: vsrl.vi v30, v26, 24 -; LMULMAX2-RV64-NEXT: vor.vv v28, v28, v30 -; LMULMAX2-RV64-NEXT: vsll.vi v30, v26, 8 +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24 +; LMULMAX2-RV64-NEXT: vor.vv v10, v10, v12 +; LMULMAX2-RV64-NEXT: vsll.vi v12, v8, 8 ; LMULMAX2-RV64-NEXT: lui a1, 4080 -; LMULMAX2-RV64-NEXT: vand.vx v30, v30, a1 -; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 24 -; LMULMAX2-RV64-NEXT: vor.vv v26, v26, v30 -; LMULMAX2-RV64-NEXT: vor.vv v26, v26, v28 -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 4 +; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a1 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 24 +; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12 +; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX2-RV64-NEXT: lui a1, 61681 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -241 -; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 4 -; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 2 +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4 +; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX2-RV64-NEXT: lui a1, 209715 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 819 -; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 2 -; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 1 +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 2 +; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX2-RV64-NEXT: lui a1, 349525 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365 -; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v26 -; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV64-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8 +; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bitreverse_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) -; LMULMAX1-RV32-NEXT: vle32.v v26, (a0) -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 8 +; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a0) +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX1-RV32-NEXT: lui a2, 16 ; LMULMAX1-RV32-NEXT: addi a2, a2, -256 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV32-NEXT: vsrl.vi v28, v25, 24 -; LMULMAX1-RV32-NEXT: vor.vv v27, v27, v28 -; LMULMAX1-RV32-NEXT: vsll.vi v28, v25, 8 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24 +; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11 +; LMULMAX1-RV32-NEXT: vsll.vi v11, v8, 8 ; LMULMAX1-RV32-NEXT: lui a6, 4080 -; LMULMAX1-RV32-NEXT: vand.vx v28, v28, a6 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 24 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 4 +; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a6 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV32-NEXT: lui a4, 61681 ; LMULMAX1-RV32-NEXT: addi a4, a4, -241 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a4 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a4 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 4 -; LMULMAX1-RV32-NEXT: vor.vv v25, v27, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 2 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4 +; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX1-RV32-NEXT: lui a5, 209715 ; LMULMAX1-RV32-NEXT: addi a5, a5, 819 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a5 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a5 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 2 -; LMULMAX1-RV32-NEXT: vor.vv v25, v27, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 1 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2 +; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV32-NEXT: lui a3, 349525 ; LMULMAX1-RV32-NEXT: addi a3, a3, 1365 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a3 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a3 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v25 -; LMULMAX1-RV32-NEXT: vor.vv v25, v27, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 8 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV32-NEXT: vsrl.vi v28, v26, 24 -; LMULMAX1-RV32-NEXT: vor.vv v27, v27, v28 -; LMULMAX1-RV32-NEXT: vsll.vi v28, v26, 8 -; LMULMAX1-RV32-NEXT: vand.vx v28, v28, a6 -; LMULMAX1-RV32-NEXT: vsll.vi v26, v26, 24 -; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v28 -; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 4 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a4 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a4 -; LMULMAX1-RV32-NEXT: vsll.vi v26, v26, 4 -; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 2 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a5 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a5 -; LMULMAX1-RV32-NEXT: vsll.vi v26, v26, 2 -; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 1 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a3 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a3 -; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v26 -; LMULMAX1-RV32-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV32-NEXT: vse32.v v26, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v25, (a1) +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a3 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8 +; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24 +; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11 +; LMULMAX1-RV32-NEXT: vsll.vi v11, v9, 8 +; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a6 +; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 24 +; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v11 +; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4 +; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 4 +; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 2 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a5 +; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 2 +; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a3 +; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v9 +; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV32-NEXT: vse32.v v9, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bitreverse_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v25, (a1) -; LMULMAX1-RV64-NEXT: vle32.v v26, (a0) -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 8 +; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a0) +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX1-RV64-NEXT: lui a2, 16 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -256 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV64-NEXT: vsrl.vi v28, v25, 24 -; LMULMAX1-RV64-NEXT: vor.vv v27, v27, v28 -; LMULMAX1-RV64-NEXT: vsll.vi v28, v25, 8 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24 +; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11 +; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8 ; LMULMAX1-RV64-NEXT: lui a6, 4080 -; LMULMAX1-RV64-NEXT: vand.vx v28, v28, a6 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 24 -; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v27 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 4 +; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 24 +; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV64-NEXT: lui a4, 61681 ; LMULMAX1-RV64-NEXT: addiw a4, a4, -241 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a4 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a4 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 4 -; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 2 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4 +; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX1-RV64-NEXT: lui a5, 209715 ; LMULMAX1-RV64-NEXT: addiw a5, a5, 819 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a5 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a5 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 2 -; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 1 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2 +; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV64-NEXT: lui a3, 349525 ; LMULMAX1-RV64-NEXT: addiw a3, a3, 1365 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a3 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a3 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v25 -; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 8 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV64-NEXT: vsrl.vi v28, v26, 24 -; LMULMAX1-RV64-NEXT: vor.vv v27, v27, v28 -; LMULMAX1-RV64-NEXT: vsll.vi v28, v26, 8 -; LMULMAX1-RV64-NEXT: vand.vx v28, v28, a6 -; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 24 -; LMULMAX1-RV64-NEXT: vor.vv v26, v26, v28 -; LMULMAX1-RV64-NEXT: vor.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 4 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a4 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a4 -; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 4 -; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 2 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a5 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a5 -; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 2 -; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 1 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a3 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a3 -; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v26 -; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vse32.v v26, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v25, (a1) +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8 +; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24 +; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11 +; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8 +; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6 +; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 24 +; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11 +; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4 +; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4 +; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5 +; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2 +; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3 +; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9 +; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vse32.v v9, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -1034,123 +1034,123 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-LABEL: bitreverse_v4i64: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle64.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi a1, zero, 56 -; LMULMAX2-RV32-NEXT: vsrl.vx v28, v26, a1 +; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a1 ; LMULMAX2-RV32-NEXT: addi a2, zero, 40 -; LMULMAX2-RV32-NEXT: vsrl.vx v30, v26, a2 +; LMULMAX2-RV32-NEXT: vsrl.vx v12, v8, a2 ; LMULMAX2-RV32-NEXT: lui a3, 16 ; LMULMAX2-RV32-NEXT: addi a3, a3, -256 -; LMULMAX2-RV32-NEXT: vand.vx v30, v30, a3 -; LMULMAX2-RV32-NEXT: vor.vv v28, v30, v28 -; LMULMAX2-RV32-NEXT: vsrl.vi v30, v26, 24 +; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a3 +; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10 +; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24 ; LMULMAX2-RV32-NEXT: lui a4, 4080 -; LMULMAX2-RV32-NEXT: vand.vx v30, v30, a4 +; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a4 ; LMULMAX2-RV32-NEXT: addi a5, zero, 85 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a5 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0 ; LMULMAX2-RV32-NEXT: lui a5, 1044480 -; LMULMAX2-RV32-NEXT: vmerge.vxm v8, v8, a5, v0 +; LMULMAX2-RV32-NEXT: vmerge.vxm v14, v14, a5, v0 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vsrl.vi v10, v26, 8 -; LMULMAX2-RV32-NEXT: vand.vv v8, v10, v8 -; LMULMAX2-RV32-NEXT: vor.vv v30, v8, v30 -; LMULMAX2-RV32-NEXT: vor.vv v28, v30, v28 +; LMULMAX2-RV32-NEXT: vsrl.vi v16, v8, 8 +; LMULMAX2-RV32-NEXT: vand.vv v14, v16, v14 +; LMULMAX2-RV32-NEXT: vor.vv v12, v14, v12 +; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10 ; LMULMAX2-RV32-NEXT: addi a5, zero, 255 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v30, a5 -; LMULMAX2-RV32-NEXT: vmerge.vim v30, v30, 0, v0 +; LMULMAX2-RV32-NEXT: vmv.v.x v12, a5 +; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 0, v0 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vsll.vi v8, v26, 8 -; LMULMAX2-RV32-NEXT: vand.vv v30, v8, v30 +; LMULMAX2-RV32-NEXT: vsll.vi v14, v8, 8 +; LMULMAX2-RV32-NEXT: vand.vv v12, v14, v12 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v8, a3 -; LMULMAX2-RV32-NEXT: vmerge.vim v8, v8, 0, v0 +; LMULMAX2-RV32-NEXT: vmv.v.x v14, a3 +; LMULMAX2-RV32-NEXT: vmerge.vim v14, v14, 0, v0 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vsll.vi v10, v26, 24 -; LMULMAX2-RV32-NEXT: vand.vv v8, v10, v8 -; LMULMAX2-RV32-NEXT: vor.vv v30, v8, v30 -; LMULMAX2-RV32-NEXT: vsll.vx v8, v26, a2 +; LMULMAX2-RV32-NEXT: vsll.vi v16, v8, 24 +; LMULMAX2-RV32-NEXT: vand.vv v14, v16, v14 +; LMULMAX2-RV32-NEXT: vor.vv v12, v14, v12 +; LMULMAX2-RV32-NEXT: vsll.vx v14, v8, a2 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v10, a4 -; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 0, v0 +; LMULMAX2-RV32-NEXT: vmv.v.x v16, a4 +; LMULMAX2-RV32-NEXT: vmerge.vim v16, v16, 0, v0 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v10 -; LMULMAX2-RV32-NEXT: vsll.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vor.vv v26, v26, v8 -; LMULMAX2-RV32-NEXT: vor.vv v26, v26, v30 -; LMULMAX2-RV32-NEXT: vor.vv v26, v26, v28 -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 4 +; LMULMAX2-RV32-NEXT: vand.vv v14, v14, v16 +; LMULMAX2-RV32-NEXT: vsll.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v14 +; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12 +; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX2-RV32-NEXT: lui a1, 61681 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v30, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vand.vv v28, v28, v30 -; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v30 -; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 4 -; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 2 +; LMULMAX2-RV32-NEXT: vand.vv v10, v10, v12 +; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v12 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 4 +; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX2-RV32-NEXT: lui a1, 209715 ; LMULMAX2-RV32-NEXT: addi a1, a1, 819 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v30, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vand.vv v28, v28, v30 -; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v30 -; LMULMAX2-RV32-NEXT: vsll.vi v26, v26, 2 -; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 1 +; LMULMAX2-RV32-NEXT: vand.vv v10, v10, v12 +; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v12 +; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 2 +; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX2-RV32-NEXT: lui a1, 349525 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1365 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v30, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vand.vv v28, v28, v30 -; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v30 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v26 -; LMULMAX2-RV32-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV32-NEXT: vand.vv v10, v10, v12 +; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v12 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v8 +; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bitreverse_v4i64: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi a1, zero, 56 -; LMULMAX2-RV64-NEXT: vsrl.vx v28, v26, a1 +; LMULMAX2-RV64-NEXT: vsrl.vx v10, v8, a1 ; LMULMAX2-RV64-NEXT: addi a2, zero, 40 -; LMULMAX2-RV64-NEXT: vsrl.vx v30, v26, a2 +; LMULMAX2-RV64-NEXT: vsrl.vx v12, v8, a2 ; LMULMAX2-RV64-NEXT: lui a3, 16 ; LMULMAX2-RV64-NEXT: addiw a3, a3, -256 -; LMULMAX2-RV64-NEXT: vand.vx v30, v30, a3 -; LMULMAX2-RV64-NEXT: vor.vv v28, v30, v28 -; LMULMAX2-RV64-NEXT: vsrl.vi v30, v26, 24 +; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a3 +; LMULMAX2-RV64-NEXT: vor.vv v10, v12, v10 +; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24 ; LMULMAX2-RV64-NEXT: lui a3, 4080 -; LMULMAX2-RV64-NEXT: vand.vx v30, v30, a3 -; LMULMAX2-RV64-NEXT: vsrl.vi v8, v26, 8 +; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a3 +; LMULMAX2-RV64-NEXT: vsrl.vi v14, v8, 8 ; LMULMAX2-RV64-NEXT: addi a3, zero, 255 ; LMULMAX2-RV64-NEXT: slli a4, a3, 24 -; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a4 -; LMULMAX2-RV64-NEXT: vor.vv v30, v8, v30 -; LMULMAX2-RV64-NEXT: vor.vv v28, v30, v28 -; LMULMAX2-RV64-NEXT: vsll.vi v30, v26, 8 +; LMULMAX2-RV64-NEXT: vand.vx v14, v14, a4 +; LMULMAX2-RV64-NEXT: vor.vv v12, v14, v12 +; LMULMAX2-RV64-NEXT: vor.vv v10, v12, v10 +; LMULMAX2-RV64-NEXT: vsll.vi v12, v8, 8 ; LMULMAX2-RV64-NEXT: slli a4, a3, 32 -; LMULMAX2-RV64-NEXT: vand.vx v30, v30, a4 -; LMULMAX2-RV64-NEXT: vsll.vi v8, v26, 24 +; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a4 +; LMULMAX2-RV64-NEXT: vsll.vi v14, v8, 24 ; LMULMAX2-RV64-NEXT: slli a4, a3, 40 -; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a4 -; LMULMAX2-RV64-NEXT: vor.vv v30, v8, v30 -; LMULMAX2-RV64-NEXT: vsll.vx v8, v26, a1 -; LMULMAX2-RV64-NEXT: vsll.vx v26, v26, a2 +; LMULMAX2-RV64-NEXT: vand.vx v14, v14, a4 +; LMULMAX2-RV64-NEXT: vor.vv v12, v14, v12 +; LMULMAX2-RV64-NEXT: vsll.vx v14, v8, a1 +; LMULMAX2-RV64-NEXT: vsll.vx v8, v8, a2 ; LMULMAX2-RV64-NEXT: slli a1, a3, 48 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vor.vv v26, v8, v26 -; LMULMAX2-RV64-NEXT: vor.vv v26, v26, v30 -; LMULMAX2-RV64-NEXT: vor.vv v26, v26, v28 -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 4 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vor.vv v8, v14, v8 +; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12 +; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX2-RV64-NEXT: lui a1, 3855 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 241 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 @@ -1159,11 +1159,11 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: addi a1, a1, 241 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 ; LMULMAX2-RV64-NEXT: addi a1, a1, -241 -; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 4 -; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 2 +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4 +; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX2-RV64-NEXT: lui a1, 13107 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 819 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 @@ -1172,11 +1172,11 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: addi a1, a1, 819 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 ; LMULMAX2-RV64-NEXT: addi a1, a1, 819 -; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vsll.vi v26, v26, 2 -; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 1 +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 2 +; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX2-RV64-NEXT: lui a1, 21845 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 @@ -1185,174 +1185,174 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: addi a1, a1, 1365 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 ; LMULMAX2-RV64-NEXT: addi a1, a1, 1365 -; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v26 -; LMULMAX2-RV64-NEXT: vor.vv v26, v28, v26 -; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8 +; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bitreverse_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v29, (a1) -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v12, (a1) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, zero, 56 -; LMULMAX1-RV32-NEXT: vsrl.vx v26, v29, a2 +; LMULMAX1-RV32-NEXT: vsrl.vx v9, v12, a2 ; LMULMAX1-RV32-NEXT: addi a3, zero, 40 -; LMULMAX1-RV32-NEXT: vsrl.vx v27, v29, a3 +; LMULMAX1-RV32-NEXT: vsrl.vx v10, v12, a3 ; LMULMAX1-RV32-NEXT: lui a4, 16 ; LMULMAX1-RV32-NEXT: addi a4, a4, -256 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a4 -; LMULMAX1-RV32-NEXT: vor.vv v27, v27, v26 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v29, 24 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4 +; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v9 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v12, 24 ; LMULMAX1-RV32-NEXT: lui a6, 4080 -; LMULMAX1-RV32-NEXT: vand.vx v28, v26, a6 +; LMULMAX1-RV32-NEXT: vand.vx v11, v9, a6 ; LMULMAX1-RV32-NEXT: addi a5, zero, 5 ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX1-RV32-NEXT: vmv.s.x v0, a5 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.i v26, 0 +; LMULMAX1-RV32-NEXT: vmv.v.i v9, 0 ; LMULMAX1-RV32-NEXT: lui a5, 1044480 -; LMULMAX1-RV32-NEXT: vmerge.vxm v26, v26, a5, v0 +; LMULMAX1-RV32-NEXT: vmerge.vxm v9, v9, a5, v0 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vsrl.vi v30, v29, 8 -; LMULMAX1-RV32-NEXT: vand.vv v30, v30, v26 -; LMULMAX1-RV32-NEXT: vor.vv v28, v30, v28 -; LMULMAX1-RV32-NEXT: vor.vv v30, v28, v27 +; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 8 +; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v9 +; LMULMAX1-RV32-NEXT: vor.vv v11, v13, v11 +; LMULMAX1-RV32-NEXT: vor.vv v13, v11, v10 ; LMULMAX1-RV32-NEXT: addi a5, zero, 255 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v27, a5 -; LMULMAX1-RV32-NEXT: vmerge.vim v27, v27, 0, v0 +; LMULMAX1-RV32-NEXT: vmv.v.x v10, a5 +; LMULMAX1-RV32-NEXT: vmerge.vim v10, v10, 0, v0 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vsll.vi v28, v29, 8 -; LMULMAX1-RV32-NEXT: vand.vv v31, v28, v27 +; LMULMAX1-RV32-NEXT: vsll.vi v11, v12, 8 +; LMULMAX1-RV32-NEXT: vand.vv v14, v11, v10 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v28, a4 -; LMULMAX1-RV32-NEXT: vmerge.vim v28, v28, 0, v0 +; LMULMAX1-RV32-NEXT: vmv.v.x v11, a4 +; LMULMAX1-RV32-NEXT: vmerge.vim v11, v11, 0, v0 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vsll.vi v8, v29, 24 -; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v28 -; LMULMAX1-RV32-NEXT: vor.vv v31, v8, v31 -; LMULMAX1-RV32-NEXT: vsll.vx v8, v29, a3 +; LMULMAX1-RV32-NEXT: vsll.vi v15, v12, 24 +; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v11 +; LMULMAX1-RV32-NEXT: vor.vv v14, v15, v14 +; LMULMAX1-RV32-NEXT: vsll.vx v15, v12, a3 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v9, a6 -; LMULMAX1-RV32-NEXT: vmerge.vim v9, v9, 0, v0 +; LMULMAX1-RV32-NEXT: vmv.v.x v16, a6 +; LMULMAX1-RV32-NEXT: vmerge.vim v16, v16, 0, v0 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v9 -; LMULMAX1-RV32-NEXT: vsll.vx v29, v29, a2 -; LMULMAX1-RV32-NEXT: vor.vv v29, v29, v8 -; LMULMAX1-RV32-NEXT: vor.vv v29, v29, v31 -; LMULMAX1-RV32-NEXT: vor.vv v29, v29, v30 -; LMULMAX1-RV32-NEXT: vsrl.vi v30, v29, 4 +; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v16 +; LMULMAX1-RV32-NEXT: vsll.vx v12, v12, a2 +; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v15 +; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v14 +; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13 +; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 4 ; LMULMAX1-RV32-NEXT: lui a5, 61681 ; LMULMAX1-RV32-NEXT: addi a5, a5, -241 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v31, a5 +; LMULMAX1-RV32-NEXT: vmv.v.x v14, a5 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vand.vv v30, v30, v31 -; LMULMAX1-RV32-NEXT: vand.vv v29, v29, v31 -; LMULMAX1-RV32-NEXT: vsll.vi v29, v29, 4 -; LMULMAX1-RV32-NEXT: vor.vv v29, v30, v29 -; LMULMAX1-RV32-NEXT: vsrl.vi v30, v29, 2 +; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v14 +; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v14 +; LMULMAX1-RV32-NEXT: vsll.vi v12, v12, 4 +; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12 +; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 2 ; LMULMAX1-RV32-NEXT: lui a5, 209715 ; LMULMAX1-RV32-NEXT: addi a5, a5, 819 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v8, a5 +; LMULMAX1-RV32-NEXT: vmv.v.x v15, a5 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vand.vv v30, v30, v8 -; LMULMAX1-RV32-NEXT: vand.vv v29, v29, v8 -; LMULMAX1-RV32-NEXT: vsll.vi v29, v29, 2 -; LMULMAX1-RV32-NEXT: vor.vv v29, v30, v29 -; LMULMAX1-RV32-NEXT: vsrl.vi v30, v29, 1 +; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v15 +; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v15 +; LMULMAX1-RV32-NEXT: vsll.vi v12, v12, 2 +; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12 +; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 1 ; LMULMAX1-RV32-NEXT: lui a5, 349525 ; LMULMAX1-RV32-NEXT: addi a5, a5, 1365 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v10, a5 +; LMULMAX1-RV32-NEXT: vmv.v.x v17, a5 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vand.vv v30, v30, v10 -; LMULMAX1-RV32-NEXT: vand.vv v29, v29, v10 -; LMULMAX1-RV32-NEXT: vadd.vv v29, v29, v29 -; LMULMAX1-RV32-NEXT: vor.vv v29, v30, v29 -; LMULMAX1-RV32-NEXT: vsrl.vx v30, v25, a2 -; LMULMAX1-RV32-NEXT: vsrl.vx v11, v25, a3 -; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a4 -; LMULMAX1-RV32-NEXT: vor.vv v30, v11, v30 -; LMULMAX1-RV32-NEXT: vsrl.vi v11, v25, 24 -; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a6 -; LMULMAX1-RV32-NEXT: vsrl.vi v12, v25, 8 -; LMULMAX1-RV32-NEXT: vand.vv v26, v12, v26 -; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v11 -; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v30 -; LMULMAX1-RV32-NEXT: vsll.vi v30, v25, 8 -; LMULMAX1-RV32-NEXT: vand.vv v27, v30, v27 -; LMULMAX1-RV32-NEXT: vsll.vi v30, v25, 24 -; LMULMAX1-RV32-NEXT: vand.vv v28, v30, v28 -; LMULMAX1-RV32-NEXT: vor.vv v27, v28, v27 -; LMULMAX1-RV32-NEXT: vsll.vx v28, v25, a3 -; LMULMAX1-RV32-NEXT: vand.vv v28, v28, v9 -; LMULMAX1-RV32-NEXT: vsll.vx v25, v25, a2 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v26 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 4 -; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v31 -; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v31 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 4 -; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v8 -; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v8 -; LMULMAX1-RV32-NEXT: vsll.vi v25, v25, 2 -; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 1 -; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v10 -; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v10 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v25 -; LMULMAX1-RV32-NEXT: vor.vv v25, v26, v25 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v29, (a1) +; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v17 +; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v17 +; LMULMAX1-RV32-NEXT: vadd.vv v12, v12, v12 +; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12 +; LMULMAX1-RV32-NEXT: vsrl.vx v13, v8, a2 +; LMULMAX1-RV32-NEXT: vsrl.vx v18, v8, a3 +; LMULMAX1-RV32-NEXT: vand.vx v18, v18, a4 +; LMULMAX1-RV32-NEXT: vor.vv v13, v18, v13 +; LMULMAX1-RV32-NEXT: vsrl.vi v18, v8, 24 +; LMULMAX1-RV32-NEXT: vand.vx v18, v18, a6 +; LMULMAX1-RV32-NEXT: vsrl.vi v19, v8, 8 +; LMULMAX1-RV32-NEXT: vand.vv v9, v19, v9 +; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v18 +; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v13 +; LMULMAX1-RV32-NEXT: vsll.vi v13, v8, 8 +; LMULMAX1-RV32-NEXT: vand.vv v10, v13, v10 +; LMULMAX1-RV32-NEXT: vsll.vi v13, v8, 24 +; LMULMAX1-RV32-NEXT: vand.vv v11, v13, v11 +; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10 +; LMULMAX1-RV32-NEXT: vsll.vx v11, v8, a3 +; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v16 +; LMULMAX1-RV32-NEXT: vsll.vx v8, v8, a2 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v9 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4 +; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v14 +; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v14 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4 +; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v15 +; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v15 +; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2 +; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1 +; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v17 +; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v17 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8 +; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v12, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bitreverse_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a7, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a7) -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a7) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi t0, zero, 56 -; LMULMAX1-RV64-NEXT: vsrl.vx v27, v26, t0 +; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, t0 ; LMULMAX1-RV64-NEXT: addi t1, zero, 40 -; LMULMAX1-RV64-NEXT: vsrl.vx v28, v26, t1 +; LMULMAX1-RV64-NEXT: vsrl.vx v11, v9, t1 ; LMULMAX1-RV64-NEXT: lui a1, 16 ; LMULMAX1-RV64-NEXT: addiw t2, a1, -256 -; LMULMAX1-RV64-NEXT: vand.vx v28, v28, t2 -; LMULMAX1-RV64-NEXT: vor.vv v27, v28, v27 -; LMULMAX1-RV64-NEXT: vsrl.vi v28, v26, 24 +; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t2 +; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 +; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV64-NEXT: lui a6, 4080 -; LMULMAX1-RV64-NEXT: vand.vx v28, v28, a6 -; LMULMAX1-RV64-NEXT: vsrl.vi v29, v26, 8 +; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6 +; LMULMAX1-RV64-NEXT: vsrl.vi v12, v9, 8 ; LMULMAX1-RV64-NEXT: addi a3, zero, 255 ; LMULMAX1-RV64-NEXT: slli t3, a3, 24 -; LMULMAX1-RV64-NEXT: vand.vx v29, v29, t3 -; LMULMAX1-RV64-NEXT: vor.vv v28, v29, v28 -; LMULMAX1-RV64-NEXT: vor.vv v27, v28, v27 -; LMULMAX1-RV64-NEXT: vsll.vi v28, v26, 8 +; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t3 +; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 +; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 +; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8 ; LMULMAX1-RV64-NEXT: slli t4, a3, 32 -; LMULMAX1-RV64-NEXT: vand.vx v28, v28, t4 -; LMULMAX1-RV64-NEXT: vsll.vi v29, v26, 24 +; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t4 +; LMULMAX1-RV64-NEXT: vsll.vi v12, v9, 24 ; LMULMAX1-RV64-NEXT: slli a2, a3, 40 -; LMULMAX1-RV64-NEXT: vand.vx v29, v29, a2 -; LMULMAX1-RV64-NEXT: vor.vv v28, v29, v28 -; LMULMAX1-RV64-NEXT: vsll.vx v29, v26, t0 -; LMULMAX1-RV64-NEXT: vsll.vx v26, v26, t1 +; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a2 +; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 +; LMULMAX1-RV64-NEXT: vsll.vx v12, v9, t0 +; LMULMAX1-RV64-NEXT: vsll.vx v9, v9, t1 ; LMULMAX1-RV64-NEXT: slli a3, a3, 48 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a3 -; LMULMAX1-RV64-NEXT: vor.vv v26, v29, v26 -; LMULMAX1-RV64-NEXT: vor.vv v26, v26, v28 -; LMULMAX1-RV64-NEXT: vor.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 4 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3 +; LMULMAX1-RV64-NEXT: vor.vv v9, v12, v9 +; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11 +; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV64-NEXT: lui a4, 3855 ; LMULMAX1-RV64-NEXT: addiw a4, a4, 241 ; LMULMAX1-RV64-NEXT: slli a4, a4, 12 @@ -1361,11 +1361,11 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: addi a4, a4, 241 ; LMULMAX1-RV64-NEXT: slli a4, a4, 12 ; LMULMAX1-RV64-NEXT: addi a4, a4, -241 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a4 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a4 -; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 4 -; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 2 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4 +; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4 +; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2 ; LMULMAX1-RV64-NEXT: lui a5, 13107 ; LMULMAX1-RV64-NEXT: addiw a5, a5, 819 ; LMULMAX1-RV64-NEXT: slli a5, a5, 12 @@ -1374,11 +1374,11 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: addi a5, a5, 819 ; LMULMAX1-RV64-NEXT: slli a5, a5, 12 ; LMULMAX1-RV64-NEXT: addi a5, a5, 819 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a5 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a5 -; LMULMAX1-RV64-NEXT: vsll.vi v26, v26, 2 -; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 1 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5 +; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2 +; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1 ; LMULMAX1-RV64-NEXT: lui a1, 21845 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 1365 ; LMULMAX1-RV64-NEXT: slli a1, a1, 12 @@ -1387,48 +1387,48 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: addi a1, a1, 1365 ; LMULMAX1-RV64-NEXT: slli a1, a1, 12 ; LMULMAX1-RV64-NEXT: addi a1, a1, 1365 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a1 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v26 -; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsrl.vx v27, v25, t0 -; LMULMAX1-RV64-NEXT: vsrl.vx v28, v25, t1 -; LMULMAX1-RV64-NEXT: vand.vx v28, v28, t2 -; LMULMAX1-RV64-NEXT: vor.vv v27, v28, v27 -; LMULMAX1-RV64-NEXT: vsrl.vi v28, v25, 24 -; LMULMAX1-RV64-NEXT: vand.vx v28, v28, a6 -; LMULMAX1-RV64-NEXT: vsrl.vi v29, v25, 8 -; LMULMAX1-RV64-NEXT: vand.vx v29, v29, t3 -; LMULMAX1-RV64-NEXT: vor.vv v28, v29, v28 -; LMULMAX1-RV64-NEXT: vor.vv v27, v28, v27 -; LMULMAX1-RV64-NEXT: vsll.vi v28, v25, 8 -; LMULMAX1-RV64-NEXT: vand.vx v28, v28, t4 -; LMULMAX1-RV64-NEXT: vsll.vi v29, v25, 24 -; LMULMAX1-RV64-NEXT: vand.vx v29, v29, a2 -; LMULMAX1-RV64-NEXT: vor.vv v28, v29, v28 -; LMULMAX1-RV64-NEXT: vsll.vx v29, v25, t0 -; LMULMAX1-RV64-NEXT: vsll.vx v25, v25, t1 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a3 -; LMULMAX1-RV64-NEXT: vor.vv v25, v29, v25 -; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v27 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 4 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a4 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a4 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 4 -; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 2 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a5 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a5 -; LMULMAX1-RV64-NEXT: vsll.vi v25, v25, 2 -; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 1 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a1 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v25 -; LMULMAX1-RV64-NEXT: vor.vv v25, v27, v25 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a7) +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9 +; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, t0 +; LMULMAX1-RV64-NEXT: vsrl.vx v11, v8, t1 +; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t2 +; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 +; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24 +; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6 +; LMULMAX1-RV64-NEXT: vsrl.vi v12, v8, 8 +; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t3 +; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 +; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 +; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8 +; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t4 +; LMULMAX1-RV64-NEXT: vsll.vi v12, v8, 24 +; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a2 +; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 +; LMULMAX1-RV64-NEXT: vsll.vx v12, v8, t0 +; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, t1 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3 +; LMULMAX1-RV64-NEXT: vor.vv v8, v12, v8 +; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4 +; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5 +; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2 +; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8 +; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a7) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll index ee19ee350fc788af334fd85204073c2f9bab362c..be43f3f78c3546ffc88867a8535faf043070f27c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll @@ -10,58 +10,58 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: addi sp, sp, -32 ; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle16.v v25, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 16(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 30(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 28(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 26(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 24(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 22(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 20(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 @@ -69,8 +69,8 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: sh a1, 18(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 16 -; LMULMAX2-RV32-NEXT: vle16.v v25, (a1) -; LMULMAX2-RV32-NEXT: vse16.v v25, (a0) +; LMULMAX2-RV32-NEXT: vle16.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 ; LMULMAX2-RV32-NEXT: ret ; @@ -79,58 +79,58 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -32 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle16.v v25, (a0) -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV64-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 30(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 26(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 22(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 20(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 @@ -138,8 +138,8 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: sh a1, 18(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle16.v v25, (a1) -; LMULMAX2-RV64-NEXT: vse16.v v25, (a0) +; LMULMAX2-RV64-NEXT: vle16.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 ; LMULMAX2-RV64-NEXT: ret ; @@ -148,58 +148,58 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: addi sp, sp, -32 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: slli a2, a1, 8 ; LMULMAX1-RV32-NEXT: slli a1, a1, 16 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: or a1, a2, a1 ; LMULMAX1-RV32-NEXT: sh a1, 16(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: slli a2, a1, 8 ; LMULMAX1-RV32-NEXT: slli a1, a1, 16 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: or a1, a2, a1 ; LMULMAX1-RV32-NEXT: sh a1, 30(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: slli a2, a1, 8 ; LMULMAX1-RV32-NEXT: slli a1, a1, 16 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: or a1, a2, a1 ; LMULMAX1-RV32-NEXT: sh a1, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: slli a2, a1, 8 ; LMULMAX1-RV32-NEXT: slli a1, a1, 16 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: or a1, a2, a1 ; LMULMAX1-RV32-NEXT: sh a1, 26(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: slli a2, a1, 8 ; LMULMAX1-RV32-NEXT: slli a1, a1, 16 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: or a1, a2, a1 ; LMULMAX1-RV32-NEXT: sh a1, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: slli a2, a1, 8 ; LMULMAX1-RV32-NEXT: slli a1, a1, 16 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: or a1, a2, a1 ; LMULMAX1-RV32-NEXT: sh a1, 22(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: slli a2, a1, 8 ; LMULMAX1-RV32-NEXT: slli a1, a1, 16 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: or a1, a2, a1 ; LMULMAX1-RV32-NEXT: sh a1, 20(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: slli a2, a1, 8 ; LMULMAX1-RV32-NEXT: slli a1, a1, 16 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 @@ -207,8 +207,8 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: sh a1, 18(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle16.v v25, (a1) -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a1) +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 ; LMULMAX1-RV32-NEXT: ret ; @@ -217,58 +217,58 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: addi sp, sp, -32 ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: slli a2, a1, 8 ; LMULMAX1-RV64-NEXT: slli a1, a1, 48 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: or a1, a2, a1 ; LMULMAX1-RV64-NEXT: sh a1, 16(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: slli a2, a1, 8 ; LMULMAX1-RV64-NEXT: slli a1, a1, 48 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: or a1, a2, a1 ; LMULMAX1-RV64-NEXT: sh a1, 30(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: slli a2, a1, 8 ; LMULMAX1-RV64-NEXT: slli a1, a1, 48 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: or a1, a2, a1 ; LMULMAX1-RV64-NEXT: sh a1, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: slli a2, a1, 8 ; LMULMAX1-RV64-NEXT: slli a1, a1, 48 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: or a1, a2, a1 ; LMULMAX1-RV64-NEXT: sh a1, 26(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: slli a2, a1, 8 ; LMULMAX1-RV64-NEXT: slli a1, a1, 48 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: or a1, a2, a1 ; LMULMAX1-RV64-NEXT: sh a1, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: slli a2, a1, 8 ; LMULMAX1-RV64-NEXT: slli a1, a1, 48 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: or a1, a2, a1 ; LMULMAX1-RV64-NEXT: sh a1, 22(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: slli a2, a1, 8 ; LMULMAX1-RV64-NEXT: slli a1, a1, 48 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: or a1, a2, a1 ; LMULMAX1-RV64-NEXT: sh a1, 20(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: slli a2, a1, 8 ; LMULMAX1-RV64-NEXT: slli a1, a1, 48 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 @@ -276,8 +276,8 @@ define void @bswap_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: sh a1, 18(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, sp, 16 -; LMULMAX1-RV64-NEXT: vle16.v v25, (a1) -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a1) +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x @@ -294,8 +294,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-NEXT: addi sp, sp, -32 ; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle32.v v25, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: srli a2, a1, 8 ; LMULMAX2-RV32-NEXT: lui a3, 16 ; LMULMAX2-RV32-NEXT: addi a3, a3, -256 @@ -310,8 +310,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-NEXT: or a1, a1, a2 ; LMULMAX2-RV32-NEXT: sw a1, 16(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: srli a2, a1, 8 ; LMULMAX2-RV32-NEXT: and a2, a2, a3 ; LMULMAX2-RV32-NEXT: srli a4, a1, 24 @@ -322,8 +322,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-NEXT: or a1, a1, a4 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 ; LMULMAX2-RV32-NEXT: sw a1, 28(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: srli a2, a1, 8 ; LMULMAX2-RV32-NEXT: and a2, a2, a3 ; LMULMAX2-RV32-NEXT: srli a4, a1, 24 @@ -334,8 +334,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-NEXT: or a1, a1, a4 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 ; LMULMAX2-RV32-NEXT: sw a1, 24(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: srli a2, a1, 8 ; LMULMAX2-RV32-NEXT: and a2, a2, a3 ; LMULMAX2-RV32-NEXT: srli a3, a1, 24 @@ -348,8 +348,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-NEXT: sw a1, 20(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 16 -; LMULMAX2-RV32-NEXT: vle32.v v25, (a1) -; LMULMAX2-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX2-RV32-NEXT: vle32.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 ; LMULMAX2-RV32-NEXT: ret ; @@ -358,8 +358,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -32 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle32.v v25, (a0) -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV64-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: srliw a2, a1, 8 ; LMULMAX2-RV64-NEXT: lui a3, 16 ; LMULMAX2-RV64-NEXT: addiw a3, a3, -256 @@ -374,8 +374,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV64-NEXT: or a1, a1, a2 ; LMULMAX2-RV64-NEXT: sw a1, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: srliw a2, a1, 8 ; LMULMAX2-RV64-NEXT: and a2, a2, a3 ; LMULMAX2-RV64-NEXT: srliw a4, a1, 24 @@ -386,8 +386,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV64-NEXT: or a1, a1, a4 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 ; LMULMAX2-RV64-NEXT: sw a1, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: srliw a2, a1, 8 ; LMULMAX2-RV64-NEXT: and a2, a2, a3 ; LMULMAX2-RV64-NEXT: srliw a4, a1, 24 @@ -398,8 +398,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV64-NEXT: or a1, a1, a4 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 ; LMULMAX2-RV64-NEXT: sw a1, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: srliw a2, a1, 8 ; LMULMAX2-RV64-NEXT: and a2, a2, a3 ; LMULMAX2-RV64-NEXT: srliw a3, a1, 24 @@ -412,8 +412,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV64-NEXT: sw a1, 20(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle32.v v25, (a1) -; LMULMAX2-RV64-NEXT: vse32.v v25, (a0) +; LMULMAX2-RV64-NEXT: vle32.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 ; LMULMAX2-RV64-NEXT: ret ; @@ -422,8 +422,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV32-NEXT: addi sp, sp, -32 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a2, a1, 8 ; LMULMAX1-RV32-NEXT: lui a3, 16 ; LMULMAX1-RV32-NEXT: addi a3, a3, -256 @@ -438,8 +438,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: sw a1, 16(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: srli a2, a1, 8 ; LMULMAX1-RV32-NEXT: and a2, a2, a3 ; LMULMAX1-RV32-NEXT: srli a4, a1, 24 @@ -450,8 +450,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a4 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: sw a1, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: srli a2, a1, 8 ; LMULMAX1-RV32-NEXT: and a2, a2, a3 ; LMULMAX1-RV32-NEXT: srli a4, a1, 24 @@ -462,8 +462,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a4 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: sw a1, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a2, a1, 8 ; LMULMAX1-RV32-NEXT: and a2, a2, a3 ; LMULMAX1-RV32-NEXT: srli a3, a1, 24 @@ -476,8 +476,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV32-NEXT: sw a1, 20(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 ; LMULMAX1-RV32-NEXT: ret ; @@ -486,8 +486,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV64-NEXT: addi sp, sp, -32 ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: srliw a2, a1, 8 ; LMULMAX1-RV64-NEXT: lui a3, 16 ; LMULMAX1-RV64-NEXT: addiw a3, a3, -256 @@ -502,8 +502,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: sw a1, 16(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: srliw a2, a1, 8 ; LMULMAX1-RV64-NEXT: and a2, a2, a3 ; LMULMAX1-RV64-NEXT: srliw a4, a1, 24 @@ -514,8 +514,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV64-NEXT: or a1, a1, a4 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: sw a1, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: srliw a2, a1, 8 ; LMULMAX1-RV64-NEXT: and a2, a2, a3 ; LMULMAX1-RV64-NEXT: srliw a4, a1, 24 @@ -526,8 +526,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV64-NEXT: or a1, a1, a4 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: sw a1, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: srliw a2, a1, 8 ; LMULMAX1-RV64-NEXT: and a2, a2, a3 ; LMULMAX1-RV64-NEXT: srliw a3, a1, 24 @@ -540,8 +540,8 @@ define void @bswap_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV64-NEXT: sw a1, 20(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, sp, 16 -; LMULMAX1-RV64-NEXT: vle32.v v25, (a1) -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x @@ -558,8 +558,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV32-NEXT: addi sp, sp, -32 ; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle64.v v25, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: srli a2, a1, 8 ; LMULMAX2-RV32-NEXT: lui a3, 16 ; LMULMAX2-RV32-NEXT: addi a3, a3, -256 @@ -574,8 +574,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV32-NEXT: or a1, a1, a2 ; LMULMAX2-RV32-NEXT: sw a1, 20(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: srli a2, a1, 8 ; LMULMAX2-RV32-NEXT: and a2, a2, a3 ; LMULMAX2-RV32-NEXT: srli a4, a1, 24 @@ -587,8 +587,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV32-NEXT: or a1, a1, a2 ; LMULMAX2-RV32-NEXT: sw a1, 28(sp) ; LMULMAX2-RV32-NEXT: addi a1, zero, 32 -; LMULMAX2-RV32-NEXT: vsrl.vx v25, v25, a1 -; LMULMAX2-RV32-NEXT: vmv.x.s a2, v25 +; LMULMAX2-RV32-NEXT: vsrl.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX2-RV32-NEXT: srli a4, a2, 8 ; LMULMAX2-RV32-NEXT: and a4, a4, a3 ; LMULMAX2-RV32-NEXT: srli a5, a2, 24 @@ -599,8 +599,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV32-NEXT: or a2, a2, a5 ; LMULMAX2-RV32-NEXT: or a2, a2, a4 ; LMULMAX2-RV32-NEXT: sw a2, 16(sp) -; LMULMAX2-RV32-NEXT: vsrl.vx v25, v26, a1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vsrl.vx v8, v9, a1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: srli a2, a1, 8 ; LMULMAX2-RV32-NEXT: and a2, a2, a3 ; LMULMAX2-RV32-NEXT: srli a3, a1, 24 @@ -613,19 +613,19 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV32-NEXT: sw a1, 24(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 16 -; LMULMAX2-RV32-NEXT: vle32.v v25, (a1) +; LMULMAX2-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: bswap_v2i64: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: srli a2, a1, 40 ; LMULMAX2-RV64-NEXT: lui a3, 16 ; LMULMAX2-RV64-NEXT: addiw a7, a3, -256 @@ -655,8 +655,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV64-NEXT: or a1, a1, a2 ; LMULMAX2-RV64-NEXT: or a1, a1, t1 ; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV64-NEXT: vmv.v.x v26, a1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV64-NEXT: vmv.v.x v9, a1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: srli a2, a1, 24 ; LMULMAX2-RV64-NEXT: and a2, a2, a6 ; LMULMAX2-RV64-NEXT: srli a4, a1, 8 @@ -679,8 +679,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV64-NEXT: or a1, a1, a3 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 ; LMULMAX2-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1 -; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vmv.s.x v9, a1 +; LMULMAX2-RV64-NEXT: vse64.v v9, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: bswap_v2i64: @@ -688,8 +688,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV32-NEXT: addi sp, sp, -32 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a2, a1, 8 ; LMULMAX1-RV32-NEXT: lui a3, 16 ; LMULMAX1-RV32-NEXT: addi a3, a3, -256 @@ -704,8 +704,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: sw a1, 20(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: srli a2, a1, 8 ; LMULMAX1-RV32-NEXT: and a2, a2, a3 ; LMULMAX1-RV32-NEXT: srli a4, a1, 24 @@ -717,8 +717,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: sw a1, 28(sp) ; LMULMAX1-RV32-NEXT: addi a1, zero, 32 -; LMULMAX1-RV32-NEXT: vsrl.vx v25, v25, a1 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV32-NEXT: vsrl.vx v8, v8, a1 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV32-NEXT: srli a4, a2, 8 ; LMULMAX1-RV32-NEXT: and a4, a4, a3 ; LMULMAX1-RV32-NEXT: srli a5, a2, 24 @@ -729,8 +729,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV32-NEXT: or a2, a2, a5 ; LMULMAX1-RV32-NEXT: or a2, a2, a4 ; LMULMAX1-RV32-NEXT: sw a2, 16(sp) -; LMULMAX1-RV32-NEXT: vsrl.vx v25, v26, a1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vsrl.vx v8, v9, a1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a2, a1, 8 ; LMULMAX1-RV32-NEXT: and a2, a2, a3 ; LMULMAX1-RV32-NEXT: srli a3, a1, 24 @@ -743,19 +743,19 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV32-NEXT: sw a1, 24(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: bswap_v2i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: srli a2, a1, 40 ; LMULMAX1-RV64-NEXT: lui a3, 16 ; LMULMAX1-RV64-NEXT: addiw a7, a3, -256 @@ -785,8 +785,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: or a1, a1, t1 ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.x v26, a1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vmv.v.x v9, a1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: srli a2, a1, 24 ; LMULMAX1-RV64-NEXT: and a2, a2, a6 ; LMULMAX1-RV64-NEXT: srli a4, a1, 8 @@ -809,8 +809,8 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV64-NEXT: or a1, a1, a3 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 -; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX1-RV64-NEXT: vmv.s.x v9, a1 +; LMULMAX1-RV64-NEXT: vse64.v v9, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -833,114 +833,114 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX2-RV32-NEXT: andi sp, sp, -32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle16.v v26, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 32(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 15 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 15 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 62(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 14 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 14 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 60(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 13 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 13 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 58(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 12 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 12 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 56(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 11 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 11 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 54(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 10 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 10 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 52(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 9 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 9 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 50(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 8 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 8 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 48(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 46(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 44(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 42(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 40(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 38(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: or a1, a2, a1 ; LMULMAX2-RV32-NEXT: sh a1, 36(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: slli a2, a1, 8 ; LMULMAX2-RV32-NEXT: slli a1, a1, 16 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 @@ -948,8 +948,8 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: sh a1, 34(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 32 -; LMULMAX2-RV32-NEXT: vle16.v v26, (a1) -; LMULMAX2-RV32-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle16.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload @@ -961,114 +961,114 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -48 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle16.v v26, (a0) -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 15 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 15 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 46(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 14 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 14 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 44(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 13 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 13 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 42(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 12 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 12 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 40(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 11 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 11 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 38(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 10 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 10 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 36(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 9 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 9 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 34(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 8 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 8 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 32(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 30(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 26(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 22(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: sh a1, 20(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: slli a2, a1, 8 ; LMULMAX2-RV64-NEXT: slli a1, a1, 48 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 @@ -1076,8 +1076,8 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: sh a1, 18(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle16.v v26, (a1) -; LMULMAX2-RV64-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle16.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 48 ; LMULMAX2-RV64-NEXT: ret ; @@ -1087,114 +1087,114 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a1) -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vle16.v v9, (a1) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: or a2, a3, a2 ; LMULMAX1-RV32-NEXT: sh a2, 32(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 7 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 7 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: or a2, a3, a2 ; LMULMAX1-RV32-NEXT: sh a2, 46(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 6 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 6 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: or a2, a3, a2 ; LMULMAX1-RV32-NEXT: sh a2, 44(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 5 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 5 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: or a2, a3, a2 ; LMULMAX1-RV32-NEXT: sh a2, 42(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 4 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 4 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: or a2, a3, a2 ; LMULMAX1-RV32-NEXT: sh a2, 40(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: or a2, a3, a2 ; LMULMAX1-RV32-NEXT: sh a2, 38(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: or a2, a3, a2 ; LMULMAX1-RV32-NEXT: sh a2, 36(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: or a2, a3, a2 ; LMULMAX1-RV32-NEXT: sh a2, 34(sp) -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: or a2, a3, a2 ; LMULMAX1-RV32-NEXT: sh a2, 16(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: or a2, a3, a2 ; LMULMAX1-RV32-NEXT: sh a2, 30(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: or a2, a3, a2 ; LMULMAX1-RV32-NEXT: sh a2, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: or a2, a3, a2 ; LMULMAX1-RV32-NEXT: sh a2, 26(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: or a2, a3, a2 ; LMULMAX1-RV32-NEXT: sh a2, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: or a2, a3, a2 ; LMULMAX1-RV32-NEXT: sh a2, 22(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: or a2, a3, a2 ; LMULMAX1-RV32-NEXT: sh a2, 20(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV32-NEXT: slli a3, a2, 8 ; LMULMAX1-RV32-NEXT: slli a2, a2, 16 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 @@ -1202,11 +1202,11 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: sh a2, 18(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a2, sp, 16 -; LMULMAX1-RV32-NEXT: vle16.v v25, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a2) ; LMULMAX1-RV32-NEXT: addi a2, sp, 32 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a1) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a1) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 ; LMULMAX1-RV32-NEXT: ret ; @@ -1216,114 +1216,114 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a1) -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vle16.v v9, (a1) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: sh a2, 32(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 7 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 7 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: sh a2, 46(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 6 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 6 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: sh a2, 44(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 5 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 5 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: sh a2, 42(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 4 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 4 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: sh a2, 40(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: sh a2, 38(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: sh a2, 36(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: sh a2, 34(sp) -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: sh a2, 16(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: sh a2, 30(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: sh a2, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: sh a2, 26(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: sh a2, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: sh a2, 22(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: sh a2, 20(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV64-NEXT: slli a3, a2, 8 ; LMULMAX1-RV64-NEXT: slli a2, a2, 48 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 @@ -1331,11 +1331,11 @@ define void @bswap_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: sh a2, 18(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a2, sp, 16 -; LMULMAX1-RV64-NEXT: vle16.v v25, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a2) ; LMULMAX1-RV64-NEXT: addi a2, sp, 32 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a1) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a1) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x @@ -1359,8 +1359,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX2-RV32-NEXT: andi sp, sp, -32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle32.v v26, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a3, v26 +; LMULMAX2-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a3, v8 ; LMULMAX2-RV32-NEXT: srli a2, a3, 8 ; LMULMAX2-RV32-NEXT: lui a1, 16 ; LMULMAX2-RV32-NEXT: addi a1, a1, -256 @@ -1375,8 +1375,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: or a3, a3, a4 ; LMULMAX2-RV32-NEXT: sw a3, 32(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV32-NEXT: vmv.x.s a3, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV32-NEXT: vmv.x.s a3, v10 ; LMULMAX2-RV32-NEXT: srli a4, a3, 8 ; LMULMAX2-RV32-NEXT: and a4, a4, a1 ; LMULMAX2-RV32-NEXT: srli a5, a3, 24 @@ -1387,8 +1387,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: or a3, a3, a5 ; LMULMAX2-RV32-NEXT: or a3, a3, a4 ; LMULMAX2-RV32-NEXT: sw a3, 60(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV32-NEXT: vmv.x.s a3, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV32-NEXT: vmv.x.s a3, v10 ; LMULMAX2-RV32-NEXT: srli a4, a3, 8 ; LMULMAX2-RV32-NEXT: and a4, a4, a1 ; LMULMAX2-RV32-NEXT: srli a5, a3, 24 @@ -1399,8 +1399,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: or a3, a3, a5 ; LMULMAX2-RV32-NEXT: or a3, a3, a4 ; LMULMAX2-RV32-NEXT: sw a3, 56(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV32-NEXT: vmv.x.s a3, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV32-NEXT: vmv.x.s a3, v10 ; LMULMAX2-RV32-NEXT: srli a4, a3, 8 ; LMULMAX2-RV32-NEXT: and a4, a4, a1 ; LMULMAX2-RV32-NEXT: srli a5, a3, 24 @@ -1411,8 +1411,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: or a3, a3, a5 ; LMULMAX2-RV32-NEXT: or a3, a3, a4 ; LMULMAX2-RV32-NEXT: sw a3, 52(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV32-NEXT: vmv.x.s a3, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV32-NEXT: vmv.x.s a3, v10 ; LMULMAX2-RV32-NEXT: srli a4, a3, 8 ; LMULMAX2-RV32-NEXT: and a4, a4, a1 ; LMULMAX2-RV32-NEXT: srli a5, a3, 24 @@ -1423,8 +1423,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: or a3, a3, a5 ; LMULMAX2-RV32-NEXT: or a3, a3, a4 ; LMULMAX2-RV32-NEXT: sw a3, 48(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a3, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a3, v10 ; LMULMAX2-RV32-NEXT: srli a4, a3, 8 ; LMULMAX2-RV32-NEXT: and a4, a4, a1 ; LMULMAX2-RV32-NEXT: srli a5, a3, 24 @@ -1435,8 +1435,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: or a3, a3, a5 ; LMULMAX2-RV32-NEXT: or a3, a3, a4 ; LMULMAX2-RV32-NEXT: sw a3, 44(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a3, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a3, v10 ; LMULMAX2-RV32-NEXT: srli a4, a3, 8 ; LMULMAX2-RV32-NEXT: and a4, a4, a1 ; LMULMAX2-RV32-NEXT: srli a5, a3, 24 @@ -1447,8 +1447,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: or a3, a3, a5 ; LMULMAX2-RV32-NEXT: or a3, a3, a4 ; LMULMAX2-RV32-NEXT: sw a3, 40(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a3, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a3, v8 ; LMULMAX2-RV32-NEXT: srli a4, a3, 8 ; LMULMAX2-RV32-NEXT: and a1, a4, a1 ; LMULMAX2-RV32-NEXT: srli a4, a3, 24 @@ -1461,8 +1461,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: sw a1, 36(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 32 -; LMULMAX2-RV32-NEXT: vle32.v v26, (a1) -; LMULMAX2-RV32-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle32.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload @@ -1474,8 +1474,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -48 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle32.v v26, (a0) -; LMULMAX2-RV64-NEXT: vmv.x.s a3, v26 +; LMULMAX2-RV64-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV64-NEXT: vmv.x.s a3, v8 ; LMULMAX2-RV64-NEXT: srliw a2, a3, 8 ; LMULMAX2-RV64-NEXT: lui a1, 16 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -256 @@ -1490,8 +1490,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: or a3, a3, a4 ; LMULMAX2-RV64-NEXT: sw a3, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV64-NEXT: vmv.x.s a3, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV64-NEXT: vmv.x.s a3, v10 ; LMULMAX2-RV64-NEXT: srliw a4, a3, 8 ; LMULMAX2-RV64-NEXT: and a4, a4, a1 ; LMULMAX2-RV64-NEXT: srliw a5, a3, 24 @@ -1502,8 +1502,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: or a3, a3, a5 ; LMULMAX2-RV64-NEXT: or a3, a3, a4 ; LMULMAX2-RV64-NEXT: sw a3, 44(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV64-NEXT: vmv.x.s a3, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV64-NEXT: vmv.x.s a3, v10 ; LMULMAX2-RV64-NEXT: srliw a4, a3, 8 ; LMULMAX2-RV64-NEXT: and a4, a4, a1 ; LMULMAX2-RV64-NEXT: srliw a5, a3, 24 @@ -1514,8 +1514,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: or a3, a3, a5 ; LMULMAX2-RV64-NEXT: or a3, a3, a4 ; LMULMAX2-RV64-NEXT: sw a3, 40(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV64-NEXT: vmv.x.s a3, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV64-NEXT: vmv.x.s a3, v10 ; LMULMAX2-RV64-NEXT: srliw a4, a3, 8 ; LMULMAX2-RV64-NEXT: and a4, a4, a1 ; LMULMAX2-RV64-NEXT: srliw a5, a3, 24 @@ -1526,8 +1526,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: or a3, a3, a5 ; LMULMAX2-RV64-NEXT: or a3, a3, a4 ; LMULMAX2-RV64-NEXT: sw a3, 36(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV64-NEXT: vmv.x.s a3, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV64-NEXT: vmv.x.s a3, v10 ; LMULMAX2-RV64-NEXT: srliw a4, a3, 8 ; LMULMAX2-RV64-NEXT: and a4, a4, a1 ; LMULMAX2-RV64-NEXT: srliw a5, a3, 24 @@ -1538,8 +1538,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: or a3, a3, a5 ; LMULMAX2-RV64-NEXT: or a3, a3, a4 ; LMULMAX2-RV64-NEXT: sw a3, 32(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a3, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a3, v10 ; LMULMAX2-RV64-NEXT: srliw a4, a3, 8 ; LMULMAX2-RV64-NEXT: and a4, a4, a1 ; LMULMAX2-RV64-NEXT: srliw a5, a3, 24 @@ -1550,8 +1550,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: or a3, a3, a5 ; LMULMAX2-RV64-NEXT: or a3, a3, a4 ; LMULMAX2-RV64-NEXT: sw a3, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a3, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a3, v10 ; LMULMAX2-RV64-NEXT: srliw a4, a3, 8 ; LMULMAX2-RV64-NEXT: and a4, a4, a1 ; LMULMAX2-RV64-NEXT: srliw a5, a3, 24 @@ -1562,8 +1562,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: or a3, a3, a5 ; LMULMAX2-RV64-NEXT: or a3, a3, a4 ; LMULMAX2-RV64-NEXT: sw a3, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a3, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a3, v8 ; LMULMAX2-RV64-NEXT: srliw a4, a3, 8 ; LMULMAX2-RV64-NEXT: and a1, a4, a1 ; LMULMAX2-RV64-NEXT: srliw a4, a3, 24 @@ -1576,8 +1576,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: sw a1, 20(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle32.v v26, (a1) -; LMULMAX2-RV64-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle32.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 48 ; LMULMAX2-RV64-NEXT: ret ; @@ -1587,9 +1587,9 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a6, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a6) -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a4, v26 +; LMULMAX1-RV32-NEXT: vle32.v v9, (a6) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a4, v9 ; LMULMAX1-RV32-NEXT: srli a3, a4, 8 ; LMULMAX1-RV32-NEXT: lui a2, 16 ; LMULMAX1-RV32-NEXT: addi a2, a2, -256 @@ -1604,8 +1604,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: sw a1, 32(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: srli a4, a1, 8 ; LMULMAX1-RV32-NEXT: and a4, a4, a2 ; LMULMAX1-RV32-NEXT: srli a5, a1, 24 @@ -1616,8 +1616,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: or a1, a1, a4 ; LMULMAX1-RV32-NEXT: sw a1, 44(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: srli a4, a1, 8 ; LMULMAX1-RV32-NEXT: and a4, a4, a2 ; LMULMAX1-RV32-NEXT: srli a5, a1, 24 @@ -1628,8 +1628,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: or a1, a1, a4 ; LMULMAX1-RV32-NEXT: sw a1, 40(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: srli a4, a1, 8 ; LMULMAX1-RV32-NEXT: and a4, a4, a2 ; LMULMAX1-RV32-NEXT: srli a5, a1, 24 @@ -1640,7 +1640,7 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: or a1, a1, a4 ; LMULMAX1-RV32-NEXT: sw a1, 36(sp) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a4, a1, 8 ; LMULMAX1-RV32-NEXT: and a4, a4, a2 ; LMULMAX1-RV32-NEXT: srli a5, a1, 24 @@ -1651,8 +1651,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: or a1, a1, a4 ; LMULMAX1-RV32-NEXT: sw a1, 16(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: srli a4, a1, 8 ; LMULMAX1-RV32-NEXT: and a4, a4, a2 ; LMULMAX1-RV32-NEXT: srli a5, a1, 24 @@ -1663,8 +1663,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: or a1, a1, a4 ; LMULMAX1-RV32-NEXT: sw a1, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: srli a4, a1, 8 ; LMULMAX1-RV32-NEXT: and a4, a4, a2 ; LMULMAX1-RV32-NEXT: srli a5, a1, 24 @@ -1675,8 +1675,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: or a1, a1, a4 ; LMULMAX1-RV32-NEXT: sw a1, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a4, a1, 8 ; LMULMAX1-RV32-NEXT: and a2, a4, a2 ; LMULMAX1-RV32-NEXT: srli a4, a1, 24 @@ -1689,11 +1689,11 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: sw a1, 20(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a1, sp, 32 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a1) -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a6) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a1) +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 ; LMULMAX1-RV32-NEXT: ret ; @@ -1703,9 +1703,9 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a6, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a6) -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vmv.x.s a4, v26 +; LMULMAX1-RV64-NEXT: vle32.v v9, (a6) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vmv.x.s a4, v9 ; LMULMAX1-RV64-NEXT: srliw a3, a4, 8 ; LMULMAX1-RV64-NEXT: lui a2, 16 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -256 @@ -1720,8 +1720,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: or a1, a1, a5 ; LMULMAX1-RV64-NEXT: sw a1, 32(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: srliw a4, a1, 8 ; LMULMAX1-RV64-NEXT: and a4, a4, a2 ; LMULMAX1-RV64-NEXT: srliw a5, a1, 24 @@ -1732,8 +1732,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: or a1, a1, a5 ; LMULMAX1-RV64-NEXT: or a1, a1, a4 ; LMULMAX1-RV64-NEXT: sw a1, 44(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: srliw a4, a1, 8 ; LMULMAX1-RV64-NEXT: and a4, a4, a2 ; LMULMAX1-RV64-NEXT: srliw a5, a1, 24 @@ -1744,8 +1744,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: or a1, a1, a5 ; LMULMAX1-RV64-NEXT: or a1, a1, a4 ; LMULMAX1-RV64-NEXT: sw a1, 40(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: srliw a4, a1, 8 ; LMULMAX1-RV64-NEXT: and a4, a4, a2 ; LMULMAX1-RV64-NEXT: srliw a5, a1, 24 @@ -1756,7 +1756,7 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: or a1, a1, a5 ; LMULMAX1-RV64-NEXT: or a1, a1, a4 ; LMULMAX1-RV64-NEXT: sw a1, 36(sp) -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: srliw a4, a1, 8 ; LMULMAX1-RV64-NEXT: and a4, a4, a2 ; LMULMAX1-RV64-NEXT: srliw a5, a1, 24 @@ -1767,8 +1767,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: or a1, a1, a5 ; LMULMAX1-RV64-NEXT: or a1, a1, a4 ; LMULMAX1-RV64-NEXT: sw a1, 16(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: srliw a4, a1, 8 ; LMULMAX1-RV64-NEXT: and a4, a4, a2 ; LMULMAX1-RV64-NEXT: srliw a5, a1, 24 @@ -1779,8 +1779,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: or a1, a1, a5 ; LMULMAX1-RV64-NEXT: or a1, a1, a4 ; LMULMAX1-RV64-NEXT: sw a1, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: srliw a4, a1, 8 ; LMULMAX1-RV64-NEXT: and a4, a4, a2 ; LMULMAX1-RV64-NEXT: srliw a5, a1, 24 @@ -1791,8 +1791,8 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: or a1, a1, a5 ; LMULMAX1-RV64-NEXT: or a1, a1, a4 ; LMULMAX1-RV64-NEXT: sw a1, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: srliw a4, a1, 8 ; LMULMAX1-RV64-NEXT: and a2, a4, a2 ; LMULMAX1-RV64-NEXT: srliw a4, a1, 24 @@ -1805,11 +1805,11 @@ define void @bswap_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: sw a1, 20(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, sp, 16 -; LMULMAX1-RV64-NEXT: vle32.v v25, (a1) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV64-NEXT: addi a1, sp, 32 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a1) -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a6) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a1) +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a6) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x @@ -1833,8 +1833,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX2-RV32-NEXT: andi sp, sp, -32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle64.v v26, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a3, v26 +; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a3, v8 ; LMULMAX2-RV32-NEXT: srli a2, a3, 8 ; LMULMAX2-RV32-NEXT: lui a1, 16 ; LMULMAX2-RV32-NEXT: addi a1, a1, -256 @@ -1849,8 +1849,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: or a3, a3, a4 ; LMULMAX2-RV32-NEXT: sw a3, 36(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a3, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a3, v10 ; LMULMAX2-RV32-NEXT: srli a4, a3, 8 ; LMULMAX2-RV32-NEXT: and a4, a4, a1 ; LMULMAX2-RV32-NEXT: srli a5, a3, 24 @@ -1861,8 +1861,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: or a3, a3, a5 ; LMULMAX2-RV32-NEXT: or a3, a3, a4 ; LMULMAX2-RV32-NEXT: sw a3, 60(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v30, v26, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a3, v30 +; LMULMAX2-RV32-NEXT: vslidedown.vi v12, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a3, v12 ; LMULMAX2-RV32-NEXT: srli a4, a3, 8 ; LMULMAX2-RV32-NEXT: and a4, a4, a1 ; LMULMAX2-RV32-NEXT: srli a5, a3, 24 @@ -1873,8 +1873,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: or a3, a3, a5 ; LMULMAX2-RV32-NEXT: or a3, a3, a4 ; LMULMAX2-RV32-NEXT: sw a3, 52(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v26, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a3, v8 +; LMULMAX2-RV32-NEXT: vslidedown.vi v14, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a3, v14 ; LMULMAX2-RV32-NEXT: srli a4, a3, 8 ; LMULMAX2-RV32-NEXT: and a4, a4, a1 ; LMULMAX2-RV32-NEXT: srli a5, a3, 24 @@ -1886,8 +1886,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: or a3, a3, a4 ; LMULMAX2-RV32-NEXT: sw a3, 44(sp) ; LMULMAX2-RV32-NEXT: addi a3, zero, 32 -; LMULMAX2-RV32-NEXT: vsrl.vx v26, v26, a3 -; LMULMAX2-RV32-NEXT: vmv.x.s a4, v26 +; LMULMAX2-RV32-NEXT: vsrl.vx v8, v8, a3 +; LMULMAX2-RV32-NEXT: vmv.x.s a4, v8 ; LMULMAX2-RV32-NEXT: srli a5, a4, 8 ; LMULMAX2-RV32-NEXT: and a5, a5, a1 ; LMULMAX2-RV32-NEXT: srli a2, a4, 24 @@ -1898,8 +1898,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: or a4, a4, a5 ; LMULMAX2-RV32-NEXT: or a2, a4, a2 ; LMULMAX2-RV32-NEXT: sw a2, 32(sp) -; LMULMAX2-RV32-NEXT: vsrl.vx v26, v28, a3 -; LMULMAX2-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX2-RV32-NEXT: vsrl.vx v8, v10, a3 +; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX2-RV32-NEXT: srli a4, a2, 8 ; LMULMAX2-RV32-NEXT: and a4, a4, a1 ; LMULMAX2-RV32-NEXT: srli a5, a2, 24 @@ -1910,8 +1910,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: or a2, a2, a5 ; LMULMAX2-RV32-NEXT: or a2, a2, a4 ; LMULMAX2-RV32-NEXT: sw a2, 56(sp) -; LMULMAX2-RV32-NEXT: vsrl.vx v26, v30, a3 -; LMULMAX2-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX2-RV32-NEXT: vsrl.vx v8, v12, a3 +; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX2-RV32-NEXT: srli a4, a2, 8 ; LMULMAX2-RV32-NEXT: and a4, a4, a1 ; LMULMAX2-RV32-NEXT: srli a5, a2, 24 @@ -1922,8 +1922,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: or a2, a2, a5 ; LMULMAX2-RV32-NEXT: or a2, a2, a4 ; LMULMAX2-RV32-NEXT: sw a2, 48(sp) -; LMULMAX2-RV32-NEXT: vsrl.vx v26, v8, a3 -; LMULMAX2-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX2-RV32-NEXT: vsrl.vx v8, v14, a3 +; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX2-RV32-NEXT: srli a3, a2, 8 ; LMULMAX2-RV32-NEXT: and a1, a3, a1 ; LMULMAX2-RV32-NEXT: srli a3, a2, 24 @@ -1936,9 +1936,9 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: sw a1, 40(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 32 -; LMULMAX2-RV32-NEXT: vle32.v v26, (a1) +; LMULMAX2-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload @@ -1950,8 +1950,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -48 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle64.v v26, (a0) -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: srli a2, a1, 24 ; LMULMAX2-RV64-NEXT: lui a6, 4080 ; LMULMAX2-RV64-NEXT: and a3, a2, a6 @@ -1982,8 +1982,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: or a1, a1, a2 ; LMULMAX2-RV64-NEXT: sd a1, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: srli a2, a1, 40 ; LMULMAX2-RV64-NEXT: and a2, a2, a5 ; LMULMAX2-RV64-NEXT: srli a3, a1, 56 @@ -2006,8 +2006,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: or a1, a1, a3 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 ; LMULMAX2-RV64-NEXT: sd a1, 40(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: srli a2, a1, 40 ; LMULMAX2-RV64-NEXT: and a2, a2, a5 ; LMULMAX2-RV64-NEXT: srli a3, a1, 56 @@ -2030,8 +2030,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: or a1, a1, a3 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 ; LMULMAX2-RV64-NEXT: sd a1, 32(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: srli a2, a1, 40 ; LMULMAX2-RV64-NEXT: and a2, a2, a5 ; LMULMAX2-RV64-NEXT: srli a3, a1, 56 @@ -2056,8 +2056,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: sd a1, 24(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle64.v v26, (a1) -; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle64.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 48 ; LMULMAX2-RV64-NEXT: ret ; @@ -2067,9 +2067,9 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a6, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a6) -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a4, v26 +; LMULMAX1-RV32-NEXT: vle64.v v9, (a6) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a4, v9 ; LMULMAX1-RV32-NEXT: srli a3, a4, 8 ; LMULMAX1-RV32-NEXT: lui a2, 16 ; LMULMAX1-RV32-NEXT: addi a2, a2, -256 @@ -2084,8 +2084,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: sw a1, 36(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: srli a4, a1, 8 ; LMULMAX1-RV32-NEXT: and a4, a4, a2 ; LMULMAX1-RV32-NEXT: srli a5, a1, 24 @@ -2097,8 +2097,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a4 ; LMULMAX1-RV32-NEXT: sw a1, 44(sp) ; LMULMAX1-RV32-NEXT: addi a7, zero, 32 -; LMULMAX1-RV32-NEXT: vsrl.vx v26, v26, a7 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vsrl.vx v9, v9, a7 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: srli a5, a1, 8 ; LMULMAX1-RV32-NEXT: and a5, a5, a2 ; LMULMAX1-RV32-NEXT: srli a4, a1, 24 @@ -2109,8 +2109,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: or a1, a1, a4 ; LMULMAX1-RV32-NEXT: sw a1, 32(sp) -; LMULMAX1-RV32-NEXT: vsrl.vx v26, v27, a7 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vsrl.vx v9, v10, a7 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: srli a4, a1, 8 ; LMULMAX1-RV32-NEXT: and a4, a4, a2 ; LMULMAX1-RV32-NEXT: srli a5, a1, 24 @@ -2121,7 +2121,7 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: or a1, a1, a4 ; LMULMAX1-RV32-NEXT: sw a1, 40(sp) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a4, a1, 8 ; LMULMAX1-RV32-NEXT: and a4, a4, a2 ; LMULMAX1-RV32-NEXT: srli a5, a1, 24 @@ -2132,8 +2132,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: or a1, a1, a4 ; LMULMAX1-RV32-NEXT: sw a1, 20(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: srli a4, a1, 8 ; LMULMAX1-RV32-NEXT: and a4, a4, a2 ; LMULMAX1-RV32-NEXT: srli a5, a1, 24 @@ -2144,8 +2144,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: or a1, a1, a4 ; LMULMAX1-RV32-NEXT: sw a1, 28(sp) -; LMULMAX1-RV32-NEXT: vsrl.vx v25, v25, a7 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vsrl.vx v8, v8, a7 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a4, a1, 8 ; LMULMAX1-RV32-NEXT: and a4, a4, a2 ; LMULMAX1-RV32-NEXT: srli a5, a1, 24 @@ -2156,8 +2156,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: or a1, a1, a4 ; LMULMAX1-RV32-NEXT: sw a1, 16(sp) -; LMULMAX1-RV32-NEXT: vsrl.vx v25, v26, a7 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vsrl.vx v8, v9, a7 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a4, a1, 8 ; LMULMAX1-RV32-NEXT: and a2, a4, a2 ; LMULMAX1-RV32-NEXT: srli a4, a1, 24 @@ -2170,12 +2170,12 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: sw a1, 24(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a1, sp, 32 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a1) ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a6) +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 ; LMULMAX1-RV32-NEXT: ret ; @@ -2183,11 +2183,11 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a6, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a6) -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a6) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v27, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a4, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v10, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a4, v9 ; LMULMAX1-RV64-NEXT: srli a1, a4, 40 ; LMULMAX1-RV64-NEXT: lui a2, 16 ; LMULMAX1-RV64-NEXT: addiw t0, a2, -256 @@ -2217,8 +2217,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: or a3, a4, a3 ; LMULMAX1-RV64-NEXT: or a2, a3, a2 ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.x v26, a2 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vmv.v.x v9, a2 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: srli a3, a2, 24 ; LMULMAX1-RV64-NEXT: and a3, a3, a7 ; LMULMAX1-RV64-NEXT: srli a4, a2, 8 @@ -2241,10 +2241,10 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: or a2, a2, a4 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX1-RV64-NEXT: vmv.s.x v26, a2 +; LMULMAX1-RV64-NEXT: vmv.s.x v9, a2 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: srli a3, a2, 40 ; LMULMAX1-RV64-NEXT: and a3, a3, t0 ; LMULMAX1-RV64-NEXT: srli a4, a2, 56 @@ -2267,8 +2267,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: or a2, a2, a4 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.x v27, a2 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV64-NEXT: vmv.v.x v10, a2 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV64-NEXT: srli a3, a2, 24 ; LMULMAX1-RV64-NEXT: and a3, a3, a7 ; LMULMAX1-RV64-NEXT: srli a4, a2, 8 @@ -2291,9 +2291,9 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: or a1, a1, a4 ; LMULMAX1-RV64-NEXT: or a1, a1, a3 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1 -; LMULMAX1-RV64-NEXT: vse64.v v27, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a6) +; LMULMAX1-RV64-NEXT: vmv.s.x v10, a1 +; LMULMAX1-RV64-NEXT: vse64.v v10, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a6) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll index 6c94fd9129f194d7d31e0fea64b44ccbd90440ad..00320dd435b4748ac8e912ed44daa34233c4a037 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll @@ -122,17 +122,17 @@ define fastcc <128 x i32> @ret_split_v128i32(<128 x i32>* %x) { ; LMULMAX4-LABEL: ret_split_v128i32: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; LMULMAX4-NEXT: vle32.v v28, (a1) +; LMULMAX4-NEXT: vle32.v v8, (a1) ; LMULMAX4-NEXT: addi a2, a1, 64 -; LMULMAX4-NEXT: vle32.v v8, (a2) -; LMULMAX4-NEXT: addi a2, a1, 128 ; LMULMAX4-NEXT: vle32.v v12, (a2) -; LMULMAX4-NEXT: addi a2, a1, 192 +; LMULMAX4-NEXT: addi a2, a1, 128 ; LMULMAX4-NEXT: vle32.v v16, (a2) -; LMULMAX4-NEXT: addi a2, a1, 256 +; LMULMAX4-NEXT: addi a2, a1, 192 ; LMULMAX4-NEXT: vle32.v v20, (a2) -; LMULMAX4-NEXT: addi a2, a1, 320 +; LMULMAX4-NEXT: addi a2, a1, 256 ; LMULMAX4-NEXT: vle32.v v24, (a2) +; LMULMAX4-NEXT: addi a2, a1, 320 +; LMULMAX4-NEXT: vle32.v v28, (a2) ; LMULMAX4-NEXT: addi a2, a1, 448 ; LMULMAX4-NEXT: vle32.v v0, (a2) ; LMULMAX4-NEXT: addi a1, a1, 384 @@ -142,16 +142,16 @@ define fastcc <128 x i32> @ret_split_v128i32(<128 x i32>* %x) { ; LMULMAX4-NEXT: addi a1, a0, 384 ; LMULMAX4-NEXT: vse32.v v4, (a1) ; LMULMAX4-NEXT: addi a1, a0, 320 -; LMULMAX4-NEXT: vse32.v v24, (a1) +; LMULMAX4-NEXT: vse32.v v28, (a1) ; LMULMAX4-NEXT: addi a1, a0, 256 -; LMULMAX4-NEXT: vse32.v v20, (a1) +; LMULMAX4-NEXT: vse32.v v24, (a1) ; LMULMAX4-NEXT: addi a1, a0, 192 -; LMULMAX4-NEXT: vse32.v v16, (a1) +; LMULMAX4-NEXT: vse32.v v20, (a1) ; LMULMAX4-NEXT: addi a1, a0, 128 -; LMULMAX4-NEXT: vse32.v v12, (a1) +; LMULMAX4-NEXT: vse32.v v16, (a1) ; LMULMAX4-NEXT: addi a1, a0, 64 -; LMULMAX4-NEXT: vse32.v v8, (a1) -; LMULMAX4-NEXT: vse32.v v28, (a0) +; LMULMAX4-NEXT: vse32.v v12, (a1) +; LMULMAX4-NEXT: vse32.v v8, (a0) ; LMULMAX4-NEXT: ret %v = load <128 x i32>, <128 x i32>* %x ret <128 x i32> %v @@ -223,14 +223,14 @@ define fastcc <32 x i32> @ret_v32i32_param_v32i32_v32i32_v32i32_i32(<32 x i32> % ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; LMULMAX4-NEXT: addi a1, a0, 64 -; LMULMAX4-NEXT: vle32.v v28, (a1) -; LMULMAX4-NEXT: vle32.v v24, (a0) +; LMULMAX4-NEXT: vle32.v v24, (a1) +; LMULMAX4-NEXT: vle32.v v28, (a0) ; LMULMAX4-NEXT: vadd.vv v8, v8, v16 ; LMULMAX4-NEXT: vadd.vv v12, v12, v20 -; LMULMAX4-NEXT: vadd.vv v28, v12, v28 -; LMULMAX4-NEXT: vadd.vv v8, v8, v24 +; LMULMAX4-NEXT: vadd.vv v12, v12, v24 +; LMULMAX4-NEXT: vadd.vv v8, v8, v28 ; LMULMAX4-NEXT: vadd.vx v8, v8, a2 -; LMULMAX4-NEXT: vadd.vx v12, v28, a2 +; LMULMAX4-NEXT: vadd.vx v12, v12, a2 ; LMULMAX4-NEXT: ret %r = add <32 x i32> %x, %y %s = add <32 x i32> %r, %z @@ -265,13 +265,13 @@ define fastcc <32 x i32> @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x ; LMULMAX4-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX4-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: .cfi_offset ra, -8 -; LMULMAX4-NEXT: vmv4r.v v28, v12 -; LMULMAX4-NEXT: vmv4r.v v24, v8 +; LMULMAX4-NEXT: vmv4r.v v24, v12 +; LMULMAX4-NEXT: vmv4r.v v28, v8 ; LMULMAX4-NEXT: addi a1, zero, 2 ; LMULMAX4-NEXT: vmv4r.v v8, v16 ; LMULMAX4-NEXT: vmv4r.v v12, v20 -; LMULMAX4-NEXT: vmv4r.v v16, v24 -; LMULMAX4-NEXT: vmv4r.v v20, v28 +; LMULMAX4-NEXT: vmv4r.v v16, v28 +; LMULMAX4-NEXT: vmv4r.v v20, v24 ; LMULMAX4-NEXT: call ext2@plt ; LMULMAX4-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: addi sp, sp, 16 @@ -307,17 +307,17 @@ define fastcc <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x ; LMULMAX4-NEXT: sd ra, 152(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: .cfi_offset ra, -8 ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; LMULMAX4-NEXT: vle32.v v28, (a0) -; LMULMAX4-NEXT: addi a0, a0, 64 ; LMULMAX4-NEXT: vle32.v v24, (a0) +; LMULMAX4-NEXT: addi a0, a0, 64 +; LMULMAX4-NEXT: vle32.v v28, (a0) ; LMULMAX4-NEXT: addi a0, sp, 80 ; LMULMAX4-NEXT: vse32.v v12, (a0) ; LMULMAX4-NEXT: addi a0, sp, 16 ; LMULMAX4-NEXT: addi a3, zero, 42 ; LMULMAX4-NEXT: addi a1, sp, 16 ; LMULMAX4-NEXT: vse32.v v8, (a1) -; LMULMAX4-NEXT: vmv4r.v v8, v28 -; LMULMAX4-NEXT: vmv4r.v v12, v24 +; LMULMAX4-NEXT: vmv4r.v v8, v24 +; LMULMAX4-NEXT: vmv4r.v v12, v28 ; LMULMAX4-NEXT: call ext3@plt ; LMULMAX4-NEXT: ld ra, 152(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: addi sp, sp, 160 @@ -342,10 +342,10 @@ define fastcc <32 x i32> @vector_arg_indirect_stack(i32 %0, i32 %1, i32 %2, i32 ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: addi a0, t2, 64 ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; LMULMAX4-NEXT: vle32.v v28, (t2) -; LMULMAX4-NEXT: vle32.v v16, (a0) -; LMULMAX4-NEXT: vadd.vv v8, v8, v28 -; LMULMAX4-NEXT: vadd.vv v12, v12, v16 +; LMULMAX4-NEXT: vle32.v v16, (t2) +; LMULMAX4-NEXT: vle32.v v20, (a0) +; LMULMAX4-NEXT: vadd.vv v8, v8, v16 +; LMULMAX4-NEXT: vadd.vv v12, v12, v20 ; LMULMAX4-NEXT: ret %s = add <32 x i32> %x, %z ret <32 x i32> %s @@ -434,13 +434,13 @@ define fastcc <32 x i32> @vector_arg_direct_stack(i32 %0, i32 %1, i32 %2, i32 %3 ; LMULMAX4-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; LMULMAX4-NEXT: addi a0, sp, 24 -; LMULMAX4-NEXT: vle32.v v28, (a0) -; LMULMAX4-NEXT: addi a0, sp, 88 ; LMULMAX4-NEXT: vle32.v v24, (a0) +; LMULMAX4-NEXT: addi a0, sp, 88 +; LMULMAX4-NEXT: vle32.v v28, (a0) ; LMULMAX4-NEXT: vadd.vv v12, v12, v20 ; LMULMAX4-NEXT: vadd.vv v8, v8, v16 -; LMULMAX4-NEXT: vadd.vv v8, v8, v28 -; LMULMAX4-NEXT: vadd.vv v12, v12, v24 +; LMULMAX4-NEXT: vadd.vv v8, v8, v24 +; LMULMAX4-NEXT: vadd.vv v12, v12, v28 ; LMULMAX4-NEXT: addi sp, sp, 16 ; LMULMAX4-NEXT: ret %s = add <32 x i32> %x, %y @@ -533,8 +533,8 @@ define fastcc <4 x i1> @vector_mask_arg_direct_stack(i32 %0, i32 %1, i32 %2, i32 ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: addi a0, sp, 152 -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vmxor.mm v0, v0, v25 +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vmxor.mm v0, v0, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %r = xor <4 x i1> %m1, %m2 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll index 0914ae1af2cda24a09ed90a4250159b88189d85b..018f2edda1f9132e2be2e069ff00b82ec1275563 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll @@ -254,17 +254,17 @@ define <128 x i32> @ret_split_v128i32(<128 x i32>* %x) { ; LMULMAX4-LABEL: ret_split_v128i32: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; LMULMAX4-NEXT: vle32.v v28, (a1) +; LMULMAX4-NEXT: vle32.v v8, (a1) ; LMULMAX4-NEXT: addi a2, a1, 64 -; LMULMAX4-NEXT: vle32.v v8, (a2) -; LMULMAX4-NEXT: addi a2, a1, 128 ; LMULMAX4-NEXT: vle32.v v12, (a2) -; LMULMAX4-NEXT: addi a2, a1, 192 +; LMULMAX4-NEXT: addi a2, a1, 128 ; LMULMAX4-NEXT: vle32.v v16, (a2) -; LMULMAX4-NEXT: addi a2, a1, 256 +; LMULMAX4-NEXT: addi a2, a1, 192 ; LMULMAX4-NEXT: vle32.v v20, (a2) -; LMULMAX4-NEXT: addi a2, a1, 320 +; LMULMAX4-NEXT: addi a2, a1, 256 ; LMULMAX4-NEXT: vle32.v v24, (a2) +; LMULMAX4-NEXT: addi a2, a1, 320 +; LMULMAX4-NEXT: vle32.v v28, (a2) ; LMULMAX4-NEXT: addi a2, a1, 448 ; LMULMAX4-NEXT: vle32.v v0, (a2) ; LMULMAX4-NEXT: addi a1, a1, 384 @@ -274,44 +274,44 @@ define <128 x i32> @ret_split_v128i32(<128 x i32>* %x) { ; LMULMAX4-NEXT: addi a1, a0, 384 ; LMULMAX4-NEXT: vse32.v v4, (a1) ; LMULMAX4-NEXT: addi a1, a0, 320 -; LMULMAX4-NEXT: vse32.v v24, (a1) +; LMULMAX4-NEXT: vse32.v v28, (a1) ; LMULMAX4-NEXT: addi a1, a0, 256 -; LMULMAX4-NEXT: vse32.v v20, (a1) +; LMULMAX4-NEXT: vse32.v v24, (a1) ; LMULMAX4-NEXT: addi a1, a0, 192 -; LMULMAX4-NEXT: vse32.v v16, (a1) +; LMULMAX4-NEXT: vse32.v v20, (a1) ; LMULMAX4-NEXT: addi a1, a0, 128 -; LMULMAX4-NEXT: vse32.v v12, (a1) +; LMULMAX4-NEXT: vse32.v v16, (a1) ; LMULMAX4-NEXT: addi a1, a0, 64 -; LMULMAX4-NEXT: vse32.v v8, (a1) -; LMULMAX4-NEXT: vse32.v v28, (a0) +; LMULMAX4-NEXT: vse32.v v12, (a1) +; LMULMAX4-NEXT: vse32.v v8, (a0) ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: ret_split_v128i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a1) +; LMULMAX2-NEXT: vle32.v v8, (a1) ; LMULMAX2-NEXT: addi a2, a1, 32 -; LMULMAX2-NEXT: vle32.v v28, (a2) +; LMULMAX2-NEXT: vle32.v v10, (a2) ; LMULMAX2-NEXT: addi a2, a1, 64 -; LMULMAX2-NEXT: vle32.v v30, (a2) +; LMULMAX2-NEXT: vle32.v v12, (a2) ; LMULMAX2-NEXT: addi a2, a1, 96 -; LMULMAX2-NEXT: vle32.v v8, (a2) +; LMULMAX2-NEXT: vle32.v v14, (a2) ; LMULMAX2-NEXT: addi a2, a1, 128 -; LMULMAX2-NEXT: vle32.v v10, (a2) +; LMULMAX2-NEXT: vle32.v v16, (a2) ; LMULMAX2-NEXT: addi a2, a1, 160 -; LMULMAX2-NEXT: vle32.v v12, (a2) +; LMULMAX2-NEXT: vle32.v v18, (a2) ; LMULMAX2-NEXT: addi a2, a1, 192 -; LMULMAX2-NEXT: vle32.v v14, (a2) +; LMULMAX2-NEXT: vle32.v v20, (a2) ; LMULMAX2-NEXT: addi a2, a1, 224 -; LMULMAX2-NEXT: vle32.v v16, (a2) +; LMULMAX2-NEXT: vle32.v v22, (a2) ; LMULMAX2-NEXT: addi a2, a1, 256 -; LMULMAX2-NEXT: vle32.v v18, (a2) +; LMULMAX2-NEXT: vle32.v v24, (a2) ; LMULMAX2-NEXT: addi a2, a1, 288 -; LMULMAX2-NEXT: vle32.v v20, (a2) +; LMULMAX2-NEXT: vle32.v v26, (a2) ; LMULMAX2-NEXT: addi a2, a1, 320 -; LMULMAX2-NEXT: vle32.v v22, (a2) +; LMULMAX2-NEXT: vle32.v v28, (a2) ; LMULMAX2-NEXT: addi a2, a1, 352 -; LMULMAX2-NEXT: vle32.v v24, (a2) +; LMULMAX2-NEXT: vle32.v v30, (a2) ; LMULMAX2-NEXT: addi a2, a1, 384 ; LMULMAX2-NEXT: vle32.v v0, (a2) ; LMULMAX2-NEXT: addi a2, a1, 416 @@ -329,80 +329,80 @@ define <128 x i32> @ret_split_v128i32(<128 x i32>* %x) { ; LMULMAX2-NEXT: addi a1, a0, 384 ; LMULMAX2-NEXT: vse32.v v0, (a1) ; LMULMAX2-NEXT: addi a1, a0, 352 -; LMULMAX2-NEXT: vse32.v v24, (a1) +; LMULMAX2-NEXT: vse32.v v30, (a1) ; LMULMAX2-NEXT: addi a1, a0, 320 -; LMULMAX2-NEXT: vse32.v v22, (a1) +; LMULMAX2-NEXT: vse32.v v28, (a1) ; LMULMAX2-NEXT: addi a1, a0, 288 -; LMULMAX2-NEXT: vse32.v v20, (a1) +; LMULMAX2-NEXT: vse32.v v26, (a1) ; LMULMAX2-NEXT: addi a1, a0, 256 -; LMULMAX2-NEXT: vse32.v v18, (a1) +; LMULMAX2-NEXT: vse32.v v24, (a1) ; LMULMAX2-NEXT: addi a1, a0, 224 -; LMULMAX2-NEXT: vse32.v v16, (a1) +; LMULMAX2-NEXT: vse32.v v22, (a1) ; LMULMAX2-NEXT: addi a1, a0, 192 -; LMULMAX2-NEXT: vse32.v v14, (a1) +; LMULMAX2-NEXT: vse32.v v20, (a1) ; LMULMAX2-NEXT: addi a1, a0, 160 -; LMULMAX2-NEXT: vse32.v v12, (a1) +; LMULMAX2-NEXT: vse32.v v18, (a1) ; LMULMAX2-NEXT: addi a1, a0, 128 -; LMULMAX2-NEXT: vse32.v v10, (a1) +; LMULMAX2-NEXT: vse32.v v16, (a1) ; LMULMAX2-NEXT: addi a1, a0, 96 -; LMULMAX2-NEXT: vse32.v v8, (a1) +; LMULMAX2-NEXT: vse32.v v14, (a1) ; LMULMAX2-NEXT: addi a1, a0, 64 -; LMULMAX2-NEXT: vse32.v v30, (a1) +; LMULMAX2-NEXT: vse32.v v12, (a1) ; LMULMAX2-NEXT: addi a1, a0, 32 -; LMULMAX2-NEXT: vse32.v v28, (a1) -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vse32.v v10, (a1) +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: ret_split_v128i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a1) +; LMULMAX1-NEXT: vle32.v v8, (a1) ; LMULMAX1-NEXT: addi a2, a1, 16 -; LMULMAX1-NEXT: vle32.v v26, (a2) +; LMULMAX1-NEXT: vle32.v v9, (a2) ; LMULMAX1-NEXT: addi a2, a1, 32 -; LMULMAX1-NEXT: vle32.v v27, (a2) +; LMULMAX1-NEXT: vle32.v v10, (a2) ; LMULMAX1-NEXT: addi a2, a1, 48 -; LMULMAX1-NEXT: vle32.v v28, (a2) +; LMULMAX1-NEXT: vle32.v v11, (a2) ; LMULMAX1-NEXT: addi a2, a1, 64 -; LMULMAX1-NEXT: vle32.v v29, (a2) +; LMULMAX1-NEXT: vle32.v v12, (a2) ; LMULMAX1-NEXT: addi a2, a1, 80 -; LMULMAX1-NEXT: vle32.v v30, (a2) +; LMULMAX1-NEXT: vle32.v v13, (a2) ; LMULMAX1-NEXT: addi a2, a1, 96 -; LMULMAX1-NEXT: vle32.v v31, (a2) +; LMULMAX1-NEXT: vle32.v v14, (a2) ; LMULMAX1-NEXT: addi a2, a1, 112 -; LMULMAX1-NEXT: vle32.v v8, (a2) +; LMULMAX1-NEXT: vle32.v v15, (a2) ; LMULMAX1-NEXT: addi a2, a1, 128 -; LMULMAX1-NEXT: vle32.v v9, (a2) +; LMULMAX1-NEXT: vle32.v v16, (a2) ; LMULMAX1-NEXT: addi a2, a1, 144 -; LMULMAX1-NEXT: vle32.v v10, (a2) +; LMULMAX1-NEXT: vle32.v v17, (a2) ; LMULMAX1-NEXT: addi a2, a1, 160 -; LMULMAX1-NEXT: vle32.v v11, (a2) +; LMULMAX1-NEXT: vle32.v v18, (a2) ; LMULMAX1-NEXT: addi a2, a1, 176 -; LMULMAX1-NEXT: vle32.v v12, (a2) +; LMULMAX1-NEXT: vle32.v v19, (a2) ; LMULMAX1-NEXT: addi a2, a1, 192 -; LMULMAX1-NEXT: vle32.v v13, (a2) +; LMULMAX1-NEXT: vle32.v v20, (a2) ; LMULMAX1-NEXT: addi a2, a1, 208 -; LMULMAX1-NEXT: vle32.v v14, (a2) +; LMULMAX1-NEXT: vle32.v v21, (a2) ; LMULMAX1-NEXT: addi a2, a1, 224 -; LMULMAX1-NEXT: vle32.v v15, (a2) +; LMULMAX1-NEXT: vle32.v v22, (a2) ; LMULMAX1-NEXT: addi a2, a1, 240 -; LMULMAX1-NEXT: vle32.v v16, (a2) +; LMULMAX1-NEXT: vle32.v v23, (a2) ; LMULMAX1-NEXT: addi a2, a1, 256 -; LMULMAX1-NEXT: vle32.v v17, (a2) +; LMULMAX1-NEXT: vle32.v v24, (a2) ; LMULMAX1-NEXT: addi a2, a1, 272 -; LMULMAX1-NEXT: vle32.v v18, (a2) +; LMULMAX1-NEXT: vle32.v v25, (a2) ; LMULMAX1-NEXT: addi a2, a1, 288 -; LMULMAX1-NEXT: vle32.v v19, (a2) +; LMULMAX1-NEXT: vle32.v v26, (a2) ; LMULMAX1-NEXT: addi a2, a1, 304 -; LMULMAX1-NEXT: vle32.v v20, (a2) +; LMULMAX1-NEXT: vle32.v v27, (a2) ; LMULMAX1-NEXT: addi a2, a1, 320 -; LMULMAX1-NEXT: vle32.v v21, (a2) +; LMULMAX1-NEXT: vle32.v v28, (a2) ; LMULMAX1-NEXT: addi a2, a1, 336 -; LMULMAX1-NEXT: vle32.v v22, (a2) +; LMULMAX1-NEXT: vle32.v v29, (a2) ; LMULMAX1-NEXT: addi a2, a1, 352 -; LMULMAX1-NEXT: vle32.v v23, (a2) +; LMULMAX1-NEXT: vle32.v v30, (a2) ; LMULMAX1-NEXT: addi a2, a1, 368 -; LMULMAX1-NEXT: vle32.v v24, (a2) +; LMULMAX1-NEXT: vle32.v v31, (a2) ; LMULMAX1-NEXT: addi a2, a1, 384 ; LMULMAX1-NEXT: vle32.v v0, (a2) ; LMULMAX1-NEXT: addi a2, a1, 400 @@ -436,52 +436,52 @@ define <128 x i32> @ret_split_v128i32(<128 x i32>* %x) { ; LMULMAX1-NEXT: addi a1, a0, 384 ; LMULMAX1-NEXT: vse32.v v0, (a1) ; LMULMAX1-NEXT: addi a1, a0, 368 -; LMULMAX1-NEXT: vse32.v v24, (a1) +; LMULMAX1-NEXT: vse32.v v31, (a1) ; LMULMAX1-NEXT: addi a1, a0, 352 -; LMULMAX1-NEXT: vse32.v v23, (a1) +; LMULMAX1-NEXT: vse32.v v30, (a1) ; LMULMAX1-NEXT: addi a1, a0, 336 -; LMULMAX1-NEXT: vse32.v v22, (a1) +; LMULMAX1-NEXT: vse32.v v29, (a1) ; LMULMAX1-NEXT: addi a1, a0, 320 -; LMULMAX1-NEXT: vse32.v v21, (a1) +; LMULMAX1-NEXT: vse32.v v28, (a1) ; LMULMAX1-NEXT: addi a1, a0, 304 -; LMULMAX1-NEXT: vse32.v v20, (a1) +; LMULMAX1-NEXT: vse32.v v27, (a1) ; LMULMAX1-NEXT: addi a1, a0, 288 -; LMULMAX1-NEXT: vse32.v v19, (a1) +; LMULMAX1-NEXT: vse32.v v26, (a1) ; LMULMAX1-NEXT: addi a1, a0, 272 -; LMULMAX1-NEXT: vse32.v v18, (a1) +; LMULMAX1-NEXT: vse32.v v25, (a1) ; LMULMAX1-NEXT: addi a1, a0, 256 -; LMULMAX1-NEXT: vse32.v v17, (a1) +; LMULMAX1-NEXT: vse32.v v24, (a1) ; LMULMAX1-NEXT: addi a1, a0, 240 -; LMULMAX1-NEXT: vse32.v v16, (a1) +; LMULMAX1-NEXT: vse32.v v23, (a1) ; LMULMAX1-NEXT: addi a1, a0, 224 -; LMULMAX1-NEXT: vse32.v v15, (a1) +; LMULMAX1-NEXT: vse32.v v22, (a1) ; LMULMAX1-NEXT: addi a1, a0, 208 -; LMULMAX1-NEXT: vse32.v v14, (a1) +; LMULMAX1-NEXT: vse32.v v21, (a1) ; LMULMAX1-NEXT: addi a1, a0, 192 -; LMULMAX1-NEXT: vse32.v v13, (a1) +; LMULMAX1-NEXT: vse32.v v20, (a1) ; LMULMAX1-NEXT: addi a1, a0, 176 -; LMULMAX1-NEXT: vse32.v v12, (a1) +; LMULMAX1-NEXT: vse32.v v19, (a1) ; LMULMAX1-NEXT: addi a1, a0, 160 -; LMULMAX1-NEXT: vse32.v v11, (a1) +; LMULMAX1-NEXT: vse32.v v18, (a1) ; LMULMAX1-NEXT: addi a1, a0, 144 -; LMULMAX1-NEXT: vse32.v v10, (a1) +; LMULMAX1-NEXT: vse32.v v17, (a1) ; LMULMAX1-NEXT: addi a1, a0, 128 -; LMULMAX1-NEXT: vse32.v v9, (a1) +; LMULMAX1-NEXT: vse32.v v16, (a1) ; LMULMAX1-NEXT: addi a1, a0, 112 -; LMULMAX1-NEXT: vse32.v v8, (a1) +; LMULMAX1-NEXT: vse32.v v15, (a1) ; LMULMAX1-NEXT: addi a1, a0, 96 -; LMULMAX1-NEXT: vse32.v v31, (a1) +; LMULMAX1-NEXT: vse32.v v14, (a1) ; LMULMAX1-NEXT: addi a1, a0, 80 -; LMULMAX1-NEXT: vse32.v v30, (a1) +; LMULMAX1-NEXT: vse32.v v13, (a1) ; LMULMAX1-NEXT: addi a1, a0, 64 -; LMULMAX1-NEXT: vse32.v v29, (a1) +; LMULMAX1-NEXT: vse32.v v12, (a1) ; LMULMAX1-NEXT: addi a1, a0, 48 -; LMULMAX1-NEXT: vse32.v v28, (a1) +; LMULMAX1-NEXT: vse32.v v11, (a1) ; LMULMAX1-NEXT: addi a1, a0, 32 -; LMULMAX1-NEXT: vse32.v v27, (a1) +; LMULMAX1-NEXT: vse32.v v10, (a1) ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vse32.v v26, (a1) -; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: vse32.v v9, (a1) +; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: ret %v = load <128 x i32>, <128 x i32>* %x ret <128 x i32> %v @@ -593,58 +593,58 @@ define <32 x i32> @ret_v32i32_param_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; LMULMAX4-NEXT: addi a1, a0, 64 -; LMULMAX4-NEXT: vle32.v v28, (a1) -; LMULMAX4-NEXT: vle32.v v24, (a0) +; LMULMAX4-NEXT: vle32.v v24, (a1) +; LMULMAX4-NEXT: vle32.v v28, (a0) ; LMULMAX4-NEXT: vadd.vv v8, v8, v16 ; LMULMAX4-NEXT: vadd.vv v12, v12, v20 -; LMULMAX4-NEXT: vadd.vv v28, v12, v28 -; LMULMAX4-NEXT: vadd.vv v8, v8, v24 +; LMULMAX4-NEXT: vadd.vv v12, v12, v24 +; LMULMAX4-NEXT: vadd.vv v8, v8, v28 ; LMULMAX4-NEXT: vadd.vx v8, v8, a2 -; LMULMAX4-NEXT: vadd.vx v12, v28, a2 +; LMULMAX4-NEXT: vadd.vx v12, v12, a2 ; LMULMAX4-NEXT: ret ; ; LMULMAX2-LABEL: ret_v32i32_param_v32i32_v32i32_v32i32_i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v24, (a0) ; LMULMAX2-NEXT: addi a1, a0, 32 -; LMULMAX2-NEXT: vle32.v v28, (a1) +; LMULMAX2-NEXT: vle32.v v26, (a1) ; LMULMAX2-NEXT: addi a1, a0, 64 -; LMULMAX2-NEXT: vle32.v v30, (a1) +; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: addi a0, a0, 96 -; LMULMAX2-NEXT: vle32.v v24, (a0) +; LMULMAX2-NEXT: vle32.v v30, (a0) ; LMULMAX2-NEXT: vadd.vv v8, v8, v16 ; LMULMAX2-NEXT: vadd.vv v10, v10, v18 ; LMULMAX2-NEXT: vadd.vv v12, v12, v20 ; LMULMAX2-NEXT: vadd.vv v14, v14, v22 -; LMULMAX2-NEXT: vadd.vv v14, v14, v24 -; LMULMAX2-NEXT: vadd.vv v30, v12, v30 -; LMULMAX2-NEXT: vadd.vv v28, v10, v28 -; LMULMAX2-NEXT: vadd.vv v26, v8, v26 -; LMULMAX2-NEXT: vadd.vx v8, v26, a4 -; LMULMAX2-NEXT: vadd.vx v10, v28, a4 -; LMULMAX2-NEXT: vadd.vx v12, v30, a4 +; LMULMAX2-NEXT: vadd.vv v14, v14, v30 +; LMULMAX2-NEXT: vadd.vv v12, v12, v28 +; LMULMAX2-NEXT: vadd.vv v10, v10, v26 +; LMULMAX2-NEXT: vadd.vv v8, v8, v24 +; LMULMAX2-NEXT: vadd.vx v8, v8, a4 +; LMULMAX2-NEXT: vadd.vx v10, v10, a4 +; LMULMAX2-NEXT: vadd.vx v12, v12, a4 ; LMULMAX2-NEXT: vadd.vx v14, v14, a4 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: ret_v32i32_param_v32i32_v32i32_v32i32_i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a0) +; LMULMAX1-NEXT: vle32.v v24, (a0) ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vle32.v v26, (a1) +; LMULMAX1-NEXT: vle32.v v25, (a1) ; LMULMAX1-NEXT: addi a1, a0, 32 -; LMULMAX1-NEXT: vle32.v v27, (a1) +; LMULMAX1-NEXT: vle32.v v26, (a1) ; LMULMAX1-NEXT: addi a1, a0, 48 -; LMULMAX1-NEXT: vle32.v v28, (a1) +; LMULMAX1-NEXT: vle32.v v27, (a1) ; LMULMAX1-NEXT: addi a1, a0, 64 -; LMULMAX1-NEXT: vle32.v v29, (a1) +; LMULMAX1-NEXT: vle32.v v28, (a1) ; LMULMAX1-NEXT: addi a1, a0, 80 -; LMULMAX1-NEXT: vle32.v v30, (a1) +; LMULMAX1-NEXT: vle32.v v29, (a1) ; LMULMAX1-NEXT: addi a1, a0, 96 -; LMULMAX1-NEXT: vle32.v v31, (a1) +; LMULMAX1-NEXT: vle32.v v30, (a1) ; LMULMAX1-NEXT: addi a0, a0, 112 -; LMULMAX1-NEXT: vle32.v v24, (a0) +; LMULMAX1-NEXT: vle32.v v31, (a0) ; LMULMAX1-NEXT: lw a0, 0(sp) ; LMULMAX1-NEXT: vadd.vv v8, v8, v16 ; LMULMAX1-NEXT: vadd.vv v9, v9, v17 @@ -654,21 +654,21 @@ define <32 x i32> @ret_v32i32_param_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 ; LMULMAX1-NEXT: vadd.vv v13, v13, v21 ; LMULMAX1-NEXT: vadd.vv v14, v14, v22 ; LMULMAX1-NEXT: vadd.vv v15, v15, v23 -; LMULMAX1-NEXT: vadd.vv v15, v15, v24 -; LMULMAX1-NEXT: vadd.vv v31, v14, v31 -; LMULMAX1-NEXT: vadd.vv v30, v13, v30 -; LMULMAX1-NEXT: vadd.vv v29, v12, v29 -; LMULMAX1-NEXT: vadd.vv v28, v11, v28 -; LMULMAX1-NEXT: vadd.vv v27, v10, v27 -; LMULMAX1-NEXT: vadd.vv v26, v9, v26 -; LMULMAX1-NEXT: vadd.vv v25, v8, v25 -; LMULMAX1-NEXT: vadd.vx v8, v25, a0 -; LMULMAX1-NEXT: vadd.vx v9, v26, a0 -; LMULMAX1-NEXT: vadd.vx v10, v27, a0 -; LMULMAX1-NEXT: vadd.vx v11, v28, a0 -; LMULMAX1-NEXT: vadd.vx v12, v29, a0 -; LMULMAX1-NEXT: vadd.vx v13, v30, a0 -; LMULMAX1-NEXT: vadd.vx v14, v31, a0 +; LMULMAX1-NEXT: vadd.vv v15, v15, v31 +; LMULMAX1-NEXT: vadd.vv v14, v14, v30 +; LMULMAX1-NEXT: vadd.vv v13, v13, v29 +; LMULMAX1-NEXT: vadd.vv v12, v12, v28 +; LMULMAX1-NEXT: vadd.vv v11, v11, v27 +; LMULMAX1-NEXT: vadd.vv v10, v10, v26 +; LMULMAX1-NEXT: vadd.vv v9, v9, v25 +; LMULMAX1-NEXT: vadd.vv v8, v8, v24 +; LMULMAX1-NEXT: vadd.vx v8, v8, a0 +; LMULMAX1-NEXT: vadd.vx v9, v9, a0 +; LMULMAX1-NEXT: vadd.vx v10, v10, a0 +; LMULMAX1-NEXT: vadd.vx v11, v11, a0 +; LMULMAX1-NEXT: vadd.vx v12, v12, a0 +; LMULMAX1-NEXT: vadd.vx v13, v13, a0 +; LMULMAX1-NEXT: vadd.vx v14, v14, a0 ; LMULMAX1-NEXT: vadd.vx v15, v15, a0 ; LMULMAX1-NEXT: ret %r = add <32 x i32> %x, %y @@ -704,13 +704,13 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> % ; LMULMAX4-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX4-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: .cfi_offset ra, -8 -; LMULMAX4-NEXT: vmv4r.v v28, v12 -; LMULMAX4-NEXT: vmv4r.v v24, v8 +; LMULMAX4-NEXT: vmv4r.v v24, v12 +; LMULMAX4-NEXT: vmv4r.v v28, v8 ; LMULMAX4-NEXT: addi a1, zero, 2 ; LMULMAX4-NEXT: vmv4r.v v8, v16 ; LMULMAX4-NEXT: vmv4r.v v12, v20 -; LMULMAX4-NEXT: vmv4r.v v16, v24 -; LMULMAX4-NEXT: vmv4r.v v20, v28 +; LMULMAX4-NEXT: vmv4r.v v16, v28 +; LMULMAX4-NEXT: vmv4r.v v20, v24 ; LMULMAX4-NEXT: call ext2@plt ; LMULMAX4-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: addi sp, sp, 16 @@ -722,19 +722,19 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> % ; LMULMAX2-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX2-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; LMULMAX2-NEXT: .cfi_offset ra, -8 -; LMULMAX2-NEXT: vmv2r.v v26, v14 -; LMULMAX2-NEXT: vmv2r.v v28, v12 -; LMULMAX2-NEXT: vmv2r.v v30, v10 -; LMULMAX2-NEXT: vmv2r.v v24, v8 +; LMULMAX2-NEXT: vmv2r.v v24, v14 +; LMULMAX2-NEXT: vmv2r.v v26, v12 +; LMULMAX2-NEXT: vmv2r.v v28, v10 +; LMULMAX2-NEXT: vmv2r.v v30, v8 ; LMULMAX2-NEXT: addi a1, zero, 2 ; LMULMAX2-NEXT: vmv2r.v v8, v16 ; LMULMAX2-NEXT: vmv2r.v v10, v18 ; LMULMAX2-NEXT: vmv2r.v v12, v20 ; LMULMAX2-NEXT: vmv2r.v v14, v22 -; LMULMAX2-NEXT: vmv2r.v v16, v24 -; LMULMAX2-NEXT: vmv2r.v v18, v30 -; LMULMAX2-NEXT: vmv2r.v v20, v28 -; LMULMAX2-NEXT: vmv2r.v v22, v26 +; LMULMAX2-NEXT: vmv2r.v v16, v30 +; LMULMAX2-NEXT: vmv2r.v v18, v28 +; LMULMAX2-NEXT: vmv2r.v v20, v26 +; LMULMAX2-NEXT: vmv2r.v v22, v24 ; LMULMAX2-NEXT: call ext2@plt ; LMULMAX2-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LMULMAX2-NEXT: addi sp, sp, 16 @@ -746,14 +746,14 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> % ; LMULMAX1-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX1-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; LMULMAX1-NEXT: .cfi_offset ra, -8 -; LMULMAX1-NEXT: vmv1r.v v25, v15 -; LMULMAX1-NEXT: vmv1r.v v26, v14 -; LMULMAX1-NEXT: vmv1r.v v27, v13 -; LMULMAX1-NEXT: vmv1r.v v28, v12 -; LMULMAX1-NEXT: vmv1r.v v29, v11 -; LMULMAX1-NEXT: vmv1r.v v30, v10 -; LMULMAX1-NEXT: vmv1r.v v31, v9 -; LMULMAX1-NEXT: vmv1r.v v24, v8 +; LMULMAX1-NEXT: vmv1r.v v24, v15 +; LMULMAX1-NEXT: vmv1r.v v25, v14 +; LMULMAX1-NEXT: vmv1r.v v26, v13 +; LMULMAX1-NEXT: vmv1r.v v27, v12 +; LMULMAX1-NEXT: vmv1r.v v28, v11 +; LMULMAX1-NEXT: vmv1r.v v29, v10 +; LMULMAX1-NEXT: vmv1r.v v30, v9 +; LMULMAX1-NEXT: vmv1r.v v31, v8 ; LMULMAX1-NEXT: addi a1, zero, 2 ; LMULMAX1-NEXT: vmv1r.v v8, v16 ; LMULMAX1-NEXT: vmv1r.v v9, v17 @@ -763,14 +763,14 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> % ; LMULMAX1-NEXT: vmv1r.v v13, v21 ; LMULMAX1-NEXT: vmv1r.v v14, v22 ; LMULMAX1-NEXT: vmv1r.v v15, v23 -; LMULMAX1-NEXT: vmv1r.v v16, v24 -; LMULMAX1-NEXT: vmv1r.v v17, v31 -; LMULMAX1-NEXT: vmv1r.v v18, v30 -; LMULMAX1-NEXT: vmv1r.v v19, v29 -; LMULMAX1-NEXT: vmv1r.v v20, v28 -; LMULMAX1-NEXT: vmv1r.v v21, v27 -; LMULMAX1-NEXT: vmv1r.v v22, v26 -; LMULMAX1-NEXT: vmv1r.v v23, v25 +; LMULMAX1-NEXT: vmv1r.v v16, v31 +; LMULMAX1-NEXT: vmv1r.v v17, v30 +; LMULMAX1-NEXT: vmv1r.v v18, v29 +; LMULMAX1-NEXT: vmv1r.v v19, v28 +; LMULMAX1-NEXT: vmv1r.v v20, v27 +; LMULMAX1-NEXT: vmv1r.v v21, v26 +; LMULMAX1-NEXT: vmv1r.v v22, v25 +; LMULMAX1-NEXT: vmv1r.v v23, v24 ; LMULMAX1-NEXT: call ext2@plt ; LMULMAX1-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LMULMAX1-NEXT: addi sp, sp, 16 @@ -806,17 +806,17 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x ; LMULMAX4-NEXT: sd ra, 152(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: .cfi_offset ra, -8 ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; LMULMAX4-NEXT: vle32.v v28, (a0) -; LMULMAX4-NEXT: addi a0, a0, 64 ; LMULMAX4-NEXT: vle32.v v24, (a0) +; LMULMAX4-NEXT: addi a0, a0, 64 +; LMULMAX4-NEXT: vle32.v v28, (a0) ; LMULMAX4-NEXT: addi a0, sp, 80 ; LMULMAX4-NEXT: vse32.v v12, (a0) ; LMULMAX4-NEXT: addi a0, sp, 16 ; LMULMAX4-NEXT: addi a3, zero, 42 ; LMULMAX4-NEXT: addi a1, sp, 16 ; LMULMAX4-NEXT: vse32.v v8, (a1) -; LMULMAX4-NEXT: vmv4r.v v8, v28 -; LMULMAX4-NEXT: vmv4r.v v12, v24 +; LMULMAX4-NEXT: vmv4r.v v8, v24 +; LMULMAX4-NEXT: vmv4r.v v12, v28 ; LMULMAX4-NEXT: call ext3@plt ; LMULMAX4-NEXT: ld ra, 152(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: addi sp, sp, 160 @@ -829,13 +829,13 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x ; LMULMAX2-NEXT: sd ra, 152(sp) # 8-byte Folded Spill ; LMULMAX2-NEXT: .cfi_offset ra, -8 ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v24, (a0) ; LMULMAX2-NEXT: addi a1, a0, 32 -; LMULMAX2-NEXT: vle32.v v28, (a1) +; LMULMAX2-NEXT: vle32.v v26, (a1) ; LMULMAX2-NEXT: addi a1, a0, 64 -; LMULMAX2-NEXT: vle32.v v30, (a1) +; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: addi a0, a0, 96 -; LMULMAX2-NEXT: vle32.v v24, (a0) +; LMULMAX2-NEXT: vle32.v v30, (a0) ; LMULMAX2-NEXT: addi a0, sp, 112 ; LMULMAX2-NEXT: vse32.v v14, (a0) ; LMULMAX2-NEXT: addi a0, sp, 80 @@ -846,10 +846,10 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x ; LMULMAX2-NEXT: addi a5, zero, 42 ; LMULMAX2-NEXT: addi a1, sp, 16 ; LMULMAX2-NEXT: vse32.v v8, (a1) -; LMULMAX2-NEXT: vmv2r.v v8, v26 -; LMULMAX2-NEXT: vmv2r.v v10, v28 -; LMULMAX2-NEXT: vmv2r.v v12, v30 -; LMULMAX2-NEXT: vmv2r.v v14, v24 +; LMULMAX2-NEXT: vmv2r.v v8, v24 +; LMULMAX2-NEXT: vmv2r.v v10, v26 +; LMULMAX2-NEXT: vmv2r.v v12, v28 +; LMULMAX2-NEXT: vmv2r.v v14, v30 ; LMULMAX2-NEXT: call ext3@plt ; LMULMAX2-NEXT: ld ra, 152(sp) # 8-byte Folded Reload ; LMULMAX2-NEXT: addi sp, sp, 160 @@ -862,21 +862,21 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x ; LMULMAX1-NEXT: sd ra, 168(sp) # 8-byte Folded Spill ; LMULMAX1-NEXT: .cfi_offset ra, -8 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a0) +; LMULMAX1-NEXT: vle32.v v24, (a0) ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vle32.v v26, (a1) +; LMULMAX1-NEXT: vle32.v v25, (a1) ; LMULMAX1-NEXT: addi a1, a0, 32 -; LMULMAX1-NEXT: vle32.v v27, (a1) +; LMULMAX1-NEXT: vle32.v v26, (a1) ; LMULMAX1-NEXT: addi a1, a0, 48 -; LMULMAX1-NEXT: vle32.v v28, (a1) +; LMULMAX1-NEXT: vle32.v v27, (a1) ; LMULMAX1-NEXT: addi a1, a0, 64 -; LMULMAX1-NEXT: vle32.v v29, (a1) +; LMULMAX1-NEXT: vle32.v v28, (a1) ; LMULMAX1-NEXT: addi a1, a0, 80 -; LMULMAX1-NEXT: vle32.v v30, (a1) +; LMULMAX1-NEXT: vle32.v v29, (a1) ; LMULMAX1-NEXT: addi a1, a0, 96 -; LMULMAX1-NEXT: vle32.v v31, (a1) +; LMULMAX1-NEXT: vle32.v v30, (a1) ; LMULMAX1-NEXT: addi a0, a0, 112 -; LMULMAX1-NEXT: vle32.v v24, (a0) +; LMULMAX1-NEXT: vle32.v v31, (a0) ; LMULMAX1-NEXT: ld a0, 176(sp) ; LMULMAX1-NEXT: addi a1, sp, 144 ; LMULMAX1-NEXT: vse32.v v15, (a1) @@ -898,14 +898,14 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x ; LMULMAX1-NEXT: addi a0, sp, 32 ; LMULMAX1-NEXT: addi a1, sp, 32 ; LMULMAX1-NEXT: vse32.v v8, (a1) -; LMULMAX1-NEXT: vmv1r.v v8, v25 -; LMULMAX1-NEXT: vmv1r.v v9, v26 -; LMULMAX1-NEXT: vmv1r.v v10, v27 -; LMULMAX1-NEXT: vmv1r.v v11, v28 -; LMULMAX1-NEXT: vmv1r.v v12, v29 -; LMULMAX1-NEXT: vmv1r.v v13, v30 -; LMULMAX1-NEXT: vmv1r.v v14, v31 -; LMULMAX1-NEXT: vmv1r.v v15, v24 +; LMULMAX1-NEXT: vmv1r.v v8, v24 +; LMULMAX1-NEXT: vmv1r.v v9, v25 +; LMULMAX1-NEXT: vmv1r.v v10, v26 +; LMULMAX1-NEXT: vmv1r.v v11, v27 +; LMULMAX1-NEXT: vmv1r.v v12, v28 +; LMULMAX1-NEXT: vmv1r.v v13, v29 +; LMULMAX1-NEXT: vmv1r.v v14, v30 +; LMULMAX1-NEXT: vmv1r.v v15, v31 ; LMULMAX1-NEXT: call ext3@plt ; LMULMAX1-NEXT: ld ra, 168(sp) # 8-byte Folded Reload ; LMULMAX1-NEXT: addi sp, sp, 176 @@ -940,9 +940,9 @@ define <32 x i32> @split_vector_args(<2 x i32>,<2 x i32>,<2 x i32>,<2 x i32>,<2 ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: addi a1, a0, 64 ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; LMULMAX4-NEXT: vle32.v v28, (a0) +; LMULMAX4-NEXT: vle32.v v8, (a0) ; LMULMAX4-NEXT: vle32.v v12, (a1) -; LMULMAX4-NEXT: vadd.vv v8, v16, v28 +; LMULMAX4-NEXT: vadd.vv v8, v16, v8 ; LMULMAX4-NEXT: vadd.vv v12, v20, v12 ; LMULMAX4-NEXT: ret ; @@ -950,36 +950,36 @@ define <32 x i32> @split_vector_args(<2 x i32>,<2 x i32>,<2 x i32>,<2 x i32>,<2 ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a1, a0, 64 ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a0) ; LMULMAX2-NEXT: addi a0, a0, 32 -; LMULMAX2-NEXT: vle32.v v28, (a0) -; LMULMAX2-NEXT: vle32.v v30, (a1) +; LMULMAX2-NEXT: vle32.v v12, (a0) +; LMULMAX2-NEXT: vle32.v v24, (a1) ; LMULMAX2-NEXT: vadd.vv v8, v14, v22 -; LMULMAX2-NEXT: vadd.vv v10, v16, v26 -; LMULMAX2-NEXT: vadd.vv v12, v18, v28 -; LMULMAX2-NEXT: vadd.vv v14, v20, v30 +; LMULMAX2-NEXT: vadd.vv v10, v16, v10 +; LMULMAX2-NEXT: vadd.vv v12, v18, v12 +; LMULMAX2-NEXT: vadd.vv v14, v20, v24 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: split_vector_args: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: addi a1, a0, 64 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a1) +; LMULMAX1-NEXT: vle32.v v24, (a1) ; LMULMAX1-NEXT: addi a1, a0, 48 -; LMULMAX1-NEXT: vle32.v v26, (a1) +; LMULMAX1-NEXT: vle32.v v25, (a1) ; LMULMAX1-NEXT: addi a1, a0, 32 -; LMULMAX1-NEXT: vle32.v v27, (a1) +; LMULMAX1-NEXT: vle32.v v26, (a1) ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vle32.v v28, (a1) -; LMULMAX1-NEXT: vle32.v v29, (a0) +; LMULMAX1-NEXT: vle32.v v12, (a1) +; LMULMAX1-NEXT: vle32.v v11, (a0) ; LMULMAX1-NEXT: vadd.vv v8, v13, v21 ; LMULMAX1-NEXT: vadd.vv v9, v14, v22 ; LMULMAX1-NEXT: vadd.vv v10, v15, v23 -; LMULMAX1-NEXT: vadd.vv v11, v16, v29 -; LMULMAX1-NEXT: vadd.vv v12, v17, v28 -; LMULMAX1-NEXT: vadd.vv v13, v18, v27 -; LMULMAX1-NEXT: vadd.vv v14, v19, v26 -; LMULMAX1-NEXT: vadd.vv v15, v20, v25 +; LMULMAX1-NEXT: vadd.vv v11, v16, v11 +; LMULMAX1-NEXT: vadd.vv v12, v17, v12 +; LMULMAX1-NEXT: vadd.vv v13, v18, v26 +; LMULMAX1-NEXT: vadd.vv v14, v19, v25 +; LMULMAX1-NEXT: vadd.vv v15, v20, v24 ; LMULMAX1-NEXT: ret %v0 = add <32 x i32> %y, %z ret <32 x i32> %v0 @@ -1141,11 +1141,11 @@ define <32 x i32> @vector_arg_via_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, ; LMULMAX4-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; LMULMAX4-NEXT: addi a0, sp, 16 -; LMULMAX4-NEXT: vle32.v v28, (a0) -; LMULMAX4-NEXT: addi a0, sp, 80 ; LMULMAX4-NEXT: vle32.v v16, (a0) -; LMULMAX4-NEXT: vadd.vv v8, v8, v28 -; LMULMAX4-NEXT: vadd.vv v12, v12, v16 +; LMULMAX4-NEXT: addi a0, sp, 80 +; LMULMAX4-NEXT: vle32.v v20, (a0) +; LMULMAX4-NEXT: vadd.vv v8, v8, v16 +; LMULMAX4-NEXT: vadd.vv v12, v12, v20 ; LMULMAX4-NEXT: addi sp, sp, 16 ; LMULMAX4-NEXT: ret ; @@ -1155,17 +1155,17 @@ define <32 x i32> @vector_arg_via_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, ; LMULMAX2-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: addi a0, sp, 16 -; LMULMAX2-NEXT: vle32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v16, (a0) ; LMULMAX2-NEXT: addi a0, sp, 48 -; LMULMAX2-NEXT: vle32.v v28, (a0) +; LMULMAX2-NEXT: vle32.v v18, (a0) ; LMULMAX2-NEXT: addi a0, sp, 80 -; LMULMAX2-NEXT: vle32.v v30, (a0) +; LMULMAX2-NEXT: vle32.v v20, (a0) ; LMULMAX2-NEXT: addi a0, sp, 112 -; LMULMAX2-NEXT: vle32.v v16, (a0) -; LMULMAX2-NEXT: vadd.vv v8, v8, v26 -; LMULMAX2-NEXT: vadd.vv v10, v10, v28 -; LMULMAX2-NEXT: vadd.vv v12, v12, v30 -; LMULMAX2-NEXT: vadd.vv v14, v14, v16 +; LMULMAX2-NEXT: vle32.v v22, (a0) +; LMULMAX2-NEXT: vadd.vv v8, v8, v16 +; LMULMAX2-NEXT: vadd.vv v10, v10, v18 +; LMULMAX2-NEXT: vadd.vv v12, v12, v20 +; LMULMAX2-NEXT: vadd.vv v14, v14, v22 ; LMULMAX2-NEXT: addi sp, sp, 16 ; LMULMAX2-NEXT: ret ; @@ -1175,29 +1175,29 @@ define <32 x i32> @vector_arg_via_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, ; LMULMAX1-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: addi a0, sp, 128 -; LMULMAX1-NEXT: vle32.v v25, (a0) +; LMULMAX1-NEXT: vle32.v v16, (a0) ; LMULMAX1-NEXT: addi a0, sp, 112 -; LMULMAX1-NEXT: vle32.v v26, (a0) +; LMULMAX1-NEXT: vle32.v v17, (a0) ; LMULMAX1-NEXT: addi a0, sp, 96 -; LMULMAX1-NEXT: vle32.v v27, (a0) +; LMULMAX1-NEXT: vle32.v v18, (a0) ; LMULMAX1-NEXT: addi a0, sp, 80 -; LMULMAX1-NEXT: vle32.v v28, (a0) +; LMULMAX1-NEXT: vle32.v v19, (a0) ; LMULMAX1-NEXT: addi a0, sp, 16 -; LMULMAX1-NEXT: vle32.v v29, (a0) +; LMULMAX1-NEXT: vle32.v v20, (a0) ; LMULMAX1-NEXT: addi a0, sp, 32 -; LMULMAX1-NEXT: vle32.v v30, (a0) +; LMULMAX1-NEXT: vle32.v v21, (a0) ; LMULMAX1-NEXT: addi a0, sp, 48 -; LMULMAX1-NEXT: vle32.v v31, (a0) +; LMULMAX1-NEXT: vle32.v v22, (a0) ; LMULMAX1-NEXT: addi a0, sp, 64 -; LMULMAX1-NEXT: vle32.v v16, (a0) -; LMULMAX1-NEXT: vadd.vv v8, v8, v29 -; LMULMAX1-NEXT: vadd.vv v9, v9, v30 -; LMULMAX1-NEXT: vadd.vv v10, v10, v31 -; LMULMAX1-NEXT: vadd.vv v11, v11, v16 -; LMULMAX1-NEXT: vadd.vv v12, v12, v28 -; LMULMAX1-NEXT: vadd.vv v13, v13, v27 -; LMULMAX1-NEXT: vadd.vv v14, v14, v26 -; LMULMAX1-NEXT: vadd.vv v15, v15, v25 +; LMULMAX1-NEXT: vle32.v v23, (a0) +; LMULMAX1-NEXT: vadd.vv v8, v8, v20 +; LMULMAX1-NEXT: vadd.vv v9, v9, v21 +; LMULMAX1-NEXT: vadd.vv v10, v10, v22 +; LMULMAX1-NEXT: vadd.vv v11, v11, v23 +; LMULMAX1-NEXT: vadd.vv v12, v12, v19 +; LMULMAX1-NEXT: vadd.vv v13, v13, v18 +; LMULMAX1-NEXT: vadd.vv v14, v14, v17 +; LMULMAX1-NEXT: vadd.vv v15, v15, v16 ; LMULMAX1-NEXT: addi sp, sp, 16 ; LMULMAX1-NEXT: ret %s = add <32 x i32> %x, %z @@ -1385,19 +1385,19 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) { ; LMULMAX8-NEXT: addi a0, zero, 8 ; LMULMAX8-NEXT: sd a0, 128(sp) ; LMULMAX8-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX8-NEXT: vmv.v.i v25, 0 -; LMULMAX8-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX8-NEXT: vmv.v.i v16, 0 +; LMULMAX8-NEXT: vmerge.vim v16, v16, 1, v0 ; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX8-NEXT: vmv.v.i v26, 0 +; LMULMAX8-NEXT: vmv.v.i v17, 0 ; LMULMAX8-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; LMULMAX8-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX8-NEXT: vslideup.vi v17, v16, 0 ; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX8-NEXT: vmsne.vi v25, v26, 0 +; LMULMAX8-NEXT: vmsne.vi v16, v17, 0 ; LMULMAX8-NEXT: addi a0, sp, 136 ; LMULMAX8-NEXT: addi a5, zero, 5 ; LMULMAX8-NEXT: addi a6, zero, 6 ; LMULMAX8-NEXT: addi a7, zero, 7 -; LMULMAX8-NEXT: vsm.v v25, (a0) +; LMULMAX8-NEXT: vsm.v v16, (a0) ; LMULMAX8-NEXT: mv a0, zero ; LMULMAX8-NEXT: mv a1, zero ; LMULMAX8-NEXT: mv a2, zero @@ -1423,19 +1423,19 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) { ; LMULMAX4-NEXT: addi a0, sp, 64 ; LMULMAX4-NEXT: vse32.v v8, (a0) ; LMULMAX4-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX4-NEXT: vmv.v.i v25, 0 -; LMULMAX4-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX4-NEXT: vmv.v.i v12, 0 +; LMULMAX4-NEXT: vmerge.vim v12, v12, 1, v0 ; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX4-NEXT: vmv.v.i v26, 0 +; LMULMAX4-NEXT: vmv.v.i v13, 0 ; LMULMAX4-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; LMULMAX4-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX4-NEXT: vslideup.vi v13, v12, 0 ; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX4-NEXT: vmsne.vi v25, v26, 0 +; LMULMAX4-NEXT: vmsne.vi v12, v13, 0 ; LMULMAX4-NEXT: addi a0, sp, 136 ; LMULMAX4-NEXT: addi a5, zero, 5 ; LMULMAX4-NEXT: addi a6, zero, 6 ; LMULMAX4-NEXT: addi a7, zero, 7 -; LMULMAX4-NEXT: vsm.v v25, (a0) +; LMULMAX4-NEXT: vsm.v v12, (a0) ; LMULMAX4-NEXT: mv a0, zero ; LMULMAX4-NEXT: mv a1, zero ; LMULMAX4-NEXT: mv a2, zero @@ -1467,19 +1467,19 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) { ; LMULMAX2-NEXT: addi a0, sp, 32 ; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX2-NEXT: vmv.v.i v25, 0 -; LMULMAX2-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX2-NEXT: vmv.v.i v10, 0 +; LMULMAX2-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v26, 0 +; LMULMAX2-NEXT: vmv.v.i v11, 0 ; LMULMAX2-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; LMULMAX2-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX2-NEXT: vslideup.vi v11, v10, 0 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX2-NEXT: vmsne.vi v25, v26, 0 +; LMULMAX2-NEXT: vmsne.vi v10, v11, 0 ; LMULMAX2-NEXT: addi a0, sp, 136 ; LMULMAX2-NEXT: addi a5, zero, 5 ; LMULMAX2-NEXT: addi a6, zero, 6 ; LMULMAX2-NEXT: addi a7, zero, 7 -; LMULMAX2-NEXT: vsm.v v25, (a0) +; LMULMAX2-NEXT: vsm.v v10, (a0) ; LMULMAX2-NEXT: mv a0, zero ; LMULMAX2-NEXT: mv a1, zero ; LMULMAX2-NEXT: mv a2, zero @@ -1523,19 +1523,19 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) { ; LMULMAX1-NEXT: addi a0, sp, 16 ; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v9, 0 +; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v10, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v25, v26, 0 +; LMULMAX1-NEXT: vmsne.vi v9, v10, 0 ; LMULMAX1-NEXT: addi a0, sp, 136 ; LMULMAX1-NEXT: addi a5, zero, 5 ; LMULMAX1-NEXT: addi a6, zero, 6 ; LMULMAX1-NEXT: addi a7, zero, 7 -; LMULMAX1-NEXT: vsm.v v25, (a0) +; LMULMAX1-NEXT: vsm.v v9, (a0) ; LMULMAX1-NEXT: mv a0, zero ; LMULMAX1-NEXT: mv a1, zero ; LMULMAX1-NEXT: mv a2, zero diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll index e2a7ac65e2c0ede42b7506438a7c365c6866dc57..e0a149ef2040e3b5fb56e75a20a8ee27f39dd612 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll @@ -10,8 +10,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: addi sp, sp, -32 ; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle8.v v25, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vle8.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -47,8 +47,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: addi a5, a5, -24 ; LMULMAX2-RV32-NEXT: sb a5, 16(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 15 -; LMULMAX2-RV32-NEXT: vmv.x.s a5, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 15 +; LMULMAX2-RV32-NEXT: vmv.x.s a5, v9 ; LMULMAX2-RV32-NEXT: andi a5, a5, 255 ; LMULMAX2-RV32-NEXT: srli a1, a5, 1 ; LMULMAX2-RV32-NEXT: or a1, a5, a1 @@ -75,8 +75,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 31(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 14 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 14 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 @@ -103,8 +103,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 30(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 13 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 13 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 @@ -131,8 +131,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 29(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 12 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 12 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 @@ -159,8 +159,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 28(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 11 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 11 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 @@ -187,8 +187,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 27(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 10 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 10 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 @@ -215,8 +215,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 26(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 9 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 9 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 @@ -243,8 +243,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 25(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 8 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 8 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 @@ -271,8 +271,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 24(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 @@ -299,8 +299,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 23(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 @@ -327,8 +327,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 22(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 @@ -355,8 +355,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 21(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 @@ -383,8 +383,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 20(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 @@ -411,8 +411,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 19(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 @@ -439,8 +439,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 18(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 @@ -469,8 +469,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: sb a1, 17(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 16 -; LMULMAX2-RV32-NEXT: vle8.v v25, (a1) -; LMULMAX2-RV32-NEXT: vse8.v v25, (a0) +; LMULMAX2-RV32-NEXT: vle8.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse8.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 ; LMULMAX2-RV32-NEXT: ret ; @@ -479,8 +479,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -32 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle8.v v25, (a0) -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV64-NEXT: vle8.v v8, (a0) +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -540,8 +540,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: addiw a5, a5, -56 ; LMULMAX2-RV64-NEXT: sb a5, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 15 -; LMULMAX2-RV64-NEXT: vmv.x.s a5, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 15 +; LMULMAX2-RV64-NEXT: vmv.x.s a5, v9 ; LMULMAX2-RV64-NEXT: andi a5, a5, 255 ; LMULMAX2-RV64-NEXT: srli a1, a5, 1 ; LMULMAX2-RV64-NEXT: or a1, a5, a1 @@ -570,8 +570,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 31(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 14 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 14 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 @@ -600,8 +600,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 30(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 13 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 13 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 @@ -630,8 +630,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 29(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 12 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 12 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 @@ -660,8 +660,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 11 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 11 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 @@ -690,8 +690,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 27(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 10 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 10 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 @@ -720,8 +720,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 26(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 9 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 9 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 @@ -750,8 +750,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 25(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 8 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 8 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 @@ -780,8 +780,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 @@ -810,8 +810,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 23(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 @@ -840,8 +840,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 22(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 @@ -870,8 +870,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 21(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 @@ -900,8 +900,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 20(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 @@ -930,8 +930,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 19(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 @@ -960,8 +960,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 18(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 @@ -992,8 +992,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: sb a1, 17(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle8.v v25, (a1) -; LMULMAX2-RV64-NEXT: vse8.v v25, (a0) +; LMULMAX2-RV64-NEXT: vle8.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse8.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 ; LMULMAX2-RV64-NEXT: ret ; @@ -1002,8 +1002,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: addi sp, sp, -32 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -1039,8 +1039,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: addi a5, a5, -24 ; LMULMAX1-RV32-NEXT: sb a5, 16(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 15 -; LMULMAX1-RV32-NEXT: vmv.x.s a5, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 15 +; LMULMAX1-RV32-NEXT: vmv.x.s a5, v9 ; LMULMAX1-RV32-NEXT: andi a5, a5, 255 ; LMULMAX1-RV32-NEXT: srli a1, a5, 1 ; LMULMAX1-RV32-NEXT: or a1, a5, a1 @@ -1067,8 +1067,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 31(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 14 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 14 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 @@ -1095,8 +1095,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 30(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 13 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 13 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 @@ -1123,8 +1123,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 29(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 12 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 12 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 @@ -1151,8 +1151,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 11 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 11 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 @@ -1179,8 +1179,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 27(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 10 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 10 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 @@ -1207,8 +1207,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 26(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 9 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 9 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 @@ -1235,8 +1235,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 25(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 8 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 8 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 @@ -1263,8 +1263,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 @@ -1291,8 +1291,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 23(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 @@ -1319,8 +1319,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 22(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 @@ -1347,8 +1347,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 21(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 @@ -1375,8 +1375,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 20(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 @@ -1403,8 +1403,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 19(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 @@ -1431,8 +1431,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 18(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 @@ -1461,8 +1461,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: sb a1, 17(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle8.v v25, (a1) -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a1) +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 ; LMULMAX1-RV32-NEXT: ret ; @@ -1471,8 +1471,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: addi sp, sp, -32 ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -1532,8 +1532,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: addiw a5, a5, -56 ; LMULMAX1-RV64-NEXT: sb a5, 16(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 15 -; LMULMAX1-RV64-NEXT: vmv.x.s a5, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 15 +; LMULMAX1-RV64-NEXT: vmv.x.s a5, v9 ; LMULMAX1-RV64-NEXT: andi a5, a5, 255 ; LMULMAX1-RV64-NEXT: srli a1, a5, 1 ; LMULMAX1-RV64-NEXT: or a1, a5, a1 @@ -1562,8 +1562,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 31(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 14 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 14 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a5, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a5 @@ -1592,8 +1592,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 30(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 13 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 13 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a5, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a5 @@ -1622,8 +1622,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 29(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 12 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 12 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a5, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a5 @@ -1652,8 +1652,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 11 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 11 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a5, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a5 @@ -1682,8 +1682,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 27(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 10 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 10 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a5, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a5 @@ -1712,8 +1712,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 26(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 9 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 9 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a5, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a5 @@ -1742,8 +1742,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 25(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 8 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 8 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a5, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a5 @@ -1772,8 +1772,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a5, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a5 @@ -1802,8 +1802,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 23(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a5, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a5 @@ -1832,8 +1832,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 22(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a5, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a5 @@ -1862,8 +1862,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 21(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a5, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a5 @@ -1892,8 +1892,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 20(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a5, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a5 @@ -1922,8 +1922,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 19(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a5, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a5 @@ -1952,8 +1952,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 18(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a5, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a5 @@ -1984,8 +1984,8 @@ define void @ctlz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: sb a1, 17(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, sp, 16 -; LMULMAX1-RV64-NEXT: vle8.v v25, (a1) -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a1) +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x @@ -2002,8 +2002,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: addi sp, sp, -32 ; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle16.v v25, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a2, v25 +; LMULMAX2-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX2-RV32-NEXT: lui a1, 16 ; LMULMAX2-RV32-NEXT: addi a6, a1, -1 ; LMULMAX2-RV32-NEXT: and a2, a2, a6 @@ -2041,8 +2041,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 16(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -2069,8 +2069,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 30(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -2097,8 +2097,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 28(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -2125,8 +2125,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 26(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -2153,8 +2153,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 24(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -2181,8 +2181,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 22(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -2209,8 +2209,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 20(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -2239,8 +2239,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: sh a1, 18(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 16 -; LMULMAX2-RV32-NEXT: vle16.v v25, (a1) -; LMULMAX2-RV32-NEXT: vse16.v v25, (a0) +; LMULMAX2-RV32-NEXT: vle16.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 ; LMULMAX2-RV32-NEXT: ret ; @@ -2249,8 +2249,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -32 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle16.v v25, (a0) -; LMULMAX2-RV64-NEXT: vmv.x.s a2, v25 +; LMULMAX2-RV64-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV64-NEXT: vmv.x.s a2, v8 ; LMULMAX2-RV64-NEXT: lui a1, 16 ; LMULMAX2-RV64-NEXT: addiw a6, a1, -1 ; LMULMAX2-RV64-NEXT: and a2, a2, a6 @@ -2312,8 +2312,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -2342,8 +2342,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 30(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -2372,8 +2372,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -2402,8 +2402,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 26(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -2432,8 +2432,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -2462,8 +2462,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 22(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -2492,8 +2492,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 20(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -2524,8 +2524,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: sh a1, 18(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle16.v v25, (a1) -; LMULMAX2-RV64-NEXT: vse16.v v25, (a0) +; LMULMAX2-RV64-NEXT: vle16.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 ; LMULMAX2-RV64-NEXT: ret ; @@ -2534,8 +2534,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: addi sp, sp, -32 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV32-NEXT: lui a1, 16 ; LMULMAX1-RV32-NEXT: addi a6, a1, -1 ; LMULMAX1-RV32-NEXT: and a2, a2, a6 @@ -2573,8 +2573,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: addi a1, a1, -16 ; LMULMAX1-RV32-NEXT: sh a1, 16(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: and a1, a1, a6 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -2601,8 +2601,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -16 ; LMULMAX1-RV32-NEXT: sh a1, 30(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: and a1, a1, a6 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -2629,8 +2629,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -16 ; LMULMAX1-RV32-NEXT: sh a1, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: and a1, a1, a6 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -2657,8 +2657,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -16 ; LMULMAX1-RV32-NEXT: sh a1, 26(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: and a1, a1, a6 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -2685,8 +2685,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -16 ; LMULMAX1-RV32-NEXT: sh a1, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: and a1, a1, a6 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -2713,8 +2713,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -16 ; LMULMAX1-RV32-NEXT: sh a1, 22(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: and a1, a1, a6 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -2741,8 +2741,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -16 ; LMULMAX1-RV32-NEXT: sh a1, 20(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: and a1, a1, a6 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -2771,8 +2771,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: sh a1, 18(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle16.v v25, (a1) -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a1) +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 ; LMULMAX1-RV32-NEXT: ret ; @@ -2781,8 +2781,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: addi sp, sp, -32 ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV64-NEXT: lui a1, 16 ; LMULMAX1-RV64-NEXT: addiw a6, a1, -1 ; LMULMAX1-RV64-NEXT: and a2, a2, a6 @@ -2844,8 +2844,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX1-RV64-NEXT: sh a1, 16(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: and a1, a1, a6 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -2874,8 +2874,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX1-RV64-NEXT: sh a1, 30(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: and a1, a1, a6 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -2904,8 +2904,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX1-RV64-NEXT: sh a1, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: and a1, a1, a6 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -2934,8 +2934,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX1-RV64-NEXT: sh a1, 26(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: and a1, a1, a6 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -2964,8 +2964,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX1-RV64-NEXT: sh a1, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: and a1, a1, a6 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -2994,8 +2994,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX1-RV64-NEXT: sh a1, 22(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: and a1, a1, a6 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -3024,8 +3024,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX1-RV64-NEXT: sh a1, 20(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: and a1, a1, a6 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -3056,8 +3056,8 @@ define void @ctlz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: sh a1, 18(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, sp, 16 -; LMULMAX1-RV64-NEXT: vle16.v v25, (a1) -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a1) +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x @@ -3074,8 +3074,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-NEXT: addi sp, sp, -32 ; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle32.v v25, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 ; LMULMAX2-RV32-NEXT: srli a2, a1, 2 @@ -3109,8 +3109,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-NEXT: srli a5, a5, 24 ; LMULMAX2-RV32-NEXT: sw a5, 16(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a5, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a5, v9 ; LMULMAX2-RV32-NEXT: srli a1, a5, 1 ; LMULMAX2-RV32-NEXT: or a1, a5, a1 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -3135,8 +3135,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 28(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -3161,8 +3161,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 24(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -3189,8 +3189,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-NEXT: sw a1, 20(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 16 -; LMULMAX2-RV32-NEXT: vle32.v v25, (a1) -; LMULMAX2-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX2-RV32-NEXT: vle32.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 ; LMULMAX2-RV32-NEXT: ret ; @@ -3199,8 +3199,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -32 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle32.v v25, (a0) -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV64-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: srliw a2, a1, 1 ; LMULMAX2-RV64-NEXT: slli a1, a1, 32 ; LMULMAX2-RV64-NEXT: srli a1, a1, 32 @@ -3261,8 +3261,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV64-NEXT: addiw a5, a5, -32 ; LMULMAX2-RV64-NEXT: sw a5, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a5, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a5, v9 ; LMULMAX2-RV64-NEXT: srliw a1, a5, 1 ; LMULMAX2-RV64-NEXT: slli a5, a5, 32 ; LMULMAX2-RV64-NEXT: srli a5, a5, 32 @@ -3292,8 +3292,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX2-RV64-NEXT: sw a1, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: srliw a5, a1, 1 ; LMULMAX2-RV64-NEXT: slli a1, a1, 32 ; LMULMAX2-RV64-NEXT: srli a1, a1, 32 @@ -3323,8 +3323,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX2-RV64-NEXT: sw a1, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: srliw a5, a1, 1 ; LMULMAX2-RV64-NEXT: slli a1, a1, 32 ; LMULMAX2-RV64-NEXT: srli a1, a1, 32 @@ -3356,8 +3356,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV64-NEXT: sw a1, 20(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle32.v v25, (a1) -; LMULMAX2-RV64-NEXT: vse32.v v25, (a0) +; LMULMAX2-RV64-NEXT: vle32.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 ; LMULMAX2-RV64-NEXT: ret ; @@ -3366,8 +3366,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV32-NEXT: addi sp, sp, -32 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: srli a2, a1, 2 @@ -3401,8 +3401,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV32-NEXT: srli a5, a5, 24 ; LMULMAX1-RV32-NEXT: sw a5, 16(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a5, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a5, v9 ; LMULMAX1-RV32-NEXT: srli a1, a5, 1 ; LMULMAX1-RV32-NEXT: or a1, a5, a1 ; LMULMAX1-RV32-NEXT: srli a5, a1, 2 @@ -3427,8 +3427,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a5, a1, 2 @@ -3453,8 +3453,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a5, a1, 2 @@ -3481,8 +3481,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV32-NEXT: sw a1, 20(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 ; LMULMAX1-RV32-NEXT: ret ; @@ -3491,8 +3491,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV64-NEXT: addi sp, sp, -32 ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: srliw a2, a1, 1 ; LMULMAX1-RV64-NEXT: slli a1, a1, 32 ; LMULMAX1-RV64-NEXT: srli a1, a1, 32 @@ -3553,8 +3553,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV64-NEXT: addiw a5, a5, -32 ; LMULMAX1-RV64-NEXT: sw a5, 16(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a5, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a5, v9 ; LMULMAX1-RV64-NEXT: srliw a1, a5, 1 ; LMULMAX1-RV64-NEXT: slli a5, a5, 32 ; LMULMAX1-RV64-NEXT: srli a5, a5, 32 @@ -3584,8 +3584,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX1-RV64-NEXT: sw a1, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: srliw a5, a1, 1 ; LMULMAX1-RV64-NEXT: slli a1, a1, 32 ; LMULMAX1-RV64-NEXT: srli a1, a1, 32 @@ -3615,8 +3615,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX1-RV64-NEXT: sw a1, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: srliw a5, a1, 1 ; LMULMAX1-RV64-NEXT: slli a1, a1, 32 ; LMULMAX1-RV64-NEXT: srli a1, a1, 32 @@ -3648,8 +3648,8 @@ define void @ctlz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV64-NEXT: sw a1, 20(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, sp, 16 -; LMULMAX1-RV64-NEXT: vle32.v v25, (a1) -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x @@ -3666,13 +3666,13 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV32-NEXT: addi sp, sp, -32 ; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32-NEXT: sw zero, 28(sp) ; LMULMAX2-RV32-NEXT: sw zero, 20(sp) ; LMULMAX2-RV32-NEXT: addi a6, zero, 32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vsrl.vx v26, v25, a6 -; LMULMAX2-RV32-NEXT: vmv.x.s a5, v26 +; LMULMAX2-RV32-NEXT: vsrl.vx v9, v8, a6 +; LMULMAX2-RV32-NEXT: vmv.x.s a5, v9 ; LMULMAX2-RV32-NEXT: lui a1, 349525 ; LMULMAX2-RV32-NEXT: addi a4, a1, 1365 ; LMULMAX2-RV32-NEXT: lui a1, 209715 @@ -3683,7 +3683,7 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV32-NEXT: addi a2, a1, 257 ; LMULMAX2-RV32-NEXT: bnez a5, .LBB3_2 ; LMULMAX2-RV32-NEXT: # %bb.1: -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -3734,13 +3734,13 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a2 ; LMULMAX2-RV32-NEXT: srli a5, a1, 24 ; LMULMAX2-RV32-NEXT: .LBB3_3: -; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX2-RV32-NEXT: vsrl.vx v26, v25, a6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vsrl.vx v9, v8, a6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: sw a5, 16(sp) ; LMULMAX2-RV32-NEXT: bnez a1, .LBB3_5 ; LMULMAX2-RV32-NEXT: # %bb.4: -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -3794,19 +3794,19 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV32-NEXT: sw a1, 24(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 16 -; LMULMAX2-RV32-NEXT: vle32.v v25, (a1) +; LMULMAX2-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctlz_v2i64: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 ; LMULMAX2-RV64-NEXT: srli a2, a1, 2 @@ -3863,8 +3863,8 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV64-NEXT: vmv.v.x v26, a1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV64-NEXT: vmv.v.x v9, a1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: srli a3, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a3 ; LMULMAX2-RV64-NEXT: srli a3, a1, 2 @@ -3891,8 +3891,8 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1 -; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vmv.s.x v9, a1 +; LMULMAX2-RV64-NEXT: vse64.v v9, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctlz_v2i64: @@ -3900,13 +3900,13 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV32-NEXT: addi sp, sp, -32 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: sw zero, 28(sp) ; LMULMAX1-RV32-NEXT: sw zero, 20(sp) ; LMULMAX1-RV32-NEXT: addi a6, zero, 32 ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a6 -; LMULMAX1-RV32-NEXT: vmv.x.s a5, v26 +; LMULMAX1-RV32-NEXT: vsrl.vx v9, v8, a6 +; LMULMAX1-RV32-NEXT: vmv.x.s a5, v9 ; LMULMAX1-RV32-NEXT: lui a1, 349525 ; LMULMAX1-RV32-NEXT: addi a4, a1, 1365 ; LMULMAX1-RV32-NEXT: lui a1, 209715 @@ -3917,7 +3917,7 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV32-NEXT: addi a2, a1, 257 ; LMULMAX1-RV32-NEXT: bnez a5, .LBB3_2 ; LMULMAX1-RV32-NEXT: # %bb.1: -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a5, a1, 2 @@ -3968,13 +3968,13 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a2 ; LMULMAX1-RV32-NEXT: srli a5, a1, 24 ; LMULMAX1-RV32-NEXT: .LBB3_3: -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vsrl.vx v9, v8, a6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: sw a5, 16(sp) ; LMULMAX1-RV32-NEXT: bnez a1, .LBB3_5 ; LMULMAX1-RV32-NEXT: # %bb.4: -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a5, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a5, a1, 2 @@ -4028,19 +4028,19 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV32-NEXT: sw a1, 24(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctlz_v2i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: srli a2, a1, 2 @@ -4097,8 +4097,8 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.x v26, a1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vmv.v.x v9, a1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: srli a3, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a3 ; LMULMAX1-RV64-NEXT: srli a3, a1, 2 @@ -4125,8 +4125,8 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 -; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX1-RV64-NEXT: vmv.s.x v9, a1 +; LMULMAX1-RV64-NEXT: vse64.v v9, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -4150,8 +4150,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: andi sp, sp, -32 ; LMULMAX2-RV32-NEXT: addi a6, zero, 32 ; LMULMAX2-RV32-NEXT: vsetvli zero, a6, e8, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle8.v v26, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX2-RV32-NEXT: vle8.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX2-RV32-NEXT: andi a2, a2, 255 ; LMULMAX2-RV32-NEXT: srli a3, a2, 1 ; LMULMAX2-RV32-NEXT: or a2, a2, a3 @@ -4187,8 +4187,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 32(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, m2, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 31 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 31 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4215,8 +4215,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 63(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 30 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 30 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4243,8 +4243,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 62(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 29 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 29 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4271,8 +4271,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 61(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 28 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 28 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4299,8 +4299,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 60(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 27 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 27 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4327,8 +4327,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 59(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 26 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 26 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4355,8 +4355,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 58(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 25 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 25 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4383,8 +4383,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 57(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 24 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 24 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4411,8 +4411,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 56(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 23 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 23 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4439,8 +4439,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 55(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 22 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 22 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4467,8 +4467,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 54(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 21 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 21 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4495,8 +4495,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 53(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 20 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 20 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4523,8 +4523,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 52(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 19 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 19 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4551,8 +4551,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 51(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 18 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 18 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4579,8 +4579,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 50(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 17 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 17 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4607,8 +4607,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 49(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 16 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 16 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4635,8 +4635,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 48(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 15 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 15 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4663,8 +4663,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 47(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 14 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 14 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4691,8 +4691,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 46(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 13 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 13 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4719,8 +4719,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 45(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 12 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 12 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4747,8 +4747,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 44(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 11 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 11 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4775,8 +4775,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 43(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 10 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 10 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4803,8 +4803,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 42(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 9 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 9 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4831,8 +4831,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 41(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 8 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 8 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4859,8 +4859,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 40(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4887,8 +4887,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 39(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4915,8 +4915,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 38(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4943,8 +4943,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 37(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4971,8 +4971,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 36(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -4999,8 +4999,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 35(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -5027,8 +5027,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -24 ; LMULMAX2-RV32-NEXT: sb a1, 34(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: andi a1, a1, 255 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -5057,8 +5057,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: sb a1, 33(sp) ; LMULMAX2-RV32-NEXT: vsetvli zero, a6, e8, m2, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 32 -; LMULMAX2-RV32-NEXT: vle8.v v26, (a1) -; LMULMAX2-RV32-NEXT: vse8.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle8.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse8.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload @@ -5071,8 +5071,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX2-RV64-NEXT: addi a6, zero, 32 ; LMULMAX2-RV64-NEXT: vsetvli zero, a6, e8, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle8.v v26, (a0) -; LMULMAX2-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX2-RV64-NEXT: vle8.v v8, (a0) +; LMULMAX2-RV64-NEXT: vmv.x.s a2, v8 ; LMULMAX2-RV64-NEXT: andi a2, a2, 255 ; LMULMAX2-RV64-NEXT: srli a3, a2, 1 ; LMULMAX2-RV64-NEXT: or a2, a2, a3 @@ -5132,8 +5132,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, m2, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 31 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 31 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5162,8 +5162,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 47(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 30 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 30 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5192,8 +5192,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 46(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 29 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 29 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5222,8 +5222,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 45(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 28 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 28 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5252,8 +5252,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 44(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 27 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 27 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5282,8 +5282,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 43(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 26 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 26 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5312,8 +5312,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 42(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 25 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 25 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5342,8 +5342,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 41(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 24 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 24 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5372,8 +5372,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 40(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 23 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 23 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5402,8 +5402,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 39(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 22 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 22 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5432,8 +5432,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 38(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 21 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 21 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5462,8 +5462,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 37(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 20 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 20 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5492,8 +5492,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 36(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 19 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 19 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5522,8 +5522,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 35(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 18 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 18 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5552,8 +5552,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 34(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 17 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 17 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5582,8 +5582,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 33(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 16 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 16 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5612,8 +5612,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 32(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 15 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 15 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5642,8 +5642,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 31(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 14 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 14 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5672,8 +5672,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 30(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 13 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 13 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5702,8 +5702,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 29(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 12 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 12 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5732,8 +5732,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 11 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 11 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5762,8 +5762,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 27(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 10 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 10 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5792,8 +5792,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 26(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 9 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 9 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5822,8 +5822,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 25(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 8 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 8 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5852,8 +5852,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5882,8 +5882,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 23(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5912,8 +5912,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 22(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5942,8 +5942,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 21(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -5972,8 +5972,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 20(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -6002,8 +6002,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 19(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -6032,8 +6032,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX2-RV64-NEXT: sb a1, 18(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: andi a1, a1, 255 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -6064,8 +6064,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: sb a1, 17(sp) ; LMULMAX2-RV64-NEXT: vsetvli zero, a6, e8, m2, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle8.v v26, (a1) -; LMULMAX2-RV64-NEXT: vse8.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle8.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse8.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 48 ; LMULMAX2-RV64-NEXT: ret ; @@ -6075,9 +6075,9 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a6, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a6) -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vle8.v v9, (a6) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: andi a2, a2, 255 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -6113,8 +6113,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 32(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 15 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 15 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6141,8 +6141,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 47(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 14 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 14 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6169,8 +6169,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 46(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 13 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 13 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6197,8 +6197,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 45(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 12 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 12 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6225,8 +6225,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 44(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 11 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 11 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6253,8 +6253,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 43(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 10 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 10 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6281,8 +6281,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 42(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 9 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 9 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6309,8 +6309,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 41(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 8 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 8 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6337,8 +6337,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 40(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 7 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 7 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6365,8 +6365,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 39(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6393,8 +6393,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 38(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 5 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 5 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6421,8 +6421,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 37(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 4 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 4 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6449,8 +6449,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 36(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6477,8 +6477,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 35(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6505,8 +6505,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 34(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6533,7 +6533,7 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 33(sp) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6560,8 +6560,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 16(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 15 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 15 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6588,8 +6588,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 31(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 14 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 14 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6616,8 +6616,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 30(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 13 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 13 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6644,8 +6644,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 29(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 12 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 12 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6672,8 +6672,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 11 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 11 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6700,8 +6700,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 27(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 10 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 10 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6728,8 +6728,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 26(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 9 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 9 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6756,8 +6756,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 25(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 8 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 8 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6784,8 +6784,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6812,8 +6812,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 23(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6840,8 +6840,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 22(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6868,8 +6868,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 21(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6896,8 +6896,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 20(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6924,8 +6924,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 19(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6952,8 +6952,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: addi a1, a1, -24 ; LMULMAX1-RV32-NEXT: sb a1, 18(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: andi a1, a1, 255 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 @@ -6982,11 +6982,11 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: sb a1, 17(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle8.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a1, sp, 32 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a1) -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a6) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a1) +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 ; LMULMAX1-RV32-NEXT: ret ; @@ -6996,9 +6996,9 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a6, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a6) -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vle8.v v9, (a6) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: andi a2, a2, 255 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -7058,8 +7058,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 32(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 15 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 15 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7088,8 +7088,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 47(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 14 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 14 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7118,8 +7118,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 46(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 13 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 13 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7148,8 +7148,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 45(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 12 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 12 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7178,8 +7178,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 44(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 11 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 11 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7208,8 +7208,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 43(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 10 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 10 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7238,8 +7238,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 42(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 9 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 9 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7268,8 +7268,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 41(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 8 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 8 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7298,8 +7298,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 40(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 7 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 7 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7328,8 +7328,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 39(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 6 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 6 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7358,8 +7358,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 38(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 5 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 5 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7388,8 +7388,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 37(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 4 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 4 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7418,8 +7418,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 36(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7448,8 +7448,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 35(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7478,8 +7478,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 34(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7508,7 +7508,7 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 33(sp) -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7537,8 +7537,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 16(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 15 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 15 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7567,8 +7567,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 31(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 14 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 14 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7597,8 +7597,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 30(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 13 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 13 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7627,8 +7627,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 29(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 12 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 12 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7657,8 +7657,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 11 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 11 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7687,8 +7687,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 27(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 10 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 10 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7717,8 +7717,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 26(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 9 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 9 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7747,8 +7747,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 25(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 8 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 8 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7777,8 +7777,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7807,8 +7807,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 23(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7837,8 +7837,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 22(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7867,8 +7867,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 21(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7897,8 +7897,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 20(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7927,8 +7927,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 19(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7957,8 +7957,8 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -56 ; LMULMAX1-RV64-NEXT: sb a1, 18(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: andi a1, a1, 255 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 @@ -7989,11 +7989,11 @@ define void @ctlz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: sb a1, 17(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, sp, 16 -; LMULMAX1-RV64-NEXT: vle8.v v25, (a1) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a1) ; LMULMAX1-RV64-NEXT: addi a1, sp, 32 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a1) -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a6) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a1) +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a6) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x @@ -8017,8 +8017,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX2-RV32-NEXT: andi sp, sp, -32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle16.v v26, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX2-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX2-RV32-NEXT: lui a1, 16 ; LMULMAX2-RV32-NEXT: addi a6, a1, -1 ; LMULMAX2-RV32-NEXT: and a2, a2, a6 @@ -8056,8 +8056,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 32(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 15 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 15 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -8084,8 +8084,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 62(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 14 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 14 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -8112,8 +8112,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 60(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 13 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 13 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -8140,8 +8140,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 58(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 12 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 12 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -8168,8 +8168,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 56(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 11 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 11 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -8196,8 +8196,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 54(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 10 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 10 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -8224,8 +8224,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 52(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 9 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 9 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -8252,8 +8252,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 50(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 8 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 8 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -8280,8 +8280,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 48(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -8308,8 +8308,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 46(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -8336,8 +8336,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 44(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -8364,8 +8364,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 42(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -8392,8 +8392,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 40(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -8420,8 +8420,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 38(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -8448,8 +8448,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: addi a1, a1, -16 ; LMULMAX2-RV32-NEXT: sh a1, 36(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: and a1, a1, a6 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 @@ -8478,8 +8478,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: sh a1, 34(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 32 -; LMULMAX2-RV32-NEXT: vle16.v v26, (a1) -; LMULMAX2-RV32-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle16.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload @@ -8491,8 +8491,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -48 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle16.v v26, (a0) -; LMULMAX2-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX2-RV64-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV64-NEXT: vmv.x.s a2, v8 ; LMULMAX2-RV64-NEXT: lui a1, 16 ; LMULMAX2-RV64-NEXT: addiw a6, a1, -1 ; LMULMAX2-RV64-NEXT: and a2, a2, a6 @@ -8554,8 +8554,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 15 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 15 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -8584,8 +8584,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 46(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 14 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 14 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -8614,8 +8614,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 44(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 13 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 13 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -8644,8 +8644,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 42(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 12 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 12 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -8674,8 +8674,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 40(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 11 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 11 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -8704,8 +8704,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 38(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 10 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 10 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -8734,8 +8734,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 36(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 9 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 9 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -8764,8 +8764,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 34(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 8 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 8 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -8794,8 +8794,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 32(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -8824,8 +8824,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 30(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -8854,8 +8854,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -8884,8 +8884,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 26(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -8914,8 +8914,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -8944,8 +8944,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 22(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -8974,8 +8974,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -48 ; LMULMAX2-RV64-NEXT: sh a1, 20(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: and a1, a1, a6 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 @@ -9006,8 +9006,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: sh a1, 18(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle16.v v26, (a1) -; LMULMAX2-RV64-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle16.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 48 ; LMULMAX2-RV64-NEXT: ret ; @@ -9017,9 +9017,9 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a6, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a6) -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vle16.v v9, (a6) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: lui a2, 16 ; LMULMAX1-RV32-NEXT: addi a7, a2, -1 ; LMULMAX1-RV32-NEXT: and a1, a1, a7 @@ -9057,8 +9057,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: addi a2, a2, -16 ; LMULMAX1-RV32-NEXT: sh a2, 32(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 7 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 7 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: and a2, a2, a7 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -9085,8 +9085,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: addi a2, a2, -16 ; LMULMAX1-RV32-NEXT: sh a2, 46(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 6 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 6 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: and a2, a2, a7 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -9113,8 +9113,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: addi a2, a2, -16 ; LMULMAX1-RV32-NEXT: sh a2, 44(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 5 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 5 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: and a2, a2, a7 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -9141,8 +9141,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: addi a2, a2, -16 ; LMULMAX1-RV32-NEXT: sh a2, 42(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 4 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 4 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: and a2, a2, a7 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -9169,8 +9169,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: addi a2, a2, -16 ; LMULMAX1-RV32-NEXT: sh a2, 40(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: and a2, a2, a7 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -9197,8 +9197,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: addi a2, a2, -16 ; LMULMAX1-RV32-NEXT: sh a2, 38(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: and a2, a2, a7 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -9225,8 +9225,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: addi a2, a2, -16 ; LMULMAX1-RV32-NEXT: sh a2, 36(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: and a2, a2, a7 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -9253,7 +9253,7 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: addi a2, a2, -16 ; LMULMAX1-RV32-NEXT: sh a2, 34(sp) -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV32-NEXT: and a2, a2, a7 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -9280,8 +9280,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: addi a2, a2, -16 ; LMULMAX1-RV32-NEXT: sh a2, 16(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: and a2, a2, a7 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -9308,8 +9308,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: addi a2, a2, -16 ; LMULMAX1-RV32-NEXT: sh a2, 30(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: and a2, a2, a7 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -9336,8 +9336,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: addi a2, a2, -16 ; LMULMAX1-RV32-NEXT: sh a2, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: and a2, a2, a7 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -9364,8 +9364,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: addi a2, a2, -16 ; LMULMAX1-RV32-NEXT: sh a2, 26(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: and a2, a2, a7 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -9392,8 +9392,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: addi a2, a2, -16 ; LMULMAX1-RV32-NEXT: sh a2, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: and a2, a2, a7 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -9420,8 +9420,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: addi a2, a2, -16 ; LMULMAX1-RV32-NEXT: sh a2, 22(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: and a2, a2, a7 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -9448,8 +9448,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: addi a2, a2, -16 ; LMULMAX1-RV32-NEXT: sh a2, 20(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV32-NEXT: and a2, a2, a7 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 @@ -9478,11 +9478,11 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: sh a1, 18(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle16.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a1, sp, 32 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a1) -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a6) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a1) +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 ; LMULMAX1-RV32-NEXT: ret ; @@ -9492,9 +9492,9 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a6, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a6) -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vle16.v v9, (a6) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: lui a2, 16 ; LMULMAX1-RV64-NEXT: addiw a7, a2, -1 ; LMULMAX1-RV64-NEXT: and a1, a1, a7 @@ -9556,8 +9556,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: addiw a2, a2, -48 ; LMULMAX1-RV64-NEXT: sh a2, 32(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 7 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 7 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: and a2, a2, a7 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -9586,8 +9586,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -48 ; LMULMAX1-RV64-NEXT: sh a2, 46(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 6 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 6 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: and a2, a2, a7 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -9616,8 +9616,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -48 ; LMULMAX1-RV64-NEXT: sh a2, 44(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 5 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 5 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: and a2, a2, a7 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -9646,8 +9646,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -48 ; LMULMAX1-RV64-NEXT: sh a2, 42(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 4 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 4 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: and a2, a2, a7 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -9676,8 +9676,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -48 ; LMULMAX1-RV64-NEXT: sh a2, 40(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: and a2, a2, a7 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -9706,8 +9706,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -48 ; LMULMAX1-RV64-NEXT: sh a2, 38(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: and a2, a2, a7 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -9736,8 +9736,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -48 ; LMULMAX1-RV64-NEXT: sh a2, 36(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: and a2, a2, a7 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -9766,7 +9766,7 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -48 ; LMULMAX1-RV64-NEXT: sh a2, 34(sp) -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV64-NEXT: and a2, a2, a7 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -9795,8 +9795,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -48 ; LMULMAX1-RV64-NEXT: sh a2, 16(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: and a2, a2, a7 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -9825,8 +9825,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -48 ; LMULMAX1-RV64-NEXT: sh a2, 30(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: and a2, a2, a7 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -9855,8 +9855,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -48 ; LMULMAX1-RV64-NEXT: sh a2, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: and a2, a2, a7 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -9885,8 +9885,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -48 ; LMULMAX1-RV64-NEXT: sh a2, 26(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: and a2, a2, a7 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -9915,8 +9915,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -48 ; LMULMAX1-RV64-NEXT: sh a2, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: and a2, a2, a7 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -9945,8 +9945,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -48 ; LMULMAX1-RV64-NEXT: sh a2, 22(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: and a2, a2, a7 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -9975,8 +9975,8 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -48 ; LMULMAX1-RV64-NEXT: sh a2, 20(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV64-NEXT: and a2, a2, a7 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 @@ -10007,11 +10007,11 @@ define void @ctlz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: sh a1, 18(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, sp, 16 -; LMULMAX1-RV64-NEXT: vle16.v v25, (a1) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a1) ; LMULMAX1-RV64-NEXT: addi a1, sp, 32 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a1) -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a6) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a1) +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a6) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x @@ -10035,8 +10035,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX2-RV32-NEXT: andi sp, sp, -32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle32.v v26, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: srli a2, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a2 ; LMULMAX2-RV32-NEXT: srli a2, a1, 2 @@ -10070,8 +10070,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: srli a5, a5, 24 ; LMULMAX2-RV32-NEXT: sw a5, 32(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV32-NEXT: vmv.x.s a5, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV32-NEXT: vmv.x.s a5, v10 ; LMULMAX2-RV32-NEXT: srli a1, a5, 1 ; LMULMAX2-RV32-NEXT: or a1, a5, a1 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -10096,8 +10096,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 60(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -10122,8 +10122,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 56(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -10148,8 +10148,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 52(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -10174,8 +10174,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 48(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -10200,8 +10200,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 44(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -10226,8 +10226,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 40(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -10254,8 +10254,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: sw a1, 36(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 32 -; LMULMAX2-RV32-NEXT: vle32.v v26, (a1) -; LMULMAX2-RV32-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle32.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload @@ -10267,8 +10267,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -48 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle32.v v26, (a0) -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: srliw a2, a1, 1 ; LMULMAX2-RV64-NEXT: slli a1, a1, 32 ; LMULMAX2-RV64-NEXT: srli a1, a1, 32 @@ -10329,8 +10329,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: addiw a5, a5, -32 ; LMULMAX2-RV64-NEXT: sw a5, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV64-NEXT: vmv.x.s a5, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV64-NEXT: vmv.x.s a5, v10 ; LMULMAX2-RV64-NEXT: srliw a1, a5, 1 ; LMULMAX2-RV64-NEXT: slli a5, a5, 32 ; LMULMAX2-RV64-NEXT: srli a5, a5, 32 @@ -10360,8 +10360,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX2-RV64-NEXT: sw a1, 44(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: srliw a5, a1, 1 ; LMULMAX2-RV64-NEXT: slli a1, a1, 32 ; LMULMAX2-RV64-NEXT: srli a1, a1, 32 @@ -10391,8 +10391,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX2-RV64-NEXT: sw a1, 40(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: srliw a5, a1, 1 ; LMULMAX2-RV64-NEXT: slli a1, a1, 32 ; LMULMAX2-RV64-NEXT: srli a1, a1, 32 @@ -10422,8 +10422,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX2-RV64-NEXT: sw a1, 36(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: srliw a5, a1, 1 ; LMULMAX2-RV64-NEXT: slli a1, a1, 32 ; LMULMAX2-RV64-NEXT: srli a1, a1, 32 @@ -10453,8 +10453,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX2-RV64-NEXT: sw a1, 32(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: srliw a5, a1, 1 ; LMULMAX2-RV64-NEXT: slli a1, a1, 32 ; LMULMAX2-RV64-NEXT: srli a1, a1, 32 @@ -10484,8 +10484,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX2-RV64-NEXT: sw a1, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: srliw a5, a1, 1 ; LMULMAX2-RV64-NEXT: slli a1, a1, 32 ; LMULMAX2-RV64-NEXT: srli a1, a1, 32 @@ -10515,8 +10515,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX2-RV64-NEXT: sw a1, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: srliw a5, a1, 1 ; LMULMAX2-RV64-NEXT: slli a1, a1, 32 ; LMULMAX2-RV64-NEXT: srli a1, a1, 32 @@ -10548,8 +10548,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: sw a1, 20(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle32.v v26, (a1) -; LMULMAX2-RV64-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle32.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 48 ; LMULMAX2-RV64-NEXT: ret ; @@ -10559,9 +10559,9 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a6, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a6) -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vle32.v v9, (a6) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: srli a3, a2, 1 ; LMULMAX1-RV32-NEXT: or a2, a2, a3 ; LMULMAX1-RV32-NEXT: srli a3, a2, 2 @@ -10595,8 +10595,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 32(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: srli a2, a1, 2 @@ -10621,8 +10621,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 44(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: srli a2, a1, 2 @@ -10647,8 +10647,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 40(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: srli a2, a1, 2 @@ -10673,7 +10673,7 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 36(sp) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: srli a2, a1, 2 @@ -10698,8 +10698,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 16(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: srli a2, a1, 2 @@ -10724,8 +10724,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: srli a2, a1, 2 @@ -10750,8 +10750,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: srli a2, a1, 2 @@ -10778,11 +10778,11 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: sw a1, 20(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a1, sp, 32 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a1) -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a6) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a1) +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 ; LMULMAX1-RV32-NEXT: ret ; @@ -10792,9 +10792,9 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a6, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a6) -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vle32.v v9, (a6) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: srliw a3, a2, 1 ; LMULMAX1-RV64-NEXT: slli a2, a2, 32 ; LMULMAX1-RV64-NEXT: srli a2, a2, 32 @@ -10855,8 +10855,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX1-RV64-NEXT: sw a1, 32(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: srliw a2, a1, 1 ; LMULMAX1-RV64-NEXT: slli a1, a1, 32 ; LMULMAX1-RV64-NEXT: srli a1, a1, 32 @@ -10886,8 +10886,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX1-RV64-NEXT: sw a1, 44(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: srliw a2, a1, 1 ; LMULMAX1-RV64-NEXT: slli a1, a1, 32 ; LMULMAX1-RV64-NEXT: srli a1, a1, 32 @@ -10917,8 +10917,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX1-RV64-NEXT: sw a1, 40(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: srliw a2, a1, 1 ; LMULMAX1-RV64-NEXT: slli a1, a1, 32 ; LMULMAX1-RV64-NEXT: srli a1, a1, 32 @@ -10948,7 +10948,7 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX1-RV64-NEXT: sw a1, 36(sp) -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: srliw a2, a1, 1 ; LMULMAX1-RV64-NEXT: slli a1, a1, 32 ; LMULMAX1-RV64-NEXT: srli a1, a1, 32 @@ -10978,8 +10978,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX1-RV64-NEXT: sw a1, 16(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: srliw a2, a1, 1 ; LMULMAX1-RV64-NEXT: slli a1, a1, 32 ; LMULMAX1-RV64-NEXT: srli a1, a1, 32 @@ -11009,8 +11009,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX1-RV64-NEXT: sw a1, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: srliw a2, a1, 1 ; LMULMAX1-RV64-NEXT: slli a1, a1, 32 ; LMULMAX1-RV64-NEXT: srli a1, a1, 32 @@ -11040,8 +11040,8 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -32 ; LMULMAX1-RV64-NEXT: sw a1, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: srliw a2, a1, 1 ; LMULMAX1-RV64-NEXT: slli a1, a1, 32 ; LMULMAX1-RV64-NEXT: srli a1, a1, 32 @@ -11073,11 +11073,11 @@ define void @ctlz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: sw a1, 20(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, sp, 16 -; LMULMAX1-RV64-NEXT: vle32.v v25, (a1) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV64-NEXT: addi a1, sp, 32 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a1) -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a6) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a1) +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a6) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x @@ -11101,15 +11101,15 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX2-RV32-NEXT: andi sp, sp, -32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle64.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32-NEXT: sw zero, 60(sp) ; LMULMAX2-RV32-NEXT: sw zero, 52(sp) ; LMULMAX2-RV32-NEXT: sw zero, 44(sp) ; LMULMAX2-RV32-NEXT: sw zero, 36(sp) ; LMULMAX2-RV32-NEXT: addi a6, zero, 32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vsrl.vx v28, v26, a6 -; LMULMAX2-RV32-NEXT: vmv.x.s a5, v28 +; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a6 +; LMULMAX2-RV32-NEXT: vmv.x.s a5, v10 ; LMULMAX2-RV32-NEXT: lui a1, 349525 ; LMULMAX2-RV32-NEXT: addi a4, a1, 1365 ; LMULMAX2-RV32-NEXT: lui a1, 209715 @@ -11120,7 +11120,7 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: addi a2, a1, 257 ; LMULMAX2-RV32-NEXT: bnez a5, .LBB7_2 ; LMULMAX2-RV32-NEXT: # %bb.1: -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -11171,13 +11171,13 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a2 ; LMULMAX2-RV32-NEXT: srli a5, a1, 24 ; LMULMAX2-RV32-NEXT: .LBB7_3: -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV32-NEXT: vsrl.vx v30, v28, a6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v30 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV32-NEXT: vsrl.vx v12, v10, a6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v12 ; LMULMAX2-RV32-NEXT: sw a5, 32(sp) ; LMULMAX2-RV32-NEXT: bnez a1, .LBB7_5 ; LMULMAX2-RV32-NEXT: # %bb.4: -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -11228,13 +11228,13 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a2 ; LMULMAX2-RV32-NEXT: srli a5, a1, 24 ; LMULMAX2-RV32-NEXT: .LBB7_6: -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV32-NEXT: vsrl.vx v30, v28, a6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v30 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV32-NEXT: vsrl.vx v12, v10, a6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v12 ; LMULMAX2-RV32-NEXT: sw a5, 56(sp) ; LMULMAX2-RV32-NEXT: bnez a1, .LBB7_8 ; LMULMAX2-RV32-NEXT: # %bb.7: -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -11285,13 +11285,13 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a2 ; LMULMAX2-RV32-NEXT: srli a5, a1, 24 ; LMULMAX2-RV32-NEXT: .LBB7_9: -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV32-NEXT: vsrl.vx v28, v26, a6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: sw a5, 48(sp) ; LMULMAX2-RV32-NEXT: bnez a1, .LBB7_11 ; LMULMAX2-RV32-NEXT: # %bb.10: -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: srli a5, a1, 1 ; LMULMAX2-RV32-NEXT: or a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a5, a1, 2 @@ -11345,9 +11345,9 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: sw a1, 40(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 32 -; LMULMAX2-RV32-NEXT: vle32.v v26, (a1) +; LMULMAX2-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload @@ -11359,8 +11359,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -48 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle64.v v26, (a0) -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: srli a2, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a2 ; LMULMAX2-RV64-NEXT: srli a2, a1, 2 @@ -11418,8 +11418,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: srli a5, a5, 56 ; LMULMAX2-RV64-NEXT: sd a5, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a5, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a5, v10 ; LMULMAX2-RV64-NEXT: srli a1, a5, 1 ; LMULMAX2-RV64-NEXT: or a1, a5, a1 ; LMULMAX2-RV64-NEXT: srli a5, a1, 2 @@ -11446,8 +11446,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sd a1, 40(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a5, a1, 2 @@ -11474,8 +11474,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sd a1, 32(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: srli a5, a1, 1 ; LMULMAX2-RV64-NEXT: or a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a5, a1, 2 @@ -11504,8 +11504,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: sd a1, 24(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle64.v v26, (a1) -; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle64.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 48 ; LMULMAX2-RV64-NEXT: ret ; @@ -11514,15 +11514,15 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: addi sp, sp, -48 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a6, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a6) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a6) ; LMULMAX1-RV32-NEXT: sw zero, 44(sp) ; LMULMAX1-RV32-NEXT: sw zero, 36(sp) ; LMULMAX1-RV32-NEXT: addi a7, zero, 32 ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vsrl.vx v27, v26, a7 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vsrl.vx v10, v9, a7 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: lui a2, 349525 ; LMULMAX1-RV32-NEXT: addi a5, a2, 1365 ; LMULMAX1-RV32-NEXT: lui a2, 209715 @@ -11533,7 +11533,7 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: addi a3, a2, 257 ; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_2 ; LMULMAX1-RV32-NEXT: # %bb.1: -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: srli a2, a1, 2 @@ -11584,13 +11584,13 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a3 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: .LBB7_3: -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV32-NEXT: vsrl.vx v27, v26, a7 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV32-NEXT: vsrl.vx v10, v9, a7 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: sw a1, 32(sp) ; LMULMAX1-RV32-NEXT: bnez a2, .LBB7_5 ; LMULMAX1-RV32-NEXT: # %bb.4: -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: srli a2, a1, 2 @@ -11643,12 +11643,12 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: .LBB7_6: ; LMULMAX1-RV32-NEXT: sw a1, 40(sp) ; LMULMAX1-RV32-NEXT: sw zero, 28(sp) -; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a7 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vsrl.vx v9, v8, a7 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: sw zero, 20(sp) ; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_8 ; LMULMAX1-RV32-NEXT: # %bb.7: -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: srli a2, a1, 2 @@ -11699,13 +11699,13 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a3 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: .LBB7_9: -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a7 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vsrl.vx v9, v8, a7 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: sw a1, 16(sp) ; LMULMAX1-RV32-NEXT: bnez a2, .LBB7_11 ; LMULMAX1-RV32-NEXT: # %bb.10: -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: srli a2, a1, 1 ; LMULMAX1-RV32-NEXT: or a1, a1, a2 ; LMULMAX1-RV32-NEXT: srli a2, a1, 2 @@ -11759,12 +11759,12 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: sw a1, 24(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a1, sp, 32 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a1) ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a6) +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 ; LMULMAX1-RV32-NEXT: ret ; @@ -11772,11 +11772,11 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a6, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a6) -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a6) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v27, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v10, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: srli a3, a2, 1 ; LMULMAX1-RV64-NEXT: or a2, a2, a3 ; LMULMAX1-RV64-NEXT: srli a3, a2, 2 @@ -11833,8 +11833,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.x v26, a1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vmv.v.x v9, a1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: srli a2, a1, 2 @@ -11861,10 +11861,10 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 +; LMULMAX1-RV64-NEXT: vmv.s.x v9, a1 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: srli a2, a1, 2 @@ -11891,8 +11891,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.x v27, a1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vmv.v.x v10, a1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: srli a2, a1, 2 @@ -11919,9 +11919,9 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1 -; LMULMAX1-RV64-NEXT: vse64.v v27, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a6) +; LMULMAX1-RV64-NEXT: vmv.s.x v10, a1 +; LMULMAX1-RV64-NEXT: vse64.v v10, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a6) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll index 1412d6a54d6d2b5c75394637ba0e057084e61714..3a337724d35cec7e2937e3a56005b7334a188ad3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll @@ -8,20 +8,20 @@ define void @ctpop_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: ctpop_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vsrl.vi v26, v25, 1 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: addi a1, zero, 85 -; CHECK-NEXT: vand.vx v26, v26, a1 -; CHECK-NEXT: vsub.vv v25, v25, v26 +; CHECK-NEXT: vand.vx v9, v9, a1 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: addi a1, zero, 51 -; CHECK-NEXT: vand.vx v26, v25, a1 -; CHECK-NEXT: vsrl.vi v25, v25, 2 -; CHECK-NEXT: vand.vx v25, v25, a1 -; CHECK-NEXT: vadd.vv v25, v26, v25 -; CHECK-NEXT: vsrl.vi v26, v25, 4 -; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vand.vi v25, v25, 15 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vand.vx v9, v8, a1 +; CHECK-NEXT: vsrl.vi v8, v8, 2 +; CHECK-NEXT: vand.vx v8, v8, a1 +; CHECK-NEXT: vadd.vv v8, v9, v8 +; CHECK-NEXT: vsrl.vi v9, v8, 4 +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: vand.vi v8, v8, 15 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -35,105 +35,105 @@ define void @ctpop_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-LABEL: ctpop_v8i16: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle16.v v25, (a0) -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX2-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX2-RV32-NEXT: lui a1, 5 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1365 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vsub.vv v25, v25, v26 +; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v9 ; LMULMAX2-RV32-NEXT: lui a1, 3 ; LMULMAX2-RV32-NEXT: addi a1, a1, 819 -; LMULMAX2-RV32-NEXT: vand.vx v26, v25, a1 -; LMULMAX2-RV32-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV32-NEXT: vadd.vv v25, v26, v25 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 4 -; LMULMAX2-RV32-NEXT: vadd.vv v25, v25, v26 +; LMULMAX2-RV32-NEXT: vand.vx v9, v8, a1 +; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v9, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 4 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v9 ; LMULMAX2-RV32-NEXT: lui a1, 1 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241 -; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV32-NEXT: addi a1, zero, 257 -; LMULMAX2-RV32-NEXT: vmul.vx v25, v25, a1 -; LMULMAX2-RV32-NEXT: vsrl.vi v25, v25, 8 -; LMULMAX2-RV32-NEXT: vse16.v v25, (a0) +; LMULMAX2-RV32-NEXT: vmul.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 8 +; LMULMAX2-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctpop_v8i16: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle16.v v25, (a0) -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX2-RV64-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX2-RV64-NEXT: lui a1, 5 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vsub.vv v25, v25, v26 +; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v9 ; LMULMAX2-RV64-NEXT: lui a1, 3 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 819 -; LMULMAX2-RV64-NEXT: vand.vx v26, v25, a1 -; LMULMAX2-RV64-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vadd.vv v25, v26, v25 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 4 -; LMULMAX2-RV64-NEXT: vadd.vv v25, v25, v26 +; LMULMAX2-RV64-NEXT: vand.vx v9, v8, a1 +; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v9, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 4 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v9 ; LMULMAX2-RV64-NEXT: lui a1, 1 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -241 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV64-NEXT: addi a1, zero, 257 -; LMULMAX2-RV64-NEXT: vmul.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vsrl.vi v25, v25, 8 -; LMULMAX2-RV64-NEXT: vse16.v v25, (a0) +; LMULMAX2-RV64-NEXT: vmul.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 8 +; LMULMAX2-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctpop_v8i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX1-RV32-NEXT: lui a1, 5 ; LMULMAX1-RV32-NEXT: addi a1, a1, 1365 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v26 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v9 ; LMULMAX1-RV32-NEXT: lui a1, 3 ; LMULMAX1-RV32-NEXT: addi a1, a1, 819 -; LMULMAX1-RV32-NEXT: vand.vx v26, v25, a1 -; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v26, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 4 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v26 +; LMULMAX1-RV32-NEXT: vand.vx v9, v8, a1 +; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v9, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v9 ; LMULMAX1-RV32-NEXT: lui a1, 1 ; LMULMAX1-RV32-NEXT: addi a1, a1, -241 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1 ; LMULMAX1-RV32-NEXT: addi a1, zero, 257 -; LMULMAX1-RV32-NEXT: vmul.vx v25, v25, a1 -; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 8 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a1 +; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 8 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctpop_v8i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX1-RV64-NEXT: lui a1, 5 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 1365 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v26 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v9 ; LMULMAX1-RV64-NEXT: lui a1, 3 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 819 -; LMULMAX1-RV64-NEXT: vand.vx v26, v25, a1 -; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v26, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 4 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v26 +; LMULMAX1-RV64-NEXT: vand.vx v9, v8, a1 +; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v9, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 4 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v9 ; LMULMAX1-RV64-NEXT: lui a1, 1 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -241 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 ; LMULMAX1-RV64-NEXT: addi a1, zero, 257 -; LMULMAX1-RV64-NEXT: vmul.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 8 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 8 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -147,109 +147,109 @@ define void @ctpop_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-LABEL: ctpop_v4i32: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle32.v v25, (a0) -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX2-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX2-RV32-NEXT: lui a1, 349525 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1365 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vsub.vv v25, v25, v26 +; LMULMAX2-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v9 ; LMULMAX2-RV32-NEXT: lui a1, 209715 ; LMULMAX2-RV32-NEXT: addi a1, a1, 819 -; LMULMAX2-RV32-NEXT: vand.vx v26, v25, a1 -; LMULMAX2-RV32-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV32-NEXT: vadd.vv v25, v26, v25 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 4 -; LMULMAX2-RV32-NEXT: vadd.vv v25, v25, v26 +; LMULMAX2-RV32-NEXT: vand.vx v9, v8, a1 +; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v9, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 4 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v9 ; LMULMAX2-RV32-NEXT: lui a1, 61681 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241 -; LMULMAX2-RV32-NEXT: vand.vx v25, v25, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV32-NEXT: lui a1, 4112 ; LMULMAX2-RV32-NEXT: addi a1, a1, 257 -; LMULMAX2-RV32-NEXT: vmul.vx v25, v25, a1 -; LMULMAX2-RV32-NEXT: vsrl.vi v25, v25, 24 -; LMULMAX2-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX2-RV32-NEXT: vmul.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 24 +; LMULMAX2-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctpop_v4i32: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle32.v v25, (a0) -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX2-RV64-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX2-RV64-NEXT: lui a1, 349525 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vsub.vv v25, v25, v26 +; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v9 ; LMULMAX2-RV64-NEXT: lui a1, 209715 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 819 -; LMULMAX2-RV64-NEXT: vand.vx v26, v25, a1 -; LMULMAX2-RV64-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vadd.vv v25, v26, v25 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 4 -; LMULMAX2-RV64-NEXT: vadd.vv v25, v25, v26 +; LMULMAX2-RV64-NEXT: vand.vx v9, v8, a1 +; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v9, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 4 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v9 ; LMULMAX2-RV64-NEXT: lui a1, 61681 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -241 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV64-NEXT: lui a1, 4112 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 257 -; LMULMAX2-RV64-NEXT: vmul.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vsrl.vi v25, v25, 24 -; LMULMAX2-RV64-NEXT: vse32.v v25, (a0) +; LMULMAX2-RV64-NEXT: vmul.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 24 +; LMULMAX2-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctpop_v4i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX1-RV32-NEXT: lui a1, 349525 ; LMULMAX1-RV32-NEXT: addi a1, a1, 1365 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v26 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v9 ; LMULMAX1-RV32-NEXT: lui a1, 209715 ; LMULMAX1-RV32-NEXT: addi a1, a1, 819 -; LMULMAX1-RV32-NEXT: vand.vx v26, v25, a1 -; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v26, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 4 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v26 +; LMULMAX1-RV32-NEXT: vand.vx v9, v8, a1 +; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v9, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v9 ; LMULMAX1-RV32-NEXT: lui a1, 61681 ; LMULMAX1-RV32-NEXT: addi a1, a1, -241 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a1 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a1 ; LMULMAX1-RV32-NEXT: lui a1, 4112 ; LMULMAX1-RV32-NEXT: addi a1, a1, 257 -; LMULMAX1-RV32-NEXT: vmul.vx v25, v25, a1 -; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 24 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a1 +; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 24 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctpop_v4i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX1-RV64-NEXT: lui a1, 349525 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 1365 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v26 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v9 ; LMULMAX1-RV64-NEXT: lui a1, 209715 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 819 -; LMULMAX1-RV64-NEXT: vand.vx v26, v25, a1 -; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v26, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 4 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v26 +; LMULMAX1-RV64-NEXT: vand.vx v9, v8, a1 +; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v9, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 4 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v9 ; LMULMAX1-RV64-NEXT: lui a1, 61681 ; LMULMAX1-RV64-NEXT: addiw a1, a1, -241 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 ; LMULMAX1-RV64-NEXT: lui a1, 4112 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 257 -; LMULMAX1-RV64-NEXT: vmul.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 24 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 24 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -263,48 +263,48 @@ define void @ctpop_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV32-LABEL: ctpop_v2i64: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle64.v v25, (a0) -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX2-RV32-NEXT: lui a1, 349525 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1365 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v27, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v27 -; LMULMAX2-RV32-NEXT: vsub.vv v25, v25, v26 +; LMULMAX2-RV32-NEXT: vand.vv v9, v9, v10 +; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v9 ; LMULMAX2-RV32-NEXT: lui a1, 209715 ; LMULMAX2-RV32-NEXT: addi a1, a1, 819 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v26, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v9, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vand.vv v27, v25, v26 -; LMULMAX2-RV32-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX2-RV32-NEXT: vand.vv v25, v25, v26 -; LMULMAX2-RV32-NEXT: vadd.vv v25, v27, v25 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v25, 4 -; LMULMAX2-RV32-NEXT: vadd.vv v25, v25, v26 +; LMULMAX2-RV32-NEXT: vand.vv v10, v8, v9 +; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v9 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v10, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v9, v8, 4 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v9 ; LMULMAX2-RV32-NEXT: lui a1, 61681 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v26, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v9, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vand.vv v25, v25, v26 +; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v9 ; LMULMAX2-RV32-NEXT: lui a1, 4112 ; LMULMAX2-RV32-NEXT: addi a1, a1, 257 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v26, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v9, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vmul.vv v25, v25, v26 +; LMULMAX2-RV32-NEXT: vmul.vv v8, v8, v9 ; LMULMAX2-RV32-NEXT: addi a1, zero, 56 -; LMULMAX2-RV32-NEXT: vsrl.vx v25, v25, a1 -; LMULMAX2-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX2-RV32-NEXT: vsrl.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctpop_v2i64: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle64.v v25, (a0) -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX2-RV64-NEXT: lui a1, 21845 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 @@ -313,8 +313,8 @@ define void @ctpop_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV64-NEXT: addi a1, a1, 1365 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 ; LMULMAX2-RV64-NEXT: addi a1, a1, 1365 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vsub.vv v25, v25, v26 +; LMULMAX2-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v9 ; LMULMAX2-RV64-NEXT: lui a1, 13107 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 819 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 @@ -323,12 +323,12 @@ define void @ctpop_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV64-NEXT: addi a1, a1, 819 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 ; LMULMAX2-RV64-NEXT: addi a1, a1, 819 -; LMULMAX2-RV64-NEXT: vand.vx v26, v25, a1 -; LMULMAX2-RV64-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vadd.vv v25, v26, v25 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v25, 4 -; LMULMAX2-RV64-NEXT: vadd.vv v25, v25, v26 +; LMULMAX2-RV64-NEXT: vand.vx v9, v8, a1 +; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v9, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v9, v8, 4 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v9 ; LMULMAX2-RV64-NEXT: lui a1, 3855 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 241 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 @@ -337,64 +337,64 @@ define void @ctpop_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV64-NEXT: addi a1, a1, 241 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 ; LMULMAX2-RV64-NEXT: addi a1, a1, -241 -; LMULMAX2-RV64-NEXT: vand.vx v25, v25, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV64-NEXT: lui a1, 4112 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 257 ; LMULMAX2-RV64-NEXT: slli a1, a1, 16 ; LMULMAX2-RV64-NEXT: addi a1, a1, 257 ; LMULMAX2-RV64-NEXT: slli a1, a1, 16 ; LMULMAX2-RV64-NEXT: addi a1, a1, 257 -; LMULMAX2-RV64-NEXT: vmul.vx v25, v25, a1 +; LMULMAX2-RV64-NEXT: vmul.vx v8, v8, a1 ; LMULMAX2-RV64-NEXT: addi a1, zero, 56 -; LMULMAX2-RV64-NEXT: vsrl.vx v25, v25, a1 -; LMULMAX2-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX2-RV64-NEXT: vsrl.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctpop_v2i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX1-RV32-NEXT: lui a1, 349525 ; LMULMAX1-RV32-NEXT: addi a1, a1, 1365 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v27, a1 +; LMULMAX1-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v26 +; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v9 ; LMULMAX1-RV32-NEXT: lui a1, 209715 ; LMULMAX1-RV32-NEXT: addi a1, a1, 819 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v26, a1 +; LMULMAX1-RV32-NEXT: vmv.v.x v9, a1 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vand.vv v27, v25, v26 -; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v26 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v27, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v25, 4 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v26 +; LMULMAX1-RV32-NEXT: vand.vv v10, v8, v9 +; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v9 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v10, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v9 ; LMULMAX1-RV32-NEXT: lui a1, 61681 ; LMULMAX1-RV32-NEXT: addi a1, a1, -241 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v26, a1 +; LMULMAX1-RV32-NEXT: vmv.v.x v9, a1 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v26 +; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v9 ; LMULMAX1-RV32-NEXT: lui a1, 4112 ; LMULMAX1-RV32-NEXT: addi a1, a1, 257 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v26, a1 +; LMULMAX1-RV32-NEXT: vmv.v.x v9, a1 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v26 +; LMULMAX1-RV32-NEXT: vmul.vv v8, v8, v9 ; LMULMAX1-RV32-NEXT: addi a1, zero, 56 -; LMULMAX1-RV32-NEXT: vsrl.vx v25, v25, a1 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vsrl.vx v8, v8, a1 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctpop_v2i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 1 +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX1-RV64-NEXT: lui a1, 21845 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 1365 ; LMULMAX1-RV64-NEXT: slli a1, a1, 12 @@ -403,8 +403,8 @@ define void @ctpop_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV64-NEXT: addi a1, a1, 1365 ; LMULMAX1-RV64-NEXT: slli a1, a1, 12 ; LMULMAX1-RV64-NEXT: addi a1, a1, 1365 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v26 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1 +; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v9 ; LMULMAX1-RV64-NEXT: lui a1, 13107 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 819 ; LMULMAX1-RV64-NEXT: slli a1, a1, 12 @@ -413,12 +413,12 @@ define void @ctpop_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV64-NEXT: addi a1, a1, 819 ; LMULMAX1-RV64-NEXT: slli a1, a1, 12 ; LMULMAX1-RV64-NEXT: addi a1, a1, 819 -; LMULMAX1-RV64-NEXT: vand.vx v26, v25, a1 -; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v26, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v25, 4 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v26 +; LMULMAX1-RV64-NEXT: vand.vx v9, v8, a1 +; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v9, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v8, 4 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v9 ; LMULMAX1-RV64-NEXT: lui a1, 3855 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 241 ; LMULMAX1-RV64-NEXT: slli a1, a1, 12 @@ -427,17 +427,17 @@ define void @ctpop_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV64-NEXT: addi a1, a1, 241 ; LMULMAX1-RV64-NEXT: slli a1, a1, 12 ; LMULMAX1-RV64-NEXT: addi a1, a1, -241 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a1 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 ; LMULMAX1-RV64-NEXT: lui a1, 4112 ; LMULMAX1-RV64-NEXT: addiw a1, a1, 257 ; LMULMAX1-RV64-NEXT: slli a1, a1, 16 ; LMULMAX1-RV64-NEXT: addi a1, a1, 257 ; LMULMAX1-RV64-NEXT: slli a1, a1, 16 ; LMULMAX1-RV64-NEXT: addi a1, a1, 257 -; LMULMAX1-RV64-NEXT: vmul.vx v25, v25, a1 +; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a1 ; LMULMAX1-RV64-NEXT: addi a1, zero, 56 -; LMULMAX1-RV64-NEXT: vsrl.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vsrl.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -452,52 +452,52 @@ define void @ctpop_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a1, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vsrl.vi v28, v26, 1 +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX2-NEXT: addi a1, zero, 85 -; LMULMAX2-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-NEXT: vsub.vv v26, v26, v28 +; LMULMAX2-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-NEXT: vsub.vv v8, v8, v10 ; LMULMAX2-NEXT: addi a1, zero, 51 -; LMULMAX2-NEXT: vand.vx v28, v26, a1 -; LMULMAX2-NEXT: vsrl.vi v26, v26, 2 -; LMULMAX2-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-NEXT: vadd.vv v26, v28, v26 -; LMULMAX2-NEXT: vsrl.vi v28, v26, 4 -; LMULMAX2-NEXT: vadd.vv v26, v26, v28 -; LMULMAX2-NEXT: vand.vi v26, v26, 15 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vand.vx v10, v8, a1 +; LMULMAX2-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX2-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-NEXT: vadd.vv v8, v10, v8 +; LMULMAX2-NEXT: vsrl.vi v10, v8, 4 +; LMULMAX2-NEXT: vadd.vv v8, v8, v10 +; LMULMAX2-NEXT: vand.vi v8, v8, 15 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: ctpop_v32i8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vle8.v v25, (a1) -; LMULMAX1-NEXT: vle8.v v26, (a0) -; LMULMAX1-NEXT: vsrl.vi v27, v25, 1 +; LMULMAX1-NEXT: vle8.v v8, (a1) +; LMULMAX1-NEXT: vle8.v v9, (a0) +; LMULMAX1-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-NEXT: addi a2, zero, 85 -; LMULMAX1-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-NEXT: vsub.vv v25, v25, v27 +; LMULMAX1-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-NEXT: vsub.vv v8, v8, v10 ; LMULMAX1-NEXT: addi a3, zero, 51 -; LMULMAX1-NEXT: vand.vx v27, v25, a3 -; LMULMAX1-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX1-NEXT: vand.vx v25, v25, a3 -; LMULMAX1-NEXT: vadd.vv v25, v27, v25 -; LMULMAX1-NEXT: vsrl.vi v27, v25, 4 -; LMULMAX1-NEXT: vadd.vv v25, v25, v27 -; LMULMAX1-NEXT: vand.vi v25, v25, 15 -; LMULMAX1-NEXT: vsrl.vi v27, v26, 1 -; LMULMAX1-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-NEXT: vsub.vv v26, v26, v27 -; LMULMAX1-NEXT: vand.vx v27, v26, a3 -; LMULMAX1-NEXT: vsrl.vi v26, v26, 2 -; LMULMAX1-NEXT: vand.vx v26, v26, a3 -; LMULMAX1-NEXT: vadd.vv v26, v27, v26 -; LMULMAX1-NEXT: vsrl.vi v27, v26, 4 -; LMULMAX1-NEXT: vadd.vv v26, v26, v27 -; LMULMAX1-NEXT: vand.vi v26, v26, 15 -; LMULMAX1-NEXT: vse8.v v26, (a0) -; LMULMAX1-NEXT: vse8.v v25, (a1) +; LMULMAX1-NEXT: vand.vx v10, v8, a3 +; LMULMAX1-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX1-NEXT: vand.vx v8, v8, a3 +; LMULMAX1-NEXT: vadd.vv v8, v10, v8 +; LMULMAX1-NEXT: vsrl.vi v10, v8, 4 +; LMULMAX1-NEXT: vadd.vv v8, v8, v10 +; LMULMAX1-NEXT: vand.vi v8, v8, 15 +; LMULMAX1-NEXT: vsrl.vi v10, v9, 1 +; LMULMAX1-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-NEXT: vsub.vv v9, v9, v10 +; LMULMAX1-NEXT: vand.vx v10, v9, a3 +; LMULMAX1-NEXT: vsrl.vi v9, v9, 2 +; LMULMAX1-NEXT: vand.vx v9, v9, a3 +; LMULMAX1-NEXT: vadd.vv v9, v10, v9 +; LMULMAX1-NEXT: vsrl.vi v10, v9, 4 +; LMULMAX1-NEXT: vadd.vv v9, v9, v10 +; LMULMAX1-NEXT: vand.vi v9, v9, 15 +; LMULMAX1-NEXT: vse8.v v9, (a0) +; LMULMAX1-NEXT: vse8.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -511,135 +511,135 @@ define void @ctpop_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-LABEL: ctpop_v16i16: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle16.v v26, (a0) -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 1 +; LMULMAX2-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX2-RV32-NEXT: lui a1, 5 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1365 -; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV32-NEXT: vsub.vv v26, v26, v28 +; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: lui a1, 3 ; LMULMAX2-RV32-NEXT: addi a1, a1, 819 -; LMULMAX2-RV32-NEXT: vand.vx v28, v26, a1 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v26, 2 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v28, v26 -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 4 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28 +; LMULMAX2-RV32-NEXT: vand.vx v10, v8, a1 +; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v10, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: lui a1, 1 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV32-NEXT: addi a1, zero, 257 -; LMULMAX2-RV32-NEXT: vmul.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v26, 8 -; LMULMAX2-RV32-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV32-NEXT: vmul.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 8 +; LMULMAX2-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctpop_v16i16: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle16.v v26, (a0) -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 1 +; LMULMAX2-RV64-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX2-RV64-NEXT: lui a1, 5 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365 -; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV64-NEXT: vsub.vv v26, v26, v28 +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: lui a1, 3 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 819 -; LMULMAX2-RV64-NEXT: vand.vx v28, v26, a1 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v26, 2 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vadd.vv v26, v28, v26 -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 4 -; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28 +; LMULMAX2-RV64-NEXT: vand.vx v10, v8, a1 +; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v10, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: lui a1, 1 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -241 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV64-NEXT: addi a1, zero, 257 -; LMULMAX2-RV64-NEXT: vmul.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v26, 8 -; LMULMAX2-RV64-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV64-NEXT: vmul.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 8 +; LMULMAX2-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctpop_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v25, (a1) -; LMULMAX1-RV32-NEXT: vle16.v v26, (a0) -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 1 +; LMULMAX1-RV32-NEXT: vle16.v v8, (a1) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a0) +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV32-NEXT: lui a2, 5 ; LMULMAX1-RV32-NEXT: addi a2, a2, 1365 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v27 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: lui a3, 3 ; LMULMAX1-RV32-NEXT: addi a3, a3, 819 -; LMULMAX1-RV32-NEXT: vand.vx v27, v25, a3 -; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a3 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v27, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 4 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v27 +; LMULMAX1-RV32-NEXT: vand.vx v10, v8, a3 +; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a3 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v10, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: lui a4, 1 ; LMULMAX1-RV32-NEXT: addi a4, a4, -241 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a4 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV32-NEXT: addi a5, zero, 257 -; LMULMAX1-RV32-NEXT: vmul.vx v25, v25, a5 -; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 8 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 1 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vand.vx v27, v26, a3 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v26, 2 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a3 -; LMULMAX1-RV32-NEXT: vadd.vv v26, v27, v26 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 4 -; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a4 -; LMULMAX1-RV32-NEXT: vmul.vx v26, v26, a5 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v26, 8 -; LMULMAX1-RV32-NEXT: vse16.v v26, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v25, (a1) +; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a5 +; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 8 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vand.vx v10, v9, a3 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 2 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a3 +; LMULMAX1-RV32-NEXT: vadd.vv v9, v10, v9 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4 +; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4 +; LMULMAX1-RV32-NEXT: vmul.vx v9, v9, a5 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 8 +; LMULMAX1-RV32-NEXT: vse16.v v9, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v8, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctpop_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v25, (a1) -; LMULMAX1-RV64-NEXT: vle16.v v26, (a0) -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 1 +; LMULMAX1-RV64-NEXT: vle16.v v8, (a1) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a0) +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV64-NEXT: lui a2, 5 ; LMULMAX1-RV64-NEXT: addiw a2, a2, 1365 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v27 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: lui a3, 3 ; LMULMAX1-RV64-NEXT: addiw a3, a3, 819 -; LMULMAX1-RV64-NEXT: vand.vx v27, v25, a3 -; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a3 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v27, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 4 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v27 +; LMULMAX1-RV64-NEXT: vand.vx v10, v8, a3 +; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: lui a4, 1 ; LMULMAX1-RV64-NEXT: addiw a4, a4, -241 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a4 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV64-NEXT: addi a5, zero, 257 -; LMULMAX1-RV64-NEXT: vmul.vx v25, v25, a5 -; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 8 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 1 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV64-NEXT: vsub.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vand.vx v27, v26, a3 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v26, 2 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a3 -; LMULMAX1-RV64-NEXT: vadd.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 4 -; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a4 -; LMULMAX1-RV64-NEXT: vmul.vx v26, v26, a5 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v26, 8 -; LMULMAX1-RV64-NEXT: vse16.v v26, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v25, (a1) +; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a5 +; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 8 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vand.vx v10, v9, a3 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 2 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3 +; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 +; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4 +; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a5 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 8 +; LMULMAX1-RV64-NEXT: vse16.v v9, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v8, (a1) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -653,139 +653,139 @@ define void @ctpop_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-LABEL: ctpop_v8i32: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle32.v v26, (a0) -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 1 +; LMULMAX2-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX2-RV32-NEXT: lui a1, 349525 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1365 -; LMULMAX2-RV32-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV32-NEXT: vsub.vv v26, v26, v28 +; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: lui a1, 209715 ; LMULMAX2-RV32-NEXT: addi a1, a1, 819 -; LMULMAX2-RV32-NEXT: vand.vx v28, v26, a1 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v26, 2 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v28, v26 -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 4 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28 +; LMULMAX2-RV32-NEXT: vand.vx v10, v8, a1 +; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v10, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: lui a1, 61681 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241 -; LMULMAX2-RV32-NEXT: vand.vx v26, v26, a1 +; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV32-NEXT: lui a1, 4112 ; LMULMAX2-RV32-NEXT: addi a1, a1, 257 -; LMULMAX2-RV32-NEXT: vmul.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v26, 24 -; LMULMAX2-RV32-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV32-NEXT: vmul.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 24 +; LMULMAX2-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctpop_v8i32: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle32.v v26, (a0) -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 1 +; LMULMAX2-RV64-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX2-RV64-NEXT: lui a1, 349525 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365 -; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV64-NEXT: vsub.vv v26, v26, v28 +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: lui a1, 209715 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 819 -; LMULMAX2-RV64-NEXT: vand.vx v28, v26, a1 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v26, 2 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vadd.vv v26, v28, v26 -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 4 -; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28 +; LMULMAX2-RV64-NEXT: vand.vx v10, v8, a1 +; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v10, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: lui a1, 61681 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -241 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV64-NEXT: lui a1, 4112 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 257 -; LMULMAX2-RV64-NEXT: vmul.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v26, 24 -; LMULMAX2-RV64-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV64-NEXT: vmul.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 24 +; LMULMAX2-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctpop_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) -; LMULMAX1-RV32-NEXT: vle32.v v26, (a0) -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 1 +; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a0) +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV32-NEXT: lui a2, 349525 ; LMULMAX1-RV32-NEXT: addi a2, a2, 1365 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v27 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: lui a3, 209715 ; LMULMAX1-RV32-NEXT: addi a3, a3, 819 -; LMULMAX1-RV32-NEXT: vand.vx v27, v25, a3 -; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a3 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v27, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 4 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v27 +; LMULMAX1-RV32-NEXT: vand.vx v10, v8, a3 +; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a3 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v10, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: lui a4, 61681 ; LMULMAX1-RV32-NEXT: addi a4, a4, -241 -; LMULMAX1-RV32-NEXT: vand.vx v25, v25, a4 +; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV32-NEXT: lui a5, 4112 ; LMULMAX1-RV32-NEXT: addi a5, a5, 257 -; LMULMAX1-RV32-NEXT: vmul.vx v25, v25, a5 -; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 24 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 1 -; LMULMAX1-RV32-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vand.vx v27, v26, a3 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v26, 2 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a3 -; LMULMAX1-RV32-NEXT: vadd.vv v26, v27, v26 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 4 -; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vand.vx v26, v26, a4 -; LMULMAX1-RV32-NEXT: vmul.vx v26, v26, a5 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v26, 24 -; LMULMAX1-RV32-NEXT: vse32.v v26, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v25, (a1) +; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a5 +; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 24 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1 +; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vand.vx v10, v9, a3 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 2 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a3 +; LMULMAX1-RV32-NEXT: vadd.vv v9, v10, v9 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4 +; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4 +; LMULMAX1-RV32-NEXT: vmul.vx v9, v9, a5 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 24 +; LMULMAX1-RV32-NEXT: vse32.v v9, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctpop_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v25, (a1) -; LMULMAX1-RV64-NEXT: vle32.v v26, (a0) -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 1 +; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a0) +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV64-NEXT: lui a2, 349525 ; LMULMAX1-RV64-NEXT: addiw a2, a2, 1365 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v27 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: lui a3, 209715 ; LMULMAX1-RV64-NEXT: addiw a3, a3, 819 -; LMULMAX1-RV64-NEXT: vand.vx v27, v25, a3 -; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a3 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v27, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 4 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v27 +; LMULMAX1-RV64-NEXT: vand.vx v10, v8, a3 +; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: lui a4, 61681 ; LMULMAX1-RV64-NEXT: addiw a4, a4, -241 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a4 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV64-NEXT: lui a5, 4112 ; LMULMAX1-RV64-NEXT: addiw a5, a5, 257 -; LMULMAX1-RV64-NEXT: vmul.vx v25, v25, a5 -; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 24 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 1 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV64-NEXT: vsub.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vand.vx v27, v26, a3 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v26, 2 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a3 -; LMULMAX1-RV64-NEXT: vadd.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 4 -; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a4 -; LMULMAX1-RV64-NEXT: vmul.vx v26, v26, a5 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v26, 24 -; LMULMAX1-RV64-NEXT: vse32.v v26, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v25, (a1) +; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a5 +; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 24 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vand.vx v10, v9, a3 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 2 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3 +; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 +; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4 +; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a5 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 24 +; LMULMAX1-RV64-NEXT: vse32.v v9, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -799,48 +799,48 @@ define void @ctpop_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-LABEL: ctpop_v4i64: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle64.v v26, (a0) -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 1 +; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX2-RV32-NEXT: lui a1, 349525 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1365 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v30, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vand.vv v28, v28, v30 -; LMULMAX2-RV32-NEXT: vsub.vv v26, v26, v28 +; LMULMAX2-RV32-NEXT: vand.vv v10, v10, v12 +; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: lui a1, 209715 ; LMULMAX2-RV32-NEXT: addi a1, a1, 819 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v28, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vand.vv v30, v26, v28 -; LMULMAX2-RV32-NEXT: vsrl.vi v26, v26, 2 -; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v28 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v30, v26 -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 4 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28 +; LMULMAX2-RV32-NEXT: vand.vv v12, v8, v10 +; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v12, v8 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: lui a1, 61681 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v28, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vand.vv v26, v26, v28 +; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: lui a1, 4112 ; LMULMAX2-RV32-NEXT: addi a1, a1, 257 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v28, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmul.vv v26, v26, v28 +; LMULMAX2-RV32-NEXT: vmul.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: addi a1, zero, 56 -; LMULMAX2-RV32-NEXT: vsrl.vx v26, v26, a1 -; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV32-NEXT: vsrl.vx v8, v8, a1 +; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: ctpop_v4i64: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle64.v v26, (a0) -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 1 +; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX2-RV64-NEXT: lui a1, 21845 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 @@ -849,8 +849,8 @@ define void @ctpop_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: addi a1, a1, 1365 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 ; LMULMAX2-RV64-NEXT: addi a1, a1, 1365 -; LMULMAX2-RV64-NEXT: vand.vx v28, v28, a1 -; LMULMAX2-RV64-NEXT: vsub.vv v26, v26, v28 +; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 +; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: lui a1, 13107 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 819 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 @@ -859,12 +859,12 @@ define void @ctpop_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: addi a1, a1, 819 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 ; LMULMAX2-RV64-NEXT: addi a1, a1, 819 -; LMULMAX2-RV64-NEXT: vand.vx v28, v26, a1 -; LMULMAX2-RV64-NEXT: vsrl.vi v26, v26, 2 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vadd.vv v26, v28, v26 -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 4 -; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28 +; LMULMAX2-RV64-NEXT: vand.vx v10, v8, a1 +; LMULMAX2-RV64-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v10, v8 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: lui a1, 3855 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 241 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 @@ -873,81 +873,81 @@ define void @ctpop_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: addi a1, a1, 241 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 ; LMULMAX2-RV64-NEXT: addi a1, a1, -241 -; LMULMAX2-RV64-NEXT: vand.vx v26, v26, a1 +; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV64-NEXT: lui a1, 4112 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 257 ; LMULMAX2-RV64-NEXT: slli a1, a1, 16 ; LMULMAX2-RV64-NEXT: addi a1, a1, 257 ; LMULMAX2-RV64-NEXT: slli a1, a1, 16 ; LMULMAX2-RV64-NEXT: addi a1, a1, 257 -; LMULMAX2-RV64-NEXT: vmul.vx v26, v26, a1 +; LMULMAX2-RV64-NEXT: vmul.vx v8, v8, a1 ; LMULMAX2-RV64-NEXT: addi a1, zero, 56 -; LMULMAX2-RV64-NEXT: vsrl.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vsrl.vx v8, v8, a1 +; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ctpop_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v25, (a1) -; LMULMAX1-RV32-NEXT: vle64.v v26, (a0) -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 1 +; LMULMAX1-RV32-NEXT: vle64.v v8, (a1) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a0) +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV32-NEXT: lui a2, 349525 ; LMULMAX1-RV32-NEXT: addi a2, a2, 1365 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v28, a2 +; LMULMAX1-RV32-NEXT: vmv.v.x v11, a2 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vand.vv v27, v27, v28 -; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v27 +; LMULMAX1-RV32-NEXT: vand.vv v10, v10, v11 +; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: lui a2, 209715 ; LMULMAX1-RV32-NEXT: addi a2, a2, 819 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v27, a2 +; LMULMAX1-RV32-NEXT: vmv.v.x v10, a2 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vand.vv v29, v25, v27 -; LMULMAX1-RV32-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v29, v25 -; LMULMAX1-RV32-NEXT: vsrl.vi v29, v25, 4 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v29 +; LMULMAX1-RV32-NEXT: vand.vv v12, v8, v10 +; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v12, v8 +; LMULMAX1-RV32-NEXT: vsrl.vi v12, v8, 4 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v12 ; LMULMAX1-RV32-NEXT: lui a2, 61681 ; LMULMAX1-RV32-NEXT: addi a2, a2, -241 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v29, a2 +; LMULMAX1-RV32-NEXT: vmv.v.x v12, a2 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v29 +; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v12 ; LMULMAX1-RV32-NEXT: lui a2, 4112 ; LMULMAX1-RV32-NEXT: addi a2, a2, 257 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v30, a2 +; LMULMAX1-RV32-NEXT: vmv.v.x v13, a2 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v30 +; LMULMAX1-RV32-NEXT: vmul.vv v8, v8, v13 ; LMULMAX1-RV32-NEXT: addi a2, zero, 56 -; LMULMAX1-RV32-NEXT: vsrl.vx v25, v25, a2 -; LMULMAX1-RV32-NEXT: vsrl.vi v31, v26, 1 -; LMULMAX1-RV32-NEXT: vand.vv v28, v31, v28 -; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v28 -; LMULMAX1-RV32-NEXT: vand.vv v28, v26, v27 -; LMULMAX1-RV32-NEXT: vsrl.vi v26, v26, 2 -; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vadd.vv v26, v28, v26 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v26, 4 -; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v29 -; LMULMAX1-RV32-NEXT: vmul.vv v26, v26, v30 -; LMULMAX1-RV32-NEXT: vsrl.vx v26, v26, a2 -; LMULMAX1-RV32-NEXT: vse64.v v26, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v25, (a1) +; LMULMAX1-RV32-NEXT: vsrl.vx v8, v8, a2 +; LMULMAX1-RV32-NEXT: vsrl.vi v14, v9, 1 +; LMULMAX1-RV32-NEXT: vand.vv v11, v14, v11 +; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v11 +; LMULMAX1-RV32-NEXT: vand.vv v11, v9, v10 +; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 2 +; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vadd.vv v9, v11, v9 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4 +; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v12 +; LMULMAX1-RV32-NEXT: vmul.vv v9, v9, v13 +; LMULMAX1-RV32-NEXT: vsrl.vx v9, v9, a2 +; LMULMAX1-RV32-NEXT: vse64.v v9, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v8, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ctpop_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a6, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v25, (a6) -; LMULMAX1-RV64-NEXT: vle64.v v26, (a0) -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 1 +; LMULMAX1-RV64-NEXT: vle64.v v8, (a6) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a0) +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV64-NEXT: lui a2, 21845 ; LMULMAX1-RV64-NEXT: addiw a2, a2, 1365 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12 @@ -956,8 +956,8 @@ define void @ctpop_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: addi a2, a2, 1365 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: addi a2, a2, 1365 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v27 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: lui a3, 13107 ; LMULMAX1-RV64-NEXT: addiw a3, a3, 819 ; LMULMAX1-RV64-NEXT: slli a3, a3, 12 @@ -966,12 +966,12 @@ define void @ctpop_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: addi a3, a3, 819 ; LMULMAX1-RV64-NEXT: slli a3, a3, 12 ; LMULMAX1-RV64-NEXT: addi a3, a3, 819 -; LMULMAX1-RV64-NEXT: vand.vx v27, v25, a3 -; LMULMAX1-RV64-NEXT: vsrl.vi v25, v25, 2 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a3 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v27, v25 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v25, 4 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v27 +; LMULMAX1-RV64-NEXT: vand.vx v10, v8, a3 +; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: lui a4, 3855 ; LMULMAX1-RV64-NEXT: addiw a4, a4, 241 ; LMULMAX1-RV64-NEXT: slli a4, a4, 12 @@ -980,30 +980,30 @@ define void @ctpop_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: addi a4, a4, 241 ; LMULMAX1-RV64-NEXT: slli a4, a4, 12 ; LMULMAX1-RV64-NEXT: addi a4, a4, -241 -; LMULMAX1-RV64-NEXT: vand.vx v25, v25, a4 +; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV64-NEXT: lui a5, 4112 ; LMULMAX1-RV64-NEXT: addiw a5, a5, 257 ; LMULMAX1-RV64-NEXT: slli a5, a5, 16 ; LMULMAX1-RV64-NEXT: addi a5, a5, 257 ; LMULMAX1-RV64-NEXT: slli a5, a5, 16 ; LMULMAX1-RV64-NEXT: addi a5, a5, 257 -; LMULMAX1-RV64-NEXT: vmul.vx v25, v25, a5 +; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a5 ; LMULMAX1-RV64-NEXT: addi a1, zero, 56 -; LMULMAX1-RV64-NEXT: vsrl.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 1 -; LMULMAX1-RV64-NEXT: vand.vx v27, v27, a2 -; LMULMAX1-RV64-NEXT: vsub.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vand.vx v27, v26, a3 -; LMULMAX1-RV64-NEXT: vsrl.vi v26, v26, 2 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a3 -; LMULMAX1-RV64-NEXT: vadd.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsrl.vi v27, v26, 4 -; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vand.vx v26, v26, a4 -; LMULMAX1-RV64-NEXT: vmul.vx v26, v26, a5 -; LMULMAX1-RV64-NEXT: vsrl.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v25, (a6) +; LMULMAX1-RV64-NEXT: vsrl.vx v8, v8, a1 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1 +; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 +; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vand.vx v10, v9, a3 +; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 2 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3 +; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 +; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4 +; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a5 +; LMULMAX1-RV64-NEXT: vsrl.vx v9, v9, a1 +; LMULMAX1-RV64-NEXT: vse64.v v9, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v8, (a6) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll index 15490a845bfc2c6a1a51d33125d0af2988c143c4..7d26d86d7386cba29a7e273b1bda3fa2bd7e1698 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll @@ -10,8 +10,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: addi sp, sp, -32 ; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle8.v v25, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vle8.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -38,8 +38,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a5, a5, 24 ; LMULMAX2-RV32-NEXT: sb a5, 16(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 15 -; LMULMAX2-RV32-NEXT: vmv.x.s a5, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 15 +; LMULMAX2-RV32-NEXT: vmv.x.s a5, v9 ; LMULMAX2-RV32-NEXT: ori a5, a5, 256 ; LMULMAX2-RV32-NEXT: addi a1, a5, -1 ; LMULMAX2-RV32-NEXT: not a5, a5 @@ -57,8 +57,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 31(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 14 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 14 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -76,8 +76,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 30(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 13 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 13 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -95,8 +95,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 29(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 12 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 12 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -114,8 +114,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 28(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 11 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 11 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -133,8 +133,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 27(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 10 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 10 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -152,8 +152,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 26(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 9 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 9 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -171,8 +171,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 25(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 8 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 8 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -190,8 +190,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 24(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -209,8 +209,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 23(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -228,8 +228,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 22(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -247,8 +247,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 21(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -266,8 +266,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 20(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -285,8 +285,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 19(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -304,8 +304,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 18(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -325,8 +325,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV32-NEXT: sb a1, 17(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 16 -; LMULMAX2-RV32-NEXT: vle8.v v25, (a1) -; LMULMAX2-RV32-NEXT: vse8.v v25, (a0) +; LMULMAX2-RV32-NEXT: vle8.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse8.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 ; LMULMAX2-RV32-NEXT: ret ; @@ -335,10 +335,10 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -32 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX2-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 15 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 15 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -386,8 +386,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a5, a5, a4 ; LMULMAX2-RV64-NEXT: srli a5, a5, 56 ; LMULMAX2-RV64-NEXT: sb a5, 31(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 14 -; LMULMAX2-RV64-NEXT: vmv.x.s a5, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 14 +; LMULMAX2-RV64-NEXT: vmv.x.s a5, v9 ; LMULMAX2-RV64-NEXT: ori a5, a5, 256 ; LMULMAX2-RV64-NEXT: addi a1, a5, -1 ; LMULMAX2-RV64-NEXT: not a5, a5 @@ -405,8 +405,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 30(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 13 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 13 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a5, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -424,8 +424,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 29(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 12 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 12 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a5, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -443,8 +443,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 11 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 11 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a5, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -462,8 +462,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 27(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 10 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 10 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a5, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -481,8 +481,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 26(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 9 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 9 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a5, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -500,8 +500,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 25(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 8 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 8 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a5, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -519,8 +519,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a5, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -538,8 +538,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 23(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a5, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -557,8 +557,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 22(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a5, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -576,8 +576,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 21(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a5, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -595,8 +595,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 20(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a5, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -614,8 +614,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 19(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a5, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -633,8 +633,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 18(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a5, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -652,7 +652,7 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a4 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 17(sp) -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a5, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -672,8 +672,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX2-RV64-NEXT: sb a1, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle8.v v25, (a1) -; LMULMAX2-RV64-NEXT: vse8.v v25, (a0) +; LMULMAX2-RV64-NEXT: vle8.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse8.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 ; LMULMAX2-RV64-NEXT: ret ; @@ -682,8 +682,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: addi sp, sp, -32 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -710,8 +710,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a5, a5, 24 ; LMULMAX1-RV32-NEXT: sb a5, 16(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 15 -; LMULMAX1-RV32-NEXT: vmv.x.s a5, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 15 +; LMULMAX1-RV32-NEXT: vmv.x.s a5, v9 ; LMULMAX1-RV32-NEXT: ori a5, a5, 256 ; LMULMAX1-RV32-NEXT: addi a1, a5, -1 ; LMULMAX1-RV32-NEXT: not a5, a5 @@ -729,8 +729,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 31(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 14 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 14 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -748,8 +748,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 30(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 13 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 13 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -767,8 +767,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 29(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 12 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 12 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -786,8 +786,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 11 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 11 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -805,8 +805,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 27(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 10 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 10 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -824,8 +824,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 26(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 9 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 9 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -843,8 +843,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 25(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 8 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 8 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -862,8 +862,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -881,8 +881,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 23(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -900,8 +900,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 22(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -919,8 +919,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 21(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -938,8 +938,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 20(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -957,8 +957,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 19(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -976,8 +976,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a4 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 18(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -997,8 +997,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV32-NEXT: sb a1, 17(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle8.v v25, (a1) -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a1) +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 ; LMULMAX1-RV32-NEXT: ret ; @@ -1007,10 +1007,10 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: addi sp, sp, -32 ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 15 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 15 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1058,8 +1058,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a5, a5, a4 ; LMULMAX1-RV64-NEXT: srli a5, a5, 56 ; LMULMAX1-RV64-NEXT: sb a5, 31(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 14 -; LMULMAX1-RV64-NEXT: vmv.x.s a5, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 14 +; LMULMAX1-RV64-NEXT: vmv.x.s a5, v9 ; LMULMAX1-RV64-NEXT: ori a5, a5, 256 ; LMULMAX1-RV64-NEXT: addi a1, a5, -1 ; LMULMAX1-RV64-NEXT: not a5, a5 @@ -1077,8 +1077,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a4 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 30(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 13 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 13 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a5, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1096,8 +1096,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a4 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 29(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 12 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 12 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a5, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1115,8 +1115,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a4 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 11 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 11 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a5, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1134,8 +1134,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a4 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 27(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 10 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 10 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a5, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1153,8 +1153,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a4 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 26(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 9 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 9 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a5, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1172,8 +1172,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a4 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 25(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 8 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 8 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a5, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1191,8 +1191,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a4 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a5, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1210,8 +1210,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a4 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 23(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a5, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1229,8 +1229,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a4 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 22(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a5, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1248,8 +1248,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a4 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 21(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a5, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1267,8 +1267,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a4 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 20(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a5, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1286,8 +1286,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a4 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 19(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a5, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1305,8 +1305,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a4 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 18(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a5, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1324,7 +1324,7 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a4 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 17(sp) -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a5, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1344,8 +1344,8 @@ define void @cttz_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; LMULMAX1-RV64-NEXT: sb a1, 16(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, sp, 16 -; LMULMAX1-RV64-NEXT: vle8.v v25, (a1) -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a1) +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x @@ -1362,8 +1362,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: addi sp, sp, -32 ; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle16.v v25, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a2, v25 +; LMULMAX2-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX2-RV32-NEXT: lui a6, 16 ; LMULMAX2-RV32-NEXT: or a2, a2, a6 ; LMULMAX2-RV32-NEXT: addi a3, a2, -1 @@ -1391,8 +1391,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 16(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -1410,8 +1410,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 30(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -1429,8 +1429,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 28(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -1448,8 +1448,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 26(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -1467,8 +1467,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 24(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -1486,8 +1486,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 22(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -1505,8 +1505,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 20(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -1526,8 +1526,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV32-NEXT: sh a1, 18(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 16 -; LMULMAX2-RV32-NEXT: vle16.v v25, (a1) -; LMULMAX2-RV32-NEXT: vse16.v v25, (a0) +; LMULMAX2-RV32-NEXT: vle16.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 ; LMULMAX2-RV32-NEXT: ret ; @@ -1536,10 +1536,10 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -32 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX2-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX2-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX2-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX2-RV64-NEXT: lui a6, 16 ; LMULMAX2-RV64-NEXT: or a2, a2, a6 ; LMULMAX2-RV64-NEXT: addi a3, a2, -1 @@ -1588,8 +1588,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 30(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -1607,8 +1607,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -1626,8 +1626,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 26(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -1645,8 +1645,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -1664,8 +1664,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 22(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -1683,8 +1683,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 20(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -1702,7 +1702,7 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 18(sp) -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -1722,8 +1722,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX2-RV64-NEXT: sh a1, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle16.v v25, (a1) -; LMULMAX2-RV64-NEXT: vse16.v v25, (a0) +; LMULMAX2-RV64-NEXT: vle16.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 ; LMULMAX2-RV64-NEXT: ret ; @@ -1732,8 +1732,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: addi sp, sp, -32 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV32-NEXT: lui a6, 16 ; LMULMAX1-RV32-NEXT: or a2, a2, a6 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 @@ -1761,8 +1761,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sh a1, 16(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: or a1, a1, a6 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -1780,8 +1780,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sh a1, 30(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: or a1, a1, a6 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -1799,8 +1799,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sh a1, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: or a1, a1, a6 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -1818,8 +1818,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sh a1, 26(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: or a1, a1, a6 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -1837,8 +1837,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sh a1, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: or a1, a1, a6 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -1856,8 +1856,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sh a1, 22(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: or a1, a1, a6 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -1875,8 +1875,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sh a1, 20(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: or a1, a1, a6 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -1896,8 +1896,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV32-NEXT: sh a1, 18(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle16.v v25, (a1) -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a1) +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 ; LMULMAX1-RV32-NEXT: ret ; @@ -1906,10 +1906,10 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: addi sp, sp, -32 ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: lui a6, 16 ; LMULMAX1-RV64-NEXT: or a2, a2, a6 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 @@ -1958,8 +1958,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sh a1, 30(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: or a1, a1, a6 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1977,8 +1977,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sh a1, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: or a1, a1, a6 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -1996,8 +1996,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sh a1, 26(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: or a1, a1, a6 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -2015,8 +2015,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sh a1, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: or a1, a1, a6 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -2034,8 +2034,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sh a1, 22(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: or a1, a1, a6 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -2053,8 +2053,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sh a1, 20(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: or a1, a1, a6 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -2072,7 +2072,7 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sh a1, 18(sp) -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: or a1, a1, a6 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -2092,8 +2092,8 @@ define void @cttz_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; LMULMAX1-RV64-NEXT: sh a1, 16(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, sp, 16 -; LMULMAX1-RV64-NEXT: vle16.v v25, (a1) -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a1) +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x @@ -2110,8 +2110,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-NEXT: addi sp, sp, -32 ; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle32.v v25, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a2, a1, a2 @@ -2137,8 +2137,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-NEXT: srli a4, a4, 24 ; LMULMAX2-RV32-NEXT: sw a4, 16(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a4, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a4, v9 ; LMULMAX2-RV32-NEXT: addi a1, a4, -1 ; LMULMAX2-RV32-NEXT: not a4, a4 ; LMULMAX2-RV32-NEXT: and a1, a4, a1 @@ -2155,8 +2155,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 28(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: addi a4, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a1, a1, a4 @@ -2173,8 +2173,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 24(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: addi a4, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a1, a1, a4 @@ -2193,8 +2193,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV32-NEXT: sw a1, 20(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 16 -; LMULMAX2-RV32-NEXT: vle32.v v25, (a1) -; LMULMAX2-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX2-RV32-NEXT: vle32.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 ; LMULMAX2-RV32-NEXT: ret ; @@ -2203,10 +2203,10 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -32 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX2-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX2-RV64-NEXT: addi a1, zero, 1 ; LMULMAX2-RV64-NEXT: slli a6, a1, 32 ; LMULMAX2-RV64-NEXT: or a2, a2, a6 @@ -2256,8 +2256,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sw a1, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -2275,8 +2275,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sw a1, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -2294,7 +2294,7 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sw a1, 20(sp) -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -2314,8 +2314,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX2-RV64-NEXT: sw a1, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle32.v v25, (a1) -; LMULMAX2-RV64-NEXT: vse32.v v25, (a0) +; LMULMAX2-RV64-NEXT: vle32.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 32 ; LMULMAX2-RV64-NEXT: ret ; @@ -2324,8 +2324,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV32-NEXT: addi sp, sp, -32 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a2, a1, a2 @@ -2351,8 +2351,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV32-NEXT: srli a4, a4, 24 ; LMULMAX1-RV32-NEXT: sw a4, 16(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a4, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a4, v9 ; LMULMAX1-RV32-NEXT: addi a1, a4, -1 ; LMULMAX1-RV32-NEXT: not a4, a4 ; LMULMAX1-RV32-NEXT: and a1, a4, a1 @@ -2369,8 +2369,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: addi a4, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a1, a1, a4 @@ -2387,8 +2387,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: addi a4, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a1, a1, a4 @@ -2407,8 +2407,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV32-NEXT: sw a1, 20(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 ; LMULMAX1-RV32-NEXT: ret ; @@ -2417,10 +2417,10 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV64-NEXT: addi sp, sp, -32 ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: addi a1, zero, 1 ; LMULMAX1-RV64-NEXT: slli a6, a1, 32 ; LMULMAX1-RV64-NEXT: or a2, a2, a6 @@ -2470,8 +2470,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sw a1, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: or a1, a1, a6 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -2489,8 +2489,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sw a1, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: or a1, a1, a6 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -2508,7 +2508,7 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sw a1, 20(sp) -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: or a1, a1, a6 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -2528,8 +2528,8 @@ define void @cttz_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; LMULMAX1-RV64-NEXT: sw a1, 16(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, sp, 16 -; LMULMAX1-RV64-NEXT: vle32.v v25, (a1) -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi sp, sp, 32 ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x @@ -2546,7 +2546,7 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV32-NEXT: addi sp, sp, -32 ; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32-NEXT: sw zero, 28(sp) ; LMULMAX2-RV32-NEXT: sw zero, 20(sp) ; LMULMAX2-RV32-NEXT: addi a6, zero, 32 @@ -2557,13 +2557,13 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV32-NEXT: lui a1, 61681 ; LMULMAX2-RV32-NEXT: addi a7, a1, -241 ; LMULMAX2-RV32-NEXT: lui a2, 4112 -; LMULMAX2-RV32-NEXT: vmv.x.s a5, v25 +; LMULMAX2-RV32-NEXT: vmv.x.s a5, v8 ; LMULMAX2-RV32-NEXT: addi a2, a2, 257 ; LMULMAX2-RV32-NEXT: bnez a5, .LBB3_2 ; LMULMAX2-RV32-NEXT: # %bb.1: ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vsrl.vx v26, v25, a6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vsrl.vx v9, v8, a6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a1, a1, a5 @@ -2600,12 +2600,12 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV32-NEXT: .LBB3_3: ; LMULMAX2-RV32-NEXT: sw a5, 16(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a5, v25 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a5, v8 ; LMULMAX2-RV32-NEXT: bnez a5, .LBB3_5 ; LMULMAX2-RV32-NEXT: # %bb.4: -; LMULMAX2-RV32-NEXT: vsrl.vx v25, v25, a6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV32-NEXT: vsrl.vx v8, v8, a6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a1, a1, a5 @@ -2643,19 +2643,19 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV32-NEXT: sw a1, 24(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 16 -; LMULMAX2-RV32-NEXT: vle32.v v25, (a1) +; LMULMAX2-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 32 ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: cttz_v2i64: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 ; LMULMAX2-RV64-NEXT: and a1, a1, a2 @@ -2702,8 +2702,8 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV64-NEXT: vmv.v.x v26, a1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX2-RV64-NEXT: vmv.v.x v9, a1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: addi a3, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 ; LMULMAX2-RV64-NEXT: and a1, a1, a3 @@ -2720,8 +2720,8 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1 -; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vmv.s.x v9, a1 +; LMULMAX2-RV64-NEXT: vse64.v v9, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: cttz_v2i64: @@ -2729,7 +2729,7 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV32-NEXT: addi sp, sp, -32 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: sw zero, 28(sp) ; LMULMAX1-RV32-NEXT: sw zero, 20(sp) ; LMULMAX1-RV32-NEXT: addi a6, zero, 32 @@ -2740,13 +2740,13 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV32-NEXT: lui a1, 61681 ; LMULMAX1-RV32-NEXT: addi a7, a1, -241 ; LMULMAX1-RV32-NEXT: lui a2, 4112 -; LMULMAX1-RV32-NEXT: vmv.x.s a5, v25 +; LMULMAX1-RV32-NEXT: vmv.x.s a5, v8 ; LMULMAX1-RV32-NEXT: addi a2, a2, 257 ; LMULMAX1-RV32-NEXT: bnez a5, .LBB3_2 ; LMULMAX1-RV32-NEXT: # %bb.1: ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vsrl.vx v9, v8, a6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a1, a1, a5 @@ -2783,12 +2783,12 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV32-NEXT: .LBB3_3: ; LMULMAX1-RV32-NEXT: sw a5, 16(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a5, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a5, v8 ; LMULMAX1-RV32-NEXT: bnez a5, .LBB3_5 ; LMULMAX1-RV32-NEXT: # %bb.4: -; LMULMAX1-RV32-NEXT: vsrl.vx v25, v25, a6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vsrl.vx v8, v8, a6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: addi a5, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a1, a1, a5 @@ -2826,19 +2826,19 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV32-NEXT: sw a1, 24(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 32 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: cttz_v2i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 ; LMULMAX1-RV64-NEXT: and a1, a1, a2 @@ -2885,8 +2885,8 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.x v26, a1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vmv.v.x v9, a1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: addi a3, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 ; LMULMAX1-RV64-NEXT: and a1, a1, a3 @@ -2903,8 +2903,8 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 -; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX1-RV64-NEXT: vmv.s.x v9, a1 +; LMULMAX1-RV64-NEXT: vse64.v v9, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -2928,8 +2928,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: andi sp, sp, -32 ; LMULMAX2-RV32-NEXT: addi a6, zero, 32 ; LMULMAX2-RV32-NEXT: vsetvli zero, a6, e8, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle8.v v26, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX2-RV32-NEXT: vle8.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX2-RV32-NEXT: ori a2, a2, 256 ; LMULMAX2-RV32-NEXT: addi a3, a2, -1 ; LMULMAX2-RV32-NEXT: not a2, a2 @@ -2956,8 +2956,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 32(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, m2, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 31 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 31 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -2975,8 +2975,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 63(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 30 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 30 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -2994,8 +2994,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 62(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 29 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 29 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3013,8 +3013,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 61(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 28 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 28 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3032,8 +3032,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 60(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 27 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 27 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3051,8 +3051,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 59(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 26 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 26 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3070,8 +3070,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 58(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 25 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 25 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3089,8 +3089,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 57(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 24 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 24 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3108,8 +3108,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 56(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 23 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 23 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3127,8 +3127,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 55(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 22 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 22 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3146,8 +3146,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 54(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 21 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 21 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3165,8 +3165,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 53(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 20 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 20 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3184,8 +3184,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 52(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 19 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 19 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3203,8 +3203,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 51(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 18 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 18 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3222,8 +3222,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 50(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 17 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 17 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3241,8 +3241,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 49(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 16 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 16 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3260,8 +3260,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 48(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 15 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 15 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3279,8 +3279,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 47(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 14 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 14 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3298,8 +3298,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 46(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 13 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 13 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3317,8 +3317,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 45(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 12 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 12 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3336,8 +3336,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 44(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 11 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 11 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3355,8 +3355,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 43(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 10 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 10 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3374,8 +3374,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 42(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 9 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 9 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3393,8 +3393,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 41(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 8 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 8 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3412,8 +3412,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 40(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3431,8 +3431,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 39(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3450,8 +3450,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 38(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3469,8 +3469,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 37(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3488,8 +3488,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 36(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3507,8 +3507,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 35(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3526,8 +3526,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sb a1, 34(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: ori a1, a1, 256 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -3547,8 +3547,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV32-NEXT: sb a1, 33(sp) ; LMULMAX2-RV32-NEXT: vsetvli zero, a6, e8, m2, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 32 -; LMULMAX2-RV32-NEXT: vle8.v v26, (a1) -; LMULMAX2-RV32-NEXT: vse8.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle8.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse8.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload @@ -3561,10 +3561,10 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX2-RV64-NEXT: addi a6, zero, 32 ; LMULMAX2-RV64-NEXT: vsetvli zero, a6, e8, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle8.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, m2, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 31 -; LMULMAX2-RV64-NEXT: vmv.x.s a2, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 31 +; LMULMAX2-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX2-RV64-NEXT: ori a2, a2, 256 ; LMULMAX2-RV64-NEXT: addi a3, a2, -1 ; LMULMAX2-RV64-NEXT: not a2, a2 @@ -3612,8 +3612,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 47(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 30 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 30 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3631,8 +3631,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 46(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 29 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 29 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3650,8 +3650,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 45(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 28 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 28 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3669,8 +3669,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 44(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 27 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 27 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3688,8 +3688,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 43(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 26 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 26 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3707,8 +3707,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 42(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 25 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 25 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3726,8 +3726,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 41(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 24 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 24 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3745,8 +3745,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 40(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 23 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 23 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3764,8 +3764,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 39(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 22 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 22 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3783,8 +3783,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 38(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 21 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 21 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3802,8 +3802,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 37(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 20 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 20 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3821,8 +3821,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 36(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 19 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 19 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3840,8 +3840,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 35(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 18 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 18 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3859,8 +3859,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 34(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 17 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 17 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3878,8 +3878,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 33(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 16 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 16 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3897,8 +3897,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 32(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 15 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 15 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3916,8 +3916,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 31(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 14 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 14 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3935,8 +3935,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 30(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 13 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 13 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3954,8 +3954,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 29(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 12 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 12 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3973,8 +3973,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 11 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 11 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -3992,8 +3992,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 27(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 10 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 10 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -4011,8 +4011,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 26(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 9 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 9 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -4030,8 +4030,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 25(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 8 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 8 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -4049,8 +4049,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -4068,8 +4068,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 23(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -4087,8 +4087,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 22(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -4106,8 +4106,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 21(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -4125,8 +4125,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 20(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -4144,8 +4144,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 19(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -4163,8 +4163,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 18(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -4182,7 +4182,7 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sb a1, 17(sp) -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: ori a1, a1, 256 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -4202,8 +4202,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2-RV64-NEXT: sb a1, 16(sp) ; LMULMAX2-RV64-NEXT: vsetvli zero, a6, e8, m2, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle8.v v26, (a1) -; LMULMAX2-RV64-NEXT: vse8.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle8.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse8.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 48 ; LMULMAX2-RV64-NEXT: ret ; @@ -4213,9 +4213,9 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a6, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a6) -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vle8.v v9, (a6) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: ori a2, a2, 256 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -4242,8 +4242,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 32(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 15 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 15 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4261,8 +4261,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 47(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 14 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 14 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4280,8 +4280,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 46(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 13 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 13 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4299,8 +4299,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 45(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 12 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 12 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4318,8 +4318,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 44(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 11 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 11 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4337,8 +4337,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 43(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 10 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 10 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4356,8 +4356,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 42(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 9 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 9 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4375,8 +4375,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 41(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 8 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 8 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4394,8 +4394,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 40(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 7 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 7 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4413,8 +4413,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 39(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4432,8 +4432,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 38(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 5 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 5 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4451,8 +4451,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 37(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 4 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 4 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4470,8 +4470,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 36(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4489,8 +4489,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 35(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4508,8 +4508,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 34(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4527,7 +4527,7 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 33(sp) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4545,8 +4545,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 16(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 15 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 15 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4564,8 +4564,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 31(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 14 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 14 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4583,8 +4583,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 30(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 13 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 13 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4602,8 +4602,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 29(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 12 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 12 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4621,8 +4621,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 11 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 11 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4640,8 +4640,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 27(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 10 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 10 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4659,8 +4659,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 26(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 9 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 9 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4678,8 +4678,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 25(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 8 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 8 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4697,8 +4697,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4716,8 +4716,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 23(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4735,8 +4735,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 22(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4754,8 +4754,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 21(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4773,8 +4773,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 20(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4792,8 +4792,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 19(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4811,8 +4811,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sb a1, 18(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: ori a1, a1, 256 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 @@ -4832,11 +4832,11 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV32-NEXT: sb a1, 17(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle8.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a1, sp, 32 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a1) -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a6) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a1) +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 ; LMULMAX1-RV32-NEXT: ret ; @@ -4846,9 +4846,9 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a6, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a6) -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vle8.v v9, (a6) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: ori a2, a2, 256 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -4897,8 +4897,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 32(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 15 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 15 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -4916,8 +4916,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 47(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 14 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 14 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -4935,8 +4935,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 46(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 13 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 13 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -4954,8 +4954,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 45(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 12 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 12 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -4973,8 +4973,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 44(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 11 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 11 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -4992,8 +4992,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 43(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 10 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 10 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5011,8 +5011,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 42(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 9 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 9 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5030,8 +5030,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 41(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 8 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 8 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5049,8 +5049,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 40(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 7 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 7 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5068,8 +5068,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 39(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 6 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 6 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5087,8 +5087,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 38(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 5 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 5 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5106,8 +5106,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 37(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 4 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 4 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5125,8 +5125,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 36(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5144,8 +5144,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 35(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5163,8 +5163,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 34(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5182,8 +5182,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 33(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 15 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 15 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5201,8 +5201,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 31(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 14 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 14 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5220,8 +5220,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 30(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 13 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 13 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5239,8 +5239,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 29(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 12 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 12 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5258,8 +5258,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 11 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 11 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5277,8 +5277,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 27(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 10 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 10 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5296,8 +5296,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 26(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 9 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 9 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5315,8 +5315,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 25(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 8 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 8 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5334,8 +5334,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5353,8 +5353,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 23(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5372,8 +5372,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 22(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5391,8 +5391,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 21(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5410,8 +5410,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 20(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5429,8 +5429,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 19(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5448,8 +5448,8 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 18(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5467,7 +5467,7 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: sb a1, 17(sp) -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: ori a1, a1, 256 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 @@ -5487,11 +5487,11 @@ define void @cttz_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX1-RV64-NEXT: sb a1, 16(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, sp, 16 -; LMULMAX1-RV64-NEXT: vle8.v v25, (a1) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a1) ; LMULMAX1-RV64-NEXT: addi a1, sp, 32 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a1) -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a6) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a1) +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a6) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x @@ -5515,8 +5515,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX2-RV32-NEXT: andi sp, sp, -32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle16.v v26, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX2-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX2-RV32-NEXT: lui a6, 16 ; LMULMAX2-RV32-NEXT: or a2, a2, a6 ; LMULMAX2-RV32-NEXT: addi a3, a2, -1 @@ -5544,8 +5544,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 32(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 15 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 15 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -5563,8 +5563,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 62(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 14 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 14 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -5582,8 +5582,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 60(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 13 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 13 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -5601,8 +5601,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 58(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 12 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 12 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -5620,8 +5620,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 56(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 11 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 11 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -5639,8 +5639,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 54(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 10 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 10 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -5658,8 +5658,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 52(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 9 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 9 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -5677,8 +5677,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 50(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 8 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 8 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -5696,8 +5696,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 48(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -5715,8 +5715,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 46(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -5734,8 +5734,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 44(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -5753,8 +5753,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 42(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -5772,8 +5772,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 40(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -5791,8 +5791,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 38(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -5810,8 +5810,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a5 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sh a1, 36(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: or a1, a1, a6 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 @@ -5831,8 +5831,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV32-NEXT: sh a1, 34(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 32 -; LMULMAX2-RV32-NEXT: vle16.v v26, (a1) -; LMULMAX2-RV32-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle16.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload @@ -5844,10 +5844,10 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -48 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle16.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 15 -; LMULMAX2-RV64-NEXT: vmv.x.s a2, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 15 +; LMULMAX2-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX2-RV64-NEXT: lui a6, 16 ; LMULMAX2-RV64-NEXT: or a2, a2, a6 ; LMULMAX2-RV64-NEXT: addi a3, a2, -1 @@ -5896,8 +5896,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 46(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 14 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 14 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -5915,8 +5915,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 44(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 13 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 13 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -5934,8 +5934,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 42(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 12 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 12 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -5953,8 +5953,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 40(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 11 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 11 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -5972,8 +5972,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 38(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 10 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 10 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -5991,8 +5991,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 36(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 9 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 9 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -6010,8 +6010,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 34(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 8 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 8 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -6029,8 +6029,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 32(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -6048,8 +6048,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 30(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -6067,8 +6067,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -6086,8 +6086,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 26(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -6105,8 +6105,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -6124,8 +6124,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 22(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -6143,8 +6143,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 20(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -6162,7 +6162,7 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sh a1, 18(sp) -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -6182,8 +6182,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-RV64-NEXT: sh a1, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle16.v v26, (a1) -; LMULMAX2-RV64-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle16.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 48 ; LMULMAX2-RV64-NEXT: ret ; @@ -6193,9 +6193,9 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a6, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a6) -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vle16.v v9, (a6) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: lui a7, 16 ; LMULMAX1-RV32-NEXT: or a1, a1, a7 ; LMULMAX1-RV32-NEXT: addi a3, a1, -1 @@ -6223,8 +6223,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: sh a2, 32(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 7 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 7 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: or a2, a2, a7 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -6242,8 +6242,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a2, a2, a1 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: sh a2, 46(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 6 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 6 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: or a2, a2, a7 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -6261,8 +6261,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a2, a2, a1 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: sh a2, 44(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 5 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 5 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: or a2, a2, a7 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -6280,8 +6280,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a2, a2, a1 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: sh a2, 42(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 4 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 4 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: or a2, a2, a7 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -6299,8 +6299,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a2, a2, a1 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: sh a2, 40(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: or a2, a2, a7 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -6318,8 +6318,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a2, a2, a1 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: sh a2, 38(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV32-NEXT: or a2, a2, a7 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -6337,8 +6337,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a2, a2, a1 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: sh a2, 36(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: or a2, a2, a7 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -6356,7 +6356,7 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a2, a2, a1 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: sh a2, 34(sp) -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV32-NEXT: or a2, a2, a7 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -6374,8 +6374,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a2, a2, a1 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: sh a2, 16(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: or a2, a2, a7 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -6393,8 +6393,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a2, a2, a1 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: sh a2, 30(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: or a2, a2, a7 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -6412,8 +6412,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a2, a2, a1 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: sh a2, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: or a2, a2, a7 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -6431,8 +6431,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a2, a2, a1 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: sh a2, 26(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: or a2, a2, a7 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -6450,8 +6450,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a2, a2, a1 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: sh a2, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: or a2, a2, a7 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -6469,8 +6469,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a2, a2, a1 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: sh a2, 22(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: or a2, a2, a7 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -6488,8 +6488,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: mul a2, a2, a1 ; LMULMAX1-RV32-NEXT: srli a2, a2, 24 ; LMULMAX1-RV32-NEXT: sh a2, 20(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV32-NEXT: or a2, a2, a7 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 @@ -6509,11 +6509,11 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV32-NEXT: sh a1, 18(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle16.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a1, sp, 32 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a1) -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a6) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a1) +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 ; LMULMAX1-RV32-NEXT: ret ; @@ -6523,9 +6523,9 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a6, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a6) -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vle16.v v9, (a6) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: lui a7, 16 ; LMULMAX1-RV64-NEXT: or a1, a1, a7 ; LMULMAX1-RV64-NEXT: addi a3, a1, -1 @@ -6575,8 +6575,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sh a2, 32(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 7 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 7 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -6594,8 +6594,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sh a2, 46(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 6 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 6 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -6613,8 +6613,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sh a2, 44(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 5 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 5 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -6632,8 +6632,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sh a2, 42(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 4 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 4 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -6651,8 +6651,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sh a2, 40(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -6670,8 +6670,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sh a2, 38(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -6689,8 +6689,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sh a2, 36(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -6708,8 +6708,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sh a2, 34(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 7 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 7 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -6727,8 +6727,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sh a2, 30(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 6 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 6 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -6746,8 +6746,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sh a2, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 5 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 5 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -6765,8 +6765,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sh a2, 26(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 4 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 4 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -6784,8 +6784,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sh a2, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -6803,8 +6803,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sh a2, 22(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -6822,8 +6822,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sh a2, 20(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -6841,7 +6841,7 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sh a2, 18(sp) -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -6861,11 +6861,11 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX1-RV64-NEXT: sh a1, 16(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, sp, 16 -; LMULMAX1-RV64-NEXT: vle16.v v25, (a1) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a1) ; LMULMAX1-RV64-NEXT: addi a1, sp, 32 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a1) -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a6) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a1) +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a6) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x @@ -6889,8 +6889,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX2-RV32-NEXT: andi sp, sp, -32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle32.v v26, (a0) -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: addi a2, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a2, a1, a2 @@ -6916,8 +6916,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: srli a5, a5, 24 ; LMULMAX2-RV32-NEXT: sw a5, 32(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV32-NEXT: vmv.x.s a5, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV32-NEXT: vmv.x.s a5, v10 ; LMULMAX2-RV32-NEXT: addi a1, a5, -1 ; LMULMAX2-RV32-NEXT: not a5, a5 ; LMULMAX2-RV32-NEXT: and a1, a5, a1 @@ -6934,8 +6934,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 60(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a1, a1, a5 @@ -6952,8 +6952,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 56(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a1, a1, a5 @@ -6970,8 +6970,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 52(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a1, a1, a5 @@ -6988,8 +6988,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 48(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a1, a1, a5 @@ -7006,8 +7006,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 44(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a1, a1, a5 @@ -7024,8 +7024,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a4 ; LMULMAX2-RV32-NEXT: srli a1, a1, 24 ; LMULMAX2-RV32-NEXT: sw a1, 40(sp) -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a1, a1, a5 @@ -7044,8 +7044,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV32-NEXT: sw a1, 36(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 32 -; LMULMAX2-RV32-NEXT: vle32.v v26, (a1) -; LMULMAX2-RV32-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle32.v v8, (a1) +; LMULMAX2-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload @@ -7057,10 +7057,10 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -48 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle32.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 7 -; LMULMAX2-RV64-NEXT: vmv.x.s a2, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 7 +; LMULMAX2-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX2-RV64-NEXT: addi a1, zero, 1 ; LMULMAX2-RV64-NEXT: slli a6, a1, 32 ; LMULMAX2-RV64-NEXT: or a2, a2, a6 @@ -7110,8 +7110,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sw a1, 44(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 6 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 6 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -7129,8 +7129,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sw a1, 40(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 5 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 5 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -7148,8 +7148,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sw a1, 36(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 4 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 4 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -7167,8 +7167,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sw a1, 32(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -7186,8 +7186,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sw a1, 28(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -7205,8 +7205,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sw a1, 24(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -7224,7 +7224,7 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sw a1, 20(sp) -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: or a1, a1, a6 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 @@ -7244,8 +7244,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-RV64-NEXT: sw a1, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle32.v v26, (a1) -; LMULMAX2-RV64-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle32.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 48 ; LMULMAX2-RV64-NEXT: ret ; @@ -7255,9 +7255,9 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a6, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a6) -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV32-NEXT: vle32.v v9, (a6) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV32-NEXT: addi a3, a2, -1 ; LMULMAX1-RV32-NEXT: not a2, a2 ; LMULMAX1-RV32-NEXT: and a3, a2, a3 @@ -7283,8 +7283,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 32(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a1, a1, a2 @@ -7301,8 +7301,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 44(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a1, a1, a2 @@ -7319,8 +7319,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 40(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a1, a1, a2 @@ -7337,7 +7337,7 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 36(sp) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a1, a1, a2 @@ -7354,8 +7354,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 16(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a1, a1, a2 @@ -7372,8 +7372,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 28(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a1, a1, a2 @@ -7390,8 +7390,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a5 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: sw a1, 24(sp) -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a1, a1, a2 @@ -7410,11 +7410,11 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV32-NEXT: sw a1, 20(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a1, sp, 32 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a1) -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a6) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a1) +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a6) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 ; LMULMAX1-RV32-NEXT: ret ; @@ -7424,9 +7424,9 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a6, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a6) -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vle32.v v9, (a6) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: addi a2, zero, 1 ; LMULMAX1-RV64-NEXT: slli a7, a2, 32 ; LMULMAX1-RV64-NEXT: or a1, a1, a7 @@ -7477,8 +7477,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sw a2, 32(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -7496,8 +7496,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sw a2, 44(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -7515,8 +7515,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sw a2, 40(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -7534,8 +7534,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sw a2, 36(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 3 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 3 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -7553,8 +7553,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sw a2, 28(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 2 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -7572,8 +7572,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sw a2, 24(sp) -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v9 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -7591,7 +7591,7 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: sw a2, 20(sp) -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV64-NEXT: or a2, a2, a7 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 @@ -7611,11 +7611,11 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX1-RV64-NEXT: sw a1, 16(sp) ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, sp, 16 -; LMULMAX1-RV64-NEXT: vle32.v v25, (a1) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV64-NEXT: addi a1, sp, 32 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a1) -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a6) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a1) +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a6) ; LMULMAX1-RV64-NEXT: addi sp, sp, 48 ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x @@ -7639,7 +7639,7 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX2-RV32-NEXT: andi sp, sp, -32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle64.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32-NEXT: sw zero, 60(sp) ; LMULMAX2-RV32-NEXT: sw zero, 52(sp) ; LMULMAX2-RV32-NEXT: sw zero, 44(sp) @@ -7652,13 +7652,13 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: lui a1, 61681 ; LMULMAX2-RV32-NEXT: addi a7, a1, -241 ; LMULMAX2-RV32-NEXT: lui a1, 4112 -; LMULMAX2-RV32-NEXT: vmv.x.s a5, v26 +; LMULMAX2-RV32-NEXT: vmv.x.s a5, v8 ; LMULMAX2-RV32-NEXT: addi a2, a1, 257 ; LMULMAX2-RV32-NEXT: bnez a5, .LBB7_2 ; LMULMAX2-RV32-NEXT: # %bb.1: ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vsrl.vx v28, v26, a6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a1, a1, a5 @@ -7695,12 +7695,12 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: .LBB7_3: ; LMULMAX2-RV32-NEXT: sw a5, 32(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV32-NEXT: vmv.x.s a5, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV32-NEXT: vmv.x.s a5, v10 ; LMULMAX2-RV32-NEXT: bnez a5, .LBB7_5 ; LMULMAX2-RV32-NEXT: # %bb.4: -; LMULMAX2-RV32-NEXT: vsrl.vx v28, v28, a6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vsrl.vx v10, v10, a6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a1, a1, a5 @@ -7735,13 +7735,13 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a2 ; LMULMAX2-RV32-NEXT: srli a5, a1, 24 ; LMULMAX2-RV32-NEXT: .LBB7_6: -; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: sw a5, 56(sp) ; LMULMAX2-RV32-NEXT: bnez a1, .LBB7_8 ; LMULMAX2-RV32-NEXT: # %bb.7: -; LMULMAX2-RV32-NEXT: vsrl.vx v28, v28, a6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV32-NEXT: vsrl.vx v10, v10, a6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a1, a1, a5 @@ -7776,13 +7776,13 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: mul a1, a1, a2 ; LMULMAX2-RV32-NEXT: srli a5, a1, 24 ; LMULMAX2-RV32-NEXT: .LBB7_9: -; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: sw a5, 48(sp) ; LMULMAX2-RV32-NEXT: bnez a1, .LBB7_11 ; LMULMAX2-RV32-NEXT: # %bb.10: -; LMULMAX2-RV32-NEXT: vsrl.vx v26, v26, a6 -; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV32-NEXT: vsrl.vx v8, v8, a6 +; LMULMAX2-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV32-NEXT: addi a5, a1, -1 ; LMULMAX2-RV32-NEXT: not a1, a1 ; LMULMAX2-RV32-NEXT: and a1, a1, a5 @@ -7820,9 +7820,9 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV32-NEXT: sw a1, 40(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 32 -; LMULMAX2-RV32-NEXT: vle32.v v26, (a1) +; LMULMAX2-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, s0, -96 ; LMULMAX2-RV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload ; LMULMAX2-RV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload @@ -7834,10 +7834,10 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: addi sp, sp, -48 ; LMULMAX2-RV64-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 3 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 3 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: addi a2, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 ; LMULMAX2-RV64-NEXT: and a2, a1, a2 @@ -7884,8 +7884,8 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: mul a4, a4, a5 ; LMULMAX2-RV64-NEXT: srli a4, a4, 56 ; LMULMAX2-RV64-NEXT: sd a4, 40(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 2 -; LMULMAX2-RV64-NEXT: vmv.x.s a4, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 2 +; LMULMAX2-RV64-NEXT: vmv.x.s a4, v10 ; LMULMAX2-RV64-NEXT: addi a1, a4, -1 ; LMULMAX2-RV64-NEXT: not a4, a4 ; LMULMAX2-RV64-NEXT: and a1, a4, a1 @@ -7902,8 +7902,8 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sd a1, 32(sp) -; LMULMAX2-RV64-NEXT: vslidedown.vi v28, v26, 1 -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v28 +; LMULMAX2-RV64-NEXT: vslidedown.vi v10, v8, 1 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v10 ; LMULMAX2-RV64-NEXT: addi a4, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 ; LMULMAX2-RV64-NEXT: and a1, a1, a4 @@ -7920,7 +7920,7 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: sd a1, 24(sp) -; LMULMAX2-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX2-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX2-RV64-NEXT: addi a4, a1, -1 ; LMULMAX2-RV64-NEXT: not a1, a1 ; LMULMAX2-RV64-NEXT: and a1, a1, a4 @@ -7939,8 +7939,8 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-RV64-NEXT: sd a1, 16(sp) ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-RV64-NEXT: addi a1, sp, 16 -; LMULMAX2-RV64-NEXT: vle64.v v26, (a1) -; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle64.v v8, (a1) +; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi sp, sp, 48 ; LMULMAX2-RV64-NEXT: ret ; @@ -7949,9 +7949,9 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: addi sp, sp, -48 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a7, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a7) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a7) ; LMULMAX1-RV32-NEXT: sw zero, 44(sp) ; LMULMAX1-RV32-NEXT: sw zero, 36(sp) ; LMULMAX1-RV32-NEXT: addi a6, zero, 32 @@ -7962,13 +7962,13 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: lui a1, 61681 ; LMULMAX1-RV32-NEXT: addi t0, a1, -241 ; LMULMAX1-RV32-NEXT: lui a2, 4112 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: addi a3, a2, 257 ; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_2 ; LMULMAX1-RV32-NEXT: # %bb.1: ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vsrl.vx v27, v26, a6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27 +; LMULMAX1-RV32-NEXT: vsrl.vx v10, v9, a6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v10 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a1, a1, a2 @@ -8005,12 +8005,12 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: .LBB7_3: ; LMULMAX1-RV32-NEXT: sw a1, 32(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v9, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_5 ; LMULMAX1-RV32-NEXT: # %bb.4: -; LMULMAX1-RV32-NEXT: vsrl.vx v26, v26, a6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vsrl.vx v9, v9, a6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a1, a1, a2 @@ -8047,12 +8047,12 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: .LBB7_6: ; LMULMAX1-RV32-NEXT: sw a1, 40(sp) ; LMULMAX1-RV32-NEXT: sw zero, 28(sp) -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: sw zero, 20(sp) ; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_8 ; LMULMAX1-RV32-NEXT: # %bb.7: -; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV32-NEXT: vsrl.vx v9, v8, a6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a1, a1, a2 @@ -8087,13 +8087,13 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: mul a1, a1, a3 ; LMULMAX1-RV32-NEXT: srli a1, a1, 24 ; LMULMAX1-RV32-NEXT: .LBB7_9: -; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25 +; LMULMAX1-RV32-NEXT: vslidedown.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vmv.x.s a2, v8 ; LMULMAX1-RV32-NEXT: sw a1, 16(sp) ; LMULMAX1-RV32-NEXT: bnez a2, .LBB7_11 ; LMULMAX1-RV32-NEXT: # %bb.10: -; LMULMAX1-RV32-NEXT: vsrl.vx v25, v25, a6 -; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV32-NEXT: vsrl.vx v8, v8, a6 +; LMULMAX1-RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV32-NEXT: addi a2, a1, -1 ; LMULMAX1-RV32-NEXT: not a1, a1 ; LMULMAX1-RV32-NEXT: and a1, a1, a2 @@ -8131,12 +8131,12 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV32-NEXT: sw a1, 24(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 16 -; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a1, sp, 32 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a1) ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a7) +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a7) ; LMULMAX1-RV32-NEXT: addi sp, sp, 48 ; LMULMAX1-RV32-NEXT: ret ; @@ -8144,11 +8144,11 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a6, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a6) -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a6) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v26, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a2, v27 +; LMULMAX1-RV64-NEXT: vslidedown.vi v10, v9, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a2, v10 ; LMULMAX1-RV64-NEXT: addi a3, a2, -1 ; LMULMAX1-RV64-NEXT: not a2, a2 ; LMULMAX1-RV64-NEXT: and a3, a2, a3 @@ -8195,8 +8195,8 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.x v27, a1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vmv.v.x v10, a1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 ; LMULMAX1-RV64-NEXT: and a1, a1, a2 @@ -8213,10 +8213,10 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1 +; LMULMAX1-RV64-NEXT: vmv.s.x v10, a1 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v26 +; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v9 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 ; LMULMAX1-RV64-NEXT: and a1, a1, a2 @@ -8233,8 +8233,8 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.x v26, a1 -; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 +; LMULMAX1-RV64-NEXT: vmv.v.x v9, a1 +; LMULMAX1-RV64-NEXT: vmv.x.s a1, v8 ; LMULMAX1-RV64-NEXT: addi a2, a1, -1 ; LMULMAX1-RV64-NEXT: not a1, a1 ; LMULMAX1-RV64-NEXT: and a1, a1, a2 @@ -8251,9 +8251,9 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 -; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v27, (a6) +; LMULMAX1-RV64-NEXT: vmv.s.x v9, a1 +; LMULMAX1-RV64-NEXT: vse64.v v9, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v10, (a6) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll index 8e78e89f1fb9052099ed67e7605dff70b856b6e3..9e6da01784589f12dadd52b6bbff3201e40144fb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll @@ -10,10 +10,10 @@ define void @add_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: add_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -71,10 +71,10 @@ define void @add_v2i32(<2 x i32>* %x, <2 x i32>* %y) { ; CHECK-LABEL: add_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %b = load <2 x i32>, <2 x i32>* %y @@ -118,10 +118,10 @@ define void @fadd_v4f32(<4 x float>* %x, <4 x float>* %y) { ; CHECK-LABEL: fadd_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vfadd.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vfadd.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -155,10 +155,10 @@ define void @fadd_v2f32(<2 x float>* %x, <2 x float>* %y) { ; CHECK-LABEL: fadd_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vfadd.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vfadd.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x float>, <2 x float>* %x %b = load <2 x float>, <2 x float>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll index f332e0bc94191c2eefab3ea6015e8fc67675d331..ab55b58c77e8ac482addfb8b06698a93d3df83ec 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll @@ -10,8 +10,8 @@ define <2 x i16> @sextload_v2i1_v2i16(<2 x i1>* %x) { ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %y = load <2 x i1>, <2 x i1>* %x %z = sext <2 x i1> %y to <2 x i16> @@ -22,9 +22,9 @@ define <2 x i16> @sextload_v2i8_v2i16(<2 x i8>* %x) { ; CHECK-LABEL: sextload_v2i8_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: vsext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load <2 x i8>, <2 x i8>* %x %z = sext <2 x i8> %y to <2 x i16> @@ -35,9 +35,9 @@ define <2 x i16> @zextload_v2i8_v2i16(<2 x i8>* %x) { ; CHECK-LABEL: zextload_v2i8_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load <2 x i8>, <2 x i8>* %x %z = zext <2 x i8> %y to <2 x i16> @@ -48,9 +48,9 @@ define <2 x i32> @sextload_v2i8_v2i32(<2 x i8>* %x) { ; CHECK-LABEL: sextload_v2i8_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: vsext.vf4 v8, v9 ; CHECK-NEXT: ret %y = load <2 x i8>, <2 x i8>* %x %z = sext <2 x i8> %y to <2 x i32> @@ -61,9 +61,9 @@ define <2 x i32> @zextload_v2i8_v2i32(<2 x i8>* %x) { ; CHECK-LABEL: zextload_v2i8_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: vzext.vf4 v8, v9 ; CHECK-NEXT: ret %y = load <2 x i8>, <2 x i8>* %x %z = zext <2 x i8> %y to <2 x i32> @@ -74,9 +74,9 @@ define <2 x i64> @sextload_v2i8_v2i64(<2 x i8>* %x) { ; CHECK-LABEL: sextload_v2i8_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf8 v8, v25 +; CHECK-NEXT: vsext.vf8 v8, v9 ; CHECK-NEXT: ret %y = load <2 x i8>, <2 x i8>* %x %z = sext <2 x i8> %y to <2 x i64> @@ -87,9 +87,9 @@ define <2 x i64> @zextload_v2i8_v2i64(<2 x i8>* %x) { ; CHECK-LABEL: zextload_v2i8_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf8 v8, v25 +; CHECK-NEXT: vzext.vf8 v8, v9 ; CHECK-NEXT: ret %y = load <2 x i8>, <2 x i8>* %x %z = zext <2 x i8> %y to <2 x i64> @@ -100,9 +100,9 @@ define <4 x i16> @sextload_v4i8_v4i16(<4 x i8>* %x) { ; CHECK-LABEL: sextload_v4i8_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: vsext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load <4 x i8>, <4 x i8>* %x %z = sext <4 x i8> %y to <4 x i16> @@ -113,9 +113,9 @@ define <4 x i16> @zextload_v4i8_v4i16(<4 x i8>* %x) { ; CHECK-LABEL: zextload_v4i8_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load <4 x i8>, <4 x i8>* %x %z = zext <4 x i8> %y to <4 x i16> @@ -126,9 +126,9 @@ define <4 x i32> @sextload_v4i8_v4i32(<4 x i8>* %x) { ; CHECK-LABEL: sextload_v4i8_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: vsext.vf4 v8, v9 ; CHECK-NEXT: ret %y = load <4 x i8>, <4 x i8>* %x %z = sext <4 x i8> %y to <4 x i32> @@ -139,9 +139,9 @@ define <4 x i32> @zextload_v4i8_v4i32(<4 x i8>* %x) { ; CHECK-LABEL: zextload_v4i8_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: vzext.vf4 v8, v9 ; CHECK-NEXT: ret %y = load <4 x i8>, <4 x i8>* %x %z = zext <4 x i8> %y to <4 x i32> @@ -152,20 +152,20 @@ define <4 x i64> @sextload_v4i8_v4i64(<4 x i8>* %x) { ; LMULMAX1-LABEL: sextload_v4i8_v4i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX1-NEXT: vle8.v v25, (a0) +; LMULMAX1-NEXT: vle8.v v10, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf8 v9, v26 -; LMULMAX1-NEXT: vsext.vf8 v8, v25 +; LMULMAX1-NEXT: vsext.vf8 v9, v8 +; LMULMAX1-NEXT: vsext.vf8 v8, v10 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v4i8_v4i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX4-NEXT: vle8.v v25, (a0) +; LMULMAX4-NEXT: vle8.v v10, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; LMULMAX4-NEXT: vsext.vf8 v8, v25 +; LMULMAX4-NEXT: vsext.vf8 v8, v10 ; LMULMAX4-NEXT: ret %y = load <4 x i8>, <4 x i8>* %x %z = sext <4 x i8> %y to <4 x i64> @@ -176,20 +176,20 @@ define <4 x i64> @zextload_v4i8_v4i64(<4 x i8>* %x) { ; LMULMAX1-LABEL: zextload_v4i8_v4i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX1-NEXT: vle8.v v25, (a0) +; LMULMAX1-NEXT: vle8.v v10, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf8 v9, v26 -; LMULMAX1-NEXT: vzext.vf8 v8, v25 +; LMULMAX1-NEXT: vzext.vf8 v9, v8 +; LMULMAX1-NEXT: vzext.vf8 v8, v10 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v4i8_v4i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX4-NEXT: vle8.v v25, (a0) +; LMULMAX4-NEXT: vle8.v v10, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; LMULMAX4-NEXT: vzext.vf8 v8, v25 +; LMULMAX4-NEXT: vzext.vf8 v8, v10 ; LMULMAX4-NEXT: ret %y = load <4 x i8>, <4 x i8>* %x %z = zext <4 x i8> %y to <4 x i64> @@ -200,9 +200,9 @@ define <8 x i16> @sextload_v8i8_v8i16(<8 x i8>* %x) { ; CHECK-LABEL: sextload_v8i8_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: vsext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load <8 x i8>, <8 x i8>* %x %z = sext <8 x i8> %y to <8 x i16> @@ -213,9 +213,9 @@ define <8 x i16> @zextload_v8i8_v8i16(<8 x i8>* %x) { ; CHECK-LABEL: zextload_v8i8_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load <8 x i8>, <8 x i8>* %x %z = zext <8 x i8> %y to <8 x i16> @@ -226,20 +226,20 @@ define <8 x i32> @sextload_v8i8_v8i32(<8 x i8>* %x) { ; LMULMAX1-LABEL: sextload_v8i8_v8i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vle8.v v25, (a0) +; LMULMAX1-NEXT: vle8.v v10, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v9, v26 -; LMULMAX1-NEXT: vsext.vf4 v8, v25 +; LMULMAX1-NEXT: vsext.vf4 v9, v8 +; LMULMAX1-NEXT: vsext.vf4 v8, v10 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v8i8_v8i32: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX4-NEXT: vle8.v v25, (a0) +; LMULMAX4-NEXT: vle8.v v10, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; LMULMAX4-NEXT: vsext.vf4 v8, v25 +; LMULMAX4-NEXT: vsext.vf4 v8, v10 ; LMULMAX4-NEXT: ret %y = load <8 x i8>, <8 x i8>* %x %z = sext <8 x i8> %y to <8 x i32> @@ -250,20 +250,20 @@ define <8 x i32> @zextload_v8i8_v8i32(<8 x i8>* %x) { ; LMULMAX1-LABEL: zextload_v8i8_v8i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vle8.v v25, (a0) +; LMULMAX1-NEXT: vle8.v v10, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v9, v26 -; LMULMAX1-NEXT: vzext.vf4 v8, v25 +; LMULMAX1-NEXT: vzext.vf4 v9, v8 +; LMULMAX1-NEXT: vzext.vf4 v8, v10 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v8i8_v8i32: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX4-NEXT: vle8.v v25, (a0) +; LMULMAX4-NEXT: vle8.v v10, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; LMULMAX4-NEXT: vzext.vf4 v8, v25 +; LMULMAX4-NEXT: vzext.vf4 v8, v10 ; LMULMAX4-NEXT: ret %y = load <8 x i8>, <8 x i8>* %x %z = zext <8 x i8> %y to <8 x i32> @@ -274,28 +274,28 @@ define <8 x i64> @sextload_v8i8_v8i64(<8 x i8>* %x) { ; LMULMAX1-LABEL: sextload_v8i8_v8i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vle8.v v25, (a0) +; LMULMAX1-NEXT: vle8.v v12, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf8 v10, v26 +; LMULMAX1-NEXT: vsext.vf8 v10, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf8 v9, v27 +; LMULMAX1-NEXT: vsext.vf8 v9, v11 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf8 v11, v26 -; LMULMAX1-NEXT: vsext.vf8 v8, v25 +; LMULMAX1-NEXT: vsext.vf8 v11, v8 +; LMULMAX1-NEXT: vsext.vf8 v8, v12 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v8i8_v8i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX4-NEXT: vle8.v v25, (a0) +; LMULMAX4-NEXT: vle8.v v12, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; LMULMAX4-NEXT: vsext.vf8 v8, v25 +; LMULMAX4-NEXT: vsext.vf8 v8, v12 ; LMULMAX4-NEXT: ret %y = load <8 x i8>, <8 x i8>* %x %z = sext <8 x i8> %y to <8 x i64> @@ -306,28 +306,28 @@ define <8 x i64> @zextload_v8i8_v8i64(<8 x i8>* %x) { ; LMULMAX1-LABEL: zextload_v8i8_v8i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vle8.v v25, (a0) +; LMULMAX1-NEXT: vle8.v v12, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf8 v10, v26 +; LMULMAX1-NEXT: vzext.vf8 v10, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf8 v9, v27 +; LMULMAX1-NEXT: vzext.vf8 v9, v11 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf8 v11, v26 -; LMULMAX1-NEXT: vzext.vf8 v8, v25 +; LMULMAX1-NEXT: vzext.vf8 v11, v8 +; LMULMAX1-NEXT: vzext.vf8 v8, v12 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v8i8_v8i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX4-NEXT: vle8.v v25, (a0) +; LMULMAX4-NEXT: vle8.v v12, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; LMULMAX4-NEXT: vzext.vf8 v8, v25 +; LMULMAX4-NEXT: vzext.vf8 v8, v12 ; LMULMAX4-NEXT: ret %y = load <8 x i8>, <8 x i8>* %x %z = zext <8 x i8> %y to <8 x i64> @@ -338,20 +338,20 @@ define <16 x i16> @sextload_v16i8_v16i16(<16 x i8>* %x) { ; LMULMAX1-LABEL: sextload_v16i8_v16i16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vle8.v v25, (a0) +; LMULMAX1-NEXT: vle8.v v10, (a0) ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 8 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 8 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf2 v9, v26 -; LMULMAX1-NEXT: vsext.vf2 v8, v25 +; LMULMAX1-NEXT: vsext.vf2 v9, v8 +; LMULMAX1-NEXT: vsext.vf2 v8, v10 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v16i8_v16i16: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX4-NEXT: vle8.v v25, (a0) +; LMULMAX4-NEXT: vle8.v v10, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; LMULMAX4-NEXT: vsext.vf2 v8, v25 +; LMULMAX4-NEXT: vsext.vf2 v8, v10 ; LMULMAX4-NEXT: ret %y = load <16 x i8>, <16 x i8>* %x %z = sext <16 x i8> %y to <16 x i16> @@ -362,20 +362,20 @@ define <16 x i16> @zextload_v16i8_v16i16(<16 x i8>* %x) { ; LMULMAX1-LABEL: zextload_v16i8_v16i16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vle8.v v25, (a0) +; LMULMAX1-NEXT: vle8.v v10, (a0) ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 8 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 8 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf2 v9, v26 -; LMULMAX1-NEXT: vzext.vf2 v8, v25 +; LMULMAX1-NEXT: vzext.vf2 v9, v8 +; LMULMAX1-NEXT: vzext.vf2 v8, v10 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v16i8_v16i16: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX4-NEXT: vle8.v v25, (a0) +; LMULMAX4-NEXT: vle8.v v10, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; LMULMAX4-NEXT: vzext.vf2 v8, v25 +; LMULMAX4-NEXT: vzext.vf2 v8, v10 ; LMULMAX4-NEXT: ret %y = load <16 x i8>, <16 x i8>* %x %z = zext <16 x i8> %y to <16 x i16> @@ -386,28 +386,28 @@ define <16 x i32> @sextload_v16i8_v16i32(<16 x i8>* %x) { ; LMULMAX1-LABEL: sextload_v16i8_v16i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vle8.v v25, (a0) +; LMULMAX1-NEXT: vle8.v v12, (a0) ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 8 +; LMULMAX1-NEXT: vslidedown.vi v8, v12, 8 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v10, v26 +; LMULMAX1-NEXT: vsext.vf4 v10, v8 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v11, v12, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v9, v27 +; LMULMAX1-NEXT: vsext.vf4 v9, v11 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v26, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v11, v26 -; LMULMAX1-NEXT: vsext.vf4 v8, v25 +; LMULMAX1-NEXT: vsext.vf4 v11, v8 +; LMULMAX1-NEXT: vsext.vf4 v8, v12 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v16i8_v16i32: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX4-NEXT: vle8.v v25, (a0) +; LMULMAX4-NEXT: vle8.v v12, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m4, ta, mu -; LMULMAX4-NEXT: vsext.vf4 v8, v25 +; LMULMAX4-NEXT: vsext.vf4 v8, v12 ; LMULMAX4-NEXT: ret %y = load <16 x i8>, <16 x i8>* %x %z = sext <16 x i8> %y to <16 x i32> @@ -418,28 +418,28 @@ define <16 x i32> @zextload_v16i8_v16i32(<16 x i8>* %x) { ; LMULMAX1-LABEL: zextload_v16i8_v16i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vle8.v v25, (a0) +; LMULMAX1-NEXT: vle8.v v12, (a0) ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 8 +; LMULMAX1-NEXT: vslidedown.vi v8, v12, 8 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v10, v26 +; LMULMAX1-NEXT: vzext.vf4 v10, v8 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v11, v12, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v9, v27 +; LMULMAX1-NEXT: vzext.vf4 v9, v11 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v26, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v11, v26 -; LMULMAX1-NEXT: vzext.vf4 v8, v25 +; LMULMAX1-NEXT: vzext.vf4 v11, v8 +; LMULMAX1-NEXT: vzext.vf4 v8, v12 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v16i8_v16i32: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX4-NEXT: vle8.v v25, (a0) +; LMULMAX4-NEXT: vle8.v v12, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m4, ta, mu -; LMULMAX4-NEXT: vzext.vf4 v8, v25 +; LMULMAX4-NEXT: vzext.vf4 v8, v12 ; LMULMAX4-NEXT: ret %y = load <16 x i8>, <16 x i8>* %x %z = zext <16 x i8> %y to <16 x i32> @@ -450,47 +450,47 @@ define <16 x i64> @sextload_v16i8_v16i64(<16 x i8>* %x) { ; LMULMAX1-LABEL: sextload_v16i8_v16i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vle8.v v25, (a0) +; LMULMAX1-NEXT: vle8.v v16, (a0) ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 8 +; LMULMAX1-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf8 v12, v26 +; LMULMAX1-NEXT: vsext.vf8 v12, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v10, v16, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf8 v9, v27 +; LMULMAX1-NEXT: vsext.vf8 v9, v10 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v11, v16, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf8 v10, v27 +; LMULMAX1-NEXT: vsext.vf8 v10, v11 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v28, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v14, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf8 v13, v28 +; LMULMAX1-NEXT: vsext.vf8 v13, v14 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v26, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf8 v14, v26 +; LMULMAX1-NEXT: vsext.vf8 v14, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v27, 2 +; LMULMAX1-NEXT: vslidedown.vi v15, v11, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf8 v11, v27 +; LMULMAX1-NEXT: vsext.vf8 v11, v15 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf8 v15, v26 -; LMULMAX1-NEXT: vsext.vf8 v8, v25 +; LMULMAX1-NEXT: vsext.vf8 v15, v8 +; LMULMAX1-NEXT: vsext.vf8 v8, v16 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v16i8_v16i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX4-NEXT: vle8.v v25, (a0) +; LMULMAX4-NEXT: vle8.v v16, (a0) ; LMULMAX4-NEXT: vsetivli zero, 8, e8, m1, ta, mu -; LMULMAX4-NEXT: vslidedown.vi v26, v25, 8 +; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; LMULMAX4-NEXT: vsext.vf8 v12, v26 -; LMULMAX4-NEXT: vsext.vf8 v8, v25 +; LMULMAX4-NEXT: vsext.vf8 v12, v8 +; LMULMAX4-NEXT: vsext.vf8 v8, v16 ; LMULMAX4-NEXT: ret %y = load <16 x i8>, <16 x i8>* %x %z = sext <16 x i8> %y to <16 x i64> @@ -501,47 +501,47 @@ define <16 x i64> @zextload_v16i8_v16i64(<16 x i8>* %x) { ; LMULMAX1-LABEL: zextload_v16i8_v16i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vle8.v v25, (a0) +; LMULMAX1-NEXT: vle8.v v16, (a0) ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 8 +; LMULMAX1-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf8 v12, v26 +; LMULMAX1-NEXT: vzext.vf8 v12, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v10, v16, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf8 v9, v27 +; LMULMAX1-NEXT: vzext.vf8 v9, v10 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v11, v16, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf8 v10, v27 +; LMULMAX1-NEXT: vzext.vf8 v10, v11 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v28, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v14, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf8 v13, v28 +; LMULMAX1-NEXT: vzext.vf8 v13, v14 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v26, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf8 v14, v26 +; LMULMAX1-NEXT: vzext.vf8 v14, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v27, 2 +; LMULMAX1-NEXT: vslidedown.vi v15, v11, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf8 v11, v27 +; LMULMAX1-NEXT: vzext.vf8 v11, v15 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf8 v15, v26 -; LMULMAX1-NEXT: vzext.vf8 v8, v25 +; LMULMAX1-NEXT: vzext.vf8 v15, v8 +; LMULMAX1-NEXT: vzext.vf8 v8, v16 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v16i8_v16i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX4-NEXT: vle8.v v25, (a0) +; LMULMAX4-NEXT: vle8.v v16, (a0) ; LMULMAX4-NEXT: vsetivli zero, 8, e8, m1, ta, mu -; LMULMAX4-NEXT: vslidedown.vi v26, v25, 8 +; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; LMULMAX4-NEXT: vzext.vf8 v12, v26 -; LMULMAX4-NEXT: vzext.vf8 v8, v25 +; LMULMAX4-NEXT: vzext.vf8 v12, v8 +; LMULMAX4-NEXT: vzext.vf8 v8, v16 ; LMULMAX4-NEXT: ret %y = load <16 x i8>, <16 x i8>* %x %z = zext <16 x i8> %y to <16 x i64> @@ -552,17 +552,17 @@ define void @truncstore_v2i8_v2i1(<2 x i8> %x, <2 x i1>* %z) { ; CHECK-LABEL: truncstore_v2i8_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %y = trunc <2 x i8> %x to <2 x i1> store <2 x i1> %y, <2 x i1>* %z @@ -573,8 +573,8 @@ define void @truncstore_v2i16_v2i8(<2 x i16> %x, <2 x i8>* %z) { ; CHECK-LABEL: truncstore_v2i16_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %y = trunc <2 x i16> %x to <2 x i8> store <2 x i8> %y, <2 x i8>* %z @@ -585,9 +585,9 @@ define <2 x i32> @sextload_v2i16_v2i32(<2 x i16>* %x) { ; CHECK-LABEL: sextload_v2i16_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: vsext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load <2 x i16>, <2 x i16>* %x %z = sext <2 x i16> %y to <2 x i32> @@ -598,9 +598,9 @@ define <2 x i32> @zextload_v2i16_v2i32(<2 x i16>* %x) { ; CHECK-LABEL: zextload_v2i16_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load <2 x i16>, <2 x i16>* %x %z = zext <2 x i16> %y to <2 x i32> @@ -611,9 +611,9 @@ define <2 x i64> @sextload_v2i16_v2i64(<2 x i16>* %x) { ; CHECK-LABEL: sextload_v2i16_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v8, v25 +; CHECK-NEXT: vsext.vf4 v8, v9 ; CHECK-NEXT: ret %y = load <2 x i16>, <2 x i16>* %x %z = sext <2 x i16> %y to <2 x i64> @@ -624,9 +624,9 @@ define <2 x i64> @zextload_v2i16_v2i64(<2 x i16>* %x) { ; CHECK-LABEL: zextload_v2i16_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v8, v25 +; CHECK-NEXT: vzext.vf4 v8, v9 ; CHECK-NEXT: ret %y = load <2 x i16>, <2 x i16>* %x %z = zext <2 x i16> %y to <2 x i64> @@ -637,8 +637,8 @@ define void @truncstore_v4i16_v4i8(<4 x i16> %x, <4 x i8>* %z) { ; CHECK-LABEL: truncstore_v4i16_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %y = trunc <4 x i16> %x to <4 x i8> store <4 x i8> %y, <4 x i8>* %z @@ -649,9 +649,9 @@ define <4 x i32> @sextload_v4i16_v4i32(<4 x i16>* %x) { ; CHECK-LABEL: sextload_v4i16_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: vsext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load <4 x i16>, <4 x i16>* %x %z = sext <4 x i16> %y to <4 x i32> @@ -662,9 +662,9 @@ define <4 x i32> @zextload_v4i16_v4i32(<4 x i16>* %x) { ; CHECK-LABEL: zextload_v4i16_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load <4 x i16>, <4 x i16>* %x %z = zext <4 x i16> %y to <4 x i32> @@ -675,20 +675,20 @@ define <4 x i64> @sextload_v4i16_v4i64(<4 x i16>* %x) { ; LMULMAX1-LABEL: sextload_v4i16_v4i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v10, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v9, v26 -; LMULMAX1-NEXT: vsext.vf4 v8, v25 +; LMULMAX1-NEXT: vsext.vf4 v9, v8 +; LMULMAX1-NEXT: vsext.vf4 v8, v10 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v4i16_v4i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX4-NEXT: vle16.v v25, (a0) +; LMULMAX4-NEXT: vle16.v v10, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; LMULMAX4-NEXT: vsext.vf4 v8, v25 +; LMULMAX4-NEXT: vsext.vf4 v8, v10 ; LMULMAX4-NEXT: ret %y = load <4 x i16>, <4 x i16>* %x %z = sext <4 x i16> %y to <4 x i64> @@ -699,20 +699,20 @@ define <4 x i64> @zextload_v4i16_v4i64(<4 x i16>* %x) { ; LMULMAX1-LABEL: zextload_v4i16_v4i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v10, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v9, v26 -; LMULMAX1-NEXT: vzext.vf4 v8, v25 +; LMULMAX1-NEXT: vzext.vf4 v9, v8 +; LMULMAX1-NEXT: vzext.vf4 v8, v10 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v4i16_v4i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX4-NEXT: vle16.v v25, (a0) +; LMULMAX4-NEXT: vle16.v v10, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; LMULMAX4-NEXT: vzext.vf4 v8, v25 +; LMULMAX4-NEXT: vzext.vf4 v8, v10 ; LMULMAX4-NEXT: ret %y = load <4 x i16>, <4 x i16>* %x %z = zext <4 x i16> %y to <4 x i64> @@ -723,8 +723,8 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, <8 x i8>* %z) { ; CHECK-LABEL: truncstore_v8i16_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %y = trunc <8 x i16> %x to <8 x i8> store <8 x i8> %y, <8 x i8>* %z @@ -735,20 +735,20 @@ define <8 x i32> @sextload_v8i16_v8i32(<8 x i16>* %x) { ; LMULMAX1-LABEL: sextload_v8i16_v8i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v10, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf2 v9, v26 -; LMULMAX1-NEXT: vsext.vf2 v8, v25 +; LMULMAX1-NEXT: vsext.vf2 v9, v8 +; LMULMAX1-NEXT: vsext.vf2 v8, v10 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v8i16_v8i32: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX4-NEXT: vle16.v v25, (a0) +; LMULMAX4-NEXT: vle16.v v10, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; LMULMAX4-NEXT: vsext.vf2 v8, v25 +; LMULMAX4-NEXT: vsext.vf2 v8, v10 ; LMULMAX4-NEXT: ret %y = load <8 x i16>, <8 x i16>* %x %z = sext <8 x i16> %y to <8 x i32> @@ -759,20 +759,20 @@ define <8 x i32> @zextload_v8i16_v8i32(<8 x i16>* %x) { ; LMULMAX1-LABEL: zextload_v8i16_v8i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v10, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf2 v9, v26 -; LMULMAX1-NEXT: vzext.vf2 v8, v25 +; LMULMAX1-NEXT: vzext.vf2 v9, v8 +; LMULMAX1-NEXT: vzext.vf2 v8, v10 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v8i16_v8i32: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX4-NEXT: vle16.v v25, (a0) +; LMULMAX4-NEXT: vle16.v v10, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; LMULMAX4-NEXT: vzext.vf2 v8, v25 +; LMULMAX4-NEXT: vzext.vf2 v8, v10 ; LMULMAX4-NEXT: ret %y = load <8 x i16>, <8 x i16>* %x %z = zext <8 x i16> %y to <8 x i32> @@ -783,28 +783,28 @@ define <8 x i64> @sextload_v8i16_v8i64(<8 x i16>* %x) { ; LMULMAX1-LABEL: sextload_v8i16_v8i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v12, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v10, v26 +; LMULMAX1-NEXT: vsext.vf4 v10, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v9, v27 +; LMULMAX1-NEXT: vsext.vf4 v9, v11 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v11, v26 -; LMULMAX1-NEXT: vsext.vf4 v8, v25 +; LMULMAX1-NEXT: vsext.vf4 v11, v8 +; LMULMAX1-NEXT: vsext.vf4 v8, v12 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v8i16_v8i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX4-NEXT: vle16.v v25, (a0) +; LMULMAX4-NEXT: vle16.v v12, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; LMULMAX4-NEXT: vsext.vf4 v8, v25 +; LMULMAX4-NEXT: vsext.vf4 v8, v12 ; LMULMAX4-NEXT: ret %y = load <8 x i16>, <8 x i16>* %x %z = sext <8 x i16> %y to <8 x i64> @@ -815,28 +815,28 @@ define <8 x i64> @zextload_v8i16_v8i64(<8 x i16>* %x) { ; LMULMAX1-LABEL: zextload_v8i16_v8i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v12, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v10, v26 +; LMULMAX1-NEXT: vzext.vf4 v10, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v9, v27 +; LMULMAX1-NEXT: vzext.vf4 v9, v11 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v11, v26 -; LMULMAX1-NEXT: vzext.vf4 v8, v25 +; LMULMAX1-NEXT: vzext.vf4 v11, v8 +; LMULMAX1-NEXT: vzext.vf4 v8, v12 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v8i16_v8i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX4-NEXT: vle16.v v25, (a0) +; LMULMAX4-NEXT: vle16.v v12, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; LMULMAX4-NEXT: vzext.vf4 v8, v25 +; LMULMAX4-NEXT: vzext.vf4 v8, v12 ; LMULMAX4-NEXT: ret %y = load <8 x i16>, <8 x i16>* %x %z = zext <8 x i16> %y to <8 x i64> @@ -847,23 +847,23 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, <16 x i8>* %z) { ; LMULMAX1-LABEL: truncstore_v16i16_v16i8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v10, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 8 -; LMULMAX1-NEXT: vse8.v v26, (a0) +; LMULMAX1-NEXT: vslideup.vi v10, v8, 8 +; LMULMAX1-NEXT: vse8.v v10, (a0) ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v16i16_v16i8: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0 -; LMULMAX4-NEXT: vse8.v v25, (a0) +; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 +; LMULMAX4-NEXT: vse8.v v10, (a0) ; LMULMAX4-NEXT: ret %y = trunc <16 x i16> %x to <16 x i8> store <16 x i8> %y, <16 x i8>* %z @@ -874,27 +874,27 @@ define <16 x i32> @sextload_v16i16_v16i32(<16 x i16>* %x) { ; LMULMAX1-LABEL: sextload_v16i16_v16i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v10, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vle16.v v26, (a0) +; LMULMAX1-NEXT: vle16.v v12, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf2 v9, v27 +; LMULMAX1-NEXT: vsext.vf2 v9, v8 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v26, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf2 v11, v27 -; LMULMAX1-NEXT: vsext.vf2 v8, v25 -; LMULMAX1-NEXT: vsext.vf2 v10, v26 +; LMULMAX1-NEXT: vsext.vf2 v11, v8 +; LMULMAX1-NEXT: vsext.vf2 v8, v10 +; LMULMAX1-NEXT: vsext.vf2 v10, v12 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v16i16_v16i32: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX4-NEXT: vle16.v v26, (a0) +; LMULMAX4-NEXT: vle16.v v12, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m4, ta, mu -; LMULMAX4-NEXT: vsext.vf2 v8, v26 +; LMULMAX4-NEXT: vsext.vf2 v8, v12 ; LMULMAX4-NEXT: ret %y = load <16 x i16>, <16 x i16>* %x %z = sext <16 x i16> %y to <16 x i32> @@ -905,27 +905,27 @@ define <16 x i32> @zextload_v16i16_v16i32(<16 x i16>* %x) { ; LMULMAX1-LABEL: zextload_v16i16_v16i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v10, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vle16.v v26, (a0) +; LMULMAX1-NEXT: vle16.v v12, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf2 v9, v27 +; LMULMAX1-NEXT: vzext.vf2 v9, v8 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v26, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf2 v11, v27 -; LMULMAX1-NEXT: vzext.vf2 v8, v25 -; LMULMAX1-NEXT: vzext.vf2 v10, v26 +; LMULMAX1-NEXT: vzext.vf2 v11, v8 +; LMULMAX1-NEXT: vzext.vf2 v8, v10 +; LMULMAX1-NEXT: vzext.vf2 v10, v12 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v16i16_v16i32: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX4-NEXT: vle16.v v26, (a0) +; LMULMAX4-NEXT: vle16.v v12, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m4, ta, mu -; LMULMAX4-NEXT: vzext.vf2 v8, v26 +; LMULMAX4-NEXT: vzext.vf2 v8, v12 ; LMULMAX4-NEXT: ret %y = load <16 x i16>, <16 x i16>* %x %z = zext <16 x i16> %y to <16 x i32> @@ -936,46 +936,46 @@ define <16 x i64> @sextload_v16i16_v16i64(<16 x i16>* %x) { ; LMULMAX1-LABEL: sextload_v16i16_v16i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v12, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vle16.v v26, (a0) +; LMULMAX1-NEXT: vle16.v v16, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v10, v27 +; LMULMAX1-NEXT: vsext.vf4 v10, v8 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v28, v26, 4 +; LMULMAX1-NEXT: vslidedown.vi v15, v16, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v14, v28 +; LMULMAX1-NEXT: vsext.vf4 v14, v15 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v29, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v9, v29 +; LMULMAX1-NEXT: vsext.vf4 v9, v11 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v27, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v11, v27 +; LMULMAX1-NEXT: vsext.vf4 v11, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v16, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v13, v27 +; LMULMAX1-NEXT: vsext.vf4 v13, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v28, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v15, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v15, v27 -; LMULMAX1-NEXT: vsext.vf4 v8, v25 -; LMULMAX1-NEXT: vsext.vf4 v12, v26 +; LMULMAX1-NEXT: vsext.vf4 v15, v8 +; LMULMAX1-NEXT: vsext.vf4 v8, v12 +; LMULMAX1-NEXT: vsext.vf4 v12, v16 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v16i16_v16i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX4-NEXT: vle16.v v26, (a0) +; LMULMAX4-NEXT: vle16.v v16, (a0) ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m2, ta, mu -; LMULMAX4-NEXT: vslidedown.vi v28, v26, 8 +; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; LMULMAX4-NEXT: vsext.vf4 v12, v28 -; LMULMAX4-NEXT: vsext.vf4 v8, v26 +; LMULMAX4-NEXT: vsext.vf4 v12, v8 +; LMULMAX4-NEXT: vsext.vf4 v8, v16 ; LMULMAX4-NEXT: ret %y = load <16 x i16>, <16 x i16>* %x %z = sext <16 x i16> %y to <16 x i64> @@ -986,46 +986,46 @@ define <16 x i64> @zextload_v16i16_v16i64(<16 x i16>* %x) { ; LMULMAX1-LABEL: zextload_v16i16_v16i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v12, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vle16.v v26, (a0) +; LMULMAX1-NEXT: vle16.v v16, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v8, v12, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v10, v27 +; LMULMAX1-NEXT: vzext.vf4 v10, v8 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v28, v26, 4 +; LMULMAX1-NEXT: vslidedown.vi v15, v16, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v14, v28 +; LMULMAX1-NEXT: vzext.vf4 v14, v15 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v29, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v11, v12, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v9, v29 +; LMULMAX1-NEXT: vzext.vf4 v9, v11 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v27, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v11, v27 +; LMULMAX1-NEXT: vzext.vf4 v11, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v16, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v13, v27 +; LMULMAX1-NEXT: vzext.vf4 v13, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v28, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v15, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v15, v27 -; LMULMAX1-NEXT: vzext.vf4 v8, v25 -; LMULMAX1-NEXT: vzext.vf4 v12, v26 +; LMULMAX1-NEXT: vzext.vf4 v15, v8 +; LMULMAX1-NEXT: vzext.vf4 v8, v12 +; LMULMAX1-NEXT: vzext.vf4 v12, v16 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v16i16_v16i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX4-NEXT: vle16.v v26, (a0) +; LMULMAX4-NEXT: vle16.v v16, (a0) ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m2, ta, mu -; LMULMAX4-NEXT: vslidedown.vi v28, v26, 8 +; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; LMULMAX4-NEXT: vzext.vf4 v12, v28 -; LMULMAX4-NEXT: vzext.vf4 v8, v26 +; LMULMAX4-NEXT: vzext.vf4 v12, v8 +; LMULMAX4-NEXT: vzext.vf4 v8, v16 ; LMULMAX4-NEXT: ret %y = load <16 x i16>, <16 x i16>* %x %z = zext <16 x i16> %y to <16 x i64> @@ -1036,10 +1036,10 @@ define void @truncstore_v2i32_v2i8(<2 x i32> %x, <2 x i8>* %z) { ; CHECK-LABEL: truncstore_v2i32_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %y = trunc <2 x i32> %x to <2 x i8> store <2 x i8> %y, <2 x i8>* %z @@ -1050,8 +1050,8 @@ define void @truncstore_v2i32_v2i16(<2 x i32> %x, <2 x i16>* %z) { ; CHECK-LABEL: truncstore_v2i32_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %y = trunc <2 x i32> %x to <2 x i16> store <2 x i16> %y, <2 x i16>* %z @@ -1062,9 +1062,9 @@ define <2 x i64> @sextload_v2i32_v2i64(<2 x i32>* %x) { ; CHECK-LABEL: sextload_v2i32_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v8, v25 +; CHECK-NEXT: vsext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load <2 x i32>, <2 x i32>* %x %z = sext <2 x i32> %y to <2 x i64> @@ -1075,9 +1075,9 @@ define <2 x i64> @zextload_v2i32_v2i64(<2 x i32>* %x) { ; CHECK-LABEL: zextload_v2i32_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v8, v25 +; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret %y = load <2 x i32>, <2 x i32>* %x %z = zext <2 x i32> %y to <2 x i64> @@ -1088,10 +1088,10 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, <4 x i8>* %z) { ; CHECK-LABEL: truncstore_v4i32_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %y = trunc <4 x i32> %x to <4 x i8> store <4 x i8> %y, <4 x i8>* %z @@ -1102,8 +1102,8 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, <4 x i16>* %z) { ; CHECK-LABEL: truncstore_v4i32_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %y = trunc <4 x i32> %x to <4 x i16> store <4 x i16> %y, <4 x i16>* %z @@ -1114,20 +1114,20 @@ define <4 x i64> @sextload_v4i32_v4i64(<4 x i32>* %x) { ; LMULMAX1-LABEL: sextload_v4i32_v4i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a0) +; LMULMAX1-NEXT: vle32.v v10, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf2 v9, v26 -; LMULMAX1-NEXT: vsext.vf2 v8, v25 +; LMULMAX1-NEXT: vsext.vf2 v9, v8 +; LMULMAX1-NEXT: vsext.vf2 v8, v10 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v4i32_v4i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX4-NEXT: vle32.v v25, (a0) +; LMULMAX4-NEXT: vle32.v v10, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; LMULMAX4-NEXT: vsext.vf2 v8, v25 +; LMULMAX4-NEXT: vsext.vf2 v8, v10 ; LMULMAX4-NEXT: ret %y = load <4 x i32>, <4 x i32>* %x %z = sext <4 x i32> %y to <4 x i64> @@ -1138,20 +1138,20 @@ define <4 x i64> @zextload_v4i32_v4i64(<4 x i32>* %x) { ; LMULMAX1-LABEL: zextload_v4i32_v4i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a0) +; LMULMAX1-NEXT: vle32.v v10, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf2 v9, v26 -; LMULMAX1-NEXT: vzext.vf2 v8, v25 +; LMULMAX1-NEXT: vzext.vf2 v9, v8 +; LMULMAX1-NEXT: vzext.vf2 v8, v10 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v4i32_v4i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX4-NEXT: vle32.v v25, (a0) +; LMULMAX4-NEXT: vle32.v v10, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; LMULMAX4-NEXT: vzext.vf2 v8, v25 +; LMULMAX4-NEXT: vzext.vf2 v8, v10 ; LMULMAX4-NEXT: ret %y = load <4 x i32>, <4 x i32>* %x %z = zext <4 x i32> %y to <4 x i64> @@ -1162,29 +1162,29 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, <8 x i8>* %z) { ; LMULMAX1-LABEL: truncstore_v8i32_v8i8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v10, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 4 -; LMULMAX1-NEXT: vse8.v v26, (a0) +; LMULMAX1-NEXT: vslideup.vi v10, v8, 4 +; LMULMAX1-NEXT: vse8.v v10, (a0) ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v8i32_v8i8: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0 -; LMULMAX4-NEXT: vse8.v v25, (a0) +; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0 +; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: ret %y = trunc <8 x i32> %x to <8 x i8> store <8 x i8> %y, <8 x i8>* %z @@ -1195,23 +1195,23 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, <8 x i16>* %z) { ; LMULMAX1-LABEL: truncstore_v8i32_v8i16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v10, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 4 -; LMULMAX1-NEXT: vse16.v v26, (a0) +; LMULMAX1-NEXT: vslideup.vi v10, v8, 4 +; LMULMAX1-NEXT: vse16.v v10, (a0) ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v8i32_v8i16: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0 -; LMULMAX4-NEXT: vse16.v v25, (a0) +; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 +; LMULMAX4-NEXT: vse16.v v10, (a0) ; LMULMAX4-NEXT: ret %y = trunc <8 x i32> %x to <8 x i16> store <8 x i16> %y, <8 x i16>* %z @@ -1222,27 +1222,27 @@ define <8 x i64> @sextload_v8i32_v8i64(<8 x i32>* %x) { ; LMULMAX1-LABEL: sextload_v8i32_v8i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a0) +; LMULMAX1-NEXT: vle32.v v10, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vle32.v v26, (a0) +; LMULMAX1-NEXT: vle32.v v12, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf2 v9, v27 +; LMULMAX1-NEXT: vsext.vf2 v9, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v12, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf2 v11, v27 -; LMULMAX1-NEXT: vsext.vf2 v8, v25 -; LMULMAX1-NEXT: vsext.vf2 v10, v26 +; LMULMAX1-NEXT: vsext.vf2 v11, v8 +; LMULMAX1-NEXT: vsext.vf2 v8, v10 +; LMULMAX1-NEXT: vsext.vf2 v10, v12 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v8i32_v8i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX4-NEXT: vle32.v v26, (a0) +; LMULMAX4-NEXT: vle32.v v12, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; LMULMAX4-NEXT: vsext.vf2 v8, v26 +; LMULMAX4-NEXT: vsext.vf2 v8, v12 ; LMULMAX4-NEXT: ret %y = load <8 x i32>, <8 x i32>* %x %z = sext <8 x i32> %y to <8 x i64> @@ -1253,27 +1253,27 @@ define <8 x i64> @zextload_v8i32_v8i64(<8 x i32>* %x) { ; LMULMAX1-LABEL: zextload_v8i32_v8i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a0) +; LMULMAX1-NEXT: vle32.v v10, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vle32.v v26, (a0) +; LMULMAX1-NEXT: vle32.v v12, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf2 v9, v27 +; LMULMAX1-NEXT: vzext.vf2 v9, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v12, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf2 v11, v27 -; LMULMAX1-NEXT: vzext.vf2 v8, v25 -; LMULMAX1-NEXT: vzext.vf2 v10, v26 +; LMULMAX1-NEXT: vzext.vf2 v11, v8 +; LMULMAX1-NEXT: vzext.vf2 v8, v10 +; LMULMAX1-NEXT: vzext.vf2 v10, v12 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v8i32_v8i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX4-NEXT: vle32.v v26, (a0) +; LMULMAX4-NEXT: vle32.v v12, (a0) ; LMULMAX4-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; LMULMAX4-NEXT: vzext.vf2 v8, v26 +; LMULMAX4-NEXT: vzext.vf2 v8, v12 ; LMULMAX4-NEXT: ret %y = load <8 x i32>, <8 x i32>* %x %z = zext <8 x i32> %y to <8 x i64> @@ -1284,41 +1284,41 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, <16 x i8>* %z) { ; LMULMAX1-LABEL: truncstore_v16i32_v16i8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v12, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v12, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 4 +; LMULMAX1-NEXT: vslideup.vi v12, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v10, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 12, e8, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 8 +; LMULMAX1-NEXT: vslideup.vi v12, v8, 8 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v11, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 12 -; LMULMAX1-NEXT: vse8.v v26, (a0) +; LMULMAX1-NEXT: vslideup.vi v12, v8, 12 +; LMULMAX1-NEXT: vse8.v v12, (a0) ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v16i32_v16i8: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0 +; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v26, 0 -; LMULMAX4-NEXT: vse8.v v25, (a0) +; LMULMAX4-NEXT: vnsrl.wi v8, v12, 0 +; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: ret %y = trunc <16 x i32> %x to <16 x i8> store <16 x i8> %y, <16 x i8>* %z @@ -1329,34 +1329,34 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, <16 x i16>* %z) { ; LMULMAX1-LABEL: truncstore_v16i32_v16i16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v12, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu -; LMULMAX1-NEXT: vmv1r.v v27, v26 -; LMULMAX1-NEXT: vslideup.vi v27, v25, 0 +; LMULMAX1-NEXT: vmv1r.v v13, v12 +; LMULMAX1-NEXT: vslideup.vi v13, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v27, v25, 4 +; LMULMAX1-NEXT: vslideup.vi v13, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v10, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v12, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v11, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 4 +; LMULMAX1-NEXT: vslideup.vi v12, v8, 4 ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vse16.v v26, (a1) -; LMULMAX1-NEXT: vse16.v v27, (a0) +; LMULMAX1-NEXT: vse16.v v12, (a1) +; LMULMAX1-NEXT: vse16.v v13, (a0) ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v16i32_v16i16: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0 -; LMULMAX4-NEXT: vse16.v v26, (a0) +; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 +; LMULMAX4-NEXT: vse16.v v12, (a0) ; LMULMAX4-NEXT: ret %y = trunc <16 x i32> %x to <16 x i16> store <16 x i16> %y, <16 x i16>* %z @@ -1368,43 +1368,43 @@ define <16 x i64> @sextload_v16i32_v16i64(<16 x i32>* %x) { ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: addi a1, a0, 48 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a1) +; LMULMAX1-NEXT: vle32.v v16, (a1) ; LMULMAX1-NEXT: addi a1, a0, 32 -; LMULMAX1-NEXT: vle32.v v26, (a1) -; LMULMAX1-NEXT: vle32.v v27, (a0) +; LMULMAX1-NEXT: vle32.v v14, (a1) +; LMULMAX1-NEXT: vle32.v v10, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vle32.v v28, (a0) +; LMULMAX1-NEXT: vle32.v v12, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v29, v27, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf2 v9, v29 +; LMULMAX1-NEXT: vsext.vf2 v9, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v29, v28, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v12, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf2 v11, v29 +; LMULMAX1-NEXT: vsext.vf2 v11, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v29, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v14, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf2 v13, v29 +; LMULMAX1-NEXT: vsext.vf2 v13, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v29, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v16, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf2 v15, v29 -; LMULMAX1-NEXT: vsext.vf2 v8, v27 -; LMULMAX1-NEXT: vsext.vf2 v10, v28 -; LMULMAX1-NEXT: vsext.vf2 v12, v26 -; LMULMAX1-NEXT: vsext.vf2 v14, v25 +; LMULMAX1-NEXT: vsext.vf2 v15, v8 +; LMULMAX1-NEXT: vsext.vf2 v8, v10 +; LMULMAX1-NEXT: vsext.vf2 v10, v12 +; LMULMAX1-NEXT: vsext.vf2 v12, v14 +; LMULMAX1-NEXT: vsext.vf2 v14, v16 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: sextload_v16i32_v16i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; LMULMAX4-NEXT: vle32.v v28, (a0) +; LMULMAX4-NEXT: vle32.v v16, (a0) ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m4, ta, mu -; LMULMAX4-NEXT: vslidedown.vi v8, v28, 8 +; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; LMULMAX4-NEXT: vsext.vf2 v12, v8 -; LMULMAX4-NEXT: vsext.vf2 v8, v28 +; LMULMAX4-NEXT: vsext.vf2 v8, v16 ; LMULMAX4-NEXT: ret %y = load <16 x i32>, <16 x i32>* %x %z = sext <16 x i32> %y to <16 x i64> @@ -1416,43 +1416,43 @@ define <16 x i64> @zextload_v16i32_v16i64(<16 x i32>* %x) { ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: addi a1, a0, 48 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a1) +; LMULMAX1-NEXT: vle32.v v16, (a1) ; LMULMAX1-NEXT: addi a1, a0, 32 -; LMULMAX1-NEXT: vle32.v v26, (a1) -; LMULMAX1-NEXT: vle32.v v27, (a0) +; LMULMAX1-NEXT: vle32.v v14, (a1) +; LMULMAX1-NEXT: vle32.v v10, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vle32.v v28, (a0) +; LMULMAX1-NEXT: vle32.v v12, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v29, v27, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf2 v9, v29 +; LMULMAX1-NEXT: vzext.vf2 v9, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v29, v28, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v12, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf2 v11, v29 +; LMULMAX1-NEXT: vzext.vf2 v11, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v29, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v14, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf2 v13, v29 +; LMULMAX1-NEXT: vzext.vf2 v13, v8 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v29, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v16, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf2 v15, v29 -; LMULMAX1-NEXT: vzext.vf2 v8, v27 -; LMULMAX1-NEXT: vzext.vf2 v10, v28 -; LMULMAX1-NEXT: vzext.vf2 v12, v26 -; LMULMAX1-NEXT: vzext.vf2 v14, v25 +; LMULMAX1-NEXT: vzext.vf2 v15, v8 +; LMULMAX1-NEXT: vzext.vf2 v8, v10 +; LMULMAX1-NEXT: vzext.vf2 v10, v12 +; LMULMAX1-NEXT: vzext.vf2 v12, v14 +; LMULMAX1-NEXT: vzext.vf2 v14, v16 ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: zextload_v16i32_v16i64: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; LMULMAX4-NEXT: vle32.v v28, (a0) +; LMULMAX4-NEXT: vle32.v v16, (a0) ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m4, ta, mu -; LMULMAX4-NEXT: vslidedown.vi v8, v28, 8 +; LMULMAX4-NEXT: vslidedown.vi v8, v16, 8 ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; LMULMAX4-NEXT: vzext.vf2 v12, v8 -; LMULMAX4-NEXT: vzext.vf2 v8, v28 +; LMULMAX4-NEXT: vzext.vf2 v8, v16 ; LMULMAX4-NEXT: ret %y = load <16 x i32>, <16 x i32>* %x %z = zext <16 x i32> %y to <16 x i64> @@ -1463,12 +1463,12 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %z) { ; CHECK-LABEL: truncstore_v2i64_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %y = trunc <2 x i64> %x to <2 x i8> store <2 x i8> %y, <2 x i8>* %z @@ -1479,10 +1479,10 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, <2 x i16>* %z) { ; CHECK-LABEL: truncstore_v2i64_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %y = trunc <2 x i64> %x to <2 x i16> store <2 x i16> %y, <2 x i16>* %z @@ -1493,8 +1493,8 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %z) { ; CHECK-LABEL: truncstore_v2i64_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %y = trunc <2 x i64> %x to <2 x i32> store <2 x i32> %y, <2 x i32>* %z @@ -1505,35 +1505,35 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, <4 x i8>* %z) { ; LMULMAX1-LABEL: truncstore_v4i64_v4i8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v10, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 -; LMULMAX1-NEXT: vse8.v v26, (a0) +; LMULMAX1-NEXT: vslideup.vi v10, v8, 2 +; LMULMAX1-NEXT: vse8.v v10, (a0) ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v4i64_v4i8: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX4-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0 -; LMULMAX4-NEXT: vse8.v v25, (a0) +; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0 +; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: ret %y = trunc <4 x i64> %x to <4 x i8> store <4 x i8> %y, <4 x i8>* %z @@ -1544,29 +1544,29 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, <4 x i16>* %z) { ; LMULMAX1-LABEL: truncstore_v4i64_v4i16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v10, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 -; LMULMAX1-NEXT: vse16.v v26, (a0) +; LMULMAX1-NEXT: vslideup.vi v10, v8, 2 +; LMULMAX1-NEXT: vse16.v v10, (a0) ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v4i64_v4i16: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX4-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0 -; LMULMAX4-NEXT: vse16.v v25, (a0) +; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0 +; LMULMAX4-NEXT: vse16.v v8, (a0) ; LMULMAX4-NEXT: ret %y = trunc <4 x i64> %x to <4 x i16> store <4 x i16> %y, <4 x i16>* %z @@ -1577,23 +1577,23 @@ define void @truncstore_v4i64_v4i32(<4 x i64> %x, <4 x i32>* %z) { ; LMULMAX1-LABEL: truncstore_v4i64_v4i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v10, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 -; LMULMAX1-NEXT: vse32.v v26, (a0) +; LMULMAX1-NEXT: vslideup.vi v10, v8, 2 +; LMULMAX1-NEXT: vse32.v v10, (a0) ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v4i64_v4i32: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v8, 0 -; LMULMAX4-NEXT: vse32.v v25, (a0) +; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 +; LMULMAX4-NEXT: vse32.v v10, (a0) ; LMULMAX4-NEXT: ret %y = trunc <4 x i64> %x to <4 x i32> store <4 x i32> %y, <4 x i32>* %z @@ -1604,51 +1604,51 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, <8 x i8>* %z) { ; LMULMAX1-LABEL: truncstore_v8i64_v8i8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v12, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v12, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 +; LMULMAX1-NEXT: vslideup.vi v12, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v10, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 4 +; LMULMAX1-NEXT: vslideup.vi v12, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v11, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 6 -; LMULMAX1-NEXT: vse8.v v26, (a0) +; LMULMAX1-NEXT: vslideup.vi v12, v8, 6 +; LMULMAX1-NEXT: vse8.v v12, (a0) ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v8i64_v8i8: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0 +; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v26, 0 +; LMULMAX4-NEXT: vnsrl.wi v8, v12, 0 ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0 -; LMULMAX4-NEXT: vse8.v v25, (a0) +; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0 +; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: ret %y = trunc <8 x i64> %x to <8 x i8> store <8 x i8> %y, <8 x i8>* %z @@ -1659,41 +1659,41 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, <8 x i16>* %z) { ; LMULMAX1-LABEL: truncstore_v8i64_v8i16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v12, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v12, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 +; LMULMAX1-NEXT: vslideup.vi v12, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v10, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 4 +; LMULMAX1-NEXT: vslideup.vi v12, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v11, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 6 -; LMULMAX1-NEXT: vse16.v v26, (a0) +; LMULMAX1-NEXT: vslideup.vi v12, v8, 6 +; LMULMAX1-NEXT: vse16.v v12, (a0) ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v8i64_v8i16: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0 +; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v26, 0 -; LMULMAX4-NEXT: vse16.v v25, (a0) +; LMULMAX4-NEXT: vnsrl.wi v8, v12, 0 +; LMULMAX4-NEXT: vse16.v v8, (a0) ; LMULMAX4-NEXT: ret %y = trunc <8 x i64> %x to <8 x i16> store <8 x i16> %y, <8 x i16>* %z @@ -1704,34 +1704,34 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, <8 x i32>* %z) { ; LMULMAX1-LABEL: truncstore_v8i64_v8i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v12, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu -; LMULMAX1-NEXT: vmv1r.v v27, v26 -; LMULMAX1-NEXT: vslideup.vi v27, v25, 0 +; LMULMAX1-NEXT: vmv1r.v v13, v12 +; LMULMAX1-NEXT: vslideup.vi v13, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v27, v25, 2 +; LMULMAX1-NEXT: vslideup.vi v13, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v10, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v12, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v11, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 +; LMULMAX1-NEXT: vslideup.vi v12, v8, 2 ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vse32.v v26, (a1) -; LMULMAX1-NEXT: vse32.v v27, (a0) +; LMULMAX1-NEXT: vse32.v v12, (a1) +; LMULMAX1-NEXT: vse32.v v13, (a0) ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v8i64_v8i32: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0 -; LMULMAX4-NEXT: vse32.v v26, (a0) +; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 +; LMULMAX4-NEXT: vse32.v v12, (a0) ; LMULMAX4-NEXT: ret %y = trunc <8 x i64> %x to <8 x i32> store <8 x i32> %y, <8 x i32>* %z @@ -1742,95 +1742,95 @@ define void @truncstore_v16i64_v16i8(<16 x i64> %x, <16 x i8>* %z) { ; LMULMAX1-LABEL: truncstore_v16i64_v16i8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v16, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v25, 0 +; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v26, 0 +; LMULMAX1-NEXT: vslideup.vi v8, v16, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v9, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v26, 2 +; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v10, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 6, e8, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v26, 4 +; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v11, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v26, 6 +; LMULMAX1-NEXT: vslideup.vi v8, v9, 6 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v12, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v12, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 10, e8, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v26, 8 +; LMULMAX1-NEXT: vslideup.vi v8, v9, 8 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v13, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v13, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 12, e8, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v26, 10 +; LMULMAX1-NEXT: vslideup.vi v8, v9, 10 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v14, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v14, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 14, e8, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v26, 12 +; LMULMAX1-NEXT: vslideup.vi v8, v9, 12 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v15, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v15, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v26, 14 -; LMULMAX1-NEXT: vse8.v v25, (a0) +; LMULMAX1-NEXT: vslideup.vi v8, v9, 14 +; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v16i64_v16i8: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0 +; LMULMAX4-NEXT: vnsrl.wi v16, v8, 0 ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v26, 0 +; LMULMAX4-NEXT: vnsrl.wi v8, v16, 0 ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX4-NEXT: vmv.v.i v26, 0 +; LMULMAX4-NEXT: vmv.v.i v9, 0 ; LMULMAX4-NEXT: vsetivli zero, 8, e8, m1, tu, mu -; LMULMAX4-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX4-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v28, v12, 0 +; LMULMAX4-NEXT: vnsrl.wi v10, v12, 0 ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v28, 0 +; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, tu, mu -; LMULMAX4-NEXT: vslideup.vi v26, v25, 8 -; LMULMAX4-NEXT: vse8.v v26, (a0) +; LMULMAX4-NEXT: vslideup.vi v9, v8, 8 +; LMULMAX4-NEXT: vse8.v v9, (a0) ; LMULMAX4-NEXT: ret %y = trunc <16 x i64> %x to <16 x i8> store <16 x i8> %y, <16 x i8>* %z @@ -1841,78 +1841,78 @@ define void @truncstore_v16i64_v16i16(<16 x i64> %x, <16 x i16>* %z) { ; LMULMAX1-LABEL: truncstore_v16i64_v16i16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v16, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu -; LMULMAX1-NEXT: vmv1r.v v27, v26 -; LMULMAX1-NEXT: vslideup.vi v27, v25, 0 +; LMULMAX1-NEXT: vmv1r.v v17, v16 +; LMULMAX1-NEXT: vslideup.vi v17, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v27, v25, 2 +; LMULMAX1-NEXT: vslideup.vi v17, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v10, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v27, v25, 4 +; LMULMAX1-NEXT: vslideup.vi v17, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v11, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v27, v25, 6 +; LMULMAX1-NEXT: vslideup.vi v17, v8, 6 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v12, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v12, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v16, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v13, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v13, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 +; LMULMAX1-NEXT: vslideup.vi v16, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v14, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v14, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 4 +; LMULMAX1-NEXT: vslideup.vi v16, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v15, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v15, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 6 +; LMULMAX1-NEXT: vslideup.vi v16, v8, 6 ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vse16.v v26, (a1) -; LMULMAX1-NEXT: vse16.v v27, (a0) +; LMULMAX1-NEXT: vse16.v v16, (a1) +; LMULMAX1-NEXT: vse16.v v17, (a0) ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v16i64_v16i16: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v26, v12, 0 +; LMULMAX4-NEXT: vnsrl.wi v16, v12, 0 ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v28, v26, 0 +; LMULMAX4-NEXT: vnsrl.wi v12, v16, 0 ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v26, v8, 0 +; LMULMAX4-NEXT: vnsrl.wi v14, v8, 0 ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v30, v26, 0 +; LMULMAX4-NEXT: vnsrl.wi v8, v14, 0 ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX4-NEXT: vmv.v.i v26, 0 +; LMULMAX4-NEXT: vmv.v.i v10, 0 ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m2, tu, mu -; LMULMAX4-NEXT: vslideup.vi v26, v30, 0 +; LMULMAX4-NEXT: vslideup.vi v10, v8, 0 ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, tu, mu -; LMULMAX4-NEXT: vslideup.vi v26, v28, 8 -; LMULMAX4-NEXT: vse16.v v26, (a0) +; LMULMAX4-NEXT: vslideup.vi v10, v12, 8 +; LMULMAX4-NEXT: vse16.v v10, (a0) ; LMULMAX4-NEXT: ret %y = trunc <16 x i64> %x to <16 x i16> store <16 x i16> %y, <16 x i16>* %z @@ -1923,62 +1923,62 @@ define void @truncstore_v16i64_v16i32(<16 x i64> %x, <16 x i32>* %z) { ; LMULMAX1-LABEL: truncstore_v16i64_v16i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v8, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v16, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu -; LMULMAX1-NEXT: vmv1r.v v27, v26 -; LMULMAX1-NEXT: vslideup.vi v27, v25, 0 +; LMULMAX1-NEXT: vmv1r.v v17, v16 +; LMULMAX1-NEXT: vslideup.vi v17, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v9, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v27, v25, 2 +; LMULMAX1-NEXT: vslideup.vi v17, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v10, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu -; LMULMAX1-NEXT: vmv1r.v v28, v26 -; LMULMAX1-NEXT: vslideup.vi v28, v25, 0 +; LMULMAX1-NEXT: vmv1r.v v9, v16 +; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v11, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v28, v25, 2 +; LMULMAX1-NEXT: vslideup.vi v9, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v12, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v12, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu -; LMULMAX1-NEXT: vmv1r.v v29, v26 -; LMULMAX1-NEXT: vslideup.vi v29, v25, 0 +; LMULMAX1-NEXT: vmv1r.v v10, v16 +; LMULMAX1-NEXT: vslideup.vi v10, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v13, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v13, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v25, 2 +; LMULMAX1-NEXT: vslideup.vi v10, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v14, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v14, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v16, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v15, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v15, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 +; LMULMAX1-NEXT: vslideup.vi v16, v8, 2 ; LMULMAX1-NEXT: addi a1, a0, 48 -; LMULMAX1-NEXT: vse32.v v26, (a1) +; LMULMAX1-NEXT: vse32.v v16, (a1) ; LMULMAX1-NEXT: addi a1, a0, 32 -; LMULMAX1-NEXT: vse32.v v29, (a1) +; LMULMAX1-NEXT: vse32.v v10, (a1) ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vse32.v v28, (a1) -; LMULMAX1-NEXT: vse32.v v27, (a0) +; LMULMAX1-NEXT: vse32.v v9, (a1) +; LMULMAX1-NEXT: vse32.v v17, (a0) ; LMULMAX1-NEXT: ret ; ; LMULMAX4-LABEL: truncstore_v16i64_v16i32: ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX4-NEXT: vnsrl.wi v28, v12, 0 +; LMULMAX4-NEXT: vnsrl.wi v16, v12, 0 ; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; LMULMAX4-NEXT: vmv.v.i v8, 0 ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m4, tu, mu ; LMULMAX4-NEXT: vslideup.vi v8, v12, 0 ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, tu, mu -; LMULMAX4-NEXT: vslideup.vi v8, v28, 8 +; LMULMAX4-NEXT: vslideup.vi v8, v16, 8 ; LMULMAX4-NEXT: vse32.v v8, (a0) ; LMULMAX4-NEXT: ret %y = trunc <16 x i64> %x to <16 x i32> @@ -1990,8 +1990,8 @@ define @extload_nxv2f16_nxv2f32(* %x) { ; CHECK-LABEL: extload_nxv2f16_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vfwcvt.f.f.v v8, v9 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2002,10 +2002,10 @@ define @extload_nxv2f16_nxv2f64(* %x) { ; CHECK-LABEL: extload_nxv2f16_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfwcvt.f.f.v v26, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfwcvt.f.f.v v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: vfwcvt.f.f.v v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2015,9 +2015,9 @@ define @extload_nxv2f16_nxv2f64(* %x) { define @extload_nxv4f16_nxv4f32(* %x) { ; CHECK-LABEL: extload_nxv4f16_nxv4f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re16.v v25, (a0) +; CHECK-NEXT: vl1re16.v v10, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: vfwcvt.f.f.v v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2027,11 +2027,11 @@ define @extload_nxv4f16_nxv4f32(* %x) { define @extload_nxv4f16_nxv4f64(* %x) { ; CHECK-LABEL: extload_nxv4f16_nxv4f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re16.v v25, (a0) +; CHECK-NEXT: vl1re16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v26, v25 +; CHECK-NEXT: vfwcvt.f.f.v v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: vfwcvt.f.f.v v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2041,9 +2041,9 @@ define @extload_nxv4f16_nxv4f64(* %x) { define @extload_nxv8f16_nxv8f32(* %x) { ; CHECK-LABEL: extload_nxv8f16_nxv8f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2re16.v v26, (a0) +; CHECK-NEXT: vl2re16.v v12, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: vfwcvt.f.f.v v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2053,11 +2053,11 @@ define @extload_nxv8f16_nxv8f32(* %x) { define @extload_nxv8f16_nxv8f64(* %x) { ; CHECK-LABEL: extload_nxv8f16_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2re16.v v26, (a0) +; CHECK-NEXT: vl2re16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v28, v26 +; CHECK-NEXT: vfwcvt.f.f.v v16, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v28 +; CHECK-NEXT: vfwcvt.f.f.v v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2067,9 +2067,9 @@ define @extload_nxv8f16_nxv8f64(* %x) { define @extload_nxv16f16_nxv16f32(* %x) { ; CHECK-LABEL: extload_nxv16f16_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v28 +; CHECK-NEXT: vfwcvt.f.f.v v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2079,13 +2079,13 @@ define @extload_nxv16f16_nxv16f32(* %x define @extload_nxv16f16_nxv16f64(* %x) { ; CHECK-LABEL: extload_nxv16f16_nxv16f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v16, v28 +; CHECK-NEXT: vfwcvt.f.f.v v20, v16 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v16 +; CHECK-NEXT: vfwcvt.f.f.v v8, v20 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v24, v30 +; CHECK-NEXT: vfwcvt.f.f.v v24, v18 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v16, v24 ; CHECK-NEXT: ret @@ -2098,8 +2098,8 @@ define void @truncstore_nxv2f32_nxv2f16( %x, %x to store %y, * %z @@ -2109,9 +2109,9 @@ define void @truncstore_nxv2f32_nxv2f16( %x, @extload_nxv2f32_nxv2f64(* %x) { ; CHECK-LABEL: extload_nxv2f32_nxv2f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re32.v v25, (a0) +; CHECK-NEXT: vl1re32.v v10, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v25 +; CHECK-NEXT: vfwcvt.f.f.v v8, v10 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2122,8 +2122,8 @@ define void @truncstore_nxv4f32_nxv4f16( %x, %x to store %y, * %z @@ -2133,9 +2133,9 @@ define void @truncstore_nxv4f32_nxv4f16( %x, @extload_nxv4f32_nxv4f64(* %x) { ; CHECK-LABEL: extload_nxv4f32_nxv4f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2re32.v v26, (a0) +; CHECK-NEXT: vl2re32.v v12, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v26 +; CHECK-NEXT: vfwcvt.f.f.v v8, v12 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2146,8 +2146,8 @@ define void @truncstore_nxv8f32_nxv8f16( %x, %x to store %y, * %z @@ -2157,9 +2157,9 @@ define void @truncstore_nxv8f32_nxv8f16( %x, @extload_nxv8f32_nxv8f64(* %x) { ; CHECK-LABEL: extload_nxv8f32_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v8, v28 +; CHECK-NEXT: vfwcvt.f.f.v v8, v16 ; CHECK-NEXT: ret %y = load , * %x %z = fpext %y to @@ -2170,8 +2170,8 @@ define void @truncstore_nxv16f32_nxv16f16( %x, %x to store %y, * %z @@ -2195,10 +2195,10 @@ define void @truncstore_nxv2f64_nxv2f16( %x, %x to store %y, * %z @@ -2209,8 +2209,8 @@ define void @truncstore_nxv2f64_nxv2f32( %x, %x to store %y, * %z @@ -2221,10 +2221,10 @@ define void @truncstore_nxv4f64_nxv4f16( %x, %x to store %y, * %z @@ -2235,8 +2235,8 @@ define void @truncstore_nxv4f64_nxv4f32( %x, %x to store %y, * %z @@ -2247,10 +2247,10 @@ define void @truncstore_nxv8f64_nxv8f16( %x, %x to store %y, * %z @@ -2261,8 +2261,8 @@ define void @truncstore_nxv8f64_nxv8f32( %x, %x to store %y, * %z @@ -2273,13 +2273,13 @@ define void @truncstore_nxv16f64_nxv16f16( %x, %x to diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll index abf94a50a752d34e1c7c7c530f8c6116250c67b0..563171cc57538b9d9f08ed7cc8068667950ee364 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll @@ -6,12 +6,12 @@ define i1 @extractelt_v1i1(<1 x i8>* %x, i64 %idx) nounwind { ; CHECK-LABEL: extractelt_v1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <1 x i8>, <1 x i8>* %x %b = icmp eq <1 x i8> %a, zeroinitializer @@ -23,13 +23,13 @@ define i1 @extractelt_v2i1(<2 x i8>* %x, i64 %idx) nounwind { ; CHECK-LABEL: extractelt_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <2 x i8>, <2 x i8>* %x %b = icmp eq <2 x i8> %a, zeroinitializer @@ -41,13 +41,13 @@ define i1 @extractelt_v4i1(<4 x i8>* %x, i64 %idx) nounwind { ; CHECK-LABEL: extractelt_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %b = icmp eq <4 x i8> %a, zeroinitializer @@ -59,13 +59,13 @@ define i1 @extractelt_v8i1(<8 x i8>* %x, i64 %idx) nounwind { ; CHECK-LABEL: extractelt_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = icmp eq <8 x i8> %a, zeroinitializer @@ -77,13 +77,13 @@ define i1 @extractelt_v16i1(<16 x i8>* %x, i64 %idx) nounwind { ; CHECK-LABEL: extractelt_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = icmp eq <16 x i8> %a, zeroinitializer @@ -96,13 +96,13 @@ define i1 @extractelt_v32i1(<32 x i8>* %x, i64 %idx) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vmseq.vi v0, v26, 0 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v26, a1 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = icmp eq <32 x i8> %a, zeroinitializer @@ -115,13 +115,13 @@ define i1 @extractelt_v64i1(<64 x i8>* %x, i64 %idx) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vmseq.vi v0, v28, 0 -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v28, v28, 1, v0 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu -; CHECK-NEXT: vslidedown.vx v28, v28, a1 -; CHECK-NEXT: vmv.x.s a0, v28 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = icmp eq <64 x i8> %a, zeroinitializer @@ -160,18 +160,18 @@ define i1 @extractelt_v256i1(<256 x i8>* %x, i64 %idx) nounwind { ; RV32-NEXT: addi a2, a0, 128 ; RV32-NEXT: addi a3, zero, 128 ; RV32-NEXT: vsetvli zero, a3, e8, m8, ta, mu -; RV32-NEXT: vle8.v v8, (a0) -; RV32-NEXT: vle8.v v16, (a2) +; RV32-NEXT: vle8.v v16, (a0) +; RV32-NEXT: vle8.v v24, (a2) ; RV32-NEXT: addi a0, sp, 128 ; RV32-NEXT: add a0, a0, a1 -; RV32-NEXT: vmseq.vi v25, v8, 0 -; RV32-NEXT: vmseq.vi v0, v16, 0 -; RV32-NEXT: vmv.v.i v8, 0 -; RV32-NEXT: vmerge.vim v16, v8, 1, v0 +; RV32-NEXT: vmseq.vi v8, v16, 0 +; RV32-NEXT: vmseq.vi v0, v24, 0 +; RV32-NEXT: vmv.v.i v16, 0 +; RV32-NEXT: vmerge.vim v24, v16, 1, v0 ; RV32-NEXT: addi a1, sp, 256 -; RV32-NEXT: vse8.v v16, (a1) -; RV32-NEXT: vmv1r.v v0, v25 -; RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; RV32-NEXT: vse8.v v24, (a1) +; RV32-NEXT: vmv1r.v v0, v8 +; RV32-NEXT: vmerge.vim v8, v16, 1, v0 ; RV32-NEXT: addi a1, sp, 128 ; RV32-NEXT: vse8.v v8, (a1) ; RV32-NEXT: lb a0, 0(a0) @@ -188,18 +188,18 @@ define i1 @extractelt_v256i1(<256 x i8>* %x, i64 %idx) nounwind { ; RV64-NEXT: addi a2, a0, 128 ; RV64-NEXT: addi a3, zero, 128 ; RV64-NEXT: vsetvli zero, a3, e8, m8, ta, mu -; RV64-NEXT: vle8.v v8, (a0) -; RV64-NEXT: vle8.v v16, (a2) +; RV64-NEXT: vle8.v v16, (a0) +; RV64-NEXT: vle8.v v24, (a2) ; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: add a0, a0, a1 -; RV64-NEXT: vmseq.vi v25, v8, 0 -; RV64-NEXT: vmseq.vi v0, v16, 0 -; RV64-NEXT: vmv.v.i v8, 0 -; RV64-NEXT: vmerge.vim v16, v8, 1, v0 +; RV64-NEXT: vmseq.vi v8, v16, 0 +; RV64-NEXT: vmseq.vi v0, v24, 0 +; RV64-NEXT: vmv.v.i v16, 0 +; RV64-NEXT: vmerge.vim v24, v16, 1, v0 ; RV64-NEXT: addi a1, sp, 144 -; RV64-NEXT: vse8.v v16, (a1) -; RV64-NEXT: vmv1r.v v0, v25 -; RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; RV64-NEXT: vse8.v v24, (a1) +; RV64-NEXT: vmv1r.v v0, v8 +; RV64-NEXT: vmerge.vim v8, v16, 1, v0 ; RV64-NEXT: addi a1, sp, 16 ; RV64-NEXT: vse8.v v8, (a1) ; RV64-NEXT: lb a0, 0(a0) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll index 9b0741afe2edb8fb7ec3bdcf8b5b4010799e4a21..690da3979a002b972c266dbfa9b4d263f127ab2e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll @@ -6,9 +6,9 @@ define void @extract_v2i8_v4i8_0(<4 x i8>* %x, <2 x i8>* %y) { ; CHECK-LABEL: extract_v2i8_v4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vse8.v v25, (a1) +; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 0) @@ -20,11 +20,11 @@ define void @extract_v2i8_v4i8_2(<4 x i8>* %x, <2 x i8>* %y) { ; CHECK-LABEL: extract_v2i8_v4i8_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v25, 2 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vse8.v v25, (a1) +; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 2) @@ -36,9 +36,9 @@ define void @extract_v2i8_v8i8_0(<8 x i8>* %x, <2 x i8>* %y) { ; CHECK-LABEL: extract_v2i8_v8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vse8.v v25, (a1) +; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 0) @@ -50,11 +50,11 @@ define void @extract_v2i8_v8i8_6(<8 x i8>* %x, <2 x i8>* %y) { ; CHECK-LABEL: extract_v2i8_v8i8_6: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v25, 6 +; CHECK-NEXT: vslidedown.vi v8, v8, 6 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vse8.v v25, (a1) +; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 6) @@ -66,17 +66,17 @@ define void @extract_v2i32_v8i32_0(<8 x i32>* %x, <2 x i32>* %y) { ; LMULMAX2-LABEL: extract_v2i32_v8i32_0: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX2-NEXT: vse32.v v26, (a1) +; LMULMAX2-NEXT: vse32.v v8, (a1) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v2i32_v8i32_0: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a0) +; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vse32.v v25, (a1) +; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 0) @@ -88,21 +88,21 @@ define void @extract_v2i32_v8i32_2(<8 x i32>* %x, <2 x i32>* %y) { ; LMULMAX2-LABEL: extract_v2i32_v8i32_2: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) ; LMULMAX2-NEXT: vsetivli zero, 2, e32, m2, ta, mu -; LMULMAX2-NEXT: vslidedown.vi v26, v26, 2 +; LMULMAX2-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX2-NEXT: vse32.v v26, (a1) +; LMULMAX2-NEXT: vse32.v v8, (a1) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v2i32_v8i32_2: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a0) +; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v25, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vse32.v v25, (a1) +; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 2) @@ -114,22 +114,22 @@ define void @extract_v2i32_v8i32_6(<8 x i32>* %x, <2 x i32>* %y) { ; LMULMAX2-LABEL: extract_v2i32_v8i32_6: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) ; LMULMAX2-NEXT: vsetivli zero, 2, e32, m2, ta, mu -; LMULMAX2-NEXT: vslidedown.vi v26, v26, 6 +; LMULMAX2-NEXT: vslidedown.vi v8, v8, 6 ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX2-NEXT: vse32.v v26, (a1) +; LMULMAX2-NEXT: vse32.v v8, (a1) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v2i32_v8i32_6: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a0) +; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v25, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vse32.v v25, (a1) +; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %c = call <2 x i32> @llvm.experimental.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 6) @@ -176,9 +176,9 @@ define void @extract_v2i8_nxv2i8_2( %x, <2 x i8>* %y) { ; CHECK-LABEL: extract_v2i8_nxv2i8_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v8, 2 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %c = call <2 x i8> @llvm.experimental.vector.extract.v2i8.nxv2i8( %x, i64 2) store <2 x i8> %c, <2 x i8>* %y @@ -214,17 +214,17 @@ define void @extract_v8i1_v64i1_0(<64 x i1>* %x, <8 x i1>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vlm.v v25, (a0) +; LMULMAX2-NEXT: vlm.v v8, (a0) ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX2-NEXT: vsm.v v25, (a1) +; LMULMAX2-NEXT: vsm.v v8, (a1) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v8i1_v64i1_0: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vlm.v v25, (a0) +; LMULMAX1-NEXT: vlm.v v8, (a0) ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vsm.v v25, (a1) +; LMULMAX1-NEXT: vsm.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <64 x i1>, <64 x i1>* %x %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 0) @@ -237,21 +237,21 @@ define void @extract_v8i1_v64i1_8(<64 x i1>* %x, <8 x i1>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vlm.v v25, (a0) +; LMULMAX2-NEXT: vlm.v v8, (a0) ; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf4, ta, mu -; LMULMAX2-NEXT: vslidedown.vi v25, v25, 1 +; LMULMAX2-NEXT: vslidedown.vi v8, v8, 1 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX2-NEXT: vsm.v v25, (a1) +; LMULMAX2-NEXT: vsm.v v8, (a1) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v8i1_v64i1_8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vlm.v v25, (a0) +; LMULMAX1-NEXT: vlm.v v8, (a0) ; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v25, v25, 1 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 1 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vsm.v v25, (a1) +; LMULMAX1-NEXT: vsm.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <64 x i1>, <64 x i1>* %x %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 8) @@ -265,20 +265,20 @@ define void @extract_v8i1_v64i1_48(<64 x i1>* %x, <8 x i1>* %y) { ; LMULMAX2-NEXT: addi a0, a0, 4 ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vlm.v v25, (a0) +; LMULMAX2-NEXT: vlm.v v8, (a0) ; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf4, ta, mu -; LMULMAX2-NEXT: vslidedown.vi v25, v25, 2 +; LMULMAX2-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX2-NEXT: vsm.v v25, (a1) +; LMULMAX2-NEXT: vsm.v v8, (a1) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v8i1_v64i1_48: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: addi a0, a0, 6 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vlm.v v25, (a0) +; LMULMAX1-NEXT: vlm.v v8, (a0) ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vsm.v v25, (a1) +; LMULMAX1-NEXT: vsm.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <64 x i1>, <64 x i1>* %x %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 48) @@ -312,9 +312,9 @@ define void @extract_v8i1_nxv64i1_8( %x, <8 x i1>* %y) { ; CHECK-LABEL: extract_v8i1_nxv64i1_8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v0, 1 +; CHECK-NEXT: vslidedown.vi v8, v0, 1 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1( %x, i64 8) store <8 x i1> %c, <8 x i1>* %y @@ -325,9 +325,9 @@ define void @extract_v8i1_nxv64i1_48( %x, <8 x i1>* %y) { ; CHECK-LABEL: extract_v8i1_nxv64i1_48: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v0, 6 +; CHECK-NEXT: vslidedown.vi v8, v0, 6 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1( %x, i64 48) store <8 x i1> %c, <8 x i1>* %y @@ -342,15 +342,15 @@ define void @extract_v2i1_v64i1_0(<64 x i1>* %x, <2 x i1>* %y) { ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; LMULMAX2-NEXT: vlm.v v0, (a0) ; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; LMULMAX2-NEXT: vmv.v.i v25, 0 -; LMULMAX2-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX2-NEXT: vmv.v.i v8, 0 +; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v26, 0 +; LMULMAX2-NEXT: vmv.v.i v9, 0 ; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; LMULMAX2-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX2-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX2-NEXT: vmsne.vi v25, v26, 0 -; LMULMAX2-NEXT: vsm.v v25, (a1) +; LMULMAX2-NEXT: vmsne.vi v8, v9, 0 +; LMULMAX2-NEXT: vsm.v v8, (a1) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v2i1_v64i1_0: @@ -358,15 +358,15 @@ define void @extract_v2i1_v64i1_0(<64 x i1>* %x, <2 x i1>* %y) { ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vlm.v v0, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v8, 0 +; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v25, v26, 0 -; LMULMAX1-NEXT: vsm.v v25, (a1) +; LMULMAX1-NEXT: vmsne.vi v8, v9, 0 +; LMULMAX1-NEXT: vsm.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <64 x i1>, <64 x i1>* %x %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0) @@ -380,42 +380,42 @@ define void @extract_v2i1_v64i1_2(<64 x i1>* %x, <2 x i1>* %y) { ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; LMULMAX2-NEXT: vlm.v v0, (a0) -; LMULMAX2-NEXT: vmv.v.i v26, 0 -; LMULMAX2-NEXT: vmerge.vim v26, v26, 1, v0 +; LMULMAX2-NEXT: vmv.v.i v8, 0 +; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX2-NEXT: vsetivli zero, 2, e8, m2, ta, mu -; LMULMAX2-NEXT: vslidedown.vi v26, v26, 2 +; LMULMAX2-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; LMULMAX2-NEXT: vmsne.vi v0, v26, 0 -; LMULMAX2-NEXT: vmv.v.i v25, 0 -; LMULMAX2-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX2-NEXT: vmsne.vi v0, v8, 0 +; LMULMAX2-NEXT: vmv.v.i v8, 0 +; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v26, 0 +; LMULMAX2-NEXT: vmv.v.i v9, 0 ; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; LMULMAX2-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX2-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX2-NEXT: vmsne.vi v25, v26, 0 -; LMULMAX2-NEXT: vsm.v v25, (a1) +; LMULMAX2-NEXT: vmsne.vi v8, v9, 0 +; LMULMAX2-NEXT: vsm.v v8, (a1) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v2i1_v64i1_2: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vlm.v v0, (a0) -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v8, 0 +; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v25, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v25, 0 -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 +; LMULMAX1-NEXT: vmv.v.i v8, 0 +; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v25, v26, 0 -; LMULMAX1-NEXT: vsm.v v25, (a1) +; LMULMAX1-NEXT: vmsne.vi v8, v9, 0 +; LMULMAX1-NEXT: vsm.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <64 x i1>, <64 x i1>* %x %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2) @@ -430,21 +430,21 @@ define void @extract_v2i1_v64i1_42(<64 x i1>* %x, <2 x i1>* %y) { ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; LMULMAX2-NEXT: vlm.v v0, (a0) -; LMULMAX2-NEXT: vmv.v.i v26, 0 -; LMULMAX2-NEXT: vmerge.vim v26, v26, 1, v0 +; LMULMAX2-NEXT: vmv.v.i v8, 0 +; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX2-NEXT: vsetivli zero, 2, e8, m2, ta, mu -; LMULMAX2-NEXT: vslidedown.vi v26, v26, 10 +; LMULMAX2-NEXT: vslidedown.vi v8, v8, 10 ; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; LMULMAX2-NEXT: vmsne.vi v0, v26, 0 -; LMULMAX2-NEXT: vmv.v.i v25, 0 -; LMULMAX2-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX2-NEXT: vmsne.vi v0, v8, 0 +; LMULMAX2-NEXT: vmv.v.i v8, 0 +; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v26, 0 +; LMULMAX2-NEXT: vmv.v.i v9, 0 ; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; LMULMAX2-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX2-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX2-NEXT: vmsne.vi v25, v26, 0 -; LMULMAX2-NEXT: vsm.v v25, (a1) +; LMULMAX2-NEXT: vmsne.vi v8, v9, 0 +; LMULMAX2-NEXT: vsm.v v8, (a1) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v2i1_v64i1_42: @@ -452,21 +452,21 @@ define void @extract_v2i1_v64i1_42(<64 x i1>* %x, <2 x i1>* %y) { ; LMULMAX1-NEXT: addi a0, a0, 4 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vlm.v v0, (a0) -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v8, 0 +; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v25, v25, 10 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 10 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v25, 0 -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 +; LMULMAX1-NEXT: vmv.v.i v8, 0 +; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 +; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v25, v26, 0 -; LMULMAX1-NEXT: vsm.v v25, (a1) +; LMULMAX1-NEXT: vmsne.vi v8, v9, 0 +; LMULMAX1-NEXT: vsm.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <64 x i1>, <64 x i1>* %x %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42) @@ -478,15 +478,15 @@ define void @extract_v2i1_nxv2i1_0( %x, <2 x i1>* %y) { ; CHECK-LABEL: extract_v2i1_nxv2i1_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1( %x, i64 0) store <2 x i1> %c, <2 x i1>* %y @@ -497,21 +497,21 @@ define void @extract_v2i1_nxv2i1_2( %x, <2 x i1>* %y) { ; CHECK-LABEL: extract_v2i1_nxv2i1_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v25, 2 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmsne.vi v0, v25, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1( %x, i64 2) store <2 x i1> %c, <2 x i1>* %y @@ -522,15 +522,15 @@ define void @extract_v2i1_nxv64i1_0( %x, <2 x i1>* %y) { ; CHECK-LABEL: extract_v2i1_nxv64i1_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1( %x, i64 0) store <2 x i1> %c, <2 x i1>* %y @@ -547,15 +547,15 @@ define void @extract_v2i1_nxv64i1_2( %x, <2 x i1>* %y) { ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vmsne.vi v0, v8, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1( %x, i64 2) store <2 x i1> %c, <2 x i1>* %y @@ -573,15 +573,15 @@ define void @extract_v2i1_nxv64i1_42( %x, <2 x i1>* %y) { ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vmsne.vi v0, v8, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1( %x, i64 42) store <2 x i1> %c, <2 x i1>* %y @@ -592,21 +592,21 @@ define void @extract_v2i1_nxv32i1_26( %x, <2 x i1>* %y) { ; CHECK-LABEL: extract_v2i1_nxv32i1_26: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v28, v28, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 2, e8, m4, ta, mu -; CHECK-NEXT: vslidedown.vi v28, v28, 26 +; CHECK-NEXT: vslidedown.vi v8, v8, 26 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmsne.vi v0, v28, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv32i1( %x, i64 26) store <2 x i1> %c, <2 x i1>* %y @@ -617,9 +617,9 @@ define void @extract_v8i1_nxv32i1_16( %x, <8 x i1>* %y) { ; CHECK-LABEL: extract_v8i1_nxv32i1_16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v0, 2 +; CHECK-NEXT: vslidedown.vi v8, v0, 2 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv32i1( %x, i64 16) store <8 x i1> %c, <8 x i1>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll index 2b2b63668f9ff2cef629eaa11408ce0c29d01bc0..37e1f229e2036ab62b041df13a4ca7e3233cb6eb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll @@ -6,10 +6,10 @@ define i8 @extractelt_v16i8(<16 x i8>* %x) nounwind { ; CHECK-LABEL: extractelt_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v25, 7 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 7 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = extractelement <16 x i8> %a, i32 7 @@ -20,10 +20,10 @@ define i16 @extractelt_v8i16(<8 x i16>* %x) nounwind { ; CHECK-LABEL: extractelt_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v25, 7 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 7 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = extractelement <8 x i16> %a, i32 7 @@ -34,10 +34,10 @@ define i32 @extractelt_v4i32(<4 x i32>* %x) nounwind { ; CHECK-LABEL: extractelt_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v25, 2 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = extractelement <4 x i32> %a, i32 2 @@ -48,19 +48,19 @@ define i64 @extractelt_v2i64(<2 x i64>* %x) nounwind { ; RV32-LABEL: extractelt_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a0, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v26, v25, a0 -; RV32-NEXT: vmv.x.s a1, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: extractelt_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = extractelement <2 x i64> %a, i32 0 @@ -71,10 +71,10 @@ define half @extractelt_v8f16(<8 x half>* %x) nounwind { ; CHECK-LABEL: extractelt_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v25, 7 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 7 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = extractelement <8 x half> %a, i32 7 @@ -85,10 +85,10 @@ define float @extractelt_v4f32(<4 x float>* %x) nounwind { ; CHECK-LABEL: extractelt_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v25, 2 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = extractelement <4 x float> %a, i32 2 @@ -99,8 +99,8 @@ define double @extractelt_v2f64(<2 x double>* %x) nounwind { ; CHECK-LABEL: extractelt_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = extractelement <2 x double> %a, i32 0 @@ -112,10 +112,10 @@ define i8 @extractelt_v32i8(<32 x i8>* %x) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v26, 7 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 7 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = extractelement <32 x i8> %a, i32 7 @@ -126,10 +126,10 @@ define i16 @extractelt_v16i16(<16 x i16>* %x) nounwind { ; CHECK-LABEL: extractelt_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v26, 7 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 7 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = extractelement <16 x i16> %a, i32 7 @@ -140,10 +140,10 @@ define i32 @extractelt_v8i32(<8 x i32>* %x) nounwind { ; CHECK-LABEL: extractelt_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v26, 6 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 6 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = extractelement <8 x i32> %a, i32 6 @@ -154,22 +154,22 @@ define i64 @extractelt_v4i64(<4 x i64>* %x) nounwind { ; RV32-LABEL: extractelt_v4i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vle64.v v26, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; RV32-NEXT: vslidedown.vi v26, v26, 3 -; RV32-NEXT: vmv.x.s a0, v26 +; RV32-NEXT: vslidedown.vi v8, v8, 3 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 -; RV32-NEXT: vsrl.vx v26, v26, a1 -; RV32-NEXT: vmv.x.s a1, v26 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: extractelt_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v26, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; RV64-NEXT: vslidedown.vi v26, v26, 3 -; RV64-NEXT: vmv.x.s a0, v26 +; RV64-NEXT: vslidedown.vi v8, v8, 3 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = extractelement <4 x i64> %a, i32 3 @@ -180,10 +180,10 @@ define half @extractelt_v16f16(<16 x half>* %x) nounwind { ; CHECK-LABEL: extractelt_v16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v26, 7 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 7 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = extractelement <16 x half> %a, i32 7 @@ -194,10 +194,10 @@ define float @extractelt_v8f32(<8 x float>* %x) nounwind { ; CHECK-LABEL: extractelt_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; CHECK-NEXT: vslidedown.vi v26, v26, 2 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = extractelement <8 x float> %a, i32 2 @@ -208,8 +208,8 @@ define double @extractelt_v4f64(<4 x double>* %x) nounwind { ; CHECK-LABEL: extractelt_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = extractelement <4 x double> %a, i32 0 @@ -224,21 +224,21 @@ define i64 @extractelt_v3i64(<3 x i64>* %x) nounwind { ; RV32-LABEL: extractelt_v3i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vle32.v v26, (a0) +; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; RV32-NEXT: vslidedown.vi v28, v26, 4 -; RV32-NEXT: vmv.x.s a0, v28 -; RV32-NEXT: vslidedown.vi v26, v26, 5 -; RV32-NEXT: vmv.x.s a1, v26 +; RV32-NEXT: vslidedown.vi v10, v8, 4 +; RV32-NEXT: vmv.x.s a0, v10 +; RV32-NEXT: vslidedown.vi v8, v8, 5 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: extractelt_v3i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v26, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; RV64-NEXT: vslidedown.vi v26, v26, 2 -; RV64-NEXT: vmv.x.s a0, v26 +; RV64-NEXT: vslidedown.vi v8, v8, 2 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %a = load <3 x i64>, <3 x i64>* %x %b = extractelement <3 x i64> %a, i32 2 @@ -249,10 +249,10 @@ define i8 @extractelt_v16i8_idx(<16 x i8>* %x, i32 signext %idx) nounwind { ; CHECK-LABEL: extractelt_v16i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = extractelement <16 x i8> %a, i32 %idx @@ -263,10 +263,10 @@ define i16 @extractelt_v8i16_idx(<8 x i16>* %x, i32 signext %idx) nounwind { ; CHECK-LABEL: extractelt_v8i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = extractelement <8 x i16> %a, i32 %idx @@ -277,11 +277,11 @@ define i32 @extractelt_v4i32_idx(<4 x i32>* %x, i32 signext %idx) nounwind { ; CHECK-LABEL: extractelt_v4i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vadd.vv v25, v25, v25 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = add <4 x i32> %a, %a @@ -293,24 +293,24 @@ define i64 @extractelt_v2i64_idx(<2 x i64>* %x, i32 signext %idx) nounwind { ; RV32-LABEL: extractelt_v2i64_idx: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) -; RV32-NEXT: vadd.vv v25, v25, v25 +; RV32-NEXT: vle64.v v8, (a0) +; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vslidedown.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vslidedown.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: extractelt_v2i64_idx: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) -; RV64-NEXT: vadd.vv v25, v25, v25 +; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vadd.vv v8, v8, v8 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV64-NEXT: vslidedown.vx v25, v25, a1 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vslidedown.vx v8, v8, a1 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = add <2 x i64> %a, %a @@ -322,11 +322,11 @@ define half @extractelt_v8f16_idx(<8 x half>* %x, i32 signext %idx) nounwind { ; CHECK-LABEL: extractelt_v8f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfadd.vv v25, v25, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfadd.vv v8, v8, v8 ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = fadd <8 x half> %a, %a @@ -338,11 +338,11 @@ define float @extractelt_v4f32_idx(<4 x float>* %x, i32 signext %idx) nounwind { ; CHECK-LABEL: extractelt_v4f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfadd.vv v25, v25, v25 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfadd.vv v8, v8, v8 ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = fadd <4 x float> %a, %a @@ -354,11 +354,11 @@ define double @extractelt_v2f64_idx(<2 x double>* %x, i32 signext %idx) nounwind ; CHECK-LABEL: extractelt_v2f64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vfadd.vv v25, v25, v25 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfadd.vv v8, v8, v8 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vslidedown.vx v25, v25, a1 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = fadd <2 x double> %a, %a @@ -371,10 +371,10 @@ define i8 @extractelt_v32i8_idx(<32 x i8>* %x, i32 signext %idx) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v26, a1 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = extractelement <32 x i8> %a, i32 %idx @@ -385,10 +385,10 @@ define i16 @extractelt_v16i16_idx(<16 x i16>* %x, i32 signext %idx) nounwind { ; CHECK-LABEL: extractelt_v16i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v26, a1 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = extractelement <16 x i16> %a, i32 %idx @@ -399,11 +399,11 @@ define i32 @extractelt_v8i32_idx(<8 x i32>* %x, i32 signext %idx) nounwind { ; CHECK-LABEL: extractelt_v8i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vadd.vv v26, v26, v26 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v26, a1 -; CHECK-NEXT: vmv.x.s a0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = add <8 x i32> %a, %a @@ -415,24 +415,24 @@ define i64 @extractelt_v4i64_idx(<4 x i64>* %x, i32 signext %idx) nounwind { ; RV32-LABEL: extractelt_v4i64_idx: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vle64.v v26, (a0) -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vle64.v v8, (a0) +; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; RV32-NEXT: vslidedown.vx v26, v26, a1 -; RV32-NEXT: vmv.x.s a0, v26 +; RV32-NEXT: vslidedown.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 -; RV32-NEXT: vsrl.vx v26, v26, a1 -; RV32-NEXT: vmv.x.s a1, v26 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: extractelt_v4i64_idx: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v26, (a0) -; RV64-NEXT: vadd.vv v26, v26, v26 +; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vadd.vv v8, v8, v8 ; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; RV64-NEXT: vslidedown.vx v26, v26, a1 -; RV64-NEXT: vmv.x.s a0, v26 +; RV64-NEXT: vslidedown.vx v8, v8, a1 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = add <4 x i64> %a, %a @@ -444,11 +444,11 @@ define half @extractelt_v16f16_idx(<16 x half>* %x, i32 signext %idx) nounwind { ; CHECK-LABEL: extractelt_v16f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vfadd.vv v26, v26, v26 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfadd.vv v8, v8, v8 ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v26, a1 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = fadd <16 x half> %a, %a @@ -460,11 +460,11 @@ define float @extractelt_v8f32_idx(<8 x float>* %x, i32 signext %idx) nounwind { ; CHECK-LABEL: extractelt_v8f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vfadd.vv v26, v26, v26 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfadd.vv v8, v8, v8 ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v26, a1 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = fadd <8 x float> %a, %a @@ -476,11 +476,11 @@ define double @extractelt_v4f64_idx(<4 x double>* %x, i32 signext %idx) nounwind ; CHECK-LABEL: extractelt_v4f64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) -; CHECK-NEXT: vfadd.vv v26, v26, v26 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfadd.vv v8, v8, v8 ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; CHECK-NEXT: vslidedown.vx v26, v26, a1 -; CHECK-NEXT: vfmv.f.s fa0, v26 +; CHECK-NEXT: vslidedown.vx v8, v8, a1 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = fadd <4 x double> %a, %a @@ -496,25 +496,25 @@ define i64 @extractelt_v3i64_idx(<3 x i64>* %x, i32 signext %idx) nounwind { ; RV32-LABEL: extractelt_v3i64_idx: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vle64.v v26, (a0) -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vle64.v v8, (a0) +; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: add a1, a1, a1 ; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; RV32-NEXT: vslidedown.vx v28, v26, a1 -; RV32-NEXT: vmv.x.s a0, v28 +; RV32-NEXT: vslidedown.vx v10, v8, a1 +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, a1, 1 -; RV32-NEXT: vslidedown.vx v26, v26, a1 -; RV32-NEXT: vmv.x.s a1, v26 +; RV32-NEXT: vslidedown.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: extractelt_v3i64_idx: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v26, (a0) -; RV64-NEXT: vadd.vv v26, v26, v26 +; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vadd.vv v8, v8, v8 ; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; RV64-NEXT: vslidedown.vx v26, v26, a1 -; RV64-NEXT: vmv.x.s a0, v26 +; RV64-NEXT: vslidedown.vx v8, v8, a1 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %a = load <3 x i64>, <3 x i64>* %x %b = add <3 x i64> %a, %a @@ -526,10 +526,10 @@ define void @store_extractelt_v16i8(<16 x i8>* %x, i8* %p) nounwind { ; CHECK-LABEL: store_extractelt_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v25, 7 -; CHECK-NEXT: vse8.v v25, (a1) +; CHECK-NEXT: vslidedown.vi v8, v8, 7 +; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = extractelement <16 x i8> %a, i32 7 @@ -541,10 +541,10 @@ define void @store_extractelt_v8i16(<8 x i16>* %x, i16* %p) nounwind { ; CHECK-LABEL: store_extractelt_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v25, 7 -; CHECK-NEXT: vse16.v v25, (a1) +; CHECK-NEXT: vslidedown.vi v8, v8, 7 +; CHECK-NEXT: vse16.v v8, (a1) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = extractelement <8 x i16> %a, i32 7 @@ -556,10 +556,10 @@ define void @store_extractelt_v4i32(<4 x i32>* %x, i32* %p) nounwind { ; CHECK-LABEL: store_extractelt_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu -; CHECK-NEXT: vslidedown.vi v25, v25, 2 -; CHECK-NEXT: vse32.v v25, (a1) +; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vse32.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = extractelement <4 x i32> %a, i32 2 @@ -572,13 +572,13 @@ define void @store_extractelt_v4i64(<2 x i64>* %x, i64* %p) nounwind { ; RV32-LABEL: store_extractelt_v4i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vslidedown.vi v25, v25, 1 +; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: addi a0, zero, 32 -; RV32-NEXT: vsrl.vx v26, v25, a0 -; RV32-NEXT: vmv.x.s a0, v26 -; RV32-NEXT: vmv.x.s a2, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a0, v9 +; RV32-NEXT: vmv.x.s a2, v8 ; RV32-NEXT: sw a2, 0(a1) ; RV32-NEXT: sw a0, 4(a1) ; RV32-NEXT: ret @@ -586,10 +586,10 @@ define void @store_extractelt_v4i64(<2 x i64>* %x, i64* %p) nounwind { ; RV64-LABEL: store_extractelt_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV64-NEXT: vslidedown.vi v25, v25, 1 -; RV64-NEXT: vse64.v v25, (a1) +; RV64-NEXT: vslidedown.vi v8, v8, 1 +; RV64-NEXT: vse64.v v8, (a1) ; RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = extractelement <2 x i64> %a, i64 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll index b3680a70c3dce326ffee6ff0f64f61d54c0208f2..d1525447c40d7799bb350739d863ee839eb45d25 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll @@ -82,8 +82,8 @@ define i64 @bitcast_v4f16_i64(<4 x half> %a) { ; RV32-FP: # %bb.0: ; RV32-FP-NEXT: addi a0, zero, 32 ; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-FP-NEXT: vsrl.vx v25, v8, a0 -; RV32-FP-NEXT: vmv.x.s a1, v25 +; RV32-FP-NEXT: vsrl.vx v9, v8, a0 +; RV32-FP-NEXT: vmv.x.s a1, v9 ; RV32-FP-NEXT: vmv.x.s a0, v8 ; RV32-FP-NEXT: ret ; @@ -101,8 +101,8 @@ define i64 @bitcast_v2f32_i64(<2 x float> %a) { ; RV32-FP: # %bb.0: ; RV32-FP-NEXT: addi a0, zero, 32 ; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-FP-NEXT: vsrl.vx v25, v8, a0 -; RV32-FP-NEXT: vmv.x.s a1, v25 +; RV32-FP-NEXT: vsrl.vx v9, v8, a0 +; RV32-FP-NEXT: vmv.x.s a1, v9 ; RV32-FP-NEXT: vmv.x.s a0, v8 ; RV32-FP-NEXT: ret ; @@ -120,8 +120,8 @@ define i64 @bitcast_v1f64_i64(<1 x double> %a) { ; RV32-FP: # %bb.0: ; RV32-FP-NEXT: addi a0, zero, 32 ; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-FP-NEXT: vsrl.vx v25, v8, a0 -; RV32-FP-NEXT: vmv.x.s a1, v25 +; RV32-FP-NEXT: vsrl.vx v9, v8, a0 +; RV32-FP-NEXT: vmv.x.s a1, v9 ; RV32-FP-NEXT: vmv.x.s a0, v8 ; RV32-FP-NEXT: ret ; @@ -246,11 +246,11 @@ define <4 x half> @bitcast_i64_v4f16(i64 %a) { ; RV32-FP-LABEL: bitcast_i64_v4f16: ; RV32-FP: # %bb.0: ; RV32-FP-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; RV32-FP-NEXT: vmv.v.i v25, 0 -; RV32-FP-NEXT: vslide1up.vx v26, v25, a1 -; RV32-FP-NEXT: vslide1up.vx v25, v26, a0 +; RV32-FP-NEXT: vmv.v.i v8, 0 +; RV32-FP-NEXT: vslide1up.vx v9, v8, a1 +; RV32-FP-NEXT: vslide1up.vx v10, v9, a0 ; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-FP-NEXT: vslideup.vi v8, v25, 0 +; RV32-FP-NEXT: vslideup.vi v8, v10, 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_i64_v4f16: @@ -266,11 +266,11 @@ define <2 x float> @bitcast_i64_v2f32(i64 %a) { ; RV32-FP-LABEL: bitcast_i64_v2f32: ; RV32-FP: # %bb.0: ; RV32-FP-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; RV32-FP-NEXT: vmv.v.i v25, 0 -; RV32-FP-NEXT: vslide1up.vx v26, v25, a1 -; RV32-FP-NEXT: vslide1up.vx v25, v26, a0 +; RV32-FP-NEXT: vmv.v.i v8, 0 +; RV32-FP-NEXT: vslide1up.vx v9, v8, a1 +; RV32-FP-NEXT: vslide1up.vx v10, v9, a0 ; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-FP-NEXT: vslideup.vi v8, v25, 0 +; RV32-FP-NEXT: vslideup.vi v8, v10, 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_i64_v2f32: @@ -286,11 +286,11 @@ define <1 x double> @bitcast_i64_v1f64(i64 %a) { ; RV32-FP-LABEL: bitcast_i64_v1f64: ; RV32-FP: # %bb.0: ; RV32-FP-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; RV32-FP-NEXT: vmv.v.i v25, 0 -; RV32-FP-NEXT: vslide1up.vx v26, v25, a1 -; RV32-FP-NEXT: vslide1up.vx v25, v26, a0 +; RV32-FP-NEXT: vmv.v.i v8, 0 +; RV32-FP-NEXT: vslide1up.vx v9, v8, a1 +; RV32-FP-NEXT: vslide1up.vx v10, v9, a0 ; RV32-FP-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-FP-NEXT: vslideup.vi v8, v25, 0 +; RV32-FP-NEXT: vslideup.vi v8, v10, 0 ; RV32-FP-NEXT: ret ; ; RV64-FP-LABEL: bitcast_i64_v1f64: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll index 3941ed6a4d4d3aadfe96a7c132a7a1c34fbaf29c..eba7f00807f6258f689f7bbda29fa7f5418d717d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll @@ -13,8 +13,8 @@ define void @buildvec_no_vid_v4f32(<4 x float>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI0_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI0_0) ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a1) -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret store <4 x float> , <4 x float>* %x ret void @@ -43,11 +43,11 @@ define <4 x float> @hang_when_merging_stores_after_legalization(<8 x float> %x, ; LMULMAX1-NEXT: vfmv.f.s ft0, v8 ; LMULMAX1-NEXT: fsw ft0, 16(sp) ; LMULMAX1-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v10, 7 -; LMULMAX1-NEXT: vfmv.f.s ft0, v26 +; LMULMAX1-NEXT: vslidedown.vi v10, v10, 7 +; LMULMAX1-NEXT: vfmv.f.s ft0, v10 ; LMULMAX1-NEXT: fsw ft0, 28(sp) -; LMULMAX1-NEXT: vslidedown.vi v26, v8, 7 -; LMULMAX1-NEXT: vfmv.f.s ft0, v26 +; LMULMAX1-NEXT: vslidedown.vi v8, v8, 7 +; LMULMAX1-NEXT: vfmv.f.s ft0, v8 ; LMULMAX1-NEXT: fsw ft0, 20(sp) ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: addi a0, sp, 16 @@ -61,19 +61,19 @@ define <4 x float> @hang_when_merging_stores_after_legalization(<8 x float> %x, ; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX2-NEXT: vmv.s.x v0, a0 ; LMULMAX2-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-NEXT: vrgather.vi v25, v8, 0 -; LMULMAX2-NEXT: vrgather.vi v25, v9, 3, v0.t +; LMULMAX2-NEXT: vrgather.vi v12, v8, 0 +; LMULMAX2-NEXT: vrgather.vi v12, v9, 3, v0.t ; LMULMAX2-NEXT: addi a0, zero, 8 ; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX2-NEXT: vmv.s.x v0, a0 ; LMULMAX2-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-NEXT: vrgather.vi v26, v10, 0 -; LMULMAX2-NEXT: vrgather.vi v26, v11, 3, v0.t +; LMULMAX2-NEXT: vrgather.vi v8, v10, 0 +; LMULMAX2-NEXT: vrgather.vi v8, v11, 3, v0.t ; LMULMAX2-NEXT: addi a0, zero, 3 ; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX2-NEXT: vmv.s.x v0, a0 ; LMULMAX2-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX2-NEXT: vmerge.vvm v8, v26, v25, v0 +; LMULMAX2-NEXT: vmerge.vvm v8, v8, v12, v0 ; LMULMAX2-NEXT: ret %z = shufflevector <8 x float> %x, <8 x float> %y, <4 x i32> ret <4 x float> %z @@ -85,11 +85,11 @@ define void @buildvec_dominant0_v2f32(<2 x float>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI2_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI2_0) ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vlse32.v v25, (a1), zero +; CHECK-NEXT: vlse32.v v8, (a1), zero ; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, tu, mu -; CHECK-NEXT: vfmv.s.f v25, ft0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vfmv.s.f v8, ft0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret store <2 x float> , <2 x float>* %x ret void @@ -104,8 +104,8 @@ define void @buildvec_dominant1_v2f32(<2 x float>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI3_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI3_0) ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a1) -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret store <2 x float> , <2 x float>* %x ret void @@ -117,13 +117,13 @@ define void @buildvec_dominant0_v4f32(<4 x float>* %x) { ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: lui a1, %hi(.LCPI4_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI4_0) -; CHECK-NEXT: vlse32.v v25, (a1), zero +; CHECK-NEXT: vlse32.v v8, (a1), zero ; CHECK-NEXT: fmv.w.x ft0, zero -; CHECK-NEXT: vfmv.s.f v26, ft0 +; CHECK-NEXT: vfmv.s.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vi v25, v26, 2 +; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret store <4 x float> , <4 x float>* %x ret void @@ -134,12 +134,12 @@ define void @buildvec_dominant1_v4f32(<4 x float>* %x, float %f) { ; CHECK: # %bb.0: ; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, ft0 -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v8, ft0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 1 +; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: ret %v0 = insertelement <4 x float> undef, float %f, i32 0 %v1 = insertelement <4 x float> %v0, float 0.0, i32 1 @@ -155,12 +155,12 @@ define void @buildvec_dominant2_v4f32(<4 x float>* %x, float %f) { ; CHECK-NEXT: lui a1, %hi(.LCPI6_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, ft0 -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v8, ft0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 1 +; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: ret %v0 = insertelement <4 x float> undef, float %f, i32 0 %v1 = insertelement <4 x float> %v0, float 2.0, i32 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll index 9324a403db0e4568de023675b33310c16963aa29..f858b69f008ad68e641cdbbf97cd86dd744353de 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll @@ -8,9 +8,9 @@ define void @fpext_v2f16_v2f32(<2 x half>* %x, <2 x float>* %y) { ; CHECK-LABEL: fpext_v2f16_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfwcvt.f.f.v v26, v25 -; CHECK-NEXT: vse32.v v26, (a1) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfwcvt.f.f.v v9, v8 +; CHECK-NEXT: vse32.v v9, (a1) ; CHECK-NEXT: ret %a = load <2 x half>, <2 x half>* %x %d = fpext <2 x half> %a to <2 x float> @@ -22,11 +22,11 @@ define void @fpext_v2f16_v2f64(<2 x half>* %x, <2 x double>* %y) { ; CHECK-LABEL: fpext_v2f16_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfwcvt.f.f.v v26, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v25, v26 -; CHECK-NEXT: vse64.v v25, (a1) +; CHECK-NEXT: vfwcvt.f.f.v v8, v9 +; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x half>, <2 x half>* %x %d = fpext <2 x half> %a to <2 x double> @@ -38,23 +38,23 @@ define void @fpext_v8f16_v8f32(<8 x half>* %x, <8 x float>* %y) { ; LMULMAX8-LABEL: fpext_v8f16_v8f32: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX8-NEXT: vle16.v v25, (a0) -; LMULMAX8-NEXT: vfwcvt.f.f.v v26, v25 -; LMULMAX8-NEXT: vse32.v v26, (a1) +; LMULMAX8-NEXT: vle16.v v8, (a0) +; LMULMAX8-NEXT: vfwcvt.f.f.v v10, v8 +; LMULMAX8-NEXT: vse32.v v10, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fpext_v8f16_v8f32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v8, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v9, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vfwcvt.f.f.v v27, v26 -; LMULMAX1-NEXT: vfwcvt.f.f.v v26, v25 +; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v9 +; LMULMAX1-NEXT: vfwcvt.f.f.v v9, v8 ; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse32.v v27, (a0) -; LMULMAX1-NEXT: vse32.v v26, (a1) +; LMULMAX1-NEXT: vse32.v v10, (a0) +; LMULMAX1-NEXT: vse32.v v9, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x half>, <8 x half>* %x %d = fpext <8 x half> %a to <8 x float> @@ -66,46 +66,46 @@ define void @fpext_v8f16_v8f64(<8 x half>* %x, <8 x double>* %y) { ; LMULMAX8-LABEL: fpext_v8f16_v8f64: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX8-NEXT: vle16.v v25, (a0) -; LMULMAX8-NEXT: vfwcvt.f.f.v v26, v25 +; LMULMAX8-NEXT: vle16.v v8, (a0) +; LMULMAX8-NEXT: vfwcvt.f.f.v v10, v8 ; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; LMULMAX8-NEXT: vfwcvt.f.f.v v28, v26 -; LMULMAX8-NEXT: vse64.v v28, (a1) +; LMULMAX8-NEXT: vfwcvt.f.f.v v12, v10 +; LMULMAX8-NEXT: vse64.v v12, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fpext_v8f16_v8f64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v8, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfwcvt.f.f.v v27, v26 +; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v9 ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfwcvt.f.f.v v26, v27 +; LMULMAX1-NEXT: vfwcvt.f.f.v v9, v10 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v28, v27, 2 +; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfwcvt.f.f.v v29, v28 +; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v11 ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfwcvt.f.f.v v28, v29 +; LMULMAX1-NEXT: vfwcvt.f.f.v v11, v12 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfwcvt.f.f.v v29, v27 +; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v10 ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfwcvt.f.f.v v27, v29 +; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v12 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfwcvt.f.f.v v29, v25 +; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v8 ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfwcvt.f.f.v v25, v29 +; LMULMAX1-NEXT: vfwcvt.f.f.v v8, v12 ; LMULMAX1-NEXT: addi a0, a1, 32 -; LMULMAX1-NEXT: vse64.v v27, (a0) -; LMULMAX1-NEXT: vse64.v v25, (a1) +; LMULMAX1-NEXT: vse64.v v10, (a0) +; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a1, 48 -; LMULMAX1-NEXT: vse64.v v28, (a0) +; LMULMAX1-NEXT: vse64.v v11, (a0) ; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse64.v v26, (a0) +; LMULMAX1-NEXT: vse64.v v9, (a0) ; LMULMAX1-NEXT: ret %a = load <8 x half>, <8 x half>* %x %d = fpext <8 x half> %a to <8 x double> @@ -117,10 +117,10 @@ define void @fpround_v2f32_v2f16(<2 x float>* %x, <2 x half>* %y) { ; CHECK-LABEL: fpround_v2f32_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.f.f.w v26, v25 -; CHECK-NEXT: vse16.v v26, (a1) +; CHECK-NEXT: vfncvt.f.f.w v9, v8 +; CHECK-NEXT: vse16.v v9, (a1) ; CHECK-NEXT: ret %a = load <2 x float>, <2 x float>* %x %d = fptrunc <2 x float> %a to <2 x half> @@ -132,12 +132,12 @@ define void @fpround_v2f64_v2f16(<2 x double>* %x, <2 x half>* %y) { ; CHECK-LABEL: fpround_v2f64_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rod.f.f.w v26, v25 +; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.f.f.w v25, v26 -; CHECK-NEXT: vse16.v v25, (a1) +; CHECK-NEXT: vfncvt.f.f.w v8, v9 +; CHECK-NEXT: vse16.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %d = fptrunc <2 x double> %a to <2 x half> @@ -149,29 +149,29 @@ define void @fpround_v8f32_v8f16(<8 x float>* %x, <8 x half>* %y) { ; LMULMAX8-LABEL: fpround_v8f32_v8f16: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX8-NEXT: vle32.v v26, (a0) +; LMULMAX8-NEXT: vle32.v v8, (a0) ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26 -; LMULMAX8-NEXT: vse16.v v25, (a1) +; LMULMAX8-NEXT: vfncvt.f.f.w v10, v8 +; LMULMAX8-NEXT: vse16.v v10, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fpround_v8f32_v8f16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a0) +; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vle32.v v26, (a0) +; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.f.f.w v27, v25 +; LMULMAX1-NEXT: vfncvt.f.f.w v10, v8 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v25, 0 +; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v27, 0 +; LMULMAX1-NEXT: vslideup.vi v8, v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.f.f.w v27, v26 +; LMULMAX1-NEXT: vfncvt.f.f.w v10, v9 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v27, 4 -; LMULMAX1-NEXT: vse16.v v25, (a1) +; LMULMAX1-NEXT: vslideup.vi v8, v10, 4 +; LMULMAX1-NEXT: vse16.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %d = fptrunc <8 x float> %a to <8 x half> @@ -183,51 +183,51 @@ define void @fpround_v8f64_v8f16(<8 x double>* %x, <8 x half>* %y) { ; LMULMAX8-LABEL: fpround_v8f64_v8f16: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; LMULMAX8-NEXT: vle64.v v28, (a0) +; LMULMAX8-NEXT: vle64.v v8, (a0) ; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; LMULMAX8-NEXT: vfncvt.rod.f.f.w v26, v28 +; LMULMAX8-NEXT: vfncvt.rod.f.f.w v12, v8 ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26 -; LMULMAX8-NEXT: vse16.v v25, (a1) +; LMULMAX8-NEXT: vfncvt.f.f.w v8, v12 +; LMULMAX8-NEXT: vse16.v v8, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fpround_v8f64_v8f16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: addi a2, a0, 48 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vle64.v v25, (a2) +; LMULMAX1-NEXT: vle64.v v8, (a2) ; LMULMAX1-NEXT: addi a2, a0, 32 -; LMULMAX1-NEXT: vle64.v v26, (a2) -; LMULMAX1-NEXT: vle64.v v27, (a0) +; LMULMAX1-NEXT: vle64.v v9, (a2) +; LMULMAX1-NEXT: vle64.v v10, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vle64.v v28, (a0) +; LMULMAX1-NEXT: vle64.v v11, (a0) ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rod.f.f.w v29, v27 +; LMULMAX1-NEXT: vfncvt.rod.f.f.w v12, v10 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfncvt.f.f.w v27, v29 +; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v29, 0 +; LMULMAX1-NEXT: vmv.v.i v12, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v27, 0 +; LMULMAX1-NEXT: vslideup.vi v12, v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rod.f.f.w v27, v28 +; LMULMAX1-NEXT: vfncvt.rod.f.f.w v10, v11 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfncvt.f.f.w v28, v27 +; LMULMAX1-NEXT: vfncvt.f.f.w v11, v10 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v28, 2 +; LMULMAX1-NEXT: vslideup.vi v12, v11, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rod.f.f.w v27, v26 +; LMULMAX1-NEXT: vfncvt.rod.f.f.w v10, v9 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfncvt.f.f.w v26, v27 +; LMULMAX1-NEXT: vfncvt.f.f.w v9, v10 ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v26, 4 +; LMULMAX1-NEXT: vslideup.vi v12, v9, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rod.f.f.w v26, v25 +; LMULMAX1-NEXT: vfncvt.rod.f.f.w v9, v8 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfncvt.f.f.w v25, v26 +; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v25, 6 -; LMULMAX1-NEXT: vse16.v v29, (a1) +; LMULMAX1-NEXT: vslideup.vi v12, v8, 6 +; LMULMAX1-NEXT: vse16.v v12, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x double>, <8 x double>* %x %d = fptrunc <8 x double> %a to <8 x half> diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll index 60508396aec1e637ac8919b43ff5e6e4963edc3e..9999efbe33808395066031d0889813d915f87e40 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll @@ -6,10 +6,10 @@ define void @fcmp_oeq_vv_v8f16(<8 x half>* %x, <8 x half>* %y, <8 x i1>* %z) { ; CHECK-LABEL: fcmp_oeq_vv_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vmfeq.vv v25, v25, v26 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vmfeq.vv v8, v8, v9 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -22,10 +22,10 @@ define void @fcmp_oeq_vv_v8f16_nonans(<8 x half>* %x, <8 x half>* %y, <8 x i1>* ; CHECK-LABEL: fcmp_oeq_vv_v8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vmfeq.vv v25, v25, v26 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vmfeq.vv v8, v8, v9 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -38,19 +38,19 @@ define void @fcmp_une_vv_v4f32(<4 x float>* %x, <4 x float>* %y, <4 x i1>* %z) { ; CHECK-LABEL: fcmp_une_vv_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vmfne.vv v0, v25, v26 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -63,19 +63,19 @@ define void @fcmp_une_vv_v4f32_nonans(<4 x float>* %x, <4 x float>* %y, <4 x i1> ; CHECK-LABEL: fcmp_une_vv_v4f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vmfne.vv v0, v25, v26 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -88,19 +88,19 @@ define void @fcmp_ogt_vv_v2f64(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z) ; CHECK-LABEL: fcmp_ogt_vv_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vmflt.vv v0, v26, v25 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -113,19 +113,19 @@ define void @fcmp_ogt_vv_v2f64_nonans(<2 x double>* %x, <2 x double>* %y, <2 x i ; CHECK-LABEL: fcmp_ogt_vv_v2f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vmflt.vv v0, v26, v25 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -138,10 +138,10 @@ define void @fcmp_olt_vv_v16f16(<16 x half>* %x, <16 x half>* %y, <16 x i1>* %z) ; CHECK-LABEL: fcmp_olt_vv_v16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vmflt.vv v25, v26, v28 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v10, (a1) +; CHECK-NEXT: vmflt.vv v12, v8, v10 +; CHECK-NEXT: vsm.v v12, (a2) ; CHECK-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = load <16 x half>, <16 x half>* %y @@ -154,10 +154,10 @@ define void @fcmp_olt_vv_v16f16_nonans(<16 x half>* %x, <16 x half>* %y, <16 x i ; CHECK-LABEL: fcmp_olt_vv_v16f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vmflt.vv v25, v26, v28 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v10, (a1) +; CHECK-NEXT: vmflt.vv v12, v8, v10 +; CHECK-NEXT: vsm.v v12, (a2) ; CHECK-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = load <16 x half>, <16 x half>* %y @@ -170,10 +170,10 @@ define void @fcmp_oge_vv_v8f32(<8 x float>* %x, <8 x float>* %y, <8 x i1>* %z) { ; CHECK-LABEL: fcmp_oge_vv_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vmfle.vv v25, v28, v26 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v10, (a1) +; CHECK-NEXT: vmfle.vv v12, v10, v8 +; CHECK-NEXT: vsm.v v12, (a2) ; CHECK-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = load <8 x float>, <8 x float>* %y @@ -186,10 +186,10 @@ define void @fcmp_oge_vv_v8f32_nonans(<8 x float>* %x, <8 x float>* %y, <8 x i1> ; CHECK-LABEL: fcmp_oge_vv_v8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vmfle.vv v25, v28, v26 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v10, (a1) +; CHECK-NEXT: vmfle.vv v12, v10, v8 +; CHECK-NEXT: vsm.v v12, (a2) ; CHECK-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = load <8 x float>, <8 x float>* %y @@ -202,19 +202,19 @@ define void @fcmp_ole_vv_v4f64(<4 x double>* %x, <4 x double>* %y, <4 x i1>* %z) ; CHECK-LABEL: fcmp_ole_vv_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) -; CHECK-NEXT: vle64.v v28, (a1) -; CHECK-NEXT: vmfle.vv v0, v26, v28 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v10, (a1) +; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = load <4 x double>, <4 x double>* %y @@ -227,19 +227,19 @@ define void @fcmp_ole_vv_v4f64_nonans(<4 x double>* %x, <4 x double>* %y, <4 x i ; CHECK-LABEL: fcmp_ole_vv_v4f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) -; CHECK-NEXT: vle64.v v28, (a1) -; CHECK-NEXT: vmfle.vv v0, v26, v28 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v10, (a1) +; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = load <4 x double>, <4 x double>* %y @@ -253,11 +253,11 @@ define void @fcmp_ule_vv_v32f16(<32 x half>* %x, <32 x half>* %y, <32 x i1>* %z) ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 32 ; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vmflt.vv v25, v8, v28 -; CHECK-NEXT: vmnand.mm v25, v25, v25 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v12, (a1) +; CHECK-NEXT: vmflt.vv v16, v12, v8 +; CHECK-NEXT: vmnand.mm v8, v16, v16 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <32 x half>, <32 x half>* %x %b = load <32 x half>, <32 x half>* %y @@ -271,10 +271,10 @@ define void @fcmp_ule_vv_v32f16_nonans(<32 x half>* %x, <32 x half>* %y, <32 x i ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 32 ; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vmfle.vv v25, v28, v8 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v12, (a1) +; CHECK-NEXT: vmfle.vv v16, v8, v12 +; CHECK-NEXT: vsm.v v16, (a2) ; CHECK-NEXT: ret %a = load <32 x half>, <32 x half>* %x %b = load <32 x half>, <32 x half>* %y @@ -287,11 +287,11 @@ define void @fcmp_uge_vv_v16f32(<16 x float>* %x, <16 x float>* %y, <16 x i1>* % ; CHECK-LABEL: fcmp_uge_vv_v16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vmflt.vv v25, v28, v8 -; CHECK-NEXT: vmnand.mm v25, v25, v25 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v12, (a1) +; CHECK-NEXT: vmflt.vv v16, v8, v12 +; CHECK-NEXT: vmnand.mm v8, v16, v16 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <16 x float>, <16 x float>* %x %b = load <16 x float>, <16 x float>* %y @@ -304,10 +304,10 @@ define void @fcmp_uge_vv_v16f32_nonans(<16 x float>* %x, <16 x float>* %y, <16 x ; CHECK-LABEL: fcmp_uge_vv_v16f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vmfle.vv v25, v8, v28 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v12, (a1) +; CHECK-NEXT: vmfle.vv v16, v12, v8 +; CHECK-NEXT: vsm.v v16, (a2) ; CHECK-NEXT: ret %a = load <16 x float>, <16 x float>* %x %b = load <16 x float>, <16 x float>* %y @@ -320,11 +320,11 @@ define void @fcmp_ult_vv_v8f64(<8 x double>* %x, <8 x double>* %y, <8 x i1>* %z) ; CHECK-LABEL: fcmp_ult_vv_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vmfle.vv v25, v8, v28 -; CHECK-NEXT: vmnand.mm v25, v25, v25 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v12, (a1) +; CHECK-NEXT: vmfle.vv v16, v12, v8 +; CHECK-NEXT: vmnand.mm v8, v16, v16 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <8 x double>, <8 x double>* %x %b = load <8 x double>, <8 x double>* %y @@ -337,10 +337,10 @@ define void @fcmp_ult_vv_v8f64_nonans(<8 x double>* %x, <8 x double>* %y, <8 x i ; CHECK-LABEL: fcmp_ult_vv_v8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vmflt.vv v25, v28, v8 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v12, (a1) +; CHECK-NEXT: vmflt.vv v16, v8, v12 +; CHECK-NEXT: vsm.v v16, (a2) ; CHECK-NEXT: ret %a = load <8 x double>, <8 x double>* %x %b = load <8 x double>, <8 x double>* %y @@ -356,9 +356,9 @@ define void @fcmp_ugt_vv_v64f16(<64 x half>* %x, <64 x half>* %y, <64 x i1>* %z) ; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, mu ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v16, (a1) -; CHECK-NEXT: vmfle.vv v25, v8, v16 -; CHECK-NEXT: vmnand.mm v25, v25, v25 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmfle.vv v24, v8, v16 +; CHECK-NEXT: vmnand.mm v8, v24, v24 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <64 x half>, <64 x half>* %x %b = load <64 x half>, <64 x half>* %y @@ -374,8 +374,8 @@ define void @fcmp_ugt_vv_v64f16_nonans(<64 x half>* %x, <64 x half>* %y, <64 x i ; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, mu ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v16, (a1) -; CHECK-NEXT: vmflt.vv v25, v16, v8 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmflt.vv v24, v16, v8 +; CHECK-NEXT: vsm.v v24, (a2) ; CHECK-NEXT: ret %a = load <64 x half>, <64 x half>* %x %b = load <64 x half>, <64 x half>* %y @@ -391,10 +391,10 @@ define void @fcmp_ueq_vv_v32f32(<32 x float>* %x, <32 x float>* %y, <32 x i1>* % ; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v16, (a1) -; CHECK-NEXT: vmflt.vv v25, v8, v16 -; CHECK-NEXT: vmflt.vv v26, v16, v8 -; CHECK-NEXT: vmnor.mm v25, v26, v25 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmflt.vv v24, v8, v16 +; CHECK-NEXT: vmflt.vv v25, v16, v8 +; CHECK-NEXT: vmnor.mm v8, v25, v24 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <32 x float>, <32 x float>* %x %b = load <32 x float>, <32 x float>* %y @@ -410,8 +410,8 @@ define void @fcmp_ueq_vv_v32f32_nonans(<32 x float>* %x, <32 x float>* %y, <32 x ; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v16, (a1) -; CHECK-NEXT: vmfeq.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmfeq.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a2) ; CHECK-NEXT: ret %a = load <32 x float>, <32 x float>* %x %b = load <32 x float>, <32 x float>* %y @@ -426,10 +426,10 @@ define void @fcmp_one_vv_v8f64(<16 x double>* %x, <16 x double>* %y, <16 x i1>* ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v16, (a1) -; CHECK-NEXT: vmflt.vv v25, v8, v16 -; CHECK-NEXT: vmflt.vv v26, v16, v8 -; CHECK-NEXT: vmor.mm v25, v26, v25 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmflt.vv v24, v8, v16 +; CHECK-NEXT: vmflt.vv v25, v16, v8 +; CHECK-NEXT: vmor.mm v8, v25, v24 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <16 x double>, <16 x double>* %x %b = load <16 x double>, <16 x double>* %y @@ -444,8 +444,8 @@ define void @fcmp_one_vv_v8f64_nonans(<16 x double>* %x, <16 x double>* %y, <16 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v16, (a1) -; CHECK-NEXT: vmfne.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmfne.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a2) ; CHECK-NEXT: ret %a = load <16 x double>, <16 x double>* %x %b = load <16 x double>, <16 x double>* %y @@ -458,21 +458,21 @@ define void @fcmp_ord_vv_v4f16(<4 x half>* %x, <4 x half>* %y, <4 x i1>* %z) { ; CHECK-LABEL: fcmp_ord_vv_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a1) -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vmfeq.vv v25, v25, v25 -; CHECK-NEXT: vmfeq.vv v26, v26, v26 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vmfeq.vv v8, v8, v8 +; CHECK-NEXT: vmfeq.vv v9, v9, v9 +; CHECK-NEXT: vmand.mm v0, v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <4 x half>, <4 x half>* %x %b = load <4 x half>, <4 x half>* %y @@ -485,21 +485,21 @@ define void @fcmp_uno_vv_v4f16(<2 x half>* %x, <2 x half>* %y, <2 x i1>* %z) { ; CHECK-LABEL: fcmp_uno_vv_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a1) -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vmfne.vv v25, v25, v25 -; CHECK-NEXT: vmfne.vv v26, v26, v26 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vmfne.vv v8, v8, v8 +; CHECK-NEXT: vmfne.vv v9, v9, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <2 x half>, <2 x half>* %x %b = load <2 x half>, <2 x half>* %y @@ -512,9 +512,9 @@ define void @fcmp_oeq_vf_v8f16(<8 x half>* %x, half %y, <8 x i1>* %z) { ; CHECK-LABEL: fcmp_oeq_vf_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vmfeq.vf v25, v25, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmfeq.vf v8, v8, fa0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -528,9 +528,9 @@ define void @fcmp_oeq_vf_v8f16_nonans(<8 x half>* %x, half %y, <8 x i1>* %z) { ; CHECK-LABEL: fcmp_oeq_vf_v8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vmfeq.vf v25, v25, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmfeq.vf v8, v8, fa0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -544,18 +544,18 @@ define void @fcmp_une_vf_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) { ; CHECK-LABEL: fcmp_une_vf_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vmfne.vf v0, v25, fa0 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -569,18 +569,18 @@ define void @fcmp_une_vf_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) { ; CHECK-LABEL: fcmp_une_vf_v4f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vmfne.vf v0, v25, fa0 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -594,18 +594,18 @@ define void @fcmp_ogt_vf_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) { ; CHECK-LABEL: fcmp_ogt_vf_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vmfgt.vf v0, v25, fa0 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -619,18 +619,18 @@ define void @fcmp_ogt_vf_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z) ; CHECK-LABEL: fcmp_ogt_vf_v2f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vmfgt.vf v0, v25, fa0 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -644,9 +644,9 @@ define void @fcmp_olt_vf_v16f16(<16 x half>* %x, half %y, <16 x i1>* %z) { ; CHECK-LABEL: fcmp_olt_vf_v16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vmflt.vf v25, v26, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmflt.vf v10, v8, fa0 +; CHECK-NEXT: vsm.v v10, (a1) ; CHECK-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = insertelement <16 x half> undef, half %y, i32 0 @@ -660,9 +660,9 @@ define void @fcmp_olt_vf_v16f16_nonans(<16 x half>* %x, half %y, <16 x i1>* %z) ; CHECK-LABEL: fcmp_olt_vf_v16f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vmflt.vf v25, v26, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmflt.vf v10, v8, fa0 +; CHECK-NEXT: vsm.v v10, (a1) ; CHECK-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = insertelement <16 x half> undef, half %y, i32 0 @@ -676,9 +676,9 @@ define void @fcmp_oge_vf_v8f32(<8 x float>* %x, float %y, <8 x i1>* %z) { ; CHECK-LABEL: fcmp_oge_vf_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vmfge.vf v25, v26, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmfge.vf v10, v8, fa0 +; CHECK-NEXT: vsm.v v10, (a1) ; CHECK-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = insertelement <8 x float> undef, float %y, i32 0 @@ -692,9 +692,9 @@ define void @fcmp_oge_vf_v8f32_nonans(<8 x float>* %x, float %y, <8 x i1>* %z) { ; CHECK-LABEL: fcmp_oge_vf_v8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vmfge.vf v25, v26, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmfge.vf v10, v8, fa0 +; CHECK-NEXT: vsm.v v10, (a1) ; CHECK-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = insertelement <8 x float> undef, float %y, i32 0 @@ -708,18 +708,18 @@ define void @fcmp_ole_vf_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) { ; CHECK-LABEL: fcmp_ole_vf_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) -; CHECK-NEXT: vmfle.vf v0, v26, fa0 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = insertelement <4 x double> undef, double %y, i32 0 @@ -733,18 +733,18 @@ define void @fcmp_ole_vf_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z) ; CHECK-LABEL: fcmp_ole_vf_v4f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) -; CHECK-NEXT: vmfle.vf v0, v26, fa0 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = insertelement <4 x double> undef, double %y, i32 0 @@ -759,10 +759,10 @@ define void @fcmp_ule_vf_v32f16(<32 x half>* %x, half %y, <32 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vmfgt.vf v25, v28, fa0 -; CHECK-NEXT: vmnand.mm v25, v25, v25 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmfgt.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v8, v12, v12 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <32 x half>, <32 x half>* %x %b = insertelement <32 x half> undef, half %y, i32 0 @@ -777,9 +777,9 @@ define void @fcmp_ule_vf_v32f16_nonans(<32 x half>* %x, half %y, <32 x i1>* %z) ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vmfle.vf v25, v28, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmfle.vf v12, v8, fa0 +; CHECK-NEXT: vsm.v v12, (a1) ; CHECK-NEXT: ret %a = load <32 x half>, <32 x half>* %x %b = insertelement <32 x half> undef, half %y, i32 0 @@ -793,10 +793,10 @@ define void @fcmp_uge_vf_v16f32(<16 x float>* %x, float %y, <16 x i1>* %z) { ; CHECK-LABEL: fcmp_uge_vf_v16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vmflt.vf v25, v28, fa0 -; CHECK-NEXT: vmnand.mm v25, v25, v25 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmflt.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v8, v12, v12 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <16 x float>, <16 x float>* %x %b = insertelement <16 x float> undef, float %y, i32 0 @@ -810,9 +810,9 @@ define void @fcmp_uge_vf_v16f32_nonans(<16 x float>* %x, float %y, <16 x i1>* %z ; CHECK-LABEL: fcmp_uge_vf_v16f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vmfge.vf v25, v28, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmfge.vf v12, v8, fa0 +; CHECK-NEXT: vsm.v v12, (a1) ; CHECK-NEXT: ret %a = load <16 x float>, <16 x float>* %x %b = insertelement <16 x float> undef, float %y, i32 0 @@ -826,10 +826,10 @@ define void @fcmp_ult_vf_v8f64(<8 x double>* %x, double %y, <8 x i1>* %z) { ; CHECK-LABEL: fcmp_ult_vf_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vmfge.vf v25, v28, fa0 -; CHECK-NEXT: vmnand.mm v25, v25, v25 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vmfge.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v8, v12, v12 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <8 x double>, <8 x double>* %x %b = insertelement <8 x double> undef, double %y, i32 0 @@ -843,9 +843,9 @@ define void @fcmp_ult_vf_v8f64_nonans(<8 x double>* %x, double %y, <8 x i1>* %z) ; CHECK-LABEL: fcmp_ult_vf_v8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vmflt.vf v25, v28, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vmflt.vf v12, v8, fa0 +; CHECK-NEXT: vsm.v v12, (a1) ; CHECK-NEXT: ret %a = load <8 x double>, <8 x double>* %x %b = insertelement <8 x double> undef, double %y, i32 0 @@ -861,9 +861,9 @@ define void @fcmp_ugt_vf_v64f16(<64 x half>* %x, half %y, <64 x i1>* %z) { ; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmfle.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v25, v25, v25 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmfle.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v8, v16, v16 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <64 x half>, <64 x half>* %x %b = insertelement <64 x half> undef, half %y, i32 0 @@ -879,8 +879,8 @@ define void @fcmp_ugt_vf_v64f16_nonans(<64 x half>* %x, half %y, <64 x i1>* %z) ; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmfgt.vf v16, v8, fa0 +; CHECK-NEXT: vsm.v v16, (a1) ; CHECK-NEXT: ret %a = load <64 x half>, <64 x half>* %x %b = insertelement <64 x half> undef, half %y, i32 0 @@ -896,10 +896,10 @@ define void @fcmp_ueq_vf_v32f32(<32 x float>* %x, float %y, <32 x i1>* %z) { ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmfgt.vf v26, v8, fa0 -; CHECK-NEXT: vmnor.mm v25, v26, v25 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmflt.vf v16, v8, fa0 +; CHECK-NEXT: vmfgt.vf v17, v8, fa0 +; CHECK-NEXT: vmnor.mm v8, v17, v16 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <32 x float>, <32 x float>* %x %b = insertelement <32 x float> undef, float %y, i32 0 @@ -915,8 +915,8 @@ define void @fcmp_ueq_vf_v32f32_nonans(<32 x float>* %x, float %y, <32 x i1>* %z ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmfeq.vf v25, v8, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmfeq.vf v16, v8, fa0 +; CHECK-NEXT: vsm.v v16, (a1) ; CHECK-NEXT: ret %a = load <32 x float>, <32 x float>* %x %b = insertelement <32 x float> undef, float %y, i32 0 @@ -931,10 +931,10 @@ define void @fcmp_one_vf_v8f64(<16 x double>* %x, double %y, <16 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmfgt.vf v26, v8, fa0 -; CHECK-NEXT: vmor.mm v25, v26, v25 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmflt.vf v16, v8, fa0 +; CHECK-NEXT: vmfgt.vf v17, v8, fa0 +; CHECK-NEXT: vmor.mm v8, v17, v16 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <16 x double>, <16 x double>* %x %b = insertelement <16 x double> undef, double %y, i32 0 @@ -949,8 +949,8 @@ define void @fcmp_one_vf_v8f64_nonans(<16 x double>* %x, double %y, <16 x i1>* % ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfne.vf v25, v8, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmfne.vf v16, v8, fa0 +; CHECK-NEXT: vsm.v v16, (a1) ; CHECK-NEXT: ret %a = load <16 x double>, <16 x double>* %x %b = insertelement <16 x double> undef, double %y, i32 0 @@ -964,21 +964,21 @@ define void @fcmp_ord_vf_v4f16(<4 x half>* %x, half %y, <4 x i1>* %z) { ; CHECK-LABEL: fcmp_ord_vf_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfeq.vf v26, v26, fa0 -; CHECK-NEXT: vmfeq.vv v25, v25, v25 -; CHECK-NEXT: vmand.mm v0, v25, v26 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfmv.v.f v9, fa0 +; CHECK-NEXT: vmfeq.vf v9, v9, fa0 +; CHECK-NEXT: vmfeq.vv v8, v8, v8 +; CHECK-NEXT: vmand.mm v0, v8, v9 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x half>, <4 x half>* %x %b = insertelement <4 x half> undef, half %y, i32 0 @@ -992,21 +992,21 @@ define void @fcmp_uno_vf_v4f16(<2 x half>* %x, half %y, <2 x i1>* %z) { ; CHECK-LABEL: fcmp_uno_vf_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfne.vf v26, v26, fa0 -; CHECK-NEXT: vmfne.vv v25, v25, v25 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfmv.v.f v9, fa0 +; CHECK-NEXT: vmfne.vf v9, v9, fa0 +; CHECK-NEXT: vmfne.vv v8, v8, v8 +; CHECK-NEXT: vmor.mm v0, v8, v9 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x half>, <2 x half>* %x %b = insertelement <2 x half> undef, half %y, i32 0 @@ -1020,9 +1020,9 @@ define void @fcmp_oeq_fv_v8f16(<8 x half>* %x, half %y, <8 x i1>* %z) { ; CHECK-LABEL: fcmp_oeq_fv_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vmfeq.vf v25, v25, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmfeq.vf v8, v8, fa0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1036,9 +1036,9 @@ define void @fcmp_oeq_fv_v8f16_nonans(<8 x half>* %x, half %y, <8 x i1>* %z) { ; CHECK-LABEL: fcmp_oeq_fv_v8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vmfeq.vf v25, v25, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmfeq.vf v8, v8, fa0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1052,18 +1052,18 @@ define void @fcmp_une_fv_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) { ; CHECK-LABEL: fcmp_une_fv_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vmfne.vf v0, v25, fa0 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1077,18 +1077,18 @@ define void @fcmp_une_fv_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) { ; CHECK-LABEL: fcmp_une_fv_v4f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vmfne.vf v0, v25, fa0 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1102,18 +1102,18 @@ define void @fcmp_ogt_fv_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) { ; CHECK-LABEL: fcmp_ogt_fv_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vmflt.vf v0, v25, fa0 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1127,18 +1127,18 @@ define void @fcmp_ogt_fv_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z) ; CHECK-LABEL: fcmp_ogt_fv_v2f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vmflt.vf v0, v25, fa0 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1152,9 +1152,9 @@ define void @fcmp_olt_fv_v16f16(<16 x half>* %x, half %y, <16 x i1>* %z) { ; CHECK-LABEL: fcmp_olt_fv_v16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vmfgt.vf v25, v26, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmfgt.vf v10, v8, fa0 +; CHECK-NEXT: vsm.v v10, (a1) ; CHECK-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = insertelement <16 x half> undef, half %y, i32 0 @@ -1168,9 +1168,9 @@ define void @fcmp_olt_fv_v16f16_nonans(<16 x half>* %x, half %y, <16 x i1>* %z) ; CHECK-LABEL: fcmp_olt_fv_v16f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vmfgt.vf v25, v26, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmfgt.vf v10, v8, fa0 +; CHECK-NEXT: vsm.v v10, (a1) ; CHECK-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = insertelement <16 x half> undef, half %y, i32 0 @@ -1184,9 +1184,9 @@ define void @fcmp_oge_fv_v8f32(<8 x float>* %x, float %y, <8 x i1>* %z) { ; CHECK-LABEL: fcmp_oge_fv_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vmfle.vf v25, v26, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmfle.vf v10, v8, fa0 +; CHECK-NEXT: vsm.v v10, (a1) ; CHECK-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = insertelement <8 x float> undef, float %y, i32 0 @@ -1200,9 +1200,9 @@ define void @fcmp_oge_fv_v8f32_nonans(<8 x float>* %x, float %y, <8 x i1>* %z) { ; CHECK-LABEL: fcmp_oge_fv_v8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vmfle.vf v25, v26, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmfle.vf v10, v8, fa0 +; CHECK-NEXT: vsm.v v10, (a1) ; CHECK-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = insertelement <8 x float> undef, float %y, i32 0 @@ -1216,18 +1216,18 @@ define void @fcmp_ole_fv_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) { ; CHECK-LABEL: fcmp_ole_fv_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) -; CHECK-NEXT: vmfge.vf v0, v26, fa0 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = insertelement <4 x double> undef, double %y, i32 0 @@ -1241,18 +1241,18 @@ define void @fcmp_ole_fv_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z) ; CHECK-LABEL: fcmp_ole_fv_v4f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) -; CHECK-NEXT: vmfge.vf v0, v26, fa0 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = insertelement <4 x double> undef, double %y, i32 0 @@ -1267,10 +1267,10 @@ define void @fcmp_ule_fv_v32f16(<32 x half>* %x, half %y, <32 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vmflt.vf v25, v28, fa0 -; CHECK-NEXT: vmnand.mm v25, v25, v25 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmflt.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v8, v12, v12 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <32 x half>, <32 x half>* %x %b = insertelement <32 x half> undef, half %y, i32 0 @@ -1285,9 +1285,9 @@ define void @fcmp_ule_fv_v32f16_nonans(<32 x half>* %x, half %y, <32 x i1>* %z) ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vmfge.vf v25, v28, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmfge.vf v12, v8, fa0 +; CHECK-NEXT: vsm.v v12, (a1) ; CHECK-NEXT: ret %a = load <32 x half>, <32 x half>* %x %b = insertelement <32 x half> undef, half %y, i32 0 @@ -1301,10 +1301,10 @@ define void @fcmp_uge_fv_v16f32(<16 x float>* %x, float %y, <16 x i1>* %z) { ; CHECK-LABEL: fcmp_uge_fv_v16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vmfgt.vf v25, v28, fa0 -; CHECK-NEXT: vmnand.mm v25, v25, v25 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmfgt.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v8, v12, v12 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <16 x float>, <16 x float>* %x %b = insertelement <16 x float> undef, float %y, i32 0 @@ -1318,9 +1318,9 @@ define void @fcmp_uge_fv_v16f32_nonans(<16 x float>* %x, float %y, <16 x i1>* %z ; CHECK-LABEL: fcmp_uge_fv_v16f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vmfle.vf v25, v28, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmfle.vf v12, v8, fa0 +; CHECK-NEXT: vsm.v v12, (a1) ; CHECK-NEXT: ret %a = load <16 x float>, <16 x float>* %x %b = insertelement <16 x float> undef, float %y, i32 0 @@ -1334,10 +1334,10 @@ define void @fcmp_ult_fv_v8f64(<8 x double>* %x, double %y, <8 x i1>* %z) { ; CHECK-LABEL: fcmp_ult_fv_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vmfle.vf v25, v28, fa0 -; CHECK-NEXT: vmnand.mm v25, v25, v25 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vmfle.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v8, v12, v12 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <8 x double>, <8 x double>* %x %b = insertelement <8 x double> undef, double %y, i32 0 @@ -1351,9 +1351,9 @@ define void @fcmp_ult_fv_v8f64_nonans(<8 x double>* %x, double %y, <8 x i1>* %z) ; CHECK-LABEL: fcmp_ult_fv_v8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vmfgt.vf v25, v28, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vmfgt.vf v12, v8, fa0 +; CHECK-NEXT: vsm.v v12, (a1) ; CHECK-NEXT: ret %a = load <8 x double>, <8 x double>* %x %b = insertelement <8 x double> undef, double %y, i32 0 @@ -1369,9 +1369,9 @@ define void @fcmp_ugt_fv_v64f16(<64 x half>* %x, half %y, <64 x i1>* %z) { ; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmfge.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v25, v25, v25 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmfge.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v8, v16, v16 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <64 x half>, <64 x half>* %x %b = insertelement <64 x half> undef, half %y, i32 0 @@ -1387,8 +1387,8 @@ define void @fcmp_ugt_fv_v64f16_nonans(<64 x half>* %x, half %y, <64 x i1>* %z) ; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmflt.vf v16, v8, fa0 +; CHECK-NEXT: vsm.v v16, (a1) ; CHECK-NEXT: ret %a = load <64 x half>, <64 x half>* %x %b = insertelement <64 x half> undef, half %y, i32 0 @@ -1404,10 +1404,10 @@ define void @fcmp_ueq_fv_v32f32(<32 x float>* %x, float %y, <32 x i1>* %z) { ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmflt.vf v26, v8, fa0 -; CHECK-NEXT: vmnor.mm v25, v26, v25 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmfgt.vf v16, v8, fa0 +; CHECK-NEXT: vmflt.vf v17, v8, fa0 +; CHECK-NEXT: vmnor.mm v8, v17, v16 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <32 x float>, <32 x float>* %x %b = insertelement <32 x float> undef, float %y, i32 0 @@ -1423,8 +1423,8 @@ define void @fcmp_ueq_fv_v32f32_nonans(<32 x float>* %x, float %y, <32 x i1>* %z ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmfeq.vf v25, v8, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmfeq.vf v16, v8, fa0 +; CHECK-NEXT: vsm.v v16, (a1) ; CHECK-NEXT: ret %a = load <32 x float>, <32 x float>* %x %b = insertelement <32 x float> undef, float %y, i32 0 @@ -1439,10 +1439,10 @@ define void @fcmp_one_fv_v8f64(<16 x double>* %x, double %y, <16 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmflt.vf v26, v8, fa0 -; CHECK-NEXT: vmor.mm v25, v26, v25 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmfgt.vf v16, v8, fa0 +; CHECK-NEXT: vmflt.vf v17, v8, fa0 +; CHECK-NEXT: vmor.mm v8, v17, v16 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <16 x double>, <16 x double>* %x %b = insertelement <16 x double> undef, double %y, i32 0 @@ -1457,8 +1457,8 @@ define void @fcmp_one_fv_v8f64_nonans(<16 x double>* %x, double %y, <16 x i1>* % ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfne.vf v25, v8, fa0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmfne.vf v16, v8, fa0 +; CHECK-NEXT: vsm.v v16, (a1) ; CHECK-NEXT: ret %a = load <16 x double>, <16 x double>* %x %b = insertelement <16 x double> undef, double %y, i32 0 @@ -1472,21 +1472,21 @@ define void @fcmp_ord_fv_v4f16(<4 x half>* %x, half %y, <4 x i1>* %z) { ; CHECK-LABEL: fcmp_ord_fv_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfeq.vf v26, v26, fa0 -; CHECK-NEXT: vmfeq.vv v25, v25, v25 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfmv.v.f v9, fa0 +; CHECK-NEXT: vmfeq.vf v9, v9, fa0 +; CHECK-NEXT: vmfeq.vv v8, v8, v8 +; CHECK-NEXT: vmand.mm v0, v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x half>, <4 x half>* %x %b = insertelement <4 x half> undef, half %y, i32 0 @@ -1500,21 +1500,21 @@ define void @fcmp_uno_fv_v4f16(<2 x half>* %x, half %y, <2 x i1>* %z) { ; CHECK-LABEL: fcmp_uno_fv_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfne.vf v26, v26, fa0 -; CHECK-NEXT: vmfne.vv v25, v25, v25 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfmv.v.f v9, fa0 +; CHECK-NEXT: vmfne.vf v9, v9, fa0 +; CHECK-NEXT: vmfne.vv v8, v8, v8 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x half>, <2 x half>* %x %b = insertelement <2 x half> undef, half %y, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll index 3a484b2e36353e5fe380384fcabae9257573daf2..35eaa42435224511e5b42e5b59166875f6afad81 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll @@ -86,10 +86,10 @@ define <4 x double> @vrgather_permute_shuffle_vu_v4f64(<4 x double> %x) { ; RV32-NEXT: lui a0, %hi(.LCPI4_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI4_0) ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; RV32-NEXT: vle16.v v25, (a0) +; RV32-NEXT: vle16.v v12, (a0) ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; RV32-NEXT: vrgatherei16.vv v26, v8, v25 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vrgatherei16.vv v10, v8, v12 +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_permute_shuffle_vu_v4f64: @@ -97,9 +97,9 @@ define <4 x double> @vrgather_permute_shuffle_vu_v4f64(<4 x double> %x) { ; RV64-NEXT: lui a0, %hi(.LCPI4_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI4_0) ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v28, (a0) -; RV64-NEXT: vrgather.vv v26, v8, v28 -; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: vle64.v v12, (a0) +; RV64-NEXT: vrgather.vv v10, v8, v12 +; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %s = shufflevector <4 x double> %x, <4 x double> undef, <4 x i32> ret <4 x double> %s @@ -111,10 +111,10 @@ define <4 x double> @vrgather_permute_shuffle_uv_v4f64(<4 x double> %x) { ; RV32-NEXT: lui a0, %hi(.LCPI5_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI5_0) ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; RV32-NEXT: vle16.v v25, (a0) +; RV32-NEXT: vle16.v v12, (a0) ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; RV32-NEXT: vrgatherei16.vv v26, v8, v25 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vrgatherei16.vv v10, v8, v12 +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_permute_shuffle_uv_v4f64: @@ -122,9 +122,9 @@ define <4 x double> @vrgather_permute_shuffle_uv_v4f64(<4 x double> %x) { ; RV64-NEXT: lui a0, %hi(.LCPI5_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI5_0) ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v28, (a0) -; RV64-NEXT: vrgather.vv v26, v8, v28 -; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: vle64.v v12, (a0) +; RV64-NEXT: vrgather.vv v10, v8, v12 +; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %s = shufflevector <4 x double> undef, <4 x double> %x, <4 x i32> ret <4 x double> %s @@ -136,15 +136,15 @@ define <4 x double> @vrgather_shuffle_vv_v4f64(<4 x double> %x, <4 x double> %y) ; RV32-NEXT: lui a0, %hi(.LCPI6_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI6_0) ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; RV32-NEXT: vle16.v v25, (a0) +; RV32-NEXT: vle16.v v14, (a0) ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; RV32-NEXT: vrgatherei16.vv v26, v8, v25 +; RV32-NEXT: vrgatherei16.vv v12, v8, v14 ; RV32-NEXT: addi a0, zero, 8 ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vmv.s.x v0, a0 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vrgather.vi v26, v10, 1, v0.t -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vrgather.vi v12, v10, 1, v0.t +; RV32-NEXT: vmv2r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_shuffle_vv_v4f64: @@ -152,14 +152,14 @@ define <4 x double> @vrgather_shuffle_vv_v4f64(<4 x double> %x, <4 x double> %y) ; RV64-NEXT: lui a0, %hi(.LCPI6_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI6_0) ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v28, (a0) -; RV64-NEXT: vrgather.vv v26, v8, v28 +; RV64-NEXT: vle64.v v14, (a0) +; RV64-NEXT: vrgather.vv v12, v8, v14 ; RV64-NEXT: addi a0, zero, 8 ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV64-NEXT: vmv.s.x v0, a0 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vrgather.vi v26, v10, 1, v0.t -; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: vrgather.vi v12, v10, 1, v0.t +; RV64-NEXT: vmv2r.v v8, v12 ; RV64-NEXT: ret %s = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> ret <4 x double> %s @@ -174,12 +174,12 @@ define <4 x double> @vrgather_shuffle_xv_v4f64(<4 x double> %x) { ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV32-NEXT: lui a0, %hi(.LCPI7_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI7_0) -; RV32-NEXT: vlse64.v v26, (a0), zero -; RV32-NEXT: vid.v v25 -; RV32-NEXT: vrsub.vi v25, v25, 4 +; RV32-NEXT: vlse64.v v10, (a0), zero +; RV32-NEXT: vid.v v12 +; RV32-NEXT: vrsub.vi v12, v12, 4 ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; RV32-NEXT: vrgatherei16.vv v26, v8, v25, v0.t -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vrgatherei16.vv v10, v8, v12, v0.t +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_shuffle_xv_v4f64: @@ -190,11 +190,11 @@ define <4 x double> @vrgather_shuffle_xv_v4f64(<4 x double> %x) { ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: lui a0, %hi(.LCPI7_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI7_0) -; RV64-NEXT: vlse64.v v26, (a0), zero -; RV64-NEXT: vid.v v28 -; RV64-NEXT: vrsub.vi v28, v28, 4 -; RV64-NEXT: vrgather.vv v26, v8, v28, v0.t -; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: vlse64.v v10, (a0), zero +; RV64-NEXT: vid.v v12 +; RV64-NEXT: vrsub.vi v12, v12, 4 +; RV64-NEXT: vrgather.vv v10, v8, v12, v0.t +; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %s = shufflevector <4 x double> , <4 x double> %x, <4 x i32> ret <4 x double> %s @@ -204,33 +204,33 @@ define <4 x double> @vrgather_shuffle_vx_v4f64(<4 x double> %x) { ; RV32-LABEL: vrgather_shuffle_vx_v4f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; RV32-NEXT: vid.v v25 +; RV32-NEXT: vid.v v10 ; RV32-NEXT: addi a0, zero, 3 -; RV32-NEXT: vmul.vx v25, v25, a0 +; RV32-NEXT: vmul.vx v12, v10, a0 ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vmv.s.x v0, a0 ; RV32-NEXT: lui a0, %hi(.LCPI8_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI8_0) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vlse64.v v26, (a0), zero -; RV32-NEXT: vrgatherei16.vv v26, v8, v25, v0.t -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vlse64.v v10, (a0), zero +; RV32-NEXT: vrgatherei16.vv v10, v8, v12, v0.t +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_shuffle_vx_v4f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vid.v v26 +; RV64-NEXT: vid.v v10 ; RV64-NEXT: addi a0, zero, 3 -; RV64-NEXT: vmul.vx v28, v26, a0 +; RV64-NEXT: vmul.vx v12, v10, a0 ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV64-NEXT: vmv.s.x v0, a0 ; RV64-NEXT: lui a0, %hi(.LCPI8_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI8_0) ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vlse64.v v26, (a0), zero -; RV64-NEXT: vrgather.vv v26, v8, v28, v0.t -; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: vlse64.v v10, (a0), zero +; RV64-NEXT: vrgather.vv v10, v8, v12, v0.t +; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %s = shufflevector <4 x double> %x, <4 x double> , <4 x i32> ret <4 x double> %s diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll index 09faa302e7d9a46b298411d6a7d1cfe38dcf934d..02c00403780df53c4ac2f412a75d1bb3706a7e2e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll @@ -8,8 +8,8 @@ define void @splat_v8f16(<8 x half>* %x, half %y) { ; CHECK-LABEL: splat_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <8 x half> undef, half %y, i32 0 %b = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> zeroinitializer @@ -21,8 +21,8 @@ define void @splat_v4f32(<4 x float>* %x, float %y) { ; CHECK-LABEL: splat_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <4 x float> undef, float %y, i32 0 %b = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> zeroinitializer @@ -34,8 +34,8 @@ define void @splat_v2f64(<2 x double>* %x, double %y) { ; CHECK-LABEL: splat_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <2 x double> undef, double %y, i32 0 %b = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> zeroinitializer @@ -47,17 +47,17 @@ define void @splat_16f16(<16 x half>* %x, half %y) { ; LMULMAX2-LABEL: splat_16f16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vfmv.v.f v26, fa0 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vfmv.v.f v8, fa0 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_16f16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vfmv.v.f v25, fa0 +; LMULMAX1-NEXT: vfmv.v.f v8, fa0 ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vse16.v v25, (a1) -; LMULMAX1-NEXT: vse16.v v25, (a0) +; LMULMAX1-NEXT: vse16.v v8, (a1) +; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: ret %a = insertelement <16 x half> undef, half %y, i32 0 %b = shufflevector <16 x half> %a, <16 x half> undef, <16 x i32> zeroinitializer @@ -69,17 +69,17 @@ define void @splat_v8f32(<8 x float>* %x, float %y) { ; LMULMAX2-LABEL: splat_v8f32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vfmv.v.f v26, fa0 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vfmv.v.f v8, fa0 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_v8f32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vfmv.v.f v25, fa0 +; LMULMAX1-NEXT: vfmv.v.f v8, fa0 ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vse32.v v25, (a1) -; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: vse32.v v8, (a1) +; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: ret %a = insertelement <8 x float> undef, float %y, i32 0 %b = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> zeroinitializer @@ -91,17 +91,17 @@ define void @splat_v4f64(<4 x double>* %x, double %y) { ; LMULMAX2-LABEL: splat_v4f64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vfmv.v.f v26, fa0 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vfmv.v.f v8, fa0 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_v4f64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vfmv.v.f v25, fa0 +; LMULMAX1-NEXT: vfmv.v.f v8, fa0 ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vse64.v v25, (a1) -; LMULMAX1-NEXT: vse64.v v25, (a0) +; LMULMAX1-NEXT: vse64.v v8, (a1) +; LMULMAX1-NEXT: vse64.v v8, (a0) ; LMULMAX1-NEXT: ret %a = insertelement <4 x double> undef, double %y, i32 0 %b = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> zeroinitializer @@ -113,8 +113,8 @@ define void @splat_zero_v8f16(<8 x half>* %x) { ; CHECK-LABEL: splat_zero_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <8 x half> undef, half 0.0, i32 0 %b = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> zeroinitializer @@ -126,8 +126,8 @@ define void @splat_zero_v4f32(<4 x float>* %x) { ; CHECK-LABEL: splat_zero_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <4 x float> undef, float 0.0, i32 0 %b = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> zeroinitializer @@ -139,8 +139,8 @@ define void @splat_zero_v2f64(<2 x double>* %x) { ; CHECK-LABEL: splat_zero_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <2 x double> undef, double 0.0, i32 0 %b = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> zeroinitializer @@ -152,17 +152,17 @@ define void @splat_zero_16f16(<16 x half>* %x) { ; LMULMAX2-LABEL: splat_zero_16f16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v26, 0 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vmv.v.i v8, 0 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_zero_16f16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vse16.v v25, (a0) +; LMULMAX1-NEXT: vmv.v.i v8, 0 +; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vse16.v v25, (a0) +; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: ret %a = insertelement <16 x half> undef, half 0.0, i32 0 %b = shufflevector <16 x half> %a, <16 x half> undef, <16 x i32> zeroinitializer @@ -174,17 +174,17 @@ define void @splat_zero_v8f32(<8 x float>* %x) { ; LMULMAX2-LABEL: splat_zero_v8f32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v26, 0 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vmv.v.i v8, 0 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_zero_v8f32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: vmv.v.i v8, 0 +; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: ret %a = insertelement <8 x float> undef, float 0.0, i32 0 %b = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> zeroinitializer @@ -196,17 +196,17 @@ define void @splat_zero_v4f64(<4 x double>* %x) { ; LMULMAX2-LABEL: splat_zero_v4f64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v26, 0 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vmv.v.i v8, 0 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_zero_v4f64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vse64.v v25, (a0) +; LMULMAX1-NEXT: vmv.v.i v8, 0 +; LMULMAX1-NEXT: vse64.v v8, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vse64.v v25, (a0) +; LMULMAX1-NEXT: vse64.v v8, (a0) ; LMULMAX1-NEXT: ret %a = insertelement <4 x double> undef, double 0.0, i32 0 %b = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll index 51715a9f91dbd5fd019aace14de03f9817596b8c..eab91b5fcca43a206a4b84962449b8597052c603 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll @@ -9,8 +9,8 @@ define void @gather_const_v8f16(<8 x half>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, 10 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vlse16.v v25, (a1), zero -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vlse16.v v8, (a1), zero +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = extractelement <8 x half> %a, i32 5 @@ -25,8 +25,8 @@ define void @gather_const_v4f32(<4 x float>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, 8 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vlse32.v v25, (a1), zero -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vlse32.v v8, (a1), zero +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = extractelement <4 x float> %a, i32 2 @@ -40,8 +40,8 @@ define void @gather_const_v2f64(<2 x double>* %x) { ; CHECK-LABEL: gather_const_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vlse64.v v8, (a0), zero +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = extractelement <2 x double> %a, i32 0 @@ -69,18 +69,18 @@ define void @gather_const_v64f16(<64 x half>* %x) { ; LMULMAX1-NEXT: addi a4, a0, 80 ; LMULMAX1-NEXT: addi a5, a0, 94 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vlse16.v v25, (a5), zero +; LMULMAX1-NEXT: vlse16.v v8, (a5), zero ; LMULMAX1-NEXT: addi a5, a0, 64 ; LMULMAX1-NEXT: addi a1, a0, 112 ; LMULMAX1-NEXT: addi a2, a0, 96 -; LMULMAX1-NEXT: vse16.v v25, (a2) -; LMULMAX1-NEXT: vse16.v v25, (a1) -; LMULMAX1-NEXT: vse16.v v25, (a5) -; LMULMAX1-NEXT: vse16.v v25, (a4) -; LMULMAX1-NEXT: vse16.v v25, (a3) -; LMULMAX1-NEXT: vse16.v v25, (a7) -; LMULMAX1-NEXT: vse16.v v25, (a0) -; LMULMAX1-NEXT: vse16.v v25, (a6) +; LMULMAX1-NEXT: vse16.v v8, (a2) +; LMULMAX1-NEXT: vse16.v v8, (a1) +; LMULMAX1-NEXT: vse16.v v8, (a5) +; LMULMAX1-NEXT: vse16.v v8, (a4) +; LMULMAX1-NEXT: vse16.v v8, (a3) +; LMULMAX1-NEXT: vse16.v v8, (a7) +; LMULMAX1-NEXT: vse16.v v8, (a0) +; LMULMAX1-NEXT: vse16.v v8, (a6) ; LMULMAX1-NEXT: ret %a = load <64 x half>, <64 x half>* %x %b = extractelement <64 x half> %a, i32 47 @@ -108,18 +108,18 @@ define void @gather_const_v32f32(<32 x float>* %x) { ; LMULMAX1-NEXT: addi a4, a0, 80 ; LMULMAX1-NEXT: addi a5, a0, 68 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vlse32.v v25, (a5), zero +; LMULMAX1-NEXT: vlse32.v v8, (a5), zero ; LMULMAX1-NEXT: addi a5, a0, 64 ; LMULMAX1-NEXT: addi a1, a0, 112 ; LMULMAX1-NEXT: addi a2, a0, 96 -; LMULMAX1-NEXT: vse32.v v25, (a2) -; LMULMAX1-NEXT: vse32.v v25, (a1) -; LMULMAX1-NEXT: vse32.v v25, (a5) -; LMULMAX1-NEXT: vse32.v v25, (a4) -; LMULMAX1-NEXT: vse32.v v25, (a3) -; LMULMAX1-NEXT: vse32.v v25, (a7) -; LMULMAX1-NEXT: vse32.v v25, (a0) -; LMULMAX1-NEXT: vse32.v v25, (a6) +; LMULMAX1-NEXT: vse32.v v8, (a2) +; LMULMAX1-NEXT: vse32.v v8, (a1) +; LMULMAX1-NEXT: vse32.v v8, (a5) +; LMULMAX1-NEXT: vse32.v v8, (a4) +; LMULMAX1-NEXT: vse32.v v8, (a3) +; LMULMAX1-NEXT: vse32.v v8, (a7) +; LMULMAX1-NEXT: vse32.v v8, (a0) +; LMULMAX1-NEXT: vse32.v v8, (a6) ; LMULMAX1-NEXT: ret %a = load <32 x float>, <32 x float>* %x %b = extractelement <32 x float> %a, i32 17 @@ -145,18 +145,18 @@ define void @gather_const_v16f64(<16 x double>* %x) { ; LMULMAX1-NEXT: addi a3, a0, 32 ; LMULMAX1-NEXT: addi a4, a0, 80 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vlse64.v v25, (a4), zero +; LMULMAX1-NEXT: vlse64.v v8, (a4), zero ; LMULMAX1-NEXT: addi a5, a0, 64 ; LMULMAX1-NEXT: addi a1, a0, 112 ; LMULMAX1-NEXT: addi a2, a0, 96 -; LMULMAX1-NEXT: vse64.v v25, (a2) -; LMULMAX1-NEXT: vse64.v v25, (a1) -; LMULMAX1-NEXT: vse64.v v25, (a5) -; LMULMAX1-NEXT: vse64.v v25, (a4) -; LMULMAX1-NEXT: vse64.v v25, (a3) -; LMULMAX1-NEXT: vse64.v v25, (a7) -; LMULMAX1-NEXT: vse64.v v25, (a0) -; LMULMAX1-NEXT: vse64.v v25, (a6) +; LMULMAX1-NEXT: vse64.v v8, (a2) +; LMULMAX1-NEXT: vse64.v v8, (a1) +; LMULMAX1-NEXT: vse64.v v8, (a5) +; LMULMAX1-NEXT: vse64.v v8, (a4) +; LMULMAX1-NEXT: vse64.v v8, (a3) +; LMULMAX1-NEXT: vse64.v v8, (a7) +; LMULMAX1-NEXT: vse64.v v8, (a0) +; LMULMAX1-NEXT: vse64.v v8, (a6) ; LMULMAX1-NEXT: ret %a = load <16 x double>, <16 x double>* %x %b = extractelement <16 x double> %a, i32 10 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll index f5ccc11b2907aeb7eae032e7ba5ab076af63d5e4..86291ef446ba08a9a7879128a29c902ba5810ac3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll @@ -8,10 +8,10 @@ define void @fadd_v8f16(<8 x half>* %x, <8 x half>* %y) { ; CHECK-LABEL: fadd_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vfadd.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vfadd.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -24,10 +24,10 @@ define void @fadd_v4f32(<4 x float>* %x, <4 x float>* %y) { ; CHECK-LABEL: fadd_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vfadd.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vfadd.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -40,10 +40,10 @@ define void @fadd_v2f64(<2 x double>* %x, <2 x double>* %y) { ; CHECK-LABEL: fadd_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vfadd.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vfadd.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -56,10 +56,10 @@ define void @fsub_v8f16(<8 x half>* %x, <8 x half>* %y) { ; CHECK-LABEL: fsub_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vfsub.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vfsub.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -72,10 +72,10 @@ define void @fsub_v4f32(<4 x float>* %x, <4 x float>* %y) { ; CHECK-LABEL: fsub_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vfsub.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vfsub.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -88,10 +88,10 @@ define void @fsub_v2f64(<2 x double>* %x, <2 x double>* %y) { ; CHECK-LABEL: fsub_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vfsub.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vfsub.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -104,10 +104,10 @@ define void @fmul_v8f16(<8 x half>* %x, <8 x half>* %y) { ; CHECK-LABEL: fmul_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vfmul.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vfmul.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -120,10 +120,10 @@ define void @fmul_v4f32(<4 x float>* %x, <4 x float>* %y) { ; CHECK-LABEL: fmul_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vfmul.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vfmul.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -136,10 +136,10 @@ define void @fmul_v2f64(<2 x double>* %x, <2 x double>* %y) { ; CHECK-LABEL: fmul_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vfmul.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vfmul.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -152,10 +152,10 @@ define void @fdiv_v8f16(<8 x half>* %x, <8 x half>* %y) { ; CHECK-LABEL: fdiv_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vfdiv.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vfdiv.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -168,10 +168,10 @@ define void @fdiv_v4f32(<4 x float>* %x, <4 x float>* %y) { ; CHECK-LABEL: fdiv_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vfdiv.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vfdiv.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -184,10 +184,10 @@ define void @fdiv_v2f64(<2 x double>* %x, <2 x double>* %y) { ; CHECK-LABEL: fdiv_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vfdiv.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vfdiv.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -200,9 +200,9 @@ define void @fneg_v8f16(<8 x half>* %x) { ; CHECK-LABEL: fneg_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfneg.v v25, v25 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfneg.v v8, v8 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = fneg <8 x half> %a @@ -214,9 +214,9 @@ define void @fneg_v4f32(<4 x float>* %x) { ; CHECK-LABEL: fneg_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfneg.v v25, v25 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfneg.v v8, v8 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = fneg <4 x float> %a @@ -228,9 +228,9 @@ define void @fneg_v2f64(<2 x double>* %x) { ; CHECK-LABEL: fneg_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vfneg.v v25, v25 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfneg.v v8, v8 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = fneg <2 x double> %a @@ -242,9 +242,9 @@ define void @fabs_v8f16(<8 x half>* %x) { ; CHECK-LABEL: fabs_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfabs.v v25, v25 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfabs.v v8, v8 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = call <8 x half> @llvm.fabs.v8f16(<8 x half> %a) @@ -257,9 +257,9 @@ define void @fabs_v4f32(<4 x float>* %x) { ; CHECK-LABEL: fabs_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfabs.v v25, v25 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfabs.v v8, v8 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a) @@ -272,9 +272,9 @@ define void @fabs_v2f64(<2 x double>* %x) { ; CHECK-LABEL: fabs_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vfabs.v v25, v25 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfabs.v v8, v8 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = call <2 x double> @llvm.fabs.v2f64(<2 x double> %a) @@ -287,10 +287,10 @@ define void @copysign_v8f16(<8 x half>* %x, <8 x half>* %y) { ; CHECK-LABEL: copysign_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vfsgnj.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vfsgnj.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -304,10 +304,10 @@ define void @copysign_v4f32(<4 x float>* %x, <4 x float>* %y) { ; CHECK-LABEL: copysign_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vfsgnj.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vfsgnj.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -321,10 +321,10 @@ define void @copysign_v2f64(<2 x double>* %x, <2 x double>* %y) { ; CHECK-LABEL: copysign_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vfsgnj.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vfsgnj.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -338,9 +338,9 @@ define void @copysign_vf_v8f16(<8 x half>* %x, half %y) { ; CHECK-LABEL: copysign_vf_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfsgnj.vf v25, v25, fa0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfsgnj.vf v8, v8, fa0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -354,9 +354,9 @@ define void @copysign_vf_v4f32(<4 x float>* %x, float %y) { ; CHECK-LABEL: copysign_vf_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfsgnj.vf v25, v25, fa0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfsgnj.vf v8, v8, fa0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -370,9 +370,9 @@ define void @copysign_vf_v2f64(<2 x double>* %x, double %y) { ; CHECK-LABEL: copysign_vf_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vfsgnj.vf v25, v25, fa0 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfsgnj.vf v8, v8, fa0 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -386,10 +386,10 @@ define void @copysign_neg_v8f16(<8 x half>* %x, <8 x half>* %y) { ; CHECK-LABEL: copysign_neg_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vfsgnjn.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vfsgnjn.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -403,10 +403,10 @@ define void @copysign_neg_v4f32(<4 x float>* %x, <4 x float>* %y) { ; CHECK-LABEL: copysign_neg_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vfsgnjn.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vfsgnjn.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -420,10 +420,10 @@ define void @copysign_neg_v2f64(<2 x double>* %x, <2 x double>* %y) { ; CHECK-LABEL: copysign_neg_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vfsgnjn.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vfsgnjn.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -437,11 +437,11 @@ define void @copysign_neg_trunc_v4f16_v4f32(<4 x half>* %x, <4 x float>* %y) { ; CHECK-LABEL: copysign_neg_trunc_v4f16_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a1) -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vfncvt.f.f.w v27, v25 -; CHECK-NEXT: vfsgnjn.vv v25, v26, v27 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vfncvt.f.f.w v10, v8 +; CHECK-NEXT: vfsgnjn.vv v8, v9, v10 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x half>, <4 x half>* %x %b = load <4 x float>, <4 x float>* %y @@ -457,13 +457,13 @@ define void @copysign_neg_ext_v2f64_v2f32(<2 x double>* %x, <2 x float>* %y) { ; CHECK-LABEL: copysign_neg_ext_v2f64_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a1) -; CHECK-NEXT: vle64.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vle64.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v27, v25 +; CHECK-NEXT: vfwcvt.f.f.v v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-NEXT: vfsgnjn.vv v25, v26, v27 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vfsgnjn.vv v8, v9, v10 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x float>, <2 x float>* %y @@ -478,9 +478,9 @@ define void @sqrt_v8f16(<8 x half>* %x) { ; CHECK-LABEL: sqrt_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfsqrt.v v25, v25 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfsqrt.v v8, v8 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = call <8 x half> @llvm.sqrt.v8f16(<8 x half> %a) @@ -493,9 +493,9 @@ define void @sqrt_v4f32(<4 x float>* %x) { ; CHECK-LABEL: sqrt_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfsqrt.v v25, v25 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfsqrt.v v8, v8 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a) @@ -508,9 +508,9 @@ define void @sqrt_v2f64(<2 x double>* %x) { ; CHECK-LABEL: sqrt_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vfsqrt.v v25, v25 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfsqrt.v v8, v8 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a) @@ -523,11 +523,11 @@ define void @fma_v8f16(<8 x half>* %x, <8 x half>* %y, <8 x half>* %z) { ; CHECK-LABEL: fma_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vle16.v v27, (a2) -; CHECK-NEXT: vfmacc.vv v27, v25, v26 -; CHECK-NEXT: vse16.v v27, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vle16.v v10, (a2) +; CHECK-NEXT: vfmacc.vv v10, v8, v9 +; CHECK-NEXT: vse16.v v10, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -542,11 +542,11 @@ define void @fma_v4f32(<4 x float>* %x, <4 x float>* %y, <4 x float>* %z) { ; CHECK-LABEL: fma_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vle32.v v27, (a2) -; CHECK-NEXT: vfmacc.vv v27, v25, v26 -; CHECK-NEXT: vse32.v v27, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vle32.v v10, (a2) +; CHECK-NEXT: vfmacc.vv v10, v8, v9 +; CHECK-NEXT: vse32.v v10, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -561,11 +561,11 @@ define void @fma_v2f64(<2 x double>* %x, <2 x double>* %y, <2 x double>* %z) { ; CHECK-LABEL: fma_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vle64.v v27, (a2) -; CHECK-NEXT: vfmacc.vv v27, v25, v26 -; CHECK-NEXT: vse64.v v27, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vle64.v v10, (a2) +; CHECK-NEXT: vfmacc.vv v10, v8, v9 +; CHECK-NEXT: vse64.v v10, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -580,11 +580,11 @@ define void @fmsub_v8f16(<8 x half>* %x, <8 x half>* %y, <8 x half>* %z) { ; CHECK-LABEL: fmsub_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vle16.v v27, (a2) -; CHECK-NEXT: vfmsac.vv v27, v25, v26 -; CHECK-NEXT: vse16.v v27, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vle16.v v10, (a2) +; CHECK-NEXT: vfmsac.vv v10, v8, v9 +; CHECK-NEXT: vse16.v v10, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -599,11 +599,11 @@ define void @fnmsub_v4f32(<4 x float>* %x, <4 x float>* %y, <4 x float>* %z) { ; CHECK-LABEL: fnmsub_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vle32.v v27, (a2) -; CHECK-NEXT: vfnmsac.vv v27, v25, v26 -; CHECK-NEXT: vse32.v v27, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vle32.v v10, (a2) +; CHECK-NEXT: vfnmsac.vv v10, v8, v9 +; CHECK-NEXT: vse32.v v10, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -618,11 +618,11 @@ define void @fnmadd_v2f64(<2 x double>* %x, <2 x double>* %y, <2 x double>* %z) ; CHECK-LABEL: fnmadd_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vle64.v v27, (a2) -; CHECK-NEXT: vfnmacc.vv v27, v25, v26 -; CHECK-NEXT: vse64.v v27, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vle64.v v10, (a2) +; CHECK-NEXT: vfnmacc.vv v10, v8, v9 +; CHECK-NEXT: vse64.v v10, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -638,40 +638,40 @@ define void @fadd_v16f16(<16 x half>* %x, <16 x half>* %y) { ; LMULMAX2-LABEL: fadd_v16f16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vfadd.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vfadd.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fadd_v16f16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vfadd.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vfadd.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vfadd.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vfadd.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fadd_v16f16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vfadd.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vfadd.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vfadd.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vfadd.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = load <16 x half>, <16 x half>* %y @@ -684,40 +684,40 @@ define void @fadd_v8f32(<8 x float>* %x, <8 x float>* %y) { ; LMULMAX2-LABEL: fadd_v8f32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vfadd.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vfadd.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fadd_v8f32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vfadd.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vfadd.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vfadd.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vfadd.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fadd_v8f32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vfadd.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vfadd.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vfadd.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vfadd.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = load <8 x float>, <8 x float>* %y @@ -730,40 +730,40 @@ define void @fadd_v4f64(<4 x double>* %x, <4 x double>* %y) { ; LMULMAX2-LABEL: fadd_v4f64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vfadd.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vfadd.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fadd_v4f64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vfadd.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vfadd.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vfadd.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vfadd.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fadd_v4f64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vfadd.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vfadd.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vfadd.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vfadd.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = load <4 x double>, <4 x double>* %y @@ -776,40 +776,40 @@ define void @fsub_v16f16(<16 x half>* %x, <16 x half>* %y) { ; LMULMAX2-LABEL: fsub_v16f16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vfsub.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vfsub.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fsub_v16f16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vfsub.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vfsub.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vfsub.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vfsub.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fsub_v16f16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vfsub.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vfsub.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vfsub.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vfsub.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = load <16 x half>, <16 x half>* %y @@ -822,40 +822,40 @@ define void @fsub_v8f32(<8 x float>* %x, <8 x float>* %y) { ; LMULMAX2-LABEL: fsub_v8f32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vfsub.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vfsub.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fsub_v8f32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vfsub.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vfsub.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vfsub.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vfsub.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fsub_v8f32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vfsub.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vfsub.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vfsub.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vfsub.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = load <8 x float>, <8 x float>* %y @@ -868,40 +868,40 @@ define void @fsub_v4f64(<4 x double>* %x, <4 x double>* %y) { ; LMULMAX2-LABEL: fsub_v4f64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vfsub.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vfsub.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fsub_v4f64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vfsub.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vfsub.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vfsub.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vfsub.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fsub_v4f64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vfsub.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vfsub.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vfsub.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vfsub.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = load <4 x double>, <4 x double>* %y @@ -914,40 +914,40 @@ define void @fmul_v16f16(<16 x half>* %x, <16 x half>* %y) { ; LMULMAX2-LABEL: fmul_v16f16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vfmul.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vfmul.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fmul_v16f16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vfmul.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vfmul.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vfmul.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vfmul.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fmul_v16f16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vfmul.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vfmul.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vfmul.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vfmul.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = load <16 x half>, <16 x half>* %y @@ -960,40 +960,40 @@ define void @fmul_v8f32(<8 x float>* %x, <8 x float>* %y) { ; LMULMAX2-LABEL: fmul_v8f32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vfmul.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vfmul.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fmul_v8f32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vfmul.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vfmul.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vfmul.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vfmul.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fmul_v8f32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vfmul.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vfmul.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vfmul.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vfmul.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = load <8 x float>, <8 x float>* %y @@ -1006,40 +1006,40 @@ define void @fmul_v4f64(<4 x double>* %x, <4 x double>* %y) { ; LMULMAX2-LABEL: fmul_v4f64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vfmul.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vfmul.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fmul_v4f64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vfmul.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vfmul.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vfmul.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vfmul.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fmul_v4f64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vfmul.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vfmul.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vfmul.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vfmul.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = load <4 x double>, <4 x double>* %y @@ -1052,40 +1052,40 @@ define void @fdiv_v16f16(<16 x half>* %x, <16 x half>* %y) { ; LMULMAX2-LABEL: fdiv_v16f16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vfdiv.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vfdiv.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fdiv_v16f16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vfdiv.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vfdiv.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vfdiv.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vfdiv.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fdiv_v16f16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vfdiv.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vfdiv.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vfdiv.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vfdiv.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = load <16 x half>, <16 x half>* %y @@ -1098,40 +1098,40 @@ define void @fdiv_v8f32(<8 x float>* %x, <8 x float>* %y) { ; LMULMAX2-LABEL: fdiv_v8f32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vfdiv.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vfdiv.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fdiv_v8f32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vfdiv.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vfdiv.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vfdiv.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vfdiv.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fdiv_v8f32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vfdiv.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vfdiv.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vfdiv.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vfdiv.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = load <8 x float>, <8 x float>* %y @@ -1144,40 +1144,40 @@ define void @fdiv_v4f64(<4 x double>* %x, <4 x double>* %y) { ; LMULMAX2-LABEL: fdiv_v4f64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vfdiv.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vfdiv.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: fdiv_v4f64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vfdiv.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vfdiv.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vfdiv.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vfdiv.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: fdiv_v4f64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vfdiv.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vfdiv.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vfdiv.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vfdiv.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = load <4 x double>, <4 x double>* %y @@ -1190,21 +1190,21 @@ define void @fneg_v16f16(<16 x half>* %x) { ; LMULMAX2-LABEL: fneg_v16f16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vfneg.v v26, v26 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vfneg.v v8, v8 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: fneg_v16f16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vle16.v v25, (a1) -; LMULMAX1-NEXT: vle16.v v26, (a0) -; LMULMAX1-NEXT: vfneg.v v25, v25 -; LMULMAX1-NEXT: vfneg.v v26, v26 -; LMULMAX1-NEXT: vse16.v v26, (a0) -; LMULMAX1-NEXT: vse16.v v25, (a1) +; LMULMAX1-NEXT: vle16.v v8, (a1) +; LMULMAX1-NEXT: vle16.v v9, (a0) +; LMULMAX1-NEXT: vfneg.v v8, v8 +; LMULMAX1-NEXT: vfneg.v v9, v9 +; LMULMAX1-NEXT: vse16.v v9, (a0) +; LMULMAX1-NEXT: vse16.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = fneg <16 x half> %a @@ -1216,21 +1216,21 @@ define void @fneg_v8f32(<8 x float>* %x) { ; LMULMAX2-LABEL: fneg_v8f32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vfneg.v v26, v26 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vfneg.v v8, v8 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: fneg_v8f32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vle32.v v25, (a1) -; LMULMAX1-NEXT: vle32.v v26, (a0) -; LMULMAX1-NEXT: vfneg.v v25, v25 -; LMULMAX1-NEXT: vfneg.v v26, v26 -; LMULMAX1-NEXT: vse32.v v26, (a0) -; LMULMAX1-NEXT: vse32.v v25, (a1) +; LMULMAX1-NEXT: vle32.v v8, (a1) +; LMULMAX1-NEXT: vle32.v v9, (a0) +; LMULMAX1-NEXT: vfneg.v v8, v8 +; LMULMAX1-NEXT: vfneg.v v9, v9 +; LMULMAX1-NEXT: vse32.v v9, (a0) +; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = fneg <8 x float> %a @@ -1242,21 +1242,21 @@ define void @fneg_v4f64(<4 x double>* %x) { ; LMULMAX2-LABEL: fneg_v4f64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vfneg.v v26, v26 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vfneg.v v8, v8 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: fneg_v4f64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vle64.v v25, (a1) -; LMULMAX1-NEXT: vle64.v v26, (a0) -; LMULMAX1-NEXT: vfneg.v v25, v25 -; LMULMAX1-NEXT: vfneg.v v26, v26 -; LMULMAX1-NEXT: vse64.v v26, (a0) -; LMULMAX1-NEXT: vse64.v v25, (a1) +; LMULMAX1-NEXT: vle64.v v8, (a1) +; LMULMAX1-NEXT: vle64.v v9, (a0) +; LMULMAX1-NEXT: vfneg.v v8, v8 +; LMULMAX1-NEXT: vfneg.v v9, v9 +; LMULMAX1-NEXT: vse64.v v9, (a0) +; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = fneg <4 x double> %a @@ -1268,29 +1268,29 @@ define void @fma_v16f16(<16 x half>* %x, <16 x half>* %y, <16 x half>* %z) { ; LMULMAX2-LABEL: fma_v16f16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vle16.v v30, (a2) -; LMULMAX2-NEXT: vfmacc.vv v30, v26, v28 -; LMULMAX2-NEXT: vse16.v v30, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vle16.v v12, (a2) +; LMULMAX2-NEXT: vfmacc.vv v12, v8, v10 +; LMULMAX2-NEXT: vse16.v v12, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: fma_v16f16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v8, (a0) ; LMULMAX1-NEXT: addi a3, a0, 16 -; LMULMAX1-NEXT: vle16.v v26, (a3) -; LMULMAX1-NEXT: vle16.v v27, (a1) +; LMULMAX1-NEXT: vle16.v v9, (a3) +; LMULMAX1-NEXT: vle16.v v10, (a1) ; LMULMAX1-NEXT: addi a1, a1, 16 -; LMULMAX1-NEXT: vle16.v v28, (a1) +; LMULMAX1-NEXT: vle16.v v11, (a1) ; LMULMAX1-NEXT: addi a1, a2, 16 -; LMULMAX1-NEXT: vle16.v v29, (a1) -; LMULMAX1-NEXT: vle16.v v30, (a2) -; LMULMAX1-NEXT: vfmacc.vv v29, v26, v28 -; LMULMAX1-NEXT: vfmacc.vv v30, v25, v27 -; LMULMAX1-NEXT: vse16.v v30, (a0) -; LMULMAX1-NEXT: vse16.v v29, (a3) +; LMULMAX1-NEXT: vle16.v v12, (a1) +; LMULMAX1-NEXT: vle16.v v13, (a2) +; LMULMAX1-NEXT: vfmacc.vv v12, v9, v11 +; LMULMAX1-NEXT: vfmacc.vv v13, v8, v10 +; LMULMAX1-NEXT: vse16.v v13, (a0) +; LMULMAX1-NEXT: vse16.v v12, (a3) ; LMULMAX1-NEXT: ret %a = load <16 x half>, <16 x half>* %x %b = load <16 x half>, <16 x half>* %y @@ -1305,29 +1305,29 @@ define void @fma_v8f32(<8 x float>* %x, <8 x float>* %y, <8 x float>* %z) { ; LMULMAX2-LABEL: fma_v8f32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vle32.v v30, (a2) -; LMULMAX2-NEXT: vfmacc.vv v30, v26, v28 -; LMULMAX2-NEXT: vse32.v v30, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vle32.v v12, (a2) +; LMULMAX2-NEXT: vfmacc.vv v12, v8, v10 +; LMULMAX2-NEXT: vse32.v v12, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: fma_v8f32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a0) +; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: addi a3, a0, 16 -; LMULMAX1-NEXT: vle32.v v26, (a3) -; LMULMAX1-NEXT: vle32.v v27, (a1) +; LMULMAX1-NEXT: vle32.v v9, (a3) +; LMULMAX1-NEXT: vle32.v v10, (a1) ; LMULMAX1-NEXT: addi a1, a1, 16 -; LMULMAX1-NEXT: vle32.v v28, (a1) +; LMULMAX1-NEXT: vle32.v v11, (a1) ; LMULMAX1-NEXT: addi a1, a2, 16 -; LMULMAX1-NEXT: vle32.v v29, (a1) -; LMULMAX1-NEXT: vle32.v v30, (a2) -; LMULMAX1-NEXT: vfmacc.vv v29, v26, v28 -; LMULMAX1-NEXT: vfmacc.vv v30, v25, v27 -; LMULMAX1-NEXT: vse32.v v30, (a0) -; LMULMAX1-NEXT: vse32.v v29, (a3) +; LMULMAX1-NEXT: vle32.v v12, (a1) +; LMULMAX1-NEXT: vle32.v v13, (a2) +; LMULMAX1-NEXT: vfmacc.vv v12, v9, v11 +; LMULMAX1-NEXT: vfmacc.vv v13, v8, v10 +; LMULMAX1-NEXT: vse32.v v13, (a0) +; LMULMAX1-NEXT: vse32.v v12, (a3) ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = load <8 x float>, <8 x float>* %y @@ -1342,29 +1342,29 @@ define void @fma_v4f64(<4 x double>* %x, <4 x double>* %y, <4 x double>* %z) { ; LMULMAX2-LABEL: fma_v4f64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vle64.v v30, (a2) -; LMULMAX2-NEXT: vfmacc.vv v30, v26, v28 -; LMULMAX2-NEXT: vse64.v v30, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vle64.v v12, (a2) +; LMULMAX2-NEXT: vfmacc.vv v12, v8, v10 +; LMULMAX2-NEXT: vse64.v v12, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: fma_v4f64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vle64.v v25, (a0) +; LMULMAX1-NEXT: vle64.v v8, (a0) ; LMULMAX1-NEXT: addi a3, a0, 16 -; LMULMAX1-NEXT: vle64.v v26, (a3) -; LMULMAX1-NEXT: vle64.v v27, (a1) +; LMULMAX1-NEXT: vle64.v v9, (a3) +; LMULMAX1-NEXT: vle64.v v10, (a1) ; LMULMAX1-NEXT: addi a1, a1, 16 -; LMULMAX1-NEXT: vle64.v v28, (a1) +; LMULMAX1-NEXT: vle64.v v11, (a1) ; LMULMAX1-NEXT: addi a1, a2, 16 -; LMULMAX1-NEXT: vle64.v v29, (a1) -; LMULMAX1-NEXT: vle64.v v30, (a2) -; LMULMAX1-NEXT: vfmacc.vv v29, v26, v28 -; LMULMAX1-NEXT: vfmacc.vv v30, v25, v27 -; LMULMAX1-NEXT: vse64.v v30, (a0) -; LMULMAX1-NEXT: vse64.v v29, (a3) +; LMULMAX1-NEXT: vle64.v v12, (a1) +; LMULMAX1-NEXT: vle64.v v13, (a2) +; LMULMAX1-NEXT: vfmacc.vv v12, v9, v11 +; LMULMAX1-NEXT: vfmacc.vv v13, v8, v10 +; LMULMAX1-NEXT: vse64.v v13, (a0) +; LMULMAX1-NEXT: vse64.v v12, (a3) ; LMULMAX1-NEXT: ret %a = load <4 x double>, <4 x double>* %x %b = load <4 x double>, <4 x double>* %y @@ -1379,9 +1379,9 @@ define void @fadd_vf_v8f16(<8 x half>* %x, half %y) { ; CHECK-LABEL: fadd_vf_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfadd.vf v25, v25, fa0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfadd.vf v8, v8, fa0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1395,9 +1395,9 @@ define void @fadd_vf_v4f32(<4 x float>* %x, float %y) { ; CHECK-LABEL: fadd_vf_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfadd.vf v25, v25, fa0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfadd.vf v8, v8, fa0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1411,9 +1411,9 @@ define void @fadd_vf_v2f64(<2 x double>* %x, double %y) { ; CHECK-LABEL: fadd_vf_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vfadd.vf v25, v25, fa0 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfadd.vf v8, v8, fa0 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1427,9 +1427,9 @@ define void @fadd_fv_v8f16(<8 x half>* %x, half %y) { ; CHECK-LABEL: fadd_fv_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfadd.vf v25, v25, fa0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfadd.vf v8, v8, fa0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1443,9 +1443,9 @@ define void @fadd_fv_v4f32(<4 x float>* %x, float %y) { ; CHECK-LABEL: fadd_fv_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfadd.vf v25, v25, fa0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfadd.vf v8, v8, fa0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1459,9 +1459,9 @@ define void @fadd_fv_v2f64(<2 x double>* %x, double %y) { ; CHECK-LABEL: fadd_fv_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vfadd.vf v25, v25, fa0 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfadd.vf v8, v8, fa0 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1475,9 +1475,9 @@ define void @fsub_vf_v8f16(<8 x half>* %x, half %y) { ; CHECK-LABEL: fsub_vf_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfsub.vf v25, v25, fa0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfsub.vf v8, v8, fa0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1491,9 +1491,9 @@ define void @fsub_vf_v4f32(<4 x float>* %x, float %y) { ; CHECK-LABEL: fsub_vf_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfsub.vf v25, v25, fa0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfsub.vf v8, v8, fa0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1507,9 +1507,9 @@ define void @fsub_vf_v2f64(<2 x double>* %x, double %y) { ; CHECK-LABEL: fsub_vf_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vfsub.vf v25, v25, fa0 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfsub.vf v8, v8, fa0 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1523,9 +1523,9 @@ define void @fsub_fv_v8f16(<8 x half>* %x, half %y) { ; CHECK-LABEL: fsub_fv_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfrsub.vf v25, v25, fa0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfrsub.vf v8, v8, fa0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1539,9 +1539,9 @@ define void @fsub_fv_v4f32(<4 x float>* %x, float %y) { ; CHECK-LABEL: fsub_fv_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfrsub.vf v25, v25, fa0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfrsub.vf v8, v8, fa0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1555,9 +1555,9 @@ define void @fsub_fv_v2f64(<2 x double>* %x, double %y) { ; CHECK-LABEL: fsub_fv_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vfrsub.vf v25, v25, fa0 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfrsub.vf v8, v8, fa0 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1571,9 +1571,9 @@ define void @fmul_vf_v8f16(<8 x half>* %x, half %y) { ; CHECK-LABEL: fmul_vf_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfmul.vf v25, v25, fa0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfmul.vf v8, v8, fa0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1587,9 +1587,9 @@ define void @fmul_vf_v4f32(<4 x float>* %x, float %y) { ; CHECK-LABEL: fmul_vf_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfmul.vf v25, v25, fa0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfmul.vf v8, v8, fa0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1603,9 +1603,9 @@ define void @fmul_vf_v2f64(<2 x double>* %x, double %y) { ; CHECK-LABEL: fmul_vf_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vfmul.vf v25, v25, fa0 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfmul.vf v8, v8, fa0 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1619,9 +1619,9 @@ define void @fmul_fv_v8f16(<8 x half>* %x, half %y) { ; CHECK-LABEL: fmul_fv_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfmul.vf v25, v25, fa0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfmul.vf v8, v8, fa0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1635,9 +1635,9 @@ define void @fmul_fv_v4f32(<4 x float>* %x, float %y) { ; CHECK-LABEL: fmul_fv_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfmul.vf v25, v25, fa0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfmul.vf v8, v8, fa0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1651,9 +1651,9 @@ define void @fmul_fv_v2f64(<2 x double>* %x, double %y) { ; CHECK-LABEL: fmul_fv_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vfmul.vf v25, v25, fa0 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfmul.vf v8, v8, fa0 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1667,9 +1667,9 @@ define void @fdiv_vf_v8f16(<8 x half>* %x, half %y) { ; CHECK-LABEL: fdiv_vf_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfdiv.vf v25, v25, fa0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1683,9 +1683,9 @@ define void @fdiv_vf_v4f32(<4 x float>* %x, float %y) { ; CHECK-LABEL: fdiv_vf_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfdiv.vf v25, v25, fa0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1699,9 +1699,9 @@ define void @fdiv_vf_v2f64(<2 x double>* %x, double %y) { ; CHECK-LABEL: fdiv_vf_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vfdiv.vf v25, v25, fa0 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1715,9 +1715,9 @@ define void @fdiv_fv_v8f16(<8 x half>* %x, half %y) { ; CHECK-LABEL: fdiv_fv_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfrdiv.vf v25, v25, fa0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = insertelement <8 x half> undef, half %y, i32 0 @@ -1731,9 +1731,9 @@ define void @fdiv_fv_v4f32(<4 x float>* %x, float %y) { ; CHECK-LABEL: fdiv_fv_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfrdiv.vf v25, v25, fa0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = insertelement <4 x float> undef, float %y, i32 0 @@ -1747,9 +1747,9 @@ define void @fdiv_fv_v2f64(<2 x double>* %x, double %y) { ; CHECK-LABEL: fdiv_fv_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vfrdiv.vf v25, v25, fa0 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = insertelement <2 x double> undef, double %y, i32 0 @@ -1763,10 +1763,10 @@ define void @fma_vf_v8f16(<8 x half>* %x, <8 x half>* %y, half %z) { ; CHECK-LABEL: fma_vf_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vfmacc.vf v26, fa0, v25 -; CHECK-NEXT: vse16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vfmacc.vf v9, fa0, v8 +; CHECK-NEXT: vse16.v v9, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -1781,10 +1781,10 @@ define void @fma_vf_v4f32(<4 x float>* %x, <4 x float>* %y, float %z) { ; CHECK-LABEL: fma_vf_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vfmacc.vf v26, fa0, v25 -; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vfmacc.vf v9, fa0, v8 +; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -1799,10 +1799,10 @@ define void @fma_vf_v2f64(<2 x double>* %x, <2 x double>* %y, double %z) { ; CHECK-LABEL: fma_vf_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vfmacc.vf v26, fa0, v25 -; CHECK-NEXT: vse64.v v26, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vfmacc.vf v9, fa0, v8 +; CHECK-NEXT: vse64.v v9, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -1817,10 +1817,10 @@ define void @fma_fv_v8f16(<8 x half>* %x, <8 x half>* %y, half %z) { ; CHECK-LABEL: fma_fv_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vfmacc.vf v26, fa0, v25 -; CHECK-NEXT: vse16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vfmacc.vf v9, fa0, v8 +; CHECK-NEXT: vse16.v v9, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -1835,10 +1835,10 @@ define void @fma_fv_v4f32(<4 x float>* %x, <4 x float>* %y, float %z) { ; CHECK-LABEL: fma_fv_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vfmacc.vf v26, fa0, v25 -; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vfmacc.vf v9, fa0, v8 +; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -1853,10 +1853,10 @@ define void @fma_fv_v2f64(<2 x double>* %x, <2 x double>* %y, double %z) { ; CHECK-LABEL: fma_fv_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vfmacc.vf v26, fa0, v25 -; CHECK-NEXT: vse64.v v26, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vfmacc.vf v9, fa0, v8 +; CHECK-NEXT: vse64.v v9, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -1871,10 +1871,10 @@ define void @fmsub_vf_v8f16(<8 x half>* %x, <8 x half>* %y, half %z) { ; CHECK-LABEL: fmsub_vf_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vfmsac.vf v26, fa0, v25 -; CHECK-NEXT: vse16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vfmsac.vf v9, fa0, v8 +; CHECK-NEXT: vse16.v v9, (a0) ; CHECK-NEXT: ret %a = load <8 x half>, <8 x half>* %x %b = load <8 x half>, <8 x half>* %y @@ -1890,10 +1890,10 @@ define void @fnmsub_vf_v4f32(<4 x float>* %x, <4 x float>* %y, float %z) { ; CHECK-LABEL: fnmsub_vf_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vfnmsac.vf v26, fa0, v25 -; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vfnmsac.vf v9, fa0, v8 +; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -1909,10 +1909,10 @@ define void @fnmadd_vf_v2f64(<2 x double>* %x, <2 x double>* %y, double %z) { ; CHECK-LABEL: fnmadd_vf_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vfnmacc.vf v26, fa0, v25 -; CHECK-NEXT: vse64.v v26, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vfnmacc.vf v9, fa0, v8 +; CHECK-NEXT: vse64.v v9, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y @@ -1929,10 +1929,10 @@ define void @fnmsub_fv_v4f32(<4 x float>* %x, <4 x float>* %y, float %z) { ; CHECK-LABEL: fnmsub_fv_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vfnmsac.vf v26, fa0, v25 -; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vfnmsac.vf v9, fa0, v8 +; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: ret %a = load <4 x float>, <4 x float>* %x %b = load <4 x float>, <4 x float>* %y @@ -1948,10 +1948,10 @@ define void @fnmadd_fv_v2f64(<2 x double>* %x, <2 x double>* %y, double %z) { ; CHECK-LABEL: fnmadd_fv_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vfnmacc.vf v26, fa0, v25 -; CHECK-NEXT: vse64.v v26, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vfnmacc.vf v9, fa0, v8 +; CHECK-NEXT: vse64.v v9, (a0) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %b = load <2 x double>, <2 x double>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll index 905f6050d80df447536fee9977dd24cf6841c275..fa3ddbb7fb7ef0a7e49a74ada39a592c448cb9bb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll @@ -8,9 +8,9 @@ define void @fp2si_v2f32_v2i32(<2 x float>* %x, <2 x i32>* %y) { ; CHECK-LABEL: fp2si_v2f32_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfcvt.rtz.x.f.v v25, v25 -; CHECK-NEXT: vse32.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: vse32.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x float>, <2 x float>* %x %d = fptosi <2 x float> %a to <2 x i32> @@ -22,9 +22,9 @@ define void @fp2ui_v2f32_v2i32(<2 x float>* %x, <2 x i32>* %y) { ; CHECK-LABEL: fp2ui_v2f32_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfcvt.rtz.xu.f.v v25, v25 -; CHECK-NEXT: vse32.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: vse32.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x float>, <2 x float>* %x %d = fptoui <2 x float> %a to <2 x i32> @@ -36,9 +36,9 @@ define <2 x i1> @fp2si_v2f32_v2i1(<2 x float> %x) { ; CHECK-LABEL: fp2si_v2f32_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %z = fptosi <2 x float> %x to <2 x i1> ret <2 x i1> %z @@ -48,9 +48,9 @@ define <2 x i1> @fp2ui_v2f32_v2i1(<2 x float> %x) { ; CHECK-LABEL: fp2ui_v2f32_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %z = fptoui <2 x float> %x to <2 x i1> ret <2 x i1> %z @@ -60,22 +60,22 @@ define void @fp2si_v8f32_v8i32(<8 x float>* %x, <8 x i32>* %y) { ; LMULMAX8-LABEL: fp2si_v8f32_v8i32: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX8-NEXT: vle32.v v26, (a0) -; LMULMAX8-NEXT: vfcvt.rtz.x.f.v v26, v26 -; LMULMAX8-NEXT: vse32.v v26, (a1) +; LMULMAX8-NEXT: vle32.v v8, (a0) +; LMULMAX8-NEXT: vfcvt.rtz.x.f.v v8, v8 +; LMULMAX8-NEXT: vse32.v v8, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2si_v8f32_v8i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: addi a2, a0, 16 -; LMULMAX1-NEXT: vle32.v v25, (a2) -; LMULMAX1-NEXT: vle32.v v26, (a0) -; LMULMAX1-NEXT: vfcvt.rtz.x.f.v v25, v25 -; LMULMAX1-NEXT: vfcvt.rtz.x.f.v v26, v26 -; LMULMAX1-NEXT: vse32.v v26, (a1) +; LMULMAX1-NEXT: vle32.v v8, (a2) +; LMULMAX1-NEXT: vle32.v v9, (a0) +; LMULMAX1-NEXT: vfcvt.rtz.x.f.v v8, v8 +; LMULMAX1-NEXT: vfcvt.rtz.x.f.v v9, v9 +; LMULMAX1-NEXT: vse32.v v9, (a1) ; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %d = fptosi <8 x float> %a to <8 x i32> @@ -87,22 +87,22 @@ define void @fp2ui_v8f32_v8i32(<8 x float>* %x, <8 x i32>* %y) { ; LMULMAX8-LABEL: fp2ui_v8f32_v8i32: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX8-NEXT: vle32.v v26, (a0) -; LMULMAX8-NEXT: vfcvt.rtz.xu.f.v v26, v26 -; LMULMAX8-NEXT: vse32.v v26, (a1) +; LMULMAX8-NEXT: vle32.v v8, (a0) +; LMULMAX8-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; LMULMAX8-NEXT: vse32.v v8, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2ui_v8f32_v8i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: addi a2, a0, 16 -; LMULMAX1-NEXT: vle32.v v25, (a2) -; LMULMAX1-NEXT: vle32.v v26, (a0) -; LMULMAX1-NEXT: vfcvt.rtz.xu.f.v v25, v25 -; LMULMAX1-NEXT: vfcvt.rtz.xu.f.v v26, v26 -; LMULMAX1-NEXT: vse32.v v26, (a1) +; LMULMAX1-NEXT: vle32.v v8, (a2) +; LMULMAX1-NEXT: vle32.v v9, (a0) +; LMULMAX1-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; LMULMAX1-NEXT: vfcvt.rtz.xu.f.v v9, v9 +; LMULMAX1-NEXT: vse32.v v9, (a1) ; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %d = fptoui <8 x float> %a to <8 x i32> @@ -114,39 +114,39 @@ define <8 x i1> @fp2si_v8f32_v8i1(<8 x float> %x) { ; LMULMAX8-LABEL: fp2si_v8f32_v8i1: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v25, v8 -; LMULMAX8-NEXT: vand.vi v25, v25, 1 -; LMULMAX8-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v10, v8 +; LMULMAX8-NEXT: vand.vi v8, v10, 1 +; LMULMAX8-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2si_v8f32_v8i1: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vmclr.m v0 -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v10, 0 +; LMULMAX1-NEXT: vmerge.vim v11, v10, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v27, v8 -; LMULMAX1-NEXT: vand.vi v27, v27, 1 -; LMULMAX1-NEXT: vmsne.vi v0, v27, 0 +; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v12, v8 +; LMULMAX1-NEXT: vand.vi v8, v12, 1 +; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; LMULMAX1-NEXT: vmv.v.i v27, 0 -; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v8, 0 +; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v28, 0 +; LMULMAX1-NEXT: vslideup.vi v11, v12, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v26, 0 -; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX1-NEXT: vmsne.vi v0, v11, 0 +; LMULMAX1-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v26, v9 -; LMULMAX1-NEXT: vand.vi v26, v26, 1 -; LMULMAX1-NEXT: vmsne.vi v0, v26, 0 +; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v11, v9 +; LMULMAX1-NEXT: vand.vi v9, v11, 1 +; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; LMULMAX1-NEXT: vmerge.vim v26, v27, 1, v0 +; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v26, 4 +; LMULMAX1-NEXT: vslideup.vi v10, v8, 4 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: ret %z = fptosi <8 x float> %x to <8 x i1> ret <8 x i1> %z @@ -156,39 +156,39 @@ define <8 x i1> @fp2ui_v8f32_v8i1(<8 x float> %x) { ; LMULMAX8-LABEL: fp2ui_v8f32_v8i1: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; LMULMAX8-NEXT: vand.vi v25, v25, 1 -; LMULMAX8-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v10, v8 +; LMULMAX8-NEXT: vand.vi v8, v10, 1 +; LMULMAX8-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2ui_v8f32_v8i1: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vmclr.m v0 -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v10, 0 +; LMULMAX1-NEXT: vmerge.vim v11, v10, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v27, v8 -; LMULMAX1-NEXT: vand.vi v27, v27, 1 -; LMULMAX1-NEXT: vmsne.vi v0, v27, 0 +; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v12, v8 +; LMULMAX1-NEXT: vand.vi v8, v12, 1 +; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; LMULMAX1-NEXT: vmv.v.i v27, 0 -; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v8, 0 +; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v28, 0 +; LMULMAX1-NEXT: vslideup.vi v11, v12, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v26, 0 -; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX1-NEXT: vmsne.vi v0, v11, 0 +; LMULMAX1-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v26, v9 -; LMULMAX1-NEXT: vand.vi v26, v26, 1 -; LMULMAX1-NEXT: vmsne.vi v0, v26, 0 +; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v11, v9 +; LMULMAX1-NEXT: vand.vi v9, v11, 1 +; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; LMULMAX1-NEXT: vmerge.vim v26, v27, 1, v0 +; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v26, 4 +; LMULMAX1-NEXT: vslideup.vi v10, v8, 4 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: ret %z = fptoui <8 x float> %x to <8 x i1> ret <8 x i1> %z @@ -198,9 +198,9 @@ define void @fp2si_v2f32_v2i64(<2 x float>* %x, <2 x i64>* %y) { ; CHECK-LABEL: fp2si_v2f32_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfwcvt.rtz.x.f.v v26, v25 -; CHECK-NEXT: vse64.v v26, (a1) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8 +; CHECK-NEXT: vse64.v v9, (a1) ; CHECK-NEXT: ret %a = load <2 x float>, <2 x float>* %x %d = fptosi <2 x float> %a to <2 x i64> @@ -212,9 +212,9 @@ define void @fp2ui_v2f32_v2i64(<2 x float>* %x, <2 x i64>* %y) { ; CHECK-LABEL: fp2ui_v2f32_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v26, v25 -; CHECK-NEXT: vse64.v v26, (a1) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8 +; CHECK-NEXT: vse64.v v9, (a1) ; CHECK-NEXT: ret %a = load <2 x float>, <2 x float>* %x %d = fptoui <2 x float> %a to <2 x i64> @@ -226,34 +226,34 @@ define void @fp2si_v8f32_v8i64(<8 x float>* %x, <8 x i64>* %y) { ; LMULMAX8-LABEL: fp2si_v8f32_v8i64: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX8-NEXT: vle32.v v26, (a0) -; LMULMAX8-NEXT: vfwcvt.rtz.x.f.v v28, v26 -; LMULMAX8-NEXT: vse64.v v28, (a1) +; LMULMAX8-NEXT: vle32.v v8, (a0) +; LMULMAX8-NEXT: vfwcvt.rtz.x.f.v v12, v8 +; LMULMAX8-NEXT: vse64.v v12, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2si_v8f32_v8i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: addi a2, a0, 16 -; LMULMAX1-NEXT: vle32.v v25, (a2) -; LMULMAX1-NEXT: vle32.v v26, (a0) +; LMULMAX1-NEXT: vle32.v v8, (a2) +; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v10, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v28, v27 +; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v11, v10 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v29, v27 -; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v27, v25 -; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v25, v26 +; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v12, v10 +; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v10, v8 +; LMULMAX1-NEXT: vfwcvt.rtz.x.f.v v8, v9 ; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse64.v v29, (a0) -; LMULMAX1-NEXT: vse64.v v25, (a1) +; LMULMAX1-NEXT: vse64.v v12, (a0) +; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a1, 48 -; LMULMAX1-NEXT: vse64.v v28, (a0) +; LMULMAX1-NEXT: vse64.v v11, (a0) ; LMULMAX1-NEXT: addi a0, a1, 32 -; LMULMAX1-NEXT: vse64.v v27, (a0) +; LMULMAX1-NEXT: vse64.v v10, (a0) ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %d = fptosi <8 x float> %a to <8 x i64> @@ -265,34 +265,34 @@ define void @fp2ui_v8f32_v8i64(<8 x float>* %x, <8 x i64>* %y) { ; LMULMAX8-LABEL: fp2ui_v8f32_v8i64: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX8-NEXT: vle32.v v26, (a0) -; LMULMAX8-NEXT: vfwcvt.rtz.xu.f.v v28, v26 -; LMULMAX8-NEXT: vse64.v v28, (a1) +; LMULMAX8-NEXT: vle32.v v8, (a0) +; LMULMAX8-NEXT: vfwcvt.rtz.xu.f.v v12, v8 +; LMULMAX8-NEXT: vse64.v v12, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2ui_v8f32_v8i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: addi a2, a0, 16 -; LMULMAX1-NEXT: vle32.v v25, (a2) -; LMULMAX1-NEXT: vle32.v v26, (a0) +; LMULMAX1-NEXT: vle32.v v8, (a2) +; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v10, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v28, v27 +; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v11, v10 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v26, 2 +; LMULMAX1-NEXT: vslidedown.vi v10, v9, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v29, v27 -; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v27, v25 -; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v25, v26 +; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v12, v10 +; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v10, v8 +; LMULMAX1-NEXT: vfwcvt.rtz.xu.f.v v8, v9 ; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse64.v v29, (a0) -; LMULMAX1-NEXT: vse64.v v25, (a1) +; LMULMAX1-NEXT: vse64.v v12, (a0) +; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a1, 48 -; LMULMAX1-NEXT: vse64.v v28, (a0) +; LMULMAX1-NEXT: vse64.v v11, (a0) ; LMULMAX1-NEXT: addi a0, a1, 32 -; LMULMAX1-NEXT: vse64.v v27, (a0) +; LMULMAX1-NEXT: vse64.v v10, (a0) ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %d = fptoui <8 x float> %a to <8 x i64> @@ -304,11 +304,11 @@ define void @fp2si_v2f16_v2i64(<2 x half>* %x, <2 x i64>* %y) { ; CHECK-LABEL: fp2si_v2f16_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfwcvt.f.f.v v26, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v26 -; CHECK-NEXT: vse64.v v25, (a1) +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9 +; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x half>, <2 x half>* %x %d = fptosi <2 x half> %a to <2 x i64> @@ -320,11 +320,11 @@ define void @fp2ui_v2f16_v2i64(<2 x half>* %x, <2 x i64>* %y) { ; CHECK-LABEL: fp2ui_v2f16_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfwcvt.f.f.v v26, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v26 -; CHECK-NEXT: vse64.v v25, (a1) +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9 +; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x half>, <2 x half>* %x %d = fptoui <2 x half> %a to <2 x i64> @@ -336,9 +336,9 @@ define <2 x i1> @fp2si_v2f16_v2i1(<2 x half> %x) { ; CHECK-LABEL: fp2si_v2f16_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %z = fptosi <2 x half> %x to <2 x i1> ret <2 x i1> %z @@ -348,9 +348,9 @@ define <2 x i1> @fp2ui_v2f16_v2i1(<2 x half> %x) { ; CHECK-LABEL: fp2ui_v2f16_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %z = fptoui <2 x half> %x to <2 x i1> ret <2 x i1> %z @@ -360,14 +360,14 @@ define void @fp2si_v2f64_v2i8(<2 x double>* %x, <2 x i8>* %y) { ; CHECK-LABEL: fp2si_v2f64_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v25 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 -; CHECK-NEXT: vse8.v v25, (a1) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %d = fptosi <2 x double> %a to <2 x i8> @@ -379,14 +379,14 @@ define void @fp2ui_v2f64_v2i8(<2 x double>* %x, <2 x i8>* %y) { ; CHECK-LABEL: fp2ui_v2f64_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v25 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 -; CHECK-NEXT: vse8.v v25, (a1) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x double>, <2 x double>* %x %d = fptoui <2 x double> %a to <2 x i8> @@ -398,9 +398,9 @@ define <2 x i1> @fp2si_v2f64_v2i1(<2 x double> %x) { ; CHECK-LABEL: fp2si_v2f64_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %z = fptosi <2 x double> %x to <2 x i1> ret <2 x i1> %z @@ -410,9 +410,9 @@ define <2 x i1> @fp2ui_v2f64_v2i1(<2 x double> %x) { ; CHECK-LABEL: fp2ui_v2f64_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %z = fptoui <2 x double> %x to <2 x i1> ret <2 x i1> %z @@ -422,61 +422,61 @@ define void @fp2si_v8f64_v8i8(<8 x double>* %x, <8 x i8>* %y) { ; LMULMAX8-LABEL: fp2si_v8f64_v8i8: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; LMULMAX8-NEXT: vle64.v v28, (a0) +; LMULMAX8-NEXT: vle64.v v8, (a0) ; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v26, v28 +; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v12, v8 ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; LMULMAX8-NEXT: vnsrl.wi v25, v26, 0 +; LMULMAX8-NEXT: vnsrl.wi v8, v12, 0 ; LMULMAX8-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; LMULMAX8-NEXT: vnsrl.wi v25, v25, 0 -; LMULMAX8-NEXT: vse8.v v25, (a1) +; LMULMAX8-NEXT: vnsrl.wi v8, v8, 0 +; LMULMAX8-NEXT: vse8.v v8, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2si_v8f64_v8i8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: addi a2, a0, 48 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vle64.v v25, (a2) +; LMULMAX1-NEXT: vle64.v v8, (a2) ; LMULMAX1-NEXT: addi a2, a0, 32 -; LMULMAX1-NEXT: vle64.v v26, (a2) -; LMULMAX1-NEXT: vle64.v v27, (a0) +; LMULMAX1-NEXT: vle64.v v9, (a2) +; LMULMAX1-NEXT: vle64.v v10, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vle64.v v28, (a0) +; LMULMAX1-NEXT: vle64.v v11, (a0) ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v29, v27 +; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v12, v10 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v27, v29, 0 +; LMULMAX1-NEXT: vnsrl.wi v10, v12, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0 +; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmv.v.i v29, 0 +; LMULMAX1-NEXT: vmv.v.i v12, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v27, 0 +; LMULMAX1-NEXT: vslideup.vi v12, v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v27, v28 +; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v11 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0 +; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0 +; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v27, 2 +; LMULMAX1-NEXT: vslideup.vi v12, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v27, v26 +; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v9 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v27, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v26, 4 +; LMULMAX1-NEXT: vslideup.vi v12, v9, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v26, v25 +; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v9, v8 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v25, 6 -; LMULMAX1-NEXT: vse8.v v29, (a1) +; LMULMAX1-NEXT: vslideup.vi v12, v8, 6 +; LMULMAX1-NEXT: vse8.v v12, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x double>, <8 x double>* %x %d = fptosi <8 x double> %a to <8 x i8> @@ -488,61 +488,61 @@ define void @fp2ui_v8f64_v8i8(<8 x double>* %x, <8 x i8>* %y) { ; LMULMAX8-LABEL: fp2ui_v8f64_v8i8: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; LMULMAX8-NEXT: vle64.v v28, (a0) +; LMULMAX8-NEXT: vle64.v v8, (a0) ; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v26, v28 +; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v12, v8 ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; LMULMAX8-NEXT: vnsrl.wi v25, v26, 0 +; LMULMAX8-NEXT: vnsrl.wi v8, v12, 0 ; LMULMAX8-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; LMULMAX8-NEXT: vnsrl.wi v25, v25, 0 -; LMULMAX8-NEXT: vse8.v v25, (a1) +; LMULMAX8-NEXT: vnsrl.wi v8, v8, 0 +; LMULMAX8-NEXT: vse8.v v8, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2ui_v8f64_v8i8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: addi a2, a0, 48 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vle64.v v25, (a2) +; LMULMAX1-NEXT: vle64.v v8, (a2) ; LMULMAX1-NEXT: addi a2, a0, 32 -; LMULMAX1-NEXT: vle64.v v26, (a2) -; LMULMAX1-NEXT: vle64.v v27, (a0) +; LMULMAX1-NEXT: vle64.v v9, (a2) +; LMULMAX1-NEXT: vle64.v v10, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vle64.v v28, (a0) +; LMULMAX1-NEXT: vle64.v v11, (a0) ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v29, v27 +; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v12, v10 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v27, v29, 0 +; LMULMAX1-NEXT: vnsrl.wi v10, v12, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0 +; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmv.v.i v29, 0 +; LMULMAX1-NEXT: vmv.v.i v12, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v27, 0 +; LMULMAX1-NEXT: vslideup.vi v12, v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v27, v28 +; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v11 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0 +; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v27, v27, 0 +; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v27, 2 +; LMULMAX1-NEXT: vslideup.vi v12, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v27, v26 +; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v9 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v27, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v26, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v26, 4 +; LMULMAX1-NEXT: vslideup.vi v12, v9, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v26, v25 +; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v25, 6 -; LMULMAX1-NEXT: vse8.v v29, (a1) +; LMULMAX1-NEXT: vslideup.vi v12, v8, 6 +; LMULMAX1-NEXT: vse8.v v12, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x double>, <8 x double>* %x %d = fptoui <8 x double> %a to <8 x i8> @@ -554,61 +554,61 @@ define <8 x i1> @fp2si_v8f64_v8i1(<8 x double> %x) { ; LMULMAX8-LABEL: fp2si_v8f64_v8i1: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v26, v8 -; LMULMAX8-NEXT: vand.vi v26, v26, 1 -; LMULMAX8-NEXT: vmsne.vi v0, v26, 0 +; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v12, v8 +; LMULMAX8-NEXT: vand.vi v8, v12, 1 +; LMULMAX8-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2si_v8f64_v8i1: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vmclr.m v0 -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v12, 0 +; LMULMAX1-NEXT: vmerge.vim v13, v12, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v27, v8 -; LMULMAX1-NEXT: vand.vi v27, v27, 1 -; LMULMAX1-NEXT: vmsne.vi v0, v27, 0 +; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v14, v8 +; LMULMAX1-NEXT: vand.vi v8, v14, 1 +; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vmv.v.i v27, 0 -; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v8, 0 +; LMULMAX1-NEXT: vmerge.vim v14, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v28, 0 +; LMULMAX1-NEXT: vslideup.vi v13, v14, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v26, 0 -; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0 +; LMULMAX1-NEXT: vmsne.vi v0, v13, 0 +; LMULMAX1-NEXT: vmerge.vim v13, v12, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v28, v9 -; LMULMAX1-NEXT: vand.vi v28, v28, 1 -; LMULMAX1-NEXT: vmsne.vi v0, v28, 0 +; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v14, v9 +; LMULMAX1-NEXT: vand.vi v9, v14, 1 +; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0 +; LMULMAX1-NEXT: vmerge.vim v9, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v28, 2 +; LMULMAX1-NEXT: vslideup.vi v13, v9, 2 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v26, 0 -; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0 +; LMULMAX1-NEXT: vmsne.vi v0, v13, 0 +; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v28, v10 -; LMULMAX1-NEXT: vand.vi v28, v28, 1 -; LMULMAX1-NEXT: vmsne.vi v0, v28, 0 +; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v13, v10 +; LMULMAX1-NEXT: vand.vi v10, v13, 1 +; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0 +; LMULMAX1-NEXT: vmerge.vim v10, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v28, 4 +; LMULMAX1-NEXT: vslideup.vi v9, v10, 4 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v26, 0 -; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 +; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v26, v11 -; LMULMAX1-NEXT: vand.vi v26, v26, 1 -; LMULMAX1-NEXT: vmsne.vi v0, v26, 0 +; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v11 +; LMULMAX1-NEXT: vand.vi v10, v10, 1 +; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vmerge.vim v26, v27, 1, v0 +; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v26, 6 +; LMULMAX1-NEXT: vslideup.vi v9, v8, 6 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: ret %z = fptosi <8 x double> %x to <8 x i1> ret <8 x i1> %z @@ -618,61 +618,61 @@ define <8 x i1> @fp2ui_v8f64_v8i1(<8 x double> %x) { ; LMULMAX8-LABEL: fp2ui_v8f64_v8i1: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v26, v8 -; LMULMAX8-NEXT: vand.vi v26, v26, 1 -; LMULMAX8-NEXT: vmsne.vi v0, v26, 0 +; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v12, v8 +; LMULMAX8-NEXT: vand.vi v8, v12, 1 +; LMULMAX8-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: fp2ui_v8f64_v8i1: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vmclr.m v0 -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v12, 0 +; LMULMAX1-NEXT: vmerge.vim v13, v12, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v27, v8 -; LMULMAX1-NEXT: vand.vi v27, v27, 1 -; LMULMAX1-NEXT: vmsne.vi v0, v27, 0 +; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v14, v8 +; LMULMAX1-NEXT: vand.vi v8, v14, 1 +; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vmv.v.i v27, 0 -; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v8, 0 +; LMULMAX1-NEXT: vmerge.vim v14, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v28, 0 +; LMULMAX1-NEXT: vslideup.vi v13, v14, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v26, 0 -; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0 +; LMULMAX1-NEXT: vmsne.vi v0, v13, 0 +; LMULMAX1-NEXT: vmerge.vim v13, v12, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v28, v9 -; LMULMAX1-NEXT: vand.vi v28, v28, 1 -; LMULMAX1-NEXT: vmsne.vi v0, v28, 0 +; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v14, v9 +; LMULMAX1-NEXT: vand.vi v9, v14, 1 +; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0 +; LMULMAX1-NEXT: vmerge.vim v9, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v28, 2 +; LMULMAX1-NEXT: vslideup.vi v13, v9, 2 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v26, 0 -; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0 +; LMULMAX1-NEXT: vmsne.vi v0, v13, 0 +; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v28, v10 -; LMULMAX1-NEXT: vand.vi v28, v28, 1 -; LMULMAX1-NEXT: vmsne.vi v0, v28, 0 +; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v13, v10 +; LMULMAX1-NEXT: vand.vi v10, v13, 1 +; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0 +; LMULMAX1-NEXT: vmerge.vim v10, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v28, 4 +; LMULMAX1-NEXT: vslideup.vi v9, v10, 4 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v26, 0 -; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0 +; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 +; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v26, v11 -; LMULMAX1-NEXT: vand.vi v26, v26, 1 -; LMULMAX1-NEXT: vmsne.vi v0, v26, 0 +; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v11 +; LMULMAX1-NEXT: vand.vi v10, v10, 1 +; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; LMULMAX1-NEXT: vmerge.vim v26, v27, 1, v0 +; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v26, 6 +; LMULMAX1-NEXT: vslideup.vi v9, v8, 6 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: ret %z = fptoui <8 x double> %x to <8 x i1> ret <8 x i1> %z diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll index d9f095dcbe19e0c53d9181373bfbb2ba6134a7f7..8559d278946e40e8fbcbaeeab438e541e7dbcabd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll @@ -8,9 +8,9 @@ define void @si2fp_v2i32_v2f32(<2 x i32>* %x, <2 x float>* %y) { ; CHECK-LABEL: si2fp_v2i32_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfcvt.f.x.v v25, v25 -; CHECK-NEXT: vse32.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: vse32.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %d = sitofp <2 x i32> %a to <2 x float> @@ -22,9 +22,9 @@ define void @ui2fp_v2i32_v2f32(<2 x i32>* %x, <2 x float>* %y) { ; CHECK-LABEL: ui2fp_v2i32_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfcvt.f.xu.v v25, v25 -; CHECK-NEXT: vse32.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: vse32.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %d = uitofp <2 x i32> %a to <2 x float> @@ -36,9 +36,9 @@ define <2 x float> @si2fp_v2i1_v2f32(<2 x i1> %x) { ; CHECK-LABEL: si2fp_v2i1_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 -; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %z = sitofp <2 x i1> %x to <2 x float> ret <2 x float> %z @@ -48,9 +48,9 @@ define <2 x float> @ui2fp_v2i1_v2f32(<2 x i1> %x) { ; CHECK-LABEL: ui2fp_v2i1_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 -; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret %z = uitofp <2 x i1> %x to <2 x float> ret <2 x float> %z @@ -60,22 +60,22 @@ define void @si2fp_v8i32_v8f32(<8 x i32>* %x, <8 x float>* %y) { ; LMULMAX8-LABEL: si2fp_v8i32_v8f32: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX8-NEXT: vle32.v v26, (a0) -; LMULMAX8-NEXT: vfcvt.f.x.v v26, v26 -; LMULMAX8-NEXT: vse32.v v26, (a1) +; LMULMAX8-NEXT: vle32.v v8, (a0) +; LMULMAX8-NEXT: vfcvt.f.x.v v8, v8 +; LMULMAX8-NEXT: vse32.v v8, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: si2fp_v8i32_v8f32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: addi a2, a0, 16 -; LMULMAX1-NEXT: vle32.v v25, (a2) -; LMULMAX1-NEXT: vle32.v v26, (a0) -; LMULMAX1-NEXT: vfcvt.f.x.v v25, v25 -; LMULMAX1-NEXT: vfcvt.f.x.v v26, v26 -; LMULMAX1-NEXT: vse32.v v26, (a1) +; LMULMAX1-NEXT: vle32.v v8, (a2) +; LMULMAX1-NEXT: vle32.v v9, (a0) +; LMULMAX1-NEXT: vfcvt.f.x.v v8, v8 +; LMULMAX1-NEXT: vfcvt.f.x.v v9, v9 +; LMULMAX1-NEXT: vse32.v v9, (a1) ; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %d = sitofp <8 x i32> %a to <8 x float> @@ -87,22 +87,22 @@ define void @ui2fp_v8i32_v8f32(<8 x i32>* %x, <8 x float>* %y) { ; LMULMAX8-LABEL: ui2fp_v8i32_v8f32: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX8-NEXT: vle32.v v26, (a0) -; LMULMAX8-NEXT: vfcvt.f.xu.v v26, v26 -; LMULMAX8-NEXT: vse32.v v26, (a1) +; LMULMAX8-NEXT: vle32.v v8, (a0) +; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v8 +; LMULMAX8-NEXT: vse32.v v8, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: ui2fp_v8i32_v8f32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: addi a2, a0, 16 -; LMULMAX1-NEXT: vle32.v v25, (a2) -; LMULMAX1-NEXT: vle32.v v26, (a0) -; LMULMAX1-NEXT: vfcvt.f.xu.v v25, v25 -; LMULMAX1-NEXT: vfcvt.f.xu.v v26, v26 -; LMULMAX1-NEXT: vse32.v v26, (a1) +; LMULMAX1-NEXT: vle32.v v8, (a2) +; LMULMAX1-NEXT: vle32.v v9, (a0) +; LMULMAX1-NEXT: vfcvt.f.xu.v v8, v8 +; LMULMAX1-NEXT: vfcvt.f.xu.v v9, v9 +; LMULMAX1-NEXT: vse32.v v9, (a1) ; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %d = uitofp <8 x i32> %a to <8 x float> @@ -313,27 +313,27 @@ define <8 x float> @si2fp_v8i1_v8f32(<8 x i1> %x) { ; LMULMAX8-LABEL: si2fp_v8i1_v8f32: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX8-NEXT: vmv.v.i v26, 0 -; LMULMAX8-NEXT: vmerge.vim v26, v26, -1, v0 -; LMULMAX8-NEXT: vfcvt.f.x.v v8, v26 +; LMULMAX8-NEXT: vmv.v.i v8, 0 +; LMULMAX8-NEXT: vmerge.vim v8, v8, -1, v0 +; LMULMAX8-NEXT: vfcvt.f.x.v v8, v8 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: si2fp_v8i1_v8f32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vmerge.vim v26, v25, -1, v0 -; LMULMAX1-NEXT: vfcvt.f.x.v v8, v26 +; LMULMAX1-NEXT: vmv.v.i v9, 0 +; LMULMAX1-NEXT: vmerge.vim v8, v9, -1, v0 +; LMULMAX1-NEXT: vfcvt.f.x.v v8, v8 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 -; LMULMAX1-NEXT: vmerge.vim v26, v26, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v10, 0 +; LMULMAX1-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v26, 4 +; LMULMAX1-NEXT: vslidedown.vi v10, v10, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v26, 0 +; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; LMULMAX1-NEXT: vmerge.vim v25, v25, -1, v0 -; LMULMAX1-NEXT: vfcvt.f.x.v v9, v25 +; LMULMAX1-NEXT: vmerge.vim v9, v9, -1, v0 +; LMULMAX1-NEXT: vfcvt.f.x.v v9, v9 ; LMULMAX1-NEXT: ret %z = sitofp <8 x i1> %x to <8 x float> ret <8 x float> %z @@ -518,27 +518,27 @@ define <8 x float> @ui2fp_v8i1_v8f32(<8 x i1> %x) { ; LMULMAX8-LABEL: ui2fp_v8i1_v8f32: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX8-NEXT: vmv.v.i v26, 0 -; LMULMAX8-NEXT: vmerge.vim v26, v26, 1, v0 -; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v26 +; LMULMAX8-NEXT: vmv.v.i v8, 0 +; LMULMAX8-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v8 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: ui2fp_v8i1_v8f32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vmerge.vim v26, v25, 1, v0 -; LMULMAX1-NEXT: vfcvt.f.xu.v v8, v26 +; LMULMAX1-NEXT: vmv.v.i v9, 0 +; LMULMAX1-NEXT: vmerge.vim v8, v9, 1, v0 +; LMULMAX1-NEXT: vfcvt.f.xu.v v8, v8 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 -; LMULMAX1-NEXT: vmerge.vim v26, v26, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v10, 0 +; LMULMAX1-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v26, 4 +; LMULMAX1-NEXT: vslidedown.vi v10, v10, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v26, 0 +; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0 -; LMULMAX1-NEXT: vfcvt.f.xu.v v9, v25 +; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0 +; LMULMAX1-NEXT: vfcvt.f.xu.v v9, v9 ; LMULMAX1-NEXT: ret %z = uitofp <8 x i1> %x to <8 x float> ret <8 x float> %z @@ -548,11 +548,11 @@ define void @si2fp_v2i16_v2f64(<2 x i16>* %x, <2 x double>* %y) { ; CHECK-LABEL: si2fp_v2i16_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v26, v25 -; CHECK-NEXT: vfcvt.f.x.v v25, v26 -; CHECK-NEXT: vse64.v v25, (a1) +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vfcvt.f.x.v v8, v9 +; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x i16>, <2 x i16>* %x %d = sitofp <2 x i16> %a to <2 x double> @@ -564,11 +564,11 @@ define void @ui2fp_v2i16_v2f64(<2 x i16>* %x, <2 x double>* %y) { ; CHECK-LABEL: ui2fp_v2i16_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v26, v25 -; CHECK-NEXT: vfcvt.f.xu.v v25, v26 -; CHECK-NEXT: vse64.v v25, (a1) +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vfcvt.f.xu.v v8, v9 +; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x i16>, <2 x i16>* %x %d = uitofp <2 x i16> %a to <2 x double> @@ -580,40 +580,40 @@ define void @si2fp_v8i16_v8f64(<8 x i16>* %x, <8 x double>* %y) { ; LMULMAX8-LABEL: si2fp_v8i16_v8f64: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX8-NEXT: vle16.v v25, (a0) +; LMULMAX8-NEXT: vle16.v v8, (a0) ; LMULMAX8-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; LMULMAX8-NEXT: vsext.vf4 v28, v25 -; LMULMAX8-NEXT: vfcvt.f.x.v v28, v28 -; LMULMAX8-NEXT: vse64.v v28, (a1) +; LMULMAX8-NEXT: vsext.vf4 v12, v8 +; LMULMAX8-NEXT: vfcvt.f.x.v v8, v12 +; LMULMAX8-NEXT: vse64.v v8, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: si2fp_v8i16_v8f64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v8, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v27, v26 -; LMULMAX1-NEXT: vfcvt.f.x.v v26, v27 +; LMULMAX1-NEXT: vsext.vf4 v10, v9 +; LMULMAX1-NEXT: vfcvt.f.x.v v9, v10 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v28, v27, 2 +; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v29, v28 -; LMULMAX1-NEXT: vfcvt.f.x.v v28, v29 -; LMULMAX1-NEXT: vsext.vf4 v29, v27 -; LMULMAX1-NEXT: vfcvt.f.x.v v27, v29 -; LMULMAX1-NEXT: vsext.vf4 v29, v25 -; LMULMAX1-NEXT: vfcvt.f.x.v v25, v29 +; LMULMAX1-NEXT: vsext.vf4 v12, v11 +; LMULMAX1-NEXT: vfcvt.f.x.v v11, v12 +; LMULMAX1-NEXT: vsext.vf4 v12, v10 +; LMULMAX1-NEXT: vfcvt.f.x.v v10, v12 +; LMULMAX1-NEXT: vsext.vf4 v12, v8 +; LMULMAX1-NEXT: vfcvt.f.x.v v8, v12 ; LMULMAX1-NEXT: addi a0, a1, 32 -; LMULMAX1-NEXT: vse64.v v27, (a0) -; LMULMAX1-NEXT: vse64.v v25, (a1) +; LMULMAX1-NEXT: vse64.v v10, (a0) +; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a1, 48 -; LMULMAX1-NEXT: vse64.v v28, (a0) +; LMULMAX1-NEXT: vse64.v v11, (a0) ; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse64.v v26, (a0) +; LMULMAX1-NEXT: vse64.v v9, (a0) ; LMULMAX1-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %d = sitofp <8 x i16> %a to <8 x double> @@ -625,40 +625,40 @@ define void @ui2fp_v8i16_v8f64(<8 x i16>* %x, <8 x double>* %y) { ; LMULMAX8-LABEL: ui2fp_v8i16_v8f64: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX8-NEXT: vle16.v v25, (a0) +; LMULMAX8-NEXT: vle16.v v8, (a0) ; LMULMAX8-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; LMULMAX8-NEXT: vzext.vf4 v28, v25 -; LMULMAX8-NEXT: vfcvt.f.xu.v v28, v28 -; LMULMAX8-NEXT: vse64.v v28, (a1) +; LMULMAX8-NEXT: vzext.vf4 v12, v8 +; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v12 +; LMULMAX8-NEXT: vse64.v v8, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: ui2fp_v8i16_v8f64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v8, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v27, v26 -; LMULMAX1-NEXT: vfcvt.f.xu.v v26, v27 +; LMULMAX1-NEXT: vzext.vf4 v10, v9 +; LMULMAX1-NEXT: vfcvt.f.xu.v v9, v10 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v28, v27, 2 +; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vzext.vf4 v29, v28 -; LMULMAX1-NEXT: vfcvt.f.xu.v v28, v29 -; LMULMAX1-NEXT: vzext.vf4 v29, v27 -; LMULMAX1-NEXT: vfcvt.f.xu.v v27, v29 -; LMULMAX1-NEXT: vzext.vf4 v29, v25 -; LMULMAX1-NEXT: vfcvt.f.xu.v v25, v29 +; LMULMAX1-NEXT: vzext.vf4 v12, v11 +; LMULMAX1-NEXT: vfcvt.f.xu.v v11, v12 +; LMULMAX1-NEXT: vzext.vf4 v12, v10 +; LMULMAX1-NEXT: vfcvt.f.xu.v v10, v12 +; LMULMAX1-NEXT: vzext.vf4 v12, v8 +; LMULMAX1-NEXT: vfcvt.f.xu.v v8, v12 ; LMULMAX1-NEXT: addi a0, a1, 32 -; LMULMAX1-NEXT: vse64.v v27, (a0) -; LMULMAX1-NEXT: vse64.v v25, (a1) +; LMULMAX1-NEXT: vse64.v v10, (a0) +; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a1, 48 -; LMULMAX1-NEXT: vse64.v v28, (a0) +; LMULMAX1-NEXT: vse64.v v11, (a0) ; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse64.v v26, (a0) +; LMULMAX1-NEXT: vse64.v v9, (a0) ; LMULMAX1-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %d = uitofp <8 x i16> %a to <8 x double> @@ -884,48 +884,48 @@ define <8 x double> @si2fp_v8i1_v8f64(<8 x i1> %x) { ; LMULMAX8-LABEL: si2fp_v8i1_v8f64: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; LMULMAX8-NEXT: vmv.v.i v28, 0 -; LMULMAX8-NEXT: vmerge.vim v28, v28, -1, v0 -; LMULMAX8-NEXT: vfcvt.f.x.v v8, v28 +; LMULMAX8-NEXT: vmv.v.i v8, 0 +; LMULMAX8-NEXT: vmerge.vim v8, v8, -1, v0 +; LMULMAX8-NEXT: vfcvt.f.x.v v8, v8 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: si2fp_v8i1_v8f64: ; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vmv1r.v v25, v0 +; LMULMAX1-NEXT: vmv1r.v v10, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 -; LMULMAX1-NEXT: vmerge.vim v27, v26, -1, v0 -; LMULMAX1-NEXT: vfcvt.f.x.v v8, v27 +; LMULMAX1-NEXT: vmv.v.i v11, 0 +; LMULMAX1-NEXT: vmerge.vim v8, v11, -1, v0 +; LMULMAX1-NEXT: vfcvt.f.x.v v8, v8 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX1-NEXT: vmv.v.i v27, 0 -; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v12, 0 +; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v28, v28, 2 +; LMULMAX1-NEXT: vslidedown.vi v9, v9, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v28, 0 +; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; LMULMAX1-NEXT: vmerge.vim v28, v26, -1, v0 -; LMULMAX1-NEXT: vfcvt.f.x.v v9, v28 +; LMULMAX1-NEXT: vmerge.vim v9, v11, -1, v0 +; LMULMAX1-NEXT: vfcvt.f.x.v v9, v9 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmv.v.i v28, 0 -; LMULMAX1-NEXT: vmv1r.v v0, v25 -; LMULMAX1-NEXT: vmerge.vim v25, v28, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v13, 0 +; LMULMAX1-NEXT: vmv1r.v v0, v10 +; LMULMAX1-NEXT: vmerge.vim v10, v13, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v25, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v10, v10, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vmerge.vim v25, v26, -1, v0 -; LMULMAX1-NEXT: vfcvt.f.x.v v10, v25 +; LMULMAX1-NEXT: vmerge.vim v10, v11, -1, v0 +; LMULMAX1-NEXT: vfcvt.f.x.v v10, v10 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX1-NEXT: vmerge.vim v25, v27, 1, v0 +; LMULMAX1-NEXT: vmerge.vim v12, v12, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v25, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v12, v12, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX1-NEXT: vmsne.vi v0, v12, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; LMULMAX1-NEXT: vmerge.vim v25, v26, -1, v0 -; LMULMAX1-NEXT: vfcvt.f.x.v v11, v25 +; LMULMAX1-NEXT: vmerge.vim v11, v11, -1, v0 +; LMULMAX1-NEXT: vfcvt.f.x.v v11, v11 ; LMULMAX1-NEXT: ret %z = sitofp <8 x i1> %x to <8 x double> ret <8 x double> %z @@ -1125,48 +1125,48 @@ define <8 x double> @ui2fp_v8i1_v8f64(<8 x i1> %x) { ; LMULMAX8-LABEL: ui2fp_v8i1_v8f64: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; LMULMAX8-NEXT: vmv.v.i v28, 0 -; LMULMAX8-NEXT: vmerge.vim v28, v28, 1, v0 -; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v28 +; LMULMAX8-NEXT: vmv.v.i v8, 0 +; LMULMAX8-NEXT: vmerge.vim v8, v8, 1, v0 +; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v8 ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: ui2fp_v8i1_v8f64: ; LMULMAX1: # %bb.0: -; LMULMAX1-NEXT: vmv1r.v v25, v0 +; LMULMAX1-NEXT: vmv1r.v v10, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v26, 0 -; LMULMAX1-NEXT: vmerge.vim v27, v26, 1, v0 -; LMULMAX1-NEXT: vfcvt.f.xu.v v8, v27 +; LMULMAX1-NEXT: vmv.v.i v11, 0 +; LMULMAX1-NEXT: vmerge.vim v8, v11, 1, v0 +; LMULMAX1-NEXT: vfcvt.f.xu.v v8, v8 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX1-NEXT: vmv.v.i v27, 0 -; LMULMAX1-NEXT: vmerge.vim v28, v27, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v12, 0 +; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v28, v28, 2 +; LMULMAX1-NEXT: vslidedown.vi v9, v9, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v28, 0 +; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; LMULMAX1-NEXT: vmerge.vim v28, v26, 1, v0 -; LMULMAX1-NEXT: vfcvt.f.xu.v v9, v28 +; LMULMAX1-NEXT: vmerge.vim v9, v11, 1, v0 +; LMULMAX1-NEXT: vfcvt.f.xu.v v9, v9 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmv.v.i v28, 0 -; LMULMAX1-NEXT: vmv1r.v v0, v25 -; LMULMAX1-NEXT: vmerge.vim v25, v28, 1, v0 +; LMULMAX1-NEXT: vmv.v.i v13, 0 +; LMULMAX1-NEXT: vmv1r.v v0, v10 +; LMULMAX1-NEXT: vmerge.vim v10, v13, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v25, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v10, v10, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vmerge.vim v25, v26, 1, v0 -; LMULMAX1-NEXT: vfcvt.f.xu.v v10, v25 +; LMULMAX1-NEXT: vmerge.vim v10, v11, 1, v0 +; LMULMAX1-NEXT: vfcvt.f.xu.v v10, v10 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; LMULMAX1-NEXT: vmerge.vim v25, v27, 1, v0 +; LMULMAX1-NEXT: vmerge.vim v12, v12, 1, v0 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v25, v25, 2 +; LMULMAX1-NEXT: vslidedown.vi v12, v12, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; LMULMAX1-NEXT: vmsne.vi v0, v25, 0 +; LMULMAX1-NEXT: vmsne.vi v0, v12, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; LMULMAX1-NEXT: vmerge.vim v25, v26, 1, v0 -; LMULMAX1-NEXT: vfcvt.f.xu.v v11, v25 +; LMULMAX1-NEXT: vmerge.vim v11, v11, 1, v0 +; LMULMAX1-NEXT: vfcvt.f.xu.v v11, v11 ; LMULMAX1-NEXT: ret %z = uitofp <8 x i1> %x to <8 x double> ret <8 x double> %z @@ -1176,12 +1176,12 @@ define void @si2fp_v2i64_v2f16(<2 x i64>* %x, <2 x half>* %y) { ; CHECK-LABEL: si2fp_v2i64_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v26, v25 +; CHECK-NEXT: vfncvt.f.x.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.f.f.w v25, v26 -; CHECK-NEXT: vse16.v v25, (a1) +; CHECK-NEXT: vfncvt.f.f.w v8, v9 +; CHECK-NEXT: vse16.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %d = sitofp <2 x i64> %a to <2 x half> @@ -1193,12 +1193,12 @@ define void @ui2fp_v2i64_v2f16(<2 x i64>* %x, <2 x half>* %y) { ; CHECK-LABEL: ui2fp_v2i64_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v26, v25 +; CHECK-NEXT: vfncvt.f.xu.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.f.f.w v25, v26 -; CHECK-NEXT: vse16.v v25, (a1) +; CHECK-NEXT: vfncvt.f.f.w v8, v9 +; CHECK-NEXT: vse16.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %d = uitofp <2 x i64> %a to <2 x half> @@ -1210,9 +1210,9 @@ define <2 x half> @si2fp_v2i1_v2f16(<2 x i1> %x) { ; CHECK-LABEL: si2fp_v2i1_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 -; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %z = sitofp <2 x i1> %x to <2 x half> ret <2 x half> %z @@ -1222,9 +1222,9 @@ define <2 x half> @ui2fp_v2i1_v2f16(<2 x i1> %x) { ; CHECK-LABEL: ui2fp_v2i1_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 -; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret %z = uitofp <2 x i1> %x to <2 x half> ret <2 x half> %z @@ -1234,51 +1234,51 @@ define void @si2fp_v8i64_v8f16(<8 x i64>* %x, <8 x half>* %y) { ; LMULMAX8-LABEL: si2fp_v8i64_v8f16: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; LMULMAX8-NEXT: vle64.v v28, (a0) +; LMULMAX8-NEXT: vle64.v v8, (a0) ; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; LMULMAX8-NEXT: vfncvt.f.x.w v26, v28 +; LMULMAX8-NEXT: vfncvt.f.x.w v12, v8 ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26 -; LMULMAX8-NEXT: vse16.v v25, (a1) +; LMULMAX8-NEXT: vfncvt.f.f.w v8, v12 +; LMULMAX8-NEXT: vse16.v v8, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: si2fp_v8i64_v8f16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: addi a2, a0, 48 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vle64.v v25, (a2) +; LMULMAX1-NEXT: vle64.v v8, (a2) ; LMULMAX1-NEXT: addi a2, a0, 32 -; LMULMAX1-NEXT: vle64.v v26, (a2) -; LMULMAX1-NEXT: vle64.v v27, (a0) +; LMULMAX1-NEXT: vle64.v v9, (a2) +; LMULMAX1-NEXT: vle64.v v10, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vle64.v v28, (a0) +; LMULMAX1-NEXT: vle64.v v11, (a0) ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.f.x.w v29, v27 +; LMULMAX1-NEXT: vfncvt.f.x.w v12, v10 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfncvt.f.f.w v27, v29 +; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v29, 0 +; LMULMAX1-NEXT: vmv.v.i v12, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v27, 0 +; LMULMAX1-NEXT: vslideup.vi v12, v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.f.x.w v27, v28 +; LMULMAX1-NEXT: vfncvt.f.x.w v10, v11 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfncvt.f.f.w v28, v27 +; LMULMAX1-NEXT: vfncvt.f.f.w v11, v10 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v28, 2 +; LMULMAX1-NEXT: vslideup.vi v12, v11, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.f.x.w v27, v26 +; LMULMAX1-NEXT: vfncvt.f.x.w v10, v9 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfncvt.f.f.w v26, v27 +; LMULMAX1-NEXT: vfncvt.f.f.w v9, v10 ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v26, 4 +; LMULMAX1-NEXT: vslideup.vi v12, v9, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.f.x.w v26, v25 +; LMULMAX1-NEXT: vfncvt.f.x.w v9, v8 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfncvt.f.f.w v25, v26 +; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v25, 6 -; LMULMAX1-NEXT: vse16.v v29, (a1) +; LMULMAX1-NEXT: vslideup.vi v12, v8, 6 +; LMULMAX1-NEXT: vse16.v v12, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %d = sitofp <8 x i64> %a to <8 x half> @@ -1290,51 +1290,51 @@ define void @ui2fp_v8i64_v8f16(<8 x i64>* %x, <8 x half>* %y) { ; LMULMAX8-LABEL: ui2fp_v8i64_v8f16: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; LMULMAX8-NEXT: vle64.v v28, (a0) +; LMULMAX8-NEXT: vle64.v v8, (a0) ; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; LMULMAX8-NEXT: vfncvt.f.xu.w v26, v28 +; LMULMAX8-NEXT: vfncvt.f.xu.w v12, v8 ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; LMULMAX8-NEXT: vfncvt.f.f.w v25, v26 -; LMULMAX8-NEXT: vse16.v v25, (a1) +; LMULMAX8-NEXT: vfncvt.f.f.w v8, v12 +; LMULMAX8-NEXT: vse16.v v8, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX1-LABEL: ui2fp_v8i64_v8f16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: addi a2, a0, 48 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vle64.v v25, (a2) +; LMULMAX1-NEXT: vle64.v v8, (a2) ; LMULMAX1-NEXT: addi a2, a0, 32 -; LMULMAX1-NEXT: vle64.v v26, (a2) -; LMULMAX1-NEXT: vle64.v v27, (a0) +; LMULMAX1-NEXT: vle64.v v9, (a2) +; LMULMAX1-NEXT: vle64.v v10, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vle64.v v28, (a0) +; LMULMAX1-NEXT: vle64.v v11, (a0) ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.f.xu.w v29, v27 +; LMULMAX1-NEXT: vfncvt.f.xu.w v12, v10 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfncvt.f.f.w v27, v29 +; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v29, 0 +; LMULMAX1-NEXT: vmv.v.i v12, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v27, 0 +; LMULMAX1-NEXT: vslideup.vi v12, v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.f.xu.w v27, v28 +; LMULMAX1-NEXT: vfncvt.f.xu.w v10, v11 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfncvt.f.f.w v28, v27 +; LMULMAX1-NEXT: vfncvt.f.f.w v11, v10 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v28, 2 +; LMULMAX1-NEXT: vslideup.vi v12, v11, 2 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.f.xu.w v27, v26 +; LMULMAX1-NEXT: vfncvt.f.xu.w v10, v9 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfncvt.f.f.w v26, v27 +; LMULMAX1-NEXT: vfncvt.f.f.w v9, v10 ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v26, 4 +; LMULMAX1-NEXT: vslideup.vi v12, v9, 4 ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vfncvt.f.xu.w v26, v25 +; LMULMAX1-NEXT: vfncvt.f.xu.w v9, v8 ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; LMULMAX1-NEXT: vfncvt.f.f.w v25, v26 +; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v29, v25, 6 -; LMULMAX1-NEXT: vse16.v v29, (a1) +; LMULMAX1-NEXT: vslideup.vi v12, v8, 6 +; LMULMAX1-NEXT: vse16.v v12, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %d = uitofp <8 x i64> %a to <8 x half> @@ -1346,9 +1346,9 @@ define <8 x half> @si2fp_v8i1_v8f16(<8 x i1> %x) { ; CHECK-LABEL: si2fp_v8i1_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 -; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %z = sitofp <8 x i1> %x to <8 x half> ret <8 x half> %z @@ -1358,9 +1358,9 @@ define <8 x half> @ui2fp_v8i1_v8f16(<8 x i1> %x) { ; CHECK-LABEL: ui2fp_v8i1_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 -; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret %z = uitofp <8 x i1> %x to <8 x half> ret <8 x half> %z diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll index c1187e035ce1184aea6ea7484d77d26c83a598a9..613433c3cd26a87ecfe5c5be525dad61d40e74d5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll @@ -8,13 +8,13 @@ define <1 x i1> @insertelt_v1i1(<1 x i1> %x, i1 %elt) nounwind { ; CHECK-LABEL: insertelt_v1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement <1 x i1> %x, i1 %elt, i64 0 ret <1 x i1> %y @@ -24,30 +24,30 @@ define <1 x i1> @insertelt_idx_v1i1(<1 x i1> %x, i1 %elt, i32 zeroext %idx) noun ; RV32-LABEL: insertelt_idx_v1i1: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; RV32-NEXT: vmv.s.x v25, a0 -; RV32-NEXT: vmv.v.i v26, 0 -; RV32-NEXT: vmerge.vim v26, v26, 1, v0 +; RV32-NEXT: vmv.s.x v8, a0 +; RV32-NEXT: vmv.v.i v9, 0 +; RV32-NEXT: vmerge.vim v9, v9, 1, v0 ; RV32-NEXT: addi a0, a1, 1 ; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu -; RV32-NEXT: vslideup.vx v26, v25, a1 +; RV32-NEXT: vslideup.vx v9, v8, a1 ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; RV32-NEXT: vand.vi v25, v26, 1 -; RV32-NEXT: vmsne.vi v0, v25, 0 +; RV32-NEXT: vand.vi v8, v9, 1 +; RV32-NEXT: vmsne.vi v0, v8, 0 ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_idx_v1i1: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; RV64-NEXT: vmv.s.x v25, a0 -; RV64-NEXT: vmv.v.i v26, 0 -; RV64-NEXT: vmerge.vim v26, v26, 1, v0 +; RV64-NEXT: vmv.s.x v8, a0 +; RV64-NEXT: vmv.v.i v9, 0 +; RV64-NEXT: vmerge.vim v9, v9, 1, v0 ; RV64-NEXT: sext.w a0, a1 ; RV64-NEXT: addi a1, a0, 1 ; RV64-NEXT: vsetvli zero, a1, e8, mf8, tu, mu -; RV64-NEXT: vslideup.vx v26, v25, a0 +; RV64-NEXT: vslideup.vx v9, v8, a0 ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; RV64-NEXT: vand.vi v25, v26, 1 -; RV64-NEXT: vmsne.vi v0, v25, 0 +; RV64-NEXT: vand.vi v8, v9, 1 +; RV64-NEXT: vmsne.vi v0, v8, 0 ; RV64-NEXT: ret %y = insertelement <1 x i1> %x, i1 %elt, i32 %idx ret <1 x i1> %y @@ -57,14 +57,14 @@ define <2 x i1> @insertelt_v2i1(<2 x i1> %x, i1 %elt) nounwind { ; CHECK-LABEL: insertelt_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 1 +; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vand.vi v25, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement <2 x i1> %x, i1 %elt, i64 1 ret <2 x i1> %y @@ -74,30 +74,30 @@ define <2 x i1> @insertelt_idx_v2i1(<2 x i1> %x, i1 %elt, i32 zeroext %idx) noun ; RV32-LABEL: insertelt_idx_v2i1: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV32-NEXT: vmv.s.x v25, a0 -; RV32-NEXT: vmv.v.i v26, 0 -; RV32-NEXT: vmerge.vim v26, v26, 1, v0 +; RV32-NEXT: vmv.s.x v8, a0 +; RV32-NEXT: vmv.v.i v9, 0 +; RV32-NEXT: vmerge.vim v9, v9, 1, v0 ; RV32-NEXT: addi a0, a1, 1 ; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu -; RV32-NEXT: vslideup.vx v26, v25, a1 +; RV32-NEXT: vslideup.vx v9, v8, a1 ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV32-NEXT: vand.vi v25, v26, 1 -; RV32-NEXT: vmsne.vi v0, v25, 0 +; RV32-NEXT: vand.vi v8, v9, 1 +; RV32-NEXT: vmsne.vi v0, v8, 0 ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_idx_v2i1: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV64-NEXT: vmv.s.x v25, a0 -; RV64-NEXT: vmv.v.i v26, 0 -; RV64-NEXT: vmerge.vim v26, v26, 1, v0 +; RV64-NEXT: vmv.s.x v8, a0 +; RV64-NEXT: vmv.v.i v9, 0 +; RV64-NEXT: vmerge.vim v9, v9, 1, v0 ; RV64-NEXT: sext.w a0, a1 ; RV64-NEXT: addi a1, a0, 1 ; RV64-NEXT: vsetvli zero, a1, e8, mf8, tu, mu -; RV64-NEXT: vslideup.vx v26, v25, a0 +; RV64-NEXT: vslideup.vx v9, v8, a0 ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV64-NEXT: vand.vi v25, v26, 1 -; RV64-NEXT: vmsne.vi v0, v25, 0 +; RV64-NEXT: vand.vi v8, v9, 1 +; RV64-NEXT: vmsne.vi v0, v8, 0 ; RV64-NEXT: ret %y = insertelement <2 x i1> %x, i1 %elt, i32 %idx ret <2 x i1> %y @@ -107,14 +107,14 @@ define <8 x i1> @insertelt_v8i1(<8 x i1> %x, i1 %elt) nounwind { ; CHECK-LABEL: insertelt_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 1 +; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vand.vi v25, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement <8 x i1> %x, i1 %elt, i64 1 ret <8 x i1> %y @@ -124,30 +124,30 @@ define <8 x i1> @insertelt_idx_v8i1(<8 x i1> %x, i1 %elt, i32 zeroext %idx) noun ; RV32-LABEL: insertelt_idx_v8i1: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmv.s.x v25, a0 -; RV32-NEXT: vmv.v.i v26, 0 -; RV32-NEXT: vmerge.vim v26, v26, 1, v0 +; RV32-NEXT: vmv.s.x v8, a0 +; RV32-NEXT: vmv.v.i v9, 0 +; RV32-NEXT: vmerge.vim v9, v9, 1, v0 ; RV32-NEXT: addi a0, a1, 1 ; RV32-NEXT: vsetvli zero, a0, e8, mf2, tu, mu -; RV32-NEXT: vslideup.vx v26, v25, a1 +; RV32-NEXT: vslideup.vx v9, v8, a1 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vand.vi v25, v26, 1 -; RV32-NEXT: vmsne.vi v0, v25, 0 +; RV32-NEXT: vand.vi v8, v9, 1 +; RV32-NEXT: vmsne.vi v0, v8, 0 ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_idx_v8i1: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vmv.s.x v25, a0 -; RV64-NEXT: vmv.v.i v26, 0 -; RV64-NEXT: vmerge.vim v26, v26, 1, v0 +; RV64-NEXT: vmv.s.x v8, a0 +; RV64-NEXT: vmv.v.i v9, 0 +; RV64-NEXT: vmerge.vim v9, v9, 1, v0 ; RV64-NEXT: sext.w a0, a1 ; RV64-NEXT: addi a1, a0, 1 ; RV64-NEXT: vsetvli zero, a1, e8, mf2, tu, mu -; RV64-NEXT: vslideup.vx v26, v25, a0 +; RV64-NEXT: vslideup.vx v9, v8, a0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vand.vi v25, v26, 1 -; RV64-NEXT: vmsne.vi v0, v25, 0 +; RV64-NEXT: vand.vi v8, v9, 1 +; RV64-NEXT: vmsne.vi v0, v8, 0 ; RV64-NEXT: ret %y = insertelement <8 x i1> %x, i1 %elt, i32 %idx ret <8 x i1> %y @@ -158,14 +158,14 @@ define <64 x i1> @insertelt_v64i1(<64 x i1> %x, i1 %elt) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 64 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 -; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v12, 0 +; CHECK-NEXT: vmerge.vim v12, v12, 1, v0 ; CHECK-NEXT: vsetivli zero, 2, e8, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 1 +; CHECK-NEXT: vslideup.vi v12, v8, 1 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vand.vi v28, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vand.vi v8, v12, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement <64 x i1> %x, i1 %elt, i64 1 ret <64 x i1> %y @@ -176,31 +176,31 @@ define <64 x i1> @insertelt_idx_v64i1(<64 x i1> %x, i1 %elt, i32 zeroext %idx) n ; RV32: # %bb.0: ; RV32-NEXT: addi a2, zero, 64 ; RV32-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; RV32-NEXT: vmv.s.x v28, a0 -; RV32-NEXT: vmv.v.i v8, 0 -; RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; RV32-NEXT: vmv.s.x v8, a0 +; RV32-NEXT: vmv.v.i v12, 0 +; RV32-NEXT: vmerge.vim v12, v12, 1, v0 ; RV32-NEXT: addi a0, a1, 1 ; RV32-NEXT: vsetvli zero, a0, e8, m4, tu, mu -; RV32-NEXT: vslideup.vx v8, v28, a1 +; RV32-NEXT: vslideup.vx v12, v8, a1 ; RV32-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; RV32-NEXT: vand.vi v28, v8, 1 -; RV32-NEXT: vmsne.vi v0, v28, 0 +; RV32-NEXT: vand.vi v8, v12, 1 +; RV32-NEXT: vmsne.vi v0, v8, 0 ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_idx_v64i1: ; RV64: # %bb.0: ; RV64-NEXT: addi a2, zero, 64 ; RV64-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; RV64-NEXT: vmv.s.x v28, a0 -; RV64-NEXT: vmv.v.i v8, 0 -; RV64-NEXT: vmerge.vim v8, v8, 1, v0 +; RV64-NEXT: vmv.s.x v8, a0 +; RV64-NEXT: vmv.v.i v12, 0 +; RV64-NEXT: vmerge.vim v12, v12, 1, v0 ; RV64-NEXT: sext.w a0, a1 ; RV64-NEXT: addi a1, a0, 1 ; RV64-NEXT: vsetvli zero, a1, e8, m4, tu, mu -; RV64-NEXT: vslideup.vx v8, v28, a0 +; RV64-NEXT: vslideup.vx v12, v8, a0 ; RV64-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; RV64-NEXT: vand.vi v28, v8, 1 -; RV64-NEXT: vmsne.vi v0, v28, 0 +; RV64-NEXT: vand.vi v8, v12, 1 +; RV64-NEXT: vmsne.vi v0, v8, 0 ; RV64-NEXT: ret %y = insertelement <64 x i1> %x, i1 %elt, i32 %idx ret <64 x i1> %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll index 14f8d2667d27806fcf8356265fa78d7b52adf130..2f9fdafa05441ad9091200ca8a900cd205704e2c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll @@ -8,9 +8,9 @@ define @insert_nxv8i32_v2i32_0( %vec, <2 x ; CHECK-LABEL: insert_nxv8i32_v2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vle32.v v12, (a0) ; CHECK-NEXT: vsetivli zero, 2, e32, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 0 +; CHECK-NEXT: vslideup.vi v8, v12, 0 ; CHECK-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %v = call @llvm.experimental.vector.insert.v2i32.nxv8i32( %vec, <2 x i32> %sv, i64 0) @@ -21,9 +21,9 @@ define @insert_nxv8i32_v2i32_2( %vec, <2 x ; CHECK-LABEL: insert_nxv8i32_v2i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vle32.v v12, (a0) ; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 2 +; CHECK-NEXT: vslideup.vi v8, v12, 2 ; CHECK-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %v = call @llvm.experimental.vector.insert.v2i32.nxv8i32( %vec, <2 x i32> %sv, i64 2) @@ -34,9 +34,9 @@ define @insert_nxv8i32_v2i32_6( %vec, <2 x ; CHECK-LABEL: insert_nxv8i32_v2i32_6: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vle32.v v12, (a0) ; CHECK-NEXT: vsetivli zero, 8, e32, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 6 +; CHECK-NEXT: vslideup.vi v8, v12, 6 ; CHECK-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %v = call @llvm.experimental.vector.insert.v2i32.nxv8i32( %vec, <2 x i32> %sv, i64 6) @@ -47,21 +47,21 @@ define @insert_nxv8i32_v8i32_0( %vec, <8 x ; LMULMAX2-LABEL: insert_nxv8i32_v8i32_0: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v28, (a0) +; LMULMAX2-NEXT: vle32.v v12, (a0) ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m4, tu, mu -; LMULMAX2-NEXT: vslideup.vi v8, v28, 0 +; LMULMAX2-NEXT: vslideup.vi v8, v12, 0 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_nxv8i32_v8i32_0: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v28, (a0) -; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vle32.v v12, (a0) +; LMULMAX1-NEXT: addi a0, a0, 16 +; LMULMAX1-NEXT: vle32.v v16, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m4, tu, mu -; LMULMAX1-NEXT: vslideup.vi v8, v28, 0 +; LMULMAX1-NEXT: vslideup.vi v8, v12, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e32, m4, tu, mu -; LMULMAX1-NEXT: vslideup.vi v8, v12, 4 +; LMULMAX1-NEXT: vslideup.vi v8, v16, 4 ; LMULMAX1-NEXT: ret %sv = load <8 x i32>, <8 x i32>* %svp %v = call @llvm.experimental.vector.insert.v8i32.nxv8i32( %vec, <8 x i32> %sv, i64 0) @@ -72,21 +72,21 @@ define @insert_nxv8i32_v8i32_8( %vec, <8 x ; LMULMAX2-LABEL: insert_nxv8i32_v8i32_8: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v28, (a0) +; LMULMAX2-NEXT: vle32.v v12, (a0) ; LMULMAX2-NEXT: vsetivli zero, 16, e32, m4, tu, mu -; LMULMAX2-NEXT: vslideup.vi v8, v28, 8 +; LMULMAX2-NEXT: vslideup.vi v8, v12, 8 ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_nxv8i32_v8i32_8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v28, (a0) -; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vle32.v v12, (a0) +; LMULMAX1-NEXT: addi a0, a0, 16 +; LMULMAX1-NEXT: vle32.v v16, (a0) ; LMULMAX1-NEXT: vsetivli zero, 12, e32, m4, tu, mu -; LMULMAX1-NEXT: vslideup.vi v8, v28, 8 +; LMULMAX1-NEXT: vslideup.vi v8, v12, 8 ; LMULMAX1-NEXT: vsetivli zero, 16, e32, m4, tu, mu -; LMULMAX1-NEXT: vslideup.vi v8, v12, 12 +; LMULMAX1-NEXT: vslideup.vi v8, v16, 12 ; LMULMAX1-NEXT: ret %sv = load <8 x i32>, <8 x i32>* %svp %v = call @llvm.experimental.vector.insert.v8i32.nxv8i32( %vec, <8 x i32> %sv, i64 8) @@ -108,13 +108,13 @@ define void @insert_v4i32_v2i32_0(<4 x i32>* %vp, <2 x i32>* %svp) { ; CHECK-LABEL: insert_v4i32_v2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %vec = load <4 x i32>, <4 x i32>* %vp @@ -127,12 +127,12 @@ define void @insert_v4i32_v2i32_2(<4 x i32>* %vp, <2 x i32>* %svp) { ; CHECK-LABEL: insert_v4i32_v2i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 2 -; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: vslideup.vi v9, v8, 2 +; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %vec = load <4 x i32>, <4 x i32>* %vp @@ -145,13 +145,13 @@ define void @insert_v4i32_undef_v2i32_0(<4 x i32>* %vp, <2 x i32>* %svp) { ; CHECK-LABEL: insert_v4i32_undef_v2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %v = call <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32> undef, <2 x i32> %sv, i64 0) @@ -163,25 +163,25 @@ define void @insert_v8i32_v2i32_0(<8 x i32>* %vp, <2 x i32>* %svp) { ; LMULMAX2-LABEL: insert_v8i32_v2i32_0: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a1) +; LMULMAX2-NEXT: vle32.v v8, (a1) ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v28, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a0) ; LMULMAX2-NEXT: vsetivli zero, 2, e32, m2, tu, mu -; LMULMAX2-NEXT: vslideup.vi v28, v26, 0 +; LMULMAX2-NEXT: vslideup.vi v10, v8, 0 ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vse32.v v28, (a0) +; LMULMAX2-NEXT: vse32.v v10, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_v8i32_v2i32_0: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a1) +; LMULMAX1-NEXT: vle32.v v8, (a1) ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v26, (a0) +; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vse32.v v26, (a0) +; LMULMAX1-NEXT: vse32.v v9, (a0) ; LMULMAX1-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %vec = load <8 x i32>, <8 x i32>* %vp @@ -194,24 +194,24 @@ define void @insert_v8i32_v2i32_2(<8 x i32>* %vp, <2 x i32>* %svp) { ; LMULMAX2-LABEL: insert_v8i32_v2i32_2: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a1) +; LMULMAX2-NEXT: vle32.v v8, (a1) ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v28, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a0) ; LMULMAX2-NEXT: vsetivli zero, 4, e32, m2, tu, mu -; LMULMAX2-NEXT: vslideup.vi v28, v26, 2 +; LMULMAX2-NEXT: vslideup.vi v10, v8, 2 ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vse32.v v28, (a0) +; LMULMAX2-NEXT: vse32.v v10, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_v8i32_v2i32_2: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a1) +; LMULMAX1-NEXT: vle32.v v8, (a1) ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v26, (a0) +; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 -; LMULMAX1-NEXT: vse32.v v26, (a0) +; LMULMAX1-NEXT: vslideup.vi v9, v8, 2 +; LMULMAX1-NEXT: vse32.v v9, (a0) ; LMULMAX1-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %vec = load <8 x i32>, <8 x i32>* %vp @@ -224,24 +224,24 @@ define void @insert_v8i32_v2i32_6(<8 x i32>* %vp, <2 x i32>* %svp) { ; LMULMAX2-LABEL: insert_v8i32_v2i32_6: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a1) +; LMULMAX2-NEXT: vle32.v v8, (a1) ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v28, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a0) ; LMULMAX2-NEXT: vsetvli zero, zero, e32, m2, tu, mu -; LMULMAX2-NEXT: vslideup.vi v28, v26, 6 -; LMULMAX2-NEXT: vse32.v v28, (a0) +; LMULMAX2-NEXT: vslideup.vi v10, v8, 6 +; LMULMAX2-NEXT: vse32.v v10, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_v8i32_v2i32_6: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a1) +; LMULMAX1-NEXT: vle32.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v26, (a0) +; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, tu, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 -; LMULMAX1-NEXT: vse32.v v26, (a0) +; LMULMAX1-NEXT: vslideup.vi v9, v8, 2 +; LMULMAX1-NEXT: vse32.v v9, (a0) ; LMULMAX1-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %vec = load <8 x i32>, <8 x i32>* %vp @@ -254,20 +254,20 @@ define void @insert_v8i32_undef_v2i32_6(<8 x i32>* %vp, <2 x i32>* %svp) { ; LMULMAX2-LABEL: insert_v8i32_undef_v2i32_6: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a1) +; LMULMAX2-NEXT: vle32.v v8, (a1) ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vslideup.vi v28, v26, 6 -; LMULMAX2-NEXT: vse32.v v28, (a0) +; LMULMAX2-NEXT: vslideup.vi v10, v8, 6 +; LMULMAX2-NEXT: vse32.v v10, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_v8i32_undef_v2i32_6: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a1) +; LMULMAX1-NEXT: vle32.v v8, (a1) ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vslideup.vi v26, v25, 2 +; LMULMAX1-NEXT: vslideup.vi v9, v8, 2 ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vse32.v v26, (a0) +; LMULMAX1-NEXT: vse32.v v9, (a0) ; LMULMAX1-NEXT: ret %sv = load <2 x i32>, <2 x i32>* %svp %v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> undef, <2 x i32> %sv, i64 6) @@ -279,13 +279,13 @@ define void @insert_v4i16_v2i16_0(<4 x i16>* %vp, <2 x i16>* %svp) { ; CHECK-LABEL: insert_v4i16_v2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v26, (a1) +; CHECK-NEXT: vle16.v v9, (a1) ; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v25, v26, 0 +; CHECK-NEXT: vslideup.vi v8, v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %vp %sv = load <2 x i16>, <2 x i16>* %svp @@ -298,12 +298,12 @@ define void @insert_v4i16_v2i16_2(<4 x i16>* %vp, <2 x i16>* %svp) { ; CHECK-LABEL: insert_v4i16_v2i16_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v26, (a1) +; CHECK-NEXT: vle16.v v9, (a1) ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v25, v26, 2 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vslideup.vi v8, v9, 2 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %vp %sv = load <2 x i16>, <2 x i16>* %svp @@ -317,25 +317,25 @@ define void @insert_v32i1_v8i1_0(<32 x i1>* %vp, <8 x i1>* %svp) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vlm.v v25, (a0) +; LMULMAX2-NEXT: vlm.v v8, (a0) ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX2-NEXT: vlm.v v26, (a1) +; LMULMAX2-NEXT: vlm.v v9, (a1) ; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf4, tu, mu -; LMULMAX2-NEXT: vslideup.vi v25, v26, 0 +; LMULMAX2-NEXT: vslideup.vi v8, v9, 0 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vsm.v v25, (a0) +; LMULMAX2-NEXT: vsm.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_v32i1_v8i1_0: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vlm.v v25, (a0) +; LMULMAX1-NEXT: vlm.v v8, (a0) ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vlm.v v26, (a1) +; LMULMAX1-NEXT: vlm.v v9, (a1) ; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v26, 0 +; LMULMAX1-NEXT: vslideup.vi v8, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vsm.v v25, (a0) +; LMULMAX1-NEXT: vsm.v v8, (a0) ; LMULMAX1-NEXT: ret %v = load <32 x i1>, <32 x i1>* %vp %sv = load <8 x i1>, <8 x i1>* %svp @@ -349,26 +349,26 @@ define void @insert_v32i1_v8i1_16(<32 x i1>* %vp, <8 x i1>* %svp) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vlm.v v25, (a0) +; LMULMAX2-NEXT: vlm.v v8, (a0) ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX2-NEXT: vlm.v v26, (a1) +; LMULMAX2-NEXT: vlm.v v9, (a1) ; LMULMAX2-NEXT: vsetivli zero, 3, e8, mf4, tu, mu -; LMULMAX2-NEXT: vslideup.vi v25, v26, 2 +; LMULMAX2-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vsm.v v25, (a0) +; LMULMAX2-NEXT: vsm.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: insert_v32i1_v8i1_16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: addi a0, a0, 2 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vlm.v v25, (a0) +; LMULMAX1-NEXT: vlm.v v8, (a0) ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vlm.v v26, (a1) +; LMULMAX1-NEXT: vlm.v v9, (a1) ; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, tu, mu -; LMULMAX1-NEXT: vslideup.vi v25, v26, 0 +; LMULMAX1-NEXT: vslideup.vi v8, v9, 0 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vsm.v v25, (a0) +; LMULMAX1-NEXT: vsm.v v8, (a0) ; LMULMAX1-NEXT: ret %v = load <32 x i1>, <32 x i1>* %vp %sv = load <8 x i1>, <8 x i1>* %svp @@ -383,19 +383,19 @@ define void @insert_v8i1_v4i1_0(<8 x i1>* %vp, <4 x i1>* %svp) { ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vlm.v v25, (a1) +; CHECK-NEXT: vlm.v v8, (a1) ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v27, 0 -; CHECK-NEXT: vmv1r.v v0, v25 -; CHECK-NEXT: vmerge.vim v25, v27, 1, v0 +; CHECK-NEXT: vmv.v.i v10, 0 +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %v = load <8 x i1>, <8 x i1>* %vp %sv = load <4 x i1>, <4 x i1>* %svp @@ -410,19 +410,19 @@ define void @insert_v8i1_v4i1_4(<8 x i1>* %vp, <4 x i1>* %svp) { ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vlm.v v25, (a1) +; CHECK-NEXT: vlm.v v8, (a1) ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v27, 0 -; CHECK-NEXT: vmv1r.v v0, v25 -; CHECK-NEXT: vmerge.vim v25, v27, 1, v0 +; CHECK-NEXT: vmv.v.i v10, 0 +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 4 +; CHECK-NEXT: vslideup.vi v9, v8, 4 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %v = load <8 x i1>, <8 x i1>* %vp %sv = load <4 x i1>, <4 x i1>* %svp @@ -435,9 +435,9 @@ define @insert_nxv2i16_v2i16_0( %v, <2 x i1 ; CHECK-LABEL: insert_nxv2i16_v2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 0 +; CHECK-NEXT: vslideup.vi v8, v9, 0 ; CHECK-NEXT: ret %sv = load <2 x i16>, <2 x i16>* %svp %c = call @llvm.experimental.vector.insert.v2i16.nxv2i16( %v, <2 x i16> %sv, i64 0) @@ -448,9 +448,9 @@ define @insert_nxv2i16_v2i16_2( %v, <2 x i1 ; CHECK-LABEL: insert_nxv2i16_v2i16_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vsetivli zero, 6, e16, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 4 +; CHECK-NEXT: vslideup.vi v8, v9, 4 ; CHECK-NEXT: ret %sv = load <2 x i16>, <2 x i16>* %svp %c = call @llvm.experimental.vector.insert.v2i16.nxv2i16( %v, <2 x i16> %sv, i64 4) @@ -461,18 +461,18 @@ define @insert_nxv2i1_v4i1_0( %v, <4 x i1>* % ; CHECK-LABEL: insert_nxv2i1_v4i1_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) +; CHECK-NEXT: vlm.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v27, 0 -; CHECK-NEXT: vmv1r.v v0, v25 -; CHECK-NEXT: vmerge.vim v25, v27, 1, v0 +; CHECK-NEXT: vmv.v.i v10, 0 +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret %sv = load <4 x i1>, <4 x i1>* %svp %c = call @llvm.experimental.vector.insert.v4i1.nxv2i1( %v, <4 x i1> %sv, i64 0) @@ -483,9 +483,9 @@ define @insert_nxv8i1_v4i1_0( %v, <8 x i1>* % ; CHECK-LABEL: insert_nxv8i1_v4i1_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) +; CHECK-NEXT: vlm.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, tu, mu -; CHECK-NEXT: vslideup.vi v0, v25, 0 +; CHECK-NEXT: vslideup.vi v0, v8, 0 ; CHECK-NEXT: ret %sv = load <8 x i1>, <8 x i1>* %svp %c = call @llvm.experimental.vector.insert.v8i1.nxv8i1( %v, <8 x i1> %sv, i64 0) @@ -496,9 +496,9 @@ define @insert_nxv8i1_v8i1_16( %v, <8 x i1>* ; CHECK-LABEL: insert_nxv8i1_v8i1_16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) +; CHECK-NEXT: vlm.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 3, e8, mf8, tu, mu -; CHECK-NEXT: vslideup.vi v0, v25, 2 +; CHECK-NEXT: vslideup.vi v0, v8, 2 ; CHECK-NEXT: ret %sv = load <8 x i1>, <8 x i1>* %svp %c = call @llvm.experimental.vector.insert.v8i1.nxv8i1( %v, <8 x i1> %sv, i64 16) @@ -564,9 +564,9 @@ define void @insert_v2i64_nxv16i64_hi(<2 x i64>* %psv, * %out ; CHECK-NEXT: slli a2, a2, 4 ; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: addi a0, sp, 80 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: addi a2, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll index 55b24cff0801f853e685e2f56c61ca27a4025a74..73b0c63764d5a8af1c37f2e291d5b792826e854b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll @@ -9,24 +9,24 @@ define void @insertelt_v4i64(<4 x i64>* %x, i64 %y) { ; RV32-LABEL: insertelt_v4i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vle64.v v26, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetivli zero, 2, e32, m2, ta, mu -; RV32-NEXT: vmv.v.i v28, 0 -; RV32-NEXT: vslide1up.vx v30, v28, a2 -; RV32-NEXT: vslide1up.vx v28, v30, a1 +; RV32-NEXT: vmv.v.i v10, 0 +; RV32-NEXT: vslide1up.vx v12, v10, a2 +; RV32-NEXT: vslide1up.vx v10, v12, a1 ; RV32-NEXT: vsetivli zero, 4, e64, m2, tu, mu -; RV32-NEXT: vslideup.vi v26, v28, 3 -; RV32-NEXT: vse64.v v26, (a0) +; RV32-NEXT: vslideup.vi v8, v10, 3 +; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v26, (a0) -; RV64-NEXT: vmv.s.x v28, a1 +; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vmv.s.x v10, a1 ; RV64-NEXT: vsetvli zero, zero, e64, m2, tu, mu -; RV64-NEXT: vslideup.vi v26, v28, 3 -; RV64-NEXT: vse64.v v26, (a0) +; RV64-NEXT: vslideup.vi v8, v10, 3 +; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = insertelement <4 x i64> %a, i64 %y, i32 3 @@ -42,29 +42,29 @@ define void @insertelt_v3i64(<3 x i64>* %x, i64 %y) { ; RV32-LABEL: insertelt_v3i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v26, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vmv.v.i v28, 0 +; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vsetivli zero, 2, e64, m2, tu, mu -; RV32-NEXT: vslideup.vi v28, v26, 0 +; RV32-NEXT: vslideup.vi v10, v8, 0 ; RV32-NEXT: lw a3, 16(a0) ; RV32-NEXT: addi a4, a0, 20 ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vlse32.v v26, (a4), zero +; RV32-NEXT: vlse32.v v8, (a4), zero ; RV32-NEXT: vsetvli zero, zero, e32, m1, tu, mu -; RV32-NEXT: vmv.s.x v26, a3 +; RV32-NEXT: vmv.s.x v8, a3 ; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, mu -; RV32-NEXT: vslideup.vi v28, v26, 2 +; RV32-NEXT: vslideup.vi v10, v8, 2 ; RV32-NEXT: vsetivli zero, 2, e32, m2, ta, mu -; RV32-NEXT: vmv.v.i v26, 0 -; RV32-NEXT: vslide1up.vx v30, v26, a2 -; RV32-NEXT: vslide1up.vx v26, v30, a1 +; RV32-NEXT: vmv.v.i v8, 0 +; RV32-NEXT: vslide1up.vx v12, v8, a2 +; RV32-NEXT: vslide1up.vx v8, v12, a1 ; RV32-NEXT: vsetivli zero, 3, e64, m2, tu, mu -; RV32-NEXT: vslideup.vi v28, v26, 2 +; RV32-NEXT: vslideup.vi v10, v8, 2 ; RV32-NEXT: sw a1, 16(a0) ; RV32-NEXT: sw a2, 20(a0) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vse64.v v28, (a0) +; RV32-NEXT: vse64.v v10, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_v3i64: @@ -81,12 +81,12 @@ define void @insertelt_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: insertelt_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmv.s.x v26, a1 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmv.s.x v9, a1 ; CHECK-NEXT: vsetivli zero, 15, e8, m1, tu, mu -; CHECK-NEXT: vslideup.vi v25, v26, 14 +; CHECK-NEXT: vslideup.vi v8, v9, 14 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> %a, i8 %y, i32 14 @@ -99,27 +99,27 @@ define void @insertelt_v32i16(<32 x i16>* %x, i16 %y, i32 %idx) { ; RV32: # %bb.0: ; RV32-NEXT: addi a3, zero, 32 ; RV32-NEXT: vsetvli zero, a3, e16, m4, ta, mu -; RV32-NEXT: vle16.v v28, (a0) -; RV32-NEXT: vmv.s.x v8, a1 +; RV32-NEXT: vle16.v v8, (a0) +; RV32-NEXT: vmv.s.x v12, a1 ; RV32-NEXT: addi a1, a2, 1 ; RV32-NEXT: vsetvli zero, a1, e16, m4, tu, mu -; RV32-NEXT: vslideup.vx v28, v8, a2 +; RV32-NEXT: vslideup.vx v8, v12, a2 ; RV32-NEXT: vsetvli zero, a3, e16, m4, ta, mu -; RV32-NEXT: vse16.v v28, (a0) +; RV32-NEXT: vse16.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_v32i16: ; RV64: # %bb.0: ; RV64-NEXT: addi a3, zero, 32 ; RV64-NEXT: vsetvli zero, a3, e16, m4, ta, mu -; RV64-NEXT: vle16.v v28, (a0) -; RV64-NEXT: vmv.s.x v8, a1 +; RV64-NEXT: vle16.v v8, (a0) +; RV64-NEXT: vmv.s.x v12, a1 ; RV64-NEXT: sext.w a1, a2 ; RV64-NEXT: addi a2, a1, 1 ; RV64-NEXT: vsetvli zero, a2, e16, m4, tu, mu -; RV64-NEXT: vslideup.vx v28, v8, a1 +; RV64-NEXT: vslideup.vx v8, v12, a1 ; RV64-NEXT: vsetvli zero, a3, e16, m4, ta, mu -; RV64-NEXT: vse16.v v28, (a0) +; RV64-NEXT: vse16.v v8, (a0) ; RV64-NEXT: ret %a = load <32 x i16>, <32 x i16>* %x %b = insertelement <32 x i16> %a, i16 %y, i32 %idx @@ -131,26 +131,26 @@ define void @insertelt_v8f32(<8 x float>* %x, float %y, i32 %idx) { ; RV32-LABEL: insertelt_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vle32.v v26, (a0) -; RV32-NEXT: vfmv.s.f v28, fa0 +; RV32-NEXT: vle32.v v8, (a0) +; RV32-NEXT: vfmv.s.f v10, fa0 ; RV32-NEXT: addi a2, a1, 1 ; RV32-NEXT: vsetvli zero, a2, e32, m2, tu, mu -; RV32-NEXT: vslideup.vx v26, v28, a1 +; RV32-NEXT: vslideup.vx v8, v10, a1 ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vse32.v v26, (a0) +; RV32-NEXT: vse32.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV64-NEXT: vle32.v v26, (a0) -; RV64-NEXT: vfmv.s.f v28, fa0 +; RV64-NEXT: vle32.v v8, (a0) +; RV64-NEXT: vfmv.s.f v10, fa0 ; RV64-NEXT: sext.w a1, a1 ; RV64-NEXT: addi a2, a1, 1 ; RV64-NEXT: vsetvli zero, a2, e32, m2, tu, mu -; RV64-NEXT: vslideup.vx v26, v28, a1 +; RV64-NEXT: vslideup.vx v8, v10, a1 ; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV64-NEXT: vse32.v v26, (a0) +; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <8 x float>, <8 x float>* %x %b = insertelement <8 x float> %a, float %y, i32 %idx @@ -162,11 +162,11 @@ define void @insertelt_v8i64_0(<8 x i64>* %x) { ; CHECK-LABEL: insertelt_v8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vle64.v v28, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: addi a1, zero, -1 ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu -; CHECK-NEXT: vmv.s.x v28, a1 -; CHECK-NEXT: vse64.v v28, (a0) +; CHECK-NEXT: vmv.s.x v8, a1 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %b = insertelement <8 x i64> %a, i64 -1, i32 0 @@ -178,28 +178,28 @@ define void @insertelt_v8i64(<8 x i64>* %x, i32 %idx) { ; RV32-LABEL: insertelt_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vle64.v v28, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a2, zero, -1 -; RV32-NEXT: vmv.s.x v8, a2 +; RV32-NEXT: vmv.s.x v12, a2 ; RV32-NEXT: addi a2, a1, 1 ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu -; RV32-NEXT: vslideup.vx v28, v8, a1 +; RV32-NEXT: vslideup.vx v8, v12, a1 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vse64.v v28, (a0) +; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v28, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: addi a2, zero, -1 -; RV64-NEXT: vmv.s.x v8, a2 +; RV64-NEXT: vmv.s.x v12, a2 ; RV64-NEXT: sext.w a1, a1 ; RV64-NEXT: addi a2, a1, 1 ; RV64-NEXT: vsetvli zero, a2, e64, m4, tu, mu -; RV64-NEXT: vslideup.vx v28, v8, a1 +; RV64-NEXT: vslideup.vx v8, v12, a1 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vse64.v v28, (a0) +; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %b = insertelement <8 x i64> %a, i64 -1, i32 %idx @@ -211,11 +211,11 @@ define void @insertelt_c6_v8i64_0(<8 x i64>* %x) { ; CHECK-LABEL: insertelt_c6_v8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vle64.v v28, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: addi a1, zero, 6 ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu -; CHECK-NEXT: vmv.s.x v28, a1 -; CHECK-NEXT: vse64.v v28, (a0) +; CHECK-NEXT: vmv.s.x v8, a1 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %b = insertelement <8 x i64> %a, i64 6, i32 0 @@ -227,28 +227,28 @@ define void @insertelt_c6_v8i64(<8 x i64>* %x, i32 %idx) { ; RV32-LABEL: insertelt_c6_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vle64.v v28, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a2, zero, 6 -; RV32-NEXT: vmv.s.x v8, a2 +; RV32-NEXT: vmv.s.x v12, a2 ; RV32-NEXT: addi a2, a1, 1 ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu -; RV32-NEXT: vslideup.vx v28, v8, a1 +; RV32-NEXT: vslideup.vx v8, v12, a1 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vse64.v v28, (a0) +; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: insertelt_c6_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v28, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: addi a2, zero, 6 -; RV64-NEXT: vmv.s.x v8, a2 +; RV64-NEXT: vmv.s.x v12, a2 ; RV64-NEXT: sext.w a1, a1 ; RV64-NEXT: addi a2, a1, 1 ; RV64-NEXT: vsetvli zero, a2, e64, m4, tu, mu -; RV64-NEXT: vslideup.vx v28, v8, a1 +; RV64-NEXT: vslideup.vx v8, v12, a1 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vse64.v v28, (a0) +; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %b = insertelement <8 x i64> %a, i64 6, i32 %idx @@ -262,14 +262,14 @@ define void @insertelt_c6_v8i64_0_add(<8 x i64>* %x, <8 x i64>* %y) { ; CHECK-LABEL: insertelt_c6_v8i64_0_add: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vle64.v v28, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: addi a2, zero, 6 ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu -; CHECK-NEXT: vmv.s.x v28, a2 +; CHECK-NEXT: vmv.s.x v8, a2 ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vadd.vv v28, v28, v8 -; CHECK-NEXT: vse64.v v28, (a0) +; CHECK-NEXT: vle64.v v12, (a1) +; CHECK-NEXT: vadd.vv v8, v8, v12 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %b = insertelement <8 x i64> %a, i64 6, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll index 714a2afdf58c77e8c0995a7b29e88074c2ac8d37..75e5ac705ca1c5e393a69877bb4b3327e4a88176 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll @@ -6,8 +6,8 @@ define void @buildvec_vid_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: buildvec_vid_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret store <16 x i8> , <16 x i8>* %x ret void @@ -17,8 +17,8 @@ define void @buildvec_vid_undefelts_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: buildvec_vid_undefelts_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret store <16 x i8> , <16 x i8>* %x ret void @@ -31,8 +31,8 @@ define void @buildvec_notquite_vid_v16i8(<16 x i8>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI2_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI2_0) ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a1) +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret store <16 x i8> , <16 x i8>* %x ret void @@ -42,9 +42,9 @@ define void @buildvec_vid_plus_imm_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: buildvec_vid_plus_imm_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vadd.vi v25, v25, 2 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vadd.vi v8, v8, 2 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret store <16 x i8> , <16 x i8>* %x ret void @@ -54,10 +54,10 @@ define void @buildvec_vid_mpy_imm_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: buildvec_vid_mpy_imm_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vid.v v25 +; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: addi a1, zero, 3 -; CHECK-NEXT: vmul.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vmul.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret store <16 x i8> , <16 x i8>* %x ret void @@ -67,12 +67,12 @@ define void @buildvec_vid_step2_add0_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8> ; CHECK-LABEL: buildvec_vid_step2_add0_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vadd.vv v25, v25, v25 -; CHECK-NEXT: vse8.v v25, (a0) -; CHECK-NEXT: vse8.v v25, (a1) -; CHECK-NEXT: vse8.v v25, (a2) -; CHECK-NEXT: vse8.v v25, (a3) +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: vse8.v v8, (a1) +; CHECK-NEXT: vse8.v v8, (a2) +; CHECK-NEXT: vse8.v v8, (a3) ; CHECK-NEXT: ret store <4 x i8> , <4 x i8>* %z0 store <4 x i8> , <4 x i8>* %z1 @@ -85,13 +85,13 @@ define void @buildvec_vid_step2_add1_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8> ; CHECK-LABEL: buildvec_vid_step2_add1_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vadd.vv v25, v25, v25 -; CHECK-NEXT: vadd.vi v25, v25, 1 -; CHECK-NEXT: vse8.v v25, (a0) -; CHECK-NEXT: vse8.v v25, (a1) -; CHECK-NEXT: vse8.v v25, (a2) -; CHECK-NEXT: vse8.v v25, (a3) +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: vadd.vi v8, v8, 1 +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: vse8.v v8, (a1) +; CHECK-NEXT: vse8.v v8, (a2) +; CHECK-NEXT: vse8.v v8, (a3) ; CHECK-NEXT: ret store <4 x i8> , <4 x i8>* %z0 store <4 x i8> , <4 x i8>* %z1 @@ -107,12 +107,12 @@ define void @buildvec_vid_stepn1_add0_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x ; CHECK-LABEL: buildvec_vid_stepn1_add0_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vi v25, v25, 0 -; CHECK-NEXT: vse8.v v25, (a0) -; CHECK-NEXT: vse8.v v25, (a1) -; CHECK-NEXT: vse8.v v25, (a2) -; CHECK-NEXT: vse8.v v25, (a3) +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vrsub.vi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: vse8.v v8, (a1) +; CHECK-NEXT: vse8.v v8, (a2) +; CHECK-NEXT: vse8.v v8, (a3) ; CHECK-NEXT: ret i8>* %z2, <4 x i8>* %z3) { store <4 x i8> , <4 x i8>* %z0 @@ -126,13 +126,13 @@ define void @buildvec_vid_stepn2_add0_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8 ; CHECK-LABEL: buildvec_vid_stepn2_add0_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vadd.vv v25, v25, v25 -; CHECK-NEXT: vrsub.vi v25, v25, 0 -; CHECK-NEXT: vse8.v v25, (a0) -; CHECK-NEXT: vse8.v v25, (a1) -; CHECK-NEXT: vse8.v v25, (a2) -; CHECK-NEXT: vse8.v v25, (a3) +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: vrsub.vi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: vse8.v v8, (a1) +; CHECK-NEXT: vse8.v v8, (a2) +; CHECK-NEXT: vse8.v v8, (a3) ; CHECK-NEXT: ret store <4 x i8> , <4 x i8>* %z0 store <4 x i8> , <4 x i8>* %z1 @@ -145,10 +145,10 @@ define void @buildvec_vid_stepn2_add3_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8 ; CHECK-LABEL: buildvec_vid_stepn2_add3_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vadd.vv v25, v25, v25 -; CHECK-NEXT: vrsub.vi v25, v25, 3 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: vrsub.vi v8, v8, 3 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret store <4 x i8> , <4 x i8>* %z0 ret void @@ -158,11 +158,11 @@ define void @buildvec_vid_stepn3_add3_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8 ; CHECK-LABEL: buildvec_vid_stepn3_add3_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 3 -; CHECK-NEXT: vid.v v26 +; CHECK-NEXT: vmv.v.i v8, 3 +; CHECK-NEXT: vid.v v9 ; CHECK-NEXT: addi a1, zero, -3 -; CHECK-NEXT: vmadd.vx v26, a1, v25 -; CHECK-NEXT: vse8.v v26, (a0) +; CHECK-NEXT: vmadd.vx v9, a1, v8 +; CHECK-NEXT: vse8.v v9, (a0) ; CHECK-NEXT: ret store <4 x i8> , <4 x i8>* %z0 ret void @@ -172,14 +172,14 @@ define void @buildvec_vid_stepn3_addn3_v4i32(<4 x i32>* %z0, <4 x i32>* %z1, <4 ; CHECK-LABEL: buildvec_vid_stepn3_addn3_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -3 -; CHECK-NEXT: vid.v v26 +; CHECK-NEXT: vmv.v.i v8, -3 +; CHECK-NEXT: vid.v v9 ; CHECK-NEXT: addi a4, zero, -3 -; CHECK-NEXT: vmadd.vx v26, a4, v25 -; CHECK-NEXT: vse32.v v26, (a0) -; CHECK-NEXT: vse32.v v26, (a1) -; CHECK-NEXT: vse32.v v26, (a2) -; CHECK-NEXT: vse32.v v26, (a3) +; CHECK-NEXT: vmadd.vx v9, a4, v8 +; CHECK-NEXT: vse32.v v9, (a0) +; CHECK-NEXT: vse32.v v9, (a1) +; CHECK-NEXT: vse32.v v9, (a2) +; CHECK-NEXT: vse32.v v9, (a3) ; CHECK-NEXT: ret store <4 x i32> , <4 x i32>* %z0 store <4 x i32> , <4 x i32>* %z1 @@ -194,10 +194,10 @@ define <4 x i64> @buildvec_vid_step1_add0_v4i64() { ; RV32: # %bb.0: ; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vmv.s.x v25, a0 +; RV32-NEXT: vmv.s.x v9, a0 ; RV32-NEXT: vmv.v.i v8, 0 ; RV32-NEXT: vsetivli zero, 3, e32, m1, tu, mu -; RV32-NEXT: vslideup.vi v8, v25, 2 +; RV32-NEXT: vslideup.vi v8, v9, 2 ; RV32-NEXT: lui a0, %hi(.LCPI12_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI12_0) ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu @@ -218,10 +218,10 @@ define <4 x i64> @buildvec_vid_step2_add0_v4i64() { ; RV32: # %bb.0: ; RV32-NEXT: addi a0, zero, 2 ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vmv.s.x v25, a0 +; RV32-NEXT: vmv.s.x v9, a0 ; RV32-NEXT: vmv.v.i v8, 0 ; RV32-NEXT: vsetivli zero, 3, e32, m1, tu, mu -; RV32-NEXT: vslideup.vi v8, v25, 2 +; RV32-NEXT: vslideup.vi v8, v9, 2 ; RV32-NEXT: lui a0, %hi(.LCPI13_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI13_0) ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu @@ -231,8 +231,8 @@ define <4 x i64> @buildvec_vid_step2_add0_v4i64() { ; RV64-LABEL: buildvec_vid_step2_add0_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vid.v v25 -; RV64-NEXT: vadd.vv v8, v25, v25 +; RV64-NEXT: vid.v v8 +; RV64-NEXT: vadd.vv v8, v8, v8 ; RV64-NEXT: vadd.vi v9, v8, 4 ; RV64-NEXT: ret ret <4 x i64> @@ -244,29 +244,29 @@ define void @buildvec_no_vid_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8>* %z2, < ; RV32-NEXT: lui a6, %hi(.LCPI14_0) ; RV32-NEXT: addi a6, a6, %lo(.LCPI14_0) ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; RV32-NEXT: vle8.v v25, (a6) +; RV32-NEXT: vle8.v v8, (a6) ; RV32-NEXT: lui a6, %hi(.LCPI14_1) ; RV32-NEXT: addi a6, a6, %lo(.LCPI14_1) -; RV32-NEXT: vle8.v v26, (a6) -; RV32-NEXT: vse8.v v25, (a0) -; RV32-NEXT: vse8.v v26, (a1) +; RV32-NEXT: vle8.v v9, (a6) +; RV32-NEXT: vse8.v v8, (a0) +; RV32-NEXT: vse8.v v9, (a1) ; RV32-NEXT: lui a0, 1 ; RV32-NEXT: addi a0, a0, -2048 ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v8, a0 ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; RV32-NEXT: vse8.v v25, (a2) +; RV32-NEXT: vse8.v v8, (a2) ; RV32-NEXT: addi a0, zero, 2047 ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v8, a0 ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; RV32-NEXT: lui a0, %hi(.LCPI14_2) ; RV32-NEXT: addi a0, a0, %lo(.LCPI14_2) -; RV32-NEXT: vle8.v v26, (a0) -; RV32-NEXT: vse8.v v25, (a3) -; RV32-NEXT: vmv.v.i v25, -2 -; RV32-NEXT: vse8.v v25, (a4) -; RV32-NEXT: vse8.v v26, (a5) +; RV32-NEXT: vle8.v v9, (a0) +; RV32-NEXT: vse8.v v8, (a3) +; RV32-NEXT: vmv.v.i v8, -2 +; RV32-NEXT: vse8.v v8, (a4) +; RV32-NEXT: vse8.v v9, (a5) ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_no_vid_v4i8: @@ -274,29 +274,29 @@ define void @buildvec_no_vid_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8>* %z2, < ; RV64-NEXT: lui a6, %hi(.LCPI14_0) ; RV64-NEXT: addi a6, a6, %lo(.LCPI14_0) ; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; RV64-NEXT: vle8.v v25, (a6) +; RV64-NEXT: vle8.v v8, (a6) ; RV64-NEXT: lui a6, %hi(.LCPI14_1) ; RV64-NEXT: addi a6, a6, %lo(.LCPI14_1) -; RV64-NEXT: vle8.v v26, (a6) -; RV64-NEXT: vse8.v v25, (a0) -; RV64-NEXT: vse8.v v26, (a1) +; RV64-NEXT: vle8.v v9, (a6) +; RV64-NEXT: vse8.v v8, (a0) +; RV64-NEXT: vse8.v v9, (a1) ; RV64-NEXT: lui a0, 1 ; RV64-NEXT: addiw a0, a0, -2048 ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v8, a0 ; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; RV64-NEXT: vse8.v v25, (a2) +; RV64-NEXT: vse8.v v8, (a2) ; RV64-NEXT: addi a0, zero, 2047 ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v8, a0 ; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; RV64-NEXT: lui a0, %hi(.LCPI14_2) ; RV64-NEXT: addi a0, a0, %lo(.LCPI14_2) -; RV64-NEXT: vle8.v v26, (a0) -; RV64-NEXT: vse8.v v25, (a3) -; RV64-NEXT: vmv.v.i v25, -2 -; RV64-NEXT: vse8.v v25, (a4) -; RV64-NEXT: vse8.v v26, (a5) +; RV64-NEXT: vle8.v v9, (a0) +; RV64-NEXT: vse8.v v8, (a3) +; RV64-NEXT: vmv.v.i v8, -2 +; RV64-NEXT: vse8.v v8, (a4) +; RV64-NEXT: vse8.v v9, (a5) ; RV64-NEXT: ret store <4 x i8> , <4 x i8>* %z0 store <4 x i8> , <4 x i8>* %z1 @@ -311,12 +311,12 @@ define void @buildvec_dominant0_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: buildvec_dominant0_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, zero -; CHECK-NEXT: vmv.v.i v26, 8 +; CHECK-NEXT: vmv.s.x v8, zero +; CHECK-NEXT: vmv.v.i v9, 8 ; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 3 +; CHECK-NEXT: vslideup.vi v9, v8, 3 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vse16.v v26, (a0) +; CHECK-NEXT: vse16.v v9, (a0) ; CHECK-NEXT: ret store <8 x i16> , <8 x i16>* %x ret void @@ -326,8 +326,8 @@ define void @buildvec_dominant1_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: buildvec_dominant1_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 8 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vmv.v.i v8, 8 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret store <8 x i16> , <8 x i16>* %x ret void @@ -345,8 +345,8 @@ define void @buildvec_dominant1_v2i8(<2 x i8>* %x) { ; CHECK-LABEL: buildvec_dominant1_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vmv.v.i v8, -1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret store <2 x i8> , <2 x i8>* %x ret void @@ -356,9 +356,9 @@ define void @buildvec_dominant2_v2i8(<2 x i8>* %x) { ; CHECK-LABEL: buildvec_dominant2_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vi v25, v25, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vrsub.vi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret store <2 x i8> , <2 x i8>* %x ret void @@ -370,14 +370,14 @@ define void @buildvec_dominant0_v2i32(<2 x i64>* %x) { ; RV32-NEXT: lui a1, %hi(.LCPI20_0) ; RV32-NEXT: addi a1, a1, %lo(.LCPI20_0) ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vle32.v v25, (a1) -; RV32-NEXT: vse32.v v25, (a0) +; RV32-NEXT: vle32.v v8, (a1) +; RV32-NEXT: vse32.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_dominant0_v2i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, -1 +; RV64-NEXT: vmv.v.i v8, -1 ; RV64-NEXT: lui a1, 3641 ; RV64-NEXT: addiw a1, a1, -455 ; RV64-NEXT: slli a1, a1, 12 @@ -387,8 +387,8 @@ define void @buildvec_dominant0_v2i32(<2 x i64>* %x) { ; RV64-NEXT: slli a1, a1, 13 ; RV64-NEXT: addi a1, a1, -910 ; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; RV64-NEXT: vmv.s.x v25, a1 -; RV64-NEXT: vse64.v v25, (a0) +; RV64-NEXT: vmv.s.x v8, a1 +; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: ret store <2 x i64> , <2 x i64>* %x ret void @@ -400,8 +400,8 @@ define void @buildvec_dominant1_optsize_v2i32(<2 x i64>* %x) optsize { ; RV32-NEXT: lui a1, %hi(.LCPI21_0) ; RV32-NEXT: addi a1, a1, %lo(.LCPI21_0) ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vle32.v v25, (a1) -; RV32-NEXT: vse32.v v25, (a0) +; RV32-NEXT: vle32.v v8, (a1) +; RV32-NEXT: vse32.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_dominant1_optsize_v2i32: @@ -409,8 +409,8 @@ define void @buildvec_dominant1_optsize_v2i32(<2 x i64>* %x) optsize { ; RV64-NEXT: lui a1, %hi(.LCPI21_0) ; RV64-NEXT: addi a1, a1, %lo(.LCPI21_0) ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a1) -; RV64-NEXT: vse64.v v25, (a0) +; RV64-NEXT: vle64.v v8, (a1) +; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: ret store <2 x i64> , <2 x i64>* %x ret void @@ -421,9 +421,9 @@ define void @buildvec_seq_v8i8_v4i16(<8 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 513 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret store <8 x i8> , <8 x i8>* %x ret void @@ -435,9 +435,9 @@ define void @buildvec_seq_v8i8_v2i32(<8 x i8>* %x) { ; RV32-NEXT: lui a1, 48 ; RV32-NEXT: addi a1, a1, 513 ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vmv.v.x v25, a1 +; RV32-NEXT: vmv.v.x v8, a1 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vse8.v v25, (a0) +; RV32-NEXT: vse8.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_seq_v8i8_v2i32: @@ -445,9 +445,9 @@ define void @buildvec_seq_v8i8_v2i32(<8 x i8>* %x) { ; RV64-NEXT: lui a1, 48 ; RV64-NEXT: addiw a1, a1, 513 ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vmv.v.x v25, a1 +; RV64-NEXT: vmv.v.x v8, a1 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vse8.v v25, (a0) +; RV64-NEXT: vse8.v v8, (a0) ; RV64-NEXT: ret store <8 x i8> , <8 x i8>* %x ret void @@ -459,8 +459,8 @@ define void @buildvec_seq_v16i8_v2i64(<16 x i8>* %x) { ; RV32-NEXT: lui a1, %hi(.LCPI24_0) ; RV32-NEXT: addi a1, a1, %lo(.LCPI24_0) ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV32-NEXT: vle8.v v25, (a1) -; RV32-NEXT: vse8.v v25, (a0) +; RV32-NEXT: vle8.v v8, (a1) +; RV32-NEXT: vse8.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_seq_v16i8_v2i64: @@ -472,9 +472,9 @@ define void @buildvec_seq_v16i8_v2i64(<16 x i8>* %x) { ; RV64-NEXT: slli a1, a1, 16 ; RV64-NEXT: addi a1, a1, 513 ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a1 +; RV64-NEXT: vmv.v.x v8, a1 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV64-NEXT: vse8.v v25, (a0) +; RV64-NEXT: vse8.v v8, (a0) ; RV64-NEXT: ret store <16 x i8> , <16 x i8>* %x ret void @@ -486,9 +486,9 @@ define void @buildvec_seq2_v16i8_v2i64(<16 x i8>* %x) { ; RV32-NEXT: lui a1, 528432 ; RV32-NEXT: addi a1, a1, 513 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a1 +; RV32-NEXT: vmv.v.x v8, a1 ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV32-NEXT: vse8.v v25, (a0) +; RV32-NEXT: vse8.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_seq2_v16i8_v2i64: @@ -496,9 +496,9 @@ define void @buildvec_seq2_v16i8_v2i64(<16 x i8>* %x) { ; RV64-NEXT: lui a1, 528432 ; RV64-NEXT: addiw a1, a1, 513 ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a1 +; RV64-NEXT: vmv.v.x v8, a1 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV64-NEXT: vse8.v v25, (a0) +; RV64-NEXT: vse8.v v8, (a0) ; RV64-NEXT: ret store <16 x i8> , <16 x i8>* %x ret void @@ -513,14 +513,14 @@ define void @buildvec_seq_v9i8(<9 x i8>* %x) { ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vmv.s.x v0, a1 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmv.v.i v25, 2 -; RV32-NEXT: vmerge.vim v25, v25, 1, v0 +; RV32-NEXT: vmv.v.i v8, 2 +; RV32-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-NEXT: addi a1, zero, 36 ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vmv.s.x v0, a1 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmerge.vim v25, v25, 3, v0 -; RV32-NEXT: vse8.v v25, (a0) +; RV32-NEXT: vmerge.vim v8, v8, 3, v0 +; RV32-NEXT: vse8.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: buildvec_seq_v9i8: @@ -544,9 +544,9 @@ define void @buildvec_seq_v4i16_v2i32(<4 x i16>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, -127 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret store <4 x i16> , <4 x i16>* %x ret void @@ -556,25 +556,25 @@ define void @buildvec_vid_step1o2_v4i32(<4 x i32>* %z0, <4 x i32>* %z1, <4 x i32 ; CHECK-LABEL: buildvec_vid_step1o2_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vsrl.vi v25, v25, 1 -; CHECK-NEXT: vse32.v v25, (a0) -; CHECK-NEXT: vse32.v v25, (a1) -; CHECK-NEXT: vse32.v v25, (a2) -; CHECK-NEXT: vse32.v v25, (a3) -; CHECK-NEXT: vse32.v v25, (a4) -; CHECK-NEXT: vmv.s.x v25, zero -; CHECK-NEXT: vmv.v.i v26, 1 +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vsrl.vi v8, v8, 1 +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: vse32.v v8, (a1) +; CHECK-NEXT: vse32.v v8, (a2) +; CHECK-NEXT: vse32.v v8, (a3) +; CHECK-NEXT: vse32.v v8, (a4) +; CHECK-NEXT: vmv.s.x v8, zero +; CHECK-NEXT: vmv.v.i v9, 1 ; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 1 +; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vse32.v v26, (a5) +; CHECK-NEXT: vse32.v v9, (a5) ; CHECK-NEXT: addi a0, zero, 1 -; CHECK-NEXT: vmv.s.x v25, a0 -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 3 -; CHECK-NEXT: vse32.v v26, (a6) +; CHECK-NEXT: vslideup.vi v9, v8, 3 +; CHECK-NEXT: vse32.v v9, (a6) ; CHECK-NEXT: ret store <4 x i32> , <4 x i32>* %z0 store <4 x i32> , <4 x i32>* %z1 @@ -592,27 +592,27 @@ define void @buildvec_vid_step1o2_add3_v4i16(<4 x i16>* %z0, <4 x i16>* %z1, <4 ; CHECK-LABEL: buildvec_vid_step1o2_add3_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vsrl.vi v25, v25, 1 -; CHECK-NEXT: vadd.vi v25, v25, 3 -; CHECK-NEXT: vse16.v v25, (a0) -; CHECK-NEXT: vse16.v v25, (a1) -; CHECK-NEXT: vse16.v v25, (a2) -; CHECK-NEXT: vse16.v v25, (a3) -; CHECK-NEXT: vse16.v v25, (a4) +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vsrl.vi v8, v8, 1 +; CHECK-NEXT: vadd.vi v8, v8, 3 +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: vse16.v v8, (a1) +; CHECK-NEXT: vse16.v v8, (a2) +; CHECK-NEXT: vse16.v v8, (a3) +; CHECK-NEXT: vse16.v v8, (a4) ; CHECK-NEXT: addi a0, zero, 3 -; CHECK-NEXT: vmv.s.x v25, a0 -; CHECK-NEXT: vmv.v.i v26, 4 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v9, 4 ; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 1 +; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vse16.v v26, (a5) +; CHECK-NEXT: vse16.v v9, (a5) ; CHECK-NEXT: addi a0, zero, 4 -; CHECK-NEXT: vmv.s.x v25, a0 -; CHECK-NEXT: vmv.v.i v26, 3 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v9, 3 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 3 -; CHECK-NEXT: vse16.v v26, (a6) +; CHECK-NEXT: vslideup.vi v9, v8, 3 +; CHECK-NEXT: vse16.v v9, (a6) ; CHECK-NEXT: ret store <4 x i16> , <4 x i16>* %z0 store <4 x i16> , <4 x i16>* %z1 @@ -630,10 +630,10 @@ define void @buildvec_vid_stepn1o4_addn5_v8i8(<8 x i8>* %z0) { ; CHECK-LABEL: buildvec_vid_stepn1o4_addn5_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vsrl.vi v25, v25, 2 -; CHECK-NEXT: vrsub.vi v25, v25, -5 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vsrl.vi v8, v8, 2 +; CHECK-NEXT: vrsub.vi v8, v8, -5 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret store <8 x i8> , <8 x i8>* %z0 ret void diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll index 9b2e93cee0c58eca749bfb132efa0b40c4f93d1f..04a14674809150bd8d5d31647b9f5afa65812c63 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll @@ -10,10 +10,10 @@ define void @sext_v4i8_v4i32(<4 x i8>* %x, <4 x i32>* %z) { ; CHECK-LABEL: sext_v4i8_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v26, v25 -; CHECK-NEXT: vse32.v v26, (a1) +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vse32.v v9, (a1) ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %b = sext <4 x i8> %a to <4 x i32> @@ -25,10 +25,10 @@ define void @zext_v4i8_v4i32(<4 x i8>* %x, <4 x i32>* %z) { ; CHECK-LABEL: zext_v4i8_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v26, v25 -; CHECK-NEXT: vse32.v v26, (a1) +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vse32.v v9, (a1) ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %b = zext <4 x i8> %a to <4 x i32> @@ -40,33 +40,33 @@ define void @sext_v8i8_v8i32(<8 x i8>* %x, <8 x i32>* %z) { ; LMULMAX8-LABEL: sext_v8i8_v8i32: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX8-NEXT: vle8.v v25, (a0) +; LMULMAX8-NEXT: vle8.v v8, (a0) ; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; LMULMAX8-NEXT: vsext.vf4 v26, v25 -; LMULMAX8-NEXT: vse32.v v26, (a1) +; LMULMAX8-NEXT: vsext.vf4 v10, v8 +; LMULMAX8-NEXT: vse32.v v10, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: sext_v8i8_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX2-NEXT: vle8.v v25, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) ; LMULMAX2-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; LMULMAX2-NEXT: vsext.vf4 v26, v25 -; LMULMAX2-NEXT: vse32.v v26, (a1) +; LMULMAX2-NEXT: vsext.vf4 v10, v8 +; LMULMAX2-NEXT: vse32.v v10, (a1) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: sext_v8i8_v8i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vle8.v v25, (a0) +; LMULMAX1-NEXT: vle8.v v8, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v26, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v9, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v27, v26 -; LMULMAX1-NEXT: vsext.vf4 v26, v25 +; LMULMAX1-NEXT: vsext.vf4 v10, v9 +; LMULMAX1-NEXT: vsext.vf4 v9, v8 ; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse32.v v27, (a0) -; LMULMAX1-NEXT: vse32.v v26, (a1) +; LMULMAX1-NEXT: vse32.v v10, (a0) +; LMULMAX1-NEXT: vse32.v v9, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = sext <8 x i8> %a to <8 x i32> @@ -79,83 +79,83 @@ define void @sext_v32i8_v32i32(<32 x i8>* %x, <32 x i32>* %z) { ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: addi a2, zero, 32 ; LMULMAX8-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX8-NEXT: vle8.v v26, (a0) +; LMULMAX8-NEXT: vle8.v v8, (a0) ; LMULMAX8-NEXT: vsetvli zero, zero, e32, m8, ta, mu -; LMULMAX8-NEXT: vsext.vf4 v8, v26 -; LMULMAX8-NEXT: vse32.v v8, (a1) +; LMULMAX8-NEXT: vsext.vf4 v16, v8 +; LMULMAX8-NEXT: vse32.v v16, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: sext_v32i8_v32i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) ; LMULMAX2-NEXT: vsetivli zero, 8, e8, m1, ta, mu -; LMULMAX2-NEXT: vslidedown.vi v25, v26, 8 +; LMULMAX2-NEXT: vslidedown.vi v10, v8, 8 ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vsext.vf4 v28, v25 +; LMULMAX2-NEXT: vsext.vf4 v12, v10 ; LMULMAX2-NEXT: vsetivli zero, 16, e8, m2, ta, mu -; LMULMAX2-NEXT: vslidedown.vi v30, v26, 16 +; LMULMAX2-NEXT: vslidedown.vi v10, v8, 16 ; LMULMAX2-NEXT: vsetivli zero, 8, e8, m1, ta, mu -; LMULMAX2-NEXT: vslidedown.vi v25, v30, 8 +; LMULMAX2-NEXT: vslidedown.vi v14, v10, 8 ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vsext.vf4 v8, v25 -; LMULMAX2-NEXT: vsext.vf4 v10, v26 -; LMULMAX2-NEXT: vsext.vf4 v26, v30 +; LMULMAX2-NEXT: vsext.vf4 v16, v14 +; LMULMAX2-NEXT: vsext.vf4 v14, v8 +; LMULMAX2-NEXT: vsext.vf4 v8, v10 ; LMULMAX2-NEXT: addi a0, a1, 64 -; LMULMAX2-NEXT: vse32.v v26, (a0) -; LMULMAX2-NEXT: vse32.v v10, (a1) -; LMULMAX2-NEXT: addi a0, a1, 96 ; LMULMAX2-NEXT: vse32.v v8, (a0) +; LMULMAX2-NEXT: vse32.v v14, (a1) +; LMULMAX2-NEXT: addi a0, a1, 96 +; LMULMAX2-NEXT: vse32.v v16, (a0) ; LMULMAX2-NEXT: addi a0, a1, 32 -; LMULMAX2-NEXT: vse32.v v28, (a0) +; LMULMAX2-NEXT: vse32.v v12, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: sext_v32i8_v32i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: addi a2, a0, 16 -; LMULMAX1-NEXT: vle8.v v25, (a2) -; LMULMAX1-NEXT: vle8.v v26, (a0) +; LMULMAX1-NEXT: vle8.v v8, (a2) +; LMULMAX1-NEXT: vle8.v v9, (a0) ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 4 +; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v28, v27 +; LMULMAX1-NEXT: vsext.vf4 v11, v10 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v27, v25, 8 +; LMULMAX1-NEXT: vslidedown.vi v10, v8, 8 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v29, v27, 4 +; LMULMAX1-NEXT: vslidedown.vi v12, v10, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v30, v29 +; LMULMAX1-NEXT: vsext.vf4 v13, v12 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v29, v26, 4 +; LMULMAX1-NEXT: vslidedown.vi v12, v9, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v31, v29 +; LMULMAX1-NEXT: vsext.vf4 v14, v12 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v29, v26, 8 +; LMULMAX1-NEXT: vslidedown.vi v12, v9, 8 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu -; LMULMAX1-NEXT: vslidedown.vi v8, v29, 4 +; LMULMAX1-NEXT: vslidedown.vi v15, v12, 4 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vsext.vf4 v9, v8 -; LMULMAX1-NEXT: vsext.vf4 v8, v27 -; LMULMAX1-NEXT: vsext.vf4 v27, v29 -; LMULMAX1-NEXT: vsext.vf4 v29, v25 -; LMULMAX1-NEXT: vsext.vf4 v25, v26 +; LMULMAX1-NEXT: vsext.vf4 v16, v15 +; LMULMAX1-NEXT: vsext.vf4 v15, v10 +; LMULMAX1-NEXT: vsext.vf4 v10, v12 +; LMULMAX1-NEXT: vsext.vf4 v12, v8 +; LMULMAX1-NEXT: vsext.vf4 v8, v9 ; LMULMAX1-NEXT: addi a0, a1, 32 -; LMULMAX1-NEXT: vse32.v v27, (a0) -; LMULMAX1-NEXT: vse32.v v25, (a1) +; LMULMAX1-NEXT: vse32.v v10, (a0) +; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a1, 96 -; LMULMAX1-NEXT: vse32.v v8, (a0) +; LMULMAX1-NEXT: vse32.v v15, (a0) ; LMULMAX1-NEXT: addi a0, a1, 64 -; LMULMAX1-NEXT: vse32.v v29, (a0) +; LMULMAX1-NEXT: vse32.v v12, (a0) ; LMULMAX1-NEXT: addi a0, a1, 48 -; LMULMAX1-NEXT: vse32.v v9, (a0) +; LMULMAX1-NEXT: vse32.v v16, (a0) ; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse32.v v31, (a0) +; LMULMAX1-NEXT: vse32.v v14, (a0) ; LMULMAX1-NEXT: addi a0, a1, 112 -; LMULMAX1-NEXT: vse32.v v30, (a0) +; LMULMAX1-NEXT: vse32.v v13, (a0) ; LMULMAX1-NEXT: addi a0, a1, 80 -; LMULMAX1-NEXT: vse32.v v28, (a0) +; LMULMAX1-NEXT: vse32.v v11, (a0) ; LMULMAX1-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = sext <32 x i8> %a to <32 x i32> @@ -167,12 +167,12 @@ define void @trunc_v4i8_v4i32(<4 x i32>* %x, <4 x i8>* %z) { ; CHECK-LABEL: trunc_v4i8_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 -; CHECK-NEXT: vse8.v v25, (a1) +; CHECK-NEXT: vnsrl.wi v8, v8, 0 +; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = trunc <4 x i32> %a to <4 x i8> @@ -184,46 +184,46 @@ define void @trunc_v8i8_v8i32(<8 x i32>* %x, <8 x i8>* %z) { ; LMULMAX8-LABEL: trunc_v8i8_v8i32: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX8-NEXT: vle32.v v26, (a0) +; LMULMAX8-NEXT: vle32.v v8, (a0) ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; LMULMAX8-NEXT: vnsrl.wi v25, v26, 0 +; LMULMAX8-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX8-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; LMULMAX8-NEXT: vnsrl.wi v25, v25, 0 -; LMULMAX8-NEXT: vse8.v v25, (a1) +; LMULMAX8-NEXT: vnsrl.wi v8, v10, 0 +; LMULMAX8-NEXT: vse8.v v8, (a1) ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: trunc_v8i8_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) ; LMULMAX2-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; LMULMAX2-NEXT: vnsrl.wi v25, v26, 0 +; LMULMAX2-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX2-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; LMULMAX2-NEXT: vnsrl.wi v25, v25, 0 -; LMULMAX2-NEXT: vse8.v v25, (a1) +; LMULMAX2-NEXT: vnsrl.wi v8, v10, 0 +; LMULMAX2-NEXT: vse8.v v8, (a1) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: trunc_v8i8_v8i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vle32.v v25, (a0) +; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vle32.v v26, (a0) +; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; LMULMAX1-NEXT: vmv.v.i v27, 0 +; LMULMAX1-NEXT: vmv.v.i v10, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v27, v25, 0 +; LMULMAX1-NEXT: vslideup.vi v10, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v26, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; LMULMAX1-NEXT: vnsrl.wi v25, v25, 0 +; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu -; LMULMAX1-NEXT: vslideup.vi v27, v25, 4 -; LMULMAX1-NEXT: vse8.v v27, (a1) +; LMULMAX1-NEXT: vslideup.vi v10, v8, 4 +; LMULMAX1-NEXT: vse8.v v10, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = trunc <8 x i32> %a to <8 x i8> diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll index 6ad98d1b1f5341087037bcc9e52a11af23cb19e8..254ff627d054c6218421dbbac577a2fecc19c939 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll @@ -10,12 +10,12 @@ define void @seteq_vv_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: seteq_vv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vmseq.vv v0, v25, v26 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -30,12 +30,12 @@ define void @setne_vv_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vmsne.vv v0, v26, v28 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 -; CHECK-NEXT: vse8.v v26, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v10, (a1) +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -50,10 +50,10 @@ define void @setgt_vv_v64i8(<64 x i8>* %x, <64 x i8>* %y, <64 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 64 ; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vle8.v v8, (a1) -; CHECK-NEXT: vmslt.vv v25, v8, v28 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v12, (a1) +; CHECK-NEXT: vmslt.vv v16, v12, v8 +; CHECK-NEXT: vsm.v v16, (a2) ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = load <64 x i8>, <64 x i8>* %y @@ -69,8 +69,8 @@ define void @setlt_vv_v128i8(<128 x i8>* %x, <128 x i8>* %y, <128 x i1>* %z) { ; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v16, (a1) -; CHECK-NEXT: vmslt.vv v25, v8, v16 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmslt.vv v24, v8, v16 +; CHECK-NEXT: vsm.v v24, (a2) ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = load <128 x i8>, <128 x i8>* %y @@ -83,10 +83,10 @@ define void @setge_vv_v8i8(<8 x i8>* %x, <8 x i8>* %y, <8 x i1>* %z) { ; CHECK-LABEL: setge_vv_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vmsle.vv v25, v26, v25 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vmsle.vv v8, v9, v8 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = load <8 x i8>, <8 x i8>* %y @@ -99,10 +99,10 @@ define void @setle_vv_v16i8(<16 x i8>* %x, <16 x i8>* %y, <16 x i1>* %z) { ; CHECK-LABEL: setle_vv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vmsle.vv v25, v25, v26 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vmsle.vv v8, v8, v9 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -116,10 +116,10 @@ define void @setugt_vv_v32i8(<32 x i8>* %x, <32 x i8>* %y, <32 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 32 ; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vmsltu.vv v25, v28, v26 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v10, (a1) +; CHECK-NEXT: vmsltu.vv v12, v10, v8 +; CHECK-NEXT: vsm.v v12, (a2) ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -133,10 +133,10 @@ define void @setult_vv_v64i8(<64 x i8>* %x, <64 x i8>* %y, <64 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 64 ; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vle8.v v8, (a1) -; CHECK-NEXT: vmsltu.vv v25, v28, v8 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v12, (a1) +; CHECK-NEXT: vmsltu.vv v16, v8, v12 +; CHECK-NEXT: vsm.v v16, (a2) ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = load <64 x i8>, <64 x i8>* %y @@ -152,8 +152,8 @@ define void @setuge_vv_v128i8(<128 x i8>* %x, <128 x i8>* %y, <128 x i1>* %z) { ; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v16, (a1) -; CHECK-NEXT: vmsleu.vv v25, v16, v8 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmsleu.vv v24, v16, v8 +; CHECK-NEXT: vsm.v v24, (a2) ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = load <128 x i8>, <128 x i8>* %y @@ -166,10 +166,10 @@ define void @setule_vv_v8i8(<8 x i8>* %x, <8 x i8>* %y, <8 x i1>* %z) { ; CHECK-LABEL: setule_vv_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vmsleu.vv v25, v25, v26 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vmsleu.vv v8, v8, v9 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = load <8 x i8>, <8 x i8>* %y @@ -182,9 +182,9 @@ define void @seteq_vx_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) { ; CHECK-LABEL: seteq_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmseq.vx v25, v25, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmseq.vx v8, v8, a1 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -199,9 +199,9 @@ define void @setne_vx_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 32 ; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vmsne.vx v25, v26, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsne.vx v10, v8, a1 +; CHECK-NEXT: vsm.v v10, (a2) ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 %y, i32 0 @@ -216,9 +216,9 @@ define void @setgt_vx_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 64 ; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vmsgt.vx v25, v28, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsgt.vx v12, v8, a1 +; CHECK-NEXT: vsm.v v12, (a2) ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 %y, i32 0 @@ -234,8 +234,8 @@ define void @setlt_vx_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) { ; CHECK-NEXT: addi a3, zero, 128 ; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmslt.vx v25, v8, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmslt.vx v16, v8, a1 +; CHECK-NEXT: vsm.v v16, (a2) ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = insertelement <128 x i8> undef, i8 %y, i32 0 @@ -249,10 +249,10 @@ define void @setge_vx_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) { ; CHECK-LABEL: setge_vx_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: vmsle.vv v25, v26, v25 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmv.v.x v9, a1 +; CHECK-NEXT: vmsle.vv v8, v9, v8 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 %y, i32 0 @@ -266,9 +266,9 @@ define void @setle_vx_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) { ; CHECK-LABEL: setle_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmsle.vx v25, v25, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsle.vx v8, v8, a1 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -283,9 +283,9 @@ define void @setugt_vx_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 32 ; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vmsgtu.vx v25, v26, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsgtu.vx v10, v8, a1 +; CHECK-NEXT: vsm.v v10, (a2) ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 %y, i32 0 @@ -300,9 +300,9 @@ define void @setult_vx_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 64 ; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vmsltu.vx v25, v28, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsltu.vx v12, v8, a1 +; CHECK-NEXT: vsm.v v12, (a2) ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 %y, i32 0 @@ -319,8 +319,8 @@ define void @setuge_vx_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) { ; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vmv.v.x v16, a1 -; CHECK-NEXT: vmsleu.vv v25, v16, v8 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmsleu.vv v24, v16, v8 +; CHECK-NEXT: vsm.v v24, (a2) ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = insertelement <128 x i8> undef, i8 %y, i32 0 @@ -334,9 +334,9 @@ define void @setule_vx_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) { ; CHECK-LABEL: setule_vx_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmsleu.vx v25, v25, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsleu.vx v8, v8, a1 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 %y, i32 0 @@ -350,9 +350,9 @@ define void @seteq_xv_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) { ; CHECK-LABEL: seteq_xv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmseq.vx v25, v25, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmseq.vx v8, v8, a1 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -367,9 +367,9 @@ define void @setne_xv_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 32 ; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vmsne.vx v25, v26, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsne.vx v10, v8, a1 +; CHECK-NEXT: vsm.v v10, (a2) ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 %y, i32 0 @@ -384,9 +384,9 @@ define void @setgt_xv_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 64 ; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vmslt.vx v25, v28, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmslt.vx v12, v8, a1 +; CHECK-NEXT: vsm.v v12, (a2) ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 %y, i32 0 @@ -402,8 +402,8 @@ define void @setlt_xv_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) { ; CHECK-NEXT: addi a3, zero, 128 ; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmsgt.vx v25, v8, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmsgt.vx v16, v8, a1 +; CHECK-NEXT: vsm.v v16, (a2) ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = insertelement <128 x i8> undef, i8 %y, i32 0 @@ -417,9 +417,9 @@ define void @setge_xv_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) { ; CHECK-LABEL: setge_xv_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmsle.vx v25, v25, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsle.vx v8, v8, a1 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 %y, i32 0 @@ -433,10 +433,10 @@ define void @setle_xv_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) { ; CHECK-LABEL: setle_xv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: vmsle.vv v25, v26, v25 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmv.v.x v9, a1 +; CHECK-NEXT: vmsle.vv v8, v9, v8 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -451,9 +451,9 @@ define void @setugt_xv_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 32 ; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vmsltu.vx v25, v26, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsltu.vx v10, v8, a1 +; CHECK-NEXT: vsm.v v10, (a2) ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 %y, i32 0 @@ -468,9 +468,9 @@ define void @setult_xv_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 64 ; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vmsgtu.vx v25, v28, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsgtu.vx v12, v8, a1 +; CHECK-NEXT: vsm.v v12, (a2) ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 %y, i32 0 @@ -486,8 +486,8 @@ define void @setuge_xv_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) { ; CHECK-NEXT: addi a3, zero, 128 ; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmsleu.vx v25, v8, a1 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vmsleu.vx v16, v8, a1 +; CHECK-NEXT: vsm.v v16, (a2) ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = insertelement <128 x i8> undef, i8 %y, i32 0 @@ -501,10 +501,10 @@ define void @setule_xv_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) { ; CHECK-LABEL: setule_xv_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmv.v.x v26, a1 -; CHECK-NEXT: vmsleu.vv v25, v26, v25 -; CHECK-NEXT: vsm.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmv.v.x v9, a1 +; CHECK-NEXT: vmsleu.vv v8, v9, v8 +; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 %y, i32 0 @@ -518,9 +518,9 @@ define void @seteq_vi_v16i8(<16 x i8>* %x, <16 x i1>* %z) { ; CHECK-LABEL: seteq_vi_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmseq.vi v25, v25, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmseq.vi v8, v8, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 0, i32 0 @@ -535,9 +535,9 @@ define void @setne_vi_v32i8(<32 x i8>* %x, <32 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsne.vi v10, v8, 0 +; CHECK-NEXT: vsm.v v10, (a1) ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 0, i32 0 @@ -552,9 +552,9 @@ define void @setgt_vi_v64i8(<64 x i8>* %x, <64 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vmsgt.vx v25, v28, zero -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsgt.vx v12, v8, zero +; CHECK-NEXT: vsm.v v12, (a1) ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 0, i32 0 @@ -570,8 +570,8 @@ define void @setlt_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) { ; CHECK-NEXT: addi a2, zero, 128 ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmsle.vi v25, v8, -1 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsle.vi v16, v8, -1 +; CHECK-NEXT: vsm.v v16, (a1) ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = insertelement <128 x i8> undef, i8 0, i32 0 @@ -585,9 +585,9 @@ define void @setge_vi_v8i8(<8 x i8>* %x, <8 x i1>* %z) { ; CHECK-LABEL: setge_vi_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmsgt.vi v25, v25, -1 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsgt.vi v8, v8, -1 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 0, i32 0 @@ -601,9 +601,9 @@ define void @setle_vi_v16i8(<16 x i8>* %x, <16 x i1>* %z) { ; CHECK-LABEL: setle_vi_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmsle.vi v25, v25, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsle.vi v8, v8, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 0, i32 0 @@ -618,10 +618,10 @@ define void @setugt_vi_v32i8(<32 x i8>* %x, <32 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, zero, 5 -; CHECK-NEXT: vmsgtu.vx v25, v26, a0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsgtu.vx v10, v8, a0 +; CHECK-NEXT: vsm.v v10, (a1) ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 5, i32 0 @@ -636,9 +636,9 @@ define void @setult_vi_v64i8(<64 x i8>* %x, <64 x i1>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vmsleu.vi v25, v28, 4 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsleu.vi v12, v8, 4 +; CHECK-NEXT: vsm.v v12, (a1) ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 5, i32 0 @@ -654,8 +654,8 @@ define void @setuge_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) { ; CHECK-NEXT: addi a2, zero, 128 ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmsgtu.vi v25, v8, 4 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsgtu.vi v16, v8, 4 +; CHECK-NEXT: vsm.v v16, (a1) ; CHECK-NEXT: ret %a = load <128 x i8>, <128 x i8>* %x %b = insertelement <128 x i8> undef, i8 5, i32 0 @@ -669,9 +669,9 @@ define void @setule_vi_v8i8(<8 x i8>* %x, <8 x i1>* %z) { ; CHECK-LABEL: setule_vi_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmsleu.vi v25, v25, 5 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmsleu.vi v8, v8, 5 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 5, i32 0 @@ -685,12 +685,12 @@ define void @seteq_vv_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: seteq_vv_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vmseq.vv v0, v25, v26 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -704,12 +704,12 @@ define void @setne_vv_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: setne_vv_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vmsne.vv v0, v25, v26 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -723,12 +723,12 @@ define void @setgt_vv_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: setgt_vv_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vmslt.vv v0, v26, v25 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vmslt.vv v0, v9, v8 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -742,12 +742,12 @@ define void @setlt_vv_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; CHECK-LABEL: setlt_vv_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vmslt.vv v0, v26, v28 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 -; CHECK-NEXT: vse16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v10, (a1) +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -761,12 +761,12 @@ define void @setugt_vv_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; CHECK-LABEL: setugt_vv_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vmsltu.vv v0, v28, v26 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 -; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v10, (a1) +; CHECK-NEXT: vmsltu.vv v0, v10, v8 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -780,12 +780,12 @@ define void @setult_vv_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; CHECK-LABEL: setult_vv_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) -; CHECK-NEXT: vle64.v v28, (a1) -; CHECK-NEXT: vmsltu.vv v0, v26, v28 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 -; CHECK-NEXT: vse64.v v26, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v10, (a1) +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll index d9ad41291a7c843692963288df4738de7c4d354a..f01eeefa18ed2dcab6dea29ff7e71994f87427f4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll @@ -60,9 +60,9 @@ define <4 x i16> @vrgather_permute_shuffle_vu_v4i16(<4 x i16> %x) { ; CHECK-NEXT: lui a0, %hi(.LCPI4_0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI4_0) ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vle16.v v10, (a0) +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %s = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> ret <4 x i16> %s @@ -74,9 +74,9 @@ define <4 x i16> @vrgather_permute_shuffle_uv_v4i16(<4 x i16> %x) { ; CHECK-NEXT: lui a0, %hi(.LCPI5_0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_0) ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vle16.v v10, (a0) +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %s = shufflevector <4 x i16> undef, <4 x i16> %x, <4 x i32> ret <4 x i16> %s @@ -88,14 +88,14 @@ define <4 x i16> @vrgather_shuffle_vv_v4i16(<4 x i16> %x, <4 x i16> %y) { ; CHECK-NEXT: lui a0, %hi(.LCPI6_0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI6_0) ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vrgather.vv v25, v8, v26 +; CHECK-NEXT: vle16.v v11, (a0) +; CHECK-NEXT: vrgather.vv v10, v8, v11 ; CHECK-NEXT: addi a0, zero, 8 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vrgather.vi v25, v9, 1, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vrgather.vi v10, v9, 1, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %s = shufflevector <4 x i16> %x, <4 x i16> %y, <4 x i32> ret <4 x i16> %s @@ -108,11 +108,11 @@ define <4 x i16> @vrgather_shuffle_xv_v4i16(<4 x i16> %x) { ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vi v26, v25, 4 -; CHECK-NEXT: vmv.v.i v25, 5 -; CHECK-NEXT: vrgather.vv v25, v8, v26, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vrsub.vi v10, v9, 4 +; CHECK-NEXT: vmv.v.i v9, 5 +; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %s = shufflevector <4 x i16> , <4 x i16> %x, <4 x i32> ret <4 x i16> %s @@ -122,15 +122,15 @@ define <4 x i16> @vrgather_shuffle_vx_v4i16(<4 x i16> %x) { ; CHECK-LABEL: vrgather_shuffle_vx_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vid.v v25 +; CHECK-NEXT: vid.v v9 ; CHECK-NEXT: addi a0, zero, 3 -; CHECK-NEXT: vmul.vx v26, v25, a0 +; CHECK-NEXT: vmul.vx v10, v9, a0 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 5 -; CHECK-NEXT: vrgather.vv v25, v8, v26, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vmv.v.i v9, 5 +; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %s = shufflevector <4 x i16> %x, <4 x i16> , <4 x i32> ret <4 x i16> %s @@ -142,10 +142,10 @@ define <8 x i64> @vrgather_permute_shuffle_vu_v8i64(<8 x i64> %x) { ; RV32-NEXT: lui a0, %hi(.LCPI9_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI9_0) ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV32-NEXT: vle16.v v25, (a0) +; RV32-NEXT: vle16.v v16, (a0) ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vrgatherei16.vv v28, v8, v25 -; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: vrgatherei16.vv v12, v8, v16 +; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_permute_shuffle_vu_v8i64: @@ -153,9 +153,9 @@ define <8 x i64> @vrgather_permute_shuffle_vu_v8i64(<8 x i64> %x) { ; RV64-NEXT: lui a0, %hi(.LCPI9_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI9_0) ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v12, (a0) -; RV64-NEXT: vrgather.vv v28, v8, v12 -; RV64-NEXT: vmv4r.v v8, v28 +; RV64-NEXT: vle64.v v16, (a0) +; RV64-NEXT: vrgather.vv v12, v8, v16 +; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %s = shufflevector <8 x i64> %x, <8 x i64> undef, <8 x i32> ret <8 x i64> %s @@ -167,10 +167,10 @@ define <8 x i64> @vrgather_permute_shuffle_uv_v8i64(<8 x i64> %x) { ; RV32-NEXT: lui a0, %hi(.LCPI10_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI10_0) ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV32-NEXT: vle16.v v25, (a0) +; RV32-NEXT: vle16.v v16, (a0) ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vrgatherei16.vv v28, v8, v25 -; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: vrgatherei16.vv v12, v8, v16 +; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_permute_shuffle_uv_v8i64: @@ -178,9 +178,9 @@ define <8 x i64> @vrgather_permute_shuffle_uv_v8i64(<8 x i64> %x) { ; RV64-NEXT: lui a0, %hi(.LCPI10_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI10_0) ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v12, (a0) -; RV64-NEXT: vrgather.vv v28, v8, v12 -; RV64-NEXT: vmv4r.v v8, v28 +; RV64-NEXT: vle64.v v16, (a0) +; RV64-NEXT: vrgather.vv v12, v8, v16 +; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %s = shufflevector <8 x i64> undef, <8 x i64> %x, <8 x i32> ret <8 x i64> %s @@ -191,43 +191,43 @@ define <8 x i64> @vrgather_shuffle_vv_v8i64(<8 x i64> %x, <8 x i64> %y) { ; RV32: # %bb.0: ; RV32-NEXT: addi a0, zero, 5 ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV32-NEXT: vmv.s.x v25, a0 -; RV32-NEXT: vmv.v.i v26, 2 +; RV32-NEXT: vmv.s.x v16, a0 +; RV32-NEXT: vmv.v.i v20, 2 ; RV32-NEXT: vsetvli zero, zero, e16, m1, tu, mu -; RV32-NEXT: vslideup.vi v26, v25, 7 +; RV32-NEXT: vslideup.vi v20, v16, 7 ; RV32-NEXT: lui a0, %hi(.LCPI11_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI11_0) ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vle16.v v25, (a0) +; RV32-NEXT: vle16.v v21, (a0) ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vrgatherei16.vv v28, v8, v25 +; RV32-NEXT: vrgatherei16.vv v16, v8, v21 ; RV32-NEXT: addi a0, zero, 164 ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vmv.s.x v0, a0 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vrgatherei16.vv v28, v12, v26, v0.t -; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: vrgatherei16.vv v16, v12, v20, v0.t +; RV32-NEXT: vmv4r.v v8, v16 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_shuffle_vv_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: addi a0, zero, 5 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vmv.s.x v28, a0 -; RV64-NEXT: vmv.v.i v16, 2 +; RV64-NEXT: vmv.s.x v16, a0 +; RV64-NEXT: vmv.v.i v20, 2 ; RV64-NEXT: vsetvli zero, zero, e64, m4, tu, mu -; RV64-NEXT: vslideup.vi v16, v28, 7 +; RV64-NEXT: vslideup.vi v20, v16, 7 ; RV64-NEXT: lui a0, %hi(.LCPI11_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI11_0) ; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV64-NEXT: vle64.v v20, (a0) -; RV64-NEXT: vrgather.vv v28, v8, v20 +; RV64-NEXT: vle64.v v24, (a0) +; RV64-NEXT: vrgather.vv v16, v8, v24 ; RV64-NEXT: addi a0, zero, 164 ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV64-NEXT: vmv.s.x v0, a0 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vrgather.vv v28, v12, v16, v0.t -; RV64-NEXT: vmv4r.v v8, v28 +; RV64-NEXT: vrgather.vv v16, v12, v20, v0.t +; RV64-NEXT: vmv4r.v v8, v16 ; RV64-NEXT: ret %s = shufflevector <8 x i64> %x, <8 x i64> %y, <8 x i32> ret <8 x i64> %s @@ -239,20 +239,20 @@ define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) { ; RV32-NEXT: lui a0, %hi(.LCPI12_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI12_0) ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV32-NEXT: vle16.v v25, (a0) +; RV32-NEXT: vle16.v v16, (a0) ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vmv.v.i v12, -1 -; RV32-NEXT: vrgatherei16.vv v28, v12, v25 +; RV32-NEXT: vmv.v.i v20, -1 +; RV32-NEXT: vrgatherei16.vv v12, v20, v16 ; RV32-NEXT: addi a0, zero, 113 ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vmv.s.x v0, a0 ; RV32-NEXT: lui a0, %hi(.LCPI12_1) ; RV32-NEXT: addi a0, a0, %lo(.LCPI12_1) ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV32-NEXT: vle16.v v25, (a0) +; RV32-NEXT: vle16.v v16, (a0) ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vrgatherei16.vv v28, v8, v25, v0.t -; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: vrgatherei16.vv v12, v8, v16, v0.t +; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_shuffle_xv_v8i64: @@ -263,10 +263,10 @@ define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) { ; RV64-NEXT: lui a0, %hi(.LCPI12_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI12_0) ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v12, (a0) -; RV64-NEXT: vmv.v.i v28, -1 -; RV64-NEXT: vrgather.vv v28, v8, v12, v0.t -; RV64-NEXT: vmv4r.v v8, v28 +; RV64-NEXT: vle64.v v16, (a0) +; RV64-NEXT: vmv.v.i v12, -1 +; RV64-NEXT: vrgather.vv v12, v8, v16, v0.t +; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %s = shufflevector <8 x i64> , <8 x i64> %x, <8 x i32> ret <8 x i64> %s @@ -278,20 +278,20 @@ define <8 x i64> @vrgather_shuffle_vx_v8i64(<8 x i64> %x) { ; RV32-NEXT: lui a0, %hi(.LCPI13_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI13_0) ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV32-NEXT: vle16.v v25, (a0) -; RV32-NEXT: vmv4r.v v28, v8 +; RV32-NEXT: vle16.v v16, (a0) +; RV32-NEXT: vmv4r.v v12, v8 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vrgatherei16.vv v8, v28, v25 +; RV32-NEXT: vrgatherei16.vv v8, v12, v16 ; RV32-NEXT: addi a0, zero, 140 ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vmv.s.x v0, a0 ; RV32-NEXT: lui a0, %hi(.LCPI13_1) ; RV32-NEXT: addi a0, a0, %lo(.LCPI13_1) ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV32-NEXT: vle16.v v25, (a0) +; RV32-NEXT: vle16.v v12, (a0) ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vmv.v.i v28, 5 -; RV32-NEXT: vrgatherei16.vv v8, v28, v25, v0.t +; RV32-NEXT: vmv.v.i v16, 5 +; RV32-NEXT: vrgatherei16.vv v8, v16, v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vrgather_shuffle_vx_v8i64: @@ -302,10 +302,10 @@ define <8 x i64> @vrgather_shuffle_vx_v8i64(<8 x i64> %x) { ; RV64-NEXT: lui a0, %hi(.LCPI13_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI13_0) ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v12, (a0) -; RV64-NEXT: vmv.v.i v28, 5 -; RV64-NEXT: vrgather.vv v28, v8, v12, v0.t -; RV64-NEXT: vmv4r.v v8, v28 +; RV64-NEXT: vle64.v v16, (a0) +; RV64-NEXT: vmv.v.i v12, 5 +; RV64-NEXT: vrgather.vv v12, v8, v16, v0.t +; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %s = shufflevector <8 x i64> %x, <8 x i64> , <8 x i32> ret <8 x i64> %s @@ -317,15 +317,15 @@ define <4 x i8> @interleave_shuffles(<4 x i8> %x) { ; CHECK-NEXT: vsetivli zero, 0, e8, mf4, ta, mu ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vrgather.vi v25, v8, 1 +; CHECK-NEXT: vrgather.vi v9, v8, 1 ; CHECK-NEXT: addi a1, zero, 10 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.s.x v0, a1 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vid.v v26 -; CHECK-NEXT: vsrl.vi v26, v26, 1 +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vsrl.vi v10, v8, 1 ; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vrgather.vv v8, v25, v26, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret %y = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> %z = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> @@ -337,8 +337,8 @@ define <8 x i8> @splat_ve4(<8 x i8> %v) { ; CHECK-LABEL: splat_ve4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vrgather.vi v25, v8, 4 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vrgather.vi v9, v8, 4 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuff @@ -348,13 +348,13 @@ define <8 x i8> @splat_ve4_ins_i0ve2(<8 x i8> %v) { ; CHECK-LABEL: splat_ve4_ins_i0ve2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 4 +; CHECK-NEXT: vmv.v.i v10, 4 ; CHECK-NEXT: addi a0, zero, 2 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuff @@ -365,13 +365,13 @@ define <8 x i8> @splat_ve4_ins_i1ve3(<8 x i8> %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 3 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 -; CHECK-NEXT: vmv.v.i v26, 4 +; CHECK-NEXT: vmv.s.x v9, a0 +; CHECK-NEXT: vmv.v.i v10, 4 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 1 +; CHECK-NEXT: vslideup.vi v10, v9, 1 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuff @@ -384,9 +384,9 @@ define <8 x i8> @splat_ve2_we0(<8 x i8> %v, <8 x i8> %w) { ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vrgather.vi v25, v8, 2 -; CHECK-NEXT: vrgather.vi v25, v9, 0, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vrgather.vi v10, v8, 2 +; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> ret <8 x i8> %shuff @@ -396,18 +396,18 @@ define <8 x i8> @splat_ve2_we0_ins_i0ve4(<8 x i8> %v, <8 x i8> %w) { ; CHECK-LABEL: splat_ve2_we0_ins_i0ve4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 2 +; CHECK-NEXT: vmv.v.i v11, 2 ; CHECK-NEXT: addi a0, zero, 4 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v11, a0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vrgather.vv v25, v8, v26 +; CHECK-NEXT: vrgather.vv v10, v8, v11 ; CHECK-NEXT: addi a0, zero, 66 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vrgather.vi v25, v9, 0, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> ret <8 x i8> %shuff @@ -420,12 +420,12 @@ define <8 x i8> @splat_ve2_we0_ins_i0we4(<8 x i8> %v, <8 x i8> %w) { ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vrgather.vi v25, v8, 2 +; CHECK-NEXT: vrgather.vi v10, v8, 2 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 4 +; CHECK-NEXT: vmv.v.i v8, 4 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vrgather.vv v25, v9, v26, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> ret <8 x i8> %shuff @@ -437,15 +437,15 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4(<8 x i8> %v, <8 x i8> %w) { ; RV32-NEXT: lui a0, 8256 ; RV32-NEXT: addi a0, a0, 514 ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vmv.v.x v26, a0 +; RV32-NEXT: vmv.v.x v11, a0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vrgather.vv v25, v8, v26 +; RV32-NEXT: vrgather.vv v10, v8, v11 ; RV32-NEXT: addi a0, zero, 66 ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vmv.s.x v0, a0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vrgather.vi v25, v9, 0, v0.t -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vrgather.vi v10, v9, 0, v0.t +; RV32-NEXT: vmv1r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: splat_ve2_we0_ins_i2ve4: @@ -453,15 +453,15 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4(<8 x i8> %v, <8 x i8> %w) { ; RV64-NEXT: lui a0, 8256 ; RV64-NEXT: addiw a0, a0, 514 ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vmv.v.x v26, a0 +; RV64-NEXT: vmv.v.x v11, a0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vrgather.vv v25, v8, v26 +; RV64-NEXT: vrgather.vv v10, v8, v11 ; RV64-NEXT: addi a0, zero, 66 ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV64-NEXT: vmv.s.x v0, a0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vrgather.vi v25, v9, 0, v0.t -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vrgather.vi v10, v9, 0, v0.t +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> ret <8 x i8> %shuff @@ -472,17 +472,17 @@ define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 4 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.s.x v10, a0 +; CHECK-NEXT: vmv.v.i v11, 0 ; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 2 +; CHECK-NEXT: vslideup.vi v11, v10, 2 ; CHECK-NEXT: addi a0, zero, 70 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vrgather.vi v25, v8, 2 -; CHECK-NEXT: vrgather.vv v25, v9, v26, v0.t -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vrgather.vi v10, v8, 2 +; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> ret <8 x i8> %shuff @@ -493,44 +493,44 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4_i5we6(<8 x i8> %v, <8 x i8> %w) { ; RV32: # %bb.0: ; RV32-NEXT: addi a0, zero, 6 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmv.s.x v25, a0 -; RV32-NEXT: vmv.v.i v26, 0 +; RV32-NEXT: vmv.s.x v10, a0 +; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vsetivli zero, 6, e8, mf2, tu, mu -; RV32-NEXT: vslideup.vi v26, v25, 5 +; RV32-NEXT: vslideup.vi v11, v10, 5 ; RV32-NEXT: lui a0, 8256 ; RV32-NEXT: addi a0, a0, 2 ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vmv.v.x v27, a0 +; RV32-NEXT: vmv.v.x v12, a0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vrgather.vv v25, v8, v27 +; RV32-NEXT: vrgather.vv v10, v8, v12 ; RV32-NEXT: addi a0, zero, 98 ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vmv.s.x v0, a0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vrgather.vv v25, v9, v26, v0.t -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vrgather.vv v10, v9, v11, v0.t +; RV32-NEXT: vmv1r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: splat_ve2_we0_ins_i2ve4_i5we6: ; RV64: # %bb.0: ; RV64-NEXT: addi a0, zero, 6 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vmv.s.x v25, a0 -; RV64-NEXT: vmv.v.i v26, 0 +; RV64-NEXT: vmv.s.x v10, a0 +; RV64-NEXT: vmv.v.i v11, 0 ; RV64-NEXT: vsetivli zero, 6, e8, mf2, tu, mu -; RV64-NEXT: vslideup.vi v26, v25, 5 +; RV64-NEXT: vslideup.vi v11, v10, 5 ; RV64-NEXT: lui a0, 8256 ; RV64-NEXT: addiw a0, a0, 2 ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vmv.v.x v27, a0 +; RV64-NEXT: vmv.v.x v12, a0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vrgather.vv v25, v8, v27 +; RV64-NEXT: vrgather.vv v10, v8, v12 ; RV64-NEXT: addi a0, zero, 98 ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV64-NEXT: vmv.s.x v0, a0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vrgather.vv v25, v9, v26, v0.t -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vrgather.vv v10, v9, v11, v0.t +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> ret <8 x i8> %shuff @@ -540,15 +540,15 @@ define <8 x i8> @widen_splat_ve3(<4 x i8> %v) { ; CHECK-LABEL: widen_splat_ve3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v25, v8, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v25, v26, 4 +; CHECK-NEXT: vslideup.vi v9, v8, 4 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vrgather.vi v8, v25, 3 +; CHECK-NEXT: vrgather.vi v8, v9, 3 ; CHECK-NEXT: ret %shuf = shufflevector <4 x i8> %v, <4 x i8> undef, <8 x i32> ret <8 x i8> %shuf diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll index 4098ff88cc14adaab2c11f1fae649210500e1ab4..024725bd1a5a9d28cb19192c65ed2d6f5eb290ef 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll @@ -10,8 +10,8 @@ define void @splat_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: splat_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <16 x i8> undef, i8 %y, i32 0 %b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer @@ -23,8 +23,8 @@ define void @splat_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: splat_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <8 x i16> undef, i16 %y, i32 0 %b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer @@ -36,8 +36,8 @@ define void @splat_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: splat_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <4 x i32> undef, i32 %y, i32 0 %b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer @@ -54,8 +54,8 @@ define void @splat_v2i64(<2 x i64>* %x, i64 %y) { ; LMULMAX8-RV32-NEXT: sw a1, 8(sp) ; LMULMAX8-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX8-RV32-NEXT: addi a1, sp, 8 -; LMULMAX8-RV32-NEXT: vlse64.v v25, (a1), zero -; LMULMAX8-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX8-RV32-NEXT: vlse64.v v8, (a1), zero +; LMULMAX8-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX8-RV32-NEXT: addi sp, sp, 16 ; LMULMAX8-RV32-NEXT: ret ; @@ -67,8 +67,8 @@ define void @splat_v2i64(<2 x i64>* %x, i64 %y) { ; LMULMAX2-RV32-NEXT: sw a1, 8(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 8 -; LMULMAX2-RV32-NEXT: vlse64.v v25, (a1), zero -; LMULMAX2-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX2-RV32-NEXT: vlse64.v v8, (a1), zero +; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 16 ; LMULMAX2-RV32-NEXT: ret ; @@ -80,30 +80,30 @@ define void @splat_v2i64(<2 x i64>* %x, i64 %y) { ; LMULMAX1-RV32-NEXT: sw a1, 8(sp) ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: addi a1, sp, 8 -; LMULMAX1-RV32-NEXT: vlse64.v v25, (a1), zero -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vlse64.v v8, (a1), zero +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi sp, sp, 16 ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX8-RV64-LABEL: splat_v2i64: ; LMULMAX8-RV64: # %bb.0: ; LMULMAX8-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX8-RV64-NEXT: vmv.v.x v25, a1 -; LMULMAX8-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX8-RV64-NEXT: vmv.v.x v8, a1 +; LMULMAX8-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX8-RV64-NEXT: ret ; ; LMULMAX2-RV64-LABEL: splat_v2i64: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX2-RV64-NEXT: vmv.v.x v25, a1 -; LMULMAX2-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX2-RV64-NEXT: vmv.v.x v8, a1 +; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_v2i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vmv.v.x v8, a1 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = insertelement <2 x i64> undef, i64 %y, i32 0 %b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer @@ -116,25 +116,25 @@ define void @splat_v32i8(<32 x i8>* %x, i8 %y) { ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: addi a2, zero, 32 ; LMULMAX8-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX8-NEXT: vmv.v.x v26, a1 -; LMULMAX8-NEXT: vse8.v v26, (a0) +; LMULMAX8-NEXT: vmv.v.x v8, a1 +; LMULMAX8-NEXT: vse8.v v8, (a0) ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_v32i8: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.x v26, a1 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vmv.v.x v8, a1 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_v32i8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.x v25, a1 +; LMULMAX1-NEXT: vmv.v.x v8, a1 ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vse8.v v25, (a1) -; LMULMAX1-NEXT: vse8.v v25, (a0) +; LMULMAX1-NEXT: vse8.v v8, (a1) +; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: ret %a = insertelement <32 x i8> undef, i8 %y, i32 0 %b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer @@ -146,24 +146,24 @@ define void @splat_v16i16(<16 x i16>* %x, i16 %y) { ; LMULMAX8-LABEL: splat_v16i16: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX8-NEXT: vmv.v.x v26, a1 -; LMULMAX8-NEXT: vse16.v v26, (a0) +; LMULMAX8-NEXT: vmv.v.x v8, a1 +; LMULMAX8-NEXT: vse16.v v8, (a0) ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.x v26, a1 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vmv.v.x v8, a1 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_v16i16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.x v25, a1 +; LMULMAX1-NEXT: vmv.v.x v8, a1 ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vse16.v v25, (a1) -; LMULMAX1-NEXT: vse16.v v25, (a0) +; LMULMAX1-NEXT: vse16.v v8, (a1) +; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: ret %a = insertelement <16 x i16> undef, i16 %y, i32 0 %b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer @@ -175,24 +175,24 @@ define void @splat_v8i32(<8 x i32>* %x, i32 %y) { ; LMULMAX8-LABEL: splat_v8i32: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX8-NEXT: vmv.v.x v26, a1 -; LMULMAX8-NEXT: vse32.v v26, (a0) +; LMULMAX8-NEXT: vmv.v.x v8, a1 +; LMULMAX8-NEXT: vse32.v v8, (a0) ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.x v26, a1 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vmv.v.x v8, a1 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_v8i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.x v25, a1 +; LMULMAX1-NEXT: vmv.v.x v8, a1 ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vse32.v v25, (a1) -; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: vse32.v v8, (a1) +; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: ret %a = insertelement <8 x i32> undef, i32 %y, i32 0 %b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer @@ -209,8 +209,8 @@ define void @splat_v4i64(<4 x i64>* %x, i64 %y) { ; LMULMAX8-RV32-NEXT: sw a1, 8(sp) ; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX8-RV32-NEXT: addi a1, sp, 8 -; LMULMAX8-RV32-NEXT: vlse64.v v26, (a1), zero -; LMULMAX8-RV32-NEXT: vse64.v v26, (a0) +; LMULMAX8-RV32-NEXT: vlse64.v v8, (a1), zero +; LMULMAX8-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX8-RV32-NEXT: addi sp, sp, 16 ; LMULMAX8-RV32-NEXT: ret ; @@ -222,8 +222,8 @@ define void @splat_v4i64(<4 x i64>* %x, i64 %y) { ; LMULMAX2-RV32-NEXT: sw a1, 8(sp) ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-RV32-NEXT: addi a1, sp, 8 -; LMULMAX2-RV32-NEXT: vlse64.v v26, (a1), zero -; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV32-NEXT: vlse64.v v8, (a1), zero +; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi sp, sp, 16 ; LMULMAX2-RV32-NEXT: ret ; @@ -233,34 +233,34 @@ define void @splat_v4i64(<4 x i64>* %x, i64 %y) { ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX1-RV32-NEXT: vmv.s.x v0, a3 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v25, a2 -; LMULMAX1-RV32-NEXT: vmerge.vxm v25, v25, a1, v0 +; LMULMAX1-RV32-NEXT: vmv.v.x v8, a2 +; LMULMAX1-RV32-NEXT: vmerge.vxm v8, v8, a1, v0 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a1) -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v8, (a1) +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX8-RV64-LABEL: splat_v4i64: ; LMULMAX8-RV64: # %bb.0: ; LMULMAX8-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX8-RV64-NEXT: vmv.v.x v26, a1 -; LMULMAX8-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX8-RV64-NEXT: vmv.v.x v8, a1 +; LMULMAX8-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX8-RV64-NEXT: ret ; ; LMULMAX2-RV64-LABEL: splat_v4i64: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV64-NEXT: vmv.v.x v26, a1 -; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vmv.v.x v8, a1 +; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1 +; LMULMAX1-RV64-NEXT: vmv.v.x v8, a1 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a1) -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v8, (a1) +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = insertelement <4 x i64> undef, i64 %y, i32 0 %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer @@ -272,8 +272,8 @@ define void @splat_zero_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: splat_zero_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <16 x i8> undef, i8 0, i32 0 %b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer @@ -285,8 +285,8 @@ define void @splat_zero_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: splat_zero_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <8 x i16> undef, i16 0, i32 0 %b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer @@ -298,8 +298,8 @@ define void @splat_zero_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: splat_zero_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <4 x i32> undef, i32 0, i32 0 %b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer @@ -311,8 +311,8 @@ define void @splat_zero_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: splat_zero_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <2 x i64> undef, i64 0, i32 0 %b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer @@ -325,25 +325,25 @@ define void @splat_zero_v32i8(<32 x i8>* %x) { ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: addi a1, zero, 32 ; LMULMAX8-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX8-NEXT: vmv.v.i v26, 0 -; LMULMAX8-NEXT: vse8.v v26, (a0) +; LMULMAX8-NEXT: vmv.v.i v8, 0 +; LMULMAX8-NEXT: vse8.v v8, (a0) ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_zero_v32i8: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a1, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v26, 0 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vmv.v.i v8, 0 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_zero_v32i8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vse8.v v25, (a0) +; LMULMAX1-NEXT: vmv.v.i v8, 0 +; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vse8.v v25, (a0) +; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: ret %a = insertelement <32 x i8> undef, i8 0, i32 0 %b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer @@ -355,24 +355,24 @@ define void @splat_zero_v16i16(<16 x i16>* %x) { ; LMULMAX8-LABEL: splat_zero_v16i16: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX8-NEXT: vmv.v.i v26, 0 -; LMULMAX8-NEXT: vse16.v v26, (a0) +; LMULMAX8-NEXT: vmv.v.i v8, 0 +; LMULMAX8-NEXT: vse16.v v8, (a0) ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_zero_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v26, 0 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vmv.v.i v8, 0 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_zero_v16i16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vse16.v v25, (a0) +; LMULMAX1-NEXT: vmv.v.i v8, 0 +; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vse16.v v25, (a0) +; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: ret %a = insertelement <16 x i16> undef, i16 0, i32 0 %b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer @@ -384,24 +384,24 @@ define void @splat_zero_v8i32(<8 x i32>* %x) { ; LMULMAX8-LABEL: splat_zero_v8i32: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX8-NEXT: vmv.v.i v26, 0 -; LMULMAX8-NEXT: vse32.v v26, (a0) +; LMULMAX8-NEXT: vmv.v.i v8, 0 +; LMULMAX8-NEXT: vse32.v v8, (a0) ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_zero_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v26, 0 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vmv.v.i v8, 0 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_zero_v8i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v25, 0 -; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: vmv.v.i v8, 0 +; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: ret %a = insertelement <8 x i32> undef, i32 0, i32 0 %b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer @@ -413,33 +413,33 @@ define void @splat_zero_v4i64(<4 x i64>* %x) { ; LMULMAX8-LABEL: splat_zero_v4i64: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX8-NEXT: vmv.v.i v26, 0 -; LMULMAX8-NEXT: vse64.v v26, (a0) +; LMULMAX8-NEXT: vmv.v.i v8, 0 +; LMULMAX8-NEXT: vse64.v v8, (a0) ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_zero_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v26, 0 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vmv.v.i v8, 0 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_zero_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.i v25, 0 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a0, a0, 16 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_zero_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.i v25, 0 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vmv.v.i v8, 0 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a0, a0, 16 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = insertelement <4 x i64> undef, i64 0, i32 0 %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer @@ -451,8 +451,8 @@ define void @splat_allones_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: splat_allones_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vmv.v.i v8, -1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <16 x i8> undef, i8 -1, i32 0 %b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer @@ -464,8 +464,8 @@ define void @splat_allones_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: splat_allones_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vmv.v.i v8, -1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <8 x i16> undef, i16 -1, i32 0 %b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer @@ -477,8 +477,8 @@ define void @splat_allones_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: splat_allones_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vmv.v.i v8, -1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <4 x i32> undef, i32 -1, i32 0 %b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer @@ -490,8 +490,8 @@ define void @splat_allones_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: splat_allones_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vmv.v.i v8, -1 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <2 x i64> undef, i64 -1, i32 0 %b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer @@ -504,25 +504,25 @@ define void @splat_allones_v32i8(<32 x i8>* %x) { ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: addi a1, zero, 32 ; LMULMAX8-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX8-NEXT: vmv.v.i v26, -1 -; LMULMAX8-NEXT: vse8.v v26, (a0) +; LMULMAX8-NEXT: vmv.v.i v8, -1 +; LMULMAX8-NEXT: vse8.v v8, (a0) ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_allones_v32i8: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a1, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v26, -1 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vmv.v.i v8, -1 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_allones_v32i8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v25, -1 -; LMULMAX1-NEXT: vse8.v v25, (a0) +; LMULMAX1-NEXT: vmv.v.i v8, -1 +; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vse8.v v25, (a0) +; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: ret %a = insertelement <32 x i8> undef, i8 -1, i32 0 %b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer @@ -534,24 +534,24 @@ define void @splat_allones_v16i16(<16 x i16>* %x) { ; LMULMAX8-LABEL: splat_allones_v16i16: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX8-NEXT: vmv.v.i v26, -1 -; LMULMAX8-NEXT: vse16.v v26, (a0) +; LMULMAX8-NEXT: vmv.v.i v8, -1 +; LMULMAX8-NEXT: vse16.v v8, (a0) ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_allones_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v26, -1 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vmv.v.i v8, -1 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_allones_v16i16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v25, -1 -; LMULMAX1-NEXT: vse16.v v25, (a0) +; LMULMAX1-NEXT: vmv.v.i v8, -1 +; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vse16.v v25, (a0) +; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: ret %a = insertelement <16 x i16> undef, i16 -1, i32 0 %b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer @@ -563,24 +563,24 @@ define void @splat_allones_v8i32(<8 x i32>* %x) { ; LMULMAX8-LABEL: splat_allones_v8i32: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX8-NEXT: vmv.v.i v26, -1 -; LMULMAX8-NEXT: vse32.v v26, (a0) +; LMULMAX8-NEXT: vmv.v.i v8, -1 +; LMULMAX8-NEXT: vse32.v v8, (a0) ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_allones_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v26, -1 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vmv.v.i v8, -1 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: splat_allones_v8i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v25, -1 -; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: vmv.v.i v8, -1 +; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: addi a0, a0, 16 -; LMULMAX1-NEXT: vse32.v v25, (a0) +; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: ret %a = insertelement <8 x i32> undef, i32 -1, i32 0 %b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer @@ -592,33 +592,33 @@ define void @splat_allones_v4i64(<4 x i64>* %x) { ; LMULMAX8-LABEL: splat_allones_v4i64: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX8-NEXT: vmv.v.i v26, -1 -; LMULMAX8-NEXT: vse64.v v26, (a0) +; LMULMAX8-NEXT: vmv.v.i v8, -1 +; LMULMAX8-NEXT: vse64.v v8, (a0) ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_allones_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v26, -1 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vmv.v.i v8, -1 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_allones_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.i v25, -1 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vmv.v.i v8, -1 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a0, a0, 16 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_allones_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.i v25, -1 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vmv.v.i v8, -1 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a0, a0, 16 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = insertelement <4 x i64> undef, i64 -1, i32 0 %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer @@ -634,44 +634,44 @@ define void @splat_allones_with_use_v4i64(<4 x i64>* %x) { ; LMULMAX8-LABEL: splat_allones_with_use_v4i64: ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX8-NEXT: vle64.v v26, (a0) -; LMULMAX8-NEXT: vadd.vi v26, v26, -1 -; LMULMAX8-NEXT: vse64.v v26, (a0) +; LMULMAX8-NEXT: vle64.v v8, (a0) +; LMULMAX8-NEXT: vadd.vi v8, v8, -1 +; LMULMAX8-NEXT: vse64.v v8, (a0) ; LMULMAX8-NEXT: ret ; ; LMULMAX2-LABEL: splat_allones_with_use_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vadd.vi v26, v26, -1 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vadd.vi v8, v8, -1 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_allones_with_use_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a1) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a1) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.i v27, -1 +; LMULMAX1-RV32-NEXT: vmv.v.i v10, -1 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a1) +; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_allones_with_use_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v25, (a1) -; LMULMAX1-RV64-NEXT: vle64.v v26, (a0) -; LMULMAX1-RV64-NEXT: vadd.vi v25, v25, -1 -; LMULMAX1-RV64-NEXT: vadd.vi v26, v26, -1 -; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v25, (a1) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a1) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a0) +; LMULMAX1-RV64-NEXT: vadd.vi v8, v8, -1 +; LMULMAX1-RV64-NEXT: vadd.vi v9, v9, -1 +; LMULMAX1-RV64-NEXT: vse64.v v9, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v8, (a1) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = add <4 x i64> %a, @@ -703,80 +703,80 @@ define void @vadd_vx_v16i64(<16 x i64>* %a, i64 %b, <16 x i64>* %c) { ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: addi a4, a0, 64 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle64.v v26, (a4) +; LMULMAX2-RV32-NEXT: vle64.v v8, (a4) ; LMULMAX2-RV32-NEXT: addi a4, a0, 96 -; LMULMAX2-RV32-NEXT: vle64.v v28, (a4) -; LMULMAX2-RV32-NEXT: vle64.v v30, (a0) +; LMULMAX2-RV32-NEXT: vle64.v v10, (a4) +; LMULMAX2-RV32-NEXT: vle64.v v12, (a0) ; LMULMAX2-RV32-NEXT: addi a0, a0, 32 -; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) +; LMULMAX2-RV32-NEXT: vle64.v v14, (a0) ; LMULMAX2-RV32-NEXT: addi a0, zero, 85 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a0 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v10, a2 -; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a1, v0 +; LMULMAX2-RV32-NEXT: vmv.v.x v16, a2 +; LMULMAX2-RV32-NEXT: vmerge.vxm v16, v16, a1, v0 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10 -; LMULMAX2-RV32-NEXT: vadd.vv v30, v30, v10 -; LMULMAX2-RV32-NEXT: vadd.vv v28, v28, v10 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v10 +; LMULMAX2-RV32-NEXT: vadd.vv v14, v14, v16 +; LMULMAX2-RV32-NEXT: vadd.vv v12, v12, v16 +; LMULMAX2-RV32-NEXT: vadd.vv v10, v10, v16 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v16 ; LMULMAX2-RV32-NEXT: addi a0, a3, 64 -; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi a0, a3, 96 -; LMULMAX2-RV32-NEXT: vse64.v v28, (a0) -; LMULMAX2-RV32-NEXT: vse64.v v30, (a3) +; LMULMAX2-RV32-NEXT: vse64.v v10, (a0) +; LMULMAX2-RV32-NEXT: vse64.v v12, (a3) ; LMULMAX2-RV32-NEXT: addi a0, a3, 32 -; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX2-RV32-NEXT: vse64.v v14, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX1-RV32-LABEL: vadd_vx_v16i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: addi a4, a0, 96 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a4) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a4) ; LMULMAX1-RV32-NEXT: addi a4, a0, 112 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a4) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a4) ; LMULMAX1-RV32-NEXT: addi a4, a0, 64 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a4) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a4) ; LMULMAX1-RV32-NEXT: addi a4, a0, 80 -; LMULMAX1-RV32-NEXT: vle64.v v28, (a4) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a4) ; LMULMAX1-RV32-NEXT: addi a4, a0, 32 -; LMULMAX1-RV32-NEXT: vle64.v v29, (a4) +; LMULMAX1-RV32-NEXT: vle64.v v12, (a4) ; LMULMAX1-RV32-NEXT: addi a4, a0, 48 -; LMULMAX1-RV32-NEXT: vle64.v v30, (a4) -; LMULMAX1-RV32-NEXT: vle64.v v31, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v13, (a4) +; LMULMAX1-RV32-NEXT: vle64.v v14, (a0) ; LMULMAX1-RV32-NEXT: addi a0, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v15, (a0) ; LMULMAX1-RV32-NEXT: addi a0, zero, 5 ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX1-RV32-NEXT: vmv.s.x v0, a0 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v9, a2 -; LMULMAX1-RV32-NEXT: vmerge.vxm v9, v9, a1, v0 +; LMULMAX1-RV32-NEXT: vmv.v.x v16, a2 +; LMULMAX1-RV32-NEXT: vmerge.vxm v16, v16, a1, v0 ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v9 -; LMULMAX1-RV32-NEXT: vadd.vv v31, v31, v9 -; LMULMAX1-RV32-NEXT: vadd.vv v30, v30, v9 -; LMULMAX1-RV32-NEXT: vadd.vv v29, v29, v9 -; LMULMAX1-RV32-NEXT: vadd.vv v28, v28, v9 -; LMULMAX1-RV32-NEXT: vadd.vv v27, v27, v9 -; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v9 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v9 +; LMULMAX1-RV32-NEXT: vadd.vv v15, v15, v16 +; LMULMAX1-RV32-NEXT: vadd.vv v14, v14, v16 +; LMULMAX1-RV32-NEXT: vadd.vv v13, v13, v16 +; LMULMAX1-RV32-NEXT: vadd.vv v12, v12, v16 +; LMULMAX1-RV32-NEXT: vadd.vv v11, v11, v16 +; LMULMAX1-RV32-NEXT: vadd.vv v10, v10, v16 +; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v16 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v16 ; LMULMAX1-RV32-NEXT: addi a0, a3, 96 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a0, a3, 112 -; LMULMAX1-RV32-NEXT: vse64.v v26, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a0) ; LMULMAX1-RV32-NEXT: addi a0, a3, 64 -; LMULMAX1-RV32-NEXT: vse64.v v27, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v10, (a0) ; LMULMAX1-RV32-NEXT: addi a0, a3, 80 -; LMULMAX1-RV32-NEXT: vse64.v v28, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v11, (a0) ; LMULMAX1-RV32-NEXT: addi a0, a3, 32 -; LMULMAX1-RV32-NEXT: vse64.v v29, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v12, (a0) ; LMULMAX1-RV32-NEXT: addi a0, a3, 48 -; LMULMAX1-RV32-NEXT: vse64.v v30, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v31, (a3) +; LMULMAX1-RV32-NEXT: vse64.v v13, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v14, (a3) ; LMULMAX1-RV32-NEXT: addi a0, a3, 16 -; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v15, (a0) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX8-RV64-LABEL: vadd_vx_v16i64: @@ -791,66 +791,66 @@ define void @vadd_vx_v16i64(<16 x i64>* %a, i64 %b, <16 x i64>* %c) { ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-RV64-NEXT: addi a3, a0, 96 -; LMULMAX2-RV64-NEXT: vle64.v v26, (a3) +; LMULMAX2-RV64-NEXT: vle64.v v8, (a3) ; LMULMAX2-RV64-NEXT: addi a3, a0, 32 -; LMULMAX2-RV64-NEXT: vle64.v v28, (a3) +; LMULMAX2-RV64-NEXT: vle64.v v10, (a3) ; LMULMAX2-RV64-NEXT: addi a3, a0, 64 -; LMULMAX2-RV64-NEXT: vle64.v v30, (a3) -; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) -; LMULMAX2-RV64-NEXT: vadd.vx v28, v28, a1 -; LMULMAX2-RV64-NEXT: vadd.vx v26, v26, a1 -; LMULMAX2-RV64-NEXT: vadd.vx v30, v30, a1 +; LMULMAX2-RV64-NEXT: vle64.v v12, (a3) +; LMULMAX2-RV64-NEXT: vle64.v v14, (a0) +; LMULMAX2-RV64-NEXT: vadd.vx v10, v10, a1 ; LMULMAX2-RV64-NEXT: vadd.vx v8, v8, a1 -; LMULMAX2-RV64-NEXT: vse64.v v8, (a2) +; LMULMAX2-RV64-NEXT: vadd.vx v12, v12, a1 +; LMULMAX2-RV64-NEXT: vadd.vx v14, v14, a1 +; LMULMAX2-RV64-NEXT: vse64.v v14, (a2) ; LMULMAX2-RV64-NEXT: addi a0, a2, 64 -; LMULMAX2-RV64-NEXT: vse64.v v30, (a0) +; LMULMAX2-RV64-NEXT: vse64.v v12, (a0) ; LMULMAX2-RV64-NEXT: addi a0, a2, 96 -; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi a0, a2, 32 -; LMULMAX2-RV64-NEXT: vse64.v v28, (a0) +; LMULMAX2-RV64-NEXT: vse64.v v10, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV64-LABEL: vadd_vx_v16i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a3, a0, 96 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a3) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a3) ; LMULMAX1-RV64-NEXT: addi a3, a0, 112 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a3) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a3) ; LMULMAX1-RV64-NEXT: addi a3, a0, 64 -; LMULMAX1-RV64-NEXT: vle64.v v28, (a3) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a3) ; LMULMAX1-RV64-NEXT: addi a3, a0, 48 -; LMULMAX1-RV64-NEXT: vle64.v v29, (a3) +; LMULMAX1-RV64-NEXT: vle64.v v12, (a3) ; LMULMAX1-RV64-NEXT: addi a3, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v30, (a3) +; LMULMAX1-RV64-NEXT: vle64.v v13, (a3) ; LMULMAX1-RV64-NEXT: addi a3, a0, 80 ; LMULMAX1-RV64-NEXT: addi a0, a0, 32 -; LMULMAX1-RV64-NEXT: vle64.v v31, (a0) -; LMULMAX1-RV64-NEXT: vle64.v v8, (a3) -; LMULMAX1-RV64-NEXT: vadd.vx v30, v30, a1 -; LMULMAX1-RV64-NEXT: vadd.vx v29, v29, a1 -; LMULMAX1-RV64-NEXT: vadd.vx v31, v31, a1 +; LMULMAX1-RV64-NEXT: vle64.v v14, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v15, (a3) +; LMULMAX1-RV64-NEXT: vadd.vx v13, v13, a1 +; LMULMAX1-RV64-NEXT: vadd.vx v12, v12, a1 +; LMULMAX1-RV64-NEXT: vadd.vx v14, v14, a1 +; LMULMAX1-RV64-NEXT: vadd.vx v15, v15, a1 +; LMULMAX1-RV64-NEXT: vadd.vx v11, v11, a1 +; LMULMAX1-RV64-NEXT: vadd.vx v10, v10, a1 +; LMULMAX1-RV64-NEXT: vadd.vx v9, v9, a1 ; LMULMAX1-RV64-NEXT: vadd.vx v8, v8, a1 -; LMULMAX1-RV64-NEXT: vadd.vx v28, v28, a1 -; LMULMAX1-RV64-NEXT: vadd.vx v27, v27, a1 -; LMULMAX1-RV64-NEXT: vadd.vx v26, v26, a1 -; LMULMAX1-RV64-NEXT: vadd.vx v25, v25, a1 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a2) +; LMULMAX1-RV64-NEXT: vse64.v v8, (a2) ; LMULMAX1-RV64-NEXT: addi a0, a2, 96 -; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a0) ; LMULMAX1-RV64-NEXT: addi a0, a2, 112 -; LMULMAX1-RV64-NEXT: vse64.v v27, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v10, (a0) ; LMULMAX1-RV64-NEXT: addi a0, a2, 64 -; LMULMAX1-RV64-NEXT: vse64.v v28, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v11, (a0) ; LMULMAX1-RV64-NEXT: addi a0, a2, 80 -; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v15, (a0) ; LMULMAX1-RV64-NEXT: addi a0, a2, 32 -; LMULMAX1-RV64-NEXT: vse64.v v31, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v14, (a0) ; LMULMAX1-RV64-NEXT: addi a0, a2, 48 -; LMULMAX1-RV64-NEXT: vse64.v v29, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v12, (a0) ; LMULMAX1-RV64-NEXT: addi a0, a2, 16 -; LMULMAX1-RV64-NEXT: vse64.v v30, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v13, (a0) ; LMULMAX1-RV64-NEXT: ret %va = load <16 x i64>, <16 x i64>* %a %head = insertelement <16 x i64> undef, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll index adc0b67a05b8eb78e87c4e5c5b989c60e403a446..aff029fe1df3014055dc9b49afddea184b34bdb3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll @@ -9,8 +9,8 @@ define void @gather_const_v16i8(<16 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, 12 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vlse8.v v25, (a1), zero -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vlse8.v v8, (a1), zero +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = extractelement <16 x i8> %a, i32 12 @@ -25,8 +25,8 @@ define void @gather_const_v8i16(<8 x i16>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, 10 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vlse16.v v25, (a1), zero -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vlse16.v v8, (a1), zero +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = extractelement <8 x i16> %a, i32 5 @@ -41,8 +41,8 @@ define void @gather_const_v4i32(<4 x i32>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, 12 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vlse32.v v25, (a1), zero -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vlse32.v v8, (a1), zero +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = extractelement <4 x i32> %a, i32 3 @@ -57,8 +57,8 @@ define void @gather_const_v2i64(<2 x i64>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, 8 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vlse64.v v25, (a1), zero -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vlse64.v v8, (a1), zero +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = extractelement <2 x i64> %a, i32 1 @@ -74,21 +74,21 @@ define void @gather_const_v64i8(<64 x i8>* %x) { ; LMULMAX4-NEXT: addi a1, a0, 32 ; LMULMAX4-NEXT: addi a2, zero, 64 ; LMULMAX4-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; LMULMAX4-NEXT: vlse8.v v28, (a1), zero -; LMULMAX4-NEXT: vse8.v v28, (a0) +; LMULMAX4-NEXT: vlse8.v v8, (a1), zero +; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: ret ; ; LMULMAX1-LABEL: gather_const_v64i8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: addi a1, a0, 32 ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vlse8.v v25, (a1), zero +; LMULMAX1-NEXT: vlse8.v v8, (a1), zero ; LMULMAX1-NEXT: addi a2, a0, 16 ; LMULMAX1-NEXT: addi a3, a0, 48 -; LMULMAX1-NEXT: vse8.v v25, (a1) -; LMULMAX1-NEXT: vse8.v v25, (a3) -; LMULMAX1-NEXT: vse8.v v25, (a0) -; LMULMAX1-NEXT: vse8.v v25, (a2) +; LMULMAX1-NEXT: vse8.v v8, (a1) +; LMULMAX1-NEXT: vse8.v v8, (a3) +; LMULMAX1-NEXT: vse8.v v8, (a0) +; LMULMAX1-NEXT: vse8.v v8, (a2) ; LMULMAX1-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = extractelement <64 x i8> %a, i32 32 @@ -104,22 +104,22 @@ define void @gather_const_v16i16(<32 x i16>* %x) { ; LMULMAX4-NEXT: addi a1, a0, 50 ; LMULMAX4-NEXT: addi a2, zero, 32 ; LMULMAX4-NEXT: vsetvli zero, a2, e16, m4, ta, mu -; LMULMAX4-NEXT: vlse16.v v28, (a1), zero -; LMULMAX4-NEXT: vse16.v v28, (a0) +; LMULMAX4-NEXT: vlse16.v v8, (a1), zero +; LMULMAX4-NEXT: vse16.v v8, (a0) ; LMULMAX4-NEXT: ret ; ; LMULMAX1-LABEL: gather_const_v16i16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: addi a1, a0, 50 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vlse16.v v25, (a1), zero +; LMULMAX1-NEXT: vlse16.v v8, (a1), zero ; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a2, a0, 48 ; LMULMAX1-NEXT: addi a3, a0, 32 -; LMULMAX1-NEXT: vse16.v v25, (a3) -; LMULMAX1-NEXT: vse16.v v25, (a2) -; LMULMAX1-NEXT: vse16.v v25, (a0) -; LMULMAX1-NEXT: vse16.v v25, (a1) +; LMULMAX1-NEXT: vse16.v v8, (a3) +; LMULMAX1-NEXT: vse16.v v8, (a2) +; LMULMAX1-NEXT: vse16.v v8, (a0) +; LMULMAX1-NEXT: vse16.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <32 x i16>, <32 x i16>* %x %b = extractelement <32 x i16> %a, i32 25 @@ -134,22 +134,22 @@ define void @gather_const_v16i32(<16 x i32>* %x) { ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: addi a1, a0, 36 ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; LMULMAX4-NEXT: vlse32.v v28, (a1), zero -; LMULMAX4-NEXT: vse32.v v28, (a0) +; LMULMAX4-NEXT: vlse32.v v8, (a1), zero +; LMULMAX4-NEXT: vse32.v v8, (a0) ; LMULMAX4-NEXT: ret ; ; LMULMAX1-LABEL: gather_const_v16i32: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: addi a1, a0, 36 ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-NEXT: vlse32.v v25, (a1), zero +; LMULMAX1-NEXT: vlse32.v v8, (a1), zero ; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a2, a0, 48 ; LMULMAX1-NEXT: addi a3, a0, 32 -; LMULMAX1-NEXT: vse32.v v25, (a3) -; LMULMAX1-NEXT: vse32.v v25, (a2) -; LMULMAX1-NEXT: vse32.v v25, (a0) -; LMULMAX1-NEXT: vse32.v v25, (a1) +; LMULMAX1-NEXT: vse32.v v8, (a3) +; LMULMAX1-NEXT: vse32.v v8, (a2) +; LMULMAX1-NEXT: vse32.v v8, (a0) +; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <16 x i32>, <16 x i32>* %x %b = extractelement <16 x i32> %a, i32 9 @@ -164,22 +164,22 @@ define void @gather_const_v8i64(<8 x i64>* %x) { ; LMULMAX4: # %bb.0: ; LMULMAX4-NEXT: addi a1, a0, 24 ; LMULMAX4-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; LMULMAX4-NEXT: vlse64.v v28, (a1), zero -; LMULMAX4-NEXT: vse64.v v28, (a0) +; LMULMAX4-NEXT: vlse64.v v8, (a1), zero +; LMULMAX4-NEXT: vse64.v v8, (a0) ; LMULMAX4-NEXT: ret ; ; LMULMAX1-LABEL: gather_const_v8i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: addi a1, a0, 24 ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vlse64.v v25, (a1), zero +; LMULMAX1-NEXT: vlse64.v v8, (a1), zero ; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a2, a0, 48 ; LMULMAX1-NEXT: addi a3, a0, 32 -; LMULMAX1-NEXT: vse64.v v25, (a3) -; LMULMAX1-NEXT: vse64.v v25, (a2) -; LMULMAX1-NEXT: vse64.v v25, (a0) -; LMULMAX1-NEXT: vse64.v v25, (a1) +; LMULMAX1-NEXT: vse64.v v8, (a3) +; LMULMAX1-NEXT: vse64.v v8, (a2) +; LMULMAX1-NEXT: vse64.v v8, (a0) +; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x i64>, <8 x i64>* %x %b = extractelement <8 x i64> %a, i32 3 @@ -194,8 +194,8 @@ define void @splat_concat_low(<4 x i16>* %x, <4 x i16>* %y, <8 x i16>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, a0, 2 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vlse16.v v25, (a0), zero -; CHECK-NEXT: vse16.v v25, (a2) +; CHECK-NEXT: vlse16.v v8, (a0), zero +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = load <4 x i16>, <4 x i16>* %y @@ -210,8 +210,8 @@ define void @splat_concat_high(<4 x i16>* %x, <4 x i16>* %y, <8 x i16>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, a1, 2 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vlse16.v v25, (a0), zero -; CHECK-NEXT: vse16.v v25, (a2) +; CHECK-NEXT: vlse16.v v8, (a0), zero +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = load <4 x i16>, <4 x i16>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll index be8e48c0e30c861c3bfe77eeeba402e2a142bed9..db42f369b77eff628ca378e6cee2190f2689599b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll @@ -8,10 +8,10 @@ define void @add_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: add_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -24,10 +24,10 @@ define void @add_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: add_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -40,10 +40,10 @@ define void @add_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: add_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -56,10 +56,10 @@ define void @add_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: add_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -72,10 +72,10 @@ define void @sub_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: sub_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsub.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -88,10 +88,10 @@ define void @sub_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: sub_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsub.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -104,10 +104,10 @@ define void @sub_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: sub_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vsub.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -120,10 +120,10 @@ define void @sub_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: sub_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vsub.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -136,10 +136,10 @@ define void @mul_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: mul_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vmul.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -152,10 +152,10 @@ define void @mul_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: mul_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vmul.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -168,10 +168,10 @@ define void @mul_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: mul_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vmul.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -184,10 +184,10 @@ define void @mul_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: mul_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vmul.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -200,10 +200,10 @@ define void @and_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: and_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vand.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -216,10 +216,10 @@ define void @and_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: and_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vand.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -232,10 +232,10 @@ define void @and_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: and_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vand.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -248,10 +248,10 @@ define void @and_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: and_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vand.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -264,10 +264,10 @@ define void @or_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: or_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vor.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -280,10 +280,10 @@ define void @or_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: or_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vor.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -296,10 +296,10 @@ define void @or_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: or_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vor.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -312,10 +312,10 @@ define void @or_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: or_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vor.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -328,10 +328,10 @@ define void @xor_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: xor_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vxor.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -344,10 +344,10 @@ define void @xor_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: xor_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vxor.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -360,10 +360,10 @@ define void @xor_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: xor_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vxor.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -376,10 +376,10 @@ define void @xor_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: xor_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vxor.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -392,10 +392,10 @@ define void @lshr_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: lshr_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsrl.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -408,10 +408,10 @@ define void @lshr_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: lshr_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsrl.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -424,10 +424,10 @@ define void @lshr_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: lshr_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vsrl.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -440,10 +440,10 @@ define void @lshr_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: lshr_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vsrl.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -456,10 +456,10 @@ define void @ashr_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: ashr_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsra.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -472,10 +472,10 @@ define void @ashr_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: ashr_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsra.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -488,10 +488,10 @@ define void @ashr_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: ashr_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vsra.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -504,10 +504,10 @@ define void @ashr_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: ashr_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vsra.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -520,10 +520,10 @@ define void @shl_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: shl_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsll.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -536,10 +536,10 @@ define void @shl_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: shl_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsll.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -552,10 +552,10 @@ define void @shl_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: shl_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vsll.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -568,10 +568,10 @@ define void @shl_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: shl_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vsll.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -584,10 +584,10 @@ define void @sdiv_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: sdiv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vdiv.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -600,10 +600,10 @@ define void @sdiv_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: sdiv_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vdiv.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -616,10 +616,10 @@ define void @sdiv_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: sdiv_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vdiv.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -632,10 +632,10 @@ define void @sdiv_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: sdiv_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vdiv.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -648,10 +648,10 @@ define void @srem_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: srem_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vrem.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -664,10 +664,10 @@ define void @srem_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: srem_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vrem.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -680,10 +680,10 @@ define void @srem_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: srem_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vrem.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -696,10 +696,10 @@ define void @srem_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: srem_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vrem.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -712,10 +712,10 @@ define void @udiv_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: udiv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vdivu.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -728,10 +728,10 @@ define void @udiv_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: udiv_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vdivu.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -744,10 +744,10 @@ define void @udiv_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: udiv_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vdivu.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -760,10 +760,10 @@ define void @udiv_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: udiv_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vdivu.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -776,10 +776,10 @@ define void @urem_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: urem_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vremu.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -792,10 +792,10 @@ define void @urem_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: urem_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vremu.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -808,10 +808,10 @@ define void @urem_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: urem_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vremu.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -824,10 +824,10 @@ define void @urem_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: urem_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vremu.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -840,95 +840,95 @@ define void @mulhu_v16i8(<16 x i8>* %x) { ; RV32-LABEL: mulhu_v16i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV32-NEXT: vle8.v v25, (a0) +; RV32-NEXT: vle8.v v8, (a0) ; RV32-NEXT: addi a1, zero, 513 ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV32-NEXT: vmv.s.x v0, a1 ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV32-NEXT: vmv.v.i v26, 4 -; RV32-NEXT: vmerge.vim v26, v26, 1, v0 +; RV32-NEXT: vmv.v.i v9, 4 +; RV32-NEXT: vmerge.vim v9, v9, 1, v0 ; RV32-NEXT: lui a1, 1 ; RV32-NEXT: addi a2, a1, 78 ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV32-NEXT: vmv.s.x v0, a2 ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV32-NEXT: vmerge.vim v26, v26, 3, v0 +; RV32-NEXT: vmerge.vim v9, v9, 3, v0 ; RV32-NEXT: lui a2, 8 ; RV32-NEXT: addi a2, a2, 304 ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV32-NEXT: vmv.s.x v0, a2 ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV32-NEXT: vmerge.vim v26, v26, 2, v0 +; RV32-NEXT: vmerge.vim v9, v9, 2, v0 ; RV32-NEXT: lui a2, 3 ; RV32-NEXT: addi a2, a2, -2044 ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV32-NEXT: vmv.s.x v0, a2 ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV32-NEXT: vmv.v.i v27, 0 +; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: addi a2, zero, -128 -; RV32-NEXT: vmerge.vxm v28, v27, a2, v0 +; RV32-NEXT: vmerge.vxm v11, v10, a2, v0 ; RV32-NEXT: addi a1, a1, 32 ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV32-NEXT: vmv.s.x v0, a1 ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV32-NEXT: lui a1, %hi(.LCPI52_0) ; RV32-NEXT: addi a1, a1, %lo(.LCPI52_0) -; RV32-NEXT: vle8.v v29, (a1) -; RV32-NEXT: vmerge.vim v27, v27, 1, v0 -; RV32-NEXT: vsrl.vv v27, v25, v27 -; RV32-NEXT: vmulhu.vv v27, v27, v29 -; RV32-NEXT: vsub.vv v25, v25, v27 -; RV32-NEXT: vmulhu.vv v25, v25, v28 -; RV32-NEXT: vadd.vv v25, v25, v27 -; RV32-NEXT: vsrl.vv v25, v25, v26 -; RV32-NEXT: vse8.v v25, (a0) +; RV32-NEXT: vle8.v v12, (a1) +; RV32-NEXT: vmerge.vim v10, v10, 1, v0 +; RV32-NEXT: vsrl.vv v10, v8, v10 +; RV32-NEXT: vmulhu.vv v10, v10, v12 +; RV32-NEXT: vsub.vv v8, v8, v10 +; RV32-NEXT: vmulhu.vv v8, v8, v11 +; RV32-NEXT: vadd.vv v8, v8, v10 +; RV32-NEXT: vsrl.vv v8, v8, v9 +; RV32-NEXT: vse8.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: mulhu_v16i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV64-NEXT: vle8.v v25, (a0) +; RV64-NEXT: vle8.v v8, (a0) ; RV64-NEXT: addi a1, zero, 513 ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV64-NEXT: vmv.s.x v0, a1 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV64-NEXT: vmv.v.i v26, 4 -; RV64-NEXT: vmerge.vim v26, v26, 1, v0 +; RV64-NEXT: vmv.v.i v9, 4 +; RV64-NEXT: vmerge.vim v9, v9, 1, v0 ; RV64-NEXT: lui a1, 1 ; RV64-NEXT: addiw a2, a1, 78 ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV64-NEXT: vmv.s.x v0, a2 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV64-NEXT: vmerge.vim v26, v26, 3, v0 +; RV64-NEXT: vmerge.vim v9, v9, 3, v0 ; RV64-NEXT: lui a2, 8 ; RV64-NEXT: addiw a2, a2, 304 ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV64-NEXT: vmv.s.x v0, a2 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV64-NEXT: vmerge.vim v26, v26, 2, v0 +; RV64-NEXT: vmerge.vim v9, v9, 2, v0 ; RV64-NEXT: lui a2, 3 ; RV64-NEXT: addiw a2, a2, -2044 ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV64-NEXT: vmv.s.x v0, a2 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV64-NEXT: vmv.v.i v27, 0 +; RV64-NEXT: vmv.v.i v10, 0 ; RV64-NEXT: addi a2, zero, -128 -; RV64-NEXT: vmerge.vxm v28, v27, a2, v0 +; RV64-NEXT: vmerge.vxm v11, v10, a2, v0 ; RV64-NEXT: addiw a1, a1, 32 ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV64-NEXT: vmv.s.x v0, a1 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64-NEXT: lui a1, %hi(.LCPI52_0) ; RV64-NEXT: addi a1, a1, %lo(.LCPI52_0) -; RV64-NEXT: vle8.v v29, (a1) -; RV64-NEXT: vmerge.vim v27, v27, 1, v0 -; RV64-NEXT: vsrl.vv v27, v25, v27 -; RV64-NEXT: vmulhu.vv v27, v27, v29 -; RV64-NEXT: vsub.vv v25, v25, v27 -; RV64-NEXT: vmulhu.vv v25, v25, v28 -; RV64-NEXT: vadd.vv v25, v25, v27 -; RV64-NEXT: vsrl.vv v25, v25, v26 -; RV64-NEXT: vse8.v v25, (a0) +; RV64-NEXT: vle8.v v12, (a1) +; RV64-NEXT: vmerge.vim v10, v10, 1, v0 +; RV64-NEXT: vsrl.vv v10, v8, v10 +; RV64-NEXT: vmulhu.vv v10, v10, v12 +; RV64-NEXT: vsub.vv v8, v8, v10 +; RV64-NEXT: vmulhu.vv v8, v8, v11 +; RV64-NEXT: vadd.vv v8, v8, v10 +; RV64-NEXT: vsrl.vv v8, v8, v9 +; RV64-NEXT: vse8.v v8, (a0) ; RV64-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = udiv <16 x i8> %a, @@ -940,36 +940,36 @@ define void @mulhu_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: mulhu_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: addi a1, zero, 1 -; CHECK-NEXT: vmv.s.x v26, a1 +; CHECK-NEXT: vmv.s.x v9, a1 ; CHECK-NEXT: addi a1, zero, 33 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.s.x v0, a1 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v27, 3 -; CHECK-NEXT: vmerge.vim v27, v27, 2, v0 +; CHECK-NEXT: vmv.v.i v10, 3 +; CHECK-NEXT: vmerge.vim v10, v10, 2, v0 ; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, mu -; CHECK-NEXT: vslideup.vi v27, v26, 6 +; CHECK-NEXT: vslideup.vi v10, v9, 6 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 +; CHECK-NEXT: vmv.v.i v11, 0 ; CHECK-NEXT: lui a1, 1048568 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, mu -; CHECK-NEXT: vmv1r.v v29, v28 -; CHECK-NEXT: vmv.s.x v29, a1 +; CHECK-NEXT: vmv1r.v v12, v11 +; CHECK-NEXT: vmv.s.x v12, a1 ; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, mu -; CHECK-NEXT: vslideup.vi v28, v26, 6 +; CHECK-NEXT: vslideup.vi v11, v9, 6 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: lui a1, %hi(.LCPI53_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI53_0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsrl.vv v28, v25, v28 -; CHECK-NEXT: vmulhu.vv v26, v28, v26 -; CHECK-NEXT: vsub.vv v25, v25, v26 -; CHECK-NEXT: vmulhu.vv v25, v25, v29 -; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vsrl.vv v25, v25, v27 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vsrl.vv v11, v8, v11 +; CHECK-NEXT: vmulhu.vv v9, v11, v9 +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: vmulhu.vv v8, v8, v12 +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = udiv <8 x i16> %a, @@ -981,28 +981,28 @@ define void @mulhu_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: mulhu_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: lui a1, 524288 -; CHECK-NEXT: vmv.s.x v26, a1 -; CHECK-NEXT: vmv.v.i v27, 0 +; CHECK-NEXT: vmv.s.x v9, a1 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vi v27, v26, 2 +; CHECK-NEXT: vslideup.vi v10, v9, 2 ; CHECK-NEXT: lui a1, %hi(.LCPI54_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI54_0) ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vmulhu.vv v26, v25, v26 -; CHECK-NEXT: vsub.vv v25, v25, v26 -; CHECK-NEXT: vmulhu.vv v25, v25, v27 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vmulhu.vv v9, v8, v9 +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: vmulhu.vv v8, v8, v10 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: addi a1, zero, 1 -; CHECK-NEXT: vmv.s.x v26, a1 -; CHECK-NEXT: vmv.v.i v27, 2 +; CHECK-NEXT: vmv.s.x v9, a1 +; CHECK-NEXT: vmv.v.i v10, 2 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vi v27, v26, 3 +; CHECK-NEXT: vslideup.vi v10, v9, 3 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vsrl.vv v25, v25, v27 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = udiv <4 x i32> %a, @@ -1014,26 +1014,26 @@ define void @mulhu_v2i64(<2 x i64>* %x) { ; RV32-LABEL: mulhu_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: lui a1, %hi(.LCPI55_0) ; RV32-NEXT: addi a1, a1, %lo(.LCPI55_0) ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vle32.v v26, (a1) +; RV32-NEXT: vle32.v v9, (a1) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vmulhu.vv v25, v25, v26 +; RV32-NEXT: vmulhu.vv v8, v8, v9 ; RV32-NEXT: lui a1, %hi(.LCPI55_1) ; RV32-NEXT: addi a1, a1, %lo(.LCPI55_1) ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vle32.v v26, (a1) +; RV32-NEXT: vle32.v v9, (a1) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vsrl.vv v25, v25, v26 -; RV32-NEXT: vse64.v v25, (a0) +; RV32-NEXT: vsrl.vv v8, v8, v9 +; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: mulhu_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: lui a1, 1035469 ; RV64-NEXT: addiw a1, a1, -819 ; RV64-NEXT: slli a1, a1, 12 @@ -1042,7 +1042,7 @@ define void @mulhu_v2i64(<2 x i64>* %x) { ; RV64-NEXT: addi a1, a1, -819 ; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: addi a1, a1, -819 -; RV64-NEXT: vmv.v.x v26, a1 +; RV64-NEXT: vmv.v.x v9, a1 ; RV64-NEXT: lui a1, 1026731 ; RV64-NEXT: addiw a1, a1, -1365 ; RV64-NEXT: slli a1, a1, 12 @@ -1052,13 +1052,13 @@ define void @mulhu_v2i64(<2 x i64>* %x) { ; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: addi a1, a1, -1365 ; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; RV64-NEXT: vmv.s.x v26, a1 +; RV64-NEXT: vmv.s.x v9, a1 ; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; RV64-NEXT: vmulhu.vv v25, v25, v26 -; RV64-NEXT: vid.v v26 -; RV64-NEXT: vadd.vi v26, v26, 1 -; RV64-NEXT: vsrl.vv v25, v25, v26 -; RV64-NEXT: vse64.v v25, (a0) +; RV64-NEXT: vmulhu.vv v8, v8, v9 +; RV64-NEXT: vid.v v9 +; RV64-NEXT: vadd.vi v9, v9, 1 +; RV64-NEXT: vsrl.vv v8, v8, v9 +; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = udiv <2 x i64> %a, @@ -1070,41 +1070,41 @@ define void @mulhs_v16i8(<16 x i8>* %x) { ; RV32-LABEL: mulhs_v16i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV32-NEXT: vle8.v v25, (a0) +; RV32-NEXT: vle8.v v8, (a0) ; RV32-NEXT: lui a1, 5 ; RV32-NEXT: addi a1, a1, -1452 ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV32-NEXT: vmv.s.x v0, a1 ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV32-NEXT: vmv.v.i v26, 7 -; RV32-NEXT: vmerge.vim v26, v26, 1, v0 +; RV32-NEXT: vmv.v.i v9, 7 +; RV32-NEXT: vmerge.vim v9, v9, 1, v0 ; RV32-NEXT: addi a1, zero, -123 -; RV32-NEXT: vmv.v.x v27, a1 +; RV32-NEXT: vmv.v.x v10, a1 ; RV32-NEXT: addi a1, zero, 57 -; RV32-NEXT: vmerge.vxm v27, v27, a1, v0 -; RV32-NEXT: vmulhu.vv v25, v25, v27 -; RV32-NEXT: vsrl.vv v25, v25, v26 -; RV32-NEXT: vse8.v v25, (a0) +; RV32-NEXT: vmerge.vxm v10, v10, a1, v0 +; RV32-NEXT: vmulhu.vv v8, v8, v10 +; RV32-NEXT: vsrl.vv v8, v8, v9 +; RV32-NEXT: vse8.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: mulhs_v16i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV64-NEXT: vle8.v v25, (a0) +; RV64-NEXT: vle8.v v8, (a0) ; RV64-NEXT: lui a1, 5 ; RV64-NEXT: addiw a1, a1, -1452 ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV64-NEXT: vmv.s.x v0, a1 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV64-NEXT: vmv.v.i v26, 7 -; RV64-NEXT: vmerge.vim v26, v26, 1, v0 +; RV64-NEXT: vmv.v.i v9, 7 +; RV64-NEXT: vmerge.vim v9, v9, 1, v0 ; RV64-NEXT: addi a1, zero, -123 -; RV64-NEXT: vmv.v.x v27, a1 +; RV64-NEXT: vmv.v.x v10, a1 ; RV64-NEXT: addi a1, zero, 57 -; RV64-NEXT: vmerge.vxm v27, v27, a1, v0 -; RV64-NEXT: vmulhu.vv v25, v25, v27 -; RV64-NEXT: vsrl.vv v25, v25, v26 -; RV64-NEXT: vse8.v v25, (a0) +; RV64-NEXT: vmerge.vxm v10, v10, a1, v0 +; RV64-NEXT: vmulhu.vv v8, v8, v10 +; RV64-NEXT: vsrl.vv v8, v8, v9 +; RV64-NEXT: vse8.v v8, (a0) ; RV64-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = udiv <16 x i8> %a, @@ -1116,43 +1116,43 @@ define void @mulhs_v8i16(<8 x i16>* %x) { ; RV32-LABEL: mulhs_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV32-NEXT: vle16.v v25, (a0) +; RV32-NEXT: vle16.v v8, (a0) ; RV32-NEXT: addi a1, zero, 105 ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vmv.s.x v0, a1 ; RV32-NEXT: lui a1, 5 ; RV32-NEXT: addi a1, a1, -1755 ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v26, a1 +; RV32-NEXT: vmv.v.x v9, a1 ; RV32-NEXT: lui a1, 1048571 ; RV32-NEXT: addi a1, a1, 1755 -; RV32-NEXT: vmerge.vxm v26, v26, a1, v0 -; RV32-NEXT: vmulh.vv v25, v25, v26 -; RV32-NEXT: vsra.vi v25, v25, 1 -; RV32-NEXT: vsrl.vi v26, v25, 15 -; RV32-NEXT: vadd.vv v25, v25, v26 -; RV32-NEXT: vse16.v v25, (a0) +; RV32-NEXT: vmerge.vxm v9, v9, a1, v0 +; RV32-NEXT: vmulh.vv v8, v8, v9 +; RV32-NEXT: vsra.vi v8, v8, 1 +; RV32-NEXT: vsrl.vi v9, v8, 15 +; RV32-NEXT: vadd.vv v8, v8, v9 +; RV32-NEXT: vse16.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: mulhs_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV64-NEXT: vle16.v v25, (a0) +; RV64-NEXT: vle16.v v8, (a0) ; RV64-NEXT: addi a1, zero, 105 ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV64-NEXT: vmv.s.x v0, a1 ; RV64-NEXT: lui a1, 5 ; RV64-NEXT: addiw a1, a1, -1755 ; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v26, a1 +; RV64-NEXT: vmv.v.x v9, a1 ; RV64-NEXT: lui a1, 1048571 ; RV64-NEXT: addiw a1, a1, 1755 -; RV64-NEXT: vmerge.vxm v26, v26, a1, v0 -; RV64-NEXT: vmulh.vv v25, v25, v26 -; RV64-NEXT: vsra.vi v25, v25, 1 -; RV64-NEXT: vsrl.vi v26, v25, 15 -; RV64-NEXT: vadd.vv v25, v25, v26 -; RV64-NEXT: vse16.v v25, (a0) +; RV64-NEXT: vmerge.vxm v9, v9, a1, v0 +; RV64-NEXT: vmulh.vv v8, v8, v9 +; RV64-NEXT: vsra.vi v8, v8, 1 +; RV64-NEXT: vsrl.vi v9, v8, 15 +; RV64-NEXT: vadd.vv v8, v8, v9 +; RV64-NEXT: vse16.v v8, (a0) ; RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = sdiv <8 x i16> %a, @@ -1164,28 +1164,28 @@ define void @mulhs_v4i32(<4 x i32>* %x) { ; RV32-LABEL: mulhs_v4i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vle32.v v25, (a0) +; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: addi a1, zero, 5 ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vmv.s.x v0, a1 ; RV32-NEXT: lui a1, 419430 ; RV32-NEXT: addi a1, a1, 1639 ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v26, a1 +; RV32-NEXT: vmv.v.x v9, a1 ; RV32-NEXT: lui a1, 629146 ; RV32-NEXT: addi a1, a1, -1639 -; RV32-NEXT: vmerge.vxm v26, v26, a1, v0 -; RV32-NEXT: vmulh.vv v25, v25, v26 -; RV32-NEXT: vsrl.vi v26, v25, 31 -; RV32-NEXT: vsra.vi v25, v25, 1 -; RV32-NEXT: vadd.vv v25, v25, v26 -; RV32-NEXT: vse32.v v25, (a0) +; RV32-NEXT: vmerge.vxm v9, v9, a1, v0 +; RV32-NEXT: vmulh.vv v8, v8, v9 +; RV32-NEXT: vsrl.vi v9, v8, 31 +; RV32-NEXT: vsra.vi v8, v8, 1 +; RV32-NEXT: vadd.vv v8, v8, v9 +; RV32-NEXT: vse32.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: mulhs_v4i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV64-NEXT: vle32.v v25, (a0) +; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: lui a1, 13107 ; RV64-NEXT: addiw a1, a1, 819 ; RV64-NEXT: slli a1, a1, 12 @@ -1195,13 +1195,13 @@ define void @mulhs_v4i32(<4 x i32>* %x) { ; RV64-NEXT: slli a1, a1, 13 ; RV64-NEXT: addi a1, a1, -1639 ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v26, a1 +; RV64-NEXT: vmv.v.x v9, a1 ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV64-NEXT: vmulh.vv v25, v25, v26 -; RV64-NEXT: vsra.vi v25, v25, 1 -; RV64-NEXT: vsrl.vi v26, v25, 31 -; RV64-NEXT: vadd.vv v25, v25, v26 -; RV64-NEXT: vse32.v v25, (a0) +; RV64-NEXT: vmulh.vv v8, v8, v9 +; RV64-NEXT: vsra.vi v8, v8, 1 +; RV64-NEXT: vsrl.vi v9, v8, 31 +; RV64-NEXT: vadd.vv v8, v8, v9 +; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = sdiv <4 x i32> %a, @@ -1213,40 +1213,40 @@ define void @mulhs_v2i64(<2 x i64>* %x) { ; RV32-LABEL: mulhs_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: addi a2, a1, 1365 ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v26, a2 +; RV32-NEXT: vmv.v.x v9, a2 ; RV32-NEXT: addi a1, a1, 1366 ; RV32-NEXT: vsetvli zero, zero, e32, m1, tu, mu -; RV32-NEXT: vmv.s.x v26, a1 +; RV32-NEXT: vmv.s.x v9, a1 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vmulh.vv v26, v25, v26 +; RV32-NEXT: vmulh.vv v9, v8, v9 ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vid.v v27 -; RV32-NEXT: vsrl.vi v27, v27, 1 -; RV32-NEXT: vrsub.vi v27, v27, 0 +; RV32-NEXT: vid.v v10 +; RV32-NEXT: vsrl.vi v10, v10, 1 +; RV32-NEXT: vrsub.vi v10, v10, 0 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vmadd.vv v27, v25, v26 +; RV32-NEXT: vmadd.vv v10, v8, v9 ; RV32-NEXT: addi a1, zero, 1 ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vmv.s.x v25, a1 -; RV32-NEXT: vmv.v.i v26, 0 +; RV32-NEXT: vmv.s.x v8, a1 +; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vsetivli zero, 3, e32, m1, tu, mu -; RV32-NEXT: vslideup.vi v26, v25, 2 +; RV32-NEXT: vslideup.vi v9, v8, 2 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vsra.vv v25, v27, v26 +; RV32-NEXT: vsra.vv v8, v10, v9 ; RV32-NEXT: addi a1, zero, 63 -; RV32-NEXT: vsrl.vx v26, v27, a1 -; RV32-NEXT: vadd.vv v25, v25, v26 -; RV32-NEXT: vse64.v v25, (a0) +; RV32-NEXT: vsrl.vx v9, v10, a1 +; RV32-NEXT: vadd.vv v8, v8, v9 +; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: mulhs_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: lui a1, 21845 ; RV64-NEXT: addiw a1, a1, 1365 ; RV64-NEXT: slli a1, a1, 12 @@ -1255,20 +1255,20 @@ define void @mulhs_v2i64(<2 x i64>* %x) { ; RV64-NEXT: addi a1, a1, 1365 ; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: addi a2, a1, 1365 -; RV64-NEXT: vmv.v.x v26, a2 +; RV64-NEXT: vmv.v.x v9, a2 ; RV64-NEXT: addi a1, a1, 1366 ; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; RV64-NEXT: vmv.s.x v26, a1 +; RV64-NEXT: vmv.s.x v9, a1 ; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; RV64-NEXT: vmulh.vv v26, v25, v26 -; RV64-NEXT: vid.v v27 -; RV64-NEXT: vrsub.vi v28, v27, 0 -; RV64-NEXT: vmadd.vv v28, v25, v26 +; RV64-NEXT: vmulh.vv v9, v8, v9 +; RV64-NEXT: vid.v v10 +; RV64-NEXT: vrsub.vi v11, v10, 0 +; RV64-NEXT: vmadd.vv v11, v8, v9 ; RV64-NEXT: addi a1, zero, 63 -; RV64-NEXT: vsrl.vx v25, v28, a1 -; RV64-NEXT: vsra.vv v26, v28, v27 -; RV64-NEXT: vadd.vv v25, v26, v25 -; RV64-NEXT: vse64.v v25, (a0) +; RV64-NEXT: vsrl.vx v8, v11, a1 +; RV64-NEXT: vsra.vv v9, v11, v10 +; RV64-NEXT: vadd.vv v8, v9, v8 +; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = sdiv <2 x i64> %a, @@ -1280,10 +1280,10 @@ define void @smin_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: smin_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vmin.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -1297,10 +1297,10 @@ define void @smin_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: smin_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vmin.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -1314,10 +1314,10 @@ define void @smin_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: smin_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vmin.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -1331,10 +1331,10 @@ define void @smin_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: smin_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vmin.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -1348,10 +1348,10 @@ define void @smax_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: smax_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vmax.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -1365,10 +1365,10 @@ define void @smax_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: smax_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vmax.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -1382,10 +1382,10 @@ define void @smax_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: smax_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vmax.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -1399,10 +1399,10 @@ define void @smax_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: smax_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vmax.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -1416,10 +1416,10 @@ define void @umin_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: umin_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vminu.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -1433,10 +1433,10 @@ define void @umin_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: umin_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vminu.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -1450,10 +1450,10 @@ define void @umin_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: umin_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vminu.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -1467,10 +1467,10 @@ define void @umin_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: umin_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vminu.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -1484,10 +1484,10 @@ define void @umax_v16i8(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: umax_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vmaxu.vv v25, v25, v26 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v9, (a1) +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -1501,10 +1501,10 @@ define void @umax_v8i16(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: umax_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vmaxu.vv v25, v25, v26 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -1518,10 +1518,10 @@ define void @umax_v4i32(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: umax_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vmaxu.vv v25, v25, v26 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -1535,10 +1535,10 @@ define void @umax_v2i64(<2 x i64>* %x, <2 x i64>* %y) { ; CHECK-LABEL: umax_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vmaxu.vv v25, v25, v26 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vle64.v v9, (a1) +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = load <2 x i64>, <2 x i64>* %y @@ -1553,40 +1553,40 @@ define void @add_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vadd.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vadd.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: add_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: add_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vadd.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -1599,40 +1599,40 @@ define void @add_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: add_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vadd.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vadd.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: add_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: add_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vadd.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -1645,40 +1645,40 @@ define void @add_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: add_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vadd.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vadd.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: add_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: add_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vadd.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -1691,40 +1691,40 @@ define void @add_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: add_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vadd.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vadd.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: add_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: add_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vadd.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -1738,40 +1738,40 @@ define void @sub_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vsub.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vsub.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sub_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sub_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsub.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsub.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -1784,40 +1784,40 @@ define void @sub_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: sub_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vsub.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vsub.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sub_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sub_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsub.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsub.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -1830,40 +1830,40 @@ define void @sub_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: sub_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vsub.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vsub.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sub_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sub_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsub.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsub.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -1876,40 +1876,40 @@ define void @sub_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: sub_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vsub.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vsub.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sub_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sub_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsub.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsub.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsub.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -1923,40 +1923,40 @@ define void @mul_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vmul.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vmul.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mul_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmul.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmul.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmul.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mul_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmul.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmul.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmul.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmul.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -1969,40 +1969,40 @@ define void @mul_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: mul_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vmul.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vmul.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mul_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmul.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmul.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmul.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mul_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmul.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmul.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmul.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmul.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -2015,40 +2015,40 @@ define void @mul_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: mul_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vmul.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vmul.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mul_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmul.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmul.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmul.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mul_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmul.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmul.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmul.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmul.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -2061,40 +2061,40 @@ define void @mul_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: mul_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vmul.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vmul.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mul_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmul.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmul.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmul.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmul.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mul_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmul.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmul.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmul.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmul.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -2108,40 +2108,40 @@ define void @and_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vand.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vand.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: and_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: and_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vand.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vand.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vand.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -2154,40 +2154,40 @@ define void @and_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: and_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vand.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vand.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: and_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: and_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vand.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vand.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vand.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -2200,40 +2200,40 @@ define void @and_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: and_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vand.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vand.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: and_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: and_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vand.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vand.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vand.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -2246,40 +2246,40 @@ define void @and_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: and_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vand.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vand.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: and_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vand.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vand.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: and_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vand.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vand.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vand.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -2293,40 +2293,40 @@ define void @or_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vor.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vor.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: or_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: or_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -2339,40 +2339,40 @@ define void @or_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: or_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vor.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vor.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: or_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: or_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -2385,40 +2385,40 @@ define void @or_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: or_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vor.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vor.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: or_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: or_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -2431,40 +2431,40 @@ define void @or_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: or_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vor.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vor.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: or_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vor.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vor.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: or_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vor.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -2478,40 +2478,40 @@ define void @xor_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vxor.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vxor.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: xor_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vxor.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vxor.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vxor.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vxor.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: xor_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vxor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vxor.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vxor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vxor.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -2524,40 +2524,40 @@ define void @xor_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: xor_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vxor.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vxor.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: xor_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vxor.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vxor.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vxor.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vxor.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: xor_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vxor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vxor.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vxor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vxor.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -2570,40 +2570,40 @@ define void @xor_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: xor_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vxor.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vxor.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: xor_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vxor.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vxor.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vxor.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vxor.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: xor_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vxor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vxor.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vxor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vxor.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -2616,40 +2616,40 @@ define void @xor_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: xor_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vxor.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vxor.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: xor_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vxor.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vxor.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vxor.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vxor.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: xor_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vxor.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vxor.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vxor.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vxor.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -2663,40 +2663,40 @@ define void @lshr_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vsrl.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vsrl.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: lshr_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsrl.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsrl.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsrl.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: lshr_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsrl.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsrl.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsrl.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -2709,40 +2709,40 @@ define void @lshr_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: lshr_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vsrl.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vsrl.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: lshr_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsrl.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsrl.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsrl.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: lshr_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsrl.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsrl.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsrl.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -2755,40 +2755,40 @@ define void @lshr_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: lshr_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vsrl.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vsrl.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: lshr_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsrl.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsrl.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsrl.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: lshr_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsrl.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsrl.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsrl.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -2801,40 +2801,40 @@ define void @lshr_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: lshr_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vsrl.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vsrl.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: lshr_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsrl.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsrl.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsrl.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: lshr_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsrl.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsrl.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsrl.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -2848,40 +2848,40 @@ define void @ashr_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vsra.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vsra.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ashr_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsra.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsra.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsra.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsra.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ashr_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsra.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsra.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsra.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -2894,40 +2894,40 @@ define void @ashr_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: ashr_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vsra.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vsra.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ashr_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsra.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsra.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsra.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsra.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ashr_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsra.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsra.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsra.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -2940,40 +2940,40 @@ define void @ashr_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: ashr_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vsra.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vsra.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ashr_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsra.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsra.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsra.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsra.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ashr_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsra.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsra.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsra.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -2986,40 +2986,40 @@ define void @ashr_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: ashr_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vsra.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vsra.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: ashr_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsra.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsra.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsra.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsra.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: ashr_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsra.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsra.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsra.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -3033,40 +3033,40 @@ define void @shl_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vsll.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vsll.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: shl_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsll.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsll.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsll.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsll.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: shl_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsll.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsll.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsll.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsll.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -3079,40 +3079,40 @@ define void @shl_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: shl_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vsll.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vsll.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: shl_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsll.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsll.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsll.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsll.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: shl_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsll.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsll.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsll.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsll.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -3125,40 +3125,40 @@ define void @shl_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: shl_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vsll.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vsll.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: shl_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsll.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsll.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsll.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsll.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: shl_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsll.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsll.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsll.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsll.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -3171,40 +3171,40 @@ define void @shl_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: shl_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vsll.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vsll.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: shl_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vsll.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsll.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vsll.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsll.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: shl_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vsll.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vsll.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vsll.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vsll.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -3218,40 +3218,40 @@ define void @sdiv_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vdiv.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vdiv.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sdiv_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vdiv.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vdiv.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vdiv.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sdiv_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vdiv.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vdiv.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vdiv.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -3264,40 +3264,40 @@ define void @sdiv_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: sdiv_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vdiv.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vdiv.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sdiv_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vdiv.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vdiv.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vdiv.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sdiv_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vdiv.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vdiv.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vdiv.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -3310,40 +3310,40 @@ define void @sdiv_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: sdiv_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vdiv.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vdiv.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sdiv_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vdiv.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vdiv.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vdiv.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sdiv_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vdiv.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vdiv.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vdiv.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -3356,40 +3356,40 @@ define void @sdiv_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: sdiv_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vdiv.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vdiv.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: sdiv_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vdiv.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vdiv.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vdiv.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: sdiv_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vdiv.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vdiv.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vdiv.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -3403,40 +3403,40 @@ define void @srem_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vrem.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vrem.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: srem_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vrem.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vrem.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vrem.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vrem.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: srem_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vrem.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vrem.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vrem.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vrem.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -3449,40 +3449,40 @@ define void @srem_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: srem_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vrem.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vrem.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: srem_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vrem.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vrem.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vrem.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vrem.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: srem_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vrem.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vrem.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vrem.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vrem.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -3495,40 +3495,40 @@ define void @srem_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: srem_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vrem.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vrem.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: srem_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vrem.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vrem.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vrem.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vrem.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: srem_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vrem.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vrem.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vrem.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vrem.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -3541,40 +3541,40 @@ define void @srem_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: srem_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vrem.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vrem.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: srem_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vrem.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vrem.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vrem.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vrem.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: srem_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vrem.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vrem.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vrem.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vrem.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -3588,40 +3588,40 @@ define void @udiv_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vdivu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vdivu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: udiv_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vdivu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vdivu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vdivu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: udiv_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vdivu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vdivu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vdivu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -3634,40 +3634,40 @@ define void @udiv_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: udiv_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vdivu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vdivu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: udiv_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vdivu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vdivu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vdivu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: udiv_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vdivu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vdivu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vdivu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -3680,40 +3680,40 @@ define void @udiv_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: udiv_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vdivu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vdivu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: udiv_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vdivu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vdivu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vdivu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: udiv_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vdivu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vdivu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vdivu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -3726,40 +3726,40 @@ define void @udiv_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: udiv_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vdivu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vdivu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: udiv_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vdivu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vdivu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vdivu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: udiv_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vdivu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vdivu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vdivu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -3773,40 +3773,40 @@ define void @urem_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vremu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vremu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: urem_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vremu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vremu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vremu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vremu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: urem_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vremu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vremu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vremu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vremu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -3819,40 +3819,40 @@ define void @urem_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: urem_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vremu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vremu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: urem_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vremu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vremu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vremu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vremu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: urem_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vremu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vremu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vremu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vremu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -3865,40 +3865,40 @@ define void @urem_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: urem_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vremu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vremu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: urem_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vremu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vremu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vremu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vremu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: urem_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vremu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vremu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vremu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vremu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -3911,40 +3911,40 @@ define void @urem_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: urem_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vremu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vremu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: urem_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vremu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vremu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vremu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vremu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: urem_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vremu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vremu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vremu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vremu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -3957,25 +3957,25 @@ define void @extract_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: extract_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vadd.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vadd.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-LABEL: extract_v4i64: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-NEXT: vle64.v v25, (a0) +; LMULMAX1-NEXT: vle64.v v8, (a0) ; LMULMAX1-NEXT: addi a2, a0, 16 -; LMULMAX1-NEXT: vle64.v v26, (a2) -; LMULMAX1-NEXT: vle64.v v27, (a1) +; LMULMAX1-NEXT: vle64.v v9, (a2) +; LMULMAX1-NEXT: vle64.v v10, (a1) ; LMULMAX1-NEXT: addi a1, a1, 16 -; LMULMAX1-NEXT: vle64.v v28, (a1) -; LMULMAX1-NEXT: vadd.vv v26, v26, v28 -; LMULMAX1-NEXT: vadd.vv v25, v25, v27 -; LMULMAX1-NEXT: vse64.v v25, (a0) -; LMULMAX1-NEXT: vse64.v v26, (a2) +; LMULMAX1-NEXT: vle64.v v11, (a1) +; LMULMAX1-NEXT: vadd.vv v9, v9, v11 +; LMULMAX1-NEXT: vadd.vv v8, v8, v10 +; LMULMAX1-NEXT: vse64.v v8, (a0) +; LMULMAX1-NEXT: vse64.v v9, (a2) ; LMULMAX1-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -3991,7 +3991,7 @@ define void @mulhu_v32i8(<32 x i8>* %x) { ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: addi a1, zero, 32 ; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle8.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX2-RV32-NEXT: lui a2, 66049 ; LMULMAX2-RV32-NEXT: addi a2, a2, 32 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu @@ -3999,49 +3999,49 @@ define void @mulhu_v32i8(<32 x i8>* %x) { ; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; LMULMAX2-RV32-NEXT: lui a2, %hi(.LCPI129_0) ; LMULMAX2-RV32-NEXT: addi a2, a2, %lo(.LCPI129_0) -; LMULMAX2-RV32-NEXT: vle8.v v28, (a2) -; LMULMAX2-RV32-NEXT: vmv.v.i v30, 0 -; LMULMAX2-RV32-NEXT: vmerge.vim v8, v30, 1, v0 -; LMULMAX2-RV32-NEXT: vsrl.vv v8, v26, v8 -; LMULMAX2-RV32-NEXT: vmulhu.vv v28, v8, v28 -; LMULMAX2-RV32-NEXT: vsub.vv v26, v26, v28 +; LMULMAX2-RV32-NEXT: vle8.v v10, (a2) +; LMULMAX2-RV32-NEXT: vmv.v.i v12, 0 +; LMULMAX2-RV32-NEXT: vmerge.vim v14, v12, 1, v0 +; LMULMAX2-RV32-NEXT: vsrl.vv v14, v8, v14 +; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v14, v10 +; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: lui a2, 163907 ; LMULMAX2-RV32-NEXT: addi a2, a2, -2044 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2 ; LMULMAX2-RV32-NEXT: addi a2, zero, -128 ; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmerge.vxm v30, v30, a2, v0 -; LMULMAX2-RV32-NEXT: vmulhu.vv v26, v26, v30 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28 +; LMULMAX2-RV32-NEXT: vmerge.vxm v12, v12, a2, v0 +; LMULMAX2-RV32-NEXT: vmulhu.vv v8, v8, v12 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: lui a2, 8208 ; LMULMAX2-RV32-NEXT: addi a2, a2, 513 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2 ; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.i v28, 4 -; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 1, v0 +; LMULMAX2-RV32-NEXT: vmv.v.i v10, 4 +; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX2-RV32-NEXT: lui a2, 66785 ; LMULMAX2-RV32-NEXT: addi a2, a2, 78 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2 ; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 3, v0 +; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 3, v0 ; LMULMAX2-RV32-NEXT: lui a2, 529160 ; LMULMAX2-RV32-NEXT: addi a2, a2, 304 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2 ; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 2, v0 -; LMULMAX2-RV32-NEXT: vsrl.vv v26, v26, v28 -; LMULMAX2-RV32-NEXT: vse8.v v26, (a0) +; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 2, v0 +; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vse8.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: mulhu_v32i8: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: addi a1, zero, 32 ; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle8.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX2-RV64-NEXT: lui a2, 66049 ; LMULMAX2-RV64-NEXT: addiw a2, a2, 32 ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu @@ -4049,57 +4049,57 @@ define void @mulhu_v32i8(<32 x i8>* %x) { ; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; LMULMAX2-RV64-NEXT: lui a2, %hi(.LCPI129_0) ; LMULMAX2-RV64-NEXT: addi a2, a2, %lo(.LCPI129_0) -; LMULMAX2-RV64-NEXT: vle8.v v28, (a2) -; LMULMAX2-RV64-NEXT: vmv.v.i v30, 0 -; LMULMAX2-RV64-NEXT: vmerge.vim v8, v30, 1, v0 -; LMULMAX2-RV64-NEXT: vsrl.vv v8, v26, v8 -; LMULMAX2-RV64-NEXT: vmulhu.vv v28, v8, v28 -; LMULMAX2-RV64-NEXT: vsub.vv v26, v26, v28 +; LMULMAX2-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX2-RV64-NEXT: vmv.v.i v12, 0 +; LMULMAX2-RV64-NEXT: vmerge.vim v14, v12, 1, v0 +; LMULMAX2-RV64-NEXT: vsrl.vv v14, v8, v14 +; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v14, v10 +; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: lui a2, 163907 ; LMULMAX2-RV64-NEXT: addiw a2, a2, -2044 ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2 ; LMULMAX2-RV64-NEXT: addi a2, zero, -128 ; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-RV64-NEXT: vmerge.vxm v30, v30, a2, v0 -; LMULMAX2-RV64-NEXT: vmulhu.vv v26, v26, v30 -; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28 +; LMULMAX2-RV64-NEXT: vmerge.vxm v12, v12, a2, v0 +; LMULMAX2-RV64-NEXT: vmulhu.vv v8, v8, v12 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: lui a2, 8208 ; LMULMAX2-RV64-NEXT: addiw a2, a2, 513 ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2 ; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-RV64-NEXT: vmv.v.i v28, 4 -; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 1, v0 +; LMULMAX2-RV64-NEXT: vmv.v.i v10, 4 +; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX2-RV64-NEXT: lui a2, 66785 ; LMULMAX2-RV64-NEXT: addiw a2, a2, 78 ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2 ; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 3, v0 +; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 3, v0 ; LMULMAX2-RV64-NEXT: lui a2, 529160 ; LMULMAX2-RV64-NEXT: addiw a2, a2, 304 ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2 ; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 2, v0 -; LMULMAX2-RV64-NEXT: vsrl.vv v26, v26, v28 -; LMULMAX2-RV64-NEXT: vse8.v v26, (a0) +; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 2, v0 +; LMULMAX2-RV64-NEXT: vsrl.vv v8, v8, v10 +; LMULMAX2-RV64-NEXT: vse8.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-LABEL: mulhu_v32i8: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vle8.v v25, (a1) +; LMULMAX1-NEXT: vle8.v v8, (a1) ; LMULMAX1-NEXT: lui a2, %hi(.LCPI129_0) ; LMULMAX1-NEXT: addi a2, a2, %lo(.LCPI129_0) -; LMULMAX1-NEXT: vle8.v v26, (a2) -; LMULMAX1-NEXT: vle8.v v27, (a0) -; LMULMAX1-NEXT: vdivu.vv v25, v25, v26 -; LMULMAX1-NEXT: vdivu.vv v26, v27, v26 -; LMULMAX1-NEXT: vse8.v v26, (a0) -; LMULMAX1-NEXT: vse8.v v25, (a1) +; LMULMAX1-NEXT: vle8.v v9, (a2) +; LMULMAX1-NEXT: vle8.v v10, (a0) +; LMULMAX1-NEXT: vdivu.vv v8, v8, v9 +; LMULMAX1-NEXT: vdivu.vv v9, v10, v9 +; LMULMAX1-NEXT: vse8.v v9, (a0) +; LMULMAX1-NEXT: vse8.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = udiv <32 x i8> %a, @@ -4111,94 +4111,94 @@ define void @mulhu_v16i16(<16 x i16>* %x) { ; LMULMAX2-RV32-LABEL: mulhu_v16i16: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle16.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle16.v v10, (a0) ; LMULMAX2-RV32-NEXT: lui a1, 2 ; LMULMAX2-RV32-NEXT: addi a1, a1, 289 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.i v28, 3 -; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 2, v0 +; LMULMAX2-RV32-NEXT: vmv.v.i v8, 3 +; LMULMAX2-RV32-NEXT: vmerge.vim v12, v8, 2, v0 ; LMULMAX2-RV32-NEXT: lui a1, 4 ; LMULMAX2-RV32-NEXT: addi a1, a1, 64 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; LMULMAX2-RV32-NEXT: vmv.s.x v25, a1 +; LMULMAX2-RV32-NEXT: vmv.s.x v8, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv1r.v v0, v25 -; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 1, v0 +; LMULMAX2-RV32-NEXT: vmv1r.v v0, v8 +; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 1, v0 ; LMULMAX2-RV32-NEXT: addi a1, zero, 257 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.i v30, 0 +; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0 ; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI130_0) ; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI130_0) -; LMULMAX2-RV32-NEXT: vle16.v v8, (a1) +; LMULMAX2-RV32-NEXT: vle16.v v16, (a1) ; LMULMAX2-RV32-NEXT: lui a1, 1048568 -; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v30, a1, v0 -; LMULMAX2-RV32-NEXT: vmv1r.v v0, v25 -; LMULMAX2-RV32-NEXT: vmerge.vim v30, v30, 1, v0 -; LMULMAX2-RV32-NEXT: vsrl.vv v30, v26, v30 -; LMULMAX2-RV32-NEXT: vmulhu.vv v30, v30, v8 -; LMULMAX2-RV32-NEXT: vsub.vv v26, v26, v30 -; LMULMAX2-RV32-NEXT: vmulhu.vv v26, v26, v10 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v30 -; LMULMAX2-RV32-NEXT: vsrl.vv v26, v26, v28 -; LMULMAX2-RV32-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV32-NEXT: vmerge.vxm v18, v14, a1, v0 +; LMULMAX2-RV32-NEXT: vmv1r.v v0, v8 +; LMULMAX2-RV32-NEXT: vmerge.vim v8, v14, 1, v0 +; LMULMAX2-RV32-NEXT: vsrl.vv v8, v10, v8 +; LMULMAX2-RV32-NEXT: vmulhu.vv v8, v8, v16 +; LMULMAX2-RV32-NEXT: vsub.vv v10, v10, v8 +; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v10, v18 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v10, v8 +; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v12 +; LMULMAX2-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: mulhu_v16i16: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle16.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle16.v v10, (a0) ; LMULMAX2-RV64-NEXT: lui a1, 2 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 289 ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; LMULMAX2-RV64-NEXT: vmv.s.x v0, a1 ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV64-NEXT: vmv.v.i v28, 3 -; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 2, v0 +; LMULMAX2-RV64-NEXT: vmv.v.i v8, 3 +; LMULMAX2-RV64-NEXT: vmerge.vim v12, v8, 2, v0 ; LMULMAX2-RV64-NEXT: lui a1, 4 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 64 ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; LMULMAX2-RV64-NEXT: vmv.s.x v25, a1 +; LMULMAX2-RV64-NEXT: vmv.s.x v8, a1 ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV64-NEXT: vmv1r.v v0, v25 -; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 1, v0 +; LMULMAX2-RV64-NEXT: vmv1r.v v0, v8 +; LMULMAX2-RV64-NEXT: vmerge.vim v12, v12, 1, v0 ; LMULMAX2-RV64-NEXT: addi a1, zero, 257 ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; LMULMAX2-RV64-NEXT: vmv.s.x v0, a1 ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV64-NEXT: vmv.v.i v30, 0 +; LMULMAX2-RV64-NEXT: vmv.v.i v14, 0 ; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI130_0) ; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI130_0) -; LMULMAX2-RV64-NEXT: vle16.v v8, (a1) +; LMULMAX2-RV64-NEXT: vle16.v v16, (a1) ; LMULMAX2-RV64-NEXT: lui a1, 1048568 -; LMULMAX2-RV64-NEXT: vmerge.vxm v10, v30, a1, v0 -; LMULMAX2-RV64-NEXT: vmv1r.v v0, v25 -; LMULMAX2-RV64-NEXT: vmerge.vim v30, v30, 1, v0 -; LMULMAX2-RV64-NEXT: vsrl.vv v30, v26, v30 -; LMULMAX2-RV64-NEXT: vmulhu.vv v30, v30, v8 -; LMULMAX2-RV64-NEXT: vsub.vv v26, v26, v30 -; LMULMAX2-RV64-NEXT: vmulhu.vv v26, v26, v10 -; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v30 -; LMULMAX2-RV64-NEXT: vsrl.vv v26, v26, v28 -; LMULMAX2-RV64-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV64-NEXT: vmerge.vxm v18, v14, a1, v0 +; LMULMAX2-RV64-NEXT: vmv1r.v v0, v8 +; LMULMAX2-RV64-NEXT: vmerge.vim v8, v14, 1, v0 +; LMULMAX2-RV64-NEXT: vsrl.vv v8, v10, v8 +; LMULMAX2-RV64-NEXT: vmulhu.vv v8, v8, v16 +; LMULMAX2-RV64-NEXT: vsub.vv v10, v10, v8 +; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v10, v18 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v10, v8 +; LMULMAX2-RV64-NEXT: vsrl.vv v8, v8, v12 +; LMULMAX2-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-LABEL: mulhu_v16i16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vle16.v v25, (a1) +; LMULMAX1-NEXT: vle16.v v8, (a1) ; LMULMAX1-NEXT: lui a2, %hi(.LCPI130_0) ; LMULMAX1-NEXT: addi a2, a2, %lo(.LCPI130_0) -; LMULMAX1-NEXT: vle16.v v26, (a2) -; LMULMAX1-NEXT: vle16.v v27, (a0) -; LMULMAX1-NEXT: vdivu.vv v25, v25, v26 -; LMULMAX1-NEXT: vdivu.vv v26, v27, v26 -; LMULMAX1-NEXT: vse16.v v26, (a0) -; LMULMAX1-NEXT: vse16.v v25, (a1) +; LMULMAX1-NEXT: vle16.v v9, (a2) +; LMULMAX1-NEXT: vle16.v v10, (a0) +; LMULMAX1-NEXT: vdivu.vv v8, v8, v9 +; LMULMAX1-NEXT: vdivu.vv v9, v10, v9 +; LMULMAX1-NEXT: vse16.v v9, (a0) +; LMULMAX1-NEXT: vse16.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = udiv <16 x i16> %a, @@ -4210,79 +4210,79 @@ define void @mulhu_v8i32(<8 x i32>* %x) { ; LMULMAX2-LABEL: mulhu_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) ; LMULMAX2-NEXT: addi a1, zero, 68 ; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX2-NEXT: vmv.s.x v0, a1 ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: lui a1, %hi(.LCPI131_0) ; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI131_0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vmv.v.i v30, 0 +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vmv.v.i v12, 0 ; LMULMAX2-NEXT: lui a1, 524288 -; LMULMAX2-NEXT: vmerge.vxm v30, v30, a1, v0 -; LMULMAX2-NEXT: vmulhu.vv v28, v26, v28 -; LMULMAX2-NEXT: vsub.vv v26, v26, v28 -; LMULMAX2-NEXT: vmulhu.vv v26, v26, v30 -; LMULMAX2-NEXT: vadd.vv v26, v26, v28 +; LMULMAX2-NEXT: vmerge.vxm v12, v12, a1, v0 +; LMULMAX2-NEXT: vmulhu.vv v10, v8, v10 +; LMULMAX2-NEXT: vsub.vv v8, v8, v10 +; LMULMAX2-NEXT: vmulhu.vv v8, v8, v12 +; LMULMAX2-NEXT: vadd.vv v8, v8, v10 ; LMULMAX2-NEXT: addi a1, zero, 136 ; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX2-NEXT: vmv.s.x v0, a1 ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.i v28, 2 -; LMULMAX2-NEXT: vmerge.vim v28, v28, 1, v0 -; LMULMAX2-NEXT: vsrl.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vmv.v.i v10, 2 +; LMULMAX2-NEXT: vmerge.vim v10, v10, 1, v0 +; LMULMAX2-NEXT: vsrl.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mulhu_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a1) ; LMULMAX1-RV32-NEXT: lui a2, 524288 -; LMULMAX1-RV32-NEXT: vmv.s.x v27, a2 -; LMULMAX1-RV32-NEXT: vmv.v.i v28, 0 +; LMULMAX1-RV32-NEXT: vmv.s.x v10, a2 +; LMULMAX1-RV32-NEXT: vmv.v.i v11, 0 ; LMULMAX1-RV32-NEXT: vsetivli zero, 3, e32, m1, tu, mu -; LMULMAX1-RV32-NEXT: vslideup.vi v28, v27, 2 +; LMULMAX1-RV32-NEXT: vslideup.vi v11, v10, 2 ; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI131_0) ; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI131_0) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV32-NEXT: vmulhu.vv v29, v26, v27 -; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v29 -; LMULMAX1-RV32-NEXT: vmulhu.vv v26, v26, v28 -; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v29 +; LMULMAX1-RV32-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV32-NEXT: vmulhu.vv v12, v9, v10 +; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v12 +; LMULMAX1-RV32-NEXT: vmulhu.vv v9, v9, v11 +; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v12 ; LMULMAX1-RV32-NEXT: addi a2, zero, 1 -; LMULMAX1-RV32-NEXT: vmv.s.x v29, a2 -; LMULMAX1-RV32-NEXT: vmv.v.i v30, 2 +; LMULMAX1-RV32-NEXT: vmv.s.x v12, a2 +; LMULMAX1-RV32-NEXT: vmv.v.i v13, 2 ; LMULMAX1-RV32-NEXT: vsetvli zero, zero, e32, m1, tu, mu -; LMULMAX1-RV32-NEXT: vslideup.vi v30, v29, 3 +; LMULMAX1-RV32-NEXT: vslideup.vi v13, v12, 3 ; LMULMAX1-RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vsrl.vv v26, v26, v30 -; LMULMAX1-RV32-NEXT: vmulhu.vv v27, v25, v27 -; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vmulhu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v30 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a1) +; LMULMAX1-RV32-NEXT: vsrl.vv v9, v9, v13 +; LMULMAX1-RV32-NEXT: vmulhu.vv v10, v8, v10 +; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vmulhu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vsrl.vv v8, v8, v13 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mulhu_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v25, (a1) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI131_0) ; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI131_0) -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v27, (a0) -; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v26 -; LMULMAX1-RV64-NEXT: vdivu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vse32.v v26, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v25, (a1) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a0) +; LMULMAX1-RV64-NEXT: vdivu.vv v8, v8, v9 +; LMULMAX1-RV64-NEXT: vdivu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vse32.v v9, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = udiv <8 x i32> %a, @@ -4294,90 +4294,90 @@ define void @mulhu_v4i64(<4 x i64>* %x) { ; LMULMAX2-RV32-LABEL: mulhu_v4i64: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle64.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI132_0) ; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI132_0) ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle32.v v28, (a1) +; LMULMAX2-RV32-NEXT: vle32.v v10, (a1) ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmulhu.vv v28, v26, v28 -; LMULMAX2-RV32-NEXT: vsub.vv v26, v26, v28 +; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v8, v10 +; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: lui a1, 524288 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.s.x v30, a1 -; LMULMAX2-RV32-NEXT: vmv.v.i v8, 0 +; LMULMAX2-RV32-NEXT: vmv.s.x v12, a1 +; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0 ; LMULMAX2-RV32-NEXT: vsetivli zero, 6, e32, m2, tu, mu -; LMULMAX2-RV32-NEXT: vslideup.vi v8, v30, 5 +; LMULMAX2-RV32-NEXT: vslideup.vi v14, v12, 5 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmulhu.vv v26, v26, v8 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28 +; LMULMAX2-RV32-NEXT: vmulhu.vv v8, v8, v14 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI132_1) ; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI132_1) ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle32.v v28, (a1) +; LMULMAX2-RV32-NEXT: vle32.v v10, (a1) ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vsrl.vv v26, v26, v28 -; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: mulhu_v4i64: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi a1, zero, -1 ; LMULMAX2-RV64-NEXT: slli a1, a1, 63 -; LMULMAX2-RV64-NEXT: vmv.s.x v28, a1 -; LMULMAX2-RV64-NEXT: vmv.v.i v30, 0 +; LMULMAX2-RV64-NEXT: vmv.s.x v10, a1 +; LMULMAX2-RV64-NEXT: vmv.v.i v12, 0 ; LMULMAX2-RV64-NEXT: vsetivli zero, 3, e64, m2, tu, mu -; LMULMAX2-RV64-NEXT: vslideup.vi v30, v28, 2 +; LMULMAX2-RV64-NEXT: vslideup.vi v12, v10, 2 ; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI132_0) ; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI132_0) ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX2-RV64-NEXT: vmulhu.vv v28, v26, v28 +; LMULMAX2-RV64-NEXT: vle64.v v10, (a1) +; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v8, v10 ; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI132_1) ; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI132_1) -; LMULMAX2-RV64-NEXT: vle64.v v8, (a1) -; LMULMAX2-RV64-NEXT: vsub.vv v26, v26, v28 -; LMULMAX2-RV64-NEXT: vmulhu.vv v26, v26, v30 -; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28 -; LMULMAX2-RV64-NEXT: vsrl.vv v26, v26, v8 -; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle64.v v14, (a1) +; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v10 +; LMULMAX2-RV64-NEXT: vmulhu.vv v8, v8, v12 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10 +; LMULMAX2-RV64-NEXT: vsrl.vv v8, v8, v14 +; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mulhu_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a1) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a1) ; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI132_0) ; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI132_0) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v27, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a2) ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vdivu.vv v26, v26, v27 +; LMULMAX1-RV32-NEXT: vdivu.vv v9, v9, v10 ; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI132_1) ; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI132_1) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v27, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a2) ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a1) +; LMULMAX1-RV32-NEXT: vdivu.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mulhu_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a1) -; LMULMAX1-RV64-NEXT: vmv.v.i v27, 0 +; LMULMAX1-RV64-NEXT: vle64.v v9, (a1) +; LMULMAX1-RV64-NEXT: vmv.v.i v10, 0 ; LMULMAX1-RV64-NEXT: addi a2, zero, -1 ; LMULMAX1-RV64-NEXT: slli a2, a2, 63 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2 +; LMULMAX1-RV64-NEXT: vmv.s.x v10, a2 ; LMULMAX1-RV64-NEXT: lui a2, 1044935 ; LMULMAX1-RV64-NEXT: addiw a2, a2, 455 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12 @@ -4387,7 +4387,7 @@ define void @mulhu_v4i64(<4 x i64>* %x) { ; LMULMAX1-RV64-NEXT: slli a2, a2, 13 ; LMULMAX1-RV64-NEXT: addi a2, a2, 911 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.x v28, a2 +; LMULMAX1-RV64-NEXT: vmv.v.x v11, a2 ; LMULMAX1-RV64-NEXT: lui a2, 4681 ; LMULMAX1-RV64-NEXT: addiw a2, a2, 585 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12 @@ -4397,15 +4397,15 @@ define void @mulhu_v4i64(<4 x i64>* %x) { ; LMULMAX1-RV64-NEXT: slli a2, a2, 13 ; LMULMAX1-RV64-NEXT: addi a2, a2, 1171 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX1-RV64-NEXT: vmv.s.x v28, a2 +; LMULMAX1-RV64-NEXT: vmv.s.x v11, a2 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmulhu.vv v28, v26, v28 -; LMULMAX1-RV64-NEXT: vsub.vv v26, v26, v28 -; LMULMAX1-RV64-NEXT: vmulhu.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v28 -; LMULMAX1-RV64-NEXT: vid.v v27 -; LMULMAX1-RV64-NEXT: vadd.vi v28, v27, 2 -; LMULMAX1-RV64-NEXT: vsrl.vv v26, v26, v28 +; LMULMAX1-RV64-NEXT: vmulhu.vv v11, v9, v11 +; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v11 +; LMULMAX1-RV64-NEXT: vmulhu.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v11 +; LMULMAX1-RV64-NEXT: vid.v v10 +; LMULMAX1-RV64-NEXT: vadd.vi v11, v10, 2 +; LMULMAX1-RV64-NEXT: vsrl.vv v9, v9, v11 ; LMULMAX1-RV64-NEXT: lui a2, 1035469 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -819 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12 @@ -4414,7 +4414,7 @@ define void @mulhu_v4i64(<4 x i64>* %x) { ; LMULMAX1-RV64-NEXT: addi a2, a2, -819 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: addi a2, a2, -819 -; LMULMAX1-RV64-NEXT: vmv.v.x v28, a2 +; LMULMAX1-RV64-NEXT: vmv.v.x v11, a2 ; LMULMAX1-RV64-NEXT: lui a2, 1026731 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -1365 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12 @@ -4424,13 +4424,13 @@ define void @mulhu_v4i64(<4 x i64>* %x) { ; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: addi a2, a2, -1365 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX1-RV64-NEXT: vmv.s.x v28, a2 +; LMULMAX1-RV64-NEXT: vmv.s.x v11, a2 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmulhu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vadd.vi v27, v27, 1 -; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v27 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a1) +; LMULMAX1-RV64-NEXT: vmulhu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vadd.vi v10, v10, 1 +; LMULMAX1-RV64-NEXT: vsrl.vv v8, v8, v10 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a1) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = udiv <4 x i64> %a, @@ -4443,80 +4443,80 @@ define void @mulhs_v32i8(<32 x i8>* %x) { ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: addi a1, zero, 32 ; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle8.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi a2, zero, -123 -; LMULMAX2-RV32-NEXT: vmv.v.x v28, a2 +; LMULMAX2-RV32-NEXT: vmv.v.x v10, a2 ; LMULMAX2-RV32-NEXT: lui a2, 304453 ; LMULMAX2-RV32-NEXT: addi a2, a2, -1452 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a2 ; LMULMAX2-RV32-NEXT: addi a2, zero, 57 ; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmerge.vxm v28, v28, a2, v0 -; LMULMAX2-RV32-NEXT: vmulhu.vv v26, v26, v28 -; LMULMAX2-RV32-NEXT: vmv.v.i v28, 7 -; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 1, v0 -; LMULMAX2-RV32-NEXT: vsrl.vv v26, v26, v28 -; LMULMAX2-RV32-NEXT: vse8.v v26, (a0) +; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a2, v0 +; LMULMAX2-RV32-NEXT: vmulhu.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vmv.v.i v10, 7 +; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 1, v0 +; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vse8.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: mulhs_v32i8: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: addi a1, zero, 32 ; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle8.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi a2, zero, -123 -; LMULMAX2-RV64-NEXT: vmv.v.x v28, a2 +; LMULMAX2-RV64-NEXT: vmv.v.x v10, a2 ; LMULMAX2-RV64-NEXT: lui a2, 304453 ; LMULMAX2-RV64-NEXT: addiw a2, a2, -1452 ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; LMULMAX2-RV64-NEXT: vmv.s.x v0, a2 ; LMULMAX2-RV64-NEXT: addi a2, zero, 57 ; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-RV64-NEXT: vmerge.vxm v28, v28, a2, v0 -; LMULMAX2-RV64-NEXT: vmulhu.vv v26, v26, v28 -; LMULMAX2-RV64-NEXT: vmv.v.i v28, 7 -; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 1, v0 -; LMULMAX2-RV64-NEXT: vsrl.vv v26, v26, v28 -; LMULMAX2-RV64-NEXT: vse8.v v26, (a0) +; LMULMAX2-RV64-NEXT: vmerge.vxm v10, v10, a2, v0 +; LMULMAX2-RV64-NEXT: vmulhu.vv v8, v8, v10 +; LMULMAX2-RV64-NEXT: vmv.v.i v10, 7 +; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 1, v0 +; LMULMAX2-RV64-NEXT: vsrl.vv v8, v8, v10 +; LMULMAX2-RV64-NEXT: vse8.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mulhs_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a1) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a1) ; LMULMAX1-RV32-NEXT: lui a2, 5 ; LMULMAX1-RV32-NEXT: addi a2, a2, -1452 ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; LMULMAX1-RV32-NEXT: vmv.s.x v0, a2 ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.i v27, -9 -; LMULMAX1-RV32-NEXT: vmerge.vim v27, v27, 9, v0 -; LMULMAX1-RV32-NEXT: vdivu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a1) +; LMULMAX1-RV32-NEXT: vmv.v.i v10, -9 +; LMULMAX1-RV32-NEXT: vmerge.vim v10, v10, 9, v0 +; LMULMAX1-RV32-NEXT: vdivu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vdivu.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mulhs_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a1) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a1) ; LMULMAX1-RV64-NEXT: lui a2, 5 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -1452 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; LMULMAX1-RV64-NEXT: vmv.s.x v0, a2 ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.i v27, -9 -; LMULMAX1-RV64-NEXT: vmerge.vim v27, v27, 9, v0 -; LMULMAX1-RV64-NEXT: vdivu.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vdivu.vv v25, v25, v27 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a1) +; LMULMAX1-RV64-NEXT: vmv.v.i v10, -9 +; LMULMAX1-RV64-NEXT: vmerge.vim v10, v10, 9, v0 +; LMULMAX1-RV64-NEXT: vdivu.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vdivu.vv v8, v8, v10 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a1) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = udiv <32 x i8> %a, @@ -4528,7 +4528,7 @@ define void @mulhs_v16i16(<16 x i16>* %x) { ; LMULMAX2-RV32-LABEL: mulhs_v16i16: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle16.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX2-RV32-NEXT: lui a1, 7 ; LMULMAX2-RV32-NEXT: addi a1, a1, -1687 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu @@ -4536,21 +4536,21 @@ define void @mulhs_v16i16(<16 x i16>* %x) { ; LMULMAX2-RV32-NEXT: lui a1, 5 ; LMULMAX2-RV32-NEXT: addi a1, a1, -1755 ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v28, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX2-RV32-NEXT: lui a1, 1048571 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1755 -; LMULMAX2-RV32-NEXT: vmerge.vxm v28, v28, a1, v0 -; LMULMAX2-RV32-NEXT: vmulh.vv v26, v26, v28 -; LMULMAX2-RV32-NEXT: vsra.vi v26, v26, 1 -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 15 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28 -; LMULMAX2-RV32-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a1, v0 +; LMULMAX2-RV32-NEXT: vmulh.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vsra.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 15 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: mulhs_v16i16: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle16.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX2-RV64-NEXT: lui a1, 7 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -1687 ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu @@ -4558,33 +4558,33 @@ define void @mulhs_v16i16(<16 x i16>* %x) { ; LMULMAX2-RV64-NEXT: lui a1, 5 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -1755 ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-RV64-NEXT: vmv.v.x v28, a1 +; LMULMAX2-RV64-NEXT: vmv.v.x v10, a1 ; LMULMAX2-RV64-NEXT: lui a1, 1048571 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1755 -; LMULMAX2-RV64-NEXT: vmerge.vxm v28, v28, a1, v0 -; LMULMAX2-RV64-NEXT: vmulh.vv v26, v26, v28 -; LMULMAX2-RV64-NEXT: vsra.vi v26, v26, 1 -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 15 -; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28 -; LMULMAX2-RV64-NEXT: vse16.v v26, (a0) +; LMULMAX2-RV64-NEXT: vmerge.vxm v10, v10, a1, v0 +; LMULMAX2-RV64-NEXT: vmulh.vv v8, v8, v10 +; LMULMAX2-RV64-NEXT: vsra.vi v8, v8, 1 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 15 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10 +; LMULMAX2-RV64-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-LABEL: mulhs_v16i16: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vle16.v v25, (a0) +; LMULMAX1-NEXT: vle16.v v8, (a0) ; LMULMAX1-NEXT: addi a1, a0, 16 -; LMULMAX1-NEXT: vle16.v v26, (a1) +; LMULMAX1-NEXT: vle16.v v9, (a1) ; LMULMAX1-NEXT: addi a2, zero, 105 ; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX1-NEXT: vmv.s.x v0, a2 ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-NEXT: vmv.v.i v27, 7 -; LMULMAX1-NEXT: vmerge.vim v27, v27, -7, v0 -; LMULMAX1-NEXT: vdiv.vv v26, v26, v27 -; LMULMAX1-NEXT: vdiv.vv v25, v25, v27 -; LMULMAX1-NEXT: vse16.v v25, (a0) -; LMULMAX1-NEXT: vse16.v v26, (a1) +; LMULMAX1-NEXT: vmv.v.i v10, 7 +; LMULMAX1-NEXT: vmerge.vim v10, v10, -7, v0 +; LMULMAX1-NEXT: vdiv.vv v9, v9, v10 +; LMULMAX1-NEXT: vdiv.vv v8, v8, v10 +; LMULMAX1-NEXT: vse16.v v8, (a0) +; LMULMAX1-NEXT: vse16.v v9, (a1) ; LMULMAX1-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = sdiv <16 x i16> %a, @@ -4596,28 +4596,28 @@ define void @mulhs_v8i32(<8 x i32>* %x) { ; LMULMAX2-RV32-LABEL: mulhs_v8i32: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle32.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi a1, zero, 85 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1 ; LMULMAX2-RV32-NEXT: lui a1, 419430 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1639 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v28, a1 +; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1 ; LMULMAX2-RV32-NEXT: lui a1, 629146 ; LMULMAX2-RV32-NEXT: addi a1, a1, -1639 -; LMULMAX2-RV32-NEXT: vmerge.vxm v28, v28, a1, v0 -; LMULMAX2-RV32-NEXT: vmulh.vv v26, v26, v28 -; LMULMAX2-RV32-NEXT: vsrl.vi v28, v26, 31 -; LMULMAX2-RV32-NEXT: vsra.vi v26, v26, 1 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28 -; LMULMAX2-RV32-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a1, v0 +; LMULMAX2-RV32-NEXT: vmulh.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 31 +; LMULMAX2-RV32-NEXT: vsra.vi v8, v8, 1 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10 +; LMULMAX2-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: mulhs_v8i32: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle32.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX2-RV64-NEXT: lui a1, 13107 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 819 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 @@ -4627,59 +4627,59 @@ define void @mulhs_v8i32(<8 x i32>* %x) { ; LMULMAX2-RV64-NEXT: slli a1, a1, 13 ; LMULMAX2-RV64-NEXT: addi a1, a1, -1639 ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV64-NEXT: vmv.v.x v28, a1 +; LMULMAX2-RV64-NEXT: vmv.v.x v10, a1 ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV64-NEXT: vmulh.vv v26, v26, v28 -; LMULMAX2-RV64-NEXT: vsra.vi v26, v26, 1 -; LMULMAX2-RV64-NEXT: vsrl.vi v28, v26, 31 -; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28 -; LMULMAX2-RV64-NEXT: vse32.v v26, (a0) +; LMULMAX2-RV64-NEXT: vmulh.vv v8, v8, v10 +; LMULMAX2-RV64-NEXT: vsra.vi v8, v8, 1 +; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 31 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10 +; LMULMAX2-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mulhs_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a1) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a1) ; LMULMAX1-RV32-NEXT: addi a2, zero, 5 ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX1-RV32-NEXT: vmv.s.x v0, a2 ; LMULMAX1-RV32-NEXT: lui a2, 419430 ; LMULMAX1-RV32-NEXT: addi a2, a2, 1639 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v27, a2 +; LMULMAX1-RV32-NEXT: vmv.v.x v10, a2 ; LMULMAX1-RV32-NEXT: lui a2, 629146 ; LMULMAX1-RV32-NEXT: addi a2, a2, -1639 -; LMULMAX1-RV32-NEXT: vmerge.vxm v27, v27, a2, v0 -; LMULMAX1-RV32-NEXT: vmulh.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vsrl.vi v28, v26, 31 -; LMULMAX1-RV32-NEXT: vsra.vi v26, v26, 1 -; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v28 -; LMULMAX1-RV32-NEXT: vmulh.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vsrl.vi v27, v25, 31 -; LMULMAX1-RV32-NEXT: vsra.vi v25, v25, 1 -; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a1) +; LMULMAX1-RV32-NEXT: vmerge.vxm v10, v10, a2, v0 +; LMULMAX1-RV32-NEXT: vmulh.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 31 +; LMULMAX1-RV32-NEXT: vsra.vi v9, v9, 1 +; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v11 +; LMULMAX1-RV32-NEXT: vmulh.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 31 +; LMULMAX1-RV32-NEXT: vsra.vi v8, v8, 1 +; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mulhs_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a1) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a1) ; LMULMAX1-RV64-NEXT: addi a2, zero, 3 ; LMULMAX1-RV64-NEXT: slli a2, a2, 33 ; LMULMAX1-RV64-NEXT: addi a2, a2, -5 ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.x v27, a2 +; LMULMAX1-RV64-NEXT: vmv.v.x v10, a2 ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vdiv.vv v26, v26, v27 -; LMULMAX1-RV64-NEXT: vdiv.vv v25, v25, v27 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a1) +; LMULMAX1-RV64-NEXT: vdiv.vv v9, v9, v10 +; LMULMAX1-RV64-NEXT: vdiv.vv v8, v8, v10 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a1) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = sdiv <8 x i32> %a, @@ -4691,50 +4691,50 @@ define void @mulhs_v4i64(<4 x i64>* %x) { ; LMULMAX2-RV32-LABEL: mulhs_v4i64: ; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vle64.v v26, (a0) +; LMULMAX2-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32-NEXT: addi a1, zero, 17 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1 ; LMULMAX2-RV32-NEXT: lui a1, 349525 ; LMULMAX2-RV32-NEXT: addi a2, a1, 1365 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.x v28, a2 +; LMULMAX2-RV32-NEXT: vmv.v.x v10, a2 ; LMULMAX2-RV32-NEXT: addi a1, a1, 1366 -; LMULMAX2-RV32-NEXT: vmerge.vxm v28, v28, a1, v0 +; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a1, v0 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmulh.vv v28, v26, v28 +; LMULMAX2-RV32-NEXT: vmulh.vv v10, v8, v10 ; LMULMAX2-RV32-NEXT: addi a1, zero, 51 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.i v30, -1 -; LMULMAX2-RV32-NEXT: vmerge.vim v30, v30, 0, v0 +; LMULMAX2-RV32-NEXT: vmv.v.i v12, -1 +; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 0, v0 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmadd.vv v30, v26, v28 +; LMULMAX2-RV32-NEXT: vmadd.vv v12, v8, v10 ; LMULMAX2-RV32-NEXT: addi a1, zero, 63 -; LMULMAX2-RV32-NEXT: vsrl.vx v26, v30, a1 +; LMULMAX2-RV32-NEXT: vsrl.vx v8, v12, a1 ; LMULMAX2-RV32-NEXT: addi a1, zero, 68 ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1 ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-RV32-NEXT: vmv.v.i v28, 0 -; LMULMAX2-RV32-NEXT: vmerge.vim v28, v28, 1, v0 +; LMULMAX2-RV32-NEXT: vmv.v.i v10, 0 +; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV32-NEXT: vsra.vv v28, v30, v28 -; LMULMAX2-RV32-NEXT: vadd.vv v26, v28, v26 -; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV32-NEXT: vsra.vv v10, v12, v10 +; LMULMAX2-RV32-NEXT: vadd.vv v8, v10, v8 +; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: ret ; ; LMULMAX2-RV64-LABEL: mulhs_v4i64: ; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV64-NEXT: vle64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64-NEXT: addi a1, zero, 5 ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX2-RV64-NEXT: vmv.s.x v0, a1 ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-RV64-NEXT: vmv.v.i v28, -1 -; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 0, v0 +; LMULMAX2-RV64-NEXT: vmv.v.i v10, -1 +; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 0, v0 ; LMULMAX2-RV64-NEXT: lui a1, 21845 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 @@ -4743,43 +4743,43 @@ define void @mulhs_v4i64(<4 x i64>* %x) { ; LMULMAX2-RV64-NEXT: addi a1, a1, 1365 ; LMULMAX2-RV64-NEXT: slli a1, a1, 12 ; LMULMAX2-RV64-NEXT: addi a2, a1, 1365 -; LMULMAX2-RV64-NEXT: vmv.v.x v30, a2 +; LMULMAX2-RV64-NEXT: vmv.v.x v12, a2 ; LMULMAX2-RV64-NEXT: addi a1, a1, 1366 -; LMULMAX2-RV64-NEXT: vmerge.vxm v30, v30, a1, v0 -; LMULMAX2-RV64-NEXT: vmulh.vv v30, v26, v30 -; LMULMAX2-RV64-NEXT: vmacc.vv v30, v26, v28 +; LMULMAX2-RV64-NEXT: vmerge.vxm v12, v12, a1, v0 +; LMULMAX2-RV64-NEXT: vmulh.vv v12, v8, v12 +; LMULMAX2-RV64-NEXT: vmacc.vv v12, v8, v10 ; LMULMAX2-RV64-NEXT: addi a1, zero, 63 -; LMULMAX2-RV64-NEXT: vsrl.vx v26, v30, a1 -; LMULMAX2-RV64-NEXT: vmv.v.i v28, 1 -; LMULMAX2-RV64-NEXT: vmerge.vim v28, v28, 0, v0 -; LMULMAX2-RV64-NEXT: vsra.vv v28, v30, v28 -; LMULMAX2-RV64-NEXT: vadd.vv v26, v28, v26 -; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) +; LMULMAX2-RV64-NEXT: vsrl.vx v8, v12, a1 +; LMULMAX2-RV64-NEXT: vmv.v.i v10, 1 +; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 0, v0 +; LMULMAX2-RV64-NEXT: vsra.vv v10, v12, v10 +; LMULMAX2-RV64-NEXT: vadd.vv v8, v10, v8 +; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: ret ; ; LMULMAX1-RV32-LABEL: mulhs_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a1, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a1) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a1) ; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI136_0) ; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI136_0) ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v27, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a2) ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vdiv.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v27 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a1) +; LMULMAX1-RV32-NEXT: vdiv.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vdiv.vv v8, v8, v10 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a1) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: mulhs_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a1, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a1) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a1) ; LMULMAX1-RV64-NEXT: lui a2, 21845 ; LMULMAX1-RV64-NEXT: addiw a2, a2, 1365 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12 @@ -4788,26 +4788,26 @@ define void @mulhs_v4i64(<4 x i64>* %x) { ; LMULMAX1-RV64-NEXT: addi a2, a2, 1365 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: addi a3, a2, 1365 -; LMULMAX1-RV64-NEXT: vmv.v.x v27, a3 +; LMULMAX1-RV64-NEXT: vmv.v.x v10, a3 ; LMULMAX1-RV64-NEXT: addi a2, a2, 1366 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2 +; LMULMAX1-RV64-NEXT: vmv.s.x v10, a2 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmulh.vv v28, v26, v27 -; LMULMAX1-RV64-NEXT: vid.v v29 -; LMULMAX1-RV64-NEXT: vrsub.vi v30, v29, 0 -; LMULMAX1-RV64-NEXT: vmacc.vv v28, v30, v26 +; LMULMAX1-RV64-NEXT: vmulh.vv v11, v9, v10 +; LMULMAX1-RV64-NEXT: vid.v v12 +; LMULMAX1-RV64-NEXT: vrsub.vi v13, v12, 0 +; LMULMAX1-RV64-NEXT: vmacc.vv v11, v13, v9 ; LMULMAX1-RV64-NEXT: addi a2, zero, 63 -; LMULMAX1-RV64-NEXT: vsrl.vx v26, v28, a2 -; LMULMAX1-RV64-NEXT: vsra.vv v28, v28, v29 -; LMULMAX1-RV64-NEXT: vadd.vv v26, v28, v26 -; LMULMAX1-RV64-NEXT: vmulh.vv v27, v25, v27 -; LMULMAX1-RV64-NEXT: vmacc.vv v27, v25, v30 -; LMULMAX1-RV64-NEXT: vsrl.vx v25, v27, a2 -; LMULMAX1-RV64-NEXT: vsra.vv v27, v27, v29 -; LMULMAX1-RV64-NEXT: vadd.vv v25, v27, v25 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a1) +; LMULMAX1-RV64-NEXT: vsrl.vx v9, v11, a2 +; LMULMAX1-RV64-NEXT: vsra.vv v11, v11, v12 +; LMULMAX1-RV64-NEXT: vadd.vv v9, v11, v9 +; LMULMAX1-RV64-NEXT: vmulh.vv v10, v8, v10 +; LMULMAX1-RV64-NEXT: vmacc.vv v10, v8, v13 +; LMULMAX1-RV64-NEXT: vsrl.vx v8, v10, a2 +; LMULMAX1-RV64-NEXT: vsra.vv v10, v10, v12 +; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a1) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = sdiv <4 x i64> %a, @@ -4820,40 +4820,40 @@ define void @smin_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vmin.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vmin.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smin_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmin.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmin.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmin.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmin.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smin_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmin.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmin.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmin.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmin.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -4867,40 +4867,40 @@ define void @smin_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: smin_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vmin.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vmin.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smin_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmin.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmin.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmin.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmin.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smin_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmin.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmin.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmin.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmin.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -4914,40 +4914,40 @@ define void @smin_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: smin_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vmin.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vmin.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smin_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmin.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmin.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmin.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmin.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smin_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmin.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmin.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmin.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmin.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -4961,40 +4961,40 @@ define void @smin_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: smin_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vmin.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vmin.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smin_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmin.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmin.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmin.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmin.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smin_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmin.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmin.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmin.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmin.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -5009,40 +5009,40 @@ define void @smax_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vmax.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vmax.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smax_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smax_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmax.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmax.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -5056,40 +5056,40 @@ define void @smax_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: smax_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vmax.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vmax.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smax_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smax_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmax.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmax.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -5103,40 +5103,40 @@ define void @smax_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: smax_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vmax.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vmax.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smax_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smax_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmax.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmax.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -5150,40 +5150,40 @@ define void @smax_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: smax_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vmax.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vmax.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: smax_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmax.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmax.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: smax_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmax.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmax.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -5198,40 +5198,40 @@ define void @umin_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vminu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vminu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umin_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vminu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vminu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vminu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vminu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umin_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vminu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vminu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vminu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vminu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -5245,40 +5245,40 @@ define void @umin_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: umin_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vminu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vminu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umin_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vminu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vminu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vminu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vminu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umin_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vminu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vminu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vminu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vminu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -5292,40 +5292,40 @@ define void @umin_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: umin_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vminu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vminu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umin_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vminu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vminu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vminu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vminu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umin_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vminu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vminu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vminu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vminu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -5339,40 +5339,40 @@ define void @umin_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: umin_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vminu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vminu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umin_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vminu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vminu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vminu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vminu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umin_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vminu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vminu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vminu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vminu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -5387,40 +5387,40 @@ define void @umax_v32i8(<32 x i8>* %x, <32 x i8>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vle8.v v26, (a0) -; LMULMAX2-NEXT: vle8.v v28, (a1) -; LMULMAX2-NEXT: vmaxu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse8.v v26, (a0) +; LMULMAX2-NEXT: vle8.v v8, (a0) +; LMULMAX2-NEXT: vle8.v v10, (a1) +; LMULMAX2-NEXT: vmaxu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umax_v32i8: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle8.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmaxu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmaxu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle8.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmaxu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmaxu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umax_v32i8: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle8.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle8.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle8.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmaxu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmaxu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse8.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse8.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle8.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmaxu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmaxu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse8.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse8.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -5434,40 +5434,40 @@ define void @umax_v16i16(<16 x i16>* %x, <16 x i16>* %y) { ; LMULMAX2-LABEL: umax_v16i16: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; LMULMAX2-NEXT: vle16.v v26, (a0) -; LMULMAX2-NEXT: vle16.v v28, (a1) -; LMULMAX2-NEXT: vmaxu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse16.v v26, (a0) +; LMULMAX2-NEXT: vle16.v v8, (a0) +; LMULMAX2-NEXT: vle16.v v10, (a1) +; LMULMAX2-NEXT: vmaxu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umax_v16i16: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle16.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmaxu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmaxu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle16.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmaxu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmaxu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umax_v16i16: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle16.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle16.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle16.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle16.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmaxu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmaxu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse16.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse16.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle16.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmaxu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmaxu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse16.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse16.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -5481,40 +5481,40 @@ define void @umax_v8i32(<8 x i32>* %x, <8 x i32>* %y) { ; LMULMAX2-LABEL: umax_v8i32: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; LMULMAX2-NEXT: vle32.v v26, (a0) -; LMULMAX2-NEXT: vle32.v v28, (a1) -; LMULMAX2-NEXT: vmaxu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse32.v v26, (a0) +; LMULMAX2-NEXT: vle32.v v8, (a0) +; LMULMAX2-NEXT: vle32.v v10, (a1) +; LMULMAX2-NEXT: vmaxu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umax_v8i32: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle32.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmaxu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmaxu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle32.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmaxu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmaxu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umax_v8i32: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle32.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle32.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle32.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmaxu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmaxu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse32.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse32.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle32.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmaxu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmaxu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse32.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -5528,40 +5528,40 @@ define void @umax_v4i64(<4 x i64>* %x, <4 x i64>* %y) { ; LMULMAX2-LABEL: umax_v4i64: ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; LMULMAX2-NEXT: vle64.v v26, (a0) -; LMULMAX2-NEXT: vle64.v v28, (a1) -; LMULMAX2-NEXT: vmaxu.vv v26, v26, v28 -; LMULMAX2-NEXT: vse64.v v26, (a0) +; LMULMAX2-NEXT: vle64.v v8, (a0) +; LMULMAX2-NEXT: vle64.v v10, (a1) +; LMULMAX2-NEXT: vmaxu.vv v8, v8, v10 +; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: umax_v4i64: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a2, a0, 16 -; LMULMAX1-RV32-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV32-NEXT: addi a3, a1, 16 -; LMULMAX1-RV32-NEXT: vle64.v v27, (a3) -; LMULMAX1-RV32-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV32-NEXT: vmaxu.vv v26, v26, v27 -; LMULMAX1-RV32-NEXT: vmaxu.vv v25, v25, v28 -; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV32-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV32-NEXT: vle64.v v10, (a3) +; LMULMAX1-RV32-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV32-NEXT: vmaxu.vv v9, v9, v10 +; LMULMAX1-RV32-NEXT: vmaxu.vv v8, v8, v11 +; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV32-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: umax_v4i64: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) +; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a2, a1, 16 -; LMULMAX1-RV64-NEXT: vle64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v9, (a2) ; LMULMAX1-RV64-NEXT: addi a2, a0, 16 -; LMULMAX1-RV64-NEXT: vle64.v v27, (a2) -; LMULMAX1-RV64-NEXT: vle64.v v28, (a1) -; LMULMAX1-RV64-NEXT: vmaxu.vv v26, v27, v26 -; LMULMAX1-RV64-NEXT: vmaxu.vv v25, v25, v28 -; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) -; LMULMAX1-RV64-NEXT: vse64.v v26, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v10, (a2) +; LMULMAX1-RV64-NEXT: vle64.v v11, (a1) +; LMULMAX1-RV64-NEXT: vmaxu.vv v9, v10, v9 +; LMULMAX1-RV64-NEXT: vmaxu.vv v8, v8, v11 +; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) +; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: ret %a = load <4 x i64>, <4 x i64>* %x %b = load <4 x i64>, <4 x i64>* %y @@ -5575,9 +5575,9 @@ define void @add_vi_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: add_vi_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vadd.vi v25, v25, -1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vadd.vi v8, v8, -1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 -1, i32 0 @@ -5591,9 +5591,9 @@ define void @add_vi_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: add_vi_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vadd.vi v25, v25, -1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vadd.vi v8, v8, -1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 -1, i32 0 @@ -5607,9 +5607,9 @@ define void @add_vi_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: add_vi_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vadd.vi v25, v25, -1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vadd.vi v8, v8, -1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 -1, i32 0 @@ -5623,9 +5623,9 @@ define void @add_vi_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: add_vi_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vadd.vi v25, v25, -1 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vadd.vi v8, v8, -1 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 -1, i32 0 @@ -5639,9 +5639,9 @@ define void @add_iv_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: add_iv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vadd.vi v25, v25, 1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vadd.vi v8, v8, 1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 1, i32 0 @@ -5655,9 +5655,9 @@ define void @add_iv_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: add_iv_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vadd.vi v25, v25, 1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vadd.vi v8, v8, 1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 1, i32 0 @@ -5671,9 +5671,9 @@ define void @add_iv_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: add_iv_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vadd.vi v25, v25, 1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vadd.vi v8, v8, 1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 1, i32 0 @@ -5687,9 +5687,9 @@ define void @add_iv_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: add_iv_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vadd.vi v25, v25, 1 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vadd.vi v8, v8, 1 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 1, i32 0 @@ -5703,9 +5703,9 @@ define void @add_vx_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: add_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vadd.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vadd.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -5719,9 +5719,9 @@ define void @add_vx_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: add_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vadd.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vadd.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -5735,9 +5735,9 @@ define void @add_vx_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: add_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vadd.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vadd.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -5751,9 +5751,9 @@ define void @add_xv_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: add_xv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vadd.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vadd.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -5767,9 +5767,9 @@ define void @add_xv_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: add_xv_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vadd.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vadd.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -5783,9 +5783,9 @@ define void @add_xv_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: add_xv_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vadd.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vadd.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -5799,10 +5799,10 @@ define void @sub_vi_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: sub_vi_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a1, zero, -1 -; CHECK-NEXT: vsub.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vsub.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 -1, i32 0 @@ -5816,10 +5816,10 @@ define void @sub_vi_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: sub_vi_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: addi a1, zero, -1 -; CHECK-NEXT: vsub.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vsub.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 -1, i32 0 @@ -5833,10 +5833,10 @@ define void @sub_vi_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: sub_vi_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: addi a1, zero, -1 -; CHECK-NEXT: vsub.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vsub.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 -1, i32 0 @@ -5850,10 +5850,10 @@ define void @sub_vi_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: sub_vi_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: addi a1, zero, -1 -; CHECK-NEXT: vsub.vx v25, v25, a1 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vsub.vx v8, v8, a1 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 -1, i32 0 @@ -5867,9 +5867,9 @@ define void @sub_iv_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: sub_iv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vrsub.vi v25, v25, 1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vrsub.vi v8, v8, 1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 1, i32 0 @@ -5883,9 +5883,9 @@ define void @sub_iv_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: sub_iv_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vrsub.vi v25, v25, 1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vrsub.vi v8, v8, 1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 1, i32 0 @@ -5899,9 +5899,9 @@ define void @sub_iv_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: sub_iv_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vrsub.vi v25, v25, 1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vrsub.vi v8, v8, 1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 1, i32 0 @@ -5915,9 +5915,9 @@ define void @sub_iv_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: sub_iv_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vrsub.vi v25, v25, 1 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vrsub.vi v8, v8, 1 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 1, i32 0 @@ -5931,9 +5931,9 @@ define void @sub_vx_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: sub_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vsub.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vsub.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -5947,9 +5947,9 @@ define void @sub_vx_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: sub_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vsub.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vsub.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -5963,9 +5963,9 @@ define void @sub_vx_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: sub_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vsub.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vsub.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -5979,9 +5979,9 @@ define void @sub_xv_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: sub_xv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vrsub.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vrsub.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -5995,9 +5995,9 @@ define void @sub_xv_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: sub_xv_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vrsub.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vrsub.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6011,9 +6011,9 @@ define void @sub_xv_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: sub_xv_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vrsub.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vrsub.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6027,9 +6027,9 @@ define void @mul_vx_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: mul_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmul.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmul.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6043,9 +6043,9 @@ define void @mul_vx_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: mul_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vmul.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmul.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6059,9 +6059,9 @@ define void @mul_vx_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: mul_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vmul.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmul.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6075,9 +6075,9 @@ define void @mul_xv_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: mul_xv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmul.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmul.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6091,9 +6091,9 @@ define void @mul_xv_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: mul_xv_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vmul.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmul.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6107,9 +6107,9 @@ define void @mul_xv_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: mul_xv_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vmul.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmul.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6123,9 +6123,9 @@ define void @and_vi_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: and_vi_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vand.vi v25, v25, -2 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vand.vi v8, v8, -2 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 -2, i32 0 @@ -6139,9 +6139,9 @@ define void @and_vi_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: and_vi_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vand.vi v25, v25, -2 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vand.vi v8, v8, -2 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 -2, i32 0 @@ -6155,9 +6155,9 @@ define void @and_vi_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: and_vi_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vand.vi v25, v25, -2 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vand.vi v8, v8, -2 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 -2, i32 0 @@ -6171,9 +6171,9 @@ define void @and_vi_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: and_vi_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vand.vi v25, v25, -2 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vand.vi v8, v8, -2 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 -2, i32 0 @@ -6187,9 +6187,9 @@ define void @and_iv_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: and_iv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 1, i32 0 @@ -6203,9 +6203,9 @@ define void @and_iv_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: and_iv_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 1, i32 0 @@ -6219,9 +6219,9 @@ define void @and_iv_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: and_iv_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 1, i32 0 @@ -6235,9 +6235,9 @@ define void @and_iv_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: and_iv_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 1, i32 0 @@ -6251,9 +6251,9 @@ define void @and_vx_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: and_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vand.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vand.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6267,9 +6267,9 @@ define void @and_vx_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: and_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vand.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vand.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6283,9 +6283,9 @@ define void @and_vx_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: and_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vand.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vand.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6299,9 +6299,9 @@ define void @and_xv_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: and_xv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vand.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vand.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6315,9 +6315,9 @@ define void @and_xv_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: and_xv_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vand.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vand.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6331,9 +6331,9 @@ define void @and_xv_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: and_xv_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vand.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vand.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6347,9 +6347,9 @@ define void @or_vi_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: or_vi_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vor.vi v25, v25, -2 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vor.vi v8, v8, -2 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 -2, i32 0 @@ -6363,9 +6363,9 @@ define void @or_vi_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: or_vi_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vor.vi v25, v25, -2 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vor.vi v8, v8, -2 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 -2, i32 0 @@ -6379,9 +6379,9 @@ define void @or_vi_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: or_vi_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vor.vi v25, v25, -2 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vor.vi v8, v8, -2 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 -2, i32 0 @@ -6395,9 +6395,9 @@ define void @or_vi_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: or_vi_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vor.vi v25, v25, -2 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vor.vi v8, v8, -2 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 -2, i32 0 @@ -6411,9 +6411,9 @@ define void @or_iv_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: or_iv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vor.vi v25, v25, 1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vor.vi v8, v8, 1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 1, i32 0 @@ -6427,9 +6427,9 @@ define void @or_iv_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: or_iv_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vor.vi v25, v25, 1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vor.vi v8, v8, 1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 1, i32 0 @@ -6443,9 +6443,9 @@ define void @or_iv_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: or_iv_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vor.vi v25, v25, 1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vor.vi v8, v8, 1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 1, i32 0 @@ -6459,9 +6459,9 @@ define void @or_iv_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: or_iv_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vor.vi v25, v25, 1 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vor.vi v8, v8, 1 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 1, i32 0 @@ -6475,9 +6475,9 @@ define void @or_vx_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: or_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vor.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vor.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6491,9 +6491,9 @@ define void @or_vx_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: or_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vor.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vor.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6507,9 +6507,9 @@ define void @or_vx_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: or_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vor.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vor.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6523,9 +6523,9 @@ define void @or_xv_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: or_xv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vor.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vor.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6539,9 +6539,9 @@ define void @or_xv_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: or_xv_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vor.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vor.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6555,9 +6555,9 @@ define void @or_xv_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: or_xv_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vor.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vor.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6571,9 +6571,9 @@ define void @xor_vi_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: xor_vi_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vnot.v v25, v25 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vnot.v v8, v8 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 -1, i32 0 @@ -6587,9 +6587,9 @@ define void @xor_vi_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: xor_vi_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vnot.v v25, v25 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vnot.v v8, v8 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 -1, i32 0 @@ -6603,9 +6603,9 @@ define void @xor_vi_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: xor_vi_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vnot.v v25, v25 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vnot.v v8, v8 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 -1, i32 0 @@ -6619,9 +6619,9 @@ define void @xor_vi_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: xor_vi_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vnot.v v25, v25 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vnot.v v8, v8 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 -1, i32 0 @@ -6635,9 +6635,9 @@ define void @xor_iv_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: xor_iv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vxor.vi v25, v25, 1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vxor.vi v8, v8, 1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 1, i32 0 @@ -6651,9 +6651,9 @@ define void @xor_iv_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: xor_iv_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vxor.vi v25, v25, 1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vxor.vi v8, v8, 1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 1, i32 0 @@ -6667,9 +6667,9 @@ define void @xor_iv_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: xor_iv_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vxor.vi v25, v25, 1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vxor.vi v8, v8, 1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 1, i32 0 @@ -6683,9 +6683,9 @@ define void @xor_iv_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: xor_iv_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vxor.vi v25, v25, 1 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vxor.vi v8, v8, 1 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 1, i32 0 @@ -6699,9 +6699,9 @@ define void @xor_vx_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: xor_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vxor.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vxor.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6715,9 +6715,9 @@ define void @xor_vx_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: xor_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vxor.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vxor.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6731,9 +6731,9 @@ define void @xor_vx_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: xor_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vxor.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vxor.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6747,9 +6747,9 @@ define void @xor_xv_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: xor_xv_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vxor.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vxor.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6763,9 +6763,9 @@ define void @xor_xv_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: xor_xv_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vxor.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vxor.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6779,9 +6779,9 @@ define void @xor_xv_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: xor_xv_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vxor.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vxor.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6795,9 +6795,9 @@ define void @lshr_vi_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: lshr_vi_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vsrl.vi v25, v25, 7 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vsrl.vi v8, v8, 7 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 7, i32 0 @@ -6811,9 +6811,9 @@ define void @lshr_vi_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: lshr_vi_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vsrl.vi v25, v25, 15 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vsrl.vi v8, v8, 15 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 15, i32 0 @@ -6827,9 +6827,9 @@ define void @lshr_vi_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: lshr_vi_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vsrl.vi v25, v25, 31 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vsrl.vi v8, v8, 31 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 31, i32 0 @@ -6843,9 +6843,9 @@ define void @lshr_vi_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: lshr_vi_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vsrl.vi v25, v25, 31 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsrl.vi v8, v8, 31 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 31, i32 0 @@ -6859,9 +6859,9 @@ define void @lshr_vx_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: lshr_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6875,9 +6875,9 @@ define void @lshr_vx_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: lshr_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -6891,9 +6891,9 @@ define void @lshr_vx_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: lshr_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -6907,9 +6907,9 @@ define void @ashr_vi_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: ashr_vi_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vsra.vi v25, v25, 7 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vsra.vi v8, v8, 7 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 7, i32 0 @@ -6923,9 +6923,9 @@ define void @ashr_vi_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: ashr_vi_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vsra.vi v25, v25, 15 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vsra.vi v8, v8, 15 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 15, i32 0 @@ -6939,9 +6939,9 @@ define void @ashr_vi_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: ashr_vi_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vsra.vi v25, v25, 31 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vsra.vi v8, v8, 31 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 31, i32 0 @@ -6955,9 +6955,9 @@ define void @ashr_vi_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: ashr_vi_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vsra.vi v25, v25, 31 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsra.vi v8, v8, 31 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 31, i32 0 @@ -6971,9 +6971,9 @@ define void @ashr_vx_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: ashr_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vsra.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vsra.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -6987,9 +6987,9 @@ define void @ashr_vx_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: ashr_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vsra.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vsra.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -7003,9 +7003,9 @@ define void @ashr_vx_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: ashr_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vsra.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vsra.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -7019,9 +7019,9 @@ define void @shl_vi_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: shl_vi_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vsll.vi v25, v25, 7 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vsll.vi v8, v8, 7 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 7, i32 0 @@ -7035,9 +7035,9 @@ define void @shl_vi_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: shl_vi_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vsll.vi v25, v25, 15 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vsll.vi v8, v8, 15 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 15, i32 0 @@ -7051,9 +7051,9 @@ define void @shl_vi_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: shl_vi_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vsll.vi v25, v25, 31 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vsll.vi v8, v8, 31 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 31, i32 0 @@ -7067,9 +7067,9 @@ define void @shl_vi_v2i64(<2 x i64>* %x) { ; CHECK-LABEL: shl_vi_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vsll.vi v25, v25, 31 -; CHECK-NEXT: vse64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsll.vi v8, v8, 31 +; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = insertelement <2 x i64> undef, i64 31, i32 0 @@ -7083,9 +7083,9 @@ define void @shl_vx_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: shl_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -7099,9 +7099,9 @@ define void @shl_vx_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: shl_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -7115,9 +7115,9 @@ define void @shl_vx_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: shl_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -7131,9 +7131,9 @@ define void @sdiv_vx_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: sdiv_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vdiv.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vdiv.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -7147,9 +7147,9 @@ define void @sdiv_vx_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: sdiv_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vdiv.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vdiv.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -7163,9 +7163,9 @@ define void @sdiv_vx_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: sdiv_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vdiv.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vdiv.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -7179,9 +7179,9 @@ define void @srem_vx_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: srem_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vrem.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vrem.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -7195,9 +7195,9 @@ define void @srem_vx_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: srem_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vrem.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vrem.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -7211,9 +7211,9 @@ define void @srem_vx_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: srem_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vrem.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vrem.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -7227,9 +7227,9 @@ define void @udiv_vx_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: udiv_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vdivu.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vdivu.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -7243,9 +7243,9 @@ define void @udiv_vx_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: udiv_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vdivu.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vdivu.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -7259,9 +7259,9 @@ define void @udiv_vx_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: udiv_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vdivu.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vdivu.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -7275,9 +7275,9 @@ define void @urem_vx_v16i8(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: urem_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vremu.vx v25, v25, a1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vremu.vx v8, v8, a1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -7291,9 +7291,9 @@ define void @urem_vx_v8i16(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: urem_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vremu.vx v25, v25, a1 -; CHECK-NEXT: vse16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vremu.vx v8, v8, a1 +; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -7307,9 +7307,9 @@ define void @urem_vx_v4i32(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: urem_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vremu.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vremu.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i32 0 @@ -7323,11 +7323,11 @@ define void @mulhu_vx_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: mulhu_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a1, zero, 57 -; CHECK-NEXT: vmulhu.vx v25, v25, a1 -; CHECK-NEXT: vsrl.vi v25, v25, 1 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vmulhu.vx v8, v8, a1 +; CHECK-NEXT: vsrl.vi v8, v8, 1 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = udiv <16 x i8> %a, @@ -7339,29 +7339,29 @@ define void @mulhu_vx_v8i16(<8 x i16>* %x) { ; RV32-LABEL: mulhu_vx_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV32-NEXT: vle16.v v25, (a0) +; RV32-NEXT: vle16.v v8, (a0) ; RV32-NEXT: lui a1, 2 ; RV32-NEXT: addi a1, a1, 1171 -; RV32-NEXT: vmulhu.vx v26, v25, a1 -; RV32-NEXT: vsub.vv v25, v25, v26 -; RV32-NEXT: vsrl.vi v25, v25, 1 -; RV32-NEXT: vadd.vv v25, v25, v26 -; RV32-NEXT: vsrl.vi v25, v25, 2 -; RV32-NEXT: vse16.v v25, (a0) +; RV32-NEXT: vmulhu.vx v9, v8, a1 +; RV32-NEXT: vsub.vv v8, v8, v9 +; RV32-NEXT: vsrl.vi v8, v8, 1 +; RV32-NEXT: vadd.vv v8, v8, v9 +; RV32-NEXT: vsrl.vi v8, v8, 2 +; RV32-NEXT: vse16.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: mulhu_vx_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV64-NEXT: vle16.v v25, (a0) +; RV64-NEXT: vle16.v v8, (a0) ; RV64-NEXT: lui a1, 2 ; RV64-NEXT: addiw a1, a1, 1171 -; RV64-NEXT: vmulhu.vx v26, v25, a1 -; RV64-NEXT: vsub.vv v25, v25, v26 -; RV64-NEXT: vsrl.vi v25, v25, 1 -; RV64-NEXT: vadd.vv v25, v25, v26 -; RV64-NEXT: vsrl.vi v25, v25, 2 -; RV64-NEXT: vse16.v v25, (a0) +; RV64-NEXT: vmulhu.vx v9, v8, a1 +; RV64-NEXT: vsub.vv v8, v8, v9 +; RV64-NEXT: vsrl.vi v8, v8, 1 +; RV64-NEXT: vadd.vv v8, v8, v9 +; RV64-NEXT: vsrl.vi v8, v8, 2 +; RV64-NEXT: vse16.v v8, (a0) ; RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = udiv <8 x i16> %a, @@ -7373,23 +7373,23 @@ define void @mulhu_vx_v4i32(<4 x i32>* %x) { ; RV32-LABEL: mulhu_vx_v4i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vle32.v v25, (a0) +; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: lui a1, 838861 ; RV32-NEXT: addi a1, a1, -819 -; RV32-NEXT: vmulhu.vx v25, v25, a1 -; RV32-NEXT: vsrl.vi v25, v25, 2 -; RV32-NEXT: vse32.v v25, (a0) +; RV32-NEXT: vmulhu.vx v8, v8, a1 +; RV32-NEXT: vsrl.vi v8, v8, 2 +; RV32-NEXT: vse32.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: mulhu_vx_v4i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV64-NEXT: vle32.v v25, (a0) +; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: lui a1, 838861 ; RV64-NEXT: addiw a1, a1, -819 -; RV64-NEXT: vmulhu.vx v25, v25, a1 -; RV64-NEXT: vsrl.vi v25, v25, 2 -; RV64-NEXT: vse32.v v25, (a0) +; RV64-NEXT: vmulhu.vx v8, v8, a1 +; RV64-NEXT: vsrl.vi v8, v8, 2 +; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = udiv <4 x i32> %a, @@ -7403,24 +7403,24 @@ define void @mulhu_vx_v2i64(<2 x i64>* %x) { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: lui a1, 699051 ; RV32-NEXT: addi a2, a1, -1366 ; RV32-NEXT: sw a2, 12(sp) ; RV32-NEXT: addi a1, a1, -1365 ; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: addi a1, sp, 8 -; RV32-NEXT: vlse64.v v26, (a1), zero -; RV32-NEXT: vmulhu.vv v25, v25, v26 -; RV32-NEXT: vsrl.vi v25, v25, 1 -; RV32-NEXT: vse64.v v25, (a0) +; RV32-NEXT: vlse64.v v9, (a1), zero +; RV32-NEXT: vmulhu.vv v8, v8, v9 +; RV32-NEXT: vsrl.vi v8, v8, 1 +; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: mulhu_vx_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: lui a1, 1026731 ; RV64-NEXT: addiw a1, a1, -1365 ; RV64-NEXT: slli a1, a1, 12 @@ -7429,9 +7429,9 @@ define void @mulhu_vx_v2i64(<2 x i64>* %x) { ; RV64-NEXT: addi a1, a1, -1365 ; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: addi a1, a1, -1365 -; RV64-NEXT: vmulhu.vx v25, v25, a1 -; RV64-NEXT: vsrl.vi v25, v25, 1 -; RV64-NEXT: vse64.v v25, (a0) +; RV64-NEXT: vmulhu.vx v8, v8, a1 +; RV64-NEXT: vsrl.vi v8, v8, 1 +; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = udiv <2 x i64> %a, @@ -7443,11 +7443,11 @@ define void @mulhs_vx_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: mulhs_vx_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a1, zero, -123 -; CHECK-NEXT: vmulhu.vx v25, v25, a1 -; CHECK-NEXT: vsrl.vi v25, v25, 7 -; CHECK-NEXT: vse8.v v25, (a0) +; CHECK-NEXT: vmulhu.vx v8, v8, a1 +; CHECK-NEXT: vsrl.vi v8, v8, 7 +; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = udiv <16 x i8> %a, @@ -7459,27 +7459,27 @@ define void @mulhs_vx_v8i16(<8 x i16>* %x) { ; RV32-LABEL: mulhs_vx_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV32-NEXT: vle16.v v25, (a0) +; RV32-NEXT: vle16.v v8, (a0) ; RV32-NEXT: lui a1, 5 ; RV32-NEXT: addi a1, a1, -1755 -; RV32-NEXT: vmulh.vx v25, v25, a1 -; RV32-NEXT: vsra.vi v25, v25, 1 -; RV32-NEXT: vsrl.vi v26, v25, 15 -; RV32-NEXT: vadd.vv v25, v25, v26 -; RV32-NEXT: vse16.v v25, (a0) +; RV32-NEXT: vmulh.vx v8, v8, a1 +; RV32-NEXT: vsra.vi v8, v8, 1 +; RV32-NEXT: vsrl.vi v9, v8, 15 +; RV32-NEXT: vadd.vv v8, v8, v9 +; RV32-NEXT: vse16.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: mulhs_vx_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV64-NEXT: vle16.v v25, (a0) +; RV64-NEXT: vle16.v v8, (a0) ; RV64-NEXT: lui a1, 5 ; RV64-NEXT: addiw a1, a1, -1755 -; RV64-NEXT: vmulh.vx v25, v25, a1 -; RV64-NEXT: vsra.vi v25, v25, 1 -; RV64-NEXT: vsrl.vi v26, v25, 15 -; RV64-NEXT: vadd.vv v25, v25, v26 -; RV64-NEXT: vse16.v v25, (a0) +; RV64-NEXT: vmulh.vx v8, v8, a1 +; RV64-NEXT: vsra.vi v8, v8, 1 +; RV64-NEXT: vsrl.vi v9, v8, 15 +; RV64-NEXT: vadd.vv v8, v8, v9 +; RV64-NEXT: vse16.v v8, (a0) ; RV64-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = sdiv <8 x i16> %a, @@ -7491,27 +7491,27 @@ define void @mulhs_vx_v4i32(<4 x i32>* %x) { ; RV32-LABEL: mulhs_vx_v4i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vle32.v v25, (a0) +; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: lui a1, 629146 ; RV32-NEXT: addi a1, a1, -1639 -; RV32-NEXT: vmulh.vx v25, v25, a1 -; RV32-NEXT: vsrl.vi v26, v25, 31 -; RV32-NEXT: vsra.vi v25, v25, 1 -; RV32-NEXT: vadd.vv v25, v25, v26 -; RV32-NEXT: vse32.v v25, (a0) +; RV32-NEXT: vmulh.vx v8, v8, a1 +; RV32-NEXT: vsrl.vi v9, v8, 31 +; RV32-NEXT: vsra.vi v8, v8, 1 +; RV32-NEXT: vadd.vv v8, v8, v9 +; RV32-NEXT: vse32.v v8, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: mulhs_vx_v4i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV64-NEXT: vle32.v v25, (a0) +; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: lui a1, 629146 ; RV64-NEXT: addiw a1, a1, -1639 -; RV64-NEXT: vmulh.vx v25, v25, a1 -; RV64-NEXT: vsra.vi v25, v25, 1 -; RV64-NEXT: vsrl.vi v26, v25, 31 -; RV64-NEXT: vadd.vv v25, v25, v26 -; RV64-NEXT: vse32.v v25, (a0) +; RV64-NEXT: vmulh.vx v8, v8, a1 +; RV64-NEXT: vsra.vi v8, v8, 1 +; RV64-NEXT: vsrl.vi v9, v8, 31 +; RV64-NEXT: vadd.vv v8, v8, v9 +; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = sdiv <4 x i32> %a, @@ -7525,26 +7525,26 @@ define void @mulhs_vx_v2i64(<2 x i64>* %x) { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: addi a2, a1, 1365 ; RV32-NEXT: sw a2, 12(sp) ; RV32-NEXT: addi a1, a1, 1366 ; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: addi a1, sp, 8 -; RV32-NEXT: vlse64.v v26, (a1), zero -; RV32-NEXT: vmulh.vv v25, v25, v26 +; RV32-NEXT: vlse64.v v9, (a1), zero +; RV32-NEXT: vmulh.vv v8, v8, v9 ; RV32-NEXT: addi a1, zero, 63 -; RV32-NEXT: vsrl.vx v26, v25, a1 -; RV32-NEXT: vadd.vv v25, v25, v26 -; RV32-NEXT: vse64.v v25, (a0) +; RV32-NEXT: vsrl.vx v9, v8, a1 +; RV32-NEXT: vadd.vv v8, v8, v9 +; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: mulhs_vx_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: lui a1, 21845 ; RV64-NEXT: addiw a1, a1, 1365 ; RV64-NEXT: slli a1, a1, 12 @@ -7553,11 +7553,11 @@ define void @mulhs_vx_v2i64(<2 x i64>* %x) { ; RV64-NEXT: addi a1, a1, 1365 ; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: addi a1, a1, 1366 -; RV64-NEXT: vmulh.vx v25, v25, a1 +; RV64-NEXT: vmulh.vx v8, v8, a1 ; RV64-NEXT: addi a1, zero, 63 -; RV64-NEXT: vsrl.vx v26, v25, a1 -; RV64-NEXT: vadd.vv v25, v25, v26 -; RV64-NEXT: vse64.v v25, (a0) +; RV64-NEXT: vsrl.vx v9, v8, a1 +; RV64-NEXT: vadd.vv v8, v8, v9 +; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: ret %a = load <2 x i64>, <2 x i64>* %x %b = sdiv <2 x i64> %a, diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll index cb81fc9fa5ae228834af75a47591ba28d9ab23ca..6b45283d3b84d30797fa74363dc7de4345a75708 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll @@ -13,8 +13,8 @@ define <1 x i1> @buildvec_mask_nonconst_v1i1(i1 %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %1 = insertelement <1 x i1> undef, i1 %x, i32 0 ret <1 x i1> %1 @@ -25,8 +25,8 @@ define <1 x i1> @buildvec_mask_optsize_nonconst_v1i1(i1 %x) optsize { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %1 = insertelement <1 x i1> undef, i1 %x, i32 0 ret <1 x i1> %1 @@ -36,12 +36,12 @@ define <2 x i1> @buildvec_mask_nonconst_v2i1(i1 %x, i1 %y) { ; CHECK-LABEL: buildvec_mask_nonconst_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a1 +; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %1 = insertelement <2 x i1> undef, i1 %x, i32 0 %2 = insertelement <2 x i1> %1, i1 %y, i32 1 @@ -58,9 +58,9 @@ define <2 x i1> @buildvec_mask_optsize_nonconst_v2i1(i1 %x, i1 %y) optsize { ; CHECK-NEXT: sb a0, 14(sp) ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: addi a0, sp, 14 -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %1 = insertelement <2 x i1> undef, i1 %x, i32 0 @@ -105,10 +105,10 @@ define <4 x i1> @buildvec_mask_nonconst_v4i1(i1 %x, i1 %y) { ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.s.x v0, a2 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: vmerge.vxm v25, v25, a0, v0 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %1 = insertelement <4 x i1> undef, i1 %x, i32 0 %2 = insertelement <4 x i1> %1, i1 %x, i32 1 @@ -129,9 +129,9 @@ define <4 x i1> @buildvec_mask_optsize_nonconst_v4i1(i1 %x, i1 %y) optsize { ; CHECK-NEXT: sb a0, 12(sp) ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: addi a0, sp, 12 -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %1 = insertelement <4 x i1> undef, i1 %x, i32 0 @@ -153,9 +153,9 @@ define <4 x i1> @buildvec_mask_nonconst_v4i1_2(i1 %x, i1 %y) { ; CHECK-NEXT: sb zero, 12(sp) ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: addi a0, sp, 12 -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %1 = insertelement <4 x i1> undef, i1 0, i32 0 @@ -182,10 +182,10 @@ define <8 x i1> @buildvec_mask_nonconst_v8i1(i1 %x, i1 %y) { ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmv.s.x v0, a2 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: vmerge.vxm v25, v25, a0, v0 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %1 = insertelement <8 x i1> undef, i1 %x, i32 0 %2 = insertelement <8 x i1> %1, i1 %x, i32 1 @@ -214,9 +214,9 @@ define <8 x i1> @buildvec_mask_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 %w) { ; CHECK-NEXT: sb a0, 8(sp) ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %1 = insertelement <8 x i1> undef, i1 %x, i32 0 @@ -246,9 +246,9 @@ define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 % ; CHECK-NEXT: sb a0, 8(sp) ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %1 = insertelement <8 x i1> undef, i1 %x, i32 0 @@ -277,9 +277,9 @@ define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1(i1 %x, i1 %y) optsize { ; CHECK-NEXT: sb a0, 8(sp) ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %1 = insertelement <8 x i1> undef, i1 %x, i32 0 @@ -459,12 +459,12 @@ define <64 x i1> @buildvec_mask_v64i1() { ; RV32-LMULMAX4-NEXT: lui a0, 748388 ; RV32-LMULMAX4-NEXT: addi a0, a0, -1793 ; RV32-LMULMAX4-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-LMULMAX4-NEXT: vmv.s.x v25, a0 +; RV32-LMULMAX4-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX4-NEXT: lui a0, 748384 ; RV32-LMULMAX4-NEXT: addi a0, a0, 1776 ; RV32-LMULMAX4-NEXT: vmv.s.x v0, a0 ; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, tu, mu -; RV32-LMULMAX4-NEXT: vslideup.vi v0, v25, 1 +; RV32-LMULMAX4-NEXT: vslideup.vi v0, v8, 1 ; RV32-LMULMAX4-NEXT: ret ; ; RV64-LMULMAX4-LABEL: buildvec_mask_v64i1: @@ -486,12 +486,12 @@ define <64 x i1> @buildvec_mask_v64i1() { ; RV32-LMULMAX8-NEXT: lui a0, 748388 ; RV32-LMULMAX8-NEXT: addi a0, a0, -1793 ; RV32-LMULMAX8-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-LMULMAX8-NEXT: vmv.s.x v25, a0 +; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX8-NEXT: lui a0, 748384 ; RV32-LMULMAX8-NEXT: addi a0, a0, 1776 ; RV32-LMULMAX8-NEXT: vmv.s.x v0, a0 ; RV32-LMULMAX8-NEXT: vsetvli zero, zero, e32, mf2, tu, mu -; RV32-LMULMAX8-NEXT: vslideup.vi v0, v25, 1 +; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 1 ; RV32-LMULMAX8-NEXT: ret ; ; RV64-LMULMAX8-LABEL: buildvec_mask_v64i1: @@ -594,21 +594,21 @@ define <128 x i1> @buildvec_mask_v128i1() { ; RV32-LMULMAX4-NEXT: lui a0, 748388 ; RV32-LMULMAX4-NEXT: addi a0, a0, -1793 ; RV32-LMULMAX4-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-LMULMAX4-NEXT: vmv.s.x v25, a0 +; RV32-LMULMAX4-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX4-NEXT: lui a0, 748384 ; RV32-LMULMAX4-NEXT: addi a0, a0, 1776 ; RV32-LMULMAX4-NEXT: vmv.s.x v0, a0 ; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, tu, mu -; RV32-LMULMAX4-NEXT: vslideup.vi v0, v25, 1 +; RV32-LMULMAX4-NEXT: vslideup.vi v0, v8, 1 ; RV32-LMULMAX4-NEXT: lui a0, 945060 ; RV32-LMULMAX4-NEXT: addi a0, a0, -1793 ; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; RV32-LMULMAX4-NEXT: vmv.s.x v25, a0 +; RV32-LMULMAX4-NEXT: vmv.s.x v9, a0 ; RV32-LMULMAX4-NEXT: lui a0, 551776 ; RV32-LMULMAX4-NEXT: addi a0, a0, 1776 ; RV32-LMULMAX4-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, tu, mu -; RV32-LMULMAX4-NEXT: vslideup.vi v8, v25, 1 +; RV32-LMULMAX4-NEXT: vslideup.vi v8, v9, 1 ; RV32-LMULMAX4-NEXT: ret ; ; RV64-LMULMAX4-LABEL: buildvec_mask_v128i1: @@ -637,24 +637,24 @@ define <128 x i1> @buildvec_mask_v128i1() { ; RV32-LMULMAX8-NEXT: lui a0, 748388 ; RV32-LMULMAX8-NEXT: addi a0, a0, -1793 ; RV32-LMULMAX8-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-LMULMAX8-NEXT: vmv.s.x v25, a0 +; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX8-NEXT: lui a0, 748384 ; RV32-LMULMAX8-NEXT: addi a0, a0, 1776 ; RV32-LMULMAX8-NEXT: vmv.s.x v0, a0 ; RV32-LMULMAX8-NEXT: vsetivli zero, 2, e32, m1, tu, mu -; RV32-LMULMAX8-NEXT: vslideup.vi v0, v25, 1 +; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 1 ; RV32-LMULMAX8-NEXT: lui a0, 551776 ; RV32-LMULMAX8-NEXT: addi a0, a0, 1776 ; RV32-LMULMAX8-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-LMULMAX8-NEXT: vmv.s.x v25, a0 +; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX8-NEXT: vsetivli zero, 3, e32, m1, tu, mu -; RV32-LMULMAX8-NEXT: vslideup.vi v0, v25, 2 +; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 2 ; RV32-LMULMAX8-NEXT: lui a0, 945060 ; RV32-LMULMAX8-NEXT: addi a0, a0, -1793 ; RV32-LMULMAX8-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-LMULMAX8-NEXT: vmv.s.x v25, a0 +; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX8-NEXT: vsetvli zero, zero, e32, m1, tu, mu -; RV32-LMULMAX8-NEXT: vslideup.vi v0, v25, 3 +; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 3 ; RV32-LMULMAX8-NEXT: ret ; ; RV64-LMULMAX8-LABEL: buildvec_mask_v128i1: @@ -666,7 +666,7 @@ define <128 x i1> @buildvec_mask_v128i1() { ; RV64-LMULMAX8-NEXT: slli a0, a0, 17 ; RV64-LMULMAX8-NEXT: addi a0, a0, 1776 ; RV64-LMULMAX8-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-LMULMAX8-NEXT: vmv.s.x v25, a0 +; RV64-LMULMAX8-NEXT: vmv.s.x v8, a0 ; RV64-LMULMAX8-NEXT: lui a0, 1048429 ; RV64-LMULMAX8-NEXT: addiw a0, a0, 1735 ; RV64-LMULMAX8-NEXT: slli a0, a0, 13 @@ -677,7 +677,7 @@ define <128 x i1> @buildvec_mask_v128i1() { ; RV64-LMULMAX8-NEXT: addi a0, a0, 1776 ; RV64-LMULMAX8-NEXT: vmv.s.x v0, a0 ; RV64-LMULMAX8-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; RV64-LMULMAX8-NEXT: vslideup.vi v0, v25, 1 +; RV64-LMULMAX8-NEXT: vslideup.vi v0, v8, 1 ; RV64-LMULMAX8-NEXT: ret ret <128 x i1> } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll index e60a1da17f843edd6f4056f112898526b53f9b21..6b58ecd313b67bef9f4bf34ee2bb90a7660fb1c3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll @@ -9,15 +9,15 @@ define void @load_store_v1i1(<1 x i1>* %x, <1 x i1>* %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vlm.v v0, (a0) -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <1 x i1>, <1 x i1>* %x store <1 x i1> %a, <1 x i1>* %y @@ -29,15 +29,15 @@ define void @load_store_v2i1(<2 x i1>* %x, <2 x i1>* %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vlm.v v0, (a0) -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x i1>, <2 x i1>* %x store <2 x i1> %a, <2 x i1>* %y @@ -49,15 +49,15 @@ define void @load_store_v4i1(<4 x i1>* %x, <4 x i1>* %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vlm.v v0, (a0) -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x i1>, <4 x i1>* %x store <4 x i1> %a, <4 x i1>* %y @@ -68,8 +68,8 @@ define void @load_store_v8i1(<8 x i1>* %x, <8 x i1>* %y) { ; CHECK-LABEL: load_store_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <8 x i1>, <8 x i1>* %x store <8 x i1> %a, <8 x i1>* %y @@ -80,8 +80,8 @@ define void @load_store_v16i1(<16 x i1>* %x, <16 x i1>* %y) { ; CHECK-LABEL: load_store_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <16 x i1>, <16 x i1>* %x store <16 x i1> %a, <16 x i1>* %y @@ -93,8 +93,8 @@ define void @load_store_v32i1(<32 x i1>* %x, <32 x i1>* %y) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vlm.v v25, (a0) -; LMULMAX2-NEXT: vsm.v v25, (a1) +; LMULMAX2-NEXT: vlm.v v8, (a0) +; LMULMAX2-NEXT: vsm.v v8, (a1) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: load_store_v32i1: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll index b4164beebb37633e8462735d55b37a187c97ad5d..fc19cee141e647505a6c9e18394670b3a78f8644 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll @@ -8,10 +8,10 @@ define void @and_v8i1(<8 x i1>* %x, <8 x i1>* %y) { ; CHECK-LABEL: and_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vlm.v v26, (a1) -; CHECK-NEXT: vmand.mm v25, v25, v26 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vlm.v v9, (a1) +; CHECK-NEXT: vmand.mm v8, v8, v9 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i1>, <8 x i1>* %x %b = load <8 x i1>, <8 x i1>* %y @@ -24,10 +24,10 @@ define void @or_v16i1(<16 x i1>* %x, <16 x i1>* %y) { ; CHECK-LABEL: or_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vlm.v v26, (a1) -; CHECK-NEXT: vmor.mm v25, v25, v26 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vlm.v v9, (a1) +; CHECK-NEXT: vmor.mm v8, v8, v9 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i1>, <16 x i1>* %x %b = load <16 x i1>, <16 x i1>* %y @@ -41,10 +41,10 @@ define void @xor_v32i1(<32 x i1>* %x, <32 x i1>* %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vlm.v v26, (a1) -; CHECK-NEXT: vmxor.mm v25, v25, v26 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vlm.v v9, (a1) +; CHECK-NEXT: vmxor.mm v8, v8, v9 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %a = load <32 x i1>, <32 x i1>* %x %b = load <32 x i1>, <32 x i1>* %y @@ -58,9 +58,9 @@ define void @not_v64i1(<64 x i1>* %x, <64 x i1>* %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 64 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vmnand.mm v25, v25, v25 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vmnand.mm v8, v8, v8 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %a = load <64 x i1>, <64 x i1>* %x %b = load <64 x i1>, <64 x i1>* %y @@ -73,10 +73,10 @@ define void @andnot_v8i1(<8 x i1>* %x, <8 x i1>* %y) { ; CHECK-LABEL: andnot_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vlm.v v26, (a1) -; CHECK-NEXT: vmandnot.mm v25, v26, v25 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vlm.v v9, (a1) +; CHECK-NEXT: vmandnot.mm v8, v9, v8 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i1>, <8 x i1>* %x %b = load <8 x i1>, <8 x i1>* %y @@ -90,10 +90,10 @@ define void @ornot_v16i1(<16 x i1>* %x, <16 x i1>* %y) { ; CHECK-LABEL: ornot_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vlm.v v26, (a1) -; CHECK-NEXT: vmornot.mm v25, v26, v25 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vlm.v v9, (a1) +; CHECK-NEXT: vmornot.mm v8, v9, v8 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i1>, <16 x i1>* %x %b = load <16 x i1>, <16 x i1>* %y @@ -108,10 +108,10 @@ define void @xornot_v32i1(<32 x i1>* %x, <32 x i1>* %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vlm.v v26, (a1) -; CHECK-NEXT: vmxnor.mm v25, v25, v26 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vlm.v v9, (a1) +; CHECK-NEXT: vmxnor.mm v8, v8, v9 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %a = load <32 x i1>, <32 x i1>* %x %b = load <32 x i1>, <32 x i1>* %y @@ -125,10 +125,10 @@ define void @nand_v8i1(<8 x i1>* %x, <8 x i1>* %y) { ; CHECK-LABEL: nand_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vlm.v v26, (a1) -; CHECK-NEXT: vmnand.mm v25, v25, v26 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vlm.v v9, (a1) +; CHECK-NEXT: vmnand.mm v8, v8, v9 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i1>, <8 x i1>* %x %b = load <8 x i1>, <8 x i1>* %y @@ -142,10 +142,10 @@ define void @nor_v16i1(<16 x i1>* %x, <16 x i1>* %y) { ; CHECK-LABEL: nor_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vlm.v v26, (a1) -; CHECK-NEXT: vmnor.mm v25, v25, v26 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vlm.v v9, (a1) +; CHECK-NEXT: vmnor.mm v8, v8, v9 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i1>, <16 x i1>* %x %b = load <16 x i1>, <16 x i1>* %y @@ -160,10 +160,10 @@ define void @xnor_v32i1(<32 x i1>* %x, <32 x i1>* %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vlm.v v26, (a1) -; CHECK-NEXT: vmxnor.mm v25, v25, v26 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vlm.v v9, (a1) +; CHECK-NEXT: vmxnor.mm v8, v8, v9 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %a = load <32 x i1>, <32 x i1>* %x %b = load <32 x i1>, <32 x i1>* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll index 015f6d31ea473c55f4f8c0cd07f19fd31325f02b..17300e9eb36cb458c4d370893f1b61471319a74e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll @@ -9,15 +9,15 @@ define void @splat_ones_v1i1(<1 x i1>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vmset.m v0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret store <1 x i1> , <1 x i1>* %x ret void @@ -28,15 +28,15 @@ define void @splat_zeros_v2i1(<2 x i1>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vmclr.m v0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret store <2 x i1> zeroinitializer, <2 x i1>* %x ret void @@ -47,17 +47,17 @@ define void @splat_v1i1(<1 x i1>* %x, i1 %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a1, a1, 1 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <1 x i1> undef, i1 %y, i32 0 %b = shufflevector <1 x i1> %a, <1 x i1> undef, <1 x i32> zeroinitializer @@ -71,17 +71,17 @@ define void @splat_v1i1_icmp(<1 x i1>* %x, i32 signext %y, i32 signext %z) { ; CHECK-NEXT: xor a1, a1, a2 ; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %c = icmp eq i32 %y, %z %a = insertelement <1 x i1> undef, i1 %c, i32 0 @@ -95,15 +95,15 @@ define void @splat_ones_v4i1(<4 x i1>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vmset.m v0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret store <4 x i1> , <4 x i1>* %x ret void @@ -114,17 +114,17 @@ define void @splat_v4i1(<4 x i1>* %x, i1 %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a1, a1, 1 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 +; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 0 +; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmsne.vi v8, v9, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <4 x i1> undef, i1 %y, i32 0 %b = shufflevector <4 x i1> %a, <4 x i1> undef, <4 x i32> zeroinitializer @@ -136,8 +136,8 @@ define void @splat_zeros_v8i1(<8 x i1>* %x) { ; CHECK-LABEL: splat_zeros_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmclr.m v25 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmclr.m v8 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret store <8 x i1> zeroinitializer, <8 x i1>* %x ret void @@ -148,9 +148,9 @@ define void @splat_v8i1(<8 x i1>* %x, i1 %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a1, a1, 1 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: vmsne.vi v25, v25, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmsne.vi v8, v8, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <8 x i1> undef, i1 %y, i32 0 %b = shufflevector <8 x i1> %a, <8 x i1> undef, <8 x i32> zeroinitializer @@ -162,8 +162,8 @@ define void @splat_ones_v16i1(<16 x i1>* %x) { ; CHECK-LABEL: splat_ones_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmset.m v25 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmset.m v8 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret store <16 x i1> , <16 x i1>* %x ret void @@ -174,9 +174,9 @@ define void @splat_v16i1(<16 x i1>* %x, i1 %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a1, a1, 1 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a1 -; CHECK-NEXT: vmsne.vi v25, v25, 0 -; CHECK-NEXT: vsm.v v25, (a0) +; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmsne.vi v8, v8, 0 +; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret %a = insertelement <16 x i1> undef, i1 %y, i32 0 %b = shufflevector <16 x i1> %a, <16 x i1> undef, <16 x i32> zeroinitializer @@ -189,26 +189,26 @@ define void @splat_zeros_v32i1(<32 x i1>* %x) { ; LMULMAX2: # %bb.0: ; LMULMAX2-NEXT: addi a1, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; LMULMAX2-NEXT: vmclr.m v25 -; LMULMAX2-NEXT: vsm.v v25, (a0) +; LMULMAX2-NEXT: vmclr.m v8 +; LMULMAX2-NEXT: vsm.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_zeros_v32i1: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmclr.m v25 -; LMULMAX1-RV32-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV32-NEXT: vmclr.m v8 +; LMULMAX1-RV32-NEXT: vsm.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a0, a0, 2 -; LMULMAX1-RV32-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV32-NEXT: vsm.v v8, (a0) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_zeros_v32i1: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmclr.m v25 -; LMULMAX1-RV64-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV64-NEXT: vmclr.m v8 +; LMULMAX1-RV64-NEXT: vsm.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a0, a0, 2 -; LMULMAX1-RV64-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV64-NEXT: vsm.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret store <32 x i1> zeroinitializer, <32 x i1>* %x ret void @@ -220,31 +220,31 @@ define void @splat_v32i1(<32 x i1>* %x, i1 %y) { ; LMULMAX2-NEXT: andi a1, a1, 1 ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.x v26, a1 -; LMULMAX2-NEXT: vmsne.vi v25, v26, 0 -; LMULMAX2-NEXT: vsm.v v25, (a0) +; LMULMAX2-NEXT: vmv.v.x v8, a1 +; LMULMAX2-NEXT: vmsne.vi v10, v8, 0 +; LMULMAX2-NEXT: vsm.v v10, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_v32i1: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: andi a1, a1, 1 ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v25, a1 -; LMULMAX1-RV32-NEXT: vmsne.vi v25, v25, 0 +; LMULMAX1-RV32-NEXT: vmv.v.x v8, a1 +; LMULMAX1-RV32-NEXT: vmsne.vi v8, v8, 0 ; LMULMAX1-RV32-NEXT: addi a1, a0, 2 -; LMULMAX1-RV32-NEXT: vsm.v v25, (a1) -; LMULMAX1-RV32-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV32-NEXT: vsm.v v8, (a1) +; LMULMAX1-RV32-NEXT: vsm.v v8, (a0) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_v32i1: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: andi a1, a1, 1 ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1 -; LMULMAX1-RV64-NEXT: vmsne.vi v25, v25, 0 +; LMULMAX1-RV64-NEXT: vmv.v.x v8, a1 +; LMULMAX1-RV64-NEXT: vmsne.vi v8, v8, 0 ; LMULMAX1-RV64-NEXT: addi a1, a0, 2 -; LMULMAX1-RV64-NEXT: vsm.v v25, (a1) -; LMULMAX1-RV64-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV64-NEXT: vsm.v v8, (a1) +; LMULMAX1-RV64-NEXT: vsm.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = insertelement <32 x i1> undef, i1 %y, i32 0 %b = shufflevector <32 x i1> %a, <32 x i1> undef, <32 x i32> zeroinitializer @@ -258,35 +258,35 @@ define void @splat_ones_v64i1(<64 x i1>* %x) { ; LMULMAX2-NEXT: addi a1, a0, 4 ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vmset.m v25 -; LMULMAX2-NEXT: vsm.v v25, (a1) -; LMULMAX2-NEXT: vsm.v v25, (a0) +; LMULMAX2-NEXT: vmset.m v8 +; LMULMAX2-NEXT: vsm.v v8, (a1) +; LMULMAX2-NEXT: vsm.v v8, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_ones_v64i1: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmset.m v25 -; LMULMAX1-RV32-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV32-NEXT: vmset.m v8 +; LMULMAX1-RV32-NEXT: vsm.v v8, (a0) ; LMULMAX1-RV32-NEXT: addi a1, a0, 6 -; LMULMAX1-RV32-NEXT: vsm.v v25, (a1) +; LMULMAX1-RV32-NEXT: vsm.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a1, a0, 4 -; LMULMAX1-RV32-NEXT: vsm.v v25, (a1) +; LMULMAX1-RV32-NEXT: vsm.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a0, a0, 2 -; LMULMAX1-RV32-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV32-NEXT: vsm.v v8, (a0) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_ones_v64i1: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmset.m v25 -; LMULMAX1-RV64-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV64-NEXT: vmset.m v8 +; LMULMAX1-RV64-NEXT: vsm.v v8, (a0) ; LMULMAX1-RV64-NEXT: addi a1, a0, 6 -; LMULMAX1-RV64-NEXT: vsm.v v25, (a1) +; LMULMAX1-RV64-NEXT: vsm.v v8, (a1) ; LMULMAX1-RV64-NEXT: addi a1, a0, 4 -; LMULMAX1-RV64-NEXT: vsm.v v25, (a1) +; LMULMAX1-RV64-NEXT: vsm.v v8, (a1) ; LMULMAX1-RV64-NEXT: addi a0, a0, 2 -; LMULMAX1-RV64-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV64-NEXT: vsm.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret store <64 x i1> , <64 x i1>* %x ret void @@ -298,41 +298,41 @@ define void @splat_v64i1(<64 x i1>* %x, i1 %y) { ; LMULMAX2-NEXT: andi a1, a1, 1 ; LMULMAX2-NEXT: addi a2, zero, 32 ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; LMULMAX2-NEXT: vmv.v.x v26, a1 -; LMULMAX2-NEXT: vmsne.vi v25, v26, 0 +; LMULMAX2-NEXT: vmv.v.x v8, a1 +; LMULMAX2-NEXT: vmsne.vi v10, v8, 0 ; LMULMAX2-NEXT: addi a1, a0, 4 -; LMULMAX2-NEXT: vsm.v v25, (a1) -; LMULMAX2-NEXT: vsm.v v25, (a0) +; LMULMAX2-NEXT: vsm.v v10, (a1) +; LMULMAX2-NEXT: vsm.v v10, (a0) ; LMULMAX2-NEXT: ret ; ; LMULMAX1-RV32-LABEL: splat_v64i1: ; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32-NEXT: andi a1, a1, 1 ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV32-NEXT: vmv.v.x v25, a1 -; LMULMAX1-RV32-NEXT: vmsne.vi v25, v25, 0 +; LMULMAX1-RV32-NEXT: vmv.v.x v8, a1 +; LMULMAX1-RV32-NEXT: vmsne.vi v8, v8, 0 ; LMULMAX1-RV32-NEXT: addi a1, a0, 6 -; LMULMAX1-RV32-NEXT: vsm.v v25, (a1) +; LMULMAX1-RV32-NEXT: vsm.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a1, a0, 4 -; LMULMAX1-RV32-NEXT: vsm.v v25, (a1) +; LMULMAX1-RV32-NEXT: vsm.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a1, a0, 2 -; LMULMAX1-RV32-NEXT: vsm.v v25, (a1) -; LMULMAX1-RV32-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV32-NEXT: vsm.v v8, (a1) +; LMULMAX1-RV32-NEXT: vsm.v v8, (a0) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX1-RV64-LABEL: splat_v64i1: ; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64-NEXT: andi a1, a1, 1 ; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1 -; LMULMAX1-RV64-NEXT: vmsne.vi v25, v25, 0 +; LMULMAX1-RV64-NEXT: vmv.v.x v8, a1 +; LMULMAX1-RV64-NEXT: vmsne.vi v8, v8, 0 ; LMULMAX1-RV64-NEXT: addi a1, a0, 6 -; LMULMAX1-RV64-NEXT: vsm.v v25, (a1) +; LMULMAX1-RV64-NEXT: vsm.v v8, (a1) ; LMULMAX1-RV64-NEXT: addi a1, a0, 4 -; LMULMAX1-RV64-NEXT: vsm.v v25, (a1) +; LMULMAX1-RV64-NEXT: vsm.v v8, (a1) ; LMULMAX1-RV64-NEXT: addi a1, a0, 2 -; LMULMAX1-RV64-NEXT: vsm.v v25, (a1) -; LMULMAX1-RV64-NEXT: vsm.v v25, (a0) +; LMULMAX1-RV64-NEXT: vsm.v v8, (a1) +; LMULMAX1-RV64-NEXT: vsm.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = insertelement <64 x i1> undef, i1 %y, i32 0 %b = shufflevector <64 x i1> %a, <64 x i1> undef, <64 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll index 590af5b9fc755c78ef3123653edebfdf92f88fcb..9fc5b5b36874878f4899ffade1ebfa6d651fac30 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll @@ -194,15 +194,15 @@ define <4 x i8> @mgather_truemask_v4i8(<4 x i8*> %ptrs, <4 x i8> %passthru) { ; RV32-LABEL: mgather_truemask_v4i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v9, (zero), v8 +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_v4i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v10, (zero), v8 +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -248,18 +248,18 @@ define <8 x i8> @mgather_baseidx_v8i8(i8* %base, <8 x i8> %idxs, <8 x i1> %m, <8 ; RV32-LABEL: mgather_baseidx_v8i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 +; RV32-NEXT: vsext.vf4 v10, v8 ; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 +; RV64-NEXT: vsext.vf8 v12, v8 ; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i8, i8* %base, <8 x i8> %idxs @@ -415,15 +415,15 @@ define <4 x i16> @mgather_truemask_v4i16(<4 x i16*> %ptrs, <4 x i16> %passthru) ; RV32-LABEL: mgather_truemask_v4i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v9, (zero), v8 +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_v4i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v10, (zero), v8 +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -469,20 +469,20 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(i16* %base, <8 x i8> %idxs, <8 x i1 ; RV32-LABEL: mgather_baseidx_v8i8_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i8_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i16, i16* %base, <8 x i8> %idxs @@ -494,20 +494,20 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(i16* %base, <8 x i8> %idxs, <8 ; RV32-LABEL: mgather_baseidx_sext_v8i8_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i16> @@ -520,20 +520,20 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(i16* %base, <8 x i8> %idxs, <8 ; RV32-LABEL: mgather_baseidx_zext_v8i8_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vzext.vf4 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vzext.vf8 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i16> @@ -546,20 +546,20 @@ define <8 x i16> @mgather_baseidx_v8i16(i16* %base, <8 x i16> %idxs, <8 x i1> %m ; RV32-LABEL: mgather_baseidx_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %idxs @@ -679,8 +679,8 @@ define <4 x i32> @mgather_truemask_v4i32(<4 x i32*> %ptrs, <4 x i32> %passthru) ; RV64-LABEL: mgather_truemask_v4i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v10, (zero), v8 +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -726,19 +726,19 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(i32* %base, <8 x i8> %idxs, <8 x i1 ; RV32-LABEL: mgather_baseidx_v8i8_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t +; RV32-NEXT: vsext.vf4 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 +; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i8_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t ; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i8> %idxs @@ -750,19 +750,19 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(i32* %base, <8 x i8> %idxs, <8 ; RV32-LABEL: mgather_baseidx_sext_v8i8_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t +; RV32-NEXT: vsext.vf4 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 +; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t ; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i32> @@ -775,19 +775,19 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(i32* %base, <8 x i8> %idxs, <8 ; RV32-LABEL: mgather_baseidx_zext_v8i8_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t +; RV32-NEXT: vzext.vf4 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 +; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t ; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i32> @@ -800,19 +800,19 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(i32* %base, <8 x i16> %idxs, <8 x ; RV32-LABEL: mgather_baseidx_v8i16_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t +; RV32-NEXT: vsext.vf2 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 +; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i16_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t ; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i16> %idxs @@ -824,19 +824,19 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(i32* %base, <8 x i16> %idxs, ; RV32-LABEL: mgather_baseidx_sext_v8i16_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t +; RV32-NEXT: vsext.vf2 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 +; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i16_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t ; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i32> @@ -849,19 +849,19 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(i32* %base, <8 x i16> %idxs, ; RV32-LABEL: mgather_baseidx_zext_v8i16_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t +; RV32-NEXT: vzext.vf2 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 +; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i16_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t ; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i32> @@ -874,18 +874,18 @@ define <8 x i32> @mgather_baseidx_v8i32(i32* %base, <8 x i32> %idxs, <8 x i1> %m ; RV32-LABEL: mgather_baseidx_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v8, 2 -; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t +; RV32-NEXT: vsll.vi v8, v8, 2 +; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf2 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t ; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %idxs @@ -957,8 +957,8 @@ define <4 x i64> @mgather_truemask_v4i64(<4 x i64*> %ptrs, <4 x i64> %passthru) ; RV32-LABEL: mgather_truemask_v4i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vluxei32.v v26, (zero), v8 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vluxei32.v v10, (zero), v8 +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_v4i64: @@ -1010,19 +1010,19 @@ define <8 x i64> @mgather_baseidx_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i1 ; RV32-LABEL: mgather_baseidx_v8i8_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i8_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vsext.vf8 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i8> %idxs @@ -1034,18 +1034,18 @@ define <8 x i64> @mgather_baseidx_sext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 ; RV32-LABEL: mgather_baseidx_sext_v8i8_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsext.vf8 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV32-NEXT: vsext.vf8 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vsext.vf8 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> @@ -1058,18 +1058,18 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 ; RV32-LABEL: mgather_baseidx_zext_v8i8_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vzext.vf8 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV32-NEXT: vzext.vf8 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vzext.vf8 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> @@ -1082,19 +1082,19 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(i64* %base, <8 x i16> %idxs, <8 x ; RV32-LABEL: mgather_baseidx_v8i16_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i16_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vsext.vf4 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i16> %idxs @@ -1106,18 +1106,18 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, ; RV32-LABEL: mgather_baseidx_sext_v8i16_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV32-NEXT: vsext.vf4 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i16_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vsext.vf4 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> @@ -1130,18 +1130,18 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, ; RV32-LABEL: mgather_baseidx_zext_v8i16_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vzext.vf4 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV32-NEXT: vzext.vf4 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i16_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vzext.vf4 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> @@ -1154,18 +1154,18 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(i64* %base, <8 x i32> %idxs, <8 x ; RV32-LABEL: mgather_baseidx_v8i32_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v8, 3 +; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i32_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vsext.vf2 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i32> %idxs @@ -1177,18 +1177,18 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, ; RV32-LABEL: mgather_baseidx_sext_v8i32_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV32-NEXT: vsext.vf2 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i32_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vsext.vf2 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> @@ -1201,18 +1201,18 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, ; RV32-LABEL: mgather_baseidx_zext_v8i32_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vzext.vf2 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV32-NEXT: vzext.vf2 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i32_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf2 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vzext.vf2 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> @@ -1225,16 +1225,16 @@ define <8 x i64> @mgather_baseidx_v8i64(i64* %base, <8 x i64> %idxs, <8 x i1> %m ; RV32-LABEL: mgather_baseidx_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsll.vi v28, v8, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV32-NEXT: vsll.vi v8, v8, 3 +; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsll.vi v28, v8, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vsll.vi v8, v8, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %idxs @@ -1306,15 +1306,15 @@ define <4 x half> @mgather_truemask_v4f16(<4 x half*> %ptrs, <4 x half> %passthr ; RV32-LABEL: mgather_truemask_v4f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v9, (zero), v8 +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_v4f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v10, (zero), v8 +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -1360,20 +1360,20 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(half* %base, <8 x i8> %idxs, <8 x ; RV32-LABEL: mgather_baseidx_v8i8_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i8_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %ptrs = getelementptr inbounds half, half* %base, <8 x i8> %idxs @@ -1385,20 +1385,20 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(half* %base, <8 x i8> %idxs, ; RV32-LABEL: mgather_baseidx_sext_v8i8_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i16> @@ -1411,20 +1411,20 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(half* %base, <8 x i8> %idxs, ; RV32-LABEL: mgather_baseidx_zext_v8i8_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vzext.vf4 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vzext.vf8 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i16> @@ -1437,20 +1437,20 @@ define <8 x half> @mgather_baseidx_v8f16(half* %base, <8 x i16> %idxs, <8 x i1> ; RV32-LABEL: mgather_baseidx_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v9, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v9, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v9, (a0), v12, v0.t ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %idxs @@ -1528,8 +1528,8 @@ define <4 x float> @mgather_truemask_v4f32(<4 x float*> %ptrs, <4 x float> %pass ; RV64-LABEL: mgather_truemask_v4f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v10, (zero), v8 +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -1575,19 +1575,19 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(float* %base, <8 x i8> %idxs, <8 ; RV32-LABEL: mgather_baseidx_v8i8_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t +; RV32-NEXT: vsext.vf4 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 +; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i8_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t ; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i8> %idxs @@ -1599,19 +1599,19 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(float* %base, <8 x i8> %idxs ; RV32-LABEL: mgather_baseidx_sext_v8i8_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t +; RV32-NEXT: vsext.vf4 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 +; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t ; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i32> @@ -1624,19 +1624,19 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(float* %base, <8 x i8> %idxs ; RV32-LABEL: mgather_baseidx_zext_v8i8_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t +; RV32-NEXT: vzext.vf4 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 +; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t ; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i32> @@ -1649,19 +1649,19 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(float* %base, <8 x i16> %idxs, < ; RV32-LABEL: mgather_baseidx_v8i16_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t +; RV32-NEXT: vsext.vf2 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 +; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i16_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t ; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i16> %idxs @@ -1673,19 +1673,19 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(float* %base, <8 x i16> %id ; RV32-LABEL: mgather_baseidx_sext_v8i16_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t +; RV32-NEXT: vsext.vf2 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 +; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i16_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t ; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i32> @@ -1698,19 +1698,19 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(float* %base, <8 x i16> %id ; RV32-LABEL: mgather_baseidx_zext_v8i16_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t +; RV32-NEXT: vzext.vf2 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 +; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i16_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t ; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i32> @@ -1723,18 +1723,18 @@ define <8 x float> @mgather_baseidx_v8f32(float* %base, <8 x i32> %idxs, <8 x i1 ; RV32-LABEL: mgather_baseidx_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v8, 2 -; RV32-NEXT: vluxei32.v v10, (a0), v26, v0.t +; RV32-NEXT: vsll.vi v8, v8, 2 +; RV32-NEXT: vluxei32.v v10, (a0), v8, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf2 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v10, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v10, (a0), v12, v0.t ; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %idxs @@ -1806,8 +1806,8 @@ define <4 x double> @mgather_truemask_v4f64(<4 x double*> %ptrs, <4 x double> %p ; RV32-LABEL: mgather_truemask_v4f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vluxei32.v v26, (zero), v8 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vluxei32.v v10, (zero), v8 +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_v4f64: @@ -1859,19 +1859,19 @@ define <8 x double> @mgather_baseidx_v8i8_v8f64(double* %base, <8 x i8> %idxs, < ; RV32-LABEL: mgather_baseidx_v8i8_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i8_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vsext.vf8 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i8> %idxs @@ -1883,18 +1883,18 @@ define <8 x double> @mgather_baseidx_sext_v8i8_v8f64(double* %base, <8 x i8> %id ; RV32-LABEL: mgather_baseidx_sext_v8i8_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsext.vf8 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV32-NEXT: vsext.vf8 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vsext.vf8 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> @@ -1907,18 +1907,18 @@ define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(double* %base, <8 x i8> %id ; RV32-LABEL: mgather_baseidx_zext_v8i8_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vzext.vf8 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV32-NEXT: vzext.vf8 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vzext.vf8 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> @@ -1931,19 +1931,19 @@ define <8 x double> @mgather_baseidx_v8i16_v8f64(double* %base, <8 x i16> %idxs, ; RV32-LABEL: mgather_baseidx_v8i16_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i16_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vsext.vf4 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i16> %idxs @@ -1955,18 +1955,18 @@ define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(double* %base, <8 x i16> % ; RV32-LABEL: mgather_baseidx_sext_v8i16_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV32-NEXT: vsext.vf4 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i16_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vsext.vf4 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> @@ -1979,18 +1979,18 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(double* %base, <8 x i16> % ; RV32-LABEL: mgather_baseidx_zext_v8i16_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vzext.vf4 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV32-NEXT: vzext.vf4 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i16_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vzext.vf4 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> @@ -2003,18 +2003,18 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(double* %base, <8 x i32> %idxs, ; RV32-LABEL: mgather_baseidx_v8i32_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v8, 3 +; RV32-NEXT: vsll.vi v8, v8, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v12, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8i32_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vsext.vf2 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i32> %idxs @@ -2026,18 +2026,18 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(double* %base, <8 x i32> % ; RV32-LABEL: mgather_baseidx_sext_v8i32_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV32-NEXT: vsext.vf2 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_sext_v8i32_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vsext.vf2 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> @@ -2050,18 +2050,18 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(double* %base, <8 x i32> % ; RV32-LABEL: mgather_baseidx_zext_v8i32_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vzext.vf2 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV32-NEXT: vzext.vf2 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 3 +; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_zext_v8i32_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf2 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vzext.vf2 v16, v8 +; RV64-NEXT: vsll.vi v8, v16, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> @@ -2074,16 +2074,16 @@ define <8 x double> @mgather_baseidx_v8f64(double* %base, <8 x i64> %idxs, <8 x ; RV32-LABEL: mgather_baseidx_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsll.vi v28, v8, 3 -; RV32-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV32-NEXT: vsll.vi v8, v8, 3 +; RV32-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_baseidx_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsll.vi v28, v8, 3 -; RV64-NEXT: vluxei64.v v12, (a0), v28, v0.t +; RV64-NEXT: vsll.vi v8, v8, 3 +; RV64-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %idxs @@ -2097,9 +2097,9 @@ define <16 x i8> @mgather_baseidx_v16i8(i8* %base, <16 x i8> %idxs, <16 x i1> %m ; RV32-LABEL: mgather_baseidx_v16i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v8 +; RV32-NEXT: vsext.vf4 v12, v8 ; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; RV32-NEXT: vluxei32.v v9, (a0), v28, v0.t +; RV32-NEXT: vluxei32.v v9, (a0), v12, v0.t ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; @@ -2131,20 +2131,20 @@ define <32 x i8> @mgather_baseidx_v32i8(i8* %base, <32 x i8> %idxs, <32 x i1> %m ; ; RV64-LABEL: mgather_baseidx_v32i8: ; RV64: # %bb.0: -; RV64-NEXT: vmv1r.v v25, v0 +; RV64-NEXT: vmv1r.v v12, v0 ; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, mu -; RV64-NEXT: vslidedown.vi v26, v10, 16 -; RV64-NEXT: vslidedown.vi v28, v8, 16 +; RV64-NEXT: vslidedown.vi v14, v10, 16 +; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vsext.vf8 v16, v28 +; RV64-NEXT: vsext.vf8 v24, v16 ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV64-NEXT: vluxei64.v v26, (a0), v16, v0.t +; RV64-NEXT: vluxei64.v v14, (a0), v24, v0.t ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV64-NEXT: vsext.vf8 v16, v8 ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; RV64-NEXT: vmv1r.v v0, v25 +; RV64-NEXT: vmv1r.v v0, v12 ; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t ; RV64-NEXT: addi a0, zero, 32 ; RV64-NEXT: vsetvli zero, a0, e8, m2, ta, mu @@ -2152,7 +2152,7 @@ define <32 x i8> @mgather_baseidx_v32i8(i8* %base, <32 x i8> %idxs, <32 x i1> %m ; RV64-NEXT: vsetivli zero, 16, e8, m2, tu, mu ; RV64-NEXT: vslideup.vi v8, v10, 0 ; RV64-NEXT: vsetvli zero, a0, e8, m2, tu, mu -; RV64-NEXT: vslideup.vi v8, v26, 16 +; RV64-NEXT: vslideup.vi v8, v14, 16 ; RV64-NEXT: ret %ptrs = getelementptr inbounds i8, i8* %base, <32 x i8> %idxs %v = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> %ptrs, i32 2, <32 x i1> %m, <32 x i8> %passthru) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll index b235508bad16fb1ee1dbaa1ac7f4caae734405f4..591f7a2bbc95d8de33e9f20d88a0c66faa4624d9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll @@ -6,11 +6,11 @@ define void @masked_load_v1f16(<1 x half>* %a, <1 x half>* %m_ptr, <1 x half>* % ; CHECK-LABEL: masked_load_v1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: fmv.h.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v25, ft0 -; CHECK-NEXT: vle16.v v25, (a0), v0.t -; CHECK-NEXT: vse16.v v25, (a2) +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %m = load <1 x half>, <1 x half>* %m_ptr %mask = fcmp oeq <1 x half> %m, zeroinitializer @@ -24,11 +24,11 @@ define void @masked_load_v1f32(<1 x float>* %a, <1 x float>* %m_ptr, <1 x float> ; CHECK-LABEL: masked_load_v1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: fmv.w.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v25, ft0 -; CHECK-NEXT: vle32.v v25, (a0), v0.t -; CHECK-NEXT: vse32.v v25, (a2) +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %m = load <1 x float>, <1 x float>* %m_ptr %mask = fcmp oeq <1 x float> %m, zeroinitializer @@ -42,21 +42,21 @@ define void @masked_load_v1f64(<1 x double>* %a, <1 x double>* %m_ptr, <1 x doub ; RV32-LABEL: masked_load_v1f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a1) +; RV32-NEXT: vle64.v v8, (a1) ; RV32-NEXT: fcvt.d.w ft0, zero -; RV32-NEXT: vmfeq.vf v0, v25, ft0 -; RV32-NEXT: vle64.v v25, (a0), v0.t -; RV32-NEXT: vse64.v v25, (a2) +; RV32-NEXT: vmfeq.vf v0, v8, ft0 +; RV32-NEXT: vle64.v v8, (a0), v0.t +; RV32-NEXT: vse64.v v8, (a2) ; RV32-NEXT: ret ; ; RV64-LABEL: masked_load_v1f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a1) +; RV64-NEXT: vle64.v v8, (a1) ; RV64-NEXT: fmv.d.x ft0, zero -; RV64-NEXT: vmfeq.vf v0, v25, ft0 -; RV64-NEXT: vle64.v v25, (a0), v0.t -; RV64-NEXT: vse64.v v25, (a2) +; RV64-NEXT: vmfeq.vf v0, v8, ft0 +; RV64-NEXT: vle64.v v8, (a0), v0.t +; RV64-NEXT: vse64.v v8, (a2) ; RV64-NEXT: ret %m = load <1 x double>, <1 x double>* %m_ptr %mask = fcmp oeq <1 x double> %m, zeroinitializer @@ -70,11 +70,11 @@ define void @masked_load_v2f16(<2 x half>* %a, <2 x half>* %m_ptr, <2 x half>* % ; CHECK-LABEL: masked_load_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: fmv.h.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v25, ft0 -; CHECK-NEXT: vle16.v v25, (a0), v0.t -; CHECK-NEXT: vse16.v v25, (a2) +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %m = load <2 x half>, <2 x half>* %m_ptr %mask = fcmp oeq <2 x half> %m, zeroinitializer @@ -88,11 +88,11 @@ define void @masked_load_v2f32(<2 x float>* %a, <2 x float>* %m_ptr, <2 x float> ; CHECK-LABEL: masked_load_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: fmv.w.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v25, ft0 -; CHECK-NEXT: vle32.v v25, (a0), v0.t -; CHECK-NEXT: vse32.v v25, (a2) +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %m = load <2 x float>, <2 x float>* %m_ptr %mask = fcmp oeq <2 x float> %m, zeroinitializer @@ -106,21 +106,21 @@ define void @masked_load_v2f64(<2 x double>* %a, <2 x double>* %m_ptr, <2 x doub ; RV32-LABEL: masked_load_v2f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a1) +; RV32-NEXT: vle64.v v8, (a1) ; RV32-NEXT: fcvt.d.w ft0, zero -; RV32-NEXT: vmfeq.vf v0, v25, ft0 -; RV32-NEXT: vle64.v v25, (a0), v0.t -; RV32-NEXT: vse64.v v25, (a2) +; RV32-NEXT: vmfeq.vf v0, v8, ft0 +; RV32-NEXT: vle64.v v8, (a0), v0.t +; RV32-NEXT: vse64.v v8, (a2) ; RV32-NEXT: ret ; ; RV64-LABEL: masked_load_v2f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a1) +; RV64-NEXT: vle64.v v8, (a1) ; RV64-NEXT: fmv.d.x ft0, zero -; RV64-NEXT: vmfeq.vf v0, v25, ft0 -; RV64-NEXT: vle64.v v25, (a0), v0.t -; RV64-NEXT: vse64.v v25, (a2) +; RV64-NEXT: vmfeq.vf v0, v8, ft0 +; RV64-NEXT: vle64.v v8, (a0), v0.t +; RV64-NEXT: vse64.v v8, (a2) ; RV64-NEXT: ret %m = load <2 x double>, <2 x double>* %m_ptr %mask = fcmp oeq <2 x double> %m, zeroinitializer @@ -134,11 +134,11 @@ define void @masked_load_v4f16(<4 x half>* %a, <4 x half>* %m_ptr, <4 x half>* % ; CHECK-LABEL: masked_load_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: fmv.h.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v25, ft0 -; CHECK-NEXT: vle16.v v25, (a0), v0.t -; CHECK-NEXT: vse16.v v25, (a2) +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %m = load <4 x half>, <4 x half>* %m_ptr %mask = fcmp oeq <4 x half> %m, zeroinitializer @@ -152,11 +152,11 @@ define void @masked_load_v4f32(<4 x float>* %a, <4 x float>* %m_ptr, <4 x float> ; CHECK-LABEL: masked_load_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a1) +; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: fmv.w.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v25, ft0 -; CHECK-NEXT: vle32.v v25, (a0), v0.t -; CHECK-NEXT: vse32.v v25, (a2) +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %m = load <4 x float>, <4 x float>* %m_ptr %mask = fcmp oeq <4 x float> %m, zeroinitializer @@ -170,21 +170,21 @@ define void @masked_load_v4f64(<4 x double>* %a, <4 x double>* %m_ptr, <4 x doub ; RV32-LABEL: masked_load_v4f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vle64.v v26, (a1) +; RV32-NEXT: vle64.v v8, (a1) ; RV32-NEXT: fcvt.d.w ft0, zero -; RV32-NEXT: vmfeq.vf v0, v26, ft0 -; RV32-NEXT: vle64.v v26, (a0), v0.t -; RV32-NEXT: vse64.v v26, (a2) +; RV32-NEXT: vmfeq.vf v0, v8, ft0 +; RV32-NEXT: vle64.v v8, (a0), v0.t +; RV32-NEXT: vse64.v v8, (a2) ; RV32-NEXT: ret ; ; RV64-LABEL: masked_load_v4f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v26, (a1) +; RV64-NEXT: vle64.v v8, (a1) ; RV64-NEXT: fmv.d.x ft0, zero -; RV64-NEXT: vmfeq.vf v0, v26, ft0 -; RV64-NEXT: vle64.v v26, (a0), v0.t -; RV64-NEXT: vse64.v v26, (a2) +; RV64-NEXT: vmfeq.vf v0, v8, ft0 +; RV64-NEXT: vle64.v v8, (a0), v0.t +; RV64-NEXT: vse64.v v8, (a2) ; RV64-NEXT: ret %m = load <4 x double>, <4 x double>* %m_ptr %mask = fcmp oeq <4 x double> %m, zeroinitializer @@ -198,11 +198,11 @@ define void @masked_load_v8f16(<8 x half>* %a, <8 x half>* %m_ptr, <8 x half>* % ; CHECK-LABEL: masked_load_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a1) +; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: fmv.h.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v25, ft0 -; CHECK-NEXT: vle16.v v25, (a0), v0.t -; CHECK-NEXT: vse16.v v25, (a2) +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %m = load <8 x half>, <8 x half>* %m_ptr %mask = fcmp oeq <8 x half> %m, zeroinitializer @@ -216,11 +216,11 @@ define void @masked_load_v8f32(<8 x float>* %a, <8 x float>* %m_ptr, <8 x float> ; CHECK-LABEL: masked_load_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a1) +; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: fmv.w.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v26, ft0 -; CHECK-NEXT: vle32.v v26, (a0), v0.t -; CHECK-NEXT: vse32.v v26, (a2) +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %m = load <8 x float>, <8 x float>* %m_ptr %mask = fcmp oeq <8 x float> %m, zeroinitializer @@ -234,21 +234,21 @@ define void @masked_load_v8f64(<8 x double>* %a, <8 x double>* %m_ptr, <8 x doub ; RV32-LABEL: masked_load_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vle64.v v28, (a1) +; RV32-NEXT: vle64.v v8, (a1) ; RV32-NEXT: fcvt.d.w ft0, zero -; RV32-NEXT: vmfeq.vf v0, v28, ft0 -; RV32-NEXT: vle64.v v28, (a0), v0.t -; RV32-NEXT: vse64.v v28, (a2) +; RV32-NEXT: vmfeq.vf v0, v8, ft0 +; RV32-NEXT: vle64.v v8, (a0), v0.t +; RV32-NEXT: vse64.v v8, (a2) ; RV32-NEXT: ret ; ; RV64-LABEL: masked_load_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v28, (a1) +; RV64-NEXT: vle64.v v8, (a1) ; RV64-NEXT: fmv.d.x ft0, zero -; RV64-NEXT: vmfeq.vf v0, v28, ft0 -; RV64-NEXT: vle64.v v28, (a0), v0.t -; RV64-NEXT: vse64.v v28, (a2) +; RV64-NEXT: vmfeq.vf v0, v8, ft0 +; RV64-NEXT: vle64.v v8, (a0), v0.t +; RV64-NEXT: vse64.v v8, (a2) ; RV64-NEXT: ret %m = load <8 x double>, <8 x double>* %m_ptr %mask = fcmp oeq <8 x double> %m, zeroinitializer @@ -262,11 +262,11 @@ define void @masked_load_v16f16(<16 x half>* %a, <16 x half>* %m_ptr, <16 x half ; CHECK-LABEL: masked_load_v16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a1) +; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: fmv.h.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v26, ft0 -; CHECK-NEXT: vle16.v v26, (a0), v0.t -; CHECK-NEXT: vse16.v v26, (a2) +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %m = load <16 x half>, <16 x half>* %m_ptr %mask = fcmp oeq <16 x half> %m, zeroinitializer @@ -280,11 +280,11 @@ define void @masked_load_v16f32(<16 x float>* %a, <16 x float>* %m_ptr, <16 x fl ; CHECK-LABEL: masked_load_v16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a1) +; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: fmv.w.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v28, ft0 -; CHECK-NEXT: vle32.v v28, (a0), v0.t -; CHECK-NEXT: vse32.v v28, (a2) +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %m = load <16 x float>, <16 x float>* %m_ptr %mask = fcmp oeq <16 x float> %m, zeroinitializer @@ -327,11 +327,11 @@ define void @masked_load_v32f16(<32 x half>* %a, <32 x half>* %m_ptr, <32 x half ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 32 ; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a1) +; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: fmv.h.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v28, ft0 -; CHECK-NEXT: vle16.v v28, (a0), v0.t -; CHECK-NEXT: vse16.v v28, (a2) +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %m = load <32 x half>, <32 x half>* %m_ptr %mask = fcmp oeq <32 x half> %m, zeroinitializer @@ -365,36 +365,36 @@ define void @masked_load_v32f64(<32 x double>* %a, <32 x double>* %m_ptr, <32 x ; RV32: # %bb.0: ; RV32-NEXT: addi a3, a1, 128 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vle64.v v8, (a1) -; RV32-NEXT: vle64.v v16, (a3) +; RV32-NEXT: vle64.v v16, (a1) +; RV32-NEXT: vle64.v v24, (a3) ; RV32-NEXT: fcvt.d.w ft0, zero -; RV32-NEXT: vmfeq.vf v25, v8, ft0 -; RV32-NEXT: vmfeq.vf v0, v16, ft0 +; RV32-NEXT: vmfeq.vf v8, v16, ft0 +; RV32-NEXT: vmfeq.vf v0, v24, ft0 ; RV32-NEXT: addi a1, a0, 128 -; RV32-NEXT: vle64.v v8, (a1), v0.t -; RV32-NEXT: vmv1r.v v0, v25 -; RV32-NEXT: vle64.v v16, (a0), v0.t -; RV32-NEXT: vse64.v v16, (a2) +; RV32-NEXT: vle64.v v16, (a1), v0.t +; RV32-NEXT: vmv1r.v v0, v8 +; RV32-NEXT: vle64.v v8, (a0), v0.t +; RV32-NEXT: vse64.v v8, (a2) ; RV32-NEXT: addi a0, a2, 128 -; RV32-NEXT: vse64.v v8, (a0) +; RV32-NEXT: vse64.v v16, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: masked_load_v32f64: ; RV64: # %bb.0: ; RV64-NEXT: addi a3, a1, 128 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vle64.v v8, (a1) -; RV64-NEXT: vle64.v v16, (a3) +; RV64-NEXT: vle64.v v16, (a1) +; RV64-NEXT: vle64.v v24, (a3) ; RV64-NEXT: fmv.d.x ft0, zero -; RV64-NEXT: vmfeq.vf v25, v8, ft0 -; RV64-NEXT: vmfeq.vf v0, v16, ft0 +; RV64-NEXT: vmfeq.vf v8, v16, ft0 +; RV64-NEXT: vmfeq.vf v0, v24, ft0 ; RV64-NEXT: addi a1, a0, 128 -; RV64-NEXT: vle64.v v8, (a1), v0.t -; RV64-NEXT: vmv1r.v v0, v25 -; RV64-NEXT: vle64.v v16, (a0), v0.t -; RV64-NEXT: vse64.v v16, (a2) +; RV64-NEXT: vle64.v v16, (a1), v0.t +; RV64-NEXT: vmv1r.v v0, v8 +; RV64-NEXT: vle64.v v8, (a0), v0.t +; RV64-NEXT: vse64.v v8, (a2) ; RV64-NEXT: addi a0, a2, 128 -; RV64-NEXT: vse64.v v8, (a0) +; RV64-NEXT: vse64.v v16, (a0) ; RV64-NEXT: ret %m = load <32 x double>, <32 x double>* %m_ptr %mask = fcmp oeq <32 x double> %m, zeroinitializer @@ -429,18 +429,18 @@ define void @masked_load_v64f32(<64 x float>* %a, <64 x float>* %m_ptr, <64 x fl ; CHECK-NEXT: addi a3, a1, 128 ; CHECK-NEXT: addi a4, zero, 32 ; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vle32.v v16, (a3) +; CHECK-NEXT: vle32.v v16, (a1) +; CHECK-NEXT: vle32.v v24, (a3) ; CHECK-NEXT: fmv.w.x ft0, zero -; CHECK-NEXT: vmfeq.vf v25, v8, ft0 -; CHECK-NEXT: vmfeq.vf v0, v16, ft0 +; CHECK-NEXT: vmfeq.vf v8, v16, ft0 +; CHECK-NEXT: vmfeq.vf v0, v24, ft0 ; CHECK-NEXT: addi a1, a0, 128 -; CHECK-NEXT: vle32.v v8, (a1), v0.t -; CHECK-NEXT: vmv1r.v v0, v25 -; CHECK-NEXT: vle32.v v16, (a0), v0.t -; CHECK-NEXT: vse32.v v16, (a2) +; CHECK-NEXT: vle32.v v16, (a1), v0.t +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: addi a0, a2, 128 -; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: vse32.v v16, (a0) ; CHECK-NEXT: ret %m = load <64 x float>, <64 x float>* %m_ptr %mask = fcmp oeq <64 x float> %m, zeroinitializer @@ -456,18 +456,18 @@ define void @masked_load_v128f16(<128 x half>* %a, <128 x half>* %m_ptr, <128 x ; CHECK-NEXT: addi a3, a1, 128 ; CHECK-NEXT: addi a4, zero, 64 ; CHECK-NEXT: vsetvli zero, a4, e16, m8, ta, mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vle16.v v16, (a3) +; CHECK-NEXT: vle16.v v16, (a1) +; CHECK-NEXT: vle16.v v24, (a3) ; CHECK-NEXT: fmv.h.x ft0, zero -; CHECK-NEXT: vmfeq.vf v25, v8, ft0 -; CHECK-NEXT: vmfeq.vf v0, v16, ft0 +; CHECK-NEXT: vmfeq.vf v8, v16, ft0 +; CHECK-NEXT: vmfeq.vf v0, v24, ft0 ; CHECK-NEXT: addi a1, a0, 128 -; CHECK-NEXT: vle16.v v8, (a1), v0.t -; CHECK-NEXT: vmv1r.v v0, v25 -; CHECK-NEXT: vle16.v v16, (a0), v0.t -; CHECK-NEXT: vse16.v v16, (a2) +; CHECK-NEXT: vle16.v v16, (a1), v0.t +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: addi a0, a2, 128 -; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: vse16.v v16, (a0) ; CHECK-NEXT: ret %m = load <128 x half>, <128 x half>* %m_ptr %mask = fcmp oeq <128 x half> %m, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll index b87f54ddfa36f54725f3c0c0be3677d9f2fde024..c66e968de5c040079022e5fe604bb3404d02fed7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll @@ -6,10 +6,10 @@ define void @masked_load_v1i8(<1 x i8>* %a, <1 x i8>* %m_ptr, <1 x i8>* %res_ptr ; CHECK-LABEL: masked_load_v1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vle8.v v25, (a0), v0.t -; CHECK-NEXT: vse8.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: vse8.v v8, (a2) ; CHECK-NEXT: ret %m = load <1 x i8>, <1 x i8>* %m_ptr %mask = icmp eq <1 x i8> %m, zeroinitializer @@ -23,10 +23,10 @@ define void @masked_load_v1i16(<1 x i16>* %a, <1 x i16>* %m_ptr, <1 x i16>* %res ; CHECK-LABEL: masked_load_v1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a1) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vle16.v v25, (a0), v0.t -; CHECK-NEXT: vse16.v v25, (a2) +; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %m = load <1 x i16>, <1 x i16>* %m_ptr %mask = icmp eq <1 x i16> %m, zeroinitializer @@ -40,10 +40,10 @@ define void @masked_load_v1i32(<1 x i32>* %a, <1 x i32>* %m_ptr, <1 x i32>* %res ; CHECK-LABEL: masked_load_v1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a1) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vle32.v v25, (a0), v0.t -; CHECK-NEXT: vse32.v v25, (a2) +; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %m = load <1 x i32>, <1 x i32>* %m_ptr %mask = icmp eq <1 x i32> %m, zeroinitializer @@ -57,10 +57,10 @@ define void @masked_load_v1i64(<1 x i64>* %a, <1 x i64>* %m_ptr, <1 x i64>* %res ; CHECK-LABEL: masked_load_v1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a1) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vle64.v v25, (a0), v0.t -; CHECK-NEXT: vse64.v v25, (a2) +; CHECK-NEXT: vle64.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: vse64.v v8, (a2) ; CHECK-NEXT: ret %m = load <1 x i64>, <1 x i64>* %m_ptr %mask = icmp eq <1 x i64> %m, zeroinitializer @@ -74,10 +74,10 @@ define void @masked_load_v2i8(<2 x i8>* %a, <2 x i8>* %m_ptr, <2 x i8>* %res_ptr ; CHECK-LABEL: masked_load_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vle8.v v25, (a0), v0.t -; CHECK-NEXT: vse8.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: vse8.v v8, (a2) ; CHECK-NEXT: ret %m = load <2 x i8>, <2 x i8>* %m_ptr %mask = icmp eq <2 x i8> %m, zeroinitializer @@ -91,10 +91,10 @@ define void @masked_load_v2i16(<2 x i16>* %a, <2 x i16>* %m_ptr, <2 x i16>* %res ; CHECK-LABEL: masked_load_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a1) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vle16.v v25, (a0), v0.t -; CHECK-NEXT: vse16.v v25, (a2) +; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %m = load <2 x i16>, <2 x i16>* %m_ptr %mask = icmp eq <2 x i16> %m, zeroinitializer @@ -108,10 +108,10 @@ define void @masked_load_v2i32(<2 x i32>* %a, <2 x i32>* %m_ptr, <2 x i32>* %res ; CHECK-LABEL: masked_load_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a1) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vle32.v v25, (a0), v0.t -; CHECK-NEXT: vse32.v v25, (a2) +; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %m = load <2 x i32>, <2 x i32>* %m_ptr %mask = icmp eq <2 x i32> %m, zeroinitializer @@ -125,10 +125,10 @@ define void @masked_load_v2i64(<2 x i64>* %a, <2 x i64>* %m_ptr, <2 x i64>* %res ; CHECK-LABEL: masked_load_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a1) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vle64.v v25, (a0), v0.t -; CHECK-NEXT: vse64.v v25, (a2) +; CHECK-NEXT: vle64.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: vse64.v v8, (a2) ; CHECK-NEXT: ret %m = load <2 x i64>, <2 x i64>* %m_ptr %mask = icmp eq <2 x i64> %m, zeroinitializer @@ -142,10 +142,10 @@ define void @masked_load_v4i8(<4 x i8>* %a, <4 x i8>* %m_ptr, <4 x i8>* %res_ptr ; CHECK-LABEL: masked_load_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vle8.v v25, (a0), v0.t -; CHECK-NEXT: vse8.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: vse8.v v8, (a2) ; CHECK-NEXT: ret %m = load <4 x i8>, <4 x i8>* %m_ptr %mask = icmp eq <4 x i8> %m, zeroinitializer @@ -159,10 +159,10 @@ define void @masked_load_v4i16(<4 x i16>* %a, <4 x i16>* %m_ptr, <4 x i16>* %res ; CHECK-LABEL: masked_load_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a1) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vle16.v v25, (a0), v0.t -; CHECK-NEXT: vse16.v v25, (a2) +; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %m = load <4 x i16>, <4 x i16>* %m_ptr %mask = icmp eq <4 x i16> %m, zeroinitializer @@ -176,10 +176,10 @@ define void @masked_load_v4i32(<4 x i32>* %a, <4 x i32>* %m_ptr, <4 x i32>* %res ; CHECK-LABEL: masked_load_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a1) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vle32.v v25, (a0), v0.t -; CHECK-NEXT: vse32.v v25, (a2) +; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %m = load <4 x i32>, <4 x i32>* %m_ptr %mask = icmp eq <4 x i32> %m, zeroinitializer @@ -193,10 +193,10 @@ define void @masked_load_v4i64(<4 x i64>* %a, <4 x i64>* %m_ptr, <4 x i64>* %res ; CHECK-LABEL: masked_load_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a1) -; CHECK-NEXT: vmseq.vi v0, v26, 0 -; CHECK-NEXT: vle64.v v26, (a0), v0.t -; CHECK-NEXT: vse64.v v26, (a2) +; CHECK-NEXT: vle64.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: vse64.v v8, (a2) ; CHECK-NEXT: ret %m = load <4 x i64>, <4 x i64>* %m_ptr %mask = icmp eq <4 x i64> %m, zeroinitializer @@ -210,10 +210,10 @@ define void @masked_load_v8i8(<8 x i8>* %a, <8 x i8>* %m_ptr, <8 x i8>* %res_ptr ; CHECK-LABEL: masked_load_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vle8.v v25, (a0), v0.t -; CHECK-NEXT: vse8.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: vse8.v v8, (a2) ; CHECK-NEXT: ret %m = load <8 x i8>, <8 x i8>* %m_ptr %mask = icmp eq <8 x i8> %m, zeroinitializer @@ -227,10 +227,10 @@ define void @masked_load_v8i16(<8 x i16>* %a, <8 x i16>* %m_ptr, <8 x i16>* %res ; CHECK-LABEL: masked_load_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a1) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vle16.v v25, (a0), v0.t -; CHECK-NEXT: vse16.v v25, (a2) +; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %m = load <8 x i16>, <8 x i16>* %m_ptr %mask = icmp eq <8 x i16> %m, zeroinitializer @@ -244,10 +244,10 @@ define void @masked_load_v8i32(<8 x i32>* %a, <8 x i32>* %m_ptr, <8 x i32>* %res ; CHECK-LABEL: masked_load_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vmseq.vi v0, v26, 0 -; CHECK-NEXT: vle32.v v26, (a0), v0.t -; CHECK-NEXT: vse32.v v26, (a2) +; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %m = load <8 x i32>, <8 x i32>* %m_ptr %mask = icmp eq <8 x i32> %m, zeroinitializer @@ -261,10 +261,10 @@ define void @masked_load_v8i64(<8 x i64>* %a, <8 x i64>* %m_ptr, <8 x i64>* %res ; CHECK-LABEL: masked_load_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vle64.v v28, (a1) -; CHECK-NEXT: vmseq.vi v0, v28, 0 -; CHECK-NEXT: vle64.v v28, (a0), v0.t -; CHECK-NEXT: vse64.v v28, (a2) +; CHECK-NEXT: vle64.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: vse64.v v8, (a2) ; CHECK-NEXT: ret %m = load <8 x i64>, <8 x i64>* %m_ptr %mask = icmp eq <8 x i64> %m, zeroinitializer @@ -278,10 +278,10 @@ define void @masked_load_v16i8(<16 x i8>* %a, <16 x i8>* %m_ptr, <16 x i8>* %res ; CHECK-LABEL: masked_load_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vle8.v v25, (a0), v0.t -; CHECK-NEXT: vse8.v v25, (a2) +; CHECK-NEXT: vle8.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: vse8.v v8, (a2) ; CHECK-NEXT: ret %m = load <16 x i8>, <16 x i8>* %m_ptr %mask = icmp eq <16 x i8> %m, zeroinitializer @@ -295,10 +295,10 @@ define void @masked_load_v16i16(<16 x i16>* %a, <16 x i16>* %m_ptr, <16 x i16>* ; CHECK-LABEL: masked_load_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vmseq.vi v0, v26, 0 -; CHECK-NEXT: vle16.v v26, (a0), v0.t -; CHECK-NEXT: vse16.v v26, (a2) +; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %m = load <16 x i16>, <16 x i16>* %m_ptr %mask = icmp eq <16 x i16> %m, zeroinitializer @@ -312,10 +312,10 @@ define void @masked_load_v16i32(<16 x i32>* %a, <16 x i32>* %m_ptr, <16 x i32>* ; CHECK-LABEL: masked_load_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vmseq.vi v0, v28, 0 -; CHECK-NEXT: vle32.v v28, (a0), v0.t -; CHECK-NEXT: vse32.v v28, (a2) +; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %m = load <16 x i32>, <16 x i32>* %m_ptr %mask = icmp eq <16 x i32> %m, zeroinitializer @@ -347,10 +347,10 @@ define void @masked_load_v32i8(<32 x i8>* %a, <32 x i8>* %m_ptr, <32 x i8>* %res ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 32 ; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vmseq.vi v0, v26, 0 -; CHECK-NEXT: vle8.v v26, (a0), v0.t -; CHECK-NEXT: vse8.v v26, (a2) +; CHECK-NEXT: vle8.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: vse8.v v8, (a2) ; CHECK-NEXT: ret %m = load <32 x i8>, <32 x i8>* %m_ptr %mask = icmp eq <32 x i8> %m, zeroinitializer @@ -365,10 +365,10 @@ define void @masked_load_v32i16(<32 x i16>* %a, <32 x i16>* %m_ptr, <32 x i16>* ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 32 ; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vmseq.vi v0, v28, 0 -; CHECK-NEXT: vle16.v v28, (a0), v0.t -; CHECK-NEXT: vse16.v v28, (a2) +; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %m = load <32 x i16>, <32 x i16>* %m_ptr %mask = icmp eq <32 x i16> %m, zeroinitializer @@ -399,52 +399,40 @@ declare <32 x i32> @llvm.masked.load.v32i32(<32 x i32>*, i32, <32 x i1>, <32 x i define void @masked_load_v32i64(<32 x i64>* %a, <32 x i64>* %m_ptr, <32 x i64>* %res_ptr) nounwind { ; RV32-LABEL: masked_load_v32i64: ; RV32: # %bb.0: -; RV32-NEXT: addi sp, sp, -16 -; RV32-NEXT: csrr a3, vlenb -; RV32-NEXT: slli a3, a3, 3 -; RV32-NEXT: sub sp, sp, a3 ; RV32-NEXT: addi a3, a1, 128 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vle64.v v8, (a3) -; RV32-NEXT: addi a3, sp, 16 -; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; RV32-NEXT: vle64.v v16, (a1) +; RV32-NEXT: vle64.v v16, (a3) +; RV32-NEXT: vle64.v v0, (a1) ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; RV32-NEXT: vmv.v.i v8, 0 +; RV32-NEXT: vmv.v.i v24, 0 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vmseq.vv v25, v16, v8 -; RV32-NEXT: addi a1, sp, 16 -; RV32-NEXT: vl8re8.v v16, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vmseq.vv v0, v16, v8 +; RV32-NEXT: vmseq.vv v8, v0, v24 +; RV32-NEXT: vmseq.vv v0, v16, v24 ; RV32-NEXT: addi a1, a0, 128 -; RV32-NEXT: vle64.v v8, (a1), v0.t -; RV32-NEXT: vmv1r.v v0, v25 -; RV32-NEXT: vle64.v v16, (a0), v0.t -; RV32-NEXT: vse64.v v16, (a2) +; RV32-NEXT: vle64.v v16, (a1), v0.t +; RV32-NEXT: vmv1r.v v0, v8 +; RV32-NEXT: vle64.v v8, (a0), v0.t +; RV32-NEXT: vse64.v v8, (a2) ; RV32-NEXT: addi a0, a2, 128 -; RV32-NEXT: vse64.v v8, (a0) -; RV32-NEXT: csrr a0, vlenb -; RV32-NEXT: slli a0, a0, 3 -; RV32-NEXT: add sp, sp, a0 -; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: vse64.v v16, (a0) ; RV32-NEXT: ret ; ; RV64-LABEL: masked_load_v32i64: ; RV64: # %bb.0: ; RV64-NEXT: addi a3, a1, 128 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vle64.v v8, (a1) -; RV64-NEXT: vle64.v v16, (a3) -; RV64-NEXT: vmseq.vi v25, v8, 0 -; RV64-NEXT: vmseq.vi v0, v16, 0 +; RV64-NEXT: vle64.v v16, (a1) +; RV64-NEXT: vle64.v v24, (a3) +; RV64-NEXT: vmseq.vi v8, v16, 0 +; RV64-NEXT: vmseq.vi v0, v24, 0 ; RV64-NEXT: addi a1, a0, 128 -; RV64-NEXT: vle64.v v8, (a1), v0.t -; RV64-NEXT: vmv1r.v v0, v25 -; RV64-NEXT: vle64.v v16, (a0), v0.t -; RV64-NEXT: vse64.v v16, (a2) +; RV64-NEXT: vle64.v v16, (a1), v0.t +; RV64-NEXT: vmv1r.v v0, v8 +; RV64-NEXT: vle64.v v8, (a0), v0.t +; RV64-NEXT: vse64.v v8, (a2) ; RV64-NEXT: addi a0, a2, 128 -; RV64-NEXT: vse64.v v8, (a0) +; RV64-NEXT: vse64.v v16, (a0) ; RV64-NEXT: ret %m = load <32 x i64>, <32 x i64>* %m_ptr %mask = icmp eq <32 x i64> %m, zeroinitializer @@ -459,10 +447,10 @@ define void @masked_load_v64i8(<64 x i8>* %a, <64 x i8>* %m_ptr, <64 x i8>* %res ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 64 ; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vmseq.vi v0, v28, 0 -; CHECK-NEXT: vle8.v v28, (a0), v0.t -; CHECK-NEXT: vse8.v v28, (a2) +; CHECK-NEXT: vle8.v v8, (a1) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: vse8.v v8, (a2) ; CHECK-NEXT: ret %m = load <64 x i8>, <64 x i8>* %m_ptr %mask = icmp eq <64 x i8> %m, zeroinitializer @@ -496,17 +484,17 @@ define void @masked_load_v64i32(<64 x i32>* %a, <64 x i32>* %m_ptr, <64 x i32>* ; CHECK-NEXT: addi a3, a1, 128 ; CHECK-NEXT: addi a4, zero, 32 ; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vle32.v v16, (a3) -; CHECK-NEXT: vmseq.vi v25, v8, 0 -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vle32.v v16, (a1) +; CHECK-NEXT: vle32.v v24, (a3) +; CHECK-NEXT: vmseq.vi v8, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v24, 0 ; CHECK-NEXT: addi a1, a0, 128 -; CHECK-NEXT: vle32.v v8, (a1), v0.t -; CHECK-NEXT: vmv1r.v v0, v25 -; CHECK-NEXT: vle32.v v16, (a0), v0.t -; CHECK-NEXT: vse32.v v16, (a2) +; CHECK-NEXT: vle32.v v16, (a1), v0.t +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: addi a0, a2, 128 -; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: vse32.v v16, (a0) ; CHECK-NEXT: ret %m = load <64 x i32>, <64 x i32>* %m_ptr %mask = icmp eq <64 x i32> %m, zeroinitializer @@ -540,17 +528,17 @@ define void @masked_load_v256i8(<256 x i8>* %a, <256 x i8>* %m_ptr, <256 x i8>* ; CHECK-NEXT: addi a3, a1, 128 ; CHECK-NEXT: addi a4, zero, 128 ; CHECK-NEXT: vsetvli zero, a4, e8, m8, ta, mu -; CHECK-NEXT: vle8.v v8, (a1) -; CHECK-NEXT: vle8.v v16, (a3) -; CHECK-NEXT: vmseq.vi v25, v8, 0 -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vle8.v v16, (a1) +; CHECK-NEXT: vle8.v v24, (a3) +; CHECK-NEXT: vmseq.vi v8, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v24, 0 ; CHECK-NEXT: addi a1, a0, 128 -; CHECK-NEXT: vle8.v v8, (a1), v0.t -; CHECK-NEXT: vmv1r.v v0, v25 -; CHECK-NEXT: vle8.v v16, (a0), v0.t -; CHECK-NEXT: vse8.v v16, (a2) +; CHECK-NEXT: vle8.v v16, (a1), v0.t +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: vse8.v v8, (a2) ; CHECK-NEXT: addi a0, a2, 128 -; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: vse8.v v16, (a0) ; CHECK-NEXT: ret %m = load <256 x i8>, <256 x i8>* %m_ptr %mask = icmp eq <256 x i8> %m, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll index 5f4e7b8c10164f0cacf1e2eae7b0572c4113eaa1..e738b95d03fff0342a78dc594cc91d10c21184c3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll @@ -44,15 +44,15 @@ define void @mscatter_v2i16_truncstore_v2i8(<2 x i16> %val, <2 x i8*> %ptrs, <2 ; RV32-LABEL: mscatter_v2i16_truncstore_v2i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV32-NEXT: vnsrl.wi v25, v8, 0 -; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: vnsrl.wi v8, v8, 0 +; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i16_truncstore_v2i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV64-NEXT: vnsrl.wi v25, v8, 0 -; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: vnsrl.wi v8, v8, 0 +; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: ret %tval = trunc <2 x i16> %val to <2 x i8> call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m) @@ -63,19 +63,19 @@ define void @mscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x i8*> %ptrs, <2 ; RV32-LABEL: mscatter_v2i32_truncstore_v2i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV32-NEXT: vnsrl.wi v25, v8, 0 +; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; RV32-NEXT: vnsrl.wi v25, v25, 0 -; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: vnsrl.wi v8, v8, 0 +; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i32_truncstore_v2i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV64-NEXT: vnsrl.wi v25, v8, 0 +; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; RV64-NEXT: vnsrl.wi v25, v25, 0 -; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: vnsrl.wi v8, v8, 0 +; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: ret %tval = trunc <2 x i32> %val to <2 x i8> call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m) @@ -86,23 +86,23 @@ define void @mscatter_v2i64_truncstore_v2i8(<2 x i64> %val, <2 x i8*> %ptrs, <2 ; RV32-LABEL: mscatter_v2i64_truncstore_v2i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vnsrl.wi v25, v8, 0 +; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; RV32-NEXT: vnsrl.wi v25, v25, 0 +; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; RV32-NEXT: vnsrl.wi v25, v25, 0 -; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: vnsrl.wi v8, v8, 0 +; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i64_truncstore_v2i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vnsrl.wi v25, v8, 0 +; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; RV64-NEXT: vnsrl.wi v25, v25, 0 +; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; RV64-NEXT: vnsrl.wi v25, v25, 0 -; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: vnsrl.wi v8, v8, 0 +; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: ret %tval = trunc <2 x i64> %val to <2 x i8> call void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, i32 1, <2 x i1> %m) @@ -179,17 +179,17 @@ define void @mscatter_baseidx_v8i8(<8 x i8> %val, i8* %base, <8 x i8> %idxs, <8 ; RV32-LABEL: mscatter_baseidx_v8i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v9 +; RV32-NEXT: vsext.vf4 v10, v9 ; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v9 +; RV64-NEXT: vsext.vf8 v12, v9 ; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i8, i8* %base, <8 x i8> %idxs call void @llvm.masked.scatter.v8i8.v8p0i8(<8 x i8> %val, <8 x i8*> %ptrs, i32 1, <8 x i1> %m) @@ -236,15 +236,15 @@ define void @mscatter_v2i32_truncstore_v2i16(<2 x i32> %val, <2 x i16*> %ptrs, < ; RV32-LABEL: mscatter_v2i32_truncstore_v2i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV32-NEXT: vnsrl.wi v25, v8, 0 -; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: vnsrl.wi v8, v8, 0 +; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i32_truncstore_v2i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV64-NEXT: vnsrl.wi v25, v8, 0 -; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: vnsrl.wi v8, v8, 0 +; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: ret %tval = trunc <2 x i32> %val to <2 x i16> call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, i32 2, <2 x i1> %m) @@ -255,19 +255,19 @@ define void @mscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x i16*> %ptrs, < ; RV32-LABEL: mscatter_v2i64_truncstore_v2i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vnsrl.wi v25, v8, 0 +; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; RV32-NEXT: vnsrl.wi v25, v25, 0 -; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: vnsrl.wi v8, v8, 0 +; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i64_truncstore_v2i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vnsrl.wi v25, v8, 0 +; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; RV64-NEXT: vnsrl.wi v25, v25, 0 -; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: vnsrl.wi v8, v8, 0 +; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: ret %tval = trunc <2 x i64> %val to <2 x i16> call void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, i32 2, <2 x i1> %m) @@ -344,19 +344,19 @@ define void @mscatter_baseidx_v8i8_v8i16(<8 x i16> %val, i16* %base, <8 x i8> %i ; RV32-LABEL: mscatter_baseidx_v8i8_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i8_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i16, i16* %base, <8 x i8> %idxs call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> %val, <8 x i16*> %ptrs, i32 2, <8 x i1> %m) @@ -367,19 +367,19 @@ define void @mscatter_baseidx_sext_v8i8_v8i16(<8 x i16> %val, i16* %base, <8 x i ; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs @@ -391,19 +391,19 @@ define void @mscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, i16* %base, <8 x i ; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vzext.vf4 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vzext.vf8 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs @@ -415,19 +415,19 @@ define void @mscatter_baseidx_v8i16(<8 x i16> %val, i16* %base, <8 x i16> %idxs, ; RV32-LABEL: mscatter_baseidx_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf2 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf4 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %idxs call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> %val, <8 x i16*> %ptrs, i32 2, <8 x i1> %m) @@ -474,15 +474,15 @@ define void @mscatter_v2i64_truncstore_v2i32(<2 x i64> %val, <2 x i32*> %ptrs, < ; RV32-LABEL: mscatter_v2i64_truncstore_v2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vnsrl.wi v25, v8, 0 -; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: vnsrl.wi v8, v8, 0 +; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_v2i64_truncstore_v2i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vnsrl.wi v25, v8, 0 -; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: vnsrl.wi v8, v8, 0 +; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: ret %tval = trunc <2 x i64> %val to <2 x i32> call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %tval, <2 x i32*> %ptrs, i32 4, <2 x i1> %m) @@ -559,18 +559,18 @@ define void @mscatter_baseidx_v8i8_v8i32(<8 x i32> %val, i32* %base, <8 x i8> %i ; RV32-LABEL: mscatter_baseidx_v8i8_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i8_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i8> %idxs call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, i32 4, <8 x i1> %m) @@ -581,18 +581,18 @@ define void @mscatter_baseidx_sext_v8i8_v8i32(<8 x i32> %val, i32* %base, <8 x i ; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -604,18 +604,18 @@ define void @mscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, i32* %base, <8 x i ; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vzext.vf4 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf8 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -627,18 +627,18 @@ define void @mscatter_baseidx_v8i16_v8i32(<8 x i32> %val, i32* %base, <8 x i16> ; RV32-LABEL: mscatter_baseidx_v8i16_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsext.vf2 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i16_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i16> %idxs call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, i32 4, <8 x i1> %m) @@ -649,18 +649,18 @@ define void @mscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, i32* %base, <8 x ; RV32-LABEL: mscatter_baseidx_sext_v8i16_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsext.vf2 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -672,18 +672,18 @@ define void @mscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, i32* %base, <8 x ; RV32-LABEL: mscatter_baseidx_zext_v8i16_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf2 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vzext.vf2 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf4 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf4 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -695,17 +695,17 @@ define void @mscatter_baseidx_v8i32(<8 x i32> %val, i32* %base, <8 x i32> %idxs, ; RV32-LABEL: mscatter_baseidx_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v10, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsll.vi v10, v10, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf2 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %idxs call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, i32 4, <8 x i1> %m) @@ -818,18 +818,18 @@ define void @mscatter_baseidx_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i8> %i ; RV32-LABEL: mscatter_baseidx_v8i8_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v12 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf4 v14, v12 +; RV32-NEXT: vsll.vi v12, v14, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i8_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsext.vf8 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i8> %idxs call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m) @@ -840,17 +840,17 @@ define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i ; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsext.vf8 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: vsext.vf8 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsext.vf8 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -862,17 +862,17 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i ; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vzext.vf8 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: vzext.vf8 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vzext.vf8 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -884,18 +884,18 @@ define void @mscatter_baseidx_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x i16> ; RV32-LABEL: mscatter_baseidx_v8i16_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v12 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf2 v14, v12 +; RV32-NEXT: vsll.vi v12, v14, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i16_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsext.vf4 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i16> %idxs call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m) @@ -906,17 +906,17 @@ define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x ; RV32-LABEL: mscatter_baseidx_sext_v8i16_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: vsext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsext.vf4 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -928,17 +928,17 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x ; RV32-LABEL: mscatter_baseidx_zext_v8i16_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vzext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: vzext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf4 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vzext.vf4 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -950,17 +950,17 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x i32> ; RV32-LABEL: mscatter_baseidx_v8i32_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v12, 3 +; RV32-NEXT: vsll.vi v12, v12, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i32_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsext.vf2 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i32> %idxs call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m) @@ -971,17 +971,17 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x ; RV32-LABEL: mscatter_baseidx_sext_v8i32_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: vsext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i32_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsext.vf2 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -993,17 +993,17 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x ; RV32-LABEL: mscatter_baseidx_zext_v8i32_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vzext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: vzext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i32_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf2 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vzext.vf2 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -1015,15 +1015,15 @@ define void @mscatter_baseidx_v8i64(<8 x i64> %val, i64* %base, <8 x i64> %idxs, ; RV32-LABEL: mscatter_baseidx_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsll.vi v28, v12, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: vsll.vi v12, v12, 3 +; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsll.vi v28, v12, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsll.vi v12, v12, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %idxs call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, i32 8, <8 x i1> %m) @@ -1136,19 +1136,19 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, half* %base, <8 x i8> ; RV32-LABEL: mscatter_baseidx_v8i8_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i8_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds half, half* %base, <8 x i8> %idxs call void @llvm.masked.scatter.v8f16.v8p0f16(<8 x half> %val, <8 x half*> %ptrs, i32 2, <8 x i1> %m) @@ -1159,19 +1159,19 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, half* %base, <8 x ; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs @@ -1183,19 +1183,19 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, half* %base, <8 x ; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vzext.vf4 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vzext.vf8 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs @@ -1207,19 +1207,19 @@ define void @mscatter_baseidx_v8f16(<8 x half> %val, half* %base, <8 x i16> %idx ; RV32-LABEL: mscatter_baseidx_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf2 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf4 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %idxs call void @llvm.masked.scatter.v8f16.v8p0f16(<8 x half> %val, <8 x half*> %ptrs, i32 2, <8 x i1> %m) @@ -1332,18 +1332,18 @@ define void @mscatter_baseidx_v8i8_v8f32(<8 x float> %val, float* %base, <8 x i8 ; RV32-LABEL: mscatter_baseidx_v8i8_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i8_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i8> %idxs call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, i32 4, <8 x i1> %m) @@ -1354,18 +1354,18 @@ define void @mscatter_baseidx_sext_v8i8_v8f32(<8 x float> %val, float* %base, <8 ; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1377,18 +1377,18 @@ define void @mscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, float* %base, <8 ; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vzext.vf4 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf8 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1400,18 +1400,18 @@ define void @mscatter_baseidx_v8i16_v8f32(<8 x float> %val, float* %base, <8 x i ; RV32-LABEL: mscatter_baseidx_v8i16_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsext.vf2 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i16_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i16> %idxs call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, i32 4, <8 x i1> %m) @@ -1422,18 +1422,18 @@ define void @mscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, float* %base, < ; RV32-LABEL: mscatter_baseidx_sext_v8i16_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsext.vf2 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1445,18 +1445,18 @@ define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, float* %base, < ; RV32-LABEL: mscatter_baseidx_zext_v8i16_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf2 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vzext.vf2 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf4 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf4 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1468,17 +1468,17 @@ define void @mscatter_baseidx_v8f32(<8 x float> %val, float* %base, <8 x i32> %i ; RV32-LABEL: mscatter_baseidx_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v10, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsll.vi v10, v10, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf2 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %idxs call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, i32 4, <8 x i1> %m) @@ -1591,18 +1591,18 @@ define void @mscatter_baseidx_v8i8_v8f64(<8 x double> %val, double* %base, <8 x ; RV32-LABEL: mscatter_baseidx_v8i8_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v12 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf4 v14, v12 +; RV32-NEXT: vsll.vi v12, v14, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i8_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsext.vf8 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i8> %idxs call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m) @@ -1613,17 +1613,17 @@ define void @mscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, double* %base, ; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsext.vf8 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: vsext.vf8 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsext.vf8 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1635,17 +1635,17 @@ define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, double* %base, ; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vzext.vf8 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: vzext.vf8 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vzext.vf8 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1657,18 +1657,18 @@ define void @mscatter_baseidx_v8i16_v8f64(<8 x double> %val, double* %base, <8 x ; RV32-LABEL: mscatter_baseidx_v8i16_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v12 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf2 v14, v12 +; RV32-NEXT: vsll.vi v12, v14, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i16_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsext.vf4 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i16> %idxs call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m) @@ -1679,17 +1679,17 @@ define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, double* %base, ; RV32-LABEL: mscatter_baseidx_sext_v8i16_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: vsext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i16_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsext.vf4 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1701,17 +1701,17 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, double* %base, ; RV32-LABEL: mscatter_baseidx_zext_v8i16_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vzext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: vzext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i16_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf4 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vzext.vf4 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1723,17 +1723,17 @@ define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, double* %base, <8 x ; RV32-LABEL: mscatter_baseidx_v8i32_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v12, 3 +; RV32-NEXT: vsll.vi v12, v12, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8i32_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsext.vf2 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i32> %idxs call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m) @@ -1744,17 +1744,17 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, double* %base, ; RV32-LABEL: mscatter_baseidx_sext_v8i32_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: vsext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_v8i32_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsext.vf2 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1766,17 +1766,17 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, double* %base, ; RV32-LABEL: mscatter_baseidx_zext_v8i32_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vzext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: vzext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 3 +; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_v8i32_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf2 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vzext.vf2 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1788,15 +1788,15 @@ define void @mscatter_baseidx_v8f64(<8 x double> %val, double* %base, <8 x i64> ; RV32-LABEL: mscatter_baseidx_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vsll.vi v28, v12, 3 -; RV32-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV32-NEXT: vsll.vi v12, v12, 3 +; RV32-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsll.vi v28, v12, 3 -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsll.vi v12, v12, 3 +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %idxs call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, i32 8, <8 x i1> %m) @@ -1809,9 +1809,9 @@ define void @mscatter_baseidx_v16i8(<16 x i8> %val, i8* %base, <16 x i8> %idxs, ; RV32-LABEL: mscatter_baseidx_v16i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v9 +; RV32-NEXT: vsext.vf4 v12, v9 ; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_v16i8: @@ -1845,14 +1845,14 @@ define void @mscatter_baseidx_v32i8(<32 x i8> %val, i8* %base, <32 x i8> %idxs, ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, mu -; RV64-NEXT: vslidedown.vi v26, v8, 16 -; RV64-NEXT: vslidedown.vi v28, v10, 16 +; RV64-NEXT: vslidedown.vi v8, v8, 16 +; RV64-NEXT: vslidedown.vi v10, v10, 16 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vsext.vf8 v8, v28 +; RV64-NEXT: vsext.vf8 v16, v10 ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV64-NEXT: vsoxei64.v v26, (a0), v8, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i8, i8* %base, <32 x i8> %idxs call void @llvm.masked.scatter.v32i8.v32p0i8(<32 x i8> %val, <32 x i8*> %ptrs, i32 1, <32 x i1> %m) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll index 0885acb3e4d885d3cd3783caa1f1eacf346608f0..f9c105e6eddc0ae0c9a3e0c40cc857e69716ff26 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll @@ -6,11 +6,11 @@ define void @masked_store_v1f16(<1 x half>* %val_ptr, <1 x half>* %a, <1 x half> ; CHECK-LABEL: masked_store_v1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a2) -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a2) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: fmv.h.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v25, ft0 -; CHECK-NEXT: vse16.v v26, (a1), v0.t +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vse16.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <1 x half>, <1 x half>* %m_ptr %mask = fcmp oeq <1 x half> %m, zeroinitializer @@ -24,11 +24,11 @@ define void @masked_store_v1f32(<1 x float>* %val_ptr, <1 x float>* %a, <1 x flo ; CHECK-LABEL: masked_store_v1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a2) -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a2) +; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: fmv.w.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v25, ft0 -; CHECK-NEXT: vse32.v v26, (a1), v0.t +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vse32.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <1 x float>, <1 x float>* %m_ptr %mask = fcmp oeq <1 x float> %m, zeroinitializer @@ -42,21 +42,21 @@ define void @masked_store_v1f64(<1 x double>* %val_ptr, <1 x double>* %a, <1 x d ; RV32-LABEL: masked_store_v1f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a2) -; RV32-NEXT: vle64.v v26, (a0) +; RV32-NEXT: vle64.v v8, (a2) +; RV32-NEXT: vle64.v v9, (a0) ; RV32-NEXT: fcvt.d.w ft0, zero -; RV32-NEXT: vmfeq.vf v0, v25, ft0 -; RV32-NEXT: vse64.v v26, (a1), v0.t +; RV32-NEXT: vmfeq.vf v0, v8, ft0 +; RV32-NEXT: vse64.v v9, (a1), v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: masked_store_v1f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a2) -; RV64-NEXT: vle64.v v26, (a0) +; RV64-NEXT: vle64.v v8, (a2) +; RV64-NEXT: vle64.v v9, (a0) ; RV64-NEXT: fmv.d.x ft0, zero -; RV64-NEXT: vmfeq.vf v0, v25, ft0 -; RV64-NEXT: vse64.v v26, (a1), v0.t +; RV64-NEXT: vmfeq.vf v0, v8, ft0 +; RV64-NEXT: vse64.v v9, (a1), v0.t ; RV64-NEXT: ret %m = load <1 x double>, <1 x double>* %m_ptr %mask = fcmp oeq <1 x double> %m, zeroinitializer @@ -70,11 +70,11 @@ define void @masked_store_v2f16(<2 x half>* %val_ptr, <2 x half>* %a, <2 x half> ; CHECK-LABEL: masked_store_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a2) -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a2) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: fmv.h.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v25, ft0 -; CHECK-NEXT: vse16.v v26, (a1), v0.t +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vse16.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <2 x half>, <2 x half>* %m_ptr %mask = fcmp oeq <2 x half> %m, zeroinitializer @@ -88,11 +88,11 @@ define void @masked_store_v2f32(<2 x float>* %val_ptr, <2 x float>* %a, <2 x flo ; CHECK-LABEL: masked_store_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a2) -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a2) +; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: fmv.w.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v25, ft0 -; CHECK-NEXT: vse32.v v26, (a1), v0.t +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vse32.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <2 x float>, <2 x float>* %m_ptr %mask = fcmp oeq <2 x float> %m, zeroinitializer @@ -106,21 +106,21 @@ define void @masked_store_v2f64(<2 x double>* %val_ptr, <2 x double>* %a, <2 x d ; RV32-LABEL: masked_store_v2f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a2) -; RV32-NEXT: vle64.v v26, (a0) +; RV32-NEXT: vle64.v v8, (a2) +; RV32-NEXT: vle64.v v9, (a0) ; RV32-NEXT: fcvt.d.w ft0, zero -; RV32-NEXT: vmfeq.vf v0, v25, ft0 -; RV32-NEXT: vse64.v v26, (a1), v0.t +; RV32-NEXT: vmfeq.vf v0, v8, ft0 +; RV32-NEXT: vse64.v v9, (a1), v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: masked_store_v2f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a2) -; RV64-NEXT: vle64.v v26, (a0) +; RV64-NEXT: vle64.v v8, (a2) +; RV64-NEXT: vle64.v v9, (a0) ; RV64-NEXT: fmv.d.x ft0, zero -; RV64-NEXT: vmfeq.vf v0, v25, ft0 -; RV64-NEXT: vse64.v v26, (a1), v0.t +; RV64-NEXT: vmfeq.vf v0, v8, ft0 +; RV64-NEXT: vse64.v v9, (a1), v0.t ; RV64-NEXT: ret %m = load <2 x double>, <2 x double>* %m_ptr %mask = fcmp oeq <2 x double> %m, zeroinitializer @@ -134,11 +134,11 @@ define void @masked_store_v4f16(<4 x half>* %val_ptr, <4 x half>* %a, <4 x half> ; CHECK-LABEL: masked_store_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a2) -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a2) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: fmv.h.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v25, ft0 -; CHECK-NEXT: vse16.v v26, (a1), v0.t +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vse16.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <4 x half>, <4 x half>* %m_ptr %mask = fcmp oeq <4 x half> %m, zeroinitializer @@ -152,11 +152,11 @@ define void @masked_store_v4f32(<4 x float>* %val_ptr, <4 x float>* %a, <4 x flo ; CHECK-LABEL: masked_store_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a2) -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a2) +; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: fmv.w.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v25, ft0 -; CHECK-NEXT: vse32.v v26, (a1), v0.t +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vse32.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <4 x float>, <4 x float>* %m_ptr %mask = fcmp oeq <4 x float> %m, zeroinitializer @@ -170,21 +170,21 @@ define void @masked_store_v4f64(<4 x double>* %val_ptr, <4 x double>* %a, <4 x d ; RV32-LABEL: masked_store_v4f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vle64.v v26, (a2) -; RV32-NEXT: vle64.v v28, (a0) +; RV32-NEXT: vle64.v v8, (a2) +; RV32-NEXT: vle64.v v10, (a0) ; RV32-NEXT: fcvt.d.w ft0, zero -; RV32-NEXT: vmfeq.vf v0, v26, ft0 -; RV32-NEXT: vse64.v v28, (a1), v0.t +; RV32-NEXT: vmfeq.vf v0, v8, ft0 +; RV32-NEXT: vse64.v v10, (a1), v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: masked_store_v4f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v26, (a2) -; RV64-NEXT: vle64.v v28, (a0) +; RV64-NEXT: vle64.v v8, (a2) +; RV64-NEXT: vle64.v v10, (a0) ; RV64-NEXT: fmv.d.x ft0, zero -; RV64-NEXT: vmfeq.vf v0, v26, ft0 -; RV64-NEXT: vse64.v v28, (a1), v0.t +; RV64-NEXT: vmfeq.vf v0, v8, ft0 +; RV64-NEXT: vse64.v v10, (a1), v0.t ; RV64-NEXT: ret %m = load <4 x double>, <4 x double>* %m_ptr %mask = fcmp oeq <4 x double> %m, zeroinitializer @@ -198,11 +198,11 @@ define void @masked_store_v8f16(<8 x half>* %val_ptr, <8 x half>* %a, <8 x half> ; CHECK-LABEL: masked_store_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a2) -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a2) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: fmv.h.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v25, ft0 -; CHECK-NEXT: vse16.v v26, (a1), v0.t +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vse16.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <8 x half>, <8 x half>* %m_ptr %mask = fcmp oeq <8 x half> %m, zeroinitializer @@ -216,11 +216,11 @@ define void @masked_store_v8f32(<8 x float>* %val_ptr, <8 x float>* %a, <8 x flo ; CHECK-LABEL: masked_store_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a2) -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vle32.v v8, (a2) +; CHECK-NEXT: vle32.v v10, (a0) ; CHECK-NEXT: fmv.w.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v26, ft0 -; CHECK-NEXT: vse32.v v28, (a1), v0.t +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vse32.v v10, (a1), v0.t ; CHECK-NEXT: ret %m = load <8 x float>, <8 x float>* %m_ptr %mask = fcmp oeq <8 x float> %m, zeroinitializer @@ -234,21 +234,21 @@ define void @masked_store_v8f64(<8 x double>* %val_ptr, <8 x double>* %a, <8 x d ; RV32-LABEL: masked_store_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vle64.v v28, (a2) -; RV32-NEXT: vle64.v v8, (a0) +; RV32-NEXT: vle64.v v8, (a2) +; RV32-NEXT: vle64.v v12, (a0) ; RV32-NEXT: fcvt.d.w ft0, zero -; RV32-NEXT: vmfeq.vf v0, v28, ft0 -; RV32-NEXT: vse64.v v8, (a1), v0.t +; RV32-NEXT: vmfeq.vf v0, v8, ft0 +; RV32-NEXT: vse64.v v12, (a1), v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: masked_store_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v28, (a2) -; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vle64.v v8, (a2) +; RV64-NEXT: vle64.v v12, (a0) ; RV64-NEXT: fmv.d.x ft0, zero -; RV64-NEXT: vmfeq.vf v0, v28, ft0 -; RV64-NEXT: vse64.v v8, (a1), v0.t +; RV64-NEXT: vmfeq.vf v0, v8, ft0 +; RV64-NEXT: vse64.v v12, (a1), v0.t ; RV64-NEXT: ret %m = load <8 x double>, <8 x double>* %m_ptr %mask = fcmp oeq <8 x double> %m, zeroinitializer @@ -262,11 +262,11 @@ define void @masked_store_v16f16(<16 x half>* %val_ptr, <16 x half>* %a, <16 x h ; CHECK-LABEL: masked_store_v16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a2) -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vle16.v v8, (a2) +; CHECK-NEXT: vle16.v v10, (a0) ; CHECK-NEXT: fmv.h.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v26, ft0 -; CHECK-NEXT: vse16.v v28, (a1), v0.t +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vse16.v v10, (a1), v0.t ; CHECK-NEXT: ret %m = load <16 x half>, <16 x half>* %m_ptr %mask = fcmp oeq <16 x half> %m, zeroinitializer @@ -280,11 +280,11 @@ define void @masked_store_v16f32(<16 x float>* %val_ptr, <16 x float>* %a, <16 x ; CHECK-LABEL: masked_store_v16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a2) -; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v8, (a2) +; CHECK-NEXT: vle32.v v12, (a0) ; CHECK-NEXT: fmv.w.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v28, ft0 -; CHECK-NEXT: vse32.v v8, (a1), v0.t +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vse32.v v12, (a1), v0.t ; CHECK-NEXT: ret %m = load <16 x float>, <16 x float>* %m_ptr %mask = fcmp oeq <16 x float> %m, zeroinitializer @@ -327,11 +327,11 @@ define void @masked_store_v32f16(<32 x half>* %val_ptr, <32 x half>* %a, <32 x h ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 32 ; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a2) -; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v8, (a2) +; CHECK-NEXT: vle16.v v12, (a0) ; CHECK-NEXT: fmv.h.x ft0, zero -; CHECK-NEXT: vmfeq.vf v0, v28, ft0 -; CHECK-NEXT: vse16.v v8, (a1), v0.t +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: vse16.v v12, (a1), v0.t ; CHECK-NEXT: ret %m = load <32 x half>, <32 x half>* %m_ptr %mask = fcmp oeq <32 x half> %m, zeroinitializer @@ -378,20 +378,20 @@ define void @masked_store_v32f64(<32 x double>* %val_ptr, <32 x double>* %a, <32 ; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: vmfeq.vf v0, v8, ft0 -; RV32-NEXT: vle64.v v8, (a0) +; RV32-NEXT: vle64.v v24, (a0) ; RV32-NEXT: addi a0, a0, 128 -; RV32-NEXT: vle64.v v16, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a0, sp, 16 -; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill +; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload -; RV32-NEXT: vmfeq.vf v25, v16, ft0 -; RV32-NEXT: vse64.v v8, (a1), v0.t +; RV32-NEXT: vmfeq.vf v8, v16, ft0 +; RV32-NEXT: vse64.v v24, (a1), v0.t ; RV32-NEXT: addi a0, a1, 128 -; RV32-NEXT: vmv1r.v v0, v25 +; RV32-NEXT: vmv1r.v v0, v8 ; RV32-NEXT: addi a1, sp, 16 ; RV32-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vse64.v v8, (a0), v0.t @@ -418,20 +418,20 @@ define void @masked_store_v32f64(<32 x double>* %val_ptr, <32 x double>* %a, <32 ; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: vmfeq.vf v0, v8, ft0 -; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vle64.v v24, (a0) ; RV64-NEXT: addi a0, a0, 128 -; RV64-NEXT: vle64.v v16, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: addi a0, sp, 16 -; RV64-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill +; RV64-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: slli a0, a0, 3 ; RV64-NEXT: add a0, sp, a0 ; RV64-NEXT: addi a0, a0, 16 ; RV64-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload -; RV64-NEXT: vmfeq.vf v25, v16, ft0 -; RV64-NEXT: vse64.v v8, (a1), v0.t +; RV64-NEXT: vmfeq.vf v8, v16, ft0 +; RV64-NEXT: vse64.v v24, (a1), v0.t ; RV64-NEXT: addi a0, a1, 128 -; RV64-NEXT: vmv1r.v v0, v25 +; RV64-NEXT: vmv1r.v v0, v8 ; RV64-NEXT: addi a1, sp, 16 ; RV64-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vse64.v v8, (a0), v0.t @@ -486,20 +486,20 @@ define void @masked_store_v64f32(<64 x float>* %val_ptr, <64 x float>* %a, <64 x ; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: vmfeq.vf v0, v8, ft0 -; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: addi a0, a0, 128 -; CHECK-NEXT: vle32.v v16, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: addi a0, sp, 16 -; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill +; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload -; CHECK-NEXT: vmfeq.vf v25, v16, ft0 -; CHECK-NEXT: vse32.v v8, (a1), v0.t +; CHECK-NEXT: vmfeq.vf v8, v16, ft0 +; CHECK-NEXT: vse32.v v24, (a1), v0.t ; CHECK-NEXT: addi a0, a1, 128 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vse32.v v8, (a0), v0.t @@ -535,20 +535,20 @@ define void @masked_store_v128f16(<128 x half>* %val_ptr, <128 x half>* %a, <128 ; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: fmv.h.x ft0, zero ; CHECK-NEXT: vmfeq.vf v0, v8, ft0 -; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: addi a0, a0, 128 -; CHECK-NEXT: vle16.v v16, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: addi a0, sp, 16 -; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill +; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload -; CHECK-NEXT: vmfeq.vf v25, v16, ft0 -; CHECK-NEXT: vse16.v v8, (a1), v0.t +; CHECK-NEXT: vmfeq.vf v8, v16, ft0 +; CHECK-NEXT: vse16.v v24, (a1), v0.t ; CHECK-NEXT: addi a0, a1, 128 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vse16.v v8, (a0), v0.t diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll index dc04ba99372f33be64f93923687858870c254872..036510dc0f528423a28e031f9217209370efe616 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll @@ -6,10 +6,10 @@ define void @masked_store_v1i8(<1 x i8>* %val_ptr, <1 x i8>* %a, <1 x i8>* %m_pt ; CHECK-LABEL: masked_store_v1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a2) -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vse8.v v26, (a1), v0.t +; CHECK-NEXT: vle8.v v8, (a2) +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse8.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <1 x i8>, <1 x i8>* %m_ptr %mask = icmp eq <1 x i8> %m, zeroinitializer @@ -23,10 +23,10 @@ define void @masked_store_v1i16(<1 x i16>* %val_ptr, <1 x i16>* %a, <1 x i16>* % ; CHECK-LABEL: masked_store_v1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a2) -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vse16.v v26, (a1), v0.t +; CHECK-NEXT: vle16.v v8, (a2) +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse16.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <1 x i16>, <1 x i16>* %m_ptr %mask = icmp eq <1 x i16> %m, zeroinitializer @@ -40,10 +40,10 @@ define void @masked_store_v1i32(<1 x i32>* %val_ptr, <1 x i32>* %a, <1 x i32>* % ; CHECK-LABEL: masked_store_v1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a2) -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vse32.v v26, (a1), v0.t +; CHECK-NEXT: vle32.v v8, (a2) +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse32.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <1 x i32>, <1 x i32>* %m_ptr %mask = icmp eq <1 x i32> %m, zeroinitializer @@ -57,10 +57,10 @@ define void @masked_store_v1i64(<1 x i64>* %val_ptr, <1 x i64>* %a, <1 x i64>* % ; CHECK-LABEL: masked_store_v1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a2) -; CHECK-NEXT: vle64.v v26, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vse64.v v26, (a1), v0.t +; CHECK-NEXT: vle64.v v8, (a2) +; CHECK-NEXT: vle64.v v9, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse64.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <1 x i64>, <1 x i64>* %m_ptr %mask = icmp eq <1 x i64> %m, zeroinitializer @@ -74,10 +74,10 @@ define void @masked_store_v2i8(<2 x i8>* %val_ptr, <2 x i8>* %a, <2 x i8>* %m_pt ; CHECK-LABEL: masked_store_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a2) -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vse8.v v26, (a1), v0.t +; CHECK-NEXT: vle8.v v8, (a2) +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse8.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <2 x i8>, <2 x i8>* %m_ptr %mask = icmp eq <2 x i8> %m, zeroinitializer @@ -91,10 +91,10 @@ define void @masked_store_v2i16(<2 x i16>* %val_ptr, <2 x i16>* %a, <2 x i16>* % ; CHECK-LABEL: masked_store_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a2) -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vse16.v v26, (a1), v0.t +; CHECK-NEXT: vle16.v v8, (a2) +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse16.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <2 x i16>, <2 x i16>* %m_ptr %mask = icmp eq <2 x i16> %m, zeroinitializer @@ -108,10 +108,10 @@ define void @masked_store_v2i32(<2 x i32>* %val_ptr, <2 x i32>* %a, <2 x i32>* % ; CHECK-LABEL: masked_store_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a2) -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vse32.v v26, (a1), v0.t +; CHECK-NEXT: vle32.v v8, (a2) +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse32.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <2 x i32>, <2 x i32>* %m_ptr %mask = icmp eq <2 x i32> %m, zeroinitializer @@ -125,10 +125,10 @@ define void @masked_store_v2i64(<2 x i64>* %val_ptr, <2 x i64>* %a, <2 x i64>* % ; CHECK-LABEL: masked_store_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a2) -; CHECK-NEXT: vle64.v v26, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vse64.v v26, (a1), v0.t +; CHECK-NEXT: vle64.v v8, (a2) +; CHECK-NEXT: vle64.v v9, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse64.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <2 x i64>, <2 x i64>* %m_ptr %mask = icmp eq <2 x i64> %m, zeroinitializer @@ -142,10 +142,10 @@ define void @masked_store_v4i8(<4 x i8>* %val_ptr, <4 x i8>* %a, <4 x i8>* %m_pt ; CHECK-LABEL: masked_store_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a2) -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vse8.v v26, (a1), v0.t +; CHECK-NEXT: vle8.v v8, (a2) +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse8.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <4 x i8>, <4 x i8>* %m_ptr %mask = icmp eq <4 x i8> %m, zeroinitializer @@ -159,10 +159,10 @@ define void @masked_store_v4i16(<4 x i16>* %val_ptr, <4 x i16>* %a, <4 x i16>* % ; CHECK-LABEL: masked_store_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a2) -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vse16.v v26, (a1), v0.t +; CHECK-NEXT: vle16.v v8, (a2) +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse16.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <4 x i16>, <4 x i16>* %m_ptr %mask = icmp eq <4 x i16> %m, zeroinitializer @@ -176,10 +176,10 @@ define void @masked_store_v4i32(<4 x i32>* %val_ptr, <4 x i32>* %a, <4 x i32>* % ; CHECK-LABEL: masked_store_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a2) -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vse32.v v26, (a1), v0.t +; CHECK-NEXT: vle32.v v8, (a2) +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse32.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <4 x i32>, <4 x i32>* %m_ptr %mask = icmp eq <4 x i32> %m, zeroinitializer @@ -193,10 +193,10 @@ define void @masked_store_v4i64(<4 x i64>* %val_ptr, <4 x i64>* %a, <4 x i64>* % ; CHECK-LABEL: masked_store_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a2) -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vmseq.vi v0, v26, 0 -; CHECK-NEXT: vse64.v v28, (a1), v0.t +; CHECK-NEXT: vle64.v v8, (a2) +; CHECK-NEXT: vle64.v v10, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse64.v v10, (a1), v0.t ; CHECK-NEXT: ret %m = load <4 x i64>, <4 x i64>* %m_ptr %mask = icmp eq <4 x i64> %m, zeroinitializer @@ -210,10 +210,10 @@ define void @masked_store_v8i8(<8 x i8>* %val_ptr, <8 x i8>* %a, <8 x i8>* %m_pt ; CHECK-LABEL: masked_store_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a2) -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vse8.v v26, (a1), v0.t +; CHECK-NEXT: vle8.v v8, (a2) +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse8.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <8 x i8>, <8 x i8>* %m_ptr %mask = icmp eq <8 x i8> %m, zeroinitializer @@ -227,10 +227,10 @@ define void @masked_store_v8i16(<8 x i16>* %val_ptr, <8 x i16>* %a, <8 x i16>* % ; CHECK-LABEL: masked_store_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a2) -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vse16.v v26, (a1), v0.t +; CHECK-NEXT: vle16.v v8, (a2) +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse16.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <8 x i16>, <8 x i16>* %m_ptr %mask = icmp eq <8 x i16> %m, zeroinitializer @@ -244,10 +244,10 @@ define void @masked_store_v8i32(<8 x i32>* %val_ptr, <8 x i32>* %a, <8 x i32>* % ; CHECK-LABEL: masked_store_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a2) -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vmseq.vi v0, v26, 0 -; CHECK-NEXT: vse32.v v28, (a1), v0.t +; CHECK-NEXT: vle32.v v8, (a2) +; CHECK-NEXT: vle32.v v10, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse32.v v10, (a1), v0.t ; CHECK-NEXT: ret %m = load <8 x i32>, <8 x i32>* %m_ptr %mask = icmp eq <8 x i32> %m, zeroinitializer @@ -261,10 +261,10 @@ define void @masked_store_v8i64(<8 x i64>* %val_ptr, <8 x i64>* %a, <8 x i64>* % ; CHECK-LABEL: masked_store_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vle64.v v28, (a2) -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmseq.vi v0, v28, 0 -; CHECK-NEXT: vse64.v v8, (a1), v0.t +; CHECK-NEXT: vle64.v v8, (a2) +; CHECK-NEXT: vle64.v v12, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse64.v v12, (a1), v0.t ; CHECK-NEXT: ret %m = load <8 x i64>, <8 x i64>* %m_ptr %mask = icmp eq <8 x i64> %m, zeroinitializer @@ -278,10 +278,10 @@ define void @masked_store_v16i8(<16 x i8>* %val_ptr, <16 x i8>* %a, <16 x i8>* % ; CHECK-LABEL: masked_store_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a2) -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vmseq.vi v0, v25, 0 -; CHECK-NEXT: vse8.v v26, (a1), v0.t +; CHECK-NEXT: vle8.v v8, (a2) +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse8.v v9, (a1), v0.t ; CHECK-NEXT: ret %m = load <16 x i8>, <16 x i8>* %m_ptr %mask = icmp eq <16 x i8> %m, zeroinitializer @@ -295,10 +295,10 @@ define void @masked_store_v16i16(<16 x i16>* %val_ptr, <16 x i16>* %a, <16 x i16 ; CHECK-LABEL: masked_store_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a2) -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vmseq.vi v0, v26, 0 -; CHECK-NEXT: vse16.v v28, (a1), v0.t +; CHECK-NEXT: vle16.v v8, (a2) +; CHECK-NEXT: vle16.v v10, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse16.v v10, (a1), v0.t ; CHECK-NEXT: ret %m = load <16 x i16>, <16 x i16>* %m_ptr %mask = icmp eq <16 x i16> %m, zeroinitializer @@ -312,10 +312,10 @@ define void @masked_store_v16i32(<16 x i32>* %val_ptr, <16 x i32>* %a, <16 x i32 ; CHECK-LABEL: masked_store_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a2) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmseq.vi v0, v28, 0 -; CHECK-NEXT: vse32.v v8, (a1), v0.t +; CHECK-NEXT: vle32.v v8, (a2) +; CHECK-NEXT: vle32.v v12, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse32.v v12, (a1), v0.t ; CHECK-NEXT: ret %m = load <16 x i32>, <16 x i32>* %m_ptr %mask = icmp eq <16 x i32> %m, zeroinitializer @@ -347,10 +347,10 @@ define void @masked_store_v32i8(<32 x i8>* %val_ptr, <32 x i8>* %a, <32 x i8>* % ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 32 ; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a2) -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vmseq.vi v0, v26, 0 -; CHECK-NEXT: vse8.v v28, (a1), v0.t +; CHECK-NEXT: vle8.v v8, (a2) +; CHECK-NEXT: vle8.v v10, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse8.v v10, (a1), v0.t ; CHECK-NEXT: ret %m = load <32 x i8>, <32 x i8>* %m_ptr %mask = icmp eq <32 x i8> %m, zeroinitializer @@ -365,10 +365,10 @@ define void @masked_store_v32i16(<32 x i16>* %val_ptr, <32 x i16>* %a, <32 x i16 ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 32 ; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a2) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmseq.vi v0, v28, 0 -; CHECK-NEXT: vse16.v v8, (a1), v0.t +; CHECK-NEXT: vle16.v v8, (a2) +; CHECK-NEXT: vle16.v v12, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse16.v v12, (a1), v0.t ; CHECK-NEXT: ret %m = load <32 x i16>, <32 x i16>* %m_ptr %mask = icmp eq <32 x i16> %m, zeroinitializer @@ -411,25 +411,25 @@ define void @masked_store_v32i64(<32 x i64>* %val_ptr, <32 x i64>* %a, <32 x i64 ; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; RV32-NEXT: vle64.v v16, (a2) +; RV32-NEXT: vle64.v v24, (a2) ; RV32-NEXT: addi a2, zero, 32 ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; RV32-NEXT: vmv.v.i v8, 0 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vmseq.vv v1, v16, v8 +; RV32-NEXT: vmseq.vv v1, v24, v8 ; RV32-NEXT: addi a2, a0, 128 -; RV32-NEXT: vle64.v v16, (a2) -; RV32-NEXT: vle64.v v24, (a0) +; RV32-NEXT: vle64.v v24, (a2) +; RV32-NEXT: vle64.v v16, (a0) ; RV32-NEXT: addi a0, sp, 16 -; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill +; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: addi a0, a0, 16 -; RV32-NEXT: vl8re8.v v24, (a0) # Unknown-size Folded Reload -; RV32-NEXT: vmseq.vv v0, v24, v8 +; RV32-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload +; RV32-NEXT: vmseq.vv v0, v16, v8 ; RV32-NEXT: addi a0, a1, 128 -; RV32-NEXT: vse64.v v16, (a0), v0.t +; RV32-NEXT: vse64.v v24, (a0), v0.t ; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vl8re8.v v8, (a0) # Unknown-size Folded Reload @@ -456,20 +456,20 @@ define void @masked_store_v32i64(<32 x i64>* %val_ptr, <32 x i64>* %a, <32 x i64 ; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; RV64-NEXT: vmseq.vi v0, v8, 0 -; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vle64.v v24, (a0) ; RV64-NEXT: addi a0, a0, 128 -; RV64-NEXT: vle64.v v16, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: addi a0, sp, 16 -; RV64-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill +; RV64-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: slli a0, a0, 3 ; RV64-NEXT: add a0, sp, a0 ; RV64-NEXT: addi a0, a0, 16 ; RV64-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload -; RV64-NEXT: vmseq.vi v25, v16, 0 -; RV64-NEXT: vse64.v v8, (a1), v0.t +; RV64-NEXT: vmseq.vi v8, v16, 0 +; RV64-NEXT: vse64.v v24, (a1), v0.t ; RV64-NEXT: addi a0, a1, 128 -; RV64-NEXT: vmv1r.v v0, v25 +; RV64-NEXT: vmv1r.v v0, v8 ; RV64-NEXT: addi a1, sp, 16 ; RV64-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vse64.v v8, (a0), v0.t @@ -491,10 +491,10 @@ define void @masked_store_v64i8(<64 x i8>* %val_ptr, <64 x i8>* %a, <64 x i8>* % ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, zero, 64 ; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a2) -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmseq.vi v0, v28, 0 -; CHECK-NEXT: vse8.v v8, (a1), v0.t +; CHECK-NEXT: vle8.v v8, (a2) +; CHECK-NEXT: vle8.v v12, (a0) +; CHECK-NEXT: vmseq.vi v0, v8, 0 +; CHECK-NEXT: vse8.v v12, (a1), v0.t ; CHECK-NEXT: ret %m = load <64 x i8>, <64 x i8>* %m_ptr %mask = icmp eq <64 x i8> %m, zeroinitializer @@ -540,20 +540,20 @@ define void @masked_store_v64i32(<64 x i32>* %val_ptr, <64 x i32>* %a, <64 x i32 ; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vmseq.vi v0, v8, 0 -; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: addi a0, a0, 128 -; CHECK-NEXT: vle32.v v16, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: addi a0, sp, 16 -; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill +; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload -; CHECK-NEXT: vmseq.vi v25, v16, 0 -; CHECK-NEXT: vse32.v v8, (a1), v0.t +; CHECK-NEXT: vmseq.vi v8, v16, 0 +; CHECK-NEXT: vse32.v v24, (a1), v0.t ; CHECK-NEXT: addi a0, a1, 128 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vse32.v v8, (a0), v0.t @@ -606,20 +606,20 @@ define void @masked_store_v128i16(<128 x i16>* %val_ptr, <128 x i16>* %a, <128 x ; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vmseq.vi v0, v8, 0 -; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: addi a0, a0, 128 -; CHECK-NEXT: vle16.v v16, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: addi a0, sp, 16 -; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill +; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload -; CHECK-NEXT: vmseq.vi v25, v16, 0 -; CHECK-NEXT: vse16.v v8, (a1), v0.t +; CHECK-NEXT: vmseq.vi v8, v16, 0 +; CHECK-NEXT: vse16.v v24, (a1), v0.t ; CHECK-NEXT: addi a0, a1, 128 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vse16.v v8, (a0), v0.t @@ -654,20 +654,20 @@ define void @masked_store_v256i8(<256 x i8>* %val_ptr, <256 x i8>* %a, <256 x i8 ; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vmseq.vi v0, v8, 0 -; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: addi a0, a0, 128 -; CHECK-NEXT: vle8.v v16, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, sp, 16 -; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill +; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload -; CHECK-NEXT: vmseq.vi v25, v16, 0 -; CHECK-NEXT: vse8.v v8, (a1), v0.t +; CHECK-NEXT: vmseq.vi v8, v16, 0 +; CHECK-NEXT: vse8.v v24, (a1), v0.t ; CHECK-NEXT: addi a0, a1, 128 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vse8.v v8, (a0), v0.t diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll index cbd636088b7655ad90f10e5514e695cf2d72de6d..0c7e258adad926938b3eaa16b73f16ad74a2c178 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll @@ -10,10 +10,10 @@ define half @vpreduce_fadd_v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 zeroex ; CHECK-LABEL: vpreduce_fadd_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vfmv.f.s fa0, v9 ; CHECK-NEXT: ret %r = call reassoc half @llvm.vp.reduce.fadd.v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 %evl) ret half %r @@ -23,10 +23,10 @@ define half @vpreduce_ord_fadd_v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 ze ; CHECK-LABEL: vpreduce_ord_fadd_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vfmv.f.s fa0, v9 ; CHECK-NEXT: ret %r = call half @llvm.vp.reduce.fadd.v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 %evl) ret half %r @@ -38,10 +38,10 @@ define half @vpreduce_fadd_v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 zeroex ; CHECK-LABEL: vpreduce_fadd_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vfmv.f.s fa0, v9 ; CHECK-NEXT: ret %r = call reassoc half @llvm.vp.reduce.fadd.v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 %evl) ret half %r @@ -51,10 +51,10 @@ define half @vpreduce_ord_fadd_v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 ze ; CHECK-LABEL: vpreduce_ord_fadd_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vfmv.f.s fa0, v9 ; CHECK-NEXT: ret %r = call half @llvm.vp.reduce.fadd.v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 %evl) ret half %r @@ -66,10 +66,10 @@ define float @vpreduce_fadd_v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 zer ; CHECK-LABEL: vpreduce_fadd_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vfmv.f.s fa0, v9 ; CHECK-NEXT: ret %r = call reassoc float @llvm.vp.reduce.fadd.v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 %evl) ret float %r @@ -79,10 +79,10 @@ define float @vpreduce_ord_fadd_v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 ; CHECK-LABEL: vpreduce_ord_fadd_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vfmv.f.s fa0, v9 ; CHECK-NEXT: ret %r = call float @llvm.vp.reduce.fadd.v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 %evl) ret float %r @@ -94,10 +94,10 @@ define float @vpreduce_fadd_v4f32(float %s, <4 x float> %v, <4 x i1> %m, i32 zer ; CHECK-LABEL: vpreduce_fadd_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vfmv.f.s fa0, v9 ; CHECK-NEXT: ret %r = call reassoc float @llvm.vp.reduce.fadd.v4f32(float %s, <4 x float> %v, <4 x i1> %m, i32 %evl) ret float %r @@ -107,10 +107,10 @@ define float @vpreduce_ord_fadd_v4f32(float %s, <4 x float> %v, <4 x i1> %m, i32 ; CHECK-LABEL: vpreduce_ord_fadd_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vfmv.f.s fa0, v9 ; CHECK-NEXT: ret %r = call float @llvm.vp.reduce.fadd.v4f32(float %s, <4 x float> %v, <4 x i1> %m, i32 %evl) ret float %r @@ -122,10 +122,10 @@ define double @vpreduce_fadd_v2f64(double %s, <2 x double> %v, <2 x i1> %m, i32 ; CHECK-LABEL: vpreduce_fadd_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vfmv.f.s fa0, v9 ; CHECK-NEXT: ret %r = call reassoc double @llvm.vp.reduce.fadd.v2f64(double %s, <2 x double> %v, <2 x i1> %m, i32 %evl) ret double %r @@ -135,10 +135,10 @@ define double @vpreduce_ord_fadd_v2f64(double %s, <2 x double> %v, <2 x i1> %m, ; CHECK-LABEL: vpreduce_ord_fadd_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vfmv.f.s fa0, v9 ; CHECK-NEXT: ret %r = call double @llvm.vp.reduce.fadd.v2f64(double %s, <2 x double> %v, <2 x i1> %m, i32 %evl) ret double %r @@ -150,10 +150,10 @@ define double @vpreduce_fadd_v4f64(double %s, <4 x double> %v, <4 x i1> %m, i32 ; CHECK-LABEL: vpreduce_fadd_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredusum.vs v10, v8, v10, v0.t +; CHECK-NEXT: vfmv.f.s fa0, v10 ; CHECK-NEXT: ret %r = call reassoc double @llvm.vp.reduce.fadd.v4f64(double %s, <4 x double> %v, <4 x i1> %m, i32 %evl) ret double %r @@ -163,10 +163,10 @@ define double @vpreduce_ord_fadd_v4f64(double %s, <4 x double> %v, <4 x i1> %m, ; CHECK-LABEL: vpreduce_ord_fadd_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v10, v8, v10, v0.t +; CHECK-NEXT: vfmv.f.s fa0, v10 ; CHECK-NEXT: ret %r = call double @llvm.vp.reduce.fadd.v4f64(double %s, <4 x double> %v, <4 x i1> %m, i32 %evl) ret double %r diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll index bc2139c2d81d0f52109acb81fb7d9a8692cbd1d0..ddef4af7b5584e4a4bea877156bb78207ea16e75 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll @@ -8,8 +8,8 @@ define half @vreduce_fadd_v1f16(<1 x half>* %x, half %s) { ; CHECK-LABEL: vreduce_fadd_v1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <1 x half>, <1 x half>* %x @@ -21,12 +21,12 @@ define half @vreduce_ord_fadd_v1f16(<1 x half>* %x, half %s) { ; CHECK-LABEL: vreduce_ord_fadd_v1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <1 x half>, <1 x half>* %x %red = call half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v) @@ -41,12 +41,12 @@ define half @vreduce_fadd_v2f16(<2 x half>* %x, half %s) { ; CHECK-NEXT: lui a1, %hi(.LCPI2_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a1) ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <2 x half>, <2 x half>* %x @@ -58,12 +58,12 @@ define half @vreduce_ord_fadd_v2f16(<2 x half>* %x, half %s) { ; CHECK-LABEL: vreduce_ord_fadd_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <2 x half>, <2 x half>* %x %red = call half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v) @@ -78,12 +78,12 @@ define half @vreduce_fadd_v4f16(<4 x half>* %x, half %s) { ; CHECK-NEXT: lui a1, %hi(.LCPI4_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x @@ -95,12 +95,12 @@ define half @vreduce_ord_fadd_v4f16(<4 x half>* %x, half %s) { ; CHECK-LABEL: vreduce_ord_fadd_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x %red = call half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v) @@ -115,12 +115,12 @@ define half @vreduce_fadd_v8f16(<8 x half>* %x, half %s) { ; CHECK-NEXT: lui a1, %hi(.LCPI6_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI6_0)(a1) ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <8 x half>, <8 x half>* %x @@ -132,12 +132,12 @@ define half @vreduce_ord_fadd_v8f16(<8 x half>* %x, half %s) { ; CHECK-LABEL: vreduce_ord_fadd_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <8 x half>, <8 x half>* %x %red = call half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v) @@ -152,12 +152,12 @@ define half @vreduce_fadd_v16f16(<16 x half>* %x, half %s) { ; CHECK-NEXT: lui a1, %hi(.LCPI8_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI8_0)(a1) ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v26, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <16 x half>, <16 x half>* %x @@ -169,12 +169,12 @@ define half @vreduce_ord_fadd_v16f16(<16 x half>* %x, half %s) { ; CHECK-LABEL: vreduce_ord_fadd_v16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v26, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <16 x half>, <16 x half>* %x %red = call half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v) @@ -190,12 +190,12 @@ define half @vreduce_fadd_v32f16(<32 x half>* %x, half %s) { ; RV32-NEXT: lui a2, %hi(.LCPI10_0) ; RV32-NEXT: flh ft0, %lo(.LCPI10_0)(a2) ; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; RV32-NEXT: vle16.v v28, (a0) +; RV32-NEXT: vle16.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; RV32-NEXT: vfmv.v.f v25, ft0 +; RV32-NEXT: vfmv.v.f v12, ft0 ; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; RV32-NEXT: vfredusum.vs v25, v28, v25 -; RV32-NEXT: vfmv.f.s ft0, v25 +; RV32-NEXT: vfredusum.vs v8, v8, v12 +; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: fadd.h fa0, fa0, ft0 ; RV32-NEXT: ret ; @@ -205,12 +205,12 @@ define half @vreduce_fadd_v32f16(<32 x half>* %x, half %s) { ; RV64-NEXT: flh ft0, %lo(.LCPI10_0)(a1) ; RV64-NEXT: addi a1, zero, 32 ; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; RV64-NEXT: vle16.v v28, (a0) +; RV64-NEXT: vle16.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; RV64-NEXT: vfmv.v.f v25, ft0 +; RV64-NEXT: vfmv.v.f v12, ft0 ; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; RV64-NEXT: vfredusum.vs v25, v28, v25 -; RV64-NEXT: vfmv.f.s ft0, v25 +; RV64-NEXT: vfredusum.vs v8, v8, v12 +; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: fadd.h fa0, fa0, ft0 ; RV64-NEXT: ret %v = load <32 x half>, <32 x half>* %x @@ -223,12 +223,12 @@ define half @vreduce_ord_fadd_v32f16(<32 x half>* %x, half %s) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v28, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v12 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <32 x half>, <32 x half>* %x %red = call half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v) @@ -246,10 +246,10 @@ define half @vreduce_fadd_v64f16(<64 x half>* %x, half %s) { ; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; RV32-NEXT: vle16.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; RV32-NEXT: vfmv.v.f v25, ft0 +; RV32-NEXT: vfmv.v.f v16, ft0 ; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; RV32-NEXT: vfredusum.vs v25, v8, v25 -; RV32-NEXT: vfmv.f.s ft0, v25 +; RV32-NEXT: vfredusum.vs v8, v8, v16 +; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: fadd.h fa0, fa0, ft0 ; RV32-NEXT: ret ; @@ -261,10 +261,10 @@ define half @vreduce_fadd_v64f16(<64 x half>* %x, half %s) { ; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; RV64-NEXT: vle16.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; RV64-NEXT: vfmv.v.f v25, ft0 +; RV64-NEXT: vfmv.v.f v16, ft0 ; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; RV64-NEXT: vfredusum.vs v25, v8, v25 -; RV64-NEXT: vfmv.f.s ft0, v25 +; RV64-NEXT: vfredusum.vs v8, v8, v16 +; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: fadd.h fa0, fa0, ft0 ; RV64-NEXT: ret %v = load <64 x half>, <64 x half>* %x @@ -279,10 +279,10 @@ define half @vreduce_ord_fadd_v64f16(<64 x half>* %x, half %s) { ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v16, fa0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <64 x half>, <64 x half>* %x %red = call half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v) @@ -303,10 +303,10 @@ define half @vreduce_fadd_v128f16(<128 x half>* %x, half %s) { ; CHECK-NEXT: flh ft0, %lo(.LCPI14_0)(a0) ; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <128 x half>, <128 x half>* %x @@ -323,15 +323,15 @@ define half @vreduce_ord_fadd_v128f16(<128 x half>* %x, half %s) { ; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v24, fa0 ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v16, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredosum.vs v16, v16, v24 +; CHECK-NEXT: vfmv.f.s ft0, v16 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <128 x half>, <128 x half>* %x %red = call half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v) @@ -344,8 +344,8 @@ define float @vreduce_fadd_v1f32(<1 x float>* %x, float %s) { ; CHECK-LABEL: vreduce_fadd_v1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <1 x float>, <1 x float>* %x @@ -357,12 +357,12 @@ define float @vreduce_ord_fadd_v1f32(<1 x float>* %x, float %s) { ; CHECK-LABEL: vreduce_ord_fadd_v1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <1 x float>, <1 x float>* %x %red = call float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v) @@ -377,12 +377,12 @@ define float @vreduce_fadd_v2f32(<2 x float>* %x, float %s) { ; CHECK-NEXT: lui a1, %hi(.LCPI18_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI18_0)(a1) ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <2 x float>, <2 x float>* %x @@ -394,12 +394,12 @@ define float @vreduce_ord_fadd_v2f32(<2 x float>* %x, float %s) { ; CHECK-LABEL: vreduce_ord_fadd_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <2 x float>, <2 x float>* %x %red = call float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v) @@ -414,12 +414,12 @@ define float @vreduce_fadd_v4f32(<4 x float>* %x, float %s) { ; CHECK-NEXT: lui a1, %hi(.LCPI20_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI20_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x @@ -431,12 +431,12 @@ define float @vreduce_ord_fadd_v4f32(<4 x float>* %x, float %s) { ; CHECK-LABEL: vreduce_ord_fadd_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x %red = call float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v) @@ -451,12 +451,12 @@ define float @vreduce_fadd_v8f32(<8 x float>* %x, float %s) { ; CHECK-NEXT: lui a1, %hi(.LCPI22_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI22_0)(a1) ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v26, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <8 x float>, <8 x float>* %x @@ -468,12 +468,12 @@ define float @vreduce_ord_fadd_v8f32(<8 x float>* %x, float %s) { ; CHECK-LABEL: vreduce_ord_fadd_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v26, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <8 x float>, <8 x float>* %x %red = call float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v) @@ -488,12 +488,12 @@ define float @vreduce_fadd_v16f32(<16 x float>* %x, float %s) { ; CHECK-NEXT: lui a1, %hi(.LCPI24_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI24_0)(a1) ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v12, ft0 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v28, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v12 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <16 x float>, <16 x float>* %x @@ -505,12 +505,12 @@ define float @vreduce_ord_fadd_v16f32(<16 x float>* %x, float %s) { ; CHECK-LABEL: vreduce_ord_fadd_v16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v28, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v12 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <16 x float>, <16 x float>* %x %red = call float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v) @@ -528,10 +528,10 @@ define float @vreduce_fadd_v32f32(<32 x float>* %x, float %s) { ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV32-NEXT: vfmv.v.f v25, ft0 +; RV32-NEXT: vfmv.v.f v16, ft0 ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; RV32-NEXT: vfredusum.vs v25, v8, v25 -; RV32-NEXT: vfmv.f.s ft0, v25 +; RV32-NEXT: vfredusum.vs v8, v8, v16 +; RV32-NEXT: vfmv.f.s ft0, v8 ; RV32-NEXT: fadd.s fa0, fa0, ft0 ; RV32-NEXT: ret ; @@ -543,10 +543,10 @@ define float @vreduce_fadd_v32f32(<32 x float>* %x, float %s) { ; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV64-NEXT: vfmv.v.f v25, ft0 +; RV64-NEXT: vfmv.v.f v16, ft0 ; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; RV64-NEXT: vfredusum.vs v25, v8, v25 -; RV64-NEXT: vfmv.f.s ft0, v25 +; RV64-NEXT: vfredusum.vs v8, v8, v16 +; RV64-NEXT: vfmv.f.s ft0, v8 ; RV64-NEXT: fadd.s fa0, fa0, ft0 ; RV64-NEXT: ret %v = load <32 x float>, <32 x float>* %x @@ -561,10 +561,10 @@ define float @vreduce_ord_fadd_v32f32(<32 x float>* %x, float %s) { ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v16, fa0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <32 x float>, <32 x float>* %x %red = call float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v) @@ -585,10 +585,10 @@ define float @vreduce_fadd_v64f32(<64 x float>* %x, float %s) { ; CHECK-NEXT: flw ft0, %lo(.LCPI28_0)(a0) ; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <64 x float>, <64 x float>* %x @@ -605,15 +605,15 @@ define float @vreduce_ord_fadd_v64f32(<64 x float>* %x, float %s) { ; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v24, fa0 ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v16, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredosum.vs v16, v16, v24 +; CHECK-NEXT: vfmv.f.s ft0, v16 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <64 x float>, <64 x float>* %x %red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v) @@ -626,8 +626,8 @@ define double @vreduce_fadd_v1f64(<1 x double>* %x, double %s) { ; CHECK-LABEL: vreduce_fadd_v1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <1 x double>, <1 x double>* %x @@ -639,12 +639,12 @@ define double @vreduce_ord_fadd_v1f64(<1 x double>* %x, double %s) { ; CHECK-LABEL: vreduce_ord_fadd_v1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <1 x double>, <1 x double>* %x %red = call double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %v) @@ -659,12 +659,12 @@ define double @vreduce_fadd_v2f64(<2 x double>* %x, double %s) { ; CHECK-NEXT: lui a1, %hi(.LCPI32_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI32_0)(a1) ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <2 x double>, <2 x double>* %x @@ -676,12 +676,12 @@ define double @vreduce_ord_fadd_v2f64(<2 x double>* %x, double %s) { ; CHECK-LABEL: vreduce_ord_fadd_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <2 x double>, <2 x double>* %x %red = call double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v) @@ -696,12 +696,12 @@ define double @vreduce_fadd_v4f64(<4 x double>* %x, double %s) { ; CHECK-NEXT: lui a1, %hi(.LCPI34_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI34_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v26, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x @@ -713,12 +713,12 @@ define double @vreduce_ord_fadd_v4f64(<4 x double>* %x, double %s) { ; CHECK-LABEL: vreduce_ord_fadd_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v26, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x %red = call double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v) @@ -733,12 +733,12 @@ define double @vreduce_fadd_v8f64(<8 x double>* %x, double %s) { ; CHECK-NEXT: lui a1, %hi(.LCPI36_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI36_0)(a1) ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vle64.v v28, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v12, ft0 ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v28, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v12 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <8 x double>, <8 x double>* %x @@ -750,12 +750,12 @@ define double @vreduce_ord_fadd_v8f64(<8 x double>* %x, double %s) { ; CHECK-LABEL: vreduce_ord_fadd_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vle64.v v28, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v28, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v12 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <8 x double>, <8 x double>* %x %red = call double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v) @@ -772,10 +772,10 @@ define double @vreduce_fadd_v16f64(<16 x double>* %x, double %s) { ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <16 x double>, <16 x double>* %x @@ -789,10 +789,10 @@ define double @vreduce_ord_fadd_v16f64(<16 x double>* %x, double %s) { ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v16, fa0 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <16 x double>, <16 x double>* %x %red = call double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v) @@ -812,10 +812,10 @@ define double @vreduce_fadd_v32f64(<32 x double>* %x, double %s) { ; CHECK-NEXT: fld ft0, %lo(.LCPI40_0)(a0) ; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret %v = load <32 x double>, <32 x double>* %x @@ -831,15 +831,15 @@ define double @vreduce_ord_fadd_v32f64(<32 x double>* %x, double %s) { ; CHECK-NEXT: vle64.v v8, (a1) ; CHECK-NEXT: vle64.v v16, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v24, fa0 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v16, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredosum.vs v16, v16, v24 +; CHECK-NEXT: vfmv.f.s ft0, v16 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <32 x double>, <32 x double>* %x %red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v) @@ -854,12 +854,12 @@ define half @vreduce_fmin_v2f16(<2 x half>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI42_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI42_0)(a1) ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <2 x half>, <2 x half>* %x %red = call half @llvm.vector.reduce.fmin.v2f16(<2 x half> %v) @@ -874,12 +874,12 @@ define half @vreduce_fmin_v4f16(<4 x half>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI43_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI43_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x %red = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v) @@ -892,12 +892,12 @@ define half @vreduce_fmin_v4f16_nonans(<4 x half>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI44_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI44_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x %red = call nnan half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v) @@ -910,12 +910,12 @@ define half @vreduce_fmin_v4f16_nonans_noinfs(<4 x half>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI45_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI45_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x %red = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v) @@ -936,10 +936,10 @@ define half @vreduce_fmin_v128f16(<128 x half>* %x) { ; CHECK-NEXT: flh ft0, %lo(.LCPI46_0)(a0) ; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <128 x half>, <128 x half>* %x %red = call half @llvm.vector.reduce.fmin.v128f16(<128 x half> %v) @@ -954,12 +954,12 @@ define float @vreduce_fmin_v2f32(<2 x float>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI47_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI47_0)(a1) ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <2 x float>, <2 x float>* %x %red = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %v) @@ -974,12 +974,12 @@ define float @vreduce_fmin_v4f32(<4 x float>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI48_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI48_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x %red = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v) @@ -992,12 +992,12 @@ define float @vreduce_fmin_v4f32_nonans(<4 x float>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI49_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI49_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x %red = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v) @@ -1010,12 +1010,12 @@ define float @vreduce_fmin_v4f32_nonans_noinfs(<4 x float>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI50_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI50_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x %red = call nnan ninf float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v) @@ -1042,10 +1042,10 @@ define float @vreduce_fmin_v128f32(<128 x float>* %x) { ; CHECK-NEXT: vfmin.vv v16, v24, v0 ; CHECK-NEXT: vfmin.vv v8, v16, v8 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <128 x float>, <128 x float>* %x %red = call float @llvm.vector.reduce.fmin.v128f32(<128 x float> %v) @@ -1060,12 +1060,12 @@ define double @vreduce_fmin_v2f64(<2 x double>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI52_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI52_0)(a1) ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <2 x double>, <2 x double>* %x %red = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %v) @@ -1080,12 +1080,12 @@ define double @vreduce_fmin_v4f64(<4 x double>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI53_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI53_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v26, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x %red = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v) @@ -1098,12 +1098,12 @@ define double @vreduce_fmin_v4f64_nonans(<4 x double>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI54_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI54_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v26, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x %red = call nnan double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v) @@ -1116,12 +1116,12 @@ define double @vreduce_fmin_v4f64_nonans_noinfs(<4 x double>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI55_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI55_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v26, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x %red = call nnan ninf double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v) @@ -1141,10 +1141,10 @@ define double @vreduce_fmin_v32f64(<32 x double>* %x) { ; CHECK-NEXT: fld ft0, %lo(.LCPI56_0)(a0) ; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <32 x double>, <32 x double>* %x %red = call double @llvm.vector.reduce.fmin.v32f64(<32 x double> %v) @@ -1159,12 +1159,12 @@ define half @vreduce_fmax_v2f16(<2 x half>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI57_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI57_0)(a1) ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <2 x half>, <2 x half>* %x %red = call half @llvm.vector.reduce.fmax.v2f16(<2 x half> %v) @@ -1179,12 +1179,12 @@ define half @vreduce_fmax_v4f16(<4 x half>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI58_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI58_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x %red = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v) @@ -1197,12 +1197,12 @@ define half @vreduce_fmax_v4f16_nonans(<4 x half>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI59_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI59_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x %red = call nnan half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v) @@ -1215,12 +1215,12 @@ define half @vreduce_fmax_v4f16_nonans_noinfs(<4 x half>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI60_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI60_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x half>, <4 x half>* %x %red = call nnan ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v) @@ -1241,10 +1241,10 @@ define half @vreduce_fmax_v128f16(<128 x half>* %x) { ; CHECK-NEXT: flh ft0, %lo(.LCPI61_0)(a0) ; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <128 x half>, <128 x half>* %x %red = call half @llvm.vector.reduce.fmax.v128f16(<128 x half> %v) @@ -1259,12 +1259,12 @@ define float @vreduce_fmax_v2f32(<2 x float>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI62_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI62_0)(a1) ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <2 x float>, <2 x float>* %x %red = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %v) @@ -1279,12 +1279,12 @@ define float @vreduce_fmax_v4f32(<4 x float>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI63_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI63_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x %red = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v) @@ -1297,12 +1297,12 @@ define float @vreduce_fmax_v4f32_nonans(<4 x float>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI64_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI64_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x %red = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v) @@ -1315,12 +1315,12 @@ define float @vreduce_fmax_v4f32_nonans_noinfs(<4 x float>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI65_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI65_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x float>, <4 x float>* %x %red = call nnan ninf float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v) @@ -1347,10 +1347,10 @@ define float @vreduce_fmax_v128f32(<128 x float>* %x) { ; CHECK-NEXT: vfmax.vv v16, v24, v0 ; CHECK-NEXT: vfmax.vv v8, v16, v8 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <128 x float>, <128 x float>* %x %red = call float @llvm.vector.reduce.fmax.v128f32(<128 x float> %v) @@ -1365,12 +1365,12 @@ define double @vreduce_fmax_v2f64(<2 x double>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI67_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI67_0)(a1) ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vle64.v v25, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v26, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v25, v26 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <2 x double>, <2 x double>* %x %red = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %v) @@ -1385,12 +1385,12 @@ define double @vreduce_fmax_v4f64(<4 x double>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI68_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI68_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v26, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x %red = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v) @@ -1403,12 +1403,12 @@ define double @vreduce_fmax_v4f64_nonans(<4 x double>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI69_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI69_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v26, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x %red = call nnan double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v) @@ -1421,12 +1421,12 @@ define double @vreduce_fmax_v4f64_nonans_noinfs(<4 x double>* %x) { ; CHECK-NEXT: lui a1, %hi(.LCPI70_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI70_0)(a1) ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vle64.v v26, (a0) +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v26, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <4 x double>, <4 x double>* %x %red = call nnan ninf double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v) @@ -1446,10 +1446,10 @@ define double @vreduce_fmax_v32f64(<32 x double>* %x) { ; CHECK-NEXT: fld ft0, %lo(.LCPI71_0)(a0) ; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <32 x double>, <32 x double>* %x %red = call double @llvm.vector.reduce.fmax.v32f64(<32 x double> %v) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll index 48e51f5fb2fadee8913d8fb6c8e8b5ba506d6e76..163e561f9ad85132cf19e08aeb4022f69e0752b6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll @@ -10,10 +10,10 @@ define signext i8 @vpreduce_add_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i3 ; CHECK-LABEL: vpreduce_add_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.add.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -26,10 +26,10 @@ define signext i8 @vpreduce_umax_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 255 ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.umax.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -41,10 +41,10 @@ define signext i8 @vpreduce_smax_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i ; CHECK-LABEL: vpreduce_smax_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.smax.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -57,10 +57,10 @@ define signext i8 @vpreduce_umin_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 255 ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.umin.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -72,10 +72,10 @@ define signext i8 @vpreduce_smin_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i ; CHECK-LABEL: vpreduce_smin_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.smin.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -87,10 +87,10 @@ define signext i8 @vpreduce_and_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i3 ; CHECK-LABEL: vpreduce_and_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu -; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.and.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -102,10 +102,10 @@ define signext i8 @vpreduce_or_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i32 ; CHECK-LABEL: vpreduce_or_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu -; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.or.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -117,10 +117,10 @@ define signext i8 @vpreduce_xor_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i3 ; CHECK-LABEL: vpreduce_xor_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.xor.v2i8(i8 %s, <2 x i8> %v, <2 x i1> %m, i32 %evl) ret i8 %r @@ -132,10 +132,10 @@ define signext i8 @vpreduce_add_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i3 ; CHECK-LABEL: vpreduce_add_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.add.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -148,10 +148,10 @@ define signext i8 @vpreduce_umax_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 255 ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.umax.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -163,10 +163,10 @@ define signext i8 @vpreduce_smax_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i ; CHECK-LABEL: vpreduce_smax_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.smax.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -179,10 +179,10 @@ define signext i8 @vpreduce_umin_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 255 ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.umin.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -194,10 +194,10 @@ define signext i8 @vpreduce_smin_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i ; CHECK-LABEL: vpreduce_smin_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.smin.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -209,10 +209,10 @@ define signext i8 @vpreduce_and_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i3 ; CHECK-LABEL: vpreduce_and_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu -; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.and.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -224,10 +224,10 @@ define signext i8 @vpreduce_or_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i32 ; CHECK-LABEL: vpreduce_or_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu -; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.or.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -239,10 +239,10 @@ define signext i8 @vpreduce_xor_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i3 ; CHECK-LABEL: vpreduce_xor_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i8 @llvm.vp.reduce.xor.v4i8(i8 %s, <4 x i8> %v, <4 x i1> %m, i32 %evl) ret i8 %r @@ -254,10 +254,10 @@ define signext i16 @vpreduce_add_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m ; CHECK-LABEL: vpreduce_add_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.add.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -272,10 +272,10 @@ define signext i16 @vpreduce_umax_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> % ; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_v2i16: @@ -284,10 +284,10 @@ define signext i16 @vpreduce_umax_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> % ; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: and a0, a0, a2 ; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i16 @llvm.vp.reduce.umax.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -299,10 +299,10 @@ define signext i16 @vpreduce_smax_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> % ; CHECK-LABEL: vpreduce_smax_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.smax.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -317,10 +317,10 @@ define signext i16 @vpreduce_umin_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> % ; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_v2i16: @@ -329,10 +329,10 @@ define signext i16 @vpreduce_umin_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> % ; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: and a0, a0, a2 ; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i16 @llvm.vp.reduce.umin.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -344,10 +344,10 @@ define signext i16 @vpreduce_smin_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> % ; CHECK-LABEL: vpreduce_smin_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.smin.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -359,10 +359,10 @@ define signext i16 @vpreduce_and_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m ; CHECK-LABEL: vpreduce_and_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.and.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -374,10 +374,10 @@ define signext i16 @vpreduce_or_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m, ; CHECK-LABEL: vpreduce_or_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.or.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -389,10 +389,10 @@ define signext i16 @vpreduce_xor_v2i16(i16 signext %s, <2 x i16> %v, <2 x i1> %m ; CHECK-LABEL: vpreduce_xor_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.xor.v2i16(i16 %s, <2 x i16> %v, <2 x i1> %m, i32 %evl) ret i16 %r @@ -404,10 +404,10 @@ define signext i16 @vpreduce_add_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m ; CHECK-LABEL: vpreduce_add_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.add.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -422,10 +422,10 @@ define signext i16 @vpreduce_umax_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> % ; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_v4i16: @@ -434,10 +434,10 @@ define signext i16 @vpreduce_umax_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> % ; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: and a0, a0, a2 ; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i16 @llvm.vp.reduce.umax.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -449,10 +449,10 @@ define signext i16 @vpreduce_smax_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> % ; CHECK-LABEL: vpreduce_smax_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.smax.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -467,10 +467,10 @@ define signext i16 @vpreduce_umin_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> % ; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_v4i16: @@ -479,10 +479,10 @@ define signext i16 @vpreduce_umin_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> % ; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: and a0, a0, a2 ; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i16 @llvm.vp.reduce.umin.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -494,10 +494,10 @@ define signext i16 @vpreduce_smin_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> % ; CHECK-LABEL: vpreduce_smin_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.smin.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -509,10 +509,10 @@ define signext i16 @vpreduce_and_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m ; CHECK-LABEL: vpreduce_and_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.and.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -524,10 +524,10 @@ define signext i16 @vpreduce_or_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m, ; CHECK-LABEL: vpreduce_or_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.or.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -539,10 +539,10 @@ define signext i16 @vpreduce_xor_v4i16(i16 signext %s, <4 x i16> %v, <4 x i1> %m ; CHECK-LABEL: vpreduce_xor_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.xor.v4i16(i16 %s, <4 x i16> %v, <4 x i1> %m, i32 %evl) ret i16 %r @@ -554,10 +554,10 @@ define signext i32 @vpreduce_add_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m ; CHECK-LABEL: vpreduce_add_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.add.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -569,10 +569,10 @@ define signext i32 @vpreduce_umax_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> % ; RV32-LABEL: vpreduce_umax_v2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_v2i32: @@ -580,10 +580,10 @@ define signext i32 @vpreduce_umax_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> % ; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: srli a0, a0, 32 ; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i32 @llvm.vp.reduce.umax.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -595,10 +595,10 @@ define signext i32 @vpreduce_smax_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> % ; CHECK-LABEL: vpreduce_smax_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.smax.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -610,10 +610,10 @@ define signext i32 @vpreduce_umin_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> % ; RV32-LABEL: vpreduce_umin_v2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_v2i32: @@ -621,10 +621,10 @@ define signext i32 @vpreduce_umin_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> % ; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: srli a0, a0, 32 ; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i32 @llvm.vp.reduce.umin.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -636,10 +636,10 @@ define signext i32 @vpreduce_smin_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> % ; CHECK-LABEL: vpreduce_smin_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.smin.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -651,10 +651,10 @@ define signext i32 @vpreduce_and_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m ; CHECK-LABEL: vpreduce_and_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.and.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -666,10 +666,10 @@ define signext i32 @vpreduce_or_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m, ; CHECK-LABEL: vpreduce_or_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.or.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -681,10 +681,10 @@ define signext i32 @vpreduce_xor_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m ; CHECK-LABEL: vpreduce_xor_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.xor.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl) ret i32 %r @@ -696,10 +696,10 @@ define signext i32 @vpreduce_add_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m ; CHECK-LABEL: vpreduce_add_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.add.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -711,10 +711,10 @@ define signext i32 @vpreduce_umax_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> % ; RV32-LABEL: vpreduce_umax_v4i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_v4i32: @@ -722,10 +722,10 @@ define signext i32 @vpreduce_umax_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> % ; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: srli a0, a0, 32 ; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i32 @llvm.vp.reduce.umax.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -737,10 +737,10 @@ define signext i32 @vpreduce_smax_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> % ; CHECK-LABEL: vpreduce_smax_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.smax.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -752,10 +752,10 @@ define signext i32 @vpreduce_umin_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> % ; RV32-LABEL: vpreduce_umin_v4i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_v4i32: @@ -763,10 +763,10 @@ define signext i32 @vpreduce_umin_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> % ; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: srli a0, a0, 32 ; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i32 @llvm.vp.reduce.umin.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -778,10 +778,10 @@ define signext i32 @vpreduce_smin_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> % ; CHECK-LABEL: vpreduce_smin_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.smin.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -793,10 +793,10 @@ define signext i32 @vpreduce_and_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m ; CHECK-LABEL: vpreduce_and_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.and.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -808,10 +808,10 @@ define signext i32 @vpreduce_or_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m, ; CHECK-LABEL: vpreduce_or_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.or.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -823,10 +823,10 @@ define signext i32 @vpreduce_xor_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m ; CHECK-LABEL: vpreduce_xor_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.xor.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) ret i32 %r @@ -843,24 +843,24 @@ define signext i64 @vpreduce_add_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredsum.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredsum.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_add_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredsum.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredsum.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.add.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -877,24 +877,24 @@ define signext i64 @vpreduce_umax_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.umax.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -911,24 +911,24 @@ define signext i64 @vpreduce_smax_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredmax.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmax.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_smax_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredmax.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmax.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.smax.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -945,24 +945,24 @@ define signext i64 @vpreduce_umin_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.umin.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -979,24 +979,24 @@ define signext i64 @vpreduce_smin_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredmin.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_smin_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredmin.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.smin.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -1013,24 +1013,24 @@ define signext i64 @vpreduce_and_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredand.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredand.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_and_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredand.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredand.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.and.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -1047,24 +1047,24 @@ define signext i64 @vpreduce_or_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredor.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredor.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_or_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredor.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredor.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.or.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -1081,24 +1081,24 @@ define signext i64 @vpreduce_xor_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredxor.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredxor.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_xor_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredxor.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredxor.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.xor.v2i64(i64 %s, <2 x i64> %v, <2 x i1> %m, i32 %evl) ret i64 %r @@ -1115,24 +1115,24 @@ define signext i64 @vpreduce_add_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredsum.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredsum.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_add_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredsum.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredsum.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.add.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r @@ -1149,24 +1149,24 @@ define signext i64 @vpreduce_umax_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.umax.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r @@ -1183,24 +1183,24 @@ define signext i64 @vpreduce_smax_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredmax.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmax.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_smax_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredmax.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmax.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.smax.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r @@ -1217,24 +1217,24 @@ define signext i64 @vpreduce_umin_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.umin.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r @@ -1251,24 +1251,24 @@ define signext i64 @vpreduce_smin_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredmin.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_smin_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredmin.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.smin.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r @@ -1285,24 +1285,24 @@ define signext i64 @vpreduce_and_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredand.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredand.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_and_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredand.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredand.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.and.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r @@ -1319,24 +1319,24 @@ define signext i64 @vpreduce_or_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredor.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredor.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_or_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredor.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredor.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.or.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r @@ -1353,24 +1353,24 @@ define signext i64 @vpreduce_xor_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredxor.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredxor.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_xor_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredxor.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredxor.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.xor.v4i64(i64 %s, <4 x i64> %v, <4 x i1> %m, i32 %evl) ret i64 %r diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll index 49997585b93ed6c16d3329a7a32f58528ccb3398..8602731a57310ff577eb6c04ae680c2d93b7fd5c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll @@ -8,8 +8,8 @@ define i8 @vreduce_add_v1i8(<1 x i8>* %x) { ; CHECK-LABEL: vreduce_add_v1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v1i8(<1 x i8> %v) @@ -22,12 +22,12 @@ define i8 @vreduce_add_v2i8(<2 x i8>* %x) { ; CHECK-LABEL: vreduce_add_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vredsum.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> %v) @@ -40,12 +40,12 @@ define i8 @vreduce_add_v4i8(<4 x i8>* %x) { ; CHECK-LABEL: vreduce_add_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vredsum.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> %v) @@ -58,12 +58,12 @@ define i8 @vreduce_add_v8i8(<8 x i8>* %x) { ; CHECK-LABEL: vreduce_add_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %v) @@ -76,12 +76,12 @@ define i8 @vreduce_add_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: vreduce_add_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vredsum.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %v) @@ -95,12 +95,12 @@ define i8 @vreduce_add_v32i8(<32 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %v) @@ -114,12 +114,12 @@ define i8 @vreduce_add_v64i8(<64 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 64 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vredsum.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> %v) @@ -135,10 +135,10 @@ define i8 @vreduce_add_v128i8(<128 x i8>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %v) @@ -157,10 +157,10 @@ define i8 @vreduce_add_v256i8(<256 x i8>* %x) { ; CHECK-NEXT: vle8.v v16, (a0) ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.add.v256i8(<256 x i8> %v) @@ -173,8 +173,8 @@ define i16 @vreduce_add_v1i16(<1 x i16>* %x) { ; CHECK-LABEL: vreduce_add_v1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %v) @@ -187,12 +187,12 @@ define i16 @vreduce_add_v2i16(<2 x i16>* %x) { ; CHECK-LABEL: vreduce_add_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vredsum.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> %v) @@ -205,12 +205,12 @@ define i16 @vreduce_add_v4i16(<4 x i16>* %x) { ; CHECK-LABEL: vreduce_add_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %v) @@ -223,12 +223,12 @@ define i16 @vreduce_add_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: vreduce_add_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vredsum.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %v) @@ -241,12 +241,12 @@ define i16 @vreduce_add_v16i16(<16 x i16>* %x) { ; CHECK-LABEL: vreduce_add_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %v) @@ -260,12 +260,12 @@ define i16 @vreduce_add_v32i16(<32 x i16>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vredsum.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> %v) @@ -281,10 +281,10 @@ define i16 @vreduce_add_v64i16(<64 x i16>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> %v) @@ -303,10 +303,10 @@ define i16 @vreduce_add_v128i16(<128 x i16>* %x) { ; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.add.v128i16(<128 x i16> %v) @@ -319,8 +319,8 @@ define i32 @vreduce_add_v1i32(<1 x i32>* %x) { ; CHECK-LABEL: vreduce_add_v1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %v) @@ -333,12 +333,12 @@ define i32 @vreduce_add_v2i32(<2 x i32>* %x) { ; CHECK-LABEL: vreduce_add_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %v) @@ -351,12 +351,12 @@ define i32 @vreduce_add_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: vreduce_add_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vredsum.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v) @@ -369,12 +369,12 @@ define i32 @vreduce_add_v8i32(<8 x i32>* %x) { ; CHECK-LABEL: vreduce_add_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %v) @@ -387,12 +387,12 @@ define i32 @vreduce_add_v16i32(<16 x i32>* %x) { ; CHECK-LABEL: vreduce_add_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vredsum.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %v) @@ -408,10 +408,10 @@ define i32 @vreduce_add_v32i32(<32 x i32>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %v) @@ -430,10 +430,10 @@ define i32 @vreduce_add_v64i32(<64 x i32>* %x) { ; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %v) @@ -446,18 +446,18 @@ define i64 @vreduce_add_v1i64(<1 x i64>* %x) { ; RV32-LABEL: vreduce_add_v1i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a0, zero, 32 -; RV32-NEXT: vsrl.vx v26, v25, a0 -; RV32-NEXT: vmv.x.s a1, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_add_v1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %v) @@ -470,27 +470,27 @@ define i64 @vreduce_add_v2i64(<2 x i64>* %x) { ; RV32-LABEL: vreduce_add_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v26, 0 +; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vredsum.vs v25, v25, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredsum.vs v8, v8, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_add_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v26, 0 +; RV64-NEXT: vmv.v.i v9, 0 ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vredsum.vs v25, v25, v26 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredsum.vs v8, v8, v9 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %v) @@ -503,27 +503,27 @@ define i64 @vreduce_add_v4i64(<4 x i64>* %x) { ; RV32-LABEL: vreduce_add_v4i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vle64.v v26, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vredsum.vs v25, v26, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredsum.vs v8, v8, v10 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_add_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v26, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v10, 0 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vredsum.vs v25, v26, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredsum.vs v8, v8, v10 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v) @@ -536,27 +536,27 @@ define i64 @vreduce_add_v8i64(<8 x i64>* %x) { ; RV32-LABEL: vreduce_add_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vle64.v v28, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v12, 0 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vredsum.vs v25, v28, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredsum.vs v8, v8, v12 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_add_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v28, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v12, 0 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vredsum.vs v25, v28, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredsum.vs v8, v8, v12 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %v) @@ -571,14 +571,14 @@ define i64 @vreduce_add_v16i64(<16 x i64>* %x) { ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredsum.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredsum.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_add_v16i64: @@ -586,10 +586,10 @@ define i64 @vreduce_add_v16i64(<16 x i64>* %x) { ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredsum.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredsum.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %v) @@ -607,14 +607,14 @@ define i64 @vreduce_add_v32i64(<32 x i64>* %x) { ; RV32-NEXT: vle64.v v16, (a0) ; RV32-NEXT: vadd.vv v8, v8, v16 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredsum.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredsum.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_add_v32i64: @@ -625,10 +625,10 @@ define i64 @vreduce_add_v32i64(<32 x i64>* %x) { ; RV64-NEXT: vle64.v v16, (a0) ; RV64-NEXT: vadd.vv v8, v8, v16 ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredsum.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredsum.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.add.v32i64(<32 x i64> %v) @@ -652,14 +652,14 @@ define i64 @vreduce_add_v64i64(<64 x i64>* %x) nounwind { ; RV32-NEXT: vadd.vv v8, v8, v0 ; RV32-NEXT: vadd.vv v8, v8, v16 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredsum.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredsum.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_add_v64i64: @@ -676,10 +676,10 @@ define i64 @vreduce_add_v64i64(<64 x i64>* %x) nounwind { ; RV64-NEXT: vadd.vv v8, v8, v0 ; RV64-NEXT: vadd.vv v8, v8, v16 ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredsum.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredsum.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <64 x i64>, <64 x i64>* %x %red = call i64 @llvm.vector.reduce.add.v64i64(<64 x i64> %v) @@ -692,8 +692,8 @@ define i8 @vreduce_and_v1i8(<1 x i8>* %x) { ; CHECK-LABEL: vreduce_and_v1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %v) @@ -706,12 +706,12 @@ define i8 @vreduce_and_v2i8(<2 x i8>* %x) { ; CHECK-LABEL: vreduce_and_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vredand.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v2i8(<2 x i8> %v) @@ -724,12 +724,12 @@ define i8 @vreduce_and_v4i8(<4 x i8>* %x) { ; CHECK-LABEL: vreduce_and_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vredand.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %v) @@ -742,12 +742,12 @@ define i8 @vreduce_and_v8i8(<8 x i8>* %x) { ; CHECK-LABEL: vreduce_and_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vredand.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %v) @@ -760,12 +760,12 @@ define i8 @vreduce_and_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: vreduce_and_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vredand.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %v) @@ -779,12 +779,12 @@ define i8 @vreduce_and_v32i8(<32 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vredand.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %v) @@ -798,12 +798,12 @@ define i8 @vreduce_and_v64i8(<64 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 64 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v12, -1 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vredand.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v64i8(<64 x i8> %v) @@ -819,10 +819,10 @@ define i8 @vreduce_and_v128i8(<128 x i8>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v16, -1 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v128i8(<128 x i8> %v) @@ -841,10 +841,10 @@ define i8 @vreduce_and_v256i8(<256 x i8>* %x) { ; CHECK-NEXT: vle8.v v16, (a0) ; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v16, -1 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.and.v256i8(<256 x i8> %v) @@ -857,8 +857,8 @@ define i16 @vreduce_and_v1i16(<1 x i16>* %x) { ; CHECK-LABEL: vreduce_and_v1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v1i16(<1 x i16> %v) @@ -871,12 +871,12 @@ define i16 @vreduce_and_v2i16(<2 x i16>* %x) { ; CHECK-LABEL: vreduce_and_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vredand.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> %v) @@ -889,12 +889,12 @@ define i16 @vreduce_and_v4i16(<4 x i16>* %x) { ; CHECK-LABEL: vreduce_and_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vredand.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %v) @@ -907,12 +907,12 @@ define i16 @vreduce_and_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: vreduce_and_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vredand.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %v) @@ -925,12 +925,12 @@ define i16 @vreduce_and_v16i16(<16 x i16>* %x) { ; CHECK-LABEL: vreduce_and_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vredand.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %v) @@ -944,12 +944,12 @@ define i16 @vreduce_and_v32i16(<32 x i16>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v12, -1 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vredand.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v32i16(<32 x i16> %v) @@ -965,10 +965,10 @@ define i16 @vreduce_and_v64i16(<64 x i16>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v16, -1 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v64i16(<64 x i16> %v) @@ -987,10 +987,10 @@ define i16 @vreduce_and_v128i16(<128 x i16>* %x) { ; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v16, -1 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.and.v128i16(<128 x i16> %v) @@ -1003,8 +1003,8 @@ define i32 @vreduce_and_v1i32(<1 x i32>* %x) { ; CHECK-LABEL: vreduce_and_v1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %v) @@ -1017,12 +1017,12 @@ define i32 @vreduce_and_v2i32(<2 x i32>* %x) { ; CHECK-LABEL: vreduce_and_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vredand.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %v) @@ -1035,12 +1035,12 @@ define i32 @vreduce_and_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: vreduce_and_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vredand.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %v) @@ -1053,12 +1053,12 @@ define i32 @vreduce_and_v8i32(<8 x i32>* %x) { ; CHECK-LABEL: vreduce_and_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vredand.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %v) @@ -1071,12 +1071,12 @@ define i32 @vreduce_and_v16i32(<16 x i32>* %x) { ; CHECK-LABEL: vreduce_and_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v12, -1 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vredand.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %v) @@ -1092,10 +1092,10 @@ define i32 @vreduce_and_v32i32(<32 x i32>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v16, -1 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.and.v32i32(<32 x i32> %v) @@ -1114,10 +1114,10 @@ define i32 @vreduce_and_v64i32(<64 x i32>* %x) { ; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v16, -1 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.and.v64i32(<64 x i32> %v) @@ -1130,18 +1130,18 @@ define i64 @vreduce_and_v1i64(<1 x i64>* %x) { ; RV32-LABEL: vreduce_and_v1i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a0, zero, 32 -; RV32-NEXT: vsrl.vx v26, v25, a0 -; RV32-NEXT: vmv.x.s a1, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_and_v1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %v) @@ -1154,27 +1154,27 @@ define i64 @vreduce_and_v2i64(<2 x i64>* %x) { ; RV32-LABEL: vreduce_and_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v26, -1 +; RV32-NEXT: vmv.v.i v9, -1 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vredand.vs v25, v25, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredand.vs v8, v8, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_and_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v26, -1 +; RV64-NEXT: vmv.v.i v9, -1 ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vredand.vs v25, v25, v26 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredand.vs v8, v8, v9 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %v) @@ -1187,27 +1187,27 @@ define i64 @vreduce_and_v4i64(<4 x i64>* %x) { ; RV32-LABEL: vreduce_and_v4i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vle64.v v26, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, -1 +; RV32-NEXT: vmv.v.i v10, -1 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vredand.vs v25, v26, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredand.vs v8, v8, v10 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_and_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v26, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, -1 +; RV64-NEXT: vmv.v.i v10, -1 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vredand.vs v25, v26, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredand.vs v8, v8, v10 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v) @@ -1220,27 +1220,27 @@ define i64 @vreduce_and_v8i64(<8 x i64>* %x) { ; RV32-LABEL: vreduce_and_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vle64.v v28, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, -1 +; RV32-NEXT: vmv.v.i v12, -1 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vredand.vs v25, v28, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredand.vs v8, v8, v12 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_and_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v28, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, -1 +; RV64-NEXT: vmv.v.i v12, -1 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vredand.vs v25, v28, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredand.vs v8, v8, v12 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %v) @@ -1255,14 +1255,14 @@ define i64 @vreduce_and_v16i64(<16 x i64>* %x) { ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, -1 +; RV32-NEXT: vmv.v.i v16, -1 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredand.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredand.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_and_v16i64: @@ -1270,10 +1270,10 @@ define i64 @vreduce_and_v16i64(<16 x i64>* %x) { ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, -1 +; RV64-NEXT: vmv.v.i v16, -1 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredand.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredand.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.and.v16i64(<16 x i64> %v) @@ -1291,14 +1291,14 @@ define i64 @vreduce_and_v32i64(<32 x i64>* %x) { ; RV32-NEXT: vle64.v v16, (a0) ; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, -1 +; RV32-NEXT: vmv.v.i v16, -1 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredand.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredand.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_and_v32i64: @@ -1309,10 +1309,10 @@ define i64 @vreduce_and_v32i64(<32 x i64>* %x) { ; RV64-NEXT: vle64.v v16, (a0) ; RV64-NEXT: vand.vv v8, v8, v16 ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, -1 +; RV64-NEXT: vmv.v.i v16, -1 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredand.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredand.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.and.v32i64(<32 x i64> %v) @@ -1336,14 +1336,14 @@ define i64 @vreduce_and_v64i64(<64 x i64>* %x) nounwind { ; RV32-NEXT: vand.vv v8, v8, v0 ; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, -1 +; RV32-NEXT: vmv.v.i v16, -1 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredand.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredand.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_and_v64i64: @@ -1360,10 +1360,10 @@ define i64 @vreduce_and_v64i64(<64 x i64>* %x) nounwind { ; RV64-NEXT: vand.vv v8, v8, v0 ; RV64-NEXT: vand.vv v8, v8, v16 ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, -1 +; RV64-NEXT: vmv.v.i v16, -1 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredand.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredand.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <64 x i64>, <64 x i64>* %x %red = call i64 @llvm.vector.reduce.and.v64i64(<64 x i64> %v) @@ -1376,8 +1376,8 @@ define i8 @vreduce_or_v1i8(<1 x i8>* %x) { ; CHECK-LABEL: vreduce_or_v1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v1i8(<1 x i8> %v) @@ -1390,12 +1390,12 @@ define i8 @vreduce_or_v2i8(<2 x i8>* %x) { ; CHECK-LABEL: vreduce_or_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vredor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v2i8(<2 x i8> %v) @@ -1408,12 +1408,12 @@ define i8 @vreduce_or_v4i8(<4 x i8>* %x) { ; CHECK-LABEL: vreduce_or_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vredor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> %v) @@ -1426,12 +1426,12 @@ define i8 @vreduce_or_v8i8(<8 x i8>* %x) { ; CHECK-LABEL: vreduce_or_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vredor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %v) @@ -1444,12 +1444,12 @@ define i8 @vreduce_or_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: vreduce_or_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vredor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %v) @@ -1463,12 +1463,12 @@ define i8 @vreduce_or_v32i8(<32 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vredor.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %v) @@ -1482,12 +1482,12 @@ define i8 @vreduce_or_v64i8(<64 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 64 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vredor.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> %v) @@ -1503,10 +1503,10 @@ define i8 @vreduce_or_v128i8(<128 x i8>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> %v) @@ -1525,10 +1525,10 @@ define i8 @vreduce_or_v256i8(<256 x i8>* %x) { ; CHECK-NEXT: vle8.v v16, (a0) ; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.or.v256i8(<256 x i8> %v) @@ -1541,8 +1541,8 @@ define i16 @vreduce_or_v1i16(<1 x i16>* %x) { ; CHECK-LABEL: vreduce_or_v1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v1i16(<1 x i16> %v) @@ -1555,12 +1555,12 @@ define i16 @vreduce_or_v2i16(<2 x i16>* %x) { ; CHECK-LABEL: vreduce_or_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vredor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> %v) @@ -1573,12 +1573,12 @@ define i16 @vreduce_or_v4i16(<4 x i16>* %x) { ; CHECK-LABEL: vreduce_or_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vredor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %v) @@ -1591,12 +1591,12 @@ define i16 @vreduce_or_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: vreduce_or_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vredor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %v) @@ -1609,12 +1609,12 @@ define i16 @vreduce_or_v16i16(<16 x i16>* %x) { ; CHECK-LABEL: vreduce_or_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vredor.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %v) @@ -1628,12 +1628,12 @@ define i16 @vreduce_or_v32i16(<32 x i16>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vredor.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> %v) @@ -1649,10 +1649,10 @@ define i16 @vreduce_or_v64i16(<64 x i16>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> %v) @@ -1671,10 +1671,10 @@ define i16 @vreduce_or_v128i16(<128 x i16>* %x) { ; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.or.v128i16(<128 x i16> %v) @@ -1687,8 +1687,8 @@ define i32 @vreduce_or_v1i32(<1 x i32>* %x) { ; CHECK-LABEL: vreduce_or_v1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.or.v1i32(<1 x i32> %v) @@ -1701,12 +1701,12 @@ define i32 @vreduce_or_v2i32(<2 x i32>* %x) { ; CHECK-LABEL: vreduce_or_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vredor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %v) @@ -1719,12 +1719,12 @@ define i32 @vreduce_or_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: vreduce_or_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vredor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %v) @@ -1737,12 +1737,12 @@ define i32 @vreduce_or_v8i32(<8 x i32>* %x) { ; CHECK-LABEL: vreduce_or_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vredor.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %v) @@ -1755,12 +1755,12 @@ define i32 @vreduce_or_v16i32(<16 x i32>* %x) { ; CHECK-LABEL: vreduce_or_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vredor.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %v) @@ -1776,10 +1776,10 @@ define i32 @vreduce_or_v32i32(<32 x i32>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> %v) @@ -1798,10 +1798,10 @@ define i32 @vreduce_or_v64i32(<64 x i32>* %x) { ; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.or.v64i32(<64 x i32> %v) @@ -1814,18 +1814,18 @@ define i64 @vreduce_or_v1i64(<1 x i64>* %x) { ; RV32-LABEL: vreduce_or_v1i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a0, zero, 32 -; RV32-NEXT: vsrl.vx v26, v25, a0 -; RV32-NEXT: vmv.x.s a1, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_or_v1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> %v) @@ -1838,27 +1838,27 @@ define i64 @vreduce_or_v2i64(<2 x i64>* %x) { ; RV32-LABEL: vreduce_or_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v26, 0 +; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vredor.vs v25, v25, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredor.vs v8, v8, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_or_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v26, 0 +; RV64-NEXT: vmv.v.i v9, 0 ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vredor.vs v25, v25, v26 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredor.vs v8, v8, v9 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %v) @@ -1871,27 +1871,27 @@ define i64 @vreduce_or_v4i64(<4 x i64>* %x) { ; RV32-LABEL: vreduce_or_v4i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vle64.v v26, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vredor.vs v25, v26, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredor.vs v8, v8, v10 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_or_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v26, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v10, 0 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vredor.vs v25, v26, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredor.vs v8, v8, v10 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %v) @@ -1904,27 +1904,27 @@ define i64 @vreduce_or_v8i64(<8 x i64>* %x) { ; RV32-LABEL: vreduce_or_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vle64.v v28, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v12, 0 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vredor.vs v25, v28, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredor.vs v8, v8, v12 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_or_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v28, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v12, 0 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vredor.vs v25, v28, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredor.vs v8, v8, v12 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %v) @@ -1939,14 +1939,14 @@ define i64 @vreduce_or_v16i64(<16 x i64>* %x) { ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredor.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredor.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_or_v16i64: @@ -1954,10 +1954,10 @@ define i64 @vreduce_or_v16i64(<16 x i64>* %x) { ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredor.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredor.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> %v) @@ -1975,14 +1975,14 @@ define i64 @vreduce_or_v32i64(<32 x i64>* %x) { ; RV32-NEXT: vle64.v v16, (a0) ; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredor.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredor.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_or_v32i64: @@ -1993,10 +1993,10 @@ define i64 @vreduce_or_v32i64(<32 x i64>* %x) { ; RV64-NEXT: vle64.v v16, (a0) ; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredor.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredor.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.or.v32i64(<32 x i64> %v) @@ -2020,14 +2020,14 @@ define i64 @vreduce_or_v64i64(<64 x i64>* %x) nounwind { ; RV32-NEXT: vor.vv v8, v8, v0 ; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredor.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredor.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_or_v64i64: @@ -2044,10 +2044,10 @@ define i64 @vreduce_or_v64i64(<64 x i64>* %x) nounwind { ; RV64-NEXT: vor.vv v8, v8, v0 ; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredor.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredor.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <64 x i64>, <64 x i64>* %x %red = call i64 @llvm.vector.reduce.or.v64i64(<64 x i64> %v) @@ -2060,8 +2060,8 @@ define i8 @vreduce_xor_v1i8(<1 x i8>* %x) { ; CHECK-LABEL: vreduce_xor_v1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v1i8(<1 x i8> %v) @@ -2074,12 +2074,12 @@ define i8 @vreduce_xor_v2i8(<2 x i8>* %x) { ; CHECK-LABEL: vreduce_xor_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vredxor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v2i8(<2 x i8> %v) @@ -2092,12 +2092,12 @@ define i8 @vreduce_xor_v4i8(<4 x i8>* %x) { ; CHECK-LABEL: vreduce_xor_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vredxor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> %v) @@ -2110,12 +2110,12 @@ define i8 @vreduce_xor_v8i8(<8 x i8>* %x) { ; CHECK-LABEL: vreduce_xor_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %v) @@ -2128,12 +2128,12 @@ define i8 @vreduce_xor_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: vreduce_xor_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vredxor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %v) @@ -2147,12 +2147,12 @@ define i8 @vreduce_xor_v32i8(<32 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %v) @@ -2166,12 +2166,12 @@ define i8 @vreduce_xor_v64i8(<64 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 64 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vredxor.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v64i8(<64 x i8> %v) @@ -2187,10 +2187,10 @@ define i8 @vreduce_xor_v128i8(<128 x i8>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> %v) @@ -2209,10 +2209,10 @@ define i8 @vreduce_xor_v256i8(<256 x i8>* %x) { ; CHECK-NEXT: vle8.v v16, (a0) ; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.xor.v256i8(<256 x i8> %v) @@ -2225,8 +2225,8 @@ define i16 @vreduce_xor_v1i16(<1 x i16>* %x) { ; CHECK-LABEL: vreduce_xor_v1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v1i16(<1 x i16> %v) @@ -2239,12 +2239,12 @@ define i16 @vreduce_xor_v2i16(<2 x i16>* %x) { ; CHECK-LABEL: vreduce_xor_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vredxor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v2i16(<2 x i16> %v) @@ -2257,12 +2257,12 @@ define i16 @vreduce_xor_v4i16(<4 x i16>* %x) { ; CHECK-LABEL: vreduce_xor_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %v) @@ -2275,12 +2275,12 @@ define i16 @vreduce_xor_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: vreduce_xor_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vredxor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %v) @@ -2293,12 +2293,12 @@ define i16 @vreduce_xor_v16i16(<16 x i16>* %x) { ; CHECK-LABEL: vreduce_xor_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %v) @@ -2312,12 +2312,12 @@ define i16 @vreduce_xor_v32i16(<32 x i16>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vredxor.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v32i16(<32 x i16> %v) @@ -2333,10 +2333,10 @@ define i16 @vreduce_xor_v64i16(<64 x i16>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v64i16(<64 x i16> %v) @@ -2355,10 +2355,10 @@ define i16 @vreduce_xor_v128i16(<128 x i16>* %x) { ; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.xor.v128i16(<128 x i16> %v) @@ -2371,8 +2371,8 @@ define i32 @vreduce_xor_v1i32(<1 x i32>* %x) { ; CHECK-LABEL: vreduce_xor_v1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.xor.v1i32(<1 x i32> %v) @@ -2385,12 +2385,12 @@ define i32 @vreduce_xor_v2i32(<2 x i32>* %x) { ; CHECK-LABEL: vreduce_xor_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %v) @@ -2403,12 +2403,12 @@ define i32 @vreduce_xor_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: vreduce_xor_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vredxor.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %v) @@ -2421,12 +2421,12 @@ define i32 @vreduce_xor_v8i32(<8 x i32>* %x) { ; CHECK-LABEL: vreduce_xor_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %v) @@ -2439,12 +2439,12 @@ define i32 @vreduce_xor_v16i32(<16 x i32>* %x) { ; CHECK-LABEL: vreduce_xor_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vredxor.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %v) @@ -2460,10 +2460,10 @@ define i32 @vreduce_xor_v32i32(<32 x i32>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.xor.v32i32(<32 x i32> %v) @@ -2482,10 +2482,10 @@ define i32 @vreduce_xor_v64i32(<64 x i32>* %x) { ; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.xor.v64i32(<64 x i32> %v) @@ -2498,18 +2498,18 @@ define i64 @vreduce_xor_v1i64(<1 x i64>* %x) { ; RV32-LABEL: vreduce_xor_v1i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a0, zero, 32 -; RV32-NEXT: vsrl.vx v26, v25, a0 -; RV32-NEXT: vmv.x.s a1, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_xor_v1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.xor.v1i64(<1 x i64> %v) @@ -2522,27 +2522,27 @@ define i64 @vreduce_xor_v2i64(<2 x i64>* %x) { ; RV32-LABEL: vreduce_xor_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v26, 0 +; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vredxor.vs v25, v25, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredxor.vs v8, v8, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_xor_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v26, 0 +; RV64-NEXT: vmv.v.i v9, 0 ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vredxor.vs v25, v25, v26 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredxor.vs v8, v8, v9 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %v) @@ -2555,27 +2555,27 @@ define i64 @vreduce_xor_v4i64(<4 x i64>* %x) { ; RV32-LABEL: vreduce_xor_v4i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vle64.v v26, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vredxor.vs v25, v26, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredxor.vs v8, v8, v10 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_xor_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v26, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v10, 0 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vredxor.vs v25, v26, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredxor.vs v8, v8, v10 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %v) @@ -2588,27 +2588,27 @@ define i64 @vreduce_xor_v8i64(<8 x i64>* %x) { ; RV32-LABEL: vreduce_xor_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vle64.v v28, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v12, 0 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vredxor.vs v25, v28, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredxor.vs v8, v8, v12 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_xor_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v28, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v12, 0 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vredxor.vs v25, v28, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredxor.vs v8, v8, v12 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %v) @@ -2623,14 +2623,14 @@ define i64 @vreduce_xor_v16i64(<16 x i64>* %x) { ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredxor.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredxor.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_xor_v16i64: @@ -2638,10 +2638,10 @@ define i64 @vreduce_xor_v16i64(<16 x i64>* %x) { ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredxor.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredxor.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.xor.v16i64(<16 x i64> %v) @@ -2659,14 +2659,14 @@ define i64 @vreduce_xor_v32i64(<32 x i64>* %x) { ; RV32-NEXT: vle64.v v16, (a0) ; RV32-NEXT: vxor.vv v8, v8, v16 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredxor.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredxor.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_xor_v32i64: @@ -2677,10 +2677,10 @@ define i64 @vreduce_xor_v32i64(<32 x i64>* %x) { ; RV64-NEXT: vle64.v v16, (a0) ; RV64-NEXT: vxor.vv v8, v8, v16 ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredxor.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredxor.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.xor.v32i64(<32 x i64> %v) @@ -2704,14 +2704,14 @@ define i64 @vreduce_xor_v64i64(<64 x i64>* %x) nounwind { ; RV32-NEXT: vxor.vv v8, v8, v0 ; RV32-NEXT: vxor.vv v8, v8, v16 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredxor.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredxor.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_xor_v64i64: @@ -2728,10 +2728,10 @@ define i64 @vreduce_xor_v64i64(<64 x i64>* %x) nounwind { ; RV64-NEXT: vxor.vv v8, v8, v0 ; RV64-NEXT: vxor.vv v8, v8, v16 ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredxor.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredxor.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <64 x i64>, <64 x i64>* %x %red = call i64 @llvm.vector.reduce.xor.v64i64(<64 x i64> %v) @@ -2744,8 +2744,8 @@ define i8 @vreduce_smin_v1i8(<1 x i8>* %x) { ; CHECK-LABEL: vreduce_smin_v1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v1i8(<1 x i8> %v) @@ -2758,13 +2758,13 @@ define i8 @vreduce_smin_v2i8(<2 x i8>* %x) { ; CHECK-LABEL: vreduce_smin_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, zero, 127 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vredmin.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> %v) @@ -2777,13 +2777,13 @@ define i8 @vreduce_smin_v4i8(<4 x i8>* %x) { ; CHECK-LABEL: vreduce_smin_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, zero, 127 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vredmin.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> %v) @@ -2796,13 +2796,13 @@ define i8 @vreduce_smin_v8i8(<8 x i8>* %x) { ; CHECK-LABEL: vreduce_smin_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, zero, 127 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vredmin.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> %v) @@ -2815,13 +2815,13 @@ define i8 @vreduce_smin_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: vreduce_smin_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, zero, 127 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vredmin.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %v) @@ -2835,13 +2835,13 @@ define i8 @vreduce_smin_v32i8(<32 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, zero, 127 ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vredmin.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> %v) @@ -2855,13 +2855,13 @@ define i8 @vreduce_smin_v64i8(<64 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 64 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, zero, 127 ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v12, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vredmin.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v64i8(<64 x i8> %v) @@ -2878,10 +2878,10 @@ define i8 @vreduce_smin_v128i8(<128 x i8>* %x) { ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, zero, 127 ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v16, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v128i8(<128 x i8> %v) @@ -2901,10 +2901,10 @@ define i8 @vreduce_smin_v256i8(<256 x i8>* %x) { ; CHECK-NEXT: vmin.vv v8, v8, v16 ; CHECK-NEXT: addi a0, zero, 127 ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v16, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.smin.v256i8(<256 x i8> %v) @@ -2917,8 +2917,8 @@ define i16 @vreduce_smin_v1i16(<1 x i16>* %x) { ; CHECK-LABEL: vreduce_smin_v1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v1i16(<1 x i16> %v) @@ -2931,27 +2931,27 @@ define i16 @vreduce_smin_v2i16(<2 x i16>* %x) { ; RV32-LABEL: vreduce_smin_v2i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV32-NEXT: vle16.v v25, (a0) +; RV32-NEXT: vle16.v v8, (a0) ; RV32-NEXT: lui a0, 8 ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v26, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV32-NEXT: vredmin.vs v25, v25, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v2i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV64-NEXT: vle16.v v25, (a0) +; RV64-NEXT: vle16.v v8, (a0) ; RV64-NEXT: lui a0, 8 ; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v26, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV64-NEXT: vredmin.vs v25, v25, v26 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v9 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> %v) @@ -2964,27 +2964,27 @@ define i16 @vreduce_smin_v4i16(<4 x i16>* %x) { ; RV32-LABEL: vreduce_smin_v4i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; RV32-NEXT: vle16.v v25, (a0) +; RV32-NEXT: vle16.v v8, (a0) ; RV32-NEXT: lui a0, 8 ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v26, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; RV32-NEXT: vredmin.vs v25, v25, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v4i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; RV64-NEXT: vle16.v v25, (a0) +; RV64-NEXT: vle16.v v8, (a0) ; RV64-NEXT: lui a0, 8 ; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v26, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; RV64-NEXT: vredmin.vs v25, v25, v26 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v9 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %v) @@ -2997,27 +2997,27 @@ define i16 @vreduce_smin_v8i16(<8 x i16>* %x) { ; RV32-LABEL: vreduce_smin_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV32-NEXT: vle16.v v25, (a0) +; RV32-NEXT: vle16.v v8, (a0) ; RV32-NEXT: lui a0, 8 ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v26, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV32-NEXT: vredmin.vs v25, v25, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV64-NEXT: vle16.v v25, (a0) +; RV64-NEXT: vle16.v v8, (a0) ; RV64-NEXT: lui a0, 8 ; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v26, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; RV64-NEXT: vredmin.vs v25, v25, v26 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v9 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %v) @@ -3030,27 +3030,27 @@ define i16 @vreduce_smin_v16i16(<16 x i16>* %x) { ; RV32-LABEL: vreduce_smin_v16i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; RV32-NEXT: vle16.v v26, (a0) +; RV32-NEXT: vle16.v v8, (a0) ; RV32-NEXT: lui a0, 8 ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v10, a0 ; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; RV32-NEXT: vredmin.vs v25, v26, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v10 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v16i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; RV64-NEXT: vle16.v v26, (a0) +; RV64-NEXT: vle16.v v8, (a0) ; RV64-NEXT: lui a0, 8 ; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; RV64-NEXT: vredmin.vs v25, v26, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v10 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %v) @@ -3064,28 +3064,28 @@ define i16 @vreduce_smin_v32i16(<32 x i16>* %x) { ; RV32: # %bb.0: ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; RV32-NEXT: vle16.v v28, (a0) +; RV32-NEXT: vle16.v v8, (a0) ; RV32-NEXT: lui a0, 8 ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v12, a0 ; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; RV32-NEXT: vredmin.vs v25, v28, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v12 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v32i16: ; RV64: # %bb.0: ; RV64-NEXT: addi a1, zero, 32 ; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; RV64-NEXT: vle16.v v28, (a0) +; RV64-NEXT: vle16.v v8, (a0) ; RV64-NEXT: lui a0, 8 ; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v12, a0 ; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; RV64-NEXT: vredmin.vs v25, v28, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v12 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v32i16(<32 x i16> %v) @@ -3103,10 +3103,10 @@ define i16 @vreduce_smin_v64i16(<64 x i16>* %x) { ; RV32-NEXT: lui a0, 8 ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v16, a0 ; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; RV32-NEXT: vredmin.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v64i16: @@ -3117,10 +3117,10 @@ define i16 @vreduce_smin_v64i16(<64 x i16>* %x) { ; RV64-NEXT: lui a0, 8 ; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; RV64-NEXT: vredmin.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> %v) @@ -3141,10 +3141,10 @@ define i16 @vreduce_smin_v128i16(<128 x i16>* %x) { ; RV32-NEXT: lui a0, 8 ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v16, a0 ; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; RV32-NEXT: vredmin.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v128i16: @@ -3158,10 +3158,10 @@ define i16 @vreduce_smin_v128i16(<128 x i16>* %x) { ; RV64-NEXT: lui a0, 8 ; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; RV64-NEXT: vredmin.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.smin.v128i16(<128 x i16> %v) @@ -3174,8 +3174,8 @@ define i32 @vreduce_smin_v1i32(<1 x i32>* %x) { ; CHECK-LABEL: vreduce_smin_v1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.smin.v1i32(<1 x i32> %v) @@ -3188,27 +3188,27 @@ define i32 @vreduce_smin_v2i32(<2 x i32>* %x) { ; RV32-LABEL: vreduce_smin_v2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vle32.v v25, (a0) +; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v26, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vredmin.vs v25, v25, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v2i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vle32.v v25, (a0) +; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: lui a0, 524288 ; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v26, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vredmin.vs v25, v25, v26 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v9 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> %v) @@ -3221,27 +3221,27 @@ define i32 @vreduce_smin_v4i32(<4 x i32>* %x) { ; RV32-LABEL: vreduce_smin_v4i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vle32.v v25, (a0) +; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v26, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vredmin.vs v25, v25, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v4i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV64-NEXT: vle32.v v25, (a0) +; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: lui a0, 524288 ; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v26, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV64-NEXT: vredmin.vs v25, v25, v26 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v9 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %v) @@ -3254,27 +3254,27 @@ define i32 @vreduce_smin_v8i32(<8 x i32>* %x) { ; RV32-LABEL: vreduce_smin_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vle32.v v26, (a0) +; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v10, a0 ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vredmin.vs v25, v26, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v10 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV64-NEXT: vle32.v v26, (a0) +; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: lui a0, 524288 ; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV64-NEXT: vredmin.vs v25, v26, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v10 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %v) @@ -3287,27 +3287,27 @@ define i32 @vreduce_smin_v16i32(<16 x i32>* %x) { ; RV32-LABEL: vreduce_smin_v16i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; RV32-NEXT: vle32.v v28, (a0) +; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v12, a0 ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; RV32-NEXT: vredmin.vs v25, v28, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v12 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v16i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; RV64-NEXT: vle32.v v28, (a0) +; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: lui a0, 524288 ; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v12, a0 ; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; RV64-NEXT: vredmin.vs v25, v28, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v12 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> %v) @@ -3325,10 +3325,10 @@ define i32 @vreduce_smin_v32i32(<32 x i32>* %x) { ; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v16, a0 ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; RV32-NEXT: vredmin.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v32i32: @@ -3339,10 +3339,10 @@ define i32 @vreduce_smin_v32i32(<32 x i32>* %x) { ; RV64-NEXT: lui a0, 524288 ; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; RV64-NEXT: vredmin.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> %v) @@ -3363,10 +3363,10 @@ define i32 @vreduce_smin_v64i32(<64 x i32>* %x) { ; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v16, a0 ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; RV32-NEXT: vredmin.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v64i32: @@ -3380,10 +3380,10 @@ define i32 @vreduce_smin_v64i32(<64 x i32>* %x) { ; RV64-NEXT: lui a0, 524288 ; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; RV64-NEXT: vredmin.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.smin.v64i32(<64 x i32> %v) @@ -3396,18 +3396,18 @@ define i64 @vreduce_smin_v1i64(<1 x i64>* %x) { ; RV32-LABEL: vreduce_smin_v1i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a0, zero, 32 -; RV32-NEXT: vsrl.vx v26, v25, a0 -; RV32-NEXT: vmv.x.s a1, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> %v) @@ -3422,7 +3422,7 @@ define i64 @vreduce_smin_v2i64(<2 x i64>* %x) { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a0, zero, -1 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: lui a0, 524288 @@ -3430,28 +3430,28 @@ define i64 @vreduce_smin_v2i64(<2 x i64>* %x) { ; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vredmin.vs v25, v25, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: addi a0, zero, -1 ; RV64-NEXT: srli a0, a0, 1 ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v26, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vredmin.vs v25, v25, v26 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v9 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %v) @@ -3466,7 +3466,7 @@ define i64 @vreduce_smin_v4i64(<4 x i64>* %x) { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vle64.v v26, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a0, zero, -1 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: lui a0, 524288 @@ -3474,28 +3474,28 @@ define i64 @vreduce_smin_v4i64(<4 x i64>* %x) { ; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vredmin.vs v25, v26, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v10 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v26, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: addi a0, zero, -1 ; RV64-NEXT: srli a0, a0, 1 ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vredmin.vs v25, v26, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v10 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %v) @@ -3510,7 +3510,7 @@ define i64 @vreduce_smin_v8i64(<8 x i64>* %x) { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vle64.v v28, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a0, zero, -1 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: lui a0, 524288 @@ -3518,28 +3518,28 @@ define i64 @vreduce_smin_v8i64(<8 x i64>* %x) { ; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vredmin.vs v25, v28, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v12 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smin_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v28, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: addi a0, zero, -1 ; RV64-NEXT: srli a0, a0, 1 ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v12, a0 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vredmin.vs v25, v28, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v12 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> %v) @@ -3562,14 +3562,14 @@ define i64 @vreduce_smin_v16i64(<16 x i64>* %x) { ; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredmin.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -3580,10 +3580,10 @@ define i64 @vreduce_smin_v16i64(<16 x i64>* %x) { ; RV64-NEXT: addi a0, zero, -1 ; RV64-NEXT: srli a0, a0, 1 ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredmin.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> %v) @@ -3609,14 +3609,14 @@ define i64 @vreduce_smin_v32i64(<32 x i64>* %x) { ; RV32-NEXT: vmin.vv v8, v8, v16 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredmin.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -3630,10 +3630,10 @@ define i64 @vreduce_smin_v32i64(<32 x i64>* %x) { ; RV64-NEXT: addi a0, zero, -1 ; RV64-NEXT: srli a0, a0, 1 ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredmin.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.smin.v32i64(<32 x i64> %v) @@ -3664,14 +3664,14 @@ define i64 @vreduce_smin_v64i64(<64 x i64>* %x) nounwind { ; RV32-NEXT: vmin.vv v8, v8, v24 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredmin.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -3691,10 +3691,10 @@ define i64 @vreduce_smin_v64i64(<64 x i64>* %x) nounwind { ; RV64-NEXT: addi a0, zero, -1 ; RV64-NEXT: srli a0, a0, 1 ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredmin.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <64 x i64>, <64 x i64>* %x %red = call i64 @llvm.vector.reduce.smin.v64i64(<64 x i64> %v) @@ -3707,8 +3707,8 @@ define i8 @vreduce_smax_v1i8(<1 x i8>* %x) { ; CHECK-LABEL: vreduce_smax_v1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v1i8(<1 x i8> %v) @@ -3721,13 +3721,13 @@ define i8 @vreduce_smax_v2i8(<2 x i8>* %x) { ; CHECK-LABEL: vreduce_smax_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, zero, -128 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vredmax.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> %v) @@ -3740,13 +3740,13 @@ define i8 @vreduce_smax_v4i8(<4 x i8>* %x) { ; CHECK-LABEL: vreduce_smax_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, zero, -128 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vredmax.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> %v) @@ -3759,13 +3759,13 @@ define i8 @vreduce_smax_v8i8(<8 x i8>* %x) { ; CHECK-LABEL: vreduce_smax_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, zero, -128 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> %v) @@ -3778,13 +3778,13 @@ define i8 @vreduce_smax_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: vreduce_smax_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, zero, -128 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vredmax.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %v) @@ -3798,13 +3798,13 @@ define i8 @vreduce_smax_v32i8(<32 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, zero, -128 ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> %v) @@ -3818,13 +3818,13 @@ define i8 @vreduce_smax_v64i8(<64 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 64 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, zero, -128 ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v12, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vredmax.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v64i8(<64 x i8> %v) @@ -3841,10 +3841,10 @@ define i8 @vreduce_smax_v128i8(<128 x i8>* %x) { ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: addi a0, zero, -128 ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v16, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v128i8(<128 x i8> %v) @@ -3864,10 +3864,10 @@ define i8 @vreduce_smax_v256i8(<256 x i8>* %x) { ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: addi a0, zero, -128 ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v16, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.smax.v256i8(<256 x i8> %v) @@ -3880,8 +3880,8 @@ define i16 @vreduce_smax_v1i16(<1 x i16>* %x) { ; CHECK-LABEL: vreduce_smax_v1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v1i16(<1 x i16> %v) @@ -3894,13 +3894,13 @@ define i16 @vreduce_smax_v2i16(<2 x i16>* %x) { ; CHECK-LABEL: vreduce_smax_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vredmax.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> %v) @@ -3913,13 +3913,13 @@ define i16 @vreduce_smax_v4i16(<4 x i16>* %x) { ; CHECK-LABEL: vreduce_smax_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %v) @@ -3932,13 +3932,13 @@ define i16 @vreduce_smax_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: vreduce_smax_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vredmax.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %v) @@ -3951,13 +3951,13 @@ define i16 @vreduce_smax_v16i16(<16 x i16>* %x) { ; CHECK-LABEL: vreduce_smax_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %v) @@ -3971,13 +3971,13 @@ define i16 @vreduce_smax_v32i16(<32 x i16>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v12, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vredmax.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v32i16(<32 x i16> %v) @@ -3994,10 +3994,10 @@ define i16 @vreduce_smax_v64i16(<64 x i16>* %x) { ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v16, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> %v) @@ -4017,10 +4017,10 @@ define i16 @vreduce_smax_v128i16(<128 x i16>* %x) { ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v16, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.smax.v128i16(<128 x i16> %v) @@ -4033,8 +4033,8 @@ define i32 @vreduce_smax_v1i32(<1 x i32>* %x) { ; CHECK-LABEL: vreduce_smax_v1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.smax.v1i32(<1 x i32> %v) @@ -4047,13 +4047,13 @@ define i32 @vreduce_smax_v2i32(<2 x i32>* %x) { ; CHECK-LABEL: vreduce_smax_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> %v) @@ -4066,13 +4066,13 @@ define i32 @vreduce_smax_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: vreduce_smax_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vredmax.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %v) @@ -4085,13 +4085,13 @@ define i32 @vreduce_smax_v8i32(<8 x i32>* %x) { ; CHECK-LABEL: vreduce_smax_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %v) @@ -4104,13 +4104,13 @@ define i32 @vreduce_smax_v16i32(<16 x i32>* %x) { ; CHECK-LABEL: vreduce_smax_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v12, a0 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vredmax.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %v) @@ -4127,10 +4127,10 @@ define i32 @vreduce_smax_v32i32(<32 x i32>* %x) { ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v16, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> %v) @@ -4150,10 +4150,10 @@ define i32 @vreduce_smax_v64i32(<64 x i32>* %x) { ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v16, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.smax.v64i32(<64 x i32> %v) @@ -4166,18 +4166,18 @@ define i64 @vreduce_smax_v1i64(<1 x i64>* %x) { ; RV32-LABEL: vreduce_smax_v1i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a0, zero, 32 -; RV32-NEXT: vsrl.vx v26, v25, a0 -; RV32-NEXT: vmv.x.s a1, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> %v) @@ -4192,34 +4192,34 @@ define i64 @vreduce_smax_v2i64(<2 x i64>* %x) { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vredmax.vs v25, v25, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmax.vs v8, v8, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: addi a0, zero, -1 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v26, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vredmax.vs v25, v25, v26 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmax.vs v8, v8, v9 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %v) @@ -4234,34 +4234,34 @@ define i64 @vreduce_smax_v4i64(<4 x i64>* %x) { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vle64.v v26, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vredmax.vs v25, v26, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmax.vs v8, v8, v10 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v26, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: addi a0, zero, -1 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vredmax.vs v25, v26, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmax.vs v8, v8, v10 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v) @@ -4276,34 +4276,34 @@ define i64 @vreduce_smax_v8i64(<8 x i64>* %x) { ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vle64.v v28, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vredmax.vs v25, v28, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmax.vs v8, v8, v12 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_smax_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v28, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: addi a0, zero, -1 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v12, a0 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vredmax.vs v25, v28, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmax.vs v8, v8, v12 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> %v) @@ -4324,14 +4324,14 @@ define i64 @vreduce_smax_v16i64(<16 x i64>* %x) { ; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredmax.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmax.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -4342,10 +4342,10 @@ define i64 @vreduce_smax_v16i64(<16 x i64>* %x) { ; RV64-NEXT: addi a0, zero, -1 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredmax.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmax.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> %v) @@ -4369,14 +4369,14 @@ define i64 @vreduce_smax_v32i64(<32 x i64>* %x) { ; RV32-NEXT: vmax.vv v8, v8, v16 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredmax.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmax.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -4390,10 +4390,10 @@ define i64 @vreduce_smax_v32i64(<32 x i64>* %x) { ; RV64-NEXT: addi a0, zero, -1 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredmax.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmax.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.smax.v32i64(<32 x i64> %v) @@ -4422,14 +4422,14 @@ define i64 @vreduce_smax_v64i64(<64 x i64>* %x) nounwind { ; RV32-NEXT: vmax.vv v8, v8, v24 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredmax.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmax.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -4449,10 +4449,10 @@ define i64 @vreduce_smax_v64i64(<64 x i64>* %x) nounwind { ; RV64-NEXT: addi a0, zero, -1 ; RV64-NEXT: slli a0, a0, 63 ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredmax.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmax.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <64 x i64>, <64 x i64>* %x %red = call i64 @llvm.vector.reduce.smax.v64i64(<64 x i64> %v) @@ -4465,8 +4465,8 @@ define i8 @vreduce_umin_v1i8(<1 x i8>* %x) { ; CHECK-LABEL: vreduce_umin_v1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v1i8(<1 x i8> %v) @@ -4479,12 +4479,12 @@ define i8 @vreduce_umin_v2i8(<2 x i8>* %x) { ; CHECK-LABEL: vreduce_umin_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vredminu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v2i8(<2 x i8> %v) @@ -4497,12 +4497,12 @@ define i8 @vreduce_umin_v4i8(<4 x i8>* %x) { ; CHECK-LABEL: vreduce_umin_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vredminu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> %v) @@ -4515,12 +4515,12 @@ define i8 @vreduce_umin_v8i8(<8 x i8>* %x) { ; CHECK-LABEL: vreduce_umin_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> %v) @@ -4533,12 +4533,12 @@ define i8 @vreduce_umin_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: vreduce_umin_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vredminu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %v) @@ -4552,12 +4552,12 @@ define i8 @vreduce_umin_v32i8(<32 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> %v) @@ -4571,12 +4571,12 @@ define i8 @vreduce_umin_v64i8(<64 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 64 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v12, -1 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vredminu.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v64i8(<64 x i8> %v) @@ -4592,10 +4592,10 @@ define i8 @vreduce_umin_v128i8(<128 x i8>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v16, -1 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v128i8(<128 x i8> %v) @@ -4614,10 +4614,10 @@ define i8 @vreduce_umin_v256i8(<256 x i8>* %x) { ; CHECK-NEXT: vle8.v v16, (a0) ; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v16, -1 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.umin.v256i8(<256 x i8> %v) @@ -4630,8 +4630,8 @@ define i16 @vreduce_umin_v1i16(<1 x i16>* %x) { ; CHECK-LABEL: vreduce_umin_v1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v1i16(<1 x i16> %v) @@ -4644,12 +4644,12 @@ define i16 @vreduce_umin_v2i16(<2 x i16>* %x) { ; CHECK-LABEL: vreduce_umin_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vredminu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v2i16(<2 x i16> %v) @@ -4662,12 +4662,12 @@ define i16 @vreduce_umin_v4i16(<4 x i16>* %x) { ; CHECK-LABEL: vreduce_umin_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> %v) @@ -4680,12 +4680,12 @@ define i16 @vreduce_umin_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: vreduce_umin_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vredminu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %v) @@ -4698,12 +4698,12 @@ define i16 @vreduce_umin_v16i16(<16 x i16>* %x) { ; CHECK-LABEL: vreduce_umin_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %v) @@ -4717,12 +4717,12 @@ define i16 @vreduce_umin_v32i16(<32 x i16>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v12, -1 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vredminu.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v32i16(<32 x i16> %v) @@ -4738,10 +4738,10 @@ define i16 @vreduce_umin_v64i16(<64 x i16>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v16, -1 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> %v) @@ -4760,10 +4760,10 @@ define i16 @vreduce_umin_v128i16(<128 x i16>* %x) { ; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v16, -1 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.umin.v128i16(<128 x i16> %v) @@ -4776,8 +4776,8 @@ define i32 @vreduce_umin_v1i32(<1 x i32>* %x) { ; CHECK-LABEL: vreduce_umin_v1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.umin.v1i32(<1 x i32> %v) @@ -4790,12 +4790,12 @@ define i32 @vreduce_umin_v2i32(<2 x i32>* %x) { ; CHECK-LABEL: vreduce_umin_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> %v) @@ -4808,12 +4808,12 @@ define i32 @vreduce_umin_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: vreduce_umin_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vredminu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %v) @@ -4826,12 +4826,12 @@ define i32 @vreduce_umin_v8i32(<8 x i32>* %x) { ; CHECK-LABEL: vreduce_umin_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %v) @@ -4844,12 +4844,12 @@ define i32 @vreduce_umin_v16i32(<16 x i32>* %x) { ; CHECK-LABEL: vreduce_umin_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v12, -1 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vredminu.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %v) @@ -4865,10 +4865,10 @@ define i32 @vreduce_umin_v32i32(<32 x i32>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v16, -1 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> %v) @@ -4887,10 +4887,10 @@ define i32 @vreduce_umin_v64i32(<64 x i32>* %x) { ; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v16, -1 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.umin.v64i32(<64 x i32> %v) @@ -4903,18 +4903,18 @@ define i64 @vreduce_umin_v1i64(<1 x i64>* %x) { ; RV32-LABEL: vreduce_umin_v1i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a0, zero, 32 -; RV32-NEXT: vsrl.vx v26, v25, a0 -; RV32-NEXT: vmv.x.s a1, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umin_v1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> %v) @@ -4927,27 +4927,27 @@ define i64 @vreduce_umin_v2i64(<2 x i64>* %x) { ; RV32-LABEL: vreduce_umin_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v26, -1 +; RV32-NEXT: vmv.v.i v9, -1 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vredminu.vs v25, v25, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v8, v8, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umin_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v26, -1 +; RV64-NEXT: vmv.v.i v9, -1 ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vredminu.vs v25, v25, v26 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v8, v8, v9 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %v) @@ -4960,27 +4960,27 @@ define i64 @vreduce_umin_v4i64(<4 x i64>* %x) { ; RV32-LABEL: vreduce_umin_v4i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vle64.v v26, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, -1 +; RV32-NEXT: vmv.v.i v10, -1 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vredminu.vs v25, v26, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v8, v8, v10 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umin_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v26, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, -1 +; RV64-NEXT: vmv.v.i v10, -1 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vredminu.vs v25, v26, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v8, v8, v10 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %v) @@ -4993,27 +4993,27 @@ define i64 @vreduce_umin_v8i64(<8 x i64>* %x) { ; RV32-LABEL: vreduce_umin_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vle64.v v28, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, -1 +; RV32-NEXT: vmv.v.i v12, -1 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vredminu.vs v25, v28, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v8, v8, v12 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umin_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v28, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, -1 +; RV64-NEXT: vmv.v.i v12, -1 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vredminu.vs v25, v28, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v8, v8, v12 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> %v) @@ -5028,14 +5028,14 @@ define i64 @vreduce_umin_v16i64(<16 x i64>* %x) { ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, -1 +; RV32-NEXT: vmv.v.i v16, -1 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredminu.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umin_v16i64: @@ -5043,10 +5043,10 @@ define i64 @vreduce_umin_v16i64(<16 x i64>* %x) { ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, -1 +; RV64-NEXT: vmv.v.i v16, -1 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredminu.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> %v) @@ -5064,14 +5064,14 @@ define i64 @vreduce_umin_v32i64(<32 x i64>* %x) { ; RV32-NEXT: vle64.v v16, (a0) ; RV32-NEXT: vminu.vv v8, v8, v16 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, -1 +; RV32-NEXT: vmv.v.i v16, -1 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredminu.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umin_v32i64: @@ -5082,10 +5082,10 @@ define i64 @vreduce_umin_v32i64(<32 x i64>* %x) { ; RV64-NEXT: vle64.v v16, (a0) ; RV64-NEXT: vminu.vv v8, v8, v16 ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, -1 +; RV64-NEXT: vmv.v.i v16, -1 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredminu.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.umin.v32i64(<32 x i64> %v) @@ -5109,14 +5109,14 @@ define i64 @vreduce_umin_v64i64(<64 x i64>* %x) nounwind { ; RV32-NEXT: vminu.vv v8, v8, v0 ; RV32-NEXT: vminu.vv v8, v8, v16 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, -1 +; RV32-NEXT: vmv.v.i v16, -1 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredminu.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umin_v64i64: @@ -5133,10 +5133,10 @@ define i64 @vreduce_umin_v64i64(<64 x i64>* %x) nounwind { ; RV64-NEXT: vminu.vv v8, v8, v0 ; RV64-NEXT: vminu.vv v8, v8, v16 ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, -1 +; RV64-NEXT: vmv.v.i v16, -1 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredminu.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <64 x i64>, <64 x i64>* %x %red = call i64 @llvm.vector.reduce.umin.v64i64(<64 x i64> %v) @@ -5149,8 +5149,8 @@ define i8 @vreduce_umax_v1i8(<1 x i8>* %x) { ; CHECK-LABEL: vreduce_umax_v1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i8>, <1 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v1i8(<1 x i8> %v) @@ -5163,12 +5163,12 @@ define i8 @vreduce_umax_v2i8(<2 x i8>* %x) { ; CHECK-LABEL: vreduce_umax_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i8>, <2 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v2i8(<2 x i8> %v) @@ -5181,12 +5181,12 @@ define i8 @vreduce_umax_v4i8(<4 x i8>* %x) { ; CHECK-LABEL: vreduce_umax_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i8>, <4 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> %v) @@ -5199,12 +5199,12 @@ define i8 @vreduce_umax_v8i8(<8 x i8>* %x) { ; CHECK-LABEL: vreduce_umax_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i8>, <8 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> %v) @@ -5217,12 +5217,12 @@ define i8 @vreduce_umax_v16i8(<16 x i8>* %x) { ; CHECK-LABEL: vreduce_umax_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i8>, <16 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %v) @@ -5236,12 +5236,12 @@ define i8 @vreduce_umax_v32i8(<32 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i8>, <32 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> %v) @@ -5255,12 +5255,12 @@ define i8 @vreduce_umax_v64i8(<64 x i8>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 64 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i8>, <64 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v64i8(<64 x i8> %v) @@ -5276,10 +5276,10 @@ define i8 @vreduce_umax_v128i8(<128 x i8>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <128 x i8>, <128 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v128i8(<128 x i8> %v) @@ -5298,10 +5298,10 @@ define i8 @vreduce_umax_v256i8(<256 x i8>* %x) { ; CHECK-NEXT: vle8.v v16, (a0) ; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <256 x i8>, <256 x i8>* %x %red = call i8 @llvm.vector.reduce.umax.v256i8(<256 x i8> %v) @@ -5314,8 +5314,8 @@ define i16 @vreduce_umax_v1i16(<1 x i16>* %x) { ; CHECK-LABEL: vreduce_umax_v1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i16>, <1 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v1i16(<1 x i16> %v) @@ -5328,12 +5328,12 @@ define i16 @vreduce_umax_v2i16(<2 x i16>* %x) { ; CHECK-LABEL: vreduce_umax_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i16>, <2 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v2i16(<2 x i16> %v) @@ -5346,12 +5346,12 @@ define i16 @vreduce_umax_v4i16(<4 x i16>* %x) { ; CHECK-LABEL: vreduce_umax_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i16>, <4 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %v) @@ -5364,12 +5364,12 @@ define i16 @vreduce_umax_v8i16(<8 x i16>* %x) { ; CHECK-LABEL: vreduce_umax_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i16>, <8 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %v) @@ -5382,12 +5382,12 @@ define i16 @vreduce_umax_v16i16(<16 x i16>* %x) { ; CHECK-LABEL: vreduce_umax_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i16>, <16 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %v) @@ -5401,12 +5401,12 @@ define i16 @vreduce_umax_v32i16(<32 x i16>* %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i16>, <32 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v32i16(<32 x i16> %v) @@ -5422,10 +5422,10 @@ define i16 @vreduce_umax_v64i16(<64 x i16>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i16>, <64 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> %v) @@ -5444,10 +5444,10 @@ define i16 @vreduce_umax_v128i16(<128 x i16>* %x) { ; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <128 x i16>, <128 x i16>* %x %red = call i16 @llvm.vector.reduce.umax.v128i16(<128 x i16> %v) @@ -5460,8 +5460,8 @@ define i32 @vreduce_umax_v1i32(<1 x i32>* %x) { ; CHECK-LABEL: vreduce_umax_v1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <1 x i32>, <1 x i32>* %x %red = call i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> %v) @@ -5474,12 +5474,12 @@ define i32 @vreduce_umax_v2i32(<2 x i32>* %x) { ; CHECK-LABEL: vreduce_umax_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <2 x i32>, <2 x i32>* %x %red = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %v) @@ -5492,12 +5492,12 @@ define i32 @vreduce_umax_v4i32(<4 x i32>* %x) { ; CHECK-LABEL: vreduce_umax_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v25, v26 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <4 x i32>, <4 x i32>* %x %red = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %v) @@ -5510,12 +5510,12 @@ define i32 @vreduce_umax_v8i32(<8 x i32>* %x) { ; CHECK-LABEL: vreduce_umax_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v26, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <8 x i32>, <8 x i32>* %x %red = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %v) @@ -5528,12 +5528,12 @@ define i32 @vreduce_umax_v16i32(<16 x i32>* %x) { ; CHECK-LABEL: vreduce_umax_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v28, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i32>, <16 x i32>* %x %red = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %v) @@ -5549,10 +5549,10 @@ define i32 @vreduce_umax_v32i32(<32 x i32>* %x) { ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <32 x i32>, <32 x i32>* %x %red = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> %v) @@ -5571,10 +5571,10 @@ define i32 @vreduce_umax_v64i32(<64 x i32>* %x) { ; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <64 x i32>, <64 x i32>* %x %red = call i32 @llvm.vector.reduce.umax.v64i32(<64 x i32> %v) @@ -5587,18 +5587,18 @@ define i64 @vreduce_umax_v1i64(<1 x i64>* %x) { ; RV32-LABEL: vreduce_umax_v1i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: addi a0, zero, 32 -; RV32-NEXT: vsrl.vx v26, v25, a0 -; RV32-NEXT: vmv.x.s a1, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vsrl.vx v9, v8, a0 +; RV32-NEXT: vmv.x.s a1, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umax_v1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vle64.v v8, (a0) +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <1 x i64>, <1 x i64>* %x %red = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> %v) @@ -5611,27 +5611,27 @@ define i64 @vreduce_umax_v2i64(<2 x i64>* %x) { ; RV32-LABEL: vreduce_umax_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vle64.v v25, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v26, 0 +; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vredmaxu.vs v25, v25, v26 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v8, v8, v9 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umax_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vle64.v v25, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v26, 0 +; RV64-NEXT: vmv.v.i v9, 0 ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vredmaxu.vs v25, v25, v26 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v8, v8, v9 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <2 x i64>, <2 x i64>* %x %red = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %v) @@ -5644,27 +5644,27 @@ define i64 @vreduce_umax_v4i64(<4 x i64>* %x) { ; RV32-LABEL: vreduce_umax_v4i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vle64.v v26, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32-NEXT: vredmaxu.vs v25, v26, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v8, v8, v10 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umax_v4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vle64.v v26, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v10, 0 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV64-NEXT: vredmaxu.vs v25, v26, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v8, v8, v10 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <4 x i64>, <4 x i64>* %x %red = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %v) @@ -5677,27 +5677,27 @@ define i64 @vreduce_umax_v8i64(<8 x i64>* %x) { ; RV32-LABEL: vreduce_umax_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vle64.v v28, (a0) +; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v12, 0 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV32-NEXT: vredmaxu.vs v25, v28, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v8, v8, v12 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umax_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vle64.v v28, (a0) +; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v12, 0 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vredmaxu.vs v25, v28, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v8, v8, v12 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <8 x i64>, <8 x i64>* %x %red = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> %v) @@ -5712,14 +5712,14 @@ define i64 @vreduce_umax_v16i64(<16 x i64>* %x) { ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umax_v16i64: @@ -5727,10 +5727,10 @@ define i64 @vreduce_umax_v16i64(<16 x i64>* %x) { ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <16 x i64>, <16 x i64>* %x %red = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> %v) @@ -5748,14 +5748,14 @@ define i64 @vreduce_umax_v32i64(<32 x i64>* %x) { ; RV32-NEXT: vle64.v v16, (a0) ; RV32-NEXT: vmaxu.vv v8, v8, v16 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umax_v32i64: @@ -5766,10 +5766,10 @@ define i64 @vreduce_umax_v32i64(<32 x i64>* %x) { ; RV64-NEXT: vle64.v v16, (a0) ; RV64-NEXT: vmaxu.vv v8, v8, v16 ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <32 x i64>, <32 x i64>* %x %red = call i64 @llvm.vector.reduce.umax.v32i64(<32 x i64> %v) @@ -5793,14 +5793,14 @@ define i64 @vreduce_umax_v64i64(<64 x i64>* %x) nounwind { ; RV32-NEXT: vmaxu.vv v8, v8, v0 ; RV32-NEXT: vmaxu.vv v8, v8, v16 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v8, v8, v16 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v8, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret ; ; RV64-LABEL: vreduce_umax_v64i64: @@ -5817,10 +5817,10 @@ define i64 @vreduce_umax_v64i64(<64 x i64>* %x) nounwind { ; RV64-NEXT: vmaxu.vv v8, v8, v0 ; RV64-NEXT: vmaxu.vv v8, v8, v16 ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v8, v8, v16 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret %v = load <64 x i64>, <64 x i64>* %x %red = call i64 @llvm.vector.reduce.umax.v64i64(<64 x i64> %v) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll index 72fc3a1ab26edddf597d36c5f77117eeb9af46a1..3bfc7e0112eff11f3646b9de655172e070135bf2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll @@ -10,9 +10,9 @@ define signext i1 @vpreduce_and_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i3 ; CHECK-LABEL: vpreduce_and_v1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 +; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 @@ -26,10 +26,10 @@ declare i1 @llvm.vp.reduce.or.v1i1(i1, <1 x i1>, <1 x i1>, i32) define signext i1 @vpreduce_or_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_or_v1i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: snez a1, a1 ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 @@ -44,10 +44,10 @@ declare i1 @llvm.vp.reduce.xor.v1i1(i1, <1 x i1>, <1 x i1>, i32) define signext i1 @vpreduce_xor_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_xor_v1i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 @@ -62,9 +62,9 @@ define signext i1 @vpreduce_and_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i3 ; CHECK-LABEL: vpreduce_and_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 +; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 @@ -78,10 +78,10 @@ declare i1 @llvm.vp.reduce.or.v2i1(i1, <2 x i1>, <2 x i1>, i32) define signext i1 @vpreduce_or_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_or_v2i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: snez a1, a1 ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 @@ -96,10 +96,10 @@ declare i1 @llvm.vp.reduce.xor.v2i1(i1, <2 x i1>, <2 x i1>, i32) define signext i1 @vpreduce_xor_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_xor_v2i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 @@ -114,9 +114,9 @@ define signext i1 @vpreduce_and_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i3 ; CHECK-LABEL: vpreduce_and_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 +; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 @@ -130,10 +130,10 @@ declare i1 @llvm.vp.reduce.or.v4i1(i1, <4 x i1>, <4 x i1>, i32) define signext i1 @vpreduce_or_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_or_v4i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: snez a1, a1 ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 @@ -148,10 +148,10 @@ declare i1 @llvm.vp.reduce.xor.v4i1(i1, <4 x i1>, <4 x i1>, i32) define signext i1 @vpreduce_xor_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_xor_v4i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 @@ -166,9 +166,9 @@ define signext i1 @vpreduce_and_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i3 ; CHECK-LABEL: vpreduce_and_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 +; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 @@ -182,10 +182,10 @@ declare i1 @llvm.vp.reduce.or.v8i1(i1, <8 x i1>, <8 x i1>, i32) define signext i1 @vpreduce_or_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_or_v8i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: snez a1, a1 ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 @@ -200,10 +200,10 @@ declare i1 @llvm.vp.reduce.xor.v8i1(i1, <8 x i1>, <8 x i1>, i32) define signext i1 @vpreduce_xor_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_xor_v8i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 @@ -218,9 +218,9 @@ define signext i1 @vpreduce_and_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, ; CHECK-LABEL: vpreduce_and_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 +; CHECK-NEXT: vmnand.mm v9, v0, v0 ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: neg a0, a0 @@ -234,10 +234,10 @@ declare i1 @llvm.vp.reduce.or.v16i1(i1, <16 x i1>, <16 x i1>, i32) define signext i1 @vpreduce_or_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_or_v16i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: snez a1, a1 ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 @@ -252,10 +252,10 @@ declare i1 @llvm.vp.reduce.xor.v16i1(i1, <16 x i1>, <16 x i1>, i32) define signext i1 @vpreduce_xor_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_xor_v16i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll index 16f9d85d7b106e06fff2db06d4a943deb94d3ea3..2ce6bfeb96beffe75ebc7652d1d43557a3710c2b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll @@ -8,8 +8,8 @@ define <2 x half> @select_v2f16(i1 zeroext %c, <2 x half> %a, <2 x half> %b) { ; CHECK-LABEL: select_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -22,8 +22,8 @@ define <2 x half> @selectcc_v2f16(half %a, half %b, <2 x half> %c, <2 x half> %d ; CHECK: # %bb.0: ; CHECK-NEXT: feq.h a0, fa0, fa1 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -36,8 +36,8 @@ define <4 x half> @select_v4f16(i1 zeroext %c, <4 x half> %a, <4 x half> %b) { ; CHECK-LABEL: select_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -50,8 +50,8 @@ define <4 x half> @selectcc_v4f16(half %a, half %b, <4 x half> %c, <4 x half> %d ; CHECK: # %bb.0: ; CHECK-NEXT: feq.h a0, fa0, fa1 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -64,8 +64,8 @@ define <8 x half> @select_v8f16(i1 zeroext %c, <8 x half> %a, <8 x half> %b) { ; CHECK-LABEL: select_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -78,8 +78,8 @@ define <8 x half> @selectcc_v8f16(half %a, half %b, <8 x half> %c, <8 x half> %d ; CHECK: # %bb.0: ; CHECK-NEXT: feq.h a0, fa0, fa1 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -415,8 +415,8 @@ define <16 x half> @select_v16f16(i1 zeroext %c, <16 x half> %a, <16 x half> %b) ; CHECK-LABEL: select_v16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -754,8 +754,8 @@ define <16 x half> @selectcc_v16f16(half %a, half %b, <16 x half> %c, <16 x half ; CHECK: # %bb.0: ; CHECK-NEXT: feq.h a0, fa0, fa1 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -768,8 +768,8 @@ define <2 x float> @select_v2f32(i1 zeroext %c, <2 x float> %a, <2 x float> %b) ; CHECK-LABEL: select_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -782,8 +782,8 @@ define <2 x float> @selectcc_v2f32(float %a, float %b, <2 x float> %c, <2 x floa ; CHECK: # %bb.0: ; CHECK-NEXT: feq.s a0, fa0, fa1 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -796,8 +796,8 @@ define <4 x float> @select_v4f32(i1 zeroext %c, <4 x float> %a, <4 x float> %b) ; CHECK-LABEL: select_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -810,8 +810,8 @@ define <4 x float> @selectcc_v4f32(float %a, float %b, <4 x float> %c, <4 x floa ; CHECK: # %bb.0: ; CHECK-NEXT: feq.s a0, fa0, fa1 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -1003,8 +1003,8 @@ define <8 x float> @select_v8f32(i1 zeroext %c, <8 x float> %a, <8 x float> %b) ; CHECK-LABEL: select_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -1198,8 +1198,8 @@ define <8 x float> @selectcc_v8f32(float %a, float %b, <8 x float> %c, <8 x floa ; CHECK: # %bb.0: ; CHECK-NEXT: feq.s a0, fa0, fa1 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -1535,8 +1535,8 @@ define <16 x float> @select_v16f32(i1 zeroext %c, <16 x float> %a, <16 x float> ; CHECK-LABEL: select_v16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret @@ -1874,8 +1874,8 @@ define <16 x float> @selectcc_v16f32(float %a, float %b, <16 x float> %c, <16 x ; CHECK: # %bb.0: ; CHECK-NEXT: feq.s a0, fa0, fa1 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret @@ -1888,8 +1888,8 @@ define <2 x double> @select_v2f64(i1 zeroext %c, <2 x double> %a, <2 x double> % ; CHECK-LABEL: select_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -1902,8 +1902,8 @@ define <2 x double> @selectcc_v2f64(double %a, double %b, <2 x double> %c, <2 x ; CHECK: # %bb.0: ; CHECK-NEXT: feq.d a0, fa0, fa1 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -2023,8 +2023,8 @@ define <4 x double> @select_v4f64(i1 zeroext %c, <4 x double> %a, <4 x double> % ; CHECK-LABEL: select_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -2146,8 +2146,8 @@ define <4 x double> @selectcc_v4f64(double %a, double %b, <4 x double> %c, <4 x ; CHECK: # %bb.0: ; CHECK-NEXT: feq.d a0, fa0, fa1 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -2339,8 +2339,8 @@ define <8 x double> @select_v8f64(i1 zeroext %c, <8 x double> %a, <8 x double> % ; CHECK-LABEL: select_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret @@ -2534,8 +2534,8 @@ define <8 x double> @selectcc_v8f64(double %a, double %b, <8 x double> %c, <8 x ; CHECK: # %bb.0: ; CHECK-NEXT: feq.d a0, fa0, fa1 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret @@ -2871,8 +2871,8 @@ define <16 x double> @select_v16f64(i1 zeroext %c, <16 x double> %a, <16 x doubl ; CHECK-LABEL: select_v16f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vmsne.vi v0, v24, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret @@ -3210,8 +3210,8 @@ define <16 x double> @selectcc_v16f64(double %a, double %b, <16 x double> %c, <1 ; CHECK: # %bb.0: ; CHECK-NEXT: feq.d a0, fa0, fa1 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vmsne.vi v0, v24, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll index 536091d1c1f6351525d922368c5e64f93cc037fa..e3f8eb3b8ef99e73add9a84b105e458580ba6658 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll @@ -8,11 +8,11 @@ define <1 x i1> @select_v1i1(i1 zeroext %c, <1 x i1> %a, <1 x i1> %b) { ; CHECK-LABEL: select_v1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v25, v25, 0 -; CHECK-NEXT: vmandnot.mm v26, v8, v25 -; CHECK-NEXT: vmand.mm v25, v0, v25 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsne.vi v9, v9, 0 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select i1 %c, <1 x i1> %a, <1 x i1> %b ret <1 x i1> %v @@ -24,11 +24,11 @@ define <1 x i1> @selectcc_v1i1(i1 signext %a, i1 signext %b, <1 x i1> %c, <1 x i ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v25, v25, 0 -; CHECK-NEXT: vmandnot.mm v26, v8, v25 -; CHECK-NEXT: vmand.mm v25, v0, v25 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsne.vi v9, v9, 0 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %cmp = icmp ne i1 %a, %b %v = select i1 %cmp, <1 x i1> %c, <1 x i1> %d @@ -39,11 +39,11 @@ define <2 x i1> @select_v2i1(i1 zeroext %c, <2 x i1> %a, <2 x i1> %b) { ; CHECK-LABEL: select_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v25, v25, 0 -; CHECK-NEXT: vmandnot.mm v26, v8, v25 -; CHECK-NEXT: vmand.mm v25, v0, v25 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsne.vi v9, v9, 0 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select i1 %c, <2 x i1> %a, <2 x i1> %b ret <2 x i1> %v @@ -55,11 +55,11 @@ define <2 x i1> @selectcc_v2i1(i1 signext %a, i1 signext %b, <2 x i1> %c, <2 x i ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v25, v25, 0 -; CHECK-NEXT: vmandnot.mm v26, v8, v25 -; CHECK-NEXT: vmand.mm v25, v0, v25 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsne.vi v9, v9, 0 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %cmp = icmp ne i1 %a, %b %v = select i1 %cmp, <2 x i1> %c, <2 x i1> %d @@ -70,11 +70,11 @@ define <4 x i1> @select_v4i1(i1 zeroext %c, <4 x i1> %a, <4 x i1> %b) { ; CHECK-LABEL: select_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v25, v25, 0 -; CHECK-NEXT: vmandnot.mm v26, v8, v25 -; CHECK-NEXT: vmand.mm v25, v0, v25 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsne.vi v9, v9, 0 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select i1 %c, <4 x i1> %a, <4 x i1> %b ret <4 x i1> %v @@ -86,11 +86,11 @@ define <4 x i1> @selectcc_v4i1(i1 signext %a, i1 signext %b, <4 x i1> %c, <4 x i ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v25, v25, 0 -; CHECK-NEXT: vmandnot.mm v26, v8, v25 -; CHECK-NEXT: vmand.mm v25, v0, v25 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsne.vi v9, v9, 0 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %cmp = icmp ne i1 %a, %b %v = select i1 %cmp, <4 x i1> %c, <4 x i1> %d @@ -101,11 +101,11 @@ define <8 x i1> @select_v8i1(i1 zeroext %c, <8 x i1> %a, <8 x i1> %b) { ; CHECK-LABEL: select_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v25, v25, 0 -; CHECK-NEXT: vmandnot.mm v26, v8, v25 -; CHECK-NEXT: vmand.mm v25, v0, v25 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsne.vi v9, v9, 0 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select i1 %c, <8 x i1> %a, <8 x i1> %b ret <8 x i1> %v @@ -117,11 +117,11 @@ define <8 x i1> @selectcc_v8i1(i1 signext %a, i1 signext %b, <8 x i1> %c, <8 x i ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v25, v25, 0 -; CHECK-NEXT: vmandnot.mm v26, v8, v25 -; CHECK-NEXT: vmand.mm v25, v0, v25 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsne.vi v9, v9, 0 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %cmp = icmp ne i1 %a, %b %v = select i1 %cmp, <8 x i1> %c, <8 x i1> %d @@ -132,11 +132,11 @@ define <16 x i1> @select_v16i1(i1 zeroext %c, <16 x i1> %a, <16 x i1> %b) { ; CHECK-LABEL: select_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v25, v25, 0 -; CHECK-NEXT: vmandnot.mm v26, v8, v25 -; CHECK-NEXT: vmand.mm v25, v0, v25 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsne.vi v9, v9, 0 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select i1 %c, <16 x i1> %a, <16 x i1> %b ret <16 x i1> %v @@ -148,11 +148,11 @@ define <16 x i1> @selectcc_v16i1(i1 signext %a, i1 signext %b, <16 x i1> %c, <16 ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v25, v25, 0 -; CHECK-NEXT: vmandnot.mm v26, v8, v25 -; CHECK-NEXT: vmand.mm v25, v0, v25 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsne.vi v9, v9, 0 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %cmp = icmp ne i1 %a, %b %v = select i1 %cmp, <16 x i1> %c, <16 x i1> %d @@ -163,8 +163,8 @@ define <2 x i8> @select_v2i8(i1 zeroext %c, <2 x i8> %a, <2 x i8> %b) { ; CHECK-LABEL: select_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %v = select i1 %c, <2 x i8> %a, <2 x i8> %b @@ -177,8 +177,8 @@ define <2 x i8> @selectcc_v2i8(i8 signext %a, i8 signext %b, <2 x i8> %c, <2 x i ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: snez a0, a0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %cmp = icmp ne i8 %a, %b @@ -190,8 +190,8 @@ define <4 x i8> @select_v4i8(i1 zeroext %c, <4 x i8> %a, <4 x i8> %b) { ; CHECK-LABEL: select_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %v = select i1 %c, <4 x i8> %a, <4 x i8> %b @@ -204,8 +204,8 @@ define <4 x i8> @selectcc_v4i8(i8 signext %a, i8 signext %b, <4 x i8> %c, <4 x i ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: snez a0, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %cmp = icmp ne i8 %a, %b @@ -217,8 +217,8 @@ define <8 x i8> @select_v8i8(i1 zeroext %c, <8 x i8> %a, <8 x i8> %b) { ; CHECK-LABEL: select_v8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %v = select i1 %c, <8 x i8> %a, <8 x i8> %b @@ -231,8 +231,8 @@ define <8 x i8> @selectcc_v8i8(i8 signext %a, i8 signext %b, <8 x i8> %c, <8 x i ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: snez a0, a0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %cmp = icmp ne i8 %a, %b @@ -244,8 +244,8 @@ define <16 x i8> @select_v16i8(i1 zeroext %c, <16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: select_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %v = select i1 %c, <16 x i8> %a, <16 x i8> %b @@ -258,8 +258,8 @@ define <16 x i8> @selectcc_v16i8(i8 signext %a, i8 signext %b, <16 x i8> %c, <16 ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: snez a0, a0 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %cmp = icmp ne i8 %a, %b @@ -271,8 +271,8 @@ define <2 x i16> @select_v2i16(i1 zeroext %c, <2 x i16> %a, <2 x i16> %b) { ; CHECK-LABEL: select_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -286,8 +286,8 @@ define <2 x i16> @selectcc_v2i16(i16 signext %a, i16 signext %b, <2 x i16> %c, < ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: snez a0, a0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -300,8 +300,8 @@ define <4 x i16> @select_v4i16(i1 zeroext %c, <4 x i16> %a, <4 x i16> %b) { ; CHECK-LABEL: select_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -315,8 +315,8 @@ define <4 x i16> @selectcc_v4i16(i16 signext %a, i16 signext %b, <4 x i16> %c, < ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: snez a0, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -329,8 +329,8 @@ define <8 x i16> @select_v8i16(i1 zeroext %c, <8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: select_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -344,8 +344,8 @@ define <8 x i16> @selectcc_v8i16(i16 signext %a, i16 signext %b, <8 x i16> %c, < ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: snez a0, a0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -358,8 +358,8 @@ define <16 x i16> @select_v16i16(i1 zeroext %c, <16 x i16> %a, <16 x i16> %b) { ; CHECK-LABEL: select_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -373,8 +373,8 @@ define <16 x i16> @selectcc_v16i16(i16 signext %a, i16 signext %b, <16 x i16> %c ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: snez a0, a0 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -387,8 +387,8 @@ define <2 x i32> @select_v2i32(i1 zeroext %c, <2 x i32> %a, <2 x i32> %b) { ; CHECK-LABEL: select_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -402,8 +402,8 @@ define <2 x i32> @selectcc_v2i32(i32 signext %a, i32 signext %b, <2 x i32> %c, < ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: snez a0, a0 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -416,8 +416,8 @@ define <4 x i32> @select_v4i32(i1 zeroext %c, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: select_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -431,8 +431,8 @@ define <4 x i32> @selectcc_v4i32(i32 signext %a, i32 signext %b, <4 x i32> %c, < ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: snez a0, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -445,8 +445,8 @@ define <8 x i32> @select_v8i32(i1 zeroext %c, <8 x i32> %a, <8 x i32> %b) { ; CHECK-LABEL: select_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -460,8 +460,8 @@ define <8 x i32> @selectcc_v8i32(i32 signext %a, i32 signext %b, <8 x i32> %c, < ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: snez a0, a0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -474,8 +474,8 @@ define <16 x i32> @select_v16i32(i1 zeroext %c, <16 x i32> %a, <16 x i32> %b) { ; CHECK-LABEL: select_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret @@ -489,8 +489,8 @@ define <16 x i32> @selectcc_v16i32(i32 signext %a, i32 signext %b, <16 x i32> %c ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: snez a0, a0 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret @@ -503,8 +503,8 @@ define <2 x i64> @select_v2i64(i1 zeroext %c, <2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: select_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -520,8 +520,8 @@ define <2 x i64> @selectcc_v2i64(i64 signext %a, i64 signext %b, <2 x i64> %c, < ; RV32-NEXT: or a0, a0, a1 ; RV32-NEXT: snez a0, a0 ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 -; RV32-NEXT: vmsne.vi v0, v25, 0 +; RV32-NEXT: vmv.v.x v10, a0 +; RV32-NEXT: vmsne.vi v0, v10, 0 ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32-NEXT: vmerge.vvm v8, v9, v8, v0 ; RV32-NEXT: ret @@ -531,8 +531,8 @@ define <2 x i64> @selectcc_v2i64(i64 signext %a, i64 signext %b, <2 x i64> %c, < ; RV64-NEXT: xor a0, a0, a1 ; RV64-NEXT: snez a0, a0 ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 -; RV64-NEXT: vmsne.vi v0, v25, 0 +; RV64-NEXT: vmv.v.x v10, a0 +; RV64-NEXT: vmsne.vi v0, v10, 0 ; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV64-NEXT: vmerge.vvm v8, v9, v8, v0 ; RV64-NEXT: ret @@ -545,8 +545,8 @@ define <4 x i64> @select_v4i64(i1 zeroext %c, <4 x i64> %a, <4 x i64> %b) { ; CHECK-LABEL: select_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -562,8 +562,8 @@ define <4 x i64> @selectcc_v4i64(i64 signext %a, i64 signext %b, <4 x i64> %c, < ; RV32-NEXT: or a0, a0, a1 ; RV32-NEXT: snez a0, a0 ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 -; RV32-NEXT: vmsne.vi v0, v25, 0 +; RV32-NEXT: vmv.v.x v12, a0 +; RV32-NEXT: vmsne.vi v0, v12, 0 ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV32-NEXT: vmerge.vvm v8, v10, v8, v0 ; RV32-NEXT: ret @@ -573,8 +573,8 @@ define <4 x i64> @selectcc_v4i64(i64 signext %a, i64 signext %b, <4 x i64> %c, < ; RV64-NEXT: xor a0, a0, a1 ; RV64-NEXT: snez a0, a0 ; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 -; RV64-NEXT: vmsne.vi v0, v25, 0 +; RV64-NEXT: vmv.v.x v12, a0 +; RV64-NEXT: vmsne.vi v0, v12, 0 ; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV64-NEXT: vmerge.vvm v8, v10, v8, v0 ; RV64-NEXT: ret @@ -587,8 +587,8 @@ define <8 x i64> @select_v8i64(i1 zeroext %c, <8 x i64> %a, <8 x i64> %b) { ; CHECK-LABEL: select_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret @@ -604,8 +604,8 @@ define <8 x i64> @selectcc_v8i64(i64 signext %a, i64 signext %b, <8 x i64> %c, < ; RV32-NEXT: or a0, a0, a1 ; RV32-NEXT: snez a0, a0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 -; RV32-NEXT: vmsne.vi v0, v25, 0 +; RV32-NEXT: vmv.v.x v16, a0 +; RV32-NEXT: vmsne.vi v0, v16, 0 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vmerge.vvm v8, v12, v8, v0 ; RV32-NEXT: ret @@ -615,8 +615,8 @@ define <8 x i64> @selectcc_v8i64(i64 signext %a, i64 signext %b, <8 x i64> %c, < ; RV64-NEXT: xor a0, a0, a1 ; RV64-NEXT: snez a0, a0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 -; RV64-NEXT: vmsne.vi v0, v25, 0 +; RV64-NEXT: vmv.v.x v16, a0 +; RV64-NEXT: vmsne.vi v0, v16, 0 ; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV64-NEXT: vmerge.vvm v8, v12, v8, v0 ; RV64-NEXT: ret @@ -629,8 +629,8 @@ define <16 x i64> @select_v16i64(i1 zeroext %c, <16 x i64> %a, <16 x i64> %b) { ; CHECK-LABEL: select_v16i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vmsne.vi v0, v24, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret @@ -646,8 +646,8 @@ define <16 x i64> @selectcc_v16i64(i64 signext %a, i64 signext %b, <16 x i64> %c ; RV32-NEXT: or a0, a0, a1 ; RV32-NEXT: snez a0, a0 ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 -; RV32-NEXT: vmsne.vi v0, v25, 0 +; RV32-NEXT: vmv.v.x v24, a0 +; RV32-NEXT: vmsne.vi v0, v24, 0 ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vmerge.vvm v8, v16, v8, v0 ; RV32-NEXT: ret @@ -657,8 +657,8 @@ define <16 x i64> @selectcc_v16i64(i64 signext %a, i64 signext %b, <16 x i64> %c ; RV64-NEXT: xor a0, a0, a1 ; RV64-NEXT: snez a0, a0 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 -; RV64-NEXT: vmsne.vi v0, v25, 0 +; RV64-NEXT: vmv.v.x v24, a0 +; RV64-NEXT: vmsne.vi v0, v24, 0 ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV64-NEXT: vmerge.vvm v8, v16, v8, v0 ; RV64-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll index 741bd68bf855f02f29741b1a952f54d4c40b0005..3ccc1410332760ad062968f7b122a7f63b3434f0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll @@ -76,16 +76,16 @@ define <2 x i16> @mgather_v2i16_align1(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16> ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 -; RV32-NEXT: vmerge.vim v25, v25, 1, v0 +; RV32-NEXT: vmv.v.i v10, 0 +; RV32-NEXT: vmerge.vim v10, v10, 1, v0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmv.v.i v26, 0 +; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; RV32-NEXT: vslideup.vi v26, v25, 0 +; RV32-NEXT: vslideup.vi v11, v10, 0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmsne.vi v25, v26, 0 +; RV32-NEXT: vmsne.vi v10, v11, 0 ; RV32-NEXT: addi a0, sp, 15 -; RV32-NEXT: vsm.v v25, (a0) +; RV32-NEXT: vsm.v v10, (a0) ; RV32-NEXT: lbu a0, 15(sp) ; RV32-NEXT: andi a1, a0, 1 ; RV32-NEXT: beqz a1, .LBB4_2 @@ -103,16 +103,16 @@ define <2 x i16> @mgather_v2i16_align1(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16> ; RV32-NEXT: beqz a0, .LBB4_4 ; RV32-NEXT: # %bb.3: # %cond.load1 ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; RV32-NEXT: vslidedown.vi v25, v8, 1 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vslidedown.vi v8, v8, 1 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: lb a1, 1(a0) ; RV32-NEXT: lbu a0, 0(a0) ; RV32-NEXT: slli a1, a1, 8 ; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV32-NEXT: vmv.s.x v25, a0 +; RV32-NEXT: vmv.s.x v8, a0 ; RV32-NEXT: vsetvli zero, zero, e16, mf4, tu, mu -; RV32-NEXT: vslideup.vi v9, v25, 1 +; RV32-NEXT: vslideup.vi v9, v8, 1 ; RV32-NEXT: .LBB4_4: # %else2 ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 @@ -123,16 +123,16 @@ define <2 x i16> @mgather_v2i16_align1(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16> ; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 -; RV64-NEXT: vmerge.vim v25, v25, 1, v0 +; RV64-NEXT: vmv.v.i v10, 0 +; RV64-NEXT: vmerge.vim v10, v10, 1, v0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vmv.v.i v26, 0 +; RV64-NEXT: vmv.v.i v11, 0 ; RV64-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; RV64-NEXT: vslideup.vi v26, v25, 0 +; RV64-NEXT: vslideup.vi v11, v10, 0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vmsne.vi v25, v26, 0 +; RV64-NEXT: vmsne.vi v10, v11, 0 ; RV64-NEXT: addi a0, sp, 15 -; RV64-NEXT: vsm.v v25, (a0) +; RV64-NEXT: vsm.v v10, (a0) ; RV64-NEXT: lbu a0, 15(sp) ; RV64-NEXT: andi a1, a0, 1 ; RV64-NEXT: beqz a1, .LBB4_2 @@ -150,16 +150,16 @@ define <2 x i16> @mgather_v2i16_align1(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16> ; RV64-NEXT: beqz a0, .LBB4_4 ; RV64-NEXT: # %bb.3: # %cond.load1 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV64-NEXT: vslidedown.vi v25, v8, 1 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vslidedown.vi v8, v8, 1 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: lb a1, 1(a0) ; RV64-NEXT: lbu a0, 0(a0) ; RV64-NEXT: slli a1, a1, 8 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV64-NEXT: vmv.s.x v25, a0 +; RV64-NEXT: vmv.s.x v8, a0 ; RV64-NEXT: vsetvli zero, zero, e16, mf4, tu, mu -; RV64-NEXT: vslideup.vi v9, v25, 1 +; RV64-NEXT: vslideup.vi v9, v8, 1 ; RV64-NEXT: .LBB4_4: # %else2 ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: addi sp, sp, 16 @@ -176,43 +176,43 @@ define <2 x i64> @mgather_v2i64_align4(<2 x i64*> %ptrs, <2 x i1> %m, <2 x i64> ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 -; RV32-NEXT: vmerge.vim v25, v25, 1, v0 +; RV32-NEXT: vmv.v.i v10, 0 +; RV32-NEXT: vmerge.vim v10, v10, 1, v0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmv.v.i v26, 0 +; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; RV32-NEXT: vslideup.vi v26, v25, 0 +; RV32-NEXT: vslideup.vi v11, v10, 0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmsne.vi v25, v26, 0 +; RV32-NEXT: vmsne.vi v10, v11, 0 ; RV32-NEXT: addi a0, sp, 15 -; RV32-NEXT: vsm.v v25, (a0) +; RV32-NEXT: vsm.v v10, (a0) ; RV32-NEXT: lbu a0, 15(sp) ; RV32-NEXT: andi a1, a0, 1 ; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: beqz a1, .LBB5_2 ; RV32-NEXT: # %bb.1: # %cond.load ; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: lw a2, 4(a1) ; RV32-NEXT: lw a1, 0(a1) -; RV32-NEXT: vslide1up.vx v26, v25, a2 -; RV32-NEXT: vslide1up.vx v27, v26, a1 +; RV32-NEXT: vslide1up.vx v11, v10, a2 +; RV32-NEXT: vslide1up.vx v12, v11, a1 ; RV32-NEXT: vsetivli zero, 1, e64, m1, tu, mu -; RV32-NEXT: vslideup.vi v9, v27, 0 +; RV32-NEXT: vslideup.vi v9, v12, 0 ; RV32-NEXT: .LBB5_2: # %else ; RV32-NEXT: andi a0, a0, 2 ; RV32-NEXT: beqz a0, .LBB5_4 ; RV32-NEXT: # %bb.3: # %cond.load1 ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; RV32-NEXT: vslidedown.vi v26, v8, 1 -; RV32-NEXT: vmv.x.s a0, v26 +; RV32-NEXT: vslidedown.vi v8, v8, 1 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: lw a1, 4(a0) ; RV32-NEXT: lw a0, 0(a0) ; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; RV32-NEXT: vslide1up.vx v26, v25, a1 -; RV32-NEXT: vslide1up.vx v25, v26, a0 +; RV32-NEXT: vslide1up.vx v8, v10, a1 +; RV32-NEXT: vslide1up.vx v10, v8, a0 ; RV32-NEXT: vsetivli zero, 2, e64, m1, tu, mu -; RV32-NEXT: vslideup.vi v9, v25, 1 +; RV32-NEXT: vslideup.vi v9, v10, 1 ; RV32-NEXT: .LBB5_4: # %else2 ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 @@ -223,16 +223,16 @@ define <2 x i64> @mgather_v2i64_align4(<2 x i64*> %ptrs, <2 x i1> %m, <2 x i64> ; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 -; RV64-NEXT: vmerge.vim v25, v25, 1, v0 +; RV64-NEXT: vmv.v.i v10, 0 +; RV64-NEXT: vmerge.vim v10, v10, 1, v0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vmv.v.i v26, 0 +; RV64-NEXT: vmv.v.i v11, 0 ; RV64-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; RV64-NEXT: vslideup.vi v26, v25, 0 +; RV64-NEXT: vslideup.vi v11, v10, 0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vmsne.vi v25, v26, 0 +; RV64-NEXT: vmsne.vi v10, v11, 0 ; RV64-NEXT: addi a0, sp, 15 -; RV64-NEXT: vsm.v v25, (a0) +; RV64-NEXT: vsm.v v10, (a0) ; RV64-NEXT: lbu a0, 15(sp) ; RV64-NEXT: andi a1, a0, 1 ; RV64-NEXT: beqz a1, .LBB5_2 @@ -250,16 +250,16 @@ define <2 x i64> @mgather_v2i64_align4(<2 x i64*> %ptrs, <2 x i1> %m, <2 x i64> ; RV64-NEXT: beqz a0, .LBB5_4 ; RV64-NEXT: # %bb.3: # %cond.load1 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV64-NEXT: vslidedown.vi v25, v8, 1 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vslidedown.vi v8, v8, 1 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: lwu a1, 4(a0) ; RV64-NEXT: lwu a0, 0(a0) ; RV64-NEXT: slli a1, a1, 32 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vmv.s.x v25, a0 +; RV64-NEXT: vmv.s.x v8, a0 ; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, mu -; RV64-NEXT: vslideup.vi v9, v25, 1 +; RV64-NEXT: vslideup.vi v9, v8, 1 ; RV64-NEXT: .LBB5_4: # %else2 ; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: addi sp, sp, 16 @@ -276,16 +276,16 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 -; RV32-NEXT: vmerge.vim v25, v25, 1, v0 +; RV32-NEXT: vmv.v.i v10, 0 +; RV32-NEXT: vmerge.vim v10, v10, 1, v0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmv.v.i v26, 0 +; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; RV32-NEXT: vslideup.vi v26, v25, 0 +; RV32-NEXT: vslideup.vi v11, v10, 0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmsne.vi v25, v26, 0 +; RV32-NEXT: vmsne.vi v10, v11, 0 ; RV32-NEXT: addi a0, sp, 15 -; RV32-NEXT: vsm.v v25, (a0) +; RV32-NEXT: vsm.v v10, (a0) ; RV32-NEXT: lbu a0, 15(sp) ; RV32-NEXT: andi a1, a0, 1 ; RV32-NEXT: bnez a1, .LBB6_5 @@ -313,11 +313,11 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m ; RV32-NEXT: beqz a1, .LBB6_2 ; RV32-NEXT: .LBB6_6: # %cond.store1 ; RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; RV32-NEXT: vslidedown.vi v25, v8, 1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vslidedown.vi v10, v8, 1 +; RV32-NEXT: vmv.x.s a1, v10 ; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; RV32-NEXT: vslidedown.vi v25, v9, 1 -; RV32-NEXT: vmv.x.s a2, v25 +; RV32-NEXT: vslidedown.vi v10, v9, 1 +; RV32-NEXT: vmv.x.s a2, v10 ; RV32-NEXT: sb a1, 0(a2) ; RV32-NEXT: srli a1, a1, 8 ; RV32-NEXT: sb a1, 1(a2) @@ -325,11 +325,11 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m ; RV32-NEXT: beqz a1, .LBB6_3 ; RV32-NEXT: .LBB6_7: # %cond.store3 ; RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; RV32-NEXT: vslidedown.vi v25, v8, 2 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vslidedown.vi v10, v8, 2 +; RV32-NEXT: vmv.x.s a1, v10 ; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; RV32-NEXT: vslidedown.vi v25, v9, 2 -; RV32-NEXT: vmv.x.s a2, v25 +; RV32-NEXT: vslidedown.vi v10, v9, 2 +; RV32-NEXT: vmv.x.s a2, v10 ; RV32-NEXT: sb a1, 0(a2) ; RV32-NEXT: srli a1, a1, 8 ; RV32-NEXT: sb a1, 1(a2) @@ -337,11 +337,11 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m ; RV32-NEXT: beqz a0, .LBB6_4 ; RV32-NEXT: .LBB6_8: # %cond.store5 ; RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; RV32-NEXT: vslidedown.vi v25, v8, 3 -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vslidedown.vi v8, v8, 3 +; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; RV32-NEXT: vslidedown.vi v25, v9, 3 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vslidedown.vi v8, v9, 3 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: sb a0, 0(a1) ; RV32-NEXT: srli a0, a0, 8 ; RV32-NEXT: sb a0, 1(a1) @@ -353,16 +353,16 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m ; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 -; RV64-NEXT: vmerge.vim v25, v25, 1, v0 +; RV64-NEXT: vmv.v.i v9, 0 +; RV64-NEXT: vmerge.vim v9, v9, 1, v0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vmv.v.i v26, 0 +; RV64-NEXT: vmv.v.i v12, 0 ; RV64-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; RV64-NEXT: vslideup.vi v26, v25, 0 +; RV64-NEXT: vslideup.vi v12, v9, 0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vmsne.vi v25, v26, 0 +; RV64-NEXT: vmsne.vi v9, v12, 0 ; RV64-NEXT: addi a0, sp, 15 -; RV64-NEXT: vsm.v v25, (a0) +; RV64-NEXT: vsm.v v9, (a0) ; RV64-NEXT: lbu a0, 15(sp) ; RV64-NEXT: andi a1, a0, 1 ; RV64-NEXT: bnez a1, .LBB6_5 @@ -390,11 +390,11 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m ; RV64-NEXT: beqz a1, .LBB6_2 ; RV64-NEXT: .LBB6_6: # %cond.store1 ; RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; RV64-NEXT: vslidedown.vi v25, v8, 1 -; RV64-NEXT: vmv.x.s a1, v25 +; RV64-NEXT: vslidedown.vi v9, v8, 1 +; RV64-NEXT: vmv.x.s a1, v9 ; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; RV64-NEXT: vslidedown.vi v26, v10, 1 -; RV64-NEXT: vmv.x.s a2, v26 +; RV64-NEXT: vslidedown.vi v12, v10, 1 +; RV64-NEXT: vmv.x.s a2, v12 ; RV64-NEXT: sb a1, 0(a2) ; RV64-NEXT: srli a1, a1, 8 ; RV64-NEXT: sb a1, 1(a2) @@ -402,11 +402,11 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m ; RV64-NEXT: beqz a1, .LBB6_3 ; RV64-NEXT: .LBB6_7: # %cond.store3 ; RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; RV64-NEXT: vslidedown.vi v25, v8, 2 -; RV64-NEXT: vmv.x.s a1, v25 +; RV64-NEXT: vslidedown.vi v9, v8, 2 +; RV64-NEXT: vmv.x.s a1, v9 ; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; RV64-NEXT: vslidedown.vi v26, v10, 2 -; RV64-NEXT: vmv.x.s a2, v26 +; RV64-NEXT: vslidedown.vi v12, v10, 2 +; RV64-NEXT: vmv.x.s a2, v12 ; RV64-NEXT: sb a1, 0(a2) ; RV64-NEXT: srli a1, a1, 8 ; RV64-NEXT: sb a1, 1(a2) @@ -414,11 +414,11 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m ; RV64-NEXT: beqz a0, .LBB6_4 ; RV64-NEXT: .LBB6_8: # %cond.store5 ; RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; RV64-NEXT: vslidedown.vi v25, v8, 3 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vslidedown.vi v8, v8, 3 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; RV64-NEXT: vslidedown.vi v26, v10, 3 -; RV64-NEXT: vmv.x.s a1, v26 +; RV64-NEXT: vslidedown.vi v8, v10, 3 +; RV64-NEXT: vmv.x.s a1, v8 ; RV64-NEXT: sb a0, 0(a1) ; RV64-NEXT: srli a0, a0, 8 ; RV64-NEXT: sb a0, 1(a1) @@ -436,16 +436,16 @@ define void @mscatter_v2i32_align2(<2 x i32> %val, <2 x i32*> %ptrs, <2 x i1> %m ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 -; RV32-NEXT: vmerge.vim v25, v25, 1, v0 +; RV32-NEXT: vmv.v.i v10, 0 +; RV32-NEXT: vmerge.vim v10, v10, 1, v0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmv.v.i v26, 0 +; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; RV32-NEXT: vslideup.vi v26, v25, 0 +; RV32-NEXT: vslideup.vi v11, v10, 0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmsne.vi v25, v26, 0 +; RV32-NEXT: vmsne.vi v10, v11, 0 ; RV32-NEXT: addi a0, sp, 15 -; RV32-NEXT: vsm.v v25, (a0) +; RV32-NEXT: vsm.v v10, (a0) ; RV32-NEXT: lbu a0, 15(sp) ; RV32-NEXT: andi a1, a0, 1 ; RV32-NEXT: bnez a1, .LBB7_3 @@ -466,10 +466,10 @@ define void @mscatter_v2i32_align2(<2 x i32> %val, <2 x i32*> %ptrs, <2 x i1> %m ; RV32-NEXT: beqz a0, .LBB7_2 ; RV32-NEXT: .LBB7_4: # %cond.store1 ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; RV32-NEXT: vslidedown.vi v25, v8, 1 -; RV32-NEXT: vmv.x.s a0, v25 -; RV32-NEXT: vslidedown.vi v25, v9, 1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vslidedown.vi v8, v8, 1 +; RV32-NEXT: vmv.x.s a0, v8 +; RV32-NEXT: vslidedown.vi v8, v9, 1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: sh a0, 0(a1) ; RV32-NEXT: srli a0, a0, 16 ; RV32-NEXT: sh a0, 2(a1) @@ -481,16 +481,16 @@ define void @mscatter_v2i32_align2(<2 x i32> %val, <2 x i32*> %ptrs, <2 x i1> %m ; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 -; RV64-NEXT: vmerge.vim v25, v25, 1, v0 +; RV64-NEXT: vmv.v.i v10, 0 +; RV64-NEXT: vmerge.vim v10, v10, 1, v0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vmv.v.i v26, 0 +; RV64-NEXT: vmv.v.i v11, 0 ; RV64-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; RV64-NEXT: vslideup.vi v26, v25, 0 +; RV64-NEXT: vslideup.vi v11, v10, 0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vmsne.vi v25, v26, 0 +; RV64-NEXT: vmsne.vi v10, v11, 0 ; RV64-NEXT: addi a0, sp, 15 -; RV64-NEXT: vsm.v v25, (a0) +; RV64-NEXT: vsm.v v10, (a0) ; RV64-NEXT: lbu a0, 15(sp) ; RV64-NEXT: andi a1, a0, 1 ; RV64-NEXT: bnez a1, .LBB7_3 @@ -512,11 +512,11 @@ define void @mscatter_v2i32_align2(<2 x i32> %val, <2 x i32*> %ptrs, <2 x i1> %m ; RV64-NEXT: beqz a0, .LBB7_2 ; RV64-NEXT: .LBB7_4: # %cond.store1 ; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; RV64-NEXT: vslidedown.vi v25, v8, 1 -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vslidedown.vi v8, v8, 1 +; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; RV64-NEXT: vslidedown.vi v25, v9, 1 -; RV64-NEXT: vmv.x.s a1, v25 +; RV64-NEXT: vslidedown.vi v8, v9, 1 +; RV64-NEXT: vmv.x.s a1, v8 ; RV64-NEXT: sh a0, 0(a1) ; RV64-NEXT: srli a0, a0, 16 ; RV64-NEXT: sh a0, 2(a1) @@ -535,16 +535,16 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vmseq.vi v0, v8, 0 ; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 -; RV32-NEXT: vmerge.vim v25, v25, 1, v0 +; RV32-NEXT: vmv.v.i v8, 0 +; RV32-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmv.v.i v26, 0 +; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; RV32-NEXT: vslideup.vi v26, v25, 0 +; RV32-NEXT: vslideup.vi v9, v8, 0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmsne.vi v25, v26, 0 +; RV32-NEXT: vmsne.vi v8, v9, 0 ; RV32-NEXT: addi a2, sp, 15 -; RV32-NEXT: vsm.v v25, (a2) +; RV32-NEXT: vsm.v v8, (a2) ; RV32-NEXT: lbu a2, 15(sp) ; RV32-NEXT: andi a3, a2, 1 ; RV32-NEXT: beqz a3, .LBB8_2 @@ -560,13 +560,13 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r ; RV32-NEXT: slli a3, a3, 16 ; RV32-NEXT: or a3, a3, a4 ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vmv.v.x v25, a3 +; RV32-NEXT: vmv.v.x v8, a3 ; RV32-NEXT: andi a2, a2, 2 ; RV32-NEXT: bnez a2, .LBB8_3 ; RV32-NEXT: j .LBB8_4 ; RV32-NEXT: .LBB8_2: ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 +; RV32-NEXT: vmv.v.i v8, 0 ; RV32-NEXT: andi a2, a2, 2 ; RV32-NEXT: beqz a2, .LBB8_4 ; RV32-NEXT: .LBB8_3: # %cond.load1 @@ -580,12 +580,12 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r ; RV32-NEXT: or a0, a3, a0 ; RV32-NEXT: slli a0, a0, 16 ; RV32-NEXT: or a0, a0, a2 -; RV32-NEXT: vmv.s.x v26, a0 +; RV32-NEXT: vmv.s.x v9, a0 ; RV32-NEXT: vsetvli zero, zero, e32, mf2, tu, mu -; RV32-NEXT: vslideup.vi v25, v26, 1 +; RV32-NEXT: vslideup.vi v8, v9, 1 ; RV32-NEXT: .LBB8_4: # %else2 ; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; RV32-NEXT: vse32.v v25, (a1) +; RV32-NEXT: vse32.v v8, (a1) ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -595,16 +595,16 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vmseq.vi v0, v8, 0 ; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 -; RV64-NEXT: vmerge.vim v25, v25, 1, v0 +; RV64-NEXT: vmv.v.i v8, 0 +; RV64-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vmv.v.i v26, 0 +; RV64-NEXT: vmv.v.i v9, 0 ; RV64-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; RV64-NEXT: vslideup.vi v26, v25, 0 +; RV64-NEXT: vslideup.vi v9, v8, 0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vmsne.vi v25, v26, 0 +; RV64-NEXT: vmsne.vi v8, v9, 0 ; RV64-NEXT: addi a2, sp, 15 -; RV64-NEXT: vsm.v v25, (a2) +; RV64-NEXT: vsm.v v8, (a2) ; RV64-NEXT: lbu a2, 15(sp) ; RV64-NEXT: andi a3, a2, 1 ; RV64-NEXT: beqz a3, .LBB8_2 @@ -620,13 +620,13 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r ; RV64-NEXT: slli a3, a3, 16 ; RV64-NEXT: or a3, a3, a4 ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vmv.v.x v25, a3 +; RV64-NEXT: vmv.v.x v8, a3 ; RV64-NEXT: andi a2, a2, 2 ; RV64-NEXT: bnez a2, .LBB8_3 ; RV64-NEXT: j .LBB8_4 ; RV64-NEXT: .LBB8_2: ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 +; RV64-NEXT: vmv.v.i v8, 0 ; RV64-NEXT: andi a2, a2, 2 ; RV64-NEXT: beqz a2, .LBB8_4 ; RV64-NEXT: .LBB8_3: # %cond.load1 @@ -640,12 +640,12 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r ; RV64-NEXT: or a0, a3, a0 ; RV64-NEXT: slli a0, a0, 16 ; RV64-NEXT: or a0, a0, a2 -; RV64-NEXT: vmv.s.x v26, a0 +; RV64-NEXT: vmv.s.x v9, a0 ; RV64-NEXT: vsetvli zero, zero, e32, mf2, tu, mu -; RV64-NEXT: vslideup.vi v25, v26, 1 +; RV64-NEXT: vslideup.vi v8, v9, 1 ; RV64-NEXT: .LBB8_4: # %else2 ; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; RV64-NEXT: vse32.v v25, (a1) +; RV64-NEXT: vse32.v v8, (a1) ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret %mask = icmp eq <2 x i32> %m, zeroinitializer @@ -663,16 +663,16 @@ define void @masked_store_v2i32_align2(<2 x i32> %val, <2 x i32>* %a, <2 x i32> ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vmseq.vi v0, v9, 0 ; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; RV32-NEXT: vmv.v.i v25, 0 -; RV32-NEXT: vmerge.vim v25, v25, 1, v0 +; RV32-NEXT: vmv.v.i v9, 0 +; RV32-NEXT: vmerge.vim v9, v9, 1, v0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmv.v.i v26, 0 +; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; RV32-NEXT: vslideup.vi v26, v25, 0 +; RV32-NEXT: vslideup.vi v10, v9, 0 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV32-NEXT: vmsne.vi v25, v26, 0 +; RV32-NEXT: vmsne.vi v9, v10, 0 ; RV32-NEXT: addi a1, sp, 15 -; RV32-NEXT: vsm.v v25, (a1) +; RV32-NEXT: vsm.v v9, (a1) ; RV32-NEXT: lbu a1, 15(sp) ; RV32-NEXT: andi a2, a1, 1 ; RV32-NEXT: bnez a2, .LBB9_3 @@ -692,8 +692,8 @@ define void @masked_store_v2i32_align2(<2 x i32> %val, <2 x i32>* %a, <2 x i32> ; RV32-NEXT: beqz a1, .LBB9_2 ; RV32-NEXT: .LBB9_4: # %cond.store1 ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; RV32-NEXT: vslidedown.vi v25, v8, 1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vslidedown.vi v8, v8, 1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: sh a1, 4(a0) ; RV32-NEXT: srli a1, a1, 16 ; RV32-NEXT: sh a1, 6(a0) @@ -706,16 +706,16 @@ define void @masked_store_v2i32_align2(<2 x i32> %val, <2 x i32>* %a, <2 x i32> ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vmseq.vi v0, v9, 0 ; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; RV64-NEXT: vmv.v.i v25, 0 -; RV64-NEXT: vmerge.vim v25, v25, 1, v0 +; RV64-NEXT: vmv.v.i v9, 0 +; RV64-NEXT: vmerge.vim v9, v9, 1, v0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vmv.v.i v26, 0 +; RV64-NEXT: vmv.v.i v10, 0 ; RV64-NEXT: vsetivli zero, 2, e8, mf2, tu, mu -; RV64-NEXT: vslideup.vi v26, v25, 0 +; RV64-NEXT: vslideup.vi v10, v9, 0 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; RV64-NEXT: vmsne.vi v25, v26, 0 +; RV64-NEXT: vmsne.vi v9, v10, 0 ; RV64-NEXT: addi a1, sp, 15 -; RV64-NEXT: vsm.v v25, (a1) +; RV64-NEXT: vsm.v v9, (a1) ; RV64-NEXT: lbu a1, 15(sp) ; RV64-NEXT: andi a2, a1, 1 ; RV64-NEXT: bnez a2, .LBB9_3 @@ -735,8 +735,8 @@ define void @masked_store_v2i32_align2(<2 x i32> %val, <2 x i32>* %a, <2 x i32> ; RV64-NEXT: beqz a1, .LBB9_2 ; RV64-NEXT: .LBB9_4: # %cond.store1 ; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu -; RV64-NEXT: vslidedown.vi v25, v8, 1 -; RV64-NEXT: vmv.x.s a1, v25 +; RV64-NEXT: vslidedown.vi v8, v8, 1 +; RV64-NEXT: vmv.x.s a1, v8 ; RV64-NEXT: sh a1, 4(a0) ; RV64-NEXT: srli a1, a1, 16 ; RV64-NEXT: sh a1, 6(a0) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll index b7fb68b14ffcc89d6a9e6200368d8eb9593eb1cd..03349765c7b94823e44deb01d75f1e44b48b8bff 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll @@ -403,23 +403,23 @@ define <256 x i8> @vadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %ev ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 128 ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu -; CHECK-NEXT: vlm.v v26, (a0) +; CHECK-NEXT: vlm.v v25, (a0) ; CHECK-NEXT: addi a3, a1, -128 -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: mv a0, zero ; CHECK-NEXT: bltu a1, a3, .LBB31_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a0, a3 ; CHECK-NEXT: .LBB31_2: ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu -; CHECK-NEXT: vmv1r.v v0, v26 +; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t ; CHECK-NEXT: bltu a1, a2, .LBB31_4 ; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: addi a1, zero, 128 ; CHECK-NEXT: .LBB31_4: ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <256 x i8> undef, i8 -1, i32 0 @@ -462,10 +462,10 @@ define <256 x i8> @vadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 128 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) +; CHECK-NEXT: vlm.v v24, (a0) ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <256 x i8> undef, i8 -1, i32 0 @@ -1130,9 +1130,9 @@ define <2 x i64> @vadd_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vadd.vv v8, v8, v25, v0.t +; RV32-NEXT: vadd.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1156,9 +1156,9 @@ define <2 x i64> @vadd_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vadd.vv v8, v8, v25 +; RV32-NEXT: vadd.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1234,9 +1234,9 @@ define <4 x i64> @vadd_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vadd.vv v8, v8, v26, v0.t +; RV32-NEXT: vadd.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1260,9 +1260,9 @@ define <4 x i64> @vadd_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vadd.vv v8, v8, v26 +; RV32-NEXT: vadd.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1338,9 +1338,9 @@ define <8 x i64> @vadd_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vadd.vv v8, v8, v28, v0.t +; RV32-NEXT: vadd.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1364,9 +1364,9 @@ define <8 x i64> @vadd_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vadd.vv v8, v8, v28 +; RV32-NEXT: vadd.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1546,7 +1546,7 @@ define <32 x i64> @vadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl ; ; RV64-LABEL: vadd_vx_v32i64: ; RV64: # %bb.0: -; RV64-NEXT: vmv1r.v v25, v0 +; RV64-NEXT: vmv1r.v v24, v0 ; RV64-NEXT: mv a1, zero ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV64-NEXT: addi a2, a0, -16 @@ -1563,7 +1563,7 @@ define <32 x i64> @vadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl ; RV64-NEXT: addi a0, zero, 16 ; RV64-NEXT: .LBB107_4: ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; RV64-NEXT: vmv1r.v v0, v25 +; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vadd.vi v8, v8, -1, v0.t ; RV64-NEXT: ret %elt.head = insertelement <32 x i64> undef, i64 -1, i32 0 @@ -1662,11 +1662,11 @@ define <32 x i64> @vadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) { ; RV64-LABEL: vadd_vx_v32i64_evl27: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, mu -; RV64-NEXT: vslidedown.vi v25, v0, 2 +; RV64-NEXT: vslidedown.vi v24, v0, 2 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vadd.vi v8, v8, -1, v0.t ; RV64-NEXT: vsetivli zero, 11, e64, m8, ta, mu -; RV64-NEXT: vmv1r.v v0, v25 +; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vadd.vi v16, v16, -1, v0.t ; RV64-NEXT: ret %elt.head = insertelement <32 x i64> undef, i64 -1, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll index dbb2df83e1ec417d5921d2fcdce9588a3672568b..3180f0445d4c171827c5ad2b488b293557af6395 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll @@ -961,9 +961,9 @@ define <2 x i64> @vand_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vand.vv v8, v8, v25, v0.t +; RV32-NEXT: vand.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -987,9 +987,9 @@ define <2 x i64> @vand_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vand.vv v8, v8, v25 +; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1065,9 +1065,9 @@ define <4 x i64> @vand_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vand.vv v8, v8, v26, v0.t +; RV32-NEXT: vand.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1091,9 +1091,9 @@ define <4 x i64> @vand_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vand.vv v8, v8, v26 +; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1169,9 +1169,9 @@ define <8 x i64> @vand_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vand.vv v8, v8, v28, v0.t +; RV32-NEXT: vand.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1195,9 +1195,9 @@ define <8 x i64> @vand_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vand.vv v8, v8, v28 +; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1267,19 +1267,19 @@ define <11 x i64> @vand_vv_v11i64_unmasked(<11 x i64> %va, <11 x i64> %b, i32 ze define <11 x i64> @vand_vx_v11i64(<11 x i64> %va, i64 %b, <11 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vand_vx_v11i64: ; RV32: # %bb.0: -; RV32-NEXT: vmv1r.v v25, v0 +; RV32-NEXT: vmv1r.v v16, v0 ; RV32-NEXT: addi a3, zero, 32 ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, mu -; RV32-NEXT: vmv.v.x v16, a1 +; RV32-NEXT: vmv.v.x v24, a1 ; RV32-NEXT: lui a1, 341 ; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-NEXT: vmv.s.x v0, a1 ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, mu -; RV32-NEXT: vmerge.vxm v16, v16, a0, v0 +; RV32-NEXT: vmerge.vxm v24, v24, a0, v0 ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu -; RV32-NEXT: vmv1r.v v0, v25 -; RV32-NEXT: vand.vv v8, v8, v16, v0.t +; RV32-NEXT: vmv1r.v v0, v16 +; RV32-NEXT: vand.vv v8, v8, v24, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vand_vx_v11i64: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll index 45293124e5dd33372620cf7fb6b23cf6fcde66e0..b7dac4e2890441e42a65d1fdd12290e8c8876fba 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll @@ -10,12 +10,12 @@ define <8 x i7> @vdiv_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex ; CHECK-LABEL: vdiv_vv_v8i7: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vadd.vv v25, v9, v9 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vadd.vv v26, v8, v8 -; CHECK-NEXT: vsra.vi v26, v26, 1 +; CHECK-NEXT: vadd.vv v9, v9, v9 +; CHECK-NEXT: vsra.vi v9, v9, 1 +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: vsra.vi v8, v8, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vdiv.vv v8, v26, v25, v0.t +; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.sdiv.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) ret <8 x i7> %v @@ -666,9 +666,9 @@ define <2 x i64> @vdiv_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vdiv.vv v8, v8, v25, v0.t +; RV32-NEXT: vdiv.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -692,9 +692,9 @@ define <2 x i64> @vdiv_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vdiv.vv v8, v8, v25 +; RV32-NEXT: vdiv.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -744,9 +744,9 @@ define <4 x i64> @vdiv_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vdiv.vv v8, v8, v26, v0.t +; RV32-NEXT: vdiv.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -770,9 +770,9 @@ define <4 x i64> @vdiv_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vdiv.vv v8, v8, v26 +; RV32-NEXT: vdiv.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -822,9 +822,9 @@ define <8 x i64> @vdiv_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vdiv.vv v8, v8, v28, v0.t +; RV32-NEXT: vdiv.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -848,9 +848,9 @@ define <8 x i64> @vdiv_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vdiv.vv v8, v8, v28 +; RV32-NEXT: vdiv.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll index 1f83ba3e5043d152d1ef2a5ecf1b7ebc6d6e511f..537583143cedf5274c2f53912aa43faefa4ab219 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll @@ -11,10 +11,10 @@ define <8 x i7> @vdivu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 127 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vand.vx v25, v9, a1 -; CHECK-NEXT: vand.vx v26, v8, a1 +; CHECK-NEXT: vand.vx v9, v9, a1 +; CHECK-NEXT: vand.vx v8, v8, a1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vdivu.vv v8, v26, v25, v0.t +; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.udiv.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) ret <8 x i7> %v @@ -665,9 +665,9 @@ define <2 x i64> @vdivu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vdivu.vv v8, v8, v25, v0.t +; RV32-NEXT: vdivu.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -691,9 +691,9 @@ define <2 x i64> @vdivu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vdivu.vv v8, v8, v25 +; RV32-NEXT: vdivu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -743,9 +743,9 @@ define <4 x i64> @vdivu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vdivu.vv v8, v8, v26, v0.t +; RV32-NEXT: vdivu.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -769,9 +769,9 @@ define <4 x i64> @vdivu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vdivu.vv v8, v8, v26 +; RV32-NEXT: vdivu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -821,9 +821,9 @@ define <8 x i64> @vdivu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vdivu.vv v8, v8, v28, v0.t +; RV32-NEXT: vdivu.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -847,9 +847,9 @@ define <8 x i64> @vdivu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vdivu.vv v8, v8, v28 +; RV32-NEXT: vdivu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll index 9302940d29ba5ac172425772cc8c61015ae29679..95e7d0702cf98d93eb090fc96d764cfa69a8b1cf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll @@ -32,9 +32,9 @@ define <2 x half> @vfadd_vf_v2f16(<2 x half> %va, half %b, <2 x i1> %m, i32 zero ; CHECK-LABEL: vfadd_vf_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> undef, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> undef, <2 x i32> zeroinitializer @@ -96,9 +96,9 @@ define <4 x half> @vfadd_vf_v4f16(<4 x half> %va, half %b, <4 x i1> %m, i32 zero ; CHECK-LABEL: vfadd_vf_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> undef, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> undef, <4 x i32> zeroinitializer @@ -148,9 +148,9 @@ define <8 x half> @vfadd_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zero ; CHECK-LABEL: vfadd_vf_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> undef, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> undef, <8 x i32> zeroinitializer @@ -200,9 +200,9 @@ define <16 x half> @vfadd_vf_v16f16(<16 x half> %va, half %b, <16 x i1> %m, i32 ; CHECK-LABEL: vfadd_vf_v16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> undef, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> undef, <16 x i32> zeroinitializer @@ -252,9 +252,9 @@ define <2 x float> @vfadd_vf_v2f32(<2 x float> %va, float %b, <2 x i1> %m, i32 z ; CHECK-LABEL: vfadd_vf_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> undef, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> undef, <2 x i32> zeroinitializer @@ -304,9 +304,9 @@ define <4 x float> @vfadd_vf_v4f32(<4 x float> %va, float %b, <4 x i1> %m, i32 z ; CHECK-LABEL: vfadd_vf_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> undef, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> undef, <4 x i32> zeroinitializer @@ -356,9 +356,9 @@ define <8 x float> @vfadd_vf_v8f32(<8 x float> %va, float %b, <8 x i1> %m, i32 z ; CHECK-LABEL: vfadd_vf_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> undef, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> undef, <8 x i32> zeroinitializer @@ -408,9 +408,9 @@ define <16 x float> @vfadd_vf_v16f32(<16 x float> %va, float %b, <16 x i1> %m, i ; CHECK-LABEL: vfadd_vf_v16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> undef, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> undef, <16 x i32> zeroinitializer @@ -460,9 +460,9 @@ define <2 x double> @vfadd_vf_v2f64(<2 x double> %va, double %b, <2 x i1> %m, i3 ; CHECK-LABEL: vfadd_vf_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> undef, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> undef, <2 x i32> zeroinitializer @@ -512,9 +512,9 @@ define <4 x double> @vfadd_vf_v4f64(<4 x double> %va, double %b, <4 x i1> %m, i3 ; CHECK-LABEL: vfadd_vf_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> undef, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> undef, <4 x i32> zeroinitializer @@ -564,9 +564,9 @@ define <8 x double> @vfadd_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i3 ; CHECK-LABEL: vfadd_vf_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> undef, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> undef, <8 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll index aa4ab8dba3a272e222e1b8fd327d545cf580bfce..355c4e99bf08dec992eae0c7b09c2c6ff576a66d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll @@ -32,9 +32,9 @@ define <2 x half> @vfdiv_vf_v2f16(<2 x half> %va, half %b, <2 x i1> %m, i32 zero ; CHECK-LABEL: vfdiv_vf_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> undef, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> undef, <2 x i32> zeroinitializer @@ -96,9 +96,9 @@ define <4 x half> @vfdiv_vf_v4f16(<4 x half> %va, half %b, <4 x i1> %m, i32 zero ; CHECK-LABEL: vfdiv_vf_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> undef, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> undef, <4 x i32> zeroinitializer @@ -148,9 +148,9 @@ define <8 x half> @vfdiv_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zero ; CHECK-LABEL: vfdiv_vf_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> undef, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> undef, <8 x i32> zeroinitializer @@ -200,9 +200,9 @@ define <16 x half> @vfdiv_vf_v16f16(<16 x half> %va, half %b, <16 x i1> %m, i32 ; CHECK-LABEL: vfdiv_vf_v16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> undef, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> undef, <16 x i32> zeroinitializer @@ -252,9 +252,9 @@ define <2 x float> @vfdiv_vf_v2f32(<2 x float> %va, float %b, <2 x i1> %m, i32 z ; CHECK-LABEL: vfdiv_vf_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> undef, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> undef, <2 x i32> zeroinitializer @@ -304,9 +304,9 @@ define <4 x float> @vfdiv_vf_v4f32(<4 x float> %va, float %b, <4 x i1> %m, i32 z ; CHECK-LABEL: vfdiv_vf_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> undef, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> undef, <4 x i32> zeroinitializer @@ -356,9 +356,9 @@ define <8 x float> @vfdiv_vf_v8f32(<8 x float> %va, float %b, <8 x i1> %m, i32 z ; CHECK-LABEL: vfdiv_vf_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> undef, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> undef, <8 x i32> zeroinitializer @@ -408,9 +408,9 @@ define <16 x float> @vfdiv_vf_v16f32(<16 x float> %va, float %b, <16 x i1> %m, i ; CHECK-LABEL: vfdiv_vf_v16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> undef, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> undef, <16 x i32> zeroinitializer @@ -460,9 +460,9 @@ define <2 x double> @vfdiv_vf_v2f64(<2 x double> %va, double %b, <2 x i1> %m, i3 ; CHECK-LABEL: vfdiv_vf_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> undef, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> undef, <2 x i32> zeroinitializer @@ -512,9 +512,9 @@ define <4 x double> @vfdiv_vf_v4f64(<4 x double> %va, double %b, <4 x i1> %m, i3 ; CHECK-LABEL: vfdiv_vf_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> undef, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> undef, <4 x i32> zeroinitializer @@ -564,9 +564,9 @@ define <8 x double> @vfdiv_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i3 ; CHECK-LABEL: vfdiv_vf_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> undef, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> undef, <8 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll index 885a16510dbb529ea241725394a22c7b3529a46c..e8ff8020665913b2b9c1a0c4d278e4fefd579ecf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll @@ -32,9 +32,9 @@ define <2 x half> @vfmul_vf_v2f16(<2 x half> %va, half %b, <2 x i1> %m, i32 zero ; CHECK-LABEL: vfmul_vf_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> undef, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> undef, <2 x i32> zeroinitializer @@ -96,9 +96,9 @@ define <4 x half> @vfmul_vf_v4f16(<4 x half> %va, half %b, <4 x i1> %m, i32 zero ; CHECK-LABEL: vfmul_vf_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> undef, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> undef, <4 x i32> zeroinitializer @@ -148,9 +148,9 @@ define <8 x half> @vfmul_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zero ; CHECK-LABEL: vfmul_vf_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> undef, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> undef, <8 x i32> zeroinitializer @@ -200,9 +200,9 @@ define <16 x half> @vfmul_vf_v16f16(<16 x half> %va, half %b, <16 x i1> %m, i32 ; CHECK-LABEL: vfmul_vf_v16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> undef, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> undef, <16 x i32> zeroinitializer @@ -252,9 +252,9 @@ define <2 x float> @vfmul_vf_v2f32(<2 x float> %va, float %b, <2 x i1> %m, i32 z ; CHECK-LABEL: vfmul_vf_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> undef, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> undef, <2 x i32> zeroinitializer @@ -304,9 +304,9 @@ define <4 x float> @vfmul_vf_v4f32(<4 x float> %va, float %b, <4 x i1> %m, i32 z ; CHECK-LABEL: vfmul_vf_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> undef, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> undef, <4 x i32> zeroinitializer @@ -356,9 +356,9 @@ define <8 x float> @vfmul_vf_v8f32(<8 x float> %va, float %b, <8 x i1> %m, i32 z ; CHECK-LABEL: vfmul_vf_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> undef, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> undef, <8 x i32> zeroinitializer @@ -408,9 +408,9 @@ define <16 x float> @vfmul_vf_v16f32(<16 x float> %va, float %b, <16 x i1> %m, i ; CHECK-LABEL: vfmul_vf_v16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> undef, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> undef, <16 x i32> zeroinitializer @@ -460,9 +460,9 @@ define <2 x double> @vfmul_vf_v2f64(<2 x double> %va, double %b, <2 x i1> %m, i3 ; CHECK-LABEL: vfmul_vf_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> undef, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> undef, <2 x i32> zeroinitializer @@ -512,9 +512,9 @@ define <4 x double> @vfmul_vf_v4f64(<4 x double> %va, double %b, <4 x i1> %m, i3 ; CHECK-LABEL: vfmul_vf_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> undef, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> undef, <4 x i32> zeroinitializer @@ -564,9 +564,9 @@ define <8 x double> @vfmul_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i3 ; CHECK-LABEL: vfmul_vf_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> undef, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> undef, <8 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll index 5745e03fc23e14becb07c6b8b7db568d7ad46672..19e9eca8d7823db1b81a53f46c5e69723cec41db 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll @@ -10,9 +10,9 @@ define <2 x half> @vfrdiv_vf_v2f16(<2 x half> %va, half %b, <2 x i1> %m, i32 zer ; CHECK-LABEL: vfrdiv_vf_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> undef, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> undef, <2 x i32> zeroinitializer @@ -40,9 +40,9 @@ define <4 x half> @vfrdiv_vf_v4f16(<4 x half> %va, half %b, <4 x i1> %m, i32 zer ; CHECK-LABEL: vfrdiv_vf_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> undef, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> undef, <4 x i32> zeroinitializer @@ -70,9 +70,9 @@ define <8 x half> @vfrdiv_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer ; CHECK-LABEL: vfrdiv_vf_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> undef, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> undef, <8 x i32> zeroinitializer @@ -100,9 +100,9 @@ define <16 x half> @vfrdiv_vf_v16f16(<16 x half> %va, half %b, <16 x i1> %m, i32 ; CHECK-LABEL: vfrdiv_vf_v16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v26, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> undef, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> undef, <16 x i32> zeroinitializer @@ -130,9 +130,9 @@ define <2 x float> @vfrdiv_vf_v2f32(<2 x float> %va, float %b, <2 x i1> %m, i32 ; CHECK-LABEL: vfrdiv_vf_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> undef, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> undef, <2 x i32> zeroinitializer @@ -160,9 +160,9 @@ define <4 x float> @vfrdiv_vf_v4f32(<4 x float> %va, float %b, <4 x i1> %m, i32 ; CHECK-LABEL: vfrdiv_vf_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> undef, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> undef, <4 x i32> zeroinitializer @@ -190,9 +190,9 @@ define <8 x float> @vfrdiv_vf_v8f32(<8 x float> %va, float %b, <8 x i1> %m, i32 ; CHECK-LABEL: vfrdiv_vf_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v26, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> undef, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> undef, <8 x i32> zeroinitializer @@ -220,9 +220,9 @@ define <16 x float> @vfrdiv_vf_v16f32(<16 x float> %va, float %b, <16 x i1> %m, ; CHECK-LABEL: vfrdiv_vf_v16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v28, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> undef, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> undef, <16 x i32> zeroinitializer @@ -250,9 +250,9 @@ define <2 x double> @vfrdiv_vf_v2f64(<2 x double> %va, double %b, <2 x i1> %m, i ; CHECK-LABEL: vfrdiv_vf_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> undef, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> undef, <2 x i32> zeroinitializer @@ -280,9 +280,9 @@ define <4 x double> @vfrdiv_vf_v4f64(<4 x double> %va, double %b, <4 x i1> %m, i ; CHECK-LABEL: vfrdiv_vf_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v26, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> undef, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> undef, <4 x i32> zeroinitializer @@ -310,9 +310,9 @@ define <8 x double> @vfrdiv_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i ; CHECK-LABEL: vfrdiv_vf_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v28, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> undef, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> undef, <8 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll index 8762766192a71d9caf38421af0acb8206926028a..b379b5a622e704fd213418e0848cb5e258471704 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll @@ -10,9 +10,9 @@ define <2 x half> @vfrsub_vf_v2f16(<2 x half> %va, half %b, <2 x i1> %m, i32 zer ; CHECK-LABEL: vfrsub_vf_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> undef, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> undef, <2 x i32> zeroinitializer @@ -40,9 +40,9 @@ define <4 x half> @vfrsub_vf_v4f16(<4 x half> %va, half %b, <4 x i1> %m, i32 zer ; CHECK-LABEL: vfrsub_vf_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> undef, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> undef, <4 x i32> zeroinitializer @@ -70,9 +70,9 @@ define <8 x half> @vfrsub_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer ; CHECK-LABEL: vfrsub_vf_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> undef, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> undef, <8 x i32> zeroinitializer @@ -100,9 +100,9 @@ define <16 x half> @vfrsub_vf_v16f16(<16 x half> %va, half %b, <16 x i1> %m, i32 ; CHECK-LABEL: vfrsub_vf_v16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v26, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> undef, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> undef, <16 x i32> zeroinitializer @@ -130,9 +130,9 @@ define <2 x float> @vfrsub_vf_v2f32(<2 x float> %va, float %b, <2 x i1> %m, i32 ; CHECK-LABEL: vfrsub_vf_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> undef, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> undef, <2 x i32> zeroinitializer @@ -160,9 +160,9 @@ define <4 x float> @vfrsub_vf_v4f32(<4 x float> %va, float %b, <4 x i1> %m, i32 ; CHECK-LABEL: vfrsub_vf_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> undef, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> undef, <4 x i32> zeroinitializer @@ -190,9 +190,9 @@ define <8 x float> @vfrsub_vf_v8f32(<8 x float> %va, float %b, <8 x i1> %m, i32 ; CHECK-LABEL: vfrsub_vf_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v26, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> undef, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> undef, <8 x i32> zeroinitializer @@ -220,9 +220,9 @@ define <16 x float> @vfrsub_vf_v16f32(<16 x float> %va, float %b, <16 x i1> %m, ; CHECK-LABEL: vfrsub_vf_v16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v28, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> undef, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> undef, <16 x i32> zeroinitializer @@ -250,9 +250,9 @@ define <2 x double> @vfrsub_vf_v2f64(<2 x double> %va, double %b, <2 x i1> %m, i ; CHECK-LABEL: vfrsub_vf_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> undef, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> undef, <2 x i32> zeroinitializer @@ -280,9 +280,9 @@ define <4 x double> @vfrsub_vf_v4f64(<4 x double> %va, double %b, <4 x i1> %m, i ; CHECK-LABEL: vfrsub_vf_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v26, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> undef, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> undef, <4 x i32> zeroinitializer @@ -310,9 +310,9 @@ define <8 x double> @vfrsub_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i ; CHECK-LABEL: vfrsub_vf_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v28, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> undef, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> undef, <8 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll index e4158640a459cfceaca458169d7fc002242ed82e..b557e29fe1127e87aeddd8ff434826bd4ddbfdcb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll @@ -32,9 +32,9 @@ define <2 x half> @vfsub_vf_v2f16(<2 x half> %va, half %b, <2 x i1> %m, i32 zero ; CHECK-LABEL: vfsub_vf_v2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> undef, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> undef, <2 x i32> zeroinitializer @@ -96,9 +96,9 @@ define <4 x half> @vfsub_vf_v4f16(<4 x half> %va, half %b, <4 x i1> %m, i32 zero ; CHECK-LABEL: vfsub_vf_v4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> undef, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> undef, <4 x i32> zeroinitializer @@ -148,9 +148,9 @@ define <8 x half> @vfsub_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zero ; CHECK-LABEL: vfsub_vf_v8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> undef, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> undef, <8 x i32> zeroinitializer @@ -200,9 +200,9 @@ define <16 x half> @vfsub_vf_v16f16(<16 x half> %va, half %b, <16 x i1> %m, i32 ; CHECK-LABEL: vfsub_vf_v16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> undef, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> undef, <16 x i32> zeroinitializer @@ -252,9 +252,9 @@ define <2 x float> @vfsub_vf_v2f32(<2 x float> %va, float %b, <2 x i1> %m, i32 z ; CHECK-LABEL: vfsub_vf_v2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> undef, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> undef, <2 x i32> zeroinitializer @@ -304,9 +304,9 @@ define <4 x float> @vfsub_vf_v4f32(<4 x float> %va, float %b, <4 x i1> %m, i32 z ; CHECK-LABEL: vfsub_vf_v4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> undef, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> undef, <4 x i32> zeroinitializer @@ -356,9 +356,9 @@ define <8 x float> @vfsub_vf_v8f32(<8 x float> %va, float %b, <8 x i1> %m, i32 z ; CHECK-LABEL: vfsub_vf_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> undef, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> undef, <8 x i32> zeroinitializer @@ -408,9 +408,9 @@ define <16 x float> @vfsub_vf_v16f32(<16 x float> %va, float %b, <16 x i1> %m, i ; CHECK-LABEL: vfsub_vf_v16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> undef, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> undef, <16 x i32> zeroinitializer @@ -460,9 +460,9 @@ define <2 x double> @vfsub_vf_v2f64(<2 x double> %va, double %b, <2 x i1> %m, i3 ; CHECK-LABEL: vfsub_vf_v2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> undef, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> undef, <2 x i32> zeroinitializer @@ -512,9 +512,9 @@ define <4 x double> @vfsub_vf_v4f64(<4 x double> %va, double %b, <4 x i1> %m, i3 ; CHECK-LABEL: vfsub_vf_v4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> undef, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> undef, <4 x i32> zeroinitializer @@ -564,9 +564,9 @@ define <8 x double> @vfsub_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i3 ; CHECK-LABEL: vfsub_vf_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> undef, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> undef, <8 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll index 41f03d22a7be3a289c45391013468a746fd0aebe..6907f6ae616888bfe98fab69fc07157808d77492 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll @@ -699,9 +699,9 @@ define <2 x i64> @vmul_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vmul.vv v8, v8, v25, v0.t +; RV32-NEXT: vmul.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -725,9 +725,9 @@ define <2 x i64> @vmul_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vmul.vv v8, v8, v25 +; RV32-NEXT: vmul.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -777,9 +777,9 @@ define <4 x i64> @vmul_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vmul.vv v8, v8, v26, v0.t +; RV32-NEXT: vmul.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -803,9 +803,9 @@ define <4 x i64> @vmul_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vmul.vv v8, v8, v26 +; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -855,9 +855,9 @@ define <8 x i64> @vmul_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vmul.vv v8, v8, v28, v0.t +; RV32-NEXT: vmul.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -881,9 +881,9 @@ define <8 x i64> @vmul_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vmul.vv v8, v8, v28 +; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll index e3877ce088adaae00db379af6c2115732d388c55..f623f11a56e2046fb98223d99a6d6da08fa8ab27 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll @@ -1037,9 +1037,9 @@ define <2 x i64> @vor_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vor.vv v8, v8, v25, v0.t +; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1063,9 +1063,9 @@ define <2 x i64> @vor_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vor.vv v8, v8, v25 +; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1141,9 +1141,9 @@ define <4 x i64> @vor_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vor.vv v8, v8, v26, v0.t +; RV32-NEXT: vor.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1167,9 +1167,9 @@ define <4 x i64> @vor_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vor.vv v8, v8, v26 +; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1245,9 +1245,9 @@ define <8 x i64> @vor_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vor.vv v8, v8, v28, v0.t +; RV32-NEXT: vor.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1271,9 +1271,9 @@ define <8 x i64> @vor_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vor.vv v8, v8, v28 +; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll index d19f2aa1e3d8d12734f1645bcce9d9fee2ea0d8e..f9a12282f423068311762060680521dcc49afb73 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll @@ -10,15 +10,15 @@ define <2 x i8> @vpgather_v2i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vpgather_v2i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t +; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 %evl) ret <2 x i8> %v @@ -28,17 +28,17 @@ define <2 x i16> @vpgather_v2i8_sextload_v2i16(<2 x i8*> %ptrs, <2 x i1> %m, i32 ; RV32-LABEL: vpgather_v2i8_sextload_v2i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV32-NEXT: vsext.vf2 v8, v25 +; RV32-NEXT: vsext.vf2 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2i8_sextload_v2i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV64-NEXT: vsext.vf2 v8, v25 +; RV64-NEXT: vsext.vf2 v8, v9 ; RV64-NEXT: ret %v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 %evl) %ev = sext <2 x i8> %v to <2 x i16> @@ -49,17 +49,17 @@ define <2 x i16> @vpgather_v2i8_zextload_v2i16(<2 x i8*> %ptrs, <2 x i1> %m, i32 ; RV32-LABEL: vpgather_v2i8_zextload_v2i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV32-NEXT: vzext.vf2 v8, v25 +; RV32-NEXT: vzext.vf2 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2i8_zextload_v2i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV64-NEXT: vzext.vf2 v8, v25 +; RV64-NEXT: vzext.vf2 v8, v9 ; RV64-NEXT: ret %v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 %evl) %ev = zext <2 x i8> %v to <2 x i16> @@ -70,17 +70,17 @@ define <2 x i32> @vpgather_v2i8_sextload_v2i32(<2 x i8*> %ptrs, <2 x i1> %m, i32 ; RV32-LABEL: vpgather_v2i8_sextload_v2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vsext.vf4 v8, v25 +; RV32-NEXT: vsext.vf4 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2i8_sextload_v2i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vsext.vf4 v8, v25 +; RV64-NEXT: vsext.vf4 v8, v9 ; RV64-NEXT: ret %v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 %evl) %ev = sext <2 x i8> %v to <2 x i32> @@ -91,17 +91,17 @@ define <2 x i32> @vpgather_v2i8_zextload_v2i32(<2 x i8*> %ptrs, <2 x i1> %m, i32 ; RV32-LABEL: vpgather_v2i8_zextload_v2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vzext.vf4 v8, v25 +; RV32-NEXT: vzext.vf4 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2i8_zextload_v2i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vzext.vf4 v8, v25 +; RV64-NEXT: vzext.vf4 v8, v9 ; RV64-NEXT: ret %v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 %evl) %ev = zext <2 x i8> %v to <2 x i32> @@ -112,17 +112,17 @@ define <2 x i64> @vpgather_v2i8_sextload_v2i64(<2 x i8*> %ptrs, <2 x i1> %m, i32 ; RV32-LABEL: vpgather_v2i8_sextload_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vsext.vf8 v8, v25 +; RV32-NEXT: vsext.vf8 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2i8_sextload_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vsext.vf8 v8, v25 +; RV64-NEXT: vsext.vf8 v8, v9 ; RV64-NEXT: ret %v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 %evl) %ev = sext <2 x i8> %v to <2 x i64> @@ -133,17 +133,17 @@ define <2 x i64> @vpgather_v2i8_zextload_v2i64(<2 x i8*> %ptrs, <2 x i1> %m, i32 ; RV32-LABEL: vpgather_v2i8_zextload_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vzext.vf8 v8, v25 +; RV32-NEXT: vzext.vf8 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2i8_zextload_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vzext.vf8 v8, v25 +; RV64-NEXT: vzext.vf8 v8, v9 ; RV64-NEXT: ret %v = call <2 x i8> @llvm.vp.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, <2 x i1> %m, i32 %evl) %ev = zext <2 x i8> %v to <2 x i64> @@ -156,15 +156,15 @@ define <4 x i8> @vpgather_v4i8(<4 x i8*> %ptrs, <4 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vpgather_v4i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v4i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %v = call <4 x i8> @llvm.vp.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, <4 x i1> %m, i32 %evl) ret <4 x i8> %v @@ -174,15 +174,15 @@ define <4 x i8> @vpgather_truemask_v4i8(<4 x i8*> %ptrs, i32 zeroext %evl) { ; RV32-LABEL: vpgather_truemask_v4i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v9, (zero), v8 +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_truemask_v4i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v10, (zero), v8 +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -196,15 +196,15 @@ define <8 x i8> @vpgather_v8i8(<8 x i8*> %ptrs, <8 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vpgather_v8i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t +; RV32-NEXT: vmv1r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v8i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t +; RV64-NEXT: vmv1r.v v8, v12 ; RV64-NEXT: ret %v = call <8 x i8> @llvm.vp.gather.v8i8.v8p0i8(<8 x i8*> %ptrs, <8 x i1> %m, i32 %evl) ret <8 x i8> %v @@ -214,17 +214,17 @@ define <8 x i8> @vpgather_baseidx_v8i8(i8* %base, <8 x i8> %idxs, <8 x i1> %m, i ; RV32-LABEL: vpgather_baseidx_v8i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 +; RV32-NEXT: vsext.vf4 v10, v8 ; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 +; RV64-NEXT: vsext.vf8 v12, v8 ; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i8, i8* %base, <8 x i8> %idxs %v = call <8 x i8> @llvm.vp.gather.v8i8.v8p0i8(<8 x i8*> %ptrs, <8 x i1> %m, i32 %evl) @@ -237,15 +237,15 @@ define <2 x i16> @vpgather_v2i16(<2 x i16*> %ptrs, <2 x i1> %m, i32 zeroext %evl ; RV32-LABEL: vpgather_v2i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t +; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, <2 x i1> %m, i32 %evl) ret <2 x i16> %v @@ -255,17 +255,17 @@ define <2 x i32> @vpgather_v2i16_sextload_v2i32(<2 x i16*> %ptrs, <2 x i1> %m, i ; RV32-LABEL: vpgather_v2i16_sextload_v2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vsext.vf2 v8, v25 +; RV32-NEXT: vsext.vf2 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2i16_sextload_v2i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vsext.vf2 v8, v25 +; RV64-NEXT: vsext.vf2 v8, v9 ; RV64-NEXT: ret %v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, <2 x i1> %m, i32 %evl) %ev = sext <2 x i16> %v to <2 x i32> @@ -276,17 +276,17 @@ define <2 x i32> @vpgather_v2i16_zextload_v2i32(<2 x i16*> %ptrs, <2 x i1> %m, i ; RV32-LABEL: vpgather_v2i16_zextload_v2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vzext.vf2 v8, v25 +; RV32-NEXT: vzext.vf2 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2i16_zextload_v2i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vzext.vf2 v8, v25 +; RV64-NEXT: vzext.vf2 v8, v9 ; RV64-NEXT: ret %v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, <2 x i1> %m, i32 %evl) %ev = zext <2 x i16> %v to <2 x i32> @@ -297,17 +297,17 @@ define <2 x i64> @vpgather_v2i16_sextload_v2i64(<2 x i16*> %ptrs, <2 x i1> %m, i ; RV32-LABEL: vpgather_v2i16_sextload_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vsext.vf4 v8, v25 +; RV32-NEXT: vsext.vf4 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2i16_sextload_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vsext.vf4 v8, v25 +; RV64-NEXT: vsext.vf4 v8, v9 ; RV64-NEXT: ret %v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, <2 x i1> %m, i32 %evl) %ev = sext <2 x i16> %v to <2 x i64> @@ -318,17 +318,17 @@ define <2 x i64> @vpgather_v2i16_zextload_v2i64(<2 x i16*> %ptrs, <2 x i1> %m, i ; RV32-LABEL: vpgather_v2i16_zextload_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vzext.vf4 v8, v25 +; RV32-NEXT: vzext.vf4 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2i16_zextload_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vzext.vf4 v8, v25 +; RV64-NEXT: vzext.vf4 v8, v9 ; RV64-NEXT: ret %v = call <2 x i16> @llvm.vp.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, <2 x i1> %m, i32 %evl) %ev = zext <2 x i16> %v to <2 x i64> @@ -341,15 +341,15 @@ define <4 x i16> @vpgather_v4i16(<4 x i16*> %ptrs, <4 x i1> %m, i32 zeroext %evl ; RV32-LABEL: vpgather_v4i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v4i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %v = call <4 x i16> @llvm.vp.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, <4 x i1> %m, i32 %evl) ret <4 x i16> %v @@ -359,15 +359,15 @@ define <4 x i16> @vpgather_truemask_v4i16(<4 x i16*> %ptrs, i32 zeroext %evl) { ; RV32-LABEL: vpgather_truemask_v4i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v9, (zero), v8 +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_truemask_v4i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v10, (zero), v8 +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -381,15 +381,15 @@ define <8 x i16> @vpgather_v8i16(<8 x i16*> %ptrs, <8 x i1> %m, i32 zeroext %evl ; RV32-LABEL: vpgather_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t +; RV32-NEXT: vmv1r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t +; RV64-NEXT: vmv1r.v v8, v12 ; RV64-NEXT: ret %v = call <8 x i16> @llvm.vp.gather.v8i16.v8p0i16(<8 x i16*> %ptrs, <8 x i1> %m, i32 %evl) ret <8 x i16> %v @@ -399,19 +399,19 @@ define <8 x i16> @vpgather_baseidx_v8i8_v8i16(i16* %base, <8 x i8> %idxs, <8 x i ; RV32-LABEL: vpgather_baseidx_v8i8_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8i8_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i16, i16* %base, <8 x i8> %idxs %v = call <8 x i16> @llvm.vp.gather.v8i16.v8p0i16(<8 x i16*> %ptrs, <8 x i1> %m, i32 %evl) @@ -422,19 +422,19 @@ define <8 x i16> @vpgather_baseidx_sext_v8i8_v8i16(i16* %base, <8 x i8> %idxs, < ; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs @@ -446,19 +446,19 @@ define <8 x i16> @vpgather_baseidx_zext_v8i8_v8i16(i16* %base, <8 x i8> %idxs, < ; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vzext.vf4 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vzext.vf8 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs @@ -470,19 +470,19 @@ define <8 x i16> @vpgather_baseidx_v8i16(i16* %base, <8 x i16> %idxs, <8 x i1> % ; RV32-LABEL: vpgather_baseidx_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %idxs %v = call <8 x i16> @llvm.vp.gather.v8i16.v8p0i16(<8 x i16*> %ptrs, <8 x i1> %m, i32 %evl) @@ -501,8 +501,8 @@ define <2 x i32> @vpgather_v2i32(<2 x i32*> %ptrs, <2 x i1> %m, i32 zeroext %evl ; RV64-LABEL: vpgather_v2i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t +; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %v = call <2 x i32> @llvm.vp.gather.v2i32.v2p0i32(<2 x i32*> %ptrs, <2 x i1> %m, i32 %evl) ret <2 x i32> %v @@ -512,17 +512,17 @@ define <2 x i64> @vpgather_v2i32_sextload_v2i64(<2 x i32*> %ptrs, <2 x i1> %m, i ; RV32-LABEL: vpgather_v2i32_sextload_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vsext.vf2 v8, v25 +; RV32-NEXT: vsext.vf2 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2i32_sextload_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vsext.vf2 v8, v25 +; RV64-NEXT: vsext.vf2 v8, v9 ; RV64-NEXT: ret %v = call <2 x i32> @llvm.vp.gather.v2i32.v2p0i32(<2 x i32*> %ptrs, <2 x i1> %m, i32 %evl) %ev = sext <2 x i32> %v to <2 x i64> @@ -533,17 +533,17 @@ define <2 x i64> @vpgather_v2i32_zextload_v2i64(<2 x i32*> %ptrs, <2 x i1> %m, i ; RV32-LABEL: vpgather_v2i32_zextload_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vzext.vf2 v8, v25 +; RV32-NEXT: vzext.vf2 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2i32_zextload_v2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vzext.vf2 v8, v25 +; RV64-NEXT: vzext.vf2 v8, v9 ; RV64-NEXT: ret %v = call <2 x i32> @llvm.vp.gather.v2i32.v2p0i32(<2 x i32*> %ptrs, <2 x i1> %m, i32 %evl) %ev = zext <2 x i32> %v to <2 x i64> @@ -562,8 +562,8 @@ define <4 x i32> @vpgather_v4i32(<4 x i32*> %ptrs, <4 x i1> %m, i32 zeroext %evl ; RV64-LABEL: vpgather_v4i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %v = call <4 x i32> @llvm.vp.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, <4 x i1> %m, i32 %evl) ret <4 x i32> %v @@ -579,8 +579,8 @@ define <4 x i32> @vpgather_truemask_v4i32(<4 x i32*> %ptrs, i32 zeroext %evl) { ; RV64-LABEL: vpgather_truemask_v4i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v10, (zero), v8 +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -600,8 +600,8 @@ define <8 x i32> @vpgather_v8i32(<8 x i32*> %ptrs, <8 x i1> %m, i32 zeroext %evl ; RV64-LABEL: vpgather_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v26, (zero), v8, v0.t -; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t +; RV64-NEXT: vmv2r.v v8, v12 ; RV64-NEXT: ret %v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0i32(<8 x i32*> %ptrs, <8 x i1> %m, i32 %evl) ret <8 x i32> %v @@ -611,19 +611,19 @@ define <8 x i32> @vpgather_baseidx_v8i8_v8i32(i32* %base, <8 x i8> %idxs, <8 x i ; RV32-LABEL: vpgather_baseidx_v8i8_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8i8_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i8> %idxs %v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0i32(<8 x i32*> %ptrs, <8 x i1> %m, i32 %evl) @@ -634,19 +634,19 @@ define <8 x i32> @vpgather_baseidx_sext_v8i8_v8i32(i32* %base, <8 x i8> %idxs, < ; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -658,19 +658,19 @@ define <8 x i32> @vpgather_baseidx_zext_v8i8_v8i32(i32* %base, <8 x i8> %idxs, < ; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vzext.vf4 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -682,19 +682,19 @@ define <8 x i32> @vpgather_baseidx_v8i16_v8i32(i32* %base, <8 x i16> %idxs, <8 x ; RV32-LABEL: vpgather_baseidx_v8i16_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8i16_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i16> %idxs %v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0i32(<8 x i32*> %ptrs, <8 x i1> %m, i32 %evl) @@ -705,19 +705,19 @@ define <8 x i32> @vpgather_baseidx_sext_v8i16_v8i32(i32* %base, <8 x i16> %idxs, ; RV32-LABEL: vpgather_baseidx_sext_v8i16_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_sext_v8i16_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -729,19 +729,19 @@ define <8 x i32> @vpgather_baseidx_zext_v8i16_v8i32(i32* %base, <8 x i16> %idxs, ; RV32-LABEL: vpgather_baseidx_zext_v8i16_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vzext.vf2 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_zext_v8i16_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -753,18 +753,18 @@ define <8 x i32> @vpgather_baseidx_v8i32(i32* %base, <8 x i32> %idxs, <8 x i1> % ; RV32-LABEL: vpgather_baseidx_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v8, 2 +; RV32-NEXT: vsll.vi v8, v8, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf2 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %idxs %v = call <8 x i32> @llvm.vp.gather.v8i32.v8p0i32(<8 x i32*> %ptrs, <8 x i1> %m, i32 %evl) @@ -777,8 +777,8 @@ define <2 x i64> @vpgather_v2i64(<2 x i64*> %ptrs, <2 x i1> %m, i32 zeroext %evl ; RV32-LABEL: vpgather_v2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2i64: @@ -796,8 +796,8 @@ define <4 x i64> @vpgather_v4i64(<4 x i64*> %ptrs, <4 x i1> %m, i32 zeroext %evl ; RV32-LABEL: vpgather_v4i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; RV32-NEXT: vluxei32.v v26, (zero), v8, v0.t -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v4i64: @@ -813,8 +813,8 @@ define <4 x i64> @vpgather_truemask_v4i64(<4 x i64*> %ptrs, i32 zeroext %evl) { ; RV32-LABEL: vpgather_truemask_v4i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; RV32-NEXT: vluxei32.v v26, (zero), v8 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vluxei32.v v10, (zero), v8 +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_truemask_v4i64: @@ -834,8 +834,8 @@ define <8 x i64> @vpgather_v8i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 zeroext %evl ; RV32-LABEL: vpgather_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v28, (zero), v8, v0.t -; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: vluxei32.v v12, (zero), v8, v0.t +; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v8i64: @@ -851,19 +851,19 @@ define <8 x i64> @vpgather_baseidx_v8i8_v8i64(i64* %base, <8 x i8> %idxs, <8 x i ; RV32-LABEL: vpgather_baseidx_v8i8_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vsll.vi v12, v10, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8i8_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i8> %idxs %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -874,10 +874,10 @@ define <8 x i64> @vpgather_baseidx_sext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, < ; CHECK-LABEL: vpgather_baseidx_sext_v8i8_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v28, v8 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vsext.vf8 v12, v8 +; CHECK-NEXT: vsll.vi v8, v12, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t ; CHECK-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -889,10 +889,10 @@ define <8 x i64> @vpgather_baseidx_zext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, < ; CHECK-LABEL: vpgather_baseidx_zext_v8i8_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v28, v8 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vzext.vf8 v12, v8 +; CHECK-NEXT: vsll.vi v8, v12, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t ; CHECK-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -904,19 +904,19 @@ define <8 x i64> @vpgather_baseidx_v8i16_v8i64(i64* %base, <8 x i16> %idxs, <8 x ; RV32-LABEL: vpgather_baseidx_v8i16_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vsll.vi v12, v10, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8i16_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i16> %idxs %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -927,10 +927,10 @@ define <8 x i64> @vpgather_baseidx_sext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, ; CHECK-LABEL: vpgather_baseidx_sext_v8i16_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v8 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vsll.vi v8, v12, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t ; CHECK-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -942,10 +942,10 @@ define <8 x i64> @vpgather_baseidx_zext_v8i16_v8i64(i64* %base, <8 x i16> %idxs, ; CHECK-LABEL: vpgather_baseidx_zext_v8i16_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v8 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vsll.vi v8, v12, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t ; CHECK-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -957,18 +957,18 @@ define <8 x i64> @vpgather_baseidx_v8i32_v8i64(i64* %base, <8 x i32> %idxs, <8 x ; RV32-LABEL: vpgather_baseidx_v8i32_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v8, 3 +; RV32-NEXT: vsll.vi v12, v8, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8i32_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 +; RV64-NEXT: vsext.vf2 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i32> %idxs %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -979,10 +979,10 @@ define <8 x i64> @vpgather_baseidx_sext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, ; CHECK-LABEL: vpgather_baseidx_sext_v8i32_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vsll.vi v8, v12, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t ; CHECK-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -994,10 +994,10 @@ define <8 x i64> @vpgather_baseidx_zext_v8i32_v8i64(i64* %base, <8 x i32> %idxs, ; CHECK-LABEL: vpgather_baseidx_zext_v8i32_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vsll.vi v8, v12, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t ; CHECK-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -1009,9 +1009,9 @@ define <8 x i64> @vpgather_baseidx_v8i64(i64* %base, <8 x i64> %idxs, <8 x i1> % ; CHECK-LABEL: vpgather_baseidx_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsll.vi v28, v8, 3 +; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t ; CHECK-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %idxs %v = call <8 x i64> @llvm.vp.gather.v8i64.v8p0i64(<8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1024,15 +1024,15 @@ define <2 x half> @vpgather_v2f16(<2 x half*> %ptrs, <2 x i1> %m, i32 zeroext %e ; RV32-LABEL: vpgather_v2f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t +; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %v = call <2 x half> @llvm.vp.gather.v2f16.v2p0f16(<2 x half*> %ptrs, <2 x i1> %m, i32 %evl) ret <2 x half> %v @@ -1044,15 +1044,15 @@ define <4 x half> @vpgather_v4f16(<4 x half*> %ptrs, <4 x i1> %m, i32 zeroext %e ; RV32-LABEL: vpgather_v4f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v4f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %v = call <4 x half> @llvm.vp.gather.v4f16.v4p0f16(<4 x half*> %ptrs, <4 x i1> %m, i32 %evl) ret <4 x half> %v @@ -1062,15 +1062,15 @@ define <4 x half> @vpgather_truemask_v4f16(<4 x half*> %ptrs, i32 zeroext %evl) ; RV32-LABEL: vpgather_truemask_v4f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v9, (zero), v8 +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_truemask_v4f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v10, (zero), v8 +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -1084,15 +1084,15 @@ define <8 x half> @vpgather_v8f16(<8 x half*> %ptrs, <8 x i1> %m, i32 zeroext %e ; RV32-LABEL: vpgather_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t +; RV32-NEXT: vmv1r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t +; RV64-NEXT: vmv1r.v v8, v12 ; RV64-NEXT: ret %v = call <8 x half> @llvm.vp.gather.v8f16.v8p0f16(<8 x half*> %ptrs, <8 x i1> %m, i32 %evl) ret <8 x half> %v @@ -1102,19 +1102,19 @@ define <8 x half> @vpgather_baseidx_v8i8_v8f16(half* %base, <8 x i8> %idxs, <8 x ; RV32-LABEL: vpgather_baseidx_v8i8_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8i8_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds half, half* %base, <8 x i8> %idxs %v = call <8 x half> @llvm.vp.gather.v8f16.v8p0f16(<8 x half*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1125,19 +1125,19 @@ define <8 x half> @vpgather_baseidx_sext_v8i8_v8f16(half* %base, <8 x i8> %idxs, ; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs @@ -1149,19 +1149,19 @@ define <8 x half> @vpgather_baseidx_zext_v8i8_v8f16(half* %base, <8 x i8> %idxs, ; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vzext.vf4 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vzext.vf8 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs @@ -1173,19 +1173,19 @@ define <8 x half> @vpgather_baseidx_v8f16(half* %base, <8 x i16> %idxs, <8 x i1> ; RV32-LABEL: vpgather_baseidx_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %idxs %v = call <8 x half> @llvm.vp.gather.v8f16.v8p0f16(<8 x half*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1204,8 +1204,8 @@ define <2 x float> @vpgather_v2f32(<2 x float*> %ptrs, <2 x i1> %m, i32 zeroext ; RV64-LABEL: vpgather_v2f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v9, (zero), v8, v0.t +; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %v = call <2 x float> @llvm.vp.gather.v2f32.v2p0f32(<2 x float*> %ptrs, <2 x i1> %m, i32 %evl) ret <2 x float> %v @@ -1223,8 +1223,8 @@ define <4 x float> @vpgather_v4f32(<4 x float*> %ptrs, <4 x i1> %m, i32 zeroext ; RV64-LABEL: vpgather_v4f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %v = call <4 x float> @llvm.vp.gather.v4f32.v4p0f32(<4 x float*> %ptrs, <4 x i1> %m, i32 %evl) ret <4 x float> %v @@ -1240,8 +1240,8 @@ define <4 x float> @vpgather_truemask_v4f32(<4 x float*> %ptrs, i32 zeroext %evl ; RV64-LABEL: vpgather_truemask_v4f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v10, (zero), v8 +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %mhead = insertelement <4 x i1> undef, i1 1, i32 0 %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> undef, <4 x i32> zeroinitializer @@ -1261,8 +1261,8 @@ define <8 x float> @vpgather_v8f32(<8 x float*> %ptrs, <8 x i1> %m, i32 zeroext ; RV64-LABEL: vpgather_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v26, (zero), v8, v0.t -; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: vluxei64.v v12, (zero), v8, v0.t +; RV64-NEXT: vmv2r.v v8, v12 ; RV64-NEXT: ret %v = call <8 x float> @llvm.vp.gather.v8f32.v8p0f32(<8 x float*> %ptrs, <8 x i1> %m, i32 %evl) ret <8 x float> %v @@ -1272,19 +1272,19 @@ define <8 x float> @vpgather_baseidx_v8i8_v8f32(float* %base, <8 x i8> %idxs, <8 ; RV32-LABEL: vpgather_baseidx_v8i8_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8i8_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i8> %idxs %v = call <8 x float> @llvm.vp.gather.v8f32.v8p0f32(<8 x float*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1295,19 +1295,19 @@ define <8 x float> @vpgather_baseidx_sext_v8i8_v8f32(float* %base, <8 x i8> %idx ; RV32-LABEL: vpgather_baseidx_sext_v8i8_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_sext_v8i8_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1319,19 +1319,19 @@ define <8 x float> @vpgather_baseidx_zext_v8i8_v8f32(float* %base, <8 x i8> %idx ; RV32-LABEL: vpgather_baseidx_zext_v8i8_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vzext.vf4 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_zext_v8i8_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1343,19 +1343,19 @@ define <8 x float> @vpgather_baseidx_v8i16_v8f32(float* %base, <8 x i16> %idxs, ; RV32-LABEL: vpgather_baseidx_v8i16_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8i16_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i16> %idxs %v = call <8 x float> @llvm.vp.gather.v8f32.v8p0f32(<8 x float*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1366,19 +1366,19 @@ define <8 x float> @vpgather_baseidx_sext_v8i16_v8f32(float* %base, <8 x i16> %i ; RV32-LABEL: vpgather_baseidx_sext_v8i16_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_sext_v8i16_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1390,19 +1390,19 @@ define <8 x float> @vpgather_baseidx_zext_v8i16_v8f32(float* %base, <8 x i16> %i ; RV32-LABEL: vpgather_baseidx_zext_v8i16_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vzext.vf2 v10, v8 +; RV32-NEXT: vsll.vi v8, v10, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_zext_v8i16_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1414,18 +1414,18 @@ define <8 x float> @vpgather_baseidx_v8f32(float* %base, <8 x i32> %idxs, <8 x i ; RV32-LABEL: vpgather_baseidx_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v8, 2 +; RV32-NEXT: vsll.vi v8, v8, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf2 v12, v8 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %idxs %v = call <8 x float> @llvm.vp.gather.v8f32.v8p0f32(<8 x float*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1438,8 +1438,8 @@ define <2 x double> @vpgather_v2f64(<2 x double*> %ptrs, <2 x i1> %m, i32 zeroex ; RV32-LABEL: vpgather_v2f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v2f64: @@ -1457,8 +1457,8 @@ define <4 x double> @vpgather_v4f64(<4 x double*> %ptrs, <4 x i1> %m, i32 zeroex ; RV32-LABEL: vpgather_v4f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; RV32-NEXT: vluxei32.v v26, (zero), v8, v0.t -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v4f64: @@ -1474,8 +1474,8 @@ define <4 x double> @vpgather_truemask_v4f64(<4 x double*> %ptrs, i32 zeroext %e ; RV32-LABEL: vpgather_truemask_v4f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; RV32-NEXT: vluxei32.v v26, (zero), v8 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vluxei32.v v10, (zero), v8 +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_truemask_v4f64: @@ -1495,8 +1495,8 @@ define <8 x double> @vpgather_v8f64(<8 x double*> %ptrs, <8 x i1> %m, i32 zeroex ; RV32-LABEL: vpgather_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v28, (zero), v8, v0.t -; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: vluxei32.v v12, (zero), v8, v0.t +; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_v8f64: @@ -1512,19 +1512,19 @@ define <8 x double> @vpgather_baseidx_v8i8_v8f64(double* %base, <8 x i8> %idxs, ; RV32-LABEL: vpgather_baseidx_v8i8_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf4 v10, v8 +; RV32-NEXT: vsll.vi v12, v10, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8i8_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 +; RV64-NEXT: vsext.vf8 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i8> %idxs %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1535,10 +1535,10 @@ define <8 x double> @vpgather_baseidx_sext_v8i8_v8f64(double* %base, <8 x i8> %i ; CHECK-LABEL: vpgather_baseidx_sext_v8i8_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v28, v8 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vsext.vf8 v12, v8 +; CHECK-NEXT: vsll.vi v8, v12, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t ; CHECK-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1550,10 +1550,10 @@ define <8 x double> @vpgather_baseidx_zext_v8i8_v8f64(double* %base, <8 x i8> %i ; CHECK-LABEL: vpgather_baseidx_zext_v8i8_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v28, v8 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vzext.vf8 v12, v8 +; CHECK-NEXT: vsll.vi v8, v12, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t ; CHECK-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1565,19 +1565,19 @@ define <8 x double> @vpgather_baseidx_v8i16_v8f64(double* %base, <8 x i16> %idxs ; RV32-LABEL: vpgather_baseidx_v8i16_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v8 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vsll.vi v12, v10, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8i16_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 +; RV64-NEXT: vsext.vf4 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i16> %idxs %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1588,10 +1588,10 @@ define <8 x double> @vpgather_baseidx_sext_v8i16_v8f64(double* %base, <8 x i16> ; CHECK-LABEL: vpgather_baseidx_sext_v8i16_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v8 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vsll.vi v8, v12, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t ; CHECK-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1603,10 +1603,10 @@ define <8 x double> @vpgather_baseidx_zext_v8i16_v8f64(double* %base, <8 x i16> ; CHECK-LABEL: vpgather_baseidx_zext_v8i16_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v8 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vsll.vi v8, v12, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t ; CHECK-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1618,18 +1618,18 @@ define <8 x double> @vpgather_baseidx_v8i32_v8f64(double* %base, <8 x i32> %idxs ; RV32-LABEL: vpgather_baseidx_v8i32_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v8, 3 +; RV32-NEXT: vsll.vi v12, v8, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_v8i32_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v8 -; RV64-NEXT: vsll.vi v28, v28, 3 +; RV64-NEXT: vsext.vf2 v12, v8 +; RV64-NEXT: vsll.vi v8, v12, 3 ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV64-NEXT: vluxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i32> %idxs %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1640,10 +1640,10 @@ define <8 x double> @vpgather_baseidx_sext_v8i32_v8f64(double* %base, <8 x i32> ; CHECK-LABEL: vpgather_baseidx_sext_v8i32_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vsll.vi v8, v12, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t ; CHECK-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1655,10 +1655,10 @@ define <8 x double> @vpgather_baseidx_zext_v8i32_v8f64(double* %base, <8 x i32> ; CHECK-LABEL: vpgather_baseidx_zext_v8i32_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vsll.vi v8, v12, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t ; CHECK-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1670,9 +1670,9 @@ define <8 x double> @vpgather_baseidx_v8f64(double* %base, <8 x i64> %idxs, <8 x ; CHECK-LABEL: vpgather_baseidx_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsll.vi v28, v8, 3 +; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vluxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vluxei64.v v8, (a0), v8, v0.t ; CHECK-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %idxs %v = call <8 x double> @llvm.vp.gather.v8f64.v8p0f64(<8 x double*> %ptrs, <8 x i1> %m, i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll index 1a4ffa0fb62ef888d719e8c43b66bcbc6fc5c3e4..52887d7a88d57a16a26d1bae121d1664d96cc25a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll @@ -26,17 +26,17 @@ define void @vpscatter_v2i16_truncstore_v2i8(<2 x i16> %val, <2 x i8*> %ptrs, <2 ; RV32-LABEL: vpscatter_v2i16_truncstore_v2i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV32-NEXT: vnsrl.wi v25, v8, 0 +; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_v2i16_truncstore_v2i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; RV64-NEXT: vnsrl.wi v25, v8, 0 +; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: ret %tval = trunc <2 x i16> %val to <2 x i8> call void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, <2 x i1> %m, i32 %evl) @@ -47,21 +47,21 @@ define void @vpscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x i8*> %ptrs, <2 ; RV32-LABEL: vpscatter_v2i32_truncstore_v2i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV32-NEXT: vnsrl.wi v25, v8, 0 +; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; RV32-NEXT: vnsrl.wi v25, v25, 0 +; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_v2i32_truncstore_v2i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV64-NEXT: vnsrl.wi v25, v8, 0 +; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; RV64-NEXT: vnsrl.wi v25, v25, 0 +; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: ret %tval = trunc <2 x i32> %val to <2 x i8> call void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, <2 x i1> %m, i32 %evl) @@ -72,25 +72,25 @@ define void @vpscatter_v2i64_truncstore_v2i8(<2 x i64> %val, <2 x i8*> %ptrs, <2 ; RV32-LABEL: vpscatter_v2i64_truncstore_v2i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vnsrl.wi v25, v8, 0 +; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; RV32-NEXT: vnsrl.wi v25, v25, 0 +; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; RV32-NEXT: vnsrl.wi v25, v25, 0 +; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_v2i64_truncstore_v2i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vnsrl.wi v25, v8, 0 +; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; RV64-NEXT: vnsrl.wi v25, v25, 0 +; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; RV64-NEXT: vnsrl.wi v25, v25, 0 +; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: ret %tval = trunc <2 x i64> %val to <2 x i8> call void @llvm.vp.scatter.v2i8.v2p0i8(<2 x i8> %tval, <2 x i8*> %ptrs, <2 x i1> %m, i32 %evl) @@ -155,17 +155,17 @@ define void @vpscatter_baseidx_v8i8(<8 x i8> %val, i8* %base, <8 x i8> %idxs, <8 ; RV32-LABEL: vpscatter_baseidx_v8i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v9 +; RV32-NEXT: vsext.vf4 v10, v9 ; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v9 +; RV64-NEXT: vsext.vf8 v12, v9 ; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i8, i8* %base, <8 x i8> %idxs call void @llvm.vp.scatter.v8i8.v8p0i8(<8 x i8> %val, <8 x i8*> %ptrs, <8 x i1> %m, i32 %evl) @@ -194,17 +194,17 @@ define void @vpscatter_v2i32_truncstore_v2i16(<2 x i32> %val, <2 x i16*> %ptrs, ; RV32-LABEL: vpscatter_v2i32_truncstore_v2i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV32-NEXT: vnsrl.wi v25, v8, 0 +; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_v2i32_truncstore_v2i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; RV64-NEXT: vnsrl.wi v25, v8, 0 +; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: ret %tval = trunc <2 x i32> %val to <2 x i16> call void @llvm.vp.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, <2 x i1> %m, i32 %evl) @@ -215,21 +215,21 @@ define void @vpscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x i16*> %ptrs, ; RV32-LABEL: vpscatter_v2i64_truncstore_v2i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vnsrl.wi v25, v8, 0 +; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; RV32-NEXT: vnsrl.wi v25, v25, 0 +; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_v2i64_truncstore_v2i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vnsrl.wi v25, v8, 0 +; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; RV64-NEXT: vnsrl.wi v25, v25, 0 +; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: ret %tval = trunc <2 x i64> %val to <2 x i16> call void @llvm.vp.scatter.v2i16.v2p0i16(<2 x i16> %tval, <2 x i16*> %ptrs, <2 x i1> %m, i32 %evl) @@ -294,19 +294,19 @@ define void @vpscatter_baseidx_v8i8_v8i16(<8 x i16> %val, i16* %base, <8 x i8> % ; RV32-LABEL: vpscatter_baseidx_v8i8_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8i8_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i16, i16* %base, <8 x i8> %idxs call void @llvm.vp.scatter.v8i16.v8p0i16(<8 x i16> %val, <8 x i16*> %ptrs, <8 x i1> %m, i32 %evl) @@ -317,19 +317,19 @@ define void @vpscatter_baseidx_sext_v8i8_v8i16(<8 x i16> %val, i16* %base, <8 x ; RV32-LABEL: vpscatter_baseidx_sext_v8i8_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_sext_v8i8_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs @@ -341,19 +341,19 @@ define void @vpscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, i16* %base, <8 x ; RV32-LABEL: vpscatter_baseidx_zext_v8i8_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vzext.vf4 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_zext_v8i8_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vzext.vf8 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs @@ -365,19 +365,19 @@ define void @vpscatter_baseidx_v8i16(<8 x i16> %val, i16* %base, <8 x i16> %idxs ; RV32-LABEL: vpscatter_baseidx_v8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf2 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf4 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %idxs call void @llvm.vp.scatter.v8i16.v8p0i16(<8 x i16> %val, <8 x i16*> %ptrs, <8 x i1> %m, i32 %evl) @@ -406,17 +406,17 @@ define void @vpscatter_v2i64_truncstore_v2i32(<2 x i64> %val, <2 x i32*> %ptrs, ; RV32-LABEL: vpscatter_v2i64_truncstore_v2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV32-NEXT: vnsrl.wi v25, v8, 0 +; RV32-NEXT: vnsrl.wi v8, v8, 0 ; RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t +; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_v2i64_truncstore_v2i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vnsrl.wi v25, v8, 0 +; RV64-NEXT: vnsrl.wi v8, v8, 0 ; RV64-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t +; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t ; RV64-NEXT: ret %tval = trunc <2 x i64> %val to <2 x i32> call void @llvm.vp.scatter.v2i32.v2p0i32(<2 x i32> %tval, <2 x i32*> %ptrs, <2 x i1> %m, i32 %evl) @@ -481,19 +481,19 @@ define void @vpscatter_baseidx_v8i8_v8i32(<8 x i32> %val, i32* %base, <8 x i8> % ; RV32-LABEL: vpscatter_baseidx_v8i8_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8i8_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i8> %idxs call void @llvm.vp.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, <8 x i1> %m, i32 %evl) @@ -504,19 +504,19 @@ define void @vpscatter_baseidx_sext_v8i8_v8i32(<8 x i32> %val, i32* %base, <8 x ; RV32-LABEL: vpscatter_baseidx_sext_v8i8_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_sext_v8i8_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -528,19 +528,19 @@ define void @vpscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, i32* %base, <8 x ; RV32-LABEL: vpscatter_baseidx_zext_v8i8_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vzext.vf4 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_zext_v8i8_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf8 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -552,19 +552,19 @@ define void @vpscatter_baseidx_v8i16_v8i32(<8 x i32> %val, i32* %base, <8 x i16> ; RV32-LABEL: vpscatter_baseidx_v8i16_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf2 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8i16_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i16> %idxs call void @llvm.vp.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, <8 x i1> %m, i32 %evl) @@ -575,19 +575,19 @@ define void @vpscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, i32* %base, <8 x ; RV32-LABEL: vpscatter_baseidx_sext_v8i16_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf2 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_sext_v8i16_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -599,19 +599,19 @@ define void @vpscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, i32* %base, <8 x ; RV32-LABEL: vpscatter_baseidx_zext_v8i16_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf2 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vzext.vf2 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_zext_v8i16_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf4 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf4 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %eidxs @@ -623,18 +623,18 @@ define void @vpscatter_baseidx_v8i32(<8 x i32> %val, i32* %base, <8 x i32> %idxs ; RV32-LABEL: vpscatter_baseidx_v8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v10, 2 +; RV32-NEXT: vsll.vi v10, v10, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf2 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i32, i32* %base, <8 x i32> %idxs call void @llvm.vp.scatter.v8i32.v8p0i32(<8 x i32> %val, <8 x i32*> %ptrs, <8 x i1> %m, i32 %evl) @@ -717,19 +717,19 @@ define void @vpscatter_baseidx_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x i8> % ; RV32-LABEL: vpscatter_baseidx_v8i8_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v12 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf4 v14, v12 +; RV32-NEXT: vsll.vi v12, v14, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8i8_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 +; RV64-NEXT: vsext.vf8 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i8> %idxs call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -740,10 +740,10 @@ define void @vpscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x ; CHECK-LABEL: vpscatter_baseidx_sext_v8i8_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v28, v12 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vsext.vf8 v16, v12 +; CHECK-NEXT: vsll.vi v12, v16, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -755,10 +755,10 @@ define void @vpscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, i64* %base, <8 x ; CHECK-LABEL: vpscatter_baseidx_zext_v8i8_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v28, v12 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vzext.vf8 v16, v12 +; CHECK-NEXT: vsll.vi v12, v16, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -770,19 +770,19 @@ define void @vpscatter_baseidx_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x i16> ; RV32-LABEL: vpscatter_baseidx_v8i16_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v12 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf2 v14, v12 +; RV32-NEXT: vsll.vi v12, v14, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8i16_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 +; RV64-NEXT: vsext.vf4 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i16> %idxs call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -793,10 +793,10 @@ define void @vpscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x ; CHECK-LABEL: vpscatter_baseidx_sext_v8i16_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v12 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vsext.vf4 v16, v12 +; CHECK-NEXT: vsll.vi v12, v16, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -808,10 +808,10 @@ define void @vpscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, i64* %base, <8 x ; CHECK-LABEL: vpscatter_baseidx_zext_v8i16_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v12 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vzext.vf4 v16, v12 +; CHECK-NEXT: vsll.vi v12, v16, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -823,18 +823,18 @@ define void @vpscatter_baseidx_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x i32> ; RV32-LABEL: vpscatter_baseidx_v8i32_v8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v12, 3 +; RV32-NEXT: vsll.vi v12, v12, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8i32_v8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 +; RV64-NEXT: vsext.vf2 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i32> %idxs call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -845,10 +845,10 @@ define void @vpscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x ; CHECK-LABEL: vpscatter_baseidx_sext_v8i32_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v12 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vsext.vf2 v16, v12 +; CHECK-NEXT: vsll.vi v12, v16, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -860,10 +860,10 @@ define void @vpscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, i64* %base, <8 x ; CHECK-LABEL: vpscatter_baseidx_zext_v8i32_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v12 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vzext.vf2 v16, v12 +; CHECK-NEXT: vsll.vi v12, v16, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %eidxs @@ -875,9 +875,9 @@ define void @vpscatter_baseidx_v8i64(<8 x i64> %val, i64* %base, <8 x i64> %idxs ; CHECK-LABEL: vpscatter_baseidx_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsll.vi v28, v12, 3 +; CHECK-NEXT: vsll.vi v12, v12, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret %ptrs = getelementptr inbounds i64, i64* %base, <8 x i64> %idxs call void @llvm.vp.scatter.v8i64.v8p0i64(<8 x i64> %val, <8 x i64*> %ptrs, <8 x i1> %m, i32 %evl) @@ -960,19 +960,19 @@ define void @vpscatter_baseidx_v8i8_v8f16(<8 x half> %val, half* %base, <8 x i8> ; RV32-LABEL: vpscatter_baseidx_v8i8_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8i8_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds half, half* %base, <8 x i8> %idxs call void @llvm.vp.scatter.v8f16.v8p0f16(<8 x half> %val, <8 x half*> %ptrs, <8 x i1> %m, i32 %evl) @@ -983,19 +983,19 @@ define void @vpscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, half* %base, <8 ; RV32-LABEL: vpscatter_baseidx_sext_v8i8_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf4 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_sext_v8i8_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf8 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs @@ -1007,19 +1007,19 @@ define void @vpscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, half* %base, <8 ; RV32-LABEL: vpscatter_baseidx_zext_v8i8_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vzext.vf4 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_zext_v8i8_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vzext.vf8 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i16> %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs @@ -1031,19 +1031,19 @@ define void @vpscatter_baseidx_v8f16(<8 x half> %val, half* %base, <8 x i16> %id ; RV32-LABEL: vpscatter_baseidx_v8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v9 -; RV32-NEXT: vadd.vv v26, v26, v26 +; RV32-NEXT: vsext.vf2 v10, v9 +; RV32-NEXT: vadd.vv v10, v10, v10 ; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v9 -; RV64-NEXT: vadd.vv v28, v28, v28 +; RV64-NEXT: vsext.vf4 v12, v9 +; RV64-NEXT: vadd.vv v12, v12, v12 ; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %idxs call void @llvm.vp.scatter.v8f16.v8p0f16(<8 x half> %val, <8 x half*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1126,19 +1126,19 @@ define void @vpscatter_baseidx_v8i8_v8f32(<8 x float> %val, float* %base, <8 x i ; RV32-LABEL: vpscatter_baseidx_v8i8_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8i8_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i8> %idxs call void @llvm.vp.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1149,19 +1149,19 @@ define void @vpscatter_baseidx_sext_v8i8_v8f32(<8 x float> %val, float* %base, < ; RV32-LABEL: vpscatter_baseidx_sext_v8i8_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_sext_v8i8_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf8 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1173,19 +1173,19 @@ define void @vpscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, float* %base, < ; RV32-LABEL: vpscatter_baseidx_zext_v8i8_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vzext.vf4 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_zext_v8i8_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf8 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf8 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1197,19 +1197,19 @@ define void @vpscatter_baseidx_v8i16_v8f32(<8 x float> %val, float* %base, <8 x ; RV32-LABEL: vpscatter_baseidx_v8i16_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf2 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8i16_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i16> %idxs call void @llvm.vp.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1220,19 +1220,19 @@ define void @vpscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, float* %base, ; RV32-LABEL: vpscatter_baseidx_sext_v8i16_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vsext.vf2 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_sext_v8i16_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf4 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1244,19 +1244,19 @@ define void @vpscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, float* %base, ; RV32-LABEL: vpscatter_baseidx_zext_v8i16_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vzext.vf2 v26, v10 -; RV32-NEXT: vsll.vi v26, v26, 2 +; RV32-NEXT: vzext.vf2 v12, v10 +; RV32-NEXT: vsll.vi v10, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_zext_v8i16_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vzext.vf4 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vzext.vf4 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i32> %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %eidxs @@ -1268,18 +1268,18 @@ define void @vpscatter_baseidx_v8f32(<8 x float> %val, float* %base, <8 x i32> % ; RV32-LABEL: vpscatter_baseidx_v8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v10, 2 +; RV32-NEXT: vsll.vi v10, v10, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v10 -; RV64-NEXT: vsll.vi v28, v28, 2 +; RV64-NEXT: vsext.vf2 v12, v10 +; RV64-NEXT: vsll.vi v12, v12, 2 ; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds float, float* %base, <8 x i32> %idxs call void @llvm.vp.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1362,19 +1362,19 @@ define void @vpscatter_baseidx_v8i8_v8f64(<8 x double> %val, double* %base, <8 x ; RV32-LABEL: vpscatter_baseidx_v8i8_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v12 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf4 v14, v12 +; RV32-NEXT: vsll.vi v12, v14, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8i8_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf8 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 +; RV64-NEXT: vsext.vf8 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i8> %idxs call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1385,10 +1385,10 @@ define void @vpscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, double* %base, ; CHECK-LABEL: vpscatter_baseidx_sext_v8i8_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v28, v12 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vsext.vf8 v16, v12 +; CHECK-NEXT: vsll.vi v12, v16, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret %eidxs = sext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1400,10 +1400,10 @@ define void @vpscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, double* %base, ; CHECK-LABEL: vpscatter_baseidx_zext_v8i8_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v28, v12 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vzext.vf8 v16, v12 +; CHECK-NEXT: vsll.vi v12, v16, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret %eidxs = zext <8 x i8> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1415,19 +1415,19 @@ define void @vpscatter_baseidx_v8i16_v8f64(<8 x double> %val, double* %base, <8 ; RV32-LABEL: vpscatter_baseidx_v8i16_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v12 -; RV32-NEXT: vsll.vi v26, v26, 3 +; RV32-NEXT: vsext.vf2 v14, v12 +; RV32-NEXT: vsll.vi v12, v14, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8i16_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf4 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 +; RV64-NEXT: vsext.vf4 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i16> %idxs call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1438,10 +1438,10 @@ define void @vpscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, double* %base ; CHECK-LABEL: vpscatter_baseidx_sext_v8i16_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v12 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vsext.vf4 v16, v12 +; CHECK-NEXT: vsll.vi v12, v16, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret %eidxs = sext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1453,10 +1453,10 @@ define void @vpscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, double* %base ; CHECK-LABEL: vpscatter_baseidx_zext_v8i16_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v12 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vzext.vf4 v16, v12 +; CHECK-NEXT: vsll.vi v12, v16, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret %eidxs = zext <8 x i16> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1468,18 +1468,18 @@ define void @vpscatter_baseidx_v8i32_v8f64(<8 x double> %val, double* %base, <8 ; RV32-LABEL: vpscatter_baseidx_v8i32_v8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32-NEXT: vsll.vi v26, v12, 3 +; RV32-NEXT: vsll.vi v12, v12, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v26, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_v8i32_v8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vsext.vf2 v28, v12 -; RV64-NEXT: vsll.vi v28, v28, 3 +; RV64-NEXT: vsext.vf2 v16, v12 +; RV64-NEXT: vsll.vi v12, v16, 3 ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; RV64-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i32> %idxs call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl) @@ -1490,10 +1490,10 @@ define void @vpscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, double* %base ; CHECK-LABEL: vpscatter_baseidx_sext_v8i32_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v12 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vsext.vf2 v16, v12 +; CHECK-NEXT: vsll.vi v12, v16, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret %eidxs = sext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1505,10 +1505,10 @@ define void @vpscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, double* %base ; CHECK-LABEL: vpscatter_baseidx_zext_v8i32_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v12 -; CHECK-NEXT: vsll.vi v28, v28, 3 +; CHECK-NEXT: vzext.vf2 v16, v12 +; CHECK-NEXT: vsll.vi v12, v16, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret %eidxs = zext <8 x i32> %idxs to <8 x i64> %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %eidxs @@ -1520,9 +1520,9 @@ define void @vpscatter_baseidx_v8f64(<8 x double> %val, double* %base, <8 x i64> ; CHECK-LABEL: vpscatter_baseidx_v8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; CHECK-NEXT: vsll.vi v28, v12, 3 +; CHECK-NEXT: vsll.vi v12, v12, 3 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %idxs call void @llvm.vp.scatter.v8f64.v8p0f64(<8 x double> %val, <8 x double*> %ptrs, <8 x i1> %m, i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll index 531f257fc84edc19d1b9c04aeabff0ed75d2917b..37f63f474e415e8d4fdadf2606cdb734c80b5665 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll @@ -10,9 +10,9 @@ define signext i1 @vreduce_or_v1i1(<1 x i1> %v) { ; CHECK-LABEL: vreduce_or_v1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -26,9 +26,9 @@ define signext i1 @vreduce_xor_v1i1(<1 x i1> %v) { ; CHECK-LABEL: vreduce_xor_v1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -42,9 +42,9 @@ define signext i1 @vreduce_and_v1i1(<1 x i1> %v) { ; CHECK-LABEL: vreduce_and_v1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -86,8 +86,8 @@ define signext i1 @vreduce_and_v2i1(<2 x i1> %v) { ; CHECK-LABEL: vreduce_and_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 -; CHECK-NEXT: vpopc.m a0, v25 +; CHECK-NEXT: vmnand.mm v8, v0, v0 +; CHECK-NEXT: vpopc.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -129,8 +129,8 @@ define signext i1 @vreduce_and_v4i1(<4 x i1> %v) { ; CHECK-LABEL: vreduce_and_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 -; CHECK-NEXT: vpopc.m a0, v25 +; CHECK-NEXT: vmnand.mm v8, v0, v0 +; CHECK-NEXT: vpopc.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -172,8 +172,8 @@ define signext i1 @vreduce_and_v8i1(<8 x i1> %v) { ; CHECK-LABEL: vreduce_and_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 -; CHECK-NEXT: vpopc.m a0, v25 +; CHECK-NEXT: vmnand.mm v8, v0, v0 +; CHECK-NEXT: vpopc.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -215,8 +215,8 @@ define signext i1 @vreduce_and_v16i1(<16 x i1> %v) { ; CHECK-LABEL: vreduce_and_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 -; CHECK-NEXT: vpopc.m a0, v25 +; CHECK-NEXT: vmnand.mm v8, v0, v0 +; CHECK-NEXT: vpopc.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -230,8 +230,8 @@ define signext i1 @vreduce_or_v32i1(<32 x i1> %v) { ; LMULMAX1-LABEL: vreduce_or_v32i1: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vmor.mm v25, v0, v8 -; LMULMAX1-NEXT: vpopc.m a0, v25 +; LMULMAX1-NEXT: vmor.mm v8, v0, v8 +; LMULMAX1-NEXT: vpopc.m a0, v8 ; LMULMAX1-NEXT: snez a0, a0 ; LMULMAX1-NEXT: neg a0, a0 ; LMULMAX1-NEXT: ret @@ -254,8 +254,8 @@ define signext i1 @vreduce_xor_v32i1(<32 x i1> %v) { ; LMULMAX1-LABEL: vreduce_xor_v32i1: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vmxor.mm v25, v0, v8 -; LMULMAX1-NEXT: vpopc.m a0, v25 +; LMULMAX1-NEXT: vmxor.mm v8, v0, v8 +; LMULMAX1-NEXT: vpopc.m a0, v8 ; LMULMAX1-NEXT: andi a0, a0, 1 ; LMULMAX1-NEXT: neg a0, a0 ; LMULMAX1-NEXT: ret @@ -278,8 +278,8 @@ define signext i1 @vreduce_and_v32i1(<32 x i1> %v) { ; LMULMAX1-LABEL: vreduce_and_v32i1: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vmnand.mm v25, v0, v8 -; LMULMAX1-NEXT: vpopc.m a0, v25 +; LMULMAX1-NEXT: vmnand.mm v8, v0, v8 +; LMULMAX1-NEXT: vpopc.m a0, v8 ; LMULMAX1-NEXT: seqz a0, a0 ; LMULMAX1-NEXT: neg a0, a0 ; LMULMAX1-NEXT: ret @@ -288,8 +288,8 @@ define signext i1 @vreduce_and_v32i1(<32 x i1> %v) { ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: addi a0, zero, 32 ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; LMULMAX8-NEXT: vmnand.mm v25, v0, v0 -; LMULMAX8-NEXT: vpopc.m a0, v25 +; LMULMAX8-NEXT: vmnand.mm v8, v0, v0 +; LMULMAX8-NEXT: vpopc.m a0, v8 ; LMULMAX8-NEXT: seqz a0, a0 ; LMULMAX8-NEXT: neg a0, a0 ; LMULMAX8-NEXT: ret @@ -303,10 +303,10 @@ define signext i1 @vreduce_or_v64i1(<64 x i1> %v) { ; LMULMAX1-LABEL: vreduce_or_v64i1: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vmor.mm v25, v8, v10 -; LMULMAX1-NEXT: vmor.mm v26, v0, v9 -; LMULMAX1-NEXT: vmor.mm v25, v26, v25 -; LMULMAX1-NEXT: vpopc.m a0, v25 +; LMULMAX1-NEXT: vmor.mm v8, v8, v10 +; LMULMAX1-NEXT: vmor.mm v9, v0, v9 +; LMULMAX1-NEXT: vmor.mm v8, v9, v8 +; LMULMAX1-NEXT: vpopc.m a0, v8 ; LMULMAX1-NEXT: snez a0, a0 ; LMULMAX1-NEXT: neg a0, a0 ; LMULMAX1-NEXT: ret @@ -329,10 +329,10 @@ define signext i1 @vreduce_xor_v64i1(<64 x i1> %v) { ; LMULMAX1-LABEL: vreduce_xor_v64i1: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vmxor.mm v25, v8, v10 -; LMULMAX1-NEXT: vmxor.mm v26, v0, v9 -; LMULMAX1-NEXT: vmxor.mm v25, v26, v25 -; LMULMAX1-NEXT: vpopc.m a0, v25 +; LMULMAX1-NEXT: vmxor.mm v8, v8, v10 +; LMULMAX1-NEXT: vmxor.mm v9, v0, v9 +; LMULMAX1-NEXT: vmxor.mm v8, v9, v8 +; LMULMAX1-NEXT: vpopc.m a0, v8 ; LMULMAX1-NEXT: andi a0, a0, 1 ; LMULMAX1-NEXT: neg a0, a0 ; LMULMAX1-NEXT: ret @@ -355,10 +355,10 @@ define signext i1 @vreduce_and_v64i1(<64 x i1> %v) { ; LMULMAX1-LABEL: vreduce_and_v64i1: ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; LMULMAX1-NEXT: vmand.mm v25, v8, v10 -; LMULMAX1-NEXT: vmand.mm v26, v0, v9 -; LMULMAX1-NEXT: vmnand.mm v25, v26, v25 -; LMULMAX1-NEXT: vpopc.m a0, v25 +; LMULMAX1-NEXT: vmand.mm v8, v8, v10 +; LMULMAX1-NEXT: vmand.mm v9, v0, v9 +; LMULMAX1-NEXT: vmnand.mm v8, v9, v8 +; LMULMAX1-NEXT: vpopc.m a0, v8 ; LMULMAX1-NEXT: seqz a0, a0 ; LMULMAX1-NEXT: neg a0, a0 ; LMULMAX1-NEXT: ret @@ -367,8 +367,8 @@ define signext i1 @vreduce_and_v64i1(<64 x i1> %v) { ; LMULMAX8: # %bb.0: ; LMULMAX8-NEXT: addi a0, zero, 64 ; LMULMAX8-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; LMULMAX8-NEXT: vmnand.mm v25, v0, v0 -; LMULMAX8-NEXT: vpopc.m a0, v25 +; LMULMAX8-NEXT: vmnand.mm v8, v0, v0 +; LMULMAX8-NEXT: vpopc.m a0, v8 ; LMULMAX8-NEXT: seqz a0, a0 ; LMULMAX8-NEXT: neg a0, a0 ; LMULMAX8-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll index d791ca37bb4606cc5e5b769b7cb604240ee80d50..9d58cb6bc49a549b6a97578096c99f04984347fb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll @@ -10,12 +10,12 @@ define <8 x i7> @vrem_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex ; CHECK-LABEL: vrem_vv_v8i7: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vadd.vv v25, v9, v9 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vadd.vv v26, v8, v8 -; CHECK-NEXT: vsra.vi v26, v26, 1 +; CHECK-NEXT: vadd.vv v9, v9, v9 +; CHECK-NEXT: vsra.vi v9, v9, 1 +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: vsra.vi v8, v8, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vrem.vv v8, v26, v25, v0.t +; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.srem.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) ret <8 x i7> %v @@ -666,9 +666,9 @@ define <2 x i64> @vrem_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vrem.vv v8, v8, v25, v0.t +; RV32-NEXT: vrem.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -692,9 +692,9 @@ define <2 x i64> @vrem_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vrem.vv v8, v8, v25 +; RV32-NEXT: vrem.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -744,9 +744,9 @@ define <4 x i64> @vrem_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vrem.vv v8, v8, v26, v0.t +; RV32-NEXT: vrem.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -770,9 +770,9 @@ define <4 x i64> @vrem_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vrem.vv v8, v8, v26 +; RV32-NEXT: vrem.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -822,9 +822,9 @@ define <8 x i64> @vrem_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vrem.vv v8, v8, v28, v0.t +; RV32-NEXT: vrem.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -848,9 +848,9 @@ define <8 x i64> @vrem_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vrem.vv v8, v8, v28 +; RV32-NEXT: vrem.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll index 09e11d9868e91da5d07fe751cfc03f33402d5055..64dadf0769fbccebde12c6bf4fc8450ddb5ea1f5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll @@ -11,10 +11,10 @@ define <8 x i7> @vremu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 127 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vand.vx v25, v9, a1 -; CHECK-NEXT: vand.vx v26, v8, a1 +; CHECK-NEXT: vand.vx v9, v9, a1 +; CHECK-NEXT: vand.vx v8, v8, a1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vremu.vv v8, v26, v25, v0.t +; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.urem.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) ret <8 x i7> %v @@ -665,9 +665,9 @@ define <2 x i64> @vremu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vremu.vv v8, v8, v25, v0.t +; RV32-NEXT: vremu.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -691,9 +691,9 @@ define <2 x i64> @vremu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vremu.vv v8, v8, v25 +; RV32-NEXT: vremu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -743,9 +743,9 @@ define <4 x i64> @vremu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vremu.vv v8, v8, v26, v0.t +; RV32-NEXT: vremu.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -769,9 +769,9 @@ define <4 x i64> @vremu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vremu.vv v8, v8, v26 +; RV32-NEXT: vremu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -821,9 +821,9 @@ define <8 x i64> @vremu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vremu.vv v8, v8, v28, v0.t +; RV32-NEXT: vremu.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -847,9 +847,9 @@ define <8 x i64> @vremu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vremu.vv v8, v8, v28 +; RV32-NEXT: vremu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll index 2affa084c7954422c47f0052180cc80509b9e26e..3bb9b61b949e3349cd1948377f5f24fb7b171fe0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll @@ -663,9 +663,9 @@ define <2 x i64> @vrsub_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vsub.vv v8, v25, v8, v0.t +; RV32-NEXT: vsub.vv v8, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -689,9 +689,9 @@ define <2 x i64> @vrsub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vsub.vv v8, v25, v8 +; RV32-NEXT: vsub.vv v8, v9, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -745,9 +745,9 @@ define <4 x i64> @vrsub_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vsub.vv v8, v26, v8, v0.t +; RV32-NEXT: vsub.vv v8, v10, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -771,9 +771,9 @@ define <4 x i64> @vrsub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vsub.vv v8, v26, v8 +; RV32-NEXT: vsub.vv v8, v10, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -827,9 +827,9 @@ define <8 x i64> @vrsub_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vsub.vv v8, v28, v8, v0.t +; RV32-NEXT: vsub.vv v8, v12, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -853,9 +853,9 @@ define <8 x i64> @vrsub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vsub.vv v8, v28, v8 +; RV32-NEXT: vsub.vv v8, v12, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll index 0d96d40dd34d9a16b70f127dbc311648ac047a4f..293a94ff1e422b4dbdf3ce01f1c78435ddf42232 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll @@ -457,8 +457,8 @@ define <2 x i64> @sadd_v2i64_vx(<2 x i64> %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero -; RV32-NEXT: vsadd.vv v8, v8, v25 +; RV32-NEXT: vlse64.v v9, (a0), zero +; RV32-NEXT: vsadd.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -506,8 +506,8 @@ define <4 x i64> @sadd_v4i64_vx(<4 x i64> %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero -; RV32-NEXT: vsadd.vv v8, v8, v26 +; RV32-NEXT: vlse64.v v10, (a0), zero +; RV32-NEXT: vsadd.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -555,8 +555,8 @@ define <8 x i64> @sadd_v8i64_vx(<8 x i64> %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero -; RV32-NEXT: vsadd.vv v8, v8, v28 +; RV32-NEXT: vlse64.v v12, (a0), zero +; RV32-NEXT: vsadd.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll index 9a698279e779f0faf1ce84cddf3cd0ef1f890492..057687fc41a526e1b25a74615bf979b4837f6e31 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll @@ -457,8 +457,8 @@ define <2 x i64> @uadd_v2i64_vx(<2 x i64> %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero -; RV32-NEXT: vsaddu.vv v8, v8, v25 +; RV32-NEXT: vlse64.v v9, (a0), zero +; RV32-NEXT: vsaddu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -506,8 +506,8 @@ define <4 x i64> @uadd_v4i64_vx(<4 x i64> %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero -; RV32-NEXT: vsaddu.vv v8, v8, v26 +; RV32-NEXT: vlse64.v v10, (a0), zero +; RV32-NEXT: vsaddu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -555,8 +555,8 @@ define <8 x i64> @uadd_v8i64_vx(<8 x i64> %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero -; RV32-NEXT: vsaddu.vv v8, v8, v28 +; RV32-NEXT: vlse64.v v12, (a0), zero +; RV32-NEXT: vsaddu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll index e6ae1cee619c9bc18e7e3267272170c57b5ec446..9845a485caa9d14c57d519f4e02bb7e723883682 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll @@ -6,11 +6,11 @@ define void @vselect_vv_v8i32(<8 x i32>* %a, <8 x i32>* %b, <8 x i1>* %cc, <8 x ; CHECK-LABEL: vselect_vv_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vlm.v v0, (a2) -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vmerge.vvm v26, v28, v26, v0 -; CHECK-NEXT: vse32.v v26, (a3) +; CHECK-NEXT: vle32.v v10, (a1) +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: vse32.v v8, (a3) ; CHECK-NEXT: ret %va = load <8 x i32>, <8 x i32>* %a %vb = load <8 x i32>, <8 x i32>* %b @@ -25,9 +25,9 @@ define void @vselect_vx_v8i32(i32 %a, <8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* % ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vlm.v v0, (a2) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vmerge.vxm v26, v26, a0, v0 -; CHECK-NEXT: vse32.v v26, (a3) +; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: vse32.v v8, (a3) ; CHECK-NEXT: ret %vb = load <8 x i32>, <8 x i32>* %b %ahead = insertelement <8 x i32> undef, i32 %a, i32 0 @@ -43,9 +43,9 @@ define void @vselect_vi_v8i32(<8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vlm.v v0, (a1) -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vmerge.vim v26, v26, -1, v0 -; CHECK-NEXT: vse32.v v26, (a2) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %vb = load <8 x i32>, <8 x i32>* %b %a = insertelement <8 x i32> undef, i32 -1, i32 0 @@ -60,11 +60,11 @@ define void @vselect_vv_v8f32(<8 x float>* %a, <8 x float>* %b, <8 x i1>* %cc, < ; CHECK-LABEL: vselect_vv_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vlm.v v0, (a2) -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vmerge.vvm v26, v28, v26, v0 -; CHECK-NEXT: vse32.v v26, (a3) +; CHECK-NEXT: vle32.v v10, (a1) +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: vse32.v v8, (a3) ; CHECK-NEXT: ret %va = load <8 x float>, <8 x float>* %a %vb = load <8 x float>, <8 x float>* %b @@ -79,9 +79,9 @@ define void @vselect_vx_v8f32(float %a, <8 x float>* %b, <8 x i1>* %cc, <8 x flo ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vlm.v v0, (a1) -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vfmerge.vfm v26, v26, fa0, v0 -; CHECK-NEXT: vse32.v v26, (a2) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %vb = load <8 x float>, <8 x float>* %b %ahead = insertelement <8 x float> undef, float %a, i32 0 @@ -97,9 +97,9 @@ define void @vselect_vfpzero_v8f32(<8 x float>* %b, <8 x i1>* %cc, <8 x float>* ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vlm.v v0, (a1) -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vmerge.vim v26, v26, 0, v0 -; CHECK-NEXT: vse32.v v26, (a2) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %vb = load <8 x float>, <8 x float>* %b %a = insertelement <8 x float> undef, float 0.0, i32 0 @@ -114,11 +114,11 @@ define void @vselect_vv_v16i16(<16 x i16>* %a, <16 x i16>* %b, <16 x i1>* %cc, < ; CHECK-LABEL: vselect_vv_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vlm.v v0, (a2) -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vmerge.vvm v26, v28, v26, v0 -; CHECK-NEXT: vse16.v v26, (a3) +; CHECK-NEXT: vle16.v v10, (a1) +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: vse16.v v8, (a3) ; CHECK-NEXT: ret %va = load <16 x i16>, <16 x i16>* %a %vb = load <16 x i16>, <16 x i16>* %b @@ -133,9 +133,9 @@ define void @vselect_vx_v16i16(i16 signext %a, <16 x i16>* %b, <16 x i1>* %cc, < ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vlm.v v0, (a2) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vmerge.vxm v26, v26, a0, v0 -; CHECK-NEXT: vse16.v v26, (a3) +; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: vse16.v v8, (a3) ; CHECK-NEXT: ret %vb = load <16 x i16>, <16 x i16>* %b %ahead = insertelement <16 x i16> undef, i16 %a, i32 0 @@ -151,9 +151,9 @@ define void @vselect_vi_v16i16(<16 x i16>* %b, <16 x i1>* %cc, <16 x i16>* %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vlm.v v0, (a1) -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vmerge.vim v26, v26, 4, v0 -; CHECK-NEXT: vse16.v v26, (a2) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmerge.vim v8, v8, 4, v0 +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %vb = load <16 x i16>, <16 x i16>* %b %a = insertelement <16 x i16> undef, i16 4, i32 0 @@ -169,11 +169,11 @@ define void @vselect_vv_v32f16(<32 x half>* %a, <32 x half>* %b, <32 x i1>* %cc, ; CHECK: # %bb.0: ; CHECK-NEXT: addi a4, zero, 32 ; CHECK-NEXT: vsetvli zero, a4, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vlm.v v0, (a2) -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vmerge.vvm v28, v8, v28, v0 -; CHECK-NEXT: vse16.v v28, (a3) +; CHECK-NEXT: vle16.v v12, (a1) +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 +; CHECK-NEXT: vse16.v v8, (a3) ; CHECK-NEXT: ret %va = load <32 x half>, <32 x half>* %a %vb = load <32 x half>, <32 x half>* %b @@ -189,9 +189,9 @@ define void @vselect_vx_v32f16(half %a, <32 x half>* %b, <32 x i1>* %cc, <32 x h ; CHECK-NEXT: addi a3, zero, 32 ; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu ; CHECK-NEXT: vlm.v v0, (a1) -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vfmerge.vfm v28, v28, fa0, v0 -; CHECK-NEXT: vse16.v v28, (a2) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %vb = load <32 x half>, <32 x half>* %b %ahead = insertelement <32 x half> undef, half %a, i32 0 @@ -208,9 +208,9 @@ define void @vselect_vfpzero_v32f16(<32 x half>* %b, <32 x i1>* %cc, <32 x half> ; CHECK-NEXT: addi a3, zero, 32 ; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu ; CHECK-NEXT: vlm.v v0, (a1) -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vmerge.vim v28, v28, 0, v0 -; CHECK-NEXT: vse16.v v28, (a2) +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %vb = load <32 x half>, <32 x half>* %b %a = insertelement <32 x half> undef, half 0.0, i32 0 @@ -225,9 +225,9 @@ define <2 x i1> @vselect_v2i1(<2 x i1> %a, <2 x i1> %b, <2 x i1> %cc) { ; CHECK-LABEL: vselect_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vmandnot.mm v25, v8, v9 -; CHECK-NEXT: vmand.mm v26, v0, v9 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select <2 x i1> %cc, <2 x i1> %a, <2 x i1> %b ret <2 x i1> %v @@ -237,9 +237,9 @@ define <4 x i1> @vselect_v4i1(<4 x i1> %a, <4 x i1> %b, <4 x i1> %cc) { ; CHECK-LABEL: vselect_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vmandnot.mm v25, v8, v9 -; CHECK-NEXT: vmand.mm v26, v0, v9 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select <4 x i1> %cc, <4 x i1> %a, <4 x i1> %b ret <4 x i1> %v @@ -249,9 +249,9 @@ define <8 x i1> @vselect_v8i1(<8 x i1> %a, <8 x i1> %b, <8 x i1> %cc) { ; CHECK-LABEL: vselect_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vmandnot.mm v25, v8, v9 -; CHECK-NEXT: vmand.mm v26, v0, v9 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select <8 x i1> %cc, <8 x i1> %a, <8 x i1> %b ret <8 x i1> %v @@ -261,9 +261,9 @@ define <16 x i1> @vselect_v16i1(<16 x i1> %a, <16 x i1> %b, <16 x i1> %cc) { ; CHECK-LABEL: vselect_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vmandnot.mm v25, v8, v9 -; CHECK-NEXT: vmand.mm v26, v0, v9 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select <16 x i1> %cc, <16 x i1> %a, <16 x i1> %b ret <16 x i1> %v @@ -274,9 +274,9 @@ define <32 x i1> @vselect_v32i1(<32 x i1> %a, <32 x i1> %b, <32 x i1> %cc) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmandnot.mm v25, v8, v9 -; CHECK-NEXT: vmand.mm v26, v0, v9 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select <32 x i1> %cc, <32 x i1> %a, <32 x i1> %b ret <32 x i1> %v @@ -287,9 +287,9 @@ define <64 x i1> @vselect_v64i1(<64 x i1> %a, <64 x i1> %b, <64 x i1> %cc) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 64 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmandnot.mm v25, v8, v9 -; CHECK-NEXT: vmand.mm v26, v0, v9 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select <64 x i1> %cc, <64 x i1> %a, <64 x i1> %b ret <64 x i1> %v diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll index 44589759e8a5dc854a6d033c642147a419aa9c24..3c191b122e712c0ec6c72c1a3b2bcef23456ee3c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll @@ -11,9 +11,9 @@ define <8 x i7> @vsll_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 127 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vand.vx v25, v9, a1 +; CHECK-NEXT: vand.vx v9, v9, a1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vsll.vv v8, v8, v25, v0.t +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.shl.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) ret <8 x i7> %v diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll index 410c325e4a687155659a704c427791955fbaa6fe..71f0580f87f6c69a7b17e90b54b0c30f06d55d52 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll @@ -11,11 +11,11 @@ define <8 x i7> @vsra_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 127 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vand.vx v25, v9, a1 -; CHECK-NEXT: vadd.vv v26, v8, v8 -; CHECK-NEXT: vsra.vi v26, v26, 1 +; CHECK-NEXT: vand.vx v9, v9, a1 +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: vsra.vi v8, v8, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vsra.vv v8, v26, v25, v0.t +; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.ashr.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) ret <8 x i7> %v diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll index fd86ee63c03f7446b83730b6333edb4503fcc213..fd5e71e4654aeeb6e4d1d049702d914847f06bd5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll @@ -11,10 +11,10 @@ define <8 x i7> @vsrl_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 127 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vand.vx v25, v9, a1 -; CHECK-NEXT: vand.vx v26, v8, a1 +; CHECK-NEXT: vand.vx v9, v9, a1 +; CHECK-NEXT: vand.vx v8, v8, a1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vsrl.vv v8, v26, v25, v0.t +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.lshr.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) ret <8 x i7> %v diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll index ebd30ef88c6f5553bbbc58de9b22ac9a4d54a4e6..b38a944f5302b6ddbe37280b830e11db8b4d34a3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll @@ -469,8 +469,8 @@ define <2 x i64> @ssub_v2i64_vx(<2 x i64> %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero -; RV32-NEXT: vssub.vv v8, v8, v25 +; RV32-NEXT: vlse64.v v9, (a0), zero +; RV32-NEXT: vssub.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -519,8 +519,8 @@ define <4 x i64> @ssub_v4i64_vx(<4 x i64> %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero -; RV32-NEXT: vssub.vv v8, v8, v26 +; RV32-NEXT: vlse64.v v10, (a0), zero +; RV32-NEXT: vssub.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -569,8 +569,8 @@ define <8 x i64> @ssub_v8i64_vx(<8 x i64> %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero -; RV32-NEXT: vssub.vv v8, v8, v28 +; RV32-NEXT: vlse64.v v12, (a0), zero +; RV32-NEXT: vssub.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll index 361d0773c06479a57974c85d6e9795efb3e7bcd0..9e345c93d3a6745bbd56a7936beee61fb10e5222 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll @@ -469,8 +469,8 @@ define <2 x i64> @usub_v2i64_vx(<2 x i64> %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero -; RV32-NEXT: vssubu.vv v8, v8, v25 +; RV32-NEXT: vlse64.v v9, (a0), zero +; RV32-NEXT: vssubu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -519,8 +519,8 @@ define <4 x i64> @usub_v4i64_vx(<4 x i64> %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero -; RV32-NEXT: vssubu.vv v8, v8, v26 +; RV32-NEXT: vlse64.v v10, (a0), zero +; RV32-NEXT: vssubu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -569,8 +569,8 @@ define <8 x i64> @usub_v8i64_vx(<8 x i64> %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero -; RV32-NEXT: vssubu.vv v8, v8, v28 +; RV32-NEXT: vlse64.v v12, (a0), zero +; RV32-NEXT: vssubu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll index d7f0b5ff2523b1fc9b9d4dd7e64972dca3e314af..e4d100c44407ffe472c3b99de94bd9cb4259d353 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll @@ -699,9 +699,9 @@ define <2 x i64> @vsub_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vsub.vv v8, v8, v25, v0.t +; RV32-NEXT: vsub.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -725,9 +725,9 @@ define <2 x i64> @vsub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vsub.vv v8, v8, v25 +; RV32-NEXT: vsub.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -777,9 +777,9 @@ define <4 x i64> @vsub_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vsub.vv v8, v8, v26, v0.t +; RV32-NEXT: vsub.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -803,9 +803,9 @@ define <4 x i64> @vsub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vsub.vv v8, v8, v26 +; RV32-NEXT: vsub.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -855,9 +855,9 @@ define <8 x i64> @vsub_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vsub.vv v8, v8, v28, v0.t +; RV32-NEXT: vsub.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -881,9 +881,9 @@ define <8 x i64> @vsub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vsub.vv v8, v8, v28 +; RV32-NEXT: vsub.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll index bd1b3e5e2c5277d2822443687e9dfa766494b15e..a7ff2aa52af63b3bc8a01915dd5cec63355399be 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll @@ -6,9 +6,9 @@ define <2 x i16> @vwmacc_v2i16(<2 x i8>* %x, <2 x i8>* %y, <2 x i16> %z) { ; CHECK-LABEL: vwmacc_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmacc.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vle8.v v10, (a1) +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <2 x i8>, <2 x i8>* %x %b = load <2 x i8>, <2 x i8>* %y @@ -23,9 +23,9 @@ define <4 x i16> @vwmacc_v4i16(<4 x i8>* %x, <4 x i8>* %y, <4 x i16> %z) { ; CHECK-LABEL: vwmacc_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmacc.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vle8.v v10, (a1) +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %b = load <4 x i8>, <4 x i8>* %y @@ -40,9 +40,9 @@ define <2 x i32> @vwmacc_v2i32(<2 x i16>* %x, <2 x i16>* %y, <2 x i32> %z) { ; CHECK-LABEL: vwmacc_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vwmacc.vv v8, v25, v26 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vle16.v v10, (a1) +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <2 x i16>, <2 x i16>* %x %b = load <2 x i16>, <2 x i16>* %y @@ -57,9 +57,9 @@ define <8 x i16> @vwmacc_v8i16(<8 x i8>* %x, <8 x i8>* %y, <8 x i16> %z) { ; CHECK-LABEL: vwmacc_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmacc.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vle8.v v10, (a1) +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = load <8 x i8>, <8 x i8>* %y @@ -74,9 +74,9 @@ define <4 x i32> @vwmacc_v4i32(<4 x i16>* %x, <4 x i16>* %y, <4 x i32> %z) { ; CHECK-LABEL: vwmacc_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vwmacc.vv v8, v25, v26 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vle16.v v10, (a1) +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = load <4 x i16>, <4 x i16>* %y @@ -91,9 +91,9 @@ define <2 x i64> @vwmacc_v2i64(<2 x i32>* %x, <2 x i32>* %y, <2 x i64> %z) { ; CHECK-LABEL: vwmacc_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vwmacc.vv v8, v25, v26 +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vle32.v v10, (a1) +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %b = load <2 x i32>, <2 x i32>* %y @@ -108,9 +108,9 @@ define <16 x i16> @vwmacc_v16i16(<16 x i8>* %x, <16 x i8>* %y, <16 x i16> %z) { ; CHECK-LABEL: vwmacc_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmacc.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v10, (a0) +; CHECK-NEXT: vle8.v v11, (a1) +; CHECK-NEXT: vwmacc.vv v8, v10, v11 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -125,9 +125,9 @@ define <8 x i32> @vwmacc_v8i32(<8 x i16>* %x, <8 x i16>* %y, <8 x i32> %z) { ; CHECK-LABEL: vwmacc_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vwmacc.vv v8, v25, v26 +; CHECK-NEXT: vle16.v v10, (a0) +; CHECK-NEXT: vle16.v v11, (a1) +; CHECK-NEXT: vwmacc.vv v8, v10, v11 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -142,9 +142,9 @@ define <4 x i64> @vwmacc_v4i64(<4 x i32>* %x, <4 x i32>* %y, <4 x i64> %z) { ; CHECK-LABEL: vwmacc_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vwmacc.vv v8, v25, v26 +; CHECK-NEXT: vle32.v v10, (a0) +; CHECK-NEXT: vle32.v v11, (a1) +; CHECK-NEXT: vwmacc.vv v8, v10, v11 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -160,9 +160,9 @@ define <32 x i16> @vwmacc_v32i16(<32 x i8>* %x, <32 x i8>* %y, <32 x i16> %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vwmacc.vv v8, v26, v28 +; CHECK-NEXT: vle8.v v12, (a0) +; CHECK-NEXT: vle8.v v14, (a1) +; CHECK-NEXT: vwmacc.vv v8, v12, v14 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -177,9 +177,9 @@ define <16 x i32> @vwmacc_v16i32(<16 x i16>* %x, <16 x i16>* %y, <16 x i32> %z) ; CHECK-LABEL: vwmacc_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vwmacc.vv v8, v26, v28 +; CHECK-NEXT: vle16.v v12, (a0) +; CHECK-NEXT: vle16.v v14, (a1) +; CHECK-NEXT: vwmacc.vv v8, v12, v14 ; CHECK-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -194,9 +194,9 @@ define <8 x i64> @vwmacc_v8i64(<8 x i32>* %x, <8 x i32>* %y, <8 x i64> %z) { ; CHECK-LABEL: vwmacc_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vwmacc.vv v8, v26, v28 +; CHECK-NEXT: vle32.v v12, (a0) +; CHECK-NEXT: vle32.v v14, (a1) +; CHECK-NEXT: vwmacc.vv v8, v12, v14 ; CHECK-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -212,9 +212,9 @@ define <64 x i16> @vwmacc_v64i16(<64 x i8>* %x, <64 x i8>* %y, <64 x i16> %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vle8.v v16, (a1) -; CHECK-NEXT: vwmacc.vv v8, v28, v16 +; CHECK-NEXT: vle8.v v16, (a0) +; CHECK-NEXT: vle8.v v20, (a1) +; CHECK-NEXT: vwmacc.vv v8, v16, v20 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = load <64 x i8>, <64 x i8>* %y @@ -230,9 +230,9 @@ define <32 x i32> @vwmacc_v32i32(<32 x i16>* %x, <32 x i16>* %y, <32 x i32> %z) ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vle16.v v16, (a1) -; CHECK-NEXT: vwmacc.vv v8, v28, v16 +; CHECK-NEXT: vle16.v v16, (a0) +; CHECK-NEXT: vle16.v v20, (a1) +; CHECK-NEXT: vwmacc.vv v8, v16, v20 ; CHECK-NEXT: ret %a = load <32 x i16>, <32 x i16>* %x %b = load <32 x i16>, <32 x i16>* %y @@ -247,9 +247,9 @@ define <16 x i64> @vwmacc_v16i64(<16 x i32>* %x, <16 x i32>* %y, <16 x i64> %z) ; CHECK-LABEL: vwmacc_v16i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vle32.v v16, (a1) -; CHECK-NEXT: vwmacc.vv v8, v28, v16 +; CHECK-NEXT: vle32.v v16, (a0) +; CHECK-NEXT: vle32.v v20, (a1) +; CHECK-NEXT: vwmacc.vv v8, v16, v20 ; CHECK-NEXT: ret %a = load <16 x i32>, <16 x i32>* %x %b = load <16 x i32>, <16 x i32>* %y @@ -264,8 +264,8 @@ define <2 x i16> @vwmacc_vx_v2i16(<2 x i8>* %x, i8 %y, <2 x i16> %z) { ; CHECK-LABEL: vwmacc_vx_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmacc.vx v8, a1, v25 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vwmacc.vx v8, a1, v9 ; CHECK-NEXT: ret %a = load <2 x i8>, <2 x i8>* %x %b = insertelement <2 x i8> undef, i8 %y, i32 0 @@ -281,8 +281,8 @@ define <4 x i16> @vwmacc_vx_v4i16(<4 x i8>* %x, i8 %y, <4 x i16> %z) { ; CHECK-LABEL: vwmacc_vx_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmacc.vx v8, a1, v25 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vwmacc.vx v8, a1, v9 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %b = insertelement <4 x i8> undef, i8 %y, i32 0 @@ -298,8 +298,8 @@ define <2 x i32> @vwmacc_vx_v2i32(<2 x i16>* %x, i16 %y, <2 x i32> %z) { ; CHECK-LABEL: vwmacc_vx_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vwmacc.vx v8, a1, v25 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vwmacc.vx v8, a1, v9 ; CHECK-NEXT: ret %a = load <2 x i16>, <2 x i16>* %x %b = insertelement <2 x i16> undef, i16 %y, i32 0 @@ -315,8 +315,8 @@ define <8 x i16> @vwmacc_vx_v8i16(<8 x i8>* %x, i8 %y, <8 x i16> %z) { ; CHECK-LABEL: vwmacc_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmacc.vx v8, a1, v25 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vwmacc.vx v8, a1, v9 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 %y, i32 0 @@ -332,8 +332,8 @@ define <4 x i32> @vwmacc_vx_v4i32(<4 x i16>* %x, i16 %y, <4 x i32> %z) { ; CHECK-LABEL: vwmacc_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vwmacc.vx v8, a1, v25 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vwmacc.vx v8, a1, v9 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = insertelement <4 x i16> undef, i16 %y, i32 0 @@ -349,8 +349,8 @@ define <2 x i64> @vwmacc_vx_v2i64(<2 x i32>* %x, i32 %y, <2 x i64> %z) { ; CHECK-LABEL: vwmacc_vx_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vwmacc.vx v8, a1, v25 +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vwmacc.vx v8, a1, v9 ; CHECK-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %b = insertelement <2 x i32> undef, i32 %y, i64 0 @@ -366,8 +366,8 @@ define <16 x i16> @vwmacc_vx_v16i16(<16 x i8>* %x, i8 %y, <16 x i16> %z) { ; CHECK-LABEL: vwmacc_vx_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmacc.vx v8, a1, v25 +; CHECK-NEXT: vle8.v v10, (a0) +; CHECK-NEXT: vwmacc.vx v8, a1, v10 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -383,8 +383,8 @@ define <8 x i32> @vwmacc_vx_v8i32(<8 x i16>* %x, i16 %y, <8 x i32> %z) { ; CHECK-LABEL: vwmacc_vx_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vwmacc.vx v8, a1, v25 +; CHECK-NEXT: vle16.v v10, (a0) +; CHECK-NEXT: vwmacc.vx v8, a1, v10 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -400,8 +400,8 @@ define <4 x i64> @vwmacc_vx_v4i64(<4 x i32>* %x, i32 %y, <4 x i64> %z) { ; CHECK-LABEL: vwmacc_vx_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vwmacc.vx v8, a1, v25 +; CHECK-NEXT: vle32.v v10, (a0) +; CHECK-NEXT: vwmacc.vx v8, a1, v10 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i64 0 @@ -418,8 +418,8 @@ define <32 x i16> @vwmacc_vx_v32i16(<32 x i8>* %x, i8 %y, <32 x i16> %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vwmacc.vx v8, a1, v26 +; CHECK-NEXT: vle8.v v12, (a0) +; CHECK-NEXT: vwmacc.vx v8, a1, v12 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 %y, i32 0 @@ -435,8 +435,8 @@ define <16 x i32> @vwmacc_vx_v16i32(<16 x i16>* %x, i16 %y, <16 x i32> %z) { ; CHECK-LABEL: vwmacc_vx_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vwmacc.vx v8, a1, v26 +; CHECK-NEXT: vle16.v v12, (a0) +; CHECK-NEXT: vwmacc.vx v8, a1, v12 ; CHECK-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = insertelement <16 x i16> undef, i16 %y, i32 0 @@ -452,8 +452,8 @@ define <8 x i64> @vwmacc_vx_v8i64(<8 x i32>* %x, i32 %y, <8 x i64> %z) { ; CHECK-LABEL: vwmacc_vx_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vwmacc.vx v8, a1, v26 +; CHECK-NEXT: vle32.v v12, (a0) +; CHECK-NEXT: vwmacc.vx v8, a1, v12 ; CHECK-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = insertelement <8 x i32> undef, i32 %y, i64 0 @@ -470,8 +470,8 @@ define <64 x i16> @vwmacc_vx_v64i16(<64 x i8>* %x, i8 %y, <64 x i16> %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vwmacc.vx v8, a1, v28 +; CHECK-NEXT: vle8.v v16, (a0) +; CHECK-NEXT: vwmacc.vx v8, a1, v16 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 %y, i32 0 @@ -488,8 +488,8 @@ define <32 x i32> @vwmacc_vx_v32i32(<32 x i16>* %x, i16 %y, <32 x i32> %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vwmacc.vx v8, a1, v28 +; CHECK-NEXT: vle16.v v16, (a0) +; CHECK-NEXT: vwmacc.vx v8, a1, v16 ; CHECK-NEXT: ret %a = load <32 x i16>, <32 x i16>* %x %b = insertelement <32 x i16> undef, i16 %y, i32 0 @@ -505,8 +505,8 @@ define <16 x i64> @vwmacc_vx_v16i64(<16 x i32>* %x, i32 %y, <16 x i64> %z) { ; CHECK-LABEL: vwmacc_vx_v16i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vwmacc.vx v8, a1, v28 +; CHECK-NEXT: vle32.v v16, (a0) +; CHECK-NEXT: vwmacc.vx v8, a1, v16 ; CHECK-NEXT: ret %a = load <16 x i32>, <16 x i32>* %x %b = insertelement <16 x i32> undef, i32 %y, i64 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll index 9cae8d23ef6f6dc73b7f5a9aa478e3d537b9ac03..040bee273e9f6ee1a91f85d9aba1d8c9abfeb8e5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll @@ -6,9 +6,9 @@ define <2 x i16> @vwmaccu_v2i16(<2 x i8>* %x, <2 x i8>* %y, <2 x i16> %z) { ; CHECK-LABEL: vwmaccu_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmaccu.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vle8.v v10, (a1) +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <2 x i8>, <2 x i8>* %x %b = load <2 x i8>, <2 x i8>* %y @@ -23,9 +23,9 @@ define <4 x i16> @vwmaccu_v4i16(<4 x i8>* %x, <4 x i8>* %y, <4 x i16> %z) { ; CHECK-LABEL: vwmaccu_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmaccu.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vle8.v v10, (a1) +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %b = load <4 x i8>, <4 x i8>* %y @@ -40,9 +40,9 @@ define <2 x i32> @vwmaccu_v2i32(<2 x i16>* %x, <2 x i16>* %y, <2 x i32> %z) { ; CHECK-LABEL: vwmaccu_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vwmaccu.vv v8, v25, v26 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vle16.v v10, (a1) +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <2 x i16>, <2 x i16>* %x %b = load <2 x i16>, <2 x i16>* %y @@ -57,9 +57,9 @@ define <8 x i16> @vwmaccu_v8i16(<8 x i8>* %x, <8 x i8>* %y, <8 x i16> %z) { ; CHECK-LABEL: vwmaccu_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmaccu.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vle8.v v10, (a1) +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = load <8 x i8>, <8 x i8>* %y @@ -74,9 +74,9 @@ define <4 x i32> @vwmaccu_v4i32(<4 x i16>* %x, <4 x i16>* %y, <4 x i32> %z) { ; CHECK-LABEL: vwmaccu_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vwmaccu.vv v8, v25, v26 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vle16.v v10, (a1) +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = load <4 x i16>, <4 x i16>* %y @@ -91,9 +91,9 @@ define <2 x i64> @vwmaccu_v2i64(<2 x i32>* %x, <2 x i32>* %y, <2 x i64> %z) { ; CHECK-LABEL: vwmaccu_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vwmaccu.vv v8, v25, v26 +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vle32.v v10, (a1) +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %b = load <2 x i32>, <2 x i32>* %y @@ -108,9 +108,9 @@ define <16 x i16> @vwmaccu_v16i16(<16 x i8>* %x, <16 x i8>* %y, <16 x i16> %z) { ; CHECK-LABEL: vwmaccu_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmaccu.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v10, (a0) +; CHECK-NEXT: vle8.v v11, (a1) +; CHECK-NEXT: vwmaccu.vv v8, v10, v11 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -125,9 +125,9 @@ define <8 x i32> @vwmaccu_v8i32(<8 x i16>* %x, <8 x i16>* %y, <8 x i32> %z) { ; CHECK-LABEL: vwmaccu_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vwmaccu.vv v8, v25, v26 +; CHECK-NEXT: vle16.v v10, (a0) +; CHECK-NEXT: vle16.v v11, (a1) +; CHECK-NEXT: vwmaccu.vv v8, v10, v11 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -142,9 +142,9 @@ define <4 x i64> @vwmaccu_v4i64(<4 x i32>* %x, <4 x i32>* %y, <4 x i64> %z) { ; CHECK-LABEL: vwmaccu_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vwmaccu.vv v8, v25, v26 +; CHECK-NEXT: vle32.v v10, (a0) +; CHECK-NEXT: vle32.v v11, (a1) +; CHECK-NEXT: vwmaccu.vv v8, v10, v11 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -160,9 +160,9 @@ define <32 x i16> @vwmaccu_v32i16(<32 x i8>* %x, <32 x i8>* %y, <32 x i16> %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vwmaccu.vv v8, v26, v28 +; CHECK-NEXT: vle8.v v12, (a0) +; CHECK-NEXT: vle8.v v14, (a1) +; CHECK-NEXT: vwmaccu.vv v8, v12, v14 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -177,9 +177,9 @@ define <16 x i32> @vwmaccu_v16i32(<16 x i16>* %x, <16 x i16>* %y, <16 x i32> %z) ; CHECK-LABEL: vwmaccu_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vwmaccu.vv v8, v26, v28 +; CHECK-NEXT: vle16.v v12, (a0) +; CHECK-NEXT: vle16.v v14, (a1) +; CHECK-NEXT: vwmaccu.vv v8, v12, v14 ; CHECK-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -194,9 +194,9 @@ define <8 x i64> @vwmaccu_v8i64(<8 x i32>* %x, <8 x i32>* %y, <8 x i64> %z) { ; CHECK-LABEL: vwmaccu_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vwmaccu.vv v8, v26, v28 +; CHECK-NEXT: vle32.v v12, (a0) +; CHECK-NEXT: vle32.v v14, (a1) +; CHECK-NEXT: vwmaccu.vv v8, v12, v14 ; CHECK-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -212,9 +212,9 @@ define <64 x i16> @vwmaccu_v64i16(<64 x i8>* %x, <64 x i8>* %y, <64 x i16> %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vle8.v v16, (a1) -; CHECK-NEXT: vwmaccu.vv v8, v28, v16 +; CHECK-NEXT: vle8.v v16, (a0) +; CHECK-NEXT: vle8.v v20, (a1) +; CHECK-NEXT: vwmaccu.vv v8, v16, v20 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = load <64 x i8>, <64 x i8>* %y @@ -230,9 +230,9 @@ define <32 x i32> @vwmaccu_v32i32(<32 x i16>* %x, <32 x i16>* %y, <32 x i32> %z) ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vle16.v v16, (a1) -; CHECK-NEXT: vwmaccu.vv v8, v28, v16 +; CHECK-NEXT: vle16.v v16, (a0) +; CHECK-NEXT: vle16.v v20, (a1) +; CHECK-NEXT: vwmaccu.vv v8, v16, v20 ; CHECK-NEXT: ret %a = load <32 x i16>, <32 x i16>* %x %b = load <32 x i16>, <32 x i16>* %y @@ -247,9 +247,9 @@ define <16 x i64> @vwmaccu_v16i64(<16 x i32>* %x, <16 x i32>* %y, <16 x i64> %z) ; CHECK-LABEL: vwmaccu_v16i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vle32.v v16, (a1) -; CHECK-NEXT: vwmaccu.vv v8, v28, v16 +; CHECK-NEXT: vle32.v v16, (a0) +; CHECK-NEXT: vle32.v v20, (a1) +; CHECK-NEXT: vwmaccu.vv v8, v16, v20 ; CHECK-NEXT: ret %a = load <16 x i32>, <16 x i32>* %x %b = load <16 x i32>, <16 x i32>* %y @@ -264,8 +264,8 @@ define <2 x i16> @vwmaccu_vx_v2i16(<2 x i8>* %x, i8 %y, <2 x i16> %z) { ; CHECK-LABEL: vwmaccu_vx_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmaccu.vx v8, a1, v25 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vwmaccu.vx v8, a1, v9 ; CHECK-NEXT: ret %a = load <2 x i8>, <2 x i8>* %x %b = insertelement <2 x i8> undef, i8 %y, i32 0 @@ -281,8 +281,8 @@ define <4 x i16> @vwmaccu_vx_v4i16(<4 x i8>* %x, i8 %y, <4 x i16> %z) { ; CHECK-LABEL: vwmaccu_vx_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmaccu.vx v8, a1, v25 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vwmaccu.vx v8, a1, v9 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %b = insertelement <4 x i8> undef, i8 %y, i32 0 @@ -298,8 +298,8 @@ define <2 x i32> @vwmaccu_vx_v2i32(<2 x i16>* %x, i16 %y, <2 x i32> %z) { ; CHECK-LABEL: vwmaccu_vx_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vwmaccu.vx v8, a1, v25 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vwmaccu.vx v8, a1, v9 ; CHECK-NEXT: ret %a = load <2 x i16>, <2 x i16>* %x %b = insertelement <2 x i16> undef, i16 %y, i32 0 @@ -315,8 +315,8 @@ define <8 x i16> @vwmaccu_vx_v8i16(<8 x i8>* %x, i8 %y, <8 x i16> %z) { ; CHECK-LABEL: vwmaccu_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmaccu.vx v8, a1, v25 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vwmaccu.vx v8, a1, v9 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 %y, i32 0 @@ -332,8 +332,8 @@ define <4 x i32> @vwmaccu_vx_v4i32(<4 x i16>* %x, i16 %y, <4 x i32> %z) { ; CHECK-LABEL: vwmaccu_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vwmaccu.vx v8, a1, v25 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vwmaccu.vx v8, a1, v9 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = insertelement <4 x i16> undef, i16 %y, i32 0 @@ -349,8 +349,8 @@ define <2 x i64> @vwmaccu_vx_v2i64(<2 x i32>* %x, i32 %y, <2 x i64> %z) { ; CHECK-LABEL: vwmaccu_vx_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vwmaccu.vx v8, a1, v25 +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vwmaccu.vx v8, a1, v9 ; CHECK-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %b = insertelement <2 x i32> undef, i32 %y, i64 0 @@ -366,8 +366,8 @@ define <16 x i16> @vwmaccu_vx_v16i16(<16 x i8>* %x, i8 %y, <16 x i16> %z) { ; CHECK-LABEL: vwmaccu_vx_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmaccu.vx v8, a1, v25 +; CHECK-NEXT: vle8.v v10, (a0) +; CHECK-NEXT: vwmaccu.vx v8, a1, v10 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -383,8 +383,8 @@ define <8 x i32> @vwmaccu_vx_v8i32(<8 x i16>* %x, i16 %y, <8 x i32> %z) { ; CHECK-LABEL: vwmaccu_vx_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vwmaccu.vx v8, a1, v25 +; CHECK-NEXT: vle16.v v10, (a0) +; CHECK-NEXT: vwmaccu.vx v8, a1, v10 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -400,8 +400,8 @@ define <4 x i64> @vwmaccu_vx_v4i64(<4 x i32>* %x, i32 %y, <4 x i64> %z) { ; CHECK-LABEL: vwmaccu_vx_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vwmaccu.vx v8, a1, v25 +; CHECK-NEXT: vle32.v v10, (a0) +; CHECK-NEXT: vwmaccu.vx v8, a1, v10 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i64 0 @@ -418,8 +418,8 @@ define <32 x i16> @vwmaccu_vx_v32i16(<32 x i8>* %x, i8 %y, <32 x i16> %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vwmaccu.vx v8, a1, v26 +; CHECK-NEXT: vle8.v v12, (a0) +; CHECK-NEXT: vwmaccu.vx v8, a1, v12 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 %y, i32 0 @@ -435,8 +435,8 @@ define <16 x i32> @vwmaccu_vx_v16i32(<16 x i16>* %x, i16 %y, <16 x i32> %z) { ; CHECK-LABEL: vwmaccu_vx_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vwmaccu.vx v8, a1, v26 +; CHECK-NEXT: vle16.v v12, (a0) +; CHECK-NEXT: vwmaccu.vx v8, a1, v12 ; CHECK-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = insertelement <16 x i16> undef, i16 %y, i32 0 @@ -452,8 +452,8 @@ define <8 x i64> @vwmaccu_vx_v8i64(<8 x i32>* %x, i32 %y, <8 x i64> %z) { ; CHECK-LABEL: vwmaccu_vx_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vwmaccu.vx v8, a1, v26 +; CHECK-NEXT: vle32.v v12, (a0) +; CHECK-NEXT: vwmaccu.vx v8, a1, v12 ; CHECK-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = insertelement <8 x i32> undef, i32 %y, i64 0 @@ -470,8 +470,8 @@ define <64 x i16> @vwmaccu_vx_v64i16(<64 x i8>* %x, i8 %y, <64 x i16> %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vwmaccu.vx v8, a1, v28 +; CHECK-NEXT: vle8.v v16, (a0) +; CHECK-NEXT: vwmaccu.vx v8, a1, v16 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 %y, i32 0 @@ -488,8 +488,8 @@ define <32 x i32> @vwmaccu_vx_v32i32(<32 x i16>* %x, i16 %y, <32 x i32> %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vwmaccu.vx v8, a1, v28 +; CHECK-NEXT: vle16.v v16, (a0) +; CHECK-NEXT: vwmaccu.vx v8, a1, v16 ; CHECK-NEXT: ret %a = load <32 x i16>, <32 x i16>* %x %b = insertelement <32 x i16> undef, i16 %y, i32 0 @@ -505,8 +505,8 @@ define <16 x i64> @vwmaccu_vx_v16i64(<16 x i32>* %x, i32 %y, <16 x i64> %z) { ; CHECK-LABEL: vwmaccu_vx_v16i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vwmaccu.vx v8, a1, v28 +; CHECK-NEXT: vle32.v v16, (a0) +; CHECK-NEXT: vwmaccu.vx v8, a1, v16 ; CHECK-NEXT: ret %a = load <16 x i32>, <16 x i32>* %x %b = insertelement <16 x i32> undef, i32 %y, i64 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll index 025e3197f0f841e574d1df2d1626b1502c911df6..8439b357b30f684b3572d6237b92ae84573ff4bf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll @@ -6,9 +6,9 @@ define <2 x i16> @vwmul_v2i16(<2 x i8>* %x, <2 x i8>* %y) { ; CHECK-LABEL: vwmul_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmul.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vle8.v v10, (a1) +; CHECK-NEXT: vwmul.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <2 x i8>, <2 x i8>* %x %b = load <2 x i8>, <2 x i8>* %y @@ -22,9 +22,9 @@ define <4 x i16> @vwmul_v4i16(<4 x i8>* %x, <4 x i8>* %y) { ; CHECK-LABEL: vwmul_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmul.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vle8.v v10, (a1) +; CHECK-NEXT: vwmul.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %b = load <4 x i8>, <4 x i8>* %y @@ -38,9 +38,9 @@ define <2 x i32> @vwmul_v2i32(<2 x i16>* %x, <2 x i16>* %y) { ; CHECK-LABEL: vwmul_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vwmul.vv v8, v25, v26 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vle16.v v10, (a1) +; CHECK-NEXT: vwmul.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <2 x i16>, <2 x i16>* %x %b = load <2 x i16>, <2 x i16>* %y @@ -54,9 +54,9 @@ define <8 x i16> @vwmul_v8i16(<8 x i8>* %x, <8 x i8>* %y) { ; CHECK-LABEL: vwmul_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmul.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vle8.v v10, (a1) +; CHECK-NEXT: vwmul.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = load <8 x i8>, <8 x i8>* %y @@ -70,9 +70,9 @@ define <4 x i32> @vwmul_v4i32(<4 x i16>* %x, <4 x i16>* %y) { ; CHECK-LABEL: vwmul_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vwmul.vv v8, v25, v26 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vle16.v v10, (a1) +; CHECK-NEXT: vwmul.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = load <4 x i16>, <4 x i16>* %y @@ -86,9 +86,9 @@ define <2 x i64> @vwmul_v2i64(<2 x i32>* %x, <2 x i32>* %y) { ; CHECK-LABEL: vwmul_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vwmul.vv v8, v25, v26 +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vle32.v v10, (a1) +; CHECK-NEXT: vwmul.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %b = load <2 x i32>, <2 x i32>* %y @@ -102,9 +102,9 @@ define <16 x i16> @vwmul_v16i16(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: vwmul_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmul.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v10, (a0) +; CHECK-NEXT: vle8.v v11, (a1) +; CHECK-NEXT: vwmul.vv v8, v10, v11 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -118,9 +118,9 @@ define <8 x i32> @vwmul_v8i32(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: vwmul_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vwmul.vv v8, v25, v26 +; CHECK-NEXT: vle16.v v10, (a0) +; CHECK-NEXT: vle16.v v11, (a1) +; CHECK-NEXT: vwmul.vv v8, v10, v11 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -134,9 +134,9 @@ define <4 x i64> @vwmul_v4i64(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: vwmul_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vwmul.vv v8, v25, v26 +; CHECK-NEXT: vle32.v v10, (a0) +; CHECK-NEXT: vle32.v v11, (a1) +; CHECK-NEXT: vwmul.vv v8, v10, v11 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -151,9 +151,9 @@ define <32 x i16> @vwmul_v32i16(<32 x i8>* %x, <32 x i8>* %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vwmul.vv v8, v26, v28 +; CHECK-NEXT: vle8.v v12, (a0) +; CHECK-NEXT: vle8.v v14, (a1) +; CHECK-NEXT: vwmul.vv v8, v12, v14 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -167,9 +167,9 @@ define <16 x i32> @vwmul_v16i32(<16 x i16>* %x, <16 x i16>* %y) { ; CHECK-LABEL: vwmul_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vwmul.vv v8, v26, v28 +; CHECK-NEXT: vle16.v v12, (a0) +; CHECK-NEXT: vle16.v v14, (a1) +; CHECK-NEXT: vwmul.vv v8, v12, v14 ; CHECK-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -183,9 +183,9 @@ define <8 x i64> @vwmul_v8i64(<8 x i32>* %x, <8 x i32>* %y) { ; CHECK-LABEL: vwmul_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vwmul.vv v8, v26, v28 +; CHECK-NEXT: vle32.v v12, (a0) +; CHECK-NEXT: vle32.v v14, (a1) +; CHECK-NEXT: vwmul.vv v8, v12, v14 ; CHECK-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -200,9 +200,9 @@ define <64 x i16> @vwmul_v64i16(<64 x i8>* %x, <64 x i8>* %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vle8.v v16, (a1) -; CHECK-NEXT: vwmul.vv v8, v28, v16 +; CHECK-NEXT: vle8.v v16, (a0) +; CHECK-NEXT: vle8.v v20, (a1) +; CHECK-NEXT: vwmul.vv v8, v16, v20 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = load <64 x i8>, <64 x i8>* %y @@ -217,9 +217,9 @@ define <32 x i32> @vwmul_v32i32(<32 x i16>* %x, <32 x i16>* %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vle16.v v16, (a1) -; CHECK-NEXT: vwmul.vv v8, v28, v16 +; CHECK-NEXT: vle16.v v16, (a0) +; CHECK-NEXT: vle16.v v20, (a1) +; CHECK-NEXT: vwmul.vv v8, v16, v20 ; CHECK-NEXT: ret %a = load <32 x i16>, <32 x i16>* %x %b = load <32 x i16>, <32 x i16>* %y @@ -233,9 +233,9 @@ define <16 x i64> @vwmul_v16i64(<16 x i32>* %x, <16 x i32>* %y) { ; CHECK-LABEL: vwmul_v16i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vle32.v v16, (a1) -; CHECK-NEXT: vwmul.vv v8, v28, v16 +; CHECK-NEXT: vle32.v v16, (a0) +; CHECK-NEXT: vle32.v v20, (a1) +; CHECK-NEXT: vwmul.vv v8, v16, v20 ; CHECK-NEXT: ret %a = load <16 x i32>, <16 x i32>* %x %b = load <16 x i32>, <16 x i32>* %y @@ -356,12 +356,12 @@ define <2 x i32> @vwmul_v2i32_v2i8(<2 x i8>* %x, <2 x i8>* %y) { ; CHECK-LABEL: vwmul_v2i32_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vle8.v v26, (a0) +; CHECK-NEXT: vle8.v v8, (a1) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vsext.vf2 v27, v25 -; CHECK-NEXT: vsext.vf2 v25, v26 -; CHECK-NEXT: vwmul.vv v8, v25, v27 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vsext.vf2 v11, v9 +; CHECK-NEXT: vwmul.vv v8, v11, v10 ; CHECK-NEXT: ret %a = load <2 x i8>, <2 x i8>* %x %b = load <2 x i8>, <2 x i8>* %y @@ -375,11 +375,11 @@ define <4 x i32> @vwmul_v4i32_v4i8_v4i16(<4 x i8>* %x, <4 x i16>* %y) { ; CHECK-LABEL: vwmul_v4i32_v4i8_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vsext.vf2 v27, v25 -; CHECK-NEXT: vwmul.vv v8, v27, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vwmul.vv v8, v10, v9 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %b = load <4 x i16>, <4 x i16>* %y @@ -393,10 +393,10 @@ define <4 x i64> @vwmul_v4i64_v4i32_v4i8(<4 x i32>* %x, <4 x i8>* %y) { ; CHECK-LABEL: vwmul_v4i64_v4i32_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vsext.vf4 v27, v25 -; CHECK-NEXT: vwmul.vv v8, v26, v27 +; CHECK-NEXT: vle8.v v8, (a1) +; CHECK-NEXT: vle32.v v10, (a0) +; CHECK-NEXT: vsext.vf4 v11, v8 +; CHECK-NEXT: vwmul.vv v8, v10, v11 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i8>, <4 x i8>* %y @@ -410,8 +410,8 @@ define <2 x i16> @vwmul_vx_v2i16(<2 x i8>* %x, i8 %y) { ; CHECK-LABEL: vwmul_vx_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmul.vx v8, v25, a1 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vwmul.vx v8, v9, a1 ; CHECK-NEXT: ret %a = load <2 x i8>, <2 x i8>* %x %b = insertelement <2 x i8> undef, i8 %y, i32 0 @@ -426,8 +426,8 @@ define <4 x i16> @vwmul_vx_v4i16(<4 x i8>* %x, i8 %y) { ; CHECK-LABEL: vwmul_vx_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmul.vx v8, v25, a1 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vwmul.vx v8, v9, a1 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %b = insertelement <4 x i8> undef, i8 %y, i32 0 @@ -442,8 +442,8 @@ define <2 x i32> @vwmul_vx_v2i32(<2 x i16>* %x, i16 %y) { ; CHECK-LABEL: vwmul_vx_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vwmul.vx v8, v25, a1 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vwmul.vx v8, v9, a1 ; CHECK-NEXT: ret %a = load <2 x i16>, <2 x i16>* %x %b = insertelement <2 x i16> undef, i16 %y, i32 0 @@ -458,8 +458,8 @@ define <8 x i16> @vwmul_vx_v8i16(<8 x i8>* %x, i8 %y) { ; CHECK-LABEL: vwmul_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmul.vx v8, v25, a1 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vwmul.vx v8, v9, a1 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 %y, i32 0 @@ -474,8 +474,8 @@ define <4 x i32> @vwmul_vx_v4i32(<4 x i16>* %x, i16 %y) { ; CHECK-LABEL: vwmul_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vwmul.vx v8, v25, a1 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vwmul.vx v8, v9, a1 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = insertelement <4 x i16> undef, i16 %y, i32 0 @@ -490,8 +490,8 @@ define <2 x i64> @vwmul_vx_v2i64(<2 x i32>* %x, i32 %y) { ; CHECK-LABEL: vwmul_vx_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vwmul.vx v8, v25, a1 +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vwmul.vx v8, v9, a1 ; CHECK-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %b = insertelement <2 x i32> undef, i32 %y, i64 0 @@ -506,8 +506,8 @@ define <16 x i16> @vwmul_vx_v16i16(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: vwmul_vx_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmul.vx v8, v25, a1 +; CHECK-NEXT: vle8.v v10, (a0) +; CHECK-NEXT: vwmul.vx v8, v10, a1 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -522,8 +522,8 @@ define <8 x i32> @vwmul_vx_v8i32(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: vwmul_vx_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vwmul.vx v8, v25, a1 +; CHECK-NEXT: vle16.v v10, (a0) +; CHECK-NEXT: vwmul.vx v8, v10, a1 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -538,8 +538,8 @@ define <4 x i64> @vwmul_vx_v4i64(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: vwmul_vx_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vwmul.vx v8, v25, a1 +; CHECK-NEXT: vle32.v v10, (a0) +; CHECK-NEXT: vwmul.vx v8, v10, a1 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i64 0 @@ -555,8 +555,8 @@ define <32 x i16> @vwmul_vx_v32i16(<32 x i8>* %x, i8 %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vwmul.vx v8, v26, a1 +; CHECK-NEXT: vle8.v v12, (a0) +; CHECK-NEXT: vwmul.vx v8, v12, a1 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 %y, i32 0 @@ -571,8 +571,8 @@ define <16 x i32> @vwmul_vx_v16i32(<16 x i16>* %x, i16 %y) { ; CHECK-LABEL: vwmul_vx_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vwmul.vx v8, v26, a1 +; CHECK-NEXT: vle16.v v12, (a0) +; CHECK-NEXT: vwmul.vx v8, v12, a1 ; CHECK-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = insertelement <16 x i16> undef, i16 %y, i32 0 @@ -587,8 +587,8 @@ define <8 x i64> @vwmul_vx_v8i64(<8 x i32>* %x, i32 %y) { ; CHECK-LABEL: vwmul_vx_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vwmul.vx v8, v26, a1 +; CHECK-NEXT: vle32.v v12, (a0) +; CHECK-NEXT: vwmul.vx v8, v12, a1 ; CHECK-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = insertelement <8 x i32> undef, i32 %y, i64 0 @@ -604,8 +604,8 @@ define <64 x i16> @vwmul_vx_v64i16(<64 x i8>* %x, i8 %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vwmul.vx v8, v28, a1 +; CHECK-NEXT: vle8.v v16, (a0) +; CHECK-NEXT: vwmul.vx v8, v16, a1 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 %y, i32 0 @@ -621,8 +621,8 @@ define <32 x i32> @vwmul_vx_v32i32(<32 x i16>* %x, i16 %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vwmul.vx v8, v28, a1 +; CHECK-NEXT: vle16.v v16, (a0) +; CHECK-NEXT: vwmul.vx v8, v16, a1 ; CHECK-NEXT: ret %a = load <32 x i16>, <32 x i16>* %x %b = insertelement <32 x i16> undef, i16 %y, i32 0 @@ -637,8 +637,8 @@ define <16 x i64> @vwmul_vx_v16i64(<16 x i32>* %x, i32 %y) { ; CHECK-LABEL: vwmul_vx_v16i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vwmul.vx v8, v28, a1 +; CHECK-NEXT: vle32.v v16, (a0) +; CHECK-NEXT: vwmul.vx v8, v16, a1 ; CHECK-NEXT: ret %a = load <16 x i32>, <16 x i32>* %x %b = insertelement <16 x i32> undef, i32 %y, i64 0 @@ -653,9 +653,9 @@ define <8 x i16> @vwmul_vx_v8i16_i8(<8 x i8>* %x, i8* %y) { ; CHECK-LABEL: vwmul_vx_v8i16_i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: lb a0, 0(a1) -; CHECK-NEXT: vwmul.vx v8, v25, a0 +; CHECK-NEXT: vwmul.vx v8, v9, a0 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = load i8, i8* %y @@ -671,11 +671,11 @@ define <8 x i16> @vwmul_vx_v8i16_i16(<8 x i8>* %x, i16* %y) { ; CHECK-LABEL: vwmul_vx_v8i16_i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: lh a0, 0(a1) ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v25 -; CHECK-NEXT: vmul.vx v8, v26, a0 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmul.vx v8, v9, a0 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = load i16, i16* %y @@ -690,9 +690,9 @@ define <4 x i32> @vwmul_vx_v4i32_i8(<4 x i16>* %x, i8* %y) { ; CHECK-LABEL: vwmul_vx_v4i32_i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: lb a0, 0(a1) -; CHECK-NEXT: vwmul.vx v8, v25, a0 +; CHECK-NEXT: vwmul.vx v8, v9, a0 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = load i8, i8* %y @@ -708,9 +708,9 @@ define <4 x i32> @vwmul_vx_v4i32_i16(<4 x i16>* %x, i16* %y) { ; CHECK-LABEL: vwmul_vx_v4i32_i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: lh a0, 0(a1) -; CHECK-NEXT: vwmul.vx v8, v25, a0 +; CHECK-NEXT: vwmul.vx v8, v9, a0 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = load i16, i16* %y @@ -726,11 +726,11 @@ define <4 x i32> @vwmul_vx_v4i32_i32(<4 x i16>* %x, i32* %y) { ; CHECK-LABEL: vwmul_vx_v4i32_i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: lw a0, 0(a1) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v25 -; CHECK-NEXT: vmul.vx v8, v26, a0 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmul.vx v8, v9, a0 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = load i32, i32* %y @@ -748,24 +748,24 @@ define <2 x i64> @vwmul_vx_v2i64_i8(<2 x i32>* %x, i8* %y) { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: lb a1, 0(a1) -; RV32-NEXT: vle32.v v25, (a0) +; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: srai a0, a1, 31 ; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; RV32-NEXT: vsext.vf2 v27, v25 -; RV32-NEXT: vmul.vv v8, v26, v27 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vmul.vv v8, v9, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vwmul_vx_v2i64_i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vle32.v v25, (a0) +; RV64-NEXT: vle32.v v9, (a0) ; RV64-NEXT: lb a0, 0(a1) -; RV64-NEXT: vwmul.vx v8, v25, a0 +; RV64-NEXT: vwmul.vx v8, v9, a0 ; RV64-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %b = load i8, i8* %y @@ -784,24 +784,24 @@ define <2 x i64> @vwmul_vx_v2i64_i16(<2 x i32>* %x, i16* %y) { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: lh a1, 0(a1) -; RV32-NEXT: vle32.v v25, (a0) +; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: srai a0, a1, 31 ; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; RV32-NEXT: vsext.vf2 v27, v25 -; RV32-NEXT: vmul.vv v8, v26, v27 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vmul.vv v8, v9, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vwmul_vx_v2i64_i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vle32.v v25, (a0) +; RV64-NEXT: vle32.v v9, (a0) ; RV64-NEXT: lh a0, 0(a1) -; RV64-NEXT: vwmul.vx v8, v25, a0 +; RV64-NEXT: vwmul.vx v8, v9, a0 ; RV64-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %b = load i16, i16* %y @@ -820,24 +820,24 @@ define <2 x i64> @vwmul_vx_v2i64_i32(<2 x i32>* %x, i32* %y) { ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: lw a1, 0(a1) -; RV32-NEXT: vle32.v v25, (a0) +; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: srai a0, a1, 31 ; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; RV32-NEXT: vsext.vf2 v27, v25 -; RV32-NEXT: vmul.vv v8, v26, v27 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vmul.vv v8, v9, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vwmul_vx_v2i64_i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vle32.v v25, (a0) +; RV64-NEXT: vle32.v v9, (a0) ; RV64-NEXT: lw a0, 0(a1) -; RV64-NEXT: vwmul.vx v8, v25, a0 +; RV64-NEXT: vwmul.vx v8, v9, a0 ; RV64-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %b = load i32, i32* %y @@ -857,25 +857,25 @@ define <2 x i64> @vwmul_vx_v2i64_i64(<2 x i32>* %x, i64* %y) { ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: lw a2, 4(a1) ; RV32-NEXT: lw a1, 0(a1) -; RV32-NEXT: vle32.v v25, (a0) +; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: sw a2, 12(sp) ; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; RV32-NEXT: vsext.vf2 v27, v25 -; RV32-NEXT: vmul.vv v8, v26, v27 +; RV32-NEXT: vsext.vf2 v10, v8 +; RV32-NEXT: vmul.vv v8, v9, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vwmul_vx_v2i64_i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; RV64-NEXT: vle32.v v25, (a0) +; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: ld a0, 0(a1) ; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; RV64-NEXT: vsext.vf2 v26, v25 -; RV64-NEXT: vmul.vx v8, v26, a0 +; RV64-NEXT: vsext.vf2 v9, v8 +; RV64-NEXT: vmul.vx v8, v9, a0 ; RV64-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %b = load i64, i64* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll index 45083b5304573aedb36a545c8c3c4e2a75b0e93e..7d3ca3bd1c2146b21bfe6bbcd26dea0e5eda6128 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll @@ -6,9 +6,9 @@ define <2 x i16> @vwmulu_v2i16(<2 x i8>* %x, <2 x i8>* %y) { ; CHECK-LABEL: vwmulu_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmulu.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vle8.v v10, (a1) +; CHECK-NEXT: vwmulu.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <2 x i8>, <2 x i8>* %x %b = load <2 x i8>, <2 x i8>* %y @@ -22,9 +22,9 @@ define <4 x i16> @vwmulu_v4i16(<4 x i8>* %x, <4 x i8>* %y) { ; CHECK-LABEL: vwmulu_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmulu.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vle8.v v10, (a1) +; CHECK-NEXT: vwmulu.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %b = load <4 x i8>, <4 x i8>* %y @@ -38,9 +38,9 @@ define <2 x i32> @vwmulu_v2i32(<2 x i16>* %x, <2 x i16>* %y) { ; CHECK-LABEL: vwmulu_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vwmulu.vv v8, v25, v26 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vle16.v v10, (a1) +; CHECK-NEXT: vwmulu.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <2 x i16>, <2 x i16>* %x %b = load <2 x i16>, <2 x i16>* %y @@ -54,9 +54,9 @@ define <8 x i16> @vwmulu_v8i16(<8 x i8>* %x, <8 x i8>* %y) { ; CHECK-LABEL: vwmulu_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmulu.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vle8.v v10, (a1) +; CHECK-NEXT: vwmulu.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = load <8 x i8>, <8 x i8>* %y @@ -70,9 +70,9 @@ define <4 x i32> @vwmulu_v4i32(<4 x i16>* %x, <4 x i16>* %y) { ; CHECK-LABEL: vwmulu_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vwmulu.vv v8, v25, v26 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vle16.v v10, (a1) +; CHECK-NEXT: vwmulu.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = load <4 x i16>, <4 x i16>* %y @@ -86,9 +86,9 @@ define <2 x i64> @vwmulu_v2i64(<2 x i32>* %x, <2 x i32>* %y) { ; CHECK-LABEL: vwmulu_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vwmulu.vv v8, v25, v26 +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vle32.v v10, (a1) +; CHECK-NEXT: vwmulu.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %b = load <2 x i32>, <2 x i32>* %y @@ -102,9 +102,9 @@ define <16 x i16> @vwmulu_v16i16(<16 x i8>* %x, <16 x i8>* %y) { ; CHECK-LABEL: vwmulu_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vwmulu.vv v8, v25, v26 +; CHECK-NEXT: vle8.v v10, (a0) +; CHECK-NEXT: vle8.v v11, (a1) +; CHECK-NEXT: vwmulu.vv v8, v10, v11 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = load <16 x i8>, <16 x i8>* %y @@ -118,9 +118,9 @@ define <8 x i32> @vwmulu_v8i32(<8 x i16>* %x, <8 x i16>* %y) { ; CHECK-LABEL: vwmulu_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vwmulu.vv v8, v25, v26 +; CHECK-NEXT: vle16.v v10, (a0) +; CHECK-NEXT: vle16.v v11, (a1) +; CHECK-NEXT: vwmulu.vv v8, v10, v11 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = load <8 x i16>, <8 x i16>* %y @@ -134,9 +134,9 @@ define <4 x i64> @vwmulu_v4i64(<4 x i32>* %x, <4 x i32>* %y) { ; CHECK-LABEL: vwmulu_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vwmulu.vv v8, v25, v26 +; CHECK-NEXT: vle32.v v10, (a0) +; CHECK-NEXT: vle32.v v11, (a1) +; CHECK-NEXT: vwmulu.vv v8, v10, v11 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i32>, <4 x i32>* %y @@ -151,9 +151,9 @@ define <32 x i16> @vwmulu_v32i16(<32 x i8>* %x, <32 x i8>* %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vwmulu.vv v8, v26, v28 +; CHECK-NEXT: vle8.v v12, (a0) +; CHECK-NEXT: vle8.v v14, (a1) +; CHECK-NEXT: vwmulu.vv v8, v12, v14 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = load <32 x i8>, <32 x i8>* %y @@ -167,9 +167,9 @@ define <16 x i32> @vwmulu_v16i32(<16 x i16>* %x, <16 x i16>* %y) { ; CHECK-LABEL: vwmulu_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vwmulu.vv v8, v26, v28 +; CHECK-NEXT: vle16.v v12, (a0) +; CHECK-NEXT: vle16.v v14, (a1) +; CHECK-NEXT: vwmulu.vv v8, v12, v14 ; CHECK-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = load <16 x i16>, <16 x i16>* %y @@ -183,9 +183,9 @@ define <8 x i64> @vwmulu_v8i64(<8 x i32>* %x, <8 x i32>* %y) { ; CHECK-LABEL: vwmulu_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vwmulu.vv v8, v26, v28 +; CHECK-NEXT: vle32.v v12, (a0) +; CHECK-NEXT: vle32.v v14, (a1) +; CHECK-NEXT: vwmulu.vv v8, v12, v14 ; CHECK-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = load <8 x i32>, <8 x i32>* %y @@ -200,9 +200,9 @@ define <64 x i16> @vwmulu_v64i16(<64 x i8>* %x, <64 x i8>* %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vle8.v v16, (a1) -; CHECK-NEXT: vwmulu.vv v8, v28, v16 +; CHECK-NEXT: vle8.v v16, (a0) +; CHECK-NEXT: vle8.v v20, (a1) +; CHECK-NEXT: vwmulu.vv v8, v16, v20 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = load <64 x i8>, <64 x i8>* %y @@ -217,9 +217,9 @@ define <32 x i32> @vwmulu_v32i32(<32 x i16>* %x, <32 x i16>* %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vle16.v v16, (a1) -; CHECK-NEXT: vwmulu.vv v8, v28, v16 +; CHECK-NEXT: vle16.v v16, (a0) +; CHECK-NEXT: vle16.v v20, (a1) +; CHECK-NEXT: vwmulu.vv v8, v16, v20 ; CHECK-NEXT: ret %a = load <32 x i16>, <32 x i16>* %x %b = load <32 x i16>, <32 x i16>* %y @@ -233,9 +233,9 @@ define <16 x i64> @vwmulu_v16i64(<16 x i32>* %x, <16 x i32>* %y) { ; CHECK-LABEL: vwmulu_v16i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vle32.v v16, (a1) -; CHECK-NEXT: vwmulu.vv v8, v28, v16 +; CHECK-NEXT: vle32.v v16, (a0) +; CHECK-NEXT: vle32.v v20, (a1) +; CHECK-NEXT: vwmulu.vv v8, v16, v20 ; CHECK-NEXT: ret %a = load <16 x i32>, <16 x i32>* %x %b = load <16 x i32>, <16 x i32>* %y @@ -356,12 +356,12 @@ define <2 x i32> @vwmulu_v2i32_v2i8(<2 x i8>* %x, <2 x i8>* %y) { ; CHECK-LABEL: vwmulu_v2i32_v2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vle8.v v26, (a0) +; CHECK-NEXT: vle8.v v8, (a1) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vzext.vf2 v27, v25 -; CHECK-NEXT: vzext.vf2 v25, v26 -; CHECK-NEXT: vwmulu.vv v8, v25, v27 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vzext.vf2 v11, v9 +; CHECK-NEXT: vwmulu.vv v8, v11, v10 ; CHECK-NEXT: ret %a = load <2 x i8>, <2 x i8>* %x %b = load <2 x i8>, <2 x i8>* %y @@ -375,11 +375,11 @@ define <4 x i32> @vwmulu_v4i32_v4i8_v4i16(<4 x i8>* %x, <4 x i16>* %y) { ; CHECK-LABEL: vwmulu_v4i32_v4i8_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vle16.v v26, (a1) +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: vle16.v v9, (a1) ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vzext.vf2 v27, v25 -; CHECK-NEXT: vwmulu.vv v8, v27, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vwmulu.vv v8, v10, v9 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %b = load <4 x i16>, <4 x i16>* %y @@ -393,10 +393,10 @@ define <4 x i64> @vwmulu_v4i64_v4i32_v4i8(<4 x i32>* %x, <4 x i8>* %y) { ; CHECK-LABEL: vwmulu_v4i64_v4i32_v4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vzext.vf4 v27, v25 -; CHECK-NEXT: vwmulu.vv v8, v26, v27 +; CHECK-NEXT: vle8.v v8, (a1) +; CHECK-NEXT: vle32.v v10, (a0) +; CHECK-NEXT: vzext.vf4 v11, v8 +; CHECK-NEXT: vwmulu.vv v8, v10, v11 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = load <4 x i8>, <4 x i8>* %y @@ -410,8 +410,8 @@ define <2 x i16> @vwmulu_vx_v2i16(<2 x i8>* %x, i8 %y) { ; CHECK-LABEL: vwmulu_vx_v2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmulu.vx v8, v25, a1 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vwmulu.vx v8, v9, a1 ; CHECK-NEXT: ret %a = load <2 x i8>, <2 x i8>* %x %b = insertelement <2 x i8> undef, i8 %y, i32 0 @@ -426,8 +426,8 @@ define <4 x i16> @vwmulu_vx_v4i16(<4 x i8>* %x, i8 %y) { ; CHECK-LABEL: vwmulu_vx_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmulu.vx v8, v25, a1 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vwmulu.vx v8, v9, a1 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x %b = insertelement <4 x i8> undef, i8 %y, i32 0 @@ -442,8 +442,8 @@ define <2 x i32> @vwmulu_vx_v2i32(<2 x i16>* %x, i16 %y) { ; CHECK-LABEL: vwmulu_vx_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vwmulu.vx v8, v25, a1 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vwmulu.vx v8, v9, a1 ; CHECK-NEXT: ret %a = load <2 x i16>, <2 x i16>* %x %b = insertelement <2 x i16> undef, i16 %y, i32 0 @@ -458,8 +458,8 @@ define <8 x i16> @vwmulu_vx_v8i16(<8 x i8>* %x, i8 %y) { ; CHECK-LABEL: vwmulu_vx_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmulu.vx v8, v25, a1 +; CHECK-NEXT: vle8.v v9, (a0) +; CHECK-NEXT: vwmulu.vx v8, v9, a1 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = insertelement <8 x i8> undef, i8 %y, i32 0 @@ -474,8 +474,8 @@ define <4 x i32> @vwmulu_vx_v4i32(<4 x i16>* %x, i16 %y) { ; CHECK-LABEL: vwmulu_vx_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vwmulu.vx v8, v25, a1 +; CHECK-NEXT: vle16.v v9, (a0) +; CHECK-NEXT: vwmulu.vx v8, v9, a1 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = insertelement <4 x i16> undef, i16 %y, i32 0 @@ -490,8 +490,8 @@ define <2 x i64> @vwmulu_vx_v2i64(<2 x i32>* %x, i32 %y) { ; CHECK-LABEL: vwmulu_vx_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vwmulu.vx v8, v25, a1 +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vwmulu.vx v8, v9, a1 ; CHECK-NEXT: ret %a = load <2 x i32>, <2 x i32>* %x %b = insertelement <2 x i32> undef, i32 %y, i64 0 @@ -506,8 +506,8 @@ define <16 x i16> @vwmulu_vx_v16i16(<16 x i8>* %x, i8 %y) { ; CHECK-LABEL: vwmulu_vx_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vwmulu.vx v8, v25, a1 +; CHECK-NEXT: vle8.v v10, (a0) +; CHECK-NEXT: vwmulu.vx v8, v10, a1 ; CHECK-NEXT: ret %a = load <16 x i8>, <16 x i8>* %x %b = insertelement <16 x i8> undef, i8 %y, i32 0 @@ -522,8 +522,8 @@ define <8 x i32> @vwmulu_vx_v8i32(<8 x i16>* %x, i16 %y) { ; CHECK-LABEL: vwmulu_vx_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) -; CHECK-NEXT: vwmulu.vx v8, v25, a1 +; CHECK-NEXT: vle16.v v10, (a0) +; CHECK-NEXT: vwmulu.vx v8, v10, a1 ; CHECK-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %b = insertelement <8 x i16> undef, i16 %y, i32 0 @@ -538,8 +538,8 @@ define <4 x i64> @vwmulu_vx_v4i64(<4 x i32>* %x, i32 %y) { ; CHECK-LABEL: vwmulu_vx_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vwmulu.vx v8, v25, a1 +; CHECK-NEXT: vle32.v v10, (a0) +; CHECK-NEXT: vwmulu.vx v8, v10, a1 ; CHECK-NEXT: ret %a = load <4 x i32>, <4 x i32>* %x %b = insertelement <4 x i32> undef, i32 %y, i64 0 @@ -555,8 +555,8 @@ define <32 x i16> @vwmulu_vx_v32i16(<32 x i8>* %x, i8 %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vwmulu.vx v8, v26, a1 +; CHECK-NEXT: vle8.v v12, (a0) +; CHECK-NEXT: vwmulu.vx v8, v12, a1 ; CHECK-NEXT: ret %a = load <32 x i8>, <32 x i8>* %x %b = insertelement <32 x i8> undef, i8 %y, i32 0 @@ -571,8 +571,8 @@ define <16 x i32> @vwmulu_vx_v16i32(<16 x i16>* %x, i16 %y) { ; CHECK-LABEL: vwmulu_vx_v16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vwmulu.vx v8, v26, a1 +; CHECK-NEXT: vle16.v v12, (a0) +; CHECK-NEXT: vwmulu.vx v8, v12, a1 ; CHECK-NEXT: ret %a = load <16 x i16>, <16 x i16>* %x %b = insertelement <16 x i16> undef, i16 %y, i32 0 @@ -587,8 +587,8 @@ define <8 x i64> @vwmulu_vx_v8i64(<8 x i32>* %x, i32 %y) { ; CHECK-LABEL: vwmulu_vx_v8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; CHECK-NEXT: vle32.v v26, (a0) -; CHECK-NEXT: vwmulu.vx v8, v26, a1 +; CHECK-NEXT: vle32.v v12, (a0) +; CHECK-NEXT: vwmulu.vx v8, v12, a1 ; CHECK-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %b = insertelement <8 x i32> undef, i32 %y, i64 0 @@ -604,8 +604,8 @@ define <64 x i16> @vwmulu_vx_v64i16(<64 x i8>* %x, i8 %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vwmulu.vx v8, v28, a1 +; CHECK-NEXT: vle8.v v16, (a0) +; CHECK-NEXT: vwmulu.vx v8, v16, a1 ; CHECK-NEXT: ret %a = load <64 x i8>, <64 x i8>* %x %b = insertelement <64 x i8> undef, i8 %y, i32 0 @@ -621,8 +621,8 @@ define <32 x i32> @vwmulu_vx_v32i32(<32 x i16>* %x, i16 %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 32 ; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vwmulu.vx v8, v28, a1 +; CHECK-NEXT: vle16.v v16, (a0) +; CHECK-NEXT: vwmulu.vx v8, v16, a1 ; CHECK-NEXT: ret %a = load <32 x i16>, <32 x i16>* %x %b = insertelement <32 x i16> undef, i16 %y, i32 0 @@ -637,8 +637,8 @@ define <16 x i64> @vwmulu_vx_v16i64(<16 x i32>* %x, i32 %y) { ; CHECK-LABEL: vwmulu_vx_v16i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vwmulu.vx v8, v28, a1 +; CHECK-NEXT: vle32.v v16, (a0) +; CHECK-NEXT: vwmulu.vx v8, v16, a1 ; CHECK-NEXT: ret %a = load <16 x i32>, <16 x i32>* %x %b = insertelement <16 x i32> undef, i32 %y, i64 0 @@ -653,9 +653,9 @@ define <8 x i16> @vwmulu_vx_v8i16_i8(<8 x i8>* %x, i8* %y) { ; CHECK-LABEL: vwmulu_vx_v8i16_i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: lbu a0, 0(a1) -; CHECK-NEXT: vwmulu.vx v8, v25, a0 +; CHECK-NEXT: vwmulu.vx v8, v9, a0 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = load i8, i8* %y @@ -671,11 +671,11 @@ define <8 x i16> @vwmulu_vx_v8i16_i16(<8 x i8>* %x, i16* %y) { ; CHECK-LABEL: vwmulu_vx_v8i16_i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu -; CHECK-NEXT: vle8.v v25, (a0) +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: lh a0, 0(a1) ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v25 -; CHECK-NEXT: vmul.vx v8, v26, a0 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmul.vx v8, v9, a0 ; CHECK-NEXT: ret %a = load <8 x i8>, <8 x i8>* %x %b = load i16, i16* %y @@ -690,9 +690,9 @@ define <4 x i32> @vwmulu_vx_v4i32_i8(<4 x i16>* %x, i8* %y) { ; CHECK-LABEL: vwmulu_vx_v4i32_i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: lbu a0, 0(a1) -; CHECK-NEXT: vwmulu.vx v8, v25, a0 +; CHECK-NEXT: vwmulu.vx v8, v9, a0 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = load i8, i8* %y @@ -708,9 +708,9 @@ define <4 x i32> @vwmulu_vx_v4i32_i16(<4 x i16>* %x, i16* %y) { ; CHECK-LABEL: vwmulu_vx_v4i32_i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: lhu a0, 0(a1) -; CHECK-NEXT: vwmulu.vx v8, v25, a0 +; CHECK-NEXT: vwmulu.vx v8, v9, a0 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = load i16, i16* %y @@ -726,11 +726,11 @@ define <4 x i32> @vwmulu_vx_v4i32_i32(<4 x i16>* %x, i32* %y) { ; CHECK-LABEL: vwmulu_vx_v4i32_i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu -; CHECK-NEXT: vle16.v v25, (a0) +; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: lw a0, 0(a1) ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v25 -; CHECK-NEXT: vmul.vx v8, v26, a0 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmul.vx v8, v9, a0 ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x %b = load i32, i32* %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll index ca1293b1930ab5d78ef71385517ab8373e5ef101..499983a3ea2d0ead9cb24cf87b85ddc220931443 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll @@ -1375,9 +1375,9 @@ define <2 x i64> @vxor_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vxor.vv v8, v8, v25, v0.t +; RV32-NEXT: vxor.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1401,9 +1401,9 @@ define <2 x i64> @vxor_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vxor.vv v8, v8, v25 +; RV32-NEXT: vxor.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1505,9 +1505,9 @@ define <4 x i64> @vxor_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vxor.vv v8, v8, v26, v0.t +; RV32-NEXT: vxor.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1531,9 +1531,9 @@ define <4 x i64> @vxor_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vxor.vv v8, v8, v26 +; RV32-NEXT: vxor.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1635,9 +1635,9 @@ define <8 x i64> @vxor_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vxor.vv v8, v8, v28, v0.t +; RV32-NEXT: vxor.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1661,9 +1661,9 @@ define <8 x i64> @vxor_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vxor.vv v8, v8, v28 +; RV32-NEXT: vxor.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll index 52a9d2bc590ca47522e4c4f7be41f624289bb37f..a49d44455bb8fc683ae85a7c1a6846b9a7c096c0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll @@ -419,18 +419,18 @@ define @insert_nxv4i1_nxv1i1_0( %v, @llvm.experimental.vector.insert.nxv1i1.nxv4i1( %v, %sv, i64 0) ret %vec @@ -440,20 +440,20 @@ define @insert_nxv4i1_nxv1i1_2( %v, @llvm.experimental.vector.insert.nxv1i1.nxv4i1( %v, %sv, i64 2) ret %vec diff --git a/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll index 30fa63f8d1df8c49e668a5e3ed8d6f66d6ed47f6..c2b1a54cdfeac21aecd2179c9acf3eba8ef6da07 100644 --- a/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll @@ -16,9 +16,9 @@ define @insertelt_nxv1f16_imm( %v, half % ; CHECK-LABEL: insertelt_nxv1f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 3 ret %r @@ -28,10 +28,10 @@ define @insertelt_nxv1f16_idx( %v, half % ; CHECK-LABEL: insertelt_nxv1f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 %idx ret %r @@ -51,9 +51,9 @@ define @insertelt_nxv2f16_imm( %v, half % ; CHECK-LABEL: insertelt_nxv2f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 3 ret %r @@ -63,10 +63,10 @@ define @insertelt_nxv2f16_idx( %v, half % ; CHECK-LABEL: insertelt_nxv2f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 %idx ret %r @@ -86,9 +86,9 @@ define @insertelt_nxv4f16_imm( %v, half % ; CHECK-LABEL: insertelt_nxv4f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 3 ret %r @@ -98,10 +98,10 @@ define @insertelt_nxv4f16_idx( %v, half % ; CHECK-LABEL: insertelt_nxv4f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 %idx ret %r @@ -121,9 +121,9 @@ define @insertelt_nxv8f16_imm( %v, half % ; CHECK-LABEL: insertelt_nxv8f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.s.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vsetivli zero, 4, e16, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 3 ret %r @@ -133,10 +133,10 @@ define @insertelt_nxv8f16_idx( %v, half % ; CHECK-LABEL: insertelt_nxv8f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.s.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 %idx ret %r @@ -156,9 +156,9 @@ define @insertelt_nxv16f16_imm( %v, hal ; CHECK-LABEL: insertelt_nxv16f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.s.f v28, fa0 +; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vsetivli zero, 4, e16, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 3 +; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 3 ret %r @@ -168,10 +168,10 @@ define @insertelt_nxv16f16_idx( %v, hal ; CHECK-LABEL: insertelt_nxv16f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.s.f v28, fa0 +; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v28, a0 +; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 %idx ret %r @@ -226,9 +226,9 @@ define @insertelt_nxv1f32_imm( %v, floa ; CHECK-LABEL: insertelt_nxv1f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 3 ret %r @@ -238,10 +238,10 @@ define @insertelt_nxv1f32_idx( %v, floa ; CHECK-LABEL: insertelt_nxv1f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 %idx ret %r @@ -261,9 +261,9 @@ define @insertelt_nxv2f32_imm( %v, floa ; CHECK-LABEL: insertelt_nxv2f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 3 ret %r @@ -273,10 +273,10 @@ define @insertelt_nxv2f32_idx( %v, floa ; CHECK-LABEL: insertelt_nxv2f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 %idx ret %r @@ -296,9 +296,9 @@ define @insertelt_nxv4f32_imm( %v, floa ; CHECK-LABEL: insertelt_nxv4f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.s.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 3 ret %r @@ -308,10 +308,10 @@ define @insertelt_nxv4f32_idx( %v, floa ; CHECK-LABEL: insertelt_nxv4f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.s.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 %idx ret %r @@ -331,9 +331,9 @@ define @insertelt_nxv8f32_imm( %v, floa ; CHECK-LABEL: insertelt_nxv8f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.s.f v28, fa0 +; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 3 +; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 3 ret %r @@ -343,10 +343,10 @@ define @insertelt_nxv8f32_idx( %v, floa ; CHECK-LABEL: insertelt_nxv8f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.s.f v28, fa0 +; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v28, a0 +; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 %idx ret %r @@ -401,9 +401,9 @@ define @insertelt_nxv1f64_imm( %v, do ; CHECK-LABEL: insertelt_nxv1f64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, double %elt, i32 3 ret %r @@ -413,10 +413,10 @@ define @insertelt_nxv1f64_idx( %v, do ; CHECK-LABEL: insertelt_nxv1f64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %r = insertelement %v, double %elt, i32 %idx ret %r @@ -436,9 +436,9 @@ define @insertelt_nxv2f64_imm( %v, do ; CHECK-LABEL: insertelt_nxv2f64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.s.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, double %elt, i32 3 ret %r @@ -448,10 +448,10 @@ define @insertelt_nxv2f64_idx( %v, do ; CHECK-LABEL: insertelt_nxv2f64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.s.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %r = insertelement %v, double %elt, i32 %idx ret %r @@ -471,9 +471,9 @@ define @insertelt_nxv4f64_imm( %v, do ; CHECK-LABEL: insertelt_nxv4f64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.s.f v28, fa0 +; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vsetivli zero, 4, e64, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 3 +; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: ret %r = insertelement %v, double %elt, i32 3 ret %r @@ -483,10 +483,10 @@ define @insertelt_nxv4f64_idx( %v, do ; CHECK-LABEL: insertelt_nxv4f64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.s.f v28, fa0 +; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v28, a0 +; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret %r = insertelement %v, double %elt, i32 %idx ret %r diff --git a/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll index e76dc336941e299673c9e6dca376d27fce676bd1..992d298b2a859fd9667066bda8c7ddbe83d147e0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll @@ -16,9 +16,9 @@ define @insertelt_nxv1f16_imm( %v, half % ; CHECK-LABEL: insertelt_nxv1f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 3 ret %r @@ -28,10 +28,10 @@ define @insertelt_nxv1f16_idx( %v, half % ; CHECK-LABEL: insertelt_nxv1f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 %idx ret %r @@ -51,9 +51,9 @@ define @insertelt_nxv2f16_imm( %v, half % ; CHECK-LABEL: insertelt_nxv2f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 3 ret %r @@ -63,10 +63,10 @@ define @insertelt_nxv2f16_idx( %v, half % ; CHECK-LABEL: insertelt_nxv2f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 %idx ret %r @@ -86,9 +86,9 @@ define @insertelt_nxv4f16_imm( %v, half % ; CHECK-LABEL: insertelt_nxv4f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 3 ret %r @@ -98,10 +98,10 @@ define @insertelt_nxv4f16_idx( %v, half % ; CHECK-LABEL: insertelt_nxv4f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 %idx ret %r @@ -121,9 +121,9 @@ define @insertelt_nxv8f16_imm( %v, half % ; CHECK-LABEL: insertelt_nxv8f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.s.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vsetivli zero, 4, e16, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 3 ret %r @@ -133,10 +133,10 @@ define @insertelt_nxv8f16_idx( %v, half % ; CHECK-LABEL: insertelt_nxv8f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.s.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 %idx ret %r @@ -156,9 +156,9 @@ define @insertelt_nxv16f16_imm( %v, hal ; CHECK-LABEL: insertelt_nxv16f16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.s.f v28, fa0 +; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vsetivli zero, 4, e16, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 3 +; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 3 ret %r @@ -168,10 +168,10 @@ define @insertelt_nxv16f16_idx( %v, hal ; CHECK-LABEL: insertelt_nxv16f16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.s.f v28, fa0 +; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v28, a0 +; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret %r = insertelement %v, half %elt, i32 %idx ret %r @@ -226,9 +226,9 @@ define @insertelt_nxv1f32_imm( %v, floa ; CHECK-LABEL: insertelt_nxv1f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 3 ret %r @@ -238,10 +238,10 @@ define @insertelt_nxv1f32_idx( %v, floa ; CHECK-LABEL: insertelt_nxv1f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 %idx ret %r @@ -261,9 +261,9 @@ define @insertelt_nxv2f32_imm( %v, floa ; CHECK-LABEL: insertelt_nxv2f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 3 ret %r @@ -273,10 +273,10 @@ define @insertelt_nxv2f32_idx( %v, floa ; CHECK-LABEL: insertelt_nxv2f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 %idx ret %r @@ -296,9 +296,9 @@ define @insertelt_nxv4f32_imm( %v, floa ; CHECK-LABEL: insertelt_nxv4f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.s.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 3 ret %r @@ -308,10 +308,10 @@ define @insertelt_nxv4f32_idx( %v, floa ; CHECK-LABEL: insertelt_nxv4f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.s.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 %idx ret %r @@ -331,9 +331,9 @@ define @insertelt_nxv8f32_imm( %v, floa ; CHECK-LABEL: insertelt_nxv8f32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.s.f v28, fa0 +; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 3 +; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 3 ret %r @@ -343,10 +343,10 @@ define @insertelt_nxv8f32_idx( %v, floa ; CHECK-LABEL: insertelt_nxv8f32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.s.f v28, fa0 +; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v28, a0 +; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret %r = insertelement %v, float %elt, i32 %idx ret %r @@ -401,9 +401,9 @@ define @insertelt_nxv1f64_imm( %v, do ; CHECK-LABEL: insertelt_nxv1f64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, double %elt, i32 3 ret %r @@ -413,10 +413,10 @@ define @insertelt_nxv1f64_idx( %v, do ; CHECK-LABEL: insertelt_nxv1f64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.s.f v25, fa0 +; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %r = insertelement %v, double %elt, i32 %idx ret %r @@ -436,9 +436,9 @@ define @insertelt_nxv2f64_imm( %v, do ; CHECK-LABEL: insertelt_nxv2f64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.s.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, double %elt, i32 3 ret %r @@ -448,10 +448,10 @@ define @insertelt_nxv2f64_idx( %v, do ; CHECK-LABEL: insertelt_nxv2f64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.s.f v26, fa0 +; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %r = insertelement %v, double %elt, i32 %idx ret %r @@ -471,9 +471,9 @@ define @insertelt_nxv4f64_imm( %v, do ; CHECK-LABEL: insertelt_nxv4f64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.s.f v28, fa0 +; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vsetivli zero, 4, e64, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 3 +; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: ret %r = insertelement %v, double %elt, i32 3 ret %r @@ -483,10 +483,10 @@ define @insertelt_nxv4f64_idx( %v, do ; CHECK-LABEL: insertelt_nxv4f64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.s.f v28, fa0 +; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v28, a0 +; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret %r = insertelement %v, double %elt, i32 %idx ret %r diff --git a/llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll b/llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll index f9290c5abf0e414fc1c8733e97b93a12dbe0b10f..cbe815d3b31bc7dc81d88fb22dc103a6f8f7a1e5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll +++ b/llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll @@ -6,14 +6,14 @@ define @insertelt_nxv1i1( %x, i1 %elt) { ; CHECK-LABEL: insertelt_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vsetivli zero, 3, e8, mf8, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 2 +; CHECK-NEXT: vslideup.vi v9, v8, 2 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vand.vi v25, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement %x, i1 %elt, i64 2 ret %y @@ -23,15 +23,15 @@ define @insertelt_idx_nxv1i1( %x, i1 %elt, i6 ; CHECK-LABEL: insertelt_idx_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu -; CHECK-NEXT: vslideup.vx v26, v25, a1 +; CHECK-NEXT: vslideup.vx v9, v8, a1 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vand.vi v25, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement %x, i1 %elt, i64 %idx ret %y @@ -41,14 +41,14 @@ define @insertelt_nxv2i1( %x, i1 %elt) { ; CHECK-LABEL: insertelt_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vsetivli zero, 3, e8, mf4, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 2 +; CHECK-NEXT: vslideup.vi v9, v8, 2 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vand.vi v25, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement %x, i1 %elt, i64 2 ret %y @@ -58,15 +58,15 @@ define @insertelt_idx_nxv2i1( %x, i1 %elt, i6 ; CHECK-LABEL: insertelt_idx_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu -; CHECK-NEXT: vslideup.vx v26, v25, a1 +; CHECK-NEXT: vslideup.vx v9, v8, a1 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vand.vi v25, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement %x, i1 %elt, i64 %idx ret %y @@ -76,14 +76,14 @@ define @insertelt_nxv4i1( %x, i1 %elt) { ; CHECK-LABEL: insertelt_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 2 +; CHECK-NEXT: vslideup.vi v9, v8, 2 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vand.vi v25, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement %x, i1 %elt, i64 2 ret %y @@ -93,15 +93,15 @@ define @insertelt_idx_nxv4i1( %x, i1 %elt, i6 ; CHECK-LABEL: insertelt_idx_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vx v26, v25, a1 +; CHECK-NEXT: vslideup.vx v9, v8, a1 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vand.vi v25, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement %x, i1 %elt, i64 %idx ret %y @@ -111,14 +111,14 @@ define @insertelt_nxv8i1( %x, i1 %elt) { ; CHECK-LABEL: insertelt_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vsetivli zero, 3, e8, m1, tu, mu -; CHECK-NEXT: vslideup.vi v26, v25, 2 +; CHECK-NEXT: vslideup.vi v9, v8, 2 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement %x, i1 %elt, i64 2 ret %y @@ -128,15 +128,15 @@ define @insertelt_idx_nxv8i1( %x, i1 %elt, i6 ; CHECK-LABEL: insertelt_idx_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu -; CHECK-NEXT: vslideup.vx v26, v25, a1 +; CHECK-NEXT: vslideup.vx v9, v8, a1 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement %x, i1 %elt, i64 %idx ret %y @@ -146,14 +146,14 @@ define @insertelt_nxv16i1( %x, i1 %elt) { ; CHECK-LABEL: insertelt_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v28, v28, 1, v0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v10, 0 +; CHECK-NEXT: vmerge.vim v10, v10, 1, v0 ; CHECK-NEXT: vsetivli zero, 3, e8, m2, tu, mu -; CHECK-NEXT: vslideup.vi v28, v26, 2 +; CHECK-NEXT: vslideup.vi v10, v8, 2 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vand.vi v26, v28, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vand.vi v8, v10, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement %x, i1 %elt, i64 2 ret %y @@ -163,15 +163,15 @@ define @insertelt_idx_nxv16i1( %x, i1 %elt, ; CHECK-LABEL: insertelt_idx_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v28, v28, 1, v0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v10, 0 +; CHECK-NEXT: vmerge.vim v10, v10, 1, v0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu -; CHECK-NEXT: vslideup.vx v28, v26, a1 +; CHECK-NEXT: vslideup.vx v10, v8, a1 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vand.vi v26, v28, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vand.vi v8, v10, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement %x, i1 %elt, i64 %idx ret %y @@ -181,14 +181,14 @@ define @insertelt_nxv32i1( %x, i1 %elt) { ; CHECK-LABEL: insertelt_nxv32i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 -; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v12, 0 +; CHECK-NEXT: vmerge.vim v12, v12, 1, v0 ; CHECK-NEXT: vsetivli zero, 3, e8, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 2 +; CHECK-NEXT: vslideup.vi v12, v8, 2 ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vand.vi v28, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vand.vi v8, v12, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement %x, i1 %elt, i64 2 ret %y @@ -198,15 +198,15 @@ define @insertelt_idx_nxv32i1( %x, i1 %elt, ; CHECK-LABEL: insertelt_idx_nxv32i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 -; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vmv.v.i v12, 0 +; CHECK-NEXT: vmerge.vim v12, v12, 1, v0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v28, a1 +; CHECK-NEXT: vslideup.vx v12, v8, a1 ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vand.vi v28, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vand.vi v8, v12, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %y = insertelement %x, i1 %elt, i64 %idx ret %y diff --git a/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll index bdc4f2e48d57a36883f4319982701e928b19956f..e2db8c1ee3ecf3a185fe2ed8911ea5e759f99550 100644 --- a/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll @@ -16,9 +16,9 @@ define @insertelt_nxv1i8_imm( %v, i8 signext ; CHECK-LABEL: insertelt_nxv1i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf8, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 3 ret %r @@ -28,10 +28,10 @@ define @insertelt_nxv1i8_idx( %v, i8 signext ; CHECK-LABEL: insertelt_nxv1i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 %idx ret %r @@ -51,9 +51,9 @@ define @insertelt_nxv2i8_imm( %v, i8 signext ; CHECK-LABEL: insertelt_nxv2i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 3 ret %r @@ -63,10 +63,10 @@ define @insertelt_nxv2i8_idx( %v, i8 signext ; CHECK-LABEL: insertelt_nxv2i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 %idx ret %r @@ -86,9 +86,9 @@ define @insertelt_nxv4i8_imm( %v, i8 signext ; CHECK-LABEL: insertelt_nxv4i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 3 ret %r @@ -98,10 +98,10 @@ define @insertelt_nxv4i8_idx( %v, i8 signext ; CHECK-LABEL: insertelt_nxv4i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 %idx ret %r @@ -121,9 +121,9 @@ define @insertelt_nxv8i8_imm( %v, i8 signext ; CHECK-LABEL: insertelt_nxv8i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 3 ret %r @@ -133,10 +133,10 @@ define @insertelt_nxv8i8_idx( %v, i8 signext ; CHECK-LABEL: insertelt_nxv8i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 %idx ret %r @@ -156,9 +156,9 @@ define @insertelt_nxv16i8_imm( %v, i8 signe ; CHECK-LABEL: insertelt_nxv16i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 3 ret %r @@ -168,10 +168,10 @@ define @insertelt_nxv16i8_idx( %v, i8 signe ; CHECK-LABEL: insertelt_nxv16i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a1 +; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 %idx ret %r @@ -191,9 +191,9 @@ define @insertelt_nxv32i8_imm( %v, i8 signe ; CHECK-LABEL: insertelt_nxv32i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 +; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 3 +; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 3 ret %r @@ -203,10 +203,10 @@ define @insertelt_nxv32i8_idx( %v, i8 signe ; CHECK-LABEL: insertelt_nxv32i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 +; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v28, a1 +; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 %idx ret %r @@ -261,9 +261,9 @@ define @insertelt_nxv1i16_imm( %v, i16 sign ; CHECK-LABEL: insertelt_nxv1i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 3 ret %r @@ -273,10 +273,10 @@ define @insertelt_nxv1i16_idx( %v, i16 sign ; CHECK-LABEL: insertelt_nxv1i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 %idx ret %r @@ -296,9 +296,9 @@ define @insertelt_nxv2i16_imm( %v, i16 sign ; CHECK-LABEL: insertelt_nxv2i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 3 ret %r @@ -308,10 +308,10 @@ define @insertelt_nxv2i16_idx( %v, i16 sign ; CHECK-LABEL: insertelt_nxv2i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 %idx ret %r @@ -331,9 +331,9 @@ define @insertelt_nxv4i16_imm( %v, i16 sign ; CHECK-LABEL: insertelt_nxv4i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 3 ret %r @@ -343,10 +343,10 @@ define @insertelt_nxv4i16_idx( %v, i16 sign ; CHECK-LABEL: insertelt_nxv4i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 %idx ret %r @@ -366,9 +366,9 @@ define @insertelt_nxv8i16_imm( %v, i16 sign ; CHECK-LABEL: insertelt_nxv8i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 3 ret %r @@ -378,10 +378,10 @@ define @insertelt_nxv8i16_idx( %v, i16 sign ; CHECK-LABEL: insertelt_nxv8i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a1 +; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 %idx ret %r @@ -401,9 +401,9 @@ define @insertelt_nxv16i16_imm( %v, i16 s ; CHECK-LABEL: insertelt_nxv16i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 +; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 3 +; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 3 ret %r @@ -413,10 +413,10 @@ define @insertelt_nxv16i16_idx( %v, i16 s ; CHECK-LABEL: insertelt_nxv16i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 +; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v28, a1 +; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 %idx ret %r @@ -471,9 +471,9 @@ define @insertelt_nxv1i32_imm( %v, i32 %elt ; CHECK-LABEL: insertelt_nxv1i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 3 ret %r @@ -483,10 +483,10 @@ define @insertelt_nxv1i32_idx( %v, i32 %elt ; CHECK-LABEL: insertelt_nxv1i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 %idx ret %r @@ -506,9 +506,9 @@ define @insertelt_nxv2i32_imm( %v, i32 %elt ; CHECK-LABEL: insertelt_nxv2i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 3 ret %r @@ -518,10 +518,10 @@ define @insertelt_nxv2i32_idx( %v, i32 %elt ; CHECK-LABEL: insertelt_nxv2i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 %idx ret %r @@ -541,9 +541,9 @@ define @insertelt_nxv4i32_imm( %v, i32 %elt ; CHECK-LABEL: insertelt_nxv4i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 3 ret %r @@ -553,10 +553,10 @@ define @insertelt_nxv4i32_idx( %v, i32 %elt ; CHECK-LABEL: insertelt_nxv4i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a1 +; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 %idx ret %r @@ -576,9 +576,9 @@ define @insertelt_nxv8i32_imm( %v, i32 %elt ; CHECK-LABEL: insertelt_nxv8i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 +; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 3 +; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 3 ret %r @@ -588,10 +588,10 @@ define @insertelt_nxv8i32_idx( %v, i32 %elt ; CHECK-LABEL: insertelt_nxv8i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 +; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v28, a1 +; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 %idx ret %r @@ -636,11 +636,11 @@ define @insertelt_nxv1i64_0( %v, i64 %elt) ; CHECK-LABEL: insertelt_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vslide1up.vx v26, v25, a1 -; CHECK-NEXT: vslide1up.vx v25, v26, a0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vslide1up.vx v10, v9, a1 +; CHECK-NEXT: vslide1up.vx v9, v10, a0 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 0 +; CHECK-NEXT: vslideup.vi v8, v9, 0 ; CHECK-NEXT: ret %r = insertelement %v, i64 %elt, i32 0 ret %r @@ -650,11 +650,11 @@ define @insertelt_nxv1i64_imm( %v, i64 %elt ; CHECK-LABEL: insertelt_nxv1i64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vslide1up.vx v26, v25, a1 -; CHECK-NEXT: vslide1up.vx v25, v26, a0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vslide1up.vx v10, v9, a1 +; CHECK-NEXT: vslide1up.vx v9, v10, a0 ; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i64 %elt, i32 3 ret %r @@ -664,12 +664,12 @@ define @insertelt_nxv1i64_idx( %v, i64 %elt ; CHECK-LABEL: insertelt_nxv1i64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vslide1up.vx v26, v25, a1 -; CHECK-NEXT: vslide1up.vx v25, v26, a0 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vslide1up.vx v10, v9, a1 +; CHECK-NEXT: vslide1up.vx v9, v10, a0 ; CHECK-NEXT: addi a0, a2, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a2 +; CHECK-NEXT: vslideup.vx v8, v9, a2 ; CHECK-NEXT: ret %r = insertelement %v, i64 %elt, i32 %idx ret %r @@ -679,11 +679,11 @@ define @insertelt_nxv2i64_0( %v, i64 %elt) ; CHECK-LABEL: insertelt_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vslide1up.vx v28, v26, a1 -; CHECK-NEXT: vslide1up.vx v26, v28, a0 +; CHECK-NEXT: vmv.v.i v10, 0 +; CHECK-NEXT: vslide1up.vx v12, v10, a1 +; CHECK-NEXT: vslide1up.vx v10, v12, a0 ; CHECK-NEXT: vsetivli zero, 1, e64, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 0 +; CHECK-NEXT: vslideup.vi v8, v10, 0 ; CHECK-NEXT: ret %r = insertelement %v, i64 %elt, i32 0 ret %r @@ -693,11 +693,11 @@ define @insertelt_nxv2i64_imm( %v, i64 %elt ; CHECK-LABEL: insertelt_nxv2i64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vslide1up.vx v28, v26, a1 -; CHECK-NEXT: vslide1up.vx v26, v28, a0 +; CHECK-NEXT: vmv.v.i v10, 0 +; CHECK-NEXT: vslide1up.vx v12, v10, a1 +; CHECK-NEXT: vslide1up.vx v10, v12, a0 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, i64 %elt, i32 3 ret %r @@ -707,12 +707,12 @@ define @insertelt_nxv2i64_idx( %v, i64 %elt ; CHECK-LABEL: insertelt_nxv2i64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vslide1up.vx v28, v26, a1 -; CHECK-NEXT: vslide1up.vx v26, v28, a0 +; CHECK-NEXT: vmv.v.i v10, 0 +; CHECK-NEXT: vslide1up.vx v12, v10, a1 +; CHECK-NEXT: vslide1up.vx v10, v12, a0 ; CHECK-NEXT: addi a0, a2, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a2 +; CHECK-NEXT: vslideup.vx v8, v10, a2 ; CHECK-NEXT: ret %r = insertelement %v, i64 %elt, i32 %idx ret %r @@ -722,11 +722,11 @@ define @insertelt_nxv4i64_0( %v, i64 %elt) ; CHECK-LABEL: insertelt_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vslide1up.vx v12, v28, a1 -; CHECK-NEXT: vslide1up.vx v28, v12, a0 +; CHECK-NEXT: vmv.v.i v12, 0 +; CHECK-NEXT: vslide1up.vx v16, v12, a1 +; CHECK-NEXT: vslide1up.vx v12, v16, a0 ; CHECK-NEXT: vsetivli zero, 1, e64, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 0 +; CHECK-NEXT: vslideup.vi v8, v12, 0 ; CHECK-NEXT: ret %r = insertelement %v, i64 %elt, i32 0 ret %r @@ -736,11 +736,11 @@ define @insertelt_nxv4i64_imm( %v, i64 %elt ; CHECK-LABEL: insertelt_nxv4i64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vslide1up.vx v12, v28, a1 -; CHECK-NEXT: vslide1up.vx v28, v12, a0 +; CHECK-NEXT: vmv.v.i v12, 0 +; CHECK-NEXT: vslide1up.vx v16, v12, a1 +; CHECK-NEXT: vslide1up.vx v12, v16, a0 ; CHECK-NEXT: vsetivli zero, 4, e64, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 3 +; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: ret %r = insertelement %v, i64 %elt, i32 3 ret %r @@ -750,12 +750,12 @@ define @insertelt_nxv4i64_idx( %v, i64 %elt ; CHECK-LABEL: insertelt_nxv4i64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vslide1up.vx v12, v28, a1 -; CHECK-NEXT: vslide1up.vx v28, v12, a0 +; CHECK-NEXT: vmv.v.i v12, 0 +; CHECK-NEXT: vslide1up.vx v16, v12, a1 +; CHECK-NEXT: vslide1up.vx v12, v16, a0 ; CHECK-NEXT: addi a0, a2, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v28, a2 +; CHECK-NEXT: vslideup.vx v8, v12, a2 ; CHECK-NEXT: ret %r = insertelement %v, i64 %elt, i32 %idx ret %r @@ -821,9 +821,9 @@ define @insertelt_nxv2i64_imm_c10( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 10 ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, i64 10, i32 3 ret %r @@ -834,10 +834,10 @@ define @insertelt_nxv2i64_idx_c10( %v, i32 ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, 10 ; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a1 +; CHECK-NEXT: vmv.s.x v10, a1 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %r = insertelement %v, i64 10, i32 %idx ret %r @@ -859,9 +859,9 @@ define @insertelt_nxv2i64_imm_cn1( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -1 ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, i64 -1, i32 3 ret %r @@ -872,10 +872,10 @@ define @insertelt_nxv2i64_idx_cn1( %v, i32 ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, zero, -1 ; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a1 +; CHECK-NEXT: vmv.s.x v10, a1 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %r = insertelement %v, i64 -1, i32 %idx ret %r diff --git a/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll index 8f07f9c1353f4cd9e3a4bf880f4ed0e8c5acf6ef..926aa8b09582b4cd11c44d70067867a3bd87d67d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll @@ -16,9 +16,9 @@ define @insertelt_nxv1i8_imm( %v, i8 signext ; CHECK-LABEL: insertelt_nxv1i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf8, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 3 ret %r @@ -28,10 +28,10 @@ define @insertelt_nxv1i8_idx( %v, i8 signext ; CHECK-LABEL: insertelt_nxv1i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 %idx ret %r @@ -51,9 +51,9 @@ define @insertelt_nxv2i8_imm( %v, i8 signext ; CHECK-LABEL: insertelt_nxv2i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 3 ret %r @@ -63,10 +63,10 @@ define @insertelt_nxv2i8_idx( %v, i8 signext ; CHECK-LABEL: insertelt_nxv2i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 %idx ret %r @@ -86,9 +86,9 @@ define @insertelt_nxv4i8_imm( %v, i8 signext ; CHECK-LABEL: insertelt_nxv4i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 3 ret %r @@ -98,10 +98,10 @@ define @insertelt_nxv4i8_idx( %v, i8 signext ; CHECK-LABEL: insertelt_nxv4i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 %idx ret %r @@ -121,9 +121,9 @@ define @insertelt_nxv8i8_imm( %v, i8 signext ; CHECK-LABEL: insertelt_nxv8i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 3 ret %r @@ -133,10 +133,10 @@ define @insertelt_nxv8i8_idx( %v, i8 signext ; CHECK-LABEL: insertelt_nxv8i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 %idx ret %r @@ -156,9 +156,9 @@ define @insertelt_nxv16i8_imm( %v, i8 signe ; CHECK-LABEL: insertelt_nxv16i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 3 ret %r @@ -168,10 +168,10 @@ define @insertelt_nxv16i8_idx( %v, i8 signe ; CHECK-LABEL: insertelt_nxv16i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a1 +; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 %idx ret %r @@ -191,9 +191,9 @@ define @insertelt_nxv32i8_imm( %v, i8 signe ; CHECK-LABEL: insertelt_nxv32i8_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 +; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 3 +; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 3 ret %r @@ -203,10 +203,10 @@ define @insertelt_nxv32i8_idx( %v, i8 signe ; CHECK-LABEL: insertelt_nxv32i8_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 +; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v28, a1 +; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: ret %r = insertelement %v, i8 %elt, i32 %idx ret %r @@ -261,9 +261,9 @@ define @insertelt_nxv1i16_imm( %v, i16 sign ; CHECK-LABEL: insertelt_nxv1i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 3 ret %r @@ -273,10 +273,10 @@ define @insertelt_nxv1i16_idx( %v, i16 sign ; CHECK-LABEL: insertelt_nxv1i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 %idx ret %r @@ -296,9 +296,9 @@ define @insertelt_nxv2i16_imm( %v, i16 sign ; CHECK-LABEL: insertelt_nxv2i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 3 ret %r @@ -308,10 +308,10 @@ define @insertelt_nxv2i16_idx( %v, i16 sign ; CHECK-LABEL: insertelt_nxv2i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 %idx ret %r @@ -331,9 +331,9 @@ define @insertelt_nxv4i16_imm( %v, i16 sign ; CHECK-LABEL: insertelt_nxv4i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 3 ret %r @@ -343,10 +343,10 @@ define @insertelt_nxv4i16_idx( %v, i16 sign ; CHECK-LABEL: insertelt_nxv4i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 %idx ret %r @@ -366,9 +366,9 @@ define @insertelt_nxv8i16_imm( %v, i16 sign ; CHECK-LABEL: insertelt_nxv8i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 3 ret %r @@ -378,10 +378,10 @@ define @insertelt_nxv8i16_idx( %v, i16 sign ; CHECK-LABEL: insertelt_nxv8i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a1 +; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 %idx ret %r @@ -401,9 +401,9 @@ define @insertelt_nxv16i16_imm( %v, i16 s ; CHECK-LABEL: insertelt_nxv16i16_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 +; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vsetivli zero, 4, e16, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 3 +; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 3 ret %r @@ -413,10 +413,10 @@ define @insertelt_nxv16i16_idx( %v, i16 s ; CHECK-LABEL: insertelt_nxv16i16_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 +; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v28, a1 +; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: ret %r = insertelement %v, i16 %elt, i32 %idx ret %r @@ -471,9 +471,9 @@ define @insertelt_nxv1i32_imm( %v, i32 sign ; CHECK-LABEL: insertelt_nxv1i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 3 ret %r @@ -483,10 +483,10 @@ define @insertelt_nxv1i32_idx( %v, i32 sign ; CHECK-LABEL: insertelt_nxv1i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 %idx ret %r @@ -506,9 +506,9 @@ define @insertelt_nxv2i32_imm( %v, i32 sign ; CHECK-LABEL: insertelt_nxv2i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 3 ret %r @@ -518,10 +518,10 @@ define @insertelt_nxv2i32_idx( %v, i32 sign ; CHECK-LABEL: insertelt_nxv2i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a1 +; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 %idx ret %r @@ -541,9 +541,9 @@ define @insertelt_nxv4i32_imm( %v, i32 sign ; CHECK-LABEL: insertelt_nxv4i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 3 ret %r @@ -553,10 +553,10 @@ define @insertelt_nxv4i32_idx( %v, i32 sign ; CHECK-LABEL: insertelt_nxv4i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a1 +; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 %idx ret %r @@ -576,9 +576,9 @@ define @insertelt_nxv8i32_imm( %v, i32 sign ; CHECK-LABEL: insertelt_nxv8i32_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 +; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 3 +; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 3 ret %r @@ -588,10 +588,10 @@ define @insertelt_nxv8i32_idx( %v, i32 sign ; CHECK-LABEL: insertelt_nxv8i32_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 +; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v28, a1 +; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: ret %r = insertelement %v, i32 %elt, i32 %idx ret %r @@ -646,9 +646,9 @@ define @insertelt_nxv1i64_imm( %v, i64 %elt ; CHECK-LABEL: insertelt_nxv1i64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, mu -; CHECK-NEXT: vslideup.vi v8, v25, 3 +; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: ret %r = insertelement %v, i64 %elt, i32 3 ret %r @@ -658,11 +658,11 @@ define @insertelt_nxv1i64_idx( %v, i64 %elt ; CHECK-LABEL: insertelt_nxv1i64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.s.x v25, a0 +; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: sext.w a0, a1 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; CHECK-NEXT: vslideup.vx v8, v25, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %r = insertelement %v, i64 %elt, i32 %idx ret %r @@ -682,9 +682,9 @@ define @insertelt_nxv2i64_imm( %v, i64 %elt ; CHECK-LABEL: insertelt_nxv2i64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu -; CHECK-NEXT: vslideup.vi v8, v26, 3 +; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: ret %r = insertelement %v, i64 %elt, i32 3 ret %r @@ -694,11 +694,11 @@ define @insertelt_nxv2i64_idx( %v, i64 %elt ; CHECK-LABEL: insertelt_nxv2i64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu -; CHECK-NEXT: vmv.s.x v26, a0 +; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: sext.w a0, a1 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; CHECK-NEXT: vslideup.vx v8, v26, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %r = insertelement %v, i64 %elt, i32 %idx ret %r @@ -718,9 +718,9 @@ define @insertelt_nxv4i64_imm( %v, i64 %elt ; CHECK-LABEL: insertelt_nxv4i64_imm: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 +; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vsetivli zero, 4, e64, m4, tu, mu -; CHECK-NEXT: vslideup.vi v8, v28, 3 +; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: ret %r = insertelement %v, i64 %elt, i32 3 ret %r @@ -730,11 +730,11 @@ define @insertelt_nxv4i64_idx( %v, i64 %elt ; CHECK-LABEL: insertelt_nxv4i64_idx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, mu -; CHECK-NEXT: vmv.s.x v28, a0 +; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: sext.w a0, a1 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu -; CHECK-NEXT: vslideup.vx v8, v28, a0 +; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret %r = insertelement %v, i64 %elt, i32 %idx ret %r diff --git a/llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll b/llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll index 7106d797965a6271e5d89ed4b29ba25495fbd701..c696f5106fa47d8d1afc467b39f601506dd2fda1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll +++ b/llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll @@ -7,28 +7,28 @@ define void @interleave256(<256 x i16>* %agg.result, <128 x i16>* %0, <128 x i16 ; RV64-1024: # %bb.0: # %entry ; RV64-1024-NEXT: addi a3, zero, 128 ; RV64-1024-NEXT: vsetvli zero, a3, e16, m2, ta, mu -; RV64-1024-NEXT: vle16.v v8, (a1) -; RV64-1024-NEXT: vle16.v v12, (a2) +; RV64-1024-NEXT: vle16.v v12, (a1) +; RV64-1024-NEXT: vle16.v v16, (a2) ; RV64-1024-NEXT: addi a1, zero, 256 ; RV64-1024-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; RV64-1024-NEXT: vmv.v.i v28, 0 +; RV64-1024-NEXT: vmv.v.i v8, 0 ; RV64-1024-NEXT: vsetvli zero, a3, e16, m4, tu, mu -; RV64-1024-NEXT: vmv4r.v v16, v28 -; RV64-1024-NEXT: vslideup.vi v16, v8, 0 +; RV64-1024-NEXT: vmv4r.v v20, v8 +; RV64-1024-NEXT: vslideup.vi v20, v12, 0 ; RV64-1024-NEXT: vsetvli zero, a3, e16, m2, ta, mu -; RV64-1024-NEXT: vmv.v.i v20, 0 +; RV64-1024-NEXT: vmv.v.i v24, 0 ; RV64-1024-NEXT: vsetvli zero, a1, e16, m4, tu, mu -; RV64-1024-NEXT: vslideup.vx v16, v20, a3 +; RV64-1024-NEXT: vslideup.vx v20, v24, a3 ; RV64-1024-NEXT: vsetvli zero, zero, e16, m4, ta, mu -; RV64-1024-NEXT: vid.v v24 -; RV64-1024-NEXT: vsrl.vi v8, v24, 1 -; RV64-1024-NEXT: vrgather.vv v0, v16, v8 +; RV64-1024-NEXT: vid.v v28 +; RV64-1024-NEXT: vsrl.vi v12, v28, 1 +; RV64-1024-NEXT: vrgather.vv v0, v20, v12 ; RV64-1024-NEXT: vsetvli zero, a3, e16, m4, tu, mu -; RV64-1024-NEXT: vslideup.vi v28, v12, 0 +; RV64-1024-NEXT: vslideup.vi v8, v16, 0 ; RV64-1024-NEXT: vsetvli zero, a1, e16, m4, tu, mu -; RV64-1024-NEXT: vslideup.vx v28, v20, a3 +; RV64-1024-NEXT: vslideup.vx v8, v24, a3 ; RV64-1024-NEXT: vsetvli zero, zero, e16, m4, ta, mu -; RV64-1024-NEXT: vrgather.vv v12, v0, v24 +; RV64-1024-NEXT: vrgather.vv v16, v0, v28 ; RV64-1024-NEXT: lui a2, 1026731 ; RV64-1024-NEXT: addiw a2, a2, -1365 ; RV64-1024-NEXT: slli a2, a2, 12 @@ -38,45 +38,45 @@ define void @interleave256(<256 x i16>* %agg.result, <128 x i16>* %0, <128 x i16 ; RV64-1024-NEXT: slli a2, a2, 12 ; RV64-1024-NEXT: addi a2, a2, -1366 ; RV64-1024-NEXT: vsetivli zero, 4, e64, m1, ta, mu -; RV64-1024-NEXT: vmv.s.x v25, a2 +; RV64-1024-NEXT: vmv.s.x v20, a2 ; RV64-1024-NEXT: vsetivli zero, 2, e64, m1, tu, mu -; RV64-1024-NEXT: vmv1r.v v0, v25 -; RV64-1024-NEXT: vslideup.vi v0, v25, 1 +; RV64-1024-NEXT: vmv1r.v v0, v20 +; RV64-1024-NEXT: vslideup.vi v0, v20, 1 ; RV64-1024-NEXT: vsetivli zero, 3, e64, m1, tu, mu -; RV64-1024-NEXT: vslideup.vi v0, v25, 2 +; RV64-1024-NEXT: vslideup.vi v0, v20, 2 ; RV64-1024-NEXT: vsetivli zero, 4, e64, m1, tu, mu -; RV64-1024-NEXT: vslideup.vi v0, v25, 3 +; RV64-1024-NEXT: vslideup.vi v0, v20, 3 ; RV64-1024-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; RV64-1024-NEXT: vrgather.vv v12, v28, v8, v0.t -; RV64-1024-NEXT: vse16.v v12, (a0) +; RV64-1024-NEXT: vrgather.vv v16, v8, v12, v0.t +; RV64-1024-NEXT: vse16.v v16, (a0) ; RV64-1024-NEXT: ret ; ; RV64-2048-LABEL: interleave256: ; RV64-2048: # %bb.0: # %entry ; RV64-2048-NEXT: addi a3, zero, 128 ; RV64-2048-NEXT: vsetvli zero, a3, e16, m1, ta, mu -; RV64-2048-NEXT: vle16.v v28, (a1) -; RV64-2048-NEXT: vle16.v v30, (a2) +; RV64-2048-NEXT: vle16.v v10, (a1) +; RV64-2048-NEXT: vle16.v v12, (a2) ; RV64-2048-NEXT: addi a1, zero, 256 ; RV64-2048-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; RV64-2048-NEXT: vmv.v.i v26, 0 +; RV64-2048-NEXT: vmv.v.i v8, 0 ; RV64-2048-NEXT: vsetvli zero, a3, e16, m2, tu, mu -; RV64-2048-NEXT: vmv2r.v v8, v26 -; RV64-2048-NEXT: vslideup.vi v8, v28, 0 +; RV64-2048-NEXT: vmv2r.v v14, v8 +; RV64-2048-NEXT: vslideup.vi v14, v10, 0 ; RV64-2048-NEXT: vsetvli zero, a3, e16, m1, ta, mu -; RV64-2048-NEXT: vmv.v.i v10, 0 +; RV64-2048-NEXT: vmv.v.i v16, 0 ; RV64-2048-NEXT: vsetvli zero, a1, e16, m2, tu, mu -; RV64-2048-NEXT: vslideup.vx v8, v10, a3 +; RV64-2048-NEXT: vslideup.vx v14, v16, a3 ; RV64-2048-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; RV64-2048-NEXT: vid.v v12 -; RV64-2048-NEXT: vsrl.vi v28, v12, 1 -; RV64-2048-NEXT: vrgather.vv v14, v8, v28 +; RV64-2048-NEXT: vid.v v18 +; RV64-2048-NEXT: vsrl.vi v10, v18, 1 +; RV64-2048-NEXT: vrgather.vv v20, v14, v10 ; RV64-2048-NEXT: vsetvli zero, a3, e16, m2, tu, mu -; RV64-2048-NEXT: vslideup.vi v26, v30, 0 +; RV64-2048-NEXT: vslideup.vi v8, v12, 0 ; RV64-2048-NEXT: vsetvli zero, a1, e16, m2, tu, mu -; RV64-2048-NEXT: vslideup.vx v26, v10, a3 +; RV64-2048-NEXT: vslideup.vx v8, v16, a3 ; RV64-2048-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; RV64-2048-NEXT: vrgather.vv v30, v14, v12 +; RV64-2048-NEXT: vrgather.vv v12, v20, v18 ; RV64-2048-NEXT: lui a2, 1026731 ; RV64-2048-NEXT: addiw a2, a2, -1365 ; RV64-2048-NEXT: slli a2, a2, 12 @@ -86,17 +86,17 @@ define void @interleave256(<256 x i16>* %agg.result, <128 x i16>* %0, <128 x i16 ; RV64-2048-NEXT: slli a2, a2, 12 ; RV64-2048-NEXT: addi a2, a2, -1366 ; RV64-2048-NEXT: vsetivli zero, 4, e64, m1, ta, mu -; RV64-2048-NEXT: vmv.s.x v25, a2 +; RV64-2048-NEXT: vmv.s.x v14, a2 ; RV64-2048-NEXT: vsetivli zero, 2, e64, m1, tu, mu -; RV64-2048-NEXT: vmv1r.v v0, v25 -; RV64-2048-NEXT: vslideup.vi v0, v25, 1 +; RV64-2048-NEXT: vmv1r.v v0, v14 +; RV64-2048-NEXT: vslideup.vi v0, v14, 1 ; RV64-2048-NEXT: vsetivli zero, 3, e64, m1, tu, mu -; RV64-2048-NEXT: vslideup.vi v0, v25, 2 +; RV64-2048-NEXT: vslideup.vi v0, v14, 2 ; RV64-2048-NEXT: vsetivli zero, 4, e64, m1, tu, mu -; RV64-2048-NEXT: vslideup.vi v0, v25, 3 +; RV64-2048-NEXT: vslideup.vi v0, v14, 3 ; RV64-2048-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; RV64-2048-NEXT: vrgather.vv v30, v26, v28, v0.t -; RV64-2048-NEXT: vse16.v v30, (a0) +; RV64-2048-NEXT: vrgather.vv v12, v8, v10, v0.t +; RV64-2048-NEXT: vse16.v v12, (a0) ; RV64-2048-NEXT: ret entry: %ve = load <128 x i16>, <128 x i16>* %0, align 256 @@ -235,28 +235,28 @@ define void @interleave512(<512 x i16>* %agg.result, <256 x i16>* %0, <256 x i16 ; RV64-2048: # %bb.0: # %entry ; RV64-2048-NEXT: addi a3, zero, 256 ; RV64-2048-NEXT: vsetvli zero, a3, e16, m2, ta, mu -; RV64-2048-NEXT: vle16.v v8, (a1) -; RV64-2048-NEXT: vle16.v v12, (a2) +; RV64-2048-NEXT: vle16.v v12, (a1) +; RV64-2048-NEXT: vle16.v v16, (a2) ; RV64-2048-NEXT: addi a1, zero, 512 ; RV64-2048-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; RV64-2048-NEXT: vmv.v.i v28, 0 +; RV64-2048-NEXT: vmv.v.i v8, 0 ; RV64-2048-NEXT: vsetvli zero, a3, e16, m4, tu, mu -; RV64-2048-NEXT: vmv4r.v v16, v28 -; RV64-2048-NEXT: vslideup.vi v16, v8, 0 +; RV64-2048-NEXT: vmv4r.v v20, v8 +; RV64-2048-NEXT: vslideup.vi v20, v12, 0 ; RV64-2048-NEXT: vsetvli zero, a3, e16, m2, ta, mu -; RV64-2048-NEXT: vmv.v.i v20, 0 +; RV64-2048-NEXT: vmv.v.i v24, 0 ; RV64-2048-NEXT: vsetvli zero, a1, e16, m4, tu, mu -; RV64-2048-NEXT: vslideup.vx v16, v20, a3 +; RV64-2048-NEXT: vslideup.vx v20, v24, a3 ; RV64-2048-NEXT: vsetvli zero, zero, e16, m4, ta, mu -; RV64-2048-NEXT: vid.v v24 -; RV64-2048-NEXT: vsrl.vi v8, v24, 1 -; RV64-2048-NEXT: vrgather.vv v0, v16, v8 +; RV64-2048-NEXT: vid.v v28 +; RV64-2048-NEXT: vsrl.vi v12, v28, 1 +; RV64-2048-NEXT: vrgather.vv v0, v20, v12 ; RV64-2048-NEXT: vsetvli zero, a3, e16, m4, tu, mu -; RV64-2048-NEXT: vslideup.vi v28, v12, 0 +; RV64-2048-NEXT: vslideup.vi v8, v16, 0 ; RV64-2048-NEXT: vsetvli zero, a1, e16, m4, tu, mu -; RV64-2048-NEXT: vslideup.vx v28, v20, a3 +; RV64-2048-NEXT: vslideup.vx v8, v24, a3 ; RV64-2048-NEXT: vsetvli zero, zero, e16, m4, ta, mu -; RV64-2048-NEXT: vrgather.vv v12, v0, v24 +; RV64-2048-NEXT: vrgather.vv v16, v0, v28 ; RV64-2048-NEXT: lui a2, 1026731 ; RV64-2048-NEXT: addiw a2, a2, -1365 ; RV64-2048-NEXT: slli a2, a2, 12 @@ -266,25 +266,25 @@ define void @interleave512(<512 x i16>* %agg.result, <256 x i16>* %0, <256 x i16 ; RV64-2048-NEXT: slli a2, a2, 12 ; RV64-2048-NEXT: addi a2, a2, -1366 ; RV64-2048-NEXT: vsetivli zero, 8, e64, m1, ta, mu -; RV64-2048-NEXT: vmv.s.x v25, a2 +; RV64-2048-NEXT: vmv.s.x v20, a2 ; RV64-2048-NEXT: vsetivli zero, 2, e64, m1, tu, mu -; RV64-2048-NEXT: vmv1r.v v0, v25 -; RV64-2048-NEXT: vslideup.vi v0, v25, 1 +; RV64-2048-NEXT: vmv1r.v v0, v20 +; RV64-2048-NEXT: vslideup.vi v0, v20, 1 ; RV64-2048-NEXT: vsetivli zero, 3, e64, m1, tu, mu -; RV64-2048-NEXT: vslideup.vi v0, v25, 2 +; RV64-2048-NEXT: vslideup.vi v0, v20, 2 ; RV64-2048-NEXT: vsetivli zero, 4, e64, m1, tu, mu -; RV64-2048-NEXT: vslideup.vi v0, v25, 3 +; RV64-2048-NEXT: vslideup.vi v0, v20, 3 ; RV64-2048-NEXT: vsetivli zero, 5, e64, m1, tu, mu -; RV64-2048-NEXT: vslideup.vi v0, v25, 4 +; RV64-2048-NEXT: vslideup.vi v0, v20, 4 ; RV64-2048-NEXT: vsetivli zero, 6, e64, m1, tu, mu -; RV64-2048-NEXT: vslideup.vi v0, v25, 5 +; RV64-2048-NEXT: vslideup.vi v0, v20, 5 ; RV64-2048-NEXT: vsetivli zero, 7, e64, m1, tu, mu -; RV64-2048-NEXT: vslideup.vi v0, v25, 6 +; RV64-2048-NEXT: vslideup.vi v0, v20, 6 ; RV64-2048-NEXT: vsetivli zero, 8, e64, m1, tu, mu -; RV64-2048-NEXT: vslideup.vi v0, v25, 7 +; RV64-2048-NEXT: vslideup.vi v0, v20, 7 ; RV64-2048-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; RV64-2048-NEXT: vrgather.vv v12, v28, v8, v0.t -; RV64-2048-NEXT: vse16.v v12, (a0) +; RV64-2048-NEXT: vrgather.vv v16, v8, v12, v0.t +; RV64-2048-NEXT: vse16.v v16, (a0) ; RV64-2048-NEXT: ret entry: %ve = load <256 x i16>, <256 x i16>* %0, align 512 diff --git a/llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll b/llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll index 466b9031f71bdb4265697fc6be08fef37f54381d..46e1c0a4d8a5ad7aba1e52e04e344252000fca27 100644 --- a/llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll +++ b/llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll @@ -6,9 +6,9 @@ define @trunc_nxv4i32_to_nxv4i5( %a) { ; CHECK-LABEL: trunc_nxv4i32_to_nxv4i5: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %v = trunc %a to ret %v @@ -18,9 +18,9 @@ define @trunc_nxv1i32_to_nxv1i5( %a) { ; CHECK-LABEL: trunc_nxv1i32_to_nxv1i5: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %v = trunc %a to ret %v diff --git a/llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll b/llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll index 7f5986137eeee3e51d8c35e956cfddb374e41648..4d0cf0fae61004053550bab0a3fe24b3d5d006e1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll +++ b/llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll @@ -7,11 +7,11 @@ define void @vadd_vint16m1( *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint16m1: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re16.v v25, (a1) -; CHECK-NEXT: vl1re16.v v26, (a2) +; CHECK-NEXT: vl1re16.v v8, (a1) +; CHECK-NEXT: vl1re16.v v9, (a2) ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: vs1r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -23,11 +23,11 @@ define void @vadd_vint16m1( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint16m2: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2re16.v v26, (a1) -; CHECK-NEXT: vl2re16.v v28, (a2) +; CHECK-NEXT: vl2re16.v v8, (a1) +; CHECK-NEXT: vl2re16.v v10, (a2) ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vadd.vv v26, v26, v28 -; CHECK-NEXT: vs2r.v v26, (a0) +; CHECK-NEXT: vadd.vv v8, v8, v10 +; CHECK-NEXT: vs2r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -39,11 +39,11 @@ define void @vadd_vint16m2( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint16m4: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4re16.v v28, (a1) -; CHECK-NEXT: vl4re16.v v8, (a2) +; CHECK-NEXT: vl4re16.v v8, (a1) +; CHECK-NEXT: vl4re16.v v12, (a2) ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vadd.vv v28, v28, v8 -; CHECK-NEXT: vs4r.v v28, (a0) +; CHECK-NEXT: vadd.vv v8, v8, v12 +; CHECK-NEXT: vs4r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -72,10 +72,10 @@ define void @vadd_vint16mf2( *%pc, *%pa, , * %pa %vb = load , * %pb @@ -88,10 +88,10 @@ define void @vadd_vint16mf4( *%pc, *%pa, , * %pa %vb = load , * %pb diff --git a/llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll b/llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll index 94907718bfaf2bf87e9f4e29228b6095f0b18bfe..73874e2782c16d4bf941e5c52ab13174aef02376 100644 --- a/llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll @@ -7,11 +7,11 @@ define void @vadd_vint32m1( *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint32m1: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re32.v v25, (a1) -; CHECK-NEXT: vl1re32.v v26, (a2) +; CHECK-NEXT: vl1re32.v v8, (a1) +; CHECK-NEXT: vl1re32.v v9, (a2) ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: vs1r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -23,11 +23,11 @@ define void @vadd_vint32m1( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint32m2: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2re32.v v26, (a1) -; CHECK-NEXT: vl2re32.v v28, (a2) +; CHECK-NEXT: vl2re32.v v8, (a1) +; CHECK-NEXT: vl2re32.v v10, (a2) ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vadd.vv v26, v26, v28 -; CHECK-NEXT: vs2r.v v26, (a0) +; CHECK-NEXT: vadd.vv v8, v8, v10 +; CHECK-NEXT: vs2r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -39,11 +39,11 @@ define void @vadd_vint32m2( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint32m4: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4re32.v v28, (a1) -; CHECK-NEXT: vl4re32.v v8, (a2) +; CHECK-NEXT: vl4re32.v v8, (a1) +; CHECK-NEXT: vl4re32.v v12, (a2) ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vadd.vv v28, v28, v8 -; CHECK-NEXT: vs4r.v v28, (a0) +; CHECK-NEXT: vadd.vv v8, v8, v12 +; CHECK-NEXT: vs4r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -72,10 +72,10 @@ define void @vadd_vint32mf2( *%pc, *%pa, , * %pa %vb = load , * %pb diff --git a/llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll b/llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll index ec41245aca7464d63851bc5915adff79992b2204..4edad9c1742e37c4e99d68736cf368290c5eea18 100644 --- a/llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll @@ -7,11 +7,11 @@ define void @vadd_vint64m1( *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint64m1: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re64.v v25, (a1) -; CHECK-NEXT: vl1re64.v v26, (a2) +; CHECK-NEXT: vl1re64.v v8, (a1) +; CHECK-NEXT: vl1re64.v v9, (a2) ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: vs1r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -23,11 +23,11 @@ define void @vadd_vint64m1( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint64m2: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2re64.v v26, (a1) -; CHECK-NEXT: vl2re64.v v28, (a2) +; CHECK-NEXT: vl2re64.v v8, (a1) +; CHECK-NEXT: vl2re64.v v10, (a2) ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vadd.vv v26, v26, v28 -; CHECK-NEXT: vs2r.v v26, (a0) +; CHECK-NEXT: vadd.vv v8, v8, v10 +; CHECK-NEXT: vs2r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -39,11 +39,11 @@ define void @vadd_vint64m2( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint64m4: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4re64.v v28, (a1) -; CHECK-NEXT: vl4re64.v v8, (a2) +; CHECK-NEXT: vl4re64.v v8, (a1) +; CHECK-NEXT: vl4re64.v v12, (a2) ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vadd.vv v28, v28, v8 -; CHECK-NEXT: vs4r.v v28, (a0) +; CHECK-NEXT: vadd.vv v8, v8, v12 +; CHECK-NEXT: vs4r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb diff --git a/llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll b/llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll index 2c3e97f1c11ec156b9fb4c654b5a4a27b03dd099..793c2dc8cdcb539f51e0326e2a4e9a214d5705fa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll +++ b/llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll @@ -7,11 +7,11 @@ define void @vadd_vint8m1( *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint8m1: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1r.v v25, (a1) -; CHECK-NEXT: vl1r.v v26, (a2) +; CHECK-NEXT: vl1r.v v8, (a1) +; CHECK-NEXT: vl1r.v v9, (a2) ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vadd.vv v25, v25, v26 -; CHECK-NEXT: vs1r.v v25, (a0) +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: vs1r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -23,11 +23,11 @@ define void @vadd_vint8m1( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint8m2: ; CHECK: # %bb.0: -; CHECK-NEXT: vl2r.v v26, (a1) -; CHECK-NEXT: vl2r.v v28, (a2) +; CHECK-NEXT: vl2r.v v8, (a1) +; CHECK-NEXT: vl2r.v v10, (a2) ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vadd.vv v26, v26, v28 -; CHECK-NEXT: vs2r.v v26, (a0) +; CHECK-NEXT: vadd.vv v8, v8, v10 +; CHECK-NEXT: vs2r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -39,11 +39,11 @@ define void @vadd_vint8m2( *%pc, *%pa, *%pc, *%pa, *%pb) nounwind { ; CHECK-LABEL: vadd_vint8m4: ; CHECK: # %bb.0: -; CHECK-NEXT: vl4r.v v28, (a1) -; CHECK-NEXT: vl4r.v v8, (a2) +; CHECK-NEXT: vl4r.v v8, (a1) +; CHECK-NEXT: vl4r.v v12, (a2) ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vadd.vv v28, v28, v8 -; CHECK-NEXT: vs4r.v v28, (a0) +; CHECK-NEXT: vadd.vv v8, v8, v12 +; CHECK-NEXT: vs4r.v v8, (a0) ; CHECK-NEXT: ret %va = load , * %pa %vb = load , * %pb @@ -72,10 +72,10 @@ define void @vadd_vint8mf2( *%pc, *%pa, , * %pa %vb = load , * %pb @@ -88,10 +88,10 @@ define void @vadd_vint8mf4( *%pc, *%pa, , * %pa %vb = load , * %pb @@ -104,10 +104,10 @@ define void @vadd_vint8mf8( *%pc, *%pa, , * %pa %vb = load , * %pb diff --git a/llvm/test/CodeGen/RISCV/rvv/load-mask.ll b/llvm/test/CodeGen/RISCV/rvv/load-mask.ll index 34a39527304268f8715c8ce18b614292c94e4d5c..40260611589435171f940d333c2f7476220dd80b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/load-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/load-mask.ll @@ -8,8 +8,8 @@ define void @test_load_mask_64(* %pa, * %pb) ; CHECK-LABEL: test_load_mask_64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load , * %pa store %a, * %pb @@ -20,8 +20,8 @@ define void @test_load_mask_32(* %pa, * %pb) ; CHECK-LABEL: test_load_mask_32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load , * %pa store %a, * %pb @@ -32,8 +32,8 @@ define void @test_load_mask_16(* %pa, * %pb) ; CHECK-LABEL: test_load_mask_16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load , * %pa store %a, * %pb @@ -44,8 +44,8 @@ define void @test_load_mask_8(* %pa, * %pb) { ; CHECK-LABEL: test_load_mask_8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load , * %pa store %a, * %pb @@ -56,8 +56,8 @@ define void @test_load_mask_4(* %pa, * %pb) { ; CHECK-LABEL: test_load_mask_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load , * %pa store %a, * %pb @@ -68,8 +68,8 @@ define void @test_load_mask_2(* %pa, * %pb) { ; CHECK-LABEL: test_load_mask_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load , * %pa store %a, * %pb @@ -80,8 +80,8 @@ define void @test_load_mask_1(* %pa, * %pb) { ; CHECK-LABEL: test_load_mask_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu -; CHECK-NEXT: vlm.v v25, (a0) -; CHECK-NEXT: vsm.v v25, (a1) +; CHECK-NEXT: vlm.v v8, (a0) +; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load , * %pa store %a, * %pb diff --git a/llvm/test/CodeGen/RISCV/rvv/localvar.ll b/llvm/test/CodeGen/RISCV/rvv/localvar.ll index 498ae61c144bf1bde298cbc69f3b910bd2a7b4c5..b42bb522b103c5ffdcfb57d7db9c8cfac522f79d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/localvar.ll +++ b/llvm/test/CodeGen/RISCV/rvv/localvar.ll @@ -14,9 +14,9 @@ define void @local_var_mf8() { ; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: addi a0, a0, 16 -; RV64IV-NEXT: vle8.v v25, (a0) +; RV64IV-NEXT: vle8.v v8, (a0) ; RV64IV-NEXT: addi a0, sp, 16 -; RV64IV-NEXT: vle8.v v25, (a0) +; RV64IV-NEXT: vle8.v v8, (a0) ; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: add sp, sp, a0 @@ -40,9 +40,9 @@ define void @local_var_m1() { ; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: addi a0, a0, 16 -; RV64IV-NEXT: vl1r.v v25, (a0) +; RV64IV-NEXT: vl1r.v v8, (a0) ; RV64IV-NEXT: addi a0, sp, 16 -; RV64IV-NEXT: vl1r.v v25, (a0) +; RV64IV-NEXT: vl1r.v v8, (a0) ; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: add sp, sp, a0 @@ -67,9 +67,9 @@ define void @local_var_m2() { ; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: addi a0, a0, 16 -; RV64IV-NEXT: vl2r.v v26, (a0) +; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: addi a0, sp, 16 -; RV64IV-NEXT: vl2r.v v26, (a0) +; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: add sp, sp, a0 @@ -94,9 +94,9 @@ define void @local_var_m4() { ; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: addi a0, a0, 16 -; RV64IV-NEXT: vl4r.v v28, (a0) +; RV64IV-NEXT: vl4r.v v8, (a0) ; RV64IV-NEXT: addi a0, sp, 16 -; RV64IV-NEXT: vl4r.v v28, (a0) +; RV64IV-NEXT: vl4r.v v8, (a0) ; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: slli a0, a0, 3 ; RV64IV-NEXT: add sp, sp, a0 @@ -149,9 +149,9 @@ define void @local_var_m2_mix_local_scalar() { ; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: addi a0, a0, 32 -; RV64IV-NEXT: vl2r.v v26, (a0) +; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: addi a0, sp, 32 -; RV64IV-NEXT: vl2r.v v26, (a0) +; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: lw a0, 24(sp) ; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: slli a0, a0, 2 @@ -196,12 +196,12 @@ define void @local_var_m2_with_varsize_object(i64 %n) { ; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: sub a0, s0, a0 ; RV64IV-NEXT: addi a0, a0, -32 -; RV64IV-NEXT: vl2r.v v26, (a0) +; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: sub a0, s0, a0 ; RV64IV-NEXT: addi a0, a0, -32 -; RV64IV-NEXT: vl2r.v v26, (a0) +; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: addi sp, s0, -32 ; RV64IV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -249,9 +249,9 @@ define void @local_var_m2_with_bp(i64 %n) { ; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: add a0, s1, a0 ; RV64IV-NEXT: addi a0, a0, 232 -; RV64IV-NEXT: vl2r.v v26, (a0) +; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: addi a0, s1, 232 -; RV64IV-NEXT: vl2r.v v26, (a0) +; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: lw a0, 120(s1) ; RV64IV-NEXT: addi sp, s0, -256 ; RV64IV-NEXT: ld s1, 232(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll index fbb084c2a19a1e3b813140446b6f69ed7fd1c54c..886f2c32b66ca92b296ac27eb98b9c0ff917f603 100644 --- a/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll @@ -5,8 +5,8 @@ define @sext_nxv1i1_nxv1i8( %v) { ; CHECK-LABEL: sext_nxv1i1_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -16,8 +16,8 @@ define @zext_nxv1i1_nxv1i8( %v) { ; CHECK-LABEL: zext_nxv1i1_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -27,8 +27,8 @@ define @trunc_nxv1i8_nxv1i1( %v) { ; CHECK-LABEL: trunc_nxv1i8_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -38,8 +38,8 @@ define @sext_nxv2i1_nxv2i8( %v) { ; CHECK-LABEL: sext_nxv2i1_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -49,8 +49,8 @@ define @zext_nxv2i1_nxv2i8( %v) { ; CHECK-LABEL: zext_nxv2i1_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -60,8 +60,8 @@ define @trunc_nxv2i8_nxv2i1( %v) { ; CHECK-LABEL: trunc_nxv2i8_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -71,8 +71,8 @@ define @sext_nxv4i1_nxv4i8( %v) { ; CHECK-LABEL: sext_nxv4i1_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -82,8 +82,8 @@ define @zext_nxv4i1_nxv4i8( %v) { ; CHECK-LABEL: zext_nxv4i1_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -93,8 +93,8 @@ define @trunc_nxv4i8_nxv4i1( %v) { ; CHECK-LABEL: trunc_nxv4i8_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -104,8 +104,8 @@ define @sext_nxv8i1_nxv8i8( %v) { ; CHECK-LABEL: sext_nxv8i1_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -115,8 +115,8 @@ define @zext_nxv8i1_nxv8i8( %v) { ; CHECK-LABEL: zext_nxv8i1_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -126,8 +126,8 @@ define @trunc_nxv8i8_nxv8i1( %v) { ; CHECK-LABEL: trunc_nxv8i8_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -137,8 +137,8 @@ define @sext_nxv16i1_nxv16i8( %v) { ; CHECK-LABEL: sext_nxv16i1_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -148,8 +148,8 @@ define @zext_nxv16i1_nxv16i8( %v) { ; CHECK-LABEL: zext_nxv16i1_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -159,8 +159,8 @@ define @trunc_nxv16i8_nxv16i1( %v) { ; CHECK-LABEL: trunc_nxv16i8_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vand.vi v26, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -170,8 +170,8 @@ define @sext_nxv32i1_nxv32i8( %v) { ; CHECK-LABEL: sext_nxv32i1_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -181,8 +181,8 @@ define @zext_nxv32i1_nxv32i8( %v) { ; CHECK-LABEL: zext_nxv32i1_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -192,8 +192,8 @@ define @trunc_nxv32i8_nxv32i1( %v) { ; CHECK-LABEL: trunc_nxv32i8_nxv32i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vand.vi v28, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -236,8 +236,8 @@ define @sext_nxv1i1_nxv1i16( %v) { ; CHECK-LABEL: sext_nxv1i1_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -247,8 +247,8 @@ define @zext_nxv1i1_nxv1i16( %v) { ; CHECK-LABEL: zext_nxv1i1_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -258,8 +258,8 @@ define @trunc_nxv1i16_nxv1i1( %v) { ; CHECK-LABEL: trunc_nxv1i16_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -269,8 +269,8 @@ define @sext_nxv2i1_nxv2i16( %v) { ; CHECK-LABEL: sext_nxv2i1_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -280,8 +280,8 @@ define @zext_nxv2i1_nxv2i16( %v) { ; CHECK-LABEL: zext_nxv2i1_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -291,8 +291,8 @@ define @trunc_nxv2i16_nxv2i1( %v) { ; CHECK-LABEL: trunc_nxv2i16_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -302,8 +302,8 @@ define @sext_nxv4i1_nxv4i16( %v) { ; CHECK-LABEL: sext_nxv4i1_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -313,8 +313,8 @@ define @zext_nxv4i1_nxv4i16( %v) { ; CHECK-LABEL: zext_nxv4i1_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -324,8 +324,8 @@ define @trunc_nxv4i16_nxv4i1( %v) { ; CHECK-LABEL: trunc_nxv4i16_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -335,8 +335,8 @@ define @sext_nxv8i1_nxv8i16( %v) { ; CHECK-LABEL: sext_nxv8i1_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -346,8 +346,8 @@ define @zext_nxv8i1_nxv8i16( %v) { ; CHECK-LABEL: zext_nxv8i1_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -357,8 +357,8 @@ define @trunc_nxv8i16_nxv8i1( %v) { ; CHECK-LABEL: trunc_nxv8i16_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vand.vi v26, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -368,8 +368,8 @@ define @sext_nxv16i1_nxv16i16( %v) { ; CHECK-LABEL: sext_nxv16i1_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -379,8 +379,8 @@ define @zext_nxv16i1_nxv16i16( %v) { ; CHECK-LABEL: zext_nxv16i1_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -390,8 +390,8 @@ define @trunc_nxv16i16_nxv16i1( %v) { ; CHECK-LABEL: trunc_nxv16i16_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vand.vi v28, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -434,8 +434,8 @@ define @sext_nxv1i1_nxv1i32( %v) { ; CHECK-LABEL: sext_nxv1i1_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -445,8 +445,8 @@ define @zext_nxv1i1_nxv1i32( %v) { ; CHECK-LABEL: zext_nxv1i1_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -456,8 +456,8 @@ define @trunc_nxv1i32_nxv1i1( %v) { ; CHECK-LABEL: trunc_nxv1i32_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -467,8 +467,8 @@ define @sext_nxv2i1_nxv2i32( %v) { ; CHECK-LABEL: sext_nxv2i1_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -478,8 +478,8 @@ define @zext_nxv2i1_nxv2i32( %v) { ; CHECK-LABEL: zext_nxv2i1_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -489,8 +489,8 @@ define @trunc_nxv2i32_nxv2i1( %v) { ; CHECK-LABEL: trunc_nxv2i32_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -500,8 +500,8 @@ define @sext_nxv4i1_nxv4i32( %v) { ; CHECK-LABEL: sext_nxv4i1_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -511,8 +511,8 @@ define @zext_nxv4i1_nxv4i32( %v) { ; CHECK-LABEL: zext_nxv4i1_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -522,8 +522,8 @@ define @trunc_nxv4i32_nxv4i1( %v) { ; CHECK-LABEL: trunc_nxv4i32_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vand.vi v26, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -533,8 +533,8 @@ define @sext_nxv8i1_nxv8i32( %v) { ; CHECK-LABEL: sext_nxv8i1_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -544,8 +544,8 @@ define @zext_nxv8i1_nxv8i32( %v) { ; CHECK-LABEL: zext_nxv8i1_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -555,8 +555,8 @@ define @trunc_nxv8i32_nxv8i1( %v) { ; CHECK-LABEL: trunc_nxv8i32_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vand.vi v28, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -599,8 +599,8 @@ define @sext_nxv1i1_nxv1i64( %v) { ; CHECK-LABEL: sext_nxv1i1_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -610,8 +610,8 @@ define @zext_nxv1i1_nxv1i64( %v) { ; CHECK-LABEL: zext_nxv1i1_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -621,8 +621,8 @@ define @trunc_nxv1i64_nxv1i1( %v) { ; CHECK-LABEL: trunc_nxv1i64_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -632,8 +632,8 @@ define @sext_nxv2i1_nxv2i64( %v) { ; CHECK-LABEL: sext_nxv2i1_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -643,8 +643,8 @@ define @zext_nxv2i1_nxv2i64( %v) { ; CHECK-LABEL: zext_nxv2i1_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -654,8 +654,8 @@ define @trunc_nxv2i64_nxv2i1( %v) { ; CHECK-LABEL: trunc_nxv2i64_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vand.vi v26, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -665,8 +665,8 @@ define @sext_nxv4i1_nxv4i64( %v) { ; CHECK-LABEL: sext_nxv4i1_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -676,8 +676,8 @@ define @zext_nxv4i1_nxv4i64( %v) { ; CHECK-LABEL: zext_nxv4i1_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -687,8 +687,8 @@ define @trunc_nxv4i64_nxv4i1( %v) { ; CHECK-LABEL: trunc_nxv4i64_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vand.vi v28, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r diff --git a/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll index e524230627423d4e76b8f7deb7ccf1111394ae60..c6801feaf5345350b7b174756860379c64052992 100644 --- a/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll @@ -5,8 +5,8 @@ define @sext_nxv1i1_nxv1i8( %v) { ; CHECK-LABEL: sext_nxv1i1_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -16,8 +16,8 @@ define @zext_nxv1i1_nxv1i8( %v) { ; CHECK-LABEL: zext_nxv1i1_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -27,8 +27,8 @@ define @trunc_nxv1i8_nxv1i1( %v) { ; CHECK-LABEL: trunc_nxv1i8_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -38,8 +38,8 @@ define @sext_nxv2i1_nxv2i8( %v) { ; CHECK-LABEL: sext_nxv2i1_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -49,8 +49,8 @@ define @zext_nxv2i1_nxv2i8( %v) { ; CHECK-LABEL: zext_nxv2i1_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -60,8 +60,8 @@ define @trunc_nxv2i8_nxv2i1( %v) { ; CHECK-LABEL: trunc_nxv2i8_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -71,8 +71,8 @@ define @sext_nxv4i1_nxv4i8( %v) { ; CHECK-LABEL: sext_nxv4i1_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -82,8 +82,8 @@ define @zext_nxv4i1_nxv4i8( %v) { ; CHECK-LABEL: zext_nxv4i1_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -93,8 +93,8 @@ define @trunc_nxv4i8_nxv4i1( %v) { ; CHECK-LABEL: trunc_nxv4i8_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -104,8 +104,8 @@ define @sext_nxv8i1_nxv8i8( %v) { ; CHECK-LABEL: sext_nxv8i1_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -115,8 +115,8 @@ define @zext_nxv8i1_nxv8i8( %v) { ; CHECK-LABEL: zext_nxv8i1_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -126,8 +126,8 @@ define @trunc_nxv8i8_nxv8i1( %v) { ; CHECK-LABEL: trunc_nxv8i8_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -137,8 +137,8 @@ define @sext_nxv16i1_nxv16i8( %v) { ; CHECK-LABEL: sext_nxv16i1_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -148,8 +148,8 @@ define @zext_nxv16i1_nxv16i8( %v) { ; CHECK-LABEL: zext_nxv16i1_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -159,8 +159,8 @@ define @trunc_nxv16i8_nxv16i1( %v) { ; CHECK-LABEL: trunc_nxv16i8_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vand.vi v26, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -170,8 +170,8 @@ define @sext_nxv32i1_nxv32i8( %v) { ; CHECK-LABEL: sext_nxv32i1_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -181,8 +181,8 @@ define @zext_nxv32i1_nxv32i8( %v) { ; CHECK-LABEL: zext_nxv32i1_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -192,8 +192,8 @@ define @trunc_nxv32i8_nxv32i1( %v) { ; CHECK-LABEL: trunc_nxv32i8_nxv32i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vand.vi v28, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -236,8 +236,8 @@ define @sext_nxv1i1_nxv1i16( %v) { ; CHECK-LABEL: sext_nxv1i1_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -247,8 +247,8 @@ define @zext_nxv1i1_nxv1i16( %v) { ; CHECK-LABEL: zext_nxv1i1_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -258,8 +258,8 @@ define @trunc_nxv1i16_nxv1i1( %v) { ; CHECK-LABEL: trunc_nxv1i16_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -269,8 +269,8 @@ define @sext_nxv2i1_nxv2i16( %v) { ; CHECK-LABEL: sext_nxv2i1_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -280,8 +280,8 @@ define @zext_nxv2i1_nxv2i16( %v) { ; CHECK-LABEL: zext_nxv2i1_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -291,8 +291,8 @@ define @trunc_nxv2i16_nxv2i1( %v) { ; CHECK-LABEL: trunc_nxv2i16_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -302,8 +302,8 @@ define @sext_nxv4i1_nxv4i16( %v) { ; CHECK-LABEL: sext_nxv4i1_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -313,8 +313,8 @@ define @zext_nxv4i1_nxv4i16( %v) { ; CHECK-LABEL: zext_nxv4i1_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -324,8 +324,8 @@ define @trunc_nxv4i16_nxv4i1( %v) { ; CHECK-LABEL: trunc_nxv4i16_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -335,8 +335,8 @@ define @sext_nxv8i1_nxv8i16( %v) { ; CHECK-LABEL: sext_nxv8i1_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -346,8 +346,8 @@ define @zext_nxv8i1_nxv8i16( %v) { ; CHECK-LABEL: zext_nxv8i1_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -357,8 +357,8 @@ define @trunc_nxv8i16_nxv8i1( %v) { ; CHECK-LABEL: trunc_nxv8i16_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vand.vi v26, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -368,8 +368,8 @@ define @sext_nxv16i1_nxv16i16( %v) { ; CHECK-LABEL: sext_nxv16i1_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -379,8 +379,8 @@ define @zext_nxv16i1_nxv16i16( %v) { ; CHECK-LABEL: zext_nxv16i1_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -390,8 +390,8 @@ define @trunc_nxv16i16_nxv16i1( %v) { ; CHECK-LABEL: trunc_nxv16i16_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vand.vi v28, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -434,8 +434,8 @@ define @sext_nxv1i1_nxv1i32( %v) { ; CHECK-LABEL: sext_nxv1i1_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -445,8 +445,8 @@ define @zext_nxv1i1_nxv1i32( %v) { ; CHECK-LABEL: zext_nxv1i1_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -456,8 +456,8 @@ define @trunc_nxv1i32_nxv1i1( %v) { ; CHECK-LABEL: trunc_nxv1i32_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -467,8 +467,8 @@ define @sext_nxv2i1_nxv2i32( %v) { ; CHECK-LABEL: sext_nxv2i1_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -478,8 +478,8 @@ define @zext_nxv2i1_nxv2i32( %v) { ; CHECK-LABEL: zext_nxv2i1_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -489,8 +489,8 @@ define @trunc_nxv2i32_nxv2i1( %v) { ; CHECK-LABEL: trunc_nxv2i32_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -500,8 +500,8 @@ define @sext_nxv4i1_nxv4i32( %v) { ; CHECK-LABEL: sext_nxv4i1_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -511,8 +511,8 @@ define @zext_nxv4i1_nxv4i32( %v) { ; CHECK-LABEL: zext_nxv4i1_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -522,8 +522,8 @@ define @trunc_nxv4i32_nxv4i1( %v) { ; CHECK-LABEL: trunc_nxv4i32_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vand.vi v26, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -533,8 +533,8 @@ define @sext_nxv8i1_nxv8i32( %v) { ; CHECK-LABEL: sext_nxv8i1_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -544,8 +544,8 @@ define @zext_nxv8i1_nxv8i32( %v) { ; CHECK-LABEL: zext_nxv8i1_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -555,8 +555,8 @@ define @trunc_nxv8i32_nxv8i1( %v) { ; CHECK-LABEL: trunc_nxv8i32_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vand.vi v28, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -599,8 +599,8 @@ define @sext_nxv1i1_nxv1i64( %v) { ; CHECK-LABEL: sext_nxv1i1_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -610,8 +610,8 @@ define @zext_nxv1i1_nxv1i64( %v) { ; CHECK-LABEL: zext_nxv1i1_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -621,8 +621,8 @@ define @trunc_nxv1i64_nxv1i1( %v) { ; CHECK-LABEL: trunc_nxv1i64_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vand.vi v25, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -632,8 +632,8 @@ define @sext_nxv2i1_nxv2i64( %v) { ; CHECK-LABEL: sext_nxv2i1_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -643,8 +643,8 @@ define @zext_nxv2i1_nxv2i64( %v) { ; CHECK-LABEL: zext_nxv2i1_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -654,8 +654,8 @@ define @trunc_nxv2i64_nxv2i1( %v) { ; CHECK-LABEL: trunc_nxv2i64_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vand.vi v26, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r @@ -665,8 +665,8 @@ define @sext_nxv4i1_nxv4i64( %v) { ; CHECK-LABEL: sext_nxv4i1_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -676,8 +676,8 @@ define @zext_nxv4i1_nxv4i64( %v) { ; CHECK-LABEL: zext_nxv4i1_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -687,8 +687,8 @@ define @trunc_nxv4i64_nxv4i1( %v) { ; CHECK-LABEL: trunc_nxv4i64_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vand.vi v28, v8, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vand.vi v8, v8, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to ret %r diff --git a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir index 74b3c0683111459d372930257135f1c10c249951..9cce462522d6bfd45704f38f7b6da535087f481b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir +++ b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir @@ -17,10 +17,10 @@ body: | ; CHECK: liveins: $v0, $v1, $v2, $v3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 64, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: renamable $v25 = PseudoVMERGE_VIM_M1 killed renamable $v2, 1, killed renamable $v0, 1, 3, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v8 = PseudoVMERGE_VIM_M1 killed renamable $v2, 1, killed renamable $v0, 1, 3, implicit $vl, implicit $vtype ; CHECK-NEXT: renamable $v0 = COPY killed renamable $v1 - ; CHECK-NEXT: renamable $v26 = PseudoVMERGE_VIM_M1 killed renamable $v3, 1, killed renamable $v0, 1, 3, implicit $vl, implicit $vtype - ; CHECK-NEXT: renamable $v0 = PseudoVADD_VV_M1 killed renamable $v25, killed renamable $v26, 1, 3, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v9 = PseudoVMERGE_VIM_M1 killed renamable $v3, 1, killed renamable $v0, 1, 3, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v0 = PseudoVADD_VV_M1 killed renamable $v8, killed renamable $v9, 1, 3, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET implicit $v0 %0:vr = COPY $v0 %1:vr = COPY $v1 diff --git a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll index d10339866583bac259f826bdc2fd813d09c716f1..f53162040c5de7f7bd2c91ed45bc92b63fa209b6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll @@ -134,8 +134,8 @@ define @mgather_nxv2i8_sextload_nxv2i64( %p ; RV32-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; RV32-NEXT: vsext.vf8 v26, v9 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vsext.vf8 v10, v9 +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_nxv2i8_sextload_nxv2i64: @@ -156,8 +156,8 @@ define @mgather_nxv2i8_zextload_nxv2i64( %p ; RV32-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; RV32-NEXT: vzext.vf8 v26, v9 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vzext.vf8 v10, v9 +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_nxv2i8_zextload_nxv2i64: @@ -196,15 +196,15 @@ define @mgather_truemask_nxv4i8( %ptrs, undef, i1 1, i32 0 %mtrue = shufflevector %mhead, undef, zeroinitializer @@ -250,9 +250,9 @@ define @mgather_baseidx_nxv8i8(i8* %base, %i ; RV32-LABEL: mgather_baseidx_nxv8i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v8 +; RV32-NEXT: vsext.vf4 v12, v8 ; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; RV32-NEXT: vluxei32.v v9, (a0), v28, v0.t +; RV32-NEXT: vluxei32.v v9, (a0), v12, v0.t ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; @@ -357,8 +357,8 @@ define @mgather_nxv2i16_sextload_nxv2i64( ; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; RV32-NEXT: vsext.vf4 v26, v9 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vsext.vf4 v10, v9 +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_nxv2i16_sextload_nxv2i64: @@ -379,8 +379,8 @@ define @mgather_nxv2i16_zextload_nxv2i64( ; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; RV32-NEXT: vzext.vf4 v26, v9 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vzext.vf4 v10, v9 +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_nxv2i16_zextload_nxv2i64: @@ -419,15 +419,15 @@ define @mgather_truemask_nxv4i16( %ptrs, < ; RV32-LABEL: mgather_truemask_nxv4i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v10, (zero), v8 +; RV32-NEXT: vmv1r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_nxv4i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v12, (zero), v8 +; RV64-NEXT: vmv1r.v v8, v12 ; RV64-NEXT: ret %mhead = insertelement undef, i1 1, i32 0 %mtrue = shufflevector %mhead, undef, zeroinitializer @@ -473,10 +473,10 @@ define @mgather_baseidx_nxv8i8_nxv8i16(i16* %base, @mgather_baseidx_sext_nxv8i8_nxv8i16(i16* %base, @mgather_baseidx_zext_nxv8i8_nxv8i16(i16* %base, @mgather_baseidx_nxv8i16(i16* %base, @mgather_nxv2i32_sextload_nxv2i64( ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; RV32-NEXT: vsext.vf2 v26, v9 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vsext.vf2 v10, v9 +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_nxv2i32_sextload_nxv2i64: @@ -639,8 +639,8 @@ define @mgather_nxv2i32_zextload_nxv2i64( ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu -; RV32-NEXT: vzext.vf2 v26, v9 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vzext.vf2 v10, v9 +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_nxv2i32_zextload_nxv2i64: @@ -685,8 +685,8 @@ define @mgather_truemask_nxv4i32( %ptrs, < ; RV64-LABEL: mgather_truemask_nxv4i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v26, (zero), v8 -; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: vluxei64.v v12, (zero), v8 +; RV64-NEXT: vmv2r.v v8, v12 ; RV64-NEXT: ret %mhead = insertelement undef, i1 1, i32 0 %mtrue = shufflevector %mhead, undef, zeroinitializer @@ -732,9 +732,9 @@ define @mgather_baseidx_nxv8i8_nxv8i32(i32* %base, @mgather_baseidx_sext_nxv8i8_nxv8i32(i32* %base, @mgather_baseidx_zext_nxv8i8_nxv8i32(i32* %base, @mgather_baseidx_nxv8i16_nxv8i32(i32* %base, @mgather_baseidx_sext_nxv8i16_nxv8i32(i32* %base, @mgather_baseidx_zext_nxv8i16_nxv8i32(i32* %base, @mgather_baseidx_nxv8i32(i32* %base, @mgather_truemask_nxv4i64( %ptrs, < ; RV32-LABEL: mgather_truemask_nxv4i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v28, (zero), v8 -; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: vluxei32.v v12, (zero), v8 +; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_nxv4i64: @@ -1016,10 +1016,10 @@ define @mgather_baseidx_nxv8i8_nxv8i64(i64* %base, @mgather_baseidx_nxv8i16_nxv8i64(i64* %base, @mgather_baseidx_nxv8i32_nxv8i64(i64* %base, @mgather_truemask_nxv4f16( %ptrs, ; RV32-LABEL: mgather_truemask_nxv4f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v10, (zero), v8 +; RV32-NEXT: vmv1r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_nxv4f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v12, (zero), v8 +; RV64-NEXT: vmv1r.v v8, v12 ; RV64-NEXT: ret %mhead = insertelement undef, i1 1, i32 0 %mtrue = shufflevector %mhead, undef, zeroinitializer @@ -1432,10 +1432,10 @@ define @mgather_baseidx_nxv8i8_nxv8f16(half* %base, @mgather_baseidx_sext_nxv8i8_nxv8f16(half* %base, @mgather_baseidx_zext_nxv8i8_nxv8f16(half* %base, @mgather_baseidx_nxv8f16(half* %base, @mgather_truemask_nxv4f32( %ptr ; RV64-LABEL: mgather_truemask_nxv4f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v26, (zero), v8 -; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: vluxei64.v v12, (zero), v8 +; RV64-NEXT: vmv2r.v v8, v12 ; RV64-NEXT: ret %mhead = insertelement undef, i1 1, i32 0 %mtrue = shufflevector %mhead, undef, zeroinitializer @@ -1647,9 +1647,9 @@ define @mgather_baseidx_nxv8i8_nxv8f32(float* %base, @mgather_baseidx_sext_nxv8i8_nxv8f32(float* %base, < ; RV32-LABEL: mgather_baseidx_sext_nxv8i8_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t +; RV32-NEXT: vsext.vf4 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 2 +; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; @@ -1696,9 +1696,9 @@ define @mgather_baseidx_zext_nxv8i8_nxv8f32(float* %base, < ; RV32-LABEL: mgather_baseidx_zext_nxv8i8_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf4 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t +; RV32-NEXT: vzext.vf4 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 2 +; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; @@ -1721,9 +1721,9 @@ define @mgather_baseidx_nxv8i16_nxv8f32(float* %base, @mgather_baseidx_sext_nxv8i16_nxv8f32(float* %base, ; RV32-LABEL: mgather_baseidx_sext_nxv8i16_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t +; RV32-NEXT: vsext.vf2 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 2 +; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; @@ -1770,9 +1770,9 @@ define @mgather_baseidx_zext_nxv8i16_nxv8f32(float* %base, ; RV32-LABEL: mgather_baseidx_zext_nxv8i16_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf2 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vluxei32.v v12, (a0), v28, v0.t +; RV32-NEXT: vzext.vf2 v16, v8 +; RV32-NEXT: vsll.vi v8, v16, 2 +; RV32-NEXT: vluxei32.v v12, (a0), v8, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; @@ -1795,8 +1795,8 @@ define @mgather_baseidx_nxv8f32(float* %base, @mgather_truemask_nxv4f64( %p ; RV32-LABEL: mgather_truemask_nxv4f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v28, (zero), v8 -; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: vluxei32.v v12, (zero), v8 +; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: mgather_truemask_nxv4f64: @@ -1931,10 +1931,10 @@ define @mgather_baseidx_nxv8i8_nxv8f64(double* %base, @mgather_baseidx_nxv8i16_nxv8f64(double* %base, @mgather_baseidx_nxv8i32_nxv8f64(double* %base, @mgather_baseidx_nxv32i8(i8* %base, ; ; RV64-LABEL: mgather_baseidx_nxv32i8: ; RV64: # %bb.0: -; RV64-NEXT: vmv1r.v v25, v0 +; RV64-NEXT: vmv1r.v v16, v0 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu -; RV64-NEXT: vsext.vf8 v16, v8 +; RV64-NEXT: vsext.vf8 v24, v8 ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; RV64-NEXT: vluxei64.v v12, (a0), v16, v0.t +; RV64-NEXT: vluxei64.v v12, (a0), v24, v0.t ; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: srli a2, a1, 3 ; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, mu ; RV64-NEXT: vslidedown.vx v0, v0, a2 ; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, mu -; RV64-NEXT: vsext.vf8 v16, v9 +; RV64-NEXT: vsext.vf8 v24, v9 ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; RV64-NEXT: vluxei64.v v13, (a0), v16, v0.t +; RV64-NEXT: vluxei64.v v13, (a0), v24, v0.t ; RV64-NEXT: srli a1, a1, 2 ; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, mu -; RV64-NEXT: vslidedown.vx v0, v25, a1 +; RV64-NEXT: vslidedown.vx v0, v16, a1 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsext.vf8 v16, v10 ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu diff --git a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll index 80ecb34b0dee9ac3951590a6a1143ba8537b0c92..1301eb9ce74cc0882039de28449b3bf70c1416e4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll @@ -44,15 +44,15 @@ define void @mscatter_nxv2i16_truncstore_nxv2i8( %val, %val to call void @llvm.masked.scatter.nxv2i8.nxv2p0i8( %tval, %ptrs, i32 1, %m) @@ -63,19 +63,19 @@ define void @mscatter_nxv2i32_truncstore_nxv2i8( %val, %val to call void @llvm.masked.scatter.nxv2i8.nxv2p0i8( %tval, %ptrs, i32 1, %m) @@ -86,23 +86,23 @@ define void @mscatter_nxv2i64_truncstore_nxv2i8( %val, %val to call void @llvm.masked.scatter.nxv2i8.nxv2p0i8( %tval, %ptrs, i32 1, %m) @@ -179,9 +179,9 @@ define void @mscatter_baseidx_nxv8i8( %val, i8* %base, %val, %val to call void @llvm.masked.scatter.nxv2i16.nxv2p0i16( %tval, %ptrs, i32 2, %m) @@ -255,19 +255,19 @@ define void @mscatter_nxv2i64_truncstore_nxv2i16( %val, %val to call void @llvm.masked.scatter.nxv2i16.nxv2p0i16( %tval, %ptrs, i32 2, %m) @@ -344,10 +344,10 @@ define void @mscatter_baseidx_nxv8i8_nxv8i16( %val, i16* %base ; RV32-LABEL: mscatter_baseidx_nxv8i8_nxv8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v10 -; RV32-NEXT: vadd.vv v28, v28, v28 +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vadd.vv v12, v12, v12 ; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_nxv8i8_nxv8i16: @@ -367,10 +367,10 @@ define void @mscatter_baseidx_sext_nxv8i8_nxv8i16( %val, i16* ; RV32-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v10 -; RV32-NEXT: vadd.vv v28, v28, v28 +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vadd.vv v12, v12, v12 ; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8i16: @@ -391,10 +391,10 @@ define void @mscatter_baseidx_zext_nxv8i8_nxv8i16( %val, i16* ; RV32-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf4 v28, v10 -; RV32-NEXT: vadd.vv v28, v28, v28 +; RV32-NEXT: vzext.vf4 v12, v10 +; RV32-NEXT: vadd.vv v12, v12, v12 ; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8i16: @@ -415,10 +415,10 @@ define void @mscatter_baseidx_nxv8i16( %val, i16* %base, %val, %val to call void @llvm.masked.scatter.nxv2i32.nxv2p0i32( %tval, %ptrs, i32 4, %m) @@ -559,9 +559,9 @@ define void @mscatter_baseidx_nxv8i8_nxv8i32( %val, i32* %base ; RV32-LABEL: mscatter_baseidx_nxv8i8_nxv8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_nxv8i8_nxv8i32: @@ -581,9 +581,9 @@ define void @mscatter_baseidx_sext_nxv8i8_nxv8i32( %val, i32* ; RV32-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8i32: @@ -604,9 +604,9 @@ define void @mscatter_baseidx_zext_nxv8i8_nxv8i32( %val, i32* ; RV32-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vzext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8i32: @@ -627,9 +627,9 @@ define void @mscatter_baseidx_nxv8i16_nxv8i32( %val, i32* %bas ; RV32-LABEL: mscatter_baseidx_nxv8i16_nxv8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_nxv8i16_nxv8i32: @@ -649,9 +649,9 @@ define void @mscatter_baseidx_sext_nxv8i16_nxv8i32( %val, i32* ; RV32-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8i32: @@ -672,9 +672,9 @@ define void @mscatter_baseidx_zext_nxv8i16_nxv8i32( %val, i32* ; RV32-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vzext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8i32: @@ -695,8 +695,8 @@ define void @mscatter_baseidx_nxv8i32( %val, i32* %base, %val, i64* %base ; RV32-LABEL: mscatter_baseidx_nxv8i8_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v16 -; RV32-NEXT: vsll.vi v28, v28, 3 +; RV32-NEXT: vsext.vf4 v20, v16 +; RV32-NEXT: vsll.vi v16, v20, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_nxv8i8_nxv8i64: @@ -884,10 +884,10 @@ define void @mscatter_baseidx_nxv8i16_nxv8i64( %val, i64* %bas ; RV32-LABEL: mscatter_baseidx_nxv8i16_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v16 -; RV32-NEXT: vsll.vi v28, v28, 3 +; RV32-NEXT: vsext.vf2 v20, v16 +; RV32-NEXT: vsll.vi v16, v20, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_nxv8i16_nxv8i64: @@ -950,9 +950,9 @@ define void @mscatter_baseidx_nxv8i32_nxv8i64( %val, i64* %bas ; RV32-LABEL: mscatter_baseidx_nxv8i32_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsll.vi v28, v16, 3 +; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_nxv8i32_nxv8i64: @@ -1136,10 +1136,10 @@ define void @mscatter_baseidx_nxv8i8_nxv8f16( %val, half* %ba ; RV32-LABEL: mscatter_baseidx_nxv8i8_nxv8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v10 -; RV32-NEXT: vadd.vv v28, v28, v28 +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vadd.vv v12, v12, v12 ; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_nxv8i8_nxv8f16: @@ -1159,10 +1159,10 @@ define void @mscatter_baseidx_sext_nxv8i8_nxv8f16( %val, half ; RV32-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v10 -; RV32-NEXT: vadd.vv v28, v28, v28 +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vadd.vv v12, v12, v12 ; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8f16: @@ -1183,10 +1183,10 @@ define void @mscatter_baseidx_zext_nxv8i8_nxv8f16( %val, half ; RV32-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf4 v28, v10 -; RV32-NEXT: vadd.vv v28, v28, v28 +; RV32-NEXT: vzext.vf4 v12, v10 +; RV32-NEXT: vadd.vv v12, v12, v12 ; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8f16: @@ -1207,10 +1207,10 @@ define void @mscatter_baseidx_nxv8f16( %val, half* %base, %val, float* % ; RV32-LABEL: mscatter_baseidx_nxv8i8_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_nxv8i8_nxv8f32: @@ -1354,9 +1354,9 @@ define void @mscatter_baseidx_sext_nxv8i8_nxv8f32( %val, flo ; RV32-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8f32: @@ -1377,9 +1377,9 @@ define void @mscatter_baseidx_zext_nxv8i8_nxv8f32( %val, flo ; RV32-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vzext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8f32: @@ -1400,9 +1400,9 @@ define void @mscatter_baseidx_nxv8i16_nxv8f32( %val, float* ; RV32-LABEL: mscatter_baseidx_nxv8i16_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_nxv8i16_nxv8f32: @@ -1422,9 +1422,9 @@ define void @mscatter_baseidx_sext_nxv8i16_nxv8f32( %val, fl ; RV32-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_sext_nxv8i16_nxv8f32: @@ -1445,9 +1445,9 @@ define void @mscatter_baseidx_zext_nxv8i16_nxv8f32( %val, fl ; RV32-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vzext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_zext_nxv8i16_nxv8f32: @@ -1468,8 +1468,8 @@ define void @mscatter_baseidx_nxv8f32( %val, float* %base, < ; RV32-LABEL: mscatter_baseidx_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsll.vi v28, v12, 2 -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsll.vi v12, v12, 2 +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_nxv8f32: @@ -1591,10 +1591,10 @@ define void @mscatter_baseidx_nxv8i8_nxv8f64( %val, double* ; RV32-LABEL: mscatter_baseidx_nxv8i8_nxv8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v16 -; RV32-NEXT: vsll.vi v28, v28, 3 +; RV32-NEXT: vsext.vf4 v20, v16 +; RV32-NEXT: vsll.vi v16, v20, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_nxv8i8_nxv8f64: @@ -1657,10 +1657,10 @@ define void @mscatter_baseidx_nxv8i16_nxv8f64( %val, double ; RV32-LABEL: mscatter_baseidx_nxv8i16_nxv8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v16 -; RV32-NEXT: vsll.vi v28, v28, 3 +; RV32-NEXT: vsext.vf2 v20, v16 +; RV32-NEXT: vsll.vi v16, v20, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_nxv8i16_nxv8f64: @@ -1723,9 +1723,9 @@ define void @mscatter_baseidx_nxv8i32_nxv8f64( %val, double ; RV32-LABEL: mscatter_baseidx_nxv8i32_nxv8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; RV32-NEXT: vsll.vi v28, v16, 3 +; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_baseidx_nxv8i32_nxv8f64: @@ -1811,16 +1811,16 @@ declare @llvm.experimental.vector.insert.nxv8p0f64.nxv16 define void @mscatter_nxv16f64( %val0, %val1, %ptrs0, %ptrs1, %m) { ; RV32-LABEL: mscatter_nxv16f64: ; RV32: # %bb.0: -; RV32-NEXT: vl4re32.v v28, (a0) -; RV32-NEXT: vl4re32.v v24, (a1) +; RV32-NEXT: vl4re32.v v24, (a0) +; RV32-NEXT: vl4re32.v v28, (a1) ; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; RV32-NEXT: vsoxei32.v v8, (zero), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (zero), v24, v0.t ; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: srli a0, a0, 3 ; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, mu ; RV32-NEXT: vslidedown.vx v0, v0, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; RV32-NEXT: vsoxei32.v v16, (zero), v24, v0.t +; RV32-NEXT: vsoxei32.v v16, (zero), v28, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: mscatter_nxv16f64: diff --git a/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll index 7ed58d53c5873b60bf6c6654ce178595ddd56d88..78997a99faf9af7e6455ccb7b212cb526d7ec848 100644 --- a/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll +++ b/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll @@ -53,11 +53,11 @@ define @reverse_nxv1i8( %a) { ; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 3 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; RV32-BITS-UNKNOWN-NEXT: vid.v v25 -; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v26, v25, a0 +; RV32-BITS-UNKNOWN-NEXT: vid.v v9 +; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26 -; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25 +; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 +; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 ; RV32-BITS-UNKNOWN-NEXT: ret ; ; RV32-BITS-256-LABEL: reverse_nxv1i8: @@ -66,10 +66,10 @@ define @reverse_nxv1i8( %a) { ; RV32-BITS-256-NEXT: srli a0, a0, 3 ; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; RV32-BITS-256-NEXT: vid.v v25 -; RV32-BITS-256-NEXT: vrsub.vx v26, v25, a0 -; RV32-BITS-256-NEXT: vrgather.vv v25, v8, v26 -; RV32-BITS-256-NEXT: vmv1r.v v8, v25 +; RV32-BITS-256-NEXT: vid.v v9 +; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0 +; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10 +; RV32-BITS-256-NEXT: vmv1r.v v8, v9 ; RV32-BITS-256-NEXT: ret ; ; RV32-BITS-512-LABEL: reverse_nxv1i8: @@ -78,10 +78,10 @@ define @reverse_nxv1i8( %a) { ; RV32-BITS-512-NEXT: srli a0, a0, 3 ; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; RV32-BITS-512-NEXT: vid.v v25 -; RV32-BITS-512-NEXT: vrsub.vx v26, v25, a0 -; RV32-BITS-512-NEXT: vrgather.vv v25, v8, v26 -; RV32-BITS-512-NEXT: vmv1r.v v8, v25 +; RV32-BITS-512-NEXT: vid.v v9 +; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0 +; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10 +; RV32-BITS-512-NEXT: vmv1r.v v8, v9 ; RV32-BITS-512-NEXT: ret ; ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv1i8: @@ -90,11 +90,11 @@ define @reverse_nxv1i8( %a) { ; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 3 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; RV64-BITS-UNKNOWN-NEXT: vid.v v25 -; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v26, v25, a0 +; RV64-BITS-UNKNOWN-NEXT: vid.v v9 +; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26 -; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25 +; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 +; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 ; RV64-BITS-UNKNOWN-NEXT: ret ; ; RV64-BITS-256-LABEL: reverse_nxv1i8: @@ -103,10 +103,10 @@ define @reverse_nxv1i8( %a) { ; RV64-BITS-256-NEXT: srli a0, a0, 3 ; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; RV64-BITS-256-NEXT: vid.v v25 -; RV64-BITS-256-NEXT: vrsub.vx v26, v25, a0 -; RV64-BITS-256-NEXT: vrgather.vv v25, v8, v26 -; RV64-BITS-256-NEXT: vmv1r.v v8, v25 +; RV64-BITS-256-NEXT: vid.v v9 +; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0 +; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10 +; RV64-BITS-256-NEXT: vmv1r.v v8, v9 ; RV64-BITS-256-NEXT: ret ; ; RV64-BITS-512-LABEL: reverse_nxv1i8: @@ -115,10 +115,10 @@ define @reverse_nxv1i8( %a) { ; RV64-BITS-512-NEXT: srli a0, a0, 3 ; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; RV64-BITS-512-NEXT: vid.v v25 -; RV64-BITS-512-NEXT: vrsub.vx v26, v25, a0 -; RV64-BITS-512-NEXT: vrgather.vv v25, v8, v26 -; RV64-BITS-512-NEXT: vmv1r.v v8, v25 +; RV64-BITS-512-NEXT: vid.v v9 +; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0 +; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10 +; RV64-BITS-512-NEXT: vmv1r.v v8, v9 ; RV64-BITS-512-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv1i8( %a) ret %res @@ -131,11 +131,11 @@ define @reverse_nxv2i8( %a) { ; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 2 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; RV32-BITS-UNKNOWN-NEXT: vid.v v25 -; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v26, v25, a0 +; RV32-BITS-UNKNOWN-NEXT: vid.v v9 +; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26 -; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25 +; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 +; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 ; RV32-BITS-UNKNOWN-NEXT: ret ; ; RV32-BITS-256-LABEL: reverse_nxv2i8: @@ -144,10 +144,10 @@ define @reverse_nxv2i8( %a) { ; RV32-BITS-256-NEXT: srli a0, a0, 2 ; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; RV32-BITS-256-NEXT: vid.v v25 -; RV32-BITS-256-NEXT: vrsub.vx v26, v25, a0 -; RV32-BITS-256-NEXT: vrgather.vv v25, v8, v26 -; RV32-BITS-256-NEXT: vmv1r.v v8, v25 +; RV32-BITS-256-NEXT: vid.v v9 +; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0 +; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10 +; RV32-BITS-256-NEXT: vmv1r.v v8, v9 ; RV32-BITS-256-NEXT: ret ; ; RV32-BITS-512-LABEL: reverse_nxv2i8: @@ -156,10 +156,10 @@ define @reverse_nxv2i8( %a) { ; RV32-BITS-512-NEXT: srli a0, a0, 2 ; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; RV32-BITS-512-NEXT: vid.v v25 -; RV32-BITS-512-NEXT: vrsub.vx v26, v25, a0 -; RV32-BITS-512-NEXT: vrgather.vv v25, v8, v26 -; RV32-BITS-512-NEXT: vmv1r.v v8, v25 +; RV32-BITS-512-NEXT: vid.v v9 +; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0 +; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10 +; RV32-BITS-512-NEXT: vmv1r.v v8, v9 ; RV32-BITS-512-NEXT: ret ; ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv2i8: @@ -168,11 +168,11 @@ define @reverse_nxv2i8( %a) { ; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 2 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; RV64-BITS-UNKNOWN-NEXT: vid.v v25 -; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v26, v25, a0 +; RV64-BITS-UNKNOWN-NEXT: vid.v v9 +; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26 -; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25 +; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 +; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 ; RV64-BITS-UNKNOWN-NEXT: ret ; ; RV64-BITS-256-LABEL: reverse_nxv2i8: @@ -181,10 +181,10 @@ define @reverse_nxv2i8( %a) { ; RV64-BITS-256-NEXT: srli a0, a0, 2 ; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; RV64-BITS-256-NEXT: vid.v v25 -; RV64-BITS-256-NEXT: vrsub.vx v26, v25, a0 -; RV64-BITS-256-NEXT: vrgather.vv v25, v8, v26 -; RV64-BITS-256-NEXT: vmv1r.v v8, v25 +; RV64-BITS-256-NEXT: vid.v v9 +; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0 +; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10 +; RV64-BITS-256-NEXT: vmv1r.v v8, v9 ; RV64-BITS-256-NEXT: ret ; ; RV64-BITS-512-LABEL: reverse_nxv2i8: @@ -193,10 +193,10 @@ define @reverse_nxv2i8( %a) { ; RV64-BITS-512-NEXT: srli a0, a0, 2 ; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; RV64-BITS-512-NEXT: vid.v v25 -; RV64-BITS-512-NEXT: vrsub.vx v26, v25, a0 -; RV64-BITS-512-NEXT: vrgather.vv v25, v8, v26 -; RV64-BITS-512-NEXT: vmv1r.v v8, v25 +; RV64-BITS-512-NEXT: vid.v v9 +; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0 +; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10 +; RV64-BITS-512-NEXT: vmv1r.v v8, v9 ; RV64-BITS-512-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv2i8( %a) ret %res @@ -209,11 +209,11 @@ define @reverse_nxv4i8( %a) { ; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; RV32-BITS-UNKNOWN-NEXT: vid.v v25 -; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v26, v25, a0 +; RV32-BITS-UNKNOWN-NEXT: vid.v v9 +; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26 -; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25 +; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 +; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 ; RV32-BITS-UNKNOWN-NEXT: ret ; ; RV32-BITS-256-LABEL: reverse_nxv4i8: @@ -222,10 +222,10 @@ define @reverse_nxv4i8( %a) { ; RV32-BITS-256-NEXT: srli a0, a0, 1 ; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; RV32-BITS-256-NEXT: vid.v v25 -; RV32-BITS-256-NEXT: vrsub.vx v26, v25, a0 -; RV32-BITS-256-NEXT: vrgather.vv v25, v8, v26 -; RV32-BITS-256-NEXT: vmv1r.v v8, v25 +; RV32-BITS-256-NEXT: vid.v v9 +; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0 +; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10 +; RV32-BITS-256-NEXT: vmv1r.v v8, v9 ; RV32-BITS-256-NEXT: ret ; ; RV32-BITS-512-LABEL: reverse_nxv4i8: @@ -234,10 +234,10 @@ define @reverse_nxv4i8( %a) { ; RV32-BITS-512-NEXT: srli a0, a0, 1 ; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; RV32-BITS-512-NEXT: vid.v v25 -; RV32-BITS-512-NEXT: vrsub.vx v26, v25, a0 -; RV32-BITS-512-NEXT: vrgather.vv v25, v8, v26 -; RV32-BITS-512-NEXT: vmv1r.v v8, v25 +; RV32-BITS-512-NEXT: vid.v v9 +; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0 +; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10 +; RV32-BITS-512-NEXT: vmv1r.v v8, v9 ; RV32-BITS-512-NEXT: ret ; ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv4i8: @@ -246,11 +246,11 @@ define @reverse_nxv4i8( %a) { ; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; RV64-BITS-UNKNOWN-NEXT: vid.v v25 -; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v26, v25, a0 +; RV64-BITS-UNKNOWN-NEXT: vid.v v9 +; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26 -; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25 +; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 +; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 ; RV64-BITS-UNKNOWN-NEXT: ret ; ; RV64-BITS-256-LABEL: reverse_nxv4i8: @@ -259,10 +259,10 @@ define @reverse_nxv4i8( %a) { ; RV64-BITS-256-NEXT: srli a0, a0, 1 ; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; RV64-BITS-256-NEXT: vid.v v25 -; RV64-BITS-256-NEXT: vrsub.vx v26, v25, a0 -; RV64-BITS-256-NEXT: vrgather.vv v25, v8, v26 -; RV64-BITS-256-NEXT: vmv1r.v v8, v25 +; RV64-BITS-256-NEXT: vid.v v9 +; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0 +; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10 +; RV64-BITS-256-NEXT: vmv1r.v v8, v9 ; RV64-BITS-256-NEXT: ret ; ; RV64-BITS-512-LABEL: reverse_nxv4i8: @@ -271,10 +271,10 @@ define @reverse_nxv4i8( %a) { ; RV64-BITS-512-NEXT: srli a0, a0, 1 ; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; RV64-BITS-512-NEXT: vid.v v25 -; RV64-BITS-512-NEXT: vrsub.vx v26, v25, a0 -; RV64-BITS-512-NEXT: vrgather.vv v25, v8, v26 -; RV64-BITS-512-NEXT: vmv1r.v v8, v25 +; RV64-BITS-512-NEXT: vid.v v9 +; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0 +; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10 +; RV64-BITS-512-NEXT: vmv1r.v v8, v9 ; RV64-BITS-512-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv4i8( %a) ret %res @@ -286,11 +286,11 @@ define @reverse_nxv8i8( %a) { ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; RV32-BITS-UNKNOWN-NEXT: vid.v v26 -; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v26, v26, a0 +; RV32-BITS-UNKNOWN-NEXT: vid.v v10 +; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0 ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26 -; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25 +; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 +; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 ; RV32-BITS-UNKNOWN-NEXT: ret ; ; RV32-BITS-256-LABEL: reverse_nxv8i8: @@ -298,10 +298,10 @@ define @reverse_nxv8i8( %a) { ; RV32-BITS-256-NEXT: csrr a0, vlenb ; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; RV32-BITS-256-NEXT: vid.v v25 -; RV32-BITS-256-NEXT: vrsub.vx v26, v25, a0 -; RV32-BITS-256-NEXT: vrgather.vv v25, v8, v26 -; RV32-BITS-256-NEXT: vmv1r.v v8, v25 +; RV32-BITS-256-NEXT: vid.v v9 +; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0 +; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10 +; RV32-BITS-256-NEXT: vmv1r.v v8, v9 ; RV32-BITS-256-NEXT: ret ; ; RV32-BITS-512-LABEL: reverse_nxv8i8: @@ -309,10 +309,10 @@ define @reverse_nxv8i8( %a) { ; RV32-BITS-512-NEXT: csrr a0, vlenb ; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; RV32-BITS-512-NEXT: vid.v v25 -; RV32-BITS-512-NEXT: vrsub.vx v26, v25, a0 -; RV32-BITS-512-NEXT: vrgather.vv v25, v8, v26 -; RV32-BITS-512-NEXT: vmv1r.v v8, v25 +; RV32-BITS-512-NEXT: vid.v v9 +; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0 +; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10 +; RV32-BITS-512-NEXT: vmv1r.v v8, v9 ; RV32-BITS-512-NEXT: ret ; ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv8i8: @@ -320,11 +320,11 @@ define @reverse_nxv8i8( %a) { ; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; RV64-BITS-UNKNOWN-NEXT: vid.v v26 -; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v26, v26, a0 +; RV64-BITS-UNKNOWN-NEXT: vid.v v10 +; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0 ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v25, v8, v26 -; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v25 +; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 +; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 ; RV64-BITS-UNKNOWN-NEXT: ret ; ; RV64-BITS-256-LABEL: reverse_nxv8i8: @@ -332,10 +332,10 @@ define @reverse_nxv8i8( %a) { ; RV64-BITS-256-NEXT: csrr a0, vlenb ; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; RV64-BITS-256-NEXT: vid.v v25 -; RV64-BITS-256-NEXT: vrsub.vx v26, v25, a0 -; RV64-BITS-256-NEXT: vrgather.vv v25, v8, v26 -; RV64-BITS-256-NEXT: vmv1r.v v8, v25 +; RV64-BITS-256-NEXT: vid.v v9 +; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0 +; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10 +; RV64-BITS-256-NEXT: vmv1r.v v8, v9 ; RV64-BITS-256-NEXT: ret ; ; RV64-BITS-512-LABEL: reverse_nxv8i8: @@ -343,10 +343,10 @@ define @reverse_nxv8i8( %a) { ; RV64-BITS-512-NEXT: csrr a0, vlenb ; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; RV64-BITS-512-NEXT: vid.v v25 -; RV64-BITS-512-NEXT: vrsub.vx v26, v25, a0 -; RV64-BITS-512-NEXT: vrgather.vv v25, v8, v26 -; RV64-BITS-512-NEXT: vmv1r.v v8, v25 +; RV64-BITS-512-NEXT: vid.v v9 +; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0 +; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10 +; RV64-BITS-512-NEXT: vmv1r.v v8, v9 ; RV64-BITS-512-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv8i8( %a) ret %res @@ -359,11 +359,11 @@ define @reverse_nxv16i8( %a) { ; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; RV32-BITS-UNKNOWN-NEXT: vid.v v28 -; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v28, v28, a0 +; RV32-BITS-UNKNOWN-NEXT: vid.v v12 +; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0 ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, mu -; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v26, v8, v28 -; RV32-BITS-UNKNOWN-NEXT: vmv2r.v v8, v26 +; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12 +; RV32-BITS-UNKNOWN-NEXT: vmv2r.v v8, v10 ; RV32-BITS-UNKNOWN-NEXT: ret ; ; RV32-BITS-256-LABEL: reverse_nxv16i8: @@ -372,10 +372,10 @@ define @reverse_nxv16i8( %a) { ; RV32-BITS-256-NEXT: slli a0, a0, 1 ; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; RV32-BITS-256-NEXT: vid.v v26 -; RV32-BITS-256-NEXT: vrsub.vx v28, v26, a0 -; RV32-BITS-256-NEXT: vrgather.vv v26, v8, v28 -; RV32-BITS-256-NEXT: vmv2r.v v8, v26 +; RV32-BITS-256-NEXT: vid.v v10 +; RV32-BITS-256-NEXT: vrsub.vx v12, v10, a0 +; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v12 +; RV32-BITS-256-NEXT: vmv2r.v v8, v10 ; RV32-BITS-256-NEXT: ret ; ; RV32-BITS-512-LABEL: reverse_nxv16i8: @@ -384,10 +384,10 @@ define @reverse_nxv16i8( %a) { ; RV32-BITS-512-NEXT: slli a0, a0, 1 ; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; RV32-BITS-512-NEXT: vid.v v26 -; RV32-BITS-512-NEXT: vrsub.vx v28, v26, a0 -; RV32-BITS-512-NEXT: vrgather.vv v26, v8, v28 -; RV32-BITS-512-NEXT: vmv2r.v v8, v26 +; RV32-BITS-512-NEXT: vid.v v10 +; RV32-BITS-512-NEXT: vrsub.vx v12, v10, a0 +; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v12 +; RV32-BITS-512-NEXT: vmv2r.v v8, v10 ; RV32-BITS-512-NEXT: ret ; ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv16i8: @@ -396,11 +396,11 @@ define @reverse_nxv16i8( %a) { ; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; RV64-BITS-UNKNOWN-NEXT: vid.v v28 -; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v28, v28, a0 +; RV64-BITS-UNKNOWN-NEXT: vid.v v12 +; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0 ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, mu -; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v26, v8, v28 -; RV64-BITS-UNKNOWN-NEXT: vmv2r.v v8, v26 +; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12 +; RV64-BITS-UNKNOWN-NEXT: vmv2r.v v8, v10 ; RV64-BITS-UNKNOWN-NEXT: ret ; ; RV64-BITS-256-LABEL: reverse_nxv16i8: @@ -409,10 +409,10 @@ define @reverse_nxv16i8( %a) { ; RV64-BITS-256-NEXT: slli a0, a0, 1 ; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; RV64-BITS-256-NEXT: vid.v v26 -; RV64-BITS-256-NEXT: vrsub.vx v28, v26, a0 -; RV64-BITS-256-NEXT: vrgather.vv v26, v8, v28 -; RV64-BITS-256-NEXT: vmv2r.v v8, v26 +; RV64-BITS-256-NEXT: vid.v v10 +; RV64-BITS-256-NEXT: vrsub.vx v12, v10, a0 +; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v12 +; RV64-BITS-256-NEXT: vmv2r.v v8, v10 ; RV64-BITS-256-NEXT: ret ; ; RV64-BITS-512-LABEL: reverse_nxv16i8: @@ -421,10 +421,10 @@ define @reverse_nxv16i8( %a) { ; RV64-BITS-512-NEXT: slli a0, a0, 1 ; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; RV64-BITS-512-NEXT: vid.v v26 -; RV64-BITS-512-NEXT: vrsub.vx v28, v26, a0 -; RV64-BITS-512-NEXT: vrgather.vv v26, v8, v28 -; RV64-BITS-512-NEXT: vmv2r.v v8, v26 +; RV64-BITS-512-NEXT: vid.v v10 +; RV64-BITS-512-NEXT: vrsub.vx v12, v10, a0 +; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v12 +; RV64-BITS-512-NEXT: vmv2r.v v8, v10 ; RV64-BITS-512-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv16i8( %a) ret %res @@ -440,8 +440,8 @@ define @reverse_nxv32i8( %a) { ; RV32-BITS-UNKNOWN-NEXT: vid.v v16 ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0 ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, mu -; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v8, v16 -; RV32-BITS-UNKNOWN-NEXT: vmv4r.v v8, v28 +; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16 +; RV32-BITS-UNKNOWN-NEXT: vmv4r.v v8, v12 ; RV32-BITS-UNKNOWN-NEXT: ret ; ; RV32-BITS-256-LABEL: reverse_nxv32i8: @@ -450,10 +450,10 @@ define @reverse_nxv32i8( %a) { ; RV32-BITS-256-NEXT: slli a0, a0, 2 ; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; RV32-BITS-256-NEXT: vid.v v28 -; RV32-BITS-256-NEXT: vrsub.vx v12, v28, a0 -; RV32-BITS-256-NEXT: vrgather.vv v28, v8, v12 -; RV32-BITS-256-NEXT: vmv4r.v v8, v28 +; RV32-BITS-256-NEXT: vid.v v12 +; RV32-BITS-256-NEXT: vrsub.vx v16, v12, a0 +; RV32-BITS-256-NEXT: vrgather.vv v12, v8, v16 +; RV32-BITS-256-NEXT: vmv4r.v v8, v12 ; RV32-BITS-256-NEXT: ret ; ; RV32-BITS-512-LABEL: reverse_nxv32i8: @@ -462,10 +462,10 @@ define @reverse_nxv32i8( %a) { ; RV32-BITS-512-NEXT: slli a0, a0, 2 ; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; RV32-BITS-512-NEXT: vid.v v28 -; RV32-BITS-512-NEXT: vrsub.vx v12, v28, a0 -; RV32-BITS-512-NEXT: vrgather.vv v28, v8, v12 -; RV32-BITS-512-NEXT: vmv4r.v v8, v28 +; RV32-BITS-512-NEXT: vid.v v12 +; RV32-BITS-512-NEXT: vrsub.vx v16, v12, a0 +; RV32-BITS-512-NEXT: vrgather.vv v12, v8, v16 +; RV32-BITS-512-NEXT: vmv4r.v v8, v12 ; RV32-BITS-512-NEXT: ret ; ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv32i8: @@ -477,8 +477,8 @@ define @reverse_nxv32i8( %a) { ; RV64-BITS-UNKNOWN-NEXT: vid.v v16 ; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0 ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, mu -; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v8, v16 -; RV64-BITS-UNKNOWN-NEXT: vmv4r.v v8, v28 +; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16 +; RV64-BITS-UNKNOWN-NEXT: vmv4r.v v8, v12 ; RV64-BITS-UNKNOWN-NEXT: ret ; ; RV64-BITS-256-LABEL: reverse_nxv32i8: @@ -487,10 +487,10 @@ define @reverse_nxv32i8( %a) { ; RV64-BITS-256-NEXT: slli a0, a0, 2 ; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; RV64-BITS-256-NEXT: vid.v v28 -; RV64-BITS-256-NEXT: vrsub.vx v12, v28, a0 -; RV64-BITS-256-NEXT: vrgather.vv v28, v8, v12 -; RV64-BITS-256-NEXT: vmv4r.v v8, v28 +; RV64-BITS-256-NEXT: vid.v v12 +; RV64-BITS-256-NEXT: vrsub.vx v16, v12, a0 +; RV64-BITS-256-NEXT: vrgather.vv v12, v8, v16 +; RV64-BITS-256-NEXT: vmv4r.v v8, v12 ; RV64-BITS-256-NEXT: ret ; ; RV64-BITS-512-LABEL: reverse_nxv32i8: @@ -499,10 +499,10 @@ define @reverse_nxv32i8( %a) { ; RV64-BITS-512-NEXT: slli a0, a0, 2 ; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; RV64-BITS-512-NEXT: vid.v v28 -; RV64-BITS-512-NEXT: vrsub.vx v12, v28, a0 -; RV64-BITS-512-NEXT: vrgather.vv v28, v8, v12 -; RV64-BITS-512-NEXT: vmv4r.v v8, v28 +; RV64-BITS-512-NEXT: vid.v v12 +; RV64-BITS-512-NEXT: vrsub.vx v16, v12, a0 +; RV64-BITS-512-NEXT: vrgather.vv v12, v8, v16 +; RV64-BITS-512-NEXT: vmv4r.v v8, v12 ; RV64-BITS-512-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv32i8( %a) ret %res @@ -541,10 +541,10 @@ define @reverse_nxv64i8( %a) { ; RV32-BITS-512-NEXT: slli a0, a0, 2 ; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; RV32-BITS-512-NEXT: vid.v v28 -; RV32-BITS-512-NEXT: vrsub.vx v28, v28, a0 -; RV32-BITS-512-NEXT: vrgather.vv v20, v8, v28 -; RV32-BITS-512-NEXT: vrgather.vv v16, v12, v28 +; RV32-BITS-512-NEXT: vid.v v16 +; RV32-BITS-512-NEXT: vrsub.vx v24, v16, a0 +; RV32-BITS-512-NEXT: vrgather.vv v20, v8, v24 +; RV32-BITS-512-NEXT: vrgather.vv v16, v12, v24 ; RV32-BITS-512-NEXT: vmv8r.v v8, v16 ; RV32-BITS-512-NEXT: ret ; @@ -580,10 +580,10 @@ define @reverse_nxv64i8( %a) { ; RV64-BITS-512-NEXT: slli a0, a0, 2 ; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; RV64-BITS-512-NEXT: vid.v v28 -; RV64-BITS-512-NEXT: vrsub.vx v28, v28, a0 -; RV64-BITS-512-NEXT: vrgather.vv v20, v8, v28 -; RV64-BITS-512-NEXT: vrgather.vv v16, v12, v28 +; RV64-BITS-512-NEXT: vid.v v16 +; RV64-BITS-512-NEXT: vrsub.vx v24, v16, a0 +; RV64-BITS-512-NEXT: vrgather.vv v20, v8, v24 +; RV64-BITS-512-NEXT: vrgather.vv v16, v12, v24 ; RV64-BITS-512-NEXT: vmv8r.v v8, v16 ; RV64-BITS-512-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv64i8( %a) @@ -597,10 +597,10 @@ define @reverse_nxv1i16( %a) { ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vx v26, v25, a0 -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vrsub.vx v10, v9, a0 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv1i16( %a) ret %res @@ -613,10 +613,10 @@ define @reverse_nxv2i16( %a) { ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vx v26, v25, a0 -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vrsub.vx v10, v9, a0 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv2i16( %a) ret %res @@ -629,10 +629,10 @@ define @reverse_nxv4i16( %a) { ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vx v26, v25, a0 -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vrsub.vx v10, v9, a0 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv4i16( %a) ret %res @@ -644,10 +644,10 @@ define @reverse_nxv8i16( %a) { ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vid.v v26 -; CHECK-NEXT: vrsub.vx v28, v26, a0 -; CHECK-NEXT: vrgather.vv v26, v8, v28 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vid.v v10 +; CHECK-NEXT: vrsub.vx v12, v10, a0 +; CHECK-NEXT: vrgather.vv v10, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv8i16( %a) ret %res @@ -660,10 +660,10 @@ define @reverse_nxv16i16( %a) { ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vid.v v28 -; CHECK-NEXT: vrsub.vx v12, v28, a0 -; CHECK-NEXT: vrgather.vv v28, v8, v12 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vid.v v12 +; CHECK-NEXT: vrsub.vx v16, v12, a0 +; CHECK-NEXT: vrgather.vv v12, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv16i16( %a) ret %res @@ -692,10 +692,10 @@ define @reverse_nxv1i32( %a) { ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vx v26, v25, a0 -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vrsub.vx v10, v9, a0 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv1i32( %a) ret %res @@ -708,10 +708,10 @@ define @reverse_nxv2i32( %a) { ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vx v26, v25, a0 -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vrsub.vx v10, v9, a0 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv2i32( %a) ret %res @@ -724,10 +724,10 @@ define @reverse_nxv4i32( %a) { ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vid.v v26 -; CHECK-NEXT: vrsub.vx v28, v26, a0 -; CHECK-NEXT: vrgather.vv v26, v8, v28 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vid.v v10 +; CHECK-NEXT: vrsub.vx v12, v10, a0 +; CHECK-NEXT: vrgather.vv v10, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv4i32( %a) ret %res @@ -739,10 +739,10 @@ define @reverse_nxv8i32( %a) { ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vid.v v28 -; CHECK-NEXT: vrsub.vx v12, v28, a0 -; CHECK-NEXT: vrgather.vv v28, v8, v12 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vid.v v12 +; CHECK-NEXT: vrsub.vx v16, v12, a0 +; CHECK-NEXT: vrgather.vv v12, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv8i32( %a) ret %res @@ -771,10 +771,10 @@ define @reverse_nxv1i64( %a) { ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vx v26, v25, a0 -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vrsub.vx v10, v9, a0 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv1i64( %a) ret %res @@ -787,10 +787,10 @@ define @reverse_nxv2i64( %a) { ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vid.v v26 -; CHECK-NEXT: vrsub.vx v28, v26, a0 -; CHECK-NEXT: vrgather.vv v26, v8, v28 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vid.v v10 +; CHECK-NEXT: vrsub.vx v12, v10, a0 +; CHECK-NEXT: vrgather.vv v10, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv2i64( %a) ret %res @@ -803,10 +803,10 @@ define @reverse_nxv4i64( %a) { ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vid.v v28 -; CHECK-NEXT: vrsub.vx v12, v28, a0 -; CHECK-NEXT: vrgather.vv v28, v8, v12 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vid.v v12 +; CHECK-NEXT: vrsub.vx v16, v12, a0 +; CHECK-NEXT: vrgather.vv v12, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv4i64( %a) ret %res @@ -838,10 +838,10 @@ define @reverse_nxv1f16( %a) { ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vx v26, v25, a0 -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vrsub.vx v10, v9, a0 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv1f16( %a) ret %res @@ -854,10 +854,10 @@ define @reverse_nxv2f16( %a) { ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vx v26, v25, a0 -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vrsub.vx v10, v9, a0 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv2f16( %a) ret %res @@ -870,10 +870,10 @@ define @reverse_nxv4f16( %a) { ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vx v26, v25, a0 -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vrsub.vx v10, v9, a0 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv4f16( %a) ret %res @@ -885,10 +885,10 @@ define @reverse_nxv8f16( %a) { ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vid.v v26 -; CHECK-NEXT: vrsub.vx v28, v26, a0 -; CHECK-NEXT: vrgather.vv v26, v8, v28 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vid.v v10 +; CHECK-NEXT: vrsub.vx v12, v10, a0 +; CHECK-NEXT: vrgather.vv v10, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv8f16( %a) ret %res @@ -901,10 +901,10 @@ define @reverse_nxv16f16( %a) { ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vid.v v28 -; CHECK-NEXT: vrsub.vx v12, v28, a0 -; CHECK-NEXT: vrgather.vv v28, v8, v12 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vid.v v12 +; CHECK-NEXT: vrsub.vx v16, v12, a0 +; CHECK-NEXT: vrgather.vv v12, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv16f16( %a) ret %res @@ -933,10 +933,10 @@ define @reverse_nxv1f32( %a) { ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vx v26, v25, a0 -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vrsub.vx v10, v9, a0 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv1f32( %a) ret %res @@ -949,10 +949,10 @@ define @reverse_nxv2f32( %a) { ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vx v26, v25, a0 -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vrsub.vx v10, v9, a0 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv2f32( %a) ret %res @@ -965,10 +965,10 @@ define @reverse_nxv4f32( %a) { ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vid.v v26 -; CHECK-NEXT: vrsub.vx v28, v26, a0 -; CHECK-NEXT: vrgather.vv v26, v8, v28 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vid.v v10 +; CHECK-NEXT: vrsub.vx v12, v10, a0 +; CHECK-NEXT: vrgather.vv v10, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv4f32( %a) ret %res @@ -980,10 +980,10 @@ define @reverse_nxv8f32( %a) { ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vid.v v28 -; CHECK-NEXT: vrsub.vx v12, v28, a0 -; CHECK-NEXT: vrgather.vv v28, v8, v12 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vid.v v12 +; CHECK-NEXT: vrsub.vx v16, v12, a0 +; CHECK-NEXT: vrgather.vv v12, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv8f32( %a) ret %res @@ -1012,10 +1012,10 @@ define @reverse_nxv1f64( %a) { ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vrsub.vx v26, v25, a0 -; CHECK-NEXT: vrgather.vv v25, v8, v26 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: vrsub.vx v10, v9, a0 +; CHECK-NEXT: vrgather.vv v9, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv1f64( %a) ret %res @@ -1028,10 +1028,10 @@ define @reverse_nxv2f64( %a) { ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vid.v v26 -; CHECK-NEXT: vrsub.vx v28, v26, a0 -; CHECK-NEXT: vrgather.vv v26, v8, v28 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vid.v v10 +; CHECK-NEXT: vrsub.vx v12, v10, a0 +; CHECK-NEXT: vrgather.vv v10, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv2f64( %a) ret %res @@ -1044,10 +1044,10 @@ define @reverse_nxv4f64( %a) { ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vid.v v28 -; CHECK-NEXT: vrsub.vx v12, v28, a0 -; CHECK-NEXT: vrgather.vv v28, v8, v12 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vid.v v12 +; CHECK-NEXT: vrsub.vx v16, v12, a0 +; CHECK-NEXT: vrgather.vv v12, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.reverse.nxv4f64( %a) ret %res diff --git a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll index c37a03a7cc56aea789a379d0cf578d781cc228ad..2e4feee53adaba2e695ae96140187f7d9a264996 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll @@ -20,14 +20,14 @@ define @foo( %a, @foo( %a, @foo( %a, @foo( %a, @spill_zvlsseg_nxv1i32(i32* %base, i32 %vl) nounwind { ; SPILL-O0-NEXT: sub sp, sp, a2 ; SPILL-O0-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; SPILL-O0-NEXT: vlseg2e32.v v0, (a0) -; SPILL-O0-NEXT: vmv1r.v v25, v1 +; SPILL-O0-NEXT: vmv1r.v v8, v1 ; SPILL-O0-NEXT: addi a0, sp, 16 -; SPILL-O0-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill +; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; SPILL-O0-NEXT: #APP ; SPILL-O0-NEXT: #NO_APP ; SPILL-O0-NEXT: addi a0, sp, 16 @@ -66,9 +66,9 @@ define @spill_zvlsseg_nxv2i32(i32* %base, i32 %vl) nounwind { ; SPILL-O0-NEXT: sub sp, sp, a2 ; SPILL-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; SPILL-O0-NEXT: vlseg2e32.v v0, (a0) -; SPILL-O0-NEXT: vmv1r.v v25, v1 +; SPILL-O0-NEXT: vmv1r.v v8, v1 ; SPILL-O0-NEXT: addi a0, sp, 16 -; SPILL-O0-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill +; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; SPILL-O0-NEXT: #APP ; SPILL-O0-NEXT: #NO_APP ; SPILL-O0-NEXT: addi a0, sp, 16 @@ -121,9 +121,9 @@ define @spill_zvlsseg_nxv4i32(i32* %base, i32 %vl) nounwind { ; SPILL-O0-NEXT: sub sp, sp, a2 ; SPILL-O0-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; SPILL-O0-NEXT: vlseg2e32.v v0, (a0) -; SPILL-O0-NEXT: vmv2r.v v26, v2 +; SPILL-O0-NEXT: vmv2r.v v8, v2 ; SPILL-O0-NEXT: addi a0, sp, 16 -; SPILL-O0-NEXT: vs2r.v v26, (a0) # Unknown-size Folded Spill +; SPILL-O0-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; SPILL-O0-NEXT: #APP ; SPILL-O0-NEXT: #NO_APP ; SPILL-O0-NEXT: addi a0, sp, 16 @@ -179,9 +179,9 @@ define @spill_zvlsseg_nxv8i32(i32* %base, i32 %vl) nounwind { ; SPILL-O0-NEXT: sub sp, sp, a2 ; SPILL-O0-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; SPILL-O0-NEXT: vlseg2e32.v v0, (a0) -; SPILL-O0-NEXT: vmv4r.v v28, v4 +; SPILL-O0-NEXT: vmv4r.v v8, v4 ; SPILL-O0-NEXT: addi a0, sp, 16 -; SPILL-O0-NEXT: vs4r.v v28, (a0) # Unknown-size Folded Spill +; SPILL-O0-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill ; SPILL-O0-NEXT: #APP ; SPILL-O0-NEXT: #NO_APP ; SPILL-O0-NEXT: addi a0, sp, 16 @@ -237,9 +237,9 @@ define @spill_zvlsseg3_nxv4i32(i32* %base, i32 %vl) nounwind ; SPILL-O0-NEXT: sub sp, sp, a2 ; SPILL-O0-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; SPILL-O0-NEXT: vlseg3e32.v v0, (a0) -; SPILL-O0-NEXT: vmv2r.v v26, v2 +; SPILL-O0-NEXT: vmv2r.v v8, v2 ; SPILL-O0-NEXT: addi a0, sp, 16 -; SPILL-O0-NEXT: vs2r.v v26, (a0) # Unknown-size Folded Spill +; SPILL-O0-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; SPILL-O0-NEXT: #APP ; SPILL-O0-NEXT: #NO_APP ; SPILL-O0-NEXT: addi a0, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll index b14bc1a696b2b2ef51602beb5a8f380b5b73376d..aa8ffefdf930077d400bb5852dd1033116729783 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll @@ -20,14 +20,14 @@ define @foo( %a, @foo( %a, @foo( %a, @foo( %a, @spill_zvlsseg_nxv1i32(i32* %base, i64 %vl) nounwind { ; SPILL-O0-NEXT: sub sp, sp, a2 ; SPILL-O0-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; SPILL-O0-NEXT: vlseg2e32.v v0, (a0) -; SPILL-O0-NEXT: vmv1r.v v25, v1 +; SPILL-O0-NEXT: vmv1r.v v8, v1 ; SPILL-O0-NEXT: addi a0, sp, 16 -; SPILL-O0-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill +; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; SPILL-O0-NEXT: #APP ; SPILL-O0-NEXT: #NO_APP ; SPILL-O0-NEXT: addi a0, sp, 16 @@ -66,9 +66,9 @@ define @spill_zvlsseg_nxv2i32(i32* %base, i64 %vl) nounwind { ; SPILL-O0-NEXT: sub sp, sp, a2 ; SPILL-O0-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; SPILL-O0-NEXT: vlseg2e32.v v0, (a0) -; SPILL-O0-NEXT: vmv1r.v v25, v1 +; SPILL-O0-NEXT: vmv1r.v v8, v1 ; SPILL-O0-NEXT: addi a0, sp, 16 -; SPILL-O0-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill +; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; SPILL-O0-NEXT: #APP ; SPILL-O0-NEXT: #NO_APP ; SPILL-O0-NEXT: addi a0, sp, 16 @@ -121,9 +121,9 @@ define @spill_zvlsseg_nxv4i32(i32* %base, i64 %vl) nounwind { ; SPILL-O0-NEXT: sub sp, sp, a2 ; SPILL-O0-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; SPILL-O0-NEXT: vlseg2e32.v v0, (a0) -; SPILL-O0-NEXT: vmv2r.v v26, v2 +; SPILL-O0-NEXT: vmv2r.v v8, v2 ; SPILL-O0-NEXT: addi a0, sp, 16 -; SPILL-O0-NEXT: vs2r.v v26, (a0) # Unknown-size Folded Spill +; SPILL-O0-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; SPILL-O0-NEXT: #APP ; SPILL-O0-NEXT: #NO_APP ; SPILL-O0-NEXT: addi a0, sp, 16 @@ -179,9 +179,9 @@ define @spill_zvlsseg_nxv8i32(i32* %base, i64 %vl) nounwind { ; SPILL-O0-NEXT: sub sp, sp, a2 ; SPILL-O0-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; SPILL-O0-NEXT: vlseg2e32.v v0, (a0) -; SPILL-O0-NEXT: vmv4r.v v28, v4 +; SPILL-O0-NEXT: vmv4r.v v8, v4 ; SPILL-O0-NEXT: addi a0, sp, 16 -; SPILL-O0-NEXT: vs4r.v v28, (a0) # Unknown-size Folded Spill +; SPILL-O0-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill ; SPILL-O0-NEXT: #APP ; SPILL-O0-NEXT: #NO_APP ; SPILL-O0-NEXT: addi a0, sp, 16 @@ -237,9 +237,9 @@ define @spill_zvlsseg3_nxv4i32(i32* %base, i64 %vl) nounwind ; SPILL-O0-NEXT: sub sp, sp, a2 ; SPILL-O0-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; SPILL-O0-NEXT: vlseg3e32.v v0, (a0) -; SPILL-O0-NEXT: vmv2r.v v26, v2 +; SPILL-O0-NEXT: vmv2r.v v8, v2 ; SPILL-O0-NEXT: addi a0, sp, 16 -; SPILL-O0-NEXT: vs2r.v v26, (a0) # Unknown-size Folded Spill +; SPILL-O0-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; SPILL-O0-NEXT: #APP ; SPILL-O0-NEXT: #NO_APP ; SPILL-O0-NEXT: addi a0, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll index ba7905f9c0f32ca4f9812e564bdced935108d43f..192a5d18c4156228fdd607fab2d6448136703e75 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll @@ -20,13 +20,13 @@ define void @rvv_vla(i64 %n, i64 %i) nounwind { ; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: sub a2, s0, a2 ; CHECK-NEXT: addi a2, a2, -32 -; CHECK-NEXT: vl1re64.v v25, (a2) +; CHECK-NEXT: vl1re64.v v8, (a2) ; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: slli a3, a2, 1 ; CHECK-NEXT: add a2, a3, a2 ; CHECK-NEXT: sub a2, s0, a2 ; CHECK-NEXT: addi a2, a2, -32 -; CHECK-NEXT: vl2re64.v v26, (a2) +; CHECK-NEXT: vl2re64.v v8, (a2) ; CHECK-NEXT: slli a1, a1, 2 ; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: lw a0, 0(a0) @@ -64,9 +64,9 @@ define void @rvv_overaligned() nounwind { ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a0, a0, 112 -; CHECK-NEXT: vl1re64.v v25, (a0) +; CHECK-NEXT: vl1re64.v v8, (a0) ; CHECK-NEXT: addi a0, sp, 112 -; CHECK-NEXT: vl2re64.v v26, (a0) +; CHECK-NEXT: vl2re64.v v8, (a0) ; CHECK-NEXT: lw a0, 64(sp) ; CHECK-NEXT: addi sp, s0, -128 ; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload @@ -108,9 +108,9 @@ define void @rvv_vla_and_overaligned(i64 %n, i64 %i) nounwind { ; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: add a2, s1, a2 ; CHECK-NEXT: addi a2, a2, 104 -; CHECK-NEXT: vl1re64.v v25, (a2) +; CHECK-NEXT: vl1re64.v v8, (a2) ; CHECK-NEXT: addi a2, s1, 104 -; CHECK-NEXT: vl2re64.v v26, (a2) +; CHECK-NEXT: vl2re64.v v8, (a2) ; CHECK-NEXT: lw a2, 64(s1) ; CHECK-NEXT: slli a1, a1, 2 ; CHECK-NEXT: add a0, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll index fe14dd6ea6142251267850cb368a91b07e91a247..e645593810308e44fd5c98a86764477d4b267b27 100644 --- a/llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll @@ -7,10 +7,10 @@ define @saddo_nvx2i32( %x, , } @llvm.sadd.with.overflow.nxv2i32( %x, %y) %b = extractvalue { , } %a, 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/select-fp.ll b/llvm/test/CodeGen/RISCV/rvv/select-fp.ll index 03b919c84f5ec3fc2495266b140bd5548dd0d4fa..361ab5ca97b7d0af863cfd2316901f5f67a1dbce 100644 --- a/llvm/test/CodeGen/RISCV/rvv/select-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/select-fp.ll @@ -10,8 +10,8 @@ define @select_nxv1f16(i1 zeroext %c, %a ; CHECK-LABEL: select_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -24,8 +24,8 @@ define @selectcc_nxv1f16(half %a, half %b, @select_nxv2f16(i1 zeroext %c, %a ; CHECK-LABEL: select_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -52,8 +52,8 @@ define @selectcc_nxv2f16(half %a, half %b, @select_nxv4f16(i1 zeroext %c, %a ; CHECK-LABEL: select_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -80,8 +80,8 @@ define @selectcc_nxv4f16(half %a, half %b, @select_nxv8f16(i1 zeroext %c, %a ; CHECK-LABEL: select_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -108,8 +108,8 @@ define @selectcc_nxv8f16(half %a, half %b, @select_nxv16f16(i1 zeroext %c, ; CHECK-LABEL: select_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret @@ -136,8 +136,8 @@ define @selectcc_nxv16f16(half %a, half %b, @select_nxv32f16(i1 zeroext %c, ; CHECK-LABEL: select_nxv32f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vmsne.vi v0, v24, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret @@ -164,8 +164,8 @@ define @selectcc_nxv32f16(half %a, half %b, @select_nxv1f32(i1 zeroext %c, ; CHECK-LABEL: select_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -192,8 +192,8 @@ define @selectcc_nxv1f32(float %a, float %b, @select_nxv2f32(i1 zeroext %c, ; CHECK-LABEL: select_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -220,8 +220,8 @@ define @selectcc_nxv2f32(float %a, float %b, @select_nxv4f32(i1 zeroext %c, ; CHECK-LABEL: select_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -248,8 +248,8 @@ define @selectcc_nxv4f32(float %a, float %b, @select_nxv8f32(i1 zeroext %c, ; CHECK-LABEL: select_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret @@ -276,8 +276,8 @@ define @selectcc_nxv8f32(float %a, float %b, @select_nxv16f32(i1 zeroext %c, @selectcc_nxv16f32(float %a, float %b, @select_nxv1f64(i1 zeroext %c, @selectcc_nxv1f64(double %a, double %b, @select_nxv2f64(i1 zeroext %c, @selectcc_nxv2f64(double %a, double %b, @select_nxv4f64(i1 zeroext %c, @selectcc_nxv4f64(double %a, double %b, @select_nxv8f64(i1 zeroext %c, @selectcc_nxv8f64(double %a, double %b, @select_nxv1i1(i1 zeroext %c, %a, %a, %b ret %v @@ -24,11 +24,11 @@ define @selectcc_nxv1i1(i1 signext %a, i1 signext %b, %c, %d @@ -39,11 +39,11 @@ define @select_nxv2i1(i1 zeroext %c, %a, %a, %b ret %v @@ -55,11 +55,11 @@ define @selectcc_nxv2i1(i1 signext %a, i1 signext %b, %c, %d @@ -70,11 +70,11 @@ define @select_nxv4i1(i1 zeroext %c, %a, %a, %b ret %v @@ -86,11 +86,11 @@ define @selectcc_nxv4i1(i1 signext %a, i1 signext %b, %c, %d @@ -101,11 +101,11 @@ define @select_nxv8i1(i1 zeroext %c, %a, %a, %b ret %v @@ -117,11 +117,11 @@ define @selectcc_nxv8i1(i1 signext %a, i1 signext %b, %c, %d @@ -132,11 +132,11 @@ define @select_nxv16i1(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsne.vi v25, v26, 0 -; CHECK-NEXT: vmandnot.mm v26, v8, v25 -; CHECK-NEXT: vmand.mm v25, v0, v25 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v9, v10, 0 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select i1 %c, %a, %b ret %v @@ -148,11 +148,11 @@ define @selectcc_nxv16i1(i1 signext %a, i1 signext %b, %c, %d @@ -163,11 +163,11 @@ define @select_nxv32i1(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv32i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsne.vi v25, v28, 0 -; CHECK-NEXT: vmandnot.mm v26, v8, v25 -; CHECK-NEXT: vmand.mm v25, v0, v25 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v9, v12, 0 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select i1 %c, %a, %b ret %v @@ -179,11 +179,11 @@ define @selectcc_nxv32i1(i1 signext %a, i1 signext %b, %c, %d @@ -195,10 +195,10 @@ define @select_nxv64i1(i1 zeroext %c, %a, ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu ; CHECK-NEXT: vmv.v.x v16, a0 -; CHECK-NEXT: vmsne.vi v25, v16, 0 -; CHECK-NEXT: vmandnot.mm v26, v8, v25 -; CHECK-NEXT: vmand.mm v25, v0, v25 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmsne.vi v9, v16, 0 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select i1 %c, %a, %b ret %v @@ -211,10 +211,10 @@ define @selectcc_nxv64i1(i1 signext %a, i1 signext %b, %c, %d @@ -225,8 +225,8 @@ define @select_nxv1i8(i1 zeroext %c, %a, %a, %b @@ -239,8 +239,8 @@ define @selectcc_nxv1i8(i8 signext %a, i8 signext %b, @select_nxv2i8(i1 zeroext %c, %a, %a, %b @@ -266,8 +266,8 @@ define @selectcc_nxv2i8(i8 signext %a, i8 signext %b, @select_nxv4i8(i1 zeroext %c, %a, %a, %b @@ -293,8 +293,8 @@ define @selectcc_nxv4i8(i8 signext %a, i8 signext %b, @select_nxv8i8(i1 zeroext %c, %a, %a, %b @@ -320,8 +320,8 @@ define @selectcc_nxv8i8(i8 signext %a, i8 signext %b, @select_nxv16i8(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %v = select i1 %c, %a, %b @@ -347,8 +347,8 @@ define @selectcc_nxv16i8(i8 signext %a, i8 signext %b, @select_nxv32i8(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %v = select i1 %c, %a, %b @@ -374,8 +374,8 @@ define @selectcc_nxv32i8(i8 signext %a, i8 signext %b, @select_nxv1i16(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -429,8 +429,8 @@ define @selectcc_nxv1i16(i16 signext %a, i16 signext %b, @select_nxv2i16(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -458,8 +458,8 @@ define @selectcc_nxv2i16(i16 signext %a, i16 signext %b, @select_nxv4i16(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -487,8 +487,8 @@ define @selectcc_nxv4i16(i16 signext %a, i16 signext %b, @select_nxv8i16(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -516,8 +516,8 @@ define @selectcc_nxv8i16(i16 signext %a, i16 signext %b, @select_nxv16i16(i1 zeroext %c, % ; CHECK-LABEL: select_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret @@ -545,8 +545,8 @@ define @selectcc_nxv16i16(i16 signext %a, i16 signext %b, @select_nxv32i16(i1 zeroext %c, % ; CHECK-LABEL: select_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vmsne.vi v0, v24, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret @@ -574,8 +574,8 @@ define @selectcc_nxv32i16(i16 signext %a, i16 signext %b, @select_nxv1i32(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -603,8 +603,8 @@ define @selectcc_nxv1i32(i32 signext %a, i32 signext %b, @select_nxv2i32(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -632,8 +632,8 @@ define @selectcc_nxv2i32(i32 signext %a, i32 signext %b, @select_nxv4i32(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -661,8 +661,8 @@ define @selectcc_nxv4i32(i32 signext %a, i32 signext %b, @select_nxv8i32(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret @@ -690,8 +690,8 @@ define @selectcc_nxv8i32(i32 signext %a, i32 signext %b, @select_nxv16i32(i1 zeroext %c, % ; CHECK-LABEL: select_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vmsne.vi v0, v24, 0 ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret @@ -719,8 +719,8 @@ define @selectcc_nxv16i32(i32 signext %a, i32 signext %b, @select_nxv1i64(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret @@ -750,8 +750,8 @@ define @selectcc_nxv1i64(i64 signext %a, i64 signext %b, @selectcc_nxv1i64(i64 signext %a, i64 signext %b, @select_nxv2i64(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret @@ -792,8 +792,8 @@ define @selectcc_nxv2i64(i64 signext %a, i64 signext %b, @selectcc_nxv2i64(i64 signext %a, i64 signext %b, @select_nxv4i64(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret @@ -834,8 +834,8 @@ define @selectcc_nxv4i64(i64 signext %a, i64 signext %b, @selectcc_nxv4i64(i64 signext %a, i64 signext %b, @select_nxv8i64(i1 zeroext %c, %a, ; CHECK-LABEL: select_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v24, a0 +; CHECK-NEXT: vmsne.vi v0, v24, 0 ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret @@ -876,8 +876,8 @@ define @selectcc_nxv8i64(i64 signext %a, i64 signext %b, @selectcc_nxv8i64(i64 signext %a, i64 signext %b, @vselect_of_consts(<4 x i1> %cc) { ; RV32-NEXT: lui a0, 284280 ; RV32-NEXT: addi a0, a0, 291 ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v8, a0 ; RV32-NEXT: lui a0, 214376 ; RV32-NEXT: addi a0, a0, -2030 -; RV32-NEXT: vmerge.vxm v8, v25, a0, v0 +; RV32-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV32-NEXT: ret ; ; RV64-LABEL: vselect_of_consts: @@ -22,10 +22,10 @@ define <4 x i32> @vselect_of_consts(<4 x i1> %cc) { ; RV64-NEXT: lui a0, 284280 ; RV64-NEXT: addiw a0, a0, 291 ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v8, a0 ; RV64-NEXT: lui a0, 214376 ; RV64-NEXT: addiw a0, a0, -2030 -; RV64-NEXT: vmerge.vxm v8, v25, a0, v0 +; RV64-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64-NEXT: ret %v = select <4 x i1> %cc, <4 x i32> , <4 x i32> ret <4 x i32> %v diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll index c4ee90b67ea5a7aa093807085f93ac3428436193..c1c124624f6e112f54b2cfdc28586016b7c177fd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll @@ -289,9 +289,9 @@ define @fcmp_one_vv_nxv8f16( %va, %va, %vb ret %vc @@ -301,9 +301,9 @@ define @fcmp_one_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_one_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmfgt.vf v26, v8, fa0 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmflt.vf v10, v8, fa0 +; CHECK-NEXT: vmfgt.vf v11, v8, fa0 +; CHECK-NEXT: vmor.mm v0, v11, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -315,9 +315,9 @@ define @fcmp_one_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_one_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmflt.vf v26, v8, fa0 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, fa0 +; CHECK-NEXT: vmflt.vf v11, v8, fa0 +; CHECK-NEXT: vmor.mm v0, v11, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -351,9 +351,9 @@ define @fcmp_ord_vv_nxv8f16( %va, %va, %vb ret %vc @@ -363,10 +363,10 @@ define @fcmp_ord_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ord_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfeq.vf v25, v26, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v10, fa0 +; CHECK-NEXT: vmfeq.vf v12, v10, fa0 +; CHECK-NEXT: vmfeq.vv v10, v8, v8 +; CHECK-NEXT: vmand.mm v0, v10, v12 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -378,10 +378,10 @@ define @fcmp_ord_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ord_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfeq.vf v25, v26, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v25, v26 +; CHECK-NEXT: vfmv.v.f v10, fa0 +; CHECK-NEXT: vmfeq.vf v12, v10, fa0 +; CHECK-NEXT: vmfeq.vv v10, v8, v8 +; CHECK-NEXT: vmand.mm v0, v12, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -393,9 +393,9 @@ define @fcmp_ord_vv_nxv8f16_nonans( %va, %va, %vb ret %vc @@ -405,10 +405,10 @@ define @fcmp_ord_vf_nxv8f16_nonans( %va, ha ; CHECK-LABEL: fcmp_ord_vf_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfeq.vf v25, v26, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v10, fa0 +; CHECK-NEXT: vmfeq.vf v12, v10, fa0 +; CHECK-NEXT: vmfeq.vv v10, v8, v8 +; CHECK-NEXT: vmand.mm v0, v10, v12 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -420,9 +420,9 @@ define @fcmp_ueq_vv_nxv8f16( %va, %va, %vb ret %vc @@ -432,9 +432,9 @@ define @fcmp_ueq_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ueq_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmfgt.vf v26, v8, fa0 -; CHECK-NEXT: vmnor.mm v0, v26, v25 +; CHECK-NEXT: vmflt.vf v10, v8, fa0 +; CHECK-NEXT: vmfgt.vf v11, v8, fa0 +; CHECK-NEXT: vmnor.mm v0, v11, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -446,9 +446,9 @@ define @fcmp_ueq_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ueq_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmflt.vf v26, v8, fa0 -; CHECK-NEXT: vmnor.mm v0, v26, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, fa0 +; CHECK-NEXT: vmflt.vf v11, v8, fa0 +; CHECK-NEXT: vmnor.mm v0, v11, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -482,8 +482,8 @@ define @fcmp_ugt_vv_nxv8f16( %va, %va, %vb ret %vc @@ -493,8 +493,8 @@ define @fcmp_ugt_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ugt_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfle.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfle.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -506,8 +506,8 @@ define @fcmp_ugt_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ugt_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfge.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfge.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -541,8 +541,8 @@ define @fcmp_uge_vv_nxv8f16( %va, %va, %vb ret %vc @@ -552,8 +552,8 @@ define @fcmp_uge_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_uge_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmflt.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -565,8 +565,8 @@ define @fcmp_uge_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_uge_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -600,8 +600,8 @@ define @fcmp_ult_vv_nxv8f16( %va, %va, %vb ret %vc @@ -611,8 +611,8 @@ define @fcmp_ult_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ult_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfge.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfge.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -624,8 +624,8 @@ define @fcmp_ult_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ult_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfle.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfle.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -659,8 +659,8 @@ define @fcmp_ule_vv_nxv8f16( %va, %va, %vb ret %vc @@ -670,8 +670,8 @@ define @fcmp_ule_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ule_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -683,8 +683,8 @@ define @fcmp_ule_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ule_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmflt.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -774,9 +774,9 @@ define @fcmp_uno_vv_nxv8f16( %va, %va, %vb ret %vc @@ -786,10 +786,10 @@ define @fcmp_uno_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_uno_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfne.vf v25, v26, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v10, fa0 +; CHECK-NEXT: vmfne.vf v12, v10, fa0 +; CHECK-NEXT: vmfne.vv v10, v8, v8 +; CHECK-NEXT: vmor.mm v0, v10, v12 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -801,10 +801,10 @@ define @fcmp_uno_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_uno_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfne.vf v25, v26, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vfmv.v.f v10, fa0 +; CHECK-NEXT: vmfne.vf v12, v10, fa0 +; CHECK-NEXT: vmfne.vv v10, v8, v8 +; CHECK-NEXT: vmor.mm v0, v12, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -816,9 +816,9 @@ define @fcmp_uno_vv_nxv8f16_nonans( %va, %va, %vb ret %vc @@ -828,10 +828,10 @@ define @fcmp_uno_vf_nxv8f16_nonans( %va, ha ; CHECK-LABEL: fcmp_uno_vf_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfne.vf v25, v26, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v10, fa0 +; CHECK-NEXT: vmfne.vf v12, v10, fa0 +; CHECK-NEXT: vmfne.vv v10, v8, v8 +; CHECK-NEXT: vmor.mm v0, v10, v12 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1123,9 +1123,9 @@ define @fcmp_one_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1135,9 +1135,9 @@ define @fcmp_one_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_one_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmfgt.vf v26, v8, fa0 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmflt.vf v12, v8, fa0 +; CHECK-NEXT: vmfgt.vf v13, v8, fa0 +; CHECK-NEXT: vmor.mm v0, v13, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1149,9 +1149,9 @@ define @fcmp_one_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_one_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmflt.vf v26, v8, fa0 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmfgt.vf v12, v8, fa0 +; CHECK-NEXT: vmflt.vf v13, v8, fa0 +; CHECK-NEXT: vmor.mm v0, v13, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1185,9 +1185,9 @@ define @fcmp_ord_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1197,10 +1197,10 @@ define @fcmp_ord_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ord_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 -; CHECK-NEXT: vmfeq.vf v25, v28, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v12, fa0 +; CHECK-NEXT: vmfeq.vf v16, v12, fa0 +; CHECK-NEXT: vmfeq.vv v12, v8, v8 +; CHECK-NEXT: vmand.mm v0, v12, v16 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1212,10 +1212,10 @@ define @fcmp_ord_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ord_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 -; CHECK-NEXT: vmfeq.vf v25, v28, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v25, v26 +; CHECK-NEXT: vfmv.v.f v12, fa0 +; CHECK-NEXT: vmfeq.vf v16, v12, fa0 +; CHECK-NEXT: vmfeq.vv v12, v8, v8 +; CHECK-NEXT: vmand.mm v0, v16, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1227,9 +1227,9 @@ define @fcmp_ord_vv_nxv8f32_nonans( %va, < ; CHECK-LABEL: fcmp_ord_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfeq.vv v25, v12, v12 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vmfeq.vv v16, v12, v12 +; CHECK-NEXT: vmfeq.vv v12, v8, v8 +; CHECK-NEXT: vmand.mm v0, v12, v16 ; CHECK-NEXT: ret %vc = fcmp ord %va, %vb ret %vc @@ -1239,10 +1239,10 @@ define @fcmp_ord_vf_nxv8f32_nonans( %va, f ; CHECK-LABEL: fcmp_ord_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 -; CHECK-NEXT: vmfeq.vf v25, v28, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v12, fa0 +; CHECK-NEXT: vmfeq.vf v16, v12, fa0 +; CHECK-NEXT: vmfeq.vv v12, v8, v8 +; CHECK-NEXT: vmand.mm v0, v12, v16 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1254,9 +1254,9 @@ define @fcmp_ueq_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1266,9 +1266,9 @@ define @fcmp_ueq_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ueq_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmfgt.vf v26, v8, fa0 -; CHECK-NEXT: vmnor.mm v0, v26, v25 +; CHECK-NEXT: vmflt.vf v12, v8, fa0 +; CHECK-NEXT: vmfgt.vf v13, v8, fa0 +; CHECK-NEXT: vmnor.mm v0, v13, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1280,9 +1280,9 @@ define @fcmp_ueq_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ueq_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmflt.vf v26, v8, fa0 -; CHECK-NEXT: vmnor.mm v0, v26, v25 +; CHECK-NEXT: vmfgt.vf v12, v8, fa0 +; CHECK-NEXT: vmflt.vf v13, v8, fa0 +; CHECK-NEXT: vmnor.mm v0, v13, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1316,8 +1316,8 @@ define @fcmp_ugt_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1327,8 +1327,8 @@ define @fcmp_ugt_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ugt_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfle.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfle.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1340,8 +1340,8 @@ define @fcmp_ugt_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ugt_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfge.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfge.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1375,8 +1375,8 @@ define @fcmp_uge_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1386,8 +1386,8 @@ define @fcmp_uge_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_uge_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmflt.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1399,8 +1399,8 @@ define @fcmp_uge_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_uge_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfgt.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1434,8 +1434,8 @@ define @fcmp_ult_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1445,8 +1445,8 @@ define @fcmp_ult_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ult_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfge.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfge.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1458,8 +1458,8 @@ define @fcmp_ult_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ult_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfle.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfle.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1493,8 +1493,8 @@ define @fcmp_ule_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1504,8 +1504,8 @@ define @fcmp_ule_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ule_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfgt.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1517,8 +1517,8 @@ define @fcmp_ule_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ule_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmflt.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1608,9 +1608,9 @@ define @fcmp_uno_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1620,10 +1620,10 @@ define @fcmp_uno_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_uno_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 -; CHECK-NEXT: vmfne.vf v25, v28, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v12, fa0 +; CHECK-NEXT: vmfne.vf v16, v12, fa0 +; CHECK-NEXT: vmfne.vv v12, v8, v8 +; CHECK-NEXT: vmor.mm v0, v12, v16 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1635,10 +1635,10 @@ define @fcmp_uno_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_uno_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 -; CHECK-NEXT: vmfne.vf v25, v28, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vfmv.v.f v12, fa0 +; CHECK-NEXT: vmfne.vf v16, v12, fa0 +; CHECK-NEXT: vmfne.vv v12, v8, v8 +; CHECK-NEXT: vmor.mm v0, v16, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1650,9 +1650,9 @@ define @fcmp_uno_vv_nxv8f32_nonans( %va, < ; CHECK-LABEL: fcmp_uno_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfne.vv v25, v12, v12 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmfne.vv v16, v12, v12 +; CHECK-NEXT: vmfne.vv v12, v8, v8 +; CHECK-NEXT: vmor.mm v0, v12, v16 ; CHECK-NEXT: ret %vc = fcmp uno %va, %vb ret %vc @@ -1662,10 +1662,10 @@ define @fcmp_uno_vf_nxv8f32_nonans( %va, f ; CHECK-LABEL: fcmp_uno_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 -; CHECK-NEXT: vmfne.vf v25, v28, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v12, fa0 +; CHECK-NEXT: vmfne.vf v16, v12, fa0 +; CHECK-NEXT: vmfne.vv v12, v8, v8 +; CHECK-NEXT: vmor.mm v0, v12, v16 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1957,9 +1957,9 @@ define @fcmp_one_vv_nxv8f64( %va, %va, %vb ret %vc @@ -1969,9 +1969,9 @@ define @fcmp_one_vf_nxv8f64( %va, double ; CHECK-LABEL: fcmp_one_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmfgt.vf v26, v8, fa0 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmflt.vf v16, v8, fa0 +; CHECK-NEXT: vmfgt.vf v17, v8, fa0 +; CHECK-NEXT: vmor.mm v0, v17, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1983,9 +1983,9 @@ define @fcmp_one_fv_nxv8f64( %va, double ; CHECK-LABEL: fcmp_one_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmflt.vf v26, v8, fa0 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmfgt.vf v16, v8, fa0 +; CHECK-NEXT: vmflt.vf v17, v8, fa0 +; CHECK-NEXT: vmor.mm v0, v17, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2019,9 +2019,9 @@ define @fcmp_ord_vv_nxv8f64( %va, %va, %vb ret %vc @@ -2032,9 +2032,9 @@ define @fcmp_ord_vf_nxv8f64( %va, double ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vfmv.v.f v16, fa0 -; CHECK-NEXT: vmfeq.vf v25, v16, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vmfeq.vf v24, v16, fa0 +; CHECK-NEXT: vmfeq.vv v16, v8, v8 +; CHECK-NEXT: vmand.mm v0, v16, v24 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2047,9 +2047,9 @@ define @fcmp_ord_fv_nxv8f64( %va, double ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vfmv.v.f v16, fa0 -; CHECK-NEXT: vmfeq.vf v25, v16, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v25, v26 +; CHECK-NEXT: vmfeq.vf v24, v16, fa0 +; CHECK-NEXT: vmfeq.vv v16, v8, v8 +; CHECK-NEXT: vmand.mm v0, v24, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2061,9 +2061,9 @@ define @fcmp_ord_vv_nxv8f64_nonans( %va, ; CHECK-LABEL: fcmp_ord_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfeq.vv v25, v16, v16 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vmfeq.vv v24, v16, v16 +; CHECK-NEXT: vmfeq.vv v16, v8, v8 +; CHECK-NEXT: vmand.mm v0, v16, v24 ; CHECK-NEXT: ret %vc = fcmp ord %va, %vb ret %vc @@ -2074,9 +2074,9 @@ define @fcmp_ord_vf_nxv8f64_nonans( %va, ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vfmv.v.f v16, fa0 -; CHECK-NEXT: vmfeq.vf v25, v16, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vmfeq.vf v24, v16, fa0 +; CHECK-NEXT: vmfeq.vv v16, v8, v8 +; CHECK-NEXT: vmand.mm v0, v16, v24 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2088,9 +2088,9 @@ define @fcmp_ueq_vv_nxv8f64( %va, %va, %vb ret %vc @@ -2100,9 +2100,9 @@ define @fcmp_ueq_vf_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ueq_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmfgt.vf v26, v8, fa0 -; CHECK-NEXT: vmnor.mm v0, v26, v25 +; CHECK-NEXT: vmflt.vf v16, v8, fa0 +; CHECK-NEXT: vmfgt.vf v17, v8, fa0 +; CHECK-NEXT: vmnor.mm v0, v17, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2114,9 +2114,9 @@ define @fcmp_ueq_fv_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ueq_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmflt.vf v26, v8, fa0 -; CHECK-NEXT: vmnor.mm v0, v26, v25 +; CHECK-NEXT: vmfgt.vf v16, v8, fa0 +; CHECK-NEXT: vmflt.vf v17, v8, fa0 +; CHECK-NEXT: vmnor.mm v0, v17, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2150,8 +2150,8 @@ define @fcmp_ugt_vv_nxv8f64( %va, %va, %vb ret %vc @@ -2161,8 +2161,8 @@ define @fcmp_ugt_vf_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ugt_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfle.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfle.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2174,8 +2174,8 @@ define @fcmp_ugt_fv_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ugt_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfge.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfge.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2209,8 +2209,8 @@ define @fcmp_uge_vv_nxv8f64( %va, %va, %vb ret %vc @@ -2220,8 +2220,8 @@ define @fcmp_uge_vf_nxv8f64( %va, double ; CHECK-LABEL: fcmp_uge_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmflt.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2233,8 +2233,8 @@ define @fcmp_uge_fv_nxv8f64( %va, double ; CHECK-LABEL: fcmp_uge_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfgt.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2268,8 +2268,8 @@ define @fcmp_ult_vv_nxv8f64( %va, %va, %vb ret %vc @@ -2279,8 +2279,8 @@ define @fcmp_ult_vf_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ult_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfge.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfge.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2292,8 +2292,8 @@ define @fcmp_ult_fv_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ult_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfle.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfle.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2327,8 +2327,8 @@ define @fcmp_ule_vv_nxv8f64( %va, %va, %vb ret %vc @@ -2338,8 +2338,8 @@ define @fcmp_ule_vf_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ule_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfgt.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2351,8 +2351,8 @@ define @fcmp_ule_fv_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ule_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmflt.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2442,9 +2442,9 @@ define @fcmp_uno_vv_nxv8f64( %va, %va, %vb ret %vc @@ -2455,9 +2455,9 @@ define @fcmp_uno_vf_nxv8f64( %va, double ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vfmv.v.f v16, fa0 -; CHECK-NEXT: vmfne.vf v25, v16, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmfne.vf v24, v16, fa0 +; CHECK-NEXT: vmfne.vv v16, v8, v8 +; CHECK-NEXT: vmor.mm v0, v16, v24 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2470,9 +2470,9 @@ define @fcmp_uno_fv_nxv8f64( %va, double ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vfmv.v.f v16, fa0 -; CHECK-NEXT: vmfne.vf v25, v16, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmfne.vf v24, v16, fa0 +; CHECK-NEXT: vmfne.vv v16, v8, v8 +; CHECK-NEXT: vmor.mm v0, v24, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2484,9 +2484,9 @@ define @fcmp_uno_vv_nxv8f64_nonans( %va, ; CHECK-LABEL: fcmp_uno_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfne.vv v25, v16, v16 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmfne.vv v24, v16, v16 +; CHECK-NEXT: vmfne.vv v16, v8, v8 +; CHECK-NEXT: vmor.mm v0, v16, v24 ; CHECK-NEXT: ret %vc = fcmp uno %va, %vb ret %vc @@ -2497,9 +2497,9 @@ define @fcmp_uno_vf_nxv8f64_nonans( %va, ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vfmv.v.f v16, fa0 -; CHECK-NEXT: vmfne.vf v25, v16, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmfne.vf v24, v16, fa0 +; CHECK-NEXT: vmfne.vv v16, v8, v8 +; CHECK-NEXT: vmor.mm v0, v16, v24 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2514,13 +2514,13 @@ define @fcmp_oeq_vf_nx16f64( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: fcvt.d.w ft0, zero ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfeq.vf v25, v16, ft0 +; CHECK-NEXT: vmfeq.vf v24, v16, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu -; CHECK-NEXT: vslideup.vx v0, v25, a0 +; CHECK-NEXT: vslideup.vx v0, v24, a0 ; CHECK-NEXT: ret %vc = fcmp oeq %va, zeroinitializer ret %vc diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll index 6ddaa042f831ddfe0c7db11b4f720ae8e2f47653..572fe9d46d2dd434e402dc4ee162021af1620d46 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll @@ -289,9 +289,9 @@ define @fcmp_one_vv_nxv8f16( %va, %va, %vb ret %vc @@ -301,9 +301,9 @@ define @fcmp_one_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_one_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmfgt.vf v26, v8, fa0 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmflt.vf v10, v8, fa0 +; CHECK-NEXT: vmfgt.vf v11, v8, fa0 +; CHECK-NEXT: vmor.mm v0, v11, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -315,9 +315,9 @@ define @fcmp_one_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_one_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmflt.vf v26, v8, fa0 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, fa0 +; CHECK-NEXT: vmflt.vf v11, v8, fa0 +; CHECK-NEXT: vmor.mm v0, v11, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -351,9 +351,9 @@ define @fcmp_ord_vv_nxv8f16( %va, %va, %vb ret %vc @@ -363,10 +363,10 @@ define @fcmp_ord_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ord_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfeq.vf v25, v26, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v10, fa0 +; CHECK-NEXT: vmfeq.vf v12, v10, fa0 +; CHECK-NEXT: vmfeq.vv v10, v8, v8 +; CHECK-NEXT: vmand.mm v0, v10, v12 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -378,10 +378,10 @@ define @fcmp_ord_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ord_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfeq.vf v25, v26, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v25, v26 +; CHECK-NEXT: vfmv.v.f v10, fa0 +; CHECK-NEXT: vmfeq.vf v12, v10, fa0 +; CHECK-NEXT: vmfeq.vv v10, v8, v8 +; CHECK-NEXT: vmand.mm v0, v12, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -393,9 +393,9 @@ define @fcmp_ord_vv_nxv8f16_nonans( %va, %va, %vb ret %vc @@ -405,10 +405,10 @@ define @fcmp_ord_vf_nxv8f16_nonans( %va, ha ; CHECK-LABEL: fcmp_ord_vf_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfeq.vf v25, v26, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v10, fa0 +; CHECK-NEXT: vmfeq.vf v12, v10, fa0 +; CHECK-NEXT: vmfeq.vv v10, v8, v8 +; CHECK-NEXT: vmand.mm v0, v10, v12 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -420,9 +420,9 @@ define @fcmp_ueq_vv_nxv8f16( %va, %va, %vb ret %vc @@ -432,9 +432,9 @@ define @fcmp_ueq_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ueq_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmfgt.vf v26, v8, fa0 -; CHECK-NEXT: vmnor.mm v0, v26, v25 +; CHECK-NEXT: vmflt.vf v10, v8, fa0 +; CHECK-NEXT: vmfgt.vf v11, v8, fa0 +; CHECK-NEXT: vmnor.mm v0, v11, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -446,9 +446,9 @@ define @fcmp_ueq_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ueq_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmflt.vf v26, v8, fa0 -; CHECK-NEXT: vmnor.mm v0, v26, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, fa0 +; CHECK-NEXT: vmflt.vf v11, v8, fa0 +; CHECK-NEXT: vmnor.mm v0, v11, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -482,8 +482,8 @@ define @fcmp_ugt_vv_nxv8f16( %va, %va, %vb ret %vc @@ -493,8 +493,8 @@ define @fcmp_ugt_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ugt_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfle.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfle.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -506,8 +506,8 @@ define @fcmp_ugt_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ugt_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfge.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfge.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -541,8 +541,8 @@ define @fcmp_uge_vv_nxv8f16( %va, %va, %vb ret %vc @@ -552,8 +552,8 @@ define @fcmp_uge_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_uge_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmflt.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -565,8 +565,8 @@ define @fcmp_uge_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_uge_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -600,8 +600,8 @@ define @fcmp_ult_vv_nxv8f16( %va, %va, %vb ret %vc @@ -611,8 +611,8 @@ define @fcmp_ult_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ult_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfge.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfge.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -624,8 +624,8 @@ define @fcmp_ult_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ult_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfle.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfle.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -659,8 +659,8 @@ define @fcmp_ule_vv_nxv8f16( %va, %va, %vb ret %vc @@ -670,8 +670,8 @@ define @fcmp_ule_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ule_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -683,8 +683,8 @@ define @fcmp_ule_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_ule_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmflt.vf v10, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -774,9 +774,9 @@ define @fcmp_uno_vv_nxv8f16( %va, %va, %vb ret %vc @@ -786,10 +786,10 @@ define @fcmp_uno_vf_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_uno_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfne.vf v25, v26, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v10, fa0 +; CHECK-NEXT: vmfne.vf v12, v10, fa0 +; CHECK-NEXT: vmfne.vv v10, v8, v8 +; CHECK-NEXT: vmor.mm v0, v10, v12 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -801,10 +801,10 @@ define @fcmp_uno_fv_nxv8f16( %va, half %b) ; CHECK-LABEL: fcmp_uno_fv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfne.vf v25, v26, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vfmv.v.f v10, fa0 +; CHECK-NEXT: vmfne.vf v12, v10, fa0 +; CHECK-NEXT: vmfne.vv v10, v8, v8 +; CHECK-NEXT: vmor.mm v0, v12, v10 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -816,9 +816,9 @@ define @fcmp_uno_vv_nxv8f16_nonans( %va, %va, %vb ret %vc @@ -828,10 +828,10 @@ define @fcmp_uno_vf_nxv8f16_nonans( %va, ha ; CHECK-LABEL: fcmp_uno_vf_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 -; CHECK-NEXT: vmfne.vf v25, v26, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v10, fa0 +; CHECK-NEXT: vmfne.vf v12, v10, fa0 +; CHECK-NEXT: vmfne.vv v10, v8, v8 +; CHECK-NEXT: vmor.mm v0, v10, v12 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1123,9 +1123,9 @@ define @fcmp_one_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1135,9 +1135,9 @@ define @fcmp_one_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_one_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmfgt.vf v26, v8, fa0 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmflt.vf v12, v8, fa0 +; CHECK-NEXT: vmfgt.vf v13, v8, fa0 +; CHECK-NEXT: vmor.mm v0, v13, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1149,9 +1149,9 @@ define @fcmp_one_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_one_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmflt.vf v26, v8, fa0 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmfgt.vf v12, v8, fa0 +; CHECK-NEXT: vmflt.vf v13, v8, fa0 +; CHECK-NEXT: vmor.mm v0, v13, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1185,9 +1185,9 @@ define @fcmp_ord_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1197,10 +1197,10 @@ define @fcmp_ord_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ord_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 -; CHECK-NEXT: vmfeq.vf v25, v28, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v12, fa0 +; CHECK-NEXT: vmfeq.vf v16, v12, fa0 +; CHECK-NEXT: vmfeq.vv v12, v8, v8 +; CHECK-NEXT: vmand.mm v0, v12, v16 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1212,10 +1212,10 @@ define @fcmp_ord_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ord_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 -; CHECK-NEXT: vmfeq.vf v25, v28, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v25, v26 +; CHECK-NEXT: vfmv.v.f v12, fa0 +; CHECK-NEXT: vmfeq.vf v16, v12, fa0 +; CHECK-NEXT: vmfeq.vv v12, v8, v8 +; CHECK-NEXT: vmand.mm v0, v16, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1227,9 +1227,9 @@ define @fcmp_ord_vv_nxv8f32_nonans( %va, < ; CHECK-LABEL: fcmp_ord_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfeq.vv v25, v12, v12 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vmfeq.vv v16, v12, v12 +; CHECK-NEXT: vmfeq.vv v12, v8, v8 +; CHECK-NEXT: vmand.mm v0, v12, v16 ; CHECK-NEXT: ret %vc = fcmp ord %va, %vb ret %vc @@ -1239,10 +1239,10 @@ define @fcmp_ord_vf_nxv8f32_nonans( %va, f ; CHECK-LABEL: fcmp_ord_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 -; CHECK-NEXT: vmfeq.vf v25, v28, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v12, fa0 +; CHECK-NEXT: vmfeq.vf v16, v12, fa0 +; CHECK-NEXT: vmfeq.vv v12, v8, v8 +; CHECK-NEXT: vmand.mm v0, v12, v16 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1254,9 +1254,9 @@ define @fcmp_ueq_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1266,9 +1266,9 @@ define @fcmp_ueq_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ueq_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmfgt.vf v26, v8, fa0 -; CHECK-NEXT: vmnor.mm v0, v26, v25 +; CHECK-NEXT: vmflt.vf v12, v8, fa0 +; CHECK-NEXT: vmfgt.vf v13, v8, fa0 +; CHECK-NEXT: vmnor.mm v0, v13, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1280,9 +1280,9 @@ define @fcmp_ueq_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ueq_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmflt.vf v26, v8, fa0 -; CHECK-NEXT: vmnor.mm v0, v26, v25 +; CHECK-NEXT: vmfgt.vf v12, v8, fa0 +; CHECK-NEXT: vmflt.vf v13, v8, fa0 +; CHECK-NEXT: vmnor.mm v0, v13, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1316,8 +1316,8 @@ define @fcmp_ugt_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1327,8 +1327,8 @@ define @fcmp_ugt_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ugt_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfle.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfle.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1340,8 +1340,8 @@ define @fcmp_ugt_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ugt_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfge.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfge.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1375,8 +1375,8 @@ define @fcmp_uge_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1386,8 +1386,8 @@ define @fcmp_uge_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_uge_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmflt.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1399,8 +1399,8 @@ define @fcmp_uge_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_uge_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfgt.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1434,8 +1434,8 @@ define @fcmp_ult_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1445,8 +1445,8 @@ define @fcmp_ult_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ult_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfge.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfge.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1458,8 +1458,8 @@ define @fcmp_ult_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ult_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfle.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfle.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1493,8 +1493,8 @@ define @fcmp_ule_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1504,8 +1504,8 @@ define @fcmp_ule_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ule_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfgt.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1517,8 +1517,8 @@ define @fcmp_ule_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_ule_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmflt.vf v12, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1608,9 +1608,9 @@ define @fcmp_uno_vv_nxv8f32( %va, %va, %vb ret %vc @@ -1620,10 +1620,10 @@ define @fcmp_uno_vf_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_uno_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 -; CHECK-NEXT: vmfne.vf v25, v28, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v12, fa0 +; CHECK-NEXT: vmfne.vf v16, v12, fa0 +; CHECK-NEXT: vmfne.vv v12, v8, v8 +; CHECK-NEXT: vmor.mm v0, v12, v16 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1635,10 +1635,10 @@ define @fcmp_uno_fv_nxv8f32( %va, float %b ; CHECK-LABEL: fcmp_uno_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 -; CHECK-NEXT: vmfne.vf v25, v28, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vfmv.v.f v12, fa0 +; CHECK-NEXT: vmfne.vf v16, v12, fa0 +; CHECK-NEXT: vmfne.vv v12, v8, v8 +; CHECK-NEXT: vmor.mm v0, v16, v12 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1650,9 +1650,9 @@ define @fcmp_uno_vv_nxv8f32_nonans( %va, < ; CHECK-LABEL: fcmp_uno_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmfne.vv v25, v12, v12 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmfne.vv v16, v12, v12 +; CHECK-NEXT: vmfne.vv v12, v8, v8 +; CHECK-NEXT: vmor.mm v0, v12, v16 ; CHECK-NEXT: ret %vc = fcmp uno %va, %vb ret %vc @@ -1662,10 +1662,10 @@ define @fcmp_uno_vf_nxv8f32_nonans( %va, f ; CHECK-LABEL: fcmp_uno_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 -; CHECK-NEXT: vmfne.vf v25, v28, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vfmv.v.f v12, fa0 +; CHECK-NEXT: vmfne.vf v16, v12, fa0 +; CHECK-NEXT: vmfne.vv v12, v8, v8 +; CHECK-NEXT: vmor.mm v0, v12, v16 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1957,9 +1957,9 @@ define @fcmp_one_vv_nxv8f64( %va, %va, %vb ret %vc @@ -1969,9 +1969,9 @@ define @fcmp_one_vf_nxv8f64( %va, double ; CHECK-LABEL: fcmp_one_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmfgt.vf v26, v8, fa0 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmflt.vf v16, v8, fa0 +; CHECK-NEXT: vmfgt.vf v17, v8, fa0 +; CHECK-NEXT: vmor.mm v0, v17, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1983,9 +1983,9 @@ define @fcmp_one_fv_nxv8f64( %va, double ; CHECK-LABEL: fcmp_one_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmflt.vf v26, v8, fa0 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmfgt.vf v16, v8, fa0 +; CHECK-NEXT: vmflt.vf v17, v8, fa0 +; CHECK-NEXT: vmor.mm v0, v17, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2019,9 +2019,9 @@ define @fcmp_ord_vv_nxv8f64( %va, %va, %vb ret %vc @@ -2032,9 +2032,9 @@ define @fcmp_ord_vf_nxv8f64( %va, double ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vfmv.v.f v16, fa0 -; CHECK-NEXT: vmfeq.vf v25, v16, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vmfeq.vf v24, v16, fa0 +; CHECK-NEXT: vmfeq.vv v16, v8, v8 +; CHECK-NEXT: vmand.mm v0, v16, v24 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2047,9 +2047,9 @@ define @fcmp_ord_fv_nxv8f64( %va, double ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vfmv.v.f v16, fa0 -; CHECK-NEXT: vmfeq.vf v25, v16, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v25, v26 +; CHECK-NEXT: vmfeq.vf v24, v16, fa0 +; CHECK-NEXT: vmfeq.vv v16, v8, v8 +; CHECK-NEXT: vmand.mm v0, v24, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2061,9 +2061,9 @@ define @fcmp_ord_vv_nxv8f64_nonans( %va, ; CHECK-LABEL: fcmp_ord_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfeq.vv v25, v16, v16 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vmfeq.vv v24, v16, v16 +; CHECK-NEXT: vmfeq.vv v16, v8, v8 +; CHECK-NEXT: vmand.mm v0, v16, v24 ; CHECK-NEXT: ret %vc = fcmp ord %va, %vb ret %vc @@ -2074,9 +2074,9 @@ define @fcmp_ord_vf_nxv8f64_nonans( %va, ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vfmv.v.f v16, fa0 -; CHECK-NEXT: vmfeq.vf v25, v16, fa0 -; CHECK-NEXT: vmfeq.vv v26, v8, v8 -; CHECK-NEXT: vmand.mm v0, v26, v25 +; CHECK-NEXT: vmfeq.vf v24, v16, fa0 +; CHECK-NEXT: vmfeq.vv v16, v8, v8 +; CHECK-NEXT: vmand.mm v0, v16, v24 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2088,9 +2088,9 @@ define @fcmp_ueq_vv_nxv8f64( %va, %va, %vb ret %vc @@ -2100,9 +2100,9 @@ define @fcmp_ueq_vf_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ueq_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmfgt.vf v26, v8, fa0 -; CHECK-NEXT: vmnor.mm v0, v26, v25 +; CHECK-NEXT: vmflt.vf v16, v8, fa0 +; CHECK-NEXT: vmfgt.vf v17, v8, fa0 +; CHECK-NEXT: vmnor.mm v0, v17, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2114,9 +2114,9 @@ define @fcmp_ueq_fv_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ueq_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmflt.vf v26, v8, fa0 -; CHECK-NEXT: vmnor.mm v0, v26, v25 +; CHECK-NEXT: vmfgt.vf v16, v8, fa0 +; CHECK-NEXT: vmflt.vf v17, v8, fa0 +; CHECK-NEXT: vmnor.mm v0, v17, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2150,8 +2150,8 @@ define @fcmp_ugt_vv_nxv8f64( %va, %va, %vb ret %vc @@ -2161,8 +2161,8 @@ define @fcmp_ugt_vf_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ugt_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfle.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfle.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2174,8 +2174,8 @@ define @fcmp_ugt_fv_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ugt_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfge.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfge.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2209,8 +2209,8 @@ define @fcmp_uge_vv_nxv8f64( %va, %va, %vb ret %vc @@ -2220,8 +2220,8 @@ define @fcmp_uge_vf_nxv8f64( %va, double ; CHECK-LABEL: fcmp_uge_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmflt.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2233,8 +2233,8 @@ define @fcmp_uge_fv_nxv8f64( %va, double ; CHECK-LABEL: fcmp_uge_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfgt.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2268,8 +2268,8 @@ define @fcmp_ult_vv_nxv8f64( %va, %va, %vb ret %vc @@ -2279,8 +2279,8 @@ define @fcmp_ult_vf_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ult_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfge.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfge.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2292,8 +2292,8 @@ define @fcmp_ult_fv_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ult_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfle.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfle.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2327,8 +2327,8 @@ define @fcmp_ule_vv_nxv8f64( %va, %va, %vb ret %vc @@ -2338,8 +2338,8 @@ define @fcmp_ule_vf_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ule_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfgt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmfgt.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2351,8 +2351,8 @@ define @fcmp_ule_fv_nxv8f64( %va, double ; CHECK-LABEL: fcmp_ule_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmflt.vf v25, v8, fa0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmflt.vf v16, v8, fa0 +; CHECK-NEXT: vmnand.mm v0, v16, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2442,9 +2442,9 @@ define @fcmp_uno_vv_nxv8f64( %va, %va, %vb ret %vc @@ -2455,9 +2455,9 @@ define @fcmp_uno_vf_nxv8f64( %va, double ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vfmv.v.f v16, fa0 -; CHECK-NEXT: vmfne.vf v25, v16, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmfne.vf v24, v16, fa0 +; CHECK-NEXT: vmfne.vv v16, v8, v8 +; CHECK-NEXT: vmor.mm v0, v16, v24 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2470,9 +2470,9 @@ define @fcmp_uno_fv_nxv8f64( %va, double ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vfmv.v.f v16, fa0 -; CHECK-NEXT: vmfne.vf v25, v16, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmfne.vf v24, v16, fa0 +; CHECK-NEXT: vmfne.vv v16, v8, v8 +; CHECK-NEXT: vmor.mm v0, v24, v16 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2484,9 +2484,9 @@ define @fcmp_uno_vv_nxv8f64_nonans( %va, ; CHECK-LABEL: fcmp_uno_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfne.vv v25, v16, v16 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmfne.vv v24, v16, v16 +; CHECK-NEXT: vmfne.vv v16, v8, v8 +; CHECK-NEXT: vmor.mm v0, v16, v24 ; CHECK-NEXT: ret %vc = fcmp uno %va, %vb ret %vc @@ -2497,9 +2497,9 @@ define @fcmp_uno_vf_nxv8f64_nonans( %va, ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vfmv.v.f v16, fa0 -; CHECK-NEXT: vmfne.vf v25, v16, fa0 -; CHECK-NEXT: vmfne.vv v26, v8, v8 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmfne.vf v24, v16, fa0 +; CHECK-NEXT: vmfne.vv v16, v8, v8 +; CHECK-NEXT: vmor.mm v0, v16, v24 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2514,13 +2514,13 @@ define @fcmp_oeq_vf_nx16f64( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: fmv.d.x ft0, zero ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmfeq.vf v25, v16, ft0 +; CHECK-NEXT: vmfeq.vf v24, v16, ft0 ; CHECK-NEXT: vmfeq.vf v0, v8, ft0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu -; CHECK-NEXT: vslideup.vx v0, v25, a0 +; CHECK-NEXT: vslideup.vx v0, v24, a0 ; CHECK-NEXT: ret %vc = fcmp oeq %va, zeroinitializer ret %vc diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll index bf7c9e218a2b876f997640ab482daf22157c12bc..2d6caeee8784f477f93359cf412c8c4c00b25428 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll @@ -27,8 +27,8 @@ define @icmp_eq_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_eq_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmseq.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmseq.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,8 +98,8 @@ define @icmp_ne_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ne_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsne.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,8 +145,8 @@ define @icmp_ugt_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ugt_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsltu.vv v0, v8, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,8 +180,8 @@ define @icmp_uge_vx_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_uge_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsleu.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -193,8 +193,8 @@ define @icmp_uge_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_uge_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsleu.vv v0, v8, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -206,8 +206,8 @@ define @icmp_uge_vi_nxv8i8_0( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -16 -; CHECK-NEXT: vmsleu.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.i v9, -16 +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -313,8 +313,8 @@ define @icmp_ult_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ult_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsltu.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -435,8 +435,8 @@ define @icmp_ule_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ule_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsleu.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -482,8 +482,8 @@ define @icmp_sgt_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_sgt_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmslt.vv v0, v8, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -517,8 +517,8 @@ define @icmp_sge_vx_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_sge_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsle.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -530,8 +530,8 @@ define @icmp_sge_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_sge_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsle.vv v0, v8, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -543,8 +543,8 @@ define @icmp_sge_vi_nxv8i8_0( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -16 -; CHECK-NEXT: vmsle.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.i v9, -16 +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -626,8 +626,8 @@ define @icmp_slt_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_slt_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmslt.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -722,8 +722,8 @@ define @icmp_sle_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_sle_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsle.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -769,8 +769,8 @@ define @icmp_eq_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_eq_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmseq.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmseq.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -840,8 +840,8 @@ define @icmp_ne_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ne_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsne.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -887,8 +887,8 @@ define @icmp_ugt_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ugt_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsltu.vv v0, v8, v26 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsltu.vv v0, v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -922,8 +922,8 @@ define @icmp_uge_vx_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_uge_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsleu.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -935,8 +935,8 @@ define @icmp_uge_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_uge_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsleu.vv v0, v8, v26 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsleu.vv v0, v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -948,8 +948,8 @@ define @icmp_uge_vi_nxv8i16_0( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, -16 -; CHECK-NEXT: vmsleu.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.i v10, -16 +; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1034,9 +1034,9 @@ define @icmp_uge_vi_nxv8i8_6( %va, i32 %vl) { ; CHECK-LABEL: icmp_uge_vi_nxv8i8_6: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmsleu.vv v0, v25, v8 +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret %splat = call @llvm.riscv.vmv.v.x.nxv8i8(i8 0, i32 %vl) %vc = icmp uge %va, %splat @@ -1069,8 +1069,8 @@ define @icmp_ult_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ult_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsltu.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsltu.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1177,8 +1177,8 @@ define @icmp_ule_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ule_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsleu.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1224,8 +1224,8 @@ define @icmp_sgt_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_sgt_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmslt.vv v0, v8, v26 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmslt.vv v0, v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1259,8 +1259,8 @@ define @icmp_sge_vx_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_sge_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsle.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1272,8 +1272,8 @@ define @icmp_sge_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_sge_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsle.vv v0, v8, v26 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsle.vv v0, v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1285,8 +1285,8 @@ define @icmp_sge_vi_nxv8i16_0( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, -16 -; CHECK-NEXT: vmsle.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.i v10, -16 +; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1368,8 +1368,8 @@ define @icmp_slt_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_slt_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmslt.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmslt.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1464,8 +1464,8 @@ define @icmp_sle_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_sle_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsle.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1511,8 +1511,8 @@ define @icmp_eq_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_eq_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmseq.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmseq.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1582,8 +1582,8 @@ define @icmp_ne_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ne_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsne.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1629,8 +1629,8 @@ define @icmp_ugt_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ugt_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsltu.vv v0, v8, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsltu.vv v0, v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1664,8 +1664,8 @@ define @icmp_uge_vx_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_uge_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsleu.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1677,8 +1677,8 @@ define @icmp_uge_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_uge_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsleu.vv v0, v8, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsleu.vv v0, v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1690,8 +1690,8 @@ define @icmp_uge_vi_nxv8i32_0( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, -16 -; CHECK-NEXT: vmsleu.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.i v12, -16 +; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1797,8 +1797,8 @@ define @icmp_ult_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ult_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsltu.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsltu.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1905,8 +1905,8 @@ define @icmp_ule_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ule_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsleu.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1952,8 +1952,8 @@ define @icmp_sgt_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_sgt_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmslt.vv v0, v8, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmslt.vv v0, v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1987,8 +1987,8 @@ define @icmp_sge_vx_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_sge_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsle.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2000,8 +2000,8 @@ define @icmp_sge_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_sge_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsle.vv v0, v8, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsle.vv v0, v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2013,8 +2013,8 @@ define @icmp_sge_vi_nxv8i32_0( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, -16 -; CHECK-NEXT: vmsle.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.i v12, -16 +; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2096,8 +2096,8 @@ define @icmp_slt_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_slt_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmslt.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmslt.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2192,8 +2192,8 @@ define @icmp_sle_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_sle_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsle.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -3096,10 +3096,10 @@ define @icmp_eq_vi_nx16i64( %va) { ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu -; CHECK-NEXT: vmseq.vi v25, v16, 0 +; CHECK-NEXT: vmseq.vi v24, v16, 0 ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu -; CHECK-NEXT: vslideup.vx v0, v25, a0 +; CHECK-NEXT: vslideup.vx v0, v24, a0 ; CHECK-NEXT: ret %vc = icmp eq %va, zeroinitializer ret %vc diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll index 108f978c6d3869254a9d4632fb36dd5f6e100b77..979c70c20a4ebb699de11ebdaacd2325658c56be 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll @@ -27,8 +27,8 @@ define @icmp_eq_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_eq_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmseq.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmseq.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,8 +98,8 @@ define @icmp_ne_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ne_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsne.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,8 +145,8 @@ define @icmp_ugt_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ugt_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsltu.vv v0, v8, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,8 +180,8 @@ define @icmp_uge_vx_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_uge_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsleu.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -193,8 +193,8 @@ define @icmp_uge_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_uge_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsleu.vv v0, v8, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -206,8 +206,8 @@ define @icmp_uge_vi_nxv8i8_0( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -16 -; CHECK-NEXT: vmsleu.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.i v9, -16 +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -292,9 +292,9 @@ define @icmp_uge_vi_nxv8i8_6( %va, i64 %vl) { ; CHECK-LABEL: icmp_uge_vi_nxv8i8_6: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmsleu.vv v0, v25, v8 +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret %splat = call @llvm.riscv.vmv.v.x.nxv8i8(i8 0, i64 %vl) %vc = icmp uge %va, %splat @@ -327,8 +327,8 @@ define @icmp_ult_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ult_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsltu.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,8 +449,8 @@ define @icmp_ule_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ule_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsleu.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -496,8 +496,8 @@ define @icmp_sgt_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_sgt_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmslt.vv v0, v8, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -531,8 +531,8 @@ define @icmp_sge_vx_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_sge_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsle.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -544,8 +544,8 @@ define @icmp_sge_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_sge_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsle.vv v0, v8, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -557,8 +557,8 @@ define @icmp_sge_vi_nxv8i8_0( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -16 -; CHECK-NEXT: vmsle.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.i v9, -16 +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -640,8 +640,8 @@ define @icmp_slt_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_slt_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmslt.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -736,8 +736,8 @@ define @icmp_sle_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_sle_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsle.vv v0, v25, v8 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -783,8 +783,8 @@ define @icmp_eq_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_eq_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmseq.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmseq.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -854,8 +854,8 @@ define @icmp_ne_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ne_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsne.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsne.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -901,8 +901,8 @@ define @icmp_ugt_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ugt_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsltu.vv v0, v8, v26 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsltu.vv v0, v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -936,8 +936,8 @@ define @icmp_uge_vx_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_uge_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsleu.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -949,8 +949,8 @@ define @icmp_uge_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_uge_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsleu.vv v0, v8, v26 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsleu.vv v0, v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -962,8 +962,8 @@ define @icmp_uge_vi_nxv8i16_0( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, -16 -; CHECK-NEXT: vmsleu.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.i v10, -16 +; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1069,8 +1069,8 @@ define @icmp_ult_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ult_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsltu.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsltu.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1177,8 +1177,8 @@ define @icmp_ule_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ule_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsleu.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1224,8 +1224,8 @@ define @icmp_sgt_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_sgt_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmslt.vv v0, v8, v26 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmslt.vv v0, v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1259,8 +1259,8 @@ define @icmp_sge_vx_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_sge_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsle.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1272,8 +1272,8 @@ define @icmp_sge_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_sge_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsle.vv v0, v8, v26 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsle.vv v0, v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1285,8 +1285,8 @@ define @icmp_sge_vi_nxv8i16_0( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, -16 -; CHECK-NEXT: vmsle.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.i v10, -16 +; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1368,8 +1368,8 @@ define @icmp_slt_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_slt_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmslt.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmslt.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1464,8 +1464,8 @@ define @icmp_sle_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_sle_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsle.vv v0, v26, v8 +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1511,8 +1511,8 @@ define @icmp_eq_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_eq_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmseq.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmseq.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1582,8 +1582,8 @@ define @icmp_ne_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ne_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsne.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsne.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1629,8 +1629,8 @@ define @icmp_ugt_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ugt_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsltu.vv v0, v8, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsltu.vv v0, v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1664,8 +1664,8 @@ define @icmp_uge_vx_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_uge_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsleu.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1677,8 +1677,8 @@ define @icmp_uge_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_uge_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsleu.vv v0, v8, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsleu.vv v0, v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1690,8 +1690,8 @@ define @icmp_uge_vi_nxv8i32_0( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, -16 -; CHECK-NEXT: vmsleu.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.i v12, -16 +; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1797,8 +1797,8 @@ define @icmp_ult_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ult_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsltu.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsltu.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1905,8 +1905,8 @@ define @icmp_ule_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ule_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsleu.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1952,8 +1952,8 @@ define @icmp_sgt_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_sgt_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmslt.vv v0, v8, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmslt.vv v0, v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1987,8 +1987,8 @@ define @icmp_sge_vx_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_sge_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsle.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2000,8 +2000,8 @@ define @icmp_sge_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_sge_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsle.vv v0, v8, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsle.vv v0, v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2013,8 +2013,8 @@ define @icmp_sge_vi_nxv8i32_0( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, -16 -; CHECK-NEXT: vmsle.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.i v12, -16 +; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2096,8 +2096,8 @@ define @icmp_slt_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_slt_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmslt.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmslt.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2192,8 +2192,8 @@ define @icmp_sle_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_sle_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsle.vv v0, v28, v8 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2947,13 +2947,13 @@ define @icmp_eq_vi_nx16i64( %va) { ; CHECK-LABEL: icmp_eq_vi_nx16i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmseq.vi v25, v16, 0 +; CHECK-NEXT: vmseq.vi v16, v16, 0 ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu -; CHECK-NEXT: vslideup.vx v0, v25, a0 +; CHECK-NEXT: vslideup.vx v0, v16, a0 ; CHECK-NEXT: ret %vc = icmp eq %va, zeroinitializer ret %vc diff --git a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll index 9d926ab64eba0f4df4ae08c23f4ae2e608894604..bc817b2b96f5687a9e3d125c8e26aff45c9caca9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll @@ -9,9 +9,9 @@ define void @sink_splat_mul(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: .LBB0_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vmul.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vmul.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a2, .LBB0_1 @@ -45,9 +45,9 @@ define void @sink_splat_add(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: .LBB1_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vadd.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vadd.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a2, .LBB1_1 @@ -81,9 +81,9 @@ define void @sink_splat_sub(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: .LBB2_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vadd.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vadd.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a2, .LBB2_1 @@ -117,9 +117,9 @@ define void @sink_splat_rsub(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: .LBB3_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vrsub.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vrsub.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a2, .LBB3_1 @@ -153,9 +153,9 @@ define void @sink_splat_and(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: .LBB4_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vand.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vand.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a2, .LBB4_1 @@ -189,9 +189,9 @@ define void @sink_splat_or(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: .LBB5_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vor.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vor.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a2, .LBB5_1 @@ -225,9 +225,9 @@ define void @sink_splat_xor(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: .LBB6_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vxor.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vxor.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a2, .LBB6_1 @@ -272,10 +272,10 @@ define void @sink_splat_mul_scalable(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: .LBB7_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl2re32.v v26, (a2) +; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu -; CHECK-NEXT: vmul.vx v26, v26, a1 -; CHECK-NEXT: vs2r.v v26, (a2) +; CHECK-NEXT: vmul.vx v8, v8, a1 +; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: bne a5, t0, .LBB7_3 @@ -365,10 +365,10 @@ define void @sink_splat_add_scalable(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: .LBB8_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl2re32.v v26, (a2) +; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu -; CHECK-NEXT: vadd.vx v26, v26, a1 -; CHECK-NEXT: vs2r.v v26, (a2) +; CHECK-NEXT: vadd.vx v8, v8, a1 +; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: bne a5, t0, .LBB8_3 @@ -458,10 +458,10 @@ define void @sink_splat_sub_scalable(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: .LBB9_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl2re32.v v26, (a2) +; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu -; CHECK-NEXT: vsub.vx v26, v26, a1 -; CHECK-NEXT: vs2r.v v26, (a2) +; CHECK-NEXT: vsub.vx v8, v8, a1 +; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: bne a5, t0, .LBB9_3 @@ -551,10 +551,10 @@ define void @sink_splat_rsub_scalable(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: .LBB10_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl2re32.v v26, (a2) +; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu -; CHECK-NEXT: vrsub.vx v26, v26, a1 -; CHECK-NEXT: vs2r.v v26, (a2) +; CHECK-NEXT: vrsub.vx v8, v8, a1 +; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: bne a5, t0, .LBB10_3 @@ -644,10 +644,10 @@ define void @sink_splat_and_scalable(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: .LBB11_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl2re32.v v26, (a2) +; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu -; CHECK-NEXT: vand.vx v26, v26, a1 -; CHECK-NEXT: vs2r.v v26, (a2) +; CHECK-NEXT: vand.vx v8, v8, a1 +; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: bne a5, t0, .LBB11_3 @@ -737,10 +737,10 @@ define void @sink_splat_or_scalable(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: .LBB12_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl2re32.v v26, (a2) +; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu -; CHECK-NEXT: vor.vx v26, v26, a1 -; CHECK-NEXT: vs2r.v v26, (a2) +; CHECK-NEXT: vor.vx v8, v8, a1 +; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: bne a5, t0, .LBB12_3 @@ -830,10 +830,10 @@ define void @sink_splat_xor_scalable(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: .LBB13_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl2re32.v v26, (a2) +; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu -; CHECK-NEXT: vxor.vx v26, v26, a1 -; CHECK-NEXT: vs2r.v v26, (a2) +; CHECK-NEXT: vxor.vx v8, v8, a1 +; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: bne a5, t0, .LBB13_3 @@ -912,9 +912,9 @@ define void @sink_splat_shl(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: .LBB14_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vsll.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a2, .LBB14_1 @@ -948,9 +948,9 @@ define void @sink_splat_lshr(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: .LBB15_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a2, .LBB15_1 @@ -984,9 +984,9 @@ define void @sink_splat_ashr(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: .LBB16_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vsra.vx v25, v25, a1 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vsra.vx v8, v8, a1 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a2, .LBB16_1 @@ -1031,10 +1031,10 @@ define void @sink_splat_shl_scalable(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: .LBB17_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl2re32.v v26, (a2) +; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu -; CHECK-NEXT: vsll.vx v26, v26, a1 -; CHECK-NEXT: vs2r.v v26, (a2) +; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: bne a5, t0, .LBB17_3 @@ -1124,10 +1124,10 @@ define void @sink_splat_lshr_scalable(i32* nocapture %a, i32 signext %x) { ; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: .LBB18_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl2re32.v v26, (a2) +; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu -; CHECK-NEXT: vsrl.vx v26, v26, a1 -; CHECK-NEXT: vs2r.v v26, (a2) +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: bne a5, t0, .LBB18_3 @@ -1217,10 +1217,10 @@ define void @sink_splat_ashr_scalable(i32* nocapture %a) { ; CHECK-NEXT: mv a3, a0 ; CHECK-NEXT: .LBB19_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl2re32.v v26, (a3) +; CHECK-NEXT: vl2re32.v v8, (a3) ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vsra.vi v26, v26, 2 -; CHECK-NEXT: vs2r.v v26, (a3) +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vs2r.v v8, (a3) ; CHECK-NEXT: add a4, a4, a7 ; CHECK-NEXT: add a3, a3, a5 ; CHECK-NEXT: bne a4, a2, .LBB19_3 @@ -1300,9 +1300,9 @@ define void @sink_splat_fmul(float* nocapture %a, float %x) { ; CHECK-NEXT: .LBB20_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfmul.vf v25, v25, ft0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a1, a1, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a1, .LBB20_1 @@ -1337,9 +1337,9 @@ define void @sink_splat_fdiv(float* nocapture %a, float %x) { ; CHECK-NEXT: .LBB21_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfdiv.vf v25, v25, ft0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a1, a1, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a1, .LBB21_1 @@ -1374,9 +1374,9 @@ define void @sink_splat_frdiv(float* nocapture %a, float %x) { ; CHECK-NEXT: .LBB22_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfrdiv.vf v25, v25, ft0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a1, a1, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a1, .LBB22_1 @@ -1411,9 +1411,9 @@ define void @sink_splat_fadd(float* nocapture %a, float %x) { ; CHECK-NEXT: .LBB23_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfadd.vf v25, v25, ft0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a1, a1, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a1, .LBB23_1 @@ -1448,9 +1448,9 @@ define void @sink_splat_fsub(float* nocapture %a, float %x) { ; CHECK-NEXT: .LBB24_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfsub.vf v25, v25, ft0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a1, a1, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a1, .LBB24_1 @@ -1485,9 +1485,9 @@ define void @sink_splat_frsub(float* nocapture %a, float %x) { ; CHECK-NEXT: .LBB25_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vfrsub.vf v25, v25, ft0 -; CHECK-NEXT: vse32.v v25, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: addi a1, a1, -4 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: bnez a1, .LBB25_1 @@ -1532,10 +1532,10 @@ define void @sink_splat_fmul_scalable(float* nocapture %a, float %x) { ; CHECK-NEXT: mv a4, a0 ; CHECK-NEXT: .LBB26_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl1re32.v v25, (a4) +; CHECK-NEXT: vl1re32.v v8, (a4) ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmul.vf v25, v25, ft0 -; CHECK-NEXT: vs1r.v v25, (a4) +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: vs1r.v v8, (a4) ; CHECK-NEXT: add a5, a5, a3 ; CHECK-NEXT: add a4, a4, a7 ; CHECK-NEXT: bne a5, a1, .LBB26_3 @@ -1625,10 +1625,10 @@ define void @sink_splat_fdiv_scalable(float* nocapture %a, float %x) { ; CHECK-NEXT: mv a4, a0 ; CHECK-NEXT: .LBB27_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl1re32.v v25, (a4) +; CHECK-NEXT: vl1re32.v v8, (a4) ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vfdiv.vf v25, v25, ft0 -; CHECK-NEXT: vs1r.v v25, (a4) +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: vs1r.v v8, (a4) ; CHECK-NEXT: add a5, a5, a3 ; CHECK-NEXT: add a4, a4, a7 ; CHECK-NEXT: bne a5, a1, .LBB27_3 @@ -1718,10 +1718,10 @@ define void @sink_splat_frdiv_scalable(float* nocapture %a, float %x) { ; CHECK-NEXT: mv a4, a0 ; CHECK-NEXT: .LBB28_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl1re32.v v25, (a4) +; CHECK-NEXT: vl1re32.v v8, (a4) ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vfrdiv.vf v25, v25, ft0 -; CHECK-NEXT: vs1r.v v25, (a4) +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: vs1r.v v8, (a4) ; CHECK-NEXT: add a5, a5, a3 ; CHECK-NEXT: add a4, a4, a7 ; CHECK-NEXT: bne a5, a1, .LBB28_3 @@ -1811,10 +1811,10 @@ define void @sink_splat_fadd_scalable(float* nocapture %a, float %x) { ; CHECK-NEXT: mv a4, a0 ; CHECK-NEXT: .LBB29_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl1re32.v v25, (a4) +; CHECK-NEXT: vl1re32.v v8, (a4) ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vfadd.vf v25, v25, ft0 -; CHECK-NEXT: vs1r.v v25, (a4) +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: vs1r.v v8, (a4) ; CHECK-NEXT: add a5, a5, a3 ; CHECK-NEXT: add a4, a4, a7 ; CHECK-NEXT: bne a5, a1, .LBB29_3 @@ -1904,10 +1904,10 @@ define void @sink_splat_fsub_scalable(float* nocapture %a, float %x) { ; CHECK-NEXT: mv a4, a0 ; CHECK-NEXT: .LBB30_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl1re32.v v25, (a4) +; CHECK-NEXT: vl1re32.v v8, (a4) ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vfsub.vf v25, v25, ft0 -; CHECK-NEXT: vs1r.v v25, (a4) +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: vs1r.v v8, (a4) ; CHECK-NEXT: add a5, a5, a3 ; CHECK-NEXT: add a4, a4, a7 ; CHECK-NEXT: bne a5, a1, .LBB30_3 @@ -1997,10 +1997,10 @@ define void @sink_splat_frsub_scalable(float* nocapture %a, float %x) { ; CHECK-NEXT: mv a4, a0 ; CHECK-NEXT: .LBB31_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vl1re32.v v25, (a4) +; CHECK-NEXT: vl1re32.v v8, (a4) ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vfrsub.vf v25, v25, ft0 -; CHECK-NEXT: vs1r.v v25, (a4) +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: vs1r.v v8, (a4) ; CHECK-NEXT: add a5, a5, a3 ; CHECK-NEXT: add a4, a4, a7 ; CHECK-NEXT: bne a5, a1, .LBB31_3 @@ -2080,10 +2080,10 @@ define void @sink_splat_fma(float* noalias nocapture %a, float* nocapture readon ; CHECK-NEXT: .LBB32_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vfmacc.vf v26, ft0, v25 -; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vfmacc.vf v9, ft0, v8 +; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a0, a0, 16 @@ -2122,10 +2122,10 @@ define void @sink_splat_fma_commute(float* noalias nocapture %a, float* nocaptur ; CHECK-NEXT: .LBB33_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vle32.v v25, (a0) -; CHECK-NEXT: vle32.v v26, (a1) -; CHECK-NEXT: vfmacc.vf v26, ft0, v25 -; CHECK-NEXT: vse32.v v26, (a0) +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: vle32.v v9, (a1) +; CHECK-NEXT: vfmacc.vf v9, ft0, v8 +; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a0, a0, 16 @@ -2175,12 +2175,12 @@ define dso_local void @sink_splat_fma_scalable(float* noalias nocapture %a, floa ; CHECK-NEXT: .LBB34_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: add a2, a0, a5 -; CHECK-NEXT: vl1re32.v v25, (a2) +; CHECK-NEXT: vl1re32.v v8, (a2) ; CHECK-NEXT: add a4, a1, a5 -; CHECK-NEXT: vl1re32.v v26, (a4) +; CHECK-NEXT: vl1re32.v v9, (a4) ; CHECK-NEXT: vsetvli a4, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmacc.vf v26, ft0, v25 -; CHECK-NEXT: vs1r.v v26, (a2) +; CHECK-NEXT: vfmacc.vf v9, ft0, v8 +; CHECK-NEXT: vs1r.v v9, (a2) ; CHECK-NEXT: add a3, a3, t1 ; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: bne a3, t0, .LBB34_3 @@ -2279,12 +2279,12 @@ define dso_local void @sink_splat_fma_commute_scalable(float* noalias nocapture ; CHECK-NEXT: .LBB35_3: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: add a2, a0, a5 -; CHECK-NEXT: vl1re32.v v25, (a2) +; CHECK-NEXT: vl1re32.v v8, (a2) ; CHECK-NEXT: add a4, a1, a5 -; CHECK-NEXT: vl1re32.v v26, (a4) +; CHECK-NEXT: vl1re32.v v9, (a4) ; CHECK-NEXT: vsetvli a4, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmacc.vf v26, ft0, v25 -; CHECK-NEXT: vs1r.v v26, (a2) +; CHECK-NEXT: vfmacc.vf v9, ft0, v8 +; CHECK-NEXT: vs1r.v v9, (a2) ; CHECK-NEXT: add a3, a3, t1 ; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: bne a3, t0, .LBB35_3 diff --git a/llvm/test/CodeGen/RISCV/rvv/stepvector.ll b/llvm/test/CodeGen/RISCV/rvv/stepvector.ll index dcf6de2c71a8c0009f8d09b015d67df1b1d3f459..aef5554ffa3deb3a7eb6d7a4907b43fc8cb6ccda 100644 --- a/llvm/test/CodeGen/RISCV/rvv/stepvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/stepvector.ll @@ -54,8 +54,8 @@ define @add_stepvector_nxv8i8() { ; CHECK-LABEL: add_stepvector_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vsll.vi v8, v25, 1 +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vsll.vi v8, v8, 1 ; CHECK-NEXT: ret entry: %0 = call @llvm.experimental.stepvector.nxv8i8() @@ -68,9 +68,9 @@ define @mul_stepvector_nxv8i8() { ; CHECK-LABEL: mul_stepvector_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vid.v v25 +; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: addi a0, zero, 3 -; CHECK-NEXT: vmul.vx v8, v25, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: %0 = insertelement poison, i8 3, i32 0 @@ -84,8 +84,8 @@ define @shl_stepvector_nxv8i8() { ; CHECK-LABEL: shl_stepvector_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vid.v v25 -; CHECK-NEXT: vsll.vi v8, v25, 2 +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vsll.vi v8, v8, 2 ; CHECK-NEXT: ret entry: %0 = insertelement poison, i8 2, i32 0 @@ -195,8 +195,8 @@ define @add_stepvector_nxv16i16() { ; CHECK-LABEL: add_stepvector_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vid.v v28 -; CHECK-NEXT: vsll.vi v8, v28, 1 +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vsll.vi v8, v8, 1 ; CHECK-NEXT: ret entry: %0 = call @llvm.experimental.stepvector.nxv16i16() @@ -209,9 +209,9 @@ define @mul_stepvector_nxv16i16() { ; CHECK-LABEL: mul_stepvector_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vid.v v28 +; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: addi a0, zero, 3 -; CHECK-NEXT: vmul.vx v8, v28, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: %0 = insertelement poison, i16 3, i32 0 @@ -225,8 +225,8 @@ define @shl_stepvector_nxv16i16() { ; CHECK-LABEL: shl_stepvector_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vid.v v28 -; CHECK-NEXT: vsll.vi v8, v28, 2 +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vsll.vi v8, v8, 2 ; CHECK-NEXT: ret entry: %0 = insertelement poison, i16 2, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll b/llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll index 6908e6280fbd2e15dbf8197e6a4162c6a3b08499..837cbc3789a488d9fc83d5c4ae90d12ece526708 100644 --- a/llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll @@ -8,15 +8,15 @@ define @test_urem_vec_even_divisor_eq0( %x) ; RV32-NEXT: lui a0, 1048571 ; RV32-NEXT: addi a0, a0, -1365 ; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; RV32-NEXT: vmul.vx v25, v8, a0 -; RV32-NEXT: vsll.vi v26, v25, 15 -; RV32-NEXT: vsrl.vi v25, v25, 1 -; RV32-NEXT: vor.vv v25, v25, v26 +; RV32-NEXT: vmul.vx v8, v8, a0 +; RV32-NEXT: vsll.vi v9, v8, 15 +; RV32-NEXT: vsrl.vi v8, v8, 1 +; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: lui a0, 3 ; RV32-NEXT: addi a0, a0, -1366 -; RV32-NEXT: vmsgtu.vx v0, v25, a0 -; RV32-NEXT: vmv.v.i v25, 0 -; RV32-NEXT: vmerge.vim v8, v25, -1, v0 +; RV32-NEXT: vmsgtu.vx v0, v8, a0 +; RV32-NEXT: vmv.v.i v8, 0 +; RV32-NEXT: vmerge.vim v8, v8, -1, v0 ; RV32-NEXT: ret ; ; RV64-LABEL: test_urem_vec_even_divisor_eq0: @@ -24,15 +24,15 @@ define @test_urem_vec_even_divisor_eq0( %x) ; RV64-NEXT: lui a0, 1048571 ; RV64-NEXT: addiw a0, a0, -1365 ; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; RV64-NEXT: vmul.vx v25, v8, a0 -; RV64-NEXT: vsll.vi v26, v25, 15 -; RV64-NEXT: vsrl.vi v25, v25, 1 -; RV64-NEXT: vor.vv v25, v25, v26 +; RV64-NEXT: vmul.vx v8, v8, a0 +; RV64-NEXT: vsll.vi v9, v8, 15 +; RV64-NEXT: vsrl.vi v8, v8, 1 +; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: lui a0, 3 ; RV64-NEXT: addiw a0, a0, -1366 -; RV64-NEXT: vmsgtu.vx v0, v25, a0 -; RV64-NEXT: vmv.v.i v25, 0 -; RV64-NEXT: vmerge.vim v8, v25, -1, v0 +; RV64-NEXT: vmsgtu.vx v0, v8, a0 +; RV64-NEXT: vmv.v.i v8, 0 +; RV64-NEXT: vmerge.vim v8, v8, -1, v0 ; RV64-NEXT: ret %ins1 = insertelement poison, i16 6, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer @@ -50,12 +50,12 @@ define @test_urem_vec_odd_divisor_eq0( %x) ; RV32-NEXT: lui a0, 1048573 ; RV32-NEXT: addi a0, a0, -819 ; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; RV32-NEXT: vmul.vx v25, v8, a0 +; RV32-NEXT: vmul.vx v8, v8, a0 ; RV32-NEXT: lui a0, 3 ; RV32-NEXT: addi a0, a0, 819 -; RV32-NEXT: vmsgtu.vx v0, v25, a0 -; RV32-NEXT: vmv.v.i v25, 0 -; RV32-NEXT: vmerge.vim v8, v25, -1, v0 +; RV32-NEXT: vmsgtu.vx v0, v8, a0 +; RV32-NEXT: vmv.v.i v8, 0 +; RV32-NEXT: vmerge.vim v8, v8, -1, v0 ; RV32-NEXT: ret ; ; RV64-LABEL: test_urem_vec_odd_divisor_eq0: @@ -63,12 +63,12 @@ define @test_urem_vec_odd_divisor_eq0( %x) ; RV64-NEXT: lui a0, 1048573 ; RV64-NEXT: addiw a0, a0, -819 ; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; RV64-NEXT: vmul.vx v25, v8, a0 +; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: lui a0, 3 ; RV64-NEXT: addiw a0, a0, 819 -; RV64-NEXT: vmsgtu.vx v0, v25, a0 -; RV64-NEXT: vmv.v.i v25, 0 -; RV64-NEXT: vmerge.vim v8, v25, -1, v0 +; RV64-NEXT: vmsgtu.vx v0, v8, a0 +; RV64-NEXT: vmv.v.i v8, 0 +; RV64-NEXT: vmerge.vim v8, v8, -1, v0 ; RV64-NEXT: ret %ins1 = insertelement poison, i16 5, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer @@ -85,36 +85,36 @@ define @test_urem_vec_even_divisor_eq1( %x) ; RV32: # %bb.0: ; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; RV32-NEXT: vsub.vx v25, v8, a0 +; RV32-NEXT: vsub.vx v8, v8, a0 ; RV32-NEXT: lui a0, 1048571 ; RV32-NEXT: addi a0, a0, -1365 -; RV32-NEXT: vmul.vx v25, v25, a0 -; RV32-NEXT: vsll.vi v26, v25, 15 -; RV32-NEXT: vsrl.vi v25, v25, 1 -; RV32-NEXT: vor.vv v25, v25, v26 +; RV32-NEXT: vmul.vx v8, v8, a0 +; RV32-NEXT: vsll.vi v9, v8, 15 +; RV32-NEXT: vsrl.vi v8, v8, 1 +; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: lui a0, 3 ; RV32-NEXT: addi a0, a0, -1366 -; RV32-NEXT: vmsgtu.vx v0, v25, a0 -; RV32-NEXT: vmv.v.i v25, 0 -; RV32-NEXT: vmerge.vim v8, v25, -1, v0 +; RV32-NEXT: vmsgtu.vx v0, v8, a0 +; RV32-NEXT: vmv.v.i v8, 0 +; RV32-NEXT: vmerge.vim v8, v8, -1, v0 ; RV32-NEXT: ret ; ; RV64-LABEL: test_urem_vec_even_divisor_eq1: ; RV64: # %bb.0: ; RV64-NEXT: addi a0, zero, 1 ; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; RV64-NEXT: vsub.vx v25, v8, a0 +; RV64-NEXT: vsub.vx v8, v8, a0 ; RV64-NEXT: lui a0, 1048571 ; RV64-NEXT: addiw a0, a0, -1365 -; RV64-NEXT: vmul.vx v25, v25, a0 -; RV64-NEXT: vsll.vi v26, v25, 15 -; RV64-NEXT: vsrl.vi v25, v25, 1 -; RV64-NEXT: vor.vv v25, v25, v26 +; RV64-NEXT: vmul.vx v8, v8, a0 +; RV64-NEXT: vsll.vi v9, v8, 15 +; RV64-NEXT: vsrl.vi v8, v8, 1 +; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: lui a0, 3 ; RV64-NEXT: addiw a0, a0, -1366 -; RV64-NEXT: vmsgtu.vx v0, v25, a0 -; RV64-NEXT: vmv.v.i v25, 0 -; RV64-NEXT: vmerge.vim v8, v25, -1, v0 +; RV64-NEXT: vmsgtu.vx v0, v8, a0 +; RV64-NEXT: vmv.v.i v8, 0 +; RV64-NEXT: vmerge.vim v8, v8, -1, v0 ; RV64-NEXT: ret %ins1 = insertelement poison, i16 6, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer @@ -131,30 +131,30 @@ define @test_urem_vec_odd_divisor_eq1( %x) ; RV32: # %bb.0: ; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; RV32-NEXT: vsub.vx v25, v8, a0 +; RV32-NEXT: vsub.vx v8, v8, a0 ; RV32-NEXT: lui a0, 1048573 ; RV32-NEXT: addi a0, a0, -819 -; RV32-NEXT: vmul.vx v25, v25, a0 +; RV32-NEXT: vmul.vx v8, v8, a0 ; RV32-NEXT: lui a0, 3 ; RV32-NEXT: addi a0, a0, 818 -; RV32-NEXT: vmsgtu.vx v0, v25, a0 -; RV32-NEXT: vmv.v.i v25, 0 -; RV32-NEXT: vmerge.vim v8, v25, -1, v0 +; RV32-NEXT: vmsgtu.vx v0, v8, a0 +; RV32-NEXT: vmv.v.i v8, 0 +; RV32-NEXT: vmerge.vim v8, v8, -1, v0 ; RV32-NEXT: ret ; ; RV64-LABEL: test_urem_vec_odd_divisor_eq1: ; RV64: # %bb.0: ; RV64-NEXT: addi a0, zero, 1 ; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; RV64-NEXT: vsub.vx v25, v8, a0 +; RV64-NEXT: vsub.vx v8, v8, a0 ; RV64-NEXT: lui a0, 1048573 ; RV64-NEXT: addiw a0, a0, -819 -; RV64-NEXT: vmul.vx v25, v25, a0 +; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: lui a0, 3 ; RV64-NEXT: addiw a0, a0, 818 -; RV64-NEXT: vmsgtu.vx v0, v25, a0 -; RV64-NEXT: vmv.v.i v25, 0 -; RV64-NEXT: vmerge.vim v8, v25, -1, v0 +; RV64-NEXT: vmsgtu.vx v0, v8, a0 +; RV64-NEXT: vmv.v.i v8, 0 +; RV64-NEXT: vmerge.vim v8, v8, -1, v0 ; RV64-NEXT: ret %ins1 = insertelement poison, i16 5, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll index 3de4f09d432dbe2a136e0187e8db57f252263838..5dbc4451332380d646b62ec5e972c9a41e9986c4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64( @intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64( @intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64( @intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64( @intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64( @intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64( @intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64( @intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64( @intrinsic_vadc_vxm_nxv1i64_nxv1i64_i64( @intrinsic_vadc_vxm_nxv2i64_nxv2i64_i64( @intrinsic_vadc_vxm_nxv4i64_nxv4i64_i64( @intrinsic_vadd_vx_nxv1i64_nxv1i64_i64( @intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vadd_vx_nxv2i64_nxv2i64_i64( @intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vadd_vx_nxv4i64_nxv4i64_i64( @intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64( @vadd_vx_nxv1i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vadd.vv v8, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -716,8 +716,8 @@ define @vadd_vx_nxv2i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vadd.vv v8, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -759,8 +759,8 @@ define @vadd_vx_nxv4i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vadd.vv v8, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll index 766ab56c402199410d982c2ac235f1662d7c7264..2c0de9f7d45b39ccad8a029eca8614ed06526375 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll @@ -642,7 +642,7 @@ define @vadd_vi_nxv128i8( %va, @vadd_vi_nxv128i8( %va, undef, i8 -1, i32 0 @@ -1532,7 +1532,7 @@ declare @llvm.vp.add.nxv32i32(, @vadd_vi_nxv32i32( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vadd_vi_nxv32i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: mv a2, zero ; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: srli a4, a1, 2 @@ -1551,7 +1551,7 @@ define @vadd_vi_nxv32i32( %va, undef, i32 -1, i32 0 @@ -1569,11 +1569,11 @@ define @vadd_vi_nxv32i32_unmasked( %va, i ; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: srli a4, a1, 2 ; CHECK-NEXT: vsetvli a3, zero, e8, m4, ta, mu -; CHECK-NEXT: vmset.m v25 +; CHECK-NEXT: vmset.m v24 ; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, mu ; CHECK-NEXT: slli a1, a1, 1 ; CHECK-NEXT: sub a3, a0, a1 -; CHECK-NEXT: vslidedown.vx v0, v25, a4 +; CHECK-NEXT: vslidedown.vx v0, v24, a4 ; CHECK-NEXT: bltu a0, a3, .LBB118_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a2, a3 @@ -1585,7 +1585,7 @@ define @vadd_vi_nxv32i32_unmasked( %va, i ; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: .LBB118_4: ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, i32 -1, i32 0 @@ -1606,7 +1606,7 @@ declare i32 @llvm.vscale.i32() define @vadd_vi_nxv32i32_evl_nx8( %va, %m) { ; CHECK-LABEL: vadd_vi_nxv32i32_evl_nx8: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: mv a2, zero ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a4, a0, 2 @@ -1625,7 +1625,7 @@ define @vadd_vi_nxv32i32_evl_nx8( %va, undef, i32 -1, i32 0 @@ -1658,12 +1658,12 @@ define @vadd_vi_nxv32i32_evl_nx16( %va, < ; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: srli a1, a0, 2 ; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, mu -; RV64-NEXT: vslidedown.vx v25, v0, a1 +; RV64-NEXT: vslidedown.vx v24, v0, a1 ; RV64-NEXT: slli a0, a0, 1 ; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; RV64-NEXT: vadd.vi v8, v8, -1, v0.t ; RV64-NEXT: vsetivli zero, 0, e32, m8, ta, mu -; RV64-NEXT: vmv1r.v v0, v25 +; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vadd.vi v16, v16, -1, v0.t ; RV64-NEXT: ret %elt.head = insertelement undef, i32 -1, i32 0 @@ -1707,9 +1707,9 @@ define @vadd_vx_nxv1i64( %va, i64 %b, @vadd_vx_nxv1i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vadd.vv v8, v8, v25 +; RV32-NEXT: vadd.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1811,9 +1811,9 @@ define @vadd_vx_nxv2i64( %va, i64 %b, @vadd_vx_nxv2i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vadd.vv v8, v8, v26 +; RV32-NEXT: vadd.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1915,9 +1915,9 @@ define @vadd_vx_nxv4i64( %va, i64 %b, @vadd_vx_nxv4i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vadd.vv v8, v8, v28 +; RV32-NEXT: vadd.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll index 2e83a369fb7545f161bf0ccfb9db63cc0c757ff7..7852acb65a7bb85cf3b7479c66de85809166ae43 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vand_vx_nxv1i64_nxv1i64_i64( @intrinsic_vand_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vand_vx_nxv2i64_nxv2i64_i64( @intrinsic_vand_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vand_vx_nxv4i64_nxv4i64_i64( @intrinsic_vand_mask_vx_nxv4i64_nxv4i64_i64( @vand_vx_nxv1i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vand.vv v8, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -1148,8 +1148,8 @@ define @vand_vx_nxv2i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vand.vv v8, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vand.vv v8, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -1214,8 +1214,8 @@ define @vand_vx_nxv4i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vand.vv v8, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vand.vv v8, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll index ceef36302f79bcce95a7e9c9e2263b2f21fbc3d2..84a8fa65ea66a5df9ec98b4d88f27e629e49232b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll @@ -1495,9 +1495,9 @@ define @vand_vx_nxv1i64( %va, i64 %b, @vand_vx_nxv1i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vand.vv v8, v8, v25 +; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1599,9 +1599,9 @@ define @vand_vx_nxv2i64( %va, i64 %b, @vand_vx_nxv2i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vand.vv v8, v8, v26 +; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1703,9 +1703,9 @@ define @vand_vx_nxv4i64( %va, i64 %b, @vand_vx_nxv4i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vand.vv v8, v8, v28 +; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll index 57bd4292f8674d6954595f0b5d9ffe4d8a5be193..e58808643c8e12eb87d930c3ee7319743c0a90b2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vasub_vx_nxv1i64_nxv1i64_i64( @intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vasub_vx_nxv2i64_nxv2i64_i64( @intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vasub_vx_nxv4i64_nxv4i64_i64( @intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64( @intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64( @intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64( @intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64( @intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64( @intrinsic_vcompress_um_nxv1i8_nxv1i8( ; CHECK-LABEL: intrinsic_vcompress_um_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vcompress.vm v25, v8, v0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vcompress.vm v9, v8, v0 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv1i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll index 39b775f5ae3d0e215398aa7f110423450e1ab581..e814c9652c704b389c0318d8bb7f1855db26590b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll @@ -820,8 +820,8 @@ define @intrinsic_vcompress_um_nxv1i8_nxv1i8( ; CHECK-LABEL: intrinsic_vcompress_um_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vcompress.vm v25, v8, v0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vcompress.vm v9, v8, v0 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv1i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll index ad6b91a0fb3e562d083f554b263d87d00181a9cb..60f4e9755a1f50d067f8474547cf7f9da3f51fb6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vdiv_vx_nxv1i64_nxv1i64_i64( @intrinsic_vdiv_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vdiv_vx_nxv2i64_nxv2i64_i64( @intrinsic_vdiv_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vdiv_vx_nxv4i64_nxv4i64_i64( @intrinsic_vdiv_mask_vx_nxv4i64_nxv4i64_i64( @vdiv_vi_nxv1i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v8, v9, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v9, v8, 7 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -91,11 +91,11 @@ define @vdiv_vi_nxv2i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v8, v9, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v9, v8, 7 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -130,11 +130,11 @@ define @vdiv_vi_nxv4i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v8, v9, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v9, v8, 7 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -169,11 +169,11 @@ define @vdiv_vi_nxv8i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v8, v9, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v9, v8, 7 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -208,11 +208,11 @@ define @vdiv_vi_nxv16i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmulh.vx v26, v8, a0 -; CHECK-NEXT: vsub.vv v26, v26, v8 -; CHECK-NEXT: vsra.vi v26, v26, 2 -; CHECK-NEXT: vsrl.vi v28, v26, 7 -; CHECK-NEXT: vadd.vv v8, v26, v28 +; CHECK-NEXT: vmulh.vx v10, v8, a0 +; CHECK-NEXT: vsub.vv v8, v10, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v10, v8, 7 +; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -247,11 +247,11 @@ define @vdiv_vi_nxv32i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmulh.vx v28, v8, a0 -; CHECK-NEXT: vsub.vv v28, v28, v8 -; CHECK-NEXT: vsra.vi v28, v28, 2 -; CHECK-NEXT: vsrl.vi v8, v28, 7 -; CHECK-NEXT: vadd.vv v8, v28, v8 +; CHECK-NEXT: vmulh.vx v12, v8, a0 +; CHECK-NEXT: vsub.vv v8, v12, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v12, v8, 7 +; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -326,10 +326,10 @@ define @vdiv_vi_nxv1i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vsrl.vi v26, v25, 15 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vsrl.vi v9, v8, 15 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -365,10 +365,10 @@ define @vdiv_vi_nxv2i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vsrl.vi v26, v25, 15 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vsrl.vi v9, v8, 15 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -404,10 +404,10 @@ define @vdiv_vi_nxv4i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vsrl.vi v26, v25, 15 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vsrl.vi v9, v8, 15 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -443,10 +443,10 @@ define @vdiv_vi_nxv8i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmulh.vx v26, v8, a0 -; CHECK-NEXT: vsra.vi v26, v26, 1 -; CHECK-NEXT: vsrl.vi v28, v26, 15 -; CHECK-NEXT: vadd.vv v8, v26, v28 +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vsrl.vi v10, v8, 15 +; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -482,10 +482,10 @@ define @vdiv_vi_nxv16i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vmulh.vx v28, v8, a0 -; CHECK-NEXT: vsra.vi v28, v28, 1 -; CHECK-NEXT: vsrl.vi v8, v28, 15 -; CHECK-NEXT: vadd.vv v8, v28, v8 +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vsrl.vi v12, v8, 15 +; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -560,11 +560,11 @@ define @vdiv_vi_nxv1i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addi a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsrl.vi v26, v25, 31 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v8, v9, v8 +; CHECK-NEXT: vsrl.vi v9, v8, 31 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -600,11 +600,11 @@ define @vdiv_vi_nxv2i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addi a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsrl.vi v26, v25, 31 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v8, v9, v8 +; CHECK-NEXT: vsrl.vi v9, v8, 31 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -640,11 +640,11 @@ define @vdiv_vi_nxv4i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addi a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vmulh.vx v26, v8, a0 -; CHECK-NEXT: vsub.vv v26, v26, v8 -; CHECK-NEXT: vsrl.vi v28, v26, 31 -; CHECK-NEXT: vsra.vi v26, v26, 2 -; CHECK-NEXT: vadd.vv v8, v26, v28 +; CHECK-NEXT: vmulh.vx v10, v8, a0 +; CHECK-NEXT: vsub.vv v8, v10, v8 +; CHECK-NEXT: vsrl.vi v10, v8, 31 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -680,11 +680,11 @@ define @vdiv_vi_nxv8i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addi a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmulh.vx v28, v8, a0 -; CHECK-NEXT: vsub.vv v28, v28, v8 -; CHECK-NEXT: vsrl.vi v8, v28, 31 -; CHECK-NEXT: vsra.vi v28, v28, 2 -; CHECK-NEXT: vadd.vv v8, v28, v8 +; CHECK-NEXT: vmulh.vx v12, v8, a0 +; CHECK-NEXT: vsub.vv v8, v12, v8 +; CHECK-NEXT: vsrl.vi v12, v8, 31 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -751,8 +751,8 @@ define @vdiv_vx_nxv1i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vdiv.vv v8, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -774,12 +774,12 @@ define @vdiv_vi_nxv1i64_0( %va) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmulh.vv v25, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmulh.vv v8, v8, v9 ; CHECK-NEXT: addi a0, zero, 63 -; CHECK-NEXT: vsrl.vx v26, v25, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vsrl.vx v9, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 @@ -807,8 +807,8 @@ define @vdiv_vx_nxv2i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vdiv.vv v8, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -830,12 +830,12 @@ define @vdiv_vi_nxv2i64_0( %va) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmulh.vv v26, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmulh.vv v8, v8, v10 ; CHECK-NEXT: addi a0, zero, 63 -; CHECK-NEXT: vsrl.vx v28, v26, a0 -; CHECK-NEXT: vsra.vi v26, v26, 1 -; CHECK-NEXT: vadd.vv v8, v26, v28 +; CHECK-NEXT: vsrl.vx v10, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 @@ -863,8 +863,8 @@ define @vdiv_vx_nxv4i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vdiv.vv v8, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -886,12 +886,12 @@ define @vdiv_vi_nxv4i64_0( %va) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmulh.vv v28, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmulh.vv v8, v8, v12 ; CHECK-NEXT: addi a0, zero, 63 -; CHECK-NEXT: vsrl.vx v8, v28, a0 -; CHECK-NEXT: vsra.vi v28, v28, 1 -; CHECK-NEXT: vadd.vv v8, v28, v8 +; CHECK-NEXT: vsrl.vx v12, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll index 0a37a6bd8c0d173023a0607c046b507782550af8..22910da428ea8054be7285e4f9c341c2f1cfd6b2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll @@ -28,11 +28,11 @@ define @vdiv_vi_nxv1i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v8, v9, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v9, v8, 7 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -67,11 +67,11 @@ define @vdiv_vi_nxv2i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v8, v9, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v9, v8, 7 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -106,11 +106,11 @@ define @vdiv_vi_nxv4i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v8, v9, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v9, v8, 7 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,11 +145,11 @@ define @vdiv_vi_nxv8i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v8, v9, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v9, v8, 7 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -184,11 +184,11 @@ define @vdiv_vi_nxv16i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmulh.vx v26, v8, a0 -; CHECK-NEXT: vsub.vv v26, v26, v8 -; CHECK-NEXT: vsra.vi v26, v26, 2 -; CHECK-NEXT: vsrl.vi v28, v26, 7 -; CHECK-NEXT: vadd.vv v8, v26, v28 +; CHECK-NEXT: vmulh.vx v10, v8, a0 +; CHECK-NEXT: vsub.vv v8, v10, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v10, v8, 7 +; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -223,11 +223,11 @@ define @vdiv_vi_nxv32i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmulh.vx v28, v8, a0 -; CHECK-NEXT: vsub.vv v28, v28, v8 -; CHECK-NEXT: vsra.vi v28, v28, 2 -; CHECK-NEXT: vsrl.vi v8, v28, 7 -; CHECK-NEXT: vadd.vv v8, v28, v8 +; CHECK-NEXT: vmulh.vx v12, v8, a0 +; CHECK-NEXT: vsub.vv v8, v12, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v12, v8, 7 +; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -302,10 +302,10 @@ define @vdiv_vi_nxv1i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addiw a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vsrl.vi v26, v25, 15 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vsrl.vi v9, v8, 15 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -341,10 +341,10 @@ define @vdiv_vi_nxv2i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addiw a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vsrl.vi v26, v25, 15 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vsrl.vi v9, v8, 15 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -380,10 +380,10 @@ define @vdiv_vi_nxv4i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addiw a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vsrl.vi v26, v25, 15 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vsrl.vi v9, v8, 15 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -419,10 +419,10 @@ define @vdiv_vi_nxv8i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addiw a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmulh.vx v26, v8, a0 -; CHECK-NEXT: vsra.vi v26, v26, 1 -; CHECK-NEXT: vsrl.vi v28, v26, 15 -; CHECK-NEXT: vadd.vv v8, v26, v28 +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vsrl.vi v10, v8, 15 +; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -458,10 +458,10 @@ define @vdiv_vi_nxv16i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addiw a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vmulh.vx v28, v8, a0 -; CHECK-NEXT: vsra.vi v28, v28, 1 -; CHECK-NEXT: vsrl.vi v8, v28, 15 -; CHECK-NEXT: vadd.vv v8, v28, v8 +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vsrl.vi v12, v8, 15 +; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -536,11 +536,11 @@ define @vdiv_vi_nxv1i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addiw a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 31 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v8, v9, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v9, v8, 31 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -576,11 +576,11 @@ define @vdiv_vi_nxv2i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addiw a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 31 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v8, v9, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v9, v8, 31 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -616,11 +616,11 @@ define @vdiv_vi_nxv4i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addiw a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vmulh.vx v26, v8, a0 -; CHECK-NEXT: vsub.vv v26, v26, v8 -; CHECK-NEXT: vsra.vi v26, v26, 2 -; CHECK-NEXT: vsrl.vi v28, v26, 31 -; CHECK-NEXT: vadd.vv v8, v26, v28 +; CHECK-NEXT: vmulh.vx v10, v8, a0 +; CHECK-NEXT: vsub.vv v8, v10, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v10, v8, 31 +; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -656,11 +656,11 @@ define @vdiv_vi_nxv8i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addiw a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmulh.vx v28, v8, a0 -; CHECK-NEXT: vsub.vv v28, v28, v8 -; CHECK-NEXT: vsra.vi v28, v28, 2 -; CHECK-NEXT: vsrl.vi v8, v28, 31 -; CHECK-NEXT: vadd.vv v8, v28, v8 +; CHECK-NEXT: vmulh.vx v12, v8, a0 +; CHECK-NEXT: vsub.vv v8, v12, v8 +; CHECK-NEXT: vsra.vi v8, v8, 2 +; CHECK-NEXT: vsrl.vi v12, v8, 31 +; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -742,11 +742,11 @@ define @vdiv_vi_nxv1i64_0( %va) { ; CHECK-NEXT: slli a0, a0, 12 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 +; CHECK-NEXT: vmulh.vx v8, v8, a0 ; CHECK-NEXT: addi a0, zero, 63 -; CHECK-NEXT: vsrl.vx v26, v25, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vadd.vv v8, v25, v26 +; CHECK-NEXT: vsrl.vx v9, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -788,11 +788,11 @@ define @vdiv_vi_nxv2i64_0( %va) { ; CHECK-NEXT: slli a0, a0, 12 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vmulh.vx v26, v8, a0 +; CHECK-NEXT: vmulh.vx v8, v8, a0 ; CHECK-NEXT: addi a0, zero, 63 -; CHECK-NEXT: vsrl.vx v28, v26, a0 -; CHECK-NEXT: vsra.vi v26, v26, 1 -; CHECK-NEXT: vadd.vv v8, v26, v28 +; CHECK-NEXT: vsrl.vx v10, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -834,11 +834,11 @@ define @vdiv_vi_nxv4i64_0( %va) { ; CHECK-NEXT: slli a0, a0, 12 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vmulh.vx v28, v8, a0 +; CHECK-NEXT: vmulh.vx v8, v8, a0 ; CHECK-NEXT: addi a0, zero, 63 -; CHECK-NEXT: vsrl.vx v8, v28, a0 -; CHECK-NEXT: vsra.vi v28, v28, 1 -; CHECK-NEXT: vadd.vv v8, v28, v8 +; CHECK-NEXT: vsrl.vx v12, v8, a0 +; CHECK-NEXT: vsra.vi v8, v8, 1 +; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll index 01709a1b0eb557898e4e10e08327a4da2d2bc847..97160b8e93457d553f48336273c802aa5cf6eafc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll @@ -10,13 +10,13 @@ define @vdiv_vx_nxv8i7( %a, i7 signext %b, undef, i7 %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -969,9 +969,9 @@ define @vdiv_vx_nxv1i64( %va, i64 %b, @vdiv_vx_nxv1i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vdiv.vv v8, v8, v25 +; RV32-NEXT: vdiv.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1047,9 +1047,9 @@ define @vdiv_vx_nxv2i64( %va, i64 %b, @vdiv_vx_nxv2i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vdiv.vv v8, v8, v26 +; RV32-NEXT: vdiv.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1125,9 +1125,9 @@ define @vdiv_vx_nxv4i64( %va, i64 %b, @vdiv_vx_nxv4i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vdiv.vv v8, v8, v28 +; RV32-NEXT: vdiv.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll index 36ae2c34ea96f0f00b4f86ccddcad19e074e62a0..47322163d6c86ae45100167732ca57409eed20d1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vdivu_vx_nxv1i64_nxv1i64_i64( @intrinsic_vdivu_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vdivu_vx_nxv2i64_nxv2i64_i64( @intrinsic_vdivu_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vdivu_vx_nxv4i64_nxv4i64_i64( @intrinsic_vdivu_mask_vx_nxv4i64_nxv4i64_i64( @vdivu_vi_nxv1i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 5 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -88,8 +88,8 @@ define @vdivu_vi_nxv2i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 5 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -124,8 +124,8 @@ define @vdivu_vi_nxv4i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 5 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -160,8 +160,8 @@ define @vdivu_vi_nxv8i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 5 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -196,8 +196,8 @@ define @vdivu_vi_nxv16i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmulhu.vx v26, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v26, 5 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -232,8 +232,8 @@ define @vdivu_vi_nxv32i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmulhu.vx v28, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v28, 5 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -305,8 +305,8 @@ define @vdivu_vi_nxv1i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 13 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -342,8 +342,8 @@ define @vdivu_vi_nxv2i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 13 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -379,8 +379,8 @@ define @vdivu_vi_nxv4i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 13 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -416,8 +416,8 @@ define @vdivu_vi_nxv8i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmulhu.vx v26, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v26, 13 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -453,8 +453,8 @@ define @vdivu_vi_nxv16i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vmulhu.vx v28, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v28, 13 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -527,8 +527,8 @@ define @vdivu_vi_nxv1i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 29 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -564,8 +564,8 @@ define @vdivu_vi_nxv2i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 29 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -601,8 +601,8 @@ define @vdivu_vi_nxv4i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vmulhu.vx v26, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v26, 29 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -638,8 +638,8 @@ define @vdivu_vi_nxv8i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmulhu.vx v28, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v28, 29 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -703,8 +703,8 @@ define @vdivu_vx_nxv1i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vdivu.vv v8, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -724,10 +724,10 @@ define @vdivu_vi_nxv1i64_0( %va) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmulhu.vv v25, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmulhu.vv v8, v8, v9 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v8, v25, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 @@ -753,8 +753,8 @@ define @vdivu_vi_nxv1i64_2( %va, undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -782,8 +782,8 @@ define @vdivu_vx_nxv2i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vdivu.vv v8, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -803,10 +803,10 @@ define @vdivu_vi_nxv2i64_0( %va) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmulhu.vv v26, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmulhu.vv v8, v8, v10 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v8, v26, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 @@ -832,8 +832,8 @@ define @vdivu_vi_nxv2i64_2( %va, undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -861,8 +861,8 @@ define @vdivu_vx_nxv4i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vdivu.vv v8, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -882,10 +882,10 @@ define @vdivu_vi_nxv4i64_0( %va) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmulhu.vv v28, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmulhu.vv v8, v8, v12 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v8, v28, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 @@ -911,8 +911,8 @@ define @vdivu_vi_nxv4i64_2( %va, undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll index a351185ea65108bff1a69ed3e7ee4bdc9f301390..daddce030d9a664af11e5ec5e6b94111ff18f69e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll @@ -28,8 +28,8 @@ define @vdivu_vi_nxv1i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 5 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -64,8 +64,8 @@ define @vdivu_vi_nxv2i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 5 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -100,8 +100,8 @@ define @vdivu_vi_nxv4i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 5 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -136,8 +136,8 @@ define @vdivu_vi_nxv8i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 5 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -172,8 +172,8 @@ define @vdivu_vi_nxv16i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmulhu.vx v26, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v26, 5 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -208,8 +208,8 @@ define @vdivu_vi_nxv32i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmulhu.vx v28, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v28, 5 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,8 +281,8 @@ define @vdivu_vi_nxv1i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 13 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -318,8 +318,8 @@ define @vdivu_vi_nxv2i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 13 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -355,8 +355,8 @@ define @vdivu_vi_nxv4i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 13 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -392,8 +392,8 @@ define @vdivu_vi_nxv8i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmulhu.vx v26, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v26, 13 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -429,8 +429,8 @@ define @vdivu_vi_nxv16i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vmulhu.vx v28, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v28, 13 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -503,8 +503,8 @@ define @vdivu_vi_nxv1i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 29 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -540,8 +540,8 @@ define @vdivu_vi_nxv2i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v25, 29 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -577,8 +577,8 @@ define @vdivu_vi_nxv4i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vmulhu.vx v26, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v26, 29 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -614,8 +614,8 @@ define @vdivu_vi_nxv8i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmulhu.vx v28, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v28, 29 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -689,9 +689,9 @@ define @vdivu_vi_nxv1i64_0( %va) { ; CHECK-NEXT: slli a0, a0, 61 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v8, v25, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -716,8 +716,8 @@ define @vdivu_vi_nxv1i64_2( %va, undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -755,9 +755,9 @@ define @vdivu_vi_nxv2i64_0( %va) { ; CHECK-NEXT: slli a0, a0, 61 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vmulhu.vx v26, v8, a0 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v8, v26, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -782,8 +782,8 @@ define @vdivu_vi_nxv2i64_2( %va, undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -821,9 +821,9 @@ define @vdivu_vi_nxv4i64_0( %va) { ; CHECK-NEXT: slli a0, a0, 61 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vmulhu.vx v28, v8, a0 +; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v8, v28, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -848,8 +848,8 @@ define @vdivu_vi_nxv4i64_2( %va, undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll index 57f0c640d84d3aad78fe9fdedb6b32993f6877b0..a45f1b23e7736d423d93c513efce4d1cb0e69ee0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll @@ -11,11 +11,11 @@ define @vdivu_vx_nxv8i7( %a, i7 signext %b, < ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 127 ; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, mu -; CHECK-NEXT: vand.vx v25, v8, a2 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vand.vx v26, v26, a2 +; CHECK-NEXT: vand.vx v8, v8, a2 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vand.vx v9, v9, a2 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vdivu.vv v8, v25, v26, v0.t +; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, i7 %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -968,9 +968,9 @@ define @vdivu_vx_nxv1i64( %va, i64 %b, @vdivu_vx_nxv1i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vdivu.vv v8, v8, v25 +; RV32-NEXT: vdivu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1046,9 +1046,9 @@ define @vdivu_vx_nxv2i64( %va, i64 %b, @vdivu_vx_nxv2i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vdivu.vv v8, v8, v26 +; RV32-NEXT: vdivu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1124,9 +1124,9 @@ define @vdivu_vx_nxv4i64( %va, i64 %b, @vdivu_vx_nxv4i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vdivu.vv v8, v8, v28 +; RV32-NEXT: vdivu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll index 8be4d1c6abf07469a7e6b7da0037b48744ccef54..ae1f11fd41969bc75d767eb03d552986c60bacb5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll @@ -5,8 +5,8 @@ define @vsext_nxv1i8_nxv1i16( %va) { ; CHECK-LABEL: vsext_nxv1i8_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -16,8 +16,8 @@ define @vzext_nxv1i8_nxv1i16( %va) { ; CHECK-LABEL: vzext_nxv1i8_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -27,8 +27,8 @@ define @vsext_nxv1i8_nxv1i32( %va) { ; CHECK-LABEL: vsext_nxv1i8_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -38,8 +38,8 @@ define @vzext_nxv1i8_nxv1i32( %va) { ; CHECK-LABEL: vzext_nxv1i8_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -49,8 +49,8 @@ define @vsext_nxv1i8_nxv1i64( %va) { ; CHECK-LABEL: vsext_nxv1i8_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf8 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf8 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -60,8 +60,8 @@ define @vzext_nxv1i8_nxv1i64( %va) { ; CHECK-LABEL: vzext_nxv1i8_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf8 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf8 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -71,8 +71,8 @@ define @vsext_nxv2i8_nxv2i16( %va) { ; CHECK-LABEL: vsext_nxv2i8_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -82,8 +82,8 @@ define @vzext_nxv2i8_nxv2i16( %va) { ; CHECK-LABEL: vzext_nxv2i8_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -93,8 +93,8 @@ define @vsext_nxv2i8_nxv2i32( %va) { ; CHECK-LABEL: vsext_nxv2i8_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -104,8 +104,8 @@ define @vzext_nxv2i8_nxv2i32( %va) { ; CHECK-LABEL: vzext_nxv2i8_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -115,8 +115,8 @@ define @vsext_nxv2i8_nxv2i64( %va) { ; CHECK-LABEL: vsext_nxv2i8_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf8 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf8 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -126,8 +126,8 @@ define @vzext_nxv2i8_nxv2i64( %va) { ; CHECK-LABEL: vzext_nxv2i8_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf8 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -137,8 +137,8 @@ define @vsext_nxv4i8_nxv4i16( %va) { ; CHECK-LABEL: vsext_nxv4i8_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -148,8 +148,8 @@ define @vzext_nxv4i8_nxv4i16( %va) { ; CHECK-LABEL: vzext_nxv4i8_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -159,8 +159,8 @@ define @vsext_nxv4i8_nxv4i32( %va) { ; CHECK-LABEL: vsext_nxv4i8_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -170,8 +170,8 @@ define @vzext_nxv4i8_nxv4i32( %va) { ; CHECK-LABEL: vzext_nxv4i8_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -181,8 +181,8 @@ define @vsext_nxv4i8_nxv4i64( %va) { ; CHECK-LABEL: vsext_nxv4i8_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf8 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -192,8 +192,8 @@ define @vzext_nxv4i8_nxv4i64( %va) { ; CHECK-LABEL: vzext_nxv4i8_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf8 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -203,8 +203,8 @@ define @vsext_nxv8i8_nxv8i16( %va) { ; CHECK-LABEL: vsext_nxv8i8_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -214,8 +214,8 @@ define @vzext_nxv8i8_nxv8i16( %va) { ; CHECK-LABEL: vzext_nxv8i8_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -225,8 +225,8 @@ define @vsext_nxv8i8_nxv8i32( %va) { ; CHECK-LABEL: vsext_nxv8i8_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -236,8 +236,8 @@ define @vzext_nxv8i8_nxv8i32( %va) { ; CHECK-LABEL: vzext_nxv8i8_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -269,8 +269,8 @@ define @vsext_nxv16i8_nxv16i16( %va) { ; CHECK-LABEL: vsext_nxv16i8_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -280,8 +280,8 @@ define @vzext_nxv16i8_nxv16i16( %va) { ; CHECK-LABEL: vzext_nxv16i8_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -335,8 +335,8 @@ define @vsext_nxv1i16_nxv1i32( %va) { ; CHECK-LABEL: vsext_nxv1i16_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -346,8 +346,8 @@ define @vzext_nxv1i16_nxv1i32( %va) { ; CHECK-LABEL: vzext_nxv1i16_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -357,8 +357,8 @@ define @vsext_nxv1i16_nxv1i64( %va) { ; CHECK-LABEL: vsext_nxv1i16_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -368,8 +368,8 @@ define @vzext_nxv1i16_nxv1i64( %va) { ; CHECK-LABEL: vzext_nxv1i16_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -379,8 +379,8 @@ define @vsext_nxv2i16_nxv2i32( %va) { ; CHECK-LABEL: vsext_nxv2i16_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -390,8 +390,8 @@ define @vzext_nxv2i16_nxv2i32( %va) { ; CHECK-LABEL: vzext_nxv2i16_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -401,8 +401,8 @@ define @vsext_nxv2i16_nxv2i64( %va) { ; CHECK-LABEL: vsext_nxv2i16_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -412,8 +412,8 @@ define @vzext_nxv2i16_nxv2i64( %va) { ; CHECK-LABEL: vzext_nxv2i16_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -423,8 +423,8 @@ define @vsext_nxv4i16_nxv4i32( %va) { ; CHECK-LABEL: vsext_nxv4i16_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -434,8 +434,8 @@ define @vzext_nxv4i16_nxv4i32( %va) { ; CHECK-LABEL: vzext_nxv4i16_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -445,8 +445,8 @@ define @vsext_nxv4i16_nxv4i64( %va) { ; CHECK-LABEL: vsext_nxv4i16_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -456,8 +456,8 @@ define @vzext_nxv4i16_nxv4i64( %va) { ; CHECK-LABEL: vzext_nxv4i16_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -467,8 +467,8 @@ define @vsext_nxv8i16_nxv8i32( %va) { ; CHECK-LABEL: vsext_nxv8i16_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -478,8 +478,8 @@ define @vzext_nxv8i16_nxv8i32( %va) { ; CHECK-LABEL: vzext_nxv8i16_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -533,8 +533,8 @@ define @vsext_nxv1i32_nxv1i64( %va) { ; CHECK-LABEL: vsext_nxv1i32_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -544,8 +544,8 @@ define @vzext_nxv1i32_nxv1i64( %va) { ; CHECK-LABEL: vzext_nxv1i32_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -555,8 +555,8 @@ define @vsext_nxv2i32_nxv2i64( %va) { ; CHECK-LABEL: vsext_nxv2i32_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -566,8 +566,8 @@ define @vzext_nxv2i32_nxv2i64( %va) { ; CHECK-LABEL: vzext_nxv2i32_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -577,8 +577,8 @@ define @vsext_nxv4i32_nxv4i64( %va) { ; CHECK-LABEL: vsext_nxv4i32_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -588,8 +588,8 @@ define @vzext_nxv4i32_nxv4i64( %va) { ; CHECK-LABEL: vzext_nxv4i32_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = zext %va to ret %evec diff --git a/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll index 0d139367aa4e30bc5d2b1d8720d902f450fc9ff1..aee93842d6135a99d3d01f83bf1b169a0b328fe5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll @@ -5,8 +5,8 @@ define @vsext_nxv1i8_nxv1i16( %va) { ; CHECK-LABEL: vsext_nxv1i8_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -16,8 +16,8 @@ define @vzext_nxv1i8_nxv1i16( %va) { ; CHECK-LABEL: vzext_nxv1i8_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -27,8 +27,8 @@ define @vsext_nxv1i8_nxv1i32( %va) { ; CHECK-LABEL: vsext_nxv1i8_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -38,8 +38,8 @@ define @vzext_nxv1i8_nxv1i32( %va) { ; CHECK-LABEL: vzext_nxv1i8_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -49,8 +49,8 @@ define @vsext_nxv1i8_nxv1i64( %va) { ; CHECK-LABEL: vsext_nxv1i8_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf8 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf8 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -60,8 +60,8 @@ define @vzext_nxv1i8_nxv1i64( %va) { ; CHECK-LABEL: vzext_nxv1i8_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf8 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf8 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -71,8 +71,8 @@ define @vsext_nxv2i8_nxv2i16( %va) { ; CHECK-LABEL: vsext_nxv2i8_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -82,8 +82,8 @@ define @vzext_nxv2i8_nxv2i16( %va) { ; CHECK-LABEL: vzext_nxv2i8_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -93,8 +93,8 @@ define @vsext_nxv2i8_nxv2i32( %va) { ; CHECK-LABEL: vsext_nxv2i8_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -104,8 +104,8 @@ define @vzext_nxv2i8_nxv2i32( %va) { ; CHECK-LABEL: vzext_nxv2i8_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -115,8 +115,8 @@ define @vsext_nxv2i8_nxv2i64( %va) { ; CHECK-LABEL: vsext_nxv2i8_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf8 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf8 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -126,8 +126,8 @@ define @vzext_nxv2i8_nxv2i64( %va) { ; CHECK-LABEL: vzext_nxv2i8_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf8 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -137,8 +137,8 @@ define @vsext_nxv4i8_nxv4i16( %va) { ; CHECK-LABEL: vsext_nxv4i8_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -148,8 +148,8 @@ define @vzext_nxv4i8_nxv4i16( %va) { ; CHECK-LABEL: vzext_nxv4i8_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -159,8 +159,8 @@ define @vsext_nxv4i8_nxv4i32( %va) { ; CHECK-LABEL: vsext_nxv4i8_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -170,8 +170,8 @@ define @vzext_nxv4i8_nxv4i32( %va) { ; CHECK-LABEL: vzext_nxv4i8_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -181,8 +181,8 @@ define @vsext_nxv4i8_nxv4i64( %va) { ; CHECK-LABEL: vsext_nxv4i8_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf8 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -192,8 +192,8 @@ define @vzext_nxv4i8_nxv4i64( %va) { ; CHECK-LABEL: vzext_nxv4i8_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf8 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -203,8 +203,8 @@ define @vsext_nxv8i8_nxv8i16( %va) { ; CHECK-LABEL: vsext_nxv8i8_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -214,8 +214,8 @@ define @vzext_nxv8i8_nxv8i16( %va) { ; CHECK-LABEL: vzext_nxv8i8_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -225,8 +225,8 @@ define @vsext_nxv8i8_nxv8i32( %va) { ; CHECK-LABEL: vsext_nxv8i8_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -236,8 +236,8 @@ define @vzext_nxv8i8_nxv8i32( %va) { ; CHECK-LABEL: vzext_nxv8i8_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -269,8 +269,8 @@ define @vsext_nxv16i8_nxv16i16( %va) { ; CHECK-LABEL: vsext_nxv16i8_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -280,8 +280,8 @@ define @vzext_nxv16i8_nxv16i16( %va) { ; CHECK-LABEL: vzext_nxv16i8_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -335,8 +335,8 @@ define @vsext_nxv1i16_nxv1i32( %va) { ; CHECK-LABEL: vsext_nxv1i16_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -346,8 +346,8 @@ define @vzext_nxv1i16_nxv1i32( %va) { ; CHECK-LABEL: vzext_nxv1i16_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -357,8 +357,8 @@ define @vsext_nxv1i16_nxv1i64( %va) { ; CHECK-LABEL: vsext_nxv1i16_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -368,8 +368,8 @@ define @vzext_nxv1i16_nxv1i64( %va) { ; CHECK-LABEL: vzext_nxv1i16_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -379,8 +379,8 @@ define @vsext_nxv2i16_nxv2i32( %va) { ; CHECK-LABEL: vsext_nxv2i16_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -390,8 +390,8 @@ define @vzext_nxv2i16_nxv2i32( %va) { ; CHECK-LABEL: vzext_nxv2i16_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -401,8 +401,8 @@ define @vsext_nxv2i16_nxv2i64( %va) { ; CHECK-LABEL: vsext_nxv2i16_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -412,8 +412,8 @@ define @vzext_nxv2i16_nxv2i64( %va) { ; CHECK-LABEL: vzext_nxv2i16_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -423,8 +423,8 @@ define @vsext_nxv4i16_nxv4i32( %va) { ; CHECK-LABEL: vsext_nxv4i16_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -434,8 +434,8 @@ define @vzext_nxv4i16_nxv4i32( %va) { ; CHECK-LABEL: vzext_nxv4i16_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -445,8 +445,8 @@ define @vsext_nxv4i16_nxv4i64( %va) { ; CHECK-LABEL: vsext_nxv4i16_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -456,8 +456,8 @@ define @vzext_nxv4i16_nxv4i64( %va) { ; CHECK-LABEL: vzext_nxv4i16_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -467,8 +467,8 @@ define @vsext_nxv8i16_nxv8i32( %va) { ; CHECK-LABEL: vsext_nxv8i16_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -478,8 +478,8 @@ define @vzext_nxv8i16_nxv8i32( %va) { ; CHECK-LABEL: vzext_nxv8i16_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -533,8 +533,8 @@ define @vsext_nxv1i32_nxv1i64( %va) { ; CHECK-LABEL: vsext_nxv1i32_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -544,8 +544,8 @@ define @vzext_nxv1i32_nxv1i64( %va) { ; CHECK-LABEL: vzext_nxv1i32_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -555,8 +555,8 @@ define @vsext_nxv2i32_nxv2i64( %va) { ; CHECK-LABEL: vsext_nxv2i32_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -566,8 +566,8 @@ define @vzext_nxv2i32_nxv2i64( %va) { ; CHECK-LABEL: vzext_nxv2i32_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -577,8 +577,8 @@ define @vsext_nxv4i32_nxv4i64( %va) { ; CHECK-LABEL: vsext_nxv4i32_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -588,8 +588,8 @@ define @vzext_nxv4i32_nxv4i64( %va) { ; CHECK-LABEL: vzext_nxv4i32_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = zext %va to ret %evec diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll index c3c40aed3670675f3b0ecb7f02de95c6f9a91b58..eb990e28e877d7ec99c8f9a40933f59757524902 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll @@ -32,9 +32,9 @@ define @vfadd_vf_nxv1f16( %va, half %b, < ; CHECK-LABEL: vfadd_vf_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -46,9 +46,9 @@ define @vfadd_vf_nxv1f16_unmasked( %va, h ; CHECK-LABEL: vfadd_vf_nxv1f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -86,9 +86,9 @@ define @vfadd_vf_nxv2f16( %va, half %b, < ; CHECK-LABEL: vfadd_vf_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -100,9 +100,9 @@ define @vfadd_vf_nxv2f16_unmasked( %va, h ; CHECK-LABEL: vfadd_vf_nxv2f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -140,9 +140,9 @@ define @vfadd_vf_nxv4f16( %va, half %b, < ; CHECK-LABEL: vfadd_vf_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -154,9 +154,9 @@ define @vfadd_vf_nxv4f16_unmasked( %va, h ; CHECK-LABEL: vfadd_vf_nxv4f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -194,9 +194,9 @@ define @vfadd_vf_nxv8f16( %va, half %b, < ; CHECK-LABEL: vfadd_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -208,9 +208,9 @@ define @vfadd_vf_nxv8f16_unmasked( %va, h ; CHECK-LABEL: vfadd_vf_nxv8f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v26 +; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -248,9 +248,9 @@ define @vfadd_vf_nxv16f16( %va, half %b ; CHECK-LABEL: vfadd_vf_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -262,9 +262,9 @@ define @vfadd_vf_nxv16f16_unmasked( %va ; CHECK-LABEL: vfadd_vf_nxv16f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v28 +; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -356,9 +356,9 @@ define @vfadd_vf_nxv1f32( %va, float %b ; CHECK-LABEL: vfadd_vf_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -370,9 +370,9 @@ define @vfadd_vf_nxv1f32_unmasked( %va, ; CHECK-LABEL: vfadd_vf_nxv1f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -410,9 +410,9 @@ define @vfadd_vf_nxv2f32( %va, float %b ; CHECK-LABEL: vfadd_vf_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -424,9 +424,9 @@ define @vfadd_vf_nxv2f32_unmasked( %va, ; CHECK-LABEL: vfadd_vf_nxv2f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -464,9 +464,9 @@ define @vfadd_vf_nxv4f32( %va, float %b ; CHECK-LABEL: vfadd_vf_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -478,9 +478,9 @@ define @vfadd_vf_nxv4f32_unmasked( %va, ; CHECK-LABEL: vfadd_vf_nxv4f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v26 +; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -518,9 +518,9 @@ define @vfadd_vf_nxv8f32( %va, float %b ; CHECK-LABEL: vfadd_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -532,9 +532,9 @@ define @vfadd_vf_nxv8f32_unmasked( %va, ; CHECK-LABEL: vfadd_vf_nxv8f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v28 +; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -626,9 +626,9 @@ define @vfadd_vf_nxv1f64( %va, double ; CHECK-LABEL: vfadd_vf_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -640,9 +640,9 @@ define @vfadd_vf_nxv1f64_unmasked( %v ; CHECK-LABEL: vfadd_vf_nxv1f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v25 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -680,9 +680,9 @@ define @vfadd_vf_nxv2f64( %va, double ; CHECK-LABEL: vfadd_vf_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -694,9 +694,9 @@ define @vfadd_vf_nxv2f64_unmasked( %v ; CHECK-LABEL: vfadd_vf_nxv2f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v26 +; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -734,9 +734,9 @@ define @vfadd_vf_nxv4f64( %va, double ; CHECK-LABEL: vfadd_vf_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfadd.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -748,9 +748,9 @@ define @vfadd_vf_nxv4f64_unmasked( %v ; CHECK-LABEL: vfadd_vf_nxv4f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfadd.vv v8, v8, v28 +; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll index 6763f13e09dce93e49be579b7015a86559f6152e..a4657bd8949c25ac1b92167649def18aacbfaf5f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll @@ -56,8 +56,8 @@ define @vfcopysign_exttrunc_vv_nxv1f16_nxv1f32( %vs to %r = call @llvm.copysign.nxv1f16( %vm, %e) @@ -68,10 +68,10 @@ define @vfcopysign_exttrunc_vf_nxv1f16_nxv1f32( undef, float %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -84,8 +84,8 @@ define @vfcopynsign_exttrunc_vv_nxv1f16_nxv1f32( %vs %eneg = fptrunc %n to @@ -97,10 +97,10 @@ define @vfcopynsign_exttrunc_vf_nxv1f16_nxv1f32( undef, float %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -114,10 +114,10 @@ define @vfcopysign_exttrunc_vv_nxv1f16_nxv1f64( %vs to %r = call @llvm.copysign.nxv1f16( %vm, %e) @@ -128,12 +128,12 @@ define @vfcopysign_exttrunc_vf_nxv1f16_nxv1f64( undef, double %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -146,10 +146,10 @@ define @vfcopynsign_exttrunc_vv_nxv1f16_nxv1f64( %vs %eneg = fptrunc %n to @@ -161,12 +161,12 @@ define @vfcopynsign_exttrunc_vf_nxv1f16_nxv1f64( undef, double %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -324,8 +324,8 @@ define @vfcopysign_exttrunc_vv_nxv8f16_nxv8f32( %vs to %r = call @llvm.copysign.nxv8f16( %vm, %e) @@ -336,10 +336,10 @@ define @vfcopysign_exttrunc_vf_nxv8f16_nxv8f32( undef, float %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -352,8 +352,8 @@ define @vfcopynsign_exttrunc_vv_nxv8f16_nxv8f32( %vs %eneg = fptrunc %n to @@ -365,10 +365,10 @@ define @vfcopynsign_exttrunc_vf_nxv8f16_nxv8f32( undef, float %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -382,10 +382,10 @@ define @vfcopysign_exttrunc_vv_nxv8f16_nxv8f64( %vs to %r = call @llvm.copysign.nxv8f16( %vm, %e) @@ -398,10 +398,10 @@ define @vfcopysign_exttrunc_vf_nxv8f16_nxv8f64( undef, double %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -414,10 +414,10 @@ define @vfcopynsign_exttrunc_vv_nxv8f16_nxv8f64( %vs %eneg = fptrunc %n to @@ -431,10 +431,10 @@ define @vfcopynsign_exttrunc_vf_nxv8f16_nxv8f64( undef, double %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -592,9 +592,9 @@ define @vfcopysign_exttrunc_vv_nxv1f32_nxv1f16( %vs to %r = call @llvm.copysign.nxv1f32( %vm, %e) @@ -605,10 +605,10 @@ define @vfcopysign_exttrunc_vf_nxv1f32_nxv1f16( undef, half %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -621,9 +621,9 @@ define @vfcopynsign_exttrunc_vv_nxv1f32_nxv1f16( %vs %eneg = fpext %n to @@ -635,10 +635,10 @@ define @vfcopynsign_exttrunc_vf_nxv1f32_nxv1f16( undef, half %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -652,8 +652,8 @@ define @vfcopysign_exttrunc_vv_nxv1f32_nxv1f64( %vs to %r = call @llvm.copysign.nxv1f32( %vm, %e) @@ -664,10 +664,10 @@ define @vfcopysign_exttrunc_vf_nxv1f32_nxv1f64( undef, double %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -680,8 +680,8 @@ define @vfcopynsign_exttrunc_vv_nxv1f32_nxv1f64( %vs %eneg = fptrunc %n to @@ -693,10 +693,10 @@ define @vfcopynsign_exttrunc_vf_nxv1f32_nxv1f64( undef, double %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -854,9 +854,9 @@ define @vfcopysign_exttrunc_vv_nxv8f32_nxv8f16( %vs to %r = call @llvm.copysign.nxv8f32( %vm, %e) @@ -867,10 +867,10 @@ define @vfcopysign_exttrunc_vf_nxv8f32_nxv8f16( undef, half %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -883,9 +883,9 @@ define @vfcopynsign_exttrunc_vv_nxv8f32_nxv8f16( %vs %eneg = fpext %n to @@ -897,10 +897,10 @@ define @vfcopynsign_exttrunc_vf_nxv8f32_nxv8f16( undef, half %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -914,8 +914,8 @@ define @vfcopysign_exttrunc_vv_nxv8f32_nxv8f64( %vs to %r = call @llvm.copysign.nxv8f32( %vm, %e) @@ -928,8 +928,8 @@ define @vfcopysign_exttrunc_vf_nxv8f32_nxv8f64( undef, double %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -942,8 +942,8 @@ define @vfcopynsign_exttrunc_vv_nxv8f32_nxv8f64( %vs %eneg = fptrunc %n to @@ -957,8 +957,8 @@ define @vfcopynsign_exttrunc_vf_nxv8f32_nxv8f64( undef, double %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1068,11 +1068,11 @@ define @vfcopysign_exttrunc_vv_nxv1f64_nxv1f16( %vs to %r = call @llvm.copysign.nxv1f64( %vm, %e) @@ -1083,12 +1083,12 @@ define @vfcopysign_exttrunc_vf_nxv1f64_nxv1f16( undef, half %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1101,11 +1101,11 @@ define @vfcopynsign_exttrunc_vv_nxv1f64_nxv1f16( %vs %eneg = fpext %n to @@ -1117,12 +1117,12 @@ define @vfcopynsign_exttrunc_vf_nxv1f64_nxv1f16( undef, half %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1136,9 +1136,9 @@ define @vfcopysign_exttrunc_vv_nxv1f64_nxv1f32( %vs to %r = call @llvm.copysign.nxv1f64( %vm, %e) @@ -1149,10 +1149,10 @@ define @vfcopysign_exttrunc_vf_nxv1f64_nxv1f32( undef, float %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1165,9 +1165,9 @@ define @vfcopynsign_exttrunc_vv_nxv1f64_nxv1f32( %vs %eneg = fpext %n to @@ -1179,10 +1179,10 @@ define @vfcopynsign_exttrunc_vf_nxv1f64_nxv1f32( undef, float %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1340,11 +1340,11 @@ define @vfcopysign_exttrunc_vv_nxv8f64_nxv8f16( %vs to %r = call @llvm.copysign.nxv8f64( %vm, %e) @@ -1355,12 +1355,12 @@ define @vfcopysign_exttrunc_vf_nxv8f64_nxv8f16( undef, half %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1373,11 +1373,11 @@ define @vfcopynsign_exttrunc_vv_nxv8f64_nxv8f16( %vs %eneg = fpext %n to @@ -1389,12 +1389,12 @@ define @vfcopynsign_exttrunc_vf_nxv8f64_nxv8f16( undef, half %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1421,10 +1421,10 @@ define @vfcopysign_exttrunc_vf_nxv8f64_nxv8f32( undef, float %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1451,10 +1451,10 @@ define @vfcopynsign_exttrunc_vf_nxv8f64_nxv8f32( undef, float %s, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll index 4146f215730c72eadba1c506a6914b6348557328..4bf8a4ac42ee8ffa40fc2eae0ffb36fdce28d563 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll @@ -32,9 +32,9 @@ define @vfdiv_vf_nxv1f16( %va, half %b, < ; CHECK-LABEL: vfdiv_vf_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -46,9 +46,9 @@ define @vfdiv_vf_nxv1f16_unmasked( %va, h ; CHECK-LABEL: vfdiv_vf_nxv1f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -86,9 +86,9 @@ define @vfdiv_vf_nxv2f16( %va, half %b, < ; CHECK-LABEL: vfdiv_vf_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -100,9 +100,9 @@ define @vfdiv_vf_nxv2f16_unmasked( %va, h ; CHECK-LABEL: vfdiv_vf_nxv2f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -140,9 +140,9 @@ define @vfdiv_vf_nxv4f16( %va, half %b, < ; CHECK-LABEL: vfdiv_vf_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -154,9 +154,9 @@ define @vfdiv_vf_nxv4f16_unmasked( %va, h ; CHECK-LABEL: vfdiv_vf_nxv4f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -194,9 +194,9 @@ define @vfdiv_vf_nxv8f16( %va, half %b, < ; CHECK-LABEL: vfdiv_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -208,9 +208,9 @@ define @vfdiv_vf_nxv8f16_unmasked( %va, h ; CHECK-LABEL: vfdiv_vf_nxv8f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v26 +; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -248,9 +248,9 @@ define @vfdiv_vf_nxv16f16( %va, half %b ; CHECK-LABEL: vfdiv_vf_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -262,9 +262,9 @@ define @vfdiv_vf_nxv16f16_unmasked( %va ; CHECK-LABEL: vfdiv_vf_nxv16f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v28 +; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -356,9 +356,9 @@ define @vfdiv_vf_nxv1f32( %va, float %b ; CHECK-LABEL: vfdiv_vf_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -370,9 +370,9 @@ define @vfdiv_vf_nxv1f32_unmasked( %va, ; CHECK-LABEL: vfdiv_vf_nxv1f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -410,9 +410,9 @@ define @vfdiv_vf_nxv2f32( %va, float %b ; CHECK-LABEL: vfdiv_vf_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -424,9 +424,9 @@ define @vfdiv_vf_nxv2f32_unmasked( %va, ; CHECK-LABEL: vfdiv_vf_nxv2f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -464,9 +464,9 @@ define @vfdiv_vf_nxv4f32( %va, float %b ; CHECK-LABEL: vfdiv_vf_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -478,9 +478,9 @@ define @vfdiv_vf_nxv4f32_unmasked( %va, ; CHECK-LABEL: vfdiv_vf_nxv4f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v26 +; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -518,9 +518,9 @@ define @vfdiv_vf_nxv8f32( %va, float %b ; CHECK-LABEL: vfdiv_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -532,9 +532,9 @@ define @vfdiv_vf_nxv8f32_unmasked( %va, ; CHECK-LABEL: vfdiv_vf_nxv8f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v28 +; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -626,9 +626,9 @@ define @vfdiv_vf_nxv1f64( %va, double ; CHECK-LABEL: vfdiv_vf_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -640,9 +640,9 @@ define @vfdiv_vf_nxv1f64_unmasked( %v ; CHECK-LABEL: vfdiv_vf_nxv1f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v25 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -680,9 +680,9 @@ define @vfdiv_vf_nxv2f64( %va, double ; CHECK-LABEL: vfdiv_vf_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -694,9 +694,9 @@ define @vfdiv_vf_nxv2f64_unmasked( %v ; CHECK-LABEL: vfdiv_vf_nxv2f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v26 +; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -734,9 +734,9 @@ define @vfdiv_vf_nxv4f64( %va, double ; CHECK-LABEL: vfdiv_vf_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfdiv.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -748,9 +748,9 @@ define @vfdiv_vf_nxv4f64_unmasked( %v ; CHECK-LABEL: vfdiv_vf_nxv4f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v8, v28 +; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll index 8c8927704fd480a2cb78f70e2c8e94ffb963c92f..dab1544783435adc16057fe7f637648ffebe87e8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll @@ -27,10 +27,10 @@ declare i32 @llvm.riscv.vfirst.mask.i32.nxv1i1( define i32 @intrinsic_vfirst_mask_m_i32_nxv1i1( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv1i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: vfirst.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vfirst.mask.i32.nxv1i1( @@ -67,10 +67,10 @@ declare i32 @llvm.riscv.vfirst.mask.i32.nxv2i1( define i32 @intrinsic_vfirst_mask_m_i32_nxv2i1( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv2i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: vfirst.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vfirst.mask.i32.nxv2i1( @@ -107,10 +107,10 @@ declare i32 @llvm.riscv.vfirst.mask.i32.nxv4i1( define i32 @intrinsic_vfirst_mask_m_i32_nxv4i1( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv4i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: vfirst.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vfirst.mask.i32.nxv4i1( @@ -147,10 +147,10 @@ declare i32 @llvm.riscv.vfirst.mask.i32.nxv8i1( define i32 @intrinsic_vfirst_mask_m_i32_nxv8i1( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv8i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: vfirst.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vfirst.mask.i32.nxv8i1( @@ -187,10 +187,10 @@ declare i32 @llvm.riscv.vfirst.mask.i32.nxv16i1( define i32 @intrinsic_vfirst_mask_m_i32_nxv16i1( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv16i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: vfirst.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vfirst.mask.i32.nxv16i1( @@ -227,10 +227,10 @@ declare i32 @llvm.riscv.vfirst.mask.i32.nxv32i1( define i32 @intrinsic_vfirst_mask_m_i32_nxv32i1( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv32i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: vfirst.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vfirst.mask.i32.nxv32i1( @@ -267,10 +267,10 @@ declare i32 @llvm.riscv.vfirst.mask.i32.nxv64i1( define i32 @intrinsic_vfirst_mask_m_i32_nxv64i1( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv64i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: vfirst.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vfirst.mask.i32.nxv64i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll index 65762fac2581740707149ab408a62c063902412b..005d023207bfe53f065fb624de2bff8a4b698f57 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll @@ -27,10 +27,10 @@ declare i64 @llvm.riscv.vfirst.mask.i64.nxv1i1( define i64 @intrinsic_vfirst_mask_m_i64_nxv1i1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv1i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: vfirst.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv1i1( @@ -67,10 +67,10 @@ declare i64 @llvm.riscv.vfirst.mask.i64.nxv2i1( define i64 @intrinsic_vfirst_mask_m_i64_nxv2i1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv2i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: vfirst.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv2i1( @@ -107,10 +107,10 @@ declare i64 @llvm.riscv.vfirst.mask.i64.nxv4i1( define i64 @intrinsic_vfirst_mask_m_i64_nxv4i1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv4i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: vfirst.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv4i1( @@ -147,10 +147,10 @@ declare i64 @llvm.riscv.vfirst.mask.i64.nxv8i1( define i64 @intrinsic_vfirst_mask_m_i64_nxv8i1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv8i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: vfirst.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv8i1( @@ -187,10 +187,10 @@ declare i64 @llvm.riscv.vfirst.mask.i64.nxv16i1( define i64 @intrinsic_vfirst_mask_m_i64_nxv16i1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv16i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: vfirst.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv16i1( @@ -227,10 +227,10 @@ declare i64 @llvm.riscv.vfirst.mask.i64.nxv32i1( define i64 @intrinsic_vfirst_mask_m_i64_nxv32i1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv32i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: vfirst.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv32i1( @@ -267,10 +267,10 @@ declare i64 @llvm.riscv.vfirst.mask.i64.nxv64i1( define i64 @intrinsic_vfirst_mask_m_i64_nxv64i1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv64i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: vfirst.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv64i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll index a474d5907d95ac1b311d32f81872a65ab1ac47cb..23a45a26f0d32d55d46920ad4b915ab1664993c5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll @@ -32,9 +32,9 @@ define @vfmul_vf_nxv1f16( %va, half %b, < ; CHECK-LABEL: vfmul_vf_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -46,9 +46,9 @@ define @vfmul_vf_nxv1f16_unmasked( %va, h ; CHECK-LABEL: vfmul_vf_nxv1f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -86,9 +86,9 @@ define @vfmul_vf_nxv2f16( %va, half %b, < ; CHECK-LABEL: vfmul_vf_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -100,9 +100,9 @@ define @vfmul_vf_nxv2f16_unmasked( %va, h ; CHECK-LABEL: vfmul_vf_nxv2f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -140,9 +140,9 @@ define @vfmul_vf_nxv4f16( %va, half %b, < ; CHECK-LABEL: vfmul_vf_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -154,9 +154,9 @@ define @vfmul_vf_nxv4f16_unmasked( %va, h ; CHECK-LABEL: vfmul_vf_nxv4f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -194,9 +194,9 @@ define @vfmul_vf_nxv8f16( %va, half %b, < ; CHECK-LABEL: vfmul_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -208,9 +208,9 @@ define @vfmul_vf_nxv8f16_unmasked( %va, h ; CHECK-LABEL: vfmul_vf_nxv8f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v26 +; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -248,9 +248,9 @@ define @vfmul_vf_nxv16f16( %va, half %b ; CHECK-LABEL: vfmul_vf_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -262,9 +262,9 @@ define @vfmul_vf_nxv16f16_unmasked( %va ; CHECK-LABEL: vfmul_vf_nxv16f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v28 +; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -356,9 +356,9 @@ define @vfmul_vf_nxv1f32( %va, float %b ; CHECK-LABEL: vfmul_vf_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -370,9 +370,9 @@ define @vfmul_vf_nxv1f32_unmasked( %va, ; CHECK-LABEL: vfmul_vf_nxv1f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -410,9 +410,9 @@ define @vfmul_vf_nxv2f32( %va, float %b ; CHECK-LABEL: vfmul_vf_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -424,9 +424,9 @@ define @vfmul_vf_nxv2f32_unmasked( %va, ; CHECK-LABEL: vfmul_vf_nxv2f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -464,9 +464,9 @@ define @vfmul_vf_nxv4f32( %va, float %b ; CHECK-LABEL: vfmul_vf_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -478,9 +478,9 @@ define @vfmul_vf_nxv4f32_unmasked( %va, ; CHECK-LABEL: vfmul_vf_nxv4f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v26 +; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -518,9 +518,9 @@ define @vfmul_vf_nxv8f32( %va, float %b ; CHECK-LABEL: vfmul_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -532,9 +532,9 @@ define @vfmul_vf_nxv8f32_unmasked( %va, ; CHECK-LABEL: vfmul_vf_nxv8f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v28 +; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -626,9 +626,9 @@ define @vfmul_vf_nxv1f64( %va, double ; CHECK-LABEL: vfmul_vf_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -640,9 +640,9 @@ define @vfmul_vf_nxv1f64_unmasked( %v ; CHECK-LABEL: vfmul_vf_nxv1f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v25 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -680,9 +680,9 @@ define @vfmul_vf_nxv2f64( %va, double ; CHECK-LABEL: vfmul_vf_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -694,9 +694,9 @@ define @vfmul_vf_nxv2f64_unmasked( %v ; CHECK-LABEL: vfmul_vf_nxv2f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v26 +; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -734,9 +734,9 @@ define @vfmul_vf_nxv4f64( %va, double ; CHECK-LABEL: vfmul_vf_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfmul.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -748,9 +748,9 @@ define @vfmul_vf_nxv4f64_unmasked( %v ; CHECK-LABEL: vfmul_vf_nxv4f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfmul.vv v8, v8, v28 +; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll index 5a6d5ad01fb71107427c4e20a7d924aa6de6783d..85d4cdd92319105ed838a6c8b099a9f7356d4f97 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32( @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32( @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32( @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32( @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32( @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64( @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64( @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64( @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64( @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll index cfda8166c53beee0cbd90c765c4247639a1f1738..aa28c03325868b612eece7665d6dce81edbb8586 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32( @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32( @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32( @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32( @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32( @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64( @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64( @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64( @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64( @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll index 2d8d9afc4497f392f9814e7f10a45bde8ecfa87a..05731ea19ac59e9b84f088bac7eef74c0c7a27ed 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32( @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32( @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32( @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32( @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32( @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64( @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64( @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64( @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64( @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll index 084c2be2aa4a20ec633a76e33faf4cf8b24c6adc..c41dae4d71e593dd074d7e31bc1b752cf03ab059 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32( @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32( @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32( @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32( @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32( @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64( @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64( @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64( @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64( @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll index 6e348bc613ce0f4810f478f23f548fde255b2bfd..057ce7b68c3daa88d33fa72dee4172b7d24c8838 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32( @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32( @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32( @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32( @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32( @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64( @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64( @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64( @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64( @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll index c7e22d42a84534623add61d283d9c17d0a948a69..5ab93002bfbf9fbc12ec7680144d02ff49f1d785 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32( @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32( @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32( @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32( @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32( @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64( @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64( @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64( @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64( @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll index c7f735ee9bf773197e810c3641eaa2c02d069bd0..a3fb4007c9dd4ea2077968999da492b4cc3c1f48 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32( @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32( @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32( @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32( @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32( @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64( @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64( @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64( @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64( @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll index 4dc5208e4010ec78faa94339b6063dcec0dfb7fe..7b68b285fed67665fcfbc00b0125408b725fc94f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32( @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32( @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32( @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32( @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32( @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64( @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64( @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64( @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64( @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll index 8f691aad14a4588af6b8b51704d6dfe3d47d8911..19c33df377e0b09a6c8440b97632332e4504b712 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16( @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16( @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16( @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16( @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16( @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16( @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32( @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i16.nxv1f32( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32( @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i16.nxv2f32( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32( @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i16.nxv4f32( @@ -387,8 +387,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32( @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i16.nxv8f32( @@ -429,8 +429,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32( @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i16.nxv16f32( @@ -471,8 +471,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64( @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i32.nxv1f64( @@ -513,8 +513,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64( @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i32.nxv2f64( @@ -555,8 +555,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64( @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i32.nxv4f64( @@ -597,8 +597,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64( @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll index e1866ffe0e9a4cc2b101d93cad5e9471638be840..fe2166a99784809704d95e4a421a31dd99d18b85 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16( @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16( @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16( @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16( @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16( @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16( @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32( @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i16.nxv1f32( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32( @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i16.nxv2f32( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32( @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i16.nxv4f32( @@ -387,8 +387,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32( @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i16.nxv8f32( @@ -429,8 +429,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32( @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i16.nxv16f32( @@ -471,8 +471,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64( @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i32.nxv1f64( @@ -513,8 +513,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64( @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i32.nxv2f64( @@ -555,8 +555,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64( @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i32.nxv4f64( @@ -597,8 +597,8 @@ define @intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64( @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll index b762b097286a960a6d167f23f6b1253e2c0de1eb..cac42418bf8fe6920e839a9d026f6e50b1a1b1f2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i16.nxv1f32( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i16.nxv2f32( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i16.nxv4f32( @@ -387,8 +387,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i16.nxv8f32( @@ -429,8 +429,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i16.nxv16f32( @@ -471,8 +471,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i32.nxv1f64( @@ -513,8 +513,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i32.nxv2f64( @@ -555,8 +555,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i32.nxv4f64( @@ -597,8 +597,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll index d9c0605fdb3a9b244010974aa795b8190b74e890..d96c48495667e2323271bcc8bb3c1d320395aa3a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i16.nxv1f32( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i16.nxv2f32( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i16.nxv4f32( @@ -387,8 +387,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i16.nxv8f32( @@ -429,8 +429,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i16.nxv16f32( @@ -471,8 +471,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i32.nxv1f64( @@ -513,8 +513,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i32.nxv2f64( @@ -555,8 +555,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i32.nxv4f64( @@ -597,8 +597,8 @@ define @intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64( @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll index 4d824137eeaf1d6c52759fd3d1ab3fe72ef824fe..c87f39e4067642972e4b9d9b6bbd2f495bbe4225 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16( @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16( @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16( @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16( @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16( @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16( @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32( @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32( @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32( @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32( @@ -387,8 +387,8 @@ define @intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32( @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32( @@ -429,8 +429,8 @@ define @intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32( @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32( @@ -471,8 +471,8 @@ define @intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64( @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64( @@ -513,8 +513,8 @@ define @intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64( @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64( @@ -555,8 +555,8 @@ define @intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64( @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64( @@ -597,8 +597,8 @@ define @intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64( @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll index 593e12d894f7bd46632404576e4e90dc56726e36..6b1d672afea2f992ff0341d8ae5c9b24d389646e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16( @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16( @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16( @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16( @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16( @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16( @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32( @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32( @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32( @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32( @@ -387,8 +387,8 @@ define @intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32( @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32( @@ -429,8 +429,8 @@ define @intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32( @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32( @@ -471,8 +471,8 @@ define @intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64( @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64( @@ -513,8 +513,8 @@ define @intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64( @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64( @@ -555,8 +555,8 @@ define @intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64( @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64( @@ -597,8 +597,8 @@ define @intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64( @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll index a340dc7cc7460a1e6278aa0e674cfb3e604d875c..daa4633aa0a85dbf1ffcb6be50884f36191807c6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16( @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16( @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16( @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16( @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16( @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16( @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32( @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32( @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32( @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32( @@ -387,8 +387,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32( @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32( @@ -429,8 +429,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32( @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32( @@ -471,8 +471,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64( @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64( @@ -513,8 +513,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64( @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64( @@ -555,8 +555,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64( @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64( @@ -597,8 +597,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64( @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll index 793cc88eeabf56de53c396cdd692c18c3a797eb0..e5f790f766c691e9e8f45da6c868d32ff6cd840b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16( @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16( @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16( @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16( @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16( @@ -177,8 +177,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16( @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16( @@ -219,8 +219,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16( @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16( @@ -261,8 +261,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32( @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32( @@ -303,8 +303,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32( @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32( @@ -345,8 +345,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32( @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32( @@ -387,8 +387,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32( @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32( @@ -429,8 +429,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32( @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32( @@ -471,8 +471,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64( @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64( @@ -513,8 +513,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64( @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64( @@ -555,8 +555,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64( @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64( @@ -597,8 +597,8 @@ define @intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64( @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll index 4648ad074f7debd2e9d21dc9a2f790d465737d38..c5b1a90a8f5a183446ace48aca17a400067078e7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll @@ -9,15 +9,15 @@ define @vfpext_nxv1f16_nxv1f32( %va) { ; RV32-LABEL: vfpext_nxv1f16_nxv1f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; RV32-NEXT: vfwcvt.f.f.v v25, v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vfwcvt.f.f.v v9, v8 +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vfpext_nxv1f16_nxv1f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; RV64-NEXT: vfwcvt.f.f.v v25, v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vfwcvt.f.f.v v9, v8 +; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %evec = fpext %va to ret %evec @@ -28,17 +28,17 @@ define @vfpext_nxv1f16_nxv1f64( %va) { ; RV32-LABEL: vfpext_nxv1f16_nxv1f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; RV32-NEXT: vfwcvt.f.f.v v25, v8 +; RV32-NEXT: vfwcvt.f.f.v v9, v8 ; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; RV32-NEXT: vfwcvt.f.f.v v8, v25 +; RV32-NEXT: vfwcvt.f.f.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vfpext_nxv1f16_nxv1f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; RV64-NEXT: vfwcvt.f.f.v v25, v8 +; RV64-NEXT: vfwcvt.f.f.v v9, v8 ; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; RV64-NEXT: vfwcvt.f.f.v v8, v25 +; RV64-NEXT: vfwcvt.f.f.v v8, v9 ; RV64-NEXT: ret %evec = fpext %va to ret %evec @@ -49,15 +49,15 @@ define @vfpext_nxv2f16_nxv2f32( %va) { ; RV32-LABEL: vfpext_nxv2f16_nxv2f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; RV32-NEXT: vfwcvt.f.f.v v25, v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vfwcvt.f.f.v v9, v8 +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vfpext_nxv2f16_nxv2f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; RV64-NEXT: vfwcvt.f.f.v v25, v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vfwcvt.f.f.v v9, v8 +; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %evec = fpext %va to ret %evec @@ -68,17 +68,17 @@ define @vfpext_nxv2f16_nxv2f64( %va) { ; RV32-LABEL: vfpext_nxv2f16_nxv2f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; RV32-NEXT: vfwcvt.f.f.v v25, v8 +; RV32-NEXT: vfwcvt.f.f.v v10, v8 ; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; RV32-NEXT: vfwcvt.f.f.v v8, v25 +; RV32-NEXT: vfwcvt.f.f.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vfpext_nxv2f16_nxv2f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; RV64-NEXT: vfwcvt.f.f.v v25, v8 +; RV64-NEXT: vfwcvt.f.f.v v10, v8 ; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; RV64-NEXT: vfwcvt.f.f.v v8, v25 +; RV64-NEXT: vfwcvt.f.f.v v8, v10 ; RV64-NEXT: ret %evec = fpext %va to ret %evec @@ -89,15 +89,15 @@ define @vfpext_nxv4f16_nxv4f32( %va) { ; RV32-LABEL: vfpext_nxv4f16_nxv4f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; RV32-NEXT: vfwcvt.f.f.v v26, v8 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vfwcvt.f.f.v v10, v8 +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vfpext_nxv4f16_nxv4f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; RV64-NEXT: vfwcvt.f.f.v v26, v8 -; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: vfwcvt.f.f.v v10, v8 +; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %evec = fpext %va to ret %evec @@ -108,17 +108,17 @@ define @vfpext_nxv4f16_nxv4f64( %va) { ; RV32-LABEL: vfpext_nxv4f16_nxv4f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; RV32-NEXT: vfwcvt.f.f.v v26, v8 +; RV32-NEXT: vfwcvt.f.f.v v12, v8 ; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV32-NEXT: vfwcvt.f.f.v v8, v26 +; RV32-NEXT: vfwcvt.f.f.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vfpext_nxv4f16_nxv4f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; RV64-NEXT: vfwcvt.f.f.v v26, v8 +; RV64-NEXT: vfwcvt.f.f.v v12, v8 ; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; RV64-NEXT: vfwcvt.f.f.v v8, v26 +; RV64-NEXT: vfwcvt.f.f.v v8, v12 ; RV64-NEXT: ret %evec = fpext %va to ret %evec @@ -129,15 +129,15 @@ define @vfpext_nxv8f16_nxv8f32( %va) { ; RV32-LABEL: vfpext_nxv8f16_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; RV32-NEXT: vfwcvt.f.f.v v28, v8 -; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: vfwcvt.f.f.v v12, v8 +; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vfpext_nxv8f16_nxv8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; RV64-NEXT: vfwcvt.f.f.v v28, v8 -; RV64-NEXT: vmv4r.v v8, v28 +; RV64-NEXT: vfwcvt.f.f.v v12, v8 +; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %evec = fpext %va to ret %evec @@ -148,17 +148,17 @@ define @vfpext_nxv8f16_nxv8f64( %va) { ; RV32-LABEL: vfpext_nxv8f16_nxv8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; RV32-NEXT: vfwcvt.f.f.v v28, v8 +; RV32-NEXT: vfwcvt.f.f.v v16, v8 ; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu -; RV32-NEXT: vfwcvt.f.f.v v8, v28 +; RV32-NEXT: vfwcvt.f.f.v v8, v16 ; RV32-NEXT: ret ; ; RV64-LABEL: vfpext_nxv8f16_nxv8f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; RV64-NEXT: vfwcvt.f.f.v v28, v8 +; RV64-NEXT: vfwcvt.f.f.v v16, v8 ; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, mu -; RV64-NEXT: vfwcvt.f.f.v v8, v28 +; RV64-NEXT: vfwcvt.f.f.v v8, v16 ; RV64-NEXT: ret %evec = fpext %va to ret %evec @@ -188,15 +188,15 @@ define @vfpext_nxv1f32_nxv1f64( %va) { ; RV32-LABEL: vfpext_nxv1f32_nxv1f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; RV32-NEXT: vfwcvt.f.f.v v25, v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vfwcvt.f.f.v v9, v8 +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vfpext_nxv1f32_nxv1f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; RV64-NEXT: vfwcvt.f.f.v v25, v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vfwcvt.f.f.v v9, v8 +; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %evec = fpext %va to ret %evec @@ -207,15 +207,15 @@ define @vfpext_nxv2f32_nxv2f64( %va) { ; RV32-LABEL: vfpext_nxv2f32_nxv2f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV32-NEXT: vfwcvt.f.f.v v26, v8 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vfwcvt.f.f.v v10, v8 +; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vfpext_nxv2f32_nxv2f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV64-NEXT: vfwcvt.f.f.v v26, v8 -; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: vfwcvt.f.f.v v10, v8 +; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: ret %evec = fpext %va to ret %evec @@ -226,15 +226,15 @@ define @vfpext_nxv4f32_nxv4f64( %va) { ; RV32-LABEL: vfpext_nxv4f32_nxv4f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; RV32-NEXT: vfwcvt.f.f.v v28, v8 -; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: vfwcvt.f.f.v v12, v8 +; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vfpext_nxv4f32_nxv4f64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; RV64-NEXT: vfwcvt.f.f.v v28, v8 -; RV64-NEXT: vmv4r.v v8, v28 +; RV64-NEXT: vfwcvt.f.f.v v12, v8 +; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: ret %evec = fpext %va to ret %evec diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll index 83d376302f2613de2182be455bed8cf7b826775a..692c8fdf472c2420e23647b7ccbd1b1ce8f9c05d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll @@ -8,9 +8,9 @@ define @vfptosi_nxv1f16_nxv1i1( %va) { ; CHECK-LABEL: vfptosi_nxv1f16_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -20,9 +20,9 @@ define @vfptoui_nxv1f16_nxv1i1( %va) { ; CHECK-LABEL: vfptoui_nxv1f16_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -32,8 +32,8 @@ define @vfptosi_nxv1f16_nxv1i8( %va) { ; CHECK-LABEL: vfptosi_nxv1f16_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -43,8 +43,8 @@ define @vfptoui_nxv1f16_nxv1i8( %va) { ; CHECK-LABEL: vfptoui_nxv1f16_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -74,8 +74,8 @@ define @vfptosi_nxv1f16_nxv1i32( %va) { ; CHECK-LABEL: vfptosi_nxv1f16_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -85,8 +85,8 @@ define @vfptoui_nxv1f16_nxv1i32( %va) { ; CHECK-LABEL: vfptoui_nxv1f16_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -96,9 +96,9 @@ define @vfptosi_nxv1f16_nxv1i64( %va) { ; CHECK-LABEL: vfptosi_nxv1f16_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v25, v8 +; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v25 +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -108,9 +108,9 @@ define @vfptoui_nxv1f16_nxv1i64( %va) { ; CHECK-LABEL: vfptoui_nxv1f16_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v25, v8 +; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v25 +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -120,9 +120,9 @@ define @vfptosi_nxv2f16_nxv2i1( %va) { ; CHECK-LABEL: vfptosi_nxv2f16_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -132,9 +132,9 @@ define @vfptoui_nxv2f16_nxv2i1( %va) { ; CHECK-LABEL: vfptoui_nxv2f16_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -144,8 +144,8 @@ define @vfptosi_nxv2f16_nxv2i8( %va) { ; CHECK-LABEL: vfptosi_nxv2f16_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -155,8 +155,8 @@ define @vfptoui_nxv2f16_nxv2i8( %va) { ; CHECK-LABEL: vfptoui_nxv2f16_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -186,8 +186,8 @@ define @vfptosi_nxv2f16_nxv2i32( %va) { ; CHECK-LABEL: vfptosi_nxv2f16_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -197,8 +197,8 @@ define @vfptoui_nxv2f16_nxv2i32( %va) { ; CHECK-LABEL: vfptoui_nxv2f16_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -208,9 +208,9 @@ define @vfptosi_nxv2f16_nxv2i64( %va) { ; CHECK-LABEL: vfptosi_nxv2f16_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v25, v8 +; CHECK-NEXT: vfwcvt.f.f.v v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v25 +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v10 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -220,9 +220,9 @@ define @vfptoui_nxv2f16_nxv2i64( %va) { ; CHECK-LABEL: vfptoui_nxv2f16_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v25, v8 +; CHECK-NEXT: vfwcvt.f.f.v v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v25 +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v10 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -232,9 +232,9 @@ define @vfptosi_nxv4f16_nxv4i1( %va) { ; CHECK-LABEL: vfptosi_nxv4f16_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -244,9 +244,9 @@ define @vfptoui_nxv4f16_nxv4i1( %va) { ; CHECK-LABEL: vfptoui_nxv4f16_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -256,8 +256,8 @@ define @vfptosi_nxv4f16_nxv4i8( %va) { ; CHECK-LABEL: vfptosi_nxv4f16_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -267,8 +267,8 @@ define @vfptoui_nxv4f16_nxv4i8( %va) { ; CHECK-LABEL: vfptoui_nxv4f16_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -298,8 +298,8 @@ define @vfptosi_nxv4f16_nxv4i32( %va) { ; CHECK-LABEL: vfptosi_nxv4f16_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfwcvt.rtz.x.f.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -309,8 +309,8 @@ define @vfptoui_nxv4f16_nxv4i32( %va) { ; CHECK-LABEL: vfptoui_nxv4f16_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -320,9 +320,9 @@ define @vfptosi_nxv4f16_nxv4i64( %va) { ; CHECK-LABEL: vfptosi_nxv4f16_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v26, v8 +; CHECK-NEXT: vfwcvt.f.f.v v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v26 +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v12 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -332,9 +332,9 @@ define @vfptoui_nxv4f16_nxv4i64( %va) { ; CHECK-LABEL: vfptoui_nxv4f16_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v26, v8 +; CHECK-NEXT: vfwcvt.f.f.v v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v26 +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v12 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -344,9 +344,9 @@ define @vfptosi_nxv8f16_nxv8i1( %va) { ; CHECK-LABEL: vfptosi_nxv8f16_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 +; CHECK-NEXT: vand.vi v8, v10, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -356,9 +356,9 @@ define @vfptoui_nxv8f16_nxv8i1( %va) { ; CHECK-LABEL: vfptoui_nxv8f16_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 +; CHECK-NEXT: vand.vi v8, v10, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -368,8 +368,8 @@ define @vfptosi_nxv8f16_nxv8i8( %va) { ; CHECK-LABEL: vfptosi_nxv8f16_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -379,8 +379,8 @@ define @vfptoui_nxv8f16_nxv8i8( %va) { ; CHECK-LABEL: vfptoui_nxv8f16_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -410,8 +410,8 @@ define @vfptosi_nxv8f16_nxv8i32( %va) { ; CHECK-LABEL: vfptosi_nxv8f16_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.x.f.v v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -421,8 +421,8 @@ define @vfptoui_nxv8f16_nxv8i32( %va) { ; CHECK-LABEL: vfptoui_nxv8f16_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -432,9 +432,9 @@ define @vfptosi_nxv8f16_nxv8i64( %va) { ; CHECK-LABEL: vfptosi_nxv8f16_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v28, v8 +; CHECK-NEXT: vfwcvt.f.f.v v16, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu -; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v28 +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v16 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -444,9 +444,9 @@ define @vfptoui_nxv8f16_nxv8i64( %va) { ; CHECK-LABEL: vfptoui_nxv8f16_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.f.v v28, v8 +; CHECK-NEXT: vfwcvt.f.f.v v16, v8 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v28 +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v16 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -456,9 +456,9 @@ define @vfptosi_nxv16f16_nxv16i1( %va) { ; CHECK-LABEL: vfptosi_nxv16f16_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 -; CHECK-NEXT: vand.vi v26, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 +; CHECK-NEXT: vand.vi v8, v12, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -468,9 +468,9 @@ define @vfptoui_nxv16f16_nxv16i1( %va) { ; CHECK-LABEL: vfptoui_nxv16f16_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 -; CHECK-NEXT: vand.vi v26, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 +; CHECK-NEXT: vand.vi v8, v12, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -480,8 +480,8 @@ define @vfptosi_nxv16f16_nxv16i8( %va) { ; CHECK-LABEL: vfptosi_nxv16f16_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -491,8 +491,8 @@ define @vfptoui_nxv16f16_nxv16i8( %va) { ; CHECK-LABEL: vfptoui_nxv16f16_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -544,9 +544,9 @@ define @vfptosi_nxv32f16_nxv32i1( %va) { ; CHECK-LABEL: vfptosi_nxv32f16_nxv32i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8 -; CHECK-NEXT: vand.vi v28, v28, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 +; CHECK-NEXT: vand.vi v8, v16, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -556,9 +556,9 @@ define @vfptoui_nxv32f16_nxv32i1( %va) { ; CHECK-LABEL: vfptoui_nxv32f16_nxv32i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8 -; CHECK-NEXT: vand.vi v28, v28, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 +; CHECK-NEXT: vand.vi v8, v16, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -568,8 +568,8 @@ define @vfptosi_nxv32f16_nxv32i8( %va) { ; CHECK-LABEL: vfptosi_nxv32f16_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -579,8 +579,8 @@ define @vfptoui_nxv32f16_nxv32i8( %va) { ; CHECK-LABEL: vfptoui_nxv32f16_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -610,9 +610,9 @@ define @vfptosi_nxv1f32_nxv1i1( %va) { ; CHECK-LABEL: vfptosi_nxv1f32_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -622,9 +622,9 @@ define @vfptoui_nxv1f32_nxv1i1( %va) { ; CHECK-LABEL: vfptoui_nxv1f32_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -634,9 +634,9 @@ define @vfptosi_nxv1f32_nxv1i8( %va) { ; CHECK-LABEL: vfptosi_nxv1f32_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -646,9 +646,9 @@ define @vfptoui_nxv1f32_nxv1i8( %va) { ; CHECK-LABEL: vfptoui_nxv1f32_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -658,8 +658,8 @@ define @vfptosi_nxv1f32_nxv1i16( %va) { ; CHECK-LABEL: vfptosi_nxv1f32_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -669,8 +669,8 @@ define @vfptoui_nxv1f32_nxv1i16( %va) { ; CHECK-LABEL: vfptoui_nxv1f32_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -700,8 +700,8 @@ define @vfptosi_nxv1f32_nxv1i64( %va) { ; CHECK-LABEL: vfptosi_nxv1f32_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -711,8 +711,8 @@ define @vfptoui_nxv1f32_nxv1i64( %va) { ; CHECK-LABEL: vfptoui_nxv1f32_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -722,9 +722,9 @@ define @vfptosi_nxv2f32_nxv2i1( %va) { ; CHECK-LABEL: vfptosi_nxv2f32_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -734,9 +734,9 @@ define @vfptoui_nxv2f32_nxv2i1( %va) { ; CHECK-LABEL: vfptoui_nxv2f32_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -746,9 +746,9 @@ define @vfptosi_nxv2f32_nxv2i8( %va) { ; CHECK-LABEL: vfptosi_nxv2f32_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -758,9 +758,9 @@ define @vfptoui_nxv2f32_nxv2i8( %va) { ; CHECK-LABEL: vfptoui_nxv2f32_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -770,8 +770,8 @@ define @vfptosi_nxv2f32_nxv2i16( %va) { ; CHECK-LABEL: vfptosi_nxv2f32_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -781,8 +781,8 @@ define @vfptoui_nxv2f32_nxv2i16( %va) { ; CHECK-LABEL: vfptoui_nxv2f32_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -812,8 +812,8 @@ define @vfptosi_nxv2f32_nxv2i64( %va) { ; CHECK-LABEL: vfptosi_nxv2f32_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.rtz.x.f.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -823,8 +823,8 @@ define @vfptoui_nxv2f32_nxv2i64( %va) { ; CHECK-LABEL: vfptoui_nxv2f32_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -834,9 +834,9 @@ define @vfptosi_nxv4f32_nxv4i1( %va) { ; CHECK-LABEL: vfptosi_nxv4f32_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 +; CHECK-NEXT: vand.vi v8, v10, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -846,9 +846,9 @@ define @vfptoui_nxv4f32_nxv4i1( %va) { ; CHECK-LABEL: vfptoui_nxv4f32_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 +; CHECK-NEXT: vand.vi v8, v10, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -858,9 +858,9 @@ define @vfptosi_nxv4f32_nxv4i8( %va) { ; CHECK-LABEL: vfptosi_nxv4f32_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -870,9 +870,9 @@ define @vfptoui_nxv4f32_nxv4i8( %va) { ; CHECK-LABEL: vfptoui_nxv4f32_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -882,8 +882,8 @@ define @vfptosi_nxv4f32_nxv4i16( %va) { ; CHECK-LABEL: vfptosi_nxv4f32_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -893,8 +893,8 @@ define @vfptoui_nxv4f32_nxv4i16( %va) { ; CHECK-LABEL: vfptoui_nxv4f32_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -924,8 +924,8 @@ define @vfptosi_nxv4f32_nxv4i64( %va) { ; CHECK-LABEL: vfptosi_nxv4f32_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.x.f.v v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -935,8 +935,8 @@ define @vfptoui_nxv4f32_nxv4i64( %va) { ; CHECK-LABEL: vfptoui_nxv4f32_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfwcvt.rtz.xu.f.v v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -946,9 +946,9 @@ define @vfptosi_nxv8f32_nxv8i1( %va) { ; CHECK-LABEL: vfptosi_nxv8f32_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 -; CHECK-NEXT: vand.vi v26, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 +; CHECK-NEXT: vand.vi v8, v12, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -958,9 +958,9 @@ define @vfptoui_nxv8f32_nxv8i1( %va) { ; CHECK-LABEL: vfptoui_nxv8f32_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 -; CHECK-NEXT: vand.vi v26, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 +; CHECK-NEXT: vand.vi v8, v12, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -970,9 +970,9 @@ define @vfptosi_nxv8f32_nxv8i8( %va) { ; CHECK-LABEL: vfptosi_nxv8f32_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -982,9 +982,9 @@ define @vfptoui_nxv8f32_nxv8i8( %va) { ; CHECK-LABEL: vfptoui_nxv8f32_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -994,8 +994,8 @@ define @vfptosi_nxv8f32_nxv8i16( %va) { ; CHECK-LABEL: vfptosi_nxv8f32_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1005,8 +1005,8 @@ define @vfptoui_nxv8f32_nxv8i16( %va) { ; CHECK-LABEL: vfptoui_nxv8f32_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1058,9 +1058,9 @@ define @vfptosi_nxv16f32_nxv16i1( %va) { ; CHECK-LABEL: vfptosi_nxv16f32_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8 -; CHECK-NEXT: vand.vi v28, v28, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 +; CHECK-NEXT: vand.vi v8, v16, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1070,9 +1070,9 @@ define @vfptoui_nxv16f32_nxv16i1( %va) { ; CHECK-LABEL: vfptoui_nxv16f32_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8 -; CHECK-NEXT: vand.vi v28, v28, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 +; CHECK-NEXT: vand.vi v8, v16, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1082,9 +1082,9 @@ define @vfptosi_nxv16f32_nxv16i8( %va) { ; CHECK-LABEL: vfptosi_nxv16f32_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v28, 0 +; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1094,9 +1094,9 @@ define @vfptoui_nxv16f32_nxv16i8( %va) { ; CHECK-LABEL: vfptoui_nxv16f32_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v28, 0 +; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1106,8 +1106,8 @@ define @vfptosi_nxv16f32_nxv16i16( %va) ; CHECK-LABEL: vfptosi_nxv16f32_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1117,8 +1117,8 @@ define @vfptoui_nxv16f32_nxv16i16( %va) ; CHECK-LABEL: vfptoui_nxv16f32_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1148,9 +1148,9 @@ define @vfptosi_nxv1f64_nxv1i1( %va) { ; CHECK-LABEL: vfptosi_nxv1f64_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1160,9 +1160,9 @@ define @vfptoui_nxv1f64_nxv1i1( %va) { ; CHECK-LABEL: vfptoui_nxv1f64_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vand.vi v8, v9, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1172,11 +1172,11 @@ define @vfptosi_nxv1f64_nxv1i8( %va) { ; CHECK-LABEL: vfptosi_nxv1f64_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1186,11 +1186,11 @@ define @vfptoui_nxv1f64_nxv1i8( %va) { ; CHECK-LABEL: vfptoui_nxv1f64_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1200,9 +1200,9 @@ define @vfptosi_nxv1f64_nxv1i16( %va) { ; CHECK-LABEL: vfptosi_nxv1f64_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1212,9 +1212,9 @@ define @vfptoui_nxv1f64_nxv1i16( %va) { ; CHECK-LABEL: vfptoui_nxv1f64_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1224,8 +1224,8 @@ define @vfptosi_nxv1f64_nxv1i32( %va) { ; CHECK-LABEL: vfptosi_nxv1f64_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1235,8 +1235,8 @@ define @vfptoui_nxv1f64_nxv1i32( %va) { ; CHECK-LABEL: vfptoui_nxv1f64_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1266,9 +1266,9 @@ define @vfptosi_nxv2f64_nxv2i1( %va) { ; CHECK-LABEL: vfptosi_nxv2f64_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 +; CHECK-NEXT: vand.vi v8, v10, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1278,9 +1278,9 @@ define @vfptoui_nxv2f64_nxv2i1( %va) { ; CHECK-LABEL: vfptoui_nxv2f64_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vand.vi v25, v25, 1 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 +; CHECK-NEXT: vand.vi v8, v10, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1290,11 +1290,11 @@ define @vfptosi_nxv2f64_nxv2i8( %va) { ; CHECK-LABEL: vfptosi_nxv2f64_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1304,11 +1304,11 @@ define @vfptoui_nxv2f64_nxv2i8( %va) { ; CHECK-LABEL: vfptoui_nxv2f64_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1318,9 +1318,9 @@ define @vfptosi_nxv2f64_nxv2i16( %va) { ; CHECK-LABEL: vfptosi_nxv2f64_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1330,9 +1330,9 @@ define @vfptoui_nxv2f64_nxv2i16( %va) { ; CHECK-LABEL: vfptoui_nxv2f64_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1342,8 +1342,8 @@ define @vfptosi_nxv2f64_nxv2i32( %va) { ; CHECK-LABEL: vfptosi_nxv2f64_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1353,8 +1353,8 @@ define @vfptoui_nxv2f64_nxv2i32( %va) { ; CHECK-LABEL: vfptoui_nxv2f64_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1384,9 +1384,9 @@ define @vfptosi_nxv4f64_nxv4i1( %va) { ; CHECK-LABEL: vfptosi_nxv4f64_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 -; CHECK-NEXT: vand.vi v26, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 +; CHECK-NEXT: vand.vi v8, v12, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1396,9 +1396,9 @@ define @vfptoui_nxv4f64_nxv4i1( %va) { ; CHECK-LABEL: vfptoui_nxv4f64_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 -; CHECK-NEXT: vand.vi v26, v26, 1 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 +; CHECK-NEXT: vand.vi v8, v12, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1408,11 +1408,11 @@ define @vfptosi_nxv4f64_nxv4i8( %va) { ; CHECK-LABEL: vfptosi_nxv4f64_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1422,11 +1422,11 @@ define @vfptoui_nxv4f64_nxv4i8( %va) { ; CHECK-LABEL: vfptoui_nxv4f64_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1436,9 +1436,9 @@ define @vfptosi_nxv4f64_nxv4i16( %va) { ; CHECK-LABEL: vfptosi_nxv4f64_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1448,9 +1448,9 @@ define @vfptoui_nxv4f64_nxv4i16( %va) { ; CHECK-LABEL: vfptoui_nxv4f64_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1460,8 +1460,8 @@ define @vfptosi_nxv4f64_nxv4i32( %va) { ; CHECK-LABEL: vfptosi_nxv4f64_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1471,8 +1471,8 @@ define @vfptoui_nxv4f64_nxv4i32( %va) { ; CHECK-LABEL: vfptoui_nxv4f64_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1502,9 +1502,9 @@ define @vfptosi_nxv8f64_nxv8i1( %va) { ; CHECK-LABEL: vfptosi_nxv8f64_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8 -; CHECK-NEXT: vand.vi v28, v28, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 +; CHECK-NEXT: vand.vi v8, v16, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1514,9 +1514,9 @@ define @vfptoui_nxv8f64_nxv8i1( %va) { ; CHECK-LABEL: vfptoui_nxv8f64_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8 -; CHECK-NEXT: vand.vi v28, v28, 1 -; CHECK-NEXT: vmsne.vi v0, v28, 0 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 +; CHECK-NEXT: vand.vi v8, v16, 1 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1526,11 +1526,11 @@ define @vfptosi_nxv8f64_nxv8i8( %va) { ; CHECK-LABEL: vfptosi_nxv8f64_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v28, 0 +; CHECK-NEXT: vnsrl.wi v10, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1540,11 +1540,11 @@ define @vfptoui_nxv8f64_nxv8i8( %va) { ; CHECK-LABEL: vfptoui_nxv8f64_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v28, 0 +; CHECK-NEXT: vnsrl.wi v10, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1554,9 +1554,9 @@ define @vfptosi_nxv8f64_nxv8i16( %va) { ; CHECK-LABEL: vfptosi_nxv8f64_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8 +; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v28, 0 +; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1566,9 +1566,9 @@ define @vfptoui_nxv8f64_nxv8i16( %va) { ; CHECK-LABEL: vfptoui_nxv8f64_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v28, 0 +; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1578,8 +1578,8 @@ define @vfptosi_nxv8f64_nxv8i32( %va) { ; CHECK-LABEL: vfptosi_nxv8f64_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1589,8 +1589,8 @@ define @vfptoui_nxv8f64_nxv8i32( %va) { ; CHECK-LABEL: vfptoui_nxv8f64_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll index 0ac7d519e33bc09144635f96c83f4128a3a7ac06..ccbb7c3d46cd51245d5f66e9dfbd89930a3beed0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll @@ -9,15 +9,15 @@ define @vfptrunc_nxv1f32_nxv1f16( %va) { ; RV32-LABEL: vfptrunc_nxv1f32_nxv1f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; RV32-NEXT: vfncvt.f.f.w v25, v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vfncvt.f.f.w v9, v8 +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vfptrunc_nxv1f32_nxv1f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; RV64-NEXT: vfncvt.f.f.w v25, v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vfncvt.f.f.w v9, v8 +; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %evec = fptrunc %va to ret %evec @@ -28,15 +28,15 @@ define @vfptrunc_nxv2f32_nxv2f16( %va) { ; RV32-LABEL: vfptrunc_nxv2f32_nxv2f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; RV32-NEXT: vfncvt.f.f.w v25, v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vfncvt.f.f.w v9, v8 +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vfptrunc_nxv2f32_nxv2f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; RV64-NEXT: vfncvt.f.f.w v25, v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vfncvt.f.f.w v9, v8 +; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %evec = fptrunc %va to ret %evec @@ -47,15 +47,15 @@ define @vfptrunc_nxv4f32_nxv4f16( %va) { ; RV32-LABEL: vfptrunc_nxv4f32_nxv4f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; RV32-NEXT: vfncvt.f.f.w v25, v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vfncvt.f.f.w v10, v8 +; RV32-NEXT: vmv1r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vfptrunc_nxv4f32_nxv4f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; RV64-NEXT: vfncvt.f.f.w v25, v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vfncvt.f.f.w v10, v8 +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %evec = fptrunc %va to ret %evec @@ -66,15 +66,15 @@ define @vfptrunc_nxv8f32_nxv8f16( %va) { ; RV32-LABEL: vfptrunc_nxv8f32_nxv8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; RV32-NEXT: vfncvt.f.f.w v26, v8 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vfncvt.f.f.w v12, v8 +; RV32-NEXT: vmv2r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vfptrunc_nxv8f32_nxv8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; RV64-NEXT: vfncvt.f.f.w v26, v8 -; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: vfncvt.f.f.w v12, v8 +; RV64-NEXT: vmv2r.v v8, v12 ; RV64-NEXT: ret %evec = fptrunc %va to ret %evec @@ -85,15 +85,15 @@ define @vfptrunc_nxv16f32_nxv16f16( %v ; RV32-LABEL: vfptrunc_nxv16f32_nxv16f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; RV32-NEXT: vfncvt.f.f.w v28, v8 -; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: vfncvt.f.f.w v16, v8 +; RV32-NEXT: vmv4r.v v8, v16 ; RV32-NEXT: ret ; ; RV64-LABEL: vfptrunc_nxv16f32_nxv16f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; RV64-NEXT: vfncvt.f.f.w v28, v8 -; RV64-NEXT: vmv4r.v v8, v28 +; RV64-NEXT: vfncvt.f.f.w v16, v8 +; RV64-NEXT: vmv4r.v v8, v16 ; RV64-NEXT: ret %evec = fptrunc %va to ret %evec @@ -104,17 +104,17 @@ define @vfptrunc_nxv1f64_nxv1f16( %va) ; RV32-LABEL: vfptrunc_nxv1f64_nxv1f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; RV32-NEXT: vfncvt.rod.f.f.w v25, v8 +; RV32-NEXT: vfncvt.rod.f.f.w v9, v8 ; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; RV32-NEXT: vfncvt.f.f.w v8, v25 +; RV32-NEXT: vfncvt.f.f.w v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vfptrunc_nxv1f64_nxv1f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; RV64-NEXT: vfncvt.rod.f.f.w v25, v8 +; RV64-NEXT: vfncvt.rod.f.f.w v9, v8 ; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; RV64-NEXT: vfncvt.f.f.w v8, v25 +; RV64-NEXT: vfncvt.f.f.w v8, v9 ; RV64-NEXT: ret %evec = fptrunc %va to ret %evec @@ -125,15 +125,15 @@ define @vfptrunc_nxv1f64_nxv1f32( %va) ; RV32-LABEL: vfptrunc_nxv1f64_nxv1f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; RV32-NEXT: vfncvt.f.f.w v25, v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vfncvt.f.f.w v9, v8 +; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vfptrunc_nxv1f64_nxv1f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; RV64-NEXT: vfncvt.f.f.w v25, v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vfncvt.f.f.w v9, v8 +; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: ret %evec = fptrunc %va to ret %evec @@ -144,17 +144,17 @@ define @vfptrunc_nxv2f64_nxv2f16( %va) ; RV32-LABEL: vfptrunc_nxv2f64_nxv2f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV32-NEXT: vfncvt.rod.f.f.w v25, v8 +; RV32-NEXT: vfncvt.rod.f.f.w v10, v8 ; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; RV32-NEXT: vfncvt.f.f.w v8, v25 +; RV32-NEXT: vfncvt.f.f.w v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vfptrunc_nxv2f64_nxv2f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV64-NEXT: vfncvt.rod.f.f.w v25, v8 +; RV64-NEXT: vfncvt.rod.f.f.w v10, v8 ; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; RV64-NEXT: vfncvt.f.f.w v8, v25 +; RV64-NEXT: vfncvt.f.f.w v8, v10 ; RV64-NEXT: ret %evec = fptrunc %va to ret %evec @@ -165,15 +165,15 @@ define @vfptrunc_nxv2f64_nxv2f32( %va) ; RV32-LABEL: vfptrunc_nxv2f64_nxv2f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV32-NEXT: vfncvt.f.f.w v25, v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vfncvt.f.f.w v10, v8 +; RV32-NEXT: vmv1r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vfptrunc_nxv2f64_nxv2f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV64-NEXT: vfncvt.f.f.w v25, v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vfncvt.f.f.w v10, v8 +; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret %evec = fptrunc %va to ret %evec @@ -184,17 +184,17 @@ define @vfptrunc_nxv4f64_nxv4f16( %va) ; RV32-LABEL: vfptrunc_nxv4f64_nxv4f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; RV32-NEXT: vfncvt.rod.f.f.w v26, v8 +; RV32-NEXT: vfncvt.rod.f.f.w v12, v8 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV32-NEXT: vfncvt.f.f.w v8, v26 +; RV32-NEXT: vfncvt.f.f.w v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vfptrunc_nxv4f64_nxv4f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; RV64-NEXT: vfncvt.rod.f.f.w v26, v8 +; RV64-NEXT: vfncvt.rod.f.f.w v12, v8 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; RV64-NEXT: vfncvt.f.f.w v8, v26 +; RV64-NEXT: vfncvt.f.f.w v8, v12 ; RV64-NEXT: ret %evec = fptrunc %va to ret %evec @@ -205,15 +205,15 @@ define @vfptrunc_nxv4f64_nxv4f32( %va) ; RV32-LABEL: vfptrunc_nxv4f64_nxv4f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; RV32-NEXT: vfncvt.f.f.w v26, v8 -; RV32-NEXT: vmv2r.v v8, v26 +; RV32-NEXT: vfncvt.f.f.w v12, v8 +; RV32-NEXT: vmv2r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vfptrunc_nxv4f64_nxv4f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; RV64-NEXT: vfncvt.f.f.w v26, v8 -; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: vfncvt.f.f.w v12, v8 +; RV64-NEXT: vmv2r.v v8, v12 ; RV64-NEXT: ret %evec = fptrunc %va to ret %evec @@ -224,17 +224,17 @@ define @vfptrunc_nxv8f64_nxv8f16( %va) ; RV32-LABEL: vfptrunc_nxv8f64_nxv8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; RV32-NEXT: vfncvt.rod.f.f.w v28, v8 +; RV32-NEXT: vfncvt.rod.f.f.w v16, v8 ; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; RV32-NEXT: vfncvt.f.f.w v8, v28 +; RV32-NEXT: vfncvt.f.f.w v8, v16 ; RV32-NEXT: ret ; ; RV64-LABEL: vfptrunc_nxv8f64_nxv8f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; RV64-NEXT: vfncvt.rod.f.f.w v28, v8 +; RV64-NEXT: vfncvt.rod.f.f.w v16, v8 ; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; RV64-NEXT: vfncvt.f.f.w v8, v28 +; RV64-NEXT: vfncvt.f.f.w v8, v16 ; RV64-NEXT: ret %evec = fptrunc %va to ret %evec @@ -245,15 +245,15 @@ define @vfptrunc_nxv8f64_nxv8f32( %va) ; RV32-LABEL: vfptrunc_nxv8f64_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; RV32-NEXT: vfncvt.f.f.w v28, v8 -; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: vfncvt.f.f.w v16, v8 +; RV32-NEXT: vmv4r.v v8, v16 ; RV32-NEXT: ret ; ; RV64-LABEL: vfptrunc_nxv8f64_nxv8f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; RV64-NEXT: vfncvt.f.f.w v28, v8 -; RV64-NEXT: vmv4r.v v8, v28 +; RV64-NEXT: vfncvt.f.f.w v16, v8 +; RV64-NEXT: vmv4r.v v8, v16 ; RV64-NEXT: ret %evec = fptrunc %va to ret %evec diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll index 8aa3875768c8b6b6d0d63dd42ff70deb26177506..22d0a1adeb75012b57d34f907174f708399d3f30 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll @@ -10,9 +10,9 @@ define @vfrdiv_vf_nxv1f16( %va, half %b, ; CHECK-LABEL: vfrdiv_vf_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -24,9 +24,9 @@ define @vfrdiv_vf_nxv1f16_unmasked( %va, ; CHECK-LABEL: vfrdiv_vf_nxv1f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8 +; CHECK-NEXT: vfdiv.vv v8, v9, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -42,9 +42,9 @@ define @vfrdiv_vf_nxv2f16( %va, half %b, ; CHECK-LABEL: vfrdiv_vf_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -56,9 +56,9 @@ define @vfrdiv_vf_nxv2f16_unmasked( %va, ; CHECK-LABEL: vfrdiv_vf_nxv2f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8 +; CHECK-NEXT: vfdiv.vv v8, v9, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -74,9 +74,9 @@ define @vfrdiv_vf_nxv4f16( %va, half %b, ; CHECK-LABEL: vfrdiv_vf_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -88,9 +88,9 @@ define @vfrdiv_vf_nxv4f16_unmasked( %va, ; CHECK-LABEL: vfrdiv_vf_nxv4f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8 +; CHECK-NEXT: vfdiv.vv v8, v9, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -106,9 +106,9 @@ define @vfrdiv_vf_nxv8f16( %va, half %b, ; CHECK-LABEL: vfrdiv_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v26, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -120,9 +120,9 @@ define @vfrdiv_vf_nxv8f16_unmasked( %va, ; CHECK-LABEL: vfrdiv_vf_nxv8f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v26, v8 +; CHECK-NEXT: vfdiv.vv v8, v10, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -138,9 +138,9 @@ define @vfrdiv_vf_nxv16f16( %va, half % ; CHECK-LABEL: vfrdiv_vf_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v28, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -152,9 +152,9 @@ define @vfrdiv_vf_nxv16f16_unmasked( %v ; CHECK-LABEL: vfrdiv_vf_nxv16f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v28, v8 +; CHECK-NEXT: vfdiv.vv v8, v12, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -202,9 +202,9 @@ define @vfrdiv_vf_nxv1f32( %va, float % ; CHECK-LABEL: vfrdiv_vf_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -216,9 +216,9 @@ define @vfrdiv_vf_nxv1f32_unmasked( %va ; CHECK-LABEL: vfrdiv_vf_nxv1f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8 +; CHECK-NEXT: vfdiv.vv v8, v9, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -234,9 +234,9 @@ define @vfrdiv_vf_nxv2f32( %va, float % ; CHECK-LABEL: vfrdiv_vf_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -248,9 +248,9 @@ define @vfrdiv_vf_nxv2f32_unmasked( %va ; CHECK-LABEL: vfrdiv_vf_nxv2f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8 +; CHECK-NEXT: vfdiv.vv v8, v9, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -266,9 +266,9 @@ define @vfrdiv_vf_nxv4f32( %va, float % ; CHECK-LABEL: vfrdiv_vf_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v26, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -280,9 +280,9 @@ define @vfrdiv_vf_nxv4f32_unmasked( %va ; CHECK-LABEL: vfrdiv_vf_nxv4f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v26, v8 +; CHECK-NEXT: vfdiv.vv v8, v10, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -298,9 +298,9 @@ define @vfrdiv_vf_nxv8f32( %va, float % ; CHECK-LABEL: vfrdiv_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v28, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -312,9 +312,9 @@ define @vfrdiv_vf_nxv8f32_unmasked( %va ; CHECK-LABEL: vfrdiv_vf_nxv8f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v28, v8 +; CHECK-NEXT: vfdiv.vv v8, v12, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -362,9 +362,9 @@ define @vfrdiv_vf_nxv1f64( %va, doubl ; CHECK-LABEL: vfrdiv_vf_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -376,9 +376,9 @@ define @vfrdiv_vf_nxv1f64_unmasked( % ; CHECK-LABEL: vfrdiv_vf_nxv1f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v25, v8 +; CHECK-NEXT: vfdiv.vv v8, v9, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -394,9 +394,9 @@ define @vfrdiv_vf_nxv2f64( %va, doubl ; CHECK-LABEL: vfrdiv_vf_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v26, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -408,9 +408,9 @@ define @vfrdiv_vf_nxv2f64_unmasked( % ; CHECK-LABEL: vfrdiv_vf_nxv2f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v26, v8 +; CHECK-NEXT: vfdiv.vv v8, v10, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -426,9 +426,9 @@ define @vfrdiv_vf_nxv4f64( %va, doubl ; CHECK-LABEL: vfrdiv_vf_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v28, v8, v0.t +; CHECK-NEXT: vfdiv.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -440,9 +440,9 @@ define @vfrdiv_vf_nxv4f64_unmasked( % ; CHECK-LABEL: vfrdiv_vf_nxv4f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfdiv.vv v8, v28, v8 +; CHECK-NEXT: vfdiv.vv v8, v12, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll index 13f5cd776633465263cbb5a1da7750be59756835..fdffa513d0e63b8b364bd466b7e5c38403a1e0e0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll @@ -10,9 +10,9 @@ define @vfrsub_vf_nxv1f16( %va, half %b, ; CHECK-LABEL: vfrsub_vf_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -24,9 +24,9 @@ define @vfrsub_vf_nxv1f16_unmasked( %va, ; CHECK-LABEL: vfrsub_vf_nxv1f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8 +; CHECK-NEXT: vfsub.vv v8, v9, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -42,9 +42,9 @@ define @vfrsub_vf_nxv2f16( %va, half %b, ; CHECK-LABEL: vfrsub_vf_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -56,9 +56,9 @@ define @vfrsub_vf_nxv2f16_unmasked( %va, ; CHECK-LABEL: vfrsub_vf_nxv2f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8 +; CHECK-NEXT: vfsub.vv v8, v9, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -74,9 +74,9 @@ define @vfrsub_vf_nxv4f16( %va, half %b, ; CHECK-LABEL: vfrsub_vf_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -88,9 +88,9 @@ define @vfrsub_vf_nxv4f16_unmasked( %va, ; CHECK-LABEL: vfrsub_vf_nxv4f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8 +; CHECK-NEXT: vfsub.vv v8, v9, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -106,9 +106,9 @@ define @vfrsub_vf_nxv8f16( %va, half %b, ; CHECK-LABEL: vfrsub_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v26, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -120,9 +120,9 @@ define @vfrsub_vf_nxv8f16_unmasked( %va, ; CHECK-LABEL: vfrsub_vf_nxv8f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v26, v8 +; CHECK-NEXT: vfsub.vv v8, v10, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -138,9 +138,9 @@ define @vfrsub_vf_nxv16f16( %va, half % ; CHECK-LABEL: vfrsub_vf_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v28, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -152,9 +152,9 @@ define @vfrsub_vf_nxv16f16_unmasked( %v ; CHECK-LABEL: vfrsub_vf_nxv16f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v28, v8 +; CHECK-NEXT: vfsub.vv v8, v12, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -202,9 +202,9 @@ define @vfrsub_vf_nxv1f32( %va, float % ; CHECK-LABEL: vfrsub_vf_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -216,9 +216,9 @@ define @vfrsub_vf_nxv1f32_unmasked( %va ; CHECK-LABEL: vfrsub_vf_nxv1f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8 +; CHECK-NEXT: vfsub.vv v8, v9, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -234,9 +234,9 @@ define @vfrsub_vf_nxv2f32( %va, float % ; CHECK-LABEL: vfrsub_vf_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -248,9 +248,9 @@ define @vfrsub_vf_nxv2f32_unmasked( %va ; CHECK-LABEL: vfrsub_vf_nxv2f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8 +; CHECK-NEXT: vfsub.vv v8, v9, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -266,9 +266,9 @@ define @vfrsub_vf_nxv4f32( %va, float % ; CHECK-LABEL: vfrsub_vf_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v26, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -280,9 +280,9 @@ define @vfrsub_vf_nxv4f32_unmasked( %va ; CHECK-LABEL: vfrsub_vf_nxv4f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v26, v8 +; CHECK-NEXT: vfsub.vv v8, v10, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -298,9 +298,9 @@ define @vfrsub_vf_nxv8f32( %va, float % ; CHECK-LABEL: vfrsub_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v28, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -312,9 +312,9 @@ define @vfrsub_vf_nxv8f32_unmasked( %va ; CHECK-LABEL: vfrsub_vf_nxv8f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v28, v8 +; CHECK-NEXT: vfsub.vv v8, v12, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -362,9 +362,9 @@ define @vfrsub_vf_nxv1f64( %va, doubl ; CHECK-LABEL: vfrsub_vf_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -376,9 +376,9 @@ define @vfrsub_vf_nxv1f64_unmasked( % ; CHECK-LABEL: vfrsub_vf_nxv1f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v25, v8 +; CHECK-NEXT: vfsub.vv v8, v9, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -394,9 +394,9 @@ define @vfrsub_vf_nxv2f64( %va, doubl ; CHECK-LABEL: vfrsub_vf_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v26, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -408,9 +408,9 @@ define @vfrsub_vf_nxv2f64_unmasked( % ; CHECK-LABEL: vfrsub_vf_nxv2f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v26, v8 +; CHECK-NEXT: vfsub.vv v8, v10, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -426,9 +426,9 @@ define @vfrsub_vf_nxv4f64( %va, doubl ; CHECK-LABEL: vfrsub_vf_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v28, v8, v0.t +; CHECK-NEXT: vfsub.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -440,9 +440,9 @@ define @vfrsub_vf_nxv4f64_unmasked( % ; CHECK-LABEL: vfrsub_vf_nxv4f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v28, v8 +; CHECK-NEXT: vfsub.vv v8, v12, v8 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll index f34ad4c0298aca72869ab1cd8c305472a617eb65..9973aafeed5af3731b9b2693caebf5fba7b5e6ef 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll @@ -11,8 +11,8 @@ define @intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16( @llvm.riscv.vfslide1up.nxv1f16.f16( @@ -59,8 +59,8 @@ define @intrinsic_vfslide1up_vf_nxv2f16_nxv2f16_f16( @llvm.riscv.vfslide1up.nxv2f16.f16( @@ -107,8 +107,8 @@ define @intrinsic_vfslide1up_vf_nxv4f16_nxv4f16_f16( @llvm.riscv.vfslide1up.nxv4f16.f16( @@ -155,8 +155,8 @@ define @intrinsic_vfslide1up_vf_nxv8f16_nxv8f16_f16( @llvm.riscv.vfslide1up.nxv8f16.f16( @@ -203,8 +203,8 @@ define @intrinsic_vfslide1up_vf_nxv16f16_nxv16f16_f16( @llvm.riscv.vfslide1up.nxv16f16.f16( @@ -299,8 +299,8 @@ define @intrinsic_vfslide1up_vf_nxv1f32_nxv1f32_f32( @llvm.riscv.vfslide1up.nxv1f32.f32( @@ -347,8 +347,8 @@ define @intrinsic_vfslide1up_vf_nxv2f32_nxv2f32_f32( @llvm.riscv.vfslide1up.nxv2f32.f32( @@ -395,8 +395,8 @@ define @intrinsic_vfslide1up_vf_nxv4f32_nxv4f32_f32( @llvm.riscv.vfslide1up.nxv4f32.f32( @@ -443,8 +443,8 @@ define @intrinsic_vfslide1up_vf_nxv8f32_nxv8f32_f32( @llvm.riscv.vfslide1up.nxv8f32.f32( @@ -542,8 +542,8 @@ define @intrinsic_vfslide1up_vf_nxv1f64_nxv1f64_f64( @intrinsic_vfslide1up_vf_nxv2f64_nxv2f64_f64( @intrinsic_vfslide1up_vf_nxv4f64_nxv4f64_f64( @intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16( @llvm.riscv.vfslide1up.nxv1f16.f16( @@ -59,8 +59,8 @@ define @intrinsic_vfslide1up_vf_nxv2f16_nxv2f16_f16( @llvm.riscv.vfslide1up.nxv2f16.f16( @@ -107,8 +107,8 @@ define @intrinsic_vfslide1up_vf_nxv4f16_nxv4f16_f16( @llvm.riscv.vfslide1up.nxv4f16.f16( @@ -155,8 +155,8 @@ define @intrinsic_vfslide1up_vf_nxv8f16_nxv8f16_f16( @llvm.riscv.vfslide1up.nxv8f16.f16( @@ -203,8 +203,8 @@ define @intrinsic_vfslide1up_vf_nxv16f16_nxv16f16_f16( @llvm.riscv.vfslide1up.nxv16f16.f16( @@ -299,8 +299,8 @@ define @intrinsic_vfslide1up_vf_nxv1f32_nxv1f32_f32( @llvm.riscv.vfslide1up.nxv1f32.f32( @@ -347,8 +347,8 @@ define @intrinsic_vfslide1up_vf_nxv2f32_nxv2f32_f32( @llvm.riscv.vfslide1up.nxv2f32.f32( @@ -395,8 +395,8 @@ define @intrinsic_vfslide1up_vf_nxv4f32_nxv4f32_f32( @llvm.riscv.vfslide1up.nxv4f32.f32( @@ -443,8 +443,8 @@ define @intrinsic_vfslide1up_vf_nxv8f32_nxv8f32_f32( @llvm.riscv.vfslide1up.nxv8f32.f32( @@ -539,8 +539,8 @@ define @intrinsic_vfslide1up_vf_nxv1f64_nxv1f64_f64( @llvm.riscv.vfslide1up.nxv1f64.f64( @@ -587,8 +587,8 @@ define @intrinsic_vfslide1up_vf_nxv2f64_nxv2f64_f64( @llvm.riscv.vfslide1up.nxv2f64.f64( @@ -635,8 +635,8 @@ define @intrinsic_vfslide1up_vf_nxv4f64_nxv4f64_f64( @llvm.riscv.vfslide1up.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll index 131ae96ad708dde20b628802dc68bc2ee27f0603..a5bff96d636ef8592bd583293c02590d764758b9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll @@ -32,9 +32,9 @@ define @vfsub_vf_nxv1f16( %va, half %b, < ; CHECK-LABEL: vfsub_vf_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -46,9 +46,9 @@ define @vfsub_vf_nxv1f16_unmasked( %va, h ; CHECK-LABEL: vfsub_vf_nxv1f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -86,9 +86,9 @@ define @vfsub_vf_nxv2f16( %va, half %b, < ; CHECK-LABEL: vfsub_vf_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -100,9 +100,9 @@ define @vfsub_vf_nxv2f16_unmasked( %va, h ; CHECK-LABEL: vfsub_vf_nxv2f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -140,9 +140,9 @@ define @vfsub_vf_nxv4f16( %va, half %b, < ; CHECK-LABEL: vfsub_vf_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -154,9 +154,9 @@ define @vfsub_vf_nxv4f16_unmasked( %va, h ; CHECK-LABEL: vfsub_vf_nxv4f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -194,9 +194,9 @@ define @vfsub_vf_nxv8f16( %va, half %b, < ; CHECK-LABEL: vfsub_vf_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -208,9 +208,9 @@ define @vfsub_vf_nxv8f16_unmasked( %va, h ; CHECK-LABEL: vfsub_vf_nxv8f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v26 +; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -248,9 +248,9 @@ define @vfsub_vf_nxv16f16( %va, half %b ; CHECK-LABEL: vfsub_vf_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -262,9 +262,9 @@ define @vfsub_vf_nxv16f16_unmasked( %va ; CHECK-LABEL: vfsub_vf_nxv16f16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v28 +; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: ret %elt.head = insertelement undef, half %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -356,9 +356,9 @@ define @vfsub_vf_nxv1f32( %va, float %b ; CHECK-LABEL: vfsub_vf_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -370,9 +370,9 @@ define @vfsub_vf_nxv1f32_unmasked( %va, ; CHECK-LABEL: vfsub_vf_nxv1f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -410,9 +410,9 @@ define @vfsub_vf_nxv2f32( %va, float %b ; CHECK-LABEL: vfsub_vf_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -424,9 +424,9 @@ define @vfsub_vf_nxv2f32_unmasked( %va, ; CHECK-LABEL: vfsub_vf_nxv2f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -464,9 +464,9 @@ define @vfsub_vf_nxv4f32( %va, float %b ; CHECK-LABEL: vfsub_vf_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -478,9 +478,9 @@ define @vfsub_vf_nxv4f32_unmasked( %va, ; CHECK-LABEL: vfsub_vf_nxv4f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v26 +; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -518,9 +518,9 @@ define @vfsub_vf_nxv8f32( %va, float %b ; CHECK-LABEL: vfsub_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -532,9 +532,9 @@ define @vfsub_vf_nxv8f32_unmasked( %va, ; CHECK-LABEL: vfsub_vf_nxv8f32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v28 +; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: ret %elt.head = insertelement undef, float %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -626,9 +626,9 @@ define @vfsub_vf_nxv1f64( %va, double ; CHECK-LABEL: vfsub_vf_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -640,9 +640,9 @@ define @vfsub_vf_nxv1f64_unmasked( %v ; CHECK-LABEL: vfsub_vf_nxv1f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v25 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -680,9 +680,9 @@ define @vfsub_vf_nxv2f64( %va, double ; CHECK-LABEL: vfsub_vf_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v26, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -694,9 +694,9 @@ define @vfsub_vf_nxv2f64_unmasked( %v ; CHECK-LABEL: vfsub_vf_nxv2f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vfmv.v.f v26, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v26 +; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -734,9 +734,9 @@ define @vfsub_vf_nxv4f64( %va, double ; CHECK-LABEL: vfsub_vf_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v28, v0.t +; CHECK-NEXT: vfsub.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -748,9 +748,9 @@ define @vfsub_vf_nxv4f64_unmasked( %v ; CHECK-LABEL: vfsub_vf_nxv4f64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vfmv.v.f v28, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vfsub.vv v8, v8, v28 +; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: ret %elt.head = insertelement undef, double %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll index bddbfb8f99c0686565d59734e036251977e1dc5b..148959bd0c6d0eff3aa5cc926501fce6cc18b17c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll @@ -10,8 +10,8 @@ define @intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16( @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16( @@ -56,8 +56,8 @@ define @intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16( @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16( @@ -102,8 +102,8 @@ define @intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16( @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16( @@ -148,8 +148,8 @@ define @intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16( @llvm.riscv.vfwadd.nxv8f32.nxv8f16.nxv8f16( @@ -240,8 +240,8 @@ define @intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32( @llvm.riscv.vfwadd.nxv1f64.nxv1f32.nxv1f32( @@ -286,8 +286,8 @@ define @intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32( @llvm.riscv.vfwadd.nxv2f64.nxv2f32.nxv2f32( @@ -332,8 +332,8 @@ define @intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32( @llvm.riscv.vfwadd.nxv4f64.nxv4f32.nxv4f32( @@ -425,8 +425,8 @@ define @intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16( @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16( @@ -473,8 +473,8 @@ define @intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16( @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16( @@ -521,8 +521,8 @@ define @intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16( @llvm.riscv.vfwadd.nxv4f32.nxv4f16.f16( @@ -569,8 +569,8 @@ define @intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16( @llvm.riscv.vfwadd.nxv8f32.nxv8f16.f16( @@ -665,8 +665,8 @@ define @intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32( @llvm.riscv.vfwadd.nxv1f64.nxv1f32.f32( @@ -713,8 +713,8 @@ define @intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32( @llvm.riscv.vfwadd.nxv2f64.nxv2f32.f32( @@ -761,8 +761,8 @@ define @intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32( @llvm.riscv.vfwadd.nxv4f64.nxv4f32.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll index b810e11ac25727ef628c67fb296223d69542b1f8..d3d79942db091ff176167f5fd161014b1cbce2ad 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll @@ -10,8 +10,8 @@ define @intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16( @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16( @@ -56,8 +56,8 @@ define @intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16( @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16( @@ -102,8 +102,8 @@ define @intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16( @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16( @@ -148,8 +148,8 @@ define @intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16( @llvm.riscv.vfwadd.nxv8f32.nxv8f16.nxv8f16( @@ -240,8 +240,8 @@ define @intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32( @llvm.riscv.vfwadd.nxv1f64.nxv1f32.nxv1f32( @@ -286,8 +286,8 @@ define @intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32( @llvm.riscv.vfwadd.nxv2f64.nxv2f32.nxv2f32( @@ -332,8 +332,8 @@ define @intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32( @llvm.riscv.vfwadd.nxv4f64.nxv4f32.nxv4f32( @@ -425,8 +425,8 @@ define @intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16( @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16( @@ -473,8 +473,8 @@ define @intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16( @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16( @@ -521,8 +521,8 @@ define @intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16( @llvm.riscv.vfwadd.nxv4f32.nxv4f16.f16( @@ -569,8 +569,8 @@ define @intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16( @llvm.riscv.vfwadd.nxv8f32.nxv8f16.f16( @@ -665,8 +665,8 @@ define @intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32( @llvm.riscv.vfwadd.nxv1f64.nxv1f32.f32( @@ -713,8 +713,8 @@ define @intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32( @llvm.riscv.vfwadd.nxv2f64.nxv2f32.f32( @@ -761,8 +761,8 @@ define @intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32( @llvm.riscv.vfwadd.nxv4f64.nxv4f32.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll index be5b58847d2234d9869a28933f86f256dd224dde..ef02214f7922119c6efecaa7b965113a04e1e70c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll @@ -212,9 +212,9 @@ declare @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16( define @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16( @@ -393,9 +393,9 @@ declare @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32( define @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32( @@ -1150,8 +1150,8 @@ define @intrinsic_vfwadd.w_wv_untie_nxv1f32_nxv1f32_nxv1f16 ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfwadd.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwadd.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16( @@ -1166,8 +1166,8 @@ define @intrinsic_vfwadd.w_wv_untie_nxv2f32_nxv2f32_nxv2f16 ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfwadd.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwadd.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16( @@ -1182,8 +1182,8 @@ define @intrinsic_vfwadd.w_wv_untie_nxv4f32_nxv4f32_nxv4f16 ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfwadd.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwadd.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv4f32.nxv4f16( @@ -1198,8 +1198,8 @@ define @intrinsic_vfwadd.w_wv_untie_nxv8f32_nxv8f32_nxv8f16 ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfwadd.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwadd.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv8f32.nxv8f16( @@ -1214,8 +1214,8 @@ define @intrinsic_vfwadd.w_wv_untie_nxv1f64_nxv1f64_nxv1f3 ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfwadd.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwadd.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv1f64.nxv1f32( @@ -1230,8 +1230,8 @@ define @intrinsic_vfwadd.w_wv_untie_nxv2f64_nxv2f64_nxv2f3 ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfwadd.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwadd.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv2f64.nxv2f32( @@ -1246,8 +1246,8 @@ define @intrinsic_vfwadd.w_wv_untie_nxv4f64_nxv4f64_nxv4f3 ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfwadd.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwadd.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv4f64.nxv4f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll index df929cf7c50893132410d0cee97b741ad1b0bb55..439989e68e2702ee09aa6ae226336599d3a93dba 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll @@ -212,9 +212,9 @@ declare @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16( define @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16( @@ -393,9 +393,9 @@ declare @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32( define @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32( @@ -1150,8 +1150,8 @@ define @intrinsic_vfwadd.w_wv_untie_nxv1f32_nxv1f32_nxv1f16 ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfwadd.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwadd.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16( @@ -1166,8 +1166,8 @@ define @intrinsic_vfwadd.w_wv_untie_nxv2f32_nxv2f32_nxv2f16 ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfwadd.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwadd.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16( @@ -1182,8 +1182,8 @@ define @intrinsic_vfwadd.w_wv_untie_nxv4f32_nxv4f32_nxv4f16 ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfwadd.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwadd.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv4f32.nxv4f16( @@ -1198,8 +1198,8 @@ define @intrinsic_vfwadd.w_wv_untie_nxv8f32_nxv8f32_nxv8f16 ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfwadd.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwadd.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv8f32.nxv8f16( @@ -1214,8 +1214,8 @@ define @intrinsic_vfwadd.w_wv_untie_nxv1f64_nxv1f64_nxv1f3 ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfwadd.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwadd.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv1f64.nxv1f32( @@ -1230,8 +1230,8 @@ define @intrinsic_vfwadd.w_wv_untie_nxv2f64_nxv2f64_nxv2f3 ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfwadd.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwadd.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv2f64.nxv2f32( @@ -1246,8 +1246,8 @@ define @intrinsic_vfwadd.w_wv_untie_nxv4f64_nxv4f64_nxv4f3 ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfwadd.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwadd.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv4f64.nxv4f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll index e585b8e2fe6ba408e6e842b9236ad31d3d694384..813e352dea626cec95553c052f616f31700f136a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16( @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16( @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16( @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16( @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16( @@ -219,8 +219,8 @@ define @intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32( @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32( @@ -261,8 +261,8 @@ define @intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32( @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32( @@ -303,8 +303,8 @@ define @intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32( @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll index ce99c3a173f01a32876619cb9b39cbf34198dcc6..48e052c1e1d399f5ff75eca3e410d0c148576bac 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16( @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16( @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16( @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16( @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16( @@ -219,8 +219,8 @@ define @intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32( @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32( @@ -261,8 +261,8 @@ define @intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32( @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32( @@ -303,8 +303,8 @@ define @intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32( @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll index 6d54fbfd2b32426e9c6cc6de4d840d819a78dbd9..96171523910590b8994913fe573f2b43b88c1137 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8( @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8( @@ -51,8 +51,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8( @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8( @@ -93,8 +93,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8( @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8( @@ -135,8 +135,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8( @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8( @@ -177,8 +177,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8( @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8( @@ -261,8 +261,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16( @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16( @@ -303,8 +303,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16( @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16( @@ -345,8 +345,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16( @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16( @@ -387,8 +387,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16( @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16( @@ -471,8 +471,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32( @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32( @@ -513,8 +513,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32( @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32( @@ -555,8 +555,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32( @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll index f9a8c8ae920fe61dcb0722092225f3f3bc762d9e..e1279189e2228e0f2b12123d90a8fad7748617d7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8( @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8( @@ -51,8 +51,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8( @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8( @@ -93,8 +93,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8( @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8( @@ -135,8 +135,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8( @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8( @@ -177,8 +177,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8( @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8( @@ -261,8 +261,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16( @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16( @@ -303,8 +303,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16( @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16( @@ -345,8 +345,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16( @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16( @@ -387,8 +387,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16( @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16( @@ -471,8 +471,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32( @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32( @@ -513,8 +513,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32( @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32( @@ -555,8 +555,8 @@ define @intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32( @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll index bd6271bec8612973f52f1a39b2181533cc22a2b2..9147750fcc50a183ccaf4b6c62c450b72ab102cf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8( @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8( @@ -51,8 +51,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8( @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8( @@ -93,8 +93,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8( @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8( @@ -135,8 +135,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8( @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8( @@ -177,8 +177,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8( @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8( @@ -261,8 +261,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16( @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16( @@ -303,8 +303,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16( @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16( @@ -345,8 +345,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16( @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16( @@ -387,8 +387,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16( @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16( @@ -471,8 +471,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32( @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32( @@ -513,8 +513,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32( @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32( @@ -555,8 +555,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32( @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll index 88eee09e887906177e9f5b6dc3f5a2ea9e833476..e0a3ff909ef799251813eae9182e5bdeedadf019 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8( @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8( @@ -51,8 +51,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8( @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8( @@ -93,8 +93,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8( @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8( @@ -135,8 +135,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8( @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8( @@ -177,8 +177,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8( @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8( @@ -261,8 +261,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16( @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16( @@ -303,8 +303,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16( @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16( @@ -345,8 +345,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16( @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16( @@ -387,8 +387,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16( @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16( @@ -471,8 +471,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32( @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32( @@ -513,8 +513,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32( @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32( @@ -555,8 +555,8 @@ define @intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32( @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll index 79ecafc642bea804acb05826d5db3d480c3fa8a3..7dfd8968633e8b91c4b0f87340757494f5c482f1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16( @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16( @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16( @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16( @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16( @@ -219,8 +219,8 @@ define @intrinsic_vfwcvt_rtz.x.f.v_nxv1i64_nxv1f32( @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32( @@ -261,8 +261,8 @@ define @intrinsic_vfwcvt_rtz.x.f.v_nxv2i64_nxv2f32( @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32( @@ -303,8 +303,8 @@ define @intrinsic_vfwcvt_rtz.x.f.v_nxv4i64_nxv4f32( @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll index f7faf81d1b941d38bc9c53e7675f2732fef45cee..30b8a19463e7748ef921a3139221c07f2553e9c5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16( @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16( @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16( @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16( @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16( @@ -219,8 +219,8 @@ define @intrinsic_vfwcvt_rtz.x.f.v_nxv1i64_nxv1f32( @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32( @@ -261,8 +261,8 @@ define @intrinsic_vfwcvt_rtz.x.f.v_nxv2i64_nxv2f32( @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32( @@ -303,8 +303,8 @@ define @intrinsic_vfwcvt_rtz.x.f.v_nxv4i64_nxv4f32( @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll index c7d2f2d3c4dba51284cef32d366cc4b278746eb8..6b0e27d477e93056471462208bbcb89639d17630 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16( @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16( @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16( @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16( @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16( @@ -219,8 +219,8 @@ define @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i64_nxv1f32( @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32( @@ -261,8 +261,8 @@ define @intrinsic_vfwcvt_rtz.xu.f.v_nxv2i64_nxv2f32( @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32( @@ -303,8 +303,8 @@ define @intrinsic_vfwcvt_rtz.xu.f.v_nxv4i64_nxv4f32( @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll index 000faf235638089a2b290bfd1c3aea57d18ccd0b..6cef7abd1404b6e9651853ffbccc648bff43dad5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16( @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16( @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16( @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16( @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16( @@ -219,8 +219,8 @@ define @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i64_nxv1f32( @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32( @@ -261,8 +261,8 @@ define @intrinsic_vfwcvt_rtz.xu.f.v_nxv2i64_nxv2f32( @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32( @@ -303,8 +303,8 @@ define @intrinsic_vfwcvt_rtz.xu.f.v_nxv4i64_nxv4f32( @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll index 7cdf8afcec97584bc3ad967fc096d6abd11f0c77..9e1f9c0ed8ea433a4ac0a290429b748019538a9a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16( @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16( @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16( @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16( @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16( @@ -219,8 +219,8 @@ define @intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32( @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32( @@ -261,8 +261,8 @@ define @intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32( @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32( @@ -303,8 +303,8 @@ define @intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32( @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll index 046db374ec12b252e4c8110878c62be9fe2d892c..b25556da757df70fc72a35d0ae0cb2e547a7499e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16( @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16( @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16( @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16( @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16( @@ -219,8 +219,8 @@ define @intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32( @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32( @@ -261,8 +261,8 @@ define @intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32( @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32( @@ -303,8 +303,8 @@ define @intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32( @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll index d655219faa436426842a1a0f688e221b774287d3..69169adb5135c6640ac06b42811641c120bd83b7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16( @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16( @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16( @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16( @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16( @@ -219,8 +219,8 @@ define @intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32( @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32( @@ -261,8 +261,8 @@ define @intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32( @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32( @@ -303,8 +303,8 @@ define @intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32( @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll index b930e85cd04eb2dcbd2ecaac30f7acbe8950eea4..69b5d60e3183dcdd3a56c168397a2ddc6828c17d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16( @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16( @@ -51,8 +51,8 @@ define @intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16( @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16( @@ -93,8 +93,8 @@ define @intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16( @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16( @@ -135,8 +135,8 @@ define @intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16( @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16( @@ -219,8 +219,8 @@ define @intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32( @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32( @@ -261,8 +261,8 @@ define @intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32( @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32( @@ -303,8 +303,8 @@ define @intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32( @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll index 75bce7633dea7e71a8e34661e1fd6c7ee0ad3f76..cc496b80a4620ae775b7bddb3efd43269278c05f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll @@ -10,8 +10,8 @@ define @intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16( @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16( @@ -56,8 +56,8 @@ define @intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16( @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16( @@ -102,8 +102,8 @@ define @intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16( @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16( @@ -148,8 +148,8 @@ define @intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16( @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16( @@ -240,8 +240,8 @@ define @intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32( @llvm.riscv.vfwmul.nxv1f64.nxv1f32.nxv1f32( @@ -286,8 +286,8 @@ define @intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32( @llvm.riscv.vfwmul.nxv2f64.nxv2f32.nxv2f32( @@ -332,8 +332,8 @@ define @intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32( @llvm.riscv.vfwmul.nxv4f64.nxv4f32.nxv4f32( @@ -425,8 +425,8 @@ define @intrinsic_vfwmul_vf_nxv1f32_nxv1f16_f16( @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16( @@ -473,8 +473,8 @@ define @intrinsic_vfwmul_vf_nxv2f32_nxv2f16_f16( @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16( @@ -521,8 +521,8 @@ define @intrinsic_vfwmul_vf_nxv4f32_nxv4f16_f16( @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16( @@ -569,8 +569,8 @@ define @intrinsic_vfwmul_vf_nxv8f32_nxv8f16_f16( @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16( @@ -665,8 +665,8 @@ define @intrinsic_vfwmul_vf_nxv1f64_nxv1f32_f32( @llvm.riscv.vfwmul.nxv1f64.nxv1f32.f32( @@ -713,8 +713,8 @@ define @intrinsic_vfwmul_vf_nxv2f64_nxv2f32_f32( @llvm.riscv.vfwmul.nxv2f64.nxv2f32.f32( @@ -761,8 +761,8 @@ define @intrinsic_vfwmul_vf_nxv4f64_nxv4f32_f32( @llvm.riscv.vfwmul.nxv4f64.nxv4f32.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll index d7a3c0b7873a7b63420912d2825b7ce172ab624c..301b6174f6677d98c42a3a21e9808cc454de21f2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll @@ -10,8 +10,8 @@ define @intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16( @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16( @@ -56,8 +56,8 @@ define @intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16( @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16( @@ -102,8 +102,8 @@ define @intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16( @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16( @@ -148,8 +148,8 @@ define @intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16( @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16( @@ -240,8 +240,8 @@ define @intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32( @llvm.riscv.vfwmul.nxv1f64.nxv1f32.nxv1f32( @@ -286,8 +286,8 @@ define @intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32( @llvm.riscv.vfwmul.nxv2f64.nxv2f32.nxv2f32( @@ -332,8 +332,8 @@ define @intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32( @llvm.riscv.vfwmul.nxv4f64.nxv4f32.nxv4f32( @@ -425,8 +425,8 @@ define @intrinsic_vfwmul_vf_nxv1f32_nxv1f16_f16( @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16( @@ -473,8 +473,8 @@ define @intrinsic_vfwmul_vf_nxv2f32_nxv2f16_f16( @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16( @@ -521,8 +521,8 @@ define @intrinsic_vfwmul_vf_nxv4f32_nxv4f16_f16( @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16( @@ -569,8 +569,8 @@ define @intrinsic_vfwmul_vf_nxv8f32_nxv8f16_f16( @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16( @@ -665,8 +665,8 @@ define @intrinsic_vfwmul_vf_nxv1f64_nxv1f32_f32( @llvm.riscv.vfwmul.nxv1f64.nxv1f32.f32( @@ -713,8 +713,8 @@ define @intrinsic_vfwmul_vf_nxv2f64_nxv2f32_f32( @llvm.riscv.vfwmul.nxv2f64.nxv2f32.f32( @@ -761,8 +761,8 @@ define @intrinsic_vfwmul_vf_nxv4f64_nxv4f32_f32( @llvm.riscv.vfwmul.nxv4f64.nxv4f32.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll index 73eafee0fbd4319642bbdaffbd3872cb0f93b156..a1850c0083235363042ab5d9740f6294a4f3798f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll @@ -10,8 +10,8 @@ define @intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16( @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16( @@ -56,8 +56,8 @@ define @intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16( @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16( @@ -102,8 +102,8 @@ define @intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16( @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16( @@ -148,8 +148,8 @@ define @intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16( @llvm.riscv.vfwsub.nxv8f32.nxv8f16.nxv8f16( @@ -240,8 +240,8 @@ define @intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32( @llvm.riscv.vfwsub.nxv1f64.nxv1f32.nxv1f32( @@ -286,8 +286,8 @@ define @intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32( @llvm.riscv.vfwsub.nxv2f64.nxv2f32.nxv2f32( @@ -332,8 +332,8 @@ define @intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32( @llvm.riscv.vfwsub.nxv4f64.nxv4f32.nxv4f32( @@ -425,8 +425,8 @@ define @intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16( @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16( @@ -473,8 +473,8 @@ define @intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16( @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16( @@ -521,8 +521,8 @@ define @intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16( @llvm.riscv.vfwsub.nxv4f32.nxv4f16.f16( @@ -569,8 +569,8 @@ define @intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16( @llvm.riscv.vfwsub.nxv8f32.nxv8f16.f16( @@ -665,8 +665,8 @@ define @intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32( @llvm.riscv.vfwsub.nxv1f64.nxv1f32.f32( @@ -713,8 +713,8 @@ define @intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32( @llvm.riscv.vfwsub.nxv2f64.nxv2f32.f32( @@ -761,8 +761,8 @@ define @intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32( @llvm.riscv.vfwsub.nxv4f64.nxv4f32.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll index 80a2edda326aabc6bff260da778900801bc9614c..7659757f732f6a5777b6ce5b9b3501d6d1c71ffa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll @@ -10,8 +10,8 @@ define @intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16( @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16( @@ -56,8 +56,8 @@ define @intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16( @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16( @@ -102,8 +102,8 @@ define @intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16( @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16( @@ -148,8 +148,8 @@ define @intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16( @llvm.riscv.vfwsub.nxv8f32.nxv8f16.nxv8f16( @@ -240,8 +240,8 @@ define @intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32( @llvm.riscv.vfwsub.nxv1f64.nxv1f32.nxv1f32( @@ -286,8 +286,8 @@ define @intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32( @llvm.riscv.vfwsub.nxv2f64.nxv2f32.nxv2f32( @@ -332,8 +332,8 @@ define @intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32( @llvm.riscv.vfwsub.nxv4f64.nxv4f32.nxv4f32( @@ -425,8 +425,8 @@ define @intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16( @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16( @@ -473,8 +473,8 @@ define @intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16( @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16( @@ -521,8 +521,8 @@ define @intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16( @llvm.riscv.vfwsub.nxv4f32.nxv4f16.f16( @@ -569,8 +569,8 @@ define @intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16( @llvm.riscv.vfwsub.nxv8f32.nxv8f16.f16( @@ -665,8 +665,8 @@ define @intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32( @llvm.riscv.vfwsub.nxv1f64.nxv1f32.f32( @@ -713,8 +713,8 @@ define @intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32( @llvm.riscv.vfwsub.nxv2f64.nxv2f32.f32( @@ -761,8 +761,8 @@ define @intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32( @llvm.riscv.vfwsub.nxv4f64.nxv4f32.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll index ab5f16b13f763c7f8dc4fcf5ff2248afe1f108d3..d645f5729f367ca291bc34d4135143d156942a03 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll @@ -212,9 +212,9 @@ declare @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16( define @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16( @@ -393,9 +393,9 @@ declare @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32( define @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32( @@ -1150,8 +1150,8 @@ define @intrinsic_vfwsub.w_wv_untie_nxv1f32_nxv1f32_nxv1f16 ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfwsub.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwsub.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( @@ -1166,8 +1166,8 @@ define @intrinsic_vfwsub.w_wv_untie_nxv2f32_nxv2f32_nxv2f16 ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfwsub.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwsub.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16( @@ -1182,8 +1182,8 @@ define @intrinsic_vfwsub.w_wv_untie_nxv4f32_nxv4f32_nxv4f16 ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfwsub.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwsub.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv4f32.nxv4f16( @@ -1198,8 +1198,8 @@ define @intrinsic_vfwsub.w_wv_untie_nxv8f32_nxv8f32_nxv8f16 ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfwsub.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwsub.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv8f32.nxv8f16( @@ -1214,8 +1214,8 @@ define @intrinsic_vfwsub.w_wv_untie_nxv1f64_nxv1f64_nxv1f3 ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfwsub.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwsub.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv1f64.nxv1f32( @@ -1230,8 +1230,8 @@ define @intrinsic_vfwsub.w_wv_untie_nxv2f64_nxv2f64_nxv2f3 ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfwsub.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwsub.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv2f64.nxv2f32( @@ -1246,8 +1246,8 @@ define @intrinsic_vfwsub.w_wv_untie_nxv4f64_nxv4f64_nxv4f3 ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfwsub.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwsub.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv4f64.nxv4f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll index 901330cf51922e4e19c9f8ee32a956bc70876ae5..e9b4e577cea3396fc380fad6a000437a1a52ac85 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll @@ -212,9 +212,9 @@ declare @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16( define @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16( @@ -393,9 +393,9 @@ declare @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32( define @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32( @@ -1150,8 +1150,8 @@ define @intrinsic_vfwsub.w_wv_untie_nxv1f32_nxv1f32_nxv1f16 ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vfwsub.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwsub.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( @@ -1166,8 +1166,8 @@ define @intrinsic_vfwsub.w_wv_untie_nxv2f32_nxv2f32_nxv2f16 ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vfwsub.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwsub.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16( @@ -1182,8 +1182,8 @@ define @intrinsic_vfwsub.w_wv_untie_nxv4f32_nxv4f32_nxv4f16 ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vfwsub.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwsub.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv4f32.nxv4f16( @@ -1198,8 +1198,8 @@ define @intrinsic_vfwsub.w_wv_untie_nxv8f32_nxv8f32_nxv8f16 ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vfwsub.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwsub.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv8f32.nxv8f16( @@ -1214,8 +1214,8 @@ define @intrinsic_vfwsub.w_wv_untie_nxv1f64_nxv1f64_nxv1f3 ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vfwsub.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwsub.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv1f64.nxv1f32( @@ -1230,8 +1230,8 @@ define @intrinsic_vfwsub.w_wv_untie_nxv2f64_nxv2f64_nxv2f3 ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vfwsub.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwsub.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv2f64.nxv2f32( @@ -1246,8 +1246,8 @@ define @intrinsic_vfwsub.w_wv_untie_nxv4f64_nxv4f64_nxv4f3 ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vfwsub.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwsub.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv4f64.nxv4f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll index 0163c71071587ebb97c6fe1090ab14bc8a2d2e68..19dfb3532a3d8d0b1af03ad63538b5d9f2020afb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll @@ -8,9 +8,9 @@ define @vsitofp_nxv1i1_nxv1f16( %va) { ; CHECK-LABEL: vsitofp_nxv1i1_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 -; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -20,9 +20,9 @@ define @vuitofp_nxv1i1_nxv1f16( %va) { ; CHECK-LABEL: vuitofp_nxv1i1_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 -; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -32,9 +32,9 @@ define @vsitofp_nxv1i1_nxv1f32( %va) { ; CHECK-LABEL: vsitofp_nxv1i1_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 -; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -44,9 +44,9 @@ define @vuitofp_nxv1i1_nxv1f32( %va) { ; CHECK-LABEL: vuitofp_nxv1i1_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 -; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -56,9 +56,9 @@ define @vsitofp_nxv1i1_nxv1f64( %va) { ; CHECK-LABEL: vsitofp_nxv1i1_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 -; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -68,9 +68,9 @@ define @vuitofp_nxv1i1_nxv1f64( %va) { ; CHECK-LABEL: vuitofp_nxv1i1_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 -; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -80,9 +80,9 @@ define @vsitofp_nxv2i1_nxv2f16( %va) { ; CHECK-LABEL: vsitofp_nxv2i1_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 -; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -92,9 +92,9 @@ define @vuitofp_nxv2i1_nxv2f16( %va) { ; CHECK-LABEL: vuitofp_nxv2i1_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 -; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -104,9 +104,9 @@ define @vsitofp_nxv2i1_nxv2f32( %va) { ; CHECK-LABEL: vsitofp_nxv2i1_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 -; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -116,9 +116,9 @@ define @vuitofp_nxv2i1_nxv2f32( %va) { ; CHECK-LABEL: vuitofp_nxv2i1_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 -; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -128,9 +128,9 @@ define @vsitofp_nxv2i1_nxv2f64( %va) { ; CHECK-LABEL: vsitofp_nxv2i1_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, -1, v0 -; CHECK-NEXT: vfcvt.f.x.v v8, v26 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -140,9 +140,9 @@ define @vuitofp_nxv2i1_nxv2f64( %va) { ; CHECK-LABEL: vuitofp_nxv2i1_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 -; CHECK-NEXT: vfcvt.f.xu.v v8, v26 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -152,9 +152,9 @@ define @vsitofp_nxv4i1_nxv4f16( %va) { ; CHECK-LABEL: vsitofp_nxv4i1_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, -1, v0 -; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -164,9 +164,9 @@ define @vuitofp_nxv4i1_nxv4f16( %va) { ; CHECK-LABEL: vuitofp_nxv4i1_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 -; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -176,9 +176,9 @@ define @vsitofp_nxv4i1_nxv4f32( %va) { ; CHECK-LABEL: vsitofp_nxv4i1_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, -1, v0 -; CHECK-NEXT: vfcvt.f.x.v v8, v26 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -188,9 +188,9 @@ define @vuitofp_nxv4i1_nxv4f32( %va) { ; CHECK-LABEL: vuitofp_nxv4i1_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 -; CHECK-NEXT: vfcvt.f.xu.v v8, v26 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -200,9 +200,9 @@ define @vsitofp_nxv4i1_nxv4f64( %va) { ; CHECK-LABEL: vsitofp_nxv4i1_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v28, v28, -1, v0 -; CHECK-NEXT: vfcvt.f.x.v v8, v28 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -212,9 +212,9 @@ define @vuitofp_nxv4i1_nxv4f64( %va) { ; CHECK-LABEL: vuitofp_nxv4i1_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v28, v28, 1, v0 -; CHECK-NEXT: vfcvt.f.xu.v v8, v28 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -224,9 +224,9 @@ define @vsitofp_nxv8i1_nxv8f16( %va) { ; CHECK-LABEL: vsitofp_nxv8i1_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, -1, v0 -; CHECK-NEXT: vfcvt.f.x.v v8, v26 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -236,9 +236,9 @@ define @vuitofp_nxv8i1_nxv8f16( %va) { ; CHECK-LABEL: vuitofp_nxv8i1_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v26, v26, 1, v0 -; CHECK-NEXT: vfcvt.f.xu.v v8, v26 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -248,9 +248,9 @@ define @vsitofp_nxv8i1_nxv8f32( %va) { ; CHECK-LABEL: vsitofp_nxv8i1_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v28, v28, -1, v0 -; CHECK-NEXT: vfcvt.f.x.v v8, v28 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -260,9 +260,9 @@ define @vuitofp_nxv8i1_nxv8f32( %va) { ; CHECK-LABEL: vuitofp_nxv8i1_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v28, v28, 1, v0 -; CHECK-NEXT: vfcvt.f.xu.v v8, v28 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -296,9 +296,9 @@ define @vsitofp_nxv16i1_nxv16f16( %va) { ; CHECK-LABEL: vsitofp_nxv16i1_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v28, v28, -1, v0 -; CHECK-NEXT: vfcvt.f.x.v v8, v28 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 +; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -308,9 +308,9 @@ define @vuitofp_nxv16i1_nxv16f16( %va) { ; CHECK-LABEL: vuitofp_nxv16i1_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v28, v28, 1, v0 -; CHECK-NEXT: vfcvt.f.xu.v v8, v28 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -368,8 +368,8 @@ define @vsitofp_nxv1i8_nxv1f16( %va) { ; CHECK-LABEL: vsitofp_nxv1i8_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vfwcvt.f.x.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.f.x.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -379,8 +379,8 @@ define @vuitofp_nxv1i8_nxv1f16( %va) { ; CHECK-LABEL: vuitofp_nxv1i8_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.f.xu.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -390,8 +390,8 @@ define @vsitofp_nxv1i8_nxv1f32( %va) { ; CHECK-LABEL: vsitofp_nxv1i8_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vfcvt.f.x.v v8, v9 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -401,8 +401,8 @@ define @vuitofp_nxv1i8_nxv1f32( %va) { ; CHECK-LABEL: vuitofp_nxv1i8_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vfcvt.f.xu.v v8, v9 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -412,8 +412,8 @@ define @vsitofp_nxv1i8_nxv1f64( %va) { ; CHECK-LABEL: vsitofp_nxv1i8_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf8 v25, v8 -; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: vsext.vf8 v9, v8 +; CHECK-NEXT: vfcvt.f.x.v v8, v9 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -423,8 +423,8 @@ define @vuitofp_nxv1i8_nxv1f64( %va) { ; CHECK-LABEL: vuitofp_nxv1i8_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf8 v25, v8 -; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: vzext.vf8 v9, v8 +; CHECK-NEXT: vfcvt.f.xu.v v8, v9 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -434,8 +434,8 @@ define @vsitofp_nxv2i8_nxv2f16( %va) { ; CHECK-LABEL: vsitofp_nxv2i8_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vfwcvt.f.x.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.f.x.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -445,8 +445,8 @@ define @vuitofp_nxv2i8_nxv2f16( %va) { ; CHECK-LABEL: vuitofp_nxv2i8_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.f.xu.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -456,8 +456,8 @@ define @vsitofp_nxv2i8_nxv2f32( %va) { ; CHECK-LABEL: vsitofp_nxv2i8_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vfcvt.f.x.v v8, v9 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -467,8 +467,8 @@ define @vuitofp_nxv2i8_nxv2f32( %va) { ; CHECK-LABEL: vuitofp_nxv2i8_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vfcvt.f.xu.v v8, v9 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -478,8 +478,8 @@ define @vsitofp_nxv2i8_nxv2f64( %va) { ; CHECK-LABEL: vsitofp_nxv2i8_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf8 v26, v8 -; CHECK-NEXT: vfcvt.f.x.v v8, v26 +; CHECK-NEXT: vsext.vf8 v10, v8 +; CHECK-NEXT: vfcvt.f.x.v v8, v10 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -489,8 +489,8 @@ define @vuitofp_nxv2i8_nxv2f64( %va) { ; CHECK-LABEL: vuitofp_nxv2i8_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf8 v26, v8 -; CHECK-NEXT: vfcvt.f.xu.v v8, v26 +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vfcvt.f.xu.v v8, v10 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -500,8 +500,8 @@ define @vsitofp_nxv4i8_nxv4f16( %va) { ; CHECK-LABEL: vsitofp_nxv4i8_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vfwcvt.f.x.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.f.x.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -511,8 +511,8 @@ define @vuitofp_nxv4i8_nxv4f16( %va) { ; CHECK-LABEL: vuitofp_nxv4i8_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.f.xu.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -522,8 +522,8 @@ define @vsitofp_nxv4i8_nxv4f32( %va) { ; CHECK-LABEL: vsitofp_nxv4i8_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf4 v26, v8 -; CHECK-NEXT: vfcvt.f.x.v v8, v26 +; CHECK-NEXT: vsext.vf4 v10, v8 +; CHECK-NEXT: vfcvt.f.x.v v8, v10 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -533,8 +533,8 @@ define @vuitofp_nxv4i8_nxv4f32( %va) { ; CHECK-LABEL: vuitofp_nxv4i8_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf4 v26, v8 -; CHECK-NEXT: vfcvt.f.xu.v v8, v26 +; CHECK-NEXT: vzext.vf4 v10, v8 +; CHECK-NEXT: vfcvt.f.xu.v v8, v10 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -544,8 +544,8 @@ define @vsitofp_nxv4i8_nxv4f64( %va) { ; CHECK-LABEL: vsitofp_nxv4i8_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v28, v8 -; CHECK-NEXT: vfcvt.f.x.v v8, v28 +; CHECK-NEXT: vsext.vf8 v12, v8 +; CHECK-NEXT: vfcvt.f.x.v v8, v12 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -555,8 +555,8 @@ define @vuitofp_nxv4i8_nxv4f64( %va) { ; CHECK-LABEL: vuitofp_nxv4i8_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v28, v8 -; CHECK-NEXT: vfcvt.f.xu.v v8, v28 +; CHECK-NEXT: vzext.vf8 v12, v8 +; CHECK-NEXT: vfcvt.f.xu.v v8, v12 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -566,8 +566,8 @@ define @vsitofp_nxv8i8_nxv8f16( %va) { ; CHECK-LABEL: vsitofp_nxv8i8_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.x.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.f.x.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -577,8 +577,8 @@ define @vuitofp_nxv8i8_nxv8f16( %va) { ; CHECK-LABEL: vuitofp_nxv8i8_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.xu.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.f.xu.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -588,8 +588,8 @@ define @vsitofp_nxv8i8_nxv8f32( %va) { ; CHECK-LABEL: vsitofp_nxv8i8_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v8 -; CHECK-NEXT: vfcvt.f.x.v v8, v28 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vfcvt.f.x.v v8, v12 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -599,8 +599,8 @@ define @vuitofp_nxv8i8_nxv8f32( %va) { ; CHECK-LABEL: vuitofp_nxv8i8_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v8 -; CHECK-NEXT: vfcvt.f.xu.v v8, v28 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vfcvt.f.xu.v v8, v12 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -632,8 +632,8 @@ define @vsitofp_nxv16i8_nxv16f16( %va) { ; CHECK-LABEL: vsitofp_nxv16i8_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.x.v v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwcvt.f.x.v v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -643,8 +643,8 @@ define @vuitofp_nxv16i8_nxv16f16( %va) { ; CHECK-LABEL: vuitofp_nxv16i8_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.xu.v v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwcvt.f.xu.v v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -718,8 +718,8 @@ define @vsitofp_nxv1i16_nxv1f32( %va) { ; CHECK-LABEL: vsitofp_nxv1i16_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfwcvt.f.x.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.f.x.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -729,8 +729,8 @@ define @vuitofp_nxv1i16_nxv1f32( %va) { ; CHECK-LABEL: vuitofp_nxv1i16_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.f.xu.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -740,8 +740,8 @@ define @vsitofp_nxv1i16_nxv1f64( %va) { ; CHECK-LABEL: vsitofp_nxv1i16_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vfcvt.f.x.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vfcvt.f.x.v v8, v9 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -751,8 +751,8 @@ define @vuitofp_nxv1i16_nxv1f64( %va) { ; CHECK-LABEL: vuitofp_nxv1i16_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vfcvt.f.xu.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vfcvt.f.xu.v v8, v9 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -782,8 +782,8 @@ define @vsitofp_nxv2i16_nxv2f32( %va) { ; CHECK-LABEL: vsitofp_nxv2i16_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfwcvt.f.x.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.f.x.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -793,8 +793,8 @@ define @vuitofp_nxv2i16_nxv2f32( %va) { ; CHECK-LABEL: vuitofp_nxv2i16_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.f.xu.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -804,8 +804,8 @@ define @vsitofp_nxv2i16_nxv2f64( %va) { ; CHECK-LABEL: vsitofp_nxv2i16_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf4 v26, v8 -; CHECK-NEXT: vfcvt.f.x.v v8, v26 +; CHECK-NEXT: vsext.vf4 v10, v8 +; CHECK-NEXT: vfcvt.f.x.v v8, v10 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -815,8 +815,8 @@ define @vuitofp_nxv2i16_nxv2f64( %va) { ; CHECK-LABEL: vuitofp_nxv2i16_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf4 v26, v8 -; CHECK-NEXT: vfcvt.f.xu.v v8, v26 +; CHECK-NEXT: vzext.vf4 v10, v8 +; CHECK-NEXT: vfcvt.f.xu.v v8, v10 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -846,8 +846,8 @@ define @vsitofp_nxv4i16_nxv4f32( %va) { ; CHECK-LABEL: vsitofp_nxv4i16_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.x.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.f.x.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -857,8 +857,8 @@ define @vuitofp_nxv4i16_nxv4f32( %va) { ; CHECK-LABEL: vuitofp_nxv4i16_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.xu.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.f.xu.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -868,8 +868,8 @@ define @vsitofp_nxv4i16_nxv4f64( %va) { ; CHECK-LABEL: vsitofp_nxv4i16_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v8 -; CHECK-NEXT: vfcvt.f.x.v v8, v28 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vfcvt.f.x.v v8, v12 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -879,8 +879,8 @@ define @vuitofp_nxv4i16_nxv4f64( %va) { ; CHECK-LABEL: vuitofp_nxv4i16_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v8 -; CHECK-NEXT: vfcvt.f.xu.v v8, v28 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vfcvt.f.xu.v v8, v12 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -910,8 +910,8 @@ define @vsitofp_nxv8i16_nxv8f32( %va) { ; CHECK-LABEL: vsitofp_nxv8i16_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.x.v v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwcvt.f.x.v v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -921,8 +921,8 @@ define @vuitofp_nxv8i16_nxv8f32( %va) { ; CHECK-LABEL: vuitofp_nxv8i16_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.xu.v v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwcvt.f.xu.v v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1016,8 +1016,8 @@ define @vsitofp_nxv1i32_nxv1f16( %va) { ; CHECK-LABEL: vsitofp_nxv1i32_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.x.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1027,8 +1027,8 @@ define @vuitofp_nxv1i32_nxv1f16( %va) { ; CHECK-LABEL: vuitofp_nxv1i32_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.xu.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1058,8 +1058,8 @@ define @vsitofp_nxv1i32_nxv1f64( %va) { ; CHECK-LABEL: vsitofp_nxv1i32_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfwcvt.f.x.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.f.x.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1069,8 +1069,8 @@ define @vuitofp_nxv1i32_nxv1f64( %va) { ; CHECK-LABEL: vuitofp_nxv1i32_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfwcvt.f.xu.v v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1080,8 +1080,8 @@ define @vsitofp_nxv2i32_nxv2f16( %va) { ; CHECK-LABEL: vsitofp_nxv2i32_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.x.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1091,8 +1091,8 @@ define @vuitofp_nxv2i32_nxv2f16( %va) { ; CHECK-LABEL: vuitofp_nxv2i32_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.xu.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1122,8 +1122,8 @@ define @vsitofp_nxv2i32_nxv2f64( %va) { ; CHECK-LABEL: vsitofp_nxv2i32_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.x.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.f.x.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1133,8 +1133,8 @@ define @vuitofp_nxv2i32_nxv2f64( %va) { ; CHECK-LABEL: vuitofp_nxv2i32_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfwcvt.f.xu.v v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfwcvt.f.xu.v v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1144,8 +1144,8 @@ define @vsitofp_nxv4i32_nxv4f16( %va) { ; CHECK-LABEL: vsitofp_nxv4i32_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.x.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1155,8 +1155,8 @@ define @vuitofp_nxv4i32_nxv4f16( %va) { ; CHECK-LABEL: vuitofp_nxv4i32_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.xu.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1186,8 +1186,8 @@ define @vsitofp_nxv4i32_nxv4f64( %va) { ; CHECK-LABEL: vsitofp_nxv4i32_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.x.v v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwcvt.f.x.v v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1197,8 +1197,8 @@ define @vuitofp_nxv4i32_nxv4f64( %va) { ; CHECK-LABEL: vuitofp_nxv4i32_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfwcvt.f.xu.v v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfwcvt.f.xu.v v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1208,8 +1208,8 @@ define @vsitofp_nxv8i32_nxv8f16( %va) { ; CHECK-LABEL: vsitofp_nxv8i32_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfncvt.f.x.w v12, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1219,8 +1219,8 @@ define @vuitofp_nxv8i32_nxv8f16( %va) { ; CHECK-LABEL: vuitofp_nxv8i32_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfncvt.f.xu.w v12, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1272,8 +1272,8 @@ define @vsitofp_nxv16i32_nxv16f16( %va) ; CHECK-LABEL: vsitofp_nxv16i32_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfncvt.f.x.w v16, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1283,8 +1283,8 @@ define @vuitofp_nxv16i32_nxv16f16( %va) ; CHECK-LABEL: vuitofp_nxv16i32_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfncvt.f.xu.w v16, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1314,9 +1314,9 @@ define @vsitofp_nxv1i64_nxv1f16( %va) { ; CHECK-LABEL: vsitofp_nxv1i64_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v25, v8 +; CHECK-NEXT: vfncvt.f.x.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.f.f.w v8, v25 +; CHECK-NEXT: vfncvt.f.f.w v8, v9 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1326,9 +1326,9 @@ define @vuitofp_nxv1i64_nxv1f16( %va) { ; CHECK-LABEL: vuitofp_nxv1i64_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v25, v8 +; CHECK-NEXT: vfncvt.f.xu.w v9, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfncvt.f.f.w v8, v25 +; CHECK-NEXT: vfncvt.f.f.w v8, v9 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1338,8 +1338,8 @@ define @vsitofp_nxv1i64_nxv1f32( %va) { ; CHECK-LABEL: vsitofp_nxv1i64_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.x.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1349,8 +1349,8 @@ define @vuitofp_nxv1i64_nxv1f32( %va) { ; CHECK-LABEL: vuitofp_nxv1i64_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.xu.w v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1380,9 +1380,9 @@ define @vsitofp_nxv2i64_nxv2f16( %va) { ; CHECK-LABEL: vsitofp_nxv2i64_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v25, v8 +; CHECK-NEXT: vfncvt.f.x.w v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfncvt.f.f.w v8, v25 +; CHECK-NEXT: vfncvt.f.f.w v8, v10 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1392,9 +1392,9 @@ define @vuitofp_nxv2i64_nxv2f16( %va) { ; CHECK-LABEL: vuitofp_nxv2i64_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v25, v8 +; CHECK-NEXT: vfncvt.f.xu.w v10, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfncvt.f.f.w v8, v25 +; CHECK-NEXT: vfncvt.f.f.w v8, v10 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1404,8 +1404,8 @@ define @vsitofp_nxv2i64_nxv2f32( %va) { ; CHECK-LABEL: vsitofp_nxv2i64_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.x.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1415,8 +1415,8 @@ define @vuitofp_nxv2i64_nxv2f32( %va) { ; CHECK-LABEL: vuitofp_nxv2i64_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vfncvt.f.xu.w v10, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1446,9 +1446,9 @@ define @vsitofp_nxv4i64_nxv4f16( %va) { ; CHECK-LABEL: vsitofp_nxv4i64_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v26, v8 +; CHECK-NEXT: vfncvt.f.x.w v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vfncvt.f.f.w v8, v26 +; CHECK-NEXT: vfncvt.f.f.w v8, v12 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1458,9 +1458,9 @@ define @vuitofp_nxv4i64_nxv4f16( %va) { ; CHECK-LABEL: vuitofp_nxv4i64_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v26, v8 +; CHECK-NEXT: vfncvt.f.xu.w v12, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vfncvt.f.f.w v8, v26 +; CHECK-NEXT: vfncvt.f.f.w v8, v12 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1470,8 +1470,8 @@ define @vsitofp_nxv4i64_nxv4f32( %va) { ; CHECK-LABEL: vsitofp_nxv4i64_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfncvt.f.x.w v12, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1481,8 +1481,8 @@ define @vuitofp_nxv4i64_nxv4f32( %va) { ; CHECK-LABEL: vuitofp_nxv4i64_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vfncvt.f.xu.w v12, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1512,9 +1512,9 @@ define @vsitofp_nxv8i64_nxv8f16( %va) { ; CHECK-LABEL: vsitofp_nxv8i64_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v28, v8 +; CHECK-NEXT: vfncvt.f.x.w v16, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vfncvt.f.f.w v8, v28 +; CHECK-NEXT: vfncvt.f.f.w v8, v16 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1524,9 +1524,9 @@ define @vuitofp_nxv8i64_nxv8f16( %va) { ; CHECK-LABEL: vuitofp_nxv8i64_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v28, v8 +; CHECK-NEXT: vfncvt.f.xu.w v16, v8 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vfncvt.f.f.w v8, v28 +; CHECK-NEXT: vfncvt.f.f.w v8, v16 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec @@ -1536,8 +1536,8 @@ define @vsitofp_nxv8i64_nxv8f32( %va) { ; CHECK-LABEL: vsitofp_nxv8i64_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfncvt.f.x.w v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfncvt.f.x.w v16, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret %evec = sitofp %va to ret %evec @@ -1547,8 +1547,8 @@ define @vuitofp_nxv8i64_nxv8f32( %va) { ; CHECK-LABEL: vuitofp_nxv8i64_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vfncvt.f.xu.w v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vfncvt.f.xu.w v16, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret %evec = uitofp %va to ret %evec diff --git a/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll index c041fa5806ef2d3caab9a96dd96dee53583fbf63..27a32d8095d00fdd111dc282f9fcfd11fef82474 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll @@ -1888,7 +1888,7 @@ define void @intrinsic_vleff_dead_value(* %0, i32 %1, i32* ; CHECK-LABEL: intrinsic_vleff_dead_value: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vle64ff.v v25, (a0) +; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: sw a0, 0(a2) ; CHECK-NEXT: ret @@ -1926,7 +1926,7 @@ define void @intrinsic_vleff_dead_all(* %0, i32 %1, i32* %2 ; CHECK-LABEL: intrinsic_vleff_dead_all: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vle64ff.v v25, (a0) +; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call { , i32 } @llvm.riscv.vleff.nxv1f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll index a7099b82dee01e1b7a79753b668f51f1a0fd1711..b76cb4b8c92e07d5f6e3cd29e61671fbe6598295 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll @@ -1888,7 +1888,7 @@ define void @intrinsic_vleff_dead_value(* %0, i64 %1, i64* ; CHECK-LABEL: intrinsic_vleff_dead_value: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vle64ff.v v25, (a0) +; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: csrr a0, vl ; CHECK-NEXT: sd a0, 0(a2) ; CHECK-NEXT: ret @@ -1926,7 +1926,7 @@ define void @intrinsic_vleff_dead_all(* %0, i64 %1) nounwin ; CHECK-LABEL: intrinsic_vleff_dead_all: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vle64ff.v v25, (a0) +; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call { , i64 } @llvm.riscv.vleff.nxv1f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll index 2a49fc1f09325713005e50d400a925b626164888..3ac1d59e7b8a2d157481f57962a54150da2d4495 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll @@ -10,8 +10,8 @@ define @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64( @llvm.riscv.vloxei.nxv1i8.nxv1i64( @@ -56,8 +56,8 @@ define @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i64( @llvm.riscv.vloxei.nxv2i8.nxv2i64( @@ -102,8 +102,8 @@ define @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i64( @llvm.riscv.vloxei.nxv4i8.nxv4i64( @@ -148,8 +148,8 @@ define @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i64( @llvm.riscv.vloxei.nxv8i8.nxv8i64( @@ -194,8 +194,8 @@ define @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64( @llvm.riscv.vloxei.nxv1i16.nxv1i64( @@ -240,8 +240,8 @@ define @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i64( @llvm.riscv.vloxei.nxv2i16.nxv2i64( @@ -286,8 +286,8 @@ define @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i64( @llvm.riscv.vloxei.nxv4i16.nxv4i64( @@ -332,8 +332,8 @@ define @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i64( @llvm.riscv.vloxei.nxv8i16.nxv8i64( @@ -378,8 +378,8 @@ define @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64( @llvm.riscv.vloxei.nxv1i32.nxv1i64( @@ -424,8 +424,8 @@ define @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i64( @llvm.riscv.vloxei.nxv2i32.nxv2i64( @@ -470,8 +470,8 @@ define @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i64( @llvm.riscv.vloxei.nxv4i32.nxv4i64( @@ -516,8 +516,8 @@ define @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i64( @llvm.riscv.vloxei.nxv8i32.nxv8i64( @@ -742,8 +742,8 @@ define @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64( @llvm.riscv.vloxei.nxv1f16.nxv1i64( @@ -788,8 +788,8 @@ define @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i64( @llvm.riscv.vloxei.nxv2f16.nxv2i64( @@ -834,8 +834,8 @@ define @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i64( @llvm.riscv.vloxei.nxv4f16.nxv4i64( @@ -880,8 +880,8 @@ define @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i64( @llvm.riscv.vloxei.nxv8f16.nxv8i64( @@ -926,8 +926,8 @@ define @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64( @llvm.riscv.vloxei.nxv1f32.nxv1i64( @@ -972,8 +972,8 @@ define @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i64( @llvm.riscv.vloxei.nxv2f32.nxv2i64( @@ -1018,8 +1018,8 @@ define @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i64( @llvm.riscv.vloxei.nxv4f32.nxv4i64( @@ -1064,8 +1064,8 @@ define @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i64( @llvm.riscv.vloxei.nxv8f32.nxv8i64( @@ -1290,8 +1290,8 @@ define @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32( @llvm.riscv.vloxei.nxv1i8.nxv1i32( @@ -1336,8 +1336,8 @@ define @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32( @llvm.riscv.vloxei.nxv2i8.nxv2i32( @@ -1382,8 +1382,8 @@ define @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32( @llvm.riscv.vloxei.nxv4i8.nxv4i32( @@ -1428,8 +1428,8 @@ define @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32( @llvm.riscv.vloxei.nxv8i8.nxv8i32( @@ -1474,8 +1474,8 @@ define @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32( @llvm.riscv.vloxei.nxv16i8.nxv16i32( @@ -1520,8 +1520,8 @@ define @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32( @llvm.riscv.vloxei.nxv1i16.nxv1i32( @@ -1566,8 +1566,8 @@ define @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32( @llvm.riscv.vloxei.nxv2i16.nxv2i32( @@ -1612,8 +1612,8 @@ define @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32( @llvm.riscv.vloxei.nxv4i16.nxv4i32( @@ -1658,8 +1658,8 @@ define @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32( @llvm.riscv.vloxei.nxv8i16.nxv8i32( @@ -1704,8 +1704,8 @@ define @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32( @llvm.riscv.vloxei.nxv16i16.nxv16i32( @@ -1975,8 +1975,8 @@ define @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32( @llvm.riscv.vloxei.nxv1i64.nxv1i32( @@ -2021,8 +2021,8 @@ define @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32( @llvm.riscv.vloxei.nxv2i64.nxv2i32( @@ -2067,8 +2067,8 @@ define @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32( @llvm.riscv.vloxei.nxv4i64.nxv4i32( @@ -2159,8 +2159,8 @@ define @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32( @llvm.riscv.vloxei.nxv1f16.nxv1i32( @@ -2205,8 +2205,8 @@ define @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32( @llvm.riscv.vloxei.nxv2f16.nxv2i32( @@ -2251,8 +2251,8 @@ define @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32( @llvm.riscv.vloxei.nxv4f16.nxv4i32( @@ -2297,8 +2297,8 @@ define @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32( @llvm.riscv.vloxei.nxv8f16.nxv8i32( @@ -2343,8 +2343,8 @@ define @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32( @llvm.riscv.vloxei.nxv16f16.nxv16i32( @@ -2614,8 +2614,8 @@ define @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32( @llvm.riscv.vloxei.nxv1f64.nxv1i32( @@ -2660,8 +2660,8 @@ define @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32( @llvm.riscv.vloxei.nxv2f64.nxv2i32( @@ -2706,8 +2706,8 @@ define @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32( @llvm.riscv.vloxei.nxv4f64.nxv4i32( @@ -2798,8 +2798,8 @@ define @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16( @llvm.riscv.vloxei.nxv1i8.nxv1i16( @@ -2844,8 +2844,8 @@ define @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16( @llvm.riscv.vloxei.nxv2i8.nxv2i16( @@ -2890,8 +2890,8 @@ define @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16( @llvm.riscv.vloxei.nxv4i8.nxv4i16( @@ -2936,8 +2936,8 @@ define @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16( @llvm.riscv.vloxei.nxv8i8.nxv8i16( @@ -2982,8 +2982,8 @@ define @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16( @llvm.riscv.vloxei.nxv16i8.nxv16i16( @@ -3028,8 +3028,8 @@ define @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16( @llvm.riscv.vloxei.nxv32i8.nxv32i16( @@ -3344,8 +3344,8 @@ define @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16( @llvm.riscv.vloxei.nxv1i32.nxv1i16( @@ -3390,8 +3390,8 @@ define @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16( @llvm.riscv.vloxei.nxv2i32.nxv2i16( @@ -3436,8 +3436,8 @@ define @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16( @llvm.riscv.vloxei.nxv4i32.nxv4i16( @@ -3482,8 +3482,8 @@ define @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16( @llvm.riscv.vloxei.nxv8i32.nxv8i16( @@ -3574,8 +3574,8 @@ define @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16( @llvm.riscv.vloxei.nxv1i64.nxv1i16( @@ -3620,8 +3620,8 @@ define @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16( @llvm.riscv.vloxei.nxv2i64.nxv2i16( @@ -3666,8 +3666,8 @@ define @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16( @llvm.riscv.vloxei.nxv4i64.nxv4i16( @@ -4028,8 +4028,8 @@ define @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16( @llvm.riscv.vloxei.nxv1f32.nxv1i16( @@ -4074,8 +4074,8 @@ define @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16( @llvm.riscv.vloxei.nxv2f32.nxv2i16( @@ -4120,8 +4120,8 @@ define @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16( @llvm.riscv.vloxei.nxv4f32.nxv4i16( @@ -4166,8 +4166,8 @@ define @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16( @llvm.riscv.vloxei.nxv8f32.nxv8i16( @@ -4258,8 +4258,8 @@ define @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16( @llvm.riscv.vloxei.nxv1f64.nxv1i16( @@ -4304,8 +4304,8 @@ define @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16( @llvm.riscv.vloxei.nxv2f64.nxv2i16( @@ -4350,8 +4350,8 @@ define @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16( @llvm.riscv.vloxei.nxv4f64.nxv4i16( @@ -4757,8 +4757,8 @@ define @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8( @llvm.riscv.vloxei.nxv1i16.nxv1i8( @@ -4803,8 +4803,8 @@ define @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8( @llvm.riscv.vloxei.nxv2i16.nxv2i8( @@ -4849,8 +4849,8 @@ define @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8( @llvm.riscv.vloxei.nxv4i16.nxv4i8( @@ -4895,8 +4895,8 @@ define @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8( @llvm.riscv.vloxei.nxv8i16.nxv8i8( @@ -4941,8 +4941,8 @@ define @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8( @llvm.riscv.vloxei.nxv16i16.nxv16i8( @@ -5033,8 +5033,8 @@ define @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8( @llvm.riscv.vloxei.nxv1i32.nxv1i8( @@ -5079,8 +5079,8 @@ define @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8( @llvm.riscv.vloxei.nxv2i32.nxv2i8( @@ -5125,8 +5125,8 @@ define @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8( @llvm.riscv.vloxei.nxv4i32.nxv4i8( @@ -5171,8 +5171,8 @@ define @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8( @llvm.riscv.vloxei.nxv8i32.nxv8i8( @@ -5263,8 +5263,8 @@ define @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8( @llvm.riscv.vloxei.nxv1i64.nxv1i8( @@ -5309,8 +5309,8 @@ define @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8( @llvm.riscv.vloxei.nxv2i64.nxv2i8( @@ -5355,8 +5355,8 @@ define @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8( @llvm.riscv.vloxei.nxv4i64.nxv4i8( @@ -5447,8 +5447,8 @@ define @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8( @llvm.riscv.vloxei.nxv1f16.nxv1i8( @@ -5493,8 +5493,8 @@ define @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8( @llvm.riscv.vloxei.nxv2f16.nxv2i8( @@ -5539,8 +5539,8 @@ define @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8( @llvm.riscv.vloxei.nxv4f16.nxv4i8( @@ -5585,8 +5585,8 @@ define @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8( @llvm.riscv.vloxei.nxv8f16.nxv8i8( @@ -5631,8 +5631,8 @@ define @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8( @llvm.riscv.vloxei.nxv16f16.nxv16i8( @@ -5723,8 +5723,8 @@ define @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8( @llvm.riscv.vloxei.nxv1f32.nxv1i8( @@ -5769,8 +5769,8 @@ define @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8( @llvm.riscv.vloxei.nxv2f32.nxv2i8( @@ -5815,8 +5815,8 @@ define @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8( @llvm.riscv.vloxei.nxv4f32.nxv4i8( @@ -5861,8 +5861,8 @@ define @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8( @llvm.riscv.vloxei.nxv8f32.nxv8i8( @@ -5953,8 +5953,8 @@ define @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8( @llvm.riscv.vloxei.nxv1f64.nxv1i8( @@ -5999,8 +5999,8 @@ define @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8( @llvm.riscv.vloxei.nxv2f64.nxv2i8( @@ -6045,8 +6045,8 @@ define @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8( @llvm.riscv.vloxei.nxv4f64.nxv4i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll index fb9db003dc5e6826d1d94358e787cdf89c01c123..47e7393c3f1cae5ee8e68a95f78effd36465e2ab 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll @@ -10,8 +10,8 @@ define @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64( @llvm.riscv.vloxei.nxv1i8.nxv1i64( @@ -56,8 +56,8 @@ define @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i64( @llvm.riscv.vloxei.nxv2i8.nxv2i64( @@ -102,8 +102,8 @@ define @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i64( @llvm.riscv.vloxei.nxv4i8.nxv4i64( @@ -148,8 +148,8 @@ define @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i64( @llvm.riscv.vloxei.nxv8i8.nxv8i64( @@ -194,8 +194,8 @@ define @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64( @llvm.riscv.vloxei.nxv1i16.nxv1i64( @@ -240,8 +240,8 @@ define @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i64( @llvm.riscv.vloxei.nxv2i16.nxv2i64( @@ -286,8 +286,8 @@ define @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i64( @llvm.riscv.vloxei.nxv4i16.nxv4i64( @@ -332,8 +332,8 @@ define @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i64( @llvm.riscv.vloxei.nxv8i16.nxv8i64( @@ -378,8 +378,8 @@ define @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64( @llvm.riscv.vloxei.nxv1i32.nxv1i64( @@ -424,8 +424,8 @@ define @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i64( @llvm.riscv.vloxei.nxv2i32.nxv2i64( @@ -470,8 +470,8 @@ define @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i64( @llvm.riscv.vloxei.nxv4i32.nxv4i64( @@ -516,8 +516,8 @@ define @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i64( @llvm.riscv.vloxei.nxv8i32.nxv8i64( @@ -742,8 +742,8 @@ define @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64( @llvm.riscv.vloxei.nxv1f16.nxv1i64( @@ -788,8 +788,8 @@ define @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i64( @llvm.riscv.vloxei.nxv2f16.nxv2i64( @@ -834,8 +834,8 @@ define @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i64( @llvm.riscv.vloxei.nxv4f16.nxv4i64( @@ -880,8 +880,8 @@ define @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i64( @llvm.riscv.vloxei.nxv8f16.nxv8i64( @@ -926,8 +926,8 @@ define @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64( @llvm.riscv.vloxei.nxv1f32.nxv1i64( @@ -972,8 +972,8 @@ define @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i64( @llvm.riscv.vloxei.nxv2f32.nxv2i64( @@ -1018,8 +1018,8 @@ define @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i64( @llvm.riscv.vloxei.nxv4f32.nxv4i64( @@ -1064,8 +1064,8 @@ define @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i64( @llvm.riscv.vloxei.nxv8f32.nxv8i64( @@ -1290,8 +1290,8 @@ define @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32( @llvm.riscv.vloxei.nxv1i8.nxv1i32( @@ -1336,8 +1336,8 @@ define @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32( @llvm.riscv.vloxei.nxv2i8.nxv2i32( @@ -1382,8 +1382,8 @@ define @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32( @llvm.riscv.vloxei.nxv4i8.nxv4i32( @@ -1428,8 +1428,8 @@ define @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32( @llvm.riscv.vloxei.nxv8i8.nxv8i32( @@ -1474,8 +1474,8 @@ define @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32( @llvm.riscv.vloxei.nxv16i8.nxv16i32( @@ -1520,8 +1520,8 @@ define @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32( @llvm.riscv.vloxei.nxv1i16.nxv1i32( @@ -1566,8 +1566,8 @@ define @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32( @llvm.riscv.vloxei.nxv2i16.nxv2i32( @@ -1612,8 +1612,8 @@ define @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32( @llvm.riscv.vloxei.nxv4i16.nxv4i32( @@ -1658,8 +1658,8 @@ define @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32( @llvm.riscv.vloxei.nxv8i16.nxv8i32( @@ -1704,8 +1704,8 @@ define @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32( @llvm.riscv.vloxei.nxv16i16.nxv16i32( @@ -1975,8 +1975,8 @@ define @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32( @llvm.riscv.vloxei.nxv1i64.nxv1i32( @@ -2021,8 +2021,8 @@ define @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32( @llvm.riscv.vloxei.nxv2i64.nxv2i32( @@ -2067,8 +2067,8 @@ define @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32( @llvm.riscv.vloxei.nxv4i64.nxv4i32( @@ -2159,8 +2159,8 @@ define @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32( @llvm.riscv.vloxei.nxv1f16.nxv1i32( @@ -2205,8 +2205,8 @@ define @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32( @llvm.riscv.vloxei.nxv2f16.nxv2i32( @@ -2251,8 +2251,8 @@ define @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32( @llvm.riscv.vloxei.nxv4f16.nxv4i32( @@ -2297,8 +2297,8 @@ define @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32( @llvm.riscv.vloxei.nxv8f16.nxv8i32( @@ -2343,8 +2343,8 @@ define @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32( @llvm.riscv.vloxei.nxv16f16.nxv16i32( @@ -2614,8 +2614,8 @@ define @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32( @llvm.riscv.vloxei.nxv1f64.nxv1i32( @@ -2660,8 +2660,8 @@ define @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32( @llvm.riscv.vloxei.nxv2f64.nxv2i32( @@ -2706,8 +2706,8 @@ define @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32( @llvm.riscv.vloxei.nxv4f64.nxv4i32( @@ -2798,8 +2798,8 @@ define @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16( @llvm.riscv.vloxei.nxv1i8.nxv1i16( @@ -2844,8 +2844,8 @@ define @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16( @llvm.riscv.vloxei.nxv2i8.nxv2i16( @@ -2890,8 +2890,8 @@ define @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16( @llvm.riscv.vloxei.nxv4i8.nxv4i16( @@ -2936,8 +2936,8 @@ define @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16( @llvm.riscv.vloxei.nxv8i8.nxv8i16( @@ -2982,8 +2982,8 @@ define @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16( @llvm.riscv.vloxei.nxv16i8.nxv16i16( @@ -3028,8 +3028,8 @@ define @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16( @llvm.riscv.vloxei.nxv32i8.nxv32i16( @@ -3344,8 +3344,8 @@ define @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16( @llvm.riscv.vloxei.nxv1i32.nxv1i16( @@ -3390,8 +3390,8 @@ define @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16( @llvm.riscv.vloxei.nxv2i32.nxv2i16( @@ -3436,8 +3436,8 @@ define @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16( @llvm.riscv.vloxei.nxv4i32.nxv4i16( @@ -3482,8 +3482,8 @@ define @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16( @llvm.riscv.vloxei.nxv8i32.nxv8i16( @@ -3574,8 +3574,8 @@ define @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16( @llvm.riscv.vloxei.nxv1i64.nxv1i16( @@ -3620,8 +3620,8 @@ define @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16( @llvm.riscv.vloxei.nxv2i64.nxv2i16( @@ -3666,8 +3666,8 @@ define @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16( @llvm.riscv.vloxei.nxv4i64.nxv4i16( @@ -4028,8 +4028,8 @@ define @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16( @llvm.riscv.vloxei.nxv1f32.nxv1i16( @@ -4074,8 +4074,8 @@ define @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16( @llvm.riscv.vloxei.nxv2f32.nxv2i16( @@ -4120,8 +4120,8 @@ define @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16( @llvm.riscv.vloxei.nxv4f32.nxv4i16( @@ -4166,8 +4166,8 @@ define @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16( @llvm.riscv.vloxei.nxv8f32.nxv8i16( @@ -4258,8 +4258,8 @@ define @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16( @llvm.riscv.vloxei.nxv1f64.nxv1i16( @@ -4304,8 +4304,8 @@ define @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16( @llvm.riscv.vloxei.nxv2f64.nxv2i16( @@ -4350,8 +4350,8 @@ define @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16( @llvm.riscv.vloxei.nxv4f64.nxv4i16( @@ -4757,8 +4757,8 @@ define @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8( @llvm.riscv.vloxei.nxv1i16.nxv1i8( @@ -4803,8 +4803,8 @@ define @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8( @llvm.riscv.vloxei.nxv2i16.nxv2i8( @@ -4849,8 +4849,8 @@ define @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8( @llvm.riscv.vloxei.nxv4i16.nxv4i8( @@ -4895,8 +4895,8 @@ define @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8( @llvm.riscv.vloxei.nxv8i16.nxv8i8( @@ -4941,8 +4941,8 @@ define @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8( @llvm.riscv.vloxei.nxv16i16.nxv16i8( @@ -5033,8 +5033,8 @@ define @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8( @llvm.riscv.vloxei.nxv1i32.nxv1i8( @@ -5079,8 +5079,8 @@ define @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8( @llvm.riscv.vloxei.nxv2i32.nxv2i8( @@ -5125,8 +5125,8 @@ define @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8( @llvm.riscv.vloxei.nxv4i32.nxv4i8( @@ -5171,8 +5171,8 @@ define @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8( @llvm.riscv.vloxei.nxv8i32.nxv8i8( @@ -5263,8 +5263,8 @@ define @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8( @llvm.riscv.vloxei.nxv1i64.nxv1i8( @@ -5309,8 +5309,8 @@ define @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8( @llvm.riscv.vloxei.nxv2i64.nxv2i8( @@ -5355,8 +5355,8 @@ define @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8( @llvm.riscv.vloxei.nxv4i64.nxv4i8( @@ -5447,8 +5447,8 @@ define @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8( @llvm.riscv.vloxei.nxv1f16.nxv1i8( @@ -5493,8 +5493,8 @@ define @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8( @llvm.riscv.vloxei.nxv2f16.nxv2i8( @@ -5539,8 +5539,8 @@ define @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8( @llvm.riscv.vloxei.nxv4f16.nxv4i8( @@ -5585,8 +5585,8 @@ define @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8( @llvm.riscv.vloxei.nxv8f16.nxv8i8( @@ -5631,8 +5631,8 @@ define @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8( @llvm.riscv.vloxei.nxv16f16.nxv16i8( @@ -5723,8 +5723,8 @@ define @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8( @llvm.riscv.vloxei.nxv1f32.nxv1i8( @@ -5769,8 +5769,8 @@ define @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8( @llvm.riscv.vloxei.nxv2f32.nxv2i8( @@ -5815,8 +5815,8 @@ define @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8( @llvm.riscv.vloxei.nxv4f32.nxv4i8( @@ -5861,8 +5861,8 @@ define @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8( @llvm.riscv.vloxei.nxv8f32.nxv8i8( @@ -5953,8 +5953,8 @@ define @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8( @llvm.riscv.vloxei.nxv1f64.nxv1i8( @@ -5999,8 +5999,8 @@ define @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8( @llvm.riscv.vloxei.nxv2f64.nxv2i8( @@ -6045,8 +6045,8 @@ define @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8( @llvm.riscv.vloxei.nxv4f64.nxv4i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll index 5a06573d78dc591e48261dff2a9b71155d5768c5..0fb8242084ac535853fd79316aaa3684b9fd7952 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll @@ -10,8 +10,8 @@ define @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64( @llvm.riscv.vluxei.nxv1i8.nxv1i64( @@ -56,8 +56,8 @@ define @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64( @llvm.riscv.vluxei.nxv2i8.nxv2i64( @@ -102,8 +102,8 @@ define @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64( @llvm.riscv.vluxei.nxv4i8.nxv4i64( @@ -148,8 +148,8 @@ define @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64( @llvm.riscv.vluxei.nxv8i8.nxv8i64( @@ -194,8 +194,8 @@ define @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64( @llvm.riscv.vluxei.nxv1i16.nxv1i64( @@ -240,8 +240,8 @@ define @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64( @llvm.riscv.vluxei.nxv2i16.nxv2i64( @@ -286,8 +286,8 @@ define @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64( @llvm.riscv.vluxei.nxv4i16.nxv4i64( @@ -332,8 +332,8 @@ define @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64( @llvm.riscv.vluxei.nxv8i16.nxv8i64( @@ -378,8 +378,8 @@ define @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64( @llvm.riscv.vluxei.nxv1i32.nxv1i64( @@ -424,8 +424,8 @@ define @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64( @llvm.riscv.vluxei.nxv2i32.nxv2i64( @@ -470,8 +470,8 @@ define @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64( @llvm.riscv.vluxei.nxv4i32.nxv4i64( @@ -516,8 +516,8 @@ define @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64( @llvm.riscv.vluxei.nxv8i32.nxv8i64( @@ -742,8 +742,8 @@ define @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64( @llvm.riscv.vluxei.nxv1f16.nxv1i64( @@ -788,8 +788,8 @@ define @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64( @llvm.riscv.vluxei.nxv2f16.nxv2i64( @@ -834,8 +834,8 @@ define @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64( @llvm.riscv.vluxei.nxv4f16.nxv4i64( @@ -880,8 +880,8 @@ define @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64( @llvm.riscv.vluxei.nxv8f16.nxv8i64( @@ -926,8 +926,8 @@ define @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64( @llvm.riscv.vluxei.nxv1f32.nxv1i64( @@ -972,8 +972,8 @@ define @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64( @llvm.riscv.vluxei.nxv2f32.nxv2i64( @@ -1018,8 +1018,8 @@ define @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64( @llvm.riscv.vluxei.nxv4f32.nxv4i64( @@ -1064,8 +1064,8 @@ define @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64( @llvm.riscv.vluxei.nxv8f32.nxv8i64( @@ -1290,8 +1290,8 @@ define @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32( @llvm.riscv.vluxei.nxv1i8.nxv1i32( @@ -1336,8 +1336,8 @@ define @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32( @llvm.riscv.vluxei.nxv2i8.nxv2i32( @@ -1382,8 +1382,8 @@ define @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32( @llvm.riscv.vluxei.nxv4i8.nxv4i32( @@ -1428,8 +1428,8 @@ define @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32( @llvm.riscv.vluxei.nxv8i8.nxv8i32( @@ -1474,8 +1474,8 @@ define @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32( @llvm.riscv.vluxei.nxv16i8.nxv16i32( @@ -1520,8 +1520,8 @@ define @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32( @llvm.riscv.vluxei.nxv1i16.nxv1i32( @@ -1566,8 +1566,8 @@ define @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32( @llvm.riscv.vluxei.nxv2i16.nxv2i32( @@ -1612,8 +1612,8 @@ define @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32( @llvm.riscv.vluxei.nxv4i16.nxv4i32( @@ -1658,8 +1658,8 @@ define @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32( @llvm.riscv.vluxei.nxv8i16.nxv8i32( @@ -1704,8 +1704,8 @@ define @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32( @llvm.riscv.vluxei.nxv16i16.nxv16i32( @@ -1975,8 +1975,8 @@ define @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32( @llvm.riscv.vluxei.nxv1i64.nxv1i32( @@ -2021,8 +2021,8 @@ define @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32( @llvm.riscv.vluxei.nxv2i64.nxv2i32( @@ -2067,8 +2067,8 @@ define @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32( @llvm.riscv.vluxei.nxv4i64.nxv4i32( @@ -2159,8 +2159,8 @@ define @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32( @llvm.riscv.vluxei.nxv1f16.nxv1i32( @@ -2205,8 +2205,8 @@ define @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32( @llvm.riscv.vluxei.nxv2f16.nxv2i32( @@ -2251,8 +2251,8 @@ define @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32( @llvm.riscv.vluxei.nxv4f16.nxv4i32( @@ -2297,8 +2297,8 @@ define @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32( @llvm.riscv.vluxei.nxv8f16.nxv8i32( @@ -2343,8 +2343,8 @@ define @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32( @llvm.riscv.vluxei.nxv16f16.nxv16i32( @@ -2614,8 +2614,8 @@ define @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32( @llvm.riscv.vluxei.nxv1f64.nxv1i32( @@ -2660,8 +2660,8 @@ define @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32( @llvm.riscv.vluxei.nxv2f64.nxv2i32( @@ -2706,8 +2706,8 @@ define @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32( @llvm.riscv.vluxei.nxv4f64.nxv4i32( @@ -2798,8 +2798,8 @@ define @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16( @llvm.riscv.vluxei.nxv1i8.nxv1i16( @@ -2844,8 +2844,8 @@ define @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16( @llvm.riscv.vluxei.nxv2i8.nxv2i16( @@ -2890,8 +2890,8 @@ define @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16( @llvm.riscv.vluxei.nxv4i8.nxv4i16( @@ -2936,8 +2936,8 @@ define @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16( @llvm.riscv.vluxei.nxv8i8.nxv8i16( @@ -2982,8 +2982,8 @@ define @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16( @llvm.riscv.vluxei.nxv16i8.nxv16i16( @@ -3028,8 +3028,8 @@ define @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16( @llvm.riscv.vluxei.nxv32i8.nxv32i16( @@ -3344,8 +3344,8 @@ define @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16( @llvm.riscv.vluxei.nxv1i32.nxv1i16( @@ -3390,8 +3390,8 @@ define @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16( @llvm.riscv.vluxei.nxv2i32.nxv2i16( @@ -3436,8 +3436,8 @@ define @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16( @llvm.riscv.vluxei.nxv4i32.nxv4i16( @@ -3482,8 +3482,8 @@ define @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16( @llvm.riscv.vluxei.nxv8i32.nxv8i16( @@ -3574,8 +3574,8 @@ define @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16( @llvm.riscv.vluxei.nxv1i64.nxv1i16( @@ -3620,8 +3620,8 @@ define @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16( @llvm.riscv.vluxei.nxv2i64.nxv2i16( @@ -3666,8 +3666,8 @@ define @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16( @llvm.riscv.vluxei.nxv4i64.nxv4i16( @@ -4028,8 +4028,8 @@ define @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16( @llvm.riscv.vluxei.nxv1f32.nxv1i16( @@ -4074,8 +4074,8 @@ define @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16( @llvm.riscv.vluxei.nxv2f32.nxv2i16( @@ -4120,8 +4120,8 @@ define @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16( @llvm.riscv.vluxei.nxv4f32.nxv4i16( @@ -4166,8 +4166,8 @@ define @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16( @llvm.riscv.vluxei.nxv8f32.nxv8i16( @@ -4258,8 +4258,8 @@ define @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16( @llvm.riscv.vluxei.nxv1f64.nxv1i16( @@ -4304,8 +4304,8 @@ define @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16( @llvm.riscv.vluxei.nxv2f64.nxv2i16( @@ -4350,8 +4350,8 @@ define @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16( @llvm.riscv.vluxei.nxv4f64.nxv4i16( @@ -4757,8 +4757,8 @@ define @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8( @llvm.riscv.vluxei.nxv1i16.nxv1i8( @@ -4803,8 +4803,8 @@ define @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8( @llvm.riscv.vluxei.nxv2i16.nxv2i8( @@ -4849,8 +4849,8 @@ define @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8( @llvm.riscv.vluxei.nxv4i16.nxv4i8( @@ -4895,8 +4895,8 @@ define @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8( @llvm.riscv.vluxei.nxv8i16.nxv8i8( @@ -4941,8 +4941,8 @@ define @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8( @llvm.riscv.vluxei.nxv16i16.nxv16i8( @@ -5033,8 +5033,8 @@ define @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8( @llvm.riscv.vluxei.nxv1i32.nxv1i8( @@ -5079,8 +5079,8 @@ define @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8( @llvm.riscv.vluxei.nxv2i32.nxv2i8( @@ -5125,8 +5125,8 @@ define @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8( @llvm.riscv.vluxei.nxv4i32.nxv4i8( @@ -5171,8 +5171,8 @@ define @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8( @llvm.riscv.vluxei.nxv8i32.nxv8i8( @@ -5263,8 +5263,8 @@ define @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8( @llvm.riscv.vluxei.nxv1i64.nxv1i8( @@ -5309,8 +5309,8 @@ define @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8( @llvm.riscv.vluxei.nxv2i64.nxv2i8( @@ -5355,8 +5355,8 @@ define @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8( @llvm.riscv.vluxei.nxv4i64.nxv4i8( @@ -5447,8 +5447,8 @@ define @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8( @llvm.riscv.vluxei.nxv1f16.nxv1i8( @@ -5493,8 +5493,8 @@ define @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8( @llvm.riscv.vluxei.nxv2f16.nxv2i8( @@ -5539,8 +5539,8 @@ define @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8( @llvm.riscv.vluxei.nxv4f16.nxv4i8( @@ -5585,8 +5585,8 @@ define @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8( @llvm.riscv.vluxei.nxv8f16.nxv8i8( @@ -5631,8 +5631,8 @@ define @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8( @llvm.riscv.vluxei.nxv16f16.nxv16i8( @@ -5723,8 +5723,8 @@ define @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8( @llvm.riscv.vluxei.nxv1f32.nxv1i8( @@ -5769,8 +5769,8 @@ define @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8( @llvm.riscv.vluxei.nxv2f32.nxv2i8( @@ -5815,8 +5815,8 @@ define @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8( @llvm.riscv.vluxei.nxv4f32.nxv4i8( @@ -5861,8 +5861,8 @@ define @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8( @llvm.riscv.vluxei.nxv8f32.nxv8i8( @@ -5953,8 +5953,8 @@ define @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8( @llvm.riscv.vluxei.nxv1f64.nxv1i8( @@ -5999,8 +5999,8 @@ define @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8( @llvm.riscv.vluxei.nxv2f64.nxv2i8( @@ -6045,8 +6045,8 @@ define @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8( @llvm.riscv.vluxei.nxv4f64.nxv4i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll index 0ec37535be5c8d44fed72a9ae281e91dcd0e5a32..a04272f3d1a01d2d9c869026ba254ef2fcb57552 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll @@ -10,8 +10,8 @@ define @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64( @llvm.riscv.vluxei.nxv1i8.nxv1i64( @@ -56,8 +56,8 @@ define @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64( @llvm.riscv.vluxei.nxv2i8.nxv2i64( @@ -102,8 +102,8 @@ define @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64( @llvm.riscv.vluxei.nxv4i8.nxv4i64( @@ -148,8 +148,8 @@ define @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64( @llvm.riscv.vluxei.nxv8i8.nxv8i64( @@ -194,8 +194,8 @@ define @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64( @llvm.riscv.vluxei.nxv1i16.nxv1i64( @@ -240,8 +240,8 @@ define @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64( @llvm.riscv.vluxei.nxv2i16.nxv2i64( @@ -286,8 +286,8 @@ define @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64( @llvm.riscv.vluxei.nxv4i16.nxv4i64( @@ -332,8 +332,8 @@ define @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64( @llvm.riscv.vluxei.nxv8i16.nxv8i64( @@ -378,8 +378,8 @@ define @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64( @llvm.riscv.vluxei.nxv1i32.nxv1i64( @@ -424,8 +424,8 @@ define @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64( @llvm.riscv.vluxei.nxv2i32.nxv2i64( @@ -470,8 +470,8 @@ define @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64( @llvm.riscv.vluxei.nxv4i32.nxv4i64( @@ -516,8 +516,8 @@ define @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64( @llvm.riscv.vluxei.nxv8i32.nxv8i64( @@ -742,8 +742,8 @@ define @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64( @llvm.riscv.vluxei.nxv1f16.nxv1i64( @@ -788,8 +788,8 @@ define @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64( @llvm.riscv.vluxei.nxv2f16.nxv2i64( @@ -834,8 +834,8 @@ define @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64( @llvm.riscv.vluxei.nxv4f16.nxv4i64( @@ -880,8 +880,8 @@ define @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64( @llvm.riscv.vluxei.nxv8f16.nxv8i64( @@ -926,8 +926,8 @@ define @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64( @llvm.riscv.vluxei.nxv1f32.nxv1i64( @@ -972,8 +972,8 @@ define @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64( @llvm.riscv.vluxei.nxv2f32.nxv2i64( @@ -1018,8 +1018,8 @@ define @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64( @llvm.riscv.vluxei.nxv4f32.nxv4i64( @@ -1064,8 +1064,8 @@ define @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64( @llvm.riscv.vluxei.nxv8f32.nxv8i64( @@ -1290,8 +1290,8 @@ define @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32( @llvm.riscv.vluxei.nxv1i8.nxv1i32( @@ -1336,8 +1336,8 @@ define @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32( @llvm.riscv.vluxei.nxv2i8.nxv2i32( @@ -1382,8 +1382,8 @@ define @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32( @llvm.riscv.vluxei.nxv4i8.nxv4i32( @@ -1428,8 +1428,8 @@ define @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32( @llvm.riscv.vluxei.nxv8i8.nxv8i32( @@ -1474,8 +1474,8 @@ define @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32( @llvm.riscv.vluxei.nxv16i8.nxv16i32( @@ -1520,8 +1520,8 @@ define @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32( @llvm.riscv.vluxei.nxv1i16.nxv1i32( @@ -1566,8 +1566,8 @@ define @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32( @llvm.riscv.vluxei.nxv2i16.nxv2i32( @@ -1612,8 +1612,8 @@ define @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32( @llvm.riscv.vluxei.nxv4i16.nxv4i32( @@ -1658,8 +1658,8 @@ define @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32( @llvm.riscv.vluxei.nxv8i16.nxv8i32( @@ -1704,8 +1704,8 @@ define @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32( @llvm.riscv.vluxei.nxv16i16.nxv16i32( @@ -1975,8 +1975,8 @@ define @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32( @llvm.riscv.vluxei.nxv1i64.nxv1i32( @@ -2021,8 +2021,8 @@ define @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32( @llvm.riscv.vluxei.nxv2i64.nxv2i32( @@ -2067,8 +2067,8 @@ define @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32( @llvm.riscv.vluxei.nxv4i64.nxv4i32( @@ -2159,8 +2159,8 @@ define @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32( @llvm.riscv.vluxei.nxv1f16.nxv1i32( @@ -2205,8 +2205,8 @@ define @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32( @llvm.riscv.vluxei.nxv2f16.nxv2i32( @@ -2251,8 +2251,8 @@ define @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32( @llvm.riscv.vluxei.nxv4f16.nxv4i32( @@ -2297,8 +2297,8 @@ define @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32( @llvm.riscv.vluxei.nxv8f16.nxv8i32( @@ -2343,8 +2343,8 @@ define @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32( @llvm.riscv.vluxei.nxv16f16.nxv16i32( @@ -2614,8 +2614,8 @@ define @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32( @llvm.riscv.vluxei.nxv1f64.nxv1i32( @@ -2660,8 +2660,8 @@ define @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32( @llvm.riscv.vluxei.nxv2f64.nxv2i32( @@ -2706,8 +2706,8 @@ define @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32( @llvm.riscv.vluxei.nxv4f64.nxv4i32( @@ -2798,8 +2798,8 @@ define @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16( @llvm.riscv.vluxei.nxv1i8.nxv1i16( @@ -2844,8 +2844,8 @@ define @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16( @llvm.riscv.vluxei.nxv2i8.nxv2i16( @@ -2890,8 +2890,8 @@ define @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16( @llvm.riscv.vluxei.nxv4i8.nxv4i16( @@ -2936,8 +2936,8 @@ define @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16( @llvm.riscv.vluxei.nxv8i8.nxv8i16( @@ -2982,8 +2982,8 @@ define @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16( @llvm.riscv.vluxei.nxv16i8.nxv16i16( @@ -3028,8 +3028,8 @@ define @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16( @llvm.riscv.vluxei.nxv32i8.nxv32i16( @@ -3344,8 +3344,8 @@ define @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16( @llvm.riscv.vluxei.nxv1i32.nxv1i16( @@ -3390,8 +3390,8 @@ define @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16( @llvm.riscv.vluxei.nxv2i32.nxv2i16( @@ -3436,8 +3436,8 @@ define @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16( @llvm.riscv.vluxei.nxv4i32.nxv4i16( @@ -3482,8 +3482,8 @@ define @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16( @llvm.riscv.vluxei.nxv8i32.nxv8i16( @@ -3574,8 +3574,8 @@ define @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16( @llvm.riscv.vluxei.nxv1i64.nxv1i16( @@ -3620,8 +3620,8 @@ define @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16( @llvm.riscv.vluxei.nxv2i64.nxv2i16( @@ -3666,8 +3666,8 @@ define @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16( @llvm.riscv.vluxei.nxv4i64.nxv4i16( @@ -4028,8 +4028,8 @@ define @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16( @llvm.riscv.vluxei.nxv1f32.nxv1i16( @@ -4074,8 +4074,8 @@ define @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16( @llvm.riscv.vluxei.nxv2f32.nxv2i16( @@ -4120,8 +4120,8 @@ define @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16( @llvm.riscv.vluxei.nxv4f32.nxv4i16( @@ -4166,8 +4166,8 @@ define @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16( @llvm.riscv.vluxei.nxv8f32.nxv8i16( @@ -4258,8 +4258,8 @@ define @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16( @llvm.riscv.vluxei.nxv1f64.nxv1i16( @@ -4304,8 +4304,8 @@ define @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16( @llvm.riscv.vluxei.nxv2f64.nxv2i16( @@ -4350,8 +4350,8 @@ define @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16( @llvm.riscv.vluxei.nxv4f64.nxv4i16( @@ -4757,8 +4757,8 @@ define @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8( @llvm.riscv.vluxei.nxv1i16.nxv1i8( @@ -4803,8 +4803,8 @@ define @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8( @llvm.riscv.vluxei.nxv2i16.nxv2i8( @@ -4849,8 +4849,8 @@ define @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8( @llvm.riscv.vluxei.nxv4i16.nxv4i8( @@ -4895,8 +4895,8 @@ define @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8( @llvm.riscv.vluxei.nxv8i16.nxv8i8( @@ -4941,8 +4941,8 @@ define @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8( @llvm.riscv.vluxei.nxv16i16.nxv16i8( @@ -5033,8 +5033,8 @@ define @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8( @llvm.riscv.vluxei.nxv1i32.nxv1i8( @@ -5079,8 +5079,8 @@ define @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8( @llvm.riscv.vluxei.nxv2i32.nxv2i8( @@ -5125,8 +5125,8 @@ define @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8( @llvm.riscv.vluxei.nxv4i32.nxv4i8( @@ -5171,8 +5171,8 @@ define @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8( @llvm.riscv.vluxei.nxv8i32.nxv8i8( @@ -5263,8 +5263,8 @@ define @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8( @llvm.riscv.vluxei.nxv1i64.nxv1i8( @@ -5309,8 +5309,8 @@ define @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8( @llvm.riscv.vluxei.nxv2i64.nxv2i8( @@ -5355,8 +5355,8 @@ define @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8( @llvm.riscv.vluxei.nxv4i64.nxv4i8( @@ -5447,8 +5447,8 @@ define @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8( @llvm.riscv.vluxei.nxv1f16.nxv1i8( @@ -5493,8 +5493,8 @@ define @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8( @llvm.riscv.vluxei.nxv2f16.nxv2i8( @@ -5539,8 +5539,8 @@ define @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8( @llvm.riscv.vluxei.nxv4f16.nxv4i8( @@ -5585,8 +5585,8 @@ define @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8( @llvm.riscv.vluxei.nxv8f16.nxv8i8( @@ -5631,8 +5631,8 @@ define @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8( @llvm.riscv.vluxei.nxv16f16.nxv16i8( @@ -5723,8 +5723,8 @@ define @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8( @llvm.riscv.vluxei.nxv1f32.nxv1i8( @@ -5769,8 +5769,8 @@ define @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8( @llvm.riscv.vluxei.nxv2f32.nxv2i8( @@ -5815,8 +5815,8 @@ define @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8( @llvm.riscv.vluxei.nxv4f32.nxv4i8( @@ -5861,8 +5861,8 @@ define @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8( @llvm.riscv.vluxei.nxv8f32.nxv8i8( @@ -5953,8 +5953,8 @@ define @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8( @llvm.riscv.vluxei.nxv1f64.nxv1i8( @@ -5999,8 +5999,8 @@ define @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8( @llvm.riscv.vluxei.nxv2f64.nxv2i8( @@ -6045,8 +6045,8 @@ define @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8( @llvm.riscv.vluxei.nxv4f64.nxv4i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll index dc70f83d8a536cd52adaca25ce1da8c146f07901..0ecbc734de624912b968b019cd4b5a0dc548bff4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll @@ -1533,9 +1533,9 @@ define @intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64( @intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64( @intrinsic_vmacc_vx_nxv2i64_i64_nxv2i64( @intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64( @intrinsic_vmacc_vx_nxv4i64_i64_nxv4i64( @intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64( @intrinsic_vmadc_vx_nxv1i1_nxv1i64_i64( @intrinsic_vmadc_vx_nxv2i1_nxv2i64_i64( @intrinsic_vmadc_vx_nxv4i1_nxv4i64_i64( @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i8_nxv1i8( @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8( @@ -34,8 +34,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i8_nxv2i8( @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8( @@ -57,8 +57,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i8_nxv4i8( @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8( @@ -80,8 +80,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i8_nxv8i8( @llvm.riscv.vmadc.carry.in.nxv8i8.nxv8i8( @@ -103,8 +103,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i8_nxv16i8( ; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmadc.vvm v12, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmadc.carry.in.nxv16i8.nxv16i8( @@ -126,8 +126,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i8_nxv32i8( ; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmadc.vvm v16, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmadc.carry.in.nxv32i8.nxv32i8( @@ -149,8 +149,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv64i1_nxv64i8_nxv64i8( ; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv64i1_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu -; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmadc.vvm v24, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmadc.carry.in.nxv64i8.nxv64i8( @@ -172,8 +172,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i16_nxv1i16( @llvm.riscv.vmadc.carry.in.nxv1i16.nxv1i16( @@ -195,8 +195,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i16_nxv2i16( @llvm.riscv.vmadc.carry.in.nxv2i16.nxv2i16( @@ -218,8 +218,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i16_nxv4i16( @llvm.riscv.vmadc.carry.in.nxv4i16.nxv4i16( @@ -241,8 +241,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i16_nxv8i16( @llvm.riscv.vmadc.carry.in.nxv8i16.nxv8i16( @@ -264,8 +264,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i16_nxv16i1 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmadc.vvm v16, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmadc.carry.in.nxv16i16.nxv16i16( @@ -287,8 +287,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i16_nxv32i1 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmadc.vvm v24, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmadc.carry.in.nxv32i16.nxv32i16( @@ -310,8 +310,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i32_nxv1i32( @llvm.riscv.vmadc.carry.in.nxv1i32.nxv1i32( @@ -333,8 +333,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i32_nxv2i32( @llvm.riscv.vmadc.carry.in.nxv2i32.nxv2i32( @@ -356,8 +356,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i32_nxv4i32( @llvm.riscv.vmadc.carry.in.nxv4i32.nxv4i32( @@ -379,8 +379,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i32_nxv8i32( @llvm.riscv.vmadc.carry.in.nxv8i32.nxv8i32( @@ -402,8 +402,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i32_nxv16i3 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmadc.vvm v24, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmadc.carry.in.nxv16i32.nxv16i32( @@ -425,8 +425,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i64_nxv1i64( @llvm.riscv.vmadc.carry.in.nxv1i64.nxv1i64( @@ -448,8 +448,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i64_nxv2i64( @llvm.riscv.vmadc.carry.in.nxv2i64.nxv2i64( @@ -471,8 +471,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i64_nxv4i64( @llvm.riscv.vmadc.carry.in.nxv4i64.nxv4i64( @@ -494,8 +494,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i64_nxv8i64( @llvm.riscv.vmadc.carry.in.nxv8i64.nxv8i64( @@ -517,8 +517,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i8_i8( @llvm.riscv.vmadc.carry.in.nxv1i8.i8( @@ -540,8 +540,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i8_i8( @llvm.riscv.vmadc.carry.in.nxv2i8.i8( @@ -563,8 +563,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i8_i8( @llvm.riscv.vmadc.carry.in.nxv4i8.i8( @@ -586,8 +586,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i8_i8( @llvm.riscv.vmadc.carry.in.nxv8i8.i8( @@ -609,8 +609,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i8_i8( @llvm.riscv.vmadc.carry.in.nxv16i8.i8( @@ -632,8 +632,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i8_i8( @llvm.riscv.vmadc.carry.in.nxv32i8.i8( @@ -655,8 +655,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv64i1_nxv64i8_i8( @llvm.riscv.vmadc.carry.in.nxv64i8.i8( @@ -678,8 +678,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i16_i16( @llvm.riscv.vmadc.carry.in.nxv1i16.i16( @@ -701,8 +701,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i16_i16( @llvm.riscv.vmadc.carry.in.nxv2i16.i16( @@ -724,8 +724,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i16_i16( @llvm.riscv.vmadc.carry.in.nxv4i16.i16( @@ -747,8 +747,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i16_i16( @llvm.riscv.vmadc.carry.in.nxv8i16.i16( @@ -770,8 +770,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i16_i16( @llvm.riscv.vmadc.carry.in.nxv16i16.i16( @@ -793,8 +793,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i16_i16( @llvm.riscv.vmadc.carry.in.nxv32i16.i16( @@ -816,8 +816,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i32_i32( @llvm.riscv.vmadc.carry.in.nxv1i32.i32( @@ -839,8 +839,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i32_i32( @llvm.riscv.vmadc.carry.in.nxv2i32.i32( @@ -862,8 +862,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i32_i32( @llvm.riscv.vmadc.carry.in.nxv4i32.i32( @@ -885,8 +885,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i32_i32( @llvm.riscv.vmadc.carry.in.nxv8i32.i32( @@ -908,8 +908,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i32_i32( @llvm.riscv.vmadc.carry.in.nxv16i32.i32( @@ -935,9 +935,9 @@ define @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i64_i64( @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i64_i64( @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i64_i64( @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i64_i64( @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i8_i8( @llvm.riscv.vmadc.carry.in.nxv1i8.i8( @@ -1058,8 +1058,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i8_i8( @llvm.riscv.vmadc.carry.in.nxv2i8.i8( @@ -1075,8 +1075,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i8_i8( @llvm.riscv.vmadc.carry.in.nxv4i8.i8( @@ -1092,8 +1092,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i8_i8( @llvm.riscv.vmadc.carry.in.nxv8i8.i8( @@ -1109,8 +1109,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i8_i8( @llvm.riscv.vmadc.carry.in.nxv16i8.i8( @@ -1126,8 +1126,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i8_i8( @llvm.riscv.vmadc.carry.in.nxv32i8.i8( @@ -1143,8 +1143,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv64i1_nxv64i8_i8( @llvm.riscv.vmadc.carry.in.nxv64i8.i8( @@ -1160,8 +1160,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i16_i16( @llvm.riscv.vmadc.carry.in.nxv1i16.i16( @@ -1177,8 +1177,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i16_i16( @llvm.riscv.vmadc.carry.in.nxv2i16.i16( @@ -1194,8 +1194,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i16_i16( @llvm.riscv.vmadc.carry.in.nxv4i16.i16( @@ -1211,8 +1211,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i16_i16( @llvm.riscv.vmadc.carry.in.nxv8i16.i16( @@ -1228,8 +1228,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i16_i16( @llvm.riscv.vmadc.carry.in.nxv16i16.i16( @@ -1245,8 +1245,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i16_i16( @llvm.riscv.vmadc.carry.in.nxv32i16.i16( @@ -1262,8 +1262,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i32_i32( @llvm.riscv.vmadc.carry.in.nxv1i32.i32( @@ -1279,8 +1279,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i32_i32( @llvm.riscv.vmadc.carry.in.nxv2i32.i32( @@ -1296,8 +1296,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i32_i32( @llvm.riscv.vmadc.carry.in.nxv4i32.i32( @@ -1313,8 +1313,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i32_i32( @llvm.riscv.vmadc.carry.in.nxv8i32.i32( @@ -1330,8 +1330,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i32_i32( @llvm.riscv.vmadc.carry.in.nxv16i32.i32( @@ -1347,8 +1347,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i64_i64( @llvm.riscv.vmadc.carry.in.nxv1i64.i64( @@ -1364,8 +1364,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i64_i64( @llvm.riscv.vmadc.carry.in.nxv2i64.i64( @@ -1381,8 +1381,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i64_i64( @llvm.riscv.vmadc.carry.in.nxv4i64.i64( @@ -1398,8 +1398,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i64_i64( @llvm.riscv.vmadc.carry.in.nxv8i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll index b1aa8103c950fb4adac893dd61593045137eb912..a29588d107d935149fa66672f8a61c6da3494e08 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll @@ -11,8 +11,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i8_nxv1i8( @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8( @@ -34,8 +34,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i8_nxv2i8( @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8( @@ -57,8 +57,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i8_nxv4i8( @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8( @@ -80,8 +80,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i8_nxv8i8( @llvm.riscv.vmadc.carry.in.nxv8i8.nxv8i8( @@ -103,8 +103,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i8_nxv16i8( ; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmadc.vvm v12, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmadc.carry.in.nxv16i8.nxv16i8( @@ -126,8 +126,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i8_nxv32i8( ; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmadc.vvm v16, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmadc.carry.in.nxv32i8.nxv32i8( @@ -149,8 +149,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv64i1_nxv64i8_nxv64i8( ; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv64i1_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu -; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmadc.vvm v24, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmadc.carry.in.nxv64i8.nxv64i8( @@ -172,8 +172,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i16_nxv1i16( @llvm.riscv.vmadc.carry.in.nxv1i16.nxv1i16( @@ -195,8 +195,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i16_nxv2i16( @llvm.riscv.vmadc.carry.in.nxv2i16.nxv2i16( @@ -218,8 +218,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i16_nxv4i16( @llvm.riscv.vmadc.carry.in.nxv4i16.nxv4i16( @@ -241,8 +241,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i16_nxv8i16( @llvm.riscv.vmadc.carry.in.nxv8i16.nxv8i16( @@ -264,8 +264,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i16_nxv16i1 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmadc.vvm v16, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmadc.carry.in.nxv16i16.nxv16i16( @@ -287,8 +287,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i16_nxv32i1 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmadc.vvm v24, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmadc.carry.in.nxv32i16.nxv32i16( @@ -310,8 +310,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i32_nxv1i32( @llvm.riscv.vmadc.carry.in.nxv1i32.nxv1i32( @@ -333,8 +333,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i32_nxv2i32( @llvm.riscv.vmadc.carry.in.nxv2i32.nxv2i32( @@ -356,8 +356,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i32_nxv4i32( @llvm.riscv.vmadc.carry.in.nxv4i32.nxv4i32( @@ -379,8 +379,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i32_nxv8i32( @llvm.riscv.vmadc.carry.in.nxv8i32.nxv8i32( @@ -402,8 +402,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i32_nxv16i3 ; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmadc.vvm v24, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmadc.carry.in.nxv16i32.nxv16i32( @@ -425,8 +425,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i64_nxv1i64( @llvm.riscv.vmadc.carry.in.nxv1i64.nxv1i64( @@ -448,8 +448,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i64_nxv2i64( @llvm.riscv.vmadc.carry.in.nxv2i64.nxv2i64( @@ -471,8 +471,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i64_nxv4i64( @llvm.riscv.vmadc.carry.in.nxv4i64.nxv4i64( @@ -494,8 +494,8 @@ define @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i64_nxv8i64( @llvm.riscv.vmadc.carry.in.nxv8i64.nxv8i64( @@ -517,8 +517,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i8_i8( @llvm.riscv.vmadc.carry.in.nxv1i8.i8( @@ -540,8 +540,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i8_i8( @llvm.riscv.vmadc.carry.in.nxv2i8.i8( @@ -563,8 +563,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i8_i8( @llvm.riscv.vmadc.carry.in.nxv4i8.i8( @@ -586,8 +586,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i8_i8( @llvm.riscv.vmadc.carry.in.nxv8i8.i8( @@ -609,8 +609,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i8_i8( @llvm.riscv.vmadc.carry.in.nxv16i8.i8( @@ -632,8 +632,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i8_i8( @llvm.riscv.vmadc.carry.in.nxv32i8.i8( @@ -655,8 +655,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv64i1_nxv64i8_i8( @llvm.riscv.vmadc.carry.in.nxv64i8.i8( @@ -678,8 +678,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i16_i16( @llvm.riscv.vmadc.carry.in.nxv1i16.i16( @@ -701,8 +701,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i16_i16( @llvm.riscv.vmadc.carry.in.nxv2i16.i16( @@ -724,8 +724,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i16_i16( @llvm.riscv.vmadc.carry.in.nxv4i16.i16( @@ -747,8 +747,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i16_i16( @llvm.riscv.vmadc.carry.in.nxv8i16.i16( @@ -770,8 +770,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i16_i16( @llvm.riscv.vmadc.carry.in.nxv16i16.i16( @@ -793,8 +793,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i16_i16( @llvm.riscv.vmadc.carry.in.nxv32i16.i16( @@ -816,8 +816,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i32_i32( @llvm.riscv.vmadc.carry.in.nxv1i32.i32( @@ -839,8 +839,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i32_i32( @llvm.riscv.vmadc.carry.in.nxv2i32.i32( @@ -862,8 +862,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i32_i32( @llvm.riscv.vmadc.carry.in.nxv4i32.i32( @@ -885,8 +885,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i32_i32( @llvm.riscv.vmadc.carry.in.nxv8i32.i32( @@ -908,8 +908,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i32_i32( @llvm.riscv.vmadc.carry.in.nxv16i32.i32( @@ -931,8 +931,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i64_i64( @llvm.riscv.vmadc.carry.in.nxv1i64.i64( @@ -954,8 +954,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i64_i64( @llvm.riscv.vmadc.carry.in.nxv2i64.i64( @@ -977,8 +977,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i64_i64( @llvm.riscv.vmadc.carry.in.nxv4i64.i64( @@ -1000,8 +1000,8 @@ define @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i64_i64( @llvm.riscv.vmadc.carry.in.nxv8i64.i64( @@ -1017,8 +1017,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i8_i8( @llvm.riscv.vmadc.carry.in.nxv1i8.i8( @@ -1034,8 +1034,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i8_i8( @llvm.riscv.vmadc.carry.in.nxv2i8.i8( @@ -1051,8 +1051,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i8_i8( @llvm.riscv.vmadc.carry.in.nxv4i8.i8( @@ -1068,8 +1068,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i8_i8( @llvm.riscv.vmadc.carry.in.nxv8i8.i8( @@ -1085,8 +1085,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i8_i8( @llvm.riscv.vmadc.carry.in.nxv16i8.i8( @@ -1102,8 +1102,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i8_i8( @llvm.riscv.vmadc.carry.in.nxv32i8.i8( @@ -1119,8 +1119,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv64i1_nxv64i8_i8( @llvm.riscv.vmadc.carry.in.nxv64i8.i8( @@ -1136,8 +1136,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i16_i16( @llvm.riscv.vmadc.carry.in.nxv1i16.i16( @@ -1153,8 +1153,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i16_i16( @llvm.riscv.vmadc.carry.in.nxv2i16.i16( @@ -1170,8 +1170,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i16_i16( @llvm.riscv.vmadc.carry.in.nxv4i16.i16( @@ -1187,8 +1187,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i16_i16( @llvm.riscv.vmadc.carry.in.nxv8i16.i16( @@ -1204,8 +1204,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i16_i16( @llvm.riscv.vmadc.carry.in.nxv16i16.i16( @@ -1221,8 +1221,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i16_i16( @llvm.riscv.vmadc.carry.in.nxv32i16.i16( @@ -1238,8 +1238,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i32_i32( @llvm.riscv.vmadc.carry.in.nxv1i32.i32( @@ -1255,8 +1255,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i32_i32( @llvm.riscv.vmadc.carry.in.nxv2i32.i32( @@ -1272,8 +1272,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i32_i32( @llvm.riscv.vmadc.carry.in.nxv4i32.i32( @@ -1289,8 +1289,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i32_i32( @llvm.riscv.vmadc.carry.in.nxv8i32.i32( @@ -1306,8 +1306,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i32_i32( @llvm.riscv.vmadc.carry.in.nxv16i32.i32( @@ -1323,8 +1323,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i64_i64( @llvm.riscv.vmadc.carry.in.nxv1i64.i64( @@ -1340,8 +1340,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i64_i64( @llvm.riscv.vmadc.carry.in.nxv2i64.i64( @@ -1357,8 +1357,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i64_i64( @llvm.riscv.vmadc.carry.in.nxv4i64.i64( @@ -1374,8 +1374,8 @@ define @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i64_i64( @llvm.riscv.vmadc.carry.in.nxv8i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll index b972e55f2c253f5f59e7a5149e1b5437463b746d..8deb23a234760543cea6e86e75127a28a661a540 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll @@ -1533,9 +1533,9 @@ define @intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64( @intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64( @intrinsic_vmadd_vx_nxv2i64_i64_nxv2i64( @intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64( @intrinsic_vmadd_vx_nxv4i64_i64_nxv4i64( @intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64( @vmadd_vx_nxv1i64( %va, @vmadd_vx_nxv2i64( %va, @vmadd_vx_nxv4i64( %va, @intrinsic_vmax_vx_nxv1i64_nxv1i64_i64( @intrinsic_vmax_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vmax_vx_nxv2i64_nxv2i64_i64( @intrinsic_vmax_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vmax_vx_nxv4i64_nxv4i64_i64( @intrinsic_vmax_mask_vx_nxv4i64_nxv4i64_i64( @vmax_vx_nxv1i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmax.vv v8, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -750,8 +750,8 @@ define @vmax_vx_nxv2i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmax.vv v8, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -795,8 +795,8 @@ define @vmax_vx_nxv4i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmax.vv v8, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll index 1b67d501e27f23f5d071535a83dd73d0f2ec18bb..3a187f536932357315332fd260265013ff7091cd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vmaxu_vx_nxv1i64_nxv1i64_i64( @intrinsic_vmaxu_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vmaxu_vx_nxv2i64_nxv2i64_i64( @intrinsic_vmaxu_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vmaxu_vx_nxv4i64_nxv4i64_i64( @intrinsic_vmaxu_mask_vx_nxv4i64_nxv4i64_i64( @vmax_vx_nxv1i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmaxu.vv v8, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -750,8 +750,8 @@ define @vmax_vx_nxv2i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmaxu.vv v8, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -795,8 +795,8 @@ define @vmax_vx_nxv4i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmaxu.vv v8, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmaxu.vv v8, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll index 5e5743466739a6df00fca9b5f0990ab9eafee8af..f0e0328907136afb315ac6d4c7d69c39b3d6114f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll @@ -895,8 +895,8 @@ define @intrinsic_vmerge_vxm_nxv1i64_nxv1i64_i64( @intrinsic_vmerge_vxm_nxv2i64_nxv2i64_i64( @intrinsic_vmerge_vxm_nxv4i64_nxv4i64_i64( @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16( @llvm.riscv.vmfeq.nxv1f16( @@ -84,11 +84,11 @@ define @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16( @llvm.riscv.vmfeq.nxv2f16( @@ -136,11 +136,11 @@ define @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16( @llvm.riscv.vmfeq.nxv4f16( @@ -188,11 +188,11 @@ define @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16( @llvm.riscv.vmfeq.nxv8f16( @@ -240,11 +240,11 @@ define @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16( @llvm.riscv.vmfeq.nxv16f16( @@ -292,11 +292,11 @@ define @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32( @llvm.riscv.vmfeq.nxv1f32( @@ -344,11 +344,11 @@ define @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32( @llvm.riscv.vmfeq.nxv2f32( @@ -396,11 +396,11 @@ define @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32( @llvm.riscv.vmfeq.nxv4f32( @@ -448,11 +448,11 @@ define @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32( @llvm.riscv.vmfeq.nxv8f32( @@ -500,11 +500,11 @@ define @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64( @llvm.riscv.vmfeq.nxv1f64( @@ -552,11 +552,11 @@ define @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64( @llvm.riscv.vmfeq.nxv2f64( @@ -604,11 +604,11 @@ define @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64( @llvm.riscv.vmfeq.nxv4f64( @@ -656,12 +656,12 @@ declare @llvm.riscv.vmfeq.mask.nxv1f16.f16( define @intrinsic_vmfeq_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv1f16.f16( @@ -705,12 +705,12 @@ declare @llvm.riscv.vmfeq.mask.nxv2f16.f16( define @intrinsic_vmfeq_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv2f16.f16( @@ -754,12 +754,12 @@ declare @llvm.riscv.vmfeq.mask.nxv4f16.f16( define @intrinsic_vmfeq_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv4f16.f16( @@ -803,12 +803,12 @@ declare @llvm.riscv.vmfeq.mask.nxv8f16.f16( define @intrinsic_vmfeq_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv8f16.f16( @@ -852,12 +852,12 @@ declare @llvm.riscv.vmfeq.mask.nxv16f16.f16( define @intrinsic_vmfeq_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv16f16.f16( @@ -901,12 +901,12 @@ declare @llvm.riscv.vmfeq.mask.nxv1f32.f32( define @intrinsic_vmfeq_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv1f32.f32( @@ -950,12 +950,12 @@ declare @llvm.riscv.vmfeq.mask.nxv2f32.f32( define @intrinsic_vmfeq_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv2f32.f32( @@ -999,12 +999,12 @@ declare @llvm.riscv.vmfeq.mask.nxv4f32.f32( define @intrinsic_vmfeq_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv4f32.f32( @@ -1048,12 +1048,12 @@ declare @llvm.riscv.vmfeq.mask.nxv8f32.f32( define @intrinsic_vmfeq_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv8f32.f32( @@ -1105,11 +1105,11 @@ define @intrinsic_vmfeq_mask_vf_nxv1f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1162,11 +1162,11 @@ define @intrinsic_vmfeq_mask_vf_nxv2f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1219,11 +1219,11 @@ define @intrinsic_vmfeq_mask_vf_nxv4f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll index 4e41827b0cf748db552a767d2164abe7eb23d049..7d4b0376ca435edcdcf877ae23042ce2b88d4f02 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll @@ -32,11 +32,11 @@ define @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16( @llvm.riscv.vmfeq.nxv1f16( @@ -84,11 +84,11 @@ define @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16( @llvm.riscv.vmfeq.nxv2f16( @@ -136,11 +136,11 @@ define @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16( @llvm.riscv.vmfeq.nxv4f16( @@ -188,11 +188,11 @@ define @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16( @llvm.riscv.vmfeq.nxv8f16( @@ -240,11 +240,11 @@ define @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16( @llvm.riscv.vmfeq.nxv16f16( @@ -292,11 +292,11 @@ define @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32( @llvm.riscv.vmfeq.nxv1f32( @@ -344,11 +344,11 @@ define @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32( @llvm.riscv.vmfeq.nxv2f32( @@ -396,11 +396,11 @@ define @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32( @llvm.riscv.vmfeq.nxv4f32( @@ -448,11 +448,11 @@ define @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32( @llvm.riscv.vmfeq.nxv8f32( @@ -500,11 +500,11 @@ define @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64( @llvm.riscv.vmfeq.nxv1f64( @@ -552,11 +552,11 @@ define @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64( @llvm.riscv.vmfeq.nxv2f64( @@ -604,11 +604,11 @@ define @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64( @llvm.riscv.vmfeq.nxv4f64( @@ -656,12 +656,12 @@ declare @llvm.riscv.vmfeq.mask.nxv1f16.f16( define @intrinsic_vmfeq_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv1f16.f16( @@ -705,12 +705,12 @@ declare @llvm.riscv.vmfeq.mask.nxv2f16.f16( define @intrinsic_vmfeq_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv2f16.f16( @@ -754,12 +754,12 @@ declare @llvm.riscv.vmfeq.mask.nxv4f16.f16( define @intrinsic_vmfeq_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv4f16.f16( @@ -803,12 +803,12 @@ declare @llvm.riscv.vmfeq.mask.nxv8f16.f16( define @intrinsic_vmfeq_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv8f16.f16( @@ -852,12 +852,12 @@ declare @llvm.riscv.vmfeq.mask.nxv16f16.f16( define @intrinsic_vmfeq_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv16f16.f16( @@ -901,12 +901,12 @@ declare @llvm.riscv.vmfeq.mask.nxv1f32.f32( define @intrinsic_vmfeq_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv1f32.f32( @@ -950,12 +950,12 @@ declare @llvm.riscv.vmfeq.mask.nxv2f32.f32( define @intrinsic_vmfeq_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv2f32.f32( @@ -999,12 +999,12 @@ declare @llvm.riscv.vmfeq.mask.nxv4f32.f32( define @intrinsic_vmfeq_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv4f32.f32( @@ -1048,12 +1048,12 @@ declare @llvm.riscv.vmfeq.mask.nxv8f32.f32( define @intrinsic_vmfeq_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv8f32.f32( @@ -1097,12 +1097,12 @@ declare @llvm.riscv.vmfeq.mask.nxv1f64.f64( define @intrinsic_vmfeq_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv1f64.f64( @@ -1146,12 +1146,12 @@ declare @llvm.riscv.vmfeq.mask.nxv2f64.f64( define @intrinsic_vmfeq_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv2f64.f64( @@ -1195,12 +1195,12 @@ declare @llvm.riscv.vmfeq.mask.nxv4f64.f64( define @intrinsic_vmfeq_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfeq.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfeq.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll index af62253486687481c106ddedee137b73286eab38..33a61ba4584f760726b3bca8dad14c28fc095550 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll @@ -32,11 +32,11 @@ define @intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16( @llvm.riscv.vmfge.nxv1f16( @@ -84,11 +84,11 @@ define @intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16( @llvm.riscv.vmfge.nxv2f16( @@ -136,11 +136,11 @@ define @intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16( @llvm.riscv.vmfge.nxv4f16( @@ -188,11 +188,11 @@ define @intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16( @llvm.riscv.vmfge.nxv8f16( @@ -240,11 +240,11 @@ define @intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16( @llvm.riscv.vmfge.nxv16f16( @@ -292,11 +292,11 @@ define @intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32( @llvm.riscv.vmfge.nxv1f32( @@ -344,11 +344,11 @@ define @intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32( @llvm.riscv.vmfge.nxv2f32( @@ -396,11 +396,11 @@ define @intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32( @llvm.riscv.vmfge.nxv4f32( @@ -448,11 +448,11 @@ define @intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32( @llvm.riscv.vmfge.nxv8f32( @@ -500,11 +500,11 @@ define @intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64( @llvm.riscv.vmfge.nxv1f64( @@ -552,11 +552,11 @@ define @intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64( @llvm.riscv.vmfge.nxv2f64( @@ -604,11 +604,11 @@ define @intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64( @llvm.riscv.vmfge.nxv4f64( @@ -656,12 +656,12 @@ declare @llvm.riscv.vmfge.mask.nxv1f16.f16( define @intrinsic_vmfge_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv1f16.f16( @@ -705,12 +705,12 @@ declare @llvm.riscv.vmfge.mask.nxv2f16.f16( define @intrinsic_vmfge_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv2f16.f16( @@ -754,12 +754,12 @@ declare @llvm.riscv.vmfge.mask.nxv4f16.f16( define @intrinsic_vmfge_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv4f16.f16( @@ -803,12 +803,12 @@ declare @llvm.riscv.vmfge.mask.nxv8f16.f16( define @intrinsic_vmfge_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv8f16.f16( @@ -852,12 +852,12 @@ declare @llvm.riscv.vmfge.mask.nxv16f16.f16( define @intrinsic_vmfge_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv16f16.f16( @@ -901,12 +901,12 @@ declare @llvm.riscv.vmfge.mask.nxv1f32.f32( define @intrinsic_vmfge_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv1f32.f32( @@ -950,12 +950,12 @@ declare @llvm.riscv.vmfge.mask.nxv2f32.f32( define @intrinsic_vmfge_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv2f32.f32( @@ -999,12 +999,12 @@ declare @llvm.riscv.vmfge.mask.nxv4f32.f32( define @intrinsic_vmfge_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv4f32.f32( @@ -1048,12 +1048,12 @@ declare @llvm.riscv.vmfge.mask.nxv8f32.f32( define @intrinsic_vmfge_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv8f32.f32( @@ -1105,11 +1105,11 @@ define @intrinsic_vmfge_mask_vf_nxv1f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1162,11 +1162,11 @@ define @intrinsic_vmfge_mask_vf_nxv2f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1219,11 +1219,11 @@ define @intrinsic_vmfge_mask_vf_nxv4f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll index 30a8fcdaf3b4b8efd42f32ab7b2c2c6c64c06968..29b0f001818aa4cb3fc35082dfa4528054c71ddd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll @@ -32,11 +32,11 @@ define @intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16( @llvm.riscv.vmfge.nxv1f16( @@ -84,11 +84,11 @@ define @intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16( @llvm.riscv.vmfge.nxv2f16( @@ -136,11 +136,11 @@ define @intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16( @llvm.riscv.vmfge.nxv4f16( @@ -188,11 +188,11 @@ define @intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16( @llvm.riscv.vmfge.nxv8f16( @@ -240,11 +240,11 @@ define @intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16( @llvm.riscv.vmfge.nxv16f16( @@ -292,11 +292,11 @@ define @intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32( @llvm.riscv.vmfge.nxv1f32( @@ -344,11 +344,11 @@ define @intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32( @llvm.riscv.vmfge.nxv2f32( @@ -396,11 +396,11 @@ define @intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32( @llvm.riscv.vmfge.nxv4f32( @@ -448,11 +448,11 @@ define @intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32( @llvm.riscv.vmfge.nxv8f32( @@ -500,11 +500,11 @@ define @intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64( @llvm.riscv.vmfge.nxv1f64( @@ -552,11 +552,11 @@ define @intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64( @llvm.riscv.vmfge.nxv2f64( @@ -604,11 +604,11 @@ define @intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64( @llvm.riscv.vmfge.nxv4f64( @@ -656,12 +656,12 @@ declare @llvm.riscv.vmfge.mask.nxv1f16.f16( define @intrinsic_vmfge_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv1f16.f16( @@ -705,12 +705,12 @@ declare @llvm.riscv.vmfge.mask.nxv2f16.f16( define @intrinsic_vmfge_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv2f16.f16( @@ -754,12 +754,12 @@ declare @llvm.riscv.vmfge.mask.nxv4f16.f16( define @intrinsic_vmfge_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv4f16.f16( @@ -803,12 +803,12 @@ declare @llvm.riscv.vmfge.mask.nxv8f16.f16( define @intrinsic_vmfge_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv8f16.f16( @@ -852,12 +852,12 @@ declare @llvm.riscv.vmfge.mask.nxv16f16.f16( define @intrinsic_vmfge_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv16f16.f16( @@ -901,12 +901,12 @@ declare @llvm.riscv.vmfge.mask.nxv1f32.f32( define @intrinsic_vmfge_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv1f32.f32( @@ -950,12 +950,12 @@ declare @llvm.riscv.vmfge.mask.nxv2f32.f32( define @intrinsic_vmfge_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv2f32.f32( @@ -999,12 +999,12 @@ declare @llvm.riscv.vmfge.mask.nxv4f32.f32( define @intrinsic_vmfge_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv4f32.f32( @@ -1048,12 +1048,12 @@ declare @llvm.riscv.vmfge.mask.nxv8f32.f32( define @intrinsic_vmfge_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv8f32.f32( @@ -1097,12 +1097,12 @@ declare @llvm.riscv.vmfge.mask.nxv1f64.f64( define @intrinsic_vmfge_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv1f64.f64( @@ -1146,12 +1146,12 @@ declare @llvm.riscv.vmfge.mask.nxv2f64.f64( define @intrinsic_vmfge_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv2f64.f64( @@ -1195,12 +1195,12 @@ declare @llvm.riscv.vmfge.mask.nxv4f64.f64( define @intrinsic_vmfge_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfge.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfge.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll index a606f4434afeed1b878d72bc6ce5ff79824a0882..5e6d3aeb1580a6789a47836f274cbb1d3fd38d18 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll @@ -32,11 +32,11 @@ define @intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16( @llvm.riscv.vmfgt.nxv1f16( @@ -84,11 +84,11 @@ define @intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16( @llvm.riscv.vmfgt.nxv2f16( @@ -136,11 +136,11 @@ define @intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16( @llvm.riscv.vmfgt.nxv4f16( @@ -188,11 +188,11 @@ define @intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16( @llvm.riscv.vmfgt.nxv8f16( @@ -240,11 +240,11 @@ define @intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16( @llvm.riscv.vmfgt.nxv16f16( @@ -292,11 +292,11 @@ define @intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32( @llvm.riscv.vmfgt.nxv1f32( @@ -344,11 +344,11 @@ define @intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32( @llvm.riscv.vmfgt.nxv2f32( @@ -396,11 +396,11 @@ define @intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32( @llvm.riscv.vmfgt.nxv4f32( @@ -448,11 +448,11 @@ define @intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32( @llvm.riscv.vmfgt.nxv8f32( @@ -500,11 +500,11 @@ define @intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64( @llvm.riscv.vmfgt.nxv1f64( @@ -552,11 +552,11 @@ define @intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64( @llvm.riscv.vmfgt.nxv2f64( @@ -604,11 +604,11 @@ define @intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64( @llvm.riscv.vmfgt.nxv4f64( @@ -656,12 +656,12 @@ declare @llvm.riscv.vmfgt.mask.nxv1f16.f16( define @intrinsic_vmfgt_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv1f16.f16( @@ -705,12 +705,12 @@ declare @llvm.riscv.vmfgt.mask.nxv2f16.f16( define @intrinsic_vmfgt_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv2f16.f16( @@ -754,12 +754,12 @@ declare @llvm.riscv.vmfgt.mask.nxv4f16.f16( define @intrinsic_vmfgt_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv4f16.f16( @@ -803,12 +803,12 @@ declare @llvm.riscv.vmfgt.mask.nxv8f16.f16( define @intrinsic_vmfgt_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv8f16.f16( @@ -852,12 +852,12 @@ declare @llvm.riscv.vmfgt.mask.nxv16f16.f16( define @intrinsic_vmfgt_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv16f16.f16( @@ -901,12 +901,12 @@ declare @llvm.riscv.vmfgt.mask.nxv1f32.f32( define @intrinsic_vmfgt_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv1f32.f32( @@ -950,12 +950,12 @@ declare @llvm.riscv.vmfgt.mask.nxv2f32.f32( define @intrinsic_vmfgt_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv2f32.f32( @@ -999,12 +999,12 @@ declare @llvm.riscv.vmfgt.mask.nxv4f32.f32( define @intrinsic_vmfgt_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv4f32.f32( @@ -1048,12 +1048,12 @@ declare @llvm.riscv.vmfgt.mask.nxv8f32.f32( define @intrinsic_vmfgt_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv8f32.f32( @@ -1105,11 +1105,11 @@ define @intrinsic_vmfgt_mask_vf_nxv1f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1162,11 +1162,11 @@ define @intrinsic_vmfgt_mask_vf_nxv2f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1219,11 +1219,11 @@ define @intrinsic_vmfgt_mask_vf_nxv4f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll index f1e0442253370c449e84e9fb8a24847336f8f5b5..4f109c570641615f45615d1ccef8516f54262c52 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll @@ -32,11 +32,11 @@ define @intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16( @llvm.riscv.vmfgt.nxv1f16( @@ -84,11 +84,11 @@ define @intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16( @llvm.riscv.vmfgt.nxv2f16( @@ -136,11 +136,11 @@ define @intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16( @llvm.riscv.vmfgt.nxv4f16( @@ -188,11 +188,11 @@ define @intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16( @llvm.riscv.vmfgt.nxv8f16( @@ -240,11 +240,11 @@ define @intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16( @llvm.riscv.vmfgt.nxv16f16( @@ -292,11 +292,11 @@ define @intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32( @llvm.riscv.vmfgt.nxv1f32( @@ -344,11 +344,11 @@ define @intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32( @llvm.riscv.vmfgt.nxv2f32( @@ -396,11 +396,11 @@ define @intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32( @llvm.riscv.vmfgt.nxv4f32( @@ -448,11 +448,11 @@ define @intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32( @llvm.riscv.vmfgt.nxv8f32( @@ -500,11 +500,11 @@ define @intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64( @llvm.riscv.vmfgt.nxv1f64( @@ -552,11 +552,11 @@ define @intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64( @llvm.riscv.vmfgt.nxv2f64( @@ -604,11 +604,11 @@ define @intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64( @llvm.riscv.vmfgt.nxv4f64( @@ -656,12 +656,12 @@ declare @llvm.riscv.vmfgt.mask.nxv1f16.f16( define @intrinsic_vmfgt_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv1f16.f16( @@ -705,12 +705,12 @@ declare @llvm.riscv.vmfgt.mask.nxv2f16.f16( define @intrinsic_vmfgt_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv2f16.f16( @@ -754,12 +754,12 @@ declare @llvm.riscv.vmfgt.mask.nxv4f16.f16( define @intrinsic_vmfgt_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv4f16.f16( @@ -803,12 +803,12 @@ declare @llvm.riscv.vmfgt.mask.nxv8f16.f16( define @intrinsic_vmfgt_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv8f16.f16( @@ -852,12 +852,12 @@ declare @llvm.riscv.vmfgt.mask.nxv16f16.f16( define @intrinsic_vmfgt_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv16f16.f16( @@ -901,12 +901,12 @@ declare @llvm.riscv.vmfgt.mask.nxv1f32.f32( define @intrinsic_vmfgt_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv1f32.f32( @@ -950,12 +950,12 @@ declare @llvm.riscv.vmfgt.mask.nxv2f32.f32( define @intrinsic_vmfgt_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv2f32.f32( @@ -999,12 +999,12 @@ declare @llvm.riscv.vmfgt.mask.nxv4f32.f32( define @intrinsic_vmfgt_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv4f32.f32( @@ -1048,12 +1048,12 @@ declare @llvm.riscv.vmfgt.mask.nxv8f32.f32( define @intrinsic_vmfgt_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv8f32.f32( @@ -1097,12 +1097,12 @@ declare @llvm.riscv.vmfgt.mask.nxv1f64.f64( define @intrinsic_vmfgt_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv1f64.f64( @@ -1146,12 +1146,12 @@ declare @llvm.riscv.vmfgt.mask.nxv2f64.f64( define @intrinsic_vmfgt_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv2f64.f64( @@ -1195,12 +1195,12 @@ declare @llvm.riscv.vmfgt.mask.nxv4f64.f64( define @intrinsic_vmfgt_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfgt.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfgt.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll index 941bb73e826425b93b6e3d9758daaf4197c7ad51..eac282bdf05c928e85a1d77900f62fdfbb493349 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll @@ -32,11 +32,11 @@ define @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16( @llvm.riscv.vmfle.nxv1f16( @@ -84,11 +84,11 @@ define @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16( @llvm.riscv.vmfle.nxv2f16( @@ -136,11 +136,11 @@ define @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16( @llvm.riscv.vmfle.nxv4f16( @@ -188,11 +188,11 @@ define @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16( @llvm.riscv.vmfle.nxv8f16( @@ -240,11 +240,11 @@ define @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16( @llvm.riscv.vmfle.nxv16f16( @@ -292,11 +292,11 @@ define @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32( @llvm.riscv.vmfle.nxv1f32( @@ -344,11 +344,11 @@ define @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32( @llvm.riscv.vmfle.nxv2f32( @@ -396,11 +396,11 @@ define @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32( @llvm.riscv.vmfle.nxv4f32( @@ -448,11 +448,11 @@ define @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32( @llvm.riscv.vmfle.nxv8f32( @@ -500,11 +500,11 @@ define @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64( @llvm.riscv.vmfle.nxv1f64( @@ -552,11 +552,11 @@ define @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64( @llvm.riscv.vmfle.nxv2f64( @@ -604,11 +604,11 @@ define @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64( @llvm.riscv.vmfle.nxv4f64( @@ -656,12 +656,12 @@ declare @llvm.riscv.vmfle.mask.nxv1f16.f16( define @intrinsic_vmfle_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv1f16.f16( @@ -705,12 +705,12 @@ declare @llvm.riscv.vmfle.mask.nxv2f16.f16( define @intrinsic_vmfle_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv2f16.f16( @@ -754,12 +754,12 @@ declare @llvm.riscv.vmfle.mask.nxv4f16.f16( define @intrinsic_vmfle_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv4f16.f16( @@ -803,12 +803,12 @@ declare @llvm.riscv.vmfle.mask.nxv8f16.f16( define @intrinsic_vmfle_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv8f16.f16( @@ -852,12 +852,12 @@ declare @llvm.riscv.vmfle.mask.nxv16f16.f16( define @intrinsic_vmfle_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv16f16.f16( @@ -901,12 +901,12 @@ declare @llvm.riscv.vmfle.mask.nxv1f32.f32( define @intrinsic_vmfle_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv1f32.f32( @@ -950,12 +950,12 @@ declare @llvm.riscv.vmfle.mask.nxv2f32.f32( define @intrinsic_vmfle_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv2f32.f32( @@ -999,12 +999,12 @@ declare @llvm.riscv.vmfle.mask.nxv4f32.f32( define @intrinsic_vmfle_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv4f32.f32( @@ -1048,12 +1048,12 @@ declare @llvm.riscv.vmfle.mask.nxv8f32.f32( define @intrinsic_vmfle_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv8f32.f32( @@ -1105,11 +1105,11 @@ define @intrinsic_vmfle_mask_vf_nxv1f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1162,11 +1162,11 @@ define @intrinsic_vmfle_mask_vf_nxv2f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1219,11 +1219,11 @@ define @intrinsic_vmfle_mask_vf_nxv4f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll index 8246b9c8cc47b0485fade32870a8c4430f763d2a..94a40203cfed28e6f0d7c8808475e4729165a14e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll @@ -32,11 +32,11 @@ define @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16( @llvm.riscv.vmfle.nxv1f16( @@ -84,11 +84,11 @@ define @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16( @llvm.riscv.vmfle.nxv2f16( @@ -136,11 +136,11 @@ define @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16( @llvm.riscv.vmfle.nxv4f16( @@ -188,11 +188,11 @@ define @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16( @llvm.riscv.vmfle.nxv8f16( @@ -240,11 +240,11 @@ define @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16( @llvm.riscv.vmfle.nxv16f16( @@ -292,11 +292,11 @@ define @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32( @llvm.riscv.vmfle.nxv1f32( @@ -344,11 +344,11 @@ define @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32( @llvm.riscv.vmfle.nxv2f32( @@ -396,11 +396,11 @@ define @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32( @llvm.riscv.vmfle.nxv4f32( @@ -448,11 +448,11 @@ define @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32( @llvm.riscv.vmfle.nxv8f32( @@ -500,11 +500,11 @@ define @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64( @llvm.riscv.vmfle.nxv1f64( @@ -552,11 +552,11 @@ define @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64( @llvm.riscv.vmfle.nxv2f64( @@ -604,11 +604,11 @@ define @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64( @llvm.riscv.vmfle.nxv4f64( @@ -656,12 +656,12 @@ declare @llvm.riscv.vmfle.mask.nxv1f16.f16( define @intrinsic_vmfle_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv1f16.f16( @@ -705,12 +705,12 @@ declare @llvm.riscv.vmfle.mask.nxv2f16.f16( define @intrinsic_vmfle_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv2f16.f16( @@ -754,12 +754,12 @@ declare @llvm.riscv.vmfle.mask.nxv4f16.f16( define @intrinsic_vmfle_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv4f16.f16( @@ -803,12 +803,12 @@ declare @llvm.riscv.vmfle.mask.nxv8f16.f16( define @intrinsic_vmfle_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv8f16.f16( @@ -852,12 +852,12 @@ declare @llvm.riscv.vmfle.mask.nxv16f16.f16( define @intrinsic_vmfle_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv16f16.f16( @@ -901,12 +901,12 @@ declare @llvm.riscv.vmfle.mask.nxv1f32.f32( define @intrinsic_vmfle_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv1f32.f32( @@ -950,12 +950,12 @@ declare @llvm.riscv.vmfle.mask.nxv2f32.f32( define @intrinsic_vmfle_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv2f32.f32( @@ -999,12 +999,12 @@ declare @llvm.riscv.vmfle.mask.nxv4f32.f32( define @intrinsic_vmfle_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv4f32.f32( @@ -1048,12 +1048,12 @@ declare @llvm.riscv.vmfle.mask.nxv8f32.f32( define @intrinsic_vmfle_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv8f32.f32( @@ -1097,12 +1097,12 @@ declare @llvm.riscv.vmfle.mask.nxv1f64.f64( define @intrinsic_vmfle_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv1f64.f64( @@ -1146,12 +1146,12 @@ declare @llvm.riscv.vmfle.mask.nxv2f64.f64( define @intrinsic_vmfle_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv2f64.f64( @@ -1195,12 +1195,12 @@ declare @llvm.riscv.vmfle.mask.nxv4f64.f64( define @intrinsic_vmfle_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll index 1c32ffa4689515a5015953f02cf34051a1246f94..c944d632f7929566264b73d848da80133fa6d439 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll @@ -32,11 +32,11 @@ define @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16( @llvm.riscv.vmflt.nxv1f16( @@ -84,11 +84,11 @@ define @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16( @llvm.riscv.vmflt.nxv2f16( @@ -136,11 +136,11 @@ define @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16( @llvm.riscv.vmflt.nxv4f16( @@ -188,11 +188,11 @@ define @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16( @llvm.riscv.vmflt.nxv8f16( @@ -240,11 +240,11 @@ define @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16( @llvm.riscv.vmflt.nxv16f16( @@ -292,11 +292,11 @@ define @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32( @llvm.riscv.vmflt.nxv1f32( @@ -344,11 +344,11 @@ define @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32( @llvm.riscv.vmflt.nxv2f32( @@ -396,11 +396,11 @@ define @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32( @llvm.riscv.vmflt.nxv4f32( @@ -448,11 +448,11 @@ define @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32( @llvm.riscv.vmflt.nxv8f32( @@ -500,11 +500,11 @@ define @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64( @llvm.riscv.vmflt.nxv1f64( @@ -552,11 +552,11 @@ define @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64( @llvm.riscv.vmflt.nxv2f64( @@ -604,11 +604,11 @@ define @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64( @llvm.riscv.vmflt.nxv4f64( @@ -656,12 +656,12 @@ declare @llvm.riscv.vmflt.mask.nxv1f16.f16( define @intrinsic_vmflt_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv1f16.f16( @@ -705,12 +705,12 @@ declare @llvm.riscv.vmflt.mask.nxv2f16.f16( define @intrinsic_vmflt_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv2f16.f16( @@ -754,12 +754,12 @@ declare @llvm.riscv.vmflt.mask.nxv4f16.f16( define @intrinsic_vmflt_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv4f16.f16( @@ -803,12 +803,12 @@ declare @llvm.riscv.vmflt.mask.nxv8f16.f16( define @intrinsic_vmflt_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv8f16.f16( @@ -852,12 +852,12 @@ declare @llvm.riscv.vmflt.mask.nxv16f16.f16( define @intrinsic_vmflt_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv16f16.f16( @@ -901,12 +901,12 @@ declare @llvm.riscv.vmflt.mask.nxv1f32.f32( define @intrinsic_vmflt_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv1f32.f32( @@ -950,12 +950,12 @@ declare @llvm.riscv.vmflt.mask.nxv2f32.f32( define @intrinsic_vmflt_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv2f32.f32( @@ -999,12 +999,12 @@ declare @llvm.riscv.vmflt.mask.nxv4f32.f32( define @intrinsic_vmflt_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv4f32.f32( @@ -1048,12 +1048,12 @@ declare @llvm.riscv.vmflt.mask.nxv8f32.f32( define @intrinsic_vmflt_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv8f32.f32( @@ -1105,11 +1105,11 @@ define @intrinsic_vmflt_mask_vf_nxv1f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1162,11 +1162,11 @@ define @intrinsic_vmflt_mask_vf_nxv2f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1219,11 +1219,11 @@ define @intrinsic_vmflt_mask_vf_nxv4f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll index e03cd16851c48aad3264e40ed1e557e5df38e23a..2db18bb32862ae737075f876abf5e5aff08faf20 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll @@ -32,11 +32,11 @@ define @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16( @llvm.riscv.vmflt.nxv1f16( @@ -84,11 +84,11 @@ define @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16( @llvm.riscv.vmflt.nxv2f16( @@ -136,11 +136,11 @@ define @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16( @llvm.riscv.vmflt.nxv4f16( @@ -188,11 +188,11 @@ define @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16( @llvm.riscv.vmflt.nxv8f16( @@ -240,11 +240,11 @@ define @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16( @llvm.riscv.vmflt.nxv16f16( @@ -292,11 +292,11 @@ define @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32( @llvm.riscv.vmflt.nxv1f32( @@ -344,11 +344,11 @@ define @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32( @llvm.riscv.vmflt.nxv2f32( @@ -396,11 +396,11 @@ define @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32( @llvm.riscv.vmflt.nxv4f32( @@ -448,11 +448,11 @@ define @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32( @llvm.riscv.vmflt.nxv8f32( @@ -500,11 +500,11 @@ define @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64( @llvm.riscv.vmflt.nxv1f64( @@ -552,11 +552,11 @@ define @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64( @llvm.riscv.vmflt.nxv2f64( @@ -604,11 +604,11 @@ define @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64( @llvm.riscv.vmflt.nxv4f64( @@ -656,12 +656,12 @@ declare @llvm.riscv.vmflt.mask.nxv1f16.f16( define @intrinsic_vmflt_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv1f16.f16( @@ -705,12 +705,12 @@ declare @llvm.riscv.vmflt.mask.nxv2f16.f16( define @intrinsic_vmflt_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv2f16.f16( @@ -754,12 +754,12 @@ declare @llvm.riscv.vmflt.mask.nxv4f16.f16( define @intrinsic_vmflt_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv4f16.f16( @@ -803,12 +803,12 @@ declare @llvm.riscv.vmflt.mask.nxv8f16.f16( define @intrinsic_vmflt_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv8f16.f16( @@ -852,12 +852,12 @@ declare @llvm.riscv.vmflt.mask.nxv16f16.f16( define @intrinsic_vmflt_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv16f16.f16( @@ -901,12 +901,12 @@ declare @llvm.riscv.vmflt.mask.nxv1f32.f32( define @intrinsic_vmflt_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv1f32.f32( @@ -950,12 +950,12 @@ declare @llvm.riscv.vmflt.mask.nxv2f32.f32( define @intrinsic_vmflt_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv2f32.f32( @@ -999,12 +999,12 @@ declare @llvm.riscv.vmflt.mask.nxv4f32.f32( define @intrinsic_vmflt_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv4f32.f32( @@ -1048,12 +1048,12 @@ declare @llvm.riscv.vmflt.mask.nxv8f32.f32( define @intrinsic_vmflt_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv8f32.f32( @@ -1097,12 +1097,12 @@ declare @llvm.riscv.vmflt.mask.nxv1f64.f64( define @intrinsic_vmflt_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv1f64.f64( @@ -1146,12 +1146,12 @@ declare @llvm.riscv.vmflt.mask.nxv2f64.f64( define @intrinsic_vmflt_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv2f64.f64( @@ -1195,12 +1195,12 @@ declare @llvm.riscv.vmflt.mask.nxv4f64.f64( define @intrinsic_vmflt_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmflt.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll index fbb7973ae1a74905b971feecd457fb8806179980..efabe7512c8b20694327ee1c97d740d5fb1407ba 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll @@ -32,11 +32,11 @@ define @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16( @llvm.riscv.vmfne.nxv1f16( @@ -84,11 +84,11 @@ define @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16( @llvm.riscv.vmfne.nxv2f16( @@ -136,11 +136,11 @@ define @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16( @llvm.riscv.vmfne.nxv4f16( @@ -188,11 +188,11 @@ define @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16( @llvm.riscv.vmfne.nxv8f16( @@ -240,11 +240,11 @@ define @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16( @llvm.riscv.vmfne.nxv16f16( @@ -292,11 +292,11 @@ define @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32( @llvm.riscv.vmfne.nxv1f32( @@ -344,11 +344,11 @@ define @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32( @llvm.riscv.vmfne.nxv2f32( @@ -396,11 +396,11 @@ define @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32( @llvm.riscv.vmfne.nxv4f32( @@ -448,11 +448,11 @@ define @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32( @llvm.riscv.vmfne.nxv8f32( @@ -500,11 +500,11 @@ define @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64( @llvm.riscv.vmfne.nxv1f64( @@ -552,11 +552,11 @@ define @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64( @llvm.riscv.vmfne.nxv2f64( @@ -604,11 +604,11 @@ define @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64( @llvm.riscv.vmfne.nxv4f64( @@ -656,12 +656,12 @@ declare @llvm.riscv.vmfne.mask.nxv1f16.f16( define @intrinsic_vmfne_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv1f16.f16( @@ -705,12 +705,12 @@ declare @llvm.riscv.vmfne.mask.nxv2f16.f16( define @intrinsic_vmfne_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv2f16.f16( @@ -754,12 +754,12 @@ declare @llvm.riscv.vmfne.mask.nxv4f16.f16( define @intrinsic_vmfne_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv4f16.f16( @@ -803,12 +803,12 @@ declare @llvm.riscv.vmfne.mask.nxv8f16.f16( define @intrinsic_vmfne_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv8f16.f16( @@ -852,12 +852,12 @@ declare @llvm.riscv.vmfne.mask.nxv16f16.f16( define @intrinsic_vmfne_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv16f16.f16( @@ -901,12 +901,12 @@ declare @llvm.riscv.vmfne.mask.nxv1f32.f32( define @intrinsic_vmfne_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv1f32.f32( @@ -950,12 +950,12 @@ declare @llvm.riscv.vmfne.mask.nxv2f32.f32( define @intrinsic_vmfne_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv2f32.f32( @@ -999,12 +999,12 @@ declare @llvm.riscv.vmfne.mask.nxv4f32.f32( define @intrinsic_vmfne_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv4f32.f32( @@ -1048,12 +1048,12 @@ declare @llvm.riscv.vmfne.mask.nxv8f32.f32( define @intrinsic_vmfne_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv8f32.f32( @@ -1105,11 +1105,11 @@ define @intrinsic_vmfne_mask_vf_nxv1f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1162,11 +1162,11 @@ define @intrinsic_vmfne_mask_vf_nxv2f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1219,11 +1219,11 @@ define @intrinsic_vmfne_mask_vf_nxv4f64_f64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll index c61dc9099fe0cf5ff0e793e944a5f7ca63dfe73e..45f5b765a8ed115c9343c57746ada42b50613841 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll @@ -32,11 +32,11 @@ define @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16( @llvm.riscv.vmfne.nxv1f16( @@ -84,11 +84,11 @@ define @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16( @llvm.riscv.vmfne.nxv2f16( @@ -136,11 +136,11 @@ define @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16( @llvm.riscv.vmfne.nxv4f16( @@ -188,11 +188,11 @@ define @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16( @llvm.riscv.vmfne.nxv8f16( @@ -240,11 +240,11 @@ define @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16( @llvm.riscv.vmfne.nxv16f16( @@ -292,11 +292,11 @@ define @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32( @llvm.riscv.vmfne.nxv1f32( @@ -344,11 +344,11 @@ define @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32( @llvm.riscv.vmfne.nxv2f32( @@ -396,11 +396,11 @@ define @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32( @llvm.riscv.vmfne.nxv4f32( @@ -448,11 +448,11 @@ define @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32( @llvm.riscv.vmfne.nxv8f32( @@ -500,11 +500,11 @@ define @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64( @llvm.riscv.vmfne.nxv1f64( @@ -552,11 +552,11 @@ define @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64( @llvm.riscv.vmfne.nxv2f64( @@ -604,11 +604,11 @@ define @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64( @llvm.riscv.vmfne.nxv4f64( @@ -656,12 +656,12 @@ declare @llvm.riscv.vmfne.mask.nxv1f16.f16( define @intrinsic_vmfne_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv1f16.f16( @@ -705,12 +705,12 @@ declare @llvm.riscv.vmfne.mask.nxv2f16.f16( define @intrinsic_vmfne_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv2f16.f16( @@ -754,12 +754,12 @@ declare @llvm.riscv.vmfne.mask.nxv4f16.f16( define @intrinsic_vmfne_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv4f16.f16( @@ -803,12 +803,12 @@ declare @llvm.riscv.vmfne.mask.nxv8f16.f16( define @intrinsic_vmfne_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv8f16.f16( @@ -852,12 +852,12 @@ declare @llvm.riscv.vmfne.mask.nxv16f16.f16( define @intrinsic_vmfne_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv16f16.f16( @@ -901,12 +901,12 @@ declare @llvm.riscv.vmfne.mask.nxv1f32.f32( define @intrinsic_vmfne_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv1f32.f32( @@ -950,12 +950,12 @@ declare @llvm.riscv.vmfne.mask.nxv2f32.f32( define @intrinsic_vmfne_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv2f32.f32( @@ -999,12 +999,12 @@ declare @llvm.riscv.vmfne.mask.nxv4f32.f32( define @intrinsic_vmfne_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv4f32.f32( @@ -1048,12 +1048,12 @@ declare @llvm.riscv.vmfne.mask.nxv8f32.f32( define @intrinsic_vmfne_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv8f32.f32( @@ -1097,12 +1097,12 @@ declare @llvm.riscv.vmfne.mask.nxv1f64.f64( define @intrinsic_vmfne_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv1f64.f64( @@ -1146,12 +1146,12 @@ declare @llvm.riscv.vmfne.mask.nxv2f64.f64( define @intrinsic_vmfne_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv2f64.f64( @@ -1195,12 +1195,12 @@ declare @llvm.riscv.vmfne.mask.nxv4f64.f64( define @intrinsic_vmfne_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfne.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll index ef5426949edd57051754a799afc9fad244538f9c..992c67262ff41e7cc2338c21285ac8c15d0fed3b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vmin_vx_nxv1i64_nxv1i64_i64( @intrinsic_vmin_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vmin_vx_nxv2i64_nxv2i64_i64( @intrinsic_vmin_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vmin_vx_nxv4i64_nxv4i64_i64( @intrinsic_vmin_mask_vx_nxv4i64_nxv4i64_i64( @vmin_vx_nxv1i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmin.vv v8, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -750,8 +750,8 @@ define @vmin_vx_nxv2i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmin.vv v8, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmin.vv v8, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -795,8 +795,8 @@ define @vmin_vx_nxv4i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmin.vv v8, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmin.vv v8, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll index 4ad1709a5082136eb6d2b4f8d31f8cca0f71990f..7da939e7b99c08cb1fe8e20827be68cbdcdb8576 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vminu_vx_nxv1i64_nxv1i64_i64( @intrinsic_vminu_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vminu_vx_nxv2i64_nxv2i64_i64( @intrinsic_vminu_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vminu_vx_nxv4i64_nxv4i64_i64( @intrinsic_vminu_mask_vx_nxv4i64_nxv4i64_i64( @vmin_vx_nxv1i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vminu.vv v8, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -750,8 +750,8 @@ define @vmin_vx_nxv2i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vminu.vv v8, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vminu.vv v8, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -795,8 +795,8 @@ define @vmin_vx_nxv4i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vminu.vv v8, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vminu.vv v8, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll index a341a2cd50a5b5560713eabc8d4a4b1eee9a6046..1ca8c1f0fe2bd679e124f1ddec97961c8b983c1b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll @@ -814,8 +814,8 @@ define @intrinsic_vmsbc_vx_nxv1i1_nxv1i64_i64( @intrinsic_vmsbc_vx_nxv2i1_nxv2i64_i64( @intrinsic_vmsbc_vx_nxv4i1_nxv4i64_i64( @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i8_nxv1i8( @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8( @@ -34,8 +34,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i8_nxv2i8( @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8( @@ -57,8 +57,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i8_nxv4i8( @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8( @@ -80,8 +80,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i8_nxv8i8( @llvm.riscv.vmsbc.borrow.in.nxv8i8.nxv8i8( @@ -103,8 +103,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i8_nxv16i8 ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i8.nxv16i8( @@ -126,8 +126,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i8_nxv32i8 ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv32i8.nxv32i8( @@ -149,8 +149,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv64i1_nxv64i8_nxv64i8 ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv64i1_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv64i8.nxv64i8( @@ -172,8 +172,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i16_nxv1i16(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i16.nxv1i16( @@ -195,8 +195,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i16_nxv2i16(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i16.nxv2i16( @@ -218,8 +218,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i16_nxv4i16(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i16.nxv4i16( @@ -241,8 +241,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i16_nxv8i16(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i16.nxv8i16( @@ -264,8 +264,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i16_nxv16i ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i16.nxv16i16( @@ -287,8 +287,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i16_nxv32i ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv32i16.nxv32i16( @@ -310,8 +310,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i32_nxv1i32(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i32.nxv1i32( @@ -333,8 +333,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i32_nxv2i32(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i32.nxv2i32( @@ -356,8 +356,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i32_nxv4i32(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i32.nxv4i32( @@ -379,8 +379,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i32_nxv8i32(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i32.nxv8i32( @@ -402,8 +402,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i32_nxv16i ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i32.nxv16i32( @@ -425,8 +425,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i64_nxv1i64(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i64.nxv1i64( @@ -448,8 +448,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i64_nxv2i64(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i64.nxv2i64( @@ -471,8 +471,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i64_nxv4i64(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i64.nxv4i64( @@ -494,8 +494,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i64_nxv8i64(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i64.nxv8i64( @@ -517,8 +517,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i8_i8( @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8( @@ -540,8 +540,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i8_i8( @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8( @@ -563,8 +563,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i8_i8( @llvm.riscv.vmsbc.borrow.in.nxv4i8.i8( @@ -586,8 +586,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i8_i8( @llvm.riscv.vmsbc.borrow.in.nxv8i8.i8( @@ -609,8 +609,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i8_i8( @llvm.riscv.vmsbc.borrow.in.nxv16i8.i8( @@ -632,8 +632,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i8_i8( @llvm.riscv.vmsbc.borrow.in.nxv32i8.i8( @@ -655,8 +655,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv64i1_nxv64i8_i8( @llvm.riscv.vmsbc.borrow.in.nxv64i8.i8( @@ -678,8 +678,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i16_i16( @llvm.riscv.vmsbc.borrow.in.nxv1i16.i16( @@ -701,8 +701,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i16_i16( @llvm.riscv.vmsbc.borrow.in.nxv2i16.i16( @@ -724,8 +724,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i16_i16( @llvm.riscv.vmsbc.borrow.in.nxv4i16.i16( @@ -747,8 +747,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i16_i16( @llvm.riscv.vmsbc.borrow.in.nxv8i16.i16( @@ -770,8 +770,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i16_i16( @llvm.riscv.vmsbc.borrow.in.nxv16i16.i16( @@ -793,8 +793,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i16_i16( @llvm.riscv.vmsbc.borrow.in.nxv32i16.i16( @@ -816,8 +816,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i32_i32( @llvm.riscv.vmsbc.borrow.in.nxv1i32.i32( @@ -839,8 +839,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i32_i32( @llvm.riscv.vmsbc.borrow.in.nxv2i32.i32( @@ -862,8 +862,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i32_i32( @llvm.riscv.vmsbc.borrow.in.nxv4i32.i32( @@ -885,8 +885,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i32_i32( @llvm.riscv.vmsbc.borrow.in.nxv8i32.i32( @@ -908,8 +908,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i32_i32( @llvm.riscv.vmsbc.borrow.in.nxv16i32.i32( @@ -935,9 +935,9 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i64_i64( @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i64_i64( @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i64_i64( @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i64_i64( @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i8_nxv1i8( @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8( @@ -34,8 +34,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i8_nxv2i8( @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8( @@ -57,8 +57,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i8_nxv4i8( @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8( @@ -80,8 +80,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i8_nxv8i8( @llvm.riscv.vmsbc.borrow.in.nxv8i8.nxv8i8( @@ -103,8 +103,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i8_nxv16i8 ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i8.nxv16i8( @@ -126,8 +126,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i8_nxv32i8 ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv32i8.nxv32i8( @@ -149,8 +149,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv64i1_nxv64i8_nxv64i8 ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv64i1_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv64i8.nxv64i8( @@ -172,8 +172,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i16_nxv1i16(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i16.nxv1i16( @@ -195,8 +195,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i16_nxv2i16(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i16.nxv2i16( @@ -218,8 +218,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i16_nxv4i16(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i16.nxv4i16( @@ -241,8 +241,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i16_nxv8i16(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i16.nxv8i16( @@ -264,8 +264,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i16_nxv16i ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i16.nxv16i16( @@ -287,8 +287,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i16_nxv32i ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv32i16.nxv32i16( @@ -310,8 +310,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i32_nxv1i32(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i32.nxv1i32( @@ -333,8 +333,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i32_nxv2i32(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i32.nxv2i32( @@ -356,8 +356,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i32_nxv4i32(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i32.nxv4i32( @@ -379,8 +379,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i32_nxv8i32(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i32.nxv8i32( @@ -402,8 +402,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i32_nxv16i ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i32.nxv16i32( @@ -425,8 +425,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i64_nxv1i64(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v10, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i64.nxv1i64( @@ -448,8 +448,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i64_nxv2i64(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v12, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i64.nxv2i64( @@ -471,8 +471,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i64_nxv4i64(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v16, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i64.nxv4i64( @@ -494,8 +494,8 @@ define @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i64_nxv8i64(< ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbc.vvm v24, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i64.nxv8i64( @@ -517,8 +517,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i8_i8( @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8( @@ -540,8 +540,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i8_i8( @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8( @@ -563,8 +563,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i8_i8( @llvm.riscv.vmsbc.borrow.in.nxv4i8.i8( @@ -586,8 +586,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i8_i8( @llvm.riscv.vmsbc.borrow.in.nxv8i8.i8( @@ -609,8 +609,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i8_i8( @llvm.riscv.vmsbc.borrow.in.nxv16i8.i8( @@ -632,8 +632,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i8_i8( @llvm.riscv.vmsbc.borrow.in.nxv32i8.i8( @@ -655,8 +655,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv64i1_nxv64i8_i8( @llvm.riscv.vmsbc.borrow.in.nxv64i8.i8( @@ -678,8 +678,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i16_i16( @llvm.riscv.vmsbc.borrow.in.nxv1i16.i16( @@ -701,8 +701,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i16_i16( @llvm.riscv.vmsbc.borrow.in.nxv2i16.i16( @@ -724,8 +724,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i16_i16( @llvm.riscv.vmsbc.borrow.in.nxv4i16.i16( @@ -747,8 +747,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i16_i16( @llvm.riscv.vmsbc.borrow.in.nxv8i16.i16( @@ -770,8 +770,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i16_i16( @llvm.riscv.vmsbc.borrow.in.nxv16i16.i16( @@ -793,8 +793,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i16_i16( @llvm.riscv.vmsbc.borrow.in.nxv32i16.i16( @@ -816,8 +816,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i32_i32( @llvm.riscv.vmsbc.borrow.in.nxv1i32.i32( @@ -839,8 +839,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i32_i32( @llvm.riscv.vmsbc.borrow.in.nxv2i32.i32( @@ -862,8 +862,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i32_i32( @llvm.riscv.vmsbc.borrow.in.nxv4i32.i32( @@ -885,8 +885,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i32_i32( @llvm.riscv.vmsbc.borrow.in.nxv8i32.i32( @@ -908,8 +908,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i32_i32( @llvm.riscv.vmsbc.borrow.in.nxv16i32.i32( @@ -931,8 +931,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i64_i64( @llvm.riscv.vmsbc.borrow.in.nxv1i64.i64( @@ -954,8 +954,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i64_i64( @llvm.riscv.vmsbc.borrow.in.nxv2i64.i64( @@ -977,8 +977,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i64_i64( @llvm.riscv.vmsbc.borrow.in.nxv4i64.i64( @@ -1000,8 +1000,8 @@ define @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i64_i64( @llvm.riscv.vmsbc.borrow.in.nxv8i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll index 5861898efed5b120cdd19c138833dd7a698d9a6b..ea87ba36f74353325cc2f5b97aa443343d16f7e8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vmsbf_m_nxv1i1( %0, i32 %1) ; CHECK-LABEL: intrinsic_vmsbf_m_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmsbf.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.nxv1i1( @@ -28,11 +28,11 @@ declare @llvm.riscv.vmsbf.mask.nxv1i1( define @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsbf.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.mask.nxv1i1( @@ -51,8 +51,8 @@ define @intrinsic_vmsbf_m_nxv2i1( %0, i32 %1) ; CHECK-LABEL: intrinsic_vmsbf_m_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmsbf.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.nxv2i1( @@ -70,11 +70,11 @@ declare @llvm.riscv.vmsbf.mask.nxv2i1( define @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsbf.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.mask.nxv2i1( @@ -93,8 +93,8 @@ define @intrinsic_vmsbf_m_nxv4i1( %0, i32 %1) ; CHECK-LABEL: intrinsic_vmsbf_m_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmsbf.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.nxv4i1( @@ -112,11 +112,11 @@ declare @llvm.riscv.vmsbf.mask.nxv4i1( define @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsbf.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.mask.nxv4i1( @@ -135,8 +135,8 @@ define @intrinsic_vmsbf_m_nxv8i1( %0, i32 %1) ; CHECK-LABEL: intrinsic_vmsbf_m_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmsbf.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.nxv8i1( @@ -154,11 +154,11 @@ declare @llvm.riscv.vmsbf.mask.nxv8i1( define @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsbf.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.mask.nxv8i1( @@ -177,8 +177,8 @@ define @intrinsic_vmsbf_m_nxv16i1( %0, i32 ; CHECK-LABEL: intrinsic_vmsbf_m_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmsbf.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.nxv16i1( @@ -196,11 +196,11 @@ declare @llvm.riscv.vmsbf.mask.nxv16i1( define @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsbf.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.mask.nxv16i1( @@ -219,8 +219,8 @@ define @intrinsic_vmsbf_m_nxv32i1( %0, i32 ; CHECK-LABEL: intrinsic_vmsbf_m_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmsbf.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.nxv32i1( @@ -238,11 +238,11 @@ declare @llvm.riscv.vmsbf.mask.nxv32i1( define @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsbf.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.mask.nxv32i1( @@ -261,8 +261,8 @@ define @intrinsic_vmsbf_m_nxv64i1( %0, i32 ; CHECK-LABEL: intrinsic_vmsbf_m_nxv64i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu -; CHECK-NEXT: vmsbf.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.nxv64i1( @@ -280,11 +280,11 @@ declare @llvm.riscv.vmsbf.mask.nxv64i1( define @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsbf.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.mask.nxv64i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll index e8916bfbe2de315104d7cf918a404d78ccd29abd..a00ae9072256930963a4aad76731bf6347a4e8ac 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vmsbf_m_nxv1i1( %0, i64 %1) ; CHECK-LABEL: intrinsic_vmsbf_m_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmsbf.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.nxv1i1( @@ -28,11 +28,11 @@ declare @llvm.riscv.vmsbf.mask.nxv1i1( define @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsbf.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.mask.nxv1i1( @@ -51,8 +51,8 @@ define @intrinsic_vmsbf_m_nxv2i1( %0, i64 %1) ; CHECK-LABEL: intrinsic_vmsbf_m_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmsbf.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.nxv2i1( @@ -70,11 +70,11 @@ declare @llvm.riscv.vmsbf.mask.nxv2i1( define @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsbf.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.mask.nxv2i1( @@ -93,8 +93,8 @@ define @intrinsic_vmsbf_m_nxv4i1( %0, i64 %1) ; CHECK-LABEL: intrinsic_vmsbf_m_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmsbf.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.nxv4i1( @@ -112,11 +112,11 @@ declare @llvm.riscv.vmsbf.mask.nxv4i1( define @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsbf.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.mask.nxv4i1( @@ -135,8 +135,8 @@ define @intrinsic_vmsbf_m_nxv8i1( %0, i64 %1) ; CHECK-LABEL: intrinsic_vmsbf_m_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmsbf.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.nxv8i1( @@ -154,11 +154,11 @@ declare @llvm.riscv.vmsbf.mask.nxv8i1( define @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsbf.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.mask.nxv8i1( @@ -177,8 +177,8 @@ define @intrinsic_vmsbf_m_nxv16i1( %0, i64 ; CHECK-LABEL: intrinsic_vmsbf_m_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmsbf.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.nxv16i1( @@ -196,11 +196,11 @@ declare @llvm.riscv.vmsbf.mask.nxv16i1( define @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsbf.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.mask.nxv16i1( @@ -219,8 +219,8 @@ define @intrinsic_vmsbf_m_nxv32i1( %0, i64 ; CHECK-LABEL: intrinsic_vmsbf_m_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmsbf.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.nxv32i1( @@ -238,11 +238,11 @@ declare @llvm.riscv.vmsbf.mask.nxv32i1( define @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsbf.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.mask.nxv32i1( @@ -261,8 +261,8 @@ define @intrinsic_vmsbf_m_nxv64i1( %0, i64 ; CHECK-LABEL: intrinsic_vmsbf_m_nxv64i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu -; CHECK-NEXT: vmsbf.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.nxv64i1( @@ -280,11 +280,11 @@ declare @llvm.riscv.vmsbf.mask.nxv64i1( define @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsbf.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsbf.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsbf.mask.nxv64i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll index 40ff8d96022e4c904199c2abf5b3191e76de374e..db3b68f43674e5f017c59169afda822ea958da10 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll @@ -32,11 +32,11 @@ define @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmseq.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmseq.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmseq.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmseq.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmseq.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmseq.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmseq.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmseq.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmseq.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmseq.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmseq.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmseq.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmseq.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmseq.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmseq.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmseq.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmseq.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmseq.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmseq.mask.nxv1i8.i8( define @intrinsic_vmseq_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmseq.mask.nxv2i8.i8( define @intrinsic_vmseq_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmseq.mask.nxv4i8.i8( define @intrinsic_vmseq_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmseq.mask.nxv8i8.i8( define @intrinsic_vmseq_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmseq.mask.nxv16i8.i8( define @intrinsic_vmseq_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmseq.mask.nxv32i8.i8( define @intrinsic_vmseq_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmseq.mask.nxv1i16.i16( define @intrinsic_vmseq_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmseq.mask.nxv2i16.i16( define @intrinsic_vmseq_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmseq.mask.nxv4i16.i16( define @intrinsic_vmseq_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmseq.mask.nxv8i16.i16( define @intrinsic_vmseq_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmseq.mask.nxv16i16.i16( define @intrinsic_vmseq_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmseq.mask.nxv1i32.i32( define @intrinsic_vmseq_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmseq.mask.nxv2i32.i32( define @intrinsic_vmseq_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmseq.mask.nxv4i32.i32( define @intrinsic_vmseq_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmseq.mask.nxv8i32.i32( define @intrinsic_vmseq_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv8i32.i32( @@ -1655,8 +1655,8 @@ define @intrinsic_vmseq_vx_nxv1i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmseq.vv v0, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1683,11 +1683,11 @@ define @intrinsic_vmseq_mask_vx_nxv1i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v11, (a0), zero +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vv v25, v8, v26, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vv v10, v8, v11, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1714,8 +1714,8 @@ define @intrinsic_vmseq_vx_nxv2i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmseq.vv v0, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmseq.vv v0, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1742,11 +1742,11 @@ define @intrinsic_vmseq_mask_vx_nxv2i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vv v25, v8, v26, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vv v11, v8, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1773,8 +1773,8 @@ define @intrinsic_vmseq_vx_nxv4i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmseq.vv v0, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmseq.vv v0, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1801,11 +1801,11 @@ define @intrinsic_vmseq_mask_vx_nxv4i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v16, (a0), zero +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vv v25, v8, v28, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vv v13, v8, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1837,11 +1837,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv1i8.i8( @@ -1872,11 +1872,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv2i8.i8( @@ -1907,11 +1907,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv4i8.i8( @@ -1942,11 +1942,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv8i8.i8( @@ -1977,11 +1977,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv16i8.i8( @@ -2012,11 +2012,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv32i8.i8( @@ -2047,11 +2047,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv1i16.i16( @@ -2082,11 +2082,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv2i16.i16( @@ -2117,11 +2117,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv4i16.i16( @@ -2152,11 +2152,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv8i16.i16( @@ -2187,11 +2187,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv16i16.i16( @@ -2222,11 +2222,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv1i32.i32( @@ -2257,11 +2257,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv2i32.i32( @@ -2292,11 +2292,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv4i32.i32( @@ -2327,11 +2327,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv8i32.i32( @@ -2362,11 +2362,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv1i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv1i64.i64( @@ -2397,11 +2397,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv2i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv2i64.i64( @@ -2432,11 +2432,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv4i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll index b418d9bba074107cf35985111f59a84e840766aa..38f2c69df1bd009c81734c2b5f3fed034ffb13af 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll @@ -32,11 +32,11 @@ define @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmseq.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmseq.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmseq.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmseq.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmseq.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmseq.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmseq.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmseq.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmseq.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmseq.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmseq.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmseq.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmseq.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmseq.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmseq.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmseq.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmseq.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmseq.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmseq.mask.nxv1i8.i8( define @intrinsic_vmseq_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmseq.mask.nxv2i8.i8( define @intrinsic_vmseq_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmseq.mask.nxv4i8.i8( define @intrinsic_vmseq_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmseq.mask.nxv8i8.i8( define @intrinsic_vmseq_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmseq.mask.nxv16i8.i8( define @intrinsic_vmseq_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmseq.mask.nxv32i8.i8( define @intrinsic_vmseq_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmseq.mask.nxv1i16.i16( define @intrinsic_vmseq_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmseq.mask.nxv2i16.i16( define @intrinsic_vmseq_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmseq.mask.nxv4i16.i16( define @intrinsic_vmseq_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmseq.mask.nxv8i16.i16( define @intrinsic_vmseq_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmseq.mask.nxv16i16.i16( define @intrinsic_vmseq_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmseq.mask.nxv1i32.i32( define @intrinsic_vmseq_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmseq.mask.nxv2i32.i32( define @intrinsic_vmseq_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmseq.mask.nxv4i32.i32( define @intrinsic_vmseq_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmseq.mask.nxv8i32.i32( define @intrinsic_vmseq_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv8i32.i32( @@ -1672,11 +1672,11 @@ declare @llvm.riscv.vmseq.mask.nxv1i64.i64( define @intrinsic_vmseq_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv1i64.i64( @@ -1719,11 +1719,11 @@ declare @llvm.riscv.vmseq.mask.nxv2i64.i64( define @intrinsic_vmseq_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv2i64.i64( @@ -1766,11 +1766,11 @@ declare @llvm.riscv.vmseq.mask.nxv4i64.i64( define @intrinsic_vmseq_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv4i64.i64( @@ -1801,11 +1801,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv1i8.i8( @@ -1836,11 +1836,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv2i8.i8( @@ -1871,11 +1871,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv4i8.i8( @@ -1906,11 +1906,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv8i8.i8( @@ -1941,11 +1941,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv16i8.i8( @@ -1976,11 +1976,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv32i8.i8( @@ -2011,11 +2011,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv1i16.i16( @@ -2046,11 +2046,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv2i16.i16( @@ -2081,11 +2081,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv4i16.i16( @@ -2116,11 +2116,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv8i16.i16( @@ -2151,11 +2151,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv16i16.i16( @@ -2186,11 +2186,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv1i32.i32( @@ -2221,11 +2221,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv2i32.i32( @@ -2256,11 +2256,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv4i32.i32( @@ -2291,11 +2291,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv8i32.i32( @@ -2326,11 +2326,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv1i64.i64( @@ -2361,11 +2361,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv2i64.i64( @@ -2396,11 +2396,11 @@ entry: define @intrinsic_vmseq_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmseq.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll index 67ee7c3a338e091e6cdc969a1a12287852d65e10..983111ad6aafc4fc37c52062c410d9c6d3f3a678 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll @@ -32,11 +32,11 @@ define @intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsge.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsge.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsge.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsge.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsge.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsge.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsge.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsge.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsge.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsge.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsge.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsge.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsge.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsge.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsge.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsge.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsge.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsge.nxv4i64( @@ -946,8 +946,8 @@ define @intrinsic_vmsge_vx_nxv1i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv1i8.i8( @@ -968,11 +968,11 @@ declare @llvm.riscv.vmsge.mask.nxv1i8.i8( define @intrinsic_vmsge_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv1i8.i8( @@ -994,8 +994,8 @@ define @intrinsic_vmsge_vx_nxv2i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv2i8.i8( @@ -1016,11 +1016,11 @@ declare @llvm.riscv.vmsge.mask.nxv2i8.i8( define @intrinsic_vmsge_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv2i8.i8( @@ -1042,8 +1042,8 @@ define @intrinsic_vmsge_vx_nxv4i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv4i8.i8( @@ -1064,11 +1064,11 @@ declare @llvm.riscv.vmsge.mask.nxv4i8.i8( define @intrinsic_vmsge_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv4i8.i8( @@ -1090,8 +1090,8 @@ define @intrinsic_vmsge_vx_nxv8i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv8i8.i8( @@ -1112,11 +1112,11 @@ declare @llvm.riscv.vmsge.mask.nxv8i8.i8( define @intrinsic_vmsge_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv8i8.i8( @@ -1138,8 +1138,8 @@ define @intrinsic_vmsge_vx_nxv16i8_i8( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv16i8.i8( @@ -1160,11 +1160,11 @@ declare @llvm.riscv.vmsge.mask.nxv16i8.i8( define @intrinsic_vmsge_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v10 +; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv16i8.i8( @@ -1186,8 +1186,8 @@ define @intrinsic_vmsge_vx_nxv32i8_i8( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v12, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv32i8.i8( @@ -1208,11 +1208,11 @@ declare @llvm.riscv.vmsge.mask.nxv32i8.i8( define @intrinsic_vmsge_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v12 +; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv32i8.i8( @@ -1234,8 +1234,8 @@ define @intrinsic_vmsge_vx_nxv1i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv1i16.i16( @@ -1256,11 +1256,11 @@ declare @llvm.riscv.vmsge.mask.nxv1i16.i16( define @intrinsic_vmsge_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv1i16.i16( @@ -1282,8 +1282,8 @@ define @intrinsic_vmsge_vx_nxv2i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv2i16.i16( @@ -1304,11 +1304,11 @@ declare @llvm.riscv.vmsge.mask.nxv2i16.i16( define @intrinsic_vmsge_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv2i16.i16( @@ -1330,8 +1330,8 @@ define @intrinsic_vmsge_vx_nxv4i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv4i16.i16( @@ -1352,11 +1352,11 @@ declare @llvm.riscv.vmsge.mask.nxv4i16.i16( define @intrinsic_vmsge_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv4i16.i16( @@ -1378,8 +1378,8 @@ define @intrinsic_vmsge_vx_nxv8i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv8i16.i16( @@ -1400,11 +1400,11 @@ declare @llvm.riscv.vmsge.mask.nxv8i16.i16( define @intrinsic_vmsge_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v10 +; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv8i16.i16( @@ -1426,8 +1426,8 @@ define @intrinsic_vmsge_vx_nxv16i16_i16( % ; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v12, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv16i16.i16( @@ -1448,11 +1448,11 @@ declare @llvm.riscv.vmsge.mask.nxv16i16.i16( define @intrinsic_vmsge_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v12 +; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv16i16.i16( @@ -1474,8 +1474,8 @@ define @intrinsic_vmsge_vx_nxv1i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv1i32.i32( @@ -1496,11 +1496,11 @@ declare @llvm.riscv.vmsge.mask.nxv1i32.i32( define @intrinsic_vmsge_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv1i32.i32( @@ -1522,8 +1522,8 @@ define @intrinsic_vmsge_vx_nxv2i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv2i32.i32( @@ -1544,11 +1544,11 @@ declare @llvm.riscv.vmsge.mask.nxv2i32.i32( define @intrinsic_vmsge_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv2i32.i32( @@ -1570,8 +1570,8 @@ define @intrinsic_vmsge_vx_nxv4i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv4i32.i32( @@ -1592,11 +1592,11 @@ declare @llvm.riscv.vmsge.mask.nxv4i32.i32( define @intrinsic_vmsge_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v10 +; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv4i32.i32( @@ -1618,8 +1618,8 @@ define @intrinsic_vmsge_vx_nxv8i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v12, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv8i32.i32( @@ -1640,11 +1640,11 @@ declare @llvm.riscv.vmsge.mask.nxv8i32.i32( define @intrinsic_vmsge_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v12 +; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv8i32.i32( @@ -1670,8 +1670,8 @@ define @intrinsic_vmsge_vx_nxv1i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmsle.vv v0, v25, v8 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1698,11 +1698,11 @@ define @intrinsic_vmsge_mask_vx_nxv1i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v11, (a0), zero +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vv v25, v26, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vv v10, v11, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1729,8 +1729,8 @@ define @intrinsic_vmsge_vx_nxv2i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmsle.vv v0, v26, v8 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1757,11 +1757,11 @@ define @intrinsic_vmsge_mask_vx_nxv2i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vv v25, v26, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vv v11, v12, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1788,8 +1788,8 @@ define @intrinsic_vmsge_vx_nxv4i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmsle.vv v0, v28, v8 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1816,11 +1816,11 @@ define @intrinsic_vmsge_mask_vx_nxv4i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v16, (a0), zero +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vv v25, v28, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vv v13, v16, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1852,11 +1852,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, -15, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, -15, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv1i8.i8( @@ -1887,11 +1887,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, -13, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, -13, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv2i8.i8( @@ -1922,11 +1922,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, -11, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, -11, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv4i8.i8( @@ -1957,11 +1957,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, -9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, -9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv8i8.i8( @@ -1992,11 +1992,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, -7, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, -7, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv16i8.i8( @@ -2027,11 +2027,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, -5, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, -5, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv32i8.i8( @@ -2062,11 +2062,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, -3, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, -3, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv1i16.i16( @@ -2097,11 +2097,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, -1, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, -1, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv2i16.i16( @@ -2132,11 +2132,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv4i16.i16( @@ -2167,11 +2167,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, 2, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, 2, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv8i16.i16( @@ -2202,11 +2202,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, 4, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, 4, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv16i16.i16( @@ -2237,11 +2237,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 6, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 6, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv1i32.i32( @@ -2272,11 +2272,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv2i32.i32( @@ -2307,11 +2307,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, 10, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, 10, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv4i32.i32( @@ -2342,11 +2342,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, 12, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, 12, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv8i32.i32( @@ -2377,11 +2377,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv1i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv1i64.i64( @@ -2412,11 +2412,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv2i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv2i64.i64( @@ -2447,11 +2447,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv4i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv4i64.i64( @@ -2469,8 +2469,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8( @llvm.riscv.vmsge.mask.nxv1i8.i8( @@ -2487,8 +2487,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8( @llvm.riscv.vmsge.mask.nxv2i8.i8( @@ -2505,8 +2505,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8( @llvm.riscv.vmsge.mask.nxv4i8.i8( @@ -2523,8 +2523,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8( @llvm.riscv.vmsge.mask.nxv8i8.i8( @@ -2541,8 +2541,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8( @llvm.riscv.vmsge.mask.nxv16i8.i8( @@ -2559,8 +2559,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8( @llvm.riscv.vmsge.mask.nxv32i8.i8( @@ -2577,8 +2577,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16( @llvm.riscv.vmsge.mask.nxv1i16.i16( @@ -2595,8 +2595,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16( @llvm.riscv.vmsge.mask.nxv2i16.i16( @@ -2613,8 +2613,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16( @llvm.riscv.vmsge.mask.nxv4i16.i16( @@ -2631,8 +2631,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16( @llvm.riscv.vmsge.mask.nxv8i16.i16( @@ -2649,8 +2649,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16( @llvm.riscv.vmsge.mask.nxv16i16.i16( @@ -2667,8 +2667,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32( @llvm.riscv.vmsge.mask.nxv1i32.i32( @@ -2685,8 +2685,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32( @llvm.riscv.vmsge.mask.nxv2i32.i32( @@ -2703,8 +2703,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32( @llvm.riscv.vmsge.mask.nxv4i32.i32( @@ -2721,8 +2721,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32( @llvm.riscv.vmsge.mask.nxv8i32.i32( @@ -2743,8 +2743,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64( @intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64( @intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64( @intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsge.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsge.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsge.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsge.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsge.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsge.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsge.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsge.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsge.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsge.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsge.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsge.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsge.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsge.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsge.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsge.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsge.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsge.nxv4i64( @@ -946,8 +946,8 @@ define @intrinsic_vmsge_vx_nxv1i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv1i8.i8( @@ -968,11 +968,11 @@ declare @llvm.riscv.vmsge.mask.nxv1i8.i8( define @intrinsic_vmsge_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv1i8.i8( @@ -994,8 +994,8 @@ define @intrinsic_vmsge_vx_nxv2i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv2i8.i8( @@ -1016,11 +1016,11 @@ declare @llvm.riscv.vmsge.mask.nxv2i8.i8( define @intrinsic_vmsge_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv2i8.i8( @@ -1042,8 +1042,8 @@ define @intrinsic_vmsge_vx_nxv4i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv4i8.i8( @@ -1064,11 +1064,11 @@ declare @llvm.riscv.vmsge.mask.nxv4i8.i8( define @intrinsic_vmsge_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv4i8.i8( @@ -1090,8 +1090,8 @@ define @intrinsic_vmsge_vx_nxv8i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv8i8.i8( @@ -1112,11 +1112,11 @@ declare @llvm.riscv.vmsge.mask.nxv8i8.i8( define @intrinsic_vmsge_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv8i8.i8( @@ -1138,8 +1138,8 @@ define @intrinsic_vmsge_vx_nxv16i8_i8( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv16i8.i8( @@ -1160,11 +1160,11 @@ declare @llvm.riscv.vmsge.mask.nxv16i8.i8( define @intrinsic_vmsge_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v10 +; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv16i8.i8( @@ -1186,8 +1186,8 @@ define @intrinsic_vmsge_vx_nxv32i8_i8( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v12, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv32i8.i8( @@ -1208,11 +1208,11 @@ declare @llvm.riscv.vmsge.mask.nxv32i8.i8( define @intrinsic_vmsge_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v12 +; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv32i8.i8( @@ -1234,8 +1234,8 @@ define @intrinsic_vmsge_vx_nxv1i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv1i16.i16( @@ -1256,11 +1256,11 @@ declare @llvm.riscv.vmsge.mask.nxv1i16.i16( define @intrinsic_vmsge_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv1i16.i16( @@ -1282,8 +1282,8 @@ define @intrinsic_vmsge_vx_nxv2i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv2i16.i16( @@ -1304,11 +1304,11 @@ declare @llvm.riscv.vmsge.mask.nxv2i16.i16( define @intrinsic_vmsge_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv2i16.i16( @@ -1330,8 +1330,8 @@ define @intrinsic_vmsge_vx_nxv4i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv4i16.i16( @@ -1352,11 +1352,11 @@ declare @llvm.riscv.vmsge.mask.nxv4i16.i16( define @intrinsic_vmsge_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv4i16.i16( @@ -1378,8 +1378,8 @@ define @intrinsic_vmsge_vx_nxv8i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv8i16.i16( @@ -1400,11 +1400,11 @@ declare @llvm.riscv.vmsge.mask.nxv8i16.i16( define @intrinsic_vmsge_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v10 +; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv8i16.i16( @@ -1426,8 +1426,8 @@ define @intrinsic_vmsge_vx_nxv16i16_i16( % ; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v12, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv16i16.i16( @@ -1448,11 +1448,11 @@ declare @llvm.riscv.vmsge.mask.nxv16i16.i16( define @intrinsic_vmsge_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v12 +; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv16i16.i16( @@ -1474,8 +1474,8 @@ define @intrinsic_vmsge_vx_nxv1i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv1i32.i32( @@ -1496,11 +1496,11 @@ declare @llvm.riscv.vmsge.mask.nxv1i32.i32( define @intrinsic_vmsge_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv1i32.i32( @@ -1522,8 +1522,8 @@ define @intrinsic_vmsge_vx_nxv2i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv2i32.i32( @@ -1544,11 +1544,11 @@ declare @llvm.riscv.vmsge.mask.nxv2i32.i32( define @intrinsic_vmsge_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv2i32.i32( @@ -1570,8 +1570,8 @@ define @intrinsic_vmsge_vx_nxv4i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv4i32.i32( @@ -1592,11 +1592,11 @@ declare @llvm.riscv.vmsge.mask.nxv4i32.i32( define @intrinsic_vmsge_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v10 +; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv4i32.i32( @@ -1618,8 +1618,8 @@ define @intrinsic_vmsge_vx_nxv8i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v12, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv8i32.i32( @@ -1640,11 +1640,11 @@ declare @llvm.riscv.vmsge.mask.nxv8i32.i32( define @intrinsic_vmsge_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v12 +; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv8i32.i32( @@ -1666,8 +1666,8 @@ define @intrinsic_vmsge_vx_nxv1i64_i64( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv1i64.i64( @@ -1688,11 +1688,11 @@ declare @llvm.riscv.vmsge.mask.nxv1i64.i64( define @intrinsic_vmsge_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv1i64.i64( @@ -1714,8 +1714,8 @@ define @intrinsic_vmsge_vx_nxv2i64_i64( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv2i64.i64( @@ -1736,11 +1736,11 @@ declare @llvm.riscv.vmsge.mask.nxv2i64.i64( define @intrinsic_vmsge_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v10 +; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv2i64.i64( @@ -1762,8 +1762,8 @@ define @intrinsic_vmsge_vx_nxv4i64_i64( %0, ; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vmslt.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmslt.vx v12, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.nxv4i64.i64( @@ -1784,11 +1784,11 @@ declare @llvm.riscv.vmsge.mask.nxv4i64.i64( define @intrinsic_vmsge_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v12 +; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv4i64.i64( @@ -1819,11 +1819,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, -15, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, -15, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv1i8.i8( @@ -1854,11 +1854,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, -13, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, -13, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv2i8.i8( @@ -1889,11 +1889,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, -11, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, -11, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv4i8.i8( @@ -1924,11 +1924,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, -9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, -9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv8i8.i8( @@ -1959,11 +1959,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, -7, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, -7, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv16i8.i8( @@ -1994,11 +1994,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, -5, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, -5, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv32i8.i8( @@ -2029,11 +2029,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, -3, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, -3, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv1i16.i16( @@ -2064,11 +2064,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, -1, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, -1, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv2i16.i16( @@ -2099,11 +2099,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv4i16.i16( @@ -2134,11 +2134,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, 2, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, 2, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv8i16.i16( @@ -2169,11 +2169,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, 4, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, 4, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv16i16.i16( @@ -2204,11 +2204,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 6, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 6, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv1i32.i32( @@ -2239,11 +2239,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv2i32.i32( @@ -2274,11 +2274,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, 10, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, 10, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv4i32.i32( @@ -2309,11 +2309,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, 12, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, 12, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv8i32.i32( @@ -2344,11 +2344,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 14, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 14, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv1i64.i64( @@ -2379,11 +2379,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, -16, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, -16, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv2i64.i64( @@ -2414,11 +2414,11 @@ entry: define @intrinsic_vmsge_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, -14, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, -14, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsge.mask.nxv4i64.i64( @@ -2436,8 +2436,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8( @llvm.riscv.vmsge.mask.nxv1i8.i8( @@ -2454,8 +2454,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8( @llvm.riscv.vmsge.mask.nxv2i8.i8( @@ -2472,8 +2472,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8( @llvm.riscv.vmsge.mask.nxv4i8.i8( @@ -2490,8 +2490,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8( @llvm.riscv.vmsge.mask.nxv8i8.i8( @@ -2508,8 +2508,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8( @llvm.riscv.vmsge.mask.nxv16i8.i8( @@ -2526,8 +2526,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8( @llvm.riscv.vmsge.mask.nxv32i8.i8( @@ -2544,8 +2544,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16( @llvm.riscv.vmsge.mask.nxv1i16.i16( @@ -2562,8 +2562,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16( @llvm.riscv.vmsge.mask.nxv2i16.i16( @@ -2580,8 +2580,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16( @llvm.riscv.vmsge.mask.nxv4i16.i16( @@ -2598,8 +2598,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16( @llvm.riscv.vmsge.mask.nxv8i16.i16( @@ -2616,8 +2616,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16( @llvm.riscv.vmsge.mask.nxv16i16.i16( @@ -2634,8 +2634,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32( @llvm.riscv.vmsge.mask.nxv1i32.i32( @@ -2652,8 +2652,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32( @llvm.riscv.vmsge.mask.nxv2i32.i32( @@ -2670,8 +2670,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32( @llvm.riscv.vmsge.mask.nxv4i32.i32( @@ -2688,8 +2688,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32( @llvm.riscv.vmsge.mask.nxv8i32.i32( @@ -2706,8 +2706,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64( @llvm.riscv.vmsge.mask.nxv1i64.i64( @@ -2724,8 +2724,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64( @llvm.riscv.vmsge.mask.nxv2i64.i64( @@ -2742,8 +2742,8 @@ define @intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64( @llvm.riscv.vmsge.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll index 4b62178aaefbe1f5327143a90565f86a19ac5810..72d2c044539ccfbc58d354d53fe3727f3f3b1aaf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll @@ -32,11 +32,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsgeu.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsgeu.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsgeu.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsgeu.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsgeu.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsgeu.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsgeu.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsgeu.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsgeu.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsgeu.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsgeu.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsgeu.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsgeu.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsgeu.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsgeu.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsgeu.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsgeu.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsgeu.nxv4i64( @@ -946,8 +946,8 @@ define @intrinsic_vmsgeu_vx_nxv1i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i8.i8( @@ -968,11 +968,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv1i8.i8( define @intrinsic_vmsgeu_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i8.i8( @@ -994,8 +994,8 @@ define @intrinsic_vmsgeu_vx_nxv2i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i8.i8( @@ -1016,11 +1016,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv2i8.i8( define @intrinsic_vmsgeu_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i8.i8( @@ -1042,8 +1042,8 @@ define @intrinsic_vmsgeu_vx_nxv4i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i8.i8( @@ -1064,11 +1064,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv4i8.i8( define @intrinsic_vmsgeu_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i8.i8( @@ -1090,8 +1090,8 @@ define @intrinsic_vmsgeu_vx_nxv8i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv8i8.i8( @@ -1112,11 +1112,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv8i8.i8( define @intrinsic_vmsgeu_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i8.i8( @@ -1138,8 +1138,8 @@ define @intrinsic_vmsgeu_vx_nxv16i8_i8( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv16i8.i8( @@ -1160,11 +1160,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv16i8.i8( define @intrinsic_vmsgeu_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v10 +; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv16i8.i8( @@ -1186,8 +1186,8 @@ define @intrinsic_vmsgeu_vx_nxv32i8_i8( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v12, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv32i8.i8( @@ -1208,11 +1208,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv32i8.i8( define @intrinsic_vmsgeu_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v12 +; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv32i8.i8( @@ -1234,8 +1234,8 @@ define @intrinsic_vmsgeu_vx_nxv1i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i16.i16( @@ -1256,11 +1256,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv1i16.i16( define @intrinsic_vmsgeu_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i16.i16( @@ -1282,8 +1282,8 @@ define @intrinsic_vmsgeu_vx_nxv2i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i16.i16( @@ -1304,11 +1304,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv2i16.i16( define @intrinsic_vmsgeu_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i16.i16( @@ -1330,8 +1330,8 @@ define @intrinsic_vmsgeu_vx_nxv4i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i16.i16( @@ -1352,11 +1352,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv4i16.i16( define @intrinsic_vmsgeu_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i16.i16( @@ -1378,8 +1378,8 @@ define @intrinsic_vmsgeu_vx_nxv8i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv8i16.i16( @@ -1400,11 +1400,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv8i16.i16( define @intrinsic_vmsgeu_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v10 +; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i16.i16( @@ -1426,8 +1426,8 @@ define @intrinsic_vmsgeu_vx_nxv16i16_i16( ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v12, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv16i16.i16( @@ -1448,11 +1448,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv16i16.i16( define @intrinsic_vmsgeu_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v12 +; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv16i16.i16( @@ -1474,8 +1474,8 @@ define @intrinsic_vmsgeu_vx_nxv1i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i32.i32( @@ -1496,11 +1496,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv1i32.i32( define @intrinsic_vmsgeu_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i32.i32( @@ -1522,8 +1522,8 @@ define @intrinsic_vmsgeu_vx_nxv2i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i32.i32( @@ -1544,11 +1544,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv2i32.i32( define @intrinsic_vmsgeu_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i32.i32( @@ -1570,8 +1570,8 @@ define @intrinsic_vmsgeu_vx_nxv4i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i32.i32( @@ -1592,11 +1592,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv4i32.i32( define @intrinsic_vmsgeu_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v10 +; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i32.i32( @@ -1618,8 +1618,8 @@ define @intrinsic_vmsgeu_vx_nxv8i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v12, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv8i32.i32( @@ -1640,11 +1640,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv8i32.i32( define @intrinsic_vmsgeu_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v12 +; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i32.i32( @@ -1670,8 +1670,8 @@ define @intrinsic_vmsgeu_vx_nxv1i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmsleu.vv v0, v25, v8 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1698,11 +1698,11 @@ define @intrinsic_vmsgeu_mask_vx_nxv1i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v11, (a0), zero +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vv v25, v26, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vv v10, v11, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1729,8 +1729,8 @@ define @intrinsic_vmsgeu_vx_nxv2i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmsleu.vv v0, v26, v8 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1757,11 +1757,11 @@ define @intrinsic_vmsgeu_mask_vx_nxv2i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vv v25, v26, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vv v11, v12, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1788,8 +1788,8 @@ define @intrinsic_vmsgeu_vx_nxv4i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmsleu.vv v0, v28, v8 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1816,11 +1816,11 @@ define @intrinsic_vmsgeu_mask_vx_nxv4i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v16, (a0), zero +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vv v25, v28, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vv v13, v16, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1852,11 +1852,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, -15, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, -15, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i8.i8( @@ -1887,11 +1887,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, -13, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, -13, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i8.i8( @@ -1922,11 +1922,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, -11, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, -11, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i8.i8( @@ -1957,11 +1957,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, -9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, -9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i8.i8( @@ -1992,11 +1992,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, -7, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, -7, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv16i8.i8( @@ -2027,11 +2027,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, -5, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, -5, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv32i8.i8( @@ -2062,11 +2062,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, -3, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, -3, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i16.i16( @@ -2097,11 +2097,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vv v25, v8, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vv v10, v8, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i16.i16( @@ -2132,11 +2132,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i16.i16( @@ -2167,11 +2167,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, 2, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, 2, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i16.i16( @@ -2202,11 +2202,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, 4, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, 4, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv16i16.i16( @@ -2237,11 +2237,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 6, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 6, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i32.i32( @@ -2272,11 +2272,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i32.i32( @@ -2307,11 +2307,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, 10, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, 10, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i32.i32( @@ -2342,11 +2342,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, 12, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, 12, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i32.i32( @@ -2377,11 +2377,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv1i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 14, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 14, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i64.i64( @@ -2412,11 +2412,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv2i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, -16, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, -16, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i64.i64( @@ -2447,11 +2447,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv4i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, -14, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, -14, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i64.i64( @@ -2469,8 +2469,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8( @llvm.riscv.vmsgeu.mask.nxv1i8.i8( @@ -2487,8 +2487,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8( @llvm.riscv.vmsgeu.mask.nxv2i8.i8( @@ -2505,8 +2505,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8( @llvm.riscv.vmsgeu.mask.nxv4i8.i8( @@ -2523,8 +2523,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8( @llvm.riscv.vmsgeu.mask.nxv8i8.i8( @@ -2541,8 +2541,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8( @llvm.riscv.vmsgeu.mask.nxv16i8.i8( @@ -2559,8 +2559,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8( @llvm.riscv.vmsgeu.mask.nxv32i8.i8( @@ -2577,8 +2577,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16( @llvm.riscv.vmsgeu.mask.nxv1i16.i16( @@ -2595,8 +2595,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16( @llvm.riscv.vmsgeu.mask.nxv2i16.i16( @@ -2613,8 +2613,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16( @llvm.riscv.vmsgeu.mask.nxv4i16.i16( @@ -2631,8 +2631,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16( @llvm.riscv.vmsgeu.mask.nxv8i16.i16( @@ -2649,8 +2649,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16( @llvm.riscv.vmsgeu.mask.nxv16i16.i16( @@ -2667,8 +2667,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32( @llvm.riscv.vmsgeu.mask.nxv1i32.i32( @@ -2685,8 +2685,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32( @llvm.riscv.vmsgeu.mask.nxv2i32.i32( @@ -2703,8 +2703,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32( @llvm.riscv.vmsgeu.mask.nxv4i32.i32( @@ -2721,8 +2721,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32( @llvm.riscv.vmsgeu.mask.nxv8i32.i32( @@ -2743,8 +2743,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64( @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64( @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64( @intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsgeu.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsgeu.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsgeu.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsgeu.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsgeu.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsgeu.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsgeu.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsgeu.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsgeu.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsgeu.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsgeu.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsgeu.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsgeu.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsgeu.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsgeu.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsgeu.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsgeu.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsgeu.nxv4i64( @@ -946,8 +946,8 @@ define @intrinsic_vmsgeu_vx_nxv1i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i8.i8( @@ -968,11 +968,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv1i8.i8( define @intrinsic_vmsgeu_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i8.i8( @@ -994,8 +994,8 @@ define @intrinsic_vmsgeu_vx_nxv2i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i8.i8( @@ -1016,11 +1016,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv2i8.i8( define @intrinsic_vmsgeu_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i8.i8( @@ -1042,8 +1042,8 @@ define @intrinsic_vmsgeu_vx_nxv4i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i8.i8( @@ -1064,11 +1064,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv4i8.i8( define @intrinsic_vmsgeu_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i8.i8( @@ -1090,8 +1090,8 @@ define @intrinsic_vmsgeu_vx_nxv8i8_i8( %0, i8 ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv8i8.i8( @@ -1112,11 +1112,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv8i8.i8( define @intrinsic_vmsgeu_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i8.i8( @@ -1138,8 +1138,8 @@ define @intrinsic_vmsgeu_vx_nxv16i8_i8( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv16i8.i8( @@ -1160,11 +1160,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv16i8.i8( define @intrinsic_vmsgeu_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v10 +; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv16i8.i8( @@ -1186,8 +1186,8 @@ define @intrinsic_vmsgeu_vx_nxv32i8_i8( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v12, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv32i8.i8( @@ -1208,11 +1208,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv32i8.i8( define @intrinsic_vmsgeu_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v12 +; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv32i8.i8( @@ -1234,8 +1234,8 @@ define @intrinsic_vmsgeu_vx_nxv1i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i16.i16( @@ -1256,11 +1256,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv1i16.i16( define @intrinsic_vmsgeu_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i16.i16( @@ -1282,8 +1282,8 @@ define @intrinsic_vmsgeu_vx_nxv2i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i16.i16( @@ -1304,11 +1304,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv2i16.i16( define @intrinsic_vmsgeu_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i16.i16( @@ -1330,8 +1330,8 @@ define @intrinsic_vmsgeu_vx_nxv4i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i16.i16( @@ -1352,11 +1352,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv4i16.i16( define @intrinsic_vmsgeu_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i16.i16( @@ -1378,8 +1378,8 @@ define @intrinsic_vmsgeu_vx_nxv8i16_i16( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv8i16.i16( @@ -1400,11 +1400,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv8i16.i16( define @intrinsic_vmsgeu_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v10 +; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i16.i16( @@ -1426,8 +1426,8 @@ define @intrinsic_vmsgeu_vx_nxv16i16_i16( ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v12, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv16i16.i16( @@ -1448,11 +1448,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv16i16.i16( define @intrinsic_vmsgeu_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v12 +; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv16i16.i16( @@ -1474,8 +1474,8 @@ define @intrinsic_vmsgeu_vx_nxv1i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i32.i32( @@ -1496,11 +1496,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv1i32.i32( define @intrinsic_vmsgeu_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i32.i32( @@ -1522,8 +1522,8 @@ define @intrinsic_vmsgeu_vx_nxv2i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i32.i32( @@ -1544,11 +1544,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv2i32.i32( define @intrinsic_vmsgeu_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i32.i32( @@ -1570,8 +1570,8 @@ define @intrinsic_vmsgeu_vx_nxv4i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i32.i32( @@ -1592,11 +1592,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv4i32.i32( define @intrinsic_vmsgeu_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v10 +; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i32.i32( @@ -1618,8 +1618,8 @@ define @intrinsic_vmsgeu_vx_nxv8i32_i32( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v12, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv8i32.i32( @@ -1640,11 +1640,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv8i32.i32( define @intrinsic_vmsgeu_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v12 +; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i32.i32( @@ -1666,8 +1666,8 @@ define @intrinsic_vmsgeu_vx_nxv1i64_i64( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v8, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v8, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i64.i64( @@ -1688,11 +1688,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv1i64.i64( define @intrinsic_vmsgeu_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v9 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i64.i64( @@ -1714,8 +1714,8 @@ define @intrinsic_vmsgeu_vx_nxv2i64_i64( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v10, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i64.i64( @@ -1736,11 +1736,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv2i64.i64( define @intrinsic_vmsgeu_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v10 +; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i64.i64( @@ -1762,8 +1762,8 @@ define @intrinsic_vmsgeu_vx_nxv4i64_i64( %0, ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vmsltu.vx v25, v8, a0 -; CHECK-NEXT: vmnand.mm v0, v25, v25 +; CHECK-NEXT: vmsltu.vx v12, v8, a0 +; CHECK-NEXT: vmnand.mm v0, v12, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i64.i64( @@ -1784,11 +1784,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv4i64.i64( define @intrinsic_vmsgeu_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmxor.mm v0, v25, v12 +; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i64.i64( @@ -1819,11 +1819,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, -15, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, -15, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i8.i8( @@ -1854,11 +1854,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, -13, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, -13, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i8.i8( @@ -1889,11 +1889,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, -11, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, -11, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i8.i8( @@ -1924,11 +1924,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, -9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, -9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i8.i8( @@ -1959,11 +1959,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, -7, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, -7, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv16i8.i8( @@ -1994,11 +1994,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, -5, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, -5, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv32i8.i8( @@ -2029,11 +2029,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, -3, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, -3, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i16.i16( @@ -2064,11 +2064,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmseq.vv v25, v8, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmseq.vv v10, v8, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i16.i16( @@ -2099,11 +2099,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i16.i16( @@ -2134,11 +2134,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, 2, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, 2, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i16.i16( @@ -2169,11 +2169,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, 4, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, 4, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv16i16.i16( @@ -2204,11 +2204,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 6, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 6, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i32.i32( @@ -2239,11 +2239,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i32.i32( @@ -2274,11 +2274,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, 10, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, 10, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i32.i32( @@ -2309,11 +2309,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, 12, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, 12, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i32.i32( @@ -2344,11 +2344,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 14, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 14, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i64.i64( @@ -2379,11 +2379,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, -16, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, -16, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i64.i64( @@ -2414,11 +2414,11 @@ entry: define @intrinsic_vmsgeu_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, -14, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, -14, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i64.i64( @@ -2436,8 +2436,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8( @llvm.riscv.vmsgeu.mask.nxv1i8.i8( @@ -2454,8 +2454,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8( @llvm.riscv.vmsgeu.mask.nxv2i8.i8( @@ -2472,8 +2472,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8( @llvm.riscv.vmsgeu.mask.nxv4i8.i8( @@ -2490,8 +2490,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8( @llvm.riscv.vmsgeu.mask.nxv8i8.i8( @@ -2508,8 +2508,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8( @llvm.riscv.vmsgeu.mask.nxv16i8.i8( @@ -2526,8 +2526,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8( @llvm.riscv.vmsgeu.mask.nxv32i8.i8( @@ -2544,8 +2544,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16( @llvm.riscv.vmsgeu.mask.nxv1i16.i16( @@ -2562,8 +2562,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16( @llvm.riscv.vmsgeu.mask.nxv2i16.i16( @@ -2580,8 +2580,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16( @llvm.riscv.vmsgeu.mask.nxv4i16.i16( @@ -2598,8 +2598,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16( @llvm.riscv.vmsgeu.mask.nxv8i16.i16( @@ -2616,8 +2616,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16( @llvm.riscv.vmsgeu.mask.nxv16i16.i16( @@ -2634,8 +2634,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32( @llvm.riscv.vmsgeu.mask.nxv1i32.i32( @@ -2652,8 +2652,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32( @llvm.riscv.vmsgeu.mask.nxv2i32.i32( @@ -2670,8 +2670,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32( @llvm.riscv.vmsgeu.mask.nxv4i32.i32( @@ -2688,8 +2688,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32( @llvm.riscv.vmsgeu.mask.nxv8i32.i32( @@ -2706,8 +2706,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64( @llvm.riscv.vmsgeu.mask.nxv1i64.i64( @@ -2724,8 +2724,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64( @llvm.riscv.vmsgeu.mask.nxv2i64.i64( @@ -2742,8 +2742,8 @@ define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64( @llvm.riscv.vmsgeu.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll index 1687a6b34563f1b6bcbff7abe1a105876b8dc661..7c4556d5493eadaf1740e8b09844d8650f67a8d7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll @@ -32,11 +32,11 @@ define @intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsgt.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsgt.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsgt.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsgt.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsgt.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsgt.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsgt.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsgt.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsgt.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsgt.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsgt.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsgt.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsgt.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsgt.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsgt.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsgt.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsgt.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsgt.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmsgt.mask.nxv1i8.i8( define @intrinsic_vmsgt_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmsgt.mask.nxv2i8.i8( define @intrinsic_vmsgt_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmsgt.mask.nxv4i8.i8( define @intrinsic_vmsgt_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmsgt.mask.nxv8i8.i8( define @intrinsic_vmsgt_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmsgt.mask.nxv16i8.i8( define @intrinsic_vmsgt_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmsgt.mask.nxv32i8.i8( define @intrinsic_vmsgt_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmsgt.mask.nxv1i16.i16( define @intrinsic_vmsgt_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmsgt.mask.nxv2i16.i16( define @intrinsic_vmsgt_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmsgt.mask.nxv4i16.i16( define @intrinsic_vmsgt_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmsgt.mask.nxv8i16.i16( define @intrinsic_vmsgt_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmsgt.mask.nxv16i16.i16( define @intrinsic_vmsgt_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmsgt.mask.nxv1i32.i32( define @intrinsic_vmsgt_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmsgt.mask.nxv2i32.i32( define @intrinsic_vmsgt_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmsgt.mask.nxv4i32.i32( define @intrinsic_vmsgt_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmsgt.mask.nxv8i32.i32( define @intrinsic_vmsgt_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv8i32.i32( @@ -1655,8 +1655,8 @@ define @intrinsic_vmsgt_vx_nxv1i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmslt.vv v0, v25, v8 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1683,11 +1683,11 @@ define @intrinsic_vmsgt_mask_vx_nxv1i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v11, (a0), zero +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vv v25, v26, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vv v10, v11, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1714,8 +1714,8 @@ define @intrinsic_vmsgt_vx_nxv2i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmslt.vv v0, v26, v8 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmslt.vv v0, v10, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1742,11 +1742,11 @@ define @intrinsic_vmsgt_mask_vx_nxv2i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vv v25, v26, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vv v11, v12, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1773,8 +1773,8 @@ define @intrinsic_vmsgt_vx_nxv4i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmslt.vv v0, v28, v8 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmslt.vv v0, v12, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1801,11 +1801,11 @@ define @intrinsic_vmsgt_mask_vx_nxv4i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v16, (a0), zero +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vv v25, v28, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vv v13, v16, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1837,11 +1837,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv1i8.i8( @@ -1872,11 +1872,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv2i8.i8( @@ -1907,11 +1907,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv4i8.i8( @@ -1942,11 +1942,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv8i8.i8( @@ -1977,11 +1977,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv16i8.i8( @@ -2012,11 +2012,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv32i8.i8( @@ -2047,11 +2047,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv1i16.i16( @@ -2082,11 +2082,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv2i16.i16( @@ -2117,11 +2117,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv4i16.i16( @@ -2152,11 +2152,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv8i16.i16( @@ -2187,11 +2187,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv16i16.i16( @@ -2222,11 +2222,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv1i32.i32( @@ -2257,11 +2257,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv2i32.i32( @@ -2292,11 +2292,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv4i32.i32( @@ -2327,11 +2327,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv8i32.i32( @@ -2362,11 +2362,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv1i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv1i64.i64( @@ -2397,11 +2397,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv2i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv2i64.i64( @@ -2432,11 +2432,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv4i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll index b0a992aeb093fca82c11447dbe6f6a54c070a3e6..6fc625c8eed6aec80b311e91864fc65d4bbea490 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll @@ -32,11 +32,11 @@ define @intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsgt.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsgt.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsgt.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsgt.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsgt.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsgt.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsgt.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsgt.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsgt.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsgt.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsgt.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsgt.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsgt.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsgt.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsgt.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsgt.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsgt.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsgt.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmsgt.mask.nxv1i8.i8( define @intrinsic_vmsgt_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmsgt.mask.nxv2i8.i8( define @intrinsic_vmsgt_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmsgt.mask.nxv4i8.i8( define @intrinsic_vmsgt_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmsgt.mask.nxv8i8.i8( define @intrinsic_vmsgt_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmsgt.mask.nxv16i8.i8( define @intrinsic_vmsgt_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmsgt.mask.nxv32i8.i8( define @intrinsic_vmsgt_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmsgt.mask.nxv1i16.i16( define @intrinsic_vmsgt_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmsgt.mask.nxv2i16.i16( define @intrinsic_vmsgt_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmsgt.mask.nxv4i16.i16( define @intrinsic_vmsgt_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmsgt.mask.nxv8i16.i16( define @intrinsic_vmsgt_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmsgt.mask.nxv16i16.i16( define @intrinsic_vmsgt_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmsgt.mask.nxv1i32.i32( define @intrinsic_vmsgt_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmsgt.mask.nxv2i32.i32( define @intrinsic_vmsgt_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmsgt.mask.nxv4i32.i32( define @intrinsic_vmsgt_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmsgt.mask.nxv8i32.i32( define @intrinsic_vmsgt_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv8i32.i32( @@ -1672,11 +1672,11 @@ declare @llvm.riscv.vmsgt.mask.nxv1i64.i64( define @intrinsic_vmsgt_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv1i64.i64( @@ -1719,11 +1719,11 @@ declare @llvm.riscv.vmsgt.mask.nxv2i64.i64( define @intrinsic_vmsgt_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv2i64.i64( @@ -1766,11 +1766,11 @@ declare @llvm.riscv.vmsgt.mask.nxv4i64.i64( define @intrinsic_vmsgt_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv4i64.i64( @@ -1801,11 +1801,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv1i8.i8( @@ -1836,11 +1836,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv2i8.i8( @@ -1871,11 +1871,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv4i8.i8( @@ -1906,11 +1906,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv8i8.i8( @@ -1941,11 +1941,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv16i8.i8( @@ -1976,11 +1976,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv32i8.i8( @@ -2011,11 +2011,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv1i16.i16( @@ -2046,11 +2046,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv2i16.i16( @@ -2081,11 +2081,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv4i16.i16( @@ -2116,11 +2116,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv8i16.i16( @@ -2151,11 +2151,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv16i16.i16( @@ -2186,11 +2186,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv1i32.i32( @@ -2221,11 +2221,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv2i32.i32( @@ -2256,11 +2256,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv4i32.i32( @@ -2291,11 +2291,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv8i32.i32( @@ -2326,11 +2326,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv1i64.i64( @@ -2361,11 +2361,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv2i64.i64( @@ -2396,11 +2396,11 @@ entry: define @intrinsic_vmsgt_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgt.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgt.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll index 3b3edb04916d57251077b783805113a698257afa..00c19c1cf1879235b3b33a00d068cee6a1b8c958 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll @@ -32,11 +32,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsgtu.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsgtu.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsgtu.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsgtu.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsgtu.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsgtu.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsgtu.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsgtu.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsgtu.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsgtu.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsgtu.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsgtu.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsgtu.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsgtu.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsgtu.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsgtu.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsgtu.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsgtu.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv1i8.i8( define @intrinsic_vmsgtu_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv2i8.i8( define @intrinsic_vmsgtu_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv4i8.i8( define @intrinsic_vmsgtu_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv8i8.i8( define @intrinsic_vmsgtu_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv16i8.i8( define @intrinsic_vmsgtu_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv32i8.i8( define @intrinsic_vmsgtu_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv1i16.i16( define @intrinsic_vmsgtu_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv2i16.i16( define @intrinsic_vmsgtu_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv4i16.i16( define @intrinsic_vmsgtu_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv8i16.i16( define @intrinsic_vmsgtu_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv16i16.i16( define @intrinsic_vmsgtu_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv1i32.i32( define @intrinsic_vmsgtu_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv2i32.i32( define @intrinsic_vmsgtu_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv4i32.i32( define @intrinsic_vmsgtu_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv8i32.i32( define @intrinsic_vmsgtu_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv8i32.i32( @@ -1655,8 +1655,8 @@ define @intrinsic_vmsgtu_vx_nxv1i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmsltu.vv v0, v25, v8 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1683,11 +1683,11 @@ define @intrinsic_vmsgtu_mask_vx_nxv1i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v11, (a0), zero +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vv v25, v26, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vv v10, v11, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1714,8 +1714,8 @@ define @intrinsic_vmsgtu_vx_nxv2i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmsltu.vv v0, v26, v8 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmsltu.vv v0, v10, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1742,11 +1742,11 @@ define @intrinsic_vmsgtu_mask_vx_nxv2i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vv v25, v26, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vv v11, v12, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1773,8 +1773,8 @@ define @intrinsic_vmsgtu_vx_nxv4i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmsltu.vv v0, v28, v8 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmsltu.vv v0, v12, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1801,11 +1801,11 @@ define @intrinsic_vmsgtu_mask_vx_nxv4i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v16, (a0), zero +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vv v25, v28, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vv v13, v16, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1837,11 +1837,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8( @@ -1872,11 +1872,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8( @@ -1907,11 +1907,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8( @@ -1942,11 +1942,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv8i8.i8( @@ -1977,11 +1977,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv16i8.i8( @@ -2012,11 +2012,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv32i8.i8( @@ -2047,11 +2047,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv1i16.i16( @@ -2082,11 +2082,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv2i16.i16( @@ -2117,11 +2117,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv4i16.i16( @@ -2152,11 +2152,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv8i16.i16( @@ -2187,11 +2187,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv16i16.i16( @@ -2222,11 +2222,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv1i32.i32( @@ -2257,11 +2257,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv2i32.i32( @@ -2292,11 +2292,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv4i32.i32( @@ -2327,11 +2327,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv8i32.i32( @@ -2362,11 +2362,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv1i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv1i64.i64( @@ -2397,11 +2397,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv2i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv2i64.i64( @@ -2432,11 +2432,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv4i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll index b0898d6eaa65605f9ed32c576545fa394f476948..c3f1890c4a34969bd7cc474c4e16d42cb6d24e80 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll @@ -32,11 +32,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsgtu.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsgtu.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsgtu.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsgtu.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsgtu.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsgtu.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsgtu.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsgtu.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsgtu.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsgtu.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsgtu.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsgtu.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsgtu.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsgtu.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsgtu.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsgtu.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsgtu.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsgtu.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv1i8.i8( define @intrinsic_vmsgtu_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv2i8.i8( define @intrinsic_vmsgtu_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv4i8.i8( define @intrinsic_vmsgtu_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv8i8.i8( define @intrinsic_vmsgtu_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv16i8.i8( define @intrinsic_vmsgtu_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv32i8.i8( define @intrinsic_vmsgtu_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv1i16.i16( define @intrinsic_vmsgtu_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv2i16.i16( define @intrinsic_vmsgtu_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv4i16.i16( define @intrinsic_vmsgtu_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv8i16.i16( define @intrinsic_vmsgtu_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv16i16.i16( define @intrinsic_vmsgtu_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv1i32.i32( define @intrinsic_vmsgtu_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv2i32.i32( define @intrinsic_vmsgtu_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv4i32.i32( define @intrinsic_vmsgtu_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv8i32.i32( define @intrinsic_vmsgtu_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv8i32.i32( @@ -1672,11 +1672,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv1i64.i64( define @intrinsic_vmsgtu_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv1i64.i64( @@ -1719,11 +1719,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv2i64.i64( define @intrinsic_vmsgtu_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv2i64.i64( @@ -1766,11 +1766,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv4i64.i64( define @intrinsic_vmsgtu_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv4i64.i64( @@ -1801,11 +1801,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8( @@ -1836,11 +1836,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8( @@ -1871,11 +1871,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8( @@ -1906,11 +1906,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv8i8.i8( @@ -1941,11 +1941,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv16i8.i8( @@ -1976,11 +1976,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv32i8.i8( @@ -2011,11 +2011,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv1i16.i16( @@ -2046,11 +2046,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv2i16.i16( @@ -2081,11 +2081,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv4i16.i16( @@ -2116,11 +2116,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv8i16.i16( @@ -2151,11 +2151,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv16i16.i16( @@ -2186,11 +2186,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv1i32.i32( @@ -2221,11 +2221,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv2i32.i32( @@ -2256,11 +2256,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv4i32.i32( @@ -2291,11 +2291,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv8i32.i32( @@ -2326,11 +2326,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv1i64.i64( @@ -2361,11 +2361,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv2i64.i64( @@ -2396,11 +2396,11 @@ entry: define @intrinsic_vmsgtu_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsgtu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgtu.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll index ccae7ce26129f835fafdab7730bfa1b2534c1982..729a40cc6b87f83bdd050631c6cb0510b62b4bca 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vmsif_m_nxv1i1( %0, i32 %1) ; CHECK-LABEL: intrinsic_vmsif_m_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmsif.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv1i1( @@ -28,11 +28,11 @@ declare @llvm.riscv.vmsif.mask.nxv1i1( define @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1_nxv1i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsif.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv1i1( @@ -51,8 +51,8 @@ define @intrinsic_vmsif_m_nxv2i1( %0, i32 %1) ; CHECK-LABEL: intrinsic_vmsif_m_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmsif.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv2i1( @@ -70,11 +70,11 @@ declare @llvm.riscv.vmsif.mask.nxv2i1( define @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1_nxv2i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsif.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv2i1( @@ -93,8 +93,8 @@ define @intrinsic_vmsif_m_nxv4i1( %0, i32 %1) ; CHECK-LABEL: intrinsic_vmsif_m_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmsif.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv4i1( @@ -112,11 +112,11 @@ declare @llvm.riscv.vmsif.mask.nxv4i1( define @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1_nxv4i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsif.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv4i1( @@ -135,8 +135,8 @@ define @intrinsic_vmsif_m_nxv8i1( %0, i32 %1) ; CHECK-LABEL: intrinsic_vmsif_m_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmsif.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv8i1( @@ -154,11 +154,11 @@ declare @llvm.riscv.vmsif.mask.nxv8i1( define @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1_nxv8i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsif.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv8i1( @@ -177,8 +177,8 @@ define @intrinsic_vmsif_m_nxv16i1( %0, i32 ; CHECK-LABEL: intrinsic_vmsif_m_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmsif.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv16i1( @@ -196,11 +196,11 @@ declare @llvm.riscv.vmsif.mask.nxv16i1( define @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1_nxv16i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsif.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv16i1( @@ -219,8 +219,8 @@ define @intrinsic_vmsif_m_nxv32i1( %0, i32 ; CHECK-LABEL: intrinsic_vmsif_m_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmsif.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv32i1( @@ -238,11 +238,11 @@ declare @llvm.riscv.vmsif.mask.nxv32i1( define @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1_nxv32i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsif.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv32i1( @@ -261,8 +261,8 @@ define @intrinsic_vmsif_m_nxv64i1( %0, i32 ; CHECK-LABEL: intrinsic_vmsif_m_nxv64i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu -; CHECK-NEXT: vmsif.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv64i1( @@ -280,11 +280,11 @@ declare @llvm.riscv.vmsif.mask.nxv64i1( define @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1_nxv64i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsif.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv64i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll index 64f446a9d53ccabbfca95eb1fadd3ca67c438a8a..af2238ec1f24635d2c5cd7d5e2d3fdbdc534eec4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vmsif_m_nxv1i1( %0, i64 %1) ; CHECK-LABEL: intrinsic_vmsif_m_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmsif.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv1i1( @@ -28,11 +28,11 @@ declare @llvm.riscv.vmsif.mask.nxv1i1( define @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1_nxv1i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsif.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv1i1( @@ -51,8 +51,8 @@ define @intrinsic_vmsif_m_nxv2i1( %0, i64 %1) ; CHECK-LABEL: intrinsic_vmsif_m_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmsif.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv2i1( @@ -70,11 +70,11 @@ declare @llvm.riscv.vmsif.mask.nxv2i1( define @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1_nxv2i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsif.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv2i1( @@ -93,8 +93,8 @@ define @intrinsic_vmsif_m_nxv4i1( %0, i64 %1) ; CHECK-LABEL: intrinsic_vmsif_m_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmsif.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv4i1( @@ -112,11 +112,11 @@ declare @llvm.riscv.vmsif.mask.nxv4i1( define @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1_nxv4i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsif.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv4i1( @@ -135,8 +135,8 @@ define @intrinsic_vmsif_m_nxv8i1( %0, i64 %1) ; CHECK-LABEL: intrinsic_vmsif_m_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmsif.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv8i1( @@ -154,11 +154,11 @@ declare @llvm.riscv.vmsif.mask.nxv8i1( define @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1_nxv8i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsif.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv8i1( @@ -177,8 +177,8 @@ define @intrinsic_vmsif_m_nxv16i1( %0, i64 ; CHECK-LABEL: intrinsic_vmsif_m_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmsif.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv16i1( @@ -196,11 +196,11 @@ declare @llvm.riscv.vmsif.mask.nxv16i1( define @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1_nxv16i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsif.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv16i1( @@ -219,8 +219,8 @@ define @intrinsic_vmsif_m_nxv32i1( %0, i64 ; CHECK-LABEL: intrinsic_vmsif_m_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmsif.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv32i1( @@ -238,11 +238,11 @@ declare @llvm.riscv.vmsif.mask.nxv32i1( define @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1_nxv32i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsif.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv32i1( @@ -261,8 +261,8 @@ define @intrinsic_vmsif_m_nxv64i1( %0, i64 ; CHECK-LABEL: intrinsic_vmsif_m_nxv64i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu -; CHECK-NEXT: vmsif.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv64i1( @@ -280,11 +280,11 @@ declare @llvm.riscv.vmsif.mask.nxv64i1( define @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1_nxv64i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsif.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsif.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv64i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll index 44484b0050cc7891f206625ad7825310df8a3e8a..38ee92455a3be01e94ac80402a19a461c85433b8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll @@ -32,11 +32,11 @@ define @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsle.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsle.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsle.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsle.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsle.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsle.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsle.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsle.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsle.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsle.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsle.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsle.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsle.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsle.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsle.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsle.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsle.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsle.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmsle.mask.nxv1i8.i8( define @intrinsic_vmsle_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmsle.mask.nxv2i8.i8( define @intrinsic_vmsle_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmsle.mask.nxv4i8.i8( define @intrinsic_vmsle_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmsle.mask.nxv8i8.i8( define @intrinsic_vmsle_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmsle.mask.nxv16i8.i8( define @intrinsic_vmsle_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmsle.mask.nxv32i8.i8( define @intrinsic_vmsle_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmsle.mask.nxv1i16.i16( define @intrinsic_vmsle_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmsle.mask.nxv2i16.i16( define @intrinsic_vmsle_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmsle.mask.nxv4i16.i16( define @intrinsic_vmsle_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmsle.mask.nxv8i16.i16( define @intrinsic_vmsle_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmsle.mask.nxv16i16.i16( define @intrinsic_vmsle_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmsle.mask.nxv1i32.i32( define @intrinsic_vmsle_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmsle.mask.nxv2i32.i32( define @intrinsic_vmsle_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmsle.mask.nxv4i32.i32( define @intrinsic_vmsle_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmsle.mask.nxv8i32.i32( define @intrinsic_vmsle_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv8i32.i32( @@ -1655,8 +1655,8 @@ define @intrinsic_vmsle_vx_nxv1i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmsle.vv v0, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1683,11 +1683,11 @@ define @intrinsic_vmsle_mask_vx_nxv1i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v11, (a0), zero +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vv v25, v8, v26, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vv v10, v8, v11, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1714,8 +1714,8 @@ define @intrinsic_vmsle_vx_nxv2i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmsle.vv v0, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmsle.vv v0, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1742,11 +1742,11 @@ define @intrinsic_vmsle_mask_vx_nxv2i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vv v25, v8, v26, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vv v11, v8, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1773,8 +1773,8 @@ define @intrinsic_vmsle_vx_nxv4i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmsle.vv v0, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmsle.vv v0, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1801,11 +1801,11 @@ define @intrinsic_vmsle_mask_vx_nxv4i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v16, (a0), zero +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vv v25, v8, v28, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vv v13, v8, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1837,11 +1837,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv1i8.i8( @@ -1872,11 +1872,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv2i8.i8( @@ -1907,11 +1907,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv4i8.i8( @@ -1942,11 +1942,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv8i8.i8( @@ -1977,11 +1977,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv16i8.i8( @@ -2012,11 +2012,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv32i8.i8( @@ -2047,11 +2047,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv1i16.i16( @@ -2082,11 +2082,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv2i16.i16( @@ -2117,11 +2117,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv4i16.i16( @@ -2152,11 +2152,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv8i16.i16( @@ -2187,11 +2187,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv16i16.i16( @@ -2222,11 +2222,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv1i32.i32( @@ -2257,11 +2257,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv2i32.i32( @@ -2292,11 +2292,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv4i32.i32( @@ -2327,11 +2327,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv8i32.i32( @@ -2362,11 +2362,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv1i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv1i64.i64( @@ -2397,11 +2397,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv2i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv2i64.i64( @@ -2432,11 +2432,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv4i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll index be1e77de78d4db974f422050f1e654186e2a5ee5..0f8db99807e1259d7306d5c40efe093d49ef7e45 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll @@ -32,11 +32,11 @@ define @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsle.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsle.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsle.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsle.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsle.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsle.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsle.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsle.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsle.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsle.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsle.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsle.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsle.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsle.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsle.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsle.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsle.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsle.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmsle.mask.nxv1i8.i8( define @intrinsic_vmsle_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmsle.mask.nxv2i8.i8( define @intrinsic_vmsle_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmsle.mask.nxv4i8.i8( define @intrinsic_vmsle_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmsle.mask.nxv8i8.i8( define @intrinsic_vmsle_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmsle.mask.nxv16i8.i8( define @intrinsic_vmsle_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmsle.mask.nxv32i8.i8( define @intrinsic_vmsle_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmsle.mask.nxv1i16.i16( define @intrinsic_vmsle_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmsle.mask.nxv2i16.i16( define @intrinsic_vmsle_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmsle.mask.nxv4i16.i16( define @intrinsic_vmsle_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmsle.mask.nxv8i16.i16( define @intrinsic_vmsle_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmsle.mask.nxv16i16.i16( define @intrinsic_vmsle_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmsle.mask.nxv1i32.i32( define @intrinsic_vmsle_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmsle.mask.nxv2i32.i32( define @intrinsic_vmsle_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmsle.mask.nxv4i32.i32( define @intrinsic_vmsle_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmsle.mask.nxv8i32.i32( define @intrinsic_vmsle_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv8i32.i32( @@ -1672,11 +1672,11 @@ declare @llvm.riscv.vmsle.mask.nxv1i64.i64( define @intrinsic_vmsle_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv1i64.i64( @@ -1719,11 +1719,11 @@ declare @llvm.riscv.vmsle.mask.nxv2i64.i64( define @intrinsic_vmsle_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv2i64.i64( @@ -1766,11 +1766,11 @@ declare @llvm.riscv.vmsle.mask.nxv4i64.i64( define @intrinsic_vmsle_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv4i64.i64( @@ -1801,11 +1801,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv1i8.i8( @@ -1836,11 +1836,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv2i8.i8( @@ -1871,11 +1871,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv4i8.i8( @@ -1906,11 +1906,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv8i8.i8( @@ -1941,11 +1941,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv16i8.i8( @@ -1976,11 +1976,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv32i8.i8( @@ -2011,11 +2011,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv1i16.i16( @@ -2046,11 +2046,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv2i16.i16( @@ -2081,11 +2081,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv4i16.i16( @@ -2116,11 +2116,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv8i16.i16( @@ -2151,11 +2151,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv16i16.i16( @@ -2186,11 +2186,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv1i32.i32( @@ -2221,11 +2221,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv2i32.i32( @@ -2256,11 +2256,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv4i32.i32( @@ -2291,11 +2291,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv8i32.i32( @@ -2326,11 +2326,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv1i64.i64( @@ -2361,11 +2361,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv2i64.i64( @@ -2396,11 +2396,11 @@ entry: define @intrinsic_vmsle_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsle.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll index 6ba9aa1da3d17b159c59003fa991c56130c35fd5..31a4f3f63e9ececd4e4e99dc99d9af7cae9306fe 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll @@ -32,11 +32,11 @@ define @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsleu.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsleu.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsleu.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsleu.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsleu.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsleu.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsleu.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsleu.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsleu.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsleu.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsleu.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsleu.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsleu.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsleu.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsleu.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsleu.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsleu.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsleu.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmsleu.mask.nxv1i8.i8( define @intrinsic_vmsleu_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmsleu.mask.nxv2i8.i8( define @intrinsic_vmsleu_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmsleu.mask.nxv4i8.i8( define @intrinsic_vmsleu_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmsleu.mask.nxv8i8.i8( define @intrinsic_vmsleu_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmsleu.mask.nxv16i8.i8( define @intrinsic_vmsleu_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmsleu.mask.nxv32i8.i8( define @intrinsic_vmsleu_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmsleu.mask.nxv1i16.i16( define @intrinsic_vmsleu_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmsleu.mask.nxv2i16.i16( define @intrinsic_vmsleu_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmsleu.mask.nxv4i16.i16( define @intrinsic_vmsleu_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmsleu.mask.nxv8i16.i16( define @intrinsic_vmsleu_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmsleu.mask.nxv16i16.i16( define @intrinsic_vmsleu_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmsleu.mask.nxv1i32.i32( define @intrinsic_vmsleu_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmsleu.mask.nxv2i32.i32( define @intrinsic_vmsleu_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmsleu.mask.nxv4i32.i32( define @intrinsic_vmsleu_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmsleu.mask.nxv8i32.i32( define @intrinsic_vmsleu_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv8i32.i32( @@ -1655,8 +1655,8 @@ define @intrinsic_vmsleu_vx_nxv1i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmsleu.vv v0, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1683,11 +1683,11 @@ define @intrinsic_vmsleu_mask_vx_nxv1i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v11, (a0), zero +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vv v25, v8, v26, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vv v10, v8, v11, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1714,8 +1714,8 @@ define @intrinsic_vmsleu_vx_nxv2i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmsleu.vv v0, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmsleu.vv v0, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1742,11 +1742,11 @@ define @intrinsic_vmsleu_mask_vx_nxv2i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vv v25, v8, v26, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vv v11, v8, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1773,8 +1773,8 @@ define @intrinsic_vmsleu_vx_nxv4i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmsleu.vv v0, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmsleu.vv v0, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1801,11 +1801,11 @@ define @intrinsic_vmsleu_mask_vx_nxv4i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v16, (a0), zero +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vv v25, v8, v28, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vv v13, v8, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1837,11 +1837,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv1i8.i8( @@ -1872,11 +1872,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv2i8.i8( @@ -1907,11 +1907,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv4i8.i8( @@ -1942,11 +1942,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv8i8.i8( @@ -1977,11 +1977,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv16i8.i8( @@ -2012,11 +2012,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv32i8.i8( @@ -2047,11 +2047,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv1i16.i16( @@ -2082,11 +2082,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv2i16.i16( @@ -2117,11 +2117,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv4i16.i16( @@ -2152,11 +2152,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv8i16.i16( @@ -2187,11 +2187,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv16i16.i16( @@ -2222,11 +2222,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv1i32.i32( @@ -2257,11 +2257,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv2i32.i32( @@ -2292,11 +2292,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv4i32.i32( @@ -2327,11 +2327,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv8i32.i32( @@ -2362,11 +2362,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv1i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv1i64.i64( @@ -2397,11 +2397,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv2i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv2i64.i64( @@ -2432,11 +2432,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv4i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll index 10016dd4110301e2b775d1acbcf8d9eaa694562b..311caf94415c4b62aab3f4460d977596117c03ff 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll @@ -32,11 +32,11 @@ define @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsleu.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsleu.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsleu.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsleu.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsleu.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsleu.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsleu.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsleu.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsleu.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsleu.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsleu.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsleu.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsleu.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsleu.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsleu.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsleu.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsleu.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsleu.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmsleu.mask.nxv1i8.i8( define @intrinsic_vmsleu_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmsleu.mask.nxv2i8.i8( define @intrinsic_vmsleu_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmsleu.mask.nxv4i8.i8( define @intrinsic_vmsleu_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmsleu.mask.nxv8i8.i8( define @intrinsic_vmsleu_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmsleu.mask.nxv16i8.i8( define @intrinsic_vmsleu_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmsleu.mask.nxv32i8.i8( define @intrinsic_vmsleu_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmsleu.mask.nxv1i16.i16( define @intrinsic_vmsleu_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmsleu.mask.nxv2i16.i16( define @intrinsic_vmsleu_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmsleu.mask.nxv4i16.i16( define @intrinsic_vmsleu_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmsleu.mask.nxv8i16.i16( define @intrinsic_vmsleu_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmsleu.mask.nxv16i16.i16( define @intrinsic_vmsleu_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmsleu.mask.nxv1i32.i32( define @intrinsic_vmsleu_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmsleu.mask.nxv2i32.i32( define @intrinsic_vmsleu_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmsleu.mask.nxv4i32.i32( define @intrinsic_vmsleu_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmsleu.mask.nxv8i32.i32( define @intrinsic_vmsleu_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv8i32.i32( @@ -1672,11 +1672,11 @@ declare @llvm.riscv.vmsleu.mask.nxv1i64.i64( define @intrinsic_vmsleu_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv1i64.i64( @@ -1719,11 +1719,11 @@ declare @llvm.riscv.vmsleu.mask.nxv2i64.i64( define @intrinsic_vmsleu_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv2i64.i64( @@ -1766,11 +1766,11 @@ declare @llvm.riscv.vmsleu.mask.nxv4i64.i64( define @intrinsic_vmsleu_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv4i64.i64( @@ -1801,11 +1801,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv1i8.i8( @@ -1836,11 +1836,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv2i8.i8( @@ -1871,11 +1871,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv4i8.i8( @@ -1906,11 +1906,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv8i8.i8( @@ -1941,11 +1941,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv16i8.i8( @@ -1976,11 +1976,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv32i8.i8( @@ -2011,11 +2011,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv1i16.i16( @@ -2046,11 +2046,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv2i16.i16( @@ -2081,11 +2081,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv4i16.i16( @@ -2116,11 +2116,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv8i16.i16( @@ -2151,11 +2151,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv16i16.i16( @@ -2186,11 +2186,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv1i32.i32( @@ -2221,11 +2221,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv2i32.i32( @@ -2256,11 +2256,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv4i32.i32( @@ -2291,11 +2291,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv8i32.i32( @@ -2326,11 +2326,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv1i64.i64( @@ -2361,11 +2361,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv2i64.i64( @@ -2396,11 +2396,11 @@ entry: define @intrinsic_vmsleu_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsleu.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll index cfe08d9816816aa1fc8d352c40b29d9d64ff032e..21cc5b9fbd6df587080a2e1af6cf9d166e91e561 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll @@ -32,11 +32,11 @@ define @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmslt.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmslt.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmslt.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmslt.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmslt.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmslt.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmslt.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmslt.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmslt.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmslt.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmslt.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmslt.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmslt.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmslt.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmslt.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmslt.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmslt.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmslt.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmslt.mask.nxv1i8.i8( define @intrinsic_vmslt_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmslt.mask.nxv2i8.i8( define @intrinsic_vmslt_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmslt.mask.nxv4i8.i8( define @intrinsic_vmslt_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmslt.mask.nxv8i8.i8( define @intrinsic_vmslt_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmslt.mask.nxv16i8.i8( define @intrinsic_vmslt_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmslt.mask.nxv32i8.i8( define @intrinsic_vmslt_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmslt.mask.nxv1i16.i16( define @intrinsic_vmslt_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmslt.mask.nxv2i16.i16( define @intrinsic_vmslt_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmslt.mask.nxv4i16.i16( define @intrinsic_vmslt_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmslt.mask.nxv8i16.i16( define @intrinsic_vmslt_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmslt.mask.nxv16i16.i16( define @intrinsic_vmslt_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmslt.mask.nxv1i32.i32( define @intrinsic_vmslt_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmslt.mask.nxv2i32.i32( define @intrinsic_vmslt_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmslt.mask.nxv4i32.i32( define @intrinsic_vmslt_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmslt.mask.nxv8i32.i32( define @intrinsic_vmslt_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv8i32.i32( @@ -1655,8 +1655,8 @@ define @intrinsic_vmslt_vx_nxv1i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmslt.vv v0, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1683,11 +1683,11 @@ define @intrinsic_vmslt_mask_vx_nxv1i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v11, (a0), zero +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vv v25, v8, v26, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vv v10, v8, v11, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1714,8 +1714,8 @@ define @intrinsic_vmslt_vx_nxv2i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmslt.vv v0, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmslt.vv v0, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1742,11 +1742,11 @@ define @intrinsic_vmslt_mask_vx_nxv2i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vv v25, v8, v26, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vv v11, v8, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1773,8 +1773,8 @@ define @intrinsic_vmslt_vx_nxv4i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmslt.vv v0, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmslt.vv v0, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1801,11 +1801,11 @@ define @intrinsic_vmslt_mask_vx_nxv4i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v16, (a0), zero +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vv v25, v8, v28, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vv v13, v8, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1837,11 +1837,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, -15, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, -15, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv1i8.i8( @@ -1872,11 +1872,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, -13, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, -13, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv2i8.i8( @@ -1907,11 +1907,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, -11, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, -11, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv4i8.i8( @@ -1942,11 +1942,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, -9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, -9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv8i8.i8( @@ -1977,11 +1977,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, -7, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, -7, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv16i8.i8( @@ -2012,11 +2012,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, -5, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, -5, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv32i8.i8( @@ -2047,11 +2047,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, -3, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, -3, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv1i16.i16( @@ -2082,11 +2082,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, -1, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, -1, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv2i16.i16( @@ -2117,11 +2117,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv4i16.i16( @@ -2152,11 +2152,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, 2, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, 2, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv8i16.i16( @@ -2187,11 +2187,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, 4, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, 4, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv16i16.i16( @@ -2222,11 +2222,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 6, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 6, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv1i32.i32( @@ -2257,11 +2257,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv2i32.i32( @@ -2292,11 +2292,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, 10, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, 10, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv4i32.i32( @@ -2327,11 +2327,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, 12, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, 12, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv8i32.i32( @@ -2362,11 +2362,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv1i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv1i64.i64( @@ -2397,11 +2397,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv2i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv2i64.i64( @@ -2432,11 +2432,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv4i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll index 1053315954316bbda8d663501ba6746d0cce7316..65e657fad254a89007c04d79e447611dc41c634e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll @@ -32,11 +32,11 @@ define @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmslt.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmslt.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmslt.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmslt.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmslt.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmslt.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmslt.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmslt.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmslt.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmslt.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmslt.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmslt.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmslt.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmslt.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmslt.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmslt.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmslt.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmslt.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmslt.mask.nxv1i8.i8( define @intrinsic_vmslt_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmslt.mask.nxv2i8.i8( define @intrinsic_vmslt_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmslt.mask.nxv4i8.i8( define @intrinsic_vmslt_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmslt.mask.nxv8i8.i8( define @intrinsic_vmslt_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmslt.mask.nxv16i8.i8( define @intrinsic_vmslt_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmslt.mask.nxv32i8.i8( define @intrinsic_vmslt_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmslt.mask.nxv1i16.i16( define @intrinsic_vmslt_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmslt.mask.nxv2i16.i16( define @intrinsic_vmslt_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmslt.mask.nxv4i16.i16( define @intrinsic_vmslt_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmslt.mask.nxv8i16.i16( define @intrinsic_vmslt_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmslt.mask.nxv16i16.i16( define @intrinsic_vmslt_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmslt.mask.nxv1i32.i32( define @intrinsic_vmslt_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmslt.mask.nxv2i32.i32( define @intrinsic_vmslt_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmslt.mask.nxv4i32.i32( define @intrinsic_vmslt_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmslt.mask.nxv8i32.i32( define @intrinsic_vmslt_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv8i32.i32( @@ -1672,11 +1672,11 @@ declare @llvm.riscv.vmslt.mask.nxv1i64.i64( define @intrinsic_vmslt_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv1i64.i64( @@ -1719,11 +1719,11 @@ declare @llvm.riscv.vmslt.mask.nxv2i64.i64( define @intrinsic_vmslt_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv2i64.i64( @@ -1766,11 +1766,11 @@ declare @llvm.riscv.vmslt.mask.nxv4i64.i64( define @intrinsic_vmslt_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv4i64.i64( @@ -1801,11 +1801,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, -15, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, -15, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv1i8.i8( @@ -1836,11 +1836,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, -13, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, -13, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv2i8.i8( @@ -1871,11 +1871,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, -11, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, -11, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv4i8.i8( @@ -1906,11 +1906,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, -9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, -9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv8i8.i8( @@ -1941,11 +1941,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, -7, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, -7, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv16i8.i8( @@ -1976,11 +1976,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, -5, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, -5, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv32i8.i8( @@ -2011,11 +2011,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, -3, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, -3, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv1i16.i16( @@ -2046,11 +2046,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, -1, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, -1, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv2i16.i16( @@ -2081,11 +2081,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv4i16.i16( @@ -2116,11 +2116,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, 2, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, 2, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv8i16.i16( @@ -2151,11 +2151,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, 4, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, 4, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv16i16.i16( @@ -2186,11 +2186,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 6, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 6, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv1i32.i32( @@ -2221,11 +2221,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv2i32.i32( @@ -2256,11 +2256,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, 10, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, 10, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv4i32.i32( @@ -2291,11 +2291,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, 12, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, 12, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv8i32.i32( @@ -2326,11 +2326,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsle.vi v25, v8, 14, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v10, v8, 14, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv1i64.i64( @@ -2361,11 +2361,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsle.vi v25, v8, -16, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v11, v8, -16, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv2i64.i64( @@ -2396,11 +2396,11 @@ entry: define @intrinsic_vmslt_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsle.vi v25, v8, -14, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsle.vi v13, v8, -14, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmslt.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll index 0ea23255f0e583fd4f44d38fbc83fbb02403b3a2..8ff7727efe307f655775fad17beb0afaef97e4eb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll @@ -32,11 +32,11 @@ define @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsltu.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsltu.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsltu.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsltu.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsltu.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsltu.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsltu.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsltu.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsltu.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsltu.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsltu.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsltu.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsltu.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsltu.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsltu.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsltu.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsltu.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsltu.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmsltu.mask.nxv1i8.i8( define @intrinsic_vmsltu_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmsltu.mask.nxv2i8.i8( define @intrinsic_vmsltu_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmsltu.mask.nxv4i8.i8( define @intrinsic_vmsltu_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmsltu.mask.nxv8i8.i8( define @intrinsic_vmsltu_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmsltu.mask.nxv16i8.i8( define @intrinsic_vmsltu_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmsltu.mask.nxv32i8.i8( define @intrinsic_vmsltu_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmsltu.mask.nxv1i16.i16( define @intrinsic_vmsltu_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmsltu.mask.nxv2i16.i16( define @intrinsic_vmsltu_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmsltu.mask.nxv4i16.i16( define @intrinsic_vmsltu_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmsltu.mask.nxv8i16.i16( define @intrinsic_vmsltu_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmsltu.mask.nxv16i16.i16( define @intrinsic_vmsltu_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmsltu.mask.nxv1i32.i32( define @intrinsic_vmsltu_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmsltu.mask.nxv2i32.i32( define @intrinsic_vmsltu_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmsltu.mask.nxv4i32.i32( define @intrinsic_vmsltu_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmsltu.mask.nxv8i32.i32( define @intrinsic_vmsltu_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv8i32.i32( @@ -1655,8 +1655,8 @@ define @intrinsic_vmsltu_vx_nxv1i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmsltu.vv v0, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1683,11 +1683,11 @@ define @intrinsic_vmsltu_mask_vx_nxv1i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v11, (a0), zero +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vv v25, v8, v26, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vv v10, v8, v11, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1714,8 +1714,8 @@ define @intrinsic_vmsltu_vx_nxv2i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmsltu.vv v0, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmsltu.vv v0, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1742,11 +1742,11 @@ define @intrinsic_vmsltu_mask_vx_nxv2i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vv v25, v8, v26, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vv v11, v8, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1773,8 +1773,8 @@ define @intrinsic_vmsltu_vx_nxv4i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmsltu.vv v0, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmsltu.vv v0, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1801,11 +1801,11 @@ define @intrinsic_vmsltu_mask_vx_nxv4i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v16, (a0), zero +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vv v25, v8, v28, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vv v13, v8, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1837,11 +1837,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, -15, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, -15, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv1i8.i8( @@ -1872,11 +1872,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, -13, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, -13, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv2i8.i8( @@ -1907,11 +1907,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, -11, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, -11, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv4i8.i8( @@ -1942,11 +1942,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, -9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, -9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv8i8.i8( @@ -1977,11 +1977,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, -7, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, -7, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv16i8.i8( @@ -2012,11 +2012,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, -5, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, -5, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv32i8.i8( @@ -2047,11 +2047,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, -3, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, -3, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv1i16.i16( @@ -2082,11 +2082,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vv v25, v8, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vv v10, v8, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv2i16.i16( @@ -2117,11 +2117,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv4i16.i16( @@ -2152,11 +2152,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, 2, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, 2, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv8i16.i16( @@ -2187,11 +2187,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, 4, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, 4, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv16i16.i16( @@ -2222,11 +2222,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 6, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 6, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv1i32.i32( @@ -2257,11 +2257,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv2i32.i32( @@ -2292,11 +2292,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, 10, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, 10, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv4i32.i32( @@ -2327,11 +2327,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, 12, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, 12, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv8i32.i32( @@ -2362,11 +2362,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv1i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 14, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 14, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv1i64.i64( @@ -2397,11 +2397,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv2i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, -16, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, -16, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv2i64.i64( @@ -2432,11 +2432,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv4i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, -14, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, -14, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll index f3d934a409fb1d1a90e66aa36c6427195716d0a4..3ed8e9572e348ac345d9462b1f3c54b30d5e4155 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll @@ -32,11 +32,11 @@ define @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsltu.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsltu.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsltu.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsltu.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsltu.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsltu.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsltu.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsltu.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsltu.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsltu.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsltu.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsltu.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsltu.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsltu.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsltu.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsltu.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsltu.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsltu.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmsltu.mask.nxv1i8.i8( define @intrinsic_vmsltu_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmsltu.mask.nxv2i8.i8( define @intrinsic_vmsltu_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmsltu.mask.nxv4i8.i8( define @intrinsic_vmsltu_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmsltu.mask.nxv8i8.i8( define @intrinsic_vmsltu_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmsltu.mask.nxv16i8.i8( define @intrinsic_vmsltu_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmsltu.mask.nxv32i8.i8( define @intrinsic_vmsltu_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmsltu.mask.nxv1i16.i16( define @intrinsic_vmsltu_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmsltu.mask.nxv2i16.i16( define @intrinsic_vmsltu_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmsltu.mask.nxv4i16.i16( define @intrinsic_vmsltu_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmsltu.mask.nxv8i16.i16( define @intrinsic_vmsltu_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmsltu.mask.nxv16i16.i16( define @intrinsic_vmsltu_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmsltu.mask.nxv1i32.i32( define @intrinsic_vmsltu_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmsltu.mask.nxv2i32.i32( define @intrinsic_vmsltu_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmsltu.mask.nxv4i32.i32( define @intrinsic_vmsltu_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmsltu.mask.nxv8i32.i32( define @intrinsic_vmsltu_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv8i32.i32( @@ -1672,11 +1672,11 @@ declare @llvm.riscv.vmsltu.mask.nxv1i64.i64( define @intrinsic_vmsltu_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv1i64.i64( @@ -1719,11 +1719,11 @@ declare @llvm.riscv.vmsltu.mask.nxv2i64.i64( define @intrinsic_vmsltu_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv2i64.i64( @@ -1766,11 +1766,11 @@ declare @llvm.riscv.vmsltu.mask.nxv4i64.i64( define @intrinsic_vmsltu_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv4i64.i64( @@ -1801,11 +1801,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, -15, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, -15, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv1i8.i8( @@ -1836,11 +1836,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, -13, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, -13, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv2i8.i8( @@ -1871,11 +1871,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, -11, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, -11, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv4i8.i8( @@ -1906,11 +1906,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, -9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, -9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv8i8.i8( @@ -1941,11 +1941,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, -7, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, -7, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv16i8.i8( @@ -1976,11 +1976,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, -5, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, -5, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv32i8.i8( @@ -2011,11 +2011,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, -3, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, -3, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv1i16.i16( @@ -2046,11 +2046,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vv v25, v8, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vv v10, v8, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv2i16.i16( @@ -2081,11 +2081,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv4i16.i16( @@ -2116,11 +2116,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, 2, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, 2, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv8i16.i16( @@ -2151,11 +2151,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, 4, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, 4, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv16i16.i16( @@ -2186,11 +2186,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 6, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 6, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv1i32.i32( @@ -2221,11 +2221,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv2i32.i32( @@ -2256,11 +2256,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, 10, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, 10, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv4i32.i32( @@ -2291,11 +2291,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, 12, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, 12, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv8i32.i32( @@ -2326,11 +2326,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsleu.vi v25, v8, 14, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v10, v8, 14, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv1i64.i64( @@ -2361,11 +2361,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsleu.vi v25, v8, -16, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v11, v8, -16, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv2i64.i64( @@ -2396,11 +2396,11 @@ entry: define @intrinsic_vmsltu_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsleu.vi v25, v8, -14, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsleu.vi v13, v8, -14, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsltu.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll index 316c750e2b2fc8c61de54c3dc61d359c88f2b0b9..a7ffa3ab585409435be2a7a3e26e4b8997a43df2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll @@ -32,11 +32,11 @@ define @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsne.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsne.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsne.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsne.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsne.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsne.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsne.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsne.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsne.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsne.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsne.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsne.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsne.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsne.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsne.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsne.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsne.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsne.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmsne.mask.nxv1i8.i8( define @intrinsic_vmsne_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmsne.mask.nxv2i8.i8( define @intrinsic_vmsne_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmsne.mask.nxv4i8.i8( define @intrinsic_vmsne_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmsne.mask.nxv8i8.i8( define @intrinsic_vmsne_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmsne.mask.nxv16i8.i8( define @intrinsic_vmsne_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmsne.mask.nxv32i8.i8( define @intrinsic_vmsne_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmsne.mask.nxv1i16.i16( define @intrinsic_vmsne_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmsne.mask.nxv2i16.i16( define @intrinsic_vmsne_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmsne.mask.nxv4i16.i16( define @intrinsic_vmsne_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmsne.mask.nxv8i16.i16( define @intrinsic_vmsne_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmsne.mask.nxv16i16.i16( define @intrinsic_vmsne_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmsne.mask.nxv1i32.i32( define @intrinsic_vmsne_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmsne.mask.nxv2i32.i32( define @intrinsic_vmsne_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmsne.mask.nxv4i32.i32( define @intrinsic_vmsne_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmsne.mask.nxv8i32.i32( define @intrinsic_vmsne_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv8i32.i32( @@ -1655,8 +1655,8 @@ define @intrinsic_vmsne_vx_nxv1i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmsne.vv v0, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1683,11 +1683,11 @@ define @intrinsic_vmsne_mask_vx_nxv1i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v11, (a0), zero +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vv v25, v8, v26, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vv v10, v8, v11, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1714,8 +1714,8 @@ define @intrinsic_vmsne_vx_nxv2i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmsne.vv v0, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmsne.vv v0, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1742,11 +1742,11 @@ define @intrinsic_vmsne_mask_vx_nxv2i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vv v25, v8, v26, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vv v11, v8, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1773,8 +1773,8 @@ define @intrinsic_vmsne_vx_nxv4i64_i64( %0, ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmsne.vv v0, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmsne.vv v0, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1801,11 +1801,11 @@ define @intrinsic_vmsne_mask_vx_nxv4i64_i64( ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vlse64.v v16, (a0), zero +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vv v25, v8, v28, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vv v13, v8, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -1837,11 +1837,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv1i8.i8( @@ -1872,11 +1872,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv2i8.i8( @@ -1907,11 +1907,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv4i8.i8( @@ -1942,11 +1942,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv8i8.i8( @@ -1977,11 +1977,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv16i8.i8( @@ -2012,11 +2012,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv32i8.i8( @@ -2047,11 +2047,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv1i16.i16( @@ -2082,11 +2082,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv2i16.i16( @@ -2117,11 +2117,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv4i16.i16( @@ -2152,11 +2152,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv8i16.i16( @@ -2187,11 +2187,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv16i16.i16( @@ -2222,11 +2222,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv1i32.i32( @@ -2257,11 +2257,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv2i32.i32( @@ -2292,11 +2292,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv4i32.i32( @@ -2327,11 +2327,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv8i32.i32( @@ -2362,11 +2362,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv1i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv1i64.i64( @@ -2397,11 +2397,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv2i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv2i64.i64( @@ -2432,11 +2432,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv4i64_i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll index a6ec285e1092e5bc6a325dace5a162fa233d2189..c8143026ea3533e34df31ec2eef1d68a3fcbcb69 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll @@ -32,11 +32,11 @@ define @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8( @llvm.riscv.vmsne.nxv1i8( @@ -84,11 +84,11 @@ define @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8( @llvm.riscv.vmsne.nxv2i8( @@ -136,11 +136,11 @@ define @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8( @llvm.riscv.vmsne.nxv4i8( @@ -188,11 +188,11 @@ define @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8( @llvm.riscv.vmsne.nxv8i8( @@ -240,11 +240,11 @@ define @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8( @llvm.riscv.vmsne.nxv16i8( @@ -292,11 +292,11 @@ define @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8( @llvm.riscv.vmsne.nxv32i8( @@ -344,11 +344,11 @@ define @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16( @llvm.riscv.vmsne.nxv1i16( @@ -396,11 +396,11 @@ define @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16( @llvm.riscv.vmsne.nxv2i16( @@ -448,11 +448,11 @@ define @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16( @llvm.riscv.vmsne.nxv4i16( @@ -500,11 +500,11 @@ define @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16( @llvm.riscv.vmsne.nxv8i16( @@ -552,11 +552,11 @@ define @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16( @llvm.riscv.vmsne.nxv16i16( @@ -604,11 +604,11 @@ define @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32( @llvm.riscv.vmsne.nxv1i32( @@ -656,11 +656,11 @@ define @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32( @llvm.riscv.vmsne.nxv2i32( @@ -708,11 +708,11 @@ define @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32( @llvm.riscv.vmsne.nxv4i32( @@ -760,11 +760,11 @@ define @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32( @llvm.riscv.vmsne.nxv8i32( @@ -812,11 +812,11 @@ define @intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64( @llvm.riscv.vmsne.nxv1i64( @@ -864,11 +864,11 @@ define @intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64( @llvm.riscv.vmsne.nxv2i64( @@ -916,11 +916,11 @@ define @intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64( @llvm.riscv.vmsne.nxv4i64( @@ -967,11 +967,11 @@ declare @llvm.riscv.vmsne.mask.nxv1i8.i8( define @intrinsic_vmsne_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv1i8.i8( @@ -1014,11 +1014,11 @@ declare @llvm.riscv.vmsne.mask.nxv2i8.i8( define @intrinsic_vmsne_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv2i8.i8( @@ -1061,11 +1061,11 @@ declare @llvm.riscv.vmsne.mask.nxv4i8.i8( define @intrinsic_vmsne_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv4i8.i8( @@ -1108,11 +1108,11 @@ declare @llvm.riscv.vmsne.mask.nxv8i8.i8( define @intrinsic_vmsne_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv8i8.i8( @@ -1155,11 +1155,11 @@ declare @llvm.riscv.vmsne.mask.nxv16i8.i8( define @intrinsic_vmsne_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv16i8.i8( @@ -1202,11 +1202,11 @@ declare @llvm.riscv.vmsne.mask.nxv32i8.i8( define @intrinsic_vmsne_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv32i8.i8( @@ -1249,11 +1249,11 @@ declare @llvm.riscv.vmsne.mask.nxv1i16.i16( define @intrinsic_vmsne_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv1i16.i16( @@ -1296,11 +1296,11 @@ declare @llvm.riscv.vmsne.mask.nxv2i16.i16( define @intrinsic_vmsne_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv2i16.i16( @@ -1343,11 +1343,11 @@ declare @llvm.riscv.vmsne.mask.nxv4i16.i16( define @intrinsic_vmsne_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv4i16.i16( @@ -1390,11 +1390,11 @@ declare @llvm.riscv.vmsne.mask.nxv8i16.i16( define @intrinsic_vmsne_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv8i16.i16( @@ -1437,11 +1437,11 @@ declare @llvm.riscv.vmsne.mask.nxv16i16.i16( define @intrinsic_vmsne_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv16i16.i16( @@ -1484,11 +1484,11 @@ declare @llvm.riscv.vmsne.mask.nxv1i32.i32( define @intrinsic_vmsne_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv1i32.i32( @@ -1531,11 +1531,11 @@ declare @llvm.riscv.vmsne.mask.nxv2i32.i32( define @intrinsic_vmsne_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv2i32.i32( @@ -1578,11 +1578,11 @@ declare @llvm.riscv.vmsne.mask.nxv4i32.i32( define @intrinsic_vmsne_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv4i32.i32( @@ -1625,11 +1625,11 @@ declare @llvm.riscv.vmsne.mask.nxv8i32.i32( define @intrinsic_vmsne_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv8i32.i32( @@ -1672,11 +1672,11 @@ declare @llvm.riscv.vmsne.mask.nxv1i64.i64( define @intrinsic_vmsne_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv1i64.i64( @@ -1719,11 +1719,11 @@ declare @llvm.riscv.vmsne.mask.nxv2i64.i64( define @intrinsic_vmsne_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv2i64.i64( @@ -1766,11 +1766,11 @@ declare @llvm.riscv.vmsne.mask.nxv4i64.i64( define @intrinsic_vmsne_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv4i64.i64( @@ -1801,11 +1801,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv1i8.i8( @@ -1836,11 +1836,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv2i8.i8( @@ -1871,11 +1871,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv4i8.i8( @@ -1906,11 +1906,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv8i8.i8( @@ -1941,11 +1941,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv16i8.i8( @@ -1976,11 +1976,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv32i8.i8( @@ -2011,11 +2011,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv1i16.i16( @@ -2046,11 +2046,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv2i16.i16( @@ -2081,11 +2081,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv4i16.i16( @@ -2116,11 +2116,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv8i16.i16( @@ -2151,11 +2151,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv16i16.i16( @@ -2186,11 +2186,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv1i32.i32( @@ -2221,11 +2221,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv2i32.i32( @@ -2256,11 +2256,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv4i32.i32( @@ -2291,11 +2291,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv8i32.i32( @@ -2326,11 +2326,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v10, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv1i64.i64( @@ -2361,11 +2361,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v11, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv2i64.i64( @@ -2396,11 +2396,11 @@ entry: define @intrinsic_vmsne_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 -; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsne.vi v13, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsne.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll index 9dac52abb23664b1eeaa336dd35ab4ae19809c2e..e4c1d4253bf4bbe59d4004dff317261e8a1ba9bd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vmsof_m_nxv1i1( %0, i32 %1) ; CHECK-LABEL: intrinsic_vmsof_m_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmsof.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.nxv1i1( @@ -28,11 +28,11 @@ declare @llvm.riscv.vmsof.mask.nxv1i1( define @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1_nxv1i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsof.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.mask.nxv1i1( @@ -51,8 +51,8 @@ define @intrinsic_vmsof_m_nxv2i1( %0, i32 %1) ; CHECK-LABEL: intrinsic_vmsof_m_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmsof.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.nxv2i1( @@ -70,11 +70,11 @@ declare @llvm.riscv.vmsof.mask.nxv2i1( define @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1_nxv2i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsof.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.mask.nxv2i1( @@ -93,8 +93,8 @@ define @intrinsic_vmsof_m_nxv4i1( %0, i32 %1) ; CHECK-LABEL: intrinsic_vmsof_m_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmsof.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.nxv4i1( @@ -112,11 +112,11 @@ declare @llvm.riscv.vmsof.mask.nxv4i1( define @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1_nxv4i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsof.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.mask.nxv4i1( @@ -135,8 +135,8 @@ define @intrinsic_vmsof_m_nxv8i1( %0, i32 %1) ; CHECK-LABEL: intrinsic_vmsof_m_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmsof.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.nxv8i1( @@ -154,11 +154,11 @@ declare @llvm.riscv.vmsof.mask.nxv8i1( define @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1_nxv8i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsof.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.mask.nxv8i1( @@ -177,8 +177,8 @@ define @intrinsic_vmsof_m_nxv16i1( %0, i32 ; CHECK-LABEL: intrinsic_vmsof_m_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmsof.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.nxv16i1( @@ -196,11 +196,11 @@ declare @llvm.riscv.vmsof.mask.nxv16i1( define @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1_nxv16i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsof.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.mask.nxv16i1( @@ -219,8 +219,8 @@ define @intrinsic_vmsof_m_nxv32i1( %0, i32 ; CHECK-LABEL: intrinsic_vmsof_m_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmsof.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.nxv32i1( @@ -238,11 +238,11 @@ declare @llvm.riscv.vmsof.mask.nxv32i1( define @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1_nxv32i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsof.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.mask.nxv32i1( @@ -261,8 +261,8 @@ define @intrinsic_vmsof_m_nxv64i1( %0, i32 ; CHECK-LABEL: intrinsic_vmsof_m_nxv64i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu -; CHECK-NEXT: vmsof.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.nxv64i1( @@ -280,11 +280,11 @@ declare @llvm.riscv.vmsof.mask.nxv64i1( define @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1_nxv64i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsof.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.mask.nxv64i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll index 90f04745735c21d592bea70b26343ae4c31c99bc..c68110dbb66bf81ae020ed6ddef05cc0eecf2d5f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vmsof_m_nxv1i1( %0, i64 %1) ; CHECK-LABEL: intrinsic_vmsof_m_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmsof.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.nxv1i1( @@ -28,11 +28,11 @@ declare @llvm.riscv.vmsof.mask.nxv1i1( define @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1_nxv1i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsof.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.mask.nxv1i1( @@ -51,8 +51,8 @@ define @intrinsic_vmsof_m_nxv2i1( %0, i64 %1) ; CHECK-LABEL: intrinsic_vmsof_m_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmsof.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.nxv2i1( @@ -70,11 +70,11 @@ declare @llvm.riscv.vmsof.mask.nxv2i1( define @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1_nxv2i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsof.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.mask.nxv2i1( @@ -93,8 +93,8 @@ define @intrinsic_vmsof_m_nxv4i1( %0, i64 %1) ; CHECK-LABEL: intrinsic_vmsof_m_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmsof.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.nxv4i1( @@ -112,11 +112,11 @@ declare @llvm.riscv.vmsof.mask.nxv4i1( define @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1_nxv4i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsof.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.mask.nxv4i1( @@ -135,8 +135,8 @@ define @intrinsic_vmsof_m_nxv8i1( %0, i64 %1) ; CHECK-LABEL: intrinsic_vmsof_m_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmsof.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.nxv8i1( @@ -154,11 +154,11 @@ declare @llvm.riscv.vmsof.mask.nxv8i1( define @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1_nxv8i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsof.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.mask.nxv8i1( @@ -177,8 +177,8 @@ define @intrinsic_vmsof_m_nxv16i1( %0, i64 ; CHECK-LABEL: intrinsic_vmsof_m_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmsof.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.nxv16i1( @@ -196,11 +196,11 @@ declare @llvm.riscv.vmsof.mask.nxv16i1( define @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1_nxv16i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsof.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.mask.nxv16i1( @@ -219,8 +219,8 @@ define @intrinsic_vmsof_m_nxv32i1( %0, i64 ; CHECK-LABEL: intrinsic_vmsof_m_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmsof.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.nxv32i1( @@ -238,11 +238,11 @@ declare @llvm.riscv.vmsof.mask.nxv32i1( define @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1_nxv32i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsof.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.mask.nxv32i1( @@ -261,8 +261,8 @@ define @intrinsic_vmsof_m_nxv64i1( %0, i64 ; CHECK-LABEL: intrinsic_vmsof_m_nxv64i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu -; CHECK-NEXT: vmsof.m v25, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v8, v0 +; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.nxv64i1( @@ -280,11 +280,11 @@ declare @llvm.riscv.vmsof.mask.nxv64i1( define @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1_nxv64i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 -; CHECK-NEXT: vmsof.m v25, v8, v0.t -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmsof.m v10, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsof.mask.nxv64i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll index 8b3023e1627ed23f32256daebe8d863ed87c325d..02564ccc1777a6583892469a1f25d6108f55dfc2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vmul_vx_nxv1i64_nxv1i64_i64( @intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vmul_vx_nxv2i64_nxv2i64_i64( @intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vmul_vx_nxv4i64_nxv4i64_i64( @intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64( @vmul_vx_nxv1i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmul.vv v8, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -716,8 +716,8 @@ define @vmul_vx_nxv2i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmul.vv v8, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -782,8 +782,8 @@ define @vmul_vx_nxv4i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmul.vv v8, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll index 0e52651c1ebd3486d0b2a3981b52826b84405569..bcf43854f94e6ce860a56a8fee829a7637522a08 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll @@ -1001,9 +1001,9 @@ define @vmul_vx_nxv1i64( %va, i64 %b, @vmul_vx_nxv1i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vmul.vv v8, v8, v25 +; RV32-NEXT: vmul.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1079,9 +1079,9 @@ define @vmul_vx_nxv2i64( %va, i64 %b, @vmul_vx_nxv2i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vmul.vv v8, v8, v26 +; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1157,9 +1157,9 @@ define @vmul_vx_nxv4i64( %va, i64 %b, @vmul_vx_nxv4i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vmul.vv v8, v8, v28 +; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll index 9080748139d08c5bf9fb76f46467e7d9994ed388..a9efb2b91566e1e4187179b9f0848d92eb77dd33 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64( @intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64( @intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64( @intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64( @srem_eq_fold_nxv4i8( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 42 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: addi a1, zero, -85 -; CHECK-NEXT: vmacc.vx v25, a1, v8 -; CHECK-NEXT: vsll.vi v26, v25, 7 -; CHECK-NEXT: vsrl.vi v25, v25, 1 -; CHECK-NEXT: vor.vv v25, v25, v26 -; CHECK-NEXT: vmsleu.vx v0, v25, a0 +; CHECK-NEXT: vmacc.vx v9, a1, v8 +; CHECK-NEXT: vsll.vi v8, v9, 7 +; CHECK-NEXT: vsrl.vi v9, v9, 1 +; CHECK-NEXT: vor.vv v8, v9, v8 +; CHECK-NEXT: vmsleu.vx v0, v8, a0 ; CHECK-NEXT: ret %head_six = insertelement undef, i8 6, i32 0 %splat_six = shufflevector %head_six, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll index 791f80f04420321aec91bdcc21b8ce8c47e0773b..a9b03186ba0a290b715842e7af99b9f66754398d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64( @intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64( @intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64( @intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64( @intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64( @intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64( @intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64( @intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64( @intrinsic_vmv.s.x_x_nxv1i64( %0, i6 ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vid.v v26 -; CHECK-NEXT: vmseq.vi v0, v26, 0 -; CHECK-NEXT: vmerge.vvm v8, v8, v25, v0 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vid.v v10 +; CHECK-NEXT: vmseq.vi v0, v10, 0 +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -266,10 +266,10 @@ define @intrinsic_vmv.s.x_x_nxv2i64( %0, i6 ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vid.v v28 -; CHECK-NEXT: vmseq.vi v0, v28, 0 -; CHECK-NEXT: vmerge.vvm v8, v8, v26, v0 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vid.v v12 +; CHECK-NEXT: vmseq.vi v0, v12, 0 +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: @@ -287,10 +287,10 @@ define @intrinsic_vmv.s.x_x_nxv4i64( %0, i6 ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vid.v v12 -; CHECK-NEXT: vmseq.vi v0, v12, 0 -; CHECK-NEXT: vmerge.vvm v8, v8, v28, v0 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vid.v v16 +; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll index e738752df9a264e1ac2caac383089c9726639008..0e2c7a77431fe3b8e6dacb8061030c4b24e17816 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll @@ -242,8 +242,8 @@ define i64 @intrinsic_vmv.x.s_s_nxv1i64( %0) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v8, a0 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v9, v8, a0 +; CHECK-NEXT: vmv.x.s a1, v9 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: @@ -258,8 +258,8 @@ define i64 @intrinsic_vmv.x.s_s_nxv2i64( %0) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; CHECK-NEXT: vsrl.vx v26, v8, a0 -; CHECK-NEXT: vmv.x.s a1, v26 +; CHECK-NEXT: vsrl.vx v10, v8, a0 +; CHECK-NEXT: vmv.x.s a1, v10 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: @@ -274,8 +274,8 @@ define i64 @intrinsic_vmv.x.s_s_nxv4i64( %0) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu -; CHECK-NEXT: vsrl.vx v28, v8, a0 -; CHECK-NEXT: vmv.x.s a1, v28 +; CHECK-NEXT: vsrl.vx v12, v8, a0 +; CHECK-NEXT: vmv.x.s a1, v12 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll index 26a91827a0bc9271223b378aca5ea3cfc8a13e8f..e57b98f1dd5ee478dd637bb12c1f2695c5d934fd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll @@ -145,8 +145,8 @@ define @intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8( @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8( @@ -191,8 +191,8 @@ define @intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8( @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8( @@ -237,8 +237,8 @@ define @intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8( @llvm.riscv.vnclip.nxv32i8.nxv32i16.nxv32i8( @@ -373,8 +373,8 @@ define @intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16( @llvm.riscv.vnclip.nxv4i16.nxv4i32.nxv4i16( @@ -419,8 +419,8 @@ define @intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16( @llvm.riscv.vnclip.nxv8i16.nxv8i32.nxv8i16( @@ -465,8 +465,8 @@ define @intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16( @llvm.riscv.vnclip.nxv16i16.nxv16i32.nxv16i16( @@ -556,8 +556,8 @@ define @intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32( @llvm.riscv.vnclip.nxv2i32.nxv2i64.nxv2i32( @@ -602,8 +602,8 @@ define @intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32( @llvm.riscv.vnclip.nxv4i32.nxv4i64.nxv4i32( @@ -648,8 +648,8 @@ define @intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32( @llvm.riscv.vnclip.nxv8i32.nxv8i64.nxv8i32( @@ -829,8 +829,8 @@ define @intrinsic_vnclip_vx_nxv8i8_nxv8i16( ; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vnclip.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnclip.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnclip.nxv8i8.nxv8i16( @@ -875,8 +875,8 @@ define @intrinsic_vnclip_vx_nxv16i8_nxv16i16( @llvm.riscv.vnclip.nxv16i8.nxv16i16( @@ -921,8 +921,8 @@ define @intrinsic_vnclip_vx_nxv32i8_nxv32i16( @llvm.riscv.vnclip.nxv32i8.nxv32i16( @@ -1057,8 +1057,8 @@ define @intrinsic_vnclip_vx_nxv4i16_nxv4i32( @llvm.riscv.vnclip.nxv4i16.nxv4i32( @@ -1103,8 +1103,8 @@ define @intrinsic_vnclip_vx_nxv8i16_nxv8i32( @llvm.riscv.vnclip.nxv8i16.nxv8i32( @@ -1149,8 +1149,8 @@ define @intrinsic_vnclip_vx_nxv16i16_nxv16i32( @llvm.riscv.vnclip.nxv16i16.nxv16i32( @@ -1240,8 +1240,8 @@ define @intrinsic_vnclip_vx_nxv2i32_nxv2i64( @llvm.riscv.vnclip.nxv2i32.nxv2i64( @@ -1286,8 +1286,8 @@ define @intrinsic_vnclip_vx_nxv4i32_nxv4i64( @llvm.riscv.vnclip.nxv4i32.nxv4i64( @@ -1332,8 +1332,8 @@ define @intrinsic_vnclip_vx_nxv8i32_nxv8i64( @llvm.riscv.vnclip.nxv8i32.nxv8i64( @@ -1469,8 +1469,8 @@ define @intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8( @llvm.riscv.vnclip.nxv8i8.nxv8i16( @@ -1502,8 +1502,8 @@ define @intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8( @llvm.riscv.vnclip.nxv16i8.nxv16i16( @@ -1535,8 +1535,8 @@ define @intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8( @llvm.riscv.vnclip.nxv32i8.nxv32i16( @@ -1632,8 +1632,8 @@ define @intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16( @llvm.riscv.vnclip.nxv4i16.nxv4i32( @@ -1665,8 +1665,8 @@ define @intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16( @llvm.riscv.vnclip.nxv8i16.nxv8i32( @@ -1698,8 +1698,8 @@ define @intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16( @llvm.riscv.vnclip.nxv16i16.nxv16i32( @@ -1763,8 +1763,8 @@ define @intrinsic_vnclip_vi_nxv2i32_nxv2i64_i32( @llvm.riscv.vnclip.nxv2i32.nxv2i64( @@ -1796,8 +1796,8 @@ define @intrinsic_vnclip_vi_nxv4i32_nxv4i64_i32( @llvm.riscv.vnclip.nxv4i32.nxv4i64( @@ -1829,8 +1829,8 @@ define @intrinsic_vnclip_vi_nxv8i32_nxv8i64_i32( @llvm.riscv.vnclip.nxv8i32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll index 2d2b8dd499b384e8d9e7accdea0b4c662a8e2160..21497e0cc7644a8d263bfa5a6989596e4fe5e44b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll @@ -145,8 +145,8 @@ define @intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8( @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8( @@ -191,8 +191,8 @@ define @intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8( @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8( @@ -237,8 +237,8 @@ define @intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8( @llvm.riscv.vnclip.nxv32i8.nxv32i16.nxv32i8( @@ -373,8 +373,8 @@ define @intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16( @llvm.riscv.vnclip.nxv4i16.nxv4i32.nxv4i16( @@ -419,8 +419,8 @@ define @intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16( @llvm.riscv.vnclip.nxv8i16.nxv8i32.nxv8i16( @@ -465,8 +465,8 @@ define @intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16( @llvm.riscv.vnclip.nxv16i16.nxv16i32.nxv16i16( @@ -556,8 +556,8 @@ define @intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32( @llvm.riscv.vnclip.nxv2i32.nxv2i64.nxv2i32( @@ -602,8 +602,8 @@ define @intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32( @llvm.riscv.vnclip.nxv4i32.nxv4i64.nxv4i32( @@ -648,8 +648,8 @@ define @intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32( @llvm.riscv.vnclip.nxv8i32.nxv8i64.nxv8i32( @@ -829,8 +829,8 @@ define @intrinsic_vnclip_vx_nxv8i8_nxv8i16( ; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vnclip.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnclip.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnclip.nxv8i8.nxv8i16( @@ -875,8 +875,8 @@ define @intrinsic_vnclip_vx_nxv16i8_nxv16i16( @llvm.riscv.vnclip.nxv16i8.nxv16i16( @@ -921,8 +921,8 @@ define @intrinsic_vnclip_vx_nxv32i8_nxv32i16( @llvm.riscv.vnclip.nxv32i8.nxv32i16( @@ -1057,8 +1057,8 @@ define @intrinsic_vnclip_vx_nxv4i16_nxv4i32( @llvm.riscv.vnclip.nxv4i16.nxv4i32( @@ -1103,8 +1103,8 @@ define @intrinsic_vnclip_vx_nxv8i16_nxv8i32( @llvm.riscv.vnclip.nxv8i16.nxv8i32( @@ -1149,8 +1149,8 @@ define @intrinsic_vnclip_vx_nxv16i16_nxv16i32( @llvm.riscv.vnclip.nxv16i16.nxv16i32( @@ -1240,8 +1240,8 @@ define @intrinsic_vnclip_vx_nxv2i32_nxv2i64( @llvm.riscv.vnclip.nxv2i32.nxv2i64( @@ -1286,8 +1286,8 @@ define @intrinsic_vnclip_vx_nxv4i32_nxv4i64( @llvm.riscv.vnclip.nxv4i32.nxv4i64( @@ -1332,8 +1332,8 @@ define @intrinsic_vnclip_vx_nxv8i32_nxv8i64( @llvm.riscv.vnclip.nxv8i32.nxv8i64( @@ -1469,8 +1469,8 @@ define @intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8( @llvm.riscv.vnclip.nxv8i8.nxv8i16( @@ -1502,8 +1502,8 @@ define @intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8( @llvm.riscv.vnclip.nxv16i8.nxv16i16( @@ -1535,8 +1535,8 @@ define @intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8( @llvm.riscv.vnclip.nxv32i8.nxv32i16( @@ -1632,8 +1632,8 @@ define @intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16( @llvm.riscv.vnclip.nxv4i16.nxv4i32( @@ -1665,8 +1665,8 @@ define @intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16( @llvm.riscv.vnclip.nxv8i16.nxv8i32( @@ -1698,8 +1698,8 @@ define @intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16( @llvm.riscv.vnclip.nxv16i16.nxv16i32( @@ -1763,8 +1763,8 @@ define @intrinsic_vnclip_vi_nxv2i32_nxv2i64_i32( @llvm.riscv.vnclip.nxv2i32.nxv2i64( @@ -1796,8 +1796,8 @@ define @intrinsic_vnclip_vi_nxv4i32_nxv4i64_i32( @llvm.riscv.vnclip.nxv4i32.nxv4i64( @@ -1829,8 +1829,8 @@ define @intrinsic_vnclip_vi_nxv8i32_nxv8i64_i32( @llvm.riscv.vnclip.nxv8i32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll index f839089ffac3b3e75e11c5ef2423be7ea3d04602..42f4ecf3e4fcfa7b797c88547de16db47c76450b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll @@ -145,8 +145,8 @@ define @intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8( @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8( @@ -191,8 +191,8 @@ define @intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8( @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8( @@ -237,8 +237,8 @@ define @intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8( @llvm.riscv.vnclipu.nxv32i8.nxv32i16.nxv32i8( @@ -373,8 +373,8 @@ define @intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16( @llvm.riscv.vnclipu.nxv4i16.nxv4i32.nxv4i16( @@ -419,8 +419,8 @@ define @intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16( @llvm.riscv.vnclipu.nxv8i16.nxv8i32.nxv8i16( @@ -465,8 +465,8 @@ define @intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16( @llvm.riscv.vnclipu.nxv16i16.nxv16i32.nxv16i16( @@ -556,8 +556,8 @@ define @intrinsic_vnclipu_wv_nxv2i32_nxv2i64_nxv2i32( @llvm.riscv.vnclipu.nxv2i32.nxv2i64.nxv2i32( @@ -602,8 +602,8 @@ define @intrinsic_vnclipu_wv_nxv4i32_nxv4i64_nxv4i32( @llvm.riscv.vnclipu.nxv4i32.nxv4i64.nxv4i32( @@ -648,8 +648,8 @@ define @intrinsic_vnclipu_wv_nxv8i32_nxv8i64_nxv8i32( @llvm.riscv.vnclipu.nxv8i32.nxv8i64.nxv8i32( @@ -829,8 +829,8 @@ define @intrinsic_vnclipu_vx_nxv8i8_nxv8i16( ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vnclipu.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnclipu.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16( @@ -875,8 +875,8 @@ define @intrinsic_vnclipu_vx_nxv16i8_nxv16i16( @llvm.riscv.vnclipu.nxv16i8.nxv16i16( @@ -921,8 +921,8 @@ define @intrinsic_vnclipu_vx_nxv32i8_nxv32i16( @llvm.riscv.vnclipu.nxv32i8.nxv32i16( @@ -1057,8 +1057,8 @@ define @intrinsic_vnclipu_vx_nxv4i16_nxv4i32( @llvm.riscv.vnclipu.nxv4i16.nxv4i32( @@ -1103,8 +1103,8 @@ define @intrinsic_vnclipu_vx_nxv8i16_nxv8i32( @llvm.riscv.vnclipu.nxv8i16.nxv8i32( @@ -1149,8 +1149,8 @@ define @intrinsic_vnclipu_vx_nxv16i16_nxv16i32( @llvm.riscv.vnclipu.nxv16i16.nxv16i32( @@ -1240,8 +1240,8 @@ define @intrinsic_vnclipu_vx_nxv2i32_nxv2i64( @llvm.riscv.vnclipu.nxv2i32.nxv2i64( @@ -1286,8 +1286,8 @@ define @intrinsic_vnclipu_vx_nxv4i32_nxv4i64( @llvm.riscv.vnclipu.nxv4i32.nxv4i64( @@ -1332,8 +1332,8 @@ define @intrinsic_vnclipu_vx_nxv8i32_nxv8i64( @llvm.riscv.vnclipu.nxv8i32.nxv8i64( @@ -1469,8 +1469,8 @@ define @intrinsic_vnclipu_vi_nxv8i8_nxv8i16_i8( @llvm.riscv.vnclipu.nxv8i8.nxv8i16( @@ -1502,8 +1502,8 @@ define @intrinsic_vnclipu_vi_nxv16i8_nxv16i16_i8( @llvm.riscv.vnclipu.nxv16i8.nxv16i16( @@ -1535,8 +1535,8 @@ define @intrinsic_vnclipu_vi_nxv32i8_nxv32i16_i8( @llvm.riscv.vnclipu.nxv32i8.nxv32i16( @@ -1632,8 +1632,8 @@ define @intrinsic_vnclipu_vi_nxv4i16_nxv4i32_i16( @llvm.riscv.vnclipu.nxv4i16.nxv4i32( @@ -1665,8 +1665,8 @@ define @intrinsic_vnclipu_vi_nxv8i16_nxv8i32_i16( @llvm.riscv.vnclipu.nxv8i16.nxv8i32( @@ -1698,8 +1698,8 @@ define @intrinsic_vnclipu_vi_nxv16i16_nxv16i32_i16( @llvm.riscv.vnclipu.nxv16i16.nxv16i32( @@ -1763,8 +1763,8 @@ define @intrinsic_vnclipu_vi_nxv2i32_nxv2i64_i32( @llvm.riscv.vnclipu.nxv2i32.nxv2i64( @@ -1796,8 +1796,8 @@ define @intrinsic_vnclipu_vi_nxv4i32_nxv4i64_i32( @llvm.riscv.vnclipu.nxv4i32.nxv4i64( @@ -1829,8 +1829,8 @@ define @intrinsic_vnclipu_vi_nxv8i32_nxv8i64_i32( @llvm.riscv.vnclipu.nxv8i32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll index 6d85bce2c20e0abdfcadd9c126cc92b391b01cdb..e8e28e5482bdf4d879335cf3b59c3b86f4d1e55e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll @@ -145,8 +145,8 @@ define @intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8( @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8( @@ -191,8 +191,8 @@ define @intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8( @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8( @@ -237,8 +237,8 @@ define @intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8( @llvm.riscv.vnclipu.nxv32i8.nxv32i16.nxv32i8( @@ -373,8 +373,8 @@ define @intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16( @llvm.riscv.vnclipu.nxv4i16.nxv4i32.nxv4i16( @@ -419,8 +419,8 @@ define @intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16( @llvm.riscv.vnclipu.nxv8i16.nxv8i32.nxv8i16( @@ -465,8 +465,8 @@ define @intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16( @llvm.riscv.vnclipu.nxv16i16.nxv16i32.nxv16i16( @@ -556,8 +556,8 @@ define @intrinsic_vnclipu_wv_nxv2i32_nxv2i64_nxv2i32( @llvm.riscv.vnclipu.nxv2i32.nxv2i64.nxv2i32( @@ -602,8 +602,8 @@ define @intrinsic_vnclipu_wv_nxv4i32_nxv4i64_nxv4i32( @llvm.riscv.vnclipu.nxv4i32.nxv4i64.nxv4i32( @@ -648,8 +648,8 @@ define @intrinsic_vnclipu_wv_nxv8i32_nxv8i64_nxv8i32( @llvm.riscv.vnclipu.nxv8i32.nxv8i64.nxv8i32( @@ -829,8 +829,8 @@ define @intrinsic_vnclipu_vx_nxv8i8_nxv8i16( ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vnclipu.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnclipu.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16( @@ -875,8 +875,8 @@ define @intrinsic_vnclipu_vx_nxv16i8_nxv16i16( @llvm.riscv.vnclipu.nxv16i8.nxv16i16( @@ -921,8 +921,8 @@ define @intrinsic_vnclipu_vx_nxv32i8_nxv32i16( @llvm.riscv.vnclipu.nxv32i8.nxv32i16( @@ -1057,8 +1057,8 @@ define @intrinsic_vnclipu_vx_nxv4i16_nxv4i32( @llvm.riscv.vnclipu.nxv4i16.nxv4i32( @@ -1103,8 +1103,8 @@ define @intrinsic_vnclipu_vx_nxv8i16_nxv8i32( @llvm.riscv.vnclipu.nxv8i16.nxv8i32( @@ -1149,8 +1149,8 @@ define @intrinsic_vnclipu_vx_nxv16i16_nxv16i32( @llvm.riscv.vnclipu.nxv16i16.nxv16i32( @@ -1240,8 +1240,8 @@ define @intrinsic_vnclipu_vx_nxv2i32_nxv2i64( @llvm.riscv.vnclipu.nxv2i32.nxv2i64( @@ -1286,8 +1286,8 @@ define @intrinsic_vnclipu_vx_nxv4i32_nxv4i64( @llvm.riscv.vnclipu.nxv4i32.nxv4i64( @@ -1332,8 +1332,8 @@ define @intrinsic_vnclipu_vx_nxv8i32_nxv8i64( @llvm.riscv.vnclipu.nxv8i32.nxv8i64( @@ -1469,8 +1469,8 @@ define @intrinsic_vnclipu_vi_nxv8i8_nxv8i16_i8( @llvm.riscv.vnclipu.nxv8i8.nxv8i16( @@ -1502,8 +1502,8 @@ define @intrinsic_vnclipu_vi_nxv16i8_nxv16i16_i8( @llvm.riscv.vnclipu.nxv16i8.nxv16i16( @@ -1535,8 +1535,8 @@ define @intrinsic_vnclipu_vi_nxv32i8_nxv32i16_i8( @llvm.riscv.vnclipu.nxv32i8.nxv32i16( @@ -1632,8 +1632,8 @@ define @intrinsic_vnclipu_vi_nxv4i16_nxv4i32_i16( @llvm.riscv.vnclipu.nxv4i16.nxv4i32( @@ -1665,8 +1665,8 @@ define @intrinsic_vnclipu_vi_nxv8i16_nxv8i32_i16( @llvm.riscv.vnclipu.nxv8i16.nxv8i32( @@ -1698,8 +1698,8 @@ define @intrinsic_vnclipu_vi_nxv16i16_nxv16i32_i16( @llvm.riscv.vnclipu.nxv16i16.nxv16i32( @@ -1763,8 +1763,8 @@ define @intrinsic_vnclipu_vi_nxv2i32_nxv2i64_i32( @llvm.riscv.vnclipu.nxv2i32.nxv2i64( @@ -1796,8 +1796,8 @@ define @intrinsic_vnclipu_vi_nxv4i32_nxv4i64_i32( @llvm.riscv.vnclipu.nxv4i32.nxv4i64( @@ -1829,8 +1829,8 @@ define @intrinsic_vnclipu_vi_nxv8i32_nxv8i64_i32( @llvm.riscv.vnclipu.nxv8i32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll index 13217aec64f0bc06ead6e4629875d09b99fda650..5ba99c50dc74f4c42e2907349b48afa85bb302f4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll @@ -1533,9 +1533,9 @@ define @intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64( @intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64( @intrinsic_vnmsac_vx_nxv2i64_i64_nxv2i64( @intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64( @intrinsic_vnmsac_vx_nxv4i64_i64_nxv4i64( @intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64( @intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64( @intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64( @intrinsic_vnmsub_vx_nxv2i64_i64_nxv2i64( @intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64( @intrinsic_vnmsub_vx_nxv4i64_i64_nxv4i64( @intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64( @vnmsub_vx_nxv1i64( %va, @vnmsub_vx_nxv2i64( %va, @vnmsub_vx_nxv4i64( %va, @intrinsic_vnsra_wv_nxv8i8_nxv8i16_nxv8i8( @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8( @@ -191,8 +191,8 @@ define @intrinsic_vnsra_wv_nxv16i8_nxv16i16_nxv16i8( @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8( @@ -237,8 +237,8 @@ define @intrinsic_vnsra_wv_nxv32i8_nxv32i16_nxv32i8( @llvm.riscv.vnsra.nxv32i8.nxv32i16.nxv32i8( @@ -373,8 +373,8 @@ define @intrinsic_vnsra_wv_nxv4i16_nxv4i32_nxv4i16( @llvm.riscv.vnsra.nxv4i16.nxv4i32.nxv4i16( @@ -419,8 +419,8 @@ define @intrinsic_vnsra_wv_nxv8i16_nxv8i32_nxv8i16( @llvm.riscv.vnsra.nxv8i16.nxv8i32.nxv8i16( @@ -465,8 +465,8 @@ define @intrinsic_vnsra_wv_nxv16i16_nxv16i32_nxv16i16( @llvm.riscv.vnsra.nxv16i16.nxv16i32.nxv16i16( @@ -556,8 +556,8 @@ define @intrinsic_vnsra_wv_nxv2i32_nxv2i64_nxv2i32( @llvm.riscv.vnsra.nxv2i32.nxv2i64.nxv2i32( @@ -602,8 +602,8 @@ define @intrinsic_vnsra_wv_nxv4i32_nxv4i64_nxv4i32( @llvm.riscv.vnsra.nxv4i32.nxv4i64.nxv4i32( @@ -648,8 +648,8 @@ define @intrinsic_vnsra_wv_nxv8i32_nxv8i64_nxv8i32( @llvm.riscv.vnsra.nxv8i32.nxv8i64.nxv8i32( @@ -829,8 +829,8 @@ define @intrinsic_vnsra_vx_nxv8i8_nxv8i16( % ; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vnsra.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsra.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsra.nxv8i8.nxv8i16( @@ -875,8 +875,8 @@ define @intrinsic_vnsra_vx_nxv16i8_nxv16i16( @llvm.riscv.vnsra.nxv16i8.nxv16i16( @@ -921,8 +921,8 @@ define @intrinsic_vnsra_vx_nxv32i8_nxv32i16( @llvm.riscv.vnsra.nxv32i8.nxv32i16( @@ -1057,8 +1057,8 @@ define @intrinsic_vnsra_vx_nxv4i16_nxv4i32( ; CHECK-LABEL: intrinsic_vnsra_vx_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vnsra.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsra.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsra.nxv4i16.nxv4i32( @@ -1103,8 +1103,8 @@ define @intrinsic_vnsra_vx_nxv8i16_nxv8i32( ; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vnsra.wx v26, v8, a0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsra.wx v12, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsra.nxv8i16.nxv8i32( @@ -1149,8 +1149,8 @@ define @intrinsic_vnsra_vx_nxv16i16_nxv16i32( @llvm.riscv.vnsra.nxv16i16.nxv16i32( @@ -1240,8 +1240,8 @@ define @intrinsic_vnsra_vx_nxv2i32_nxv2i64( ; CHECK-LABEL: intrinsic_vnsra_vx_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vnsra.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsra.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsra.nxv2i32.nxv2i64( @@ -1286,8 +1286,8 @@ define @intrinsic_vnsra_vx_nxv4i32_nxv4i64( ; CHECK-LABEL: intrinsic_vnsra_vx_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vnsra.wx v26, v8, a0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsra.wx v12, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsra.nxv4i32.nxv4i64( @@ -1332,8 +1332,8 @@ define @intrinsic_vnsra_vx_nxv8i32_nxv8i64( ; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vnsra.wx v28, v8, a0 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vnsra.wx v16, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsra.nxv8i32.nxv8i64( @@ -1469,8 +1469,8 @@ define @intrinsic_vnsra_vi_nxv8i8_nxv8i16_i8( @llvm.riscv.vnsra.nxv8i8.nxv8i16( @@ -1502,8 +1502,8 @@ define @intrinsic_vnsra_vi_nxv16i8_nxv16i16_i8( @llvm.riscv.vnsra.nxv16i8.nxv16i16( @@ -1535,8 +1535,8 @@ define @intrinsic_vnsra_vi_nxv32i8_nxv32i16_i8( @llvm.riscv.vnsra.nxv32i8.nxv32i16( @@ -1632,8 +1632,8 @@ define @intrinsic_vnsra_vi_nxv4i16_nxv4i32_i16( @llvm.riscv.vnsra.nxv4i16.nxv4i32( @@ -1665,8 +1665,8 @@ define @intrinsic_vnsra_vi_nxv8i16_nxv8i32_i16( @llvm.riscv.vnsra.nxv8i16.nxv8i32( @@ -1698,8 +1698,8 @@ define @intrinsic_vnsra_vi_nxv16i16_nxv16i32_i16( @llvm.riscv.vnsra.nxv16i16.nxv16i32( @@ -1763,8 +1763,8 @@ define @intrinsic_vnsra_vi_nxv2i32_nxv2i64_i32( @llvm.riscv.vnsra.nxv2i32.nxv2i64( @@ -1796,8 +1796,8 @@ define @intrinsic_vnsra_vi_nxv4i32_nxv4i64_i32( @llvm.riscv.vnsra.nxv4i32.nxv4i64( @@ -1829,8 +1829,8 @@ define @intrinsic_vnsra_vi_nxv8i32_nxv8i64_i32( @llvm.riscv.vnsra.nxv8i32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll index 5cacd53ad1c95f3aa5ee29aa714d5d0817a3ac31..fc1f3f0e8ba1222f4b31bd559e06e44025ba32c7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll @@ -145,8 +145,8 @@ define @intrinsic_vnsra_wv_nxv8i8_nxv8i16_nxv8i8( @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8( @@ -191,8 +191,8 @@ define @intrinsic_vnsra_wv_nxv16i8_nxv16i16_nxv16i8( @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8( @@ -237,8 +237,8 @@ define @intrinsic_vnsra_wv_nxv32i8_nxv32i16_nxv32i8( @llvm.riscv.vnsra.nxv32i8.nxv32i16.nxv32i8( @@ -373,8 +373,8 @@ define @intrinsic_vnsra_wv_nxv4i16_nxv4i32_nxv4i16( @llvm.riscv.vnsra.nxv4i16.nxv4i32.nxv4i16( @@ -419,8 +419,8 @@ define @intrinsic_vnsra_wv_nxv8i16_nxv8i32_nxv8i16( @llvm.riscv.vnsra.nxv8i16.nxv8i32.nxv8i16( @@ -465,8 +465,8 @@ define @intrinsic_vnsra_wv_nxv16i16_nxv16i32_nxv16i16( @llvm.riscv.vnsra.nxv16i16.nxv16i32.nxv16i16( @@ -556,8 +556,8 @@ define @intrinsic_vnsra_wv_nxv2i32_nxv2i64_nxv2i32( @llvm.riscv.vnsra.nxv2i32.nxv2i64.nxv2i32( @@ -602,8 +602,8 @@ define @intrinsic_vnsra_wv_nxv4i32_nxv4i64_nxv4i32( @llvm.riscv.vnsra.nxv4i32.nxv4i64.nxv4i32( @@ -648,8 +648,8 @@ define @intrinsic_vnsra_wv_nxv8i32_nxv8i64_nxv8i32( @llvm.riscv.vnsra.nxv8i32.nxv8i64.nxv8i32( @@ -829,8 +829,8 @@ define @intrinsic_vnsra_vx_nxv8i8_nxv8i16( % ; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vnsra.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsra.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsra.nxv8i8.nxv8i16( @@ -875,8 +875,8 @@ define @intrinsic_vnsra_vx_nxv16i8_nxv16i16( @llvm.riscv.vnsra.nxv16i8.nxv16i16( @@ -921,8 +921,8 @@ define @intrinsic_vnsra_vx_nxv32i8_nxv32i16( @llvm.riscv.vnsra.nxv32i8.nxv32i16( @@ -1057,8 +1057,8 @@ define @intrinsic_vnsra_vx_nxv4i16_nxv4i32( ; CHECK-LABEL: intrinsic_vnsra_vx_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vnsra.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsra.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsra.nxv4i16.nxv4i32( @@ -1103,8 +1103,8 @@ define @intrinsic_vnsra_vx_nxv8i16_nxv8i32( ; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vnsra.wx v26, v8, a0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsra.wx v12, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsra.nxv8i16.nxv8i32( @@ -1149,8 +1149,8 @@ define @intrinsic_vnsra_vx_nxv16i16_nxv16i32( @llvm.riscv.vnsra.nxv16i16.nxv16i32( @@ -1240,8 +1240,8 @@ define @intrinsic_vnsra_vx_nxv2i32_nxv2i64( ; CHECK-LABEL: intrinsic_vnsra_vx_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vnsra.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsra.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsra.nxv2i32.nxv2i64( @@ -1286,8 +1286,8 @@ define @intrinsic_vnsra_vx_nxv4i32_nxv4i64( ; CHECK-LABEL: intrinsic_vnsra_vx_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vnsra.wx v26, v8, a0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsra.wx v12, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsra.nxv4i32.nxv4i64( @@ -1332,8 +1332,8 @@ define @intrinsic_vnsra_vx_nxv8i32_nxv8i64( ; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vnsra.wx v28, v8, a0 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vnsra.wx v16, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsra.nxv8i32.nxv8i64( @@ -1469,8 +1469,8 @@ define @intrinsic_vnsra_vi_nxv8i8_nxv8i16_i8( @llvm.riscv.vnsra.nxv8i8.nxv8i16( @@ -1502,8 +1502,8 @@ define @intrinsic_vnsra_vi_nxv16i8_nxv16i16_i8( @llvm.riscv.vnsra.nxv16i8.nxv16i16( @@ -1535,8 +1535,8 @@ define @intrinsic_vnsra_vi_nxv32i8_nxv32i16_i8( @llvm.riscv.vnsra.nxv32i8.nxv32i16( @@ -1632,8 +1632,8 @@ define @intrinsic_vnsra_vi_nxv4i16_nxv4i32_i16( @llvm.riscv.vnsra.nxv4i16.nxv4i32( @@ -1665,8 +1665,8 @@ define @intrinsic_vnsra_vi_nxv8i16_nxv8i32_i16( @llvm.riscv.vnsra.nxv8i16.nxv8i32( @@ -1698,8 +1698,8 @@ define @intrinsic_vnsra_vi_nxv16i16_nxv16i32_i16( @llvm.riscv.vnsra.nxv16i16.nxv16i32( @@ -1763,8 +1763,8 @@ define @intrinsic_vnsra_vi_nxv2i32_nxv2i64_i32( @llvm.riscv.vnsra.nxv2i32.nxv2i64( @@ -1796,8 +1796,8 @@ define @intrinsic_vnsra_vi_nxv4i32_nxv4i64_i32( @llvm.riscv.vnsra.nxv4i32.nxv4i64( @@ -1829,8 +1829,8 @@ define @intrinsic_vnsra_vi_nxv8i32_nxv8i64_i32( @llvm.riscv.vnsra.nxv8i32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll index b3384d5b0999b6be3bd30c486509983718ed3d2d..2c0330fd2b0f66ad636bbf3bc3f889357e4138b3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll @@ -145,8 +145,8 @@ define @intrinsic_vnsrl_wv_nxv8i8_nxv8i16_nxv8i8( @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8( @@ -191,8 +191,8 @@ define @intrinsic_vnsrl_wv_nxv16i8_nxv16i16_nxv16i8( @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8( @@ -237,8 +237,8 @@ define @intrinsic_vnsrl_wv_nxv32i8_nxv32i16_nxv32i8( @llvm.riscv.vnsrl.nxv32i8.nxv32i16.nxv32i8( @@ -373,8 +373,8 @@ define @intrinsic_vnsrl_wv_nxv4i16_nxv4i32_nxv4i16( @llvm.riscv.vnsrl.nxv4i16.nxv4i32.nxv4i16( @@ -419,8 +419,8 @@ define @intrinsic_vnsrl_wv_nxv8i16_nxv8i32_nxv8i16( @llvm.riscv.vnsrl.nxv8i16.nxv8i32.nxv8i16( @@ -465,8 +465,8 @@ define @intrinsic_vnsrl_wv_nxv16i16_nxv16i32_nxv16i16( @llvm.riscv.vnsrl.nxv16i16.nxv16i32.nxv16i16( @@ -556,8 +556,8 @@ define @intrinsic_vnsrl_wv_nxv2i32_nxv2i64_nxv2i32( @llvm.riscv.vnsrl.nxv2i32.nxv2i64.nxv2i32( @@ -602,8 +602,8 @@ define @intrinsic_vnsrl_wv_nxv4i32_nxv4i64_nxv4i32( @llvm.riscv.vnsrl.nxv4i32.nxv4i64.nxv4i32( @@ -648,8 +648,8 @@ define @intrinsic_vnsrl_wv_nxv8i32_nxv8i64_nxv8i32( @llvm.riscv.vnsrl.nxv8i32.nxv8i64.nxv8i32( @@ -829,8 +829,8 @@ define @intrinsic_vnsrl_vx_nxv8i8_nxv8i16( % ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16( @@ -875,8 +875,8 @@ define @intrinsic_vnsrl_vx_nxv16i8_nxv16i16( @llvm.riscv.vnsrl.nxv16i8.nxv16i16( @@ -921,8 +921,8 @@ define @intrinsic_vnsrl_vx_nxv32i8_nxv32i16( @llvm.riscv.vnsrl.nxv32i8.nxv32i16( @@ -1057,8 +1057,8 @@ define @intrinsic_vnsrl_vx_nxv4i16_nxv4i32( ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsrl.nxv4i16.nxv4i32( @@ -1103,8 +1103,8 @@ define @intrinsic_vnsrl_vx_nxv8i16_nxv8i32( ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wx v26, v8, a0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsrl.wx v12, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsrl.nxv8i16.nxv8i32( @@ -1149,8 +1149,8 @@ define @intrinsic_vnsrl_vx_nxv16i16_nxv16i32( @llvm.riscv.vnsrl.nxv16i16.nxv16i32( @@ -1240,8 +1240,8 @@ define @intrinsic_vnsrl_vx_nxv2i32_nxv2i64( ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vnsrl.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsrl.nxv2i32.nxv2i64( @@ -1286,8 +1286,8 @@ define @intrinsic_vnsrl_vx_nxv4i32_nxv4i64( ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vnsrl.wx v26, v8, a0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsrl.wx v12, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsrl.nxv4i32.nxv4i64( @@ -1332,8 +1332,8 @@ define @intrinsic_vnsrl_vx_nxv8i32_nxv8i64( ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vnsrl.wx v28, v8, a0 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vnsrl.wx v16, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsrl.nxv8i32.nxv8i64( @@ -1469,8 +1469,8 @@ define @intrinsic_vnsrl_vi_nxv8i8_nxv8i16_i8( @llvm.riscv.vnsrl.nxv8i8.nxv8i16( @@ -1502,8 +1502,8 @@ define @intrinsic_vnsrl_vi_nxv16i8_nxv16i16_i8( @llvm.riscv.vnsrl.nxv16i8.nxv16i16( @@ -1535,8 +1535,8 @@ define @intrinsic_vnsrl_vi_nxv32i8_nxv32i16_i8( @llvm.riscv.vnsrl.nxv32i8.nxv32i16( @@ -1632,8 +1632,8 @@ define @intrinsic_vnsrl_vi_nxv4i16_nxv4i32_i16( @llvm.riscv.vnsrl.nxv4i16.nxv4i32( @@ -1665,8 +1665,8 @@ define @intrinsic_vnsrl_vi_nxv8i16_nxv8i32_i16( @llvm.riscv.vnsrl.nxv8i16.nxv8i32( @@ -1698,8 +1698,8 @@ define @intrinsic_vnsrl_vi_nxv16i16_nxv16i32_i16( @llvm.riscv.vnsrl.nxv16i16.nxv16i32( @@ -1763,8 +1763,8 @@ define @intrinsic_vnsrl_vi_nxv2i32_nxv2i64_i32( @llvm.riscv.vnsrl.nxv2i32.nxv2i64( @@ -1796,8 +1796,8 @@ define @intrinsic_vnsrl_vi_nxv4i32_nxv4i64_i32( @llvm.riscv.vnsrl.nxv4i32.nxv4i64( @@ -1829,8 +1829,8 @@ define @intrinsic_vnsrl_vi_nxv8i32_nxv8i64_i32( @llvm.riscv.vnsrl.nxv8i32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll index e1982f72da33652f751528f5a86c36a32347a392..5e453c045e07a65e9f6c7bca5969ed76ed010786 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll @@ -145,8 +145,8 @@ define @intrinsic_vnsrl_wv_nxv8i8_nxv8i16_nxv8i8( @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8( @@ -191,8 +191,8 @@ define @intrinsic_vnsrl_wv_nxv16i8_nxv16i16_nxv16i8( @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8( @@ -237,8 +237,8 @@ define @intrinsic_vnsrl_wv_nxv32i8_nxv32i16_nxv32i8( @llvm.riscv.vnsrl.nxv32i8.nxv32i16.nxv32i8( @@ -373,8 +373,8 @@ define @intrinsic_vnsrl_wv_nxv4i16_nxv4i32_nxv4i16( @llvm.riscv.vnsrl.nxv4i16.nxv4i32.nxv4i16( @@ -419,8 +419,8 @@ define @intrinsic_vnsrl_wv_nxv8i16_nxv8i32_nxv8i16( @llvm.riscv.vnsrl.nxv8i16.nxv8i32.nxv8i16( @@ -465,8 +465,8 @@ define @intrinsic_vnsrl_wv_nxv16i16_nxv16i32_nxv16i16( @llvm.riscv.vnsrl.nxv16i16.nxv16i32.nxv16i16( @@ -556,8 +556,8 @@ define @intrinsic_vnsrl_wv_nxv2i32_nxv2i64_nxv2i32( @llvm.riscv.vnsrl.nxv2i32.nxv2i64.nxv2i32( @@ -602,8 +602,8 @@ define @intrinsic_vnsrl_wv_nxv4i32_nxv4i64_nxv4i32( @llvm.riscv.vnsrl.nxv4i32.nxv4i64.nxv4i32( @@ -648,8 +648,8 @@ define @intrinsic_vnsrl_wv_nxv8i32_nxv8i64_nxv8i32( @llvm.riscv.vnsrl.nxv8i32.nxv8i64.nxv8i32( @@ -829,8 +829,8 @@ define @intrinsic_vnsrl_vx_nxv8i8_nxv8i16( % ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16( @@ -875,8 +875,8 @@ define @intrinsic_vnsrl_vx_nxv16i8_nxv16i16( @llvm.riscv.vnsrl.nxv16i8.nxv16i16( @@ -921,8 +921,8 @@ define @intrinsic_vnsrl_vx_nxv32i8_nxv32i16( @llvm.riscv.vnsrl.nxv32i8.nxv32i16( @@ -1057,8 +1057,8 @@ define @intrinsic_vnsrl_vx_nxv4i16_nxv4i32( ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsrl.nxv4i16.nxv4i32( @@ -1103,8 +1103,8 @@ define @intrinsic_vnsrl_vx_nxv8i16_nxv8i32( ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wx v26, v8, a0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsrl.wx v12, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsrl.nxv8i16.nxv8i32( @@ -1149,8 +1149,8 @@ define @intrinsic_vnsrl_vx_nxv16i16_nxv16i32( @llvm.riscv.vnsrl.nxv16i16.nxv16i32( @@ -1240,8 +1240,8 @@ define @intrinsic_vnsrl_vx_nxv2i32_nxv2i64( ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vnsrl.wx v25, v8, a0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wx v10, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsrl.nxv2i32.nxv2i64( @@ -1286,8 +1286,8 @@ define @intrinsic_vnsrl_vx_nxv4i32_nxv4i64( ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vnsrl.wx v26, v8, a0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsrl.wx v12, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsrl.nxv4i32.nxv4i64( @@ -1332,8 +1332,8 @@ define @intrinsic_vnsrl_vx_nxv8i32_nxv8i64( ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vnsrl.wx v28, v8, a0 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vnsrl.wx v16, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vnsrl.nxv8i32.nxv8i64( @@ -1469,8 +1469,8 @@ define @intrinsic_vnsrl_vi_nxv8i8_nxv8i16_i8( @llvm.riscv.vnsrl.nxv8i8.nxv8i16( @@ -1502,8 +1502,8 @@ define @intrinsic_vnsrl_vi_nxv16i8_nxv16i16_i8( @llvm.riscv.vnsrl.nxv16i8.nxv16i16( @@ -1535,8 +1535,8 @@ define @intrinsic_vnsrl_vi_nxv32i8_nxv32i16_i8( @llvm.riscv.vnsrl.nxv32i8.nxv32i16( @@ -1632,8 +1632,8 @@ define @intrinsic_vnsrl_vi_nxv4i16_nxv4i32_i16( @llvm.riscv.vnsrl.nxv4i16.nxv4i32( @@ -1665,8 +1665,8 @@ define @intrinsic_vnsrl_vi_nxv8i16_nxv8i32_i16( @llvm.riscv.vnsrl.nxv8i16.nxv8i32( @@ -1698,8 +1698,8 @@ define @intrinsic_vnsrl_vi_nxv16i16_nxv16i32_i16( @llvm.riscv.vnsrl.nxv16i16.nxv16i32( @@ -1763,8 +1763,8 @@ define @intrinsic_vnsrl_vi_nxv2i32_nxv2i64_i32( @llvm.riscv.vnsrl.nxv2i32.nxv2i64( @@ -1796,8 +1796,8 @@ define @intrinsic_vnsrl_vi_nxv4i32_nxv4i64_i32( @llvm.riscv.vnsrl.nxv4i32.nxv4i64( @@ -1829,8 +1829,8 @@ define @intrinsic_vnsrl_vi_nxv8i32_nxv8i64_i32( @llvm.riscv.vnsrl.nxv8i32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll index ec2705d0eb7de6ce3b02e386b7d24ab7554c87fe..2550b308ca03978599d2c6b88a21719a9eedf96f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vor_vx_nxv1i64_nxv1i64_i64( @intrinsic_vor_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vor_vx_nxv2i64_nxv2i64_i64( @intrinsic_vor_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vor_vx_nxv4i64_nxv4i64_i64( @intrinsic_vor_mask_vx_nxv4i64_nxv4i64_i64( @vor_vx_nxv1i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vor.vv v8, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -948,8 +948,8 @@ define @vor_vx_nxv2i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vor.vv v8, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -1004,8 +1004,8 @@ define @vor_vx_nxv4i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vor.vv v8, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll index 4a6cc0cf8a07db7dc35ca729a2adbf96973f9cb7..5c08d547204d836eee218d2474820be4776c3438 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll @@ -1495,9 +1495,9 @@ define @vor_vx_nxv1i64( %va, i64 %b, @vor_vx_nxv1i64_unmasked( %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vor.vv v8, v8, v25 +; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1599,9 +1599,9 @@ define @vor_vx_nxv2i64( %va, i64 %b, @vor_vx_nxv2i64_unmasked( %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vor.vv v8, v8, v26 +; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1703,9 +1703,9 @@ define @vor_vx_nxv4i64( %va, i64 %b, @vor_vx_nxv4i64_unmasked( %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vor.vv v8, v8, v28 +; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll index d383790954c128a2c5c77022907cca2451973de0..64295ffc31f55c248605e0f396082dbcd8e02d2b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll @@ -10,15 +10,15 @@ define @vpgather_nxv1i8( %ptrs, @llvm.vp.gather.nxv1i8.nxv1p0i8( %ptrs, %m, i32 %evl) ret %v @@ -30,15 +30,15 @@ define @vpgather_nxv2i8( %ptrs, @llvm.vp.gather.nxv2i8.nxv2p0i8( %ptrs, %m, i32 %evl) ret %v @@ -48,17 +48,17 @@ define @vpgather_nxv2i8_sextload_nxv2i16( % ; RV32-LABEL: vpgather_nxv2i8_sextload_nxv2i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; RV32-NEXT: vsext.vf2 v8, v25 +; RV32-NEXT: vsext.vf2 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_nxv2i8_sextload_nxv2i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; RV64-NEXT: vsext.vf2 v8, v25 +; RV64-NEXT: vsext.vf2 v8, v10 ; RV64-NEXT: ret %v = call @llvm.vp.gather.nxv2i8.nxv2p0i8( %ptrs, %m, i32 %evl) %ev = sext %v to @@ -69,17 +69,17 @@ define @vpgather_nxv2i8_zextload_nxv2i16( % ; RV32-LABEL: vpgather_nxv2i8_zextload_nxv2i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; RV32-NEXT: vzext.vf2 v8, v25 +; RV32-NEXT: vzext.vf2 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_nxv2i8_zextload_nxv2i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; RV64-NEXT: vzext.vf2 v8, v25 +; RV64-NEXT: vzext.vf2 v8, v10 ; RV64-NEXT: ret %v = call @llvm.vp.gather.nxv2i8.nxv2p0i8( %ptrs, %m, i32 %evl) %ev = zext %v to @@ -90,17 +90,17 @@ define @vpgather_nxv2i8_sextload_nxv2i32( % ; RV32-LABEL: vpgather_nxv2i8_sextload_nxv2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV32-NEXT: vsext.vf4 v8, v25 +; RV32-NEXT: vsext.vf4 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_nxv2i8_sextload_nxv2i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV64-NEXT: vsext.vf4 v8, v25 +; RV64-NEXT: vsext.vf4 v8, v10 ; RV64-NEXT: ret %v = call @llvm.vp.gather.nxv2i8.nxv2p0i8( %ptrs, %m, i32 %evl) %ev = sext %v to @@ -111,17 +111,17 @@ define @vpgather_nxv2i8_zextload_nxv2i32( % ; RV32-LABEL: vpgather_nxv2i8_zextload_nxv2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV32-NEXT: vzext.vf4 v8, v25 +; RV32-NEXT: vzext.vf4 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_nxv2i8_zextload_nxv2i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV64-NEXT: vzext.vf4 v8, v25 +; RV64-NEXT: vzext.vf4 v8, v10 ; RV64-NEXT: ret %v = call @llvm.vp.gather.nxv2i8.nxv2p0i8( %ptrs, %m, i32 %evl) %ev = zext %v to @@ -132,17 +132,17 @@ define @vpgather_nxv2i8_sextload_nxv2i64( % ; RV32-LABEL: vpgather_nxv2i8_sextload_nxv2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; RV32-NEXT: vsext.vf8 v8, v25 +; RV32-NEXT: vsext.vf8 v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_nxv2i8_sextload_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; RV64-NEXT: vsext.vf8 v8, v25 +; RV64-NEXT: vsext.vf8 v8, v10 ; RV64-NEXT: ret %v = call @llvm.vp.gather.nxv2i8.nxv2p0i8( %ptrs, %m, i32 %evl) %ev = sext %v to @@ -153,17 +153,17 @@ define @vpgather_nxv2i8_zextload_nxv2i64( % ; RV32-LABEL: vpgather_nxv2i8_zextload_nxv2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; RV32-NEXT: vzext.vf8 v8, v25 +; RV32-NEXT: vzext.vf8 v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_nxv2i8_zextload_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; RV64-NEXT: vzext.vf8 v8, v25 +; RV64-NEXT: vzext.vf8 v8, v10 ; RV64-NEXT: ret %v = call @llvm.vp.gather.nxv2i8.nxv2p0i8( %ptrs, %m, i32 %evl) %ev = zext %v to @@ -176,15 +176,15 @@ define @vpgather_nxv4i8( %ptrs, @llvm.vp.gather.nxv4i8.nxv4p0i8( %ptrs, %m, i32 %evl) ret %v @@ -194,15 +194,15 @@ define @vpgather_truemask_nxv4i8( %ptrs, i32 ; RV32-LABEL: vpgather_truemask_nxv4i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v10, (zero), v8 +; RV32-NEXT: vmv1r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_truemask_nxv4i8: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v12, (zero), v8 +; RV64-NEXT: vmv1r.v v8, v12 ; RV64-NEXT: ret %mhead = insertelement undef, i1 1, i32 0 %mtrue = shufflevector %mhead, undef, zeroinitializer @@ -216,15 +216,15 @@ define @vpgather_nxv8i8( %ptrs, @llvm.vp.gather.nxv8i8.nxv8p0i8( %ptrs, %m, i32 %evl) ret %v @@ -234,9 +234,9 @@ define @vpgather_baseidx_nxv8i8(i8* %base, % ; RV32-LABEL: vpgather_baseidx_nxv8i8: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v8 +; RV32-NEXT: vsext.vf4 v12, v8 ; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_nxv8i8: @@ -257,15 +257,15 @@ define @vpgather_nxv1i16( %ptrs, @llvm.vp.gather.nxv1i16.nxv1p0i16( %ptrs, %m, i32 %evl) ret %v @@ -277,15 +277,15 @@ define @vpgather_nxv2i16( %ptrs, @llvm.vp.gather.nxv2i16.nxv2p0i16( %ptrs, %m, i32 %evl) ret %v @@ -295,17 +295,17 @@ define @vpgather_nxv2i16_sextload_nxv2i32( ; RV32-LABEL: vpgather_nxv2i16_sextload_nxv2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV32-NEXT: vsext.vf2 v8, v25 +; RV32-NEXT: vsext.vf2 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_nxv2i16_sextload_nxv2i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV64-NEXT: vsext.vf2 v8, v25 +; RV64-NEXT: vsext.vf2 v8, v10 ; RV64-NEXT: ret %v = call @llvm.vp.gather.nxv2i16.nxv2p0i16( %ptrs, %m, i32 %evl) %ev = sext %v to @@ -316,17 +316,17 @@ define @vpgather_nxv2i16_zextload_nxv2i32( ; RV32-LABEL: vpgather_nxv2i16_zextload_nxv2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v9, (zero), v8, v0.t ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV32-NEXT: vzext.vf2 v8, v25 +; RV32-NEXT: vzext.vf2 v8, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_nxv2i16_zextload_nxv2i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; RV64-NEXT: vzext.vf2 v8, v25 +; RV64-NEXT: vzext.vf2 v8, v10 ; RV64-NEXT: ret %v = call @llvm.vp.gather.nxv2i16.nxv2p0i16( %ptrs, %m, i32 %evl) %ev = zext %v to @@ -337,17 +337,17 @@ define @vpgather_nxv2i16_sextload_nxv2i64( ; RV32-LABEL: vpgather_nxv2i16_sextload_nxv2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; RV32-NEXT: vsext.vf4 v8, v25 +; RV32-NEXT: vsext.vf4 v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_nxv2i16_sextload_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; RV64-NEXT: vsext.vf4 v8, v25 +; RV64-NEXT: vsext.vf4 v8, v10 ; RV64-NEXT: ret %v = call @llvm.vp.gather.nxv2i16.nxv2p0i16( %ptrs, %m, i32 %evl) %ev = sext %v to @@ -358,17 +358,17 @@ define @vpgather_nxv2i16_zextload_nxv2i64( ; RV32-LABEL: vpgather_nxv2i16_zextload_nxv2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; RV32-NEXT: vzext.vf4 v8, v25 +; RV32-NEXT: vzext.vf4 v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_nxv2i16_zextload_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; RV64-NEXT: vzext.vf4 v8, v25 +; RV64-NEXT: vzext.vf4 v8, v10 ; RV64-NEXT: ret %v = call @llvm.vp.gather.nxv2i16.nxv2p0i16( %ptrs, %m, i32 %evl) %ev = zext %v to @@ -381,15 +381,15 @@ define @vpgather_nxv4i16( %ptrs, @llvm.vp.gather.nxv4i16.nxv4p0i16( %ptrs, %m, i32 %evl) ret %v @@ -399,15 +399,15 @@ define @vpgather_truemask_nxv4i16( %ptrs, ; RV32-LABEL: vpgather_truemask_nxv4i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v10, (zero), v8 +; RV32-NEXT: vmv1r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_truemask_nxv4i16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v12, (zero), v8 +; RV64-NEXT: vmv1r.v v8, v12 ; RV64-NEXT: ret %mhead = insertelement undef, i1 1, i32 0 %mtrue = shufflevector %mhead, undef, zeroinitializer @@ -421,15 +421,15 @@ define @vpgather_nxv8i16( %ptrs, @llvm.vp.gather.nxv8i16.nxv8p0i16( %ptrs, %m, i32 %evl) ret %v @@ -439,10 +439,10 @@ define @vpgather_baseidx_nxv8i8_nxv8i16(i16* %base, @vpgather_baseidx_sext_nxv8i8_nxv8i16(i16* %base, @vpgather_baseidx_zext_nxv8i8_nxv8i16(i16* %base, @vpgather_baseidx_nxv8i16(i16* %base, @vpgather_nxv1i32( %ptrs, @llvm.vp.gather.nxv1i32.nxv1p0i32( %ptrs, %m, i32 %evl) ret %v @@ -560,8 +560,8 @@ define @vpgather_nxv2i32( %ptrs, @llvm.vp.gather.nxv2i32.nxv2p0i32( %ptrs, %m, i32 %evl) ret %v @@ -571,17 +571,17 @@ define @vpgather_nxv2i32_sextload_nxv2i64( ; RV32-LABEL: vpgather_nxv2i32_sextload_nxv2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; RV32-NEXT: vsext.vf2 v8, v25 +; RV32-NEXT: vsext.vf2 v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_nxv2i32_sextload_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; RV64-NEXT: vsext.vf2 v8, v25 +; RV64-NEXT: vsext.vf2 v8, v10 ; RV64-NEXT: ret %v = call @llvm.vp.gather.nxv2i32.nxv2p0i32( %ptrs, %m, i32 %evl) %ev = sext %v to @@ -592,17 +592,17 @@ define @vpgather_nxv2i32_zextload_nxv2i64( ; RV32-LABEL: vpgather_nxv2i32_zextload_nxv2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8, v0.t +; RV32-NEXT: vluxei32.v v10, (zero), v8, v0.t ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; RV32-NEXT: vzext.vf2 v8, v25 +; RV32-NEXT: vzext.vf2 v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_nxv2i32_zextload_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8, v0.t +; RV64-NEXT: vluxei64.v v10, (zero), v8, v0.t ; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; RV64-NEXT: vzext.vf2 v8, v25 +; RV64-NEXT: vzext.vf2 v8, v10 ; RV64-NEXT: ret %v = call @llvm.vp.gather.nxv2i32.nxv2p0i32( %ptrs, %m, i32 %evl) %ev = zext %v to @@ -621,8 +621,8 @@ define @vpgather_nxv4i32( %ptrs, @llvm.vp.gather.nxv4i32.nxv4p0i32( %ptrs, %m, i32 %evl) ret %v @@ -638,8 +638,8 @@ define @vpgather_truemask_nxv4i32( %ptrs, ; RV64-LABEL: vpgather_truemask_nxv4i32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v26, (zero), v8 -; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: vluxei64.v v12, (zero), v8 +; RV64-NEXT: vmv2r.v v8, v12 ; RV64-NEXT: ret %mhead = insertelement undef, i1 1, i32 0 %mtrue = shufflevector %mhead, undef, zeroinitializer @@ -659,8 +659,8 @@ define @vpgather_nxv8i32( %ptrs, @llvm.vp.gather.nxv8i32.nxv8p0i32( %ptrs, %m, i32 %evl) ret %v @@ -670,10 +670,10 @@ define @vpgather_baseidx_nxv8i8_nxv8i32(i32* %base, @vpgather_baseidx_sext_nxv8i8_nxv8i32(i32* %base, @vpgather_baseidx_zext_nxv8i8_nxv8i32(i32* %base, @vpgather_baseidx_nxv8i16_nxv8i32(i32* %base, @vpgather_baseidx_sext_nxv8i16_nxv8i32(i32* %base, @vpgather_baseidx_zext_nxv8i16_nxv8i32(i32* %base, @vpgather_baseidx_nxv8i32(i32* %base, @vpgather_nxv1i64( %ptrs, @vpgather_nxv2i64( %ptrs, @vpgather_nxv4i64( %ptrs, @vpgather_truemask_nxv4i64( %ptrs, ; RV32-LABEL: vpgather_truemask_nxv4i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v28, (zero), v8 -; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: vluxei32.v v12, (zero), v8 +; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_truemask_nxv4i64: @@ -929,10 +929,10 @@ define @vpgather_baseidx_nxv8i8_nxv8i64(i64* %base, @vpgather_baseidx_nxv8i16_nxv8i64(i64* %base, @vpgather_baseidx_nxv8i32_nxv8i64(i64* %base, @vpgather_nxv1f16( %ptrs, @llvm.vp.gather.nxv1f16.nxv1p0f16( %ptrs, %m, i32 %evl) ret %v @@ -1122,15 +1122,15 @@ define @vpgather_nxv2f16( %ptrs, @llvm.vp.gather.nxv2f16.nxv2p0f16( %ptrs, %m, i32 %evl) ret %v @@ -1142,15 +1142,15 @@ define @vpgather_nxv4f16( %ptrs, @llvm.vp.gather.nxv4f16.nxv4p0f16( %ptrs, %m, i32 %evl) ret %v @@ -1160,15 +1160,15 @@ define @vpgather_truemask_nxv4f16( %ptrs ; RV32-LABEL: vpgather_truemask_nxv4f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; RV32-NEXT: vluxei32.v v25, (zero), v8 -; RV32-NEXT: vmv1r.v v8, v25 +; RV32-NEXT: vluxei32.v v10, (zero), v8 +; RV32-NEXT: vmv1r.v v8, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_truemask_nxv4f16: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; RV64-NEXT: vluxei64.v v25, (zero), v8 -; RV64-NEXT: vmv1r.v v8, v25 +; RV64-NEXT: vluxei64.v v12, (zero), v8 +; RV64-NEXT: vmv1r.v v8, v12 ; RV64-NEXT: ret %mhead = insertelement undef, i1 1, i32 0 %mtrue = shufflevector %mhead, undef, zeroinitializer @@ -1182,15 +1182,15 @@ define @vpgather_nxv8f16( %ptrs, @llvm.vp.gather.nxv8f16.nxv8p0f16( %ptrs, %m, i32 %evl) ret %v @@ -1200,10 +1200,10 @@ define @vpgather_baseidx_nxv8i8_nxv8f16(half* %base, @vpgather_baseidx_sext_nxv8i8_nxv8f16(half* %base, @vpgather_baseidx_zext_nxv8i8_nxv8f16(half* %base, @vpgather_baseidx_nxv8f16(half* %base, @vpgather_nxv1f32( %ptrs, @llvm.vp.gather.nxv1f32.nxv1p0f32( %ptrs, %m, i32 %evl) ret %v @@ -1321,8 +1321,8 @@ define @vpgather_nxv2f32( %ptrs, @llvm.vp.gather.nxv2f32.nxv2p0f32( %ptrs, %m, i32 %evl) ret %v @@ -1340,8 +1340,8 @@ define @vpgather_nxv4f32( %ptrs, @llvm.vp.gather.nxv4f32.nxv4p0f32( %ptrs, %m, i32 %evl) ret %v @@ -1357,8 +1357,8 @@ define @vpgather_truemask_nxv4f32( %pt ; RV64-LABEL: vpgather_truemask_nxv4f32: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; RV64-NEXT: vluxei64.v v26, (zero), v8 -; RV64-NEXT: vmv2r.v v8, v26 +; RV64-NEXT: vluxei64.v v12, (zero), v8 +; RV64-NEXT: vmv2r.v v8, v12 ; RV64-NEXT: ret %mhead = insertelement undef, i1 1, i32 0 %mtrue = shufflevector %mhead, undef, zeroinitializer @@ -1378,8 +1378,8 @@ define @vpgather_nxv8f32( %ptrs, @llvm.vp.gather.nxv8f32.nxv8p0f32( %ptrs, %m, i32 %evl) ret %v @@ -1389,10 +1389,10 @@ define @vpgather_baseidx_nxv8i8_nxv8f32(float* %base, @vpgather_baseidx_sext_nxv8i8_nxv8f32(float* %base, ; RV32-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vsext.vf4 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_sext_nxv8i8_nxv8f32: @@ -1436,10 +1436,10 @@ define @vpgather_baseidx_zext_nxv8i8_nxv8f32(float* %base, ; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf4 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vzext.vf4 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f32: @@ -1460,10 +1460,10 @@ define @vpgather_baseidx_nxv8i16_nxv8f32(float* %base, @vpgather_baseidx_sext_nxv8i16_nxv8f32(float* %base, ; RV32-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vsext.vf2 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_sext_nxv8i16_nxv8f32: @@ -1507,10 +1507,10 @@ define @vpgather_baseidx_zext_nxv8i16_nxv8f32(float* %base, ; RV32-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf2 v28, v8 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vzext.vf2 v12, v8 +; RV32-NEXT: vsll.vi v8, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vluxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vluxei32.v v8, (a0), v8, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f32: @@ -1531,9 +1531,9 @@ define @vpgather_baseidx_nxv8f32(float* %base, @vpgather_nxv1f64( %ptrs, @vpgather_nxv2f64( %ptrs, @vpgather_nxv4f64( %ptrs, @vpgather_truemask_nxv4f64( % ; RV32-LABEL: vpgather_truemask_nxv4f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; RV32-NEXT: vluxei32.v v28, (zero), v8 -; RV32-NEXT: vmv4r.v v8, v28 +; RV32-NEXT: vluxei32.v v12, (zero), v8 +; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: ret ; ; RV64-LABEL: vpgather_truemask_nxv4f64: @@ -1648,10 +1648,10 @@ define @vpgather_baseidx_nxv8i8_nxv8f64(double* %base, @vpgather_baseidx_nxv8i16_nxv8f64(double* %base, @vpgather_baseidx_nxv8i32_nxv8f64(double* %base, %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv1i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: vpopc.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vpopc.mask.i32.nxv1i1( @@ -67,10 +67,10 @@ declare i32 @llvm.riscv.vpopc.mask.i32.nxv2i1( define i32 @intrinsic_vpopc_mask_m_i32_nxv2i1( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv2i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: vpopc.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vpopc.mask.i32.nxv2i1( @@ -107,10 +107,10 @@ declare i32 @llvm.riscv.vpopc.mask.i32.nxv4i1( define i32 @intrinsic_vpopc_mask_m_i32_nxv4i1( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv4i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: vpopc.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vpopc.mask.i32.nxv4i1( @@ -147,10 +147,10 @@ declare i32 @llvm.riscv.vpopc.mask.i32.nxv8i1( define i32 @intrinsic_vpopc_mask_m_i32_nxv8i1( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv8i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: vpopc.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vpopc.mask.i32.nxv8i1( @@ -187,10 +187,10 @@ declare i32 @llvm.riscv.vpopc.mask.i32.nxv16i1( define i32 @intrinsic_vpopc_mask_m_i32_nxv16i1( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv16i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: vpopc.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vpopc.mask.i32.nxv16i1( @@ -227,10 +227,10 @@ declare i32 @llvm.riscv.vpopc.mask.i32.nxv32i1( define i32 @intrinsic_vpopc_mask_m_i32_nxv32i1( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv32i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: vpopc.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vpopc.mask.i32.nxv32i1( @@ -267,10 +267,10 @@ declare i32 @llvm.riscv.vpopc.mask.i32.nxv64i1( define i32 @intrinsic_vpopc_mask_m_i32_nxv64i1( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv64i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: vpopc.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vpopc.mask.i32.nxv64i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll index a29d7b3660f0295a4bf893b8270b98fa9ea31db3..10c72e381fb9442d22de93421eb7aa8feead0242 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll @@ -27,10 +27,10 @@ declare i64 @llvm.riscv.vpopc.mask.i64.nxv1i1( define i64 @intrinsic_vpopc_mask_m_i64_nxv1i1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv1i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: vpopc.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv1i1( @@ -67,10 +67,10 @@ declare i64 @llvm.riscv.vpopc.mask.i64.nxv2i1( define i64 @intrinsic_vpopc_mask_m_i64_nxv2i1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv2i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: vpopc.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv2i1( @@ -107,10 +107,10 @@ declare i64 @llvm.riscv.vpopc.mask.i64.nxv4i1( define i64 @intrinsic_vpopc_mask_m_i64_nxv4i1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv4i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: vpopc.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv4i1( @@ -147,10 +147,10 @@ declare i64 @llvm.riscv.vpopc.mask.i64.nxv8i1( define i64 @intrinsic_vpopc_mask_m_i64_nxv8i1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv8i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: vpopc.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv8i1( @@ -187,10 +187,10 @@ declare i64 @llvm.riscv.vpopc.mask.i64.nxv16i1( define i64 @intrinsic_vpopc_mask_m_i64_nxv16i1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv16i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: vpopc.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv16i1( @@ -227,10 +227,10 @@ declare i64 @llvm.riscv.vpopc.mask.i64.nxv32i1( define i64 @intrinsic_vpopc_mask_m_i64_nxv32i1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv32i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: vpopc.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv32i1( @@ -267,10 +267,10 @@ declare i64 @llvm.riscv.vpopc.mask.i64.nxv64i1( define i64 @intrinsic_vpopc_mask_m_i64_nxv64i1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv64i1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: vpopc.m a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv64i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll index c041c3411281d2c185ccd4f3d0c7b0e4893a6b84..c0db7f57a190f96cba1d1a4a9aecae55bc32f426 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll @@ -44,17 +44,17 @@ define void @vpscatter_nxv2i16_truncstore_nxv2i8( %val, %val to call void @llvm.vp.scatter.nxv2i8.nxv2p0i8( %tval, %ptrs, %m, i32 %evl) @@ -65,21 +65,21 @@ define void @vpscatter_nxv2i32_truncstore_nxv2i8( %val, %val to call void @llvm.vp.scatter.nxv2i8.nxv2p0i8( %tval, %ptrs, %m, i32 %evl) @@ -90,25 +90,25 @@ define void @vpscatter_nxv2i64_truncstore_nxv2i8( %val, %val to call void @llvm.vp.scatter.nxv2i8.nxv2p0i8( %tval, %ptrs, %m, i32 %evl) @@ -173,9 +173,9 @@ define void @vpscatter_baseidx_nxv8i8( %val, i8* %base, %val, %val to call void @llvm.vp.scatter.nxv2i16.nxv2p0i16( %tval, %ptrs, %m, i32 %evl) @@ -251,21 +251,21 @@ define void @vpscatter_nxv2i64_truncstore_nxv2i16( %val, %val to call void @llvm.vp.scatter.nxv2i16.nxv2p0i16( %tval, %ptrs, %m, i32 %evl) @@ -330,10 +330,10 @@ define void @vpscatter_baseidx_nxv8i8_nxv8i16( %val, i16* %bas ; RV32-LABEL: vpscatter_baseidx_nxv8i8_nxv8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v10 -; RV32-NEXT: vadd.vv v28, v28, v28 +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vadd.vv v12, v12, v12 ; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_nxv8i8_nxv8i16: @@ -353,10 +353,10 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8i16( %val, i16* ; RV32-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v10 -; RV32-NEXT: vadd.vv v28, v28, v28 +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vadd.vv v12, v12, v12 ; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8i16: @@ -377,10 +377,10 @@ define void @vpscatter_baseidx_zext_nxv8i8_nxv8i16( %val, i16* ; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf4 v28, v10 -; RV32-NEXT: vadd.vv v28, v28, v28 +; RV32-NEXT: vzext.vf4 v12, v10 +; RV32-NEXT: vadd.vv v12, v12, v12 ; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i16: @@ -401,10 +401,10 @@ define void @vpscatter_baseidx_nxv8i16( %val, i16* %base, %val, %val to call void @llvm.vp.scatter.nxv2i32.nxv2p0i32( %tval, %ptrs, %m, i32 %evl) @@ -535,10 +535,10 @@ define void @vpscatter_baseidx_nxv8i8_nxv8i32( %val, i32* %bas ; RV32-LABEL: vpscatter_baseidx_nxv8i8_nxv8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vsext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_nxv8i8_nxv8i32: @@ -558,10 +558,10 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8i32( %val, i32* ; RV32-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vsext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8i32: @@ -582,10 +582,10 @@ define void @vpscatter_baseidx_zext_nxv8i8_nxv8i32( %val, i32* ; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vzext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i32: @@ -606,10 +606,10 @@ define void @vpscatter_baseidx_nxv8i16_nxv8i32( %val, i32* %ba ; RV32-LABEL: vpscatter_baseidx_nxv8i16_nxv8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vsext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_nxv8i16_nxv8i32: @@ -629,10 +629,10 @@ define void @vpscatter_baseidx_sext_nxv8i16_nxv8i32( %val, i32 ; RV32-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vsext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8i32: @@ -653,10 +653,10 @@ define void @vpscatter_baseidx_zext_nxv8i16_nxv8i32( %val, i32 ; RV32-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vzext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i32: @@ -677,9 +677,9 @@ define void @vpscatter_baseidx_nxv8i32( %val, i32* %base, %val, i64* %bas ; RV32-LABEL: vpscatter_baseidx_nxv8i8_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v16 -; RV32-NEXT: vsll.vi v28, v28, 3 +; RV32-NEXT: vsext.vf4 v20, v16 +; RV32-NEXT: vsll.vi v16, v20, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_nxv8i8_nxv8i64: @@ -842,10 +842,10 @@ define void @vpscatter_baseidx_nxv8i16_nxv8i64( %val, i64* %ba ; RV32-LABEL: vpscatter_baseidx_nxv8i16_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v16 -; RV32-NEXT: vsll.vi v28, v28, 3 +; RV32-NEXT: vsext.vf2 v20, v16 +; RV32-NEXT: vsll.vi v16, v20, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_nxv8i16_nxv8i64: @@ -895,9 +895,9 @@ define void @vpscatter_baseidx_nxv8i32_nxv8i64( %val, i64* %ba ; RV32-LABEL: vpscatter_baseidx_nxv8i32_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsll.vi v28, v16, 3 +; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_nxv8i32_nxv8i64: @@ -1050,10 +1050,10 @@ define void @vpscatter_baseidx_nxv8i8_nxv8f16( %val, half* %b ; RV32-LABEL: vpscatter_baseidx_nxv8i8_nxv8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v10 -; RV32-NEXT: vadd.vv v28, v28, v28 +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vadd.vv v12, v12, v12 ; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_nxv8i8_nxv8f16: @@ -1073,10 +1073,10 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8f16( %val, hal ; RV32-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v10 -; RV32-NEXT: vadd.vv v28, v28, v28 +; RV32-NEXT: vsext.vf4 v12, v10 +; RV32-NEXT: vadd.vv v12, v12, v12 ; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8f16: @@ -1097,10 +1097,10 @@ define void @vpscatter_baseidx_zext_nxv8i8_nxv8f16( %val, hal ; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f16: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf4 v28, v10 -; RV32-NEXT: vadd.vv v28, v28, v28 +; RV32-NEXT: vzext.vf4 v12, v10 +; RV32-NEXT: vadd.vv v12, v12, v12 ; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f16: @@ -1121,10 +1121,10 @@ define void @vpscatter_baseidx_nxv8f16( %val, half* %base, %val, float* ; RV32-LABEL: vpscatter_baseidx_nxv8i8_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vsext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_nxv8i8_nxv8f32: @@ -1257,10 +1257,10 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8f32( %val, fl ; RV32-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vsext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_sext_nxv8i8_nxv8f32: @@ -1281,10 +1281,10 @@ define void @vpscatter_baseidx_zext_nxv8i8_nxv8f32( %val, fl ; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf4 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vzext.vf4 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f32: @@ -1305,10 +1305,10 @@ define void @vpscatter_baseidx_nxv8i16_nxv8f32( %val, float* ; RV32-LABEL: vpscatter_baseidx_nxv8i16_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vsext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_nxv8i16_nxv8f32: @@ -1328,10 +1328,10 @@ define void @vpscatter_baseidx_sext_nxv8i16_nxv8f32( %val, f ; RV32-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vsext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_sext_nxv8i16_nxv8f32: @@ -1352,10 +1352,10 @@ define void @vpscatter_baseidx_zext_nxv8i16_nxv8f32( %val, f ; RV32-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vzext.vf2 v28, v12 -; RV32-NEXT: vsll.vi v28, v28, 2 +; RV32-NEXT: vzext.vf2 v16, v12 +; RV32-NEXT: vsll.vi v12, v16, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f32: @@ -1376,9 +1376,9 @@ define void @vpscatter_baseidx_nxv8f32( %val, float* %base, ; RV32-LABEL: vpscatter_baseidx_nxv8f32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsll.vi v28, v12, 2 +; RV32-NEXT: vsll.vi v12, v12, 2 ; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_nxv8f32: @@ -1488,10 +1488,10 @@ define void @vpscatter_baseidx_nxv8i8_nxv8f64( %val, double ; RV32-LABEL: vpscatter_baseidx_nxv8i8_nxv8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf4 v28, v16 -; RV32-NEXT: vsll.vi v28, v28, 3 +; RV32-NEXT: vsext.vf4 v20, v16 +; RV32-NEXT: vsll.vi v16, v20, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_nxv8i8_nxv8f64: @@ -1541,10 +1541,10 @@ define void @vpscatter_baseidx_nxv8i16_nxv8f64( %val, doubl ; RV32-LABEL: vpscatter_baseidx_nxv8i16_nxv8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsext.vf2 v28, v16 -; RV32-NEXT: vsll.vi v28, v28, 3 +; RV32-NEXT: vsext.vf2 v20, v16 +; RV32-NEXT: vsll.vi v16, v20, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_nxv8i16_nxv8f64: @@ -1594,9 +1594,9 @@ define void @vpscatter_baseidx_nxv8i32_nxv8f64( %val, doubl ; RV32-LABEL: vpscatter_baseidx_nxv8i32_nxv8f64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, mu -; RV32-NEXT: vsll.vi v28, v16, 3 +; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; RV32-NEXT: vsoxei32.v v8, (a0), v28, v0.t +; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: ret ; ; RV64-LABEL: vpscatter_baseidx_nxv8i32_nxv8f64: diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll index 07b224f38f155202af5d0c4574a62f43a08d471b..5a27b4384c1f6f93b033b8c57a61fd54add09b75 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll @@ -12,10 +12,10 @@ define half @vreduce_fadd_nxv1f16( %v, half %s) { ; CHECK-NEXT: lui a0, %hi(.LCPI0_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI0_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret %red = call reassoc half @llvm.vector.reduce.fadd.nxv1f16(half %s, %v) @@ -26,10 +26,10 @@ define half @vreduce_ord_fadd_nxv1f16( %v, half %s) { ; CHECK-LABEL: vreduce_ord_fadd_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call half @llvm.vector.reduce.fadd.nxv1f16(half %s, %v) ret half %red @@ -43,10 +43,10 @@ define half @vreduce_fadd_nxv2f16( %v, half %s) { ; CHECK-NEXT: lui a0, %hi(.LCPI2_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret %red = call reassoc half @llvm.vector.reduce.fadd.nxv2f16(half %s, %v) @@ -57,10 +57,10 @@ define half @vreduce_ord_fadd_nxv2f16( %v, half %s) { ; CHECK-LABEL: vreduce_ord_fadd_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call half @llvm.vector.reduce.fadd.nxv2f16(half %s, %v) ret half %red @@ -74,9 +74,9 @@ define half @vreduce_fadd_nxv4f16( %v, half %s) { ; CHECK-NEXT: lui a0, %hi(.LCPI4_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredusum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfmv.v.f v9, ft0 +; CHECK-NEXT: vfredusum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: ret %red = call reassoc half @llvm.vector.reduce.fadd.nxv4f16(half %s, %v) @@ -87,9 +87,9 @@ define half @vreduce_ord_fadd_nxv4f16( %v, half %s) { ; CHECK-LABEL: vreduce_ord_fadd_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfmv.v.f v9, fa0 +; CHECK-NEXT: vfredosum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call half @llvm.vector.reduce.fadd.nxv4f16(half %s, %v) ret half %red @@ -103,10 +103,10 @@ define float @vreduce_fadd_nxv1f32( %v, float %s) { ; CHECK-NEXT: lui a0, %hi(.LCPI6_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret %red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, %v) @@ -117,10 +117,10 @@ define float @vreduce_ord_fadd_nxv1f32( %v, float %s) { ; CHECK-LABEL: vreduce_ord_fadd_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call float @llvm.vector.reduce.fadd.nxv1f32(float %s, %v) ret float %red @@ -134,9 +134,9 @@ define float @vreduce_fadd_nxv2f32( %v, float %s) { ; CHECK-NEXT: lui a0, %hi(.LCPI8_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredusum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfmv.v.f v9, ft0 +; CHECK-NEXT: vfredusum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret %red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, %v) @@ -147,9 +147,9 @@ define float @vreduce_ord_fadd_nxv2f32( %v, float %s) { ; CHECK-LABEL: vreduce_ord_fadd_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfmv.v.f v9, fa0 +; CHECK-NEXT: vfredosum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call float @llvm.vector.reduce.fadd.nxv2f32(float %s, %v) ret float %red @@ -163,10 +163,10 @@ define float @vreduce_fadd_nxv4f32( %v, float %s) { ; CHECK-NEXT: lui a0, %hi(.LCPI10_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: ret %red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, %v) @@ -177,10 +177,10 @@ define float @vreduce_ord_fadd_nxv4f32( %v, float %s) { ; CHECK-LABEL: vreduce_ord_fadd_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call float @llvm.vector.reduce.fadd.nxv4f32(float %s, %v) ret float %red @@ -194,9 +194,9 @@ define double @vreduce_fadd_nxv1f64( %v, double %s) { ; CHECK-NEXT: lui a0, %hi(.LCPI12_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredusum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfmv.v.f v9, ft0 +; CHECK-NEXT: vfredusum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret %red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, %v) @@ -207,9 +207,9 @@ define double @vreduce_ord_fadd_nxv1f64( %v, double %s) { ; CHECK-LABEL: vreduce_ord_fadd_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfmv.v.f v9, fa0 +; CHECK-NEXT: vfredosum.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call double @llvm.vector.reduce.fadd.nxv1f64(double %s, %v) ret double %red @@ -223,10 +223,10 @@ define double @vreduce_fadd_nxv2f64( %v, double %s) { ; CHECK-NEXT: lui a0, %hi(.LCPI14_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI14_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret %red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, %v) @@ -237,10 +237,10 @@ define double @vreduce_ord_fadd_nxv2f64( %v, double %s) { ; CHECK-LABEL: vreduce_ord_fadd_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call double @llvm.vector.reduce.fadd.nxv2f64(double %s, %v) ret double %red @@ -254,10 +254,10 @@ define double @vreduce_fadd_nxv4f64( %v, double %s) { ; CHECK-NEXT: lui a0, %hi(.LCPI16_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI16_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v12, ft0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vfredusum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s ft0, v25 +; CHECK-NEXT: vfredusum.vs v8, v8, v12 +; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: ret %red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, %v) @@ -268,10 +268,10 @@ define double @vreduce_ord_fadd_nxv4f64( %v, double %s) { ; CHECK-LABEL: vreduce_ord_fadd_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, fa0 +; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vfredosum.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredosum.vs v8, v8, v12 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call double @llvm.vector.reduce.fadd.nxv4f64(double %s, %v) ret double %red @@ -285,10 +285,10 @@ define half @vreduce_fmin_nxv1f16( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI18_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI18_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call half @llvm.vector.reduce.fmin.nxv1f16( %v) ret half %red @@ -300,10 +300,10 @@ define half @vreduce_fmin_nxv1f16_nonans( %v) #0 { ; CHECK-NEXT: lui a0, %hi(.LCPI19_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI19_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call nnan half @llvm.vector.reduce.fmin.nxv1f16( %v) ret half %red @@ -315,10 +315,10 @@ define half @vreduce_fmin_nxv1f16_nonans_noinfs( %v) #1 { ; CHECK-NEXT: lui a0, %hi(.LCPI20_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI20_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call nnan ninf half @llvm.vector.reduce.fmin.nxv1f16( %v) ret half %red @@ -332,10 +332,10 @@ define half @vreduce_fmin_nxv2f16( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI21_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI21_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call half @llvm.vector.reduce.fmin.nxv2f16( %v) ret half %red @@ -349,9 +349,9 @@ define half @vreduce_fmin_nxv4f16( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI22_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI22_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfmv.v.f v9, ft0 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call half @llvm.vector.reduce.fmin.nxv4f16( %v) ret half %red @@ -367,10 +367,10 @@ define half @vreduce_fmin_nxv64f16( %v) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call half @llvm.vector.reduce.fmin.nxv64f16( %v) ret half %red @@ -384,10 +384,10 @@ define float @vreduce_fmin_nxv1f32( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI24_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI24_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call float @llvm.vector.reduce.fmin.nxv1f32( %v) ret float %red @@ -399,10 +399,10 @@ define float @vreduce_fmin_nxv1f32_nonans( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI25_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI25_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call nnan float @llvm.vector.reduce.fmin.nxv1f32( %v) ret float %red @@ -414,10 +414,10 @@ define float @vreduce_fmin_nxv1f32_nonans_noinfs( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI26_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI26_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call nnan ninf float @llvm.vector.reduce.fmin.nxv1f32( %v) ret float %red @@ -431,9 +431,9 @@ define float @vreduce_fmin_nxv2f32( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI27_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI27_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfmv.v.f v9, ft0 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call float @llvm.vector.reduce.fmin.nxv2f32( %v) ret float %red @@ -447,10 +447,10 @@ define float @vreduce_fmin_nxv4f32( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI28_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI28_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call float @llvm.vector.reduce.fmin.nxv4f32( %v) ret float %red @@ -466,10 +466,10 @@ define float @vreduce_fmin_nxv32f32( %v) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call float @llvm.vector.reduce.fmin.nxv32f32( %v) ret float %red @@ -483,9 +483,9 @@ define double @vreduce_fmin_nxv1f64( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI30_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI30_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfmv.v.f v9, ft0 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call double @llvm.vector.reduce.fmin.nxv1f64( %v) ret double %red @@ -497,9 +497,9 @@ define double @vreduce_fmin_nxv1f64_nonans( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI31_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI31_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfmv.v.f v9, ft0 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call nnan double @llvm.vector.reduce.fmin.nxv1f64( %v) ret double %red @@ -511,9 +511,9 @@ define double @vreduce_fmin_nxv1f64_nonans_noinfs( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI32_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI32_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfmv.v.f v9, ft0 +; CHECK-NEXT: vfredmin.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call nnan ninf double @llvm.vector.reduce.fmin.nxv1f64( %v) ret double %red @@ -527,10 +527,10 @@ define double @vreduce_fmin_nxv2f64( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI33_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI33_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call double @llvm.vector.reduce.fmin.nxv2f64( %v) ret double %red @@ -544,10 +544,10 @@ define double @vreduce_fmin_nxv4f64( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI34_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI34_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v12, ft0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v12 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call double @llvm.vector.reduce.fmin.nxv4f64( %v) ret double %red @@ -563,10 +563,10 @@ define double @vreduce_fmin_nxv16f64( %v) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vfredmin.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmin.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call double @llvm.vector.reduce.fmin.nxv16f64( %v) ret double %red @@ -580,10 +580,10 @@ define half @vreduce_fmax_nxv1f16( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI36_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI36_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call half @llvm.vector.reduce.fmax.nxv1f16( %v) ret half %red @@ -595,10 +595,10 @@ define half @vreduce_fmax_nxv1f16_nonans( %v) #0 { ; CHECK-NEXT: lui a0, %hi(.LCPI37_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI37_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call nnan half @llvm.vector.reduce.fmax.nxv1f16( %v) ret half %red @@ -610,10 +610,10 @@ define half @vreduce_fmax_nxv1f16_nonans_noinfs( %v) #1 { ; CHECK-NEXT: lui a0, %hi(.LCPI38_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI38_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call nnan ninf half @llvm.vector.reduce.fmax.nxv1f16( %v) ret half %red @@ -627,10 +627,10 @@ define half @vreduce_fmax_nxv2f16( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI39_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI39_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call half @llvm.vector.reduce.fmax.nxv2f16( %v) ret half %red @@ -644,9 +644,9 @@ define half @vreduce_fmax_nxv4f16( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI40_0) ; CHECK-NEXT: flh ft0, %lo(.LCPI40_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfmv.v.f v9, ft0 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call half @llvm.vector.reduce.fmax.nxv4f16( %v) ret half %red @@ -662,10 +662,10 @@ define half @vreduce_fmax_nxv64f16( %v) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call half @llvm.vector.reduce.fmax.nxv64f16( %v) ret half %red @@ -679,10 +679,10 @@ define float @vreduce_fmax_nxv1f32( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI42_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI42_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call float @llvm.vector.reduce.fmax.nxv1f32( %v) ret float %red @@ -694,10 +694,10 @@ define float @vreduce_fmax_nxv1f32_nonans( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI43_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI43_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call nnan float @llvm.vector.reduce.fmax.nxv1f32( %v) ret float %red @@ -709,10 +709,10 @@ define float @vreduce_fmax_nxv1f32_nonans_noinfs( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI44_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI44_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call nnan ninf float @llvm.vector.reduce.fmax.nxv1f32( %v) ret float %red @@ -726,9 +726,9 @@ define float @vreduce_fmax_nxv2f32( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI45_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI45_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfmv.v.f v9, ft0 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call float @llvm.vector.reduce.fmax.nxv2f32( %v) ret float %red @@ -742,10 +742,10 @@ define float @vreduce_fmax_nxv4f32( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI46_0) ; CHECK-NEXT: flw ft0, %lo(.LCPI46_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call float @llvm.vector.reduce.fmax.nxv4f32( %v) ret float %red @@ -761,10 +761,10 @@ define float @vreduce_fmax_nxv32f32( %v) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call float @llvm.vector.reduce.fmax.nxv32f32( %v) ret float %red @@ -778,9 +778,9 @@ define double @vreduce_fmax_nxv1f64( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI48_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI48_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfmv.v.f v9, ft0 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call double @llvm.vector.reduce.fmax.nxv1f64( %v) ret double %red @@ -792,9 +792,9 @@ define double @vreduce_fmax_nxv1f64_nonans( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI49_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI49_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfmv.v.f v9, ft0 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call nnan double @llvm.vector.reduce.fmax.nxv1f64( %v) ret double %red @@ -806,9 +806,9 @@ define double @vreduce_fmax_nxv1f64_nonans_noinfs( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI50_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI50_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfmv.v.f v9, ft0 +; CHECK-NEXT: vfredmax.vs v8, v8, v9 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call nnan ninf double @llvm.vector.reduce.fmax.nxv1f64( %v) ret double %red @@ -822,10 +822,10 @@ define double @vreduce_fmax_nxv2f64( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI51_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI51_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call double @llvm.vector.reduce.fmax.nxv2f64( %v) ret double %red @@ -839,10 +839,10 @@ define double @vreduce_fmax_nxv4f64( %v) { ; CHECK-NEXT: lui a0, %hi(.LCPI52_0) ; CHECK-NEXT: fld ft0, %lo(.LCPI52_0)(a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v12, ft0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v12 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call double @llvm.vector.reduce.fmax.nxv4f64( %v) ret double %red @@ -858,10 +858,10 @@ define double @vreduce_fmax_nxv16f64( %v) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vfmv.v.f v25, ft0 +; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vfredmax.vs v25, v8, v25 -; CHECK-NEXT: vfmv.f.s fa0, v25 +; CHECK-NEXT: vfredmax.vs v8, v8, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %red = call double @llvm.vector.reduce.fmax.nxv16f64( %v) ret double %red diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll index 588c97231504d5232eac026a09d30f67e7d75e24..74861743998c69b20bcd721fc3db7886d39cae50 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll @@ -10,10 +10,10 @@ define half @vpreduce_fadd_nxv1f16(half %s, %v, %v, %m, i32 %evl) ret half %r @@ -23,10 +23,10 @@ define half @vpreduce_ord_fadd_nxv1f16(half %s, %v, %v, %m, i32 %evl) ret half %r @@ -38,10 +38,10 @@ define half @vpreduce_fadd_nxv2f16(half %s, %v, %v, %m, i32 %evl) ret half %r @@ -51,10 +51,10 @@ define half @vpreduce_ord_fadd_nxv2f16(half %s, %v, %v, %m, i32 %evl) ret half %r @@ -66,10 +66,10 @@ define half @vpreduce_fadd_nxv4f16(half %s, %v, %v, %m, i32 %evl) ret half %r @@ -79,10 +79,10 @@ define half @vpreduce_ord_fadd_nxv4f16(half %s, %v, %v, %m, i32 %evl) ret half %r @@ -94,10 +94,10 @@ define float @vpreduce_fadd_nxv1f32(float %s, %v, %v, %m, i32 %evl) ret float %r @@ -107,10 +107,10 @@ define float @vpreduce_ord_fadd_nxv1f32(float %s, %v, %v, %m, i32 %evl) ret float %r @@ -122,10 +122,10 @@ define float @vpreduce_fadd_nxv2f32(float %s, %v, %v, %m, i32 %evl) ret float %r @@ -135,10 +135,10 @@ define float @vpreduce_ord_fadd_nxv2f32(float %s, %v, %v, %m, i32 %evl) ret float %r @@ -150,10 +150,10 @@ define float @vpreduce_fadd_nxv4f32(float %s, %v, %v, %m, i32 %evl) ret float %r @@ -163,10 +163,10 @@ define float @vpreduce_ord_fadd_nxv4f32(float %s, %v, %v, %m, i32 %evl) ret float %r @@ -178,10 +178,10 @@ define double @vpreduce_fadd_nxv1f64(double %s, %v, %v, %m, i32 %evl) ret double %r @@ -191,10 +191,10 @@ define double @vpreduce_ord_fadd_nxv1f64(double %s, %v, %v, %m, i32 %evl) ret double %r @@ -206,10 +206,10 @@ define double @vpreduce_fadd_nxv2f64(double %s, %v, %v, %m, i32 %evl) ret double %r @@ -219,10 +219,10 @@ define double @vpreduce_ord_fadd_nxv2f64(double %s, %v, %v, %m, i32 %evl) ret double %r @@ -234,10 +234,10 @@ define double @vpreduce_fadd_nxv4f64(double %s, %v, %v, %m, i32 %evl) ret double %r @@ -247,10 +247,10 @@ define double @vpreduce_ord_fadd_nxv4f64(double %s, %v, %v, %m, i32 %evl) ret double %r diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll index db0a336814359cfdc36e32566b15a42445db4a88..8709adddce5c551fffcc2ebbcc0c60bf6b3cd311 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll @@ -7,10 +7,10 @@ define signext i8 @vreduce_add_nxv1i8( %v) { ; CHECK-LABEL: vreduce_add_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.add.nxv1i8( %v) ret i8 %red @@ -22,10 +22,10 @@ define signext i8 @vreduce_umax_nxv1i8( %v) { ; CHECK-LABEL: vreduce_umax_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.umax.nxv1i8( %v) ret i8 %red @@ -38,10 +38,10 @@ define signext i8 @vreduce_smax_nxv1i8( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -128 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.smax.nxv1i8( %v) ret i8 %red @@ -53,10 +53,10 @@ define signext i8 @vreduce_umin_nxv1i8( %v) { ; CHECK-LABEL: vreduce_umin_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.umin.nxv1i8( %v) ret i8 %red @@ -69,10 +69,10 @@ define signext i8 @vreduce_smin_nxv1i8( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 127 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.smin.nxv1i8( %v) ret i8 %red @@ -84,10 +84,10 @@ define signext i8 @vreduce_and_nxv1i8( %v) { ; CHECK-LABEL: vreduce_and_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.and.nxv1i8( %v) ret i8 %red @@ -99,10 +99,10 @@ define signext i8 @vreduce_or_nxv1i8( %v) { ; CHECK-LABEL: vreduce_or_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.or.nxv1i8( %v) ret i8 %red @@ -114,10 +114,10 @@ define signext i8 @vreduce_xor_nxv1i8( %v) { ; CHECK-LABEL: vreduce_xor_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.xor.nxv1i8( %v) ret i8 %red @@ -129,10 +129,10 @@ define signext i8 @vreduce_add_nxv2i8( %v) { ; CHECK-LABEL: vreduce_add_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.add.nxv2i8( %v) ret i8 %red @@ -144,10 +144,10 @@ define signext i8 @vreduce_umax_nxv2i8( %v) { ; CHECK-LABEL: vreduce_umax_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.umax.nxv2i8( %v) ret i8 %red @@ -160,10 +160,10 @@ define signext i8 @vreduce_smax_nxv2i8( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -128 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.smax.nxv2i8( %v) ret i8 %red @@ -175,10 +175,10 @@ define signext i8 @vreduce_umin_nxv2i8( %v) { ; CHECK-LABEL: vreduce_umin_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.umin.nxv2i8( %v) ret i8 %red @@ -191,10 +191,10 @@ define signext i8 @vreduce_smin_nxv2i8( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 127 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.smin.nxv2i8( %v) ret i8 %red @@ -206,10 +206,10 @@ define signext i8 @vreduce_and_nxv2i8( %v) { ; CHECK-LABEL: vreduce_and_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.and.nxv2i8( %v) ret i8 %red @@ -221,10 +221,10 @@ define signext i8 @vreduce_or_nxv2i8( %v) { ; CHECK-LABEL: vreduce_or_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.or.nxv2i8( %v) ret i8 %red @@ -236,10 +236,10 @@ define signext i8 @vreduce_xor_nxv2i8( %v) { ; CHECK-LABEL: vreduce_xor_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.xor.nxv2i8( %v) ret i8 %red @@ -251,10 +251,10 @@ define signext i8 @vreduce_add_nxv4i8( %v) { ; CHECK-LABEL: vreduce_add_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.add.nxv4i8( %v) ret i8 %red @@ -266,10 +266,10 @@ define signext i8 @vreduce_umax_nxv4i8( %v) { ; CHECK-LABEL: vreduce_umax_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.umax.nxv4i8( %v) ret i8 %red @@ -282,10 +282,10 @@ define signext i8 @vreduce_smax_nxv4i8( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -128 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.smax.nxv4i8( %v) ret i8 %red @@ -297,10 +297,10 @@ define signext i8 @vreduce_umin_nxv4i8( %v) { ; CHECK-LABEL: vreduce_umin_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.umin.nxv4i8( %v) ret i8 %red @@ -313,10 +313,10 @@ define signext i8 @vreduce_smin_nxv4i8( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 127 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.smin.nxv4i8( %v) ret i8 %red @@ -328,10 +328,10 @@ define signext i8 @vreduce_and_nxv4i8( %v) { ; CHECK-LABEL: vreduce_and_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.and.nxv4i8( %v) ret i8 %red @@ -343,10 +343,10 @@ define signext i8 @vreduce_or_nxv4i8( %v) { ; CHECK-LABEL: vreduce_or_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.or.nxv4i8( %v) ret i8 %red @@ -358,10 +358,10 @@ define signext i8 @vreduce_xor_nxv4i8( %v) { ; CHECK-LABEL: vreduce_xor_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.xor.nxv4i8( %v) ret i8 %red @@ -373,10 +373,10 @@ define signext i16 @vreduce_add_nxv1i16( %v) { ; CHECK-LABEL: vreduce_add_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.add.nxv1i16( %v) ret i16 %red @@ -388,10 +388,10 @@ define signext i16 @vreduce_umax_nxv1i16( %v) { ; CHECK-LABEL: vreduce_umax_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.umax.nxv1i16( %v) ret i16 %red @@ -404,10 +404,10 @@ define signext i16 @vreduce_smax_nxv1i16( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.smax.nxv1i16( %v) ret i16 %red @@ -419,10 +419,10 @@ define signext i16 @vreduce_umin_nxv1i16( %v) { ; CHECK-LABEL: vreduce_umin_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.umin.nxv1i16( %v) ret i16 %red @@ -436,10 +436,10 @@ define signext i16 @vreduce_smin_nxv1i16( %v) { ; CHECK-NEXT: lui a0, 8 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.smin.nxv1i16( %v) ret i16 %red @@ -451,10 +451,10 @@ define signext i16 @vreduce_and_nxv1i16( %v) { ; CHECK-LABEL: vreduce_and_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.and.nxv1i16( %v) ret i16 %red @@ -466,10 +466,10 @@ define signext i16 @vreduce_or_nxv1i16( %v) { ; CHECK-LABEL: vreduce_or_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.or.nxv1i16( %v) ret i16 %red @@ -481,10 +481,10 @@ define signext i16 @vreduce_xor_nxv1i16( %v) { ; CHECK-LABEL: vreduce_xor_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.xor.nxv1i16( %v) ret i16 %red @@ -496,10 +496,10 @@ define signext i16 @vreduce_add_nxv2i16( %v) { ; CHECK-LABEL: vreduce_add_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.add.nxv2i16( %v) ret i16 %red @@ -511,10 +511,10 @@ define signext i16 @vreduce_umax_nxv2i16( %v) { ; CHECK-LABEL: vreduce_umax_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.umax.nxv2i16( %v) ret i16 %red @@ -527,10 +527,10 @@ define signext i16 @vreduce_smax_nxv2i16( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.smax.nxv2i16( %v) ret i16 %red @@ -542,10 +542,10 @@ define signext i16 @vreduce_umin_nxv2i16( %v) { ; CHECK-LABEL: vreduce_umin_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.umin.nxv2i16( %v) ret i16 %red @@ -559,10 +559,10 @@ define signext i16 @vreduce_smin_nxv2i16( %v) { ; CHECK-NEXT: lui a0, 8 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.smin.nxv2i16( %v) ret i16 %red @@ -574,10 +574,10 @@ define signext i16 @vreduce_and_nxv2i16( %v) { ; CHECK-LABEL: vreduce_and_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.and.nxv2i16( %v) ret i16 %red @@ -589,10 +589,10 @@ define signext i16 @vreduce_or_nxv2i16( %v) { ; CHECK-LABEL: vreduce_or_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.or.nxv2i16( %v) ret i16 %red @@ -604,10 +604,10 @@ define signext i16 @vreduce_xor_nxv2i16( %v) { ; CHECK-LABEL: vreduce_xor_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.xor.nxv2i16( %v) ret i16 %red @@ -619,9 +619,9 @@ define signext i16 @vreduce_add_nxv4i16( %v) { ; CHECK-LABEL: vreduce_add_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.add.nxv4i16( %v) ret i16 %red @@ -633,9 +633,9 @@ define signext i16 @vreduce_umax_nxv4i16( %v) { ; CHECK-LABEL: vreduce_umax_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.umax.nxv4i16( %v) ret i16 %red @@ -648,9 +648,9 @@ define signext i16 @vreduce_smax_nxv4i16( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.smax.nxv4i16( %v) ret i16 %red @@ -662,9 +662,9 @@ define signext i16 @vreduce_umin_nxv4i16( %v) { ; CHECK-LABEL: vreduce_umin_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, -1 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.umin.nxv4i16( %v) ret i16 %red @@ -678,9 +678,9 @@ define signext i16 @vreduce_smin_nxv4i16( %v) { ; CHECK-NEXT: lui a0, 8 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.smin.nxv4i16( %v) ret i16 %red @@ -692,9 +692,9 @@ define signext i16 @vreduce_and_nxv4i16( %v) { ; CHECK-LABEL: vreduce_and_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, -1 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.and.nxv4i16( %v) ret i16 %red @@ -706,9 +706,9 @@ define signext i16 @vreduce_or_nxv4i16( %v) { ; CHECK-LABEL: vreduce_or_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.or.nxv4i16( %v) ret i16 %red @@ -720,9 +720,9 @@ define signext i16 @vreduce_xor_nxv4i16( %v) { ; CHECK-LABEL: vreduce_xor_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.xor.nxv4i16( %v) ret i16 %red @@ -734,10 +734,10 @@ define i32 @vreduce_add_nxv1i32( %v) { ; CHECK-LABEL: vreduce_add_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.add.nxv1i32( %v) ret i32 %red @@ -749,10 +749,10 @@ define i32 @vreduce_umax_nxv1i32( %v) { ; CHECK-LABEL: vreduce_umax_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.umax.nxv1i32( %v) ret i32 %red @@ -765,10 +765,10 @@ define i32 @vreduce_smax_nxv1i32( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.smax.nxv1i32( %v) ret i32 %red @@ -780,10 +780,10 @@ define i32 @vreduce_umin_nxv1i32( %v) { ; CHECK-LABEL: vreduce_umin_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.umin.nxv1i32( %v) ret i32 %red @@ -797,10 +797,10 @@ define i32 @vreduce_smin_nxv1i32( %v) { ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.smin.nxv1i32( %v) ret i32 %red @@ -812,10 +812,10 @@ define i32 @vreduce_and_nxv1i32( %v) { ; CHECK-LABEL: vreduce_and_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.and.nxv1i32( %v) ret i32 %red @@ -827,10 +827,10 @@ define i32 @vreduce_or_nxv1i32( %v) { ; CHECK-LABEL: vreduce_or_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.or.nxv1i32( %v) ret i32 %red @@ -842,10 +842,10 @@ define i32 @vreduce_xor_nxv1i32( %v) { ; CHECK-LABEL: vreduce_xor_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.xor.nxv1i32( %v) ret i32 %red @@ -857,9 +857,9 @@ define i32 @vreduce_add_nxv2i32( %v) { ; CHECK-LABEL: vreduce_add_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.add.nxv2i32( %v) ret i32 %red @@ -871,9 +871,9 @@ define i32 @vreduce_umax_nxv2i32( %v) { ; CHECK-LABEL: vreduce_umax_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.umax.nxv2i32( %v) ret i32 %red @@ -886,9 +886,9 @@ define i32 @vreduce_smax_nxv2i32( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.smax.nxv2i32( %v) ret i32 %red @@ -900,9 +900,9 @@ define i32 @vreduce_umin_nxv2i32( %v) { ; CHECK-LABEL: vreduce_umin_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, -1 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.umin.nxv2i32( %v) ret i32 %red @@ -916,9 +916,9 @@ define i32 @vreduce_smin_nxv2i32( %v) { ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.smin.nxv2i32( %v) ret i32 %red @@ -930,9 +930,9 @@ define i32 @vreduce_and_nxv2i32( %v) { ; CHECK-LABEL: vreduce_and_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, -1 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.and.nxv2i32( %v) ret i32 %red @@ -944,9 +944,9 @@ define i32 @vreduce_or_nxv2i32( %v) { ; CHECK-LABEL: vreduce_or_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.or.nxv2i32( %v) ret i32 %red @@ -958,9 +958,9 @@ define i32 @vreduce_xor_nxv2i32( %v) { ; CHECK-LABEL: vreduce_xor_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.xor.nxv2i32( %v) ret i32 %red @@ -972,10 +972,10 @@ define i32 @vreduce_add_nxv4i32( %v) { ; CHECK-LABEL: vreduce_add_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.add.nxv4i32( %v) ret i32 %red @@ -987,10 +987,10 @@ define i32 @vreduce_umax_nxv4i32( %v) { ; CHECK-LABEL: vreduce_umax_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.umax.nxv4i32( %v) ret i32 %red @@ -1003,10 +1003,10 @@ define i32 @vreduce_smax_nxv4i32( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.smax.nxv4i32( %v) ret i32 %red @@ -1018,10 +1018,10 @@ define i32 @vreduce_umin_nxv4i32( %v) { ; CHECK-LABEL: vreduce_umin_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.umin.nxv4i32( %v) ret i32 %red @@ -1035,10 +1035,10 @@ define i32 @vreduce_smin_nxv4i32( %v) { ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.smin.nxv4i32( %v) ret i32 %red @@ -1050,10 +1050,10 @@ define i32 @vreduce_and_nxv4i32( %v) { ; CHECK-LABEL: vreduce_and_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.and.nxv4i32( %v) ret i32 %red @@ -1065,10 +1065,10 @@ define i32 @vreduce_or_nxv4i32( %v) { ; CHECK-LABEL: vreduce_or_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.or.nxv4i32( %v) ret i32 %red @@ -1080,10 +1080,10 @@ define i32 @vreduce_xor_nxv4i32( %v) { ; CHECK-LABEL: vreduce_xor_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.xor.nxv4i32( %v) ret i32 %red @@ -1095,13 +1095,13 @@ define i64 @vreduce_add_nxv1i64( %v) { ; CHECK-LABEL: vreduce_add_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.add.nxv1i64( %v) ret i64 %red @@ -1113,13 +1113,13 @@ define i64 @vreduce_umax_nxv1i64( %v) { ; CHECK-LABEL: vreduce_umax_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.umax.nxv1i64( %v) ret i64 %red @@ -1137,13 +1137,13 @@ define i64 @vreduce_smax_nxv1i64( %v) { ; CHECK-NEXT: sw zero, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smax.nxv1i64( %v) @@ -1156,13 +1156,13 @@ define i64 @vreduce_umin_nxv1i64( %v) { ; CHECK-LABEL: vreduce_umin_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, -1 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.umin.nxv1i64( %v) ret i64 %red @@ -1182,13 +1182,13 @@ define i64 @vreduce_smin_nxv1i64( %v) { ; CHECK-NEXT: sw a0, 12(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smin.nxv1i64( %v) @@ -1201,13 +1201,13 @@ define i64 @vreduce_and_nxv1i64( %v) { ; CHECK-LABEL: vreduce_and_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, -1 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.and.nxv1i64( %v) ret i64 %red @@ -1219,13 +1219,13 @@ define i64 @vreduce_or_nxv1i64( %v) { ; CHECK-LABEL: vreduce_or_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.or.nxv1i64( %v) ret i64 %red @@ -1237,13 +1237,13 @@ define i64 @vreduce_xor_nxv1i64( %v) { ; CHECK-LABEL: vreduce_xor_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.xor.nxv1i64( %v) ret i64 %red @@ -1255,14 +1255,14 @@ define i64 @vreduce_add_nxv2i64( %v) { ; CHECK-LABEL: vreduce_add_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.add.nxv2i64( %v) ret i64 %red @@ -1274,14 +1274,14 @@ define i64 @vreduce_umax_nxv2i64( %v) { ; CHECK-LABEL: vreduce_umax_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.umax.nxv2i64( %v) ret i64 %red @@ -1299,14 +1299,14 @@ define i64 @vreduce_smax_nxv2i64( %v) { ; CHECK-NEXT: sw zero, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero +; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smax.nxv2i64( %v) @@ -1319,14 +1319,14 @@ define i64 @vreduce_umin_nxv2i64( %v) { ; CHECK-LABEL: vreduce_umin_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.umin.nxv2i64( %v) ret i64 %red @@ -1346,14 +1346,14 @@ define i64 @vreduce_smin_nxv2i64( %v) { ; CHECK-NEXT: sw a0, 12(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero +; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smin.nxv2i64( %v) @@ -1366,14 +1366,14 @@ define i64 @vreduce_and_nxv2i64( %v) { ; CHECK-LABEL: vreduce_and_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.and.nxv2i64( %v) ret i64 %red @@ -1385,14 +1385,14 @@ define i64 @vreduce_or_nxv2i64( %v) { ; CHECK-LABEL: vreduce_or_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.or.nxv2i64( %v) ret i64 %red @@ -1404,14 +1404,14 @@ define i64 @vreduce_xor_nxv2i64( %v) { ; CHECK-LABEL: vreduce_xor_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.xor.nxv2i64( %v) ret i64 %red @@ -1423,14 +1423,14 @@ define i64 @vreduce_add_nxv4i64( %v) { ; CHECK-LABEL: vreduce_add_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.add.nxv4i64( %v) ret i64 %red @@ -1442,14 +1442,14 @@ define i64 @vreduce_umax_nxv4i64( %v) { ; CHECK-LABEL: vreduce_umax_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.umax.nxv4i64( %v) ret i64 %red @@ -1467,14 +1467,14 @@ define i64 @vreduce_smax_nxv4i64( %v) { ; CHECK-NEXT: sw zero, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero +; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smax.nxv4i64( %v) @@ -1487,14 +1487,14 @@ define i64 @vreduce_umin_nxv4i64( %v) { ; CHECK-LABEL: vreduce_umin_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v12, -1 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.umin.nxv4i64( %v) ret i64 %red @@ -1514,14 +1514,14 @@ define i64 @vreduce_smin_nxv4i64( %v) { ; CHECK-NEXT: sw a0, 12(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero +; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smin.nxv4i64( %v) @@ -1534,14 +1534,14 @@ define i64 @vreduce_and_nxv4i64( %v) { ; CHECK-LABEL: vreduce_and_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v12, -1 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.and.nxv4i64( %v) ret i64 %red @@ -1553,14 +1553,14 @@ define i64 @vreduce_or_nxv4i64( %v) { ; CHECK-LABEL: vreduce_or_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.or.nxv4i64( %v) ret i64 %red @@ -1572,14 +1572,14 @@ define i64 @vreduce_xor_nxv4i64( %v) { ; CHECK-LABEL: vreduce_xor_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; CHECK-NEXT: vsrl.vx v25, v25, a1 -; CHECK-NEXT: vmv.x.s a1, v25 +; CHECK-NEXT: vsrl.vx v8, v8, a1 +; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.xor.nxv4i64( %v) ret i64 %red diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll index be7b735f4a28eb0db6df59df9a11be495fd0733b..fa4d650ab710ad663f29358937a48980336fb69a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll @@ -7,10 +7,10 @@ define signext i8 @vreduce_add_nxv1i8( %v) { ; CHECK-LABEL: vreduce_add_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.add.nxv1i8( %v) ret i8 %red @@ -22,10 +22,10 @@ define signext i8 @vreduce_umax_nxv1i8( %v) { ; CHECK-LABEL: vreduce_umax_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.umax.nxv1i8( %v) ret i8 %red @@ -38,10 +38,10 @@ define signext i8 @vreduce_smax_nxv1i8( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -128 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.smax.nxv1i8( %v) ret i8 %red @@ -53,10 +53,10 @@ define signext i8 @vreduce_umin_nxv1i8( %v) { ; CHECK-LABEL: vreduce_umin_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.umin.nxv1i8( %v) ret i8 %red @@ -69,10 +69,10 @@ define signext i8 @vreduce_smin_nxv1i8( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 127 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.smin.nxv1i8( %v) ret i8 %red @@ -84,10 +84,10 @@ define signext i8 @vreduce_and_nxv1i8( %v) { ; CHECK-LABEL: vreduce_and_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.and.nxv1i8( %v) ret i8 %red @@ -99,10 +99,10 @@ define signext i8 @vreduce_or_nxv1i8( %v) { ; CHECK-LABEL: vreduce_or_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.or.nxv1i8( %v) ret i8 %red @@ -114,10 +114,10 @@ define signext i8 @vreduce_xor_nxv1i8( %v) { ; CHECK-LABEL: vreduce_xor_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.xor.nxv1i8( %v) ret i8 %red @@ -129,10 +129,10 @@ define signext i8 @vreduce_add_nxv2i8( %v) { ; CHECK-LABEL: vreduce_add_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.add.nxv2i8( %v) ret i8 %red @@ -144,10 +144,10 @@ define signext i8 @vreduce_umax_nxv2i8( %v) { ; CHECK-LABEL: vreduce_umax_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.umax.nxv2i8( %v) ret i8 %red @@ -160,10 +160,10 @@ define signext i8 @vreduce_smax_nxv2i8( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -128 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.smax.nxv2i8( %v) ret i8 %red @@ -175,10 +175,10 @@ define signext i8 @vreduce_umin_nxv2i8( %v) { ; CHECK-LABEL: vreduce_umin_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.umin.nxv2i8( %v) ret i8 %red @@ -191,10 +191,10 @@ define signext i8 @vreduce_smin_nxv2i8( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 127 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.smin.nxv2i8( %v) ret i8 %red @@ -206,10 +206,10 @@ define signext i8 @vreduce_and_nxv2i8( %v) { ; CHECK-LABEL: vreduce_and_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.and.nxv2i8( %v) ret i8 %red @@ -221,10 +221,10 @@ define signext i8 @vreduce_or_nxv2i8( %v) { ; CHECK-LABEL: vreduce_or_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.or.nxv2i8( %v) ret i8 %red @@ -236,10 +236,10 @@ define signext i8 @vreduce_xor_nxv2i8( %v) { ; CHECK-LABEL: vreduce_xor_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.xor.nxv2i8( %v) ret i8 %red @@ -251,10 +251,10 @@ define signext i8 @vreduce_add_nxv4i8( %v) { ; CHECK-LABEL: vreduce_add_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.add.nxv4i8( %v) ret i8 %red @@ -266,10 +266,10 @@ define signext i8 @vreduce_umax_nxv4i8( %v) { ; CHECK-LABEL: vreduce_umax_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.umax.nxv4i8( %v) ret i8 %red @@ -282,10 +282,10 @@ define signext i8 @vreduce_smax_nxv4i8( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -128 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.smax.nxv4i8( %v) ret i8 %red @@ -297,10 +297,10 @@ define signext i8 @vreduce_umin_nxv4i8( %v) { ; CHECK-LABEL: vreduce_umin_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.umin.nxv4i8( %v) ret i8 %red @@ -313,10 +313,10 @@ define signext i8 @vreduce_smin_nxv4i8( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 127 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.smin.nxv4i8( %v) ret i8 %red @@ -328,10 +328,10 @@ define signext i8 @vreduce_and_nxv4i8( %v) { ; CHECK-LABEL: vreduce_and_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.and.nxv4i8( %v) ret i8 %red @@ -343,10 +343,10 @@ define signext i8 @vreduce_or_nxv4i8( %v) { ; CHECK-LABEL: vreduce_or_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.or.nxv4i8( %v) ret i8 %red @@ -358,10 +358,10 @@ define signext i8 @vreduce_xor_nxv4i8( %v) { ; CHECK-LABEL: vreduce_xor_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i8 @llvm.vector.reduce.xor.nxv4i8( %v) ret i8 %red @@ -373,10 +373,10 @@ define signext i16 @vreduce_add_nxv1i16( %v) { ; CHECK-LABEL: vreduce_add_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.add.nxv1i16( %v) ret i16 %red @@ -388,10 +388,10 @@ define signext i16 @vreduce_umax_nxv1i16( %v) { ; CHECK-LABEL: vreduce_umax_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.umax.nxv1i16( %v) ret i16 %red @@ -404,10 +404,10 @@ define signext i16 @vreduce_smax_nxv1i16( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.smax.nxv1i16( %v) ret i16 %red @@ -419,10 +419,10 @@ define signext i16 @vreduce_umin_nxv1i16( %v) { ; CHECK-LABEL: vreduce_umin_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.umin.nxv1i16( %v) ret i16 %red @@ -436,10 +436,10 @@ define signext i16 @vreduce_smin_nxv1i16( %v) { ; CHECK-NEXT: lui a0, 8 ; CHECK-NEXT: addiw a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.smin.nxv1i16( %v) ret i16 %red @@ -451,10 +451,10 @@ define signext i16 @vreduce_and_nxv1i16( %v) { ; CHECK-LABEL: vreduce_and_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.and.nxv1i16( %v) ret i16 %red @@ -466,10 +466,10 @@ define signext i16 @vreduce_or_nxv1i16( %v) { ; CHECK-LABEL: vreduce_or_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.or.nxv1i16( %v) ret i16 %red @@ -481,10 +481,10 @@ define signext i16 @vreduce_xor_nxv1i16( %v) { ; CHECK-LABEL: vreduce_xor_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.xor.nxv1i16( %v) ret i16 %red @@ -496,10 +496,10 @@ define signext i16 @vreduce_add_nxv2i16( %v) { ; CHECK-LABEL: vreduce_add_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.add.nxv2i16( %v) ret i16 %red @@ -511,10 +511,10 @@ define signext i16 @vreduce_umax_nxv2i16( %v) { ; CHECK-LABEL: vreduce_umax_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.umax.nxv2i16( %v) ret i16 %red @@ -527,10 +527,10 @@ define signext i16 @vreduce_smax_nxv2i16( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.smax.nxv2i16( %v) ret i16 %red @@ -542,10 +542,10 @@ define signext i16 @vreduce_umin_nxv2i16( %v) { ; CHECK-LABEL: vreduce_umin_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.umin.nxv2i16( %v) ret i16 %red @@ -559,10 +559,10 @@ define signext i16 @vreduce_smin_nxv2i16( %v) { ; CHECK-NEXT: lui a0, 8 ; CHECK-NEXT: addiw a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.smin.nxv2i16( %v) ret i16 %red @@ -574,10 +574,10 @@ define signext i16 @vreduce_and_nxv2i16( %v) { ; CHECK-LABEL: vreduce_and_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.and.nxv2i16( %v) ret i16 %red @@ -589,10 +589,10 @@ define signext i16 @vreduce_or_nxv2i16( %v) { ; CHECK-LABEL: vreduce_or_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.or.nxv2i16( %v) ret i16 %red @@ -604,10 +604,10 @@ define signext i16 @vreduce_xor_nxv2i16( %v) { ; CHECK-LABEL: vreduce_xor_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.xor.nxv2i16( %v) ret i16 %red @@ -619,9 +619,9 @@ define signext i16 @vreduce_add_nxv4i16( %v) { ; CHECK-LABEL: vreduce_add_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.add.nxv4i16( %v) ret i16 %red @@ -633,9 +633,9 @@ define signext i16 @vreduce_umax_nxv4i16( %v) { ; CHECK-LABEL: vreduce_umax_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.umax.nxv4i16( %v) ret i16 %red @@ -648,9 +648,9 @@ define signext i16 @vreduce_smax_nxv4i16( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.smax.nxv4i16( %v) ret i16 %red @@ -662,9 +662,9 @@ define signext i16 @vreduce_umin_nxv4i16( %v) { ; CHECK-LABEL: vreduce_umin_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, -1 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.umin.nxv4i16( %v) ret i16 %red @@ -678,9 +678,9 @@ define signext i16 @vreduce_smin_nxv4i16( %v) { ; CHECK-NEXT: lui a0, 8 ; CHECK-NEXT: addiw a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.smin.nxv4i16( %v) ret i16 %red @@ -692,9 +692,9 @@ define signext i16 @vreduce_and_nxv4i16( %v) { ; CHECK-LABEL: vreduce_and_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, -1 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.and.nxv4i16( %v) ret i16 %red @@ -706,9 +706,9 @@ define signext i16 @vreduce_or_nxv4i16( %v) { ; CHECK-LABEL: vreduce_or_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.or.nxv4i16( %v) ret i16 %red @@ -720,9 +720,9 @@ define signext i16 @vreduce_xor_nxv4i16( %v) { ; CHECK-LABEL: vreduce_xor_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i16 @llvm.vector.reduce.xor.nxv4i16( %v) ret i16 %red @@ -734,10 +734,10 @@ define signext i32 @vreduce_add_nxv1i32( %v) { ; CHECK-LABEL: vreduce_add_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.add.nxv1i32( %v) ret i32 %red @@ -749,10 +749,10 @@ define signext i32 @vreduce_umax_nxv1i32( %v) { ; CHECK-LABEL: vreduce_umax_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.umax.nxv1i32( %v) ret i32 %red @@ -765,10 +765,10 @@ define signext i32 @vreduce_smax_nxv1i32( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.smax.nxv1i32( %v) ret i32 %red @@ -780,10 +780,10 @@ define signext i32 @vreduce_umin_nxv1i32( %v) { ; CHECK-LABEL: vreduce_umin_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.umin.nxv1i32( %v) ret i32 %red @@ -797,10 +797,10 @@ define signext i32 @vreduce_smin_nxv1i32( %v) { ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: addiw a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.smin.nxv1i32( %v) ret i32 %red @@ -812,10 +812,10 @@ define signext i32 @vreduce_and_nxv1i32( %v) { ; CHECK-LABEL: vreduce_and_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v9, -1 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.and.nxv1i32( %v) ret i32 %red @@ -827,10 +827,10 @@ define signext i32 @vreduce_or_nxv1i32( %v) { ; CHECK-LABEL: vreduce_or_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.or.nxv1i32( %v) ret i32 %red @@ -842,10 +842,10 @@ define signext i32 @vreduce_xor_nxv1i32( %v) { ; CHECK-LABEL: vreduce_xor_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.xor.nxv1i32( %v) ret i32 %red @@ -857,9 +857,9 @@ define signext i32 @vreduce_add_nxv2i32( %v) { ; CHECK-LABEL: vreduce_add_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.add.nxv2i32( %v) ret i32 %red @@ -871,9 +871,9 @@ define signext i32 @vreduce_umax_nxv2i32( %v) { ; CHECK-LABEL: vreduce_umax_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.umax.nxv2i32( %v) ret i32 %red @@ -886,9 +886,9 @@ define signext i32 @vreduce_smax_nxv2i32( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.smax.nxv2i32( %v) ret i32 %red @@ -900,9 +900,9 @@ define signext i32 @vreduce_umin_nxv2i32( %v) { ; CHECK-LABEL: vreduce_umin_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, -1 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.umin.nxv2i32( %v) ret i32 %red @@ -916,9 +916,9 @@ define signext i32 @vreduce_smin_nxv2i32( %v) { ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: addiw a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.smin.nxv2i32( %v) ret i32 %red @@ -930,9 +930,9 @@ define signext i32 @vreduce_and_nxv2i32( %v) { ; CHECK-LABEL: vreduce_and_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, -1 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.and.nxv2i32( %v) ret i32 %red @@ -944,9 +944,9 @@ define signext i32 @vreduce_or_nxv2i32( %v) { ; CHECK-LABEL: vreduce_or_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.or.nxv2i32( %v) ret i32 %red @@ -958,9 +958,9 @@ define signext i32 @vreduce_xor_nxv2i32( %v) { ; CHECK-LABEL: vreduce_xor_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.xor.nxv2i32( %v) ret i32 %red @@ -972,10 +972,10 @@ define signext i32 @vreduce_add_nxv4i32( %v) { ; CHECK-LABEL: vreduce_add_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.add.nxv4i32( %v) ret i32 %red @@ -987,10 +987,10 @@ define signext i32 @vreduce_umax_nxv4i32( %v) { ; CHECK-LABEL: vreduce_umax_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.umax.nxv4i32( %v) ret i32 %red @@ -1003,10 +1003,10 @@ define signext i32 @vreduce_smax_nxv4i32( %v) { ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.smax.nxv4i32( %v) ret i32 %red @@ -1018,10 +1018,10 @@ define signext i32 @vreduce_umin_nxv4i32( %v) { ; CHECK-LABEL: vreduce_umin_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.umin.nxv4i32( %v) ret i32 %red @@ -1035,10 +1035,10 @@ define signext i32 @vreduce_smin_nxv4i32( %v) { ; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: addiw a0, a0, -1 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.smin.nxv4i32( %v) ret i32 %red @@ -1050,10 +1050,10 @@ define signext i32 @vreduce_and_nxv4i32( %v) { ; CHECK-LABEL: vreduce_and_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.and.nxv4i32( %v) ret i32 %red @@ -1065,10 +1065,10 @@ define signext i32 @vreduce_or_nxv4i32( %v) { ; CHECK-LABEL: vreduce_or_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.or.nxv4i32( %v) ret i32 %red @@ -1080,10 +1080,10 @@ define signext i32 @vreduce_xor_nxv4i32( %v) { ; CHECK-LABEL: vreduce_xor_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i32 @llvm.vector.reduce.xor.nxv4i32( %v) ret i32 %red @@ -1095,9 +1095,9 @@ define i64 @vreduce_add_nxv1i64( %v) { ; CHECK-LABEL: vreduce_add_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredsum.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.add.nxv1i64( %v) ret i64 %red @@ -1109,9 +1109,9 @@ define i64 @vreduce_umax_nxv1i64( %v) { ; CHECK-LABEL: vreduce_umax_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredmaxu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.umax.nxv1i64( %v) ret i64 %red @@ -1125,9 +1125,9 @@ define i64 @vreduce_smax_nxv1i64( %v) { ; CHECK-NEXT: addi a0, zero, -1 ; CHECK-NEXT: slli a0, a0, 63 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vredmax.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smax.nxv1i64( %v) ret i64 %red @@ -1139,9 +1139,9 @@ define i64 @vreduce_umin_nxv1i64( %v) { ; CHECK-LABEL: vreduce_umin_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, -1 +; CHECK-NEXT: vredminu.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.umin.nxv1i64( %v) ret i64 %red @@ -1155,9 +1155,9 @@ define i64 @vreduce_smin_nxv1i64( %v) { ; CHECK-NEXT: addi a0, zero, -1 ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vredmin.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smin.nxv1i64( %v) ret i64 %red @@ -1169,9 +1169,9 @@ define i64 @vreduce_and_nxv1i64( %v) { ; CHECK-LABEL: vreduce_and_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, -1 +; CHECK-NEXT: vredand.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.and.nxv1i64( %v) ret i64 %red @@ -1183,9 +1183,9 @@ define i64 @vreduce_or_nxv1i64( %v) { ; CHECK-LABEL: vreduce_or_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.or.nxv1i64( %v) ret i64 %red @@ -1197,9 +1197,9 @@ define i64 @vreduce_xor_nxv1i64( %v) { ; CHECK-LABEL: vreduce_xor_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vmv.v.i v9, 0 +; CHECK-NEXT: vredxor.vs v8, v8, v9 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.xor.nxv1i64( %v) ret i64 %red @@ -1211,10 +1211,10 @@ define i64 @vreduce_add_nxv2i64( %v) { ; CHECK-LABEL: vreduce_add_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.add.nxv2i64( %v) ret i64 %red @@ -1226,10 +1226,10 @@ define i64 @vreduce_umax_nxv2i64( %v) { ; CHECK-LABEL: vreduce_umax_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.umax.nxv2i64( %v) ret i64 %red @@ -1243,10 +1243,10 @@ define i64 @vreduce_smax_nxv2i64( %v) { ; CHECK-NEXT: addi a0, zero, -1 ; CHECK-NEXT: slli a0, a0, 63 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smax.nxv2i64( %v) ret i64 %red @@ -1258,10 +1258,10 @@ define i64 @vreduce_umin_nxv2i64( %v) { ; CHECK-LABEL: vreduce_umin_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.umin.nxv2i64( %v) ret i64 %red @@ -1275,10 +1275,10 @@ define i64 @vreduce_smin_nxv2i64( %v) { ; CHECK-NEXT: addi a0, zero, -1 ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smin.nxv2i64( %v) ret i64 %red @@ -1290,10 +1290,10 @@ define i64 @vreduce_and_nxv2i64( %v) { ; CHECK-LABEL: vreduce_and_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.and.nxv2i64( %v) ret i64 %red @@ -1305,10 +1305,10 @@ define i64 @vreduce_or_nxv2i64( %v) { ; CHECK-LABEL: vreduce_or_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.or.nxv2i64( %v) ret i64 %red @@ -1320,10 +1320,10 @@ define i64 @vreduce_xor_nxv2i64( %v) { ; CHECK-LABEL: vreduce_xor_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v10 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.xor.nxv2i64( %v) ret i64 %red @@ -1335,10 +1335,10 @@ define i64 @vreduce_add_nxv4i64( %v) { ; CHECK-LABEL: vreduce_add_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.add.nxv4i64( %v) ret i64 %red @@ -1350,10 +1350,10 @@ define i64 @vreduce_umax_nxv4i64( %v) { ; CHECK-LABEL: vreduce_umax_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredmaxu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmaxu.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.umax.nxv4i64( %v) ret i64 %red @@ -1367,10 +1367,10 @@ define i64 @vreduce_smax_nxv4i64( %v) { ; CHECK-NEXT: addi a0, zero, -1 ; CHECK-NEXT: slli a0, a0, 63 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v12, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smax.nxv4i64( %v) ret i64 %red @@ -1382,10 +1382,10 @@ define i64 @vreduce_umin_nxv4i64( %v) { ; CHECK-LABEL: vreduce_umin_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v12, -1 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredminu.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredminu.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.umin.nxv4i64( %v) ret i64 %red @@ -1399,10 +1399,10 @@ define i64 @vreduce_smin_nxv4i64( %v) { ; CHECK-NEXT: addi a0, zero, -1 ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v12, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.smin.nxv4i64( %v) ret i64 %red @@ -1414,10 +1414,10 @@ define i64 @vreduce_and_nxv4i64( %v) { ; CHECK-LABEL: vreduce_and_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, -1 +; CHECK-NEXT: vmv.v.i v12, -1 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredand.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.and.nxv4i64( %v) ret i64 %red @@ -1429,10 +1429,10 @@ define i64 @vreduce_or_nxv4i64( %v) { ; CHECK-LABEL: vreduce_or_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.or.nxv4i64( %v) ret i64 %red @@ -1444,10 +1444,10 @@ define i64 @vreduce_xor_nxv4i64( %v) { ; CHECK-LABEL: vreduce_xor_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu -; CHECK-NEXT: vmv.v.i v25, 0 +; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25 -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v8, v8, v12 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %red = call i64 @llvm.vector.reduce.xor.nxv4i64( %v) ret i64 %red diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll index b190d66fa97532d411392dfcda3c67064d6bdf38..c67ca4e2087945806679f903266a8b2fb986c360 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll @@ -10,10 +10,10 @@ define signext i8 @vpreduce_add_nxv1i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -26,10 +26,10 @@ define signext i8 @vpreduce_umax_nxv1i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -41,10 +41,10 @@ define signext i8 @vpreduce_smax_nxv1i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -57,10 +57,10 @@ define signext i8 @vpreduce_umin_nxv1i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -72,10 +72,10 @@ define signext i8 @vpreduce_smin_nxv1i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -87,10 +87,10 @@ define signext i8 @vpreduce_and_nxv1i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -102,10 +102,10 @@ define signext i8 @vpreduce_or_nxv1i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -117,10 +117,10 @@ define signext i8 @vpreduce_xor_nxv1i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -132,10 +132,10 @@ define signext i8 @vpreduce_add_nxv2i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -148,10 +148,10 @@ define signext i8 @vpreduce_umax_nxv2i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -163,10 +163,10 @@ define signext i8 @vpreduce_smax_nxv2i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -179,10 +179,10 @@ define signext i8 @vpreduce_umin_nxv2i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -194,10 +194,10 @@ define signext i8 @vpreduce_smin_nxv2i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -209,10 +209,10 @@ define signext i8 @vpreduce_and_nxv2i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -224,10 +224,10 @@ define signext i8 @vpreduce_or_nxv2i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -239,10 +239,10 @@ define signext i8 @vpreduce_xor_nxv2i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -254,10 +254,10 @@ define signext i8 @vpreduce_add_nxv4i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -270,10 +270,10 @@ define signext i8 @vpreduce_umax_nxv4i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -285,10 +285,10 @@ define signext i8 @vpreduce_smax_nxv4i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -301,10 +301,10 @@ define signext i8 @vpreduce_umin_nxv4i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -316,10 +316,10 @@ define signext i8 @vpreduce_smin_nxv4i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -331,10 +331,10 @@ define signext i8 @vpreduce_and_nxv4i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -346,10 +346,10 @@ define signext i8 @vpreduce_or_nxv4i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -361,10 +361,10 @@ define signext i8 @vpreduce_xor_nxv4i8(i8 signext %s, %v, %v, %m, i32 %evl) ret i8 %r @@ -376,10 +376,10 @@ define signext i16 @vpreduce_add_nxv1i16(i16 signext %s, %v, ; CHECK-LABEL: vpreduce_add_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.add.nxv1i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -394,10 +394,10 @@ define signext i16 @vpreduce_umax_nxv1i16(i16 signext %s, %v, ; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_nxv1i16: @@ -406,10 +406,10 @@ define signext i16 @vpreduce_umax_nxv1i16(i16 signext %s, %v, ; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: and a0, a0, a2 ; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i16 @llvm.vp.reduce.umax.nxv1i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -421,10 +421,10 @@ define signext i16 @vpreduce_smax_nxv1i16(i16 signext %s, %v, ; CHECK-LABEL: vpreduce_smax_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.smax.nxv1i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -439,10 +439,10 @@ define signext i16 @vpreduce_umin_nxv1i16(i16 signext %s, %v, ; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_nxv1i16: @@ -451,10 +451,10 @@ define signext i16 @vpreduce_umin_nxv1i16(i16 signext %s, %v, ; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: and a0, a0, a2 ; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i16 @llvm.vp.reduce.umin.nxv1i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -466,10 +466,10 @@ define signext i16 @vpreduce_smin_nxv1i16(i16 signext %s, %v, ; CHECK-LABEL: vpreduce_smin_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.smin.nxv1i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -481,10 +481,10 @@ define signext i16 @vpreduce_and_nxv1i16(i16 signext %s, %v, ; CHECK-LABEL: vpreduce_and_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.and.nxv1i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -496,10 +496,10 @@ define signext i16 @vpreduce_or_nxv1i16(i16 signext %s, %v, < ; CHECK-LABEL: vpreduce_or_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.or.nxv1i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -511,10 +511,10 @@ define signext i16 @vpreduce_xor_nxv1i16(i16 signext %s, %v, ; CHECK-LABEL: vpreduce_xor_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.xor.nxv1i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -526,10 +526,10 @@ define signext i16 @vpreduce_add_nxv2i16(i16 signext %s, %v, ; CHECK-LABEL: vpreduce_add_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.add.nxv2i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -544,10 +544,10 @@ define signext i16 @vpreduce_umax_nxv2i16(i16 signext %s, %v, ; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_nxv2i16: @@ -556,10 +556,10 @@ define signext i16 @vpreduce_umax_nxv2i16(i16 signext %s, %v, ; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: and a0, a0, a2 ; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i16 @llvm.vp.reduce.umax.nxv2i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -571,10 +571,10 @@ define signext i16 @vpreduce_smax_nxv2i16(i16 signext %s, %v, ; CHECK-LABEL: vpreduce_smax_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.smax.nxv2i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -589,10 +589,10 @@ define signext i16 @vpreduce_umin_nxv2i16(i16 signext %s, %v, ; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_nxv2i16: @@ -601,10 +601,10 @@ define signext i16 @vpreduce_umin_nxv2i16(i16 signext %s, %v, ; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: and a0, a0, a2 ; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i16 @llvm.vp.reduce.umin.nxv2i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -616,10 +616,10 @@ define signext i16 @vpreduce_smin_nxv2i16(i16 signext %s, %v, ; CHECK-LABEL: vpreduce_smin_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.smin.nxv2i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -631,10 +631,10 @@ define signext i16 @vpreduce_and_nxv2i16(i16 signext %s, %v, ; CHECK-LABEL: vpreduce_and_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.and.nxv2i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -646,10 +646,10 @@ define signext i16 @vpreduce_or_nxv2i16(i16 signext %s, %v, < ; CHECK-LABEL: vpreduce_or_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.or.nxv2i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -661,10 +661,10 @@ define signext i16 @vpreduce_xor_nxv2i16(i16 signext %s, %v, ; CHECK-LABEL: vpreduce_xor_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.xor.nxv2i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -676,10 +676,10 @@ define signext i16 @vpreduce_add_nxv4i16(i16 signext %s, %v, ; CHECK-LABEL: vpreduce_add_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.add.nxv4i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -694,10 +694,10 @@ define signext i16 @vpreduce_umax_nxv4i16(i16 signext %s, %v, ; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e16, m1, tu, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_nxv4i16: @@ -706,10 +706,10 @@ define signext i16 @vpreduce_umax_nxv4i16(i16 signext %s, %v, ; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: and a0, a0, a2 ; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e16, m1, tu, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i16 @llvm.vp.reduce.umax.nxv4i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -721,10 +721,10 @@ define signext i16 @vpreduce_smax_nxv4i16(i16 signext %s, %v, ; CHECK-LABEL: vpreduce_smax_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.smax.nxv4i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -739,10 +739,10 @@ define signext i16 @vpreduce_umin_nxv4i16(i16 signext %s, %v, ; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e16, m1, tu, mu -; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_nxv4i16: @@ -751,10 +751,10 @@ define signext i16 @vpreduce_umin_nxv4i16(i16 signext %s, %v, ; RV64-NEXT: addiw a2, a2, -1 ; RV64-NEXT: and a0, a0, a2 ; RV64-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e16, m1, tu, mu -; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i16 @llvm.vp.reduce.umin.nxv4i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -766,10 +766,10 @@ define signext i16 @vpreduce_smin_nxv4i16(i16 signext %s, %v, ; CHECK-LABEL: vpreduce_smin_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.smin.nxv4i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -781,10 +781,10 @@ define signext i16 @vpreduce_and_nxv4i16(i16 signext %s, %v, ; CHECK-LABEL: vpreduce_and_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu -; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.and.nxv4i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -796,10 +796,10 @@ define signext i16 @vpreduce_or_nxv4i16(i16 signext %s, %v, < ; CHECK-LABEL: vpreduce_or_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu -; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.or.nxv4i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -811,10 +811,10 @@ define signext i16 @vpreduce_xor_nxv4i16(i16 signext %s, %v, ; CHECK-LABEL: vpreduce_xor_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i16 @llvm.vp.reduce.xor.nxv4i16(i16 %s, %v, %m, i32 %evl) ret i16 %r @@ -826,10 +826,10 @@ define signext i32 @vpreduce_add_nxv1i32(i32 signext %s, %v, ; CHECK-LABEL: vpreduce_add_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.add.nxv1i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -841,10 +841,10 @@ define signext i32 @vpreduce_umax_nxv1i32(i32 signext %s, %v, ; RV32-LABEL: vpreduce_umax_nxv1i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_nxv1i32: @@ -852,10 +852,10 @@ define signext i32 @vpreduce_umax_nxv1i32(i32 signext %s, %v, ; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: srli a0, a0, 32 ; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i32 @llvm.vp.reduce.umax.nxv1i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -867,10 +867,10 @@ define signext i32 @vpreduce_smax_nxv1i32(i32 signext %s, %v, ; CHECK-LABEL: vpreduce_smax_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.smax.nxv1i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -882,10 +882,10 @@ define signext i32 @vpreduce_umin_nxv1i32(i32 signext %s, %v, ; RV32-LABEL: vpreduce_umin_nxv1i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_nxv1i32: @@ -893,10 +893,10 @@ define signext i32 @vpreduce_umin_nxv1i32(i32 signext %s, %v, ; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: srli a0, a0, 32 ; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i32 @llvm.vp.reduce.umin.nxv1i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -908,10 +908,10 @@ define signext i32 @vpreduce_smin_nxv1i32(i32 signext %s, %v, ; CHECK-LABEL: vpreduce_smin_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.smin.nxv1i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -923,10 +923,10 @@ define signext i32 @vpreduce_and_nxv1i32(i32 signext %s, %v, ; CHECK-LABEL: vpreduce_and_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.and.nxv1i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -938,10 +938,10 @@ define signext i32 @vpreduce_or_nxv1i32(i32 signext %s, %v, < ; CHECK-LABEL: vpreduce_or_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.or.nxv1i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -953,10 +953,10 @@ define signext i32 @vpreduce_xor_nxv1i32(i32 signext %s, %v, ; CHECK-LABEL: vpreduce_xor_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.xor.nxv1i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -968,10 +968,10 @@ define signext i32 @vpreduce_add_nxv2i32(i32 signext %s, %v, ; CHECK-LABEL: vpreduce_add_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.add.nxv2i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -983,10 +983,10 @@ define signext i32 @vpreduce_umax_nxv2i32(i32 signext %s, %v, ; RV32-LABEL: vpreduce_umax_nxv2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_nxv2i32: @@ -994,10 +994,10 @@ define signext i32 @vpreduce_umax_nxv2i32(i32 signext %s, %v, ; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: srli a0, a0, 32 ; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i32 @llvm.vp.reduce.umax.nxv2i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -1009,10 +1009,10 @@ define signext i32 @vpreduce_smax_nxv2i32(i32 signext %s, %v, ; CHECK-LABEL: vpreduce_smax_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.smax.nxv2i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -1024,10 +1024,10 @@ define signext i32 @vpreduce_umin_nxv2i32(i32 signext %s, %v, ; RV32-LABEL: vpreduce_umin_nxv2i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_nxv2i32: @@ -1035,10 +1035,10 @@ define signext i32 @vpreduce_umin_nxv2i32(i32 signext %s, %v, ; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: srli a0, a0, 32 ; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i32 @llvm.vp.reduce.umin.nxv2i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -1050,10 +1050,10 @@ define signext i32 @vpreduce_smin_nxv2i32(i32 signext %s, %v, ; CHECK-LABEL: vpreduce_smin_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.smin.nxv2i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -1065,10 +1065,10 @@ define signext i32 @vpreduce_and_nxv2i32(i32 signext %s, %v, ; CHECK-LABEL: vpreduce_and_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.and.nxv2i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -1080,10 +1080,10 @@ define signext i32 @vpreduce_or_nxv2i32(i32 signext %s, %v, < ; CHECK-LABEL: vpreduce_or_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.or.nxv2i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -1095,10 +1095,10 @@ define signext i32 @vpreduce_xor_nxv2i32(i32 signext %s, %v, ; CHECK-LABEL: vpreduce_xor_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t +; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.xor.nxv2i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -1110,10 +1110,10 @@ define signext i32 @vpreduce_add_nxv4i32(i32 signext %s, %v, ; CHECK-LABEL: vpreduce_add_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu -; CHECK-NEXT: vredsum.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredsum.vs v10, v8, v10, v0.t +; CHECK-NEXT: vmv.x.s a0, v10 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.add.nxv4i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -1125,10 +1125,10 @@ define signext i32 @vpreduce_umax_nxv4i32(i32 signext %s, %v, ; RV32-LABEL: vpreduce_umax_nxv4i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v10, a0 ; RV32-NEXT: vsetvli zero, a1, e32, m2, tu, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_nxv4i32: @@ -1136,10 +1136,10 @@ define signext i32 @vpreduce_umax_nxv4i32(i32 signext %s, %v, ; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: srli a0, a0, 32 ; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e32, m2, tu, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i32 @llvm.vp.reduce.umax.nxv4i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -1151,10 +1151,10 @@ define signext i32 @vpreduce_smax_nxv4i32(i32 signext %s, %v, ; CHECK-LABEL: vpreduce_smax_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu -; CHECK-NEXT: vredmax.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmax.vs v10, v8, v10, v0.t +; CHECK-NEXT: vmv.x.s a0, v10 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.smax.nxv4i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -1166,10 +1166,10 @@ define signext i32 @vpreduce_umin_nxv4i32(i32 signext %s, %v, ; RV32-LABEL: vpreduce_umin_nxv4i32: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV32-NEXT: vmv.v.x v25, a0 +; RV32-NEXT: vmv.v.x v10, a0 ; RV32-NEXT: vsetvli zero, a1, e32, m2, tu, mu -; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_nxv4i32: @@ -1177,10 +1177,10 @@ define signext i32 @vpreduce_umin_nxv4i32(i32 signext %s, %v, ; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: srli a0, a0, 32 ; RV64-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e32, m2, tu, mu -; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i32 @llvm.vp.reduce.umin.nxv4i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -1192,10 +1192,10 @@ define signext i32 @vpreduce_smin_nxv4i32(i32 signext %s, %v, ; CHECK-LABEL: vpreduce_smin_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu -; CHECK-NEXT: vredmin.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredmin.vs v10, v8, v10, v0.t +; CHECK-NEXT: vmv.x.s a0, v10 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.smin.nxv4i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -1207,10 +1207,10 @@ define signext i32 @vpreduce_and_nxv4i32(i32 signext %s, %v, ; CHECK-LABEL: vpreduce_and_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu -; CHECK-NEXT: vredand.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredand.vs v10, v8, v10, v0.t +; CHECK-NEXT: vmv.x.s a0, v10 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.and.nxv4i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -1222,10 +1222,10 @@ define signext i32 @vpreduce_or_nxv4i32(i32 signext %s, %v, < ; CHECK-LABEL: vpreduce_or_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu -; CHECK-NEXT: vredor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredor.vs v10, v8, v10, v0.t +; CHECK-NEXT: vmv.x.s a0, v10 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.or.nxv4i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -1237,10 +1237,10 @@ define signext i32 @vpreduce_xor_nxv4i32(i32 signext %s, %v, ; CHECK-LABEL: vpreduce_xor_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 +; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu -; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t -; CHECK-NEXT: vmv.x.s a0, v25 +; CHECK-NEXT: vredxor.vs v10, v8, v10, v0.t +; CHECK-NEXT: vmv.x.s a0, v10 ; CHECK-NEXT: ret %r = call i32 @llvm.vp.reduce.xor.nxv4i32(i32 %s, %v, %m, i32 %evl) ret i32 %r @@ -1257,24 +1257,24 @@ define signext i64 @vpreduce_add_nxv1i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredsum.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredsum.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_add_nxv1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredsum.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredsum.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.add.nxv1i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1291,24 +1291,24 @@ define signext i64 @vpreduce_umax_nxv1i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_nxv1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.umax.nxv1i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1325,24 +1325,24 @@ define signext i64 @vpreduce_smax_nxv1i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredmax.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmax.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_smax_nxv1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredmax.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmax.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.smax.nxv1i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1359,24 +1359,24 @@ define signext i64 @vpreduce_umin_nxv1i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_nxv1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.umin.nxv1i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1393,24 +1393,24 @@ define signext i64 @vpreduce_smin_nxv1i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredmin.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_smin_nxv1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredmin.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.smin.nxv1i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1427,24 +1427,24 @@ define signext i64 @vpreduce_and_nxv1i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredand.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredand.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_and_nxv1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredand.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredand.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.and.nxv1i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1461,24 +1461,24 @@ define signext i64 @vpreduce_or_nxv1i64(i64 signext %s, %v, < ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredor.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredor.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_or_nxv1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredor.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredor.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.or.nxv1i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1495,24 +1495,24 @@ define signext i64 @vpreduce_xor_nxv1i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu -; RV32-NEXT: vredxor.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredxor.vs v9, v8, v9, v0.t +; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v9, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_xor_nxv1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v9, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu -; RV64-NEXT: vredxor.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredxor.vs v9, v8, v9, v0.t +; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.xor.nxv1i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1529,24 +1529,24 @@ define signext i64 @vpreduce_add_nxv2i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredsum.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredsum.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_add_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredsum.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredsum.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.add.nxv2i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1563,24 +1563,24 @@ define signext i64 @vpreduce_umax_nxv2i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.umax.nxv2i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1597,24 +1597,24 @@ define signext i64 @vpreduce_smax_nxv2i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredmax.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmax.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_smax_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredmax.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmax.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.smax.nxv2i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1631,24 +1631,24 @@ define signext i64 @vpreduce_umin_nxv2i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.umin.nxv2i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1665,24 +1665,24 @@ define signext i64 @vpreduce_smin_nxv2i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredmin.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_smin_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredmin.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.smin.nxv2i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1699,24 +1699,24 @@ define signext i64 @vpreduce_and_nxv2i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredand.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredand.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_and_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredand.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredand.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.and.nxv2i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1733,24 +1733,24 @@ define signext i64 @vpreduce_or_nxv2i64(i64 signext %s, %v, < ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredor.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredor.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_or_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredor.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredor.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.or.nxv2i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1767,24 +1767,24 @@ define signext i64 @vpreduce_xor_nxv2i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu -; RV32-NEXT: vredxor.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredxor.vs v10, v8, v10, v0.t +; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v10, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_xor_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v10, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu -; RV64-NEXT: vredxor.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredxor.vs v10, v8, v10, v0.t +; RV64-NEXT: vmv.x.s a0, v10 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.xor.nxv2i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1801,24 +1801,24 @@ define signext i64 @vpreduce_add_nxv4i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu -; RV32-NEXT: vredsum.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredsum.vs v12, v8, v12, v0.t +; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v12, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_add_nxv4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v12, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu -; RV64-NEXT: vredsum.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredsum.vs v12, v8, v12, v0.t +; RV64-NEXT: vmv.x.s a0, v12 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.add.nxv4i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1835,24 +1835,24 @@ define signext i64 @vpreduce_umax_nxv4i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu -; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmaxu.vs v12, v8, v12, v0.t +; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v12, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umax_nxv4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v12, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu -; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmaxu.vs v12, v8, v12, v0.t +; RV64-NEXT: vmv.x.s a0, v12 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.umax.nxv4i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1869,24 +1869,24 @@ define signext i64 @vpreduce_smax_nxv4i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu -; RV32-NEXT: vredmax.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmax.vs v12, v8, v12, v0.t +; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v12, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_smax_nxv4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v12, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu -; RV64-NEXT: vredmax.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmax.vs v12, v8, v12, v0.t +; RV64-NEXT: vmv.x.s a0, v12 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.smax.nxv4i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1903,24 +1903,24 @@ define signext i64 @vpreduce_umin_nxv4i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu -; RV32-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredminu.vs v12, v8, v12, v0.t +; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v12, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_umin_nxv4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v12, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu -; RV64-NEXT: vredminu.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredminu.vs v12, v8, v12, v0.t +; RV64-NEXT: vmv.x.s a0, v12 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.umin.nxv4i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1937,24 +1937,24 @@ define signext i64 @vpreduce_smin_nxv4i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu -; RV32-NEXT: vredmin.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredmin.vs v12, v8, v12, v0.t +; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v12, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_smin_nxv4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v12, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu -; RV64-NEXT: vredmin.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredmin.vs v12, v8, v12, v0.t +; RV64-NEXT: vmv.x.s a0, v12 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.smin.nxv4i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -1971,24 +1971,24 @@ define signext i64 @vpreduce_and_nxv4i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu -; RV32-NEXT: vredand.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredand.vs v12, v8, v12, v0.t +; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v12, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_and_nxv4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v12, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu -; RV64-NEXT: vredand.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredand.vs v12, v8, v12, v0.t +; RV64-NEXT: vmv.x.s a0, v12 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.and.nxv4i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -2005,24 +2005,24 @@ define signext i64 @vpreduce_or_nxv4i64(i64 signext %s, %v, < ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu -; RV32-NEXT: vredor.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredor.vs v12, v8, v12, v0.t +; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v12, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_or_nxv4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v12, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu -; RV64-NEXT: vredor.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredor.vs v12, v8, v12, v0.t +; RV64-NEXT: vmv.x.s a0, v12 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.or.nxv4i64(i64 %s, %v, %m, i32 %evl) ret i64 %r @@ -2039,24 +2039,24 @@ define signext i64 @vpreduce_xor_nxv4i64(i64 signext %s, %v, ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu -; RV32-NEXT: vredxor.vs v25, v8, v25, v0.t -; RV32-NEXT: vmv.x.s a0, v25 +; RV32-NEXT: vredxor.vs v12, v8, v12, v0.t +; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: addi a1, zero, 32 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu -; RV32-NEXT: vsrl.vx v25, v25, a1 -; RV32-NEXT: vmv.x.s a1, v25 +; RV32-NEXT: vsrl.vx v8, v12, a1 +; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vpreduce_xor_nxv4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a2, zero, e64, m1, ta, mu -; RV64-NEXT: vmv.v.x v25, a0 +; RV64-NEXT: vmv.v.x v12, a0 ; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu -; RV64-NEXT: vredxor.vs v25, v8, v25, v0.t -; RV64-NEXT: vmv.x.s a0, v25 +; RV64-NEXT: vredxor.vs v12, v8, v12, v0.t +; RV64-NEXT: vmv.x.s a0, v12 ; RV64-NEXT: ret %r = call i64 @llvm.vp.reduce.xor.nxv4i64(i64 %s, %v, %m, i32 %evl) ret i64 %r diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll index acd8806516e2126e899daa51f42983763a31b9bc..1d8797daa6ebc541a294497f19f310a3581b2754 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll @@ -8,9 +8,9 @@ define signext i1 @vpreduce_and_nxv1i1(i1 signext %s, %v, , , i define signext i1 @vpreduce_or_nxv1i1(i1 signext %s, %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_or_nxv1i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: snez a1, a1 ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 @@ -42,10 +42,10 @@ declare i1 @llvm.vp.reduce.xor.nxv1i1(i1, , , define signext i1 @vpreduce_xor_nxv1i1(i1 signext %s, %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_xor_nxv1i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 @@ -60,9 +60,9 @@ define signext i1 @vpreduce_and_nxv2i1(i1 signext %s, %v, , , i define signext i1 @vpreduce_or_nxv2i1(i1 signext %s, %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_or_nxv2i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: snez a1, a1 ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 @@ -94,10 +94,10 @@ declare i1 @llvm.vp.reduce.xor.nxv2i1(i1, , , define signext i1 @vpreduce_xor_nxv2i1(i1 signext %s, %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_xor_nxv2i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 @@ -112,9 +112,9 @@ define signext i1 @vpreduce_and_nxv4i1(i1 signext %s, %v, , , i define signext i1 @vpreduce_or_nxv4i1(i1 signext %s, %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_or_nxv4i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: snez a1, a1 ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 @@ -146,10 +146,10 @@ declare i1 @llvm.vp.reduce.xor.nxv4i1(i1, , , define signext i1 @vpreduce_xor_nxv4i1(i1 signext %s, %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_xor_nxv4i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 @@ -164,9 +164,9 @@ define signext i1 @vpreduce_and_nxv8i1(i1 signext %s, %v, , , i define signext i1 @vpreduce_or_nxv8i1(i1 signext %s, %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_or_nxv8i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: snez a1, a1 ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 @@ -198,10 +198,10 @@ declare i1 @llvm.vp.reduce.xor.nxv8i1(i1, , , define signext i1 @vpreduce_xor_nxv8i1(i1 signext %s, %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_xor_nxv8i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 @@ -216,9 +216,9 @@ define signext i1 @vpreduce_and_nxv16i1(i1 signext %s, %v, , define signext i1 @vpreduce_or_nxv16i1(i1 signext %s, %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_or_nxv16i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: snez a1, a1 ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 @@ -250,10 +250,10 @@ declare i1 @llvm.vp.reduce.xor.nxv16i1(i1, , %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_xor_nxv16i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 @@ -268,9 +268,9 @@ define signext i1 @vpreduce_and_nxv32i1(i1 signext %s, %v, , define signext i1 @vpreduce_or_nxv32i1(i1 signext %s, %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_or_nxv32i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: snez a1, a1 ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 @@ -302,10 +302,10 @@ declare i1 @llvm.vp.reduce.xor.nxv32i1(i1, , %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_xor_nxv32i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 @@ -320,9 +320,9 @@ define signext i1 @vpreduce_and_nxv64i1(i1 signext %s, %v, , define signext i1 @vpreduce_or_nxv64i1(i1 signext %s, %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_or_nxv64i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: snez a1, a1 ; CHECK-NEXT: or a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 @@ -354,10 +354,10 @@ declare i1 @llvm.vp.reduce.xor.nxv64i1(i1, , %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_xor_nxv64i1: ; CHECK: # %bb.0: -; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v8 -; CHECK-NEXT: vpopc.m a1, v25, v0.t +; CHECK-NEXT: vpopc.m a1, v9, v0.t ; CHECK-NEXT: xor a0, a1, a0 ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: neg a0, a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll index 93c22436f82e09d3cf5290510c66e3922f46e89a..d3a595534ef763504ee0a8bccfab5ef40bb15574 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll @@ -36,8 +36,8 @@ define signext i1 @vreduce_and_nxv1i1( %v) { ; CHECK-LABEL: vreduce_and_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 -; CHECK-NEXT: vpopc.m a0, v25 +; CHECK-NEXT: vmnand.mm v8, v0, v0 +; CHECK-NEXT: vpopc.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -79,8 +79,8 @@ define signext i1 @vreduce_and_nxv2i1( %v) { ; CHECK-LABEL: vreduce_and_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 -; CHECK-NEXT: vpopc.m a0, v25 +; CHECK-NEXT: vmnand.mm v8, v0, v0 +; CHECK-NEXT: vpopc.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -122,8 +122,8 @@ define signext i1 @vreduce_and_nxv4i1( %v) { ; CHECK-LABEL: vreduce_and_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 -; CHECK-NEXT: vpopc.m a0, v25 +; CHECK-NEXT: vmnand.mm v8, v0, v0 +; CHECK-NEXT: vpopc.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -165,8 +165,8 @@ define signext i1 @vreduce_and_nxv8i1( %v) { ; CHECK-LABEL: vreduce_and_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 -; CHECK-NEXT: vpopc.m a0, v25 +; CHECK-NEXT: vmnand.mm v8, v0, v0 +; CHECK-NEXT: vpopc.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -208,8 +208,8 @@ define signext i1 @vreduce_and_nxv16i1( %v) { ; CHECK-LABEL: vreduce_and_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 -; CHECK-NEXT: vpopc.m a0, v25 +; CHECK-NEXT: vmnand.mm v8, v0, v0 +; CHECK-NEXT: vpopc.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -251,8 +251,8 @@ define signext i1 @vreduce_and_nxv32i1( %v) { ; CHECK-LABEL: vreduce_and_nxv32i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 -; CHECK-NEXT: vpopc.m a0, v25 +; CHECK-NEXT: vmnand.mm v8, v0, v0 +; CHECK-NEXT: vpopc.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret @@ -294,8 +294,8 @@ define signext i1 @vreduce_and_nxv64i1( %v) { ; CHECK-LABEL: vreduce_and_nxv64i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu -; CHECK-NEXT: vmnand.mm v25, v0, v0 -; CHECK-NEXT: vpopc.m a0, v25 +; CHECK-NEXT: vmnand.mm v8, v0, v0 +; CHECK-NEXT: vpopc.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll index fca64ecf037aaf843a0915809e40a89a8f1ef022..f0bfe6c3226a697faba9b7f6d1dbc6267a64a27b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vrem_vx_nxv1i64_nxv1i64_i64( @intrinsic_vrem_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vrem_vx_nxv2i64_nxv2i64_i64( @intrinsic_vrem_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vrem_vx_nxv4i64_nxv4i64_i64( @intrinsic_vrem_mask_vx_nxv4i64_nxv4i64_i64( @vrem_vi_nxv1i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v9, v9, v8 +; CHECK-NEXT: vsra.vi v9, v9, 2 +; CHECK-NEXT: vsrl.vi v10, v9, 7 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -69,13 +69,13 @@ define @vrem_vi_nxv2i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v9, v9, v8 +; CHECK-NEXT: vsra.vi v9, v9, 2 +; CHECK-NEXT: vsrl.vi v10, v9, 7 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -110,13 +110,13 @@ define @vrem_vi_nxv4i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v9, v9, v8 +; CHECK-NEXT: vsra.vi v9, v9, 2 +; CHECK-NEXT: vsrl.vi v10, v9, 7 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -151,13 +151,13 @@ define @vrem_vi_nxv8i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v9, v9, v8 +; CHECK-NEXT: vsra.vi v9, v9, 2 +; CHECK-NEXT: vsrl.vi v10, v9, 7 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -192,13 +192,13 @@ define @vrem_vi_nxv16i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmulh.vx v26, v8, a0 -; CHECK-NEXT: vsub.vv v26, v26, v8 -; CHECK-NEXT: vsra.vi v26, v26, 2 -; CHECK-NEXT: vsrl.vi v28, v26, 7 -; CHECK-NEXT: vadd.vv v26, v26, v28 +; CHECK-NEXT: vmulh.vx v10, v8, a0 +; CHECK-NEXT: vsub.vv v10, v10, v8 +; CHECK-NEXT: vsra.vi v10, v10, 2 +; CHECK-NEXT: vsrl.vi v12, v10, 7 +; CHECK-NEXT: vadd.vv v10, v10, v12 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -233,13 +233,13 @@ define @vrem_vi_nxv32i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmulh.vx v28, v8, a0 -; CHECK-NEXT: vsub.vv v28, v28, v8 -; CHECK-NEXT: vsra.vi v28, v28, 2 -; CHECK-NEXT: vsrl.vi v12, v28, 7 -; CHECK-NEXT: vadd.vv v28, v28, v12 +; CHECK-NEXT: vmulh.vx v12, v8, a0 +; CHECK-NEXT: vsub.vv v12, v12, v8 +; CHECK-NEXT: vsra.vi v12, v12, 2 +; CHECK-NEXT: vsrl.vi v16, v12, 7 +; CHECK-NEXT: vadd.vv v12, v12, v16 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -316,12 +316,12 @@ define @vrem_vi_nxv1i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vsrl.vi v26, v25, 15 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsra.vi v9, v9, 1 +; CHECK-NEXT: vsrl.vi v10, v9, 15 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -357,12 +357,12 @@ define @vrem_vi_nxv2i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vsrl.vi v26, v25, 15 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsra.vi v9, v9, 1 +; CHECK-NEXT: vsrl.vi v10, v9, 15 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -398,12 +398,12 @@ define @vrem_vi_nxv4i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vsrl.vi v26, v25, 15 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsra.vi v9, v9, 1 +; CHECK-NEXT: vsrl.vi v10, v9, 15 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -439,12 +439,12 @@ define @vrem_vi_nxv8i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmulh.vx v26, v8, a0 -; CHECK-NEXT: vsra.vi v26, v26, 1 -; CHECK-NEXT: vsrl.vi v28, v26, 15 -; CHECK-NEXT: vadd.vv v26, v26, v28 +; CHECK-NEXT: vmulh.vx v10, v8, a0 +; CHECK-NEXT: vsra.vi v10, v10, 1 +; CHECK-NEXT: vsrl.vi v12, v10, 15 +; CHECK-NEXT: vadd.vv v10, v10, v12 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -480,12 +480,12 @@ define @vrem_vi_nxv16i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vmulh.vx v28, v8, a0 -; CHECK-NEXT: vsra.vi v28, v28, 1 -; CHECK-NEXT: vsrl.vi v12, v28, 15 -; CHECK-NEXT: vadd.vv v28, v28, v12 +; CHECK-NEXT: vmulh.vx v12, v8, a0 +; CHECK-NEXT: vsra.vi v12, v12, 1 +; CHECK-NEXT: vsrl.vi v16, v12, 15 +; CHECK-NEXT: vadd.vv v12, v12, v16 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -562,13 +562,13 @@ define @vrem_vi_nxv1i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addi a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsrl.vi v26, v25, 31 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v9, v9, v8 +; CHECK-NEXT: vsrl.vi v10, v9, 31 +; CHECK-NEXT: vsra.vi v9, v9, 2 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -604,13 +604,13 @@ define @vrem_vi_nxv2i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addi a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsrl.vi v26, v25, 31 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v9, v9, v8 +; CHECK-NEXT: vsrl.vi v10, v9, 31 +; CHECK-NEXT: vsra.vi v9, v9, 2 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -646,13 +646,13 @@ define @vrem_vi_nxv4i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addi a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vmulh.vx v26, v8, a0 -; CHECK-NEXT: vsub.vv v26, v26, v8 -; CHECK-NEXT: vsrl.vi v28, v26, 31 -; CHECK-NEXT: vsra.vi v26, v26, 2 -; CHECK-NEXT: vadd.vv v26, v26, v28 +; CHECK-NEXT: vmulh.vx v10, v8, a0 +; CHECK-NEXT: vsub.vv v10, v10, v8 +; CHECK-NEXT: vsrl.vi v12, v10, 31 +; CHECK-NEXT: vsra.vi v10, v10, 2 +; CHECK-NEXT: vadd.vv v10, v10, v12 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -688,13 +688,13 @@ define @vrem_vi_nxv8i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addi a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmulh.vx v28, v8, a0 -; CHECK-NEXT: vsub.vv v28, v28, v8 -; CHECK-NEXT: vsrl.vi v12, v28, 31 -; CHECK-NEXT: vsra.vi v28, v28, 2 -; CHECK-NEXT: vadd.vv v28, v28, v12 +; CHECK-NEXT: vmulh.vx v12, v8, a0 +; CHECK-NEXT: vsub.vv v12, v12, v8 +; CHECK-NEXT: vsrl.vi v16, v12, 31 +; CHECK-NEXT: vsra.vi v12, v12, 2 +; CHECK-NEXT: vadd.vv v12, v12, v16 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -763,8 +763,8 @@ define @vrem_vx_nxv1i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vrem.vv v8, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -786,14 +786,14 @@ define @vrem_vi_nxv1i64_0( %va) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmulh.vv v25, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmulh.vv v9, v8, v9 ; CHECK-NEXT: addi a0, zero, 63 -; CHECK-NEXT: vsrl.vx v26, v25, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vsrl.vx v10, v9, a0 +; CHECK-NEXT: vsra.vi v9, v9, 1 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 @@ -821,8 +821,8 @@ define @vrem_vx_nxv2i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vrem.vv v8, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vrem.vv v8, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -844,14 +844,14 @@ define @vrem_vi_nxv2i64_0( %va) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmulh.vv v26, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmulh.vv v10, v8, v10 ; CHECK-NEXT: addi a0, zero, 63 -; CHECK-NEXT: vsrl.vx v28, v26, a0 -; CHECK-NEXT: vsra.vi v26, v26, 1 -; CHECK-NEXT: vadd.vv v26, v26, v28 +; CHECK-NEXT: vsrl.vx v12, v10, a0 +; CHECK-NEXT: vsra.vi v10, v10, 1 +; CHECK-NEXT: vadd.vv v10, v10, v12 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 @@ -879,8 +879,8 @@ define @vrem_vx_nxv4i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vrem.vv v8, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vrem.vv v8, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -902,14 +902,14 @@ define @vrem_vi_nxv4i64_0( %va) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmulh.vv v28, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmulh.vv v12, v8, v12 ; CHECK-NEXT: addi a0, zero, 63 -; CHECK-NEXT: vsrl.vx v12, v28, a0 -; CHECK-NEXT: vsra.vi v28, v28, 1 -; CHECK-NEXT: vadd.vv v28, v28, v12 +; CHECK-NEXT: vsrl.vx v16, v12, a0 +; CHECK-NEXT: vsra.vi v12, v12, 1 +; CHECK-NEXT: vadd.vv v12, v12, v16 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll index a56f28eb435e06c74e94b0805e9bda151587ee88..5fb123b5186deeaf00038bf4c04aba5190e0733c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll @@ -28,13 +28,13 @@ define @vrem_vi_nxv1i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v9, v9, v8 +; CHECK-NEXT: vsra.vi v9, v9, 2 +; CHECK-NEXT: vsrl.vi v10, v9, 7 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -69,13 +69,13 @@ define @vrem_vi_nxv2i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v9, v9, v8 +; CHECK-NEXT: vsra.vi v9, v9, 2 +; CHECK-NEXT: vsrl.vi v10, v9, 7 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -110,13 +110,13 @@ define @vrem_vi_nxv4i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v9, v9, v8 +; CHECK-NEXT: vsra.vi v9, v9, 2 +; CHECK-NEXT: vsrl.vi v10, v9, 7 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -151,13 +151,13 @@ define @vrem_vi_nxv8i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 7 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v9, v9, v8 +; CHECK-NEXT: vsra.vi v9, v9, 2 +; CHECK-NEXT: vsrl.vi v10, v9, 7 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -192,13 +192,13 @@ define @vrem_vi_nxv16i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmulh.vx v26, v8, a0 -; CHECK-NEXT: vsub.vv v26, v26, v8 -; CHECK-NEXT: vsra.vi v26, v26, 2 -; CHECK-NEXT: vsrl.vi v28, v26, 7 -; CHECK-NEXT: vadd.vv v26, v26, v28 +; CHECK-NEXT: vmulh.vx v10, v8, a0 +; CHECK-NEXT: vsub.vv v10, v10, v8 +; CHECK-NEXT: vsra.vi v10, v10, 2 +; CHECK-NEXT: vsrl.vi v12, v10, 7 +; CHECK-NEXT: vadd.vv v10, v10, v12 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -233,13 +233,13 @@ define @vrem_vi_nxv32i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 109 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmulh.vx v28, v8, a0 -; CHECK-NEXT: vsub.vv v28, v28, v8 -; CHECK-NEXT: vsra.vi v28, v28, 2 -; CHECK-NEXT: vsrl.vi v12, v28, 7 -; CHECK-NEXT: vadd.vv v28, v28, v12 +; CHECK-NEXT: vmulh.vx v12, v8, a0 +; CHECK-NEXT: vsub.vv v12, v12, v8 +; CHECK-NEXT: vsra.vi v12, v12, 2 +; CHECK-NEXT: vsrl.vi v16, v12, 7 +; CHECK-NEXT: vadd.vv v12, v12, v16 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -316,12 +316,12 @@ define @vrem_vi_nxv1i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addiw a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vsrl.vi v26, v25, 15 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsra.vi v9, v9, 1 +; CHECK-NEXT: vsrl.vi v10, v9, 15 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -357,12 +357,12 @@ define @vrem_vi_nxv2i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addiw a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vsrl.vi v26, v25, 15 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsra.vi v9, v9, 1 +; CHECK-NEXT: vsrl.vi v10, v9, 15 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -398,12 +398,12 @@ define @vrem_vi_nxv4i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addiw a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vsrl.vi v26, v25, 15 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsra.vi v9, v9, 1 +; CHECK-NEXT: vsrl.vi v10, v9, 15 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -439,12 +439,12 @@ define @vrem_vi_nxv8i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addiw a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmulh.vx v26, v8, a0 -; CHECK-NEXT: vsra.vi v26, v26, 1 -; CHECK-NEXT: vsrl.vi v28, v26, 15 -; CHECK-NEXT: vadd.vv v26, v26, v28 +; CHECK-NEXT: vmulh.vx v10, v8, a0 +; CHECK-NEXT: vsra.vi v10, v10, 1 +; CHECK-NEXT: vsrl.vi v12, v10, 15 +; CHECK-NEXT: vadd.vv v10, v10, v12 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -480,12 +480,12 @@ define @vrem_vi_nxv16i16_0( %va) { ; CHECK-NEXT: lui a0, 1048571 ; CHECK-NEXT: addiw a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vmulh.vx v28, v8, a0 -; CHECK-NEXT: vsra.vi v28, v28, 1 -; CHECK-NEXT: vsrl.vi v12, v28, 15 -; CHECK-NEXT: vadd.vv v28, v28, v12 +; CHECK-NEXT: vmulh.vx v12, v8, a0 +; CHECK-NEXT: vsra.vi v12, v12, 1 +; CHECK-NEXT: vsrl.vi v16, v12, 15 +; CHECK-NEXT: vadd.vv v12, v12, v16 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -562,13 +562,13 @@ define @vrem_vi_nxv1i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addiw a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 31 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v9, v9, v8 +; CHECK-NEXT: vsra.vi v9, v9, 2 +; CHECK-NEXT: vsrl.vi v10, v9, 31 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -604,13 +604,13 @@ define @vrem_vi_nxv2i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addiw a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 -; CHECK-NEXT: vsub.vv v25, v25, v8 -; CHECK-NEXT: vsra.vi v25, v25, 2 -; CHECK-NEXT: vsrl.vi v26, v25, 31 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vmulh.vx v9, v8, a0 +; CHECK-NEXT: vsub.vv v9, v9, v8 +; CHECK-NEXT: vsra.vi v9, v9, 2 +; CHECK-NEXT: vsrl.vi v10, v9, 31 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -646,13 +646,13 @@ define @vrem_vi_nxv4i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addiw a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vmulh.vx v26, v8, a0 -; CHECK-NEXT: vsub.vv v26, v26, v8 -; CHECK-NEXT: vsra.vi v26, v26, 2 -; CHECK-NEXT: vsrl.vi v28, v26, 31 -; CHECK-NEXT: vadd.vv v26, v26, v28 +; CHECK-NEXT: vmulh.vx v10, v8, a0 +; CHECK-NEXT: vsub.vv v10, v10, v8 +; CHECK-NEXT: vsra.vi v10, v10, 2 +; CHECK-NEXT: vsrl.vi v12, v10, 31 +; CHECK-NEXT: vadd.vv v10, v10, v12 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -688,13 +688,13 @@ define @vrem_vi_nxv8i32_0( %va) { ; CHECK-NEXT: lui a0, 449390 ; CHECK-NEXT: addiw a0, a0, -1171 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmulh.vx v28, v8, a0 -; CHECK-NEXT: vsub.vv v28, v28, v8 -; CHECK-NEXT: vsra.vi v28, v28, 2 -; CHECK-NEXT: vsrl.vi v12, v28, 31 -; CHECK-NEXT: vadd.vv v28, v28, v12 +; CHECK-NEXT: vmulh.vx v12, v8, a0 +; CHECK-NEXT: vsub.vv v12, v12, v8 +; CHECK-NEXT: vsra.vi v12, v12, 2 +; CHECK-NEXT: vsrl.vi v16, v12, 31 +; CHECK-NEXT: vadd.vv v12, v12, v16 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -778,13 +778,13 @@ define @vrem_vi_nxv1i64_0( %va) { ; CHECK-NEXT: slli a0, a0, 12 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vmulh.vx v25, v8, a0 +; CHECK-NEXT: vmulh.vx v9, v8, a0 ; CHECK-NEXT: addi a0, zero, 63 -; CHECK-NEXT: vsrl.vx v26, v25, a0 -; CHECK-NEXT: vsra.vi v25, v25, 1 -; CHECK-NEXT: vadd.vv v25, v25, v26 +; CHECK-NEXT: vsrl.vx v10, v9, a0 +; CHECK-NEXT: vsra.vi v9, v9, 1 +; CHECK-NEXT: vadd.vv v9, v9, v10 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -826,13 +826,13 @@ define @vrem_vi_nxv2i64_0( %va) { ; CHECK-NEXT: slli a0, a0, 12 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vmulh.vx v26, v8, a0 +; CHECK-NEXT: vmulh.vx v10, v8, a0 ; CHECK-NEXT: addi a0, zero, 63 -; CHECK-NEXT: vsrl.vx v28, v26, a0 -; CHECK-NEXT: vsra.vi v26, v26, 1 -; CHECK-NEXT: vadd.vv v26, v26, v28 +; CHECK-NEXT: vsrl.vx v12, v10, a0 +; CHECK-NEXT: vsra.vi v10, v10, 1 +; CHECK-NEXT: vadd.vv v10, v10, v12 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -874,13 +874,13 @@ define @vrem_vi_nxv4i64_0( %va) { ; CHECK-NEXT: slli a0, a0, 12 ; CHECK-NEXT: addi a0, a0, 1755 ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vmulh.vx v28, v8, a0 +; CHECK-NEXT: vmulh.vx v12, v8, a0 ; CHECK-NEXT: addi a0, zero, 63 -; CHECK-NEXT: vsrl.vx v12, v28, a0 -; CHECK-NEXT: vsra.vi v28, v28, 1 -; CHECK-NEXT: vadd.vv v28, v28, v12 +; CHECK-NEXT: vsrl.vx v16, v12, a0 +; CHECK-NEXT: vsra.vi v12, v12, 1 +; CHECK-NEXT: vadd.vv v12, v12, v16 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll index ede8de0acadd1d8c9c8a734b2fca62e1f6029e87..5b299da083174136a78db85ecc99e38734b253a1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll @@ -10,13 +10,13 @@ define @vrem_vx_nxv8i7( %a, i7 signext %b, undef, i7 %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -969,9 +969,9 @@ define @vrem_vx_nxv1i64( %va, i64 %b, @vrem_vx_nxv1i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vrem.vv v8, v8, v25 +; RV32-NEXT: vrem.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1047,9 +1047,9 @@ define @vrem_vx_nxv2i64( %va, i64 %b, @vrem_vx_nxv2i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vrem.vv v8, v8, v26 +; RV32-NEXT: vrem.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1125,9 +1125,9 @@ define @vrem_vx_nxv4i64( %va, i64 %b, @vrem_vx_nxv4i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vrem.vv v8, v8, v28 +; RV32-NEXT: vrem.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll index 9d468bd9a6c4aaed1df0b9088e851195f95df92c..8f1ebf185f620328f1577454added778eade7ab6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vremu_vx_nxv1i64_nxv1i64_i64( @intrinsic_vremu_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vremu_vx_nxv2i64_nxv2i64_i64( @intrinsic_vremu_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vremu_vx_nxv4i64_nxv4i64_i64( @intrinsic_vremu_mask_vx_nxv4i64_nxv4i64_i64( @vremu_vi_nxv1i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 5 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 5 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -66,10 +66,10 @@ define @vremu_vi_nxv2i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 5 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 5 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -104,10 +104,10 @@ define @vremu_vi_nxv4i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 5 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 5 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -142,10 +142,10 @@ define @vremu_vi_nxv8i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 5 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 5 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,10 +180,10 @@ define @vremu_vi_nxv16i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmulhu.vx v26, v8, a0 -; CHECK-NEXT: vsrl.vi v26, v26, 5 +; CHECK-NEXT: vmulhu.vx v10, v8, a0 +; CHECK-NEXT: vsrl.vi v10, v10, 5 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -218,10 +218,10 @@ define @vremu_vi_nxv32i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmulhu.vx v28, v8, a0 -; CHECK-NEXT: vsrl.vi v28, v28, 5 +; CHECK-NEXT: vmulhu.vx v12, v8, a0 +; CHECK-NEXT: vsrl.vi v12, v12, 5 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -295,10 +295,10 @@ define @vremu_vi_nxv1i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 13 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 13 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -334,10 +334,10 @@ define @vremu_vi_nxv2i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 13 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 13 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -373,10 +373,10 @@ define @vremu_vi_nxv4i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 13 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 13 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -412,10 +412,10 @@ define @vremu_vi_nxv8i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmulhu.vx v26, v8, a0 -; CHECK-NEXT: vsrl.vi v26, v26, 13 +; CHECK-NEXT: vmulhu.vx v10, v8, a0 +; CHECK-NEXT: vsrl.vi v10, v10, 13 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -451,10 +451,10 @@ define @vremu_vi_nxv16i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vmulhu.vx v28, v8, a0 -; CHECK-NEXT: vsrl.vi v28, v28, 13 +; CHECK-NEXT: vmulhu.vx v12, v8, a0 +; CHECK-NEXT: vsrl.vi v12, v12, 13 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -529,10 +529,10 @@ define @vremu_vi_nxv1i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 29 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 29 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -568,10 +568,10 @@ define @vremu_vi_nxv2i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 29 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 29 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -607,10 +607,10 @@ define @vremu_vi_nxv4i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vmulhu.vx v26, v8, a0 -; CHECK-NEXT: vsrl.vi v26, v26, 29 +; CHECK-NEXT: vmulhu.vx v10, v8, a0 +; CHECK-NEXT: vsrl.vi v10, v10, 29 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -646,10 +646,10 @@ define @vremu_vi_nxv8i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmulhu.vx v28, v8, a0 -; CHECK-NEXT: vsrl.vi v28, v28, 29 +; CHECK-NEXT: vmulhu.vx v12, v8, a0 +; CHECK-NEXT: vsrl.vi v12, v12, 29 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -715,8 +715,8 @@ define @vremu_vx_nxv1i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vremu.vv v8, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -736,12 +736,12 @@ define @vremu_vi_nxv1i64_0( %va) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vmulhu.vv v25, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vmulhu.vv v9, v8, v9 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v25, v25, a0 +; CHECK-NEXT: vsrl.vx v9, v9, a0 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 @@ -769,10 +769,10 @@ define @vremu_vi_nxv1i64_2( %va, undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -800,8 +800,8 @@ define @vremu_vx_nxv2i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vremu.vv v8, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vremu.vv v8, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -821,12 +821,12 @@ define @vremu_vi_nxv2i64_0( %va) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vmulhu.vv v26, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vmulhu.vv v10, v8, v10 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v26, v26, a0 +; CHECK-NEXT: vsrl.vx v10, v10, a0 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 @@ -854,10 +854,10 @@ define @vremu_vi_nxv2i64_2( %va, undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -885,8 +885,8 @@ define @vremu_vx_nxv4i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vremu.vv v8, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vremu.vv v8, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -906,12 +906,12 @@ define @vremu_vi_nxv4i64_0( %va) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vmulhu.vv v28, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vmulhu.vv v12, v8, v12 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v28, v28, a0 +; CHECK-NEXT: vsrl.vx v12, v12, a0 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 @@ -939,10 +939,10 @@ define @vremu_vi_nxv4i64_2( %va, undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll index 70bebb1fcf16871d585532144498b6b91b06a308..b8c112e94d7881f1a1166c99128a7bb8d6801b5a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll @@ -28,10 +28,10 @@ define @vremu_vi_nxv1i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 5 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 5 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -66,10 +66,10 @@ define @vremu_vi_nxv2i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 5 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 5 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -104,10 +104,10 @@ define @vremu_vi_nxv4i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 5 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 5 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -142,10 +142,10 @@ define @vremu_vi_nxv8i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 5 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 5 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,10 +180,10 @@ define @vremu_vi_nxv16i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmulhu.vx v26, v8, a0 -; CHECK-NEXT: vsrl.vi v26, v26, 5 +; CHECK-NEXT: vmulhu.vx v10, v8, a0 +; CHECK-NEXT: vsrl.vi v10, v10, 5 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -218,10 +218,10 @@ define @vremu_vi_nxv32i8_0( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu -; CHECK-NEXT: vmulhu.vx v28, v8, a0 -; CHECK-NEXT: vsrl.vi v28, v28, 5 +; CHECK-NEXT: vmulhu.vx v12, v8, a0 +; CHECK-NEXT: vsrl.vi v12, v12, 5 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -295,10 +295,10 @@ define @vremu_vi_nxv1i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 13 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 13 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -334,10 +334,10 @@ define @vremu_vi_nxv2i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 13 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 13 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -373,10 +373,10 @@ define @vremu_vi_nxv4i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 13 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 13 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -412,10 +412,10 @@ define @vremu_vi_nxv8i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu -; CHECK-NEXT: vmulhu.vx v26, v8, a0 -; CHECK-NEXT: vsrl.vi v26, v26, 13 +; CHECK-NEXT: vmulhu.vx v10, v8, a0 +; CHECK-NEXT: vsrl.vi v10, v10, 13 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -451,10 +451,10 @@ define @vremu_vi_nxv16i16_0( %va) { ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu -; CHECK-NEXT: vmulhu.vx v28, v8, a0 -; CHECK-NEXT: vsrl.vi v28, v28, 13 +; CHECK-NEXT: vmulhu.vx v12, v8, a0 +; CHECK-NEXT: vsrl.vi v12, v12, 13 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -529,10 +529,10 @@ define @vremu_vi_nxv1i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 29 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 29 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -568,10 +568,10 @@ define @vremu_vi_nxv2i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 -; CHECK-NEXT: vsrl.vi v25, v25, 29 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 +; CHECK-NEXT: vsrl.vi v9, v9, 29 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -607,10 +607,10 @@ define @vremu_vi_nxv4i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu -; CHECK-NEXT: vmulhu.vx v26, v8, a0 -; CHECK-NEXT: vsrl.vi v26, v26, 29 +; CHECK-NEXT: vmulhu.vx v10, v8, a0 +; CHECK-NEXT: vsrl.vi v10, v10, 29 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -646,10 +646,10 @@ define @vremu_vi_nxv8i32_0( %va) { ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addiw a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu -; CHECK-NEXT: vmulhu.vx v28, v8, a0 -; CHECK-NEXT: vsrl.vi v28, v28, 29 +; CHECK-NEXT: vmulhu.vx v12, v8, a0 +; CHECK-NEXT: vsrl.vi v12, v12, 29 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -725,11 +725,11 @@ define @vremu_vi_nxv1i64_0( %va) { ; CHECK-NEXT: slli a0, a0, 61 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu -; CHECK-NEXT: vmulhu.vx v25, v8, a0 +; CHECK-NEXT: vmulhu.vx v9, v8, a0 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v25, v25, a0 +; CHECK-NEXT: vsrl.vx v9, v9, a0 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v25 +; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -756,10 +756,10 @@ define @vremu_vi_nxv1i64_2( %va, undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -797,11 +797,11 @@ define @vremu_vi_nxv2i64_0( %va) { ; CHECK-NEXT: slli a0, a0, 61 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu -; CHECK-NEXT: vmulhu.vx v26, v8, a0 +; CHECK-NEXT: vmulhu.vx v10, v8, a0 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v26, v26, a0 +; CHECK-NEXT: vsrl.vx v10, v10, a0 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v26 +; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -828,10 +828,10 @@ define @vremu_vi_nxv2i64_2( %va, undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -869,11 +869,11 @@ define @vremu_vi_nxv4i64_0( %va) { ; CHECK-NEXT: slli a0, a0, 61 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu -; CHECK-NEXT: vmulhu.vx v28, v8, a0 +; CHECK-NEXT: vmulhu.vx v12, v8, a0 ; CHECK-NEXT: addi a0, zero, 61 -; CHECK-NEXT: vsrl.vx v28, v28, a0 +; CHECK-NEXT: vsrl.vx v12, v12, a0 ; CHECK-NEXT: addi a0, zero, -7 -; CHECK-NEXT: vnmsac.vx v8, a0, v28 +; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -900,10 +900,10 @@ define @vremu_vi_nxv4i64_2( %va, undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll index d1ce409e62cd3c49012f7c1fd2e6bb9ee6f832b3..cd1a4379b38bc1dc51b5875a3fb6fe31751c2707 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll @@ -11,11 +11,11 @@ define @vremu_vx_nxv8i7( %a, i7 signext %b, < ; CHECK: # %bb.0: ; CHECK-NEXT: addi a2, zero, 127 ; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, mu -; CHECK-NEXT: vand.vx v25, v8, a2 -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vand.vx v26, v26, a2 +; CHECK-NEXT: vand.vx v8, v8, a2 +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vand.vx v9, v9, a2 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vremu.vv v8, v25, v26, v0.t +; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement undef, i7 %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer @@ -968,9 +968,9 @@ define @vremu_vx_nxv1i64( %va, i64 %b, @vremu_vx_nxv1i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vremu.vv v8, v8, v25 +; RV32-NEXT: vremu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1046,9 +1046,9 @@ define @vremu_vx_nxv2i64( %va, i64 %b, @vremu_vx_nxv2i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vremu.vv v8, v8, v26 +; RV32-NEXT: vremu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1124,9 +1124,9 @@ define @vremu_vx_nxv4i64( %va, i64 %b, @vremu_vx_nxv4i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vremu.vv v8, v8, v28 +; RV32-NEXT: vremu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll index 3c596398d69aa57896571d226762b1137640f639..89bb37d9eb0e720c98a5de7823cf93f9137d15b4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll @@ -10,8 +10,8 @@ define @intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8( @llvm.riscv.vrgather.vv.nxv1i8.i32( @@ -56,8 +56,8 @@ define @intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8( @llvm.riscv.vrgather.vv.nxv2i8.i32( @@ -102,8 +102,8 @@ define @intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8( @llvm.riscv.vrgather.vv.nxv4i8.i32( @@ -148,8 +148,8 @@ define @intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8( @llvm.riscv.vrgather.vv.nxv8i8.i32( @@ -194,8 +194,8 @@ define @intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8( @llvm.riscv.vrgather.vv.nxv16i8.i32( @@ -240,8 +240,8 @@ define @intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8( @llvm.riscv.vrgather.vv.nxv32i8.i32( @@ -333,8 +333,8 @@ define @intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16( @llvm.riscv.vrgather.vv.nxv1i16.i32( @@ -379,8 +379,8 @@ define @intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16( @llvm.riscv.vrgather.vv.nxv2i16.i32( @@ -425,8 +425,8 @@ define @intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16( @llvm.riscv.vrgather.vv.nxv4i16.i32( @@ -471,8 +471,8 @@ define @intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16( @llvm.riscv.vrgather.vv.nxv8i16.i32( @@ -517,8 +517,8 @@ define @intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16( @llvm.riscv.vrgather.vv.nxv16i16.i32( @@ -610,8 +610,8 @@ define @intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32( @llvm.riscv.vrgather.vv.nxv1i32.i32( @@ -656,8 +656,8 @@ define @intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32( @llvm.riscv.vrgather.vv.nxv2i32.i32( @@ -702,8 +702,8 @@ define @intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32( @llvm.riscv.vrgather.vv.nxv4i32.i32( @@ -748,8 +748,8 @@ define @intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32( @llvm.riscv.vrgather.vv.nxv8i32.i32( @@ -841,8 +841,8 @@ define @intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16( @llvm.riscv.vrgather.vv.nxv1f16.i32( @@ -887,8 +887,8 @@ define @intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16( @llvm.riscv.vrgather.vv.nxv2f16.i32( @@ -933,8 +933,8 @@ define @intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16( @llvm.riscv.vrgather.vv.nxv4f16.i32( @@ -979,8 +979,8 @@ define @intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16( @llvm.riscv.vrgather.vv.nxv8f16.i32( @@ -1025,8 +1025,8 @@ define @intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16( @llvm.riscv.vrgather.vv.nxv16f16.i32( @@ -1118,8 +1118,8 @@ define @intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32( @llvm.riscv.vrgather.vv.nxv1f32.i32( @@ -1164,8 +1164,8 @@ define @intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32( @llvm.riscv.vrgather.vv.nxv2f32.i32( @@ -1210,8 +1210,8 @@ define @intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32( @llvm.riscv.vrgather.vv.nxv4f32.i32( @@ -1256,8 +1256,8 @@ define @intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32( @llvm.riscv.vrgather.vv.nxv8f32.i32( @@ -1349,8 +1349,8 @@ define @intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64( @llvm.riscv.vrgather.vv.nxv1f64.i32( @@ -1395,8 +1395,8 @@ define @intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64( @llvm.riscv.vrgather.vv.nxv2f64.i32( @@ -1441,8 +1441,8 @@ define @intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64( @llvm.riscv.vrgather.vv.nxv4f64.i32( @@ -1534,8 +1534,8 @@ define @intrinsic_vrgather_vx_nxv1i8_nxv1i8_i32( @llvm.riscv.vrgather.vx.nxv1i8.i32( @@ -1580,8 +1580,8 @@ define @intrinsic_vrgather_vx_nxv2i8_nxv2i8_i32( @llvm.riscv.vrgather.vx.nxv2i8.i32( @@ -1626,8 +1626,8 @@ define @intrinsic_vrgather_vx_nxv4i8_nxv4i8_i32( @llvm.riscv.vrgather.vx.nxv4i8.i32( @@ -1672,8 +1672,8 @@ define @intrinsic_vrgather_vx_nxv8i8_nxv8i8_i32( @llvm.riscv.vrgather.vx.nxv8i8.i32( @@ -1718,8 +1718,8 @@ define @intrinsic_vrgather_vx_nxv16i8_nxv16i8_i32( @llvm.riscv.vrgather.vx.nxv16i8.i32( @@ -1764,8 +1764,8 @@ define @intrinsic_vrgather_vx_nxv32i8_nxv32i8_i32( @llvm.riscv.vrgather.vx.nxv32i8.i32( @@ -1856,8 +1856,8 @@ define @intrinsic_vrgather_vx_nxv1i16_nxv1i16_i32( @llvm.riscv.vrgather.vx.nxv1i16.i32( @@ -1902,8 +1902,8 @@ define @intrinsic_vrgather_vx_nxv2i16_nxv2i16_i32( @llvm.riscv.vrgather.vx.nxv2i16.i32( @@ -1948,8 +1948,8 @@ define @intrinsic_vrgather_vx_nxv4i16_nxv4i16_i32( @llvm.riscv.vrgather.vx.nxv4i16.i32( @@ -1994,8 +1994,8 @@ define @intrinsic_vrgather_vx_nxv8i16_nxv8i16_i32( @llvm.riscv.vrgather.vx.nxv8i16.i32( @@ -2040,8 +2040,8 @@ define @intrinsic_vrgather_vx_nxv16i16_nxv16i16_i32( @llvm.riscv.vrgather.vx.nxv16i16.i32( @@ -2132,8 +2132,8 @@ define @intrinsic_vrgather_vx_nxv1i32_nxv1i32_i32( @llvm.riscv.vrgather.vx.nxv1i32.i32( @@ -2178,8 +2178,8 @@ define @intrinsic_vrgather_vx_nxv2i32_nxv2i32_i32( @llvm.riscv.vrgather.vx.nxv2i32.i32( @@ -2224,8 +2224,8 @@ define @intrinsic_vrgather_vx_nxv4i32_nxv4i32_i32( @llvm.riscv.vrgather.vx.nxv4i32.i32( @@ -2270,8 +2270,8 @@ define @intrinsic_vrgather_vx_nxv8i32_nxv8i32_i32( @llvm.riscv.vrgather.vx.nxv8i32.i32( @@ -2362,8 +2362,8 @@ define @intrinsic_vrgather_vx_nxv1f16_nxv1f16_i32( @llvm.riscv.vrgather.vx.nxv1f16.i32( @@ -2408,8 +2408,8 @@ define @intrinsic_vrgather_vx_nxv2f16_nxv2f16_i32( @llvm.riscv.vrgather.vx.nxv2f16.i32( @@ -2454,8 +2454,8 @@ define @intrinsic_vrgather_vx_nxv4f16_nxv4f16_i32( @llvm.riscv.vrgather.vx.nxv4f16.i32( @@ -2500,8 +2500,8 @@ define @intrinsic_vrgather_vx_nxv8f16_nxv8f16_i32( @llvm.riscv.vrgather.vx.nxv8f16.i32( @@ -2546,8 +2546,8 @@ define @intrinsic_vrgather_vx_nxv16f16_nxv16f16_i32( @llvm.riscv.vrgather.vx.nxv16f16.i32( @@ -2638,8 +2638,8 @@ define @intrinsic_vrgather_vx_nxv1f32_nxv1f32_i32( @llvm.riscv.vrgather.vx.nxv1f32.i32( @@ -2684,8 +2684,8 @@ define @intrinsic_vrgather_vx_nxv2f32_nxv2f32_i32( @llvm.riscv.vrgather.vx.nxv2f32.i32( @@ -2730,8 +2730,8 @@ define @intrinsic_vrgather_vx_nxv4f32_nxv4f32_i32( @llvm.riscv.vrgather.vx.nxv4f32.i32( @@ -2776,8 +2776,8 @@ define @intrinsic_vrgather_vx_nxv8f32_nxv8f32_i32( @llvm.riscv.vrgather.vx.nxv8f32.i32( @@ -2868,8 +2868,8 @@ define @intrinsic_vrgather_vx_nxv1f64_nxv1f64_i32( @llvm.riscv.vrgather.vx.nxv1f64.i32( @@ -2914,8 +2914,8 @@ define @intrinsic_vrgather_vx_nxv2f64_nxv2f64_i32( @llvm.riscv.vrgather.vx.nxv2f64.i32( @@ -2960,8 +2960,8 @@ define @intrinsic_vrgather_vx_nxv4f64_nxv4f64_i32( @llvm.riscv.vrgather.vx.nxv4f64.i32( @@ -3047,8 +3047,8 @@ define @intrinsic_vrgather_vi_nxv1i8_nxv1i8_i32( @llvm.riscv.vrgather.vx.nxv1i8.i32( @@ -3080,8 +3080,8 @@ define @intrinsic_vrgather_vi_nxv2i8_nxv2i8_i32( @llvm.riscv.vrgather.vx.nxv2i8.i32( @@ -3113,8 +3113,8 @@ define @intrinsic_vrgather_vi_nxv4i8_nxv4i8_i32( @llvm.riscv.vrgather.vx.nxv4i8.i32( @@ -3146,8 +3146,8 @@ define @intrinsic_vrgather_vi_nxv8i8_nxv8i8_i32( @llvm.riscv.vrgather.vx.nxv8i8.i32( @@ -3179,8 +3179,8 @@ define @intrinsic_vrgather_vi_nxv16i8_nxv16i8_i32( @llvm.riscv.vrgather.vx.nxv16i8.i32( @@ -3212,8 +3212,8 @@ define @intrinsic_vrgather_vi_nxv32i8_nxv32i8_i32( @llvm.riscv.vrgather.vx.nxv32i8.i32( @@ -3278,8 +3278,8 @@ define @intrinsic_vrgather_vi_nxv1i16_nxv1i16_i32( @llvm.riscv.vrgather.vx.nxv1i16.i32( @@ -3311,8 +3311,8 @@ define @intrinsic_vrgather_vi_nxv2i16_nxv2i16_i32( @llvm.riscv.vrgather.vx.nxv2i16.i32( @@ -3344,8 +3344,8 @@ define @intrinsic_vrgather_vi_nxv4i16_nxv4i16_i32( @llvm.riscv.vrgather.vx.nxv4i16.i32( @@ -3377,8 +3377,8 @@ define @intrinsic_vrgather_vi_nxv8i16_nxv8i16_i32( @llvm.riscv.vrgather.vx.nxv8i16.i32( @@ -3410,8 +3410,8 @@ define @intrinsic_vrgather_vi_nxv16i16_nxv16i16_i32( @llvm.riscv.vrgather.vx.nxv16i16.i32( @@ -3476,8 +3476,8 @@ define @intrinsic_vrgather_vi_nxv1i32_nxv1i32_i32( @llvm.riscv.vrgather.vx.nxv1i32.i32( @@ -3509,8 +3509,8 @@ define @intrinsic_vrgather_vi_nxv2i32_nxv2i32_i32( @llvm.riscv.vrgather.vx.nxv2i32.i32( @@ -3542,8 +3542,8 @@ define @intrinsic_vrgather_vi_nxv4i32_nxv4i32_i32( @llvm.riscv.vrgather.vx.nxv4i32.i32( @@ -3575,8 +3575,8 @@ define @intrinsic_vrgather_vi_nxv8i32_nxv8i32_i32( @llvm.riscv.vrgather.vx.nxv8i32.i32( @@ -3641,8 +3641,8 @@ define @intrinsic_vrgather_vi_nxv1f16_nxv1f16_i32( @llvm.riscv.vrgather.vx.nxv1f16.i32( @@ -3674,8 +3674,8 @@ define @intrinsic_vrgather_vi_nxv2f16_nxv2f16_i32( @llvm.riscv.vrgather.vx.nxv2f16.i32( @@ -3707,8 +3707,8 @@ define @intrinsic_vrgather_vi_nxv4f16_nxv4f16_i32( @llvm.riscv.vrgather.vx.nxv4f16.i32( @@ -3740,8 +3740,8 @@ define @intrinsic_vrgather_vi_nxv8f16_nxv8f16_i32( @llvm.riscv.vrgather.vx.nxv8f16.i32( @@ -3773,8 +3773,8 @@ define @intrinsic_vrgather_vi_nxv16f16_nxv16f16_i32( @llvm.riscv.vrgather.vx.nxv16f16.i32( @@ -3839,8 +3839,8 @@ define @intrinsic_vrgather_vi_nxv1f32_nxv1f32_i32( @llvm.riscv.vrgather.vx.nxv1f32.i32( @@ -3872,8 +3872,8 @@ define @intrinsic_vrgather_vi_nxv2f32_nxv2f32_i32( @llvm.riscv.vrgather.vx.nxv2f32.i32( @@ -3905,8 +3905,8 @@ define @intrinsic_vrgather_vi_nxv4f32_nxv4f32_i32( @llvm.riscv.vrgather.vx.nxv4f32.i32( @@ -3938,8 +3938,8 @@ define @intrinsic_vrgather_vi_nxv8f32_nxv8f32_i32( @llvm.riscv.vrgather.vx.nxv8f32.i32( @@ -4004,8 +4004,8 @@ define @intrinsic_vrgather_vi_nxv1f64_nxv1f64_i32( @llvm.riscv.vrgather.vx.nxv1f64.i32( @@ -4037,8 +4037,8 @@ define @intrinsic_vrgather_vi_nxv2f64_nxv2f64_i32( @llvm.riscv.vrgather.vx.nxv2f64.i32( @@ -4070,8 +4070,8 @@ define @intrinsic_vrgather_vi_nxv4f64_nxv4f64_i32( @llvm.riscv.vrgather.vx.nxv4f64.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll index 3c571f23af4a8b2db1cade7a5dce0a1664c8192f..7c94903ee064407dd23b232863897c0bca653392 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll @@ -10,8 +10,8 @@ define @intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8( @llvm.riscv.vrgather.vv.nxv1i8.i64( @@ -56,8 +56,8 @@ define @intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8( @llvm.riscv.vrgather.vv.nxv2i8.i64( @@ -102,8 +102,8 @@ define @intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8( @llvm.riscv.vrgather.vv.nxv4i8.i64( @@ -148,8 +148,8 @@ define @intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8( @llvm.riscv.vrgather.vv.nxv8i8.i64( @@ -194,8 +194,8 @@ define @intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8( @llvm.riscv.vrgather.vv.nxv16i8.i64( @@ -240,8 +240,8 @@ define @intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8( @llvm.riscv.vrgather.vv.nxv32i8.i64( @@ -333,8 +333,8 @@ define @intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16( @llvm.riscv.vrgather.vv.nxv1i16.i64( @@ -379,8 +379,8 @@ define @intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16( @llvm.riscv.vrgather.vv.nxv2i16.i64( @@ -425,8 +425,8 @@ define @intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16( @llvm.riscv.vrgather.vv.nxv4i16.i64( @@ -471,8 +471,8 @@ define @intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16( @llvm.riscv.vrgather.vv.nxv8i16.i64( @@ -517,8 +517,8 @@ define @intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16( @llvm.riscv.vrgather.vv.nxv16i16.i64( @@ -610,8 +610,8 @@ define @intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32( @llvm.riscv.vrgather.vv.nxv1i32.i64( @@ -656,8 +656,8 @@ define @intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32( @llvm.riscv.vrgather.vv.nxv2i32.i64( @@ -702,8 +702,8 @@ define @intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32( @llvm.riscv.vrgather.vv.nxv4i32.i64( @@ -748,8 +748,8 @@ define @intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32( @llvm.riscv.vrgather.vv.nxv8i32.i64( @@ -841,8 +841,8 @@ define @intrinsic_vrgather_vv_nxv1i64_nxv1i64_nxv1i64( @llvm.riscv.vrgather.vv.nxv1i64.i64( @@ -887,8 +887,8 @@ define @intrinsic_vrgather_vv_nxv2i64_nxv2i64_nxv2i64( @llvm.riscv.vrgather.vv.nxv2i64.i64( @@ -933,8 +933,8 @@ define @intrinsic_vrgather_vv_nxv4i64_nxv4i64_nxv4i64( @llvm.riscv.vrgather.vv.nxv4i64.i64( @@ -1026,8 +1026,8 @@ define @intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16( @llvm.riscv.vrgather.vv.nxv1f16.i64( @@ -1072,8 +1072,8 @@ define @intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16( @llvm.riscv.vrgather.vv.nxv2f16.i64( @@ -1118,8 +1118,8 @@ define @intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16( @llvm.riscv.vrgather.vv.nxv4f16.i64( @@ -1164,8 +1164,8 @@ define @intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16( @llvm.riscv.vrgather.vv.nxv8f16.i64( @@ -1210,8 +1210,8 @@ define @intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16( @llvm.riscv.vrgather.vv.nxv16f16.i64( @@ -1303,8 +1303,8 @@ define @intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32( @llvm.riscv.vrgather.vv.nxv1f32.i64( @@ -1349,8 +1349,8 @@ define @intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32( @llvm.riscv.vrgather.vv.nxv2f32.i64( @@ -1395,8 +1395,8 @@ define @intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32( @llvm.riscv.vrgather.vv.nxv4f32.i64( @@ -1441,8 +1441,8 @@ define @intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32( @llvm.riscv.vrgather.vv.nxv8f32.i64( @@ -1534,8 +1534,8 @@ define @intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64( @llvm.riscv.vrgather.vv.nxv1f64.i64( @@ -1580,8 +1580,8 @@ define @intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64( @llvm.riscv.vrgather.vv.nxv2f64.i64( @@ -1626,8 +1626,8 @@ define @intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64( @llvm.riscv.vrgather.vv.nxv4f64.i64( @@ -1719,8 +1719,8 @@ define @intrinsic_vrgather_vx_nxv1i8_nxv1i8_i64( @llvm.riscv.vrgather.vx.nxv1i8.i64( @@ -1765,8 +1765,8 @@ define @intrinsic_vrgather_vx_nxv2i8_nxv2i8_i64( @llvm.riscv.vrgather.vx.nxv2i8.i64( @@ -1811,8 +1811,8 @@ define @intrinsic_vrgather_vx_nxv4i8_nxv4i8_i64( @llvm.riscv.vrgather.vx.nxv4i8.i64( @@ -1857,8 +1857,8 @@ define @intrinsic_vrgather_vx_nxv8i8_nxv8i8_i64( @llvm.riscv.vrgather.vx.nxv8i8.i64( @@ -1903,8 +1903,8 @@ define @intrinsic_vrgather_vx_nxv16i8_nxv16i8_i64( @llvm.riscv.vrgather.vx.nxv16i8.i64( @@ -1949,8 +1949,8 @@ define @intrinsic_vrgather_vx_nxv32i8_nxv32i8_i64( @llvm.riscv.vrgather.vx.nxv32i8.i64( @@ -2041,8 +2041,8 @@ define @intrinsic_vrgather_vx_nxv1i16_nxv1i16_i64( @llvm.riscv.vrgather.vx.nxv1i16.i64( @@ -2087,8 +2087,8 @@ define @intrinsic_vrgather_vx_nxv2i16_nxv2i16_i64( @llvm.riscv.vrgather.vx.nxv2i16.i64( @@ -2133,8 +2133,8 @@ define @intrinsic_vrgather_vx_nxv4i16_nxv4i16_i64( @llvm.riscv.vrgather.vx.nxv4i16.i64( @@ -2179,8 +2179,8 @@ define @intrinsic_vrgather_vx_nxv8i16_nxv8i16_i64( @llvm.riscv.vrgather.vx.nxv8i16.i64( @@ -2225,8 +2225,8 @@ define @intrinsic_vrgather_vx_nxv16i16_nxv16i16_i64( @llvm.riscv.vrgather.vx.nxv16i16.i64( @@ -2317,8 +2317,8 @@ define @intrinsic_vrgather_vx_nxv1i32_nxv1i32_i64( @llvm.riscv.vrgather.vx.nxv1i32.i64( @@ -2363,8 +2363,8 @@ define @intrinsic_vrgather_vx_nxv2i32_nxv2i32_i64( @llvm.riscv.vrgather.vx.nxv2i32.i64( @@ -2409,8 +2409,8 @@ define @intrinsic_vrgather_vx_nxv4i32_nxv4i32_i64( @llvm.riscv.vrgather.vx.nxv4i32.i64( @@ -2455,8 +2455,8 @@ define @intrinsic_vrgather_vx_nxv8i32_nxv8i32_i64( @llvm.riscv.vrgather.vx.nxv8i32.i64( @@ -2547,8 +2547,8 @@ define @intrinsic_vrgather_vx_nxv1i64_nxv1i64_i64( @llvm.riscv.vrgather.vx.nxv1i64.i64( @@ -2593,8 +2593,8 @@ define @intrinsic_vrgather_vx_nxv2i64_nxv2i64_i64( @llvm.riscv.vrgather.vx.nxv2i64.i64( @@ -2639,8 +2639,8 @@ define @intrinsic_vrgather_vx_nxv4i64_nxv4i64_i64( @llvm.riscv.vrgather.vx.nxv4i64.i64( @@ -2731,8 +2731,8 @@ define @intrinsic_vrgather_vx_nxv1f16_nxv1f16_i64( @llvm.riscv.vrgather.vx.nxv1f16.i64( @@ -2777,8 +2777,8 @@ define @intrinsic_vrgather_vx_nxv2f16_nxv2f16_i64( @llvm.riscv.vrgather.vx.nxv2f16.i64( @@ -2823,8 +2823,8 @@ define @intrinsic_vrgather_vx_nxv4f16_nxv4f16_i64( @llvm.riscv.vrgather.vx.nxv4f16.i64( @@ -2869,8 +2869,8 @@ define @intrinsic_vrgather_vx_nxv8f16_nxv8f16_i64( @llvm.riscv.vrgather.vx.nxv8f16.i64( @@ -2915,8 +2915,8 @@ define @intrinsic_vrgather_vx_nxv16f16_nxv16f16_i64( @llvm.riscv.vrgather.vx.nxv16f16.i64( @@ -3007,8 +3007,8 @@ define @intrinsic_vrgather_vx_nxv1f32_nxv1f32_i64( @llvm.riscv.vrgather.vx.nxv1f32.i64( @@ -3053,8 +3053,8 @@ define @intrinsic_vrgather_vx_nxv2f32_nxv2f32_i64( @llvm.riscv.vrgather.vx.nxv2f32.i64( @@ -3099,8 +3099,8 @@ define @intrinsic_vrgather_vx_nxv4f32_nxv4f32_i64( @llvm.riscv.vrgather.vx.nxv4f32.i64( @@ -3145,8 +3145,8 @@ define @intrinsic_vrgather_vx_nxv8f32_nxv8f32_i64( @llvm.riscv.vrgather.vx.nxv8f32.i64( @@ -3237,8 +3237,8 @@ define @intrinsic_vrgather_vx_nxv1f64_nxv1f64_i64( @llvm.riscv.vrgather.vx.nxv1f64.i64( @@ -3283,8 +3283,8 @@ define @intrinsic_vrgather_vx_nxv2f64_nxv2f64_i64( @llvm.riscv.vrgather.vx.nxv2f64.i64( @@ -3329,8 +3329,8 @@ define @intrinsic_vrgather_vx_nxv4f64_nxv4f64_i64( @llvm.riscv.vrgather.vx.nxv4f64.i64( @@ -3416,8 +3416,8 @@ define @intrinsic_vrgather_vi_nxv1i8_nxv1i8_i64( @llvm.riscv.vrgather.vx.nxv1i8.i64( @@ -3449,8 +3449,8 @@ define @intrinsic_vrgather_vi_nxv2i8_nxv2i8_i64( @llvm.riscv.vrgather.vx.nxv2i8.i64( @@ -3482,8 +3482,8 @@ define @intrinsic_vrgather_vi_nxv4i8_nxv4i8_i64( @llvm.riscv.vrgather.vx.nxv4i8.i64( @@ -3515,8 +3515,8 @@ define @intrinsic_vrgather_vi_nxv8i8_nxv8i8_i64( @llvm.riscv.vrgather.vx.nxv8i8.i64( @@ -3548,8 +3548,8 @@ define @intrinsic_vrgather_vi_nxv16i8_nxv16i8_i64( @llvm.riscv.vrgather.vx.nxv16i8.i64( @@ -3581,8 +3581,8 @@ define @intrinsic_vrgather_vi_nxv32i8_nxv32i8_i64( @llvm.riscv.vrgather.vx.nxv32i8.i64( @@ -3647,8 +3647,8 @@ define @intrinsic_vrgather_vi_nxv1i16_nxv1i16_i64( @llvm.riscv.vrgather.vx.nxv1i16.i64( @@ -3680,8 +3680,8 @@ define @intrinsic_vrgather_vi_nxv2i16_nxv2i16_i64( @llvm.riscv.vrgather.vx.nxv2i16.i64( @@ -3713,8 +3713,8 @@ define @intrinsic_vrgather_vi_nxv4i16_nxv4i16_i64( @llvm.riscv.vrgather.vx.nxv4i16.i64( @@ -3746,8 +3746,8 @@ define @intrinsic_vrgather_vi_nxv8i16_nxv8i16_i64( @llvm.riscv.vrgather.vx.nxv8i16.i64( @@ -3779,8 +3779,8 @@ define @intrinsic_vrgather_vi_nxv16i16_nxv16i16_i64( @llvm.riscv.vrgather.vx.nxv16i16.i64( @@ -3845,8 +3845,8 @@ define @intrinsic_vrgather_vi_nxv1i32_nxv1i32_i64( @llvm.riscv.vrgather.vx.nxv1i32.i64( @@ -3878,8 +3878,8 @@ define @intrinsic_vrgather_vi_nxv2i32_nxv2i32_i64( @llvm.riscv.vrgather.vx.nxv2i32.i64( @@ -3911,8 +3911,8 @@ define @intrinsic_vrgather_vi_nxv4i32_nxv4i32_i64( @llvm.riscv.vrgather.vx.nxv4i32.i64( @@ -3944,8 +3944,8 @@ define @intrinsic_vrgather_vi_nxv8i32_nxv8i32_i64( @llvm.riscv.vrgather.vx.nxv8i32.i64( @@ -4010,8 +4010,8 @@ define @intrinsic_vrgather_vi_nxv1i64_nxv1i64_i64( @llvm.riscv.vrgather.vx.nxv1i64.i64( @@ -4043,8 +4043,8 @@ define @intrinsic_vrgather_vi_nxv2i64_nxv2i64_i64( @llvm.riscv.vrgather.vx.nxv2i64.i64( @@ -4076,8 +4076,8 @@ define @intrinsic_vrgather_vi_nxv4i64_nxv4i64_i64( @llvm.riscv.vrgather.vx.nxv4i64.i64( @@ -4142,8 +4142,8 @@ define @intrinsic_vrgather_vi_nxv1f16_nxv1f16_i64( @llvm.riscv.vrgather.vx.nxv1f16.i64( @@ -4175,8 +4175,8 @@ define @intrinsic_vrgather_vi_nxv2f16_nxv2f16_i64( @llvm.riscv.vrgather.vx.nxv2f16.i64( @@ -4208,8 +4208,8 @@ define @intrinsic_vrgather_vi_nxv4f16_nxv4f16_i64( @llvm.riscv.vrgather.vx.nxv4f16.i64( @@ -4241,8 +4241,8 @@ define @intrinsic_vrgather_vi_nxv8f16_nxv8f16_i64( @llvm.riscv.vrgather.vx.nxv8f16.i64( @@ -4274,8 +4274,8 @@ define @intrinsic_vrgather_vi_nxv16f16_nxv16f16_i64( @llvm.riscv.vrgather.vx.nxv16f16.i64( @@ -4340,8 +4340,8 @@ define @intrinsic_vrgather_vi_nxv1f32_nxv1f32_i64( @llvm.riscv.vrgather.vx.nxv1f32.i64( @@ -4373,8 +4373,8 @@ define @intrinsic_vrgather_vi_nxv2f32_nxv2f32_i64( @llvm.riscv.vrgather.vx.nxv2f32.i64( @@ -4406,8 +4406,8 @@ define @intrinsic_vrgather_vi_nxv4f32_nxv4f32_i64( @llvm.riscv.vrgather.vx.nxv4f32.i64( @@ -4439,8 +4439,8 @@ define @intrinsic_vrgather_vi_nxv8f32_nxv8f32_i64( @llvm.riscv.vrgather.vx.nxv8f32.i64( @@ -4505,8 +4505,8 @@ define @intrinsic_vrgather_vi_nxv1f64_nxv1f64_i64( @llvm.riscv.vrgather.vx.nxv1f64.i64( @@ -4538,8 +4538,8 @@ define @intrinsic_vrgather_vi_nxv2f64_nxv2f64_i64( @llvm.riscv.vrgather.vx.nxv2f64.i64( @@ -4571,8 +4571,8 @@ define @intrinsic_vrgather_vi_nxv4f64_nxv4f64_i64( @llvm.riscv.vrgather.vx.nxv4f64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll index f4842d35b82b5ba9a01bf102d533be8e62516ded..91d2d15a898493829b74893f26c5d87d796ca681 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll @@ -10,8 +10,8 @@ define @intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8( @llvm.riscv.vrgatherei16.vv.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8( @llvm.riscv.vrgatherei16.vv.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8( @llvm.riscv.vrgatherei16.vv.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8( @llvm.riscv.vrgatherei16.vv.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8( @llvm.riscv.vrgatherei16.vv.nxv16i8( @@ -240,8 +240,8 @@ define @intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8( @llvm.riscv.vrgatherei16.vv.nxv32i8( @@ -286,8 +286,8 @@ define @intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16( @llvm.riscv.vrgatherei16.vv.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16( @llvm.riscv.vrgatherei16.vv.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16( @llvm.riscv.vrgatherei16.vv.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16( @llvm.riscv.vrgatherei16.vv.nxv8i16( @@ -470,8 +470,8 @@ define @intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16( @llvm.riscv.vrgatherei16.vv.nxv16i16( @@ -563,8 +563,8 @@ define @intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32( @llvm.riscv.vrgatherei16.vv.nxv1i32( @@ -609,8 +609,8 @@ define @intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32( @llvm.riscv.vrgatherei16.vv.nxv4i32( @@ -655,8 +655,8 @@ define @intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32( @llvm.riscv.vrgatherei16.vv.nxv8i32( @@ -724,9 +724,9 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv16i32( define @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t +; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vrgatherei16.vv.mask.nxv16i32( @@ -748,8 +748,8 @@ define @intrinsic_vrgatherei16_vv_nxv4i64_nxv4i64( @llvm.riscv.vrgatherei16.vv.nxv4i64( @@ -817,9 +817,9 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv8i64( define @intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl2re16.v v26, (a0) +; CHECK-NEXT: vl2re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t +; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vrgatherei16.vv.mask.nxv8i64( @@ -841,8 +841,8 @@ define @intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16( @llvm.riscv.vrgatherei16.vv.nxv1f16( @@ -887,8 +887,8 @@ define @intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16( @llvm.riscv.vrgatherei16.vv.nxv2f16( @@ -933,8 +933,8 @@ define @intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16( @llvm.riscv.vrgatherei16.vv.nxv4f16( @@ -979,8 +979,8 @@ define @intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16( @llvm.riscv.vrgatherei16.vv.nxv8f16( @@ -1025,8 +1025,8 @@ define @intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16( @llvm.riscv.vrgatherei16.vv.nxv16f16( @@ -1118,8 +1118,8 @@ define @intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32( @llvm.riscv.vrgatherei16.vv.nxv1f32( @@ -1164,8 +1164,8 @@ define @intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32( @llvm.riscv.vrgatherei16.vv.nxv4f32( @@ -1210,8 +1210,8 @@ define @intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32( @llvm.riscv.vrgatherei16.vv.nxv8f32( @@ -1279,9 +1279,9 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv16f32( define @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t +; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vrgatherei16.vv.mask.nxv16f32( @@ -1303,8 +1303,8 @@ define @intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64( @llvm.riscv.vrgatherei16.vv.nxv4f64( @@ -1372,9 +1372,9 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv8f64( define @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl2re16.v v26, (a0) +; CHECK-NEXT: vl2re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t +; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vrgatherei16.vv.mask.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll index 44a6cff647ff08a4c6f0a585b2159b478d18c3f7..f08d485c64b3a442105232ce4af33732dacce9b0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll @@ -10,8 +10,8 @@ define @intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8( @llvm.riscv.vrgatherei16.vv.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8( @llvm.riscv.vrgatherei16.vv.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8( @llvm.riscv.vrgatherei16.vv.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8( @llvm.riscv.vrgatherei16.vv.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8( @llvm.riscv.vrgatherei16.vv.nxv16i8( @@ -240,8 +240,8 @@ define @intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8( @llvm.riscv.vrgatherei16.vv.nxv32i8( @@ -286,8 +286,8 @@ define @intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16( @llvm.riscv.vrgatherei16.vv.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16( @llvm.riscv.vrgatherei16.vv.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16( @llvm.riscv.vrgatherei16.vv.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16( @llvm.riscv.vrgatherei16.vv.nxv8i16( @@ -470,8 +470,8 @@ define @intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16( @llvm.riscv.vrgatherei16.vv.nxv16i16( @@ -563,8 +563,8 @@ define @intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32( @llvm.riscv.vrgatherei16.vv.nxv1i32( @@ -609,8 +609,8 @@ define @intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32( @llvm.riscv.vrgatherei16.vv.nxv4i32( @@ -655,8 +655,8 @@ define @intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32( @llvm.riscv.vrgatherei16.vv.nxv8i32( @@ -724,9 +724,9 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv16i32( define @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t +; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vrgatherei16.vv.mask.nxv16i32( @@ -748,8 +748,8 @@ define @intrinsic_vrgatherei16_vv_nxv4i64_nxv4i64( @llvm.riscv.vrgatherei16.vv.nxv4i64( @@ -817,9 +817,9 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv8i64( define @intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl2re16.v v26, (a0) +; CHECK-NEXT: vl2re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t +; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vrgatherei16.vv.mask.nxv8i64( @@ -841,8 +841,8 @@ define @intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16( @llvm.riscv.vrgatherei16.vv.nxv1f16( @@ -887,8 +887,8 @@ define @intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16( @llvm.riscv.vrgatherei16.vv.nxv2f16( @@ -933,8 +933,8 @@ define @intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16( @llvm.riscv.vrgatherei16.vv.nxv4f16( @@ -979,8 +979,8 @@ define @intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16( @llvm.riscv.vrgatherei16.vv.nxv8f16( @@ -1025,8 +1025,8 @@ define @intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16( @llvm.riscv.vrgatherei16.vv.nxv16f16( @@ -1118,8 +1118,8 @@ define @intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32( @llvm.riscv.vrgatherei16.vv.nxv1f32( @@ -1164,8 +1164,8 @@ define @intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32( @llvm.riscv.vrgatherei16.vv.nxv4f32( @@ -1210,8 +1210,8 @@ define @intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32( @llvm.riscv.vrgatherei16.vv.nxv8f32( @@ -1279,9 +1279,9 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv16f32( define @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu -; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t +; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vrgatherei16.vv.mask.nxv16f32( @@ -1303,8 +1303,8 @@ define @intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64( @llvm.riscv.vrgatherei16.vv.nxv4f64( @@ -1372,9 +1372,9 @@ declare @llvm.riscv.vrgatherei16.vv.mask.nxv8f64( define @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl2re16.v v26, (a0) +; CHECK-NEXT: vl2re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu -; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t +; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vrgatherei16.vv.mask.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll index e9675eb3103208affe8b6e26444ad545ff264a33..d0474e9397b5b57dc96a9f6af0a65a596ab2518b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll @@ -824,8 +824,8 @@ define @intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64( @intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64( @intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64( @intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64( @vrsub_vx_nxv1i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vsub.vv v8, v25, v8 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vsub.vv v8, v9, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -473,8 +473,8 @@ define @vrsub_vx_nxv2i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vsub.vv v8, v26, v8 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vsub.vv v8, v10, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -504,8 +504,8 @@ define @vrsub_vx_nxv4i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vsub.vv v8, v28, v8 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vsub.vv v8, v12, v8 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll index 333b519dd5eddd5a09cb6e56afbb28d2cd3e9bd6..99bf38d64c92bd31d4a93d063788b4e4061e851a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll @@ -987,9 +987,9 @@ define @vrsub_vx_nxv1i64( %va, i64 %b, @vrsub_vx_nxv1i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vsub.vv v8, v25, v8 +; RV32-NEXT: vsub.vv v8, v9, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1069,9 +1069,9 @@ define @vrsub_vx_nxv2i64( %va, i64 %b, @vrsub_vx_nxv2i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vsub.vv v8, v26, v8 +; RV32-NEXT: vsub.vv v8, v10, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1151,9 +1151,9 @@ define @vrsub_vx_nxv4i64( %va, i64 %b, @vrsub_vx_nxv4i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vsub.vv v8, v28, v8 +; RV32-NEXT: vsub.vv v8, v12, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll index b5036009a589f867076786ef9a1e855fb419f1a9..610e277942d5a783ca15491280487633ccf94175 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64( @intrinsic_vsadd_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vsadd_vx_nxv2i64_nxv2i64_i64( @intrinsic_vsadd_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vsadd_vx_nxv4i64_nxv4i64_i64( @intrinsic_vsadd_mask_vx_nxv4i64_nxv4i64_i64( @sadd_nxv1i64_vx( %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero -; RV32-NEXT: vsadd.vv v8, v8, v25 +; RV32-NEXT: vlse64.v v9, (a0), zero +; RV32-NEXT: vsadd.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -722,8 +722,8 @@ define @sadd_nxv2i64_vx( %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero -; RV32-NEXT: vsadd.vv v8, v8, v26 +; RV32-NEXT: vlse64.v v10, (a0), zero +; RV32-NEXT: vsadd.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -771,8 +771,8 @@ define @sadd_nxv4i64_vx( %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero -; RV32-NEXT: vsadd.vv v8, v8, v28 +; RV32-NEXT: vlse64.v v12, (a0), zero +; RV32-NEXT: vsadd.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll index 609ba4a28baa656337de83423e121469eaf62972..7223bf6f11d5dfcabdd23399419e9a54c5f1a014 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vsaddu_vx_nxv1i64_nxv1i64_i64( @intrinsic_vsaddu_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vsaddu_vx_nxv2i64_nxv2i64_i64( @intrinsic_vsaddu_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vsaddu_vx_nxv4i64_nxv4i64_i64( @intrinsic_vsaddu_mask_vx_nxv4i64_nxv4i64_i64( @uadd_nxv1i64_vx( %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero -; RV32-NEXT: vsaddu.vv v8, v8, v25 +; RV32-NEXT: vlse64.v v9, (a0), zero +; RV32-NEXT: vsaddu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -722,8 +722,8 @@ define @uadd_nxv2i64_vx( %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero -; RV32-NEXT: vsaddu.vv v8, v8, v26 +; RV32-NEXT: vlse64.v v10, (a0), zero +; RV32-NEXT: vsaddu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -771,8 +771,8 @@ define @uadd_nxv4i64_vx( %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero -; RV32-NEXT: vsaddu.vv v8, v8, v28 +; RV32-NEXT: vlse64.v v12, (a0), zero +; RV32-NEXT: vsaddu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll index 422463b7bb0bc939bc6e1d8289cfe32d08ce73d1..c15ad9f2f3a1bc03981bad8f0580e1dee7ccd7ca 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll @@ -895,8 +895,8 @@ define @intrinsic_vsbc_vxm_nxv1i64_nxv1i64_i64( @intrinsic_vsbc_vxm_nxv2i64_nxv2i64_i64( @intrinsic_vsbc_vxm_nxv4i64_nxv4i64_i64( @vselect_combine_regression( %v ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vl8re64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmseq.vi v25, v16, 0 +; CHECK-NEXT: vmseq.vi v24, v16, 0 ; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vmseq.vi v0, v16, 0 ; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: add a0, sp, a0 @@ -435,8 +435,8 @@ define void @vselect_legalize_regression( %a, @vselect_combine_regression( %v ; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: sub sp, sp, a1 -; CHECK-NEXT: vmv8r.v v0, v16 ; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: add a1, a0, a1 -; CHECK-NEXT: vl8re64.v v16, (a1) -; CHECK-NEXT: vl8re64.v v24, (a0) +; CHECK-NEXT: vl8re64.v v24, (a1) +; CHECK-NEXT: vl8re64.v v0, (a0) ; CHECK-NEXT: addi a0, sp, 16 -; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill +; CHECK-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu -; CHECK-NEXT: vmseq.vi v25, v8, 0 -; CHECK-NEXT: vmseq.vi v0, v0, 0 +; CHECK-NEXT: vmseq.vi v1, v8, 0 +; CHECK-NEXT: vmseq.vi v0, v16, 0 ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 -; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0 +; CHECK-NEXT: vmv1r.v v0, v1 ; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: vl8re8.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0 @@ -426,8 +425,8 @@ define void @vselect_legalize_regression( %a, @vmerge_xv_nxv1i64( %va, i64 %b, undef, i64 %b, i32 0 @@ -673,8 +673,8 @@ define @vmerge_xv_nxv2i64( %va, i64 %b, undef, i64 %b, i32 0 @@ -714,8 +714,8 @@ define @vmerge_xv_nxv4i64( %va, i64 %b, undef, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll index bff226bc11f8d236fd043f80cb465509c992b47f..0862603c3200d935a18c4e9bbcd2a5c6cd3fe00e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll @@ -6,9 +6,9 @@ define @vselect_nxv1i1( %a, ; CHECK-LABEL: vselect_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmandnot.mm v25, v8, v9 -; CHECK-NEXT: vmand.mm v26, v0, v9 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select %cc, %a, %b ret %v @@ -18,9 +18,9 @@ define @vselect_nxv2i1( %a, ; CHECK-LABEL: vselect_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmandnot.mm v25, v8, v9 -; CHECK-NEXT: vmand.mm v26, v0, v9 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select %cc, %a, %b ret %v @@ -30,9 +30,9 @@ define @vselect_nxv4i1( %a, ; CHECK-LABEL: vselect_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmandnot.mm v25, v8, v9 -; CHECK-NEXT: vmand.mm v26, v0, v9 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select %cc, %a, %b ret %v @@ -42,9 +42,9 @@ define @vselect_nxv8i1( %a, ; CHECK-LABEL: vselect_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vmandnot.mm v25, v8, v9 -; CHECK-NEXT: vmand.mm v26, v0, v9 -; CHECK-NEXT: vmor.mm v0, v26, v25 +; CHECK-NEXT: vmandnot.mm v8, v8, v9 +; CHECK-NEXT: vmand.mm v9, v0, v9 +; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: ret %v = select %cc, %a, %b ret %v @@ -54,9 +54,9 @@ define @vselect_nxv16i1( %a, %cc, %a, %b ret %v @@ -66,9 +66,9 @@ define @vselect_nxv32i1( %a, %cc, %a, %b ret %v @@ -78,9 +78,9 @@ define @vselect_nxv64i1( %a, %cc, %a, %b ret %v diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll index 519c55862f7266548aa9e3b22851ff5743e3db55..0a13453c6f5906c44b9025640ba3f9ffb1c0d85d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll @@ -57,12 +57,12 @@ define @test2(i64 %avl, i8 zeroext %cond, @test3(i64 %avl, i8 zeroext %cond, @test4(i64 %avl, i8 zeroext %cond, @test5(i64 %avl, i8 zeroext %cond, @test6(i64 %avl, i8 zeroext %cond, @test8(i64 %avl, i8 zeroext %cond, @test9(i64 %avl, i8 zeroext %cond, @test_vsetvli_x0_x0(* %x, @llvm.riscv.vle.nxv2i32(* %x, i64 %vl) @@ -542,23 +542,23 @@ define @test_vsetvli_x0_x0_2(* %x, @llvm.riscv.vle.nxv2i32(* %x, i64 %vl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll index dd760f3e6abaae1b55faaab688f3573330d7969c..3c8e5d9c0d5b0f57b7b4a77412047d598abba839 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll @@ -10,8 +10,8 @@ define i32 @illegal_preserve_vl( %a, %x, @intrinsic_vsext_vf8_nxv1i64( %0, i32 ; CHECK-LABEL: intrinsic_vsext_vf8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf8 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf8 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv1i64.nxv1i8( @@ -51,8 +51,8 @@ define @intrinsic_vsext_vf8_nxv2i64( %0, i32 ; CHECK-LABEL: intrinsic_vsext_vf8_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf8 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf8 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv2i64.nxv2i8( @@ -93,8 +93,8 @@ define @intrinsic_vsext_vf8_nxv4i64( %0, i32 ; CHECK-LABEL: intrinsic_vsext_vf8_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf8 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv4i64.nxv4i8( @@ -177,8 +177,8 @@ define @intrinsic_vsext_vf4_nxv1i64( %0, i3 ; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv1i64.nxv1i16( @@ -219,8 +219,8 @@ define @intrinsic_vsext_vf4_nxv2i64( %0, i3 ; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv2i64.nxv2i16( @@ -261,8 +261,8 @@ define @intrinsic_vsext_vf4_nxv4i64( %0, i3 ; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv4i64.nxv4i16( @@ -345,8 +345,8 @@ define @intrinsic_vsext_vf4_nxv1i32( %0, i32 ; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv1i32.nxv1i8( @@ -387,8 +387,8 @@ define @intrinsic_vsext_vf4_nxv2i32( %0, i32 ; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv2i32.nxv2i8( @@ -429,8 +429,8 @@ define @intrinsic_vsext_vf4_nxv4i32( %0, i32 ; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv4i32.nxv4i8( @@ -471,8 +471,8 @@ define @intrinsic_vsext_vf4_nxv8i32( %0, i32 ; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv8i32.nxv8i8( @@ -555,8 +555,8 @@ define @intrinsic_vsext_vf2_nxv1i32( %0, i3 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv1i32.nxv1i16( @@ -597,8 +597,8 @@ define @intrinsic_vsext_vf2_nxv2i32( %0, i3 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv2i32.nxv2i16( @@ -639,8 +639,8 @@ define @intrinsic_vsext_vf2_nxv4i32( %0, i3 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv4i32.nxv4i16( @@ -681,8 +681,8 @@ define @intrinsic_vsext_vf2_nxv8i32( %0, i3 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv8i32.nxv8i16( @@ -765,8 +765,8 @@ define @intrinsic_vsext_vf2_nxv1i16( %0, i32 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv1i16.nxv1i8( @@ -807,8 +807,8 @@ define @intrinsic_vsext_vf2_nxv2i16( %0, i32 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv2i16.nxv2i8( @@ -849,8 +849,8 @@ define @intrinsic_vsext_vf2_nxv4i16( %0, i32 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv4i16.nxv4i8( @@ -891,8 +891,8 @@ define @intrinsic_vsext_vf2_nxv8i16( %0, i32 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv8i16.nxv8i8( @@ -933,8 +933,8 @@ define @intrinsic_vsext_vf2_nxv16i16( %0, ; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv16i16.nxv16i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll index 61037177d3da853ad59affa9c78ea8489690be84..209c9c70f3b2427589f6cb54a8294f9e6bec776c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vsext_vf8_nxv1i64( %0, i64 ; CHECK-LABEL: intrinsic_vsext_vf8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf8 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf8 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv1i64.nxv1i8( @@ -51,8 +51,8 @@ define @intrinsic_vsext_vf8_nxv2i64( %0, i64 ; CHECK-LABEL: intrinsic_vsext_vf8_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf8 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf8 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv2i64.nxv2i8( @@ -93,8 +93,8 @@ define @intrinsic_vsext_vf8_nxv4i64( %0, i64 ; CHECK-LABEL: intrinsic_vsext_vf8_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf8 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf8 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv4i64.nxv4i8( @@ -177,8 +177,8 @@ define @intrinsic_vsext_vf4_nxv1i64( %0, i6 ; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv1i64.nxv1i16( @@ -219,8 +219,8 @@ define @intrinsic_vsext_vf4_nxv2i64( %0, i6 ; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv2i64.nxv2i16( @@ -261,8 +261,8 @@ define @intrinsic_vsext_vf4_nxv4i64( %0, i6 ; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv4i64.nxv4i16( @@ -345,8 +345,8 @@ define @intrinsic_vsext_vf4_nxv1i32( %0, i64 ; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv1i32.nxv1i8( @@ -387,8 +387,8 @@ define @intrinsic_vsext_vf4_nxv2i32( %0, i64 ; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv2i32.nxv2i8( @@ -429,8 +429,8 @@ define @intrinsic_vsext_vf4_nxv4i32( %0, i64 ; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv4i32.nxv4i8( @@ -471,8 +471,8 @@ define @intrinsic_vsext_vf4_nxv8i32( %0, i64 ; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vsext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv8i32.nxv8i8( @@ -555,8 +555,8 @@ define @intrinsic_vsext_vf2_nxv1i64( %0, i6 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv1i64.nxv1i32( @@ -597,8 +597,8 @@ define @intrinsic_vsext_vf2_nxv2i64( %0, i6 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv2i64.nxv2i32( @@ -639,8 +639,8 @@ define @intrinsic_vsext_vf2_nxv4i64( %0, i6 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv4i64.nxv4i32( @@ -723,8 +723,8 @@ define @intrinsic_vsext_vf2_nxv1i32( %0, i6 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv1i32.nxv1i16( @@ -765,8 +765,8 @@ define @intrinsic_vsext_vf2_nxv2i32( %0, i6 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv2i32.nxv2i16( @@ -807,8 +807,8 @@ define @intrinsic_vsext_vf2_nxv4i32( %0, i6 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv4i32.nxv4i16( @@ -849,8 +849,8 @@ define @intrinsic_vsext_vf2_nxv8i32( %0, i6 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv8i32.nxv8i16( @@ -933,8 +933,8 @@ define @intrinsic_vsext_vf2_nxv1i16( %0, i64 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv1i16.nxv1i8( @@ -975,8 +975,8 @@ define @intrinsic_vsext_vf2_nxv2i16( %0, i64 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv2i16.nxv2i8( @@ -1017,8 +1017,8 @@ define @intrinsic_vsext_vf2_nxv4i16( %0, i64 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vsext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vsext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv4i16.nxv4i8( @@ -1059,8 +1059,8 @@ define @intrinsic_vsext_vf2_nxv8i16( %0, i64 ; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vsext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv8i16.nxv8i8( @@ -1101,8 +1101,8 @@ define @intrinsic_vsext_vf2_nxv16i16( %0, ; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vsext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vsext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsext.nxv16i16.nxv16i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll index aaf7db3a34adc3a1ba65d89c9da5d649bc1de7a0..8dabc1395187d89f457b24fade2309234462f5e1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll @@ -10,11 +10,11 @@ define @vsll_vx_nxv8i7( %a, i7 signext %b, undef, i7 %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll index 4b45bc6750ab7e00a3c75053925101fd2e66e80d..9674d9d711c9a6ca06095f619c851382e0128f0a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll @@ -821,8 +821,8 @@ define @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64( @llvm.riscv.vslide1down.nxv1i64.i64( @@ -846,10 +846,10 @@ define @intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64( @llvm.riscv.vslide1down.mask.nxv1i64.i64( @@ -872,8 +872,8 @@ define @intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64( @llvm.riscv.vslide1down.nxv2i64.i64( @@ -897,10 +897,10 @@ define @intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64( @llvm.riscv.vslide1down.mask.nxv2i64.i64( @@ -923,8 +923,8 @@ define @intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64( @llvm.riscv.vslide1down.nxv4i64.i64( @@ -948,10 +948,10 @@ define @intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64( @llvm.riscv.vslide1down.mask.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll index b13605200d99909e94e728f3f0bce0eb4bcaf6c1..2e40e606fb1473dc11c14e31c40c285fb197c9ec 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll @@ -10,8 +10,8 @@ define @intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8( @llvm.riscv.vslide1up.nxv1i8.i8( @@ -56,8 +56,8 @@ define @intrinsic_vslide1up_vx_nxv2i8_nxv2i8_i8( @llvm.riscv.vslide1up.nxv2i8.i8( @@ -102,8 +102,8 @@ define @intrinsic_vslide1up_vx_nxv4i8_nxv4i8_i8( @llvm.riscv.vslide1up.nxv4i8.i8( @@ -148,8 +148,8 @@ define @intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8( @llvm.riscv.vslide1up.nxv8i8.i8( @@ -194,8 +194,8 @@ define @intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8( @llvm.riscv.vslide1up.nxv16i8.i8( @@ -240,8 +240,8 @@ define @intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8( @llvm.riscv.vslide1up.nxv32i8.i8( @@ -332,8 +332,8 @@ define @intrinsic_vslide1up_vx_nxv1i16_nxv1i16_i16( @llvm.riscv.vslide1up.nxv1i16.i16( @@ -378,8 +378,8 @@ define @intrinsic_vslide1up_vx_nxv2i16_nxv2i16_i16( @llvm.riscv.vslide1up.nxv2i16.i16( @@ -424,8 +424,8 @@ define @intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16( @llvm.riscv.vslide1up.nxv4i16.i16( @@ -470,8 +470,8 @@ define @intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16( @llvm.riscv.vslide1up.nxv8i16.i16( @@ -516,8 +516,8 @@ define @intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16( @llvm.riscv.vslide1up.nxv16i16.i16( @@ -608,8 +608,8 @@ define @intrinsic_vslide1up_vx_nxv1i32_nxv1i32_i32( @llvm.riscv.vslide1up.nxv1i32.i32( @@ -654,8 +654,8 @@ define @intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32( @llvm.riscv.vslide1up.nxv2i32.i32( @@ -700,8 +700,8 @@ define @intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32( @llvm.riscv.vslide1up.nxv4i32.i32( @@ -746,8 +746,8 @@ define @intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32( @llvm.riscv.vslide1up.nxv8i32.i32( @@ -839,8 +839,8 @@ define @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64( @llvm.riscv.vslide1up.nxv1i64.i64( @@ -864,10 +864,10 @@ define @intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64( @llvm.riscv.vslide1up.mask.nxv1i64.i64( @@ -890,8 +890,8 @@ define @intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64( @llvm.riscv.vslide1up.nxv2i64.i64( @@ -915,10 +915,10 @@ define @intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64( @llvm.riscv.vslide1up.mask.nxv2i64.i64( @@ -941,8 +941,8 @@ define @intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64( @llvm.riscv.vslide1up.nxv4i64.i64( @@ -966,8 +966,8 @@ define @intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64( @intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8( @llvm.riscv.vslide1up.nxv1i8.i8( @@ -56,8 +56,8 @@ define @intrinsic_vslide1up_vx_nxv2i8_nxv2i8_i8( @llvm.riscv.vslide1up.nxv2i8.i8( @@ -102,8 +102,8 @@ define @intrinsic_vslide1up_vx_nxv4i8_nxv4i8_i8( @llvm.riscv.vslide1up.nxv4i8.i8( @@ -148,8 +148,8 @@ define @intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8( @llvm.riscv.vslide1up.nxv8i8.i8( @@ -194,8 +194,8 @@ define @intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8( @llvm.riscv.vslide1up.nxv16i8.i8( @@ -240,8 +240,8 @@ define @intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8( @llvm.riscv.vslide1up.nxv32i8.i8( @@ -332,8 +332,8 @@ define @intrinsic_vslide1up_vx_nxv1i16_nxv1i16_i16( @llvm.riscv.vslide1up.nxv1i16.i16( @@ -378,8 +378,8 @@ define @intrinsic_vslide1up_vx_nxv2i16_nxv2i16_i16( @llvm.riscv.vslide1up.nxv2i16.i16( @@ -424,8 +424,8 @@ define @intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16( @llvm.riscv.vslide1up.nxv4i16.i16( @@ -470,8 +470,8 @@ define @intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16( @llvm.riscv.vslide1up.nxv8i16.i16( @@ -516,8 +516,8 @@ define @intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16( @llvm.riscv.vslide1up.nxv16i16.i16( @@ -608,8 +608,8 @@ define @intrinsic_vslide1up_vx_nxv1i32_nxv1i32_i32( @llvm.riscv.vslide1up.nxv1i32.i32( @@ -654,8 +654,8 @@ define @intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32( @llvm.riscv.vslide1up.nxv2i32.i32( @@ -700,8 +700,8 @@ define @intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32( @llvm.riscv.vslide1up.nxv4i32.i32( @@ -746,8 +746,8 @@ define @intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32( @llvm.riscv.vslide1up.nxv8i32.i32( @@ -838,8 +838,8 @@ define @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64( @llvm.riscv.vslide1up.nxv1i64.i64( @@ -884,8 +884,8 @@ define @intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64( @llvm.riscv.vslide1up.nxv2i64.i64( @@ -930,8 +930,8 @@ define @intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64( @llvm.riscv.vslide1up.nxv4i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll index 51a15cd9b205943089c1c7993af03b0b3651b08d..2736ac8d2cc6e6b6aece91cc907492c72e0e43af 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll @@ -103,8 +103,8 @@ define void @test_vsetvli_i16( %0, %1, @llvm.riscv.vmseq.nxv1i16( @@ -124,8 +124,8 @@ define void @test_vsetvli_i32( %0, %1, @llvm.riscv.vmseq.nxv1i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll index a0fba4301bb4d06473847da467b960d6814a3f4f..2547cf3386f18dacb07403e31875b0c597bc5004 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll @@ -103,8 +103,8 @@ define void @test_vsetvli_i16( %0, %1, @llvm.riscv.vmseq.nxv1i16( @@ -124,8 +124,8 @@ define void @test_vsetvli_i32( %0, %1, @llvm.riscv.vmseq.nxv1i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll index 61eed5f8c6a3ea74b99b6f0b5b5bd246f5bfd783..caaecbba2bb86ef493802cafe6033d98c0094e5e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64( @intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64( @intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64( @intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64( %val, i16* %bas ; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16( %val, %val, i16* %base, %index, i32 %vl) @@ -23,10 +23,10 @@ define void @test_vsoxseg2_mask_nxv16i16_nxv16i16( %val, i16* ; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -40,10 +40,10 @@ define void @test_vsoxseg2_nxv16i16_nxv16i8( %val, i16* %base ; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i8( %val, %val, i16* %base, %index, i32 %vl) @@ -54,10 +54,10 @@ define void @test_vsoxseg2_mask_nxv16i16_nxv16i8( %val, i16* ; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i8( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -100,10 +100,10 @@ define void @test_vsoxseg2_nxv1i8_nxv1i8( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -114,10 +114,10 @@ define void @test_vsoxseg2_mask_nxv1i8_nxv1i8( %val, i8* %base, ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i8( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -131,10 +131,10 @@ define void @test_vsoxseg2_nxv1i8_nxv1i32( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -145,10 +145,10 @@ define void @test_vsoxseg2_mask_nxv1i8_nxv1i32( %val, i8* %base ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i32( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -162,10 +162,10 @@ define void @test_vsoxseg2_nxv1i8_nxv1i16( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -176,10 +176,10 @@ define void @test_vsoxseg2_mask_nxv1i8_nxv1i16( %val, i8* %base ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i16( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -870,10 +870,10 @@ define void @test_vsoxseg2_nxv16i8_nxv16i8( %val, i8* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv16i8.nxv16i8( %val, %val, i8* %base, %index, i32 %vl) @@ -884,10 +884,10 @@ define void @test_vsoxseg2_mask_nxv16i8_nxv16i8( %val, i8* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv16i8.nxv16i8( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -1122,10 +1122,10 @@ define void @test_vsoxseg2_nxv2i32_nxv2i32( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i32( %val, %val, i32* %base, %index, i32 %vl) @@ -1136,10 +1136,10 @@ define void @test_vsoxseg2_mask_nxv2i32_nxv2i32( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i32( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -1153,10 +1153,10 @@ define void @test_vsoxseg2_nxv2i32_nxv2i8( %val, i32* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i8( %val, %val, i32* %base, %index, i32 %vl) @@ -1167,10 +1167,10 @@ define void @test_vsoxseg2_mask_nxv2i32_nxv2i8( %val, i32* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i8( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -1184,10 +1184,10 @@ define void @test_vsoxseg2_nxv2i32_nxv2i16( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i16( %val, %val, i32* %base, %index, i32 %vl) @@ -1198,10 +1198,10 @@ define void @test_vsoxseg2_mask_nxv2i32_nxv2i16( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i16( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -1863,10 +1863,10 @@ define void @test_vsoxseg2_nxv4i16_nxv4i16( %val, i16* %base, ; CHECK-LABEL: test_vsoxseg2_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i16( %val, %val, i16* %base, %index, i32 %vl) @@ -1877,10 +1877,10 @@ define void @test_vsoxseg2_mask_nxv4i16_nxv4i16( %val, i16* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i16( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -1894,10 +1894,10 @@ define void @test_vsoxseg2_nxv4i16_nxv4i8( %val, i16* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i8( %val, %val, i16* %base, %index, i32 %vl) @@ -1908,10 +1908,10 @@ define void @test_vsoxseg2_mask_nxv4i16_nxv4i8( %val, i16* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i8( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -2602,10 +2602,10 @@ define void @test_vsoxseg2_nxv1i32_nxv1i8( %val, i32* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i8( %val, %val, i32* %base, %index, i32 %vl) @@ -2616,10 +2616,10 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i8( %val, i32* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i8( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -2633,10 +2633,10 @@ define void @test_vsoxseg2_nxv1i32_nxv1i32( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i32( %val, %val, i32* %base, %index, i32 %vl) @@ -2647,10 +2647,10 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i32( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i32( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -2664,10 +2664,10 @@ define void @test_vsoxseg2_nxv1i32_nxv1i16( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i16( %val, %val, i32* %base, %index, i32 %vl) @@ -2678,10 +2678,10 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i16( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i16( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -3343,10 +3343,10 @@ define void @test_vsoxseg2_nxv8i16_nxv8i16( %val, i16* %base, ; CHECK-LABEL: test_vsoxseg2_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i16( %val, %val, i16* %base, %index, i32 %vl) @@ -3357,10 +3357,10 @@ define void @test_vsoxseg2_mask_nxv8i16_nxv8i16( %val, i16* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i16( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -3374,10 +3374,10 @@ define void @test_vsoxseg2_nxv8i16_nxv8i8( %val, i16* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i8( %val, %val, i16* %base, %index, i32 %vl) @@ -3388,10 +3388,10 @@ define void @test_vsoxseg2_mask_nxv8i16_nxv8i8( %val, i16* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i8( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -3655,10 +3655,10 @@ define void @test_vsoxseg2_nxv8i8_nxv8i8( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -3669,10 +3669,10 @@ define void @test_vsoxseg2_mask_nxv8i8_nxv8i8( %val, i8* %base, ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8i8.nxv8i8( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -4363,10 +4363,10 @@ define void @test_vsoxseg2_nxv8i32_nxv8i16( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i16( %val, %val, i32* %base, %index, i32 %vl) @@ -4377,10 +4377,10 @@ define void @test_vsoxseg2_mask_nxv8i32_nxv8i16( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i16( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -4394,10 +4394,10 @@ define void @test_vsoxseg2_nxv8i32_nxv8i8( %val, i32* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i8( %val, %val, i32* %base, %index, i32 %vl) @@ -4408,10 +4408,10 @@ define void @test_vsoxseg2_mask_nxv8i32_nxv8i8( %val, i32* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i8( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -4425,10 +4425,10 @@ define void @test_vsoxseg2_nxv8i32_nxv8i32( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i32( %val, %val, i32* %base, %index, i32 %vl) @@ -4439,10 +4439,10 @@ define void @test_vsoxseg2_mask_nxv8i32_nxv8i32( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i32( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -4456,10 +4456,10 @@ define void @test_vsoxseg2_nxv4i8_nxv4i16( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -4470,10 +4470,10 @@ define void @test_vsoxseg2_mask_nxv4i8_nxv4i16( %val, i8* %base ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i16( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -4487,10 +4487,10 @@ define void @test_vsoxseg2_nxv4i8_nxv4i8( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -4501,10 +4501,10 @@ define void @test_vsoxseg2_mask_nxv4i8_nxv4i8( %val, i8* %base, ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i8( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -5195,10 +5195,10 @@ define void @test_vsoxseg2_nxv1i16_nxv1i8( %val, i16* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i8( %val, %val, i16* %base, %index, i32 %vl) @@ -5209,10 +5209,10 @@ define void @test_vsoxseg2_mask_nxv1i16_nxv1i8( %val, i16* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i8( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -5226,10 +5226,10 @@ define void @test_vsoxseg2_nxv1i16_nxv1i32( %val, i16* %base, ; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i32( %val, %val, i16* %base, %index, i32 %vl) @@ -5240,10 +5240,10 @@ define void @test_vsoxseg2_mask_nxv1i16_nxv1i32( %val, i16* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i32( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -5257,10 +5257,10 @@ define void @test_vsoxseg2_nxv1i16_nxv1i16( %val, i16* %base, ; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i16( %val, %val, i16* %base, %index, i32 %vl) @@ -5271,10 +5271,10 @@ define void @test_vsoxseg2_mask_nxv1i16_nxv1i16( %val, i16* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i16( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -5965,10 +5965,10 @@ define void @test_vsoxseg2_nxv32i8_nxv32i8( %val, i8* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v28 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv32i8.nxv32i8( %val, %val, i8* %base, %index, i32 %vl) @@ -5979,10 +5979,10 @@ define void @test_vsoxseg2_mask_nxv32i8_nxv32i8( %val, i8* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv32i8.nxv32i8( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -5996,10 +5996,10 @@ define void @test_vsoxseg2_nxv2i8_nxv2i32( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -6010,10 +6010,10 @@ define void @test_vsoxseg2_mask_nxv2i8_nxv2i32( %val, i8* %base ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i32( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -6027,10 +6027,10 @@ define void @test_vsoxseg2_nxv2i8_nxv2i8( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -6041,10 +6041,10 @@ define void @test_vsoxseg2_mask_nxv2i8_nxv2i8( %val, i8* %base, ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i8( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -6058,10 +6058,10 @@ define void @test_vsoxseg2_nxv2i8_nxv2i16( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -6072,10 +6072,10 @@ define void @test_vsoxseg2_mask_nxv2i8_nxv2i16( %val, i8* %base ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i16( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -6737,10 +6737,10 @@ define void @test_vsoxseg2_nxv2i16_nxv2i32( %val, i16* %base, ; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i32( %val, %val, i16* %base, %index, i32 %vl) @@ -6751,10 +6751,10 @@ define void @test_vsoxseg2_mask_nxv2i16_nxv2i32( %val, i16* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i32( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -6768,10 +6768,10 @@ define void @test_vsoxseg2_nxv2i16_nxv2i8( %val, i16* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i8( %val, %val, i16* %base, %index, i32 %vl) @@ -6782,10 +6782,10 @@ define void @test_vsoxseg2_mask_nxv2i16_nxv2i8( %val, i16* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i8( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -6799,10 +6799,10 @@ define void @test_vsoxseg2_nxv2i16_nxv2i16( %val, i16* %base, ; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i16( %val, %val, i16* %base, %index, i32 %vl) @@ -6813,10 +6813,10 @@ define void @test_vsoxseg2_mask_nxv2i16_nxv2i16( %val, i16* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i16( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -7478,10 +7478,10 @@ define void @test_vsoxseg2_nxv4i32_nxv4i16( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i16( %val, %val, i32* %base, %index, i32 %vl) @@ -7492,10 +7492,10 @@ define void @test_vsoxseg2_mask_nxv4i32_nxv4i16( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i16( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -7509,10 +7509,10 @@ define void @test_vsoxseg2_nxv4i32_nxv4i8( %val, i32* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i8( %val, %val, i32* %base, %index, i32 %vl) @@ -7523,10 +7523,10 @@ define void @test_vsoxseg2_mask_nxv4i32_nxv4i8( %val, i32* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i8( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -7540,10 +7540,10 @@ define void @test_vsoxseg2_nxv4i32_nxv4i32( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i32( %val, %val, i32* %base, %index, i32 %vl) @@ -7554,10 +7554,10 @@ define void @test_vsoxseg2_mask_nxv4i32_nxv4i32( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i32( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -7763,10 +7763,10 @@ define void @test_vsoxseg2_nxv16f16_nxv16i16( %val, half* %b ; CHECK-LABEL: test_vsoxseg2_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv16f16.nxv16i16( %val, %val, half* %base, %index, i32 %vl) @@ -7777,10 +7777,10 @@ define void @test_vsoxseg2_mask_nxv16f16_nxv16i16( %val, hal ; CHECK-LABEL: test_vsoxseg2_mask_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv16f16.nxv16i16( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -7794,10 +7794,10 @@ define void @test_vsoxseg2_nxv16f16_nxv16i8( %val, half* %ba ; CHECK-LABEL: test_vsoxseg2_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv16f16.nxv16i8( %val, %val, half* %base, %index, i32 %vl) @@ -7808,10 +7808,10 @@ define void @test_vsoxseg2_mask_nxv16f16_nxv16i8( %val, half ; CHECK-LABEL: test_vsoxseg2_mask_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv16f16.nxv16i8( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -7854,10 +7854,10 @@ define void @test_vsoxseg2_nxv4f64_nxv4i16( %val, double* % ; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i16( %val, %val, double* %base, %index, i32 %vl) @@ -7868,10 +7868,10 @@ define void @test_vsoxseg2_mask_nxv4f64_nxv4i16( %val, doub ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i16( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -7885,10 +7885,10 @@ define void @test_vsoxseg2_nxv4f64_nxv4i8( %val, double* %b ; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i8( %val, %val, double* %base, %index, i32 %vl) @@ -7899,10 +7899,10 @@ define void @test_vsoxseg2_mask_nxv4f64_nxv4i8( %val, doubl ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i8( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -7916,10 +7916,10 @@ define void @test_vsoxseg2_nxv4f64_nxv4i32( %val, double* % ; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i32( %val, %val, double* %base, %index, i32 %vl) @@ -7930,10 +7930,10 @@ define void @test_vsoxseg2_mask_nxv4f64_nxv4i32( %val, doub ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i32( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -7947,10 +7947,10 @@ define void @test_vsoxseg2_nxv1f64_nxv1i8( %val, double* %b ; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i8( %val, %val, double* %base, %index, i32 %vl) @@ -7961,10 +7961,10 @@ define void @test_vsoxseg2_mask_nxv1f64_nxv1i8( %val, doubl ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i8( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -7978,10 +7978,10 @@ define void @test_vsoxseg2_nxv1f64_nxv1i32( %val, double* % ; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i32( %val, %val, double* %base, %index, i32 %vl) @@ -7992,10 +7992,10 @@ define void @test_vsoxseg2_mask_nxv1f64_nxv1i32( %val, doub ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i32( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -8009,10 +8009,10 @@ define void @test_vsoxseg2_nxv1f64_nxv1i16( %val, double* % ; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i16( %val, %val, double* %base, %index, i32 %vl) @@ -8023,10 +8023,10 @@ define void @test_vsoxseg2_mask_nxv1f64_nxv1i16( %val, doub ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i16( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -8688,10 +8688,10 @@ define void @test_vsoxseg2_nxv2f32_nxv2i32( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i32( %val, %val, float* %base, %index, i32 %vl) @@ -8702,10 +8702,10 @@ define void @test_vsoxseg2_mask_nxv2f32_nxv2i32( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i32( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -8719,10 +8719,10 @@ define void @test_vsoxseg2_nxv2f32_nxv2i8( %val, float* %bas ; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i8( %val, %val, float* %base, %index, i32 %vl) @@ -8733,10 +8733,10 @@ define void @test_vsoxseg2_mask_nxv2f32_nxv2i8( %val, float* ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i8( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -8750,10 +8750,10 @@ define void @test_vsoxseg2_nxv2f32_nxv2i16( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i16( %val, %val, float* %base, %index, i32 %vl) @@ -8764,10 +8764,10 @@ define void @test_vsoxseg2_mask_nxv2f32_nxv2i16( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i16( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -9429,10 +9429,10 @@ define void @test_vsoxseg2_nxv1f16_nxv1i8( %val, half* %base, ; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i8( %val, %val, half* %base, %index, i32 %vl) @@ -9443,10 +9443,10 @@ define void @test_vsoxseg2_mask_nxv1f16_nxv1i8( %val, half* % ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i8( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -9460,10 +9460,10 @@ define void @test_vsoxseg2_nxv1f16_nxv1i32( %val, half* %base ; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i32( %val, %val, half* %base, %index, i32 %vl) @@ -9474,10 +9474,10 @@ define void @test_vsoxseg2_mask_nxv1f16_nxv1i32( %val, half* ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i32( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -9491,10 +9491,10 @@ define void @test_vsoxseg2_nxv1f16_nxv1i16( %val, half* %base ; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i16( %val, %val, half* %base, %index, i32 %vl) @@ -9505,10 +9505,10 @@ define void @test_vsoxseg2_mask_nxv1f16_nxv1i16( %val, half* ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i16( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -10170,10 +10170,10 @@ define void @test_vsoxseg2_nxv1f32_nxv1i8( %val, float* %bas ; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i8( %val, %val, float* %base, %index, i32 %vl) @@ -10184,10 +10184,10 @@ define void @test_vsoxseg2_mask_nxv1f32_nxv1i8( %val, float* ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i8( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -10201,10 +10201,10 @@ define void @test_vsoxseg2_nxv1f32_nxv1i32( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i32( %val, %val, float* %base, %index, i32 %vl) @@ -10215,10 +10215,10 @@ define void @test_vsoxseg2_mask_nxv1f32_nxv1i32( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i32( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -10232,10 +10232,10 @@ define void @test_vsoxseg2_nxv1f32_nxv1i16( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i16( %val, %val, float* %base, %index, i32 %vl) @@ -10246,10 +10246,10 @@ define void @test_vsoxseg2_mask_nxv1f32_nxv1i16( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i16( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -10911,10 +10911,10 @@ define void @test_vsoxseg2_nxv8f16_nxv8i16( %val, half* %base ; CHECK-LABEL: test_vsoxseg2_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i16( %val, %val, half* %base, %index, i32 %vl) @@ -10925,10 +10925,10 @@ define void @test_vsoxseg2_mask_nxv8f16_nxv8i16( %val, half* ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i16( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -10942,10 +10942,10 @@ define void @test_vsoxseg2_nxv8f16_nxv8i8( %val, half* %base, ; CHECK-LABEL: test_vsoxseg2_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i8( %val, %val, half* %base, %index, i32 %vl) @@ -10956,10 +10956,10 @@ define void @test_vsoxseg2_mask_nxv8f16_nxv8i8( %val, half* % ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i8( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -11194,10 +11194,10 @@ define void @test_vsoxseg2_nxv8f32_nxv8i16( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i16( %val, %val, float* %base, %index, i32 %vl) @@ -11208,10 +11208,10 @@ define void @test_vsoxseg2_mask_nxv8f32_nxv8i16( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i16( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -11225,10 +11225,10 @@ define void @test_vsoxseg2_nxv8f32_nxv8i8( %val, float* %bas ; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i8( %val, %val, float* %base, %index, i32 %vl) @@ -11239,10 +11239,10 @@ define void @test_vsoxseg2_mask_nxv8f32_nxv8i8( %val, float* ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i8( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -11256,10 +11256,10 @@ define void @test_vsoxseg2_nxv8f32_nxv8i32( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i32( %val, %val, float* %base, %index, i32 %vl) @@ -11270,10 +11270,10 @@ define void @test_vsoxseg2_mask_nxv8f32_nxv8i32( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i32( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -11287,10 +11287,10 @@ define void @test_vsoxseg2_nxv2f64_nxv2i32( %val, double* % ; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i32( %val, %val, double* %base, %index, i32 %vl) @@ -11301,10 +11301,10 @@ define void @test_vsoxseg2_mask_nxv2f64_nxv2i32( %val, doub ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i32( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -11318,10 +11318,10 @@ define void @test_vsoxseg2_nxv2f64_nxv2i8( %val, double* %b ; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i8( %val, %val, double* %base, %index, i32 %vl) @@ -11332,10 +11332,10 @@ define void @test_vsoxseg2_mask_nxv2f64_nxv2i8( %val, doubl ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i8( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -11349,10 +11349,10 @@ define void @test_vsoxseg2_nxv2f64_nxv2i16( %val, double* % ; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i16( %val, %val, double* %base, %index, i32 %vl) @@ -11363,10 +11363,10 @@ define void @test_vsoxseg2_mask_nxv2f64_nxv2i16( %val, doub ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i16( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -11572,10 +11572,10 @@ define void @test_vsoxseg2_nxv4f16_nxv4i16( %val, half* %base ; CHECK-LABEL: test_vsoxseg2_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i16( %val, %val, half* %base, %index, i32 %vl) @@ -11586,10 +11586,10 @@ define void @test_vsoxseg2_mask_nxv4f16_nxv4i16( %val, half* ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i16( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -11603,10 +11603,10 @@ define void @test_vsoxseg2_nxv4f16_nxv4i8( %val, half* %base, ; CHECK-LABEL: test_vsoxseg2_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i8( %val, %val, half* %base, %index, i32 %vl) @@ -11617,10 +11617,10 @@ define void @test_vsoxseg2_mask_nxv4f16_nxv4i8( %val, half* % ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i8( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -12311,10 +12311,10 @@ define void @test_vsoxseg2_nxv2f16_nxv2i32( %val, half* %base ; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i32( %val, %val, half* %base, %index, i32 %vl) @@ -12325,10 +12325,10 @@ define void @test_vsoxseg2_mask_nxv2f16_nxv2i32( %val, half* ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i32( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -12342,10 +12342,10 @@ define void @test_vsoxseg2_nxv2f16_nxv2i8( %val, half* %base, ; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i8( %val, %val, half* %base, %index, i32 %vl) @@ -12356,10 +12356,10 @@ define void @test_vsoxseg2_mask_nxv2f16_nxv2i8( %val, half* % ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i8( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -12373,10 +12373,10 @@ define void @test_vsoxseg2_nxv2f16_nxv2i16( %val, half* %base ; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i16( %val, %val, half* %base, %index, i32 %vl) @@ -12387,10 +12387,10 @@ define void @test_vsoxseg2_mask_nxv2f16_nxv2i16( %val, half* ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i16( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -13052,10 +13052,10 @@ define void @test_vsoxseg2_nxv4f32_nxv4i16( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i16( %val, %val, float* %base, %index, i32 %vl) @@ -13066,10 +13066,10 @@ define void @test_vsoxseg2_mask_nxv4f32_nxv4i16( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i16( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -13083,10 +13083,10 @@ define void @test_vsoxseg2_nxv4f32_nxv4i8( %val, float* %bas ; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i8( %val, %val, float* %base, %index, i32 %vl) @@ -13097,10 +13097,10 @@ define void @test_vsoxseg2_mask_nxv4f32_nxv4i8( %val, float* ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i8( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -13114,10 +13114,10 @@ define void @test_vsoxseg2_nxv4f32_nxv4i32( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i32( %val, %val, float* %base, %index, i32 %vl) @@ -13128,10 +13128,10 @@ define void @test_vsoxseg2_mask_nxv4f32_nxv4i32( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i32( %val, %val, float* %base, %index, %mask, i32 %vl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll index b1a94bfe1920ae746f0ad9db60aca245c66963ca..d499471d570231eb14e4a508784708ebb7678196 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll @@ -9,10 +9,10 @@ define void @test_vsoxseg2_nxv16i16_nxv16i16( %val, i16* %bas ; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16( %val, %val, i16* %base, %index, i64 %vl) @@ -23,10 +23,10 @@ define void @test_vsoxseg2_mask_nxv16i16_nxv16i16( %val, i16* ; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -40,10 +40,10 @@ define void @test_vsoxseg2_nxv16i16_nxv16i8( %val, i16* %base ; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i8( %val, %val, i16* %base, %index, i64 %vl) @@ -54,10 +54,10 @@ define void @test_vsoxseg2_mask_nxv16i16_nxv16i8( %val, i16* ; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i8( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -100,10 +100,10 @@ define void @test_vsoxseg2_nxv4i32_nxv4i32( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i32( %val, %val, i32* %base, %index, i64 %vl) @@ -114,10 +114,10 @@ define void @test_vsoxseg2_mask_nxv4i32_nxv4i32( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i32( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -131,10 +131,10 @@ define void @test_vsoxseg2_nxv4i32_nxv4i8( %val, i32* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i8( %val, %val, i32* %base, %index, i64 %vl) @@ -145,10 +145,10 @@ define void @test_vsoxseg2_mask_nxv4i32_nxv4i8( %val, i32* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i8( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -191,10 +191,10 @@ define void @test_vsoxseg2_nxv4i32_nxv4i16( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4i32.nxv4i16( %val, %val, i32* %base, %index, i64 %vl) @@ -205,10 +205,10 @@ define void @test_vsoxseg2_mask_nxv4i32_nxv4i16( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i32.nxv4i16( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -507,10 +507,10 @@ define void @test_vsoxseg2_nxv16i8_nxv16i8( %val, i8* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv16i8.nxv16i8( %val, %val, i8* %base, %index, i64 %vl) @@ -521,10 +521,10 @@ define void @test_vsoxseg2_mask_nxv16i8_nxv16i8( %val, i8* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv16i8.nxv16i8( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -759,10 +759,10 @@ define void @test_vsoxseg2_nxv1i64_nxv1i64( %val, i64* %base, ; CHECK-LABEL: test_vsoxseg2_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i64( %val, %val, i64* %base, %index, i64 %vl) @@ -773,10 +773,10 @@ define void @test_vsoxseg2_mask_nxv1i64_nxv1i64( %val, i64* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i64( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -790,10 +790,10 @@ define void @test_vsoxseg2_nxv1i64_nxv1i32( %val, i64* %base, ; CHECK-LABEL: test_vsoxseg2_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i32( %val, %val, i64* %base, %index, i64 %vl) @@ -804,10 +804,10 @@ define void @test_vsoxseg2_mask_nxv1i64_nxv1i32( %val, i64* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i32( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -821,10 +821,10 @@ define void @test_vsoxseg2_nxv1i64_nxv1i16( %val, i64* %base, ; CHECK-LABEL: test_vsoxseg2_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i16( %val, %val, i64* %base, %index, i64 %vl) @@ -835,10 +835,10 @@ define void @test_vsoxseg2_mask_nxv1i64_nxv1i16( %val, i64* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i16( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -852,10 +852,10 @@ define void @test_vsoxseg2_nxv1i64_nxv1i8( %val, i64* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i64.nxv1i8( %val, %val, i64* %base, %index, i64 %vl) @@ -866,10 +866,10 @@ define void @test_vsoxseg2_mask_nxv1i64_nxv1i8( %val, i64* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i64.nxv1i8( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -1747,10 +1747,10 @@ define void @test_vsoxseg2_nxv1i32_nxv1i64( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i64( %val, %val, i32* %base, %index, i64 %vl) @@ -1761,10 +1761,10 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i64( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i64( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -1778,10 +1778,10 @@ define void @test_vsoxseg2_nxv1i32_nxv1i32( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i32( %val, %val, i32* %base, %index, i64 %vl) @@ -1792,10 +1792,10 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i32( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i32( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -1809,10 +1809,10 @@ define void @test_vsoxseg2_nxv1i32_nxv1i16( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i16( %val, %val, i32* %base, %index, i64 %vl) @@ -1823,10 +1823,10 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i16( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i16( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -1840,10 +1840,10 @@ define void @test_vsoxseg2_nxv1i32_nxv1i8( %val, i32* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i32.nxv1i8( %val, %val, i32* %base, %index, i64 %vl) @@ -1854,10 +1854,10 @@ define void @test_vsoxseg2_mask_nxv1i32_nxv1i8( %val, i32* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i32.nxv1i8( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -2735,10 +2735,10 @@ define void @test_vsoxseg2_nxv8i16_nxv8i16( %val, i16* %base, ; CHECK-LABEL: test_vsoxseg2_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i16( %val, %val, i16* %base, %index, i64 %vl) @@ -2749,10 +2749,10 @@ define void @test_vsoxseg2_mask_nxv8i16_nxv8i16( %val, i16* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i16( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -2766,10 +2766,10 @@ define void @test_vsoxseg2_nxv8i16_nxv8i8( %val, i16* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8i16.nxv8i8( %val, %val, i16* %base, %index, i64 %vl) @@ -2780,10 +2780,10 @@ define void @test_vsoxseg2_mask_nxv8i16_nxv8i8( %val, i16* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8i16.nxv8i8( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -3140,10 +3140,10 @@ define void @test_vsoxseg2_nxv4i8_nxv4i8( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -3154,10 +3154,10 @@ define void @test_vsoxseg2_mask_nxv4i8_nxv4i8( %val, i8* %base, ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i8( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -3200,10 +3200,10 @@ define void @test_vsoxseg2_nxv4i8_nxv4i16( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -3214,10 +3214,10 @@ define void @test_vsoxseg2_mask_nxv4i8_nxv4i16( %val, i8* %base ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i8.nxv4i16( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -4095,10 +4095,10 @@ define void @test_vsoxseg2_nxv1i16_nxv1i64( %val, i16* %base, ; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i64( %val, %val, i16* %base, %index, i64 %vl) @@ -4109,10 +4109,10 @@ define void @test_vsoxseg2_mask_nxv1i16_nxv1i64( %val, i16* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i64( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -4126,10 +4126,10 @@ define void @test_vsoxseg2_nxv1i16_nxv1i32( %val, i16* %base, ; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i32( %val, %val, i16* %base, %index, i64 %vl) @@ -4140,10 +4140,10 @@ define void @test_vsoxseg2_mask_nxv1i16_nxv1i32( %val, i16* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i32( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -4157,10 +4157,10 @@ define void @test_vsoxseg2_nxv1i16_nxv1i16( %val, i16* %base, ; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i16( %val, %val, i16* %base, %index, i64 %vl) @@ -4171,10 +4171,10 @@ define void @test_vsoxseg2_mask_nxv1i16_nxv1i16( %val, i16* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i16( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -4188,10 +4188,10 @@ define void @test_vsoxseg2_nxv1i16_nxv1i8( %val, i16* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1i16.nxv1i8( %val, %val, i16* %base, %index, i64 %vl) @@ -4202,10 +4202,10 @@ define void @test_vsoxseg2_mask_nxv1i16_nxv1i8( %val, i16* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i16.nxv1i8( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -5083,10 +5083,10 @@ define void @test_vsoxseg2_nxv2i32_nxv2i32( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i32( %val, %val, i32* %base, %index, i64 %vl) @@ -5097,10 +5097,10 @@ define void @test_vsoxseg2_mask_nxv2i32_nxv2i32( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i32( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -5114,10 +5114,10 @@ define void @test_vsoxseg2_nxv2i32_nxv2i8( %val, i32* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i8( %val, %val, i32* %base, %index, i64 %vl) @@ -5128,10 +5128,10 @@ define void @test_vsoxseg2_mask_nxv2i32_nxv2i8( %val, i32* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i8( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -5145,10 +5145,10 @@ define void @test_vsoxseg2_nxv2i32_nxv2i16( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i16( %val, %val, i32* %base, %index, i64 %vl) @@ -5159,10 +5159,10 @@ define void @test_vsoxseg2_mask_nxv2i32_nxv2i16( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i32.nxv2i16( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -6098,10 +6098,10 @@ define void @test_vsoxseg2_nxv8i8_nxv8i8( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -6112,10 +6112,10 @@ define void @test_vsoxseg2_mask_nxv8i8_nxv8i8( %val, i8* %base, ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8i8.nxv8i8( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -7051,10 +7051,10 @@ define void @test_vsoxseg2_nxv4i64_nxv4i32( %val, i64* %base, ; CHECK-LABEL: test_vsoxseg2_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i32( %val, %val, i64* %base, %index, i64 %vl) @@ -7065,10 +7065,10 @@ define void @test_vsoxseg2_mask_nxv4i64_nxv4i32( %val, i64* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i32( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -7082,10 +7082,10 @@ define void @test_vsoxseg2_nxv4i64_nxv4i8( %val, i64* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i8( %val, %val, i64* %base, %index, i64 %vl) @@ -7096,10 +7096,10 @@ define void @test_vsoxseg2_mask_nxv4i64_nxv4i8( %val, i64* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i8( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -7113,10 +7113,10 @@ define void @test_vsoxseg2_nxv4i64_nxv4i64( %val, i64* %base, ; CHECK-LABEL: test_vsoxseg2_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v28 +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i64( %val, %val, i64* %base, %index, i64 %vl) @@ -7127,10 +7127,10 @@ define void @test_vsoxseg2_mask_nxv4i64_nxv4i64( %val, i64* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i64( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -7144,10 +7144,10 @@ define void @test_vsoxseg2_nxv4i64_nxv4i16( %val, i64* %base, ; CHECK-LABEL: test_vsoxseg2_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4i64.nxv4i16( %val, %val, i64* %base, %index, i64 %vl) @@ -7158,10 +7158,10 @@ define void @test_vsoxseg2_mask_nxv4i64_nxv4i16( %val, i64* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i64.nxv4i16( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -7204,10 +7204,10 @@ define void @test_vsoxseg2_nxv4i16_nxv4i8( %val, i16* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i8( %val, %val, i16* %base, %index, i64 %vl) @@ -7218,10 +7218,10 @@ define void @test_vsoxseg2_mask_nxv4i16_nxv4i8( %val, i16* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i8( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -7264,10 +7264,10 @@ define void @test_vsoxseg2_nxv4i16_nxv4i16( %val, i16* %base, ; CHECK-LABEL: test_vsoxseg2_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4i16.nxv4i16( %val, %val, i16* %base, %index, i64 %vl) @@ -7278,10 +7278,10 @@ define void @test_vsoxseg2_mask_nxv4i16_nxv4i16( %val, i16* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4i16.nxv4i16( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -8159,10 +8159,10 @@ define void @test_vsoxseg2_nxv1i8_nxv1i64( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -8173,10 +8173,10 @@ define void @test_vsoxseg2_mask_nxv1i8_nxv1i64( %val, i8* %base ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i64( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -8190,10 +8190,10 @@ define void @test_vsoxseg2_nxv1i8_nxv1i32( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -8204,10 +8204,10 @@ define void @test_vsoxseg2_mask_nxv1i8_nxv1i32( %val, i8* %base ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i32( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -8221,10 +8221,10 @@ define void @test_vsoxseg2_nxv1i8_nxv1i16( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -8235,10 +8235,10 @@ define void @test_vsoxseg2_mask_nxv1i8_nxv1i16( %val, i8* %base ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i16( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -8252,10 +8252,10 @@ define void @test_vsoxseg2_nxv1i8_nxv1i8( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -8266,10 +8266,10 @@ define void @test_vsoxseg2_mask_nxv1i8_nxv1i8( %val, i8* %base, ; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1i8.nxv1i8( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -9147,10 +9147,10 @@ define void @test_vsoxseg2_nxv2i8_nxv2i32( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -9161,10 +9161,10 @@ define void @test_vsoxseg2_mask_nxv2i8_nxv2i32( %val, i8* %base ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i32( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -9178,10 +9178,10 @@ define void @test_vsoxseg2_nxv2i8_nxv2i8( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -9192,10 +9192,10 @@ define void @test_vsoxseg2_mask_nxv2i8_nxv2i8( %val, i8* %base, ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i8( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -9209,10 +9209,10 @@ define void @test_vsoxseg2_nxv2i8_nxv2i16( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -9223,10 +9223,10 @@ define void @test_vsoxseg2_mask_nxv2i8_nxv2i16( %val, i8* %base ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i8.nxv2i16( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -10133,10 +10133,10 @@ define void @test_vsoxseg2_nxv8i32_nxv8i16( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i16( %val, %val, i32* %base, %index, i64 %vl) @@ -10147,10 +10147,10 @@ define void @test_vsoxseg2_mask_nxv8i32_nxv8i16( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i16( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -10164,10 +10164,10 @@ define void @test_vsoxseg2_nxv8i32_nxv8i8( %val, i32* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i8( %val, %val, i32* %base, %index, i64 %vl) @@ -10178,10 +10178,10 @@ define void @test_vsoxseg2_mask_nxv8i32_nxv8i8( %val, i32* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i8( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -10224,10 +10224,10 @@ define void @test_vsoxseg2_nxv8i32_nxv8i32( %val, i32* %base, ; CHECK-LABEL: test_vsoxseg2_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8i32.nxv8i32( %val, %val, i32* %base, %index, i64 %vl) @@ -10238,10 +10238,10 @@ define void @test_vsoxseg2_mask_nxv8i32_nxv8i32( %val, i32* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8i32.nxv8i32( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -10284,10 +10284,10 @@ define void @test_vsoxseg2_nxv32i8_nxv32i8( %val, i8* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v28 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv32i8.nxv32i8( %val, %val, i8* %base, %index, i64 %vl) @@ -10298,10 +10298,10 @@ define void @test_vsoxseg2_mask_nxv32i8_nxv32i8( %val, i8* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv32i8.nxv32i8( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -10315,10 +10315,10 @@ define void @test_vsoxseg2_nxv2i16_nxv2i32( %val, i16* %base, ; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i32( %val, %val, i16* %base, %index, i64 %vl) @@ -10329,10 +10329,10 @@ define void @test_vsoxseg2_mask_nxv2i16_nxv2i32( %val, i16* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i32( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -10346,10 +10346,10 @@ define void @test_vsoxseg2_nxv2i16_nxv2i8( %val, i16* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i8( %val, %val, i16* %base, %index, i64 %vl) @@ -10360,10 +10360,10 @@ define void @test_vsoxseg2_mask_nxv2i16_nxv2i8( %val, i16* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i8( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -10377,10 +10377,10 @@ define void @test_vsoxseg2_nxv2i16_nxv2i16( %val, i16* %base, ; CHECK-LABEL: test_vsoxseg2_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i16.nxv2i16( %val, %val, i16* %base, %index, i64 %vl) @@ -10391,10 +10391,10 @@ define void @test_vsoxseg2_mask_nxv2i16_nxv2i16( %val, i16* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i16.nxv2i16( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -11301,10 +11301,10 @@ define void @test_vsoxseg2_nxv2i64_nxv2i32( %val, i64* %base, ; CHECK-LABEL: test_vsoxseg2_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i32( %val, %val, i64* %base, %index, i64 %vl) @@ -11315,10 +11315,10 @@ define void @test_vsoxseg2_mask_nxv2i64_nxv2i32( %val, i64* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i32( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -11332,10 +11332,10 @@ define void @test_vsoxseg2_nxv2i64_nxv2i8( %val, i64* %base, < ; CHECK-LABEL: test_vsoxseg2_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i8( %val, %val, i64* %base, %index, i64 %vl) @@ -11346,10 +11346,10 @@ define void @test_vsoxseg2_mask_nxv2i64_nxv2i8( %val, i64* %ba ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i8( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -11363,10 +11363,10 @@ define void @test_vsoxseg2_nxv2i64_nxv2i16( %val, i64* %base, ; CHECK-LABEL: test_vsoxseg2_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i16( %val, %val, i64* %base, %index, i64 %vl) @@ -11377,10 +11377,10 @@ define void @test_vsoxseg2_mask_nxv2i64_nxv2i16( %val, i64* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i16( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -11394,10 +11394,10 @@ define void @test_vsoxseg2_nxv2i64_nxv2i64( %val, i64* %base, ; CHECK-LABEL: test_vsoxseg2_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2i64.nxv2i64( %val, %val, i64* %base, %index, i64 %vl) @@ -11408,10 +11408,10 @@ define void @test_vsoxseg2_mask_nxv2i64_nxv2i64( %val, i64* %b ; CHECK-LABEL: test_vsoxseg2_mask_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2i64.nxv2i64( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -11681,10 +11681,10 @@ define void @test_vsoxseg2_nxv16f16_nxv16i16( %val, half* %b ; CHECK-LABEL: test_vsoxseg2_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv16f16.nxv16i16( %val, %val, half* %base, %index, i64 %vl) @@ -11695,10 +11695,10 @@ define void @test_vsoxseg2_mask_nxv16f16_nxv16i16( %val, hal ; CHECK-LABEL: test_vsoxseg2_mask_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv16f16.nxv16i16( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -11712,10 +11712,10 @@ define void @test_vsoxseg2_nxv16f16_nxv16i8( %val, half* %ba ; CHECK-LABEL: test_vsoxseg2_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv16f16.nxv16i8( %val, %val, half* %base, %index, i64 %vl) @@ -11726,10 +11726,10 @@ define void @test_vsoxseg2_mask_nxv16f16_nxv16i8( %val, half ; CHECK-LABEL: test_vsoxseg2_mask_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv16f16.nxv16i8( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -11772,10 +11772,10 @@ define void @test_vsoxseg2_nxv4f64_nxv4i32( %val, double* % ; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i32( %val, %val, double* %base, %index, i64 %vl) @@ -11786,10 +11786,10 @@ define void @test_vsoxseg2_mask_nxv4f64_nxv4i32( %val, doub ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i32( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -11803,10 +11803,10 @@ define void @test_vsoxseg2_nxv4f64_nxv4i8( %val, double* %b ; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i8( %val, %val, double* %base, %index, i64 %vl) @@ -11817,10 +11817,10 @@ define void @test_vsoxseg2_mask_nxv4f64_nxv4i8( %val, doubl ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i8( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -11834,10 +11834,10 @@ define void @test_vsoxseg2_nxv4f64_nxv4i64( %val, double* % ; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v28 +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i64( %val, %val, double* %base, %index, i64 %vl) @@ -11848,10 +11848,10 @@ define void @test_vsoxseg2_mask_nxv4f64_nxv4i64( %val, doub ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i64( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -11865,10 +11865,10 @@ define void @test_vsoxseg2_nxv4f64_nxv4i16( %val, double* % ; CHECK-LABEL: test_vsoxseg2_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f64.nxv4i16( %val, %val, double* %base, %index, i64 %vl) @@ -11879,10 +11879,10 @@ define void @test_vsoxseg2_mask_nxv4f64_nxv4i16( %val, doub ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f64.nxv4i16( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -11896,10 +11896,10 @@ define void @test_vsoxseg2_nxv1f64_nxv1i64( %val, double* % ; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i64( %val, %val, double* %base, %index, i64 %vl) @@ -11910,10 +11910,10 @@ define void @test_vsoxseg2_mask_nxv1f64_nxv1i64( %val, doub ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i64( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -11927,10 +11927,10 @@ define void @test_vsoxseg2_nxv1f64_nxv1i32( %val, double* % ; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i32( %val, %val, double* %base, %index, i64 %vl) @@ -11941,10 +11941,10 @@ define void @test_vsoxseg2_mask_nxv1f64_nxv1i32( %val, doub ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i32( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -11958,10 +11958,10 @@ define void @test_vsoxseg2_nxv1f64_nxv1i16( %val, double* % ; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i16( %val, %val, double* %base, %index, i64 %vl) @@ -11972,10 +11972,10 @@ define void @test_vsoxseg2_mask_nxv1f64_nxv1i16( %val, doub ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i16( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -11989,10 +11989,10 @@ define void @test_vsoxseg2_nxv1f64_nxv1i8( %val, double* %b ; CHECK-LABEL: test_vsoxseg2_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f64.nxv1i8( %val, %val, double* %base, %index, i64 %vl) @@ -12003,10 +12003,10 @@ define void @test_vsoxseg2_mask_nxv1f64_nxv1i8( %val, doubl ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f64.nxv1i8( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -12884,10 +12884,10 @@ define void @test_vsoxseg2_nxv2f32_nxv2i32( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i32( %val, %val, float* %base, %index, i64 %vl) @@ -12898,10 +12898,10 @@ define void @test_vsoxseg2_mask_nxv2f32_nxv2i32( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i32( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -12915,10 +12915,10 @@ define void @test_vsoxseg2_nxv2f32_nxv2i8( %val, float* %bas ; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i8( %val, %val, float* %base, %index, i64 %vl) @@ -12929,10 +12929,10 @@ define void @test_vsoxseg2_mask_nxv2f32_nxv2i8( %val, float* ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i8( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -12946,10 +12946,10 @@ define void @test_vsoxseg2_nxv2f32_nxv2i16( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f32.nxv2i16( %val, %val, float* %base, %index, i64 %vl) @@ -12960,10 +12960,10 @@ define void @test_vsoxseg2_mask_nxv2f32_nxv2i16( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f32.nxv2i16( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -13870,10 +13870,10 @@ define void @test_vsoxseg2_nxv1f16_nxv1i64( %val, half* %base ; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i64( %val, %val, half* %base, %index, i64 %vl) @@ -13884,10 +13884,10 @@ define void @test_vsoxseg2_mask_nxv1f16_nxv1i64( %val, half* ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i64( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -13901,10 +13901,10 @@ define void @test_vsoxseg2_nxv1f16_nxv1i32( %val, half* %base ; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i32( %val, %val, half* %base, %index, i64 %vl) @@ -13915,10 +13915,10 @@ define void @test_vsoxseg2_mask_nxv1f16_nxv1i32( %val, half* ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i32( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -13932,10 +13932,10 @@ define void @test_vsoxseg2_nxv1f16_nxv1i16( %val, half* %base ; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i16( %val, %val, half* %base, %index, i64 %vl) @@ -13946,10 +13946,10 @@ define void @test_vsoxseg2_mask_nxv1f16_nxv1i16( %val, half* ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i16( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -13963,10 +13963,10 @@ define void @test_vsoxseg2_nxv1f16_nxv1i8( %val, half* %base, ; CHECK-LABEL: test_vsoxseg2_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f16.nxv1i8( %val, %val, half* %base, %index, i64 %vl) @@ -13977,10 +13977,10 @@ define void @test_vsoxseg2_mask_nxv1f16_nxv1i8( %val, half* % ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f16.nxv1i8( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -14858,10 +14858,10 @@ define void @test_vsoxseg2_nxv1f32_nxv1i64( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i64( %val, %val, float* %base, %index, i64 %vl) @@ -14872,10 +14872,10 @@ define void @test_vsoxseg2_mask_nxv1f32_nxv1i64( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i64( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -14889,10 +14889,10 @@ define void @test_vsoxseg2_nxv1f32_nxv1i32( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i32( %val, %val, float* %base, %index, i64 %vl) @@ -14903,10 +14903,10 @@ define void @test_vsoxseg2_mask_nxv1f32_nxv1i32( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i32( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -14920,10 +14920,10 @@ define void @test_vsoxseg2_nxv1f32_nxv1i16( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i16( %val, %val, float* %base, %index, i64 %vl) @@ -14934,10 +14934,10 @@ define void @test_vsoxseg2_mask_nxv1f32_nxv1i16( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i16( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -14951,10 +14951,10 @@ define void @test_vsoxseg2_nxv1f32_nxv1i8( %val, float* %bas ; CHECK-LABEL: test_vsoxseg2_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv1f32.nxv1i8( %val, %val, float* %base, %index, i64 %vl) @@ -14965,10 +14965,10 @@ define void @test_vsoxseg2_mask_nxv1f32_nxv1i8( %val, float* ; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv1f32.nxv1i8( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -15846,10 +15846,10 @@ define void @test_vsoxseg2_nxv8f16_nxv8i16( %val, half* %base ; CHECK-LABEL: test_vsoxseg2_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i16( %val, %val, half* %base, %index, i64 %vl) @@ -15860,10 +15860,10 @@ define void @test_vsoxseg2_mask_nxv8f16_nxv8i16( %val, half* ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i16( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -15877,10 +15877,10 @@ define void @test_vsoxseg2_nxv8f16_nxv8i8( %val, half* %base, ; CHECK-LABEL: test_vsoxseg2_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8f16.nxv8i8( %val, %val, half* %base, %index, i64 %vl) @@ -15891,10 +15891,10 @@ define void @test_vsoxseg2_mask_nxv8f16_nxv8i8( %val, half* % ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8f16.nxv8i8( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -16222,10 +16222,10 @@ define void @test_vsoxseg2_nxv8f32_nxv8i16( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i16( %val, %val, float* %base, %index, i64 %vl) @@ -16236,10 +16236,10 @@ define void @test_vsoxseg2_mask_nxv8f32_nxv8i16( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i16( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -16253,10 +16253,10 @@ define void @test_vsoxseg2_nxv8f32_nxv8i8( %val, float* %bas ; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i8( %val, %val, float* %base, %index, i64 %vl) @@ -16267,10 +16267,10 @@ define void @test_vsoxseg2_mask_nxv8f32_nxv8i8( %val, float* ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i8( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -16313,10 +16313,10 @@ define void @test_vsoxseg2_nxv8f32_nxv8i32( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv8f32.nxv8i32( %val, %val, float* %base, %index, i64 %vl) @@ -16327,10 +16327,10 @@ define void @test_vsoxseg2_mask_nxv8f32_nxv8i32( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv8f32.nxv8i32( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -16344,10 +16344,10 @@ define void @test_vsoxseg2_nxv2f64_nxv2i32( %val, double* % ; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i32( %val, %val, double* %base, %index, i64 %vl) @@ -16358,10 +16358,10 @@ define void @test_vsoxseg2_mask_nxv2f64_nxv2i32( %val, doub ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i32( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -16375,10 +16375,10 @@ define void @test_vsoxseg2_nxv2f64_nxv2i8( %val, double* %b ; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i8( %val, %val, double* %base, %index, i64 %vl) @@ -16389,10 +16389,10 @@ define void @test_vsoxseg2_mask_nxv2f64_nxv2i8( %val, doubl ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i8( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -16406,10 +16406,10 @@ define void @test_vsoxseg2_nxv2f64_nxv2i16( %val, double* % ; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i16( %val, %val, double* %base, %index, i64 %vl) @@ -16420,10 +16420,10 @@ define void @test_vsoxseg2_mask_nxv2f64_nxv2i16( %val, doub ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i16( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -16437,10 +16437,10 @@ define void @test_vsoxseg2_nxv2f64_nxv2i64( %val, double* % ; CHECK-LABEL: test_vsoxseg2_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f64.nxv2i64( %val, %val, double* %base, %index, i64 %vl) @@ -16451,10 +16451,10 @@ define void @test_vsoxseg2_mask_nxv2f64_nxv2i64( %val, doub ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f64.nxv2i64( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -16753,10 +16753,10 @@ define void @test_vsoxseg2_nxv4f16_nxv4i8( %val, half* %base, ; CHECK-LABEL: test_vsoxseg2_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i8( %val, %val, half* %base, %index, i64 %vl) @@ -16767,10 +16767,10 @@ define void @test_vsoxseg2_mask_nxv4f16_nxv4i8( %val, half* % ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i8( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -16813,10 +16813,10 @@ define void @test_vsoxseg2_nxv4f16_nxv4i16( %val, half* %base ; CHECK-LABEL: test_vsoxseg2_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f16.nxv4i16( %val, %val, half* %base, %index, i64 %vl) @@ -16827,10 +16827,10 @@ define void @test_vsoxseg2_mask_nxv4f16_nxv4i16( %val, half* ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f16.nxv4i16( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -17708,10 +17708,10 @@ define void @test_vsoxseg2_nxv2f16_nxv2i32( %val, half* %base ; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i32( %val, %val, half* %base, %index, i64 %vl) @@ -17722,10 +17722,10 @@ define void @test_vsoxseg2_mask_nxv2f16_nxv2i32( %val, half* ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i32( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -17739,10 +17739,10 @@ define void @test_vsoxseg2_nxv2f16_nxv2i8( %val, half* %base, ; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i8( %val, %val, half* %base, %index, i64 %vl) @@ -17753,10 +17753,10 @@ define void @test_vsoxseg2_mask_nxv2f16_nxv2i8( %val, half* % ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i8( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -17770,10 +17770,10 @@ define void @test_vsoxseg2_nxv2f16_nxv2i16( %val, half* %base ; CHECK-LABEL: test_vsoxseg2_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv2f16.nxv2i16( %val, %val, half* %base, %index, i64 %vl) @@ -17784,10 +17784,10 @@ define void @test_vsoxseg2_mask_nxv2f16_nxv2i16( %val, half* ; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv2f16.nxv2i16( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -18694,10 +18694,10 @@ define void @test_vsoxseg2_nxv4f32_nxv4i32( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26 +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i32( %val, %val, float* %base, %index, i64 %vl) @@ -18708,10 +18708,10 @@ define void @test_vsoxseg2_mask_nxv4f32_nxv4i32( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsoxseg2ei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i32( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -18725,10 +18725,10 @@ define void @test_vsoxseg2_nxv4f32_nxv4i8( %val, float* %bas ; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i8( %val, %val, float* %base, %index, i64 %vl) @@ -18739,10 +18739,10 @@ define void @test_vsoxseg2_mask_nxv4f32_nxv4i8( %val, float* ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i8( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -18785,10 +18785,10 @@ define void @test_vsoxseg2_nxv4f32_nxv4i16( %val, float* %ba ; CHECK-LABEL: test_vsoxseg2_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv4f32.nxv4i16( %val, %val, float* %base, %index, i64 %vl) @@ -18799,10 +18799,10 @@ define void @test_vsoxseg2_mask_nxv4f32_nxv4i16( %val, float ; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv4f32.nxv4i16( %val, %val, float* %base, %index, %mask, i64 %vl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll index 974ea638750aa40419142f33fc1bc7255fa6d8f1..29073eb2c8fd5a1458fa3b32f9266559020fb69f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll @@ -29,8 +29,8 @@ define @vsplat_nxv1i1_2(i1 %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i1 %x, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -43,8 +43,8 @@ define @vsplat_nxv1i1_3(i32 signext %x, i32 signext %y) { ; CHECK-NEXT: xor a0, a0, a1 ; CHECK-NEXT: snez a0, a0 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %c = icmp ne i32 %x, %y %head = insertelement undef, i1 %c, i32 0 @@ -79,8 +79,8 @@ define @vsplat_nxv2i1_2(i1 %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i1 %x, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -114,8 +114,8 @@ define @vsplat_nxv4i1_2(i1 %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i1 %x, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -149,8 +149,8 @@ define @vsplat_nxv8i1_2(i1 %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu -; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vi v0, v25, 0 +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i1 %x, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -184,8 +184,8 @@ define @vsplat_nxv16i1_2(i1 %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu -; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsne.vi v0, v26, 0 +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i1 %x, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll index f86ba341ef4dfce68ec00c04114c019ebf6a3e6e..32a351f3a766efb2bd8cf8477a2c7dde4b6c1c9f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll @@ -10,13 +10,13 @@ define @vsra_vx_nxv8i7( %a, i7 signext %b, undef, i7 %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll index bb35b36132fda73d88bbf2eede77498325e8f763..24c6497a0a64470c39334e92729b7fe96db8094f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll @@ -11,11 +11,11 @@ define @vsrl_vx_nxv8i7( %a, i7 signext %b, undef, i7 %b, i32 0 %vb = shufflevector %elt.head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll index 73c9670d83cbe6129fe756dbdc4cc354255bf2af..d79d235d7dfdff9c40846e0dc3083ebc314e8bb6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vssub_vx_nxv1i64_nxv1i64_i64( @intrinsic_vssub_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vssub_vx_nxv2i64_nxv2i64_i64( @intrinsic_vssub_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vssub_vx_nxv4i64_nxv4i64_i64( @intrinsic_vssub_mask_vx_nxv4i64_nxv4i64_i64( @ssub_nxv1i64_vx( %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero -; RV32-NEXT: vssub.vv v8, v8, v25 +; RV32-NEXT: vlse64.v v9, (a0), zero +; RV32-NEXT: vssub.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -741,8 +741,8 @@ define @ssub_nxv2i64_vx( %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero -; RV32-NEXT: vssub.vv v8, v8, v26 +; RV32-NEXT: vlse64.v v10, (a0), zero +; RV32-NEXT: vssub.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -791,8 +791,8 @@ define @ssub_nxv4i64_vx( %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero -; RV32-NEXT: vssub.vv v8, v8, v28 +; RV32-NEXT: vlse64.v v12, (a0), zero +; RV32-NEXT: vssub.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll index 9ac0944f13a1f0b83865b0f1669a1ff334375ac6..d3eeb06981798a7628ed41a91b28af30a32f90b9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64( @intrinsic_vssubu_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vssubu_vx_nxv2i64_nxv2i64_i64( @intrinsic_vssubu_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vssubu_vx_nxv4i64_nxv4i64_i64( @intrinsic_vssubu_mask_vx_nxv4i64_nxv4i64_i64( @usub_nxv1i64_vx( %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero -; RV32-NEXT: vssubu.vv v8, v8, v25 +; RV32-NEXT: vlse64.v v9, (a0), zero +; RV32-NEXT: vssubu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -741,8 +741,8 @@ define @usub_nxv2i64_vx( %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero -; RV32-NEXT: vssubu.vv v8, v8, v26 +; RV32-NEXT: vlse64.v v10, (a0), zero +; RV32-NEXT: vssubu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -791,8 +791,8 @@ define @usub_nxv4i64_vx( %va, i64 %b) { ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero -; RV32-NEXT: vssubu.vv v8, v8, v28 +; RV32-NEXT: vlse64.v v12, (a0), zero +; RV32-NEXT: vssubu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll index b247135d34dbe6c26e47c92604be56fa162e7176..536d4223cf95c9db19b07971b4ad2c60e07a03de 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vsub_vx_nxv1i64_nxv1i64_i64( @intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vsub_vx_nxv2i64_nxv2i64_i64( @intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vsub_vx_nxv4i64_nxv4i64_i64( @intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64( @vsub_vx_nxv1i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vsub.vv v8, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -707,8 +707,8 @@ define @vsub_vx_nxv2i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vsub.vv v8, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -749,8 +749,8 @@ define @vsub_vx_nxv4i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vsub.vv v8, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll index 499d1ca4064be80d9b5b72eec89e8d5b28020a6f..d4818c7514049c78a1fe00460d13aad3acffa494 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll @@ -1001,9 +1001,9 @@ define @vsub_vx_nxv1i64( %va, i64 %b, @vsub_vx_nxv1i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vsub.vv v8, v8, v25 +; RV32-NEXT: vsub.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1079,9 +1079,9 @@ define @vsub_vx_nxv2i64( %va, i64 %b, @vsub_vx_nxv2i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vsub.vv v8, v8, v26 +; RV32-NEXT: vsub.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -1157,9 +1157,9 @@ define @vsub_vx_nxv4i64( %va, i64 %b, @vsub_vx_nxv4i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vsub.vv v8, v8, v28 +; RV32-NEXT: vsub.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll index ba9db863b0e31f309caf73ed250eb8bf424dae36..690ec3b4c466a961c46c79880ac28198b51bd45c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll @@ -9,10 +9,10 @@ define void @test_vsuxseg2_nxv16i16_nxv16i16( %val, i16* %bas ; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16( %val, %val, i16* %base, %index, i32 %vl) @@ -23,10 +23,10 @@ define void @test_vsuxseg2_mask_nxv16i16_nxv16i16( %val, i16* ; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -40,10 +40,10 @@ define void @test_vsuxseg2_nxv16i16_nxv16i8( %val, i16* %base ; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i8( %val, %val, i16* %base, %index, i32 %vl) @@ -54,10 +54,10 @@ define void @test_vsuxseg2_mask_nxv16i16_nxv16i8( %val, i16* ; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i8( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -100,10 +100,10 @@ define void @test_vsuxseg2_nxv1i8_nxv1i8( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -114,10 +114,10 @@ define void @test_vsuxseg2_mask_nxv1i8_nxv1i8( %val, i8* %base, ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i8( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -131,10 +131,10 @@ define void @test_vsuxseg2_nxv1i8_nxv1i32( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -145,10 +145,10 @@ define void @test_vsuxseg2_mask_nxv1i8_nxv1i32( %val, i8* %base ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i32( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -162,10 +162,10 @@ define void @test_vsuxseg2_nxv1i8_nxv1i16( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -176,10 +176,10 @@ define void @test_vsuxseg2_mask_nxv1i8_nxv1i16( %val, i8* %base ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i16( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -870,10 +870,10 @@ define void @test_vsuxseg2_nxv16i8_nxv16i8( %val, i8* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i8( %val, %val, i8* %base, %index, i32 %vl) @@ -884,10 +884,10 @@ define void @test_vsuxseg2_mask_nxv16i8_nxv16i8( %val, i8* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i8( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -1122,10 +1122,10 @@ define void @test_vsuxseg2_nxv2i32_nxv2i32( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32( %val, %val, i32* %base, %index, i32 %vl) @@ -1136,10 +1136,10 @@ define void @test_vsuxseg2_mask_nxv2i32_nxv2i32( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -1153,10 +1153,10 @@ define void @test_vsuxseg2_nxv2i32_nxv2i8( %val, i32* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i8( %val, %val, i32* %base, %index, i32 %vl) @@ -1167,10 +1167,10 @@ define void @test_vsuxseg2_mask_nxv2i32_nxv2i8( %val, i32* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i8( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -1184,10 +1184,10 @@ define void @test_vsuxseg2_nxv2i32_nxv2i16( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i16( %val, %val, i32* %base, %index, i32 %vl) @@ -1198,10 +1198,10 @@ define void @test_vsuxseg2_mask_nxv2i32_nxv2i16( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i16( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -1863,10 +1863,10 @@ define void @test_vsuxseg2_nxv4i16_nxv4i16( %val, i16* %base, ; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i16( %val, %val, i16* %base, %index, i32 %vl) @@ -1877,10 +1877,10 @@ define void @test_vsuxseg2_mask_nxv4i16_nxv4i16( %val, i16* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i16( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -1894,10 +1894,10 @@ define void @test_vsuxseg2_nxv4i16_nxv4i8( %val, i16* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i8( %val, %val, i16* %base, %index, i32 %vl) @@ -1908,10 +1908,10 @@ define void @test_vsuxseg2_mask_nxv4i16_nxv4i8( %val, i16* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i8( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -2602,10 +2602,10 @@ define void @test_vsuxseg2_nxv1i32_nxv1i8( %val, i32* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i8( %val, %val, i32* %base, %index, i32 %vl) @@ -2616,10 +2616,10 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i8( %val, i32* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i8( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -2633,10 +2633,10 @@ define void @test_vsuxseg2_nxv1i32_nxv1i32( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i32( %val, %val, i32* %base, %index, i32 %vl) @@ -2647,10 +2647,10 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i32( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i32( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -2664,10 +2664,10 @@ define void @test_vsuxseg2_nxv1i32_nxv1i16( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16( %val, %val, i32* %base, %index, i32 %vl) @@ -2678,10 +2678,10 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i16( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -3343,10 +3343,10 @@ define void @test_vsuxseg2_nxv8i16_nxv8i16( %val, i16* %base, ; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i16( %val, %val, i16* %base, %index, i32 %vl) @@ -3357,10 +3357,10 @@ define void @test_vsuxseg2_mask_nxv8i16_nxv8i16( %val, i16* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i16( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -3374,10 +3374,10 @@ define void @test_vsuxseg2_nxv8i16_nxv8i8( %val, i16* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i8( %val, %val, i16* %base, %index, i32 %vl) @@ -3388,10 +3388,10 @@ define void @test_vsuxseg2_mask_nxv8i16_nxv8i8( %val, i16* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i8( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -3655,10 +3655,10 @@ define void @test_vsuxseg2_nxv8i8_nxv8i8( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -3669,10 +3669,10 @@ define void @test_vsuxseg2_mask_nxv8i8_nxv8i8( %val, i8* %base, ; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i8( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -4363,10 +4363,10 @@ define void @test_vsuxseg2_nxv8i32_nxv8i16( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i16( %val, %val, i32* %base, %index, i32 %vl) @@ -4377,10 +4377,10 @@ define void @test_vsuxseg2_mask_nxv8i32_nxv8i16( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i16( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -4394,10 +4394,10 @@ define void @test_vsuxseg2_nxv8i32_nxv8i8( %val, i32* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i8( %val, %val, i32* %base, %index, i32 %vl) @@ -4408,10 +4408,10 @@ define void @test_vsuxseg2_mask_nxv8i32_nxv8i8( %val, i32* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i8( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -4425,10 +4425,10 @@ define void @test_vsuxseg2_nxv8i32_nxv8i32( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i32( %val, %val, i32* %base, %index, i32 %vl) @@ -4439,10 +4439,10 @@ define void @test_vsuxseg2_mask_nxv8i32_nxv8i32( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i32( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -4456,10 +4456,10 @@ define void @test_vsuxseg2_nxv4i8_nxv4i16( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -4470,10 +4470,10 @@ define void @test_vsuxseg2_mask_nxv4i8_nxv4i16( %val, i8* %base ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i16( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -4487,10 +4487,10 @@ define void @test_vsuxseg2_nxv4i8_nxv4i8( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -4501,10 +4501,10 @@ define void @test_vsuxseg2_mask_nxv4i8_nxv4i8( %val, i8* %base, ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i8( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -5195,10 +5195,10 @@ define void @test_vsuxseg2_nxv1i16_nxv1i8( %val, i16* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i8( %val, %val, i16* %base, %index, i32 %vl) @@ -5209,10 +5209,10 @@ define void @test_vsuxseg2_mask_nxv1i16_nxv1i8( %val, i16* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i8( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -5226,10 +5226,10 @@ define void @test_vsuxseg2_nxv1i16_nxv1i32( %val, i16* %base, ; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i32( %val, %val, i16* %base, %index, i32 %vl) @@ -5240,10 +5240,10 @@ define void @test_vsuxseg2_mask_nxv1i16_nxv1i32( %val, i16* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i32( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -5257,10 +5257,10 @@ define void @test_vsuxseg2_nxv1i16_nxv1i16( %val, i16* %base, ; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i16( %val, %val, i16* %base, %index, i32 %vl) @@ -5271,10 +5271,10 @@ define void @test_vsuxseg2_mask_nxv1i16_nxv1i16( %val, i16* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i16( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -5965,10 +5965,10 @@ define void @test_vsuxseg2_nxv32i8_nxv32i8( %val, i8* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i8( %val, %val, i8* %base, %index, i32 %vl) @@ -5979,10 +5979,10 @@ define void @test_vsuxseg2_mask_nxv32i8_nxv32i8( %val, i8* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i8( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -5996,10 +5996,10 @@ define void @test_vsuxseg2_nxv2i8_nxv2i32( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -6010,10 +6010,10 @@ define void @test_vsuxseg2_mask_nxv2i8_nxv2i32( %val, i8* %base ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i32( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -6027,10 +6027,10 @@ define void @test_vsuxseg2_nxv2i8_nxv2i8( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -6041,10 +6041,10 @@ define void @test_vsuxseg2_mask_nxv2i8_nxv2i8( %val, i8* %base, ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i8( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -6058,10 +6058,10 @@ define void @test_vsuxseg2_nxv2i8_nxv2i16( %val, i8* %base, %val, %val, i8* %base, %index, i32 %vl) @@ -6072,10 +6072,10 @@ define void @test_vsuxseg2_mask_nxv2i8_nxv2i16( %val, i8* %base ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i16( %val, %val, i8* %base, %index, %mask, i32 %vl) @@ -6737,10 +6737,10 @@ define void @test_vsuxseg2_nxv2i16_nxv2i32( %val, i16* %base, ; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i32( %val, %val, i16* %base, %index, i32 %vl) @@ -6751,10 +6751,10 @@ define void @test_vsuxseg2_mask_nxv2i16_nxv2i32( %val, i16* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i32( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -6768,10 +6768,10 @@ define void @test_vsuxseg2_nxv2i16_nxv2i8( %val, i16* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i8( %val, %val, i16* %base, %index, i32 %vl) @@ -6782,10 +6782,10 @@ define void @test_vsuxseg2_mask_nxv2i16_nxv2i8( %val, i16* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i8( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -6799,10 +6799,10 @@ define void @test_vsuxseg2_nxv2i16_nxv2i16( %val, i16* %base, ; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i16( %val, %val, i16* %base, %index, i32 %vl) @@ -6813,10 +6813,10 @@ define void @test_vsuxseg2_mask_nxv2i16_nxv2i16( %val, i16* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i16( %val, %val, i16* %base, %index, %mask, i32 %vl) @@ -7478,10 +7478,10 @@ define void @test_vsuxseg2_nxv4i32_nxv4i16( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i16( %val, %val, i32* %base, %index, i32 %vl) @@ -7492,10 +7492,10 @@ define void @test_vsuxseg2_mask_nxv4i32_nxv4i16( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i16( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -7509,10 +7509,10 @@ define void @test_vsuxseg2_nxv4i32_nxv4i8( %val, i32* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i8( %val, %val, i32* %base, %index, i32 %vl) @@ -7523,10 +7523,10 @@ define void @test_vsuxseg2_mask_nxv4i32_nxv4i8( %val, i32* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i8( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -7540,10 +7540,10 @@ define void @test_vsuxseg2_nxv4i32_nxv4i32( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i32( %val, %val, i32* %base, %index, i32 %vl) @@ -7554,10 +7554,10 @@ define void @test_vsuxseg2_mask_nxv4i32_nxv4i32( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i32( %val, %val, i32* %base, %index, %mask, i32 %vl) @@ -7763,10 +7763,10 @@ define void @test_vsuxseg2_nxv16f16_nxv16i16( %val, half* %b ; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i16( %val, %val, half* %base, %index, i32 %vl) @@ -7777,10 +7777,10 @@ define void @test_vsuxseg2_mask_nxv16f16_nxv16i16( %val, hal ; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i16( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -7794,10 +7794,10 @@ define void @test_vsuxseg2_nxv16f16_nxv16i8( %val, half* %ba ; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i8( %val, %val, half* %base, %index, i32 %vl) @@ -7808,10 +7808,10 @@ define void @test_vsuxseg2_mask_nxv16f16_nxv16i8( %val, half ; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i8( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -7854,10 +7854,10 @@ define void @test_vsuxseg2_nxv4f64_nxv4i16( %val, double* % ; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i16( %val, %val, double* %base, %index, i32 %vl) @@ -7868,10 +7868,10 @@ define void @test_vsuxseg2_mask_nxv4f64_nxv4i16( %val, doub ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i16( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -7885,10 +7885,10 @@ define void @test_vsuxseg2_nxv4f64_nxv4i8( %val, double* %b ; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i8( %val, %val, double* %base, %index, i32 %vl) @@ -7899,10 +7899,10 @@ define void @test_vsuxseg2_mask_nxv4f64_nxv4i8( %val, doubl ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i8( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -7916,10 +7916,10 @@ define void @test_vsuxseg2_nxv4f64_nxv4i32( %val, double* % ; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i32( %val, %val, double* %base, %index, i32 %vl) @@ -7930,10 +7930,10 @@ define void @test_vsuxseg2_mask_nxv4f64_nxv4i32( %val, doub ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i32( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -7947,10 +7947,10 @@ define void @test_vsuxseg2_nxv1f64_nxv1i8( %val, double* %b ; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i8( %val, %val, double* %base, %index, i32 %vl) @@ -7961,10 +7961,10 @@ define void @test_vsuxseg2_mask_nxv1f64_nxv1i8( %val, doubl ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i8( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -7978,10 +7978,10 @@ define void @test_vsuxseg2_nxv1f64_nxv1i32( %val, double* % ; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i32( %val, %val, double* %base, %index, i32 %vl) @@ -7992,10 +7992,10 @@ define void @test_vsuxseg2_mask_nxv1f64_nxv1i32( %val, doub ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i32( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -8009,10 +8009,10 @@ define void @test_vsuxseg2_nxv1f64_nxv1i16( %val, double* % ; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i16( %val, %val, double* %base, %index, i32 %vl) @@ -8023,10 +8023,10 @@ define void @test_vsuxseg2_mask_nxv1f64_nxv1i16( %val, doub ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i16( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -8688,10 +8688,10 @@ define void @test_vsuxseg2_nxv2f32_nxv2i32( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i32( %val, %val, float* %base, %index, i32 %vl) @@ -8702,10 +8702,10 @@ define void @test_vsuxseg2_mask_nxv2f32_nxv2i32( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i32( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -8719,10 +8719,10 @@ define void @test_vsuxseg2_nxv2f32_nxv2i8( %val, float* %bas ; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i8( %val, %val, float* %base, %index, i32 %vl) @@ -8733,10 +8733,10 @@ define void @test_vsuxseg2_mask_nxv2f32_nxv2i8( %val, float* ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i8( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -8750,10 +8750,10 @@ define void @test_vsuxseg2_nxv2f32_nxv2i16( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i16( %val, %val, float* %base, %index, i32 %vl) @@ -8764,10 +8764,10 @@ define void @test_vsuxseg2_mask_nxv2f32_nxv2i16( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i16( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -9429,10 +9429,10 @@ define void @test_vsuxseg2_nxv1f16_nxv1i8( %val, half* %base, ; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i8( %val, %val, half* %base, %index, i32 %vl) @@ -9443,10 +9443,10 @@ define void @test_vsuxseg2_mask_nxv1f16_nxv1i8( %val, half* % ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i8( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -9460,10 +9460,10 @@ define void @test_vsuxseg2_nxv1f16_nxv1i32( %val, half* %base ; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i32( %val, %val, half* %base, %index, i32 %vl) @@ -9474,10 +9474,10 @@ define void @test_vsuxseg2_mask_nxv1f16_nxv1i32( %val, half* ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i32( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -9491,10 +9491,10 @@ define void @test_vsuxseg2_nxv1f16_nxv1i16( %val, half* %base ; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i16( %val, %val, half* %base, %index, i32 %vl) @@ -9505,10 +9505,10 @@ define void @test_vsuxseg2_mask_nxv1f16_nxv1i16( %val, half* ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i16( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -10170,10 +10170,10 @@ define void @test_vsuxseg2_nxv1f32_nxv1i8( %val, float* %bas ; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i8( %val, %val, float* %base, %index, i32 %vl) @@ -10184,10 +10184,10 @@ define void @test_vsuxseg2_mask_nxv1f32_nxv1i8( %val, float* ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i8( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -10201,10 +10201,10 @@ define void @test_vsuxseg2_nxv1f32_nxv1i32( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i32( %val, %val, float* %base, %index, i32 %vl) @@ -10215,10 +10215,10 @@ define void @test_vsuxseg2_mask_nxv1f32_nxv1i32( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i32( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -10232,10 +10232,10 @@ define void @test_vsuxseg2_nxv1f32_nxv1i16( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i16( %val, %val, float* %base, %index, i32 %vl) @@ -10246,10 +10246,10 @@ define void @test_vsuxseg2_mask_nxv1f32_nxv1i16( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i16( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -10911,10 +10911,10 @@ define void @test_vsuxseg2_nxv8f16_nxv8i16( %val, half* %base ; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i16( %val, %val, half* %base, %index, i32 %vl) @@ -10925,10 +10925,10 @@ define void @test_vsuxseg2_mask_nxv8f16_nxv8i16( %val, half* ; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i16( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -10942,10 +10942,10 @@ define void @test_vsuxseg2_nxv8f16_nxv8i8( %val, half* %base, ; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i8( %val, %val, half* %base, %index, i32 %vl) @@ -10956,10 +10956,10 @@ define void @test_vsuxseg2_mask_nxv8f16_nxv8i8( %val, half* % ; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i8( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -11194,10 +11194,10 @@ define void @test_vsuxseg2_nxv8f32_nxv8i16( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i16( %val, %val, float* %base, %index, i32 %vl) @@ -11208,10 +11208,10 @@ define void @test_vsuxseg2_mask_nxv8f32_nxv8i16( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i16( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -11225,10 +11225,10 @@ define void @test_vsuxseg2_nxv8f32_nxv8i8( %val, float* %bas ; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i8( %val, %val, float* %base, %index, i32 %vl) @@ -11239,10 +11239,10 @@ define void @test_vsuxseg2_mask_nxv8f32_nxv8i8( %val, float* ; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i8( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -11256,10 +11256,10 @@ define void @test_vsuxseg2_nxv8f32_nxv8i32( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i32( %val, %val, float* %base, %index, i32 %vl) @@ -11270,10 +11270,10 @@ define void @test_vsuxseg2_mask_nxv8f32_nxv8i32( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i32( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -11287,10 +11287,10 @@ define void @test_vsuxseg2_nxv2f64_nxv2i32( %val, double* % ; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i32( %val, %val, double* %base, %index, i32 %vl) @@ -11301,10 +11301,10 @@ define void @test_vsuxseg2_mask_nxv2f64_nxv2i32( %val, doub ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i32( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -11318,10 +11318,10 @@ define void @test_vsuxseg2_nxv2f64_nxv2i8( %val, double* %b ; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i8( %val, %val, double* %base, %index, i32 %vl) @@ -11332,10 +11332,10 @@ define void @test_vsuxseg2_mask_nxv2f64_nxv2i8( %val, doubl ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i8( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -11349,10 +11349,10 @@ define void @test_vsuxseg2_nxv2f64_nxv2i16( %val, double* % ; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i16( %val, %val, double* %base, %index, i32 %vl) @@ -11363,10 +11363,10 @@ define void @test_vsuxseg2_mask_nxv2f64_nxv2i16( %val, doub ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i16( %val, %val, double* %base, %index, %mask, i32 %vl) @@ -11572,10 +11572,10 @@ define void @test_vsuxseg2_nxv4f16_nxv4i16( %val, half* %base ; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i16( %val, %val, half* %base, %index, i32 %vl) @@ -11586,10 +11586,10 @@ define void @test_vsuxseg2_mask_nxv4f16_nxv4i16( %val, half* ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i16( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -11603,10 +11603,10 @@ define void @test_vsuxseg2_nxv4f16_nxv4i8( %val, half* %base, ; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i8( %val, %val, half* %base, %index, i32 %vl) @@ -11617,10 +11617,10 @@ define void @test_vsuxseg2_mask_nxv4f16_nxv4i8( %val, half* % ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i8( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -12311,10 +12311,10 @@ define void @test_vsuxseg2_nxv2f16_nxv2i32( %val, half* %base ; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i32( %val, %val, half* %base, %index, i32 %vl) @@ -12325,10 +12325,10 @@ define void @test_vsuxseg2_mask_nxv2f16_nxv2i32( %val, half* ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i32( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -12342,10 +12342,10 @@ define void @test_vsuxseg2_nxv2f16_nxv2i8( %val, half* %base, ; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i8( %val, %val, half* %base, %index, i32 %vl) @@ -12356,10 +12356,10 @@ define void @test_vsuxseg2_mask_nxv2f16_nxv2i8( %val, half* % ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i8( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -12373,10 +12373,10 @@ define void @test_vsuxseg2_nxv2f16_nxv2i16( %val, half* %base ; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i16( %val, %val, half* %base, %index, i32 %vl) @@ -12387,10 +12387,10 @@ define void @test_vsuxseg2_mask_nxv2f16_nxv2i16( %val, half* ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i16( %val, %val, half* %base, %index, %mask, i32 %vl) @@ -13052,10 +13052,10 @@ define void @test_vsuxseg2_nxv4f32_nxv4i16( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i16( %val, %val, float* %base, %index, i32 %vl) @@ -13066,10 +13066,10 @@ define void @test_vsuxseg2_mask_nxv4f32_nxv4i16( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i16( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -13083,10 +13083,10 @@ define void @test_vsuxseg2_nxv4f32_nxv4i8( %val, float* %bas ; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i8( %val, %val, float* %base, %index, i32 %vl) @@ -13097,10 +13097,10 @@ define void @test_vsuxseg2_mask_nxv4f32_nxv4i8( %val, float* ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i8( %val, %val, float* %base, %index, %mask, i32 %vl) @@ -13114,10 +13114,10 @@ define void @test_vsuxseg2_nxv4f32_nxv4i32( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i32( %val, %val, float* %base, %index, i32 %vl) @@ -13128,10 +13128,10 @@ define void @test_vsuxseg2_mask_nxv4f32_nxv4i32( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i32( %val, %val, float* %base, %index, %mask, i32 %vl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll index f89f8ab96b7961bb1de8d17375504d8fc6d6c5eb..b0c4c51ea73895ef31f40046f017d9bee8007022 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll @@ -9,10 +9,10 @@ define void @test_vsuxseg2_nxv16i16_nxv16i16( %val, i16* %bas ; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16( %val, %val, i16* %base, %index, i64 %vl) @@ -23,10 +23,10 @@ define void @test_vsuxseg2_mask_nxv16i16_nxv16i16( %val, i16* ; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -40,10 +40,10 @@ define void @test_vsuxseg2_nxv16i16_nxv16i8( %val, i16* %base ; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i8( %val, %val, i16* %base, %index, i64 %vl) @@ -54,10 +54,10 @@ define void @test_vsuxseg2_mask_nxv16i16_nxv16i8( %val, i16* ; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i8( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -100,10 +100,10 @@ define void @test_vsuxseg2_nxv4i32_nxv4i32( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i32( %val, %val, i32* %base, %index, i64 %vl) @@ -114,10 +114,10 @@ define void @test_vsuxseg2_mask_nxv4i32_nxv4i32( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i32( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -131,10 +131,10 @@ define void @test_vsuxseg2_nxv4i32_nxv4i8( %val, i32* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i8( %val, %val, i32* %base, %index, i64 %vl) @@ -145,10 +145,10 @@ define void @test_vsuxseg2_mask_nxv4i32_nxv4i8( %val, i32* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i8( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -191,10 +191,10 @@ define void @test_vsuxseg2_nxv4i32_nxv4i16( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i16( %val, %val, i32* %base, %index, i64 %vl) @@ -205,10 +205,10 @@ define void @test_vsuxseg2_mask_nxv4i32_nxv4i16( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i16( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -507,10 +507,10 @@ define void @test_vsuxseg2_nxv16i8_nxv16i8( %val, i8* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i8( %val, %val, i8* %base, %index, i64 %vl) @@ -521,10 +521,10 @@ define void @test_vsuxseg2_mask_nxv16i8_nxv16i8( %val, i8* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i8( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -759,10 +759,10 @@ define void @test_vsuxseg2_nxv1i64_nxv1i64( %val, i64* %base, ; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i64( %val, %val, i64* %base, %index, i64 %vl) @@ -773,10 +773,10 @@ define void @test_vsuxseg2_mask_nxv1i64_nxv1i64( %val, i64* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i64( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -790,10 +790,10 @@ define void @test_vsuxseg2_nxv1i64_nxv1i32( %val, i64* %base, ; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i32( %val, %val, i64* %base, %index, i64 %vl) @@ -804,10 +804,10 @@ define void @test_vsuxseg2_mask_nxv1i64_nxv1i32( %val, i64* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i32( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -821,10 +821,10 @@ define void @test_vsuxseg2_nxv1i64_nxv1i16( %val, i64* %base, ; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i16( %val, %val, i64* %base, %index, i64 %vl) @@ -835,10 +835,10 @@ define void @test_vsuxseg2_mask_nxv1i64_nxv1i16( %val, i64* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i16( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -852,10 +852,10 @@ define void @test_vsuxseg2_nxv1i64_nxv1i8( %val, i64* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i64.nxv1i8( %val, %val, i64* %base, %index, i64 %vl) @@ -866,10 +866,10 @@ define void @test_vsuxseg2_mask_nxv1i64_nxv1i8( %val, i64* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i64.nxv1i8( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -1747,10 +1747,10 @@ define void @test_vsuxseg2_nxv1i32_nxv1i64( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i64( %val, %val, i32* %base, %index, i64 %vl) @@ -1761,10 +1761,10 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i64( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i64( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -1778,10 +1778,10 @@ define void @test_vsuxseg2_nxv1i32_nxv1i32( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i32( %val, %val, i32* %base, %index, i64 %vl) @@ -1792,10 +1792,10 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i32( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i32( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -1809,10 +1809,10 @@ define void @test_vsuxseg2_nxv1i32_nxv1i16( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16( %val, %val, i32* %base, %index, i64 %vl) @@ -1823,10 +1823,10 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i16( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -1840,10 +1840,10 @@ define void @test_vsuxseg2_nxv1i32_nxv1i8( %val, i32* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i8( %val, %val, i32* %base, %index, i64 %vl) @@ -1854,10 +1854,10 @@ define void @test_vsuxseg2_mask_nxv1i32_nxv1i8( %val, i32* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i8( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -2735,10 +2735,10 @@ define void @test_vsuxseg2_nxv8i16_nxv8i16( %val, i16* %base, ; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i16( %val, %val, i16* %base, %index, i64 %vl) @@ -2749,10 +2749,10 @@ define void @test_vsuxseg2_mask_nxv8i16_nxv8i16( %val, i16* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i16( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -2766,10 +2766,10 @@ define void @test_vsuxseg2_nxv8i16_nxv8i8( %val, i16* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i8( %val, %val, i16* %base, %index, i64 %vl) @@ -2780,10 +2780,10 @@ define void @test_vsuxseg2_mask_nxv8i16_nxv8i8( %val, i16* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i8( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -3140,10 +3140,10 @@ define void @test_vsuxseg2_nxv4i8_nxv4i8( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -3154,10 +3154,10 @@ define void @test_vsuxseg2_mask_nxv4i8_nxv4i8( %val, i8* %base, ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i8( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -3200,10 +3200,10 @@ define void @test_vsuxseg2_nxv4i8_nxv4i16( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -3214,10 +3214,10 @@ define void @test_vsuxseg2_mask_nxv4i8_nxv4i16( %val, i8* %base ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i16( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -4095,10 +4095,10 @@ define void @test_vsuxseg2_nxv1i16_nxv1i64( %val, i16* %base, ; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i64( %val, %val, i16* %base, %index, i64 %vl) @@ -4109,10 +4109,10 @@ define void @test_vsuxseg2_mask_nxv1i16_nxv1i64( %val, i16* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i64( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -4126,10 +4126,10 @@ define void @test_vsuxseg2_nxv1i16_nxv1i32( %val, i16* %base, ; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i32( %val, %val, i16* %base, %index, i64 %vl) @@ -4140,10 +4140,10 @@ define void @test_vsuxseg2_mask_nxv1i16_nxv1i32( %val, i16* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i32( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -4157,10 +4157,10 @@ define void @test_vsuxseg2_nxv1i16_nxv1i16( %val, i16* %base, ; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i16( %val, %val, i16* %base, %index, i64 %vl) @@ -4171,10 +4171,10 @@ define void @test_vsuxseg2_mask_nxv1i16_nxv1i16( %val, i16* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i16( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -4188,10 +4188,10 @@ define void @test_vsuxseg2_nxv1i16_nxv1i8( %val, i16* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i8( %val, %val, i16* %base, %index, i64 %vl) @@ -4202,10 +4202,10 @@ define void @test_vsuxseg2_mask_nxv1i16_nxv1i8( %val, i16* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i8( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -5083,10 +5083,10 @@ define void @test_vsuxseg2_nxv2i32_nxv2i32( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32( %val, %val, i32* %base, %index, i64 %vl) @@ -5097,10 +5097,10 @@ define void @test_vsuxseg2_mask_nxv2i32_nxv2i32( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -5114,10 +5114,10 @@ define void @test_vsuxseg2_nxv2i32_nxv2i8( %val, i32* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i8( %val, %val, i32* %base, %index, i64 %vl) @@ -5128,10 +5128,10 @@ define void @test_vsuxseg2_mask_nxv2i32_nxv2i8( %val, i32* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i8( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -5145,10 +5145,10 @@ define void @test_vsuxseg2_nxv2i32_nxv2i16( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i16( %val, %val, i32* %base, %index, i64 %vl) @@ -5159,10 +5159,10 @@ define void @test_vsuxseg2_mask_nxv2i32_nxv2i16( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i16( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -6098,10 +6098,10 @@ define void @test_vsuxseg2_nxv8i8_nxv8i8( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -6112,10 +6112,10 @@ define void @test_vsuxseg2_mask_nxv8i8_nxv8i8( %val, i8* %base, ; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i8( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -7051,10 +7051,10 @@ define void @test_vsuxseg2_nxv4i64_nxv4i32( %val, i64* %base, ; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i32( %val, %val, i64* %base, %index, i64 %vl) @@ -7065,10 +7065,10 @@ define void @test_vsuxseg2_mask_nxv4i64_nxv4i32( %val, i64* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i32( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -7082,10 +7082,10 @@ define void @test_vsuxseg2_nxv4i64_nxv4i8( %val, i64* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i8( %val, %val, i64* %base, %index, i64 %vl) @@ -7096,10 +7096,10 @@ define void @test_vsuxseg2_mask_nxv4i64_nxv4i8( %val, i64* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i8( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -7113,10 +7113,10 @@ define void @test_vsuxseg2_nxv4i64_nxv4i64( %val, i64* %base, ; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v28 +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i64( %val, %val, i64* %base, %index, i64 %vl) @@ -7127,10 +7127,10 @@ define void @test_vsuxseg2_mask_nxv4i64_nxv4i64( %val, i64* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i64( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -7144,10 +7144,10 @@ define void @test_vsuxseg2_nxv4i64_nxv4i16( %val, i64* %base, ; CHECK-LABEL: test_vsuxseg2_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4i64.nxv4i16( %val, %val, i64* %base, %index, i64 %vl) @@ -7158,10 +7158,10 @@ define void @test_vsuxseg2_mask_nxv4i64_nxv4i16( %val, i64* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i64.nxv4i16( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -7204,10 +7204,10 @@ define void @test_vsuxseg2_nxv4i16_nxv4i8( %val, i16* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i8( %val, %val, i16* %base, %index, i64 %vl) @@ -7218,10 +7218,10 @@ define void @test_vsuxseg2_mask_nxv4i16_nxv4i8( %val, i16* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i8( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -7264,10 +7264,10 @@ define void @test_vsuxseg2_nxv4i16_nxv4i16( %val, i16* %base, ; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i16( %val, %val, i16* %base, %index, i64 %vl) @@ -7278,10 +7278,10 @@ define void @test_vsuxseg2_mask_nxv4i16_nxv4i16( %val, i16* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i16( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -8159,10 +8159,10 @@ define void @test_vsuxseg2_nxv1i8_nxv1i64( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -8173,10 +8173,10 @@ define void @test_vsuxseg2_mask_nxv1i8_nxv1i64( %val, i8* %base ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i64( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -8190,10 +8190,10 @@ define void @test_vsuxseg2_nxv1i8_nxv1i32( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -8204,10 +8204,10 @@ define void @test_vsuxseg2_mask_nxv1i8_nxv1i32( %val, i8* %base ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i32( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -8221,10 +8221,10 @@ define void @test_vsuxseg2_nxv1i8_nxv1i16( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -8235,10 +8235,10 @@ define void @test_vsuxseg2_mask_nxv1i8_nxv1i16( %val, i8* %base ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i16( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -8252,10 +8252,10 @@ define void @test_vsuxseg2_nxv1i8_nxv1i8( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -8266,10 +8266,10 @@ define void @test_vsuxseg2_mask_nxv1i8_nxv1i8( %val, i8* %base, ; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i8( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -9147,10 +9147,10 @@ define void @test_vsuxseg2_nxv2i8_nxv2i32( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -9161,10 +9161,10 @@ define void @test_vsuxseg2_mask_nxv2i8_nxv2i32( %val, i8* %base ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i32( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -9178,10 +9178,10 @@ define void @test_vsuxseg2_nxv2i8_nxv2i8( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -9192,10 +9192,10 @@ define void @test_vsuxseg2_mask_nxv2i8_nxv2i8( %val, i8* %base, ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i8( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -9209,10 +9209,10 @@ define void @test_vsuxseg2_nxv2i8_nxv2i16( %val, i8* %base, %val, %val, i8* %base, %index, i64 %vl) @@ -9223,10 +9223,10 @@ define void @test_vsuxseg2_mask_nxv2i8_nxv2i16( %val, i8* %base ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i16( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -10133,10 +10133,10 @@ define void @test_vsuxseg2_nxv8i32_nxv8i16( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i16( %val, %val, i32* %base, %index, i64 %vl) @@ -10147,10 +10147,10 @@ define void @test_vsuxseg2_mask_nxv8i32_nxv8i16( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i16( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -10164,10 +10164,10 @@ define void @test_vsuxseg2_nxv8i32_nxv8i8( %val, i32* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i8( %val, %val, i32* %base, %index, i64 %vl) @@ -10178,10 +10178,10 @@ define void @test_vsuxseg2_mask_nxv8i32_nxv8i8( %val, i32* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i8( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -10224,10 +10224,10 @@ define void @test_vsuxseg2_nxv8i32_nxv8i32( %val, i32* %base, ; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i32( %val, %val, i32* %base, %index, i64 %vl) @@ -10238,10 +10238,10 @@ define void @test_vsuxseg2_mask_nxv8i32_nxv8i32( %val, i32* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i32( %val, %val, i32* %base, %index, %mask, i64 %vl) @@ -10284,10 +10284,10 @@ define void @test_vsuxseg2_nxv32i8_nxv32i8( %val, i8* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i8( %val, %val, i8* %base, %index, i64 %vl) @@ -10298,10 +10298,10 @@ define void @test_vsuxseg2_mask_nxv32i8_nxv32i8( %val, i8* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i8( %val, %val, i8* %base, %index, %mask, i64 %vl) @@ -10315,10 +10315,10 @@ define void @test_vsuxseg2_nxv2i16_nxv2i32( %val, i16* %base, ; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i32( %val, %val, i16* %base, %index, i64 %vl) @@ -10329,10 +10329,10 @@ define void @test_vsuxseg2_mask_nxv2i16_nxv2i32( %val, i16* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i32( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -10346,10 +10346,10 @@ define void @test_vsuxseg2_nxv2i16_nxv2i8( %val, i16* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i8( %val, %val, i16* %base, %index, i64 %vl) @@ -10360,10 +10360,10 @@ define void @test_vsuxseg2_mask_nxv2i16_nxv2i8( %val, i16* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i8( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -10377,10 +10377,10 @@ define void @test_vsuxseg2_nxv2i16_nxv2i16( %val, i16* %base, ; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i16( %val, %val, i16* %base, %index, i64 %vl) @@ -10391,10 +10391,10 @@ define void @test_vsuxseg2_mask_nxv2i16_nxv2i16( %val, i16* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i16( %val, %val, i16* %base, %index, %mask, i64 %vl) @@ -11301,10 +11301,10 @@ define void @test_vsuxseg2_nxv2i64_nxv2i32( %val, i64* %base, ; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i32( %val, %val, i64* %base, %index, i64 %vl) @@ -11315,10 +11315,10 @@ define void @test_vsuxseg2_mask_nxv2i64_nxv2i32( %val, i64* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i32( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -11332,10 +11332,10 @@ define void @test_vsuxseg2_nxv2i64_nxv2i8( %val, i64* %base, < ; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i8( %val, %val, i64* %base, %index, i64 %vl) @@ -11346,10 +11346,10 @@ define void @test_vsuxseg2_mask_nxv2i64_nxv2i8( %val, i64* %ba ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i8( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -11363,10 +11363,10 @@ define void @test_vsuxseg2_nxv2i64_nxv2i16( %val, i64* %base, ; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i16( %val, %val, i64* %base, %index, i64 %vl) @@ -11377,10 +11377,10 @@ define void @test_vsuxseg2_mask_nxv2i64_nxv2i16( %val, i64* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i16( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -11394,10 +11394,10 @@ define void @test_vsuxseg2_nxv2i64_nxv2i64( %val, i64* %base, ; CHECK-LABEL: test_vsuxseg2_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2i64.nxv2i64( %val, %val, i64* %base, %index, i64 %vl) @@ -11408,10 +11408,10 @@ define void @test_vsuxseg2_mask_nxv2i64_nxv2i64( %val, i64* %b ; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2i64.nxv2i64( %val, %val, i64* %base, %index, %mask, i64 %vl) @@ -11681,10 +11681,10 @@ define void @test_vsuxseg2_nxv16f16_nxv16i16( %val, half* %b ; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i16( %val, %val, half* %base, %index, i64 %vl) @@ -11695,10 +11695,10 @@ define void @test_vsuxseg2_mask_nxv16f16_nxv16i16( %val, hal ; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i16( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -11712,10 +11712,10 @@ define void @test_vsuxseg2_nxv16f16_nxv16i8( %val, half* %ba ; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i8( %val, %val, half* %base, %index, i64 %vl) @@ -11726,10 +11726,10 @@ define void @test_vsuxseg2_mask_nxv16f16_nxv16i8( %val, half ; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i8( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -11772,10 +11772,10 @@ define void @test_vsuxseg2_nxv4f64_nxv4i32( %val, double* % ; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i32( %val, %val, double* %base, %index, i64 %vl) @@ -11786,10 +11786,10 @@ define void @test_vsuxseg2_mask_nxv4f64_nxv4i32( %val, doub ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i32( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -11803,10 +11803,10 @@ define void @test_vsuxseg2_nxv4f64_nxv4i8( %val, double* %b ; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i8( %val, %val, double* %base, %index, i64 %vl) @@ -11817,10 +11817,10 @@ define void @test_vsuxseg2_mask_nxv4f64_nxv4i8( %val, doubl ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i8( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -11834,10 +11834,10 @@ define void @test_vsuxseg2_nxv4f64_nxv4i64( %val, double* % ; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v28 +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i64( %val, %val, double* %base, %index, i64 %vl) @@ -11848,10 +11848,10 @@ define void @test_vsuxseg2_mask_nxv4f64_nxv4i64( %val, doub ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i64( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -11865,10 +11865,10 @@ define void @test_vsuxseg2_nxv4f64_nxv4i16( %val, double* % ; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i16( %val, %val, double* %base, %index, i64 %vl) @@ -11879,10 +11879,10 @@ define void @test_vsuxseg2_mask_nxv4f64_nxv4i16( %val, doub ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i16( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -11896,10 +11896,10 @@ define void @test_vsuxseg2_nxv1f64_nxv1i64( %val, double* % ; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i64( %val, %val, double* %base, %index, i64 %vl) @@ -11910,10 +11910,10 @@ define void @test_vsuxseg2_mask_nxv1f64_nxv1i64( %val, doub ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i64( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -11927,10 +11927,10 @@ define void @test_vsuxseg2_nxv1f64_nxv1i32( %val, double* % ; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i32( %val, %val, double* %base, %index, i64 %vl) @@ -11941,10 +11941,10 @@ define void @test_vsuxseg2_mask_nxv1f64_nxv1i32( %val, doub ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i32( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -11958,10 +11958,10 @@ define void @test_vsuxseg2_nxv1f64_nxv1i16( %val, double* % ; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i16( %val, %val, double* %base, %index, i64 %vl) @@ -11972,10 +11972,10 @@ define void @test_vsuxseg2_mask_nxv1f64_nxv1i16( %val, doub ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i16( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -11989,10 +11989,10 @@ define void @test_vsuxseg2_nxv1f64_nxv1i8( %val, double* %b ; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i8( %val, %val, double* %base, %index, i64 %vl) @@ -12003,10 +12003,10 @@ define void @test_vsuxseg2_mask_nxv1f64_nxv1i8( %val, doubl ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i8( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -12884,10 +12884,10 @@ define void @test_vsuxseg2_nxv2f32_nxv2i32( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i32( %val, %val, float* %base, %index, i64 %vl) @@ -12898,10 +12898,10 @@ define void @test_vsuxseg2_mask_nxv2f32_nxv2i32( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i32( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -12915,10 +12915,10 @@ define void @test_vsuxseg2_nxv2f32_nxv2i8( %val, float* %bas ; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i8( %val, %val, float* %base, %index, i64 %vl) @@ -12929,10 +12929,10 @@ define void @test_vsuxseg2_mask_nxv2f32_nxv2i8( %val, float* ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i8( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -12946,10 +12946,10 @@ define void @test_vsuxseg2_nxv2f32_nxv2i16( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i16( %val, %val, float* %base, %index, i64 %vl) @@ -12960,10 +12960,10 @@ define void @test_vsuxseg2_mask_nxv2f32_nxv2i16( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i16( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -13870,10 +13870,10 @@ define void @test_vsuxseg2_nxv1f16_nxv1i64( %val, half* %base ; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i64( %val, %val, half* %base, %index, i64 %vl) @@ -13884,10 +13884,10 @@ define void @test_vsuxseg2_mask_nxv1f16_nxv1i64( %val, half* ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i64( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -13901,10 +13901,10 @@ define void @test_vsuxseg2_nxv1f16_nxv1i32( %val, half* %base ; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i32( %val, %val, half* %base, %index, i64 %vl) @@ -13915,10 +13915,10 @@ define void @test_vsuxseg2_mask_nxv1f16_nxv1i32( %val, half* ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i32( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -13932,10 +13932,10 @@ define void @test_vsuxseg2_nxv1f16_nxv1i16( %val, half* %base ; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i16( %val, %val, half* %base, %index, i64 %vl) @@ -13946,10 +13946,10 @@ define void @test_vsuxseg2_mask_nxv1f16_nxv1i16( %val, half* ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i16( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -13963,10 +13963,10 @@ define void @test_vsuxseg2_nxv1f16_nxv1i8( %val, half* %base, ; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i8( %val, %val, half* %base, %index, i64 %vl) @@ -13977,10 +13977,10 @@ define void @test_vsuxseg2_mask_nxv1f16_nxv1i8( %val, half* % ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i8( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -14858,10 +14858,10 @@ define void @test_vsuxseg2_nxv1f32_nxv1i64( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i64( %val, %val, float* %base, %index, i64 %vl) @@ -14872,10 +14872,10 @@ define void @test_vsuxseg2_mask_nxv1f32_nxv1i64( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i64( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -14889,10 +14889,10 @@ define void @test_vsuxseg2_nxv1f32_nxv1i32( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i32( %val, %val, float* %base, %index, i64 %vl) @@ -14903,10 +14903,10 @@ define void @test_vsuxseg2_mask_nxv1f32_nxv1i32( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i32( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -14920,10 +14920,10 @@ define void @test_vsuxseg2_nxv1f32_nxv1i16( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i16( %val, %val, float* %base, %index, i64 %vl) @@ -14934,10 +14934,10 @@ define void @test_vsuxseg2_mask_nxv1f32_nxv1i16( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i16( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -14951,10 +14951,10 @@ define void @test_vsuxseg2_nxv1f32_nxv1i8( %val, float* %bas ; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i8( %val, %val, float* %base, %index, i64 %vl) @@ -14965,10 +14965,10 @@ define void @test_vsuxseg2_mask_nxv1f32_nxv1i8( %val, float* ; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i8( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -15846,10 +15846,10 @@ define void @test_vsuxseg2_nxv8f16_nxv8i16( %val, half* %base ; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i16( %val, %val, half* %base, %index, i64 %vl) @@ -15860,10 +15860,10 @@ define void @test_vsuxseg2_mask_nxv8f16_nxv8i16( %val, half* ; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i16( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -15877,10 +15877,10 @@ define void @test_vsuxseg2_nxv8f16_nxv8i8( %val, half* %base, ; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i8( %val, %val, half* %base, %index, i64 %vl) @@ -15891,10 +15891,10 @@ define void @test_vsuxseg2_mask_nxv8f16_nxv8i8( %val, half* % ; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i8( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -16222,10 +16222,10 @@ define void @test_vsuxseg2_nxv8f32_nxv8i16( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i16( %val, %val, float* %base, %index, i64 %vl) @@ -16236,10 +16236,10 @@ define void @test_vsuxseg2_mask_nxv8f32_nxv8i16( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv2r.v v26, v12 +; CHECK-NEXT: vmv2r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i16( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -16253,10 +16253,10 @@ define void @test_vsuxseg2_nxv8f32_nxv8i8( %val, float* %bas ; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i8( %val, %val, float* %base, %index, i64 %vl) @@ -16267,10 +16267,10 @@ define void @test_vsuxseg2_mask_nxv8f32_nxv8i8( %val, float* ; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv1r.v v25, v12 +; CHECK-NEXT: vmv1r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i8( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -16313,10 +16313,10 @@ define void @test_vsuxseg2_nxv8f32_nxv8i32( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i32( %val, %val, float* %base, %index, i64 %vl) @@ -16327,10 +16327,10 @@ define void @test_vsuxseg2_mask_nxv8f32_nxv8i32( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i32( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -16344,10 +16344,10 @@ define void @test_vsuxseg2_nxv2f64_nxv2i32( %val, double* % ; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i32( %val, %val, double* %base, %index, i64 %vl) @@ -16358,10 +16358,10 @@ define void @test_vsuxseg2_mask_nxv2f64_nxv2i32( %val, doub ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i32( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -16375,10 +16375,10 @@ define void @test_vsuxseg2_nxv2f64_nxv2i8( %val, double* %b ; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i8( %val, %val, double* %base, %index, i64 %vl) @@ -16389,10 +16389,10 @@ define void @test_vsuxseg2_mask_nxv2f64_nxv2i8( %val, doubl ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i8( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -16406,10 +16406,10 @@ define void @test_vsuxseg2_nxv2f64_nxv2i16( %val, double* % ; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i16( %val, %val, double* %base, %index, i64 %vl) @@ -16420,10 +16420,10 @@ define void @test_vsuxseg2_mask_nxv2f64_nxv2i16( %val, doub ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i16( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -16437,10 +16437,10 @@ define void @test_vsuxseg2_nxv2f64_nxv2i64( %val, double* % ; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i64( %val, %val, double* %base, %index, i64 %vl) @@ -16451,10 +16451,10 @@ define void @test_vsuxseg2_mask_nxv2f64_nxv2i64( %val, doub ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i64( %val, %val, double* %base, %index, %mask, i64 %vl) @@ -16753,10 +16753,10 @@ define void @test_vsuxseg2_nxv4f16_nxv4i8( %val, half* %base, ; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i8( %val, %val, half* %base, %index, i64 %vl) @@ -16767,10 +16767,10 @@ define void @test_vsuxseg2_mask_nxv4f16_nxv4i8( %val, half* % ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i8( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -16813,10 +16813,10 @@ define void @test_vsuxseg2_nxv4f16_nxv4i16( %val, half* %base ; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i16( %val, %val, half* %base, %index, i64 %vl) @@ -16827,10 +16827,10 @@ define void @test_vsuxseg2_mask_nxv4f16_nxv4i16( %val, half* ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i16( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -17708,10 +17708,10 @@ define void @test_vsuxseg2_nxv2f16_nxv2i32( %val, half* %base ; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i32( %val, %val, half* %base, %index, i64 %vl) @@ -17722,10 +17722,10 @@ define void @test_vsuxseg2_mask_nxv2f16_nxv2i32( %val, half* ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i32( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -17739,10 +17739,10 @@ define void @test_vsuxseg2_nxv2f16_nxv2i8( %val, half* %base, ; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i8( %val, %val, half* %base, %index, i64 %vl) @@ -17753,10 +17753,10 @@ define void @test_vsuxseg2_mask_nxv2f16_nxv2i8( %val, half* % ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i8( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -17770,10 +17770,10 @@ define void @test_vsuxseg2_nxv2f16_nxv2i16( %val, half* %base ; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i16( %val, %val, half* %base, %index, i64 %vl) @@ -17784,10 +17784,10 @@ define void @test_vsuxseg2_mask_nxv2f16_nxv2i16( %val, half* ; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9 -; CHECK-NEXT: vmv1r.v v25, v9 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i16( %val, %val, half* %base, %index, %mask, i64 %vl) @@ -18694,10 +18694,10 @@ define void @test_vsuxseg2_nxv4f32_nxv4i32( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26 +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i32( %val, %val, float* %base, %index, i64 %vl) @@ -18708,10 +18708,10 @@ define void @test_vsuxseg2_mask_nxv4f32_nxv4i32( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv2r.v v26, v10 +; CHECK-NEXT: vmv2r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v26, v0.t +; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i32( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -18725,10 +18725,10 @@ define void @test_vsuxseg2_nxv4f32_nxv4i8( %val, float* %bas ; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i8( %val, %val, float* %base, %index, i64 %vl) @@ -18739,10 +18739,10 @@ define void @test_vsuxseg2_mask_nxv4f32_nxv4i8( %val, float* ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i8( %val, %val, float* %base, %index, %mask, i64 %vl) @@ -18785,10 +18785,10 @@ define void @test_vsuxseg2_nxv4f32_nxv4i16( %val, float* %ba ; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i16( %val, %val, float* %base, %index, i64 %vl) @@ -18799,10 +18799,10 @@ define void @test_vsuxseg2_mask_nxv4f32_nxv4i16( %val, float ; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2 -; CHECK-NEXT: vmv1r.v v25, v10 +; CHECK-NEXT: vmv1r.v v12, v10 ; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v25, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i16( %val, %val, float* %base, %index, %mask, i64 %vl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll index 26f4bb49c6947d17869ebb55406f339aa7e392a5..d359263def2e9a70a5d3cea85ec3e8782f67c02c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll @@ -35,8 +35,8 @@ define @vtrunc_nxv8i16_nxv8i8( %va) { ; CHECK-LABEL: vtrunc_nxv8i16_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -46,8 +46,8 @@ define @vtrunc_nxv16i16_nxv16i8( %va) { ; CHECK-LABEL: vtrunc_nxv16i16_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -57,9 +57,9 @@ define @vtrunc_nxv1i32_nxv1i8( %va) { ; CHECK-LABEL: vtrunc_nxv1i32_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -79,9 +79,9 @@ define @vtrunc_nxv2i32_nxv2i8( %va) { ; CHECK-LABEL: vtrunc_nxv2i32_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -101,9 +101,9 @@ define @vtrunc_nxv4i32_nxv4i8( %va) { ; CHECK-LABEL: vtrunc_nxv4i32_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -113,8 +113,8 @@ define @vtrunc_nxv4i32_nxv4i16( %va) { ; CHECK-LABEL: vtrunc_nxv4i32_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -124,9 +124,9 @@ define @vtrunc_nxv8i32_nxv8i8( %va) { ; CHECK-LABEL: vtrunc_nxv8i32_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -136,8 +136,8 @@ define @vtrunc_nxv8i32_nxv8i16( %va) { ; CHECK-LABEL: vtrunc_nxv8i32_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -147,9 +147,9 @@ define @vtrunc_nxv16i32_nxv16i8( %va) { ; CHECK-LABEL: vtrunc_nxv16i32_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v28, 0 +; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -159,8 +159,8 @@ define @vtrunc_nxv16i32_nxv16i16( %va) { ; CHECK-LABEL: vtrunc_nxv16i32_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -170,11 +170,11 @@ define @vtrunc_nxv1i64_nxv1i8( %va) { ; CHECK-LABEL: vtrunc_nxv1i64_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -184,9 +184,9 @@ define @vtrunc_nxv1i64_nxv1i16( %va) { ; CHECK-LABEL: vtrunc_nxv1i64_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -206,11 +206,11 @@ define @vtrunc_nxv2i64_nxv2i8( %va) { ; CHECK-LABEL: vtrunc_nxv2i64_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -220,9 +220,9 @@ define @vtrunc_nxv2i64_nxv2i16( %va) { ; CHECK-LABEL: vtrunc_nxv2i64_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -232,8 +232,8 @@ define @vtrunc_nxv2i64_nxv2i32( %va) { ; CHECK-LABEL: vtrunc_nxv2i64_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -243,11 +243,11 @@ define @vtrunc_nxv4i64_nxv4i8( %va) { ; CHECK-LABEL: vtrunc_nxv4i64_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -257,9 +257,9 @@ define @vtrunc_nxv4i64_nxv4i16( %va) { ; CHECK-LABEL: vtrunc_nxv4i64_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -269,8 +269,8 @@ define @vtrunc_nxv4i64_nxv4i32( %va) { ; CHECK-LABEL: vtrunc_nxv4i64_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -280,11 +280,11 @@ define @vtrunc_nxv8i64_nxv8i8( %va) { ; CHECK-LABEL: vtrunc_nxv8i64_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v28, 0 +; CHECK-NEXT: vnsrl.wi v10, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -294,9 +294,9 @@ define @vtrunc_nxv8i64_nxv8i16( %va) { ; CHECK-LABEL: vtrunc_nxv8i64_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v28, 0 +; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -306,8 +306,8 @@ define @vtrunc_nxv8i64_nxv8i32( %va) { ; CHECK-LABEL: vtrunc_nxv8i64_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec diff --git a/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll index d204f44fadd1aba2d5c53d8fe78a3536c798e069..138f1e6f805f6aa0dd3552289978b156e499df9a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll @@ -35,8 +35,8 @@ define @vtrunc_nxv8i16_nxv8i8( %va) { ; CHECK-LABEL: vtrunc_nxv8i16_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -46,8 +46,8 @@ define @vtrunc_nxv16i16_nxv16i8( %va) { ; CHECK-LABEL: vtrunc_nxv16i16_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -57,9 +57,9 @@ define @vtrunc_nxv1i32_nxv1i8( %va) { ; CHECK-LABEL: vtrunc_nxv1i32_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -79,9 +79,9 @@ define @vtrunc_nxv2i32_nxv2i8( %va) { ; CHECK-LABEL: vtrunc_nxv2i32_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -101,9 +101,9 @@ define @vtrunc_nxv4i32_nxv4i8( %va) { ; CHECK-LABEL: vtrunc_nxv4i32_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -113,8 +113,8 @@ define @vtrunc_nxv4i32_nxv4i16( %va) { ; CHECK-LABEL: vtrunc_nxv4i32_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -124,9 +124,9 @@ define @vtrunc_nxv8i32_nxv8i8( %va) { ; CHECK-LABEL: vtrunc_nxv8i32_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -136,8 +136,8 @@ define @vtrunc_nxv8i32_nxv8i16( %va) { ; CHECK-LABEL: vtrunc_nxv8i32_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -147,9 +147,9 @@ define @vtrunc_nxv16i32_nxv16i8( %va) { ; CHECK-LABEL: vtrunc_nxv16i32_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v28, 0 +; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -159,8 +159,8 @@ define @vtrunc_nxv16i32_nxv16i16( %va) { ; CHECK-LABEL: vtrunc_nxv16i32_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -170,11 +170,11 @@ define @vtrunc_nxv1i64_nxv1i8( %va) { ; CHECK-LABEL: vtrunc_nxv1i64_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -184,9 +184,9 @@ define @vtrunc_nxv1i64_nxv1i16( %va) { ; CHECK-LABEL: vtrunc_nxv1i64_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -206,11 +206,11 @@ define @vtrunc_nxv2i64_nxv2i8( %va) { ; CHECK-LABEL: vtrunc_nxv2i64_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -220,9 +220,9 @@ define @vtrunc_nxv2i64_nxv2i16( %va) { ; CHECK-LABEL: vtrunc_nxv2i64_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -232,8 +232,8 @@ define @vtrunc_nxv2i64_nxv2i32( %va) { ; CHECK-LABEL: vtrunc_nxv2i64_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v8, 0 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vnsrl.wi v10, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -243,11 +243,11 @@ define @vtrunc_nxv4i64_nxv4i8( %va) { ; CHECK-LABEL: vtrunc_nxv4i64_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v25, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -257,9 +257,9 @@ define @vtrunc_nxv4i64_nxv4i16( %va) { ; CHECK-LABEL: vtrunc_nxv4i64_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -269,8 +269,8 @@ define @vtrunc_nxv4i64_nxv4i32( %va) { ; CHECK-LABEL: vtrunc_nxv4i64_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v8, 0 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vnsrl.wi v12, v8, 0 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -280,11 +280,11 @@ define @vtrunc_nxv8i64_nxv8i8( %va) { ; CHECK-LABEL: vtrunc_nxv8i64_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v26, v28, 0 +; CHECK-NEXT: vnsrl.wi v10, v16, 0 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -294,9 +294,9 @@ define @vtrunc_nxv8i64_nxv8i16( %va) { ; CHECK-LABEL: vtrunc_nxv8i64_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vnsrl.wi v8, v28, 0 +; CHECK-NEXT: vnsrl.wi v8, v16, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -306,8 +306,8 @@ define @vtrunc_nxv8i64_nxv8i32( %va) { ; CHECK-LABEL: vtrunc_nxv8i64_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu -; CHECK-NEXT: vnsrl.wi v28, v8, 0 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vnsrl.wi v16, v8, 0 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll index 19e2d3459d681f88c0a4e727ce5c9a943f63add6..f57bf32b789cdcbb8b145d79b44d6a893006c6f0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll @@ -10,8 +10,8 @@ define @intrinsic_vwadd_vv_nxv1i16_nxv1i8_nxv1i8( @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vwadd_vv_nxv2i16_nxv2i8_nxv2i8( @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vwadd_vv_nxv4i16_nxv4i8_nxv4i8( @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vwadd_vv_nxv8i16_nxv8i8_nxv8i8( @llvm.riscv.vwadd.nxv8i16.nxv8i8.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vwadd_vv_nxv16i16_nxv16i8_nxv16i8( @llvm.riscv.vwadd.nxv16i16.nxv16i8.nxv16i8( @@ -286,8 +286,8 @@ define @intrinsic_vwadd_vv_nxv1i32_nxv1i16_nxv1i16( @llvm.riscv.vwadd.nxv1i32.nxv1i16.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vwadd_vv_nxv2i32_nxv2i16_nxv2i16( @llvm.riscv.vwadd.nxv2i32.nxv2i16.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vwadd_vv_nxv4i32_nxv4i16_nxv4i16( @llvm.riscv.vwadd.nxv4i32.nxv4i16.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vwadd_vv_nxv8i32_nxv8i16_nxv8i16( @llvm.riscv.vwadd.nxv8i32.nxv8i16.nxv8i16( @@ -516,8 +516,8 @@ define @intrinsic_vwadd_vv_nxv1i64_nxv1i32_nxv1i32( @llvm.riscv.vwadd.nxv1i64.nxv1i32.nxv1i32( @@ -562,8 +562,8 @@ define @intrinsic_vwadd_vv_nxv2i64_nxv2i32_nxv2i32( @llvm.riscv.vwadd.nxv2i64.nxv2i32.nxv2i32( @@ -608,8 +608,8 @@ define @intrinsic_vwadd_vv_nxv4i64_nxv4i32_nxv4i32( @llvm.riscv.vwadd.nxv4i64.nxv4i32.nxv4i32( @@ -700,8 +700,8 @@ define @intrinsic_vwadd_vx_nxv1i16_nxv1i8_i8( @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8( @@ -746,8 +746,8 @@ define @intrinsic_vwadd_vx_nxv2i16_nxv2i8_i8( @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8( @@ -792,8 +792,8 @@ define @intrinsic_vwadd_vx_nxv4i16_nxv4i8_i8( @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8( @@ -838,8 +838,8 @@ define @intrinsic_vwadd_vx_nxv8i16_nxv8i8_i8( @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8( @@ -884,8 +884,8 @@ define @intrinsic_vwadd_vx_nxv16i16_nxv16i8_i8( @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8( @@ -976,8 +976,8 @@ define @intrinsic_vwadd_vx_nxv1i32_nxv1i16_i16( @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16( @@ -1022,8 +1022,8 @@ define @intrinsic_vwadd_vx_nxv2i32_nxv2i16_i16( @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16( @@ -1068,8 +1068,8 @@ define @intrinsic_vwadd_vx_nxv4i32_nxv4i16_i16( @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16( @@ -1114,8 +1114,8 @@ define @intrinsic_vwadd_vx_nxv8i32_nxv8i16_i16( @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16( @@ -1206,8 +1206,8 @@ define @intrinsic_vwadd_vx_nxv1i64_nxv1i32_i32( @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32( @@ -1252,8 +1252,8 @@ define @intrinsic_vwadd_vx_nxv2i64_nxv2i32_i32( @llvm.riscv.vwadd.nxv2i64.nxv2i32.i32( @@ -1298,8 +1298,8 @@ define @intrinsic_vwadd_vx_nxv4i64_nxv4i32_i32( @llvm.riscv.vwadd.nxv4i64.nxv4i32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll index fa250394fdab7fce3bc7d3a66786f7c5e2921594..7ec1fa4e4a950a71286d95ca8e3945781fa38d8a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll @@ -10,8 +10,8 @@ define @intrinsic_vwadd_vv_nxv1i16_nxv1i8_nxv1i8( @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vwadd_vv_nxv2i16_nxv2i8_nxv2i8( @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vwadd_vv_nxv4i16_nxv4i8_nxv4i8( @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vwadd_vv_nxv8i16_nxv8i8_nxv8i8( @llvm.riscv.vwadd.nxv8i16.nxv8i8.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vwadd_vv_nxv16i16_nxv16i8_nxv16i8( @llvm.riscv.vwadd.nxv16i16.nxv16i8.nxv16i8( @@ -286,8 +286,8 @@ define @intrinsic_vwadd_vv_nxv1i32_nxv1i16_nxv1i16( @llvm.riscv.vwadd.nxv1i32.nxv1i16.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vwadd_vv_nxv2i32_nxv2i16_nxv2i16( @llvm.riscv.vwadd.nxv2i32.nxv2i16.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vwadd_vv_nxv4i32_nxv4i16_nxv4i16( @llvm.riscv.vwadd.nxv4i32.nxv4i16.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vwadd_vv_nxv8i32_nxv8i16_nxv8i16( @llvm.riscv.vwadd.nxv8i32.nxv8i16.nxv8i16( @@ -516,8 +516,8 @@ define @intrinsic_vwadd_vv_nxv1i64_nxv1i32_nxv1i32( @llvm.riscv.vwadd.nxv1i64.nxv1i32.nxv1i32( @@ -562,8 +562,8 @@ define @intrinsic_vwadd_vv_nxv2i64_nxv2i32_nxv2i32( @llvm.riscv.vwadd.nxv2i64.nxv2i32.nxv2i32( @@ -608,8 +608,8 @@ define @intrinsic_vwadd_vv_nxv4i64_nxv4i32_nxv4i32( @llvm.riscv.vwadd.nxv4i64.nxv4i32.nxv4i32( @@ -700,8 +700,8 @@ define @intrinsic_vwadd_vx_nxv1i16_nxv1i8_i8( @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8( @@ -746,8 +746,8 @@ define @intrinsic_vwadd_vx_nxv2i16_nxv2i8_i8( @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8( @@ -792,8 +792,8 @@ define @intrinsic_vwadd_vx_nxv4i16_nxv4i8_i8( @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8( @@ -838,8 +838,8 @@ define @intrinsic_vwadd_vx_nxv8i16_nxv8i8_i8( @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8( @@ -884,8 +884,8 @@ define @intrinsic_vwadd_vx_nxv16i16_nxv16i8_i8( @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8( @@ -976,8 +976,8 @@ define @intrinsic_vwadd_vx_nxv1i32_nxv1i16_i16( @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16( @@ -1022,8 +1022,8 @@ define @intrinsic_vwadd_vx_nxv2i32_nxv2i16_i16( @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16( @@ -1068,8 +1068,8 @@ define @intrinsic_vwadd_vx_nxv4i32_nxv4i16_i16( @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16( @@ -1114,8 +1114,8 @@ define @intrinsic_vwadd_vx_nxv8i32_nxv8i16_i16( @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16( @@ -1206,8 +1206,8 @@ define @intrinsic_vwadd_vx_nxv1i64_nxv1i32_i32( @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32( @@ -1252,8 +1252,8 @@ define @intrinsic_vwadd_vx_nxv2i64_nxv2i32_i32( @llvm.riscv.vwadd.nxv2i64.nxv2i32.i32( @@ -1298,8 +1298,8 @@ define @intrinsic_vwadd_vx_nxv4i64_nxv4i32_i32( @llvm.riscv.vwadd.nxv4i64.nxv4i32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll index ffc5bfce5077d675a42b9330ead472ec011bcbc9..d88618fd7a66bc50692d22fd88a8d539e34e65cf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll @@ -257,9 +257,9 @@ declare @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4r.v v28, (a0) +; CHECK-NEXT: vl4r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8( @@ -483,9 +483,9 @@ declare @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16( @@ -664,9 +664,9 @@ declare @llvm.riscv.vwadd.w.mask.nxv8i64.nxv8i32( define @intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwadd.w.mask.nxv8i64.nxv8i32( @@ -1868,8 +1868,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv1i16_nxv1i16_nxv1i8( @llvm.riscv.vwadd.w.nxv1i16.nxv1i8( @@ -1884,8 +1884,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv2i16_nxv2i16_nxv2i8( @llvm.riscv.vwadd.w.nxv2i16.nxv2i8( @@ -1900,8 +1900,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv4i16_nxv4i16_nxv4i8( @llvm.riscv.vwadd.w.nxv4i16.nxv4i8( @@ -1916,8 +1916,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv8i16_nxv8i16_nxv8i8( @llvm.riscv.vwadd.w.nxv8i16.nxv8i8( @@ -1932,8 +1932,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv16i16_nxv16i16_nxv16i8 ; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vwadd.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwadd.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwadd.w.nxv16i16.nxv16i8( @@ -1964,8 +1964,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv1i32_nxv1i32_nxv1i16( @llvm.riscv.vwadd.w.nxv1i32.nxv1i16( @@ -1980,8 +1980,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv2i32_nxv2i32_nxv2i16( @llvm.riscv.vwadd.w.nxv2i32.nxv2i16( @@ -1996,8 +1996,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv4i32_nxv4i32_nxv4i16( @llvm.riscv.vwadd.w.nxv4i32.nxv4i16( @@ -2012,8 +2012,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv8i32_nxv8i32_nxv8i16( @llvm.riscv.vwadd.w.nxv8i32.nxv8i16( @@ -2028,8 +2028,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv1i64_nxv1i64_nxv1i32( @llvm.riscv.vwadd.w.nxv1i64.nxv1i32( @@ -2044,8 +2044,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv2i64_nxv2i64_nxv2i32( @llvm.riscv.vwadd.w.nxv2i64.nxv2i32( @@ -2060,8 +2060,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv4i64_nxv4i64_nxv4i32( @llvm.riscv.vwadd.w.nxv4i64.nxv4i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll index 916ee88c5cbba705df624e877588b734a0794a4c..9c383c2dfee965b72aac10bdd102132bc81a40da 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll @@ -257,9 +257,9 @@ declare @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4r.v v28, (a0) +; CHECK-NEXT: vl4r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8( @@ -483,9 +483,9 @@ declare @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16( @@ -664,9 +664,9 @@ declare @llvm.riscv.vwadd.w.mask.nxv8i64.nxv8i32( define @intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwadd.w.mask.nxv8i64.nxv8i32( @@ -1868,8 +1868,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv1i16_nxv1i16_nxv1i8( @llvm.riscv.vwadd.w.nxv1i16.nxv1i8( @@ -1884,8 +1884,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv2i16_nxv2i16_nxv2i8( @llvm.riscv.vwadd.w.nxv2i16.nxv2i8( @@ -1900,8 +1900,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv4i16_nxv4i16_nxv4i8( @llvm.riscv.vwadd.w.nxv4i16.nxv4i8( @@ -1916,8 +1916,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv8i16_nxv8i16_nxv8i8( @llvm.riscv.vwadd.w.nxv8i16.nxv8i8( @@ -1932,8 +1932,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv16i16_nxv16i16_nxv16i8 ; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vwadd.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwadd.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwadd.w.nxv16i16.nxv16i8( @@ -1964,8 +1964,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv1i32_nxv1i32_nxv1i16( @llvm.riscv.vwadd.w.nxv1i32.nxv1i16( @@ -1980,8 +1980,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv2i32_nxv2i32_nxv2i16( @llvm.riscv.vwadd.w.nxv2i32.nxv2i16( @@ -1996,8 +1996,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv4i32_nxv4i32_nxv4i16( @llvm.riscv.vwadd.w.nxv4i32.nxv4i16( @@ -2012,8 +2012,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv8i32_nxv8i32_nxv8i16( @llvm.riscv.vwadd.w.nxv8i32.nxv8i16( @@ -2028,8 +2028,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv1i64_nxv1i64_nxv1i32( @llvm.riscv.vwadd.w.nxv1i64.nxv1i32( @@ -2044,8 +2044,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv2i64_nxv2i64_nxv2i32( @llvm.riscv.vwadd.w.nxv2i64.nxv2i32( @@ -2060,8 +2060,8 @@ define @intrinsic_vwadd.w_wv_untie_nxv4i64_nxv4i64_nxv4i32( @llvm.riscv.vwadd.w.nxv4i64.nxv4i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll index 0480753c043c24b425b206f275800fbeee1f5402..e42ccf233604b418d480cf4f245fb7d5905f2651 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll @@ -10,8 +10,8 @@ define @intrinsic_vwaddu_vv_nxv1i16_nxv1i8_nxv1i8( @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vwaddu_vv_nxv2i16_nxv2i8_nxv2i8( @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vwaddu_vv_nxv4i16_nxv4i8_nxv4i8( @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vwaddu_vv_nxv8i16_nxv8i8_nxv8i8( @llvm.riscv.vwaddu.nxv8i16.nxv8i8.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vwaddu_vv_nxv16i16_nxv16i8_nxv16i8( @llvm.riscv.vwaddu.nxv16i16.nxv16i8.nxv16i8( @@ -286,8 +286,8 @@ define @intrinsic_vwaddu_vv_nxv1i32_nxv1i16_nxv1i16( @llvm.riscv.vwaddu.nxv1i32.nxv1i16.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vwaddu_vv_nxv2i32_nxv2i16_nxv2i16( @llvm.riscv.vwaddu.nxv2i32.nxv2i16.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vwaddu_vv_nxv4i32_nxv4i16_nxv4i16( @llvm.riscv.vwaddu.nxv4i32.nxv4i16.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vwaddu_vv_nxv8i32_nxv8i16_nxv8i16( @llvm.riscv.vwaddu.nxv8i32.nxv8i16.nxv8i16( @@ -516,8 +516,8 @@ define @intrinsic_vwaddu_vv_nxv1i64_nxv1i32_nxv1i32( @llvm.riscv.vwaddu.nxv1i64.nxv1i32.nxv1i32( @@ -562,8 +562,8 @@ define @intrinsic_vwaddu_vv_nxv2i64_nxv2i32_nxv2i32( @llvm.riscv.vwaddu.nxv2i64.nxv2i32.nxv2i32( @@ -608,8 +608,8 @@ define @intrinsic_vwaddu_vv_nxv4i64_nxv4i32_nxv4i32( @llvm.riscv.vwaddu.nxv4i64.nxv4i32.nxv4i32( @@ -700,8 +700,8 @@ define @intrinsic_vwaddu_vx_nxv1i16_nxv1i8_i8( @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8( @@ -746,8 +746,8 @@ define @intrinsic_vwaddu_vx_nxv2i16_nxv2i8_i8( @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8( @@ -792,8 +792,8 @@ define @intrinsic_vwaddu_vx_nxv4i16_nxv4i8_i8( @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8( @@ -838,8 +838,8 @@ define @intrinsic_vwaddu_vx_nxv8i16_nxv8i8_i8( @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8( @@ -884,8 +884,8 @@ define @intrinsic_vwaddu_vx_nxv16i16_nxv16i8_i8( @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8( @@ -976,8 +976,8 @@ define @intrinsic_vwaddu_vx_nxv1i32_nxv1i16_i16( @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16( @@ -1022,8 +1022,8 @@ define @intrinsic_vwaddu_vx_nxv2i32_nxv2i16_i16( @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16( @@ -1068,8 +1068,8 @@ define @intrinsic_vwaddu_vx_nxv4i32_nxv4i16_i16( @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16( @@ -1114,8 +1114,8 @@ define @intrinsic_vwaddu_vx_nxv8i32_nxv8i16_i16( @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16( @@ -1206,8 +1206,8 @@ define @intrinsic_vwaddu_vx_nxv1i64_nxv1i32_i32( @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32( @@ -1252,8 +1252,8 @@ define @intrinsic_vwaddu_vx_nxv2i64_nxv2i32_i32( @llvm.riscv.vwaddu.nxv2i64.nxv2i32.i32( @@ -1298,8 +1298,8 @@ define @intrinsic_vwaddu_vx_nxv4i64_nxv4i32_i32( @llvm.riscv.vwaddu.nxv4i64.nxv4i32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll index f63f3db025507d84b7fa3d56f0ee6302dc71817d..f9ad3eb2a24ab34616a5b7278727ffcddc72d4f0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll @@ -10,8 +10,8 @@ define @intrinsic_vwaddu_vv_nxv1i16_nxv1i8_nxv1i8( @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vwaddu_vv_nxv2i16_nxv2i8_nxv2i8( @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vwaddu_vv_nxv4i16_nxv4i8_nxv4i8( @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vwaddu_vv_nxv8i16_nxv8i8_nxv8i8( @llvm.riscv.vwaddu.nxv8i16.nxv8i8.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vwaddu_vv_nxv16i16_nxv16i8_nxv16i8( @llvm.riscv.vwaddu.nxv16i16.nxv16i8.nxv16i8( @@ -286,8 +286,8 @@ define @intrinsic_vwaddu_vv_nxv1i32_nxv1i16_nxv1i16( @llvm.riscv.vwaddu.nxv1i32.nxv1i16.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vwaddu_vv_nxv2i32_nxv2i16_nxv2i16( @llvm.riscv.vwaddu.nxv2i32.nxv2i16.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vwaddu_vv_nxv4i32_nxv4i16_nxv4i16( @llvm.riscv.vwaddu.nxv4i32.nxv4i16.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vwaddu_vv_nxv8i32_nxv8i16_nxv8i16( @llvm.riscv.vwaddu.nxv8i32.nxv8i16.nxv8i16( @@ -516,8 +516,8 @@ define @intrinsic_vwaddu_vv_nxv1i64_nxv1i32_nxv1i32( @llvm.riscv.vwaddu.nxv1i64.nxv1i32.nxv1i32( @@ -562,8 +562,8 @@ define @intrinsic_vwaddu_vv_nxv2i64_nxv2i32_nxv2i32( @llvm.riscv.vwaddu.nxv2i64.nxv2i32.nxv2i32( @@ -608,8 +608,8 @@ define @intrinsic_vwaddu_vv_nxv4i64_nxv4i32_nxv4i32( @llvm.riscv.vwaddu.nxv4i64.nxv4i32.nxv4i32( @@ -700,8 +700,8 @@ define @intrinsic_vwaddu_vx_nxv1i16_nxv1i8_i8( @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8( @@ -746,8 +746,8 @@ define @intrinsic_vwaddu_vx_nxv2i16_nxv2i8_i8( @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8( @@ -792,8 +792,8 @@ define @intrinsic_vwaddu_vx_nxv4i16_nxv4i8_i8( @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8( @@ -838,8 +838,8 @@ define @intrinsic_vwaddu_vx_nxv8i16_nxv8i8_i8( @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8( @@ -884,8 +884,8 @@ define @intrinsic_vwaddu_vx_nxv16i16_nxv16i8_i8( @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8( @@ -976,8 +976,8 @@ define @intrinsic_vwaddu_vx_nxv1i32_nxv1i16_i16( @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16( @@ -1022,8 +1022,8 @@ define @intrinsic_vwaddu_vx_nxv2i32_nxv2i16_i16( @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16( @@ -1068,8 +1068,8 @@ define @intrinsic_vwaddu_vx_nxv4i32_nxv4i16_i16( @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16( @@ -1114,8 +1114,8 @@ define @intrinsic_vwaddu_vx_nxv8i32_nxv8i16_i16( @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16( @@ -1206,8 +1206,8 @@ define @intrinsic_vwaddu_vx_nxv1i64_nxv1i32_i32( @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32( @@ -1252,8 +1252,8 @@ define @intrinsic_vwaddu_vx_nxv2i64_nxv2i32_i32( @llvm.riscv.vwaddu.nxv2i64.nxv2i32.i32( @@ -1298,8 +1298,8 @@ define @intrinsic_vwaddu_vx_nxv4i64_nxv4i32_i32( @llvm.riscv.vwaddu.nxv4i64.nxv4i32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll index d904716bce829b90845d7c3ec3cca9e0de677505..0ffeabaa38290566a91e70e17366eb6eede23557 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll @@ -257,9 +257,9 @@ declare @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4r.v v28, (a0) +; CHECK-NEXT: vl4r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwaddu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8( @@ -483,9 +483,9 @@ declare @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwaddu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16( @@ -664,9 +664,9 @@ declare @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32( define @intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwaddu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32( @@ -1868,8 +1868,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8( @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8( @@ -1884,8 +1884,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8( @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8( @@ -1900,8 +1900,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8( @llvm.riscv.vwaddu.w.nxv4i16.nxv4i8( @@ -1916,8 +1916,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8( @llvm.riscv.vwaddu.w.nxv8i16.nxv8i8( @@ -1932,8 +1932,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv16i16_nxv16i16_nxv16i ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vwaddu.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwaddu.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv16i16.nxv16i8( @@ -1964,8 +1964,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(< ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vwaddu.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vwaddu.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv1i32.nxv1i16( @@ -1980,8 +1980,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(< ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vwaddu.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vwaddu.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv2i32.nxv2i16( @@ -1996,8 +1996,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(< ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vwaddu.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vwaddu.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv4i32.nxv4i16( @@ -2012,8 +2012,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(< ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vwaddu.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwaddu.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv8i32.nxv8i16( @@ -2028,8 +2028,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(< ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vwaddu.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vwaddu.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv1i64.nxv1i32( @@ -2044,8 +2044,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(< ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vwaddu.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vwaddu.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv2i64.nxv2i32( @@ -2060,8 +2060,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(< ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vwaddu.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwaddu.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv4i64.nxv4i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll index 4a35416acf0c519a19bc07e7035dfefca661c984..044737e1e30076e21f1c431e60efdd270a26e282 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll @@ -257,9 +257,9 @@ declare @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4r.v v28, (a0) +; CHECK-NEXT: vl4r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwaddu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8( @@ -483,9 +483,9 @@ declare @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwaddu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16( @@ -664,9 +664,9 @@ declare @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32( define @intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwaddu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32( @@ -1868,8 +1868,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8( @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8( @@ -1884,8 +1884,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8( @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8( @@ -1900,8 +1900,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8( @llvm.riscv.vwaddu.w.nxv4i16.nxv4i8( @@ -1916,8 +1916,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8( @llvm.riscv.vwaddu.w.nxv8i16.nxv8i8( @@ -1932,8 +1932,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv16i16_nxv16i16_nxv16i ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vwaddu.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwaddu.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv16i16.nxv16i8( @@ -1964,8 +1964,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(< ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vwaddu.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vwaddu.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv1i32.nxv1i16( @@ -1980,8 +1980,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(< ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vwaddu.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vwaddu.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv2i32.nxv2i16( @@ -1996,8 +1996,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(< ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vwaddu.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vwaddu.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv4i32.nxv4i16( @@ -2012,8 +2012,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(< ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vwaddu.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwaddu.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv8i32.nxv8i16( @@ -2028,8 +2028,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(< ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vwaddu.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vwaddu.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv1i64.nxv1i32( @@ -2044,8 +2044,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(< ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vwaddu.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vwaddu.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv2i64.nxv2i32( @@ -2060,8 +2060,8 @@ define @intrinsic_vwaddu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(< ; CHECK-LABEL: intrinsic_vwaddu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vwaddu.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwaddu.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwaddu.w.nxv4i64.nxv4i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll index b04e2c0d171fc48967eadd4c1370421a0430c292..47ecba522f2fe13ab18d889d9b14256ae472a5af 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll @@ -10,8 +10,8 @@ define @intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8( @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8( @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8( @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8( @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8( @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8( @@ -286,8 +286,8 @@ define @intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16( @llvm.riscv.vwmul.nxv1i32.nxv1i16.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16( @llvm.riscv.vwmul.nxv2i32.nxv2i16.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16( @llvm.riscv.vwmul.nxv4i32.nxv4i16.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16( @llvm.riscv.vwmul.nxv8i32.nxv8i16.nxv8i16( @@ -516,8 +516,8 @@ define @intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32( @llvm.riscv.vwmul.nxv1i64.nxv1i32.nxv1i32( @@ -562,8 +562,8 @@ define @intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32( @llvm.riscv.vwmul.nxv2i64.nxv2i32.nxv2i32( @@ -608,8 +608,8 @@ define @intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32( @llvm.riscv.vwmul.nxv4i64.nxv4i32.nxv4i32( @@ -700,8 +700,8 @@ define @intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8( @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8( @@ -746,8 +746,8 @@ define @intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8( @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8( @@ -792,8 +792,8 @@ define @intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8( @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8( @@ -838,8 +838,8 @@ define @intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8( @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8( @@ -884,8 +884,8 @@ define @intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8( @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8( @@ -976,8 +976,8 @@ define @intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16( @llvm.riscv.vwmul.nxv1i32.nxv1i16.i16( @@ -1022,8 +1022,8 @@ define @intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16( @llvm.riscv.vwmul.nxv2i32.nxv2i16.i16( @@ -1068,8 +1068,8 @@ define @intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16( @llvm.riscv.vwmul.nxv4i32.nxv4i16.i16( @@ -1114,8 +1114,8 @@ define @intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16( @llvm.riscv.vwmul.nxv8i32.nxv8i16.i16( @@ -1206,8 +1206,8 @@ define @intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32( @llvm.riscv.vwmul.nxv1i64.nxv1i32.i32( @@ -1252,8 +1252,8 @@ define @intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32( @llvm.riscv.vwmul.nxv2i64.nxv2i32.i32( @@ -1298,8 +1298,8 @@ define @intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32( @llvm.riscv.vwmul.nxv4i64.nxv4i32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll index 0e8567dcfdc8acce4a34564e5a4da492a722ac68..05bdcf70f548067c751bc90399bcd34af290f9de 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll @@ -10,8 +10,8 @@ define @intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8( @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8( @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8( @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8( @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8( @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8( @@ -286,8 +286,8 @@ define @intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16( @llvm.riscv.vwmul.nxv1i32.nxv1i16.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16( @llvm.riscv.vwmul.nxv2i32.nxv2i16.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16( @llvm.riscv.vwmul.nxv4i32.nxv4i16.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16( @llvm.riscv.vwmul.nxv8i32.nxv8i16.nxv8i16( @@ -516,8 +516,8 @@ define @intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32( @llvm.riscv.vwmul.nxv1i64.nxv1i32.nxv1i32( @@ -562,8 +562,8 @@ define @intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32( @llvm.riscv.vwmul.nxv2i64.nxv2i32.nxv2i32( @@ -608,8 +608,8 @@ define @intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32( @llvm.riscv.vwmul.nxv4i64.nxv4i32.nxv4i32( @@ -700,8 +700,8 @@ define @intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8( @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8( @@ -746,8 +746,8 @@ define @intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8( @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8( @@ -792,8 +792,8 @@ define @intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8( @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8( @@ -838,8 +838,8 @@ define @intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8( @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8( @@ -884,8 +884,8 @@ define @intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8( @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8( @@ -976,8 +976,8 @@ define @intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16( @llvm.riscv.vwmul.nxv1i32.nxv1i16.i16( @@ -1022,8 +1022,8 @@ define @intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16( @llvm.riscv.vwmul.nxv2i32.nxv2i16.i16( @@ -1068,8 +1068,8 @@ define @intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16( @llvm.riscv.vwmul.nxv4i32.nxv4i16.i16( @@ -1114,8 +1114,8 @@ define @intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16( @llvm.riscv.vwmul.nxv8i32.nxv8i16.i16( @@ -1206,8 +1206,8 @@ define @intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32( @llvm.riscv.vwmul.nxv1i64.nxv1i32.i32( @@ -1252,8 +1252,8 @@ define @intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32( @llvm.riscv.vwmul.nxv2i64.nxv2i32.i32( @@ -1298,8 +1298,8 @@ define @intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32( @llvm.riscv.vwmul.nxv4i64.nxv4i32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll index b3cc2e7d13557ae104bc78e33aaf3d5016e3896a..0d91f668b792d7c41a3f3787d76a8dbe8b607c5b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll @@ -10,8 +10,8 @@ define @intrinsic_vwmulsu_vv_nxv1i16_nxv1i8_nxv1i8( @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vwmulsu_vv_nxv2i16_nxv2i8_nxv2i8( @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vwmulsu_vv_nxv4i16_nxv4i8_nxv4i8( @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vwmulsu_vv_nxv8i16_nxv8i8_nxv8i8( @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vwmulsu_vv_nxv16i16_nxv16i8_nxv16i8( @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8( @@ -286,8 +286,8 @@ define @intrinsic_vwmulsu_vv_nxv1i32_nxv1i16_nxv1i16( @llvm.riscv.vwmulsu.nxv1i32.nxv1i16.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vwmulsu_vv_nxv2i32_nxv2i16_nxv2i16( @llvm.riscv.vwmulsu.nxv2i32.nxv2i16.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vwmulsu_vv_nxv4i32_nxv4i16_nxv4i16( @llvm.riscv.vwmulsu.nxv4i32.nxv4i16.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vwmulsu_vv_nxv8i32_nxv8i16_nxv8i16( @llvm.riscv.vwmulsu.nxv8i32.nxv8i16.nxv8i16( @@ -516,8 +516,8 @@ define @intrinsic_vwmulsu_vv_nxv1i64_nxv1i32_nxv1i32( @llvm.riscv.vwmulsu.nxv1i64.nxv1i32.nxv1i32( @@ -562,8 +562,8 @@ define @intrinsic_vwmulsu_vv_nxv2i64_nxv2i32_nxv2i32( @llvm.riscv.vwmulsu.nxv2i64.nxv2i32.nxv2i32( @@ -608,8 +608,8 @@ define @intrinsic_vwmulsu_vv_nxv4i64_nxv4i32_nxv4i32( @llvm.riscv.vwmulsu.nxv4i64.nxv4i32.nxv4i32( @@ -700,8 +700,8 @@ define @intrinsic_vwmulsu_vx_nxv1i16_nxv1i8_i8( @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8( @@ -746,8 +746,8 @@ define @intrinsic_vwmulsu_vx_nxv2i16_nxv2i8_i8( @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8( @@ -792,8 +792,8 @@ define @intrinsic_vwmulsu_vx_nxv4i16_nxv4i8_i8( @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8( @@ -838,8 +838,8 @@ define @intrinsic_vwmulsu_vx_nxv8i16_nxv8i8_i8( @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8( @@ -884,8 +884,8 @@ define @intrinsic_vwmulsu_vx_nxv16i16_nxv16i8_i8( @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8( @@ -976,8 +976,8 @@ define @intrinsic_vwmulsu_vx_nxv1i32_nxv1i16_i16( @llvm.riscv.vwmulsu.nxv1i32.nxv1i16.i16( @@ -1022,8 +1022,8 @@ define @intrinsic_vwmulsu_vx_nxv2i32_nxv2i16_i16( @llvm.riscv.vwmulsu.nxv2i32.nxv2i16.i16( @@ -1068,8 +1068,8 @@ define @intrinsic_vwmulsu_vx_nxv4i32_nxv4i16_i16( @llvm.riscv.vwmulsu.nxv4i32.nxv4i16.i16( @@ -1114,8 +1114,8 @@ define @intrinsic_vwmulsu_vx_nxv8i32_nxv8i16_i16( @llvm.riscv.vwmulsu.nxv8i32.nxv8i16.i16( @@ -1206,8 +1206,8 @@ define @intrinsic_vwmulsu_vx_nxv1i64_nxv1i32_i32( @llvm.riscv.vwmulsu.nxv1i64.nxv1i32.i32( @@ -1252,8 +1252,8 @@ define @intrinsic_vwmulsu_vx_nxv2i64_nxv2i32_i32( @llvm.riscv.vwmulsu.nxv2i64.nxv2i32.i32( @@ -1298,8 +1298,8 @@ define @intrinsic_vwmulsu_vx_nxv4i64_nxv4i32_i32( @llvm.riscv.vwmulsu.nxv4i64.nxv4i32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll index d121b66424af77b6305a4b29ae38ce167edcebb3..4ac17a317522a37e2b96fed5f8674fe569c3f557 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll @@ -10,8 +10,8 @@ define @intrinsic_vwmulsu_vv_nxv1i16_nxv1i8_nxv1i8( @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vwmulsu_vv_nxv2i16_nxv2i8_nxv2i8( @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vwmulsu_vv_nxv4i16_nxv4i8_nxv4i8( @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vwmulsu_vv_nxv8i16_nxv8i8_nxv8i8( @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vwmulsu_vv_nxv16i16_nxv16i8_nxv16i8( @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8( @@ -286,8 +286,8 @@ define @intrinsic_vwmulsu_vv_nxv1i32_nxv1i16_nxv1i16( @llvm.riscv.vwmulsu.nxv1i32.nxv1i16.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vwmulsu_vv_nxv2i32_nxv2i16_nxv2i16( @llvm.riscv.vwmulsu.nxv2i32.nxv2i16.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vwmulsu_vv_nxv4i32_nxv4i16_nxv4i16( @llvm.riscv.vwmulsu.nxv4i32.nxv4i16.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vwmulsu_vv_nxv8i32_nxv8i16_nxv8i16( @llvm.riscv.vwmulsu.nxv8i32.nxv8i16.nxv8i16( @@ -516,8 +516,8 @@ define @intrinsic_vwmulsu_vv_nxv1i64_nxv1i32_nxv1i32( @llvm.riscv.vwmulsu.nxv1i64.nxv1i32.nxv1i32( @@ -562,8 +562,8 @@ define @intrinsic_vwmulsu_vv_nxv2i64_nxv2i32_nxv2i32( @llvm.riscv.vwmulsu.nxv2i64.nxv2i32.nxv2i32( @@ -608,8 +608,8 @@ define @intrinsic_vwmulsu_vv_nxv4i64_nxv4i32_nxv4i32( @llvm.riscv.vwmulsu.nxv4i64.nxv4i32.nxv4i32( @@ -700,8 +700,8 @@ define @intrinsic_vwmulsu_vx_nxv1i16_nxv1i8_i8( @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8( @@ -746,8 +746,8 @@ define @intrinsic_vwmulsu_vx_nxv2i16_nxv2i8_i8( @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8( @@ -792,8 +792,8 @@ define @intrinsic_vwmulsu_vx_nxv4i16_nxv4i8_i8( @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8( @@ -838,8 +838,8 @@ define @intrinsic_vwmulsu_vx_nxv8i16_nxv8i8_i8( @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8( @@ -884,8 +884,8 @@ define @intrinsic_vwmulsu_vx_nxv16i16_nxv16i8_i8( @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8( @@ -976,8 +976,8 @@ define @intrinsic_vwmulsu_vx_nxv1i32_nxv1i16_i16( @llvm.riscv.vwmulsu.nxv1i32.nxv1i16.i16( @@ -1022,8 +1022,8 @@ define @intrinsic_vwmulsu_vx_nxv2i32_nxv2i16_i16( @llvm.riscv.vwmulsu.nxv2i32.nxv2i16.i16( @@ -1068,8 +1068,8 @@ define @intrinsic_vwmulsu_vx_nxv4i32_nxv4i16_i16( @llvm.riscv.vwmulsu.nxv4i32.nxv4i16.i16( @@ -1114,8 +1114,8 @@ define @intrinsic_vwmulsu_vx_nxv8i32_nxv8i16_i16( @llvm.riscv.vwmulsu.nxv8i32.nxv8i16.i16( @@ -1206,8 +1206,8 @@ define @intrinsic_vwmulsu_vx_nxv1i64_nxv1i32_i32( @llvm.riscv.vwmulsu.nxv1i64.nxv1i32.i32( @@ -1252,8 +1252,8 @@ define @intrinsic_vwmulsu_vx_nxv2i64_nxv2i32_i32( @llvm.riscv.vwmulsu.nxv2i64.nxv2i32.i32( @@ -1298,8 +1298,8 @@ define @intrinsic_vwmulsu_vx_nxv4i64_nxv4i32_i32( @llvm.riscv.vwmulsu.nxv4i64.nxv4i32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll index f2ee2f583ff397163690935428fa5215182346fe..9f46f19b99386832a71df85ba414feccaa896c2f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll @@ -10,8 +10,8 @@ define @intrinsic_vwmulu_vv_nxv1i16_nxv1i8_nxv1i8( @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vwmulu_vv_nxv2i16_nxv2i8_nxv2i8( @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vwmulu_vv_nxv4i16_nxv4i8_nxv4i8( @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vwmulu_vv_nxv8i16_nxv8i8_nxv8i8( @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vwmulu_vv_nxv16i16_nxv16i8_nxv16i8( @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8( @@ -286,8 +286,8 @@ define @intrinsic_vwmulu_vv_nxv1i32_nxv1i16_nxv1i16( @llvm.riscv.vwmulu.nxv1i32.nxv1i16.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vwmulu_vv_nxv2i32_nxv2i16_nxv2i16( @llvm.riscv.vwmulu.nxv2i32.nxv2i16.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vwmulu_vv_nxv4i32_nxv4i16_nxv4i16( @llvm.riscv.vwmulu.nxv4i32.nxv4i16.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vwmulu_vv_nxv8i32_nxv8i16_nxv8i16( @llvm.riscv.vwmulu.nxv8i32.nxv8i16.nxv8i16( @@ -516,8 +516,8 @@ define @intrinsic_vwmulu_vv_nxv1i64_nxv1i32_nxv1i32( @llvm.riscv.vwmulu.nxv1i64.nxv1i32.nxv1i32( @@ -562,8 +562,8 @@ define @intrinsic_vwmulu_vv_nxv2i64_nxv2i32_nxv2i32( @llvm.riscv.vwmulu.nxv2i64.nxv2i32.nxv2i32( @@ -608,8 +608,8 @@ define @intrinsic_vwmulu_vv_nxv4i64_nxv4i32_nxv4i32( @llvm.riscv.vwmulu.nxv4i64.nxv4i32.nxv4i32( @@ -700,8 +700,8 @@ define @intrinsic_vwmulu_vx_nxv1i16_nxv1i8_i8( @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8( @@ -746,8 +746,8 @@ define @intrinsic_vwmulu_vx_nxv2i16_nxv2i8_i8( @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8( @@ -792,8 +792,8 @@ define @intrinsic_vwmulu_vx_nxv4i16_nxv4i8_i8( @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8( @@ -838,8 +838,8 @@ define @intrinsic_vwmulu_vx_nxv8i16_nxv8i8_i8( @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8( @@ -884,8 +884,8 @@ define @intrinsic_vwmulu_vx_nxv16i16_nxv16i8_i8( @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8( @@ -976,8 +976,8 @@ define @intrinsic_vwmulu_vx_nxv1i32_nxv1i16_i16( @llvm.riscv.vwmulu.nxv1i32.nxv1i16.i16( @@ -1022,8 +1022,8 @@ define @intrinsic_vwmulu_vx_nxv2i32_nxv2i16_i16( @llvm.riscv.vwmulu.nxv2i32.nxv2i16.i16( @@ -1068,8 +1068,8 @@ define @intrinsic_vwmulu_vx_nxv4i32_nxv4i16_i16( @llvm.riscv.vwmulu.nxv4i32.nxv4i16.i16( @@ -1114,8 +1114,8 @@ define @intrinsic_vwmulu_vx_nxv8i32_nxv8i16_i16( @llvm.riscv.vwmulu.nxv8i32.nxv8i16.i16( @@ -1206,8 +1206,8 @@ define @intrinsic_vwmulu_vx_nxv1i64_nxv1i32_i32( @llvm.riscv.vwmulu.nxv1i64.nxv1i32.i32( @@ -1252,8 +1252,8 @@ define @intrinsic_vwmulu_vx_nxv2i64_nxv2i32_i32( @llvm.riscv.vwmulu.nxv2i64.nxv2i32.i32( @@ -1298,8 +1298,8 @@ define @intrinsic_vwmulu_vx_nxv4i64_nxv4i32_i32( @llvm.riscv.vwmulu.nxv4i64.nxv4i32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll index ba274eed8e3895ba28103c181251516a5b05954d..99a0d2183133a6462c9adc204c3717aaadb0bdd0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll @@ -10,8 +10,8 @@ define @intrinsic_vwmulu_vv_nxv1i16_nxv1i8_nxv1i8( @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vwmulu_vv_nxv2i16_nxv2i8_nxv2i8( @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vwmulu_vv_nxv4i16_nxv4i8_nxv4i8( @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vwmulu_vv_nxv8i16_nxv8i8_nxv8i8( @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vwmulu_vv_nxv16i16_nxv16i8_nxv16i8( @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8( @@ -286,8 +286,8 @@ define @intrinsic_vwmulu_vv_nxv1i32_nxv1i16_nxv1i16( @llvm.riscv.vwmulu.nxv1i32.nxv1i16.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vwmulu_vv_nxv2i32_nxv2i16_nxv2i16( @llvm.riscv.vwmulu.nxv2i32.nxv2i16.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vwmulu_vv_nxv4i32_nxv4i16_nxv4i16( @llvm.riscv.vwmulu.nxv4i32.nxv4i16.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vwmulu_vv_nxv8i32_nxv8i16_nxv8i16( @llvm.riscv.vwmulu.nxv8i32.nxv8i16.nxv8i16( @@ -516,8 +516,8 @@ define @intrinsic_vwmulu_vv_nxv1i64_nxv1i32_nxv1i32( @llvm.riscv.vwmulu.nxv1i64.nxv1i32.nxv1i32( @@ -562,8 +562,8 @@ define @intrinsic_vwmulu_vv_nxv2i64_nxv2i32_nxv2i32( @llvm.riscv.vwmulu.nxv2i64.nxv2i32.nxv2i32( @@ -608,8 +608,8 @@ define @intrinsic_vwmulu_vv_nxv4i64_nxv4i32_nxv4i32( @llvm.riscv.vwmulu.nxv4i64.nxv4i32.nxv4i32( @@ -700,8 +700,8 @@ define @intrinsic_vwmulu_vx_nxv1i16_nxv1i8_i8( @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8( @@ -746,8 +746,8 @@ define @intrinsic_vwmulu_vx_nxv2i16_nxv2i8_i8( @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8( @@ -792,8 +792,8 @@ define @intrinsic_vwmulu_vx_nxv4i16_nxv4i8_i8( @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8( @@ -838,8 +838,8 @@ define @intrinsic_vwmulu_vx_nxv8i16_nxv8i8_i8( @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8( @@ -884,8 +884,8 @@ define @intrinsic_vwmulu_vx_nxv16i16_nxv16i8_i8( @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8( @@ -976,8 +976,8 @@ define @intrinsic_vwmulu_vx_nxv1i32_nxv1i16_i16( @llvm.riscv.vwmulu.nxv1i32.nxv1i16.i16( @@ -1022,8 +1022,8 @@ define @intrinsic_vwmulu_vx_nxv2i32_nxv2i16_i16( @llvm.riscv.vwmulu.nxv2i32.nxv2i16.i16( @@ -1068,8 +1068,8 @@ define @intrinsic_vwmulu_vx_nxv4i32_nxv4i16_i16( @llvm.riscv.vwmulu.nxv4i32.nxv4i16.i16( @@ -1114,8 +1114,8 @@ define @intrinsic_vwmulu_vx_nxv8i32_nxv8i16_i16( @llvm.riscv.vwmulu.nxv8i32.nxv8i16.i16( @@ -1206,8 +1206,8 @@ define @intrinsic_vwmulu_vx_nxv1i64_nxv1i32_i32( @llvm.riscv.vwmulu.nxv1i64.nxv1i32.i32( @@ -1252,8 +1252,8 @@ define @intrinsic_vwmulu_vx_nxv2i64_nxv2i32_i32( @llvm.riscv.vwmulu.nxv2i64.nxv2i32.i32( @@ -1298,8 +1298,8 @@ define @intrinsic_vwmulu_vx_nxv4i64_nxv4i32_i32( @llvm.riscv.vwmulu.nxv4i64.nxv4i32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll index 9dd180c412f5d1a769021c0b91df96a909b98bfd..82b59dc788f5a95842b128617a343eab9ee44fec 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll @@ -10,8 +10,8 @@ define @intrinsic_vwsub_vv_nxv1i16_nxv1i8_nxv1i8( @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vwsub_vv_nxv2i16_nxv2i8_nxv2i8( @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vwsub_vv_nxv4i16_nxv4i8_nxv4i8( @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vwsub_vv_nxv8i16_nxv8i8_nxv8i8( @llvm.riscv.vwsub.nxv8i16.nxv8i8.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vwsub_vv_nxv16i16_nxv16i8_nxv16i8( @llvm.riscv.vwsub.nxv16i16.nxv16i8.nxv16i8( @@ -286,8 +286,8 @@ define @intrinsic_vwsub_vv_nxv1i32_nxv1i16_nxv1i16( @llvm.riscv.vwsub.nxv1i32.nxv1i16.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vwsub_vv_nxv2i32_nxv2i16_nxv2i16( @llvm.riscv.vwsub.nxv2i32.nxv2i16.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vwsub_vv_nxv4i32_nxv4i16_nxv4i16( @llvm.riscv.vwsub.nxv4i32.nxv4i16.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vwsub_vv_nxv8i32_nxv8i16_nxv8i16( @llvm.riscv.vwsub.nxv8i32.nxv8i16.nxv8i16( @@ -516,8 +516,8 @@ define @intrinsic_vwsub_vv_nxv1i64_nxv1i32_nxv1i32( @llvm.riscv.vwsub.nxv1i64.nxv1i32.nxv1i32( @@ -562,8 +562,8 @@ define @intrinsic_vwsub_vv_nxv2i64_nxv2i32_nxv2i32( @llvm.riscv.vwsub.nxv2i64.nxv2i32.nxv2i32( @@ -608,8 +608,8 @@ define @intrinsic_vwsub_vv_nxv4i64_nxv4i32_nxv4i32( @llvm.riscv.vwsub.nxv4i64.nxv4i32.nxv4i32( @@ -700,8 +700,8 @@ define @intrinsic_vwsub_vx_nxv1i16_nxv1i8_i8( @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8( @@ -746,8 +746,8 @@ define @intrinsic_vwsub_vx_nxv2i16_nxv2i8_i8( @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8( @@ -792,8 +792,8 @@ define @intrinsic_vwsub_vx_nxv4i16_nxv4i8_i8( @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8( @@ -838,8 +838,8 @@ define @intrinsic_vwsub_vx_nxv8i16_nxv8i8_i8( @llvm.riscv.vwsub.nxv8i16.nxv8i8.i8( @@ -884,8 +884,8 @@ define @intrinsic_vwsub_vx_nxv16i16_nxv16i8_i8( @llvm.riscv.vwsub.nxv16i16.nxv16i8.i8( @@ -976,8 +976,8 @@ define @intrinsic_vwsub_vx_nxv1i32_nxv1i16_i16( @llvm.riscv.vwsub.nxv1i32.nxv1i16.i16( @@ -1022,8 +1022,8 @@ define @intrinsic_vwsub_vx_nxv2i32_nxv2i16_i16( @llvm.riscv.vwsub.nxv2i32.nxv2i16.i16( @@ -1068,8 +1068,8 @@ define @intrinsic_vwsub_vx_nxv4i32_nxv4i16_i16( @llvm.riscv.vwsub.nxv4i32.nxv4i16.i16( @@ -1114,8 +1114,8 @@ define @intrinsic_vwsub_vx_nxv8i32_nxv8i16_i16( @llvm.riscv.vwsub.nxv8i32.nxv8i16.i16( @@ -1206,8 +1206,8 @@ define @intrinsic_vwsub_vx_nxv1i64_nxv1i32_i32( @llvm.riscv.vwsub.nxv1i64.nxv1i32.i32( @@ -1252,8 +1252,8 @@ define @intrinsic_vwsub_vx_nxv2i64_nxv2i32_i32( @llvm.riscv.vwsub.nxv2i64.nxv2i32.i32( @@ -1298,8 +1298,8 @@ define @intrinsic_vwsub_vx_nxv4i64_nxv4i32_i32( @llvm.riscv.vwsub.nxv4i64.nxv4i32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll index 904e8ee4cae14d1dfbd48643c64ff8d896f93dea..9aac53ae44b5cebd061b33671701aaeef21e4f29 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll @@ -10,8 +10,8 @@ define @intrinsic_vwsub_vv_nxv1i16_nxv1i8_nxv1i8( @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vwsub_vv_nxv2i16_nxv2i8_nxv2i8( @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vwsub_vv_nxv4i16_nxv4i8_nxv4i8( @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vwsub_vv_nxv8i16_nxv8i8_nxv8i8( @llvm.riscv.vwsub.nxv8i16.nxv8i8.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vwsub_vv_nxv16i16_nxv16i8_nxv16i8( @llvm.riscv.vwsub.nxv16i16.nxv16i8.nxv16i8( @@ -286,8 +286,8 @@ define @intrinsic_vwsub_vv_nxv1i32_nxv1i16_nxv1i16( @llvm.riscv.vwsub.nxv1i32.nxv1i16.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vwsub_vv_nxv2i32_nxv2i16_nxv2i16( @llvm.riscv.vwsub.nxv2i32.nxv2i16.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vwsub_vv_nxv4i32_nxv4i16_nxv4i16( @llvm.riscv.vwsub.nxv4i32.nxv4i16.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vwsub_vv_nxv8i32_nxv8i16_nxv8i16( @llvm.riscv.vwsub.nxv8i32.nxv8i16.nxv8i16( @@ -516,8 +516,8 @@ define @intrinsic_vwsub_vv_nxv1i64_nxv1i32_nxv1i32( @llvm.riscv.vwsub.nxv1i64.nxv1i32.nxv1i32( @@ -562,8 +562,8 @@ define @intrinsic_vwsub_vv_nxv2i64_nxv2i32_nxv2i32( @llvm.riscv.vwsub.nxv2i64.nxv2i32.nxv2i32( @@ -608,8 +608,8 @@ define @intrinsic_vwsub_vv_nxv4i64_nxv4i32_nxv4i32( @llvm.riscv.vwsub.nxv4i64.nxv4i32.nxv4i32( @@ -700,8 +700,8 @@ define @intrinsic_vwsub_vx_nxv1i16_nxv1i8_i8( @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8( @@ -746,8 +746,8 @@ define @intrinsic_vwsub_vx_nxv2i16_nxv2i8_i8( @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8( @@ -792,8 +792,8 @@ define @intrinsic_vwsub_vx_nxv4i16_nxv4i8_i8( @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8( @@ -838,8 +838,8 @@ define @intrinsic_vwsub_vx_nxv8i16_nxv8i8_i8( @llvm.riscv.vwsub.nxv8i16.nxv8i8.i8( @@ -884,8 +884,8 @@ define @intrinsic_vwsub_vx_nxv16i16_nxv16i8_i8( @llvm.riscv.vwsub.nxv16i16.nxv16i8.i8( @@ -976,8 +976,8 @@ define @intrinsic_vwsub_vx_nxv1i32_nxv1i16_i16( @llvm.riscv.vwsub.nxv1i32.nxv1i16.i16( @@ -1022,8 +1022,8 @@ define @intrinsic_vwsub_vx_nxv2i32_nxv2i16_i16( @llvm.riscv.vwsub.nxv2i32.nxv2i16.i16( @@ -1068,8 +1068,8 @@ define @intrinsic_vwsub_vx_nxv4i32_nxv4i16_i16( @llvm.riscv.vwsub.nxv4i32.nxv4i16.i16( @@ -1114,8 +1114,8 @@ define @intrinsic_vwsub_vx_nxv8i32_nxv8i16_i16( @llvm.riscv.vwsub.nxv8i32.nxv8i16.i16( @@ -1206,8 +1206,8 @@ define @intrinsic_vwsub_vx_nxv1i64_nxv1i32_i32( @llvm.riscv.vwsub.nxv1i64.nxv1i32.i32( @@ -1252,8 +1252,8 @@ define @intrinsic_vwsub_vx_nxv2i64_nxv2i32_i32( @llvm.riscv.vwsub.nxv2i64.nxv2i32.i32( @@ -1298,8 +1298,8 @@ define @intrinsic_vwsub_vx_nxv4i64_nxv4i32_i32( @llvm.riscv.vwsub.nxv4i64.nxv4i32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll index 3ee54535f7f335172ff1cf7045d8f4c8414f886b..42c6411fa4d65d86e113621d31549ea5df83dfe4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll @@ -257,9 +257,9 @@ declare @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4r.v v28, (a0) +; CHECK-NEXT: vl4r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8( @@ -483,9 +483,9 @@ declare @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16( @@ -664,9 +664,9 @@ declare @llvm.riscv.vwsub.w.mask.nxv8i64.nxv8i32( define @intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsub.w.mask.nxv8i64.nxv8i32( @@ -1868,8 +1868,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv1i16_nxv1i16_nxv1i8( @llvm.riscv.vwsub.w.nxv1i16.nxv1i8( @@ -1884,8 +1884,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv2i16_nxv2i16_nxv2i8( @llvm.riscv.vwsub.w.nxv2i16.nxv2i8( @@ -1900,8 +1900,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv4i16_nxv4i16_nxv4i8( @llvm.riscv.vwsub.w.nxv4i16.nxv4i8( @@ -1916,8 +1916,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv8i16_nxv8i16_nxv8i8( @llvm.riscv.vwsub.w.nxv8i16.nxv8i8( @@ -1932,8 +1932,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv16i16_nxv16i16_nxv16i8 ; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vwsub.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwsub.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsub.w.nxv16i16.nxv16i8( @@ -1964,8 +1964,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv1i32_nxv1i32_nxv1i16( @llvm.riscv.vwsub.w.nxv1i32.nxv1i16( @@ -1980,8 +1980,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv2i32_nxv2i32_nxv2i16( @llvm.riscv.vwsub.w.nxv2i32.nxv2i16( @@ -1996,8 +1996,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv4i32_nxv4i32_nxv4i16( @llvm.riscv.vwsub.w.nxv4i32.nxv4i16( @@ -2012,8 +2012,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv8i32_nxv8i32_nxv8i16( @llvm.riscv.vwsub.w.nxv8i32.nxv8i16( @@ -2028,8 +2028,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv1i64_nxv1i64_nxv1i32( @llvm.riscv.vwsub.w.nxv1i64.nxv1i32( @@ -2044,8 +2044,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv2i64_nxv2i64_nxv2i32( @llvm.riscv.vwsub.w.nxv2i64.nxv2i32( @@ -2060,8 +2060,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv4i64_nxv4i64_nxv4i32( @llvm.riscv.vwsub.w.nxv4i64.nxv4i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll index 5ef9b77be484bf7d341438ba5f6d7b0273abf44a..1257f5a546307b6baa8e0007506880f2304c7934 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll @@ -257,9 +257,9 @@ declare @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4r.v v28, (a0) +; CHECK-NEXT: vl4r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8( @@ -483,9 +483,9 @@ declare @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16( @@ -664,9 +664,9 @@ declare @llvm.riscv.vwsub.w.mask.nxv8i64.nxv8i32( define @intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsub.w.mask.nxv8i64.nxv8i32( @@ -1868,8 +1868,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv1i16_nxv1i16_nxv1i8( @llvm.riscv.vwsub.w.nxv1i16.nxv1i8( @@ -1884,8 +1884,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv2i16_nxv2i16_nxv2i8( @llvm.riscv.vwsub.w.nxv2i16.nxv2i8( @@ -1900,8 +1900,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv4i16_nxv4i16_nxv4i8( @llvm.riscv.vwsub.w.nxv4i16.nxv4i8( @@ -1916,8 +1916,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv8i16_nxv8i16_nxv8i8( @llvm.riscv.vwsub.w.nxv8i16.nxv8i8( @@ -1932,8 +1932,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv16i16_nxv16i16_nxv16i8 ; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vwsub.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwsub.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsub.w.nxv16i16.nxv16i8( @@ -1964,8 +1964,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv1i32_nxv1i32_nxv1i16( @llvm.riscv.vwsub.w.nxv1i32.nxv1i16( @@ -1980,8 +1980,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv2i32_nxv2i32_nxv2i16( @llvm.riscv.vwsub.w.nxv2i32.nxv2i16( @@ -1996,8 +1996,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv4i32_nxv4i32_nxv4i16( @llvm.riscv.vwsub.w.nxv4i32.nxv4i16( @@ -2012,8 +2012,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv8i32_nxv8i32_nxv8i16( @llvm.riscv.vwsub.w.nxv8i32.nxv8i16( @@ -2028,8 +2028,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv1i64_nxv1i64_nxv1i32( @llvm.riscv.vwsub.w.nxv1i64.nxv1i32( @@ -2044,8 +2044,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv2i64_nxv2i64_nxv2i32( @llvm.riscv.vwsub.w.nxv2i64.nxv2i32( @@ -2060,8 +2060,8 @@ define @intrinsic_vwsub.w_wv_untie_nxv4i64_nxv4i64_nxv4i32( @llvm.riscv.vwsub.w.nxv4i64.nxv4i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll index 1292599d6ea74ad0ee9c96d9f9b1c85e610efd5e..acee77f9bbd01b4ad178af14b71a658a59a173f8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll @@ -10,8 +10,8 @@ define @intrinsic_vwsubu_vv_nxv1i16_nxv1i8_nxv1i8( @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vwsubu_vv_nxv2i16_nxv2i8_nxv2i8( @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vwsubu_vv_nxv4i16_nxv4i8_nxv4i8( @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vwsubu_vv_nxv8i16_nxv8i8_nxv8i8( @llvm.riscv.vwsubu.nxv8i16.nxv8i8.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vwsubu_vv_nxv16i16_nxv16i8_nxv16i8( @llvm.riscv.vwsubu.nxv16i16.nxv16i8.nxv16i8( @@ -286,8 +286,8 @@ define @intrinsic_vwsubu_vv_nxv1i32_nxv1i16_nxv1i16( @llvm.riscv.vwsubu.nxv1i32.nxv1i16.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vwsubu_vv_nxv2i32_nxv2i16_nxv2i16( @llvm.riscv.vwsubu.nxv2i32.nxv2i16.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vwsubu_vv_nxv4i32_nxv4i16_nxv4i16( @llvm.riscv.vwsubu.nxv4i32.nxv4i16.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vwsubu_vv_nxv8i32_nxv8i16_nxv8i16( @llvm.riscv.vwsubu.nxv8i32.nxv8i16.nxv8i16( @@ -516,8 +516,8 @@ define @intrinsic_vwsubu_vv_nxv1i64_nxv1i32_nxv1i32( @llvm.riscv.vwsubu.nxv1i64.nxv1i32.nxv1i32( @@ -562,8 +562,8 @@ define @intrinsic_vwsubu_vv_nxv2i64_nxv2i32_nxv2i32( @llvm.riscv.vwsubu.nxv2i64.nxv2i32.nxv2i32( @@ -608,8 +608,8 @@ define @intrinsic_vwsubu_vv_nxv4i64_nxv4i32_nxv4i32( @llvm.riscv.vwsubu.nxv4i64.nxv4i32.nxv4i32( @@ -700,8 +700,8 @@ define @intrinsic_vwsubu_vx_nxv1i16_nxv1i8_i8( @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8( @@ -746,8 +746,8 @@ define @intrinsic_vwsubu_vx_nxv2i16_nxv2i8_i8( @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8( @@ -792,8 +792,8 @@ define @intrinsic_vwsubu_vx_nxv4i16_nxv4i8_i8( @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8( @@ -838,8 +838,8 @@ define @intrinsic_vwsubu_vx_nxv8i16_nxv8i8_i8( @llvm.riscv.vwsubu.nxv8i16.nxv8i8.i8( @@ -884,8 +884,8 @@ define @intrinsic_vwsubu_vx_nxv16i16_nxv16i8_i8( @llvm.riscv.vwsubu.nxv16i16.nxv16i8.i8( @@ -976,8 +976,8 @@ define @intrinsic_vwsubu_vx_nxv1i32_nxv1i16_i16( @llvm.riscv.vwsubu.nxv1i32.nxv1i16.i16( @@ -1022,8 +1022,8 @@ define @intrinsic_vwsubu_vx_nxv2i32_nxv2i16_i16( @llvm.riscv.vwsubu.nxv2i32.nxv2i16.i16( @@ -1068,8 +1068,8 @@ define @intrinsic_vwsubu_vx_nxv4i32_nxv4i16_i16( @llvm.riscv.vwsubu.nxv4i32.nxv4i16.i16( @@ -1114,8 +1114,8 @@ define @intrinsic_vwsubu_vx_nxv8i32_nxv8i16_i16( @llvm.riscv.vwsubu.nxv8i32.nxv8i16.i16( @@ -1206,8 +1206,8 @@ define @intrinsic_vwsubu_vx_nxv1i64_nxv1i32_i32( @llvm.riscv.vwsubu.nxv1i64.nxv1i32.i32( @@ -1252,8 +1252,8 @@ define @intrinsic_vwsubu_vx_nxv2i64_nxv2i32_i32( @llvm.riscv.vwsubu.nxv2i64.nxv2i32.i32( @@ -1298,8 +1298,8 @@ define @intrinsic_vwsubu_vx_nxv4i64_nxv4i32_i32( @llvm.riscv.vwsubu.nxv4i64.nxv4i32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll index 40d197de57b56ce563d991f94f64ff67912e5c67..65a7c23e6225cdb3171fe7ad6900c0f1607e0d45 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll @@ -10,8 +10,8 @@ define @intrinsic_vwsubu_vv_nxv1i16_nxv1i8_nxv1i8( @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8( @@ -56,8 +56,8 @@ define @intrinsic_vwsubu_vv_nxv2i16_nxv2i8_nxv2i8( @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8( @@ -102,8 +102,8 @@ define @intrinsic_vwsubu_vv_nxv4i16_nxv4i8_nxv4i8( @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8( @@ -148,8 +148,8 @@ define @intrinsic_vwsubu_vv_nxv8i16_nxv8i8_nxv8i8( @llvm.riscv.vwsubu.nxv8i16.nxv8i8.nxv8i8( @@ -194,8 +194,8 @@ define @intrinsic_vwsubu_vv_nxv16i16_nxv16i8_nxv16i8( @llvm.riscv.vwsubu.nxv16i16.nxv16i8.nxv16i8( @@ -286,8 +286,8 @@ define @intrinsic_vwsubu_vv_nxv1i32_nxv1i16_nxv1i16( @llvm.riscv.vwsubu.nxv1i32.nxv1i16.nxv1i16( @@ -332,8 +332,8 @@ define @intrinsic_vwsubu_vv_nxv2i32_nxv2i16_nxv2i16( @llvm.riscv.vwsubu.nxv2i32.nxv2i16.nxv2i16( @@ -378,8 +378,8 @@ define @intrinsic_vwsubu_vv_nxv4i32_nxv4i16_nxv4i16( @llvm.riscv.vwsubu.nxv4i32.nxv4i16.nxv4i16( @@ -424,8 +424,8 @@ define @intrinsic_vwsubu_vv_nxv8i32_nxv8i16_nxv8i16( @llvm.riscv.vwsubu.nxv8i32.nxv8i16.nxv8i16( @@ -516,8 +516,8 @@ define @intrinsic_vwsubu_vv_nxv1i64_nxv1i32_nxv1i32( @llvm.riscv.vwsubu.nxv1i64.nxv1i32.nxv1i32( @@ -562,8 +562,8 @@ define @intrinsic_vwsubu_vv_nxv2i64_nxv2i32_nxv2i32( @llvm.riscv.vwsubu.nxv2i64.nxv2i32.nxv2i32( @@ -608,8 +608,8 @@ define @intrinsic_vwsubu_vv_nxv4i64_nxv4i32_nxv4i32( @llvm.riscv.vwsubu.nxv4i64.nxv4i32.nxv4i32( @@ -700,8 +700,8 @@ define @intrinsic_vwsubu_vx_nxv1i16_nxv1i8_i8( @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8( @@ -746,8 +746,8 @@ define @intrinsic_vwsubu_vx_nxv2i16_nxv2i8_i8( @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8( @@ -792,8 +792,8 @@ define @intrinsic_vwsubu_vx_nxv4i16_nxv4i8_i8( @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8( @@ -838,8 +838,8 @@ define @intrinsic_vwsubu_vx_nxv8i16_nxv8i8_i8( @llvm.riscv.vwsubu.nxv8i16.nxv8i8.i8( @@ -884,8 +884,8 @@ define @intrinsic_vwsubu_vx_nxv16i16_nxv16i8_i8( @llvm.riscv.vwsubu.nxv16i16.nxv16i8.i8( @@ -976,8 +976,8 @@ define @intrinsic_vwsubu_vx_nxv1i32_nxv1i16_i16( @llvm.riscv.vwsubu.nxv1i32.nxv1i16.i16( @@ -1022,8 +1022,8 @@ define @intrinsic_vwsubu_vx_nxv2i32_nxv2i16_i16( @llvm.riscv.vwsubu.nxv2i32.nxv2i16.i16( @@ -1068,8 +1068,8 @@ define @intrinsic_vwsubu_vx_nxv4i32_nxv4i16_i16( @llvm.riscv.vwsubu.nxv4i32.nxv4i16.i16( @@ -1114,8 +1114,8 @@ define @intrinsic_vwsubu_vx_nxv8i32_nxv8i16_i16( @llvm.riscv.vwsubu.nxv8i32.nxv8i16.i16( @@ -1206,8 +1206,8 @@ define @intrinsic_vwsubu_vx_nxv1i64_nxv1i32_i32( @llvm.riscv.vwsubu.nxv1i64.nxv1i32.i32( @@ -1252,8 +1252,8 @@ define @intrinsic_vwsubu_vx_nxv2i64_nxv2i32_i32( @llvm.riscv.vwsubu.nxv2i64.nxv2i32.i32( @@ -1298,8 +1298,8 @@ define @intrinsic_vwsubu_vx_nxv4i64_nxv4i32_i32( @llvm.riscv.vwsubu.nxv4i64.nxv4i32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll index f821f81508401de17027b7adbad8fb62a2151a2b..7a4ac1c97e4be355a67402704ecfec02eaec781c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll @@ -257,9 +257,9 @@ declare @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4r.v v28, (a0) +; CHECK-NEXT: vl4r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8( @@ -483,9 +483,9 @@ declare @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16( @@ -664,9 +664,9 @@ declare @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32( define @intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32( @@ -1868,8 +1868,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8( @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8( @@ -1884,8 +1884,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8( @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8( @@ -1900,8 +1900,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8( @llvm.riscv.vwsubu.w.nxv4i16.nxv4i8( @@ -1916,8 +1916,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8( @llvm.riscv.vwsubu.w.nxv8i16.nxv8i8( @@ -1932,8 +1932,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv16i16_nxv16i16_nxv16i ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vwsubu.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwsubu.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv16i16.nxv16i8( @@ -1964,8 +1964,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(< ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vwsubu.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vwsubu.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv1i32.nxv1i16( @@ -1980,8 +1980,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(< ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vwsubu.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vwsubu.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv2i32.nxv2i16( @@ -1996,8 +1996,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(< ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vwsubu.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vwsubu.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv4i32.nxv4i16( @@ -2012,8 +2012,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(< ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vwsubu.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwsubu.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv8i32.nxv8i16( @@ -2028,8 +2028,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(< ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vwsubu.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vwsubu.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv1i64.nxv1i32( @@ -2044,8 +2044,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(< ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vwsubu.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vwsubu.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv2i64.nxv2i32( @@ -2060,8 +2060,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(< ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vwsubu.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwsubu.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv4i64.nxv4i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll index 7272d7ee6fcfe545a361e7fde09d4fc48f4d2969..4de4be003f58a7bff3107f441a5ba34348918e0a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll @@ -257,9 +257,9 @@ declare @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8( define @intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4r.v v28, (a0) +; CHECK-NEXT: vl4r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu -; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8( @@ -483,9 +483,9 @@ declare @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16( define @intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v28, (a0) +; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu -; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16( @@ -664,9 +664,9 @@ declare @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32( define @intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v28, (a0) +; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu -; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t +; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32( @@ -1868,8 +1868,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8( @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8( @@ -1884,8 +1884,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8( @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8( @@ -1900,8 +1900,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8( @llvm.riscv.vwsubu.w.nxv4i16.nxv4i8( @@ -1916,8 +1916,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8( @llvm.riscv.vwsubu.w.nxv8i16.nxv8i8( @@ -1932,8 +1932,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv16i16_nxv16i16_nxv16i ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vwsubu.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwsubu.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv16i16.nxv16i8( @@ -1964,8 +1964,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(< ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vwsubu.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vwsubu.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv1i32.nxv1i16( @@ -1980,8 +1980,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(< ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vwsubu.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vwsubu.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv2i32.nxv2i16( @@ -1996,8 +1996,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(< ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vwsubu.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vwsubu.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv4i32.nxv4i16( @@ -2012,8 +2012,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(< ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vwsubu.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwsubu.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv8i32.nxv8i16( @@ -2028,8 +2028,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(< ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vwsubu.wv v25, v9, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vwsubu.wv v10, v9, v8 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv1i64.nxv1i32( @@ -2044,8 +2044,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(< ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vwsubu.wv v26, v10, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vwsubu.wv v12, v10, v8 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv2i64.nxv2i32( @@ -2060,8 +2060,8 @@ define @intrinsic_vwsubu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(< ; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vwsubu.wv v28, v12, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vwsubu.wv v16, v12, v8 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwsubu.w.nxv4i64.nxv4i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll index e580e5533a53265c755c94587cfd93f06b730df1..418aee23c1363446db1698b618a97fdc7815a445 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll @@ -1818,8 +1818,8 @@ define @intrinsic_vxor_vx_nxv1i64_nxv1i64_i64( @intrinsic_vxor_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vxor_vx_nxv2i64_nxv2i64_i64( @intrinsic_vxor_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vxor_vx_nxv4i64_nxv4i64_i64( @intrinsic_vxor_mask_vx_nxv4i64_nxv4i64_i64( @vxor_vx_nxv1i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v25, (a0), zero -; CHECK-NEXT: vxor.vv v8, v8, v25 +; CHECK-NEXT: vlse64.v v9, (a0), zero +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -1148,8 +1148,8 @@ define @vxor_vx_nxv2i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v26, (a0), zero -; CHECK-NEXT: vxor.vv v8, v8, v26 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vxor.vv v8, v8, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 @@ -1214,8 +1214,8 @@ define @vxor_vx_nxv4i64( %va, i64 %b) { ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vlse64.v v28, (a0), zero -; CHECK-NEXT: vxor.vv v8, v8, v28 +; CHECK-NEXT: vlse64.v v12, (a0), zero +; CHECK-NEXT: vxor.vv v8, v8, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll index b692f16378dc17b596deaaa0f573a20c2ac587e3..dab165c0a450f426efaea82e54cb151b266f1c32 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll @@ -1989,9 +1989,9 @@ define @vxor_vx_nxv1i64( %va, i64 %b, @vxor_vx_nxv1i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu -; RV32-NEXT: vxor.vv v8, v8, v25 +; RV32-NEXT: vxor.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -2119,9 +2119,9 @@ define @vxor_vx_nxv2i64( %va, i64 %b, @vxor_vx_nxv2i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu -; RV32-NEXT: vxor.vv v8, v8, v26 +; RV32-NEXT: vxor.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; @@ -2249,9 +2249,9 @@ define @vxor_vx_nxv4i64( %va, i64 %b, @vxor_vx_nxv4i64_unmasked( %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu -; RV32-NEXT: vxor.vv v8, v8, v28 +; RV32-NEXT: vxor.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll index 3031b116c315d33bbd39318805eca04d45422a3a..57c8ad7ce5eb46e727cb4b0c591bf425b3c9a084 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll @@ -9,8 +9,8 @@ define @intrinsic_vzext_vf8_nxv1i64( %0, i32 ; CHECK-LABEL: intrinsic_vzext_vf8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf8 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf8 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv1i64.nxv1i8( @@ -51,8 +51,8 @@ define @intrinsic_vzext_vf8_nxv2i64( %0, i32 ; CHECK-LABEL: intrinsic_vzext_vf8_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf8 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv2i64.nxv2i8( @@ -93,8 +93,8 @@ define @intrinsic_vzext_vf8_nxv4i64( %0, i32 ; CHECK-LABEL: intrinsic_vzext_vf8_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf8 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv4i64.nxv4i8( @@ -177,8 +177,8 @@ define @intrinsic_vzext_vf4_nxv1i64( %0, i3 ; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv1i64.nxv1i16( @@ -219,8 +219,8 @@ define @intrinsic_vzext_vf4_nxv2i64( %0, i3 ; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv2i64.nxv2i16( @@ -261,8 +261,8 @@ define @intrinsic_vzext_vf4_nxv4i64( %0, i3 ; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv4i64.nxv4i16( @@ -345,8 +345,8 @@ define @intrinsic_vzext_vf4_nxv1i32( %0, i32 ; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv1i32.nxv1i8( @@ -387,8 +387,8 @@ define @intrinsic_vzext_vf4_nxv2i32( %0, i32 ; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv2i32.nxv2i8( @@ -429,8 +429,8 @@ define @intrinsic_vzext_vf4_nxv4i32( %0, i32 ; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv4i32.nxv4i8( @@ -471,8 +471,8 @@ define @intrinsic_vzext_vf4_nxv8i32( %0, i32 ; CHECK-LABEL: intrinsic_vzext_vf4_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv8i32.nxv8i8( @@ -555,8 +555,8 @@ define @intrinsic_vzext_vf2_nxv1i64( %0, i3 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv1i64.nxv1i32( @@ -597,8 +597,8 @@ define @intrinsic_vzext_vf2_nxv2i64( %0, i3 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv2i64.nxv2i32( @@ -639,8 +639,8 @@ define @intrinsic_vzext_vf2_nxv4i64( %0, i3 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv4i64.nxv4i32( @@ -723,8 +723,8 @@ define @intrinsic_vzext_vf2_nxv1i32( %0, i3 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv1i32.nxv1i16( @@ -765,8 +765,8 @@ define @intrinsic_vzext_vf2_nxv2i32( %0, i3 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv2i32.nxv2i16( @@ -807,8 +807,8 @@ define @intrinsic_vzext_vf2_nxv4i32( %0, i3 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv4i32.nxv4i16( @@ -849,8 +849,8 @@ define @intrinsic_vzext_vf2_nxv8i32( %0, i3 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv8i32.nxv8i16( @@ -933,8 +933,8 @@ define @intrinsic_vzext_vf2_nxv1i16( %0, i32 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv1i16.nxv1i8( @@ -975,8 +975,8 @@ define @intrinsic_vzext_vf2_nxv2i16( %0, i32 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv2i16.nxv2i8( @@ -1017,8 +1017,8 @@ define @intrinsic_vzext_vf2_nxv4i16( %0, i32 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv4i16.nxv4i8( @@ -1059,8 +1059,8 @@ define @intrinsic_vzext_vf2_nxv8i16( %0, i32 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv8i16.nxv8i8( @@ -1101,8 +1101,8 @@ define @intrinsic_vzext_vf2_nxv16i16( %0, ; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv16i16.nxv16i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll index df42a045534e659ee91986fe147ba5a60a13e1c7..f6c4aac0e22f76d7631ff7656b14ee18a624886c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll @@ -9,8 +9,8 @@ define @intrinsic_vzext_vf8_nxv1i64( %0, i64 ; CHECK-LABEL: intrinsic_vzext_vf8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf8 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf8 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv1i64.nxv1i8( @@ -51,8 +51,8 @@ define @intrinsic_vzext_vf8_nxv2i64( %0, i64 ; CHECK-LABEL: intrinsic_vzext_vf8_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf8 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv2i64.nxv2i8( @@ -93,8 +93,8 @@ define @intrinsic_vzext_vf8_nxv4i64( %0, i64 ; CHECK-LABEL: intrinsic_vzext_vf8_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf8 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf8 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv4i64.nxv4i8( @@ -177,8 +177,8 @@ define @intrinsic_vzext_vf4_nxv1i64( %0, i6 ; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv1i64.nxv1i16( @@ -219,8 +219,8 @@ define @intrinsic_vzext_vf4_nxv2i64( %0, i6 ; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv2i64.nxv2i16( @@ -261,8 +261,8 @@ define @intrinsic_vzext_vf4_nxv4i64( %0, i6 ; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv4i64.nxv4i16( @@ -345,8 +345,8 @@ define @intrinsic_vzext_vf4_nxv1i32( %0, i64 ; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv1i32.nxv1i8( @@ -387,8 +387,8 @@ define @intrinsic_vzext_vf4_nxv2i32( %0, i64 ; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf4 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf4 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv2i32.nxv2i8( @@ -429,8 +429,8 @@ define @intrinsic_vzext_vf4_nxv4i32( %0, i64 ; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf4 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf4 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv4i32.nxv4i8( @@ -471,8 +471,8 @@ define @intrinsic_vzext_vf4_nxv8i32( %0, i64 ; CHECK-LABEL: intrinsic_vzext_vf4_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vzext.vf4 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf4 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv8i32.nxv8i8( @@ -555,8 +555,8 @@ define @intrinsic_vzext_vf2_nxv1i64( %0, i6 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv1i64.nxv1i32( @@ -597,8 +597,8 @@ define @intrinsic_vzext_vf2_nxv2i64( %0, i6 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv2i64.nxv2i32( @@ -639,8 +639,8 @@ define @intrinsic_vzext_vf2_nxv4i64( %0, i6 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv4i64.nxv4i32( @@ -723,8 +723,8 @@ define @intrinsic_vzext_vf2_nxv1i32( %0, i6 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv1i32.nxv1i16( @@ -765,8 +765,8 @@ define @intrinsic_vzext_vf2_nxv2i32( %0, i6 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv2i32.nxv2i16( @@ -807,8 +807,8 @@ define @intrinsic_vzext_vf2_nxv4i32( %0, i6 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv4i32.nxv4i16( @@ -849,8 +849,8 @@ define @intrinsic_vzext_vf2_nxv8i32( %0, i6 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv8i32.nxv8i16( @@ -933,8 +933,8 @@ define @intrinsic_vzext_vf2_nxv1i16( %0, i64 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv1i16.nxv1i8( @@ -975,8 +975,8 @@ define @intrinsic_vzext_vf2_nxv2i16( %0, i64 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv2i16.nxv2i8( @@ -1017,8 +1017,8 @@ define @intrinsic_vzext_vf2_nxv4i16( %0, i64 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vzext.vf2 v25, v8 -; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: vzext.vf2 v9, v8 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv4i16.nxv4i8( @@ -1059,8 +1059,8 @@ define @intrinsic_vzext_vf2_nxv8i16( %0, i64 ; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vzext.vf2 v26, v8 -; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv8i16.nxv8i8( @@ -1101,8 +1101,8 @@ define @intrinsic_vzext_vf2_nxv16i16( %0, ; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vzext.vf2 v28, v8 -; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vzext.nxv16i16.nxv16i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll index 55c97c83fd45082d2f3c56cc41c4d899d26b50a5..98d1630053d16ae7417ddbaab838a3a62ef42416 100644 --- a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll +++ b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll @@ -187,10 +187,10 @@ define void @test_vsoxseg2_nxv16i16_nxv16i16( %val, i16* %bas ; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28 +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16( %val, %val, i16* %base, %index, i64 0) @@ -201,10 +201,10 @@ define void @test_vsoxseg2_mask_nxv16i16_nxv16i16( %val, i16* ; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu -; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16( %val, %val, i16* %base, %index, %mask, i64 0) @@ -218,10 +218,10 @@ define void @test_vsuxseg2_nxv16i16_nxv16i16( %val, i16* %bas ; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28 +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16( %val, %val, i16* %base, %index, i64 0) @@ -232,10 +232,10 @@ define void @test_vsuxseg2_mask_nxv16i16_nxv16i16( %val, i16* ; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4 -; CHECK-NEXT: vmv4r.v v28, v12 +; CHECK-NEXT: vmv4r.v v16, v12 ; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu -; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t +; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16( %val, %val, i16* %base, %index, %mask, i64 0) diff --git a/llvm/test/CodeGen/RISCV/select-optimize-multiple.mir b/llvm/test/CodeGen/RISCV/select-optimize-multiple.mir index 62e8b9f86dbfd81c94e6a4300df49c2b4cdd9345..f4fb4a5bb83609fbc84d7e7f26703d8253dc767d 100644 --- a/llvm/test/CodeGen/RISCV/select-optimize-multiple.mir +++ b/llvm/test/CodeGen/RISCV/select-optimize-multiple.mir @@ -48,92 +48,116 @@ body: | ; RV32I-LABEL: name: cmov_interleaved_bad ; RV32I: successors: %bb.1, %bb.2 - ; RV32I: liveins: $x10, $x11, $x12, $x13 - ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x13 - ; RV32I: [[COPY1:%[0-9]+]]:gpr = COPY $x12 - ; RV32I: [[COPY2:%[0-9]+]]:gpr = COPY $x11 - ; RV32I: [[COPY3:%[0-9]+]]:gpr = COPY $x10 - ; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 - ; RV32I: [[COPY4:%[0-9]+]]:gpr = COPY $x0 - ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2 - ; RV32I: .1: - ; RV32I: .2: - ; RV32I: successors: %bb.3, %bb.4 - ; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 - ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 - ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.4 - ; RV32I: .3: - ; RV32I: .4: - ; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3 - ; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] - ; RV32I: $x10 = COPY [[ADD]] - ; RV32I: PseudoRET implicit $x10 + ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 + ; RV32I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 + ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: .1: + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: .2: + ; RV32I-NEXT: successors: %bb.3, %bb.4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 + ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: .3: + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: .4: + ; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3 + ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] + ; RV32I-NEXT: $x10 = COPY [[ADD]] + ; RV32I-NEXT: PseudoRET implicit $x10 ; RV32IBT-LABEL: name: cmov_interleaved_bad ; RV32IBT: successors: %bb.1, %bb.2 - ; RV32IBT: liveins: $x10, $x11, $x12, $x13 - ; RV32IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13 - ; RV32IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 - ; RV32IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 - ; RV32IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 - ; RV32IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 - ; RV32IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 - ; RV32IBT: BNE [[ANDI]], [[COPY4]], %bb.2 - ; RV32IBT: .1: - ; RV32IBT: .2: - ; RV32IBT: successors: %bb.3, %bb.4 - ; RV32IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 - ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 - ; RV32IBT: BNE [[ANDI]], [[COPY4]], %bb.4 - ; RV32IBT: .3: - ; RV32IBT: .4: - ; RV32IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3 - ; RV32IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] - ; RV32IBT: $x10 = COPY [[ADD]] - ; RV32IBT: PseudoRET implicit $x10 + ; RV32IBT-NEXT: liveins: $x10, $x11, $x12, $x13 + ; RV32IBT-NEXT: {{ $}} + ; RV32IBT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; RV32IBT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; RV32IBT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; RV32IBT-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; RV32IBT-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 + ; RV32IBT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 + ; RV32IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2 + ; RV32IBT-NEXT: {{ $}} + ; RV32IBT-NEXT: .1: + ; RV32IBT-NEXT: {{ $}} + ; RV32IBT-NEXT: .2: + ; RV32IBT-NEXT: successors: %bb.3, %bb.4 + ; RV32IBT-NEXT: {{ $}} + ; RV32IBT-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 + ; RV32IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 + ; RV32IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4 + ; RV32IBT-NEXT: {{ $}} + ; RV32IBT-NEXT: .3: + ; RV32IBT-NEXT: {{ $}} + ; RV32IBT-NEXT: .4: + ; RV32IBT-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3 + ; RV32IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] + ; RV32IBT-NEXT: $x10 = COPY [[ADD]] + ; RV32IBT-NEXT: PseudoRET implicit $x10 ; RV64I-LABEL: name: cmov_interleaved_bad ; RV64I: successors: %bb.1, %bb.2 - ; RV64I: liveins: $x10, $x11, $x12, $x13 - ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13 - ; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12 - ; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11 - ; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10 - ; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 - ; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0 - ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2 - ; RV64I: .1: - ; RV64I: .2: - ; RV64I: successors: %bb.3, %bb.4 - ; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 - ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 - ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.4 - ; RV64I: .3: - ; RV64I: .4: - ; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3 - ; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] - ; RV64I: $x10 = COPY [[ADD]] - ; RV64I: PseudoRET implicit $x10 + ; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 + ; RV64I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 + ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: .1: + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: .2: + ; RV64I-NEXT: successors: %bb.3, %bb.4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 + ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 + ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: .3: + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: .4: + ; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3 + ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] + ; RV64I-NEXT: $x10 = COPY [[ADD]] + ; RV64I-NEXT: PseudoRET implicit $x10 ; RV64IBT-LABEL: name: cmov_interleaved_bad ; RV64IBT: successors: %bb.1, %bb.2 - ; RV64IBT: liveins: $x10, $x11, $x12, $x13 - ; RV64IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13 - ; RV64IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 - ; RV64IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 - ; RV64IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 - ; RV64IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 - ; RV64IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 - ; RV64IBT: BNE [[ANDI]], [[COPY4]], %bb.2 - ; RV64IBT: .1: - ; RV64IBT: .2: - ; RV64IBT: successors: %bb.3, %bb.4 - ; RV64IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 - ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 - ; RV64IBT: BNE [[ANDI]], [[COPY4]], %bb.4 - ; RV64IBT: .3: - ; RV64IBT: .4: - ; RV64IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3 - ; RV64IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] - ; RV64IBT: $x10 = COPY [[ADD]] - ; RV64IBT: PseudoRET implicit $x10 + ; RV64IBT-NEXT: liveins: $x10, $x11, $x12, $x13 + ; RV64IBT-NEXT: {{ $}} + ; RV64IBT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; RV64IBT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; RV64IBT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; RV64IBT-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; RV64IBT-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 + ; RV64IBT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 + ; RV64IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2 + ; RV64IBT-NEXT: {{ $}} + ; RV64IBT-NEXT: .1: + ; RV64IBT-NEXT: {{ $}} + ; RV64IBT-NEXT: .2: + ; RV64IBT-NEXT: successors: %bb.3, %bb.4 + ; RV64IBT-NEXT: {{ $}} + ; RV64IBT-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 + ; RV64IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 + ; RV64IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.4 + ; RV64IBT-NEXT: {{ $}} + ; RV64IBT-NEXT: .3: + ; RV64IBT-NEXT: {{ $}} + ; RV64IBT-NEXT: .4: + ; RV64IBT-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3 + ; RV64IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] + ; RV64IBT-NEXT: $x10 = COPY [[ADD]] + ; RV64IBT-NEXT: PseudoRET implicit $x10 %3:gpr = COPY $x13 %2:gpr = COPY $x12 %1:gpr = COPY $x11 @@ -178,88 +202,100 @@ body: | ; RV32I-LABEL: name: cmov_interleaved_debug_value ; RV32I: successors: %bb.1, %bb.2 - ; RV32I: liveins: $x10, $x11, $x12, $x13 - ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x13 - ; RV32I: [[COPY1:%[0-9]+]]:gpr = COPY $x12 - ; RV32I: [[COPY2:%[0-9]+]]:gpr = COPY $x11 - ; RV32I: [[COPY3:%[0-9]+]]:gpr = COPY $x10 - ; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 - ; RV32I: [[COPY4:%[0-9]+]]:gpr = COPY $x0 - ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1 - ; RV32I: DBG_VALUE [[ADDI]], $noreg - ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2 - ; RV32I: .1: - ; RV32I: .2: - ; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 - ; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1 - ; RV32I: DBG_VALUE [[PHI]], $noreg - ; RV32I: DBG_VALUE [[PHI1]], $noreg - ; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] - ; RV32I: $x10 = COPY [[ADD]] - ; RV32I: PseudoRET implicit $x10 + ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 + ; RV32I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1 + ; RV32I-NEXT: DBG_VALUE [[ADDI]], $noreg + ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: .1: + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: .2: + ; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 + ; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1 + ; RV32I-NEXT: DBG_VALUE [[PHI]], $noreg + ; RV32I-NEXT: DBG_VALUE [[PHI1]], $noreg + ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] + ; RV32I-NEXT: $x10 = COPY [[ADD]] + ; RV32I-NEXT: PseudoRET implicit $x10 ; RV32IBT-LABEL: name: cmov_interleaved_debug_value ; RV32IBT: successors: %bb.1, %bb.2 - ; RV32IBT: liveins: $x10, $x11, $x12, $x13 - ; RV32IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13 - ; RV32IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 - ; RV32IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 - ; RV32IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 - ; RV32IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 - ; RV32IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 - ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1 - ; RV32IBT: DBG_VALUE [[ADDI]], $noreg - ; RV32IBT: BNE [[ANDI]], [[COPY4]], %bb.2 - ; RV32IBT: .1: - ; RV32IBT: .2: - ; RV32IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 - ; RV32IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1 - ; RV32IBT: DBG_VALUE [[PHI]], $noreg - ; RV32IBT: DBG_VALUE [[PHI1]], $noreg - ; RV32IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] - ; RV32IBT: $x10 = COPY [[ADD]] - ; RV32IBT: PseudoRET implicit $x10 + ; RV32IBT-NEXT: liveins: $x10, $x11, $x12, $x13 + ; RV32IBT-NEXT: {{ $}} + ; RV32IBT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; RV32IBT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; RV32IBT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; RV32IBT-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; RV32IBT-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 + ; RV32IBT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 + ; RV32IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1 + ; RV32IBT-NEXT: DBG_VALUE [[ADDI]], $noreg + ; RV32IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2 + ; RV32IBT-NEXT: {{ $}} + ; RV32IBT-NEXT: .1: + ; RV32IBT-NEXT: {{ $}} + ; RV32IBT-NEXT: .2: + ; RV32IBT-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 + ; RV32IBT-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1 + ; RV32IBT-NEXT: DBG_VALUE [[PHI]], $noreg + ; RV32IBT-NEXT: DBG_VALUE [[PHI1]], $noreg + ; RV32IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] + ; RV32IBT-NEXT: $x10 = COPY [[ADD]] + ; RV32IBT-NEXT: PseudoRET implicit $x10 ; RV64I-LABEL: name: cmov_interleaved_debug_value ; RV64I: successors: %bb.1, %bb.2 - ; RV64I: liveins: $x10, $x11, $x12, $x13 - ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13 - ; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12 - ; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11 - ; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10 - ; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 - ; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0 - ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1 - ; RV64I: DBG_VALUE [[ADDI]], $noreg - ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2 - ; RV64I: .1: - ; RV64I: .2: - ; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 - ; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1 - ; RV64I: DBG_VALUE [[PHI]], $noreg - ; RV64I: DBG_VALUE [[PHI1]], $noreg - ; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] - ; RV64I: $x10 = COPY [[ADD]] - ; RV64I: PseudoRET implicit $x10 + ; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 + ; RV64I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 + ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1 + ; RV64I-NEXT: DBG_VALUE [[ADDI]], $noreg + ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: .1: + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: .2: + ; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 + ; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1 + ; RV64I-NEXT: DBG_VALUE [[PHI]], $noreg + ; RV64I-NEXT: DBG_VALUE [[PHI1]], $noreg + ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] + ; RV64I-NEXT: $x10 = COPY [[ADD]] + ; RV64I-NEXT: PseudoRET implicit $x10 ; RV64IBT-LABEL: name: cmov_interleaved_debug_value ; RV64IBT: successors: %bb.1, %bb.2 - ; RV64IBT: liveins: $x10, $x11, $x12, $x13 - ; RV64IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13 - ; RV64IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 - ; RV64IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 - ; RV64IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 - ; RV64IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 - ; RV64IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 - ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1 - ; RV64IBT: DBG_VALUE [[ADDI]], $noreg - ; RV64IBT: BNE [[ANDI]], [[COPY4]], %bb.2 - ; RV64IBT: .1: - ; RV64IBT: .2: - ; RV64IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 - ; RV64IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1 - ; RV64IBT: DBG_VALUE [[PHI]], $noreg - ; RV64IBT: DBG_VALUE [[PHI1]], $noreg - ; RV64IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] - ; RV64IBT: $x10 = COPY [[ADD]] - ; RV64IBT: PseudoRET implicit $x10 + ; RV64IBT-NEXT: liveins: $x10, $x11, $x12, $x13 + ; RV64IBT-NEXT: {{ $}} + ; RV64IBT-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13 + ; RV64IBT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12 + ; RV64IBT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 + ; RV64IBT-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 + ; RV64IBT-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 + ; RV64IBT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 + ; RV64IBT-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1 + ; RV64IBT-NEXT: DBG_VALUE [[ADDI]], $noreg + ; RV64IBT-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2 + ; RV64IBT-NEXT: {{ $}} + ; RV64IBT-NEXT: .1: + ; RV64IBT-NEXT: {{ $}} + ; RV64IBT-NEXT: .2: + ; RV64IBT-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 + ; RV64IBT-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1 + ; RV64IBT-NEXT: DBG_VALUE [[PHI]], $noreg + ; RV64IBT-NEXT: DBG_VALUE [[PHI1]], $noreg + ; RV64IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] + ; RV64IBT-NEXT: $x10 = COPY [[ADD]] + ; RV64IBT-NEXT: PseudoRET implicit $x10 %3:gpr = COPY $x13 %2:gpr = COPY $x12 %1:gpr = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll index c876531db0c837dcbcf98639e35cfd9dad8dd8b2..cfc6be79050356368aa770352b9abc0bc9f040a4 100644 --- a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll +++ b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll @@ -715,39 +715,39 @@ define void @test_srem_vec(<3 x i33>* %X) nounwind { ; RV32MV-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32MV-NEXT: vmv.s.x v0, a0 ; RV32MV-NEXT: vsetivli zero, 8, e32, m2, ta, mu -; RV32MV-NEXT: vmv.v.i v26, 1 +; RV32MV-NEXT: vmv.v.i v8, 1 ; RV32MV-NEXT: addi a0, sp, 32 -; RV32MV-NEXT: vle32.v v28, (a0) +; RV32MV-NEXT: vle32.v v10, (a0) ; RV32MV-NEXT: lui a0, %hi(.LCPI3_0) ; RV32MV-NEXT: addi a0, a0, %lo(.LCPI3_0) -; RV32MV-NEXT: vle32.v v30, (a0) -; RV32MV-NEXT: vmerge.vim v26, v26, -1, v0 -; RV32MV-NEXT: vand.vv v26, v28, v26 +; RV32MV-NEXT: vle32.v v12, (a0) +; RV32MV-NEXT: vmerge.vim v8, v8, -1, v0 +; RV32MV-NEXT: vand.vv v8, v10, v8 ; RV32MV-NEXT: vsetivli zero, 4, e64, m2, ta, mu -; RV32MV-NEXT: vmsne.vv v0, v26, v30 -; RV32MV-NEXT: vmv.v.i v26, 0 -; RV32MV-NEXT: vmerge.vim v26, v26, -1, v0 +; RV32MV-NEXT: vmsne.vv v0, v8, v12 +; RV32MV-NEXT: vmv.v.i v8, 0 +; RV32MV-NEXT: vmerge.vim v8, v8, -1, v0 ; RV32MV-NEXT: vsetivli zero, 1, e32, m2, ta, mu -; RV32MV-NEXT: vse32.v v26, (s1) -; RV32MV-NEXT: vslidedown.vi v28, v26, 1 -; RV32MV-NEXT: vmv.x.s a0, v28 -; RV32MV-NEXT: vslidedown.vi v28, v26, 2 -; RV32MV-NEXT: vmv.x.s a1, v28 +; RV32MV-NEXT: vse32.v v8, (s1) +; RV32MV-NEXT: vslidedown.vi v10, v8, 1 +; RV32MV-NEXT: vmv.x.s a0, v10 +; RV32MV-NEXT: vslidedown.vi v10, v8, 2 +; RV32MV-NEXT: vmv.x.s a1, v10 ; RV32MV-NEXT: slli a2, a1, 1 ; RV32MV-NEXT: sub a0, a2, a0 ; RV32MV-NEXT: sw a0, 4(s1) -; RV32MV-NEXT: vslidedown.vi v28, v26, 4 -; RV32MV-NEXT: vmv.x.s a0, v28 +; RV32MV-NEXT: vslidedown.vi v10, v8, 4 +; RV32MV-NEXT: vmv.x.s a0, v10 ; RV32MV-NEXT: srli a2, a0, 30 -; RV32MV-NEXT: vslidedown.vi v28, v26, 5 -; RV32MV-NEXT: vmv.x.s a3, v28 +; RV32MV-NEXT: vslidedown.vi v10, v8, 5 +; RV32MV-NEXT: vmv.x.s a3, v10 ; RV32MV-NEXT: slli a3, a3, 2 ; RV32MV-NEXT: or a2, a3, a2 ; RV32MV-NEXT: andi a2, a2, 7 ; RV32MV-NEXT: sb a2, 12(s1) ; RV32MV-NEXT: srli a1, a1, 31 -; RV32MV-NEXT: vslidedown.vi v26, v26, 3 -; RV32MV-NEXT: vmv.x.s a2, v26 +; RV32MV-NEXT: vslidedown.vi v8, v8, 3 +; RV32MV-NEXT: vmv.x.s a2, v8 ; RV32MV-NEXT: andi a2, a2, 1 ; RV32MV-NEXT: slli a2, a2, 1 ; RV32MV-NEXT: or a1, a1, a2 @@ -834,29 +834,29 @@ define void @test_srem_vec(<3 x i33>* %X) nounwind { ; RV64MV-NEXT: sd a1, 24(sp) ; RV64MV-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64MV-NEXT: addi a1, sp, 16 -; RV64MV-NEXT: vle64.v v26, (a1) +; RV64MV-NEXT: vle64.v v8, (a1) ; RV64MV-NEXT: lui a1, %hi(.LCPI3_0) ; RV64MV-NEXT: addi a1, a1, %lo(.LCPI3_0) -; RV64MV-NEXT: vle64.v v28, (a1) +; RV64MV-NEXT: vle64.v v10, (a1) ; RV64MV-NEXT: srli a1, a6, 31 -; RV64MV-NEXT: vand.vx v26, v26, a1 -; RV64MV-NEXT: vmsne.vv v0, v26, v28 -; RV64MV-NEXT: vmv.v.i v26, 0 -; RV64MV-NEXT: vmerge.vim v26, v26, -1, v0 +; RV64MV-NEXT: vand.vx v8, v8, a1 +; RV64MV-NEXT: vmsne.vv v0, v8, v10 +; RV64MV-NEXT: vmv.v.i v8, 0 +; RV64MV-NEXT: vmerge.vim v8, v8, -1, v0 ; RV64MV-NEXT: vsetivli zero, 1, e64, m2, ta, mu -; RV64MV-NEXT: vslidedown.vi v28, v26, 2 -; RV64MV-NEXT: vmv.x.s a2, v28 +; RV64MV-NEXT: vslidedown.vi v10, v8, 2 +; RV64MV-NEXT: vmv.x.s a2, v10 ; RV64MV-NEXT: srli a3, a2, 30 ; RV64MV-NEXT: andi a3, a3, 7 ; RV64MV-NEXT: sb a3, 12(a0) ; RV64MV-NEXT: slli a2, a2, 2 -; RV64MV-NEXT: vslidedown.vi v28, v26, 1 -; RV64MV-NEXT: vmv.x.s a3, v28 +; RV64MV-NEXT: vslidedown.vi v10, v8, 1 +; RV64MV-NEXT: vmv.x.s a3, v10 ; RV64MV-NEXT: and a3, a3, a1 ; RV64MV-NEXT: srli a4, a3, 31 ; RV64MV-NEXT: or a2, a4, a2 ; RV64MV-NEXT: sw a2, 8(a0) -; RV64MV-NEXT: vmv.x.s a2, v26 +; RV64MV-NEXT: vmv.x.s a2, v8 ; RV64MV-NEXT: and a1, a2, a1 ; RV64MV-NEXT: slli a2, a3, 33 ; RV64MV-NEXT: or a1, a1, a2 diff --git a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll index b57f68a330c302b2688911de449e44cb076aa475..dbb8b31759d6a0e50430a152f3114e370d931aee 100644 --- a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll +++ b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll @@ -568,46 +568,46 @@ define void @test_urem_vec(<3 x i11>* %X) nounwind { ; RV32MV-NEXT: sh a1, 12(sp) ; RV32MV-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV32MV-NEXT: addi a1, sp, 8 -; RV32MV-NEXT: vle16.v v25, (a1) +; RV32MV-NEXT: vle16.v v8, (a1) ; RV32MV-NEXT: lui a1, %hi(.LCPI4_0) ; RV32MV-NEXT: addi a1, a1, %lo(.LCPI4_0) -; RV32MV-NEXT: vle16.v v26, (a1) -; RV32MV-NEXT: vid.v v27 -; RV32MV-NEXT: vsub.vv v25, v25, v27 -; RV32MV-NEXT: vmul.vv v25, v25, v26 -; RV32MV-NEXT: vadd.vv v26, v25, v25 +; RV32MV-NEXT: vle16.v v9, (a1) +; RV32MV-NEXT: vid.v v10 +; RV32MV-NEXT: vsub.vv v8, v8, v10 +; RV32MV-NEXT: vmul.vv v8, v8, v9 +; RV32MV-NEXT: vadd.vv v9, v8, v8 ; RV32MV-NEXT: addi a1, zero, 9 -; RV32MV-NEXT: vmv.v.i v27, 10 +; RV32MV-NEXT: vmv.v.i v10, 10 ; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, tu, mu -; RV32MV-NEXT: vmv.s.x v27, a1 +; RV32MV-NEXT: vmv.s.x v10, a1 ; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; RV32MV-NEXT: vsll.vv v26, v26, v27 +; RV32MV-NEXT: vsll.vv v9, v9, v10 ; RV32MV-NEXT: addi a1, zero, 2047 -; RV32MV-NEXT: vand.vx v25, v25, a1 -; RV32MV-NEXT: vmv.v.i v27, 0 +; RV32MV-NEXT: vand.vx v8, v8, a1 +; RV32MV-NEXT: vmv.v.i v10, 0 ; RV32MV-NEXT: addi a2, zero, 1 ; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, tu, mu -; RV32MV-NEXT: vmv1r.v v28, v27 -; RV32MV-NEXT: vmv.s.x v28, a2 +; RV32MV-NEXT: vmv1r.v v11, v10 +; RV32MV-NEXT: vmv.s.x v11, a2 ; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32MV-NEXT: lui a2, %hi(.LCPI4_1) ; RV32MV-NEXT: addi a2, a2, %lo(.LCPI4_1) -; RV32MV-NEXT: vle16.v v29, (a2) -; RV32MV-NEXT: vsrl.vv v25, v25, v28 -; RV32MV-NEXT: vor.vv v25, v25, v26 -; RV32MV-NEXT: vand.vx v25, v25, a1 -; RV32MV-NEXT: vmsltu.vv v0, v29, v25 -; RV32MV-NEXT: vmerge.vim v25, v27, -1, v0 +; RV32MV-NEXT: vle16.v v12, (a2) +; RV32MV-NEXT: vsrl.vv v8, v8, v11 +; RV32MV-NEXT: vor.vv v8, v8, v9 +; RV32MV-NEXT: vand.vx v8, v8, a1 +; RV32MV-NEXT: vmsltu.vv v0, v12, v8 +; RV32MV-NEXT: vmerge.vim v8, v10, -1, v0 ; RV32MV-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; RV32MV-NEXT: vslidedown.vi v26, v25, 2 -; RV32MV-NEXT: vmv.x.s a1, v26 +; RV32MV-NEXT: vslidedown.vi v9, v8, 2 +; RV32MV-NEXT: vmv.x.s a1, v9 ; RV32MV-NEXT: srli a2, a1, 10 ; RV32MV-NEXT: andi a2, a2, 1 ; RV32MV-NEXT: sb a2, 4(a0) -; RV32MV-NEXT: vmv.x.s a2, v25 +; RV32MV-NEXT: vmv.x.s a2, v8 ; RV32MV-NEXT: andi a2, a2, 2047 -; RV32MV-NEXT: vslidedown.vi v25, v25, 1 -; RV32MV-NEXT: vmv.x.s a3, v25 +; RV32MV-NEXT: vslidedown.vi v8, v8, 1 +; RV32MV-NEXT: vmv.x.s a3, v8 ; RV32MV-NEXT: andi a3, a3, 2047 ; RV32MV-NEXT: slli a3, a3, 11 ; RV32MV-NEXT: or a2, a2, a3 @@ -633,46 +633,46 @@ define void @test_urem_vec(<3 x i11>* %X) nounwind { ; RV64MV-NEXT: sh a1, 10(sp) ; RV64MV-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; RV64MV-NEXT: addi a1, sp, 8 -; RV64MV-NEXT: vle16.v v25, (a1) +; RV64MV-NEXT: vle16.v v8, (a1) ; RV64MV-NEXT: lui a1, %hi(.LCPI4_0) ; RV64MV-NEXT: addi a1, a1, %lo(.LCPI4_0) -; RV64MV-NEXT: vle16.v v26, (a1) -; RV64MV-NEXT: vid.v v27 -; RV64MV-NEXT: vsub.vv v25, v25, v27 -; RV64MV-NEXT: vmul.vv v25, v25, v26 -; RV64MV-NEXT: vadd.vv v26, v25, v25 +; RV64MV-NEXT: vle16.v v9, (a1) +; RV64MV-NEXT: vid.v v10 +; RV64MV-NEXT: vsub.vv v8, v8, v10 +; RV64MV-NEXT: vmul.vv v8, v8, v9 +; RV64MV-NEXT: vadd.vv v9, v8, v8 ; RV64MV-NEXT: addi a1, zero, 9 -; RV64MV-NEXT: vmv.v.i v27, 10 +; RV64MV-NEXT: vmv.v.i v10, 10 ; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, tu, mu -; RV64MV-NEXT: vmv.s.x v27, a1 +; RV64MV-NEXT: vmv.s.x v10, a1 ; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; RV64MV-NEXT: vsll.vv v26, v26, v27 +; RV64MV-NEXT: vsll.vv v9, v9, v10 ; RV64MV-NEXT: addi a1, zero, 2047 -; RV64MV-NEXT: vand.vx v25, v25, a1 -; RV64MV-NEXT: vmv.v.i v27, 0 +; RV64MV-NEXT: vand.vx v8, v8, a1 +; RV64MV-NEXT: vmv.v.i v10, 0 ; RV64MV-NEXT: addi a2, zero, 1 ; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, tu, mu -; RV64MV-NEXT: vmv1r.v v28, v27 -; RV64MV-NEXT: vmv.s.x v28, a2 +; RV64MV-NEXT: vmv1r.v v11, v10 +; RV64MV-NEXT: vmv.s.x v11, a2 ; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV64MV-NEXT: lui a2, %hi(.LCPI4_1) ; RV64MV-NEXT: addi a2, a2, %lo(.LCPI4_1) -; RV64MV-NEXT: vle16.v v29, (a2) -; RV64MV-NEXT: vsrl.vv v25, v25, v28 -; RV64MV-NEXT: vor.vv v25, v25, v26 -; RV64MV-NEXT: vand.vx v25, v25, a1 -; RV64MV-NEXT: vmsltu.vv v0, v29, v25 -; RV64MV-NEXT: vmerge.vim v25, v27, -1, v0 -; RV64MV-NEXT: vmv.x.s a1, v25 +; RV64MV-NEXT: vle16.v v12, (a2) +; RV64MV-NEXT: vsrl.vv v8, v8, v11 +; RV64MV-NEXT: vor.vv v8, v8, v9 +; RV64MV-NEXT: vand.vx v8, v8, a1 +; RV64MV-NEXT: vmsltu.vv v0, v12, v8 +; RV64MV-NEXT: vmerge.vim v8, v10, -1, v0 +; RV64MV-NEXT: vmv.x.s a1, v8 ; RV64MV-NEXT: andi a1, a1, 2047 ; RV64MV-NEXT: vsetivli zero, 1, e16, mf2, ta, mu -; RV64MV-NEXT: vslidedown.vi v26, v25, 1 -; RV64MV-NEXT: vmv.x.s a2, v26 +; RV64MV-NEXT: vslidedown.vi v9, v8, 1 +; RV64MV-NEXT: vmv.x.s a2, v9 ; RV64MV-NEXT: andi a2, a2, 2047 ; RV64MV-NEXT: slli a2, a2, 11 ; RV64MV-NEXT: or a1, a1, a2 -; RV64MV-NEXT: vslidedown.vi v25, v25, 2 -; RV64MV-NEXT: vmv.x.s a2, v25 +; RV64MV-NEXT: vslidedown.vi v8, v8, 2 +; RV64MV-NEXT: vmv.x.s a2, v8 ; RV64MV-NEXT: slli a2, a2, 22 ; RV64MV-NEXT: or a1, a1, a2 ; RV64MV-NEXT: sw a1, 0(a0) diff --git a/llvm/test/CodeGen/X86/pmulh.ll b/llvm/test/CodeGen/X86/pmulh.ll index 244deecf602c450ce01a747c09b1f42d76a271c2..4db1061de1da9464653936ff89dc20bd19007502 100644 --- a/llvm/test/CodeGen/X86/pmulh.ll +++ b/llvm/test/CodeGen/X86/pmulh.ll @@ -118,18 +118,18 @@ define <4 x i16> @ashr_mulhw_v4i16(<4 x i32> %a, <4 x i32> %b) { ; ; SSE41-LABEL: ashr_mulhw_v4i16: ; SSE41: # %bb.0: -; SSE41-NEXT: psrad $16, %xmm0 -; SSE41-NEXT: psrad $16, %xmm1 -; SSE41-NEXT: pmulld %xmm1, %xmm0 +; SSE41-NEXT: psrld $16, %xmm1 +; SSE41-NEXT: psrld $16, %xmm0 +; SSE41-NEXT: pmaddwd %xmm1, %xmm0 ; SSE41-NEXT: psrld $16, %xmm0 ; SSE41-NEXT: packusdw %xmm0, %xmm0 ; SSE41-NEXT: retq ; ; AVX-LABEL: ashr_mulhw_v4i16: ; AVX: # %bb.0: -; AVX-NEXT: vpsrad $16, %xmm0, %xmm0 -; AVX-NEXT: vpsrad $16, %xmm1, %xmm1 -; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vpsrld $16, %xmm1, %xmm1 +; AVX-NEXT: vpsrld $16, %xmm0, %xmm0 +; AVX-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpsrld $16, %xmm0, %xmm0 ; AVX-NEXT: vpackusdw %xmm0, %xmm0, %xmm0 ; AVX-NEXT: retq @@ -462,49 +462,58 @@ define <16 x i16> @ashr_mulhuw_v16i16(<16 x i32> %a, <16 x i32> %b) { ; ; SSE41-LABEL: ashr_mulhuw_v16i16: ; SSE41: # %bb.0: -; SSE41-NEXT: psrad $16, %xmm3 -; SSE41-NEXT: psrad $16, %xmm2 -; SSE41-NEXT: psrad $16, %xmm1 -; SSE41-NEXT: psrad $16, %xmm0 -; SSE41-NEXT: psrad $16, %xmm7 -; SSE41-NEXT: pmulld %xmm3, %xmm7 -; SSE41-NEXT: psrad $16, %xmm6 -; SSE41-NEXT: pmulld %xmm2, %xmm6 -; SSE41-NEXT: psrad $16, %xmm5 -; SSE41-NEXT: pmulld %xmm1, %xmm5 -; SSE41-NEXT: psrad $16, %xmm4 -; SSE41-NEXT: pmulld %xmm4, %xmm0 -; SSE41-NEXT: psrld $16, %xmm7 -; SSE41-NEXT: psrld $16, %xmm6 -; SSE41-NEXT: packusdw %xmm7, %xmm6 +; SSE41-NEXT: psrld $16, %xmm4 +; SSE41-NEXT: psrld $16, %xmm0 +; SSE41-NEXT: pmaddwd %xmm4, %xmm0 ; SSE41-NEXT: psrld $16, %xmm5 +; SSE41-NEXT: psrld $16, %xmm1 +; SSE41-NEXT: pmaddwd %xmm5, %xmm1 +; SSE41-NEXT: psrld $16, %xmm6 +; SSE41-NEXT: psrld $16, %xmm2 +; SSE41-NEXT: pmaddwd %xmm6, %xmm2 +; SSE41-NEXT: psrld $16, %xmm7 +; SSE41-NEXT: psrld $16, %xmm3 +; SSE41-NEXT: pmaddwd %xmm7, %xmm3 +; SSE41-NEXT: psrld $16, %xmm3 +; SSE41-NEXT: psrld $16, %xmm2 +; SSE41-NEXT: packusdw %xmm3, %xmm2 +; SSE41-NEXT: psrld $16, %xmm1 ; SSE41-NEXT: psrld $16, %xmm0 -; SSE41-NEXT: packusdw %xmm5, %xmm0 -; SSE41-NEXT: movdqa %xmm6, %xmm1 +; SSE41-NEXT: packusdw %xmm1, %xmm0 +; SSE41-NEXT: movdqa %xmm2, %xmm1 ; SSE41-NEXT: retq ; ; AVX2-LABEL: ashr_mulhuw_v16i16: ; AVX2: # %bb.0: -; AVX2-NEXT: vpsrad $16, %ymm1, %ymm1 -; AVX2-NEXT: vpsrad $16, %ymm0, %ymm0 -; AVX2-NEXT: vpsrad $16, %ymm3, %ymm3 -; AVX2-NEXT: vpmulld %ymm3, %ymm1, %ymm1 -; AVX2-NEXT: vpsrad $16, %ymm2, %ymm2 -; AVX2-NEXT: vpmulld %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpsrld $16, %ymm2, %ymm2 +; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX2-NEXT: vpmaddwd %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpsrld $16, %ymm3, %ymm2 +; AVX2-NEXT: vpsrld $16, %ymm1, %ymm1 +; AVX2-NEXT: vpmaddwd %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpsrld $16, %ymm1, %ymm1 ; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 ; AVX2-NEXT: vpackusdw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3] ; AVX2-NEXT: retq ; -; AVX512-LABEL: ashr_mulhuw_v16i16: -; AVX512: # %bb.0: -; AVX512-NEXT: vpsrad $16, %zmm0, %zmm0 -; AVX512-NEXT: vpsrad $16, %zmm1, %zmm1 -; AVX512-NEXT: vpmulld %zmm1, %zmm0, %zmm0 -; AVX512-NEXT: vpsrld $16, %zmm0, %zmm0 -; AVX512-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512-NEXT: retq +; AVX512F-LABEL: ashr_mulhuw_v16i16: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vpsrad $16, %zmm0, %zmm0 +; AVX512F-NEXT: vpsrad $16, %zmm1, %zmm1 +; AVX512F-NEXT: vpmulld %zmm1, %zmm0, %zmm0 +; AVX512F-NEXT: vpsrld $16, %zmm0, %zmm0 +; AVX512F-NEXT: vpmovdw %zmm0, %ymm0 +; AVX512F-NEXT: retq +; +; AVX512BW-LABEL: ashr_mulhuw_v16i16: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vpsrld $16, %zmm1, %zmm1 +; AVX512BW-NEXT: vpsrld $16, %zmm0, %zmm0 +; AVX512BW-NEXT: vpmaddwd %zmm1, %zmm0, %zmm0 +; AVX512BW-NEXT: vpsrld $16, %zmm0, %zmm0 +; AVX512BW-NEXT: vpmovdw %zmm0, %ymm0 +; AVX512BW-NEXT: retq %a1 = ashr <16 x i32> %a, %b1 = ashr <16 x i32> %b, %c = mul <16 x i32> %a1, %b1 diff --git a/llvm/test/CodeGen/X86/tagged-globals-pic.ll b/llvm/test/CodeGen/X86/tagged-globals-pic.ll new file mode 100644 index 0000000000000000000000000000000000000000..98bf75a5326a1839972a3c4053c4deb78967f54e --- /dev/null +++ b/llvm/test/CodeGen/X86/tagged-globals-pic.ll @@ -0,0 +1,45 @@ +; RUN: llc --relocation-model=pic < %s | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@global = external global i32 +declare void @func() + +define i32* @global_addr() #0 { + ; CHECK-LABEL: global_addr: + ; CHECK: movq global@GOTPCREL(%rip), %rax + ; CHECK: retq + + ret i32* @global +} + +define i32 @global_load() #0 { + ; CHECK-LABEL: global_load: + ; CHECK: movq global@GOTPCREL(%rip), [[REG:%r[0-9a-z]+]] + ; CHECK: movl ([[REG]]), %eax + ; CHECK: retq + + %load = load i32, i32* @global + ret i32 %load +} + +define void @global_store() #0 { + ; CHECK-LABEL: global_store: + ; CHECK: movq global@GOTPCREL(%rip), [[REG:%r[0-9a-z]+]] + ; CHECK: movl $0, ([[REG]]) + ; CHECK: retq + + store i32 0, i32* @global + ret void +} + +define void ()* @func_addr() #0 { + ; CHECK-LABEL: func_addr: + ; CHECK: movq func@GOTPCREL(%rip), %rax + ; CHECK: retq + + ret void ()* @func +} + +attributes #0 = { "target-features"="+tagged-globals" } diff --git a/llvm/test/CodeGen/X86/tagged-globals-static.ll b/llvm/test/CodeGen/X86/tagged-globals-static.ll new file mode 100644 index 0000000000000000000000000000000000000000..af2fae227ed4d7a5fe39c6b3c1c1c71285776850 --- /dev/null +++ b/llvm/test/CodeGen/X86/tagged-globals-static.ll @@ -0,0 +1,45 @@ +; RUN: llc --relocation-model=static < %s | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@global = external dso_local global i32 +declare dso_local void @func() + +define i32* @global_addr() #0 { + ; CHECK-LABEL: global_addr: + ; CHECK: movq global@GOTPCREL(%rip), %rax + ; CHECK: retq + + ret i32* @global +} + +define i32 @global_load() #0 { + ; CHECK-LABEL: global_load: + ; CHECK: movq global@GOTPCREL(%rip), [[REG:%r[0-9a-z]+]] + ; CHECK: movl ([[REG]]), %eax + ; CHECK: retq + + %load = load i32, i32* @global + ret i32 %load +} + +define void @global_store() #0 { + ; CHECK-LABEL: global_store: + ; CHECK: movq global@GOTPCREL(%rip), [[REG:%r[0-9a-z]+]] + ; CHECK: movl $0, ([[REG]]) + ; CHECK: retq + + store i32 0, i32* @global + ret void +} + +define void ()* @func_addr() #0 { + ; CHECK-LABEL: func_addr: + ; CHECK: movl $func, %eax + ; CHECK: retq + + ret void ()* @func +} + +attributes #0 = { "target-features"="+tagged-globals" } diff --git a/llvm/test/CodeGen/X86/testb-je-fusion.ll b/llvm/test/CodeGen/X86/testb-je-fusion.ll index 5a511cb9f826eb5258a8156bddab1337aff6b873..8fe9eb46f2763ec1ddf8ee8e1c2ce607f64c06ad 100644 --- a/llvm/test/CodeGen/X86/testb-je-fusion.ll +++ b/llvm/test/CodeGen/X86/testb-je-fusion.ll @@ -1,84 +1,40 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,-branchfusion -post-RA-scheduler=0 | FileCheck %s --check-prefix=NOFUSION_NOPOSTRA -; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,+branchfusion -post-RA-scheduler=0 | FileCheck %s --check-prefixes=BRANCHFUSION_NOPOSTRA,BRANCHFUSIONONLY_NOPOSTRA -; RUN: llc < %s -mtriple=x86_64-- -mattr=+macrofusion,-branchfusion -post-RA-scheduler=0 | FileCheck %s --check-prefixes=BRANCHFUSION_NOPOSTRA,MACROFUSION_NOPOSTRA -; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,-branchfusion -post-RA-scheduler=1 | FileCheck %s --check-prefix=NOFUSION_POSTRA -; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,+branchfusion -post-RA-scheduler=1 | FileCheck %s --check-prefix=BRANCHFUSION_POSTRA -; RUN: llc < %s -mtriple=x86_64-- -mattr=+macrofusion,-branchfusion -post-RA-scheduler=1 | FileCheck %s --check-prefix=BRANCHFUSION_POSTRA -; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,-branchfusion -enable-misched=0 -misched-postra=1 -enable-post-misched | FileCheck %s --check-prefix=NOFUSION_MISCHEDPOSTRA -; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,+branchfusion -enable-misched=0 -misched-postra=1 -enable-post-misched | FileCheck %s --check-prefix=BRANCHFUSION_MISCHEDPOSTRA -; RUN: llc < %s -mtriple=x86_64-- -mattr=+macrofusion,-branchfusion -enable-misched=0 -misched-postra=1 -enable-post-misched | FileCheck %s --check-prefix=BRANCHFUSION_MISCHEDPOSTRA +; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,-branchfusion -post-RA-scheduler=0 | FileCheck %s --check-prefixes=NOFUSION,NOFUSION_NOPOSTRA +; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,+branchfusion -post-RA-scheduler=0 | FileCheck %s --check-prefixes=FUSION,BRANCHFUSIONONLY_NOPOSTRA +; RUN: llc < %s -mtriple=x86_64-- -mattr=+macrofusion,-branchfusion -post-RA-scheduler=0 | FileCheck %s --check-prefixes=FUSION,MACROFUSION_NOPOSTRA +; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,-branchfusion -post-RA-scheduler=1 | FileCheck %s --check-prefixes=NOFUSION,NOFUSION_POSTRA +; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,+branchfusion -post-RA-scheduler=1 | FileCheck %s --check-prefixes=FUSION,BRANCHFUSION_POSTRA +; RUN: llc < %s -mtriple=x86_64-- -mattr=+macrofusion,-branchfusion -post-RA-scheduler=1 | FileCheck %s --check-prefixes=FUSION,BRANCHFUSION_POSTRA +; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,-branchfusion -enable-misched=0 -misched-postra=1 -enable-post-misched | FileCheck %s --check-prefixes=NOFUSION,NOFUSION_MISCHEDPOSTRA +; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,+branchfusion -enable-misched=0 -misched-postra=1 -enable-post-misched | FileCheck %s --check-prefixes=FUSION,BRANCHFUSION_MISCHEDPOSTRA +; RUN: llc < %s -mtriple=x86_64-- -mattr=+macrofusion,-branchfusion -enable-misched=0 -misched-postra=1 -enable-post-misched | FileCheck %s --check-prefixes=FUSION,BRANCHFUSION_MISCHEDPOSTRA ; testb should be scheduled right before je to enable macro-fusion. define i32 @macrofuse_test_je(i32 %flags, i8* %p) nounwind { -; NOFUSION_NOPOSTRA-LABEL: macrofuse_test_je: -; NOFUSION_NOPOSTRA: # %bb.0: # %entry -; NOFUSION_NOPOSTRA-NEXT: xorl %eax, %eax -; NOFUSION_NOPOSTRA-NEXT: testl $512, %edi # imm = 0x200 -; NOFUSION_NOPOSTRA-NEXT: movb $1, (%rsi) -; NOFUSION_NOPOSTRA-NEXT: je .LBB0_2 -; NOFUSION_NOPOSTRA-NEXT: # %bb.1: # %if.then -; NOFUSION_NOPOSTRA-NEXT: movl $1, %eax -; NOFUSION_NOPOSTRA-NEXT: .LBB0_2: # %if.end -; NOFUSION_NOPOSTRA-NEXT: retq -; -; BRANCHFUSION_NOPOSTRA-LABEL: macrofuse_test_je: -; BRANCHFUSION_NOPOSTRA: # %bb.0: # %entry -; BRANCHFUSION_NOPOSTRA-NEXT: xorl %eax, %eax -; BRANCHFUSION_NOPOSTRA-NEXT: movb $1, (%rsi) -; BRANCHFUSION_NOPOSTRA-NEXT: testl $512, %edi # imm = 0x200 -; BRANCHFUSION_NOPOSTRA-NEXT: je .LBB0_2 -; BRANCHFUSION_NOPOSTRA-NEXT: # %bb.1: # %if.then -; BRANCHFUSION_NOPOSTRA-NEXT: movl $1, %eax -; BRANCHFUSION_NOPOSTRA-NEXT: .LBB0_2: # %if.end -; BRANCHFUSION_NOPOSTRA-NEXT: retq +; NOFUSION-LABEL: macrofuse_test_je: +; NOFUSION: # %bb.0: # %entry +; NOFUSION-NEXT: xorl %eax, %eax +; NOFUSION-NEXT: testl $512, %edi # imm = 0x200 +; NOFUSION-NEXT: movb $1, (%rsi) +; NOFUSION-NEXT: je .LBB0_2 +; NOFUSION-NEXT: # %bb.1: # %if.then +; NOFUSION-NEXT: movl $1, %eax +; NOFUSION-NEXT: .LBB0_2: # %if.end +; NOFUSION-NEXT: retq ; -; NOFUSION_POSTRA-LABEL: macrofuse_test_je: -; NOFUSION_POSTRA: # %bb.0: # %entry -; NOFUSION_POSTRA-NEXT: xorl %eax, %eax -; NOFUSION_POSTRA-NEXT: testl $512, %edi # imm = 0x200 -; NOFUSION_POSTRA-NEXT: movb $1, (%rsi) -; NOFUSION_POSTRA-NEXT: je .LBB0_2 -; NOFUSION_POSTRA-NEXT: # %bb.1: # %if.then -; NOFUSION_POSTRA-NEXT: movl $1, %eax -; NOFUSION_POSTRA-NEXT: .LBB0_2: # %if.end -; NOFUSION_POSTRA-NEXT: retq -; -; BRANCHFUSION_POSTRA-LABEL: macrofuse_test_je: -; BRANCHFUSION_POSTRA: # %bb.0: # %entry -; BRANCHFUSION_POSTRA-NEXT: xorl %eax, %eax -; BRANCHFUSION_POSTRA-NEXT: movb $1, (%rsi) -; BRANCHFUSION_POSTRA-NEXT: testl $512, %edi # imm = 0x200 -; BRANCHFUSION_POSTRA-NEXT: je .LBB0_2 -; BRANCHFUSION_POSTRA-NEXT: # %bb.1: # %if.then -; BRANCHFUSION_POSTRA-NEXT: movl $1, %eax -; BRANCHFUSION_POSTRA-NEXT: .LBB0_2: # %if.end -; BRANCHFUSION_POSTRA-NEXT: retq -; -; NOFUSION_MISCHEDPOSTRA-LABEL: macrofuse_test_je: -; NOFUSION_MISCHEDPOSTRA: # %bb.0: # %entry -; NOFUSION_MISCHEDPOSTRA-NEXT: xorl %eax, %eax -; NOFUSION_MISCHEDPOSTRA-NEXT: testl $512, %edi # imm = 0x200 -; NOFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi) -; NOFUSION_MISCHEDPOSTRA-NEXT: je .LBB0_2 -; NOFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then -; NOFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax -; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB0_2: # %if.end -; NOFUSION_MISCHEDPOSTRA-NEXT: retq -; -; BRANCHFUSION_MISCHEDPOSTRA-LABEL: macrofuse_test_je: -; BRANCHFUSION_MISCHEDPOSTRA: # %bb.0: # %entry -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: xorl %eax, %eax -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi) -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: testl $512, %edi # imm = 0x200 -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: je .LBB0_2 -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: .LBB0_2: # %if.end -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: retq +; FUSION-LABEL: macrofuse_test_je: +; FUSION: # %bb.0: # %entry +; FUSION-NEXT: xorl %eax, %eax +; FUSION-NEXT: movb $1, (%rsi) +; FUSION-NEXT: testl $512, %edi # imm = 0x200 +; FUSION-NEXT: je .LBB0_2 +; FUSION-NEXT: # %bb.1: # %if.then +; FUSION-NEXT: movl $1, %eax +; FUSION-NEXT: .LBB0_2: # %if.end +; FUSION-NEXT: retq entry: %and = and i32 %flags, 512 %tobool = icmp eq i32 %and, 0 @@ -94,77 +50,29 @@ if.end: } define i32 @macrofuse_cmp_je(i32 %flags, i8* %p) nounwind { -; NOFUSION_NOPOSTRA-LABEL: macrofuse_cmp_je: -; NOFUSION_NOPOSTRA: # %bb.0: # %entry -; NOFUSION_NOPOSTRA-NEXT: cmpl $512, %edi # imm = 0x200 -; NOFUSION_NOPOSTRA-NEXT: movb $1, (%rsi) -; NOFUSION_NOPOSTRA-NEXT: je .LBB1_1 -; NOFUSION_NOPOSTRA-NEXT: # %bb.2: # %if.then -; NOFUSION_NOPOSTRA-NEXT: movl $1, %eax -; NOFUSION_NOPOSTRA-NEXT: retq -; NOFUSION_NOPOSTRA-NEXT: .LBB1_1: -; NOFUSION_NOPOSTRA-NEXT: xorl %eax, %eax -; NOFUSION_NOPOSTRA-NEXT: retq -; -; BRANCHFUSION_NOPOSTRA-LABEL: macrofuse_cmp_je: -; BRANCHFUSION_NOPOSTRA: # %bb.0: # %entry -; BRANCHFUSION_NOPOSTRA-NEXT: movb $1, (%rsi) -; BRANCHFUSION_NOPOSTRA-NEXT: cmpl $512, %edi # imm = 0x200 -; BRANCHFUSION_NOPOSTRA-NEXT: je .LBB1_1 -; BRANCHFUSION_NOPOSTRA-NEXT: # %bb.2: # %if.then -; BRANCHFUSION_NOPOSTRA-NEXT: movl $1, %eax -; BRANCHFUSION_NOPOSTRA-NEXT: retq -; BRANCHFUSION_NOPOSTRA-NEXT: .LBB1_1: -; BRANCHFUSION_NOPOSTRA-NEXT: xorl %eax, %eax -; BRANCHFUSION_NOPOSTRA-NEXT: retq +; NOFUSION-LABEL: macrofuse_cmp_je: +; NOFUSION: # %bb.0: # %entry +; NOFUSION-NEXT: cmpl $512, %edi # imm = 0x200 +; NOFUSION-NEXT: movb $1, (%rsi) +; NOFUSION-NEXT: je .LBB1_1 +; NOFUSION-NEXT: # %bb.2: # %if.then +; NOFUSION-NEXT: movl $1, %eax +; NOFUSION-NEXT: retq +; NOFUSION-NEXT: .LBB1_1: +; NOFUSION-NEXT: xorl %eax, %eax +; NOFUSION-NEXT: retq ; -; NOFUSION_POSTRA-LABEL: macrofuse_cmp_je: -; NOFUSION_POSTRA: # %bb.0: # %entry -; NOFUSION_POSTRA-NEXT: cmpl $512, %edi # imm = 0x200 -; NOFUSION_POSTRA-NEXT: movb $1, (%rsi) -; NOFUSION_POSTRA-NEXT: je .LBB1_1 -; NOFUSION_POSTRA-NEXT: # %bb.2: # %if.then -; NOFUSION_POSTRA-NEXT: movl $1, %eax -; NOFUSION_POSTRA-NEXT: retq -; NOFUSION_POSTRA-NEXT: .LBB1_1: -; NOFUSION_POSTRA-NEXT: xorl %eax, %eax -; NOFUSION_POSTRA-NEXT: retq -; -; BRANCHFUSION_POSTRA-LABEL: macrofuse_cmp_je: -; BRANCHFUSION_POSTRA: # %bb.0: # %entry -; BRANCHFUSION_POSTRA-NEXT: movb $1, (%rsi) -; BRANCHFUSION_POSTRA-NEXT: cmpl $512, %edi # imm = 0x200 -; BRANCHFUSION_POSTRA-NEXT: je .LBB1_1 -; BRANCHFUSION_POSTRA-NEXT: # %bb.2: # %if.then -; BRANCHFUSION_POSTRA-NEXT: movl $1, %eax -; BRANCHFUSION_POSTRA-NEXT: retq -; BRANCHFUSION_POSTRA-NEXT: .LBB1_1: -; BRANCHFUSION_POSTRA-NEXT: xorl %eax, %eax -; BRANCHFUSION_POSTRA-NEXT: retq -; -; NOFUSION_MISCHEDPOSTRA-LABEL: macrofuse_cmp_je: -; NOFUSION_MISCHEDPOSTRA: # %bb.0: # %entry -; NOFUSION_MISCHEDPOSTRA-NEXT: cmpl $512, %edi # imm = 0x200 -; NOFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi) -; NOFUSION_MISCHEDPOSTRA-NEXT: je .LBB1_1 -; NOFUSION_MISCHEDPOSTRA-NEXT: # %bb.2: # %if.then -; NOFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax -; NOFUSION_MISCHEDPOSTRA-NEXT: retq -; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB1_1: -; NOFUSION_MISCHEDPOSTRA-NEXT: xorl %eax, %eax -; NOFUSION_MISCHEDPOSTRA-NEXT: retq -; -; BRANCHFUSION_MISCHEDPOSTRA-LABEL: macrofuse_cmp_je: -; BRANCHFUSION_MISCHEDPOSTRA: # %bb.0: # %entry -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi) -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: cmpl $512, %edi # imm = 0x200 -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: je .LBB1_1 -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: # %bb.2: # %if.then -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: retq -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: .LBB1_1: -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: xorl %eax, %eax -; BRANCHFUSION_MISCHEDPOSTRA-NEXT: retq +; FUSION-LABEL: macrofuse_cmp_je: +; FUSION: # %bb.0: # %entry +; FUSION-NEXT: movb $1, (%rsi) +; FUSION-NEXT: cmpl $512, %edi # imm = 0x200 +; FUSION-NEXT: je .LBB1_1 +; FUSION-NEXT: # %bb.2: # %if.then +; FUSION-NEXT: movl $1, %eax +; FUSION-NEXT: retq +; FUSION-NEXT: .LBB1_1: +; FUSION-NEXT: xorl %eax, %eax +; FUSION-NEXT: retq entry: %sub = sub i32 %flags, 512 %tobool = icmp eq i32 %sub, 0 diff --git a/llvm/test/DebugInfo/ARM/rwpi.ll b/llvm/test/DebugInfo/ARM/rwpi.ll new file mode 100644 index 0000000000000000000000000000000000000000..c8f73ba4803d26aac434f444ee37e685bdaa2bb3 --- /dev/null +++ b/llvm/test/DebugInfo/ARM/rwpi.ll @@ -0,0 +1,34 @@ +; RUN: llc -mtriple armv7-linux -relocation-model=rwpi -o - %s | FileCheck %s +; RUN: llc -mtriple armv7-linux -relocation-model=ropi-rwpi -o - %s | FileCheck %s + +@global = global i32 5, align 4, !dbg !0 + +; 8 bytes of data +; CHECK: .byte 8 @ DW_AT_location +; DW_OP_const4u +; CHECK-NEXT: .byte 12 +; relocation offset +; CHECK-NEXT: .long global(sbrel) +; DW_OP_breg9 +; CHECK-NEXT: .byte 121 +; offset from breg9 +; CHECK-NEXT: .byte 0 +; DW_OP_plus +; CHECK-NEXT: .byte 34 + +!llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!6, !7, !8, !9, !10} +!llvm.ident = !{!11} + +!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) +!1 = distinct !DIGlobalVariable(name: "global", scope: !2, file: !3, line: 1, type: !5, isLocal: false, isDefinition: true) +!2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang version 14.0.0 (https://github.com/llvm/llvm-project.git 9f5c70c7ad404f0cb52416a0574d9e48d520be5d)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: !4, splitDebugInlining: false, nameTableKind: None) +!3 = !DIFile(filename: "rwpi.c", directory: "/tmp") +!4 = !{!0} +!5 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!6 = !{i32 7, !"Dwarf Version", i32 4} +!7 = !{i32 2, !"Debug Info Version", i32 3} +!8 = !{i32 1, !"wchar_size", i32 4} +!9 = !{i32 1, !"min_enum_size", i32 4} +!10 = !{i32 7, !"frame-pointer", i32 2} +!11 = !{!"clang version 14.0.0 (https://github.com/llvm/llvm-project.git 9f5c70c7ad404f0cb52416a0574d9e48d520be5d)"} diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_launder_invariant.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_launder_invariant.ll index d3d57fda6771b1d14a2e7563a00e9311415bc526..6dd2c442244d879eb639a7d340aef917744e11c4 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_launder_invariant.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_launder_invariant.ll @@ -1,7 +1,7 @@ ; Make sure MSan handles llvm.launder.invariant.group correctly. -; RUN: opt < %s -msan -msan-kernel=1 -O1 -S | FileCheck -check-prefixes=CHECK %s -; RUN: opt < %s -msan -O1 -S | FileCheck -check-prefixes=CHECK %s +; RUN: opt < %s -passes='function(msan),default' -msan-kernel=1 -S | FileCheck -check-prefixes=CHECK %s +; RUN: opt < %s -passes='function(msan),default' -S | FileCheck -check-prefixes=CHECK %s target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_strip_invariant.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_strip_invariant.ll index aa7745f38165b1bcf2c6dbe1f5d218b2beef8cea..063ca6ea7dc42f8bf24961dbe77612c380dd9376 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_strip_invariant.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_strip_invariant.ll @@ -1,7 +1,7 @@ ; Make sure MSan handles llvm.launder.invariant.group correctly. -; RUN: opt < %s -msan -msan-kernel=1 -O1 -S | FileCheck -check-prefixes=CHECK %s -; RUN: opt < %s -msan -O1 -S | FileCheck -check-prefixes=CHECK %s +; RUN: opt < %s -passes='function(msan),default' -msan-kernel=1 -S | FileCheck -check-prefixes=CHECK %s +; RUN: opt < %s -passes='function(msan),default' -S | FileCheck -check-prefixes=CHECK %s target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Other/new-pm-eager-invalidate.ll b/llvm/test/Other/new-pm-eager-invalidate.ll new file mode 100644 index 0000000000000000000000000000000000000000..188ac9bcaf0393ee5542792d1c5158750e969c20 --- /dev/null +++ b/llvm/test/Other/new-pm-eager-invalidate.ll @@ -0,0 +1,8 @@ +; RUN: opt -disable-verify -debug-pass-manager -passes='function(require)' -disable-output -eagerly-invalidate-analyses %s 2>&1 | FileCheck %s +; RUN: opt -disable-verify -debug-pass-manager -passes='cgscc(function(require))' -disable-output -eagerly-invalidate-analyses %s 2>&1 | FileCheck %s + +; CHECK: Invalidating analysis: NoOpFunctionAnalysis + +define void @foo() { + unreachable +} diff --git a/llvm/test/Other/opt-On.ll b/llvm/test/Other/opt-On.ll new file mode 100644 index 0000000000000000000000000000000000000000..4bbbd0ff68227a7bb0ae352d149b0761b9826721 --- /dev/null +++ b/llvm/test/Other/opt-On.ll @@ -0,0 +1,19 @@ +; RUN: not opt -O1 -O2 < %s 2>&1 | FileCheck %s --check-prefix=MULTIPLE +; RUN: not opt -O1 -passes='no-op-module' < %s 2>&1 | FileCheck %s --check-prefix=BOTH +; RUN: opt -O0 < %s -S 2>&1 | FileCheck %s --check-prefix=OPT +; RUN: opt -O1 < %s -S 2>&1 | FileCheck %s --check-prefix=OPT +; RUN: opt -O2 < %s -S 2>&1 | FileCheck %s --check-prefix=OPT +; RUN: opt -O3 < %s -S 2>&1 | FileCheck %s --check-prefix=OPT +; RUN: opt -Os < %s -S 2>&1 | FileCheck %s --check-prefix=OPT +; RUN: opt -Oz < %s -S 2>&1 | FileCheck %s --check-prefix=OPT +; RUN: opt -O2 -debug-pass-manager -disable-output < %s 2>&1 | FileCheck %s --check-prefix=AA + +; MULTIPLE: Cannot specify multiple -O# +; BOTH: Cannot specify -O# and --passes= +; OPT: define void @f +; Make sure we run the default AA pipeline with `opt -O#` +; AA: Running analysis: ScopedNoAliasAA + +define void @f() { + unreachable +} diff --git a/llvm/test/Transforms/GlobalOpt/long-compilation-global-sra.ll b/llvm/test/Transforms/GlobalOpt/long-compilation-global-sra.ll index 69a358edcadb153595dbd946d4b4e1655a580643..c71ac3258c4034e583942f6d9a6ad59199cc75ea 100644 --- a/llvm/test/Transforms/GlobalOpt/long-compilation-global-sra.ll +++ b/llvm/test/Transforms/GlobalOpt/long-compilation-global-sra.ll @@ -1,4 +1,4 @@ -; RUN: opt %s --O0 -globalopt -S -o - +; RUN: opt %s -passes='default,globalopt' -S -o - ; This is a regression test against very slow execution... ; In bad case it should fail by timeout. diff --git a/llvm/test/Transforms/Inline/cgscc-inline-replay.ll b/llvm/test/Transforms/Inline/cgscc-inline-replay.ll index 82f4fc20bad20107134ef402ec4c29d53d30e7c6..9bdd0e32e9cbe4d6658043ab109a2e1d9870912a 100644 --- a/llvm/test/Transforms/Inline/cgscc-inline-replay.ll +++ b/llvm/test/Transforms/Inline/cgscc-inline-replay.ll @@ -1,8 +1,32 @@ ;; Note that this needs new pass manager for now. Passing `-cgscc-inline-replay` to legacy pass manager is a no-op. -;; Check replay inline decisions -; RUN: opt < %s -passes=inline -pass-remarks=inline -S 2>&1 | FileCheck -check-prefix=DEFAULT %s -; RUN: opt < %s -passes=inline -cgscc-inline-replay=%S/Inputs/cgscc-inline-replay.txt -pass-remarks=inline -S 2>&1 | FileCheck -check-prefix=REPLAY %s +;; Check baseline inline decisions +; RUN: opt < %s -passes=inline -pass-remarks=inline --disable-output 2>&1 | FileCheck -check-prefix=DEFAULT %s + +;; Check module-scope replay inline decisions +; RUN: opt < %s -passes=inline -cgscc-inline-replay=%S/Inputs/cgscc-inline-replay.txt -cgscc-inline-replay-scope=Module -pass-remarks=inline --disable-output 2>&1 | FileCheck -check-prefix=REPLAY %s + +;; Check function-scope inline replay decisions +; RUN: opt < %s -passes=inline -cgscc-inline-replay=%S/Inputs/cgscc-inline-replay.txt -cgscc-inline-replay-scope=Function -pass-remarks=inline --disable-output 2>&1 | FileCheck -check-prefix=REPLAY-FUNCTION %s + +;; Check behavior on non-existent replay file +; RUN: not opt < %s -passes=inline -cgscc-inline-replay=%S -pass-remarks=inline --disable-output 2>&1 | FileCheck -check-prefix=REPLAY-ERROR %s + +;; Check scope inlining errors out on non inputs +; RUN: not opt < %s -passes=inline -cgscc-inline-replay=%S/Inputs/cgscc-inline-replay.txt -cgscc-inline-replay-scope=function -pass-remarks=inline --disable-output 2>&1 | FileCheck -check-prefix=REPLAY-ERROR-SCOPE %s + +; DEFAULT: '_Z3subii' inlined into '_Z3sumii' with (cost={{[-0-9]+}} +; DEFAULT: '_Z3sumii' inlined into 'main' with (cost={{[-0-9]+}} +; DEFAULT-NOT: '_Z3subii' inlined into 'main' + +; REPLAY: '_Z3sumii' inlined into 'main' with (cost=always) +; REPLAY: '_Z3subii' inlined into 'main' with (cost=always) + +; REPLAY-FUNCTION: '_Z3subii' inlined into '_Z3sumii' with (cost={{[-0-9]+}} +; REPLAY-FUNCTION: '_Z3sumii' inlined into 'main' with (cost=always) + +; REPLAY-ERROR: error: Could not open remarks file: +; REPLAY-ERROR-SCOPE: for the --cgscc-inline-replay-scope option: Cannot find option named 'function'! @.str = private unnamed_addr constant [11 x i8] c"sum is %d\0A\00", align 1 @@ -109,11 +133,3 @@ attributes #0 = { "use-sample-profile" } !24 = !DILexicalBlockFile(scope: !18, file: !1, discriminator: 6) !25 = !DILocation(line: 11, scope: !12) !26 = !DILocation(line: 12, scope: !12) - -; DEFAULT: '_Z3subii' inlined into '_Z3sumii' -; DEFAULT: '_Z3sumii' inlined into 'main' -; DEFAULT-NOT: '_Z3subii' inlined into 'main' - -; REPLAY: '_Z3sumii' inlined into 'main' -; REPLAY: '_Z3subii' inlined into 'main' -; REPLAY-NOT: '_Z3subii' inlined into '_Z3sumii' diff --git a/llvm/test/Transforms/Inline/devirtualize-3.ll b/llvm/test/Transforms/Inline/devirtualize-3.ll index 987463a03766281df992d317c1fdea5c54d09345..ea6d39af365b304e5125fb685ccbab067b19dee9 100644 --- a/llvm/test/Transforms/Inline/devirtualize-3.ll +++ b/llvm/test/Transforms/Inline/devirtualize-3.ll @@ -1,4 +1,3 @@ -; RUN: opt -basic-aa -S -O2 < %s | FileCheck %s ; RUN: opt -aa-pipeline=basic-aa -S -passes='default' < %s | FileCheck %s ; PR5009 diff --git a/llvm/test/Transforms/Inline/inline-cost-annotation-pass.ll b/llvm/test/Transforms/Inline/inline-cost-annotation-pass.ll index 73b8a0bb0c0b38509dbd3fc28ac3643f88eb77df..17b2e1581e6e7eb5fca1737abfad053d5217b4c1 100644 --- a/llvm/test/Transforms/Inline/inline-cost-annotation-pass.ll +++ b/llvm/test/Transforms/Inline/inline-cost-annotation-pass.ll @@ -20,6 +20,8 @@ ; CHECK: ContainsNoDuplicateCall: {{.*}} ; CHECK: Cost: {{.*}} ; CHECK: Threshold: {{.*}} +; CHECK-EMPTY: +; CHECK: Analyzing call of foo... (caller:main) define i8 addrspace(1)** @foo() { %1 = inttoptr i64 754974720 to i8 addrspace(1)** @@ -28,5 +30,6 @@ define i8 addrspace(1)** @foo() { define i8 addrspace(1)** @main() { %1 = call i8 addrspace(1)** @foo() + %2 = call i8 addrspace(1)** @foo() ret i8 addrspace(1)** %1 } diff --git a/llvm/test/Transforms/LoopDistribute/basic-with-memchecks.ll b/llvm/test/Transforms/LoopDistribute/basic-with-memchecks.ll index 35a0f75808d2d327763cfd00efae7c92583acbe9..e8c03ad2752ed61093eca0693c402229818d62dc 100644 --- a/llvm/test/Transforms/LoopDistribute/basic-with-memchecks.ll +++ b/llvm/test/Transforms/LoopDistribute/basic-with-memchecks.ll @@ -54,7 +54,7 @@ entry: ; CHECK: = icmp ; CHECK-NOT: = icmp -; CHECK: br i1 %memcheck.conflict, label %for.body.ph.lver.orig, label %for.body.ph.ldist1 +; CHECK: br i1 %conflict.rdx25, label %for.body.ph.lver.orig, label %for.body.ph.ldist1 ; The non-distributed loop that the memchecks fall back on. diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll index f63effd6cda10e106b55cf95ccf6c1730cf9e91d..39b91e2ef5cae9d1bfc6d778a2b004dc0c79afb5 100644 --- a/llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll +++ b/llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll @@ -1,5 +1,5 @@ -; RUN: opt < %s -debug-only=loop-vectorize -loop-vectorize -vectorizer-maximize-bandwidth -O2 -mtriple=powerpc64-unknown-linux -S -mcpu=pwr8 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-PWR8 -; RUN: opt < %s -debug-only=loop-vectorize -loop-vectorize -vectorizer-maximize-bandwidth -O2 -mtriple=powerpc64le-unknown-linux -S -mcpu=pwr9 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-PWR9 +; RUN: opt < %s -debug-only=loop-vectorize -passes='function(loop-vectorize),default' -vectorizer-maximize-bandwidth -mtriple=powerpc64-unknown-linux -S -mcpu=pwr8 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-PWR8 +; RUN: opt < %s -debug-only=loop-vectorize -passes='function(loop-vectorize),default' -vectorizer-maximize-bandwidth -mtriple=powerpc64le-unknown-linux -S -mcpu=pwr9 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-PWR9 ; REQUIRES: asserts @a = global [1024 x i8] zeroinitializer, align 16 diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll index f498679402d198cdd14e7af26be50b7d1f354365..c6b06dcfe45d9458fa08ca020ec137a5a1a1839c 100644 --- a/llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll +++ b/llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -vector-library=MASSV -force-vector-interleave=1 \ -; RUN: -vectorizer-maximize-bandwidth -O2 -inject-tli-mappings -loop-vectorize \ +; RUN: -vectorizer-maximize-bandwidth -passes='default,inject-tli-mappings,loop-vectorize' \ ; RUN: -mtriple=powerpc64le-unknown-linux -S -mcpu=pwr9 2>&1 | FileCheck %s define dso_local double @test(float* %Arr) { diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/epi-daxpy.ll b/llvm/test/Transforms/LoopVectorize/RISCV/epi-daxpy.ll index e2e0e8d47e02509d6e9cb10ad12414775068db37..e63370fe717a338a7e532247e51b4fcc77676e12 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/epi-daxpy.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/epi-daxpy.ll @@ -30,8 +30,7 @@ define dso_local void @axpy_ref(double %a, double* nocapture readonly %dx, doubl ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult i8* [[DY1]], [[SCEVGEP45]] ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult i8* [[DX3]], [[SCEVGEP2]] ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] -; CHECK-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[FOUND_CONFLICT]], true -; CHECK-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 8 @@ -102,8 +101,7 @@ define dso_local void @axpy_ref(double %a, double* nocapture readonly %dx, doubl ; CHECK1-NEXT: [[BOUND0:%.*]] = icmp ult i8* [[DY1]], [[SCEVGEP45]] ; CHECK1-NEXT: [[BOUND1:%.*]] = icmp ult i8* [[DX3]], [[SCEVGEP2]] ; CHECK1-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] -; CHECK1-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[FOUND_CONFLICT]], true -; CHECK1-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK1-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; CHECK1: vector.ph: ; CHECK1-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64() ; CHECK1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[WIDE_TRIP_COUNT]], [[TMP1]] diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll b/llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll index 9313a5ec64aaafdad246267e22b05855f5424cbb..3e4c6009aa741cc72cc7272c6d8fccea86c09094 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll @@ -34,8 +34,7 @@ define void @foo4(double* nocapture %A, double* nocapture readonly %B, i32* noca ; RV32-NEXT: [[BOUND110:%.*]] = icmp ult i8* [[B6]], [[SCEVGEP2]] ; RV32-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; RV32-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; RV32-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; RV32-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; RV32-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; RV32: vector.ph: ; RV32-NEXT: br label [[VECTOR_BODY:%.*]] ; RV32: vector.body: @@ -103,8 +102,7 @@ define void @foo4(double* nocapture %A, double* nocapture readonly %B, i32* noca ; RV64-NEXT: [[BOUND110:%.*]] = icmp ult i8* [[B6]], [[SCEVGEP2]] ; RV64-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; RV64-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; RV64-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; RV64-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; RV64-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; RV64: vector.ph: ; RV64-NEXT: br label [[VECTOR_BODY:%.*]] ; RV64: vector.body: diff --git a/llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll b/llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll index 2296fb1b6a8a97d5a622476a93bbb718861c0d11..254a4c301483899a74f1d75b148a6bad149d3e05 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -O3 -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -keep-loops=false -mcpu=core-avx2 -mtriple=x86_64-unknown-linux-gnu -S | FileCheck --check-prefix AUTO_VEC %s +; RUN: opt < %s -passes='default,simplifycfg' -simplifycfg-require-and-preserve-domtree=1 -keep-loops=false -mcpu=core-avx2 -mtriple=x86_64-unknown-linux-gnu -S | FileCheck --check-prefix AUTO_VEC %s target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll b/llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll index b058f52540807d96da99f85a2b5acc3a9d63e441..2a6d929366f65c7896b92748ea9ada296cea6f29 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll @@ -38,8 +38,7 @@ define void @foo1(i32* nocapture %A, i32* nocapture readonly %B, i32* nocapture ; AVX1-NEXT: [[BOUND110:%.*]] = icmp ult i8* [[B6]], [[SCEVGEP2]] ; AVX1-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; AVX1-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; AVX1-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; AVX1-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; AVX1-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; AVX1: vector.ph: ; AVX1-NEXT: br label [[VECTOR_BODY:%.*]] ; AVX1: vector.body: @@ -108,8 +107,7 @@ define void @foo1(i32* nocapture %A, i32* nocapture readonly %B, i32* nocapture ; AVX2-NEXT: [[BOUND110:%.*]] = icmp ult i8* [[B6]], [[SCEVGEP2]] ; AVX2-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; AVX2-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; AVX2-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; AVX2-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; AVX2-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; AVX2: vector.ph: ; AVX2-NEXT: br label [[VECTOR_BODY:%.*]] ; AVX2: vector.body: @@ -223,8 +221,7 @@ define void @foo1(i32* nocapture %A, i32* nocapture readonly %B, i32* nocapture ; AVX512-NEXT: [[BOUND110:%.*]] = icmp ult i8* [[B6]], [[SCEVGEP2]] ; AVX512-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; AVX512-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; AVX512-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; AVX512-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[VEC_EPILOG_SCALAR_PH]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] +; AVX512-NEXT: br i1 [[CONFLICT_RDX]], label [[VEC_EPILOG_SCALAR_PH]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] ; AVX512: vector.main.loop.iter.check: ; AVX512-NEXT: br i1 false, label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]] ; AVX512: vector.ph: @@ -400,8 +397,7 @@ define void @foo1_addrspace1(i32 addrspace(1)* nocapture %A, i32 addrspace(1)* n ; AVX1-NEXT: [[BOUND110:%.*]] = icmp ult i8 addrspace(1)* [[B6]], [[SCEVGEP2]] ; AVX1-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; AVX1-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; AVX1-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; AVX1-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; AVX1-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; AVX1: vector.ph: ; AVX1-NEXT: br label [[VECTOR_BODY:%.*]] ; AVX1: vector.body: @@ -470,8 +466,7 @@ define void @foo1_addrspace1(i32 addrspace(1)* nocapture %A, i32 addrspace(1)* n ; AVX2-NEXT: [[BOUND110:%.*]] = icmp ult i8 addrspace(1)* [[B6]], [[SCEVGEP2]] ; AVX2-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; AVX2-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; AVX2-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; AVX2-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; AVX2-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; AVX2: vector.ph: ; AVX2-NEXT: br label [[VECTOR_BODY:%.*]] ; AVX2: vector.body: @@ -585,8 +580,7 @@ define void @foo1_addrspace1(i32 addrspace(1)* nocapture %A, i32 addrspace(1)* n ; AVX512-NEXT: [[BOUND110:%.*]] = icmp ult i8 addrspace(1)* [[B6]], [[SCEVGEP2]] ; AVX512-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; AVX512-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; AVX512-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; AVX512-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[VEC_EPILOG_SCALAR_PH]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] +; AVX512-NEXT: br i1 [[CONFLICT_RDX]], label [[VEC_EPILOG_SCALAR_PH]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] ; AVX512: vector.main.loop.iter.check: ; AVX512-NEXT: br i1 false, label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]] ; AVX512: vector.ph: @@ -771,8 +765,7 @@ define void @foo2(float* nocapture %A, float* nocapture readonly %B, i32* nocapt ; AVX1-NEXT: [[BOUND110:%.*]] = icmp ult i8* [[B6]], [[SCEVGEP2]] ; AVX1-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; AVX1-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; AVX1-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; AVX1-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; AVX1-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; AVX1: vector.ph: ; AVX1-NEXT: br label [[VECTOR_BODY:%.*]] ; AVX1: vector.body: @@ -843,8 +836,7 @@ define void @foo2(float* nocapture %A, float* nocapture readonly %B, i32* nocapt ; AVX2-NEXT: [[BOUND110:%.*]] = icmp ult i8* [[B6]], [[SCEVGEP2]] ; AVX2-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; AVX2-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; AVX2-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; AVX2-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; AVX2-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; AVX2: vector.ph: ; AVX2-NEXT: br label [[VECTOR_BODY:%.*]] ; AVX2: vector.body: @@ -963,8 +955,7 @@ define void @foo2(float* nocapture %A, float* nocapture readonly %B, i32* nocapt ; AVX512-NEXT: [[BOUND110:%.*]] = icmp ult i8* [[B6]], [[SCEVGEP2]] ; AVX512-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; AVX512-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; AVX512-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; AVX512-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[VEC_EPILOG_SCALAR_PH]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] +; AVX512-NEXT: br i1 [[CONFLICT_RDX]], label [[VEC_EPILOG_SCALAR_PH]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] ; AVX512: vector.main.loop.iter.check: ; AVX512-NEXT: br i1 false, label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]] ; AVX512: vector.ph: @@ -1156,8 +1147,7 @@ define void @foo3(double* nocapture %A, double* nocapture readonly %B, i32* noca ; AVX-NEXT: [[BOUND110:%.*]] = icmp ult i8* [[B6]], [[SCEVGEP2]] ; AVX-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; AVX-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; AVX-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; AVX-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; AVX-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; AVX: vector.ph: ; AVX-NEXT: br label [[VECTOR_BODY:%.*]] ; AVX: vector.body: @@ -1276,8 +1266,7 @@ define void @foo3(double* nocapture %A, double* nocapture readonly %B, i32* noca ; AVX512-NEXT: [[BOUND110:%.*]] = icmp ult i8* [[B6]], [[SCEVGEP2]] ; AVX512-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; AVX512-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; AVX512-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; AVX512-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; AVX512-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; AVX512: vector.ph: ; AVX512-NEXT: br label [[VECTOR_BODY:%.*]] ; AVX512: vector.body: @@ -1461,8 +1450,7 @@ define void @foo4(double* nocapture %A, double* nocapture readonly %B, i32* noca ; AVX512-NEXT: [[BOUND110:%.*]] = icmp ult i8* [[B6]], [[SCEVGEP2]] ; AVX512-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; AVX512-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; AVX512-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; AVX512-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; AVX512-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; AVX512: vector.ph: ; AVX512-NEXT: br label [[VECTOR_BODY:%.*]] ; AVX512: vector.body: @@ -1664,8 +1652,7 @@ define void @foo6(double* nocapture readonly %in, double* nocapture %out, i32 %s ; AVX2-NEXT: [[BOUND110:%.*]] = icmp ult i8* [[IN6]], [[SCEVGEP2]] ; AVX2-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; AVX2-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; AVX2-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; AVX2-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; AVX2-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; AVX2: vector.ph: ; AVX2-NEXT: br label [[VECTOR_BODY:%.*]] ; AVX2: vector.body: @@ -1808,8 +1795,7 @@ define void @foo6(double* nocapture readonly %in, double* nocapture %out, i32 %s ; AVX512-NEXT: [[BOUND110:%.*]] = icmp ult i8* [[IN6]], [[SCEVGEP2]] ; AVX512-NEXT: [[FOUND_CONFLICT11:%.*]] = and i1 [[BOUND09]], [[BOUND110]] ; AVX512-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT11]] -; AVX512-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; AVX512-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; AVX512-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; AVX512: vector.ph: ; AVX512-NEXT: br label [[VECTOR_BODY:%.*]] ; AVX512: vector.body: diff --git a/llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll b/llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll index 84aaf337ff60a5fb47119f2baf637faaa024fbb0..e24ec51fa59528d7e9b5b76a0d6a51c5cb40cc31 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll @@ -1,14 +1,13 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -mcpu=corei7 -O1 -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O1 -; RUN: opt < %s -mcpu=corei7 -O2 -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O2 -; RUN: opt < %s -mcpu=corei7 -O3 -S -unroll-threshold=150 -unroll-allow-partial=0 | FileCheck %s --check-prefix=O3 -; RUN: opt < %s -mcpu=corei7 -O3 -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O3DEFAULT -; RUN: opt < %s -mcpu=corei7 -Os -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=Os -; RUN: opt < %s -mcpu=corei7 -Oz -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=Oz -; RUN: opt < %s -mcpu=corei7 -O1 -loop-vectorize -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O1VEC2 -; RUN: opt < %s -mcpu=corei7 -Oz -loop-vectorize -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=OzVEC2 -; RUN: opt < %s -mcpu=corei7 -O3 -unroll-threshold=150 -vectorize-loops=false -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O3DIS -; RUN: opt < %s -mcpu=corei7 -O1 -loop-vectorize -S -unroll-allow-partial=0 -enable-new-pm=1 | FileCheck %s --check-prefix=O1VEC2 +; RUN: opt < %s -mcpu=corei7 -passes='default' -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O1 +; RUN: opt < %s -mcpu=corei7 -passes='default' -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O2 +; RUN: opt < %s -mcpu=corei7 -passes='default' -S -unroll-threshold=150 -unroll-allow-partial=0 | FileCheck %s --check-prefix=O3 +; RUN: opt < %s -mcpu=corei7 -passes='default' -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O3DEFAULT +; RUN: opt < %s -mcpu=corei7 -passes='default' -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=Os +; RUN: opt < %s -mcpu=corei7 -passes='default' -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=Oz +; RUN: opt < %s -mcpu=corei7 -passes='default,loop-vectorize' -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O1VEC2 +; RUN: opt < %s -mcpu=corei7 -passes='default,loop-vectorize' -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=OzVEC2 +; RUN: opt < %s -mcpu=corei7 -passes='default' -unroll-threshold=150 -vectorize-loops=false -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O3DIS ; This file tests the llvm.loop.vectorize.enable metadata forcing ; vectorization even when optimization levels are too low, or when diff --git a/llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll b/llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll index 81eadef0536fa2d8d570ae9d058c2b07f1a83184..7a6cf203f1622e4ac7b037ba1fdf2141a10f565a 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll @@ -399,8 +399,7 @@ define void @uniform_copy(i32* %A, i32* %B) { ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult i8* [[B1]], [[SCEVGEP45]] ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult i8* [[A3]], [[SCEVGEP2]] ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] -; CHECK-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[FOUND_CONFLICT]], true -; CHECK-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: diff --git a/llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll b/llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll index 5c9077f1d6e07a5fdb6f16cc5893633507e3bb27..37df46fc6718e499e2b91172609db7305c0ad2f7 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -O3 -loop-vectorize -force-vector-interleave=1 -force-vector-width=2 -S < %s | FileCheck %s +; RUN: opt -passes='default,loop-vectorize' -force-vector-interleave=1 -force-vector-width=2 -S < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.7.0" diff --git a/llvm/test/Transforms/LoopVectorize/global_alias.ll b/llvm/test/Transforms/LoopVectorize/global_alias.ll index 7333af3b925406bae1ed2b8ceab7403af4102b08..abf294273ddbc505ab66b68175311baea7f2306a 100644 --- a/llvm/test/Transforms/LoopVectorize/global_alias.ll +++ b/llvm/test/Transforms/LoopVectorize/global_alias.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -O1 -loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -dce -instcombine -S | FileCheck %s +; RUN: opt < %s -passes='default,loop-vectorize,dce,instcombine' -force-vector-interleave=1 -force-vector-width=4 -S | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" diff --git a/llvm/test/Transforms/LoopVectorize/multiple-strides-vectorization.ll b/llvm/test/Transforms/LoopVectorize/multiple-strides-vectorization.ll index c6435fb9412fac854673203a5de2f6231f2702ab..0214fa66c64b642ebd7d3e293e85bdd7b327ad20 100644 --- a/llvm/test/Transforms/LoopVectorize/multiple-strides-vectorization.ll +++ b/llvm/test/Transforms/LoopVectorize/multiple-strides-vectorization.ll @@ -55,8 +55,7 @@ define void @Test(%struct.s* nocapture %obj, i64 %z) #0 { ; CHECK-NEXT: [[BOUND112:%.*]] = icmp ult i8* [[SCEVGEP78]], [[SCEVGEP23]] ; CHECK-NEXT: [[FOUND_CONFLICT13:%.*]] = and i1 [[BOUND011]], [[BOUND112]] ; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT13]] -; CHECK-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[CONFLICT_RDX]], true -; CHECK-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[Z]], 4 ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[Z]], [[N_MOD_VF]] diff --git a/llvm/test/Transforms/LoopVectorize/no_outside_user.ll b/llvm/test/Transforms/LoopVectorize/no_outside_user.ll index f2dd557e80a9c9dded589d6b5c4887a97021a796..c1e2bc1460d6141624a260aa79d77b31f81013e6 100644 --- a/llvm/test/Transforms/LoopVectorize/no_outside_user.ll +++ b/llvm/test/Transforms/LoopVectorize/no_outside_user.ll @@ -334,7 +334,7 @@ for.end: ; preds = %for.body, %entry ; loop ; CHECK-LABEL: sum_arrays_outside_use( ; CHECK-LABEL: vector.memcheck: -; CHECK: br i1 %memcheck.conflict, label %scalar.ph, label %vector.ph +; CHECK: br i1 %conflict.rdx, label %scalar.ph, label %vector.ph ; CHECK-LABEL: vector.body: ; CHECK: %wide.load = load <2 x i32>, <2 x i32>* diff --git a/llvm/test/Transforms/LoopVectorize/pr47343-expander-lcssa-after-cfg-update.ll b/llvm/test/Transforms/LoopVectorize/pr47343-expander-lcssa-after-cfg-update.ll index 23943ab4bc81ca3f055707c0203c4438b4fd6a70..4a5cea67fed30a13d2be9f35bf6d9e860e11070f 100644 --- a/llvm/test/Transforms/LoopVectorize/pr47343-expander-lcssa-after-cfg-update.ll +++ b/llvm/test/Transforms/LoopVectorize/pr47343-expander-lcssa-after-cfg-update.ll @@ -41,8 +41,7 @@ define void @f() { ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult i8* bitcast (i32* @f.e to i8*), [[SCEVGEP]] ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult i8* [[TMP1]], bitcast (i32* getelementptr inbounds (i32, i32* @f.e, i64 1) to i8*) ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] -; CHECK-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[FOUND_CONFLICT]], true -; CHECK-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: diff --git a/llvm/test/Transforms/LoopVectorize/pr50686.ll b/llvm/test/Transforms/LoopVectorize/pr50686.ll index 599b6e544efe0edc1243de6be90eadd5910521c8..2beb01808c1c8540b2c898cdd7115127b1805a3a 100644 --- a/llvm/test/Transforms/LoopVectorize/pr50686.ll +++ b/llvm/test/Transforms/LoopVectorize/pr50686.ll @@ -17,8 +17,7 @@ define void @m(i32* nocapture %p, i32* nocapture %p2, i32 %q) { ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult i8* [[P1]], [[SCEVGEP45]] ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult i8* [[P23]], [[SCEVGEP2]] ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] -; CHECK-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[FOUND_CONFLICT]], true -; CHECK-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: diff --git a/llvm/test/Transforms/LoopVectorize/runtime-check-small-clamped-bounds.ll b/llvm/test/Transforms/LoopVectorize/runtime-check-small-clamped-bounds.ll index 0b4d1f5a468c378a5671beffe845005d64bd8ded..da8163df973cacc2a0ec25fbf6c69e4819f7a8d0 100644 --- a/llvm/test/Transforms/LoopVectorize/runtime-check-small-clamped-bounds.ll +++ b/llvm/test/Transforms/LoopVectorize/runtime-check-small-clamped-bounds.ll @@ -44,8 +44,7 @@ define void @load_clamped_index(i32* %A, i32* %B, i32 %N) { ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult i8* [[B1]], [[SCEVGEP45]] ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult i8* [[A3]], [[SCEVGEP2]] ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] -; CHECK-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[FOUND_CONFLICT]], true -; CHECK-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 2 ; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]] @@ -140,8 +139,7 @@ define void @store_clamped_index(i32* %A, i32* %B, i32 %N) { ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult i8* [[B1]], [[SCEVGEP45]] ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult i8* [[A3]], [[SCEVGEP2]] ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] -; CHECK-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[FOUND_CONFLICT]], true -; CHECK-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 2 ; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]] diff --git a/llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll b/llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll index f8861e57564d6448dcfdaaf07cff1ca02f8263a6..004b69ff1f93bfae6fc86140278c7dedd41fc803 100644 --- a/llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll +++ b/llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll @@ -41,8 +41,7 @@ define i16 @test(i16** %arg, i64 %N) { ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult i8* [[L_2_LCSSA3]], [[SCEVGEP912]] ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult i8* [[SCEVGEP58]], [[SCEVGEP4]] ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] -; CHECK-NEXT: [[MEMCHECK_CONFLICT:%.*]] = and i1 [[FOUND_CONFLICT]], true -; CHECK-NEXT: br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2 ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] diff --git a/llvm/test/Transforms/LoopVersioning/basic.ll b/llvm/test/Transforms/LoopVersioning/basic.ll index 69ebff5ad0ca2b63f2af5d610f32381fd2c1e71c..52afa8163e61e4f19cf397f95a6afdcf1fd23f6e 100644 --- a/llvm/test/Transforms/LoopVersioning/basic.ll +++ b/llvm/test/Transforms/LoopVersioning/basic.ll @@ -15,7 +15,7 @@ entry: ; CHECK: icmp ; CHECK: icmp ; CHECK-NOT: icmp -; CHECK: br i1 %memcheck.conflict, label %for.body.ph.lver.orig, label %for.body.ph +; CHECK: br i1 %conflict.rdx, label %for.body.ph.lver.orig, label %for.body.ph ; CHECK: for.body.ph.lver.orig: ; CHECK: for.body.lver.orig: diff --git a/llvm/test/Transforms/LoopVersioning/lcssa.ll b/llvm/test/Transforms/LoopVersioning/lcssa.ll index f507b43ea2b512e9132856d8d8c3173b7596dc8f..2865e2cc8e66d5bdda5e724e32ee11c0202a3810 100644 --- a/llvm/test/Transforms/LoopVersioning/lcssa.ll +++ b/llvm/test/Transforms/LoopVersioning/lcssa.ll @@ -3,7 +3,7 @@ target triple = "x86_64-unknown-linux-gnu" define void @fill(i8** %ls1.20, i8** %ls2.21, i8* %cse3.22) { ; CHECK: bb1.lver.check: -; CHECK: br i1 %memcheck.conflict, label %bb1.ph.lver.orig, label %bb1.ph +; CHECK: br i1 %found.conflict, label %bb1.ph.lver.orig, label %bb1.ph bb1.ph: %ls1.20.promoted = load i8*, i8** %ls1.20 %ls2.21.promoted = load i8*, i8** %ls2.21 @@ -37,7 +37,7 @@ bb3: define void @fill_no_null_opt(i8** %ls1.20, i8** %ls2.21, i8* %cse3.22) #0 { ; CHECK-LABEL: fill_no_null_opt( ; CHECK: bb1.lver.check: -; CHECK: %lver.safe = or i1 %memcheck.conflict, %{{.*}} +; CHECK: %lver.safe = or i1 %found.conflict, %{{.*}} ; CHECK: br i1 %lver.safe, label %bb1.ph.lver.orig, label %bb1.ph bb1.ph: %ls1.20.promoted = load i8*, i8** %ls1.20 diff --git a/llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM3.ll b/llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM3.ll index f5da40b1c7817cb44ccf65c9ef60e125faf489ee..0db07edf0d0c94632653f2baf9ff5476439f9f33 100644 --- a/llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM3.ll +++ b/llvm/test/Transforms/LoopVersioningLICM/loopversioningLICM3.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -O1 -S -loop-versioning-licm -debug-only=loop-versioning-licm 2>&1 | FileCheck %s +; RUN: opt < %s -S -passes='default,loop-versioning-licm' -debug-only=loop-versioning-licm 2>&1 | FileCheck %s ; RUN: opt < %s -S -passes='loop-versioning-licm' -debug-only=loop-versioning-licm 2>&1 | FileCheck %s ; REQUIRES: asserts ; diff --git a/llvm/test/Transforms/LoopVersioningLICM/metadata.ll b/llvm/test/Transforms/LoopVersioningLICM/metadata.ll index 445b09c0721870def40930779d27c61e0198c706..3656218ac63c0ebb5957c6a98f8beccd4b12c0f8 100644 --- a/llvm/test/Transforms/LoopVersioningLICM/metadata.ll +++ b/llvm/test/Transforms/LoopVersioningLICM/metadata.ll @@ -1,4 +1,3 @@ -; RUN: opt < %s -O1 -S -loop-versioning-licm -licm 2>&1 | FileCheck %s ; RUN: opt < %s -S -passes='function(loop-versioning-licm,loop-mssa(licm))' 2>&1 | FileCheck %s ; CHECK-LABEL: @without_metadata( diff --git a/llvm/test/Transforms/MergeFunc/mergefunc-preserve-debug-info.ll b/llvm/test/Transforms/MergeFunc/mergefunc-preserve-debug-info.ll index bb633586e87ab047c9ea69a2c23ea180e94120da..65169a201c9aeab97c75966ddbf2813187e65b04 100644 --- a/llvm/test/Transforms/MergeFunc/mergefunc-preserve-debug-info.ll +++ b/llvm/test/Transforms/MergeFunc/mergefunc-preserve-debug-info.ll @@ -1,5 +1,5 @@ -; RUN: opt -O0 -S -mergefunc -mergefunc-preserve-debug-info < %s | FileCheck %s --check-prefix=OPTIMIZATION_LEVEL_0 -; RUN: opt -O2 -S -mergefunc -mergefunc-preserve-debug-info < %s | FileCheck %s --check-prefix=OPTIMIZATION_LEVEL_2 +; RUN: opt -passes='default,mergefunc' -S -mergefunc-preserve-debug-info < %s | FileCheck %s --check-prefix=OPTIMIZATION_LEVEL_0 +; RUN: opt -passes='default,mergefunc' -S -mergefunc-preserve-debug-info < %s | FileCheck %s --check-prefix=OPTIMIZATION_LEVEL_2 ; Preserve debug info in thunks under -mergefunc -mergefunc-preserve-debug-info ; diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shrink_after_reorder2.ll b/llvm/test/Transforms/SLPVectorizer/X86/shrink_after_reorder2.ll index 5c92ddef01c4e02c73ba701f10c8b46e0d218db0..a4a388e9d095cb0789daabdfe0ab63065ce9b231 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/shrink_after_reorder2.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/shrink_after_reorder2.ll @@ -23,7 +23,7 @@ define void @foo(%class.e* %this, %struct.a* %p, i32 %add7) { ; CHECK: sw.bb: ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32* [[G]] to <2 x i32>* ; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i32>, <2 x i32>* [[TMP2]], align 4 -; CHECK-NEXT: [[SHRINK_SHUFFLE:%.*]] = shufflevector <4 x i32> [[SHUFFLE]], <4 x i32> poison, <2 x i32> +; CHECK-NEXT: [[SHRINK_SHUFFLE:%.*]] = shufflevector <4 x i32> [[SHUFFLE]], <4 x i32> poison, <2 x i32> ; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i32> [[SHRINK_SHUFFLE]], ; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i32> [[TMP3]], [[TMP4]] ; CHECK-NEXT: br label [[SW_EPILOG]] diff --git a/llvm/test/Transforms/SampleProfile/Inputs/inline-replay-function-scope.txt b/llvm/test/Transforms/SampleProfile/Inputs/inline-replay-function-scope.txt new file mode 100644 index 0000000000000000000000000000000000000000..7dba64fb139b3913dd5d726c79b52729cde5cd05 --- /dev/null +++ b/llvm/test/Transforms/SampleProfile/Inputs/inline-replay-function-scope.txt @@ -0,0 +1 @@ +remark: calls.cc:10:0: '_Z3sumii' inlined into 'main' to match profiling context with (cost=45, threshold=337) at callsite main:3:0.1; \ No newline at end of file diff --git a/llvm/test/Transforms/SampleProfile/Inputs/inline-replay.txt b/llvm/test/Transforms/SampleProfile/Inputs/inline-replay.txt index 9d720ec452493eeafd001bdf49d071e2bb47a5f4..89a48da26cc3a660e2fbae7b7452295b4b14b3c1 100644 --- a/llvm/test/Transforms/SampleProfile/Inputs/inline-replay.txt +++ b/llvm/test/Transforms/SampleProfile/Inputs/inline-replay.txt @@ -1,2 +1,2 @@ remark: calls.cc:10:0: '_Z3sumii' inlined into 'main' to match profiling context with (cost=45, threshold=337) at callsite main:3:0.1; -remark: calls.cc:4:0: '_Z3subii' inlined into 'main' to match profiling context with (cost=-5, threshold=337) at callsite _Z3sumii:1:0 @ main:3:0.1; +remark: calls.cc:4:0: '_Z3subii' inlined into 'main' to match profiling context with (cost=-5, threshold=337) at callsite _Z3sumii:1:0 @ main:3:0.1; \ No newline at end of file diff --git a/llvm/test/Transforms/SampleProfile/Inputs/inline-topdown-inline-all.prof b/llvm/test/Transforms/SampleProfile/Inputs/inline-topdown-inline-all.prof new file mode 100644 index 0000000000000000000000000000000000000000..6e0d987f50751943731c907e023593ed548b71ba --- /dev/null +++ b/llvm/test/Transforms/SampleProfile/Inputs/inline-topdown-inline-all.prof @@ -0,0 +1,10 @@ +main:225715:0 + 2.1: 5553 + 3: 5391 + 3.1: _Z3sumii:50000 + 1: _Z3subii:50000 + 1: 0 + +_Z3sumii:6010:50000 + 1: _Z3subii:60000 + 1: 9 \ No newline at end of file diff --git a/llvm/test/Transforms/SampleProfile/inline-replay.ll b/llvm/test/Transforms/SampleProfile/inline-replay.ll index 0f06104161de25ffbf872986f6eeb56d472906d1..2235797febe775586ff5ff63e5b6c198c15ebe91 100644 --- a/llvm/test/Transforms/SampleProfile/inline-replay.ll +++ b/llvm/test/Transforms/SampleProfile/inline-replay.ll @@ -4,7 +4,40 @@ ; RUN: opt < %s -passes=sample-profile -sample-profile-file=%S/Inputs/inline-topdown.prof -sample-profile-merge-inlinee -sample-profile-top-down-load -pass-remarks=inline -S 2>&1 | FileCheck -check-prefix=DEFAULT %s ;; Check replay inline decisions -; RUN: opt < %s -passes=sample-profile -sample-profile-file=%S/Inputs/inline-topdown.prof -sample-profile-inline-replay=%S/Inputs/inline-replay.txt -sample-profile-merge-inlinee -sample-profile-top-down-load -pass-remarks=inline -S 2>&1 | FileCheck -check-prefix=REPLAY %s +; RUN: opt < %s -passes=sample-profile -sample-profile-file=%S/Inputs/inline-topdown.prof -sample-profile-inline-replay=%S/Inputs/inline-replay.txt -sample-profile-inline-replay-scope=Module -sample-profile-merge-inlinee -sample-profile-top-down-load -pass-remarks=inline -S 2>&1 | FileCheck -check-prefix=REPLAY %s + +;; Check baseline inline decisions with "inline-topdown-inline-all.prof" which inlines all sites +; RUN: opt < %s -passes=sample-profile -sample-profile-file=%S/Inputs/inline-topdown-inline-all.prof -sample-profile-merge-inlinee -sample-profile-top-down-load -pass-remarks=inline -S 2>&1 | FileCheck -check-prefix=DEFAULT-ALL %s + +;; Check function scope replay inline decisions with "inline-topdown-inline-all.prof" and "inline-topdown-function-scope.txt" which only contains: '_Z3sumii' inlined into 'main' +;; 1. _Z3sumii is inlined into main, but all other inline candidates in main (e.g. _Z3subii) are not inlined +;; 2. Inline decisions made in other functions match default sample inlining, in this case _Z3subii is inlined into _Z3sumii +; RUN: opt < %s -passes=sample-profile -sample-profile-file=%S/Inputs/inline-topdown-inline-all.prof -sample-profile-inline-replay=%S/Inputs/inline-replay-function-scope.txt -sample-profile-inline-replay-scope=Function -sample-profile-merge-inlinee -sample-profile-top-down-load -pass-remarks=inline -S 2>&1 | FileCheck -check-prefix=REPLAY-ALL-FUNCTION %s + +;; Check behavior on non-existent replay file +; RUN: not opt < %s -passes=sample-profile -sample-profile-file=%S/Inputs/inline-topdown.prof -sample-profile-inline-replay=%S -sample-profile-merge-inlinee -sample-profile-top-down-load -pass-remarks=inline -S 2>&1 | FileCheck -check-prefix=REPLAY-ERROR %s + +;; Check scope inlining errors out on non inputs +; RUN: not opt < %s -passes=sample-profile -sample-profile-file=%S/Inputs/inline-topdown.prof -sample-profile-inline-replay=%S/Inputs/inline-replay.txt -sample-profile-inline-replay-scope=function -sample-profile-merge-inlinee -sample-profile-top-down-load -pass-remarks=inline -S 2>&1 | FileCheck -check-prefix=REPLAY-ERROR-SCOPE %s + +; DEFAULT: '_Z3sumii' inlined into 'main' to match profiling context with (cost={{[-0-9]+}} +; DEFAULT: '_Z3subii' inlined into '_Z3sumii' to match profiling context with (cost={{[-0-9]+}} +; DEFAULT-NOT: '_Z3subii' inlined into 'main' + +; REPLAY: '_Z3sumii' inlined into 'main' to match profiling context with (cost=always) +; REPLAY: '_Z3subii' inlined into 'main' to match profiling context with (cost=always) +; REPLAY-NOT: '_Z3subii' inlined into '_Z3sumii' + +; DEFAULT-ALL: '_Z3sumii' inlined into 'main' to match profiling context with (cost={{[-0-9]+}} +; DEFAULT-ALL: '_Z3subii' inlined into 'main' to match profiling context with (cost={{[-0-9]+}} +; DEFAULT-ALL: '_Z3subii' inlined into '_Z3sumii' to match profiling context with (cost={{[-0-9]+}} + +; REPLAY-ALL-FUNCTION : _Z3sumii' inlined into 'main' to match profiling context with (cost=always) +; REPLAY-ALL-FUNCTION-NOT: '_Z3subii' inlined into 'main' to match profiling context with (cost={{[-0-9]+}} +; REPLAY-ALL-FUNCTION: '_Z3subii' inlined into '_Z3sumii' to match profiling context with (cost={{[-0-9]+}} + +; REPLAY-ERROR: error: Could not open remarks file: +; REPLAY-ERROR-SCOPE: for the --sample-profile-inline-replay-scope option: Cannot find option named 'function'! @.str = private unnamed_addr constant [11 x i8] c"sum is %d\0A\00", align 1 @@ -111,12 +144,3 @@ attributes #0 = { "use-sample-profile" } !24 = !DILexicalBlockFile(scope: !18, file: !1, discriminator: 6) !25 = !DILocation(line: 11, scope: !12) !26 = !DILocation(line: 12, scope: !12) - - -; DEFAULT: '_Z3sumii' inlined into 'main' -; DEFAULT: '_Z3subii' inlined into '_Z3sumii' -; DEFAULT-NOT: '_Z3subii' inlined into 'main' - -; REPLAY: '_Z3sumii' inlined into 'main' -; REPLAY: '_Z3subii' inlined into 'main' -; REPLAY-NOT: '_Z3subii' inlined into '_Z3sumii' diff --git a/llvm/tools/gold/gold-plugin.cpp b/llvm/tools/gold/gold-plugin.cpp index 6bcb1e4353cfde6dd30a007067894e6fc37fa698..ef30c5b65130c25ba140695b600247d2eb8918a3 100644 --- a/llvm/tools/gold/gold-plugin.cpp +++ b/llvm/tools/gold/gold-plugin.cpp @@ -19,11 +19,11 @@ #include "llvm/Config/llvm-config.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DiagnosticPrinter.h" -#include "llvm/LTO/Caching.h" #include "llvm/LTO/LTO.h" #include "llvm/Object/Error.h" #include "llvm/Remarks/HotnessThresholdParser.h" #include "llvm/Support/CachePruning.h" +#include "llvm/Support/Caching.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/Host.h" @@ -1081,12 +1081,11 @@ static std::vector, bool>> runLTO() { size_t MaxTasks = Lto->getMaxTasks(); std::vector, bool>> Files(MaxTasks); - auto AddStream = - [&](size_t Task) -> std::unique_ptr { + auto AddStream = [&](size_t Task) -> std::unique_ptr { Files[Task].second = !SaveTemps; int FD = getOutputFileName(Filename, /* TempOutFile */ !SaveTemps, Files[Task].first, Task); - return std::make_unique( + return std::make_unique( std::make_unique(FD, true)); }; @@ -1096,7 +1095,7 @@ static std::vector, bool>> runLTO() { NativeObjectCache Cache; if (!options::cache_dir.empty()) - Cache = check(localCache(options::cache_dir, AddBuffer)); + Cache = check(localCache("ThinLTO", "Thin", options::cache_dir, AddBuffer)); check(Lto->run(AddStream, Cache)); diff --git a/llvm/tools/llvm-lto/llvm-lto.cpp b/llvm/tools/llvm-lto/llvm-lto.cpp index c4afd724d5a2c73198d5376adb27308c003748af..2e6705724c22a4be19d888a77c30f93e6ee3dacb 100644 --- a/llvm/tools/llvm-lto/llvm-lto.cpp +++ b/llvm/tools/llvm-lto/llvm-lto.cpp @@ -1097,8 +1097,7 @@ int main(int argc, char **argv) { error("writing merged module failed."); } - auto AddStream = - [&](size_t Task) -> std::unique_ptr { + auto AddStream = [&](size_t Task) -> std::unique_ptr { std::string PartFilename = OutputFilename; if (Parallelism != 1) PartFilename += "." + utostr(Task); @@ -1108,7 +1107,7 @@ int main(int argc, char **argv) { std::make_unique(PartFilename, EC, sys::fs::OF_None); if (EC) error("error opening the file '" + PartFilename + "': " + EC.message()); - return std::make_unique(std::move(S)); + return std::make_unique(std::move(S)); }; if (!CodeGen.compileOptimized(AddStream, Parallelism)) diff --git a/llvm/tools/llvm-lto2/llvm-lto2.cpp b/llvm/tools/llvm-lto2/llvm-lto2.cpp index c0bff1eabee27e5f2a6b4e11197ba3618065c1b7..b6f37fef9075eb0ee2f7c3dfdaaeb0d446d89d41 100644 --- a/llvm/tools/llvm-lto2/llvm-lto2.cpp +++ b/llvm/tools/llvm-lto2/llvm-lto2.cpp @@ -19,10 +19,10 @@ #include "llvm/CodeGen/CommandFlags.h" #include "llvm/Config/llvm-config.h" #include "llvm/IR/DiagnosticPrinter.h" -#include "llvm/LTO/Caching.h" #include "llvm/LTO/LTO.h" #include "llvm/Passes/PassPlugin.h" #include "llvm/Remarks/HotnessThresholdParser.h" +#include "llvm/Support/Caching.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/InitLLVM.h" @@ -362,14 +362,13 @@ static int run(int argc, char **argv) { if (HasErrors) return 1; - auto AddStream = - [&](size_t Task) -> std::unique_ptr { + auto AddStream = [&](size_t Task) -> std::unique_ptr { std::string Path = OutputFilename + "." + utostr(Task); std::error_code EC; auto S = std::make_unique(Path, EC, sys::fs::OF_None); check(EC, Path); - return std::make_unique(std::move(S)); + return std::make_unique(std::move(S)); }; auto AddBuffer = [&](size_t Task, std::unique_ptr MB) { @@ -378,7 +377,8 @@ static int run(int argc, char **argv) { NativeObjectCache Cache; if (!CacheDir.empty()) - Cache = check(localCache(CacheDir, AddBuffer), "failed to create cache"); + Cache = check(localCache("ThinLTO", "Thin", CacheDir, AddBuffer), + "failed to create cache"); check(Lto.run(AddStream, Cache), "LTO::run failed"); return 0; diff --git a/llvm/tools/opt/opt.cpp b/llvm/tools/opt/opt.cpp index fafde7a5f80c7a23b5c08c2d29270d9572a898b3..ab890b6a640801288204a999f0012e8d9151d5b2 100644 --- a/llvm/tools/opt/opt.cpp +++ b/llvm/tools/opt/opt.cpp @@ -772,19 +772,32 @@ int main(int argc, char **argv) { << "Cannot specify passes via both -foo-pass and --passes=foo-pass\n"; return 1; } + auto NumOLevel = OptLevelO0 + OptLevelO1 + OptLevelO2 + OptLevelO3 + + OptLevelOs + OptLevelOz; + if (NumOLevel > 1) { + errs() << "Cannot specify multiple -O#\n"; + return 1; + } + if (NumOLevel > 0 && PassPipeline.getNumOccurrences() > 0) { + errs() << "Cannot specify -O# and --passes=, use " + "-passes='default,other-pass'\n"; + return 1; + } + std::string Pipeline = PassPipeline; + SmallVector Passes; if (OptLevelO0) - Passes.push_back("default"); + Pipeline = "default"; if (OptLevelO1) - Passes.push_back("default"); + Pipeline = "default"; if (OptLevelO2) - Passes.push_back("default"); + Pipeline = "default"; if (OptLevelO3) - Passes.push_back("default"); + Pipeline = "default"; if (OptLevelOs) - Passes.push_back("default"); + Pipeline = "default"; if (OptLevelOz) - Passes.push_back("default"); + Pipeline = "default"; for (const auto &P : PassList) Passes.push_back(P->getPassArgument()); OutputKind OK = OK_NoOutput; @@ -803,7 +816,7 @@ int main(int argc, char **argv) { // string. Hand off the rest of the functionality to the new code for that // layer. return runPassPipeline(argv[0], *M, TM.get(), &TLII, Out.get(), - ThinLinkOut.get(), RemarksFile.get(), PassPipeline, + ThinLinkOut.get(), RemarksFile.get(), Pipeline, Passes, OK, VK, PreserveAssemblyUseListOrder, PreserveBitcodeUseListOrder, EmitSummaryIndex, EmitModuleHash, EnableDebugify) diff --git a/llvm/unittests/ADT/APIntTest.cpp b/llvm/unittests/ADT/APIntTest.cpp index 3631c126718a86a42a899b955dd71f39cf656692..0efe28f111ca9a3253f9ee5d15cd00ffc93731c7 100644 --- a/llvm/unittests/ADT/APIntTest.cpp +++ b/llvm/unittests/ADT/APIntTest.cpp @@ -1769,7 +1769,7 @@ TEST(APIntTest, isPowerOf2) { EXPECT_FALSE(APInt(5, 0x00).isPowerOf2()); EXPECT_FALSE(APInt(32, 0x11).isPowerOf2()); EXPECT_TRUE(APInt(17, 0x01).isPowerOf2()); - EXPECT_TRUE(APInt(32, 0xff << 31).isPowerOf2()); + EXPECT_TRUE(APInt(32, (unsigned)(0xffu << 31)).isPowerOf2()); for (int N : {1, 2, 3, 4, 7, 8, 16, 32, 64, 127, 128, 129, 256}) { EXPECT_FALSE(APInt(N, 0).isPowerOf2()); diff --git a/llvm/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp b/llvm/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp index 6d6d4e06fb5ffea2c2d1a8d36170abb7feffe35a..a4e6b56456a3719b5791549fbb0e362c97001a2f 100644 --- a/llvm/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp +++ b/llvm/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp @@ -392,7 +392,11 @@ TEST(DWARFDebugInfo, TestDWARF32Version2Addr4AllForms) { TestAllForms<2, AddrType, RefAddrType>(); } +#ifdef _AIX +TEST(DWARFDebugInfo, DISABLED_TestDWARF32Version2Addr8AllForms) { +#else TEST(DWARFDebugInfo, TestDWARF32Version2Addr8AllForms) { +#endif // Test that we can decode all forms for DWARF32, version 2, with 4 byte // addresses. typedef uint64_t AddrType; @@ -410,7 +414,11 @@ TEST(DWARFDebugInfo, TestDWARF32Version3Addr4AllForms) { TestAllForms<3, AddrType, RefAddrType>(); } +#ifdef _AIX +TEST(DWARFDebugInfo, DISABLED_TestDWARF32Version3Addr8AllForms) { +#else TEST(DWARFDebugInfo, TestDWARF32Version3Addr8AllForms) { +#endif // Test that we can decode all forms for DWARF32, version 3, with 8 byte // addresses. typedef uint64_t AddrType; @@ -428,7 +436,11 @@ TEST(DWARFDebugInfo, TestDWARF32Version4Addr4AllForms) { TestAllForms<4, AddrType, RefAddrType>(); } +#ifdef _AIX +TEST(DWARFDebugInfo, DISABLED_TestDWARF32Version4Addr8AllForms) { +#else TEST(DWARFDebugInfo, TestDWARF32Version4Addr8AllForms) { +#endif // Test that we can decode all forms for DWARF32, version 4, with 8 byte // addresses. typedef uint64_t AddrType; @@ -558,7 +570,11 @@ TEST(DWARFDebugInfo, TestDWARF32Version2Addr4Children) { TestChildren<2, AddrType>(); } +#ifdef _AIX +TEST(DWARFDebugInfo, DISABLED_TestDWARF32Version2Addr8Children) { +#else TEST(DWARFDebugInfo, TestDWARF32Version2Addr8Children) { +#endif // Test that we can decode all forms for DWARF32, version 2, with 8 byte // addresses. typedef uint64_t AddrType; @@ -572,7 +588,11 @@ TEST(DWARFDebugInfo, TestDWARF32Version3Addr4Children) { TestChildren<3, AddrType>(); } +#ifdef _AIX +TEST(DWARFDebugInfo, DISABLED_TestDWARF32Version3Addr8Children) { +#else TEST(DWARFDebugInfo, TestDWARF32Version3Addr8Children) { +#endif // Test that we can decode all forms for DWARF32, version 3, with 8 byte // addresses. typedef uint64_t AddrType; @@ -586,7 +606,11 @@ TEST(DWARFDebugInfo, TestDWARF32Version4Addr4Children) { TestChildren<4, AddrType>(); } +#ifdef _AIX +TEST(DWARFDebugInfo, DISABLED_TestDWARF32Version4Addr8Children) { +#else TEST(DWARFDebugInfo, TestDWARF32Version4Addr8Children) { +#endif // Test that we can decode all forms for DWARF32, version 4, with 8 byte // addresses. typedef uint64_t AddrType; @@ -808,7 +832,11 @@ TEST(DWARFDebugInfo, TestDWARF32Version2Addr4References) { TestReferences<2, AddrType>(); } +#ifdef _AIX +TEST(DWARFDebugInfo, DISABLED_TestDWARF32Version2Addr8References) { +#else TEST(DWARFDebugInfo, TestDWARF32Version2Addr8References) { +#endif // Test that we can decode all forms for DWARF32, version 2, with 8 byte // addresses. typedef uint64_t AddrType; @@ -822,7 +850,11 @@ TEST(DWARFDebugInfo, TestDWARF32Version3Addr4References) { TestReferences<3, AddrType>(); } +#ifdef _AIX +TEST(DWARFDebugInfo, DISABLED_TestDWARF32Version3Addr8References) { +#else TEST(DWARFDebugInfo, TestDWARF32Version3Addr8References) { +#endif // Test that we can decode all forms for DWARF32, version 3, with 8 byte // addresses. typedef uint64_t AddrType; @@ -836,7 +868,11 @@ TEST(DWARFDebugInfo, TestDWARF32Version4Addr4References) { TestReferences<4, AddrType>(); } +#ifdef _AIX +TEST(DWARFDebugInfo, DISABLED_TestDWARF32Version4Addr8References) { +#else TEST(DWARFDebugInfo, TestDWARF32Version4Addr8References) { +#endif // Test that we can decode all forms for DWARF32, version 4, with 8 byte // addresses. typedef uint64_t AddrType; @@ -980,7 +1016,11 @@ TEST(DWARFDebugInfo, TestDWARF32Version2Addr4Addresses) { TestAddresses<2, AddrType>(); } +#ifdef _AIX +TEST(DWARFDebugInfo, DISABLED_TestDWARF32Version2Addr8Addresses) { +#else TEST(DWARFDebugInfo, TestDWARF32Version2Addr8Addresses) { +#endif // Test that we can decode address values in DWARF32, version 2, with 8 byte // addresses. typedef uint64_t AddrType; @@ -994,7 +1034,11 @@ TEST(DWARFDebugInfo, TestDWARF32Version3Addr4Addresses) { TestAddresses<3, AddrType>(); } +#ifdef _AIX +TEST(DWARFDebugInfo, DISABLED_TestDWARF32Version3Addr8Addresses) { +#else TEST(DWARFDebugInfo, TestDWARF32Version3Addr8Addresses) { +#endif // Test that we can decode address values in DWARF32, version 3, with 8 byte // addresses. typedef uint64_t AddrType; @@ -1008,7 +1052,11 @@ TEST(DWARFDebugInfo, TestDWARF32Version4Addr4Addresses) { TestAddresses<4, AddrType>(); } +#ifdef _AIX +TEST(DWARFDebugInfo, DISABLED_TestDWARF32Version4Addr8Addresses) { +#else TEST(DWARFDebugInfo, TestDWARF32Version4Addr8Addresses) { +#endif // Test that we can decode address values in DWARF32, version 4, with 8 byte // addresses. typedef uint64_t AddrType; diff --git a/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp b/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp index 9de6c83f5cc66f708ac3d2af4cc04828e60d3381..c01a20e9186c2489e117e2126264e4d1edf721f4 100644 --- a/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp +++ b/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp @@ -177,7 +177,11 @@ void checkDefaultPrologue(uint16_t Version, DwarfFormat Format, EXPECT_STREQ(*Prologue.FileNames[0].Name.getAsCString(), "a file"); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, DISABLED_GetOrParseLineTableAtInvalidOffset) { +#else TEST_F(DebugLineBasicFixture, GetOrParseLineTableAtInvalidOffset) { +#endif if (!setupGenerator()) return; generate(); @@ -199,7 +203,12 @@ TEST_F(DebugLineBasicFixture, GetOrParseLineTableAtInvalidOffset) { "offset 0x00000001 is not a valid debug line section offset")); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, + DISABLED_GetOrParseLineTableAtInvalidOffsetAfterData) { +#else TEST_F(DebugLineBasicFixture, GetOrParseLineTableAtInvalidOffsetAfterData) { +#endif if (!setupGenerator()) return; @@ -220,7 +229,11 @@ TEST_F(DebugLineBasicFixture, GetOrParseLineTableAtInvalidOffsetAfterData) { "offset 0x00000001 is not a valid debug line section offset")); } +#ifdef _AIX +TEST_P(DebugLineParameterisedFixture, DISABLED_PrologueGetLength) { +#else TEST_P(DebugLineParameterisedFixture, PrologueGetLength) { +#endif if (!setupGenerator(Version)) return; LineTable < = Gen->addLineTable(Format); @@ -243,7 +256,11 @@ TEST_P(DebugLineParameterisedFixture, PrologueGetLength) { EXPECT_EQ((*ExpectedLineTable)->Prologue.getLength(), ExpectedLength); } +#ifdef _AIX +TEST_P(DebugLineParameterisedFixture, DISABLED_GetOrParseLineTableValidTable) { +#else TEST_P(DebugLineParameterisedFixture, GetOrParseLineTableValidTable) { +#endif if (!setupGenerator(Version)) return; @@ -309,7 +326,11 @@ TEST_P(DebugLineParameterisedFixture, GetOrParseLineTableValidTable) { // correctly. } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, DISABLED_ErrorForReservedLength) { +#else TEST_F(DebugLineBasicFixture, ErrorForReservedLength) { +#endif if (!setupGenerator()) return; @@ -332,7 +353,12 @@ struct DebugLineUnsupportedVersionFixture : public TestWithParam, uint16_t Version; }; +#ifdef _AIX +TEST_P(DebugLineUnsupportedVersionFixture, + DISABLED_ErrorForUnsupportedVersion) { +#else TEST_P(DebugLineUnsupportedVersionFixture, ErrorForUnsupportedVersion) { +#endif if (!setupGenerator()) return; @@ -354,7 +380,11 @@ INSTANTIATE_TEST_SUITE_P(UnsupportedVersionTestParams, Values(/*1 below min */ 1, /* 1 above max */ 6, /* Maximum possible */ 0xffff)); +#ifdef _AIX +TEST_F(DebugLineBasicFixture, DISABLED_ErrorForInvalidV5IncludeDirTable) { +#else TEST_F(DebugLineBasicFixture, ErrorForInvalidV5IncludeDirTable) { +#endif if (!setupGenerator(5)) return; @@ -395,7 +425,11 @@ TEST_F(DebugLineBasicFixture, ErrorForInvalidV5IncludeDirTable) { "found")); } +#ifdef _AIX +TEST_P(DebugLineParameterisedFixture, DISABLED_ErrorForTooLargePrologueLength) { +#else TEST_P(DebugLineParameterisedFixture, ErrorForTooLargePrologueLength) { +#endif if (!setupGenerator(Version)) return; @@ -431,7 +465,11 @@ TEST_P(DebugLineParameterisedFixture, ErrorForTooLargePrologueLength) { .str())); } +#ifdef _AIX +TEST_P(DebugLineParameterisedFixture, DISABLED_ErrorForTooShortPrologueLength) { +#else TEST_P(DebugLineParameterisedFixture, ErrorForTooShortPrologueLength) { +#endif if (!setupGenerator(Version)) return; @@ -485,7 +523,12 @@ INSTANTIATE_TEST_SUITE_P( std::make_pair(4, DWARF64), // Test v4 fields and DWARF64. std::make_pair(5, DWARF32), std::make_pair(5, DWARF64))); +#ifdef _AIX +TEST_F(DebugLineBasicFixture, + DISABLED_ErrorForExtendedOpcodeLengthSmallerThanExpected) { +#else TEST_F(DebugLineBasicFixture, ErrorForExtendedOpcodeLengthSmallerThanExpected) { +#endif if (!setupGenerator()) return; @@ -514,7 +557,12 @@ TEST_F(DebugLineBasicFixture, ErrorForExtendedOpcodeLengthSmallerThanExpected) { EXPECT_EQ((*ExpectedLineTable)->Rows[1].Discriminator, DW_LNS_negate_stmt); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, + DISABLED_ErrorForExtendedOpcodeLengthLargerThanExpected) { +#else TEST_F(DebugLineBasicFixture, ErrorForExtendedOpcodeLengthLargerThanExpected) { +#endif if (!setupGenerator()) return; @@ -543,7 +591,11 @@ TEST_F(DebugLineBasicFixture, ErrorForExtendedOpcodeLengthLargerThanExpected) { EXPECT_EQ((*ExpectedLineTable)->Rows[2].IsStmt, 1u); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, DISABLED_ErrorForUnitLengthTooLarge) { +#else TEST_F(DebugLineBasicFixture, ErrorForUnitLengthTooLarge) { +#endif if (!setupGenerator()) return; @@ -572,7 +624,11 @@ TEST_F(DebugLineBasicFixture, ErrorForUnitLengthTooLarge) { EXPECT_EQ((*ExpectedLineTable)->Sequences.size(), 1u); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, DISABLED_ErrorForMismatchedAddressSize) { +#else TEST_F(DebugLineBasicFixture, ErrorForMismatchedAddressSize) { +#endif if (!setupGenerator(4, 8)) return; @@ -601,8 +657,13 @@ TEST_F(DebugLineBasicFixture, ErrorForMismatchedAddressSize) { EXPECT_EQ((*ExpectedLineTable)->Rows[1].Address.Address, Addr2); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, + DISABLED_ErrorForMismatchedAddressSizeUnsetInitialAddress) { +#else TEST_F(DebugLineBasicFixture, ErrorForMismatchedAddressSizeUnsetInitialAddress) { +#endif if (!setupGenerator(4, 0)) return; @@ -628,8 +689,13 @@ TEST_F(DebugLineBasicFixture, EXPECT_EQ((*ExpectedLineTable)->Rows[1].Address.Address, Addr2); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, + DISABLED_ErrorForUnsupportedAddressSizeInSetAddressLength) { +#else TEST_F(DebugLineBasicFixture, ErrorForUnsupportedAddressSizeInSetAddressLength) { +#endif // Use DWARF v4, and 0 for data extractor address size so that the address // size is derived from the opcode length. if (!setupGenerator(4, 0)) @@ -661,7 +727,11 @@ TEST_F(DebugLineBasicFixture, EXPECT_EQ((*ExpectedLineTable)->Rows[0].Address.Address, 0u); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, DISABLED_ErrorForAddressSizeGreaterThanByteSize) { +#else TEST_F(DebugLineBasicFixture, ErrorForAddressSizeGreaterThanByteSize) { +#endif // Use DWARF v4, and 0 for data extractor address size so that the address // size is derived from the opcode length. if (!setupGenerator(4, 0)) @@ -685,7 +755,12 @@ TEST_F(DebugLineBasicFixture, ErrorForAddressSizeGreaterThanByteSize) { ASSERT_THAT_EXPECTED(ExpectedLineTable, Succeeded()); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, + DISABLED_ErrorForUnsupportedAddressSizeDefinedInHeader) { +#else TEST_F(DebugLineBasicFixture, ErrorForUnsupportedAddressSizeDefinedInHeader) { +#endif // Use 0 for data extractor address size so that it does not clash with the // header address size. if (!setupGenerator(5, 0)) @@ -722,7 +797,11 @@ TEST_F(DebugLineBasicFixture, ErrorForUnsupportedAddressSizeDefinedInHeader) { EXPECT_EQ((*ExpectedLineTable)->Rows[0].Address.Address, 0u); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, DISABLED_CallbackUsedForUnterminatedSequence) { +#else TEST_F(DebugLineBasicFixture, CallbackUsedForUnterminatedSequence) { +#endif if (!setupGenerator()) return; @@ -943,7 +1022,11 @@ struct MaxOpsPerInstFixture uint8_t MaxOpsPerInst; }; +#ifdef _AIX +TEST_P(MaxOpsPerInstFixture, DISABLED_MaxOpsPerInstProblemsReportedCorrectly) { +#else TEST_P(MaxOpsPerInstFixture, MaxOpsPerInstProblemsReportedCorrectly) { +#endif runTest(/*CheckAdvancePC=*/true, "but the prologue maximum_operations_per_instruction value is " + Twine(unsigned(MaxOpsPerInst)) + @@ -987,7 +1070,11 @@ struct LineRangeFixture : TestWithParam>, uint8_t LineRange; }; +#ifdef _AIX +TEST_P(LineRangeFixture, DISABLED_LineRangeProblemsReportedCorrectly) { +#else TEST_P(LineRangeFixture, LineRangeProblemsReportedCorrectly) { +#endif runTest(/*CheckAdvancePC=*/false, "but the prologue line_range value is 0. The address and line will " "not be adjusted"); @@ -1022,7 +1109,11 @@ struct BadMinInstLenFixture : TestWithParam>, uint8_t MinInstLength; }; +#ifdef _AIX +TEST_P(BadMinInstLenFixture, DISABLED_MinInstLengthProblemsReportedCorrectly) { +#else TEST_P(BadMinInstLenFixture, MinInstLengthProblemsReportedCorrectly) { +#endif runTest(/*CheckAdvancePC=*/true, "but the prologue minimum_instruction_length value is 0, which " "prevents any address advancing"); @@ -1033,7 +1124,11 @@ INSTANTIATE_TEST_SUITE_P( Values(std::make_tuple(0, true), // Test zero value (error). std::make_tuple(1, false))); // Test non-zero value (no error). +#ifdef _AIX +TEST_F(DebugLineBasicFixture, DISABLED_ParserParsesCorrectly) { +#else TEST_F(DebugLineBasicFixture, ParserParsesCorrectly) { +#endif if (!setupGenerator()) return; @@ -1060,7 +1155,11 @@ TEST_F(DebugLineBasicFixture, ParserParsesCorrectly) { EXPECT_FALSE(Unrecoverable); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, DISABLED_ParserSkipsCorrectly) { +#else TEST_F(DebugLineBasicFixture, ParserSkipsCorrectly) { +#endif if (!setupGenerator()) return; @@ -1081,7 +1180,11 @@ TEST_F(DebugLineBasicFixture, ParserSkipsCorrectly) { EXPECT_FALSE(Unrecoverable); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, DISABLED_ParserAlwaysDoneForEmptySection) { +#else TEST_F(DebugLineBasicFixture, ParserAlwaysDoneForEmptySection) { +#endif if (!setupGenerator()) return; @@ -1091,7 +1194,12 @@ TEST_F(DebugLineBasicFixture, ParserAlwaysDoneForEmptySection) { EXPECT_TRUE(Parser.done()); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, + DISABLED_ParserMarkedAsDoneForBadLengthWhenParsing) { +#else TEST_F(DebugLineBasicFixture, ParserMarkedAsDoneForBadLengthWhenParsing) { +#endif if (!setupGenerator()) return; @@ -1114,7 +1222,12 @@ TEST_F(DebugLineBasicFixture, ParserMarkedAsDoneForBadLengthWhenParsing) { "reserved unit length of value 0xfffffff0")); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, + DISABLED_ParserMarkedAsDoneForBadLengthWhenSkipping) { +#else TEST_F(DebugLineBasicFixture, ParserMarkedAsDoneForBadLengthWhenSkipping) { +#endif if (!setupGenerator()) return; @@ -1137,7 +1250,12 @@ TEST_F(DebugLineBasicFixture, ParserMarkedAsDoneForBadLengthWhenSkipping) { "reserved unit length of value 0xfffffff0")); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, + DISABLED_ParserReportsFirstErrorInEachTableWhenParsing) { +#else TEST_F(DebugLineBasicFixture, ParserReportsFirstErrorInEachTableWhenParsing) { +#endif if (!setupGenerator()) return; @@ -1163,7 +1281,12 @@ TEST_F(DebugLineBasicFixture, ParserReportsFirstErrorInEachTableWhenParsing) { "unsupported version 1")); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, + DISABLED_ParserReportsNonPrologueProblemsWhenParsing) { +#else TEST_F(DebugLineBasicFixture, ParserReportsNonPrologueProblemsWhenParsing) { +#endif if (!setupGenerator()) return; @@ -1195,8 +1318,13 @@ TEST_F(DebugLineBasicFixture, ParserReportsNonPrologueProblemsWhenParsing) { EXPECT_FALSE(Unrecoverable); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, + DISABLED_ParserReportsPrologueErrorsInEachTableWhenSkipping) { +#else TEST_F(DebugLineBasicFixture, ParserReportsPrologueErrorsInEachTableWhenSkipping) { +#endif if (!setupGenerator()) return; @@ -1222,7 +1350,12 @@ TEST_F(DebugLineBasicFixture, "unsupported version 1")); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, + DISABLED_ParserIgnoresNonPrologueErrorsWhenSkipping) { +#else TEST_F(DebugLineBasicFixture, ParserIgnoresNonPrologueErrorsWhenSkipping) { +#endif if (!setupGenerator()) return; @@ -1238,7 +1371,11 @@ TEST_F(DebugLineBasicFixture, ParserIgnoresNonPrologueErrorsWhenSkipping) { EXPECT_FALSE(Unrecoverable); } +#ifdef _AIX +TEST_F(DebugLineBasicFixture, DISABLED_VerboseOutput) { +#else TEST_F(DebugLineBasicFixture, VerboseOutput) { +#endif if (!setupGenerator(5)) return; @@ -1394,7 +1531,11 @@ struct TruncatedPrologueFixture StringRef ExpectedErr; }; +#ifdef _AIX +TEST_P(TruncatedPrologueFixture, DISABLED_ErrorForTruncatedPrologue) { +#else TEST_P(TruncatedPrologueFixture, ErrorForTruncatedPrologue) { +#endif if (!setupGenerator(Version)) return; @@ -1571,7 +1712,12 @@ struct TruncatedExtendedOpcodeFixture uint64_t OpcodeLength; }; +#ifdef _AIX +TEST_P(TruncatedExtendedOpcodeFixture, + DISABLED_ErrorForTruncatedExtendedOpcode) { +#else TEST_P(TruncatedExtendedOpcodeFixture, ErrorForTruncatedExtendedOpcode) { +#endif if (!setupGenerator()) return; LineTable < = setupTable(); @@ -1650,7 +1796,12 @@ INSTANTIATE_TEST_SUITE_P( "unexpected end of data at offset 0x35 while reading [0x32, " "0x36)"))); +#ifdef _AIX +TEST_P(TruncatedStandardOpcodeFixture, + DISABLED_ErrorForTruncatedStandardOpcode) { +#else TEST_P(TruncatedStandardOpcodeFixture, ErrorForTruncatedStandardOpcode) { +#endif if (!setupGenerator()) return; LineTable < = setupTable(); @@ -1706,7 +1857,11 @@ INSTANTIATE_TEST_SUITE_P( "unable to decode LEB128 at offset 0x00000032: " "malformed uleb128, extends past end"))); +#ifdef _AIX +TEST_F(DebugLineBasicFixture, DISABLED_PrintPathsProperly) { +#else TEST_F(DebugLineBasicFixture, PrintPathsProperly) { +#endif if (!setupGenerator(5)) return; diff --git a/llvm/unittests/ExecutionEngine/JITLink/LinkGraphTests.cpp b/llvm/unittests/ExecutionEngine/JITLink/LinkGraphTests.cpp index 964bef5991780c5336e4af3bf6bdeed66ce88f7f..c8958e4d9f3b8597dc10c5e6fe207eb4f98b6a95 100644 --- a/llvm/unittests/ExecutionEngine/JITLink/LinkGraphTests.cpp +++ b/llvm/unittests/ExecutionEngine/JITLink/LinkGraphTests.cpp @@ -345,8 +345,9 @@ TEST(LinkGraphTest, TransferDefinedSymbolAcrossSections) { EXPECT_EQ(Sec1.symbols_size(), 0u) << "Symbol was not removed from Sec1"; EXPECT_EQ(Sec2.symbols_size(), 1u) << "Symbol was not added to Sec2"; - if (Sec2.symbols_size() == 1) + if (Sec2.symbols_size() == 1) { EXPECT_EQ(*Sec2.symbols().begin(), &S1) << "Unexpected symbol"; + } } TEST(LinkGraphTest, TransferBlock) { diff --git a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp index 22ca09e6949ffc4768d784cfe55956299d3e451b..b543c4cc8761bb274d2f3d41f7ad80f76dee4d11 100644 --- a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp +++ b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp @@ -936,7 +936,7 @@ TEST(VPRecipeTest, CastVPWidenMemoryInstructionRecipeToVPUserAndVPDef) { new LoadInst(Int32, UndefValue::get(Int32Ptr), "", false, Align(1)); VPValue Addr; VPValue Mask; - VPWidenMemoryInstructionRecipe Recipe(*Load, &Addr, &Mask); + VPWidenMemoryInstructionRecipe Recipe(*Load, &Addr, &Mask, true, false); EXPECT_TRUE(isa(&Recipe)); VPRecipeBase *BaseR = &Recipe; EXPECT_TRUE(isa(BaseR)); @@ -1032,7 +1032,7 @@ TEST(VPRecipeTest, MayHaveSideEffectsAndMayReadWriteMemory) { new LoadInst(Int32, UndefValue::get(Int32Ptr), "", false, Align(1)); VPValue Addr; VPValue Mask; - VPWidenMemoryInstructionRecipe Recipe(*Load, &Addr, &Mask); + VPWidenMemoryInstructionRecipe Recipe(*Load, &Addr, &Mask, true, false); EXPECT_TRUE(Recipe.mayHaveSideEffects()); EXPECT_TRUE(Recipe.mayReadFromMemory()); EXPECT_FALSE(Recipe.mayWriteToMemory()); @@ -1046,7 +1046,8 @@ TEST(VPRecipeTest, MayHaveSideEffectsAndMayReadWriteMemory) { VPValue Addr; VPValue Mask; VPValue StoredV; - VPWidenMemoryInstructionRecipe Recipe(*Store, &Addr, &StoredV, &Mask); + VPWidenMemoryInstructionRecipe Recipe(*Store, &Addr, &StoredV, &Mask, false, + false); EXPECT_TRUE(Recipe.mayHaveSideEffects()); EXPECT_FALSE(Recipe.mayReadFromMemory()); EXPECT_TRUE(Recipe.mayWriteToMemory()); diff --git a/llvm/utils/gn/secondary/llvm/lib/LTO/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/LTO/BUILD.gn index 20821b61150ac6002e32448f05022e7208a62d03..80bca782ebe5b052205ecbeeaef00f36cb403cc5 100644 --- a/llvm/utils/gn/secondary/llvm/lib/LTO/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/LTO/BUILD.gn @@ -22,7 +22,6 @@ static_library("LTO") { "//llvm/lib/Transforms/Utils", ] sources = [ - "Caching.cpp", "LTO.cpp", "LTOBackend.cpp", "LTOCodeGenerator.cpp", diff --git a/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn index 15a6b92d7c713917d961145c10c5347929a78b03..461b7498978f4392a96138ea5ce9cb38bead0b02 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn @@ -54,6 +54,7 @@ static_library("Support") { "COM.cpp", "CRC.cpp", "CachePruning.cpp", + "Caching.cpp", "Chrono.cpp", "CodeGenCoverage.cpp", "CommandLine.cpp", diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn index e1fcc140c6efd7907700ee311b8564b211d2fca0..fe9098f6ef7177ec573f9041a97763288b5dcdc4 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn @@ -64,6 +64,7 @@ static_library("LLVMBPFCodeGen") { "BPFAsmPrinter.cpp", "BPFCheckAndAdjustIR.cpp", "BPFFrameLowering.cpp", + "BPFIRPeephole.cpp", "BPFISelDAGToDAG.cpp", "BPFISelLowering.cpp", "BPFInstrInfo.cpp", diff --git a/mlir/docs/Tutorials/Toy/Ch-6.md b/mlir/docs/Tutorials/Toy/Ch-6.md index c567c788e3a4bb3cdc1ed8a22d5bf59e4977f006..9a31c8d249fa71197e41d98210bf6281c99a4002 100644 --- a/mlir/docs/Tutorials/Toy/Ch-6.md +++ b/mlir/docs/Tutorials/Toy/Ch-6.md @@ -95,7 +95,8 @@ multiple stages by relying on mlir::RewritePatternSet patterns(&getContext()); mlir::populateAffineToStdConversionPatterns(patterns, &getContext()); mlir::populateLoopToStdConversionPatterns(patterns, &getContext()); - mlir::populateArithmeticToLLVMConversionPatterns(typeConverter, patterns); + mlir::arith::populateArithmeticToLLVMConversionPatterns(typeConverter, + patterns); mlir::populateStdToLLVMConversionPatterns(typeConverter, patterns); // The only remaining operation, to lower from the `toy` dialect, is the diff --git a/mlir/include/mlir/Dialect/SCF/SCF.h b/mlir/include/mlir/Dialect/SCF/SCF.h index ba1caa1151602ad49f1f67af0f6e94895b9d89f0..49f5be00c9785a20cc0ed5833ec9fca47ef3c879 100644 --- a/mlir/include/mlir/Dialect/SCF/SCF.h +++ b/mlir/include/mlir/Dialect/SCF/SCF.h @@ -50,6 +50,11 @@ ForOp getForInductionVarOwner(Value val); /// value is not an induction variable, then return nullptr. ParallelOp getParallelForInductionVarOwner(Value val); +/// Return true if ops a and b (or their ancestors) are in mutually exclusive +/// regions/blocks of an IfOp. +// TODO: Consider moving this functionality to RegionBranchOpInterface. +bool insideMutuallyExclusiveBranches(Operation *a, Operation *b); + /// An owning vector of values, handy to return from functions. using ValueVector = std::vector; using LoopVector = std::vector; diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOCLOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOCLOps.td index fda4a0ce3c6ef592d30db1573b77a88cc3b72fda..ecbe2b63356dde3d32992b1a5107b4614f750f94 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOCLOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOCLOps.td @@ -78,6 +78,36 @@ class SPV_OCLBinaryArithmeticOp { + let summary = "Compute the cosine of x radians."; + + let description = [{ + Result Type and x must be floating-point or vector(2,3,4,8,16) of + floating-point values. + + All of the operands, including the Result Type operand, must be of the + same type. + + + + ``` + float-scalar-vector-type ::= float-type | + `vector<` integer-literal `x` float-type `>` + abs-op ::= ssa-id `=` `spv.OCL.cos` ssa-use `:` + float-scalar-vector-type + ```mlir + + #### Example: + + ``` + %2 = spv.OCL.cos %0 : f32 + %3 = spv.OCL.cos %1 : vector<3xf16> + ``` + }]; +} + +// ----- + def SPV_OCLExpOp : SPV_OCLUnaryArithmeticOp<"exp", 19, SPV_Float> { let summary = "Exponentiation of Operand 1"; @@ -138,6 +168,96 @@ def SPV_OCLFAbsOp : SPV_OCLUnaryArithmeticOp<"fabs", 23, SPV_Float> { // ----- +def SPV_OCLLogOp : SPV_OCLUnaryArithmeticOp<"log", 37, SPV_Float> { + let summary = "Compute the natural logarithm of x."; + + let description = [{ + Result Type and x must be floating-point or vector(2,3,4,8,16) of + floating-point values. + + All of the operands, including the Result Type operand, must be of the + same type. + + + + ``` + float-scalar-vector-type ::= float-type | + `vector<` integer-literal `x` float-type `>` + abs-op ::= ssa-id `=` `spv.OCL.log` ssa-use `:` + float-scalar-vector-type + ```mlir + + #### Example: + + ``` + %2 = spv.OCL.log %0 : f32 + %3 = spv.OCL.log %1 : vector<3xf16> + ``` + }]; +} + +// ----- + +def SPV_OCLSinOp : SPV_OCLUnaryArithmeticOp<"sin", 57, SPV_Float> { + let summary = "Compute sine of x radians."; + + let description = [{ + Result Type and x must be floating-point or vector(2,3,4,8,16) of + floating-point values. + + All of the operands, including the Result Type operand, must be of the + same type. + + + + ``` + float-scalar-vector-type ::= float-type | + `vector<` integer-literal `x` float-type `>` + abs-op ::= ssa-id `=` `spv.OCL.sin` ssa-use `:` + float-scalar-vector-type + ```mlir + + #### Example: + + ``` + %2 = spv.OCL.sin %0 : f32 + %3 = spv.OCL.sin %1 : vector<3xf16> + ``` + }]; +} + +// ----- + +def SPV_OCLSqrtOp : SPV_OCLUnaryArithmeticOp<"sqrt", 61, SPV_Float> { + let summary = "Compute square root of x."; + + let description = [{ + Result Type and x must be floating-point or vector(2,3,4,8,16) of + floating-point values. + + All of the operands, including the Result Type operand, must be of the + same type. + + + + ``` + float-scalar-vector-type ::= float-type | + `vector<` integer-literal `x` float-type `>` + abs-op ::= ssa-id `=` `spv.OCL.sqrt` ssa-use `:` + float-scalar-vector-type + ```mlir + + #### Example: + + ``` + %2 = spv.OCL.sqrt %0 : f32 + %3 = spv.OCL.sqrt %1 : vector<3xf16> + ``` + }]; +} + +// ----- + def SPV_OCLSAbsOp : SPV_OCLUnaryArithmeticOp<"s_abs", 141, SPV_Integer> { let summary = "Absolute value of operand"; diff --git a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td index c7e6e0a408f2c9ec3c60daf4691a14160a8559ef..d1724b4c6f5cc36676b3e49086cd212297b079ac 100644 --- a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td +++ b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td @@ -80,9 +80,9 @@ def SparseTensor_ConvertOp : SparseTensor_Op<"convert", string summary = "Converts between different tensor types"; string description = [{ Converts one sparse or dense tensor type to another tensor type. The rank - and dimensions of the source and destination types must match exactly, - only the sparse encoding of these types may be different. The name `convert` - was preferred over `cast`, since the operation may incur a non-trivial cost. + and dimensions of the source and destination types must match, but the sparse + encoding of these types can obviously be different. The name `convert` was + preferred over `cast`, since the operation may incur a non-trivial cost. When converting between two different sparse tensor types, only explicitly stored values are moved from one underlying sparse storage format to @@ -97,9 +97,14 @@ def SparseTensor_ConvertOp : SparseTensor_Op<"convert", Examples: ```mlir - %0 = sparse_tensor.convert %1 : tensor<32x32xf32> to tensor<32x32xf32, #CSR> - - %2 = sparse_tensor.convert %3 : tensor<8x8xi32, #CSC> to tensor<8x8xi32, #CSR> + %0 = sparse_tensor.convert %a : tensor<32x32xf32> to tensor<32x32xf32, #CSR> + %1 = sparse_tensor.convert %a : tensor<32x32xf32> to tensor + %2 = sparse_tensor.convert %b : tensor<8x8xi32, #CSC> to tensor<8x8xi32, #CSR> + %3 = sparse_tensor.convert %c : tensor<4x8xf64, #CSR> to tensor<4x?xf64, #CSC> + + // The following conversion is not allowed (since it would require a + // runtime assertion that the source's dimension size is actually 100). + %4 = sparse_tensor.convert %d : tensor to tensor<100xf64, #SV> ``` }]; diff --git a/mlir/include/mlir/IR/Diagnostics.h b/mlir/include/mlir/IR/Diagnostics.h index 7bf35c7b5de55bafa8259f05a5716501b3dfc7c1..5f6d870fc805efb8b2de174792e432dfaee6fa09 100644 --- a/mlir/include/mlir/IR/Diagnostics.h +++ b/mlir/include/mlir/IR/Diagnostics.h @@ -29,6 +29,7 @@ struct LogicalResult; class MLIRContext; class Operation; class OperationName; +class OpPrintingFlags; class Type; class Value; @@ -218,6 +219,8 @@ public: Diagnostic &operator<<(Operation *val) { return *this << *val; } + /// Append an operation with the given printing flags. + Diagnostic &appendOp(Operation &val, const OpPrintingFlags &flags); /// Stream in a Value. Diagnostic &operator<<(Value val); diff --git a/mlir/include/mlir/IR/Dominance.h b/mlir/include/mlir/IR/Dominance.h index dcf45130ad1ea4c83f46d723784f98d76ba86d82..83b2b819a5ce04d727c2308d7fe720feaaf351d0 100644 --- a/mlir/include/mlir/IR/Dominance.h +++ b/mlir/include/mlir/IR/Dominance.h @@ -124,8 +124,12 @@ public: /// an SSACFG region, Operation A dominates Operation B in the same block if A /// preceeds B. In a Graph region, all operations in a block dominate all /// other operations in the same block. - bool properlyDominates(Operation *a, Operation *b) const { - return properlyDominatesImpl(a, b, /*enclosingOpOk=*/true); + /// + /// The `enclosingOpOk` flag says whether we should return true if the B op + /// is enclosed by a region on A. + bool properlyDominates(Operation *a, Operation *b, + bool enclosingOpOk = true) const { + return properlyDominatesImpl(a, b, enclosingOpOk); } /// Return true if operation A dominates operation B, i.e. if A and B are the diff --git a/mlir/include/mlir/IR/OpBase.td b/mlir/include/mlir/IR/OpBase.td index f555329d374d9360ef213de92dfc0b981bb36bb2..f30693dc7672055138ba1194712f7d19a01b764f 100644 --- a/mlir/include/mlir/IR/OpBase.td +++ b/mlir/include/mlir/IR/OpBase.td @@ -955,6 +955,19 @@ def AnyAttr : Attr, "any attribute"> { let constBuilderCall = "$0"; } +// Any attribute from the given list +class AnyAttrOf allowedAttrs, string summary = "", + string cppClassName = "::mlir::Attribute", + string fromStorage = "$_self"> : Attr< + // Satisfy any of the allowed attribute's condition + Or, + !if(!eq(summary, ""), + !interleave(!foreach(t, allowedAttrs, t.summary), " or "), + summary)> { + let returnType = cppClassName; + let convertFromStorage = fromStorage; +} + def BoolAttr : Attr()">, "bool attribute"> { let storageType = [{ ::mlir::BoolAttr }]; let returnType = [{ bool }]; diff --git a/mlir/include/mlir/IR/OpImplementation.h b/mlir/include/mlir/IR/OpImplementation.h index 2cbe08815baa3be2334b4f568db0c6361bf5638a..db1f7a3c071d2aed3613d6030da0de9b56cdd8ef 100644 --- a/mlir/include/mlir/IR/OpImplementation.h +++ b/mlir/include/mlir/IR/OpImplementation.h @@ -639,28 +639,6 @@ public: return parseAttribute(result, Type(), attrName, attrs); } - /// Parse an optional attribute. - virtual OptionalParseResult parseOptionalAttribute(Attribute &result, - Type type, - StringRef attrName, - NamedAttrList &attrs) = 0; - template - OptionalParseResult parseOptionalAttribute(AttrT &result, StringRef attrName, - NamedAttrList &attrs) { - return parseOptionalAttribute(result, Type(), attrName, attrs); - } - - /// Specialized variants of `parseOptionalAttribute` that remove potential - /// ambiguities in syntax. - virtual OptionalParseResult parseOptionalAttribute(ArrayAttr &result, - Type type, - StringRef attrName, - NamedAttrList &attrs) = 0; - virtual OptionalParseResult parseOptionalAttribute(StringAttr &result, - Type type, - StringRef attrName, - NamedAttrList &attrs) = 0; - /// Parse an arbitrary attribute of a given type and return it in result. This /// also adds the attribute to the specified attribute list with the specified /// name. @@ -683,6 +661,40 @@ public: return success(); } + /// Parse an arbitrary optional attribute of a given type and return it in + /// result. + virtual OptionalParseResult parseOptionalAttribute(Attribute &result, + Type type = {}) = 0; + + /// Parse an optional array attribute and return it in result. + virtual OptionalParseResult parseOptionalAttribute(ArrayAttr &result, + Type type = {}) = 0; + + /// Parse an optional string attribute and return it in result. + virtual OptionalParseResult parseOptionalAttribute(StringAttr &result, + Type type = {}) = 0; + + /// Parse an optional attribute of a specific type and add it to the list with + /// the specified name. + template + OptionalParseResult parseOptionalAttribute(AttrType &result, + StringRef attrName, + NamedAttrList &attrs) { + return parseOptionalAttribute(result, Type(), attrName, attrs); + } + + /// Parse an optional attribute of a specific type and add it to the list with + /// the specified name. + template + OptionalParseResult parseOptionalAttribute(AttrType &result, Type type, + StringRef attrName, + NamedAttrList &attrs) { + OptionalParseResult parseResult = parseOptionalAttribute(result, type); + if (parseResult.hasValue() && succeeded(*parseResult)) + attrs.append(attrName, result); + return parseResult; + } + /// Parse a named dictionary into 'result' if it is present. virtual ParseResult parseOptionalAttrDict(NamedAttrList &result) = 0; diff --git a/mlir/include/mlir/IR/OperationSupport.h b/mlir/include/mlir/IR/OperationSupport.h index 0ac793fdaa91d08c0de7b0f317a33834d2e0327e..1e85b4f0f7f919ee25cbe295a25ba221dc8f48cb 100644 --- a/mlir/include/mlir/IR/OperationSupport.h +++ b/mlir/include/mlir/IR/OperationSupport.h @@ -301,7 +301,7 @@ public: /// Replaces the attributes with new list of attributes. void assign(ArrayRef range) { - append(range.begin(), range.end()); + assign(range.begin(), range.end()); } bool empty() const { return attrs.empty(); } diff --git a/mlir/include/mlir/TableGen/Constraint.h b/mlir/include/mlir/TableGen/Constraint.h index 4a74cac6dc69ef647cae01dc63ffbbc732327e40..5ecf326da1e79965328f7defdbdc109403431e3f 100644 --- a/mlir/include/mlir/TableGen/Constraint.h +++ b/mlir/include/mlir/TableGen/Constraint.h @@ -59,6 +59,9 @@ public: return Constraint(reinterpret_cast(ptr)); } + // Return the underlying def. + const llvm::Record *getDef() const { return def; } + protected: Constraint(Kind kind, const llvm::Record *record); diff --git a/mlir/lib/Dialect/Math/Transforms/PolynomialApproximation.cpp b/mlir/lib/Dialect/Math/Transforms/PolynomialApproximation.cpp index 94442dd605415be9ad5aa30496743ed8b2a01e25..29fd0b6cda3ab8f776a698cb57f8067d6a0b1c26 100644 --- a/mlir/lib/Dialect/Math/Transforms/PolynomialApproximation.cpp +++ b/mlir/lib/Dialect/Math/Transforms/PolynomialApproximation.cpp @@ -209,8 +209,8 @@ TanhApproximation::matchAndRewrite(math::TanhOp op, }; // Clamp operand into [plusClamp, minusClamp] range. - Value minusClamp = bcast(f32Cst(builder, -7.9053111076354980f)); - Value plusClamp = bcast(f32Cst(builder, 7.90531110763549805f)); + Value minusClamp = bcast(f32Cst(builder, -7.99881172180175781f)); + Value plusClamp = bcast(f32Cst(builder, 7.99881172180175781f)); Value x = clamp(builder, op.operand(), minusClamp, plusClamp); // Mask for tiny values that are approximated with `operand`. diff --git a/mlir/lib/Dialect/SCF/SCF.cpp b/mlir/lib/Dialect/SCF/SCF.cpp index 05da1f56cf100fb63d478535397c77b7e55ee394..cc68ff622cdc56346d63a823a3199e35b3ea6910 100644 --- a/mlir/lib/Dialect/SCF/SCF.cpp +++ b/mlir/lib/Dialect/SCF/SCF.cpp @@ -1010,6 +1010,26 @@ void ForOp::getCanonicalizationPatterns(RewritePatternSet &results, // IfOp //===----------------------------------------------------------------------===// +bool mlir::scf::insideMutuallyExclusiveBranches(Operation *a, Operation *b) { + assert(a && "expected non-empty operation"); + assert(b && "expected non-empty operation"); + + IfOp ifOp = a->getParentOfType(); + while (ifOp) { + // Check if b is inside ifOp. (We already know that a is.) + if (ifOp->isProperAncestor(b)) + // b is contained in ifOp. a and b are in mutually exclusive branches if + // they are in different blocks of ifOp. + return static_cast(ifOp.thenBlock()->findAncestorOpInBlock(*a)) != + static_cast(ifOp.thenBlock()->findAncestorOpInBlock(*b)); + // Check next enclosing IfOp. + ifOp = ifOp->getParentOfType(); + } + + // Could not find a common IfOp among a's and b's ancestors. + return false; +} + void IfOp::build(OpBuilder &builder, OperationState &result, Value cond, bool withElseRegion) { build(builder, result, /*resultTypes=*/llvm::None, cond, withElseRegion); diff --git a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp index 8a0e4677d5056352ca8d2379f169f4d97518c489..bb499be5052a3f02e8a3ad8364689c4763741412 100644 --- a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp +++ b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp @@ -240,8 +240,11 @@ static LogicalResult verify(ConvertOp op) { assert(tp1.getRank() == tp2.getRank()); auto shape1 = tp1.getShape(); auto shape2 = tp2.getShape(); + // Accept size matches between the source and the destination type + // (e.g. 10 vs. 10, 10 vs. ?, or ? vs. ?), but reject direct mismatches or + // matches that would need a runtime assert (e.g. 10 vs. 20 or ? vs. 10). for (unsigned d = 0, rank = tp1.getRank(); d < rank; d++) { - if (shape1[d] != shape2[d]) + if (shape1[d] != shape2[d] && shape2[d] != ShapedType::kDynamicSize) return op.emitError("unexpected conversion mismatch in dimension ") << d; } diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp index e98b1fa2617314fd088b0264b24c1c3af35a9589..ffd852fef7333976137fd1a0c7fe4a429ff65bdd 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp @@ -99,7 +99,7 @@ inline static Value constantZero(ConversionPatternRewriter &rewriter, /// Generates a constant of `index` type. inline static Value constantIndex(ConversionPatternRewriter &rewriter, - Location loc, unsigned i) { + Location loc, int64_t i) { return rewriter.create(loc, i); } @@ -144,6 +144,70 @@ static FlatSymbolRefAttr getFunc(Operation *op, StringRef name, return result; } +/// Generates dimension size call. +static Value genDimSizeCall(ConversionPatternRewriter &rewriter, Operation *op, + SparseTensorEncodingAttr &enc, Value src, + int64_t idx) { + // Permute the index according to an optional dimension ordering. + if (AffineMap p = enc.getDimOrdering()) + idx = p.getPermutedPosition(idx); + // Generate the call. + Location loc = op->getLoc(); + StringRef name = "sparseDimSize"; + SmallVector params; + params.push_back(src); + params.push_back(constantIndex(rewriter, loc, idx)); + Type iTp = rewriter.getIndexType(); + auto fn = getFunc(op, name, iTp, params); + return rewriter.create(loc, iTp, fn, params).getResult(0); +} + +/// Generates a call into the "swiss army knife" method of the sparse runtime +/// support library for materializing sparse tensors into the computation. +static Value genNewCall(ConversionPatternRewriter &rewriter, Operation *op, + ArrayRef params) { + Location loc = op->getLoc(); + StringRef name = "newSparseTensor"; + Type pTp = LLVM::LLVMPointerType::get(rewriter.getI8Type()); + auto fn = getFunc(op, name, pTp, params, /*emitCInterface=*/true); + auto call = rewriter.create(loc, pTp, fn, params); + return call.getResult(0); +} + +/// Populates given sizes array from type. +static void sizesFromType(ConversionPatternRewriter &rewriter, + SmallVector &sizes, Location loc, + ShapedType stp) { + auto shape = stp.getShape(); + for (unsigned i = 0, rank = stp.getRank(); i < rank; i++) { + uint64_t s = shape[i] == ShapedType::kDynamicSize ? 0 : shape[i]; + sizes.push_back(constantIndex(rewriter, loc, s)); + } +} + +/// Populates given sizes array from source. +static void sizesFromSrc(ConversionPatternRewriter &rewriter, + SmallVector &sizes, Location loc, + Value src) { + ShapedType stp = src.getType().cast(); + for (unsigned i = 0, rank = stp.getRank(); i < rank; i++) + sizes.push_back(linalg::createOrFoldDimOp(rewriter, loc, src, i)); +} + +/// Populates given sizes array from type (for static sizes) and from +/// an already converted into opague pointer source (for dynamic sizes). +static void sizesFromPtr(ConversionPatternRewriter &rewriter, + SmallVector &sizes, Operation *op, + SparseTensorEncodingAttr &enc, ShapedType stp, + Value src) { + auto shape = stp.getShape(); + for (unsigned i = 0, rank = stp.getRank(); i < rank; i++) + if (shape[i] == ShapedType::kDynamicSize) + sizes.push_back(genDimSizeCall(rewriter, op, enc, src, i)); + else + sizes.push_back(constantIndex(rewriter, op->getLoc(), shape[i])); +} + /// Generates a temporary buffer of the given size and type. static Value genAlloca(ConversionPatternRewriter &rewriter, Location loc, unsigned sz, Type tp) { @@ -152,7 +216,7 @@ static Value genAlloca(ConversionPatternRewriter &rewriter, Location loc, return rewriter.create(loc, memTp, ValueRange{a}); } -/// Fills a temporary buffer of the given type with arguments. +/// Generates a temporary buffer of the given type and given contents. static Value genBuffer(ConversionPatternRewriter &rewriter, Location loc, ArrayRef values) { unsigned sz = values.size(); @@ -165,36 +229,28 @@ static Value genBuffer(ConversionPatternRewriter &rewriter, Location loc, return buffer; } -/// Generates a call into the "swiss army knife" method of the sparse runtime -/// support library for materializing sparse tensors into the computation. The -/// method returns the call value and assigns the permutation to 'perm'. -static Value genNewCall(ConversionPatternRewriter &rewriter, Operation *op, - SparseTensorEncodingAttr &enc, uint32_t action, - Value &perm, ValueRange szs, Value ptr = Value()) { +/// Populates parameters required to call the "swiss army knife" method of the +/// sparse runtime support library for materializing sparse tensors into the +/// computation. +static void newParams(ConversionPatternRewriter &rewriter, + SmallVector ¶ms, Operation *op, + SparseTensorEncodingAttr &enc, uint32_t action, + ValueRange szs, Value ptr = Value()) { Location loc = op->getLoc(); - ShapedType resType = op->getResult(0).getType().cast(); - SmallVector params; - // Sparsity annotations in tensor constant form. - SmallVector attrs; ArrayRef dlt = enc.getDimLevelType(); unsigned sz = dlt.size(); + // Sparsity annotations. + SmallVector attrs; for (unsigned i = 0; i < sz; i++) attrs.push_back(constantI8(rewriter, loc, getDimLevelTypeEncoding(dlt[i]))); params.push_back(genBuffer(rewriter, loc, attrs)); - // Dimension sizes array of the enveloping *dense* tensor. Useful for either + // Dimension sizes array of the enveloping tensor. Useful for either // verification of external data, or for construction of internal data. - auto shape = resType.getShape(); + // The index type is casted to I64 for API consistency. + Type iTp = rewriter.getI64Type(); SmallVector sizes; - if (szs.size() > 0) { - for (Value s : szs) - sizes.push_back( - rewriter.create(loc, s, rewriter.getI64Type())); - } else { - for (unsigned i = 0; i < sz; i++) { - uint64_t s = shape[i] == ShapedType::kDynamicSize ? 0 : shape[i]; - sizes.push_back(constantI64(rewriter, loc, s)); - } - } + for (Value s : szs) + sizes.push_back(rewriter.create(loc, s, iTp)); params.push_back(genBuffer(rewriter, loc, sizes)); // Dimension order permutation array. This is the "identity" permutation by // default, or otherwise the "reverse" permutation of a given ordering, so @@ -207,9 +263,9 @@ static Value genNewCall(ConversionPatternRewriter &rewriter, Operation *op, for (unsigned i = 0; i < sz; i++) rev[i] = constantI64(rewriter, loc, i); } - perm = genBuffer(rewriter, loc, rev); - params.push_back(perm); + params.push_back(genBuffer(rewriter, loc, rev)); // Secondary and primary types encoding. + ShapedType resType = op->getResult(0).getType().cast(); unsigned secPtr = getOverheadTypeEncoding(enc.getPointerBitWidth()); unsigned secInd = getOverheadTypeEncoding(enc.getIndexBitWidth()); unsigned primary = getPrimaryTypeEncoding(resType.getElementType()); @@ -223,12 +279,6 @@ static Value genNewCall(ConversionPatternRewriter &rewriter, Operation *op, ptr = rewriter.create(loc, pTp); params.push_back(constantI32(rewriter, loc, action)); params.push_back(ptr); - // Generate the call to create new tensor. - StringRef name = "newSparseTensor"; - auto call = rewriter.create( - loc, pTp, getFunc(op, name, pTp, params, /*emitCInterface=*/true), - params); - return call.getResult(0); } /// Generates the comparison `v != 0` where `v` is of numeric type `t`. @@ -299,9 +349,8 @@ static void genAddEltCall(ConversionPatternRewriter &rewriter, Operation *op, params.push_back(ind); params.push_back(perm); Type pTp = LLVM::LLVMPointerType::get(rewriter.getI8Type()); - rewriter.create( - loc, pTp, getFunc(op, name, pTp, params, /*emitCInterface=*/true), - params); + auto fn = getFunc(op, name, pTp, params, /*emitCInterface=*/true); + rewriter.create(loc, pTp, fn, params); } /// If the tensor is a sparse constant, generates and returns the pair of @@ -362,24 +411,17 @@ public: LogicalResult matchAndRewrite(tensor::DimOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { - Type resType = op.getType(); + // Only rewrite annotated DimOp with constant index. auto enc = getSparseTensorEncoding(op.source().getType()); if (!enc) return failure(); - // Permute the dim index. Optional index = op.getConstantIndex(); if (!index.hasValue()) return failure(); - int64_t idx = index.getValue(); - if (AffineMap p = enc.getDimOrdering()) - idx = p.getPermutedPosition(idx); // Generate the call. - StringRef name = "sparseDimSize"; - SmallVector params; - params.push_back(adaptor.getOperands()[0]); - params.push_back(constantIndex(rewriter, op.getLoc(), idx)); - rewriter.replaceOpWithNewOp( - op, resType, getFunc(op, name, resType, params), params); + Value src = adaptor.getOperands()[0]; + int64_t idx = index.getValue(); + rewriter.replaceOp(op, genDimSizeCall(rewriter, op, enc, src, idx)); return success(); } }; @@ -394,9 +436,14 @@ class SparseTensorNewConverter : public OpConversionPattern { auto enc = getSparseTensorEncoding(resType); if (!enc) return failure(); - Value perm; - rewriter.replaceOp(op, genNewCall(rewriter, op, enc, kFromFile, perm, {}, - adaptor.getOperands()[0])); + // Generate the call to construct tensor from ptr. The sizes are + // inferred from the result type of the new operator. + SmallVector sizes; + SmallVector params; + sizesFromType(rewriter, sizes, op.getLoc(), resType.cast()); + Value ptr = adaptor.getOperands()[0]; + newParams(rewriter, params, op, enc, kFromFile, sizes, ptr); + rewriter.replaceOp(op, genNewCall(rewriter, op, params)); return success(); } }; @@ -411,9 +458,11 @@ class SparseTensorInitConverter : public OpConversionPattern { auto enc = getSparseTensorEncoding(resType); if (!enc) return failure(); - Value perm; - rewriter.replaceOp( - op, genNewCall(rewriter, op, enc, kEmpty, perm, adaptor.getOperands())); + // Generate the call to construct empty tensor. The sizes are + // explicitly defined by the arguments to the init operator. + SmallVector params; + newParams(rewriter, params, op, enc, kEmpty, adaptor.getOperands()); + rewriter.replaceOp(op, genNewCall(rewriter, op, params)); return success(); } }; @@ -424,10 +473,12 @@ class SparseTensorConvertConverter : public OpConversionPattern { LogicalResult matchAndRewrite(ConvertOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { + Location loc = op->getLoc(); Type resType = op.getType(); + Type srcType = op.source().getType(); auto encDst = getSparseTensorEncoding(resType); - auto encSrc = getSparseTensorEncoding(op.source().getType()); - auto src = adaptor.getOperands()[0]; + auto encSrc = getSparseTensorEncoding(srcType); + Value src = adaptor.getOperands()[0]; if (encDst && encSrc) { // This is a sparse => sparse conversion, which is handled as follows: // t = src->toCOO(); ; src to COO in dst order @@ -435,10 +486,15 @@ class SparseTensorConvertConverter : public OpConversionPattern { // Using the coordinate scheme as an intermediate does not always // yield the fastest conversion but avoids the need for a full // O(N^2) conversion matrix. - Value perm; - Value coo = genNewCall(rewriter, op, encDst, kToCOO, perm, {}, src); - rewriter.replaceOp( - op, genNewCall(rewriter, op, encDst, kFromCOO, perm, {}, coo)); + SmallVector sizes; + SmallVector params; + sizesFromPtr(rewriter, sizes, op, encSrc, srcType.cast(), + src); + newParams(rewriter, params, op, encDst, kToCOO, sizes, src); + Value coo = genNewCall(rewriter, op, params); + params[6] = constantI32(rewriter, loc, kFromCOO); + params[7] = coo; + rewriter.replaceOp(op, genNewCall(rewriter, op, params)); return success(); } if (!encDst || encSrc) { @@ -471,12 +527,15 @@ class SparseTensorConvertConverter : public OpConversionPattern { // Also note that the code below only generates the "new" ops and // the loop-nest per se; whereas the entire body of the innermost // loop is generated by genAddElt(). - Location loc = op->getLoc(); - ShapedType shape = resType.cast(); - Value perm; - Value ptr = genNewCall(rewriter, op, encDst, kEmptyCOO, perm, {}); - Value ind = - genAlloca(rewriter, loc, shape.getRank(), rewriter.getIndexType()); + ShapedType stp = resType.cast(); + unsigned rank = stp.getRank(); + SmallVector sizes; + SmallVector params; + sizesFromSrc(rewriter, sizes, loc, src); + newParams(rewriter, params, op, encDst, kEmptyCOO, sizes); + Value ptr = genNewCall(rewriter, op, params); + Value ind = genAlloca(rewriter, loc, rank, rewriter.getIndexType()); + Value perm = params[2]; SmallVector lo; SmallVector hi; SmallVector st; @@ -493,14 +552,13 @@ class SparseTensorConvertConverter : public OpConversionPattern { hi.push_back(linalg::createOrFoldDimOp(rewriter, loc, values, 0)); st.push_back(one); } else { - for (unsigned i = 0, rank = shape.getRank(); i < rank; i++) { + for (unsigned i = 0; i < rank; i++) { lo.push_back(zero); hi.push_back(linalg::createOrFoldDimOp(rewriter, loc, src, i)); st.push_back(one); } } - Type eltType = shape.getElementType(); - unsigned rank = shape.getRank(); + Type eltType = stp.getElementType(); scf::buildLoopNest( rewriter, op.getLoc(), lo, hi, st, {}, [&](OpBuilder &builder, Location loc, ValueRange ivs, @@ -514,8 +572,10 @@ class SparseTensorConvertConverter : public OpConversionPattern { genAddEltCall(rewriter, op, eltType, ptr, val, ind, perm); return {}; }); - rewriter.replaceOp( - op, genNewCall(rewriter, op, encDst, kFromCOO, perm, {}, ptr)); + // Final call to construct sparse tensor storage. + params[6] = constantI32(rewriter, loc, kFromCOO); + params[7] = ptr; + rewriter.replaceOp(op, genNewCall(rewriter, op, params)); return success(); } }; @@ -529,9 +589,8 @@ public: ConversionPatternRewriter &rewriter) const override { StringRef name = "delSparseTensor"; TypeRange none; - rewriter.create(op.getLoc(), none, - getFunc(op, name, none, adaptor.getOperands()), - adaptor.getOperands()); + auto fn = getFunc(op, name, none, adaptor.getOperands()); + rewriter.create(op.getLoc(), none, fn, adaptor.getOperands()); rewriter.eraseOp(op); return success(); } @@ -560,11 +619,9 @@ public: name = "sparsePointers8"; else return failure(); - rewriter.replaceOpWithNewOp(op, resType, - getFunc(op, name, resType, - adaptor.getOperands(), - /*emitCInterface=*/true), - adaptor.getOperands()); + auto fn = getFunc(op, name, resType, adaptor.getOperands(), + /*emitCInterface=*/true); + rewriter.replaceOpWithNewOp(op, resType, fn, adaptor.getOperands()); return success(); } }; @@ -591,11 +648,9 @@ public: name = "sparseIndices8"; else return failure(); - rewriter.replaceOpWithNewOp(op, resType, - getFunc(op, name, resType, - adaptor.getOperands(), - /*emitCInterface=*/true), - adaptor.getOperands()); + auto fn = getFunc(op, name, resType, adaptor.getOperands(), + /*emitCInterface=*/true); + rewriter.replaceOpWithNewOp(op, resType, fn, adaptor.getOperands()); return success(); } }; @@ -624,11 +679,9 @@ public: name = "sparseValuesI8"; else return failure(); - rewriter.replaceOpWithNewOp(op, resType, - getFunc(op, name, resType, - adaptor.getOperands(), - /*emitCInterface=*/true), - adaptor.getOperands()); + auto fn = getFunc(op, name, resType, adaptor.getOperands(), + /*emitCInterface=*/true); + rewriter.replaceOpWithNewOp(op, resType, fn, adaptor.getOperands()); return success(); } }; diff --git a/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp b/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp index 9c8d4ac54a8486ccc1b8e03a8d60d9fd9b4f32be..2ad14f5bf1809db31f65319708343f2f3e226a2c 100644 --- a/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp +++ b/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp @@ -222,9 +222,37 @@ struct ConstantTransposeOptimization } }; +struct NoOpOptimization : public OpRewritePattern { + using OpRewritePattern::OpRewritePattern; + + LogicalResult matchAndRewrite(tosa::TransposeOp op, + PatternRewriter &rewriter) const override { + auto perm = op.perms(); + + DenseIntElementsAttr permAttr; + if (!matchPattern(perm, m_Constant(&permAttr))) { + return failure(); + } + + SmallVector permValues = llvm::to_vector<6>( + llvm::map_range(permAttr.getValues(), + [](const APInt &val) { return val.getSExtValue(); })); + + for (int i = 0, s = permValues.size(); i < s; i++) { + if (i != permValues[i]) { + return failure(); + } + } + + rewriter.replaceOp(op, op.input1()); + return success(); + } +}; + void TransposeOp::getCanonicalizationPatterns(OwningRewritePatternList &results, MLIRContext *context) { results.insert(context); + results.insert(context); } //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Dialect/Vector/VectorOps.cpp b/mlir/lib/Dialect/Vector/VectorOps.cpp index ee87e5b3eec1fa7329ac4aade6963d95fe730730..fdec267934bb739866dc525dfa0f6db435e2feaf 100644 --- a/mlir/lib/Dialect/Vector/VectorOps.cpp +++ b/mlir/lib/Dialect/Vector/VectorOps.cpp @@ -3634,6 +3634,20 @@ OpFoldResult ShapeCastOp::fold(ArrayRef operands) { if (auto otherOp = source().getDefiningOp()) { if (result().getType() == otherOp.source().getType()) return otherOp.source(); + + // Only allows valid transitive folding. + VectorType srcType = otherOp.source().getType().cast(); + VectorType resultType = getResult().getType().cast(); + if (srcType.getRank() < resultType.getRank()) { + if (!isValidShapeCast(srcType.getShape(), resultType.getShape())) + return {}; + } else if (srcType.getRank() > resultType.getRank()) { + if (!isValidShapeCast(resultType.getShape(), srcType.getShape())) + return {}; + } else { + return {}; + } + setOperand(otherOp.source()); return getResult(); } diff --git a/mlir/lib/IR/BuiltinAttributes.cpp b/mlir/lib/IR/BuiltinAttributes.cpp index 27d851c6594ee5e85482583c79b752f02b0cb12f..9bb90a035e341820931cf561caf5f280196a18cf 100644 --- a/mlir/lib/IR/BuiltinAttributes.cpp +++ b/mlir/lib/IR/BuiltinAttributes.cpp @@ -68,6 +68,8 @@ static bool dictionaryAttrSort(ArrayRef value, switch (value.size()) { case 0: // Zero already sorted. + if (!inPlace) + storage.clear(); break; case 1: // One already sorted but may need to be copied. diff --git a/mlir/lib/IR/Diagnostics.cpp b/mlir/lib/IR/Diagnostics.cpp index 339f5607abdb3137705d7abd4b704d09b0533cef..31391b2b9405eeb017eabf0fd35a6723ceddacf4 100644 --- a/mlir/lib/IR/Diagnostics.cpp +++ b/mlir/lib/IR/Diagnostics.cpp @@ -127,9 +127,13 @@ Diagnostic &Diagnostic::operator<<(OperationName val) { /// Stream in an Operation. Diagnostic &Diagnostic::operator<<(Operation &val) { + return appendOp(val, OpPrintingFlags()); +} +Diagnostic &Diagnostic::appendOp(Operation &val, const OpPrintingFlags &flags) { std::string str; llvm::raw_string_ostream os(str); - val.print(os, OpPrintingFlags().useLocalScope().elideLargeElementsAttrs()); + val.print(os, + OpPrintingFlags(flags).useLocalScope().elideLargeElementsAttrs()); return *this << os.str(); } diff --git a/mlir/lib/IR/Operation.cpp b/mlir/lib/IR/Operation.cpp index 8eb4c612dd612b3a2bfdfe3e046a1bbcfc0c764e..e877449fa83fbf85d4cc238b44f844d92e15517d 100644 --- a/mlir/lib/IR/Operation.cpp +++ b/mlir/lib/IR/Operation.cpp @@ -276,17 +276,9 @@ void Operation::insertOperands(unsigned index, ValueRange operands) { InFlightDiagnostic Operation::emitError(const Twine &message) { InFlightDiagnostic diag = mlir::emitError(getLoc(), message); if (getContext()->shouldPrintOpOnDiagnostic()) { - // Print out the operation explicitly here so that we can print the generic - // form. - // TODO: It would be nice if we could instead provide the - // specific printing flags when adding the operation as an argument to the - // diagnostic. - std::string printedOp; - { - llvm::raw_string_ostream os(printedOp); - print(os, OpPrintingFlags().printGenericOpForm().useLocalScope()); - } - diag.attachNote(getLoc()) << "see current operation: " << printedOp; + diag.attachNote(getLoc()) + .append("see current operation: ") + .appendOp(*this, OpPrintingFlags().printGenericOpForm()); } return diag; } diff --git a/mlir/lib/Parser/AsmParserImpl.h b/mlir/lib/Parser/AsmParserImpl.h index 2d35225717bbaf291fa372f9484954c30bc01517..70039c2736a426d7839c99fd07e039b07aa0d230 100644 --- a/mlir/lib/Parser/AsmParserImpl.h +++ b/mlir/lib/Parser/AsmParserImpl.h @@ -343,31 +343,17 @@ public: return success(static_cast(result)); } - /// Parse an optional attribute. - template - OptionalParseResult - parseOptionalAttributeAndAddToList(AttrT &result, Type type, - StringRef attrName, NamedAttrList &attrs) { - OptionalParseResult parseResult = - parser.parseOptionalAttribute(result, type); - if (parseResult.hasValue() && succeeded(*parseResult)) - attrs.push_back(parser.builder.getNamedAttr(attrName, result)); - return parseResult; - } - OptionalParseResult parseOptionalAttribute(Attribute &result, Type type, - StringRef attrName, - NamedAttrList &attrs) override { - return parseOptionalAttributeAndAddToList(result, type, attrName, attrs); - } - OptionalParseResult parseOptionalAttribute(ArrayAttr &result, Type type, - StringRef attrName, - NamedAttrList &attrs) override { - return parseOptionalAttributeAndAddToList(result, type, attrName, attrs); - } - OptionalParseResult parseOptionalAttribute(StringAttr &result, Type type, - StringRef attrName, - NamedAttrList &attrs) override { - return parseOptionalAttributeAndAddToList(result, type, attrName, attrs); + OptionalParseResult parseOptionalAttribute(Attribute &result, + Type type) override { + return parser.parseOptionalAttribute(result, type); + } + OptionalParseResult parseOptionalAttribute(ArrayAttr &result, + Type type) override { + return parser.parseOptionalAttribute(result, type); + } + OptionalParseResult parseOptionalAttribute(StringAttr &result, + Type type) override { + return parser.parseOptionalAttribute(result, type); } /// Parse a named dictionary into 'result' if it is present. diff --git a/mlir/lib/Pass/PassCrashRecovery.cpp b/mlir/lib/Pass/PassCrashRecovery.cpp index d4657b072f7c6a8e29e35f63214657507a4622de..fdc995c335ccc9393879f2b5f43a5bde37676ed8 100644 --- a/mlir/lib/Pass/PassCrashRecovery.cpp +++ b/mlir/lib/Pass/PassCrashRecovery.cpp @@ -153,8 +153,7 @@ void RecoveryReproducerContext::crashHandler(void *) { context->generate(description); // Emit an error using information only available within the context. - context->preCrashOperation->getContext()->printOpOnDiagnostic(false); - context->preCrashOperation->emitError() + emitError(context->preCrashOperation->getLoc()) << "A failure has been detected while processing the MLIR module:" << description; } @@ -235,13 +234,9 @@ void PassCrashReproducerGenerator::finalize(Operation *rootOp, if (succeeded(executionResult)) return impl->activeContexts.clear(); - MLIRContext *context = rootOp->getContext(); - bool shouldPrintOnOp = context->shouldPrintOpOnDiagnostic(); - context->printOpOnDiagnostic(false); - InFlightDiagnostic diag = rootOp->emitError() + InFlightDiagnostic diag = emitError(rootOp->getLoc()) << "Failures have been detected while " "processing an MLIR pass pipeline"; - context->printOpOnDiagnostic(shouldPrintOnOp); // If we are generating a global reproducer, we include all of the running // passes in the error message for the only active context. diff --git a/mlir/test/Dialect/Math/polynomial-approximation.mlir b/mlir/test/Dialect/Math/polynomial-approximation.mlir index 3ffc108534506fcfd02792ddf1ff7e92c71190e4..7d9ec8832acf17b7c63820c09a5c3ea513ffcd0b 100644 --- a/mlir/test/Dialect/Math/polynomial-approximation.mlir +++ b/mlir/test/Dialect/Math/polynomial-approximation.mlir @@ -248,8 +248,8 @@ func @log1p_vector(%arg0: vector<8xf32>) -> vector<8xf32> { // CHECK-LABEL: func @tanh_scalar( // CHECK-SAME: %[[VAL_0:.*]]: f32) -> f32 { -// CHECK: %[[VAL_1:.*]] = arith.constant -7.90531111 : f32 -// CHECK: %[[VAL_2:.*]] = arith.constant 7.90531111 : f32 +// CHECK: %[[VAL_1:.*]] = arith.constant -7.99881172 : f32 +// CHECK: %[[VAL_2:.*]] = arith.constant 7.99881172 : f32 // CHECK: %[[VAL_3:.*]] = arith.constant 4.000000e-04 : f32 // CHECK: %[[VAL_4:.*]] = arith.constant 0.00489352457 : f32 // CHECK: %[[VAL_5:.*]] = arith.constant 6.37261954E-4 : f32 @@ -290,7 +290,7 @@ func @tanh_scalar(%arg0: f32) -> f32 { // CHECK-LABEL: func @tanh_vector( // CHECK-SAME: %[[VAL_0:.*]]: vector<8xf32>) -> vector<8xf32> { -// CHECK: %[[VAL_1:.*]] = arith.constant dense<-7.90531111> : vector<8xf32> +// CHECK: %[[VAL_1:.*]] = arith.constant dense<-7.99881172> : vector<8xf32> // CHECK-NOT: tanh // CHECK-COUNT-2: select // CHECK: %[[VAL_33:.*]] = select diff --git a/mlir/test/Dialect/SparseTensor/conversion.mlir b/mlir/test/Dialect/SparseTensor/conversion.mlir index d6e43079d8c0bb7a2cabe94207e6efdf196e0393..577b79c6e9b0c57f1f47b1d9407ea4e97199d3ff 100644 --- a/mlir/test/Dialect/SparseTensor/conversion.mlir +++ b/mlir/test/Dialect/SparseTensor/conversion.mlir @@ -127,8 +127,8 @@ func @sparse_new3d(%arg0: !llvm.ptr) -> tensor { // CHECK-DAG: %[[JJ:.*]] = arith.index_cast %[[J]] : index to i64 // CHECK-DAG: memref.store %[[II]], %[[Q]][%[[C0]]] : memref<2xi64> // CHECK-DAG: memref.store %[[JJ]], %[[Q]][%[[C1]]] : memref<2xi64> -// CHECK: %[[A:.*]] = llvm.mlir.null : !llvm.ptr -// CHECK: %[[T:.*]] = call @newSparseTensor(%[[X]], %[[Y]], %[[Z]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[A]]) +// CHECK: %[[NP:.*]] = llvm.mlir.null : !llvm.ptr +// CHECK: %[[T:.*]] = call @newSparseTensor(%[[X]], %[[Y]], %[[Z]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[NP]]) // CHECK: return %[[T]] : !llvm.ptr func @sparse_init(%arg0: index, %arg1: index) -> tensor { %0 = sparse_tensor.init [%arg0, %arg1] : tensor @@ -156,22 +156,23 @@ func @sparse_nop_convert(%arg0: tensor<64xf32, #SparseVector>) -> tensor<64xf32, // CHECK-SAME: %[[A:.*]]: tensor) -> !llvm.ptr // CHECK-DAG: %[[C0:.*]] = arith.constant 0 : index // CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index +// CHECK-DAG: %[[U:.*]] = tensor.dim %[[A]], %[[C0]] : tensor // CHECK-DAG: %[[P:.*]] = memref.alloca() : memref<1xi8> // CHECK-DAG: %[[Q:.*]] = memref.alloca() : memref<1xi64> // CHECK-DAG: %[[R:.*]] = memref.alloca() : memref<1xi64> // CHECK-DAG: %[[X:.*]] = memref.cast %[[P]] : memref<1xi8> to memref // CHECK-DAG: %[[Y:.*]] = memref.cast %[[Q]] : memref<1xi64> to memref // CHECK-DAG: %[[Z:.*]] = memref.cast %[[R]] : memref<1xi64> to memref -// CHECK: %[[C:.*]] = call @newSparseTensor(%[[X]], %[[Y]], %[[Z]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.}}) +// CHECK: %[[NP:.*]] = llvm.mlir.null : !llvm.ptr +// CHECK: %[[C:.*]] = call @newSparseTensor(%[[X]], %[[Y]], %[[Z]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[NP]]) // CHECK: %[[M:.*]] = memref.alloca() : memref<1xindex> // CHECK: %[[T:.*]] = memref.cast %[[M]] : memref<1xindex> to memref -// CHECK: %[[U:.*]] = tensor.dim %[[A]], %[[C0]] : tensor // CHECK: scf.for %[[I:.*]] = %[[C0]] to %[[U]] step %[[C1]] { // CHECK: %[[E:.*]] = tensor.extract %[[A]][%[[I]]] : tensor // CHECK: memref.store %[[I]], %[[M]][%[[C0]]] : memref<1xindex> // CHECK: call @addEltI32(%[[C]], %[[E]], %[[T]], %[[Z]]) // CHECK: } -// CHECK: %[[T:.*]] = call @newSparseTensor(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[C]]) +// CHECK: %[[T:.*]] = call @newSparseTensor(%[[X]], %[[Y]], %[[Z]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[C]]) // CHECK: return %[[T]] : !llvm.ptr func @sparse_convert_1d(%arg0: tensor) -> tensor { %0 = sparse_tensor.convert %arg0 : tensor to tensor @@ -180,8 +181,14 @@ func @sparse_convert_1d(%arg0: tensor) -> tensor { // CHECK-LABEL: func @sparse_convert_1d_ss( // CHECK-SAME: %[[A:.*]]: !llvm.ptr) -// CHECK: %[[C:.*]] = call @newSparseTensor(%{{.}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[A]]) -// CHECK: %[[T:.*]] = call @newSparseTensor(%{{.}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[C]]) +// CHECK-DAG: %[[P:.*]] = memref.alloca() : memref<1xi8> +// CHECK-DAG: %[[Q:.*]] = memref.alloca() : memref<1xi64> +// CHECK-DAG: %[[R:.*]] = memref.alloca() : memref<1xi64> +// CHECK-DAG: %[[X:.*]] = memref.cast %[[P]] : memref<1xi8> to memref +// CHECK-DAG: %[[Y:.*]] = memref.cast %[[Q]] : memref<1xi64> to memref +// CHECK-DAG: %[[Z:.*]] = memref.cast %[[R]] : memref<1xi64> to memref +// CHECK: %[[C:.*]] = call @newSparseTensor(%[[X]], %[[Y]], %[[Z]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[A]]) +// CHECK: %[[T:.*]] = call @newSparseTensor(%[[X]], %[[Y]], %[[Z]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[C]]) // CHECK: return %[[T]] : !llvm.ptr func @sparse_convert_1d_ss(%arg0: tensor) -> tensor { %0 = sparse_tensor.convert %arg0 : tensor to tensor @@ -198,7 +205,8 @@ func @sparse_convert_1d_ss(%arg0: tensor) -> tensor to memref // CHECK-DAG: %[[Y:.*]] = memref.cast %[[Q]] : memref<2xi64> to memref // CHECK-DAG: %[[Z:.*]] = memref.cast %[[R]] : memref<2xi64> to memref -// CHECK: %[[C:.*]] = call @newSparseTensor(%[[X]], %[[Y]], %[[Z]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.}}) +// CHECK: %[[NP:.*]] = llvm.mlir.null : !llvm.ptr +// CHECK: %[[C:.*]] = call @newSparseTensor(%[[X]], %[[Y]], %[[Z]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[NP]]) // CHECK: %[[M:.*]] = memref.alloca() : memref<2xindex> // CHECK: %[[T:.*]] = memref.cast %[[M]] : memref<2xindex> to memref // CHECK: scf.for %[[I:.*]] = %[[C0]] to %{{.*}} step %[[C1]] { @@ -209,7 +217,7 @@ func @sparse_convert_1d_ss(%arg0: tensor) -> tensor func @sparse_convert_2d(%arg0: tensor<2x4xf64>) -> tensor<2x4xf64, #SparseMatrix> { %0 = sparse_tensor.convert %arg0 : tensor<2x4xf64> to tensor<2x4xf64, #SparseMatrix> @@ -226,7 +234,8 @@ func @sparse_convert_2d(%arg0: tensor<2x4xf64>) -> tensor<2x4xf64, #SparseMatrix // CHECK-DAG: %[[X:.*]] = memref.cast %[[P]] : memref<2xi8> to memref // CHECK-DAG: %[[Y:.*]] = memref.cast %[[Q]] : memref<2xi64> to memref // CHECK-DAG: %[[Z:.*]] = memref.cast %[[R]] : memref<2xi64> to memref -// CHECK: %[[C:.*]] = call @newSparseTensor(%[[X]], %[[Y]], %[[Z]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.}}) +// CHECK: %[[NP:.*]] = llvm.mlir.null : !llvm.ptr +// CHECK: %[[C:.*]] = call @newSparseTensor(%[[X]], %[[Y]], %[[Z]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[NP]]) // CHECK: %[[M:.*]] = memref.alloca() : memref<2xindex> // CHECK: %[[N:.*]] = memref.cast %[[M]] : memref<2xindex> to memref // CHECK: scf.for %[[I:.*]] = %[[C0]] to %[[C2]] step %[[C1]] { @@ -235,7 +244,7 @@ func @sparse_convert_2d(%arg0: tensor<2x4xf64>) -> tensor<2x4xf64, #SparseMatrix // CHECK: %[[V:.*]] = tensor.extract %{{.*}}[%[[I]]] : tensor<2xf32> // CHECK: call @addEltF32(%{{.*}}, %[[V]], %[[N]], %{{.*}}) // CHECK: } -// CHECK: %[[T:.*]] = call @newSparseTensor(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[C]]) +// CHECK: %[[T:.*]] = call @newSparseTensor(%[[X]], %[[Y]], %[[Z]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[C]]) // CHECK: return %[[T]] : !llvm.ptr func @sparse_constant() -> tensor<8x7xf32, #SparseMatrix>{ // Initialize a tensor. @@ -250,18 +259,19 @@ func @sparse_constant() -> tensor<8x7xf32, #SparseMatrix>{ // CHECK-DAG: %[[C0:.*]] = arith.constant 0 : index // CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index // CHECK-DAG: %[[C2:.*]] = arith.constant 2 : index +// CHECK-DAG: %[[U1:.*]] = tensor.dim %[[A]], %[[C0]] : tensor +// CHECK-DAG: %[[U2:.*]] = tensor.dim %[[A]], %[[C1]] : tensor +// CHECK-DAG: %[[U3:.*]] = tensor.dim %[[A]], %[[C2]] : tensor // CHECK-DAG: %[[P:.*]] = memref.alloca() : memref<3xi8> // CHECK-DAG: %[[Q:.*]] = memref.alloca() : memref<3xi64> // CHECK-DAG: %[[R:.*]] = memref.alloca() : memref<3xi64> // CHECK-DAG: %[[X:.*]] = memref.cast %[[P]] : memref<3xi8> to memref // CHECK-DAG: %[[Y:.*]] = memref.cast %[[Q]] : memref<3xi64> to memref // CHECK-DAG: %[[Z:.*]] = memref.cast %[[R]] : memref<3xi64> to memref -// CHECK: %[[C:.*]] = call @newSparseTensor(%[[X]], %[[Y]], %[[Z]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.}}) +// CHECK: %[[NP:.*]] = llvm.mlir.null : !llvm.ptr +// CHECK: %[[C:.*]] = call @newSparseTensor(%[[X]], %[[Y]], %[[Z]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[NP]]) // CHECK: %[[M:.*]] = memref.alloca() : memref<3xindex> // CHECK: %[[N:.*]] = memref.cast %[[M]] : memref<3xindex> to memref -// CHECK: %[[U1:.*]] = tensor.dim %[[A]], %[[C0]] : tensor -// CHECK: %[[U2:.*]] = tensor.dim %[[A]], %[[C1]] : tensor -// CHECK: %[[U3:.*]] = tensor.dim %[[A]], %[[C2]] : tensor // CHECK: scf.for %[[I:.*]] = %[[C0]] to %[[U1]] step %[[C1]] { // CHECK: scf.for %[[J:.*]] = %[[C0]] to %[[U2]] step %[[C1]] { // CHECK: scf.for %[[K:.*]] = %[[C0]] to %[[U3]] step %[[C1]] { @@ -273,7 +283,7 @@ func @sparse_constant() -> tensor<8x7xf32, #SparseMatrix>{ // CHECK: } // CHECK: } // CHECK: } -// CHECK: %[[T:.*]] = call @newSparseTensor(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[C]]) +// CHECK: %[[T:.*]] = call @newSparseTensor(%[[X]], %[[Y]], %[[Z]], %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %[[C]]) // CHECK: return %[[T]] : !llvm.ptr func @sparse_convert_3d(%arg0: tensor) -> tensor { %0 = sparse_tensor.convert %arg0 : tensor to tensor diff --git a/mlir/test/Dialect/SparseTensor/invalid.mlir b/mlir/test/Dialect/SparseTensor/invalid.mlir index 03abcb5e82d0b538517e77aacb63b67123d28790..89553595c81422927f72b7307486b4e9f65cfd08 100644 --- a/mlir/test/Dialect/SparseTensor/invalid.mlir +++ b/mlir/test/Dialect/SparseTensor/invalid.mlir @@ -162,8 +162,8 @@ func @sparse_convert_unranked(%arg0: tensor<*xf32>) -> tensor<10xf32> { #CSR = #sparse_tensor.encoding<{dimLevelType = ["dense", "compressed"]}> -func @sparse_convert_mismatch(%arg0: tensor<10x10xf32>) -> tensor<10x?xf32, #CSR> { +func @sparse_convert_mismatch(%arg0: tensor<10x?xf32>) -> tensor<10x10xf32, #CSR> { // expected-error@+1 {{unexpected conversion mismatch in dimension 1}} - %0 = sparse_tensor.convert %arg0 : tensor<10x10xf32> to tensor<10x?xf32, #CSR> - return %0 : tensor<10x?xf32, #CSR> + %0 = sparse_tensor.convert %arg0 : tensor<10x?xf32> to tensor<10x10xf32, #CSR> + return %0 : tensor<10x10xf32, #CSR> } diff --git a/mlir/test/Dialect/Tosa/canonicalize.mlir b/mlir/test/Dialect/Tosa/canonicalize.mlir index 5fe5bd44e14959782f393e20b6c3c525ab28a27b..983ce58c0c65275424cde0b06ed88126b8703a2e 100644 --- a/mlir/test/Dialect/Tosa/canonicalize.mlir +++ b/mlir/test/Dialect/Tosa/canonicalize.mlir @@ -233,7 +233,7 @@ func @transpose_nofold(%arg0: tensor<3x3xf32>) -> tensor<3x3xf32> { // CHECK-LABEL: @transpose_nofold_shape func @transpose_nofold_shape(%arg0: tensor<3x4xf32>) -> tensor { // CHECK: "tosa.transpose" - %0 = arith.constant dense<[0, 1]> : tensor<2xi32> + %0 = arith.constant dense<[1, 0]> : tensor<2xi32> %1 = "tosa.transpose"(%arg0, %0) { perms = [1, 0] }: (tensor<3x4xf32>, tensor<2xi32>) -> tensor return %1 : tensor } @@ -325,3 +325,14 @@ func @transpose_nofold_quantized_types() -> tensor<1x1x16x1x!quant.uniform, tensor<4xi32>) -> tensor<1x1x16x1x!quant.uniform:f32:3, {1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,2.100000e+00,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01}>> return %0: tensor<1x1x16x1x!quant.uniform:f32:3, {1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,2.100000e+00,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01,1.000000e-01}>> } + +// ----- + +// CHECK-LABEL: @transpose_no_op +func @transpose_no_op(%arg0: tensor<3x4x5x6xf32>) -> tensor<3x4x5x6xf32> { + // CHECK: return %arg0 + // CHECK-NOT: tosa.transpose + %perms = "tosa.const"() {value = dense<[0, 1, 2, 3]> : tensor<4xi32>} : () -> tensor<4xi32> + %1 = "tosa.transpose"(%arg0, %perms) : (tensor<3x4x5x6xf32>, tensor<4xi32>) -> tensor<3x4x5x6xf32> + return %1 : tensor<3x4x5x6xf32> +} diff --git a/mlir/test/Dialect/Vector/canonicalize.mlir b/mlir/test/Dialect/Vector/canonicalize.mlir index 6c232cc0f7ab5ea312dd8a6fb009e6cd4d460184..cf05308e8129b4fb410f0d24bee3d9d8054bb3df 100644 --- a/mlir/test/Dialect/Vector/canonicalize.mlir +++ b/mlir/test/Dialect/Vector/canonicalize.mlir @@ -542,6 +542,17 @@ func @fold_extract_shapecast_negative(%arg0 : vector<16xf32>, return %r : vector<4x2xf32> } +// ----- + +// CHECK-LABEL: dont_fold_expand_collapse +// CHECK: %[[A:.*]] = vector.shape_cast %{{.*}} : vector<1x1x64xf32> to vector<1x1x8x8xf32> +// CHECK: %[[B:.*]] = vector.shape_cast %{{.*}} : vector<1x1x8x8xf32> to vector<8x8xf32> +// CHECK: return %[[B]] : vector<8x8xf32> +func @dont_fold_expand_collapse(%arg0: vector<1x1x64xf32>) -> vector<8x8xf32> { + %0 = vector.shape_cast %arg0 : vector<1x1x64xf32> to vector<1x1x8x8xf32> + %1 = vector.shape_cast %0 : vector<1x1x8x8xf32> to vector<8x8xf32> + return %1 : vector<8x8xf32> +} // ----- diff --git a/mlir/test/IR/attribute.mlir b/mlir/test/IR/attribute.mlir index 06ac2cf9c9b804e2afe088a4d79feef784f59430..f8c07e37b63dc515513fc68f41ca3d049ac5cc17 100644 --- a/mlir/test/IR/attribute.mlir +++ b/mlir/test/IR/attribute.mlir @@ -1,5 +1,36 @@ // RUN: mlir-opt %s -split-input-file -allow-unregistered-dialect -verify-diagnostics | FileCheck %s +//===----------------------------------------------------------------------===// +// Test AnyAttrOf attributes +//===----------------------------------------------------------------------===// + +func @any_attr_of_pass() { + "test.any_attr_of_i32_str"() { + // CHECK: attr = 3 : i32 + attr = 3 : i32 + } : () -> () + + "test.any_attr_of_i32_str"() { + // CHECK: attr = "string_data" + attr = "string_data" + } : () -> () + + return +} + +// ----- + +func @any_attr_of_fail() { + // expected-error @+1 {{'test.any_attr_of_i32_str' op attribute 'attr' failed to satisfy constraint: 32-bit signless integer attribute or string attribute}} + "test.any_attr_of_i32_str"() { + attr = 3 : i64 + } : () -> () + + return +} + +// ----- + //===----------------------------------------------------------------------===// // Test integer attributes //===----------------------------------------------------------------------===// diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion.mlir index 2f651ce4eee9f41481818c5e75290b8397a800be..7fe6d00594d32509812eb643c023e3183d7a8b50 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion.mlir @@ -184,25 +184,25 @@ module { %c11 = sparse_tensor.indices %c, %c1 : tensor<2x3x4xf64, #Tensor1> to memref %c12 = sparse_tensor.indices %c, %c2 : tensor<2x3x4xf64, #Tensor1> to memref - %d10 = sparse_tensor.indices %d, %c0 : tensor<2x3x4xf64, #Tensor2> to memref - %d11 = sparse_tensor.indices %d, %c1 : tensor<2x3x4xf64, #Tensor2> to memref - %d12 = sparse_tensor.indices %d, %c2 : tensor<2x3x4xf64, #Tensor2> to memref - %e10 = sparse_tensor.indices %e, %c0 : tensor<2x3x4xf64, #Tensor2> to memref - %e11 = sparse_tensor.indices %e, %c1 : tensor<2x3x4xf64, #Tensor2> to memref - %e12 = sparse_tensor.indices %e, %c2 : tensor<2x3x4xf64, #Tensor2> to memref - %f10 = sparse_tensor.indices %f, %c0 : tensor<2x3x4xf64, #Tensor2> to memref - %f11 = sparse_tensor.indices %f, %c1 : tensor<2x3x4xf64, #Tensor2> to memref - %f12 = sparse_tensor.indices %f, %c2 : tensor<2x3x4xf64, #Tensor2> to memref + %d20 = sparse_tensor.indices %d, %c0 : tensor<2x3x4xf64, #Tensor2> to memref + %d21 = sparse_tensor.indices %d, %c1 : tensor<2x3x4xf64, #Tensor2> to memref + %d22 = sparse_tensor.indices %d, %c2 : tensor<2x3x4xf64, #Tensor2> to memref + %e20 = sparse_tensor.indices %e, %c0 : tensor<2x3x4xf64, #Tensor2> to memref + %e21 = sparse_tensor.indices %e, %c1 : tensor<2x3x4xf64, #Tensor2> to memref + %e22 = sparse_tensor.indices %e, %c2 : tensor<2x3x4xf64, #Tensor2> to memref + %f20 = sparse_tensor.indices %f, %c0 : tensor<2x3x4xf64, #Tensor2> to memref + %f21 = sparse_tensor.indices %f, %c1 : tensor<2x3x4xf64, #Tensor2> to memref + %f22 = sparse_tensor.indices %f, %c2 : tensor<2x3x4xf64, #Tensor2> to memref - %g10 = sparse_tensor.indices %g, %c0 : tensor<2x3x4xf64, #Tensor3> to memref - %g11 = sparse_tensor.indices %g, %c1 : tensor<2x3x4xf64, #Tensor3> to memref - %g12 = sparse_tensor.indices %g, %c2 : tensor<2x3x4xf64, #Tensor3> to memref - %h10 = sparse_tensor.indices %h, %c0 : tensor<2x3x4xf64, #Tensor3> to memref - %h11 = sparse_tensor.indices %h, %c1 : tensor<2x3x4xf64, #Tensor3> to memref - %h12 = sparse_tensor.indices %h, %c2 : tensor<2x3x4xf64, #Tensor3> to memref - %i10 = sparse_tensor.indices %i, %c0 : tensor<2x3x4xf64, #Tensor3> to memref - %i11 = sparse_tensor.indices %i, %c1 : tensor<2x3x4xf64, #Tensor3> to memref - %i12 = sparse_tensor.indices %i, %c2 : tensor<2x3x4xf64, #Tensor3> to memref + %g30 = sparse_tensor.indices %g, %c0 : tensor<2x3x4xf64, #Tensor3> to memref + %g31 = sparse_tensor.indices %g, %c1 : tensor<2x3x4xf64, #Tensor3> to memref + %g32 = sparse_tensor.indices %g, %c2 : tensor<2x3x4xf64, #Tensor3> to memref + %h30 = sparse_tensor.indices %h, %c0 : tensor<2x3x4xf64, #Tensor3> to memref + %h31 = sparse_tensor.indices %h, %c1 : tensor<2x3x4xf64, #Tensor3> to memref + %h32 = sparse_tensor.indices %h, %c2 : tensor<2x3x4xf64, #Tensor3> to memref + %i30 = sparse_tensor.indices %i, %c0 : tensor<2x3x4xf64, #Tensor3> to memref + %i31 = sparse_tensor.indices %i, %c1 : tensor<2x3x4xf64, #Tensor3> to memref + %i32 = sparse_tensor.indices %i, %c2 : tensor<2x3x4xf64, #Tensor3> to memref call @check(%v10, %a10) : (memref, memref) -> () call @check(%v11, %a11) : (memref, memref) -> () @@ -214,25 +214,25 @@ module { call @check(%v11, %c11) : (memref, memref) -> () call @check(%v12, %c12) : (memref, memref) -> () - call @check(%v20, %d10) : (memref, memref) -> () - call @check(%v21, %d11) : (memref, memref) -> () - call @check(%v22, %d12) : (memref, memref) -> () - call @check(%v20, %e10) : (memref, memref) -> () - call @check(%v21, %e11) : (memref, memref) -> () - call @check(%v22, %e12) : (memref, memref) -> () - call @check(%v20, %f10) : (memref, memref) -> () - call @check(%v21, %f11) : (memref, memref) -> () - call @check(%v22, %f12) : (memref, memref) -> () + call @check(%v20, %d20) : (memref, memref) -> () + call @check(%v21, %d21) : (memref, memref) -> () + call @check(%v22, %d22) : (memref, memref) -> () + call @check(%v20, %e20) : (memref, memref) -> () + call @check(%v21, %e21) : (memref, memref) -> () + call @check(%v22, %e22) : (memref, memref) -> () + call @check(%v20, %f20) : (memref, memref) -> () + call @check(%v21, %f21) : (memref, memref) -> () + call @check(%v22, %f22) : (memref, memref) -> () - call @check(%v30, %g10) : (memref, memref) -> () - call @check(%v31, %g11) : (memref, memref) -> () - call @check(%v32, %g12) : (memref, memref) -> () - call @check(%v30, %h10) : (memref, memref) -> () - call @check(%v31, %h11) : (memref, memref) -> () - call @check(%v32, %h12) : (memref, memref) -> () - call @check(%v30, %i10) : (memref, memref) -> () - call @check(%v31, %i11) : (memref, memref) -> () - call @check(%v32, %i12) : (memref, memref) -> () + call @check(%v30, %g30) : (memref, memref) -> () + call @check(%v31, %g31) : (memref, memref) -> () + call @check(%v32, %g32) : (memref, memref) -> () + call @check(%v30, %h30) : (memref, memref) -> () + call @check(%v31, %h31) : (memref, memref) -> () + call @check(%v32, %h32) : (memref, memref) -> () + call @check(%v30, %i30) : (memref, memref) -> () + call @check(%v31, %i31) : (memref, memref) -> () + call @check(%v32, %i32) : (memref, memref) -> () // // Sanity check direct results. diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_convert.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_convert.mlir new file mode 100644 index 0000000000000000000000000000000000000000..3bfd0df72d6f23c58ce4f0a2b22e1414e053d749 --- /dev/null +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_convert.mlir @@ -0,0 +1,91 @@ +// RUN: mlir-opt %s \ +// RUN: --sparsification --sparse-tensor-conversion \ +// RUN: --linalg-bufferize --convert-linalg-to-loops \ +// RUN: --convert-vector-to-scf --convert-scf-to-std \ +// RUN: --func-bufferize --tensor-constant-bufferize --tensor-bufferize \ +// RUN: --std-bufferize --finalizing-bufferize --lower-affine \ +// RUN: --convert-vector-to-llvm --convert-memref-to-llvm --convert-math-to-llvm \ +// RUN: --convert-std-to-llvm --reconcile-unrealized-casts | \ +// RUN: mlir-cpu-runner \ +// RUN: -e entry -entry-point-result=void \ +// RUN: -shared-libs=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \ +// RUN: FileCheck %s + +#DCSR = #sparse_tensor.encoding<{ + dimLevelType = [ "compressed", "compressed" ] +}> + +#DCSC = #sparse_tensor.encoding<{ + dimLevelType = [ "compressed", "compressed" ], + dimOrdering = affine_map<(i,j) -> (j,i)> +}> + +// +// Integration test that tests conversions between sparse tensors, +// where the dynamic sizes of the shape of the enveloping tensor +// may change (the actual underlying sizes obviously never change). +// +module { + + // + // Helper method to print values array. The transfer actually + // reads more than required to verify size of buffer as well. + // + func @dump(%arg0: memref) { + %c = arith.constant 0 : index + %d = arith.constant -1.0 : f64 + %0 = vector.transfer_read %arg0[%c], %d: memref, vector<8xf64> + vector.print %0 : vector<8xf64> + return + } + + func @entry() { + %t1 = arith.constant sparse< + [ [0,0], [0,1], [0,63], [1,0], [1,1], [31,0], [31,63] ], + [ 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0 ]> : tensor<32x64xf64> + %t2 = tensor.cast %t1 : tensor<32x64xf64> to tensor + + // Four dense to sparse conversions. + %1 = sparse_tensor.convert %t1 : tensor<32x64xf64> to tensor + %2 = sparse_tensor.convert %t1 : tensor<32x64xf64> to tensor + %3 = sparse_tensor.convert %t2 : tensor to tensor + %4 = sparse_tensor.convert %t2 : tensor to tensor + + // Two cross conversions. + %5 = sparse_tensor.convert %3 : tensor to tensor + %6 = sparse_tensor.convert %4 : tensor to tensor + + // + // All proper row-/column-wise? + // + // CHECK: ( 1, 2, 3, 4, 5, 6, 7, -1 ) + // CHECK: ( 1, 4, 6, 2, 5, 3, 7, -1 ) + // CHECK: ( 1, 2, 3, 4, 5, 6, 7, -1 ) + // CHECK: ( 1, 4, 6, 2, 5, 3, 7, -1 ) + // CHECK: ( 1, 4, 6, 2, 5, 3, 7, -1 ) + // CHECK: ( 1, 2, 3, 4, 5, 6, 7, -1 ) + // + %m1 = sparse_tensor.values %1 : tensor to memref + %m2 = sparse_tensor.values %2 : tensor to memref + %m3 = sparse_tensor.values %3 : tensor to memref + %m4 = sparse_tensor.values %4 : tensor to memref + %m5 = sparse_tensor.values %5 : tensor to memref + %m6 = sparse_tensor.values %6 : tensor to memref + call @dump(%m1) : (memref) -> () + call @dump(%m2) : (memref) -> () + call @dump(%m3) : (memref) -> () + call @dump(%m4) : (memref) -> () + call @dump(%m5) : (memref) -> () + call @dump(%m6) : (memref) -> () + + // Release the resources. + sparse_tensor.release %1 : tensor + sparse_tensor.release %2 : tensor + sparse_tensor.release %3 : tensor + sparse_tensor.release %4 : tensor + sparse_tensor.release %5 : tensor + sparse_tensor.release %6 : tensor + + return + } +} diff --git a/mlir/test/Target/SPIRV/ocl-ops.mlir b/mlir/test/Target/SPIRV/ocl-ops.mlir index 2fd0476ad361277ca5ea5ce88144d01b50506670..37ab7d90e2bc5e945e4036826204f19be2e5e079 100644 --- a/mlir/test/Target/SPIRV/ocl-ops.mlir +++ b/mlir/test/Target/SPIRV/ocl-ops.mlir @@ -6,6 +6,14 @@ spv.module Physical64 OpenCL requires #spv.vce { %0 = spv.OCL.exp %arg0 : f32 // CHECK: {{%.*}} = spv.OCL.fabs {{%.*}} : f32 %1 = spv.OCL.fabs %arg0 : f32 + // CHECK: {{%.*}} = spv.OCL.sin {{%.*}} : f32 + %2 = spv.OCL.sin %arg0 : f32 + // CHECK: {{%.*}} = spv.OCL.cos {{%.*}} : f32 + %3 = spv.OCL.cos %arg0 : f32 + // CHECK: {{%.*}} = spv.OCL.log {{%.*}} : f32 + %4 = spv.OCL.log %arg0 : f32 + // CHECK: {{%.*}} = spv.OCL.sqrt {{%.*}} : f32 + %5 = spv.OCL.sqrt %arg0 : f32 spv.Return } diff --git a/mlir/test/lib/Dialect/Test/TestDialect.cpp b/mlir/test/lib/Dialect/Test/TestDialect.cpp index b846f89145b43518fa7c2d0a0ac4c943d3c897b2..6040823239bf997ddca1e146f133b03f74376c1e 100644 --- a/mlir/test/lib/Dialect/Test/TestDialect.cpp +++ b/mlir/test/lib/Dialect/Test/TestDialect.cpp @@ -771,7 +771,7 @@ OpFoldResult TestOpConstant::fold(ArrayRef operands) { LogicalResult TestOpWithVariadicResultsAndFolder::fold( ArrayRef operands, SmallVectorImpl &results) { - for (Value input : this->operands()) { + for (Value input : this->getOperands()) { results.push_back(input); } return success(); diff --git a/mlir/test/lib/Dialect/Test/TestOps.td b/mlir/test/lib/Dialect/Test/TestOps.td index 0433c3075ca60f3bb58d56f9701c010279031a9f..e7144ccf29f62f7d8a3b9173d67bda3408c99f38 100644 --- a/mlir/test/lib/Dialect/Test/TestOps.td +++ b/mlir/test/lib/Dialect/Test/TestOps.td @@ -26,6 +26,9 @@ include "TestInterfaces.td" def Test_Dialect : Dialect { let name = "test"; let cppNamespace = "::test"; + // Temporarily flipping to _Both (given this is test only/not intended for + // general use, this won't be following the 2 week process here). + let emitAccessorPrefix = kEmitAccessorPrefix_Both; let hasCanonicalizer = 1; let hasConstantMaterializer = 1; let hasOperationAttrVerify = 1; @@ -160,7 +163,7 @@ def MixedNormalVariadicOperandOp : TEST_Op< def VariadicWithSameOperandsResult : TEST_Op<"variadic_with_same_operand_results", [SameOperandsAndResultType]> { - let arguments = (ins Variadic:$operands); + let arguments = (ins Variadic); let results = (outs AnySignlessInteger:$result); } @@ -187,6 +190,10 @@ def MixedNormalVariadicResults : TEST_Op< // Test Attributes //===----------------------------------------------------------------------===// +def AnyAttrOfOp : TEST_Op<"any_attr_of_i32_str"> { + let arguments = (ins AnyAttrOf<[I32Attr, StrAttr]>:$attr); +} + def NonNegIntAttrOp : TEST_Op<"non_negative_int_attr"> { let arguments = (ins Confined:$i32attr, @@ -957,9 +964,6 @@ def TestOpWithRegionPattern : TEST_Op<"op_with_region_pattern"> { def TestOpConstant : TEST_Op<"constant", [ConstantLike, NoSideEffect]> { let arguments = (ins AnyAttr:$value); let results = (outs AnyType); - let extraClassDeclaration = [{ - ::mlir::Attribute getValue() { return (*this)->getAttr("value"); } - }]; let hasFolder = 1; } @@ -985,7 +989,7 @@ def TestOpWithRegionFold : TEST_Op<"op_with_region_fold"> { } def TestOpWithVariadicResultsAndFolder: TEST_Op<"op_with_variadic_results_and_folder"> { - let arguments = (ins Variadic:$operands); + let arguments = (ins Variadic); let results = (outs Variadic); let hasFolder = 1; } @@ -1831,9 +1835,9 @@ def FormatTwoVariadicOperandsNoBuildableTypeOp def FormatInferVariadicTypeFromNonVariadic : TEST_Op<"format_infer_variadic_type_from_non_variadic", [SameOperandsAndResultType]> { - let arguments = (ins Variadic:$operands); + let arguments = (ins Variadic:$args); let results = (outs AnyType:$result); - let assemblyFormat = "$operands attr-dict `:` type($result)"; + let assemblyFormat = "$args attr-dict `:` type($result)"; } def FormatOptionalUnitAttr : TEST_Op<"format_optional_unit_attribute"> { @@ -2063,10 +2067,6 @@ def CopyOp : TEST_Op<"copy", [CopyOpInterface]> { `(` $source `,` $target `)` `:` `(` type($source) `,` type($target) `)` attr-dict }]; - let extraClassDeclaration = [{ - ::mlir::Value getSource() { return source(); } - ::mlir::Value getTarget() { return target(); } - }]; } //===----------------------------------------------------------------------===// diff --git a/mlir/unittests/IR/OperationSupportTest.cpp b/mlir/unittests/IR/OperationSupportTest.cpp index 3d03329216db34065bc4f465bc160ff53f80801b..6939064314db3ba94dfc525d0f9ec33a7acd8d68 100644 --- a/mlir/unittests/IR/OperationSupportTest.cpp +++ b/mlir/unittests/IR/OperationSupportTest.cpp @@ -225,4 +225,48 @@ TEST(OperationFormatPrintTest, CanUseVariadicFormat) { ASSERT_STREQ(str.c_str(), "\"foo.bar\"() : () -> ()"); } +TEST(NamedAttrListTest, TestAppendAssign) { + MLIRContext ctx; + NamedAttrList attrs; + Builder b(&ctx); + + attrs.append("foo", b.getStringAttr("bar")); + attrs.append("baz", b.getStringAttr("boo")); + + { + auto it = attrs.begin(); + EXPECT_EQ(it->first, b.getIdentifier("foo")); + EXPECT_EQ(it->second, b.getStringAttr("bar")); + ++it; + EXPECT_EQ(it->first, b.getIdentifier("baz")); + EXPECT_EQ(it->second, b.getStringAttr("boo")); + } + + attrs.append("foo", b.getStringAttr("zoo")); + { + auto dup = attrs.findDuplicate(); + ASSERT_TRUE(dup.hasValue()); + } + + SmallVector newAttrs = { + b.getNamedAttr("foo", b.getStringAttr("f")), + b.getNamedAttr("zoo", b.getStringAttr("z")), + }; + attrs.assign(newAttrs); + + auto dup = attrs.findDuplicate(); + ASSERT_FALSE(dup.hasValue()); + + { + auto it = attrs.begin(); + EXPECT_EQ(it->first, b.getIdentifier("foo")); + EXPECT_EQ(it->second, b.getStringAttr("f")); + ++it; + EXPECT_EQ(it->first, b.getIdentifier("zoo")); + EXPECT_EQ(it->second, b.getStringAttr("z")); + } + + attrs.assign({}); + ASSERT_TRUE(attrs.empty()); +} } // end namespace diff --git a/openmp/libomptarget/test/lit.cfg b/openmp/libomptarget/test/lit.cfg index 3693343969d809f48298d17804bc9c93fdfa4984..5b3e2f54f8e5e6cdaef40d946ec9f216aa1f50fd 100644 --- a/openmp/libomptarget/test/lit.cfg +++ b/openmp/libomptarget/test/lit.cfg @@ -17,6 +17,9 @@ if 'CUDA_VISIBLE_DEVICES' in os.environ: if 'LIBOMPTARGET_DEBUG' in os.environ: config.environment['LIBOMPTARGET_DEBUG'] = os.environ['LIBOMPTARGET_DEBUG'] +if 'OMP_TARGET_OFFLOAD' in os.environ: + config.environment['OMP_TARGET_OFFLOAD'] = os.environ['OMP_TARGET_OFFLOAD'] + def append_dynamic_library_path(name, value, sep): if name in config.environment: config.environment[name] = value + sep + config.environment[name] diff --git a/openmp/runtime/src/kmp_tasking.cpp b/openmp/runtime/src/kmp_tasking.cpp index 32e85a6b30f350d279059dae04e8c35b31d28722..d956df1b2a37bde679dbd3b815dffa9b3952f6fb 100644 --- a/openmp/runtime/src/kmp_tasking.cpp +++ b/openmp/runtime/src/kmp_tasking.cpp @@ -1621,13 +1621,15 @@ static void __kmp_invoke_task(kmp_int32 gtid, kmp_task_t *task, KMP_FSYNC_ACQUIRED(taskdata); // acquired self (new task) #endif + if (task->routine != NULL) { #ifdef KMP_GOMP_COMPAT - if (taskdata->td_flags.native) { - ((void (*)(void *))(*(task->routine)))(task->shareds); - } else + if (taskdata->td_flags.native) { + ((void (*)(void *))(*(task->routine)))(task->shareds); + } else #endif /* KMP_GOMP_COMPAT */ - { - (*(task->routine))(gtid, task); + { + (*(task->routine))(gtid, task); + } } KMP_POP_PARTITIONED_TIMER(); diff --git a/openmp/runtime/test/tasking/kmp_taskwait_nowait.c b/openmp/runtime/test/tasking/kmp_taskwait_nowait.c new file mode 100644 index 0000000000000000000000000000000000000000..809642aea2c4838477d79f2aca41ecd1247745af --- /dev/null +++ b/openmp/runtime/test/tasking/kmp_taskwait_nowait.c @@ -0,0 +1,86 @@ +// RUN: %libomp-compile-and-run + +// test checks IN dep kind in depend clause on taskwait nowait +// uses codegen emulation +// Note: no outlined task routine used +#include +#include +// --------------------------------------------------------------------------- +// internal data to emulate compiler codegen +#define TIED 1 +typedef struct DEP { + size_t addr; + size_t len; + int flags; +} _dep; +typedef struct ID { + int reserved_1; + int flags; + int reserved_2; + int reserved_3; + char *psource; +} _id; +typedef struct task { + void** shareds; + void* entry; + int part_id; + void* destr_thunk; + int priority; + long long device_id; + int f_priv; +} task_t; +typedef int(*entry_t)(int, task_t*); + +#ifdef __cplusplus +extern "C" { +#endif +extern int __kmpc_global_thread_num(_id*); +task_t *__kmpc_omp_task_alloc(_id *loc, int gtid, int flags, + size_t sz, size_t shar, entry_t rtn); +int __kmpc_omp_task_with_deps(_id *loc, int gtid, task_t *task, int ndeps, + _dep *dep_lst, int nd_noalias, _dep *noalias_l); +#ifdef __cplusplus +} // extern "C" +#endif + +int main() +{ + int i1,i2,i3; + omp_set_num_threads(2); + printf("addresses: %p %p %p\n", &i1, &i2, &i3); + #pragma omp parallel + { + int t = omp_get_thread_num(); + printf("thread %d enters parallel\n", t); + #pragma omp single + { + #pragma omp task depend(in: i3) + { + int th = omp_get_thread_num(); + printf("task 0 created by th %d, executed by th %d\n", t, th); + } + #pragma omp task depend(in: i2) + { + int th = omp_get_thread_num(); + printf("task 1 created by th %d, executed by th %d\n", t, th); + } +// #pragma omp taskwait depend(in: i1, i2) nowait + { + _dep sdep[2]; + static _id loc = {0, 2, 0, 0, ";test.c;func;67;0;;"}; + int gtid = __kmpc_global_thread_num(&loc); +// instead of creating an empty task function we can now send NULL to runtime + task_t *ptr = __kmpc_omp_task_alloc(&loc, gtid, TIED, + sizeof(task_t), 0, NULL); + sdep[0].addr = (size_t)&i2; + sdep[0].flags = 1; // 1-in, 2-out, 3-inout, 4-mtx, 8-inoutset + sdep[1].addr = (size_t)&i1; + sdep[1].flags = 1; // in + __kmpc_omp_task_with_deps(&loc, gtid, ptr, 2, sdep, 0, NULL); + } + printf("single done\n"); + } + } + printf("passed\n"); + return 0; +} diff --git a/polly/lib/Analysis/ScopInfo.cpp b/polly/lib/Analysis/ScopInfo.cpp index dc2d4848ba3bc80dee0b931ebb4b6a75489865e2..06b0aa3c3e8df21a2c016267d39163e2a22ba299 100644 --- a/polly/lib/Analysis/ScopInfo.cpp +++ b/polly/lib/Analysis/ScopInfo.cpp @@ -1303,8 +1303,7 @@ void ScopStmt::removeMemoryAccess(MemoryAccess *MA) { Parent.removeAccessData(MA); } } - MemAccs.erase(std::remove_if(MemAccs.begin(), MemAccs.end(), Predicate), - MemAccs.end()); + llvm::erase_if(MemAccs, Predicate); InstructionToAccess.erase(MA->getAccessInstruction()); } diff --git a/runtimes/CMakeLists.txt b/runtimes/CMakeLists.txt index 39961bc5c43292de5051d2b8315cab74c2f35c40..2cc8eab3e73d826790cc913ca5658c666f57fa59 100644 --- a/runtimes/CMakeLists.txt +++ b/runtimes/CMakeLists.txt @@ -117,6 +117,8 @@ if (NOT LLVM_DEFAULT_TARGET_TRIPLE) endif() option(LLVM_INCLUDE_TESTS "Generate build targets for the runtimes unit tests." ON) +option(LLVM_INCLUDE_DOCS "Generate build targets for the runtimes documentation." ON) +option(LLVM_ENABLE_SPHINX "Use Sphinx to generate the runtimes documentation." OFF) # Use libtool instead of ar if you are both on an Apple host, and targeting Apple. if(CMAKE_HOST_APPLE AND APPLE)